Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 45
- Kernel Warnings: 31
- Boot result: PASS
- Errors: 0
1 11:49:33.716967 lava-dispatcher, installed at version: 2023.10
2 11:49:33.717189 start: 0 validate
3 11:49:33.717321 Start time: 2023-11-24 11:49:33.717314+00:00 (UTC)
4 11:49:33.717449 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:49:33.717585 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:49:33.988479 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:49:33.989376 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:49:34.261559 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:49:34.262426 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:49:34.534997 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:49:34.535769 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:49:34.804282 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:49:34.804472 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:49:35.073780 validate duration: 1.36
16 11:49:35.074039 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:49:35.074137 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:49:35.074226 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:49:35.074350 Not decompressing ramdisk as can be used compressed.
20 11:49:35.074433 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:49:35.074533 saving as /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/ramdisk/initrd.cpio.gz
22 11:49:35.074598 total size: 4665395 (4 MB)
23 11:49:35.075655 progress 0 % (0 MB)
24 11:49:35.077145 progress 5 % (0 MB)
25 11:49:35.078447 progress 10 % (0 MB)
26 11:49:35.079697 progress 15 % (0 MB)
27 11:49:35.080912 progress 20 % (0 MB)
28 11:49:35.082192 progress 25 % (1 MB)
29 11:49:35.083520 progress 30 % (1 MB)
30 11:49:35.084719 progress 35 % (1 MB)
31 11:49:35.086018 progress 40 % (1 MB)
32 11:49:35.087380 progress 45 % (2 MB)
33 11:49:35.088588 progress 50 % (2 MB)
34 11:49:35.089858 progress 55 % (2 MB)
35 11:49:35.091058 progress 60 % (2 MB)
36 11:49:35.092256 progress 65 % (2 MB)
37 11:49:35.093526 progress 70 % (3 MB)
38 11:49:35.094735 progress 75 % (3 MB)
39 11:49:35.095958 progress 80 % (3 MB)
40 11:49:35.097359 progress 85 % (3 MB)
41 11:49:35.098654 progress 90 % (4 MB)
42 11:49:35.099855 progress 95 % (4 MB)
43 11:49:35.101089 progress 100 % (4 MB)
44 11:49:35.101240 4 MB downloaded in 0.03 s (166.99 MB/s)
45 11:49:35.101388 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:49:35.101663 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:49:35.101748 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:49:35.101830 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:49:35.101960 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:49:35.102032 saving as /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/kernel/Image
52 11:49:35.102093 total size: 49107456 (46 MB)
53 11:49:35.102153 No compression specified
54 11:49:35.103261 progress 0 % (0 MB)
55 11:49:35.115863 progress 5 % (2 MB)
56 11:49:35.128685 progress 10 % (4 MB)
57 11:49:35.141391 progress 15 % (7 MB)
58 11:49:35.154191 progress 20 % (9 MB)
59 11:49:35.167091 progress 25 % (11 MB)
60 11:49:35.179872 progress 30 % (14 MB)
61 11:49:35.192732 progress 35 % (16 MB)
62 11:49:35.205623 progress 40 % (18 MB)
63 11:49:35.218302 progress 45 % (21 MB)
64 11:49:35.231070 progress 50 % (23 MB)
65 11:49:35.244009 progress 55 % (25 MB)
66 11:49:35.256898 progress 60 % (28 MB)
67 11:49:35.270087 progress 65 % (30 MB)
68 11:49:35.283015 progress 70 % (32 MB)
69 11:49:35.295829 progress 75 % (35 MB)
70 11:49:35.308725 progress 80 % (37 MB)
71 11:49:35.321525 progress 85 % (39 MB)
72 11:49:35.334233 progress 90 % (42 MB)
73 11:49:35.346737 progress 95 % (44 MB)
74 11:49:35.359220 progress 100 % (46 MB)
75 11:49:35.359448 46 MB downloaded in 0.26 s (181.98 MB/s)
76 11:49:35.359622 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:49:35.359893 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:49:35.359996 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:49:35.360104 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:49:35.360261 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:49:35.360337 saving as /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/dtb/mt8192-asurada-spherion-r0.dtb
83 11:49:35.360438 total size: 47278 (0 MB)
84 11:49:35.360540 No compression specified
85 11:49:35.362260 progress 69 % (0 MB)
86 11:49:35.362569 progress 100 % (0 MB)
87 11:49:35.362767 0 MB downloaded in 0.00 s (19.38 MB/s)
88 11:49:35.362942 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:49:35.363224 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:49:35.363331 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:49:35.363429 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:49:35.363561 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:49:35.363634 saving as /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/nfsrootfs/full.rootfs.tar
95 11:49:35.363722 total size: 200813988 (191 MB)
96 11:49:35.363824 Using unxz to decompress xz
97 11:49:35.368376 progress 0 % (0 MB)
98 11:49:35.895243 progress 5 % (9 MB)
99 11:49:36.410046 progress 10 % (19 MB)
100 11:49:36.993735 progress 15 % (28 MB)
101 11:49:37.365866 progress 20 % (38 MB)
102 11:49:37.690182 progress 25 % (47 MB)
103 11:49:38.278862 progress 30 % (57 MB)
104 11:49:38.826476 progress 35 % (67 MB)
105 11:49:39.416328 progress 40 % (76 MB)
106 11:49:39.974859 progress 45 % (86 MB)
107 11:49:40.559406 progress 50 % (95 MB)
108 11:49:41.187581 progress 55 % (105 MB)
109 11:49:41.849322 progress 60 % (114 MB)
110 11:49:41.966668 progress 65 % (124 MB)
111 11:49:42.105669 progress 70 % (134 MB)
112 11:49:42.201513 progress 75 % (143 MB)
113 11:49:42.272230 progress 80 % (153 MB)
114 11:49:42.340254 progress 85 % (162 MB)
115 11:49:42.440629 progress 90 % (172 MB)
116 11:49:42.720068 progress 95 % (181 MB)
117 11:49:43.299311 progress 100 % (191 MB)
118 11:49:43.304470 191 MB downloaded in 7.94 s (24.12 MB/s)
119 11:49:43.304725 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:49:43.304987 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:49:43.305075 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:49:43.305161 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:49:43.305318 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:49:43.305391 saving as /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/modules/modules.tar
126 11:49:43.305460 total size: 8624756 (8 MB)
127 11:49:43.305525 Using unxz to decompress xz
128 11:49:43.309674 progress 0 % (0 MB)
129 11:49:43.330541 progress 5 % (0 MB)
130 11:49:43.353900 progress 10 % (0 MB)
131 11:49:43.377213 progress 15 % (1 MB)
132 11:49:43.400730 progress 20 % (1 MB)
133 11:49:43.425128 progress 25 % (2 MB)
134 11:49:43.450709 progress 30 % (2 MB)
135 11:49:43.476517 progress 35 % (2 MB)
136 11:49:43.499721 progress 40 % (3 MB)
137 11:49:43.523780 progress 45 % (3 MB)
138 11:49:43.549132 progress 50 % (4 MB)
139 11:49:43.573287 progress 55 % (4 MB)
140 11:49:43.597773 progress 60 % (4 MB)
141 11:49:43.624978 progress 65 % (5 MB)
142 11:49:43.649766 progress 70 % (5 MB)
143 11:49:43.673591 progress 75 % (6 MB)
144 11:49:43.700959 progress 80 % (6 MB)
145 11:49:43.726656 progress 85 % (7 MB)
146 11:49:43.751648 progress 90 % (7 MB)
147 11:49:43.782923 progress 95 % (7 MB)
148 11:49:43.811018 progress 100 % (8 MB)
149 11:49:43.815890 8 MB downloaded in 0.51 s (16.11 MB/s)
150 11:49:43.816149 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:49:43.816416 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:49:43.816508 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:49:43.816602 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:49:47.378705 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5
156 11:49:47.378926 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:49:47.379026 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:49:47.379207 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6
159 11:49:47.379345 makedir: /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin
160 11:49:47.379450 makedir: /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/tests
161 11:49:47.379554 makedir: /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/results
162 11:49:47.379660 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-add-keys
163 11:49:47.379814 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-add-sources
164 11:49:47.379950 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-background-process-start
165 11:49:47.380088 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-background-process-stop
166 11:49:47.380217 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-common-functions
167 11:49:47.380344 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-echo-ipv4
168 11:49:47.380477 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-install-packages
169 11:49:47.380604 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-installed-packages
170 11:49:47.380731 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-os-build
171 11:49:47.380859 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-probe-channel
172 11:49:47.380988 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-probe-ip
173 11:49:47.381117 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-target-ip
174 11:49:47.381244 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-target-mac
175 11:49:47.381372 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-target-storage
176 11:49:47.381753 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-case
177 11:49:47.381886 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-event
178 11:49:47.382015 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-feedback
179 11:49:47.382143 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-raise
180 11:49:47.382269 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-reference
181 11:49:47.382395 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-runner
182 11:49:47.382523 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-set
183 11:49:47.382652 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-test-shell
184 11:49:47.382782 Updating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-add-keys (debian)
185 11:49:47.382937 Updating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-add-sources (debian)
186 11:49:47.383084 Updating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-install-packages (debian)
187 11:49:47.383226 Updating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-installed-packages (debian)
188 11:49:47.383367 Updating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/bin/lava-os-build (debian)
189 11:49:47.383490 Creating /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/environment
190 11:49:47.383590 LAVA metadata
191 11:49:47.383662 - LAVA_JOB_ID=12074064
192 11:49:47.383726 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:49:47.383835 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:49:47.383902 skipped lava-vland-overlay
195 11:49:47.383977 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:49:47.384058 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:49:47.384118 skipped lava-multinode-overlay
198 11:49:47.384203 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:49:47.384281 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:49:47.384357 Loading test definitions
201 11:49:47.384447 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:49:47.384519 Using /lava-12074064 at stage 0
203 11:49:47.384819 uuid=12074064_1.6.2.3.1 testdef=None
204 11:49:47.384910 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:49:47.384995 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:49:47.385513 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:49:47.385741 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:49:47.386312 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:49:47.386544 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:49:47.387094 runner path: /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/0/tests/0_timesync-off test_uuid 12074064_1.6.2.3.1
213 11:49:47.387254 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:49:47.387482 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:49:47.387556 Using /lava-12074064 at stage 0
217 11:49:47.387655 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:49:47.387735 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/0/tests/1_kselftest-rtc'
219 11:49:54.858243 Running '/usr/bin/git checkout kernelci.org
220 11:49:55.009036 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:49:55.009840 uuid=12074064_1.6.2.3.5 testdef=None
222 11:49:55.010005 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 11:49:55.010268 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 11:49:55.011106 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:49:55.011346 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 11:49:55.012348 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:49:55.012585 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 11:49:55.013615 runner path: /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/0/tests/1_kselftest-rtc test_uuid 12074064_1.6.2.3.5
232 11:49:55.013711 BOARD='mt8192-asurada-spherion-r0'
233 11:49:55.013777 BRANCH='cip-gitlab'
234 11:49:55.013838 SKIPFILE='/dev/null'
235 11:49:55.013897 SKIP_INSTALL='True'
236 11:49:55.013955 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:49:55.014014 TST_CASENAME=''
238 11:49:55.014071 TST_CMDFILES='rtc'
239 11:49:55.014216 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:49:55.014421 Creating lava-test-runner.conf files
242 11:49:55.014487 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074064/lava-overlay-7g50zpx6/lava-12074064/0 for stage 0
243 11:49:55.014612 - 0_timesync-off
244 11:49:55.014682 - 1_kselftest-rtc
245 11:49:55.014780 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 11:49:55.014868 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 11:50:02.542598 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:50:02.542784 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 11:50:02.542872 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:50:02.543090 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 11:50:02.543218 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 11:50:02.663973 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:50:02.664366 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 11:50:02.664487 extracting modules file /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5
255 11:50:02.890797 extracting modules file /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074064/extract-overlay-ramdisk-3a06tfcx/ramdisk
256 11:50:03.123405 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:50:03.123579 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 11:50:03.123673 [common] Applying overlay to NFS
259 11:50:03.123746 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074064/compress-overlay-3x4gtt4j/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5
260 11:50:04.058887 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:50:04.059111 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 11:50:04.059251 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:50:04.059345 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 11:50:04.059483 Building ramdisk /var/lib/lava/dispatcher/tmp/12074064/extract-overlay-ramdisk-3a06tfcx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074064/extract-overlay-ramdisk-3a06tfcx/ramdisk
265 11:50:04.381374 >> 119398 blocks
266 11:50:06.347417 rename /var/lib/lava/dispatcher/tmp/12074064/extract-overlay-ramdisk-3a06tfcx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/ramdisk/ramdisk.cpio.gz
267 11:50:06.347892 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:50:06.348043 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 11:50:06.348176 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 11:50:06.348320 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/kernel/Image'
271 11:50:18.848105 Returned 0 in 12 seconds
272 11:50:18.948742 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/kernel/image.itb
273 11:50:19.308881 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:50:19.309274 output: Created: Fri Nov 24 11:50:19 2023
275 11:50:19.309351 output: Image 0 (kernel-1)
276 11:50:19.309445 output: Description:
277 11:50:19.309528 output: Created: Fri Nov 24 11:50:19 2023
278 11:50:19.309594 output: Type: Kernel Image
279 11:50:19.309655 output: Compression: lzma compressed
280 11:50:19.309717 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
281 11:50:19.309776 output: Architecture: AArch64
282 11:50:19.309832 output: OS: Linux
283 11:50:19.309889 output: Load Address: 0x00000000
284 11:50:19.309945 output: Entry Point: 0x00000000
285 11:50:19.310002 output: Hash algo: crc32
286 11:50:19.310061 output: Hash value: 43cfb6ad
287 11:50:19.310118 output: Image 1 (fdt-1)
288 11:50:19.310175 output: Description: mt8192-asurada-spherion-r0
289 11:50:19.310229 output: Created: Fri Nov 24 11:50:19 2023
290 11:50:19.310283 output: Type: Flat Device Tree
291 11:50:19.310336 output: Compression: uncompressed
292 11:50:19.310389 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:50:19.310442 output: Architecture: AArch64
294 11:50:19.310496 output: Hash algo: crc32
295 11:50:19.310549 output: Hash value: cc4352de
296 11:50:19.310602 output: Image 2 (ramdisk-1)
297 11:50:19.310654 output: Description: unavailable
298 11:50:19.310707 output: Created: Fri Nov 24 11:50:19 2023
299 11:50:19.310760 output: Type: RAMDisk Image
300 11:50:19.310813 output: Compression: Unknown Compression
301 11:50:19.310866 output: Data Size: 17794859 Bytes = 17377.79 KiB = 16.97 MiB
302 11:50:19.310919 output: Architecture: AArch64
303 11:50:19.310972 output: OS: Linux
304 11:50:19.311025 output: Load Address: unavailable
305 11:50:19.311078 output: Entry Point: unavailable
306 11:50:19.311131 output: Hash algo: crc32
307 11:50:19.311184 output: Hash value: dd760dad
308 11:50:19.311237 output: Default Configuration: 'conf-1'
309 11:50:19.311290 output: Configuration 0 (conf-1)
310 11:50:19.311342 output: Description: mt8192-asurada-spherion-r0
311 11:50:19.311395 output: Kernel: kernel-1
312 11:50:19.311448 output: Init Ramdisk: ramdisk-1
313 11:50:19.311501 output: FDT: fdt-1
314 11:50:19.311554 output: Loadables: kernel-1
315 11:50:19.311607 output:
316 11:50:19.311812 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:50:19.311908 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:50:19.312015 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 11:50:19.312109 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 11:50:19.312190 No LXC device requested
321 11:50:19.312266 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:50:19.312351 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 11:50:19.312429 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:50:19.312500 Checking files for TFTP limit of 4294967296 bytes.
325 11:50:19.313111 end: 1 tftp-deploy (duration 00:00:44) [common]
326 11:50:19.313222 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:50:19.313319 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:50:19.313497 substitutions:
329 11:50:19.313568 - {DTB}: 12074064/tftp-deploy-1je_ui1h/dtb/mt8192-asurada-spherion-r0.dtb
330 11:50:19.313633 - {INITRD}: 12074064/tftp-deploy-1je_ui1h/ramdisk/ramdisk.cpio.gz
331 11:50:19.313692 - {KERNEL}: 12074064/tftp-deploy-1je_ui1h/kernel/Image
332 11:50:19.313751 - {LAVA_MAC}: None
333 11:50:19.313808 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5
334 11:50:19.313865 - {NFS_SERVER_IP}: 192.168.201.1
335 11:50:19.313921 - {PRESEED_CONFIG}: None
336 11:50:19.313977 - {PRESEED_LOCAL}: None
337 11:50:19.314032 - {RAMDISK}: 12074064/tftp-deploy-1je_ui1h/ramdisk/ramdisk.cpio.gz
338 11:50:19.314087 - {ROOT_PART}: None
339 11:50:19.314141 - {ROOT}: None
340 11:50:19.314196 - {SERVER_IP}: 192.168.201.1
341 11:50:19.314250 - {TEE}: None
342 11:50:19.314304 Parsed boot commands:
343 11:50:19.314357 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:50:19.314542 Parsed boot commands: tftpboot 192.168.201.1 12074064/tftp-deploy-1je_ui1h/kernel/image.itb 12074064/tftp-deploy-1je_ui1h/kernel/cmdline
345 11:50:19.314641 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:50:19.314728 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:50:19.314825 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:50:19.314916 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:50:19.314989 Not connected, no need to disconnect.
350 11:50:19.315064 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:50:19.315142 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:50:19.315207 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 11:50:19.319230 Setting prompt string to ['lava-test: # ']
354 11:50:19.319677 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:50:19.319785 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:50:19.319922 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:50:19.320012 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:50:19.320246 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 11:50:24.457958 >> Command sent successfully.
360 11:50:24.460898 Returned 0 in 5 seconds
361 11:50:24.561732 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:50:24.563183 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:50:24.563736 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:50:24.564225 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:50:24.564591 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:50:24.564974 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:50:24.566250 [Enter `^Ec?' for help]
369 11:50:24.733211
370 11:50:24.733879
371 11:50:24.734277 F0: 102B 0000
372 11:50:24.734654
373 11:50:24.735007 F3: 1001 0000 [0200]
374 11:50:24.735346
375 11:50:24.737052 F3: 1001 0000
376 11:50:24.737579
377 11:50:24.737962 F7: 102D 0000
378 11:50:24.738322
379 11:50:24.738663 F1: 0000 0000
380 11:50:24.741053
381 11:50:24.741576 V0: 0000 0000 [0001]
382 11:50:24.741966
383 11:50:24.742319 00: 0007 8000
384 11:50:24.742688
385 11:50:24.743755 01: 0000 0000
386 11:50:24.744243
387 11:50:24.744621 BP: 0C00 0209 [0000]
388 11:50:24.744979
389 11:50:24.747299 G0: 1182 0000
390 11:50:24.747733
391 11:50:24.748078 EC: 0000 0021 [4000]
392 11:50:24.748399
393 11:50:24.750784 S7: 0000 0000 [0000]
394 11:50:24.751215
395 11:50:24.751559 CC: 0000 0000 [0001]
396 11:50:24.751876
397 11:50:24.753940 T0: 0000 0040 [010F]
398 11:50:24.754377
399 11:50:24.754721 Jump to BL
400 11:50:24.755041
401 11:50:24.780035
402 11:50:24.780563
403 11:50:24.780910
404 11:50:24.787932 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:50:24.792020 ARM64: Exception handlers installed.
406 11:50:24.794816 ARM64: Testing exception
407 11:50:24.798577 ARM64: Done test exception
408 11:50:24.805557 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:50:24.813023 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:50:24.820234 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:50:24.831748 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:50:24.838947 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:50:24.845013 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:50:24.857106 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:50:24.863536 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:50:24.884058 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:50:24.886287 WDT: Last reset was cold boot
418 11:50:24.889969 SPI1(PAD0) initialized at 2873684 Hz
419 11:50:24.892825 SPI5(PAD0) initialized at 992727 Hz
420 11:50:24.896278 VBOOT: Loading verstage.
421 11:50:24.902549 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:50:24.906063 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:50:24.910370 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:50:24.912688 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:50:24.920844 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:50:24.927271 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:50:24.938249 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:50:24.938842
429 11:50:24.939309
430 11:50:24.948280 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:50:24.951635 ARM64: Exception handlers installed.
432 11:50:24.954850 ARM64: Testing exception
433 11:50:24.955328 ARM64: Done test exception
434 11:50:24.961333 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:50:24.965269 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:50:24.979131 Probing TPM: . done!
437 11:50:24.979794 TPM ready after 0 ms
438 11:50:24.985725 Connected to device vid:did:rid of 1ae0:0028:00
439 11:50:24.992240 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:50:25.033924 Initialized TPM device CR50 revision 0
441 11:50:25.045293 tlcl_send_startup: Startup return code is 0
442 11:50:25.045486 TPM: setup succeeded
443 11:50:25.056992 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:50:25.066035 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:50:25.075666 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:50:25.084768 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:50:25.087889 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:50:25.091374 in-header: 03 07 00 00 08 00 00 00
449 11:50:25.094753 in-data: aa e4 47 04 13 02 00 00
450 11:50:25.097816 Chrome EC: UHEPI supported
451 11:50:25.105185 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:50:25.107955 in-header: 03 ad 00 00 08 00 00 00
453 11:50:25.111284 in-data: 00 20 20 08 00 00 00 00
454 11:50:25.111483 Phase 1
455 11:50:25.117525 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:50:25.124325 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:50:25.127646 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:50:25.130724 Recovery requested (1009000e)
459 11:50:25.138834 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:50:25.144159 tlcl_extend: response is 0
461 11:50:25.153166 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:50:25.157823 tlcl_extend: response is 0
463 11:50:25.164573 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:50:25.185279 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:50:25.192018 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:50:25.192596
467 11:50:25.192973
468 11:50:25.201850 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:50:25.205162 ARM64: Exception handlers installed.
470 11:50:25.208459 ARM64: Testing exception
471 11:50:25.208936 ARM64: Done test exception
472 11:50:25.230734 pmic_efuse_setting: Set efuses in 11 msecs
473 11:50:25.234399 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:50:25.238734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:50:25.244708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:50:25.248434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:50:25.255050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:50:25.257781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:50:25.265517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:50:25.268561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:50:25.271771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:50:25.279057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:50:25.281939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:50:25.288766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:50:25.291977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:50:25.295828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:50:25.301611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:50:25.308895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:50:25.315110 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:50:25.318170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:50:25.325461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:50:25.331824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:50:25.338009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:50:25.341770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:50:25.349072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:50:25.352021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:50:25.359201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:50:25.362514 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:50:25.369684 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:50:25.374034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:50:25.380137 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:50:25.383255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:50:25.390559 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:50:25.393639 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:50:25.400433 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:50:25.403635 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:50:25.410556 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:50:25.413527 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:50:25.420487 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:50:25.423661 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:50:25.430143 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:50:25.433308 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:50:25.436936 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:50:25.443917 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:50:25.448012 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:50:25.451295 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:50:25.454280 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:50:25.461510 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:50:25.464371 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:50:25.467672 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:50:25.474328 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:50:25.477970 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:50:25.481062 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:50:25.484225 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:50:25.494805 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:50:25.500836 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:50:25.507410 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:50:25.514208 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:50:25.524120 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:50:25.527254 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:50:25.531346 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:50:25.536959 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:50:25.543914 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x3
534 11:50:25.547044 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:50:25.554867 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 11:50:25.558419 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:50:25.567202 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 11:50:25.577131 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 11:50:25.586416 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 11:50:25.595970 [RTC]rtc_get_frequency_meter,154: input=13, output=804
541 11:50:25.606069 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 11:50:25.615382 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 11:50:25.624209 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 11:50:25.627794 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 11:50:25.635107 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 11:50:25.638284 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:50:25.641216 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:50:25.648858 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:50:25.651442 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:50:25.654906 ADC[4]: Raw value=905988 ID=7
551 11:50:25.655378 ADC[3]: Raw value=214021 ID=1
552 11:50:25.658514 RAM Code: 0x71
553 11:50:25.661512 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:50:25.668320 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:50:25.674505 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:50:25.681849 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:50:25.684694 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:50:25.688123 in-header: 03 07 00 00 08 00 00 00
559 11:50:25.691637 in-data: aa e4 47 04 13 02 00 00
560 11:50:25.694997 Chrome EC: UHEPI supported
561 11:50:25.701754 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:50:25.704506 in-header: 03 dd 00 00 08 00 00 00
563 11:50:25.708064 in-data: 90 20 60 08 00 00 00 00
564 11:50:25.711294 MRC: failed to locate region type 0.
565 11:50:25.717737 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:50:25.720991 DRAM-K: Running full calibration
567 11:50:25.727877 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:50:25.731280 header.status = 0x0
569 11:50:25.734488 header.version = 0x6 (expected: 0x6)
570 11:50:25.737777 header.size = 0xd00 (expected: 0xd00)
571 11:50:25.738253 header.flags = 0x0
572 11:50:25.743880 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:50:25.761542 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 11:50:25.768718 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:50:25.771527 dram_init: ddr_geometry: 2
576 11:50:25.775082 [EMI] MDL number = 2
577 11:50:25.775665 [EMI] Get MDL freq = 0
578 11:50:25.777759 dram_init: ddr_type: 0
579 11:50:25.778233 is_discrete_lpddr4: 1
580 11:50:25.781559 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:50:25.782134
582 11:50:25.784820
583 11:50:25.785384 [Bian_co] ETT version 0.0.0.1
584 11:50:25.791288 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:50:25.791868
586 11:50:25.795243 dramc_set_vcore_voltage set vcore to 650000
587 11:50:25.798251 Read voltage for 800, 4
588 11:50:25.798825 Vio18 = 0
589 11:50:25.799207 Vcore = 650000
590 11:50:25.800877 Vdram = 0
591 11:50:25.801397 Vddq = 0
592 11:50:25.801816 Vmddr = 0
593 11:50:25.804686 dram_init: config_dvfs: 1
594 11:50:25.807770 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:50:25.814047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:50:25.817735 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 11:50:25.821050 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 11:50:25.824103 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 11:50:25.830380 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 11:50:25.830857 MEM_TYPE=3, freq_sel=18
601 11:50:25.834040 sv_algorithm_assistance_LP4_1600
602 11:50:25.837379 ============ PULL DRAM RESETB DOWN ============
603 11:50:25.843650 ========== PULL DRAM RESETB DOWN end =========
604 11:50:25.846891 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:50:25.850242 ===================================
606 11:50:25.853540 LPDDR4 DRAM CONFIGURATION
607 11:50:25.856649 ===================================
608 11:50:25.857278 EX_ROW_EN[0] = 0x0
609 11:50:25.860703 EX_ROW_EN[1] = 0x0
610 11:50:25.863240 LP4Y_EN = 0x0
611 11:50:25.863821 WORK_FSP = 0x0
612 11:50:25.867304 WL = 0x2
613 11:50:25.867889 RL = 0x2
614 11:50:25.870031 BL = 0x2
615 11:50:25.870508 RPST = 0x0
616 11:50:25.874165 RD_PRE = 0x0
617 11:50:25.874810 WR_PRE = 0x1
618 11:50:25.876564 WR_PST = 0x0
619 11:50:25.877037 DBI_WR = 0x0
620 11:50:25.880552 DBI_RD = 0x0
621 11:50:25.881127 OTF = 0x1
622 11:50:25.883833 ===================================
623 11:50:25.886856 ===================================
624 11:50:25.890236 ANA top config
625 11:50:25.894150 ===================================
626 11:50:25.894726 DLL_ASYNC_EN = 0
627 11:50:25.896950 ALL_SLAVE_EN = 1
628 11:50:25.900198 NEW_RANK_MODE = 1
629 11:50:25.903682 DLL_IDLE_MODE = 1
630 11:50:25.907350 LP45_APHY_COMB_EN = 1
631 11:50:25.907926 TX_ODT_DIS = 1
632 11:50:25.909791 NEW_8X_MODE = 1
633 11:50:25.914263 ===================================
634 11:50:25.916892 ===================================
635 11:50:25.920414 data_rate = 1600
636 11:50:25.923436 CKR = 1
637 11:50:25.926934 DQ_P2S_RATIO = 8
638 11:50:25.930182 ===================================
639 11:50:25.930656 CA_P2S_RATIO = 8
640 11:50:25.933545 DQ_CA_OPEN = 0
641 11:50:25.936569 DQ_SEMI_OPEN = 0
642 11:50:25.939971 CA_SEMI_OPEN = 0
643 11:50:25.943600 CA_FULL_RATE = 0
644 11:50:25.946353 DQ_CKDIV4_EN = 1
645 11:50:25.946828 CA_CKDIV4_EN = 1
646 11:50:25.950068 CA_PREDIV_EN = 0
647 11:50:25.953238 PH8_DLY = 0
648 11:50:25.957877 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:50:25.959822 DQ_AAMCK_DIV = 4
650 11:50:25.963840 CA_AAMCK_DIV = 4
651 11:50:25.964410 CA_ADMCK_DIV = 4
652 11:50:25.966514 DQ_TRACK_CA_EN = 0
653 11:50:25.969682 CA_PICK = 800
654 11:50:25.973570 CA_MCKIO = 800
655 11:50:25.976396 MCKIO_SEMI = 0
656 11:50:25.980204 PLL_FREQ = 3068
657 11:50:25.983204 DQ_UI_PI_RATIO = 32
658 11:50:25.983832 CA_UI_PI_RATIO = 0
659 11:50:25.986615 ===================================
660 11:50:25.989979 ===================================
661 11:50:25.992998 memory_type:LPDDR4
662 11:50:25.996232 GP_NUM : 10
663 11:50:25.996726 SRAM_EN : 1
664 11:50:25.999654 MD32_EN : 0
665 11:50:26.002748 ===================================
666 11:50:26.006034 [ANA_INIT] >>>>>>>>>>>>>>
667 11:50:26.009745 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:50:26.013231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:50:26.016354 ===================================
670 11:50:26.016933 data_rate = 1600,PCW = 0X7600
671 11:50:26.019823 ===================================
672 11:50:26.023453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:50:26.029336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:50:26.036397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:50:26.039478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:50:26.043036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:50:26.046051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:50:26.049766 [ANA_INIT] flow start
679 11:50:26.052778 [ANA_INIT] PLL >>>>>>>>
680 11:50:26.053257 [ANA_INIT] PLL <<<<<<<<
681 11:50:26.055789 [ANA_INIT] MIDPI >>>>>>>>
682 11:50:26.059504 [ANA_INIT] MIDPI <<<<<<<<
683 11:50:26.059968 [ANA_INIT] DLL >>>>>>>>
684 11:50:26.062342 [ANA_INIT] flow end
685 11:50:26.066500 ============ LP4 DIFF to SE enter ============
686 11:50:26.069241 ============ LP4 DIFF to SE exit ============
687 11:50:26.072686 [ANA_INIT] <<<<<<<<<<<<<
688 11:50:26.076594 [Flow] Enable top DCM control >>>>>
689 11:50:26.079065 [Flow] Enable top DCM control <<<<<
690 11:50:26.082217 Enable DLL master slave shuffle
691 11:50:26.089463 ==============================================================
692 11:50:26.090047 Gating Mode config
693 11:50:26.096245 ==============================================================
694 11:50:26.096824 Config description:
695 11:50:26.105469 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:50:26.112675 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:50:26.119039 SELPH_MODE 0: By rank 1: By Phase
698 11:50:26.122031 ==============================================================
699 11:50:26.125528 GAT_TRACK_EN = 1
700 11:50:26.128777 RX_GATING_MODE = 2
701 11:50:26.132442 RX_GATING_TRACK_MODE = 2
702 11:50:26.135728 SELPH_MODE = 1
703 11:50:26.138621 PICG_EARLY_EN = 1
704 11:50:26.142186 VALID_LAT_VALUE = 1
705 11:50:26.148584 ==============================================================
706 11:50:26.152022 Enter into Gating configuration >>>>
707 11:50:26.155205 Exit from Gating configuration <<<<
708 11:50:26.158438 Enter into DVFS_PRE_config >>>>>
709 11:50:26.169090 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:50:26.172003 Exit from DVFS_PRE_config <<<<<
711 11:50:26.175383 Enter into PICG configuration >>>>
712 11:50:26.178744 Exit from PICG configuration <<<<
713 11:50:26.182102 [RX_INPUT] configuration >>>>>
714 11:50:26.182677 [RX_INPUT] configuration <<<<<
715 11:50:26.189757 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:50:26.192092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:50:26.199637 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:50:26.206848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:50:26.210835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:50:26.217678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:50:26.221026 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:50:26.224591 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:50:26.231053 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:50:26.234945 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:50:26.238620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:50:26.242017 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:50:26.244937 ===================================
728 11:50:26.249011 LPDDR4 DRAM CONFIGURATION
729 11:50:26.252482 ===================================
730 11:50:26.253111 EX_ROW_EN[0] = 0x0
731 11:50:26.256277 EX_ROW_EN[1] = 0x0
732 11:50:26.259567 LP4Y_EN = 0x0
733 11:50:26.259999 WORK_FSP = 0x0
734 11:50:26.260341 WL = 0x2
735 11:50:26.263502 RL = 0x2
736 11:50:26.263931 BL = 0x2
737 11:50:26.267117 RPST = 0x0
738 11:50:26.267548 RD_PRE = 0x0
739 11:50:26.271166 WR_PRE = 0x1
740 11:50:26.271747 WR_PST = 0x0
741 11:50:26.274541 DBI_WR = 0x0
742 11:50:26.274969 DBI_RD = 0x0
743 11:50:26.278405 OTF = 0x1
744 11:50:26.281975 ===================================
745 11:50:26.285984 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:50:26.289909 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:50:26.293682 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:50:26.297148 ===================================
749 11:50:26.297812 LPDDR4 DRAM CONFIGURATION
750 11:50:26.300464 ===================================
751 11:50:26.304457 EX_ROW_EN[0] = 0x10
752 11:50:26.308163 EX_ROW_EN[1] = 0x0
753 11:50:26.308749 LP4Y_EN = 0x0
754 11:50:26.309129 WORK_FSP = 0x0
755 11:50:26.312316 WL = 0x2
756 11:50:26.312899 RL = 0x2
757 11:50:26.315847 BL = 0x2
758 11:50:26.316421 RPST = 0x0
759 11:50:26.318700 RD_PRE = 0x0
760 11:50:26.319170 WR_PRE = 0x1
761 11:50:26.323138 WR_PST = 0x0
762 11:50:26.323722 DBI_WR = 0x0
763 11:50:26.326410 DBI_RD = 0x0
764 11:50:26.326883 OTF = 0x1
765 11:50:26.329770 ===================================
766 11:50:26.336581 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:50:26.340133 nWR fixed to 40
768 11:50:26.340691 [ModeRegInit_LP4] CH0 RK0
769 11:50:26.344773 [ModeRegInit_LP4] CH0 RK1
770 11:50:26.348023 [ModeRegInit_LP4] CH1 RK0
771 11:50:26.348553 [ModeRegInit_LP4] CH1 RK1
772 11:50:26.351093 match AC timing 13
773 11:50:26.355050 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:50:26.358100 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:50:26.365148 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:50:26.368240 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:50:26.371580 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:50:26.375016 [EMI DOE] emi_dcm 0
779 11:50:26.378244 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:50:26.378671 ==
781 11:50:26.381625 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:50:26.389324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:50:26.389954 ==
784 11:50:26.391804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:50:26.398111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:50:26.407038 [CA 0] Center 37 (6~68) winsize 63
787 11:50:26.411303 [CA 1] Center 36 (6~67) winsize 62
788 11:50:26.414381 [CA 2] Center 34 (4~65) winsize 62
789 11:50:26.417680 [CA 3] Center 34 (4~65) winsize 62
790 11:50:26.420955 [CA 4] Center 33 (3~64) winsize 62
791 11:50:26.424494 [CA 5] Center 33 (3~64) winsize 62
792 11:50:26.425065
793 11:50:26.427498 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:50:26.427967
795 11:50:26.430910 [CATrainingPosCal] consider 1 rank data
796 11:50:26.433868 u2DelayCellTimex100 = 270/100 ps
797 11:50:26.437204 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 11:50:26.440878 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 11:50:26.447096 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:50:26.450997 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:50:26.453843 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:50:26.457953 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:50:26.458533
804 11:50:26.461125 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:50:26.461635
806 11:50:26.463742 [CBTSetCACLKResult] CA Dly = 33
807 11:50:26.464215 CS Dly: 7 (0~38)
808 11:50:26.467071 ==
809 11:50:26.467500 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:50:26.474056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:50:26.474602 ==
812 11:50:26.477089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:50:26.483474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:50:26.493714 [CA 0] Center 37 (6~68) winsize 63
815 11:50:26.497257 [CA 1] Center 37 (7~68) winsize 62
816 11:50:26.499919 [CA 2] Center 34 (4~65) winsize 62
817 11:50:26.503150 [CA 3] Center 34 (4~65) winsize 62
818 11:50:26.506909 [CA 4] Center 33 (3~64) winsize 62
819 11:50:26.509874 [CA 5] Center 33 (2~64) winsize 63
820 11:50:26.510346
821 11:50:26.513342 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:50:26.513989
823 11:50:26.516484 [CATrainingPosCal] consider 2 rank data
824 11:50:26.519885 u2DelayCellTimex100 = 270/100 ps
825 11:50:26.523291 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 11:50:26.529930 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 11:50:26.530400 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:50:26.537108 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:50:26.537679 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:50:26.541339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:50:26.541820
832 11:50:26.548136 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:50:26.548696
834 11:50:26.549248 [CBTSetCACLKResult] CA Dly = 33
835 11:50:26.551650 CS Dly: 7 (0~39)
836 11:50:26.552250
837 11:50:26.554420 ----->DramcWriteLeveling(PI) begin...
838 11:50:26.554871 ==
839 11:50:26.558280 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:50:26.561693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:50:26.562235 ==
842 11:50:26.565074 Write leveling (Byte 0): 32 => 32
843 11:50:26.569042 Write leveling (Byte 1): 30 => 30
844 11:50:26.571931 DramcWriteLeveling(PI) end<-----
845 11:50:26.572363
846 11:50:26.572702 ==
847 11:50:26.575197 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:50:26.578946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:50:26.579381 ==
850 11:50:26.582091 [Gating] SW mode calibration
851 11:50:26.588347 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:50:26.595794 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:50:26.598744 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:50:26.604960 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:50:26.608129 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:50:26.611877 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:50:26.615066 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:50:26.621528 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:50:26.625102 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:50:26.628311 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:50:26.634826 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:50:26.638350 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:50:26.641388 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:50:26.647947 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:50:26.651323 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:50:26.654714 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:50:26.661669 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:50:26.664772 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:50:26.667798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:50:26.674603 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:50:26.677746 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 11:50:26.681072 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:50:26.688229 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:50:26.690959 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:50:26.694219 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:50:26.701867 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:50:26.704893 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:50:26.708012 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:50:26.714642 0 9 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
880 11:50:26.717973 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
881 11:50:26.721176 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:50:26.727561 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:50:26.731144 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:50:26.734328 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:50:26.741060 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:50:26.744045 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
887 11:50:26.747350 0 10 8 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
888 11:50:26.753838 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
889 11:50:26.757672 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:50:26.760440 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:50:26.767451 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:50:26.770510 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:50:26.774175 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:50:26.780399 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 11:50:26.783974 0 11 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
896 11:50:26.786936 0 11 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
897 11:50:26.793586 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:50:26.796906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:50:26.800419 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:50:26.806893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:50:26.810388 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:50:26.813760 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:50:26.820292 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:50:26.823428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
905 11:50:26.826781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:50:26.829952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:50:26.836735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:50:26.839979 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:50:26.843812 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:50:26.849803 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:50:26.853066 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:50:26.856590 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:50:26.863806 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:50:26.866754 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:50:26.870235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:50:26.876704 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:50:26.879935 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:50:26.883441 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:50:26.889838 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 11:50:26.893380 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
921 11:50:26.896529 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 11:50:26.899637 Total UI for P1: 0, mck2ui 16
923 11:50:26.903353 best dqsien dly found for B0: ( 0, 14, 10)
924 11:50:26.906533 Total UI for P1: 0, mck2ui 16
925 11:50:26.909843 best dqsien dly found for B1: ( 0, 14, 12)
926 11:50:26.913071 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
927 11:50:26.916402 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 11:50:26.919924
929 11:50:26.923141 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 11:50:26.927106 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 11:50:26.927607 [Gating] SW calibration Done
932 11:50:26.930767 ==
933 11:50:26.931263 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:50:26.937857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:50:26.938331 ==
936 11:50:26.938724 RX Vref Scan: 0
937 11:50:26.939069
938 11:50:26.942059 RX Vref 0 -> 0, step: 1
939 11:50:26.942506
940 11:50:26.945004 RX Delay -130 -> 252, step: 16
941 11:50:26.947731 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 11:50:26.951326 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 11:50:26.955080 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 11:50:26.958071 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 11:50:26.961726 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 11:50:26.964961 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 11:50:26.972500 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 11:50:26.976247 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 11:50:26.980100 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
950 11:50:26.983740 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
951 11:50:26.987599 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 11:50:26.990757 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
953 11:50:26.994204 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
954 11:50:26.997453 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
955 11:50:27.003961 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 11:50:27.007240 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
957 11:50:27.007400 ==
958 11:50:27.010785 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:50:27.013624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:50:27.013767 ==
961 11:50:27.017304 DQS Delay:
962 11:50:27.017456 DQS0 = 0, DQS1 = 0
963 11:50:27.017584 DQM Delay:
964 11:50:27.020715 DQM0 = 86, DQM1 = 71
965 11:50:27.020852 DQ Delay:
966 11:50:27.023618 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 11:50:27.027176 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
968 11:50:27.030241 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
969 11:50:27.034271 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
970 11:50:27.034504
971 11:50:27.034760
972 11:50:27.034989 ==
973 11:50:27.038139 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:50:27.041603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:50:27.041788 ==
976 11:50:27.045095
977 11:50:27.045379
978 11:50:27.045600 TX Vref Scan disable
979 11:50:27.048695 == TX Byte 0 ==
980 11:50:27.052013 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 11:50:27.055799 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 11:50:27.056111 == TX Byte 1 ==
983 11:50:27.062584 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
984 11:50:27.065810 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
985 11:50:27.066116 ==
986 11:50:27.068801 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:50:27.072128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:50:27.072528 ==
989 11:50:27.086833 TX Vref=22, minBit 12, minWin=26, winSum=438
990 11:50:27.089761 TX Vref=24, minBit 5, minWin=27, winSum=443
991 11:50:27.092985 TX Vref=26, minBit 8, minWin=27, winSum=447
992 11:50:27.096325 TX Vref=28, minBit 10, minWin=27, winSum=449
993 11:50:27.099824 TX Vref=30, minBit 8, minWin=27, winSum=448
994 11:50:27.106511 TX Vref=32, minBit 5, minWin=27, winSum=443
995 11:50:27.110136 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 28
996 11:50:27.110472
997 11:50:27.113307 Final TX Range 1 Vref 28
998 11:50:27.113721
999 11:50:27.113969 ==
1000 11:50:27.116960 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:50:27.119727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:50:27.123224 ==
1003 11:50:27.123647
1004 11:50:27.123996
1005 11:50:27.124265 TX Vref Scan disable
1006 11:50:27.126773 == TX Byte 0 ==
1007 11:50:27.130884 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 11:50:27.136549 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 11:50:27.136866 == TX Byte 1 ==
1010 11:50:27.140345 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1011 11:50:27.146873 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1012 11:50:27.147195
1013 11:50:27.147455 [DATLAT]
1014 11:50:27.147707 Freq=800, CH0 RK0
1015 11:50:27.147934
1016 11:50:27.150078 DATLAT Default: 0xa
1017 11:50:27.150479 0, 0xFFFF, sum = 0
1018 11:50:27.153363 1, 0xFFFF, sum = 0
1019 11:50:27.153723 2, 0xFFFF, sum = 0
1020 11:50:27.156553 3, 0xFFFF, sum = 0
1021 11:50:27.160535 4, 0xFFFF, sum = 0
1022 11:50:27.160843 5, 0xFFFF, sum = 0
1023 11:50:27.162866 6, 0xFFFF, sum = 0
1024 11:50:27.162950 7, 0xFFFF, sum = 0
1025 11:50:27.166596 8, 0xFFFF, sum = 0
1026 11:50:27.166680 9, 0x0, sum = 1
1027 11:50:27.170975 10, 0x0, sum = 2
1028 11:50:27.171059 11, 0x0, sum = 3
1029 11:50:27.171124 12, 0x0, sum = 4
1030 11:50:27.173169 best_step = 10
1031 11:50:27.173250
1032 11:50:27.173314 ==
1033 11:50:27.176132 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:50:27.179753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:50:27.179835 ==
1036 11:50:27.183124 RX Vref Scan: 1
1037 11:50:27.183204
1038 11:50:27.186512 Set Vref Range= 32 -> 127
1039 11:50:27.186593
1040 11:50:27.186657 RX Vref 32 -> 127, step: 1
1041 11:50:27.186718
1042 11:50:27.189270 RX Delay -111 -> 252, step: 8
1043 11:50:27.189351
1044 11:50:27.192835 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:50:27.196159 [Byte1]: 32
1046 11:50:27.199604
1047 11:50:27.199713 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:50:27.202660 [Byte1]: 33
1049 11:50:27.207058
1050 11:50:27.207139 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:50:27.210359 [Byte1]: 34
1052 11:50:27.215341
1053 11:50:27.215422 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:50:27.218032 [Byte1]: 35
1055 11:50:27.222361
1056 11:50:27.222442 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:50:27.225753 [Byte1]: 36
1058 11:50:27.229677
1059 11:50:27.229758 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:50:27.233073 [Byte1]: 37
1061 11:50:27.237738
1062 11:50:27.237839 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:50:27.240795 [Byte1]: 38
1064 11:50:27.245228
1065 11:50:27.245309 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:50:27.248841 [Byte1]: 39
1067 11:50:27.252939
1068 11:50:27.253035 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:50:27.256123 [Byte1]: 40
1070 11:50:27.260404
1071 11:50:27.260484 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:50:27.264053 [Byte1]: 41
1073 11:50:27.268262
1074 11:50:27.268344 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:50:27.271530 [Byte1]: 42
1076 11:50:27.275857
1077 11:50:27.275938 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:50:27.278978 [Byte1]: 43
1079 11:50:27.283728
1080 11:50:27.283809 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:50:27.287440 [Byte1]: 44
1082 11:50:27.291209
1083 11:50:27.291296 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:50:27.295207 [Byte1]: 45
1085 11:50:27.298595
1086 11:50:27.298698 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:50:27.302375 [Byte1]: 46
1088 11:50:27.306396
1089 11:50:27.306514 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:50:27.309923 [Byte1]: 47
1091 11:50:27.315110
1092 11:50:27.315244 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:50:27.317401 [Byte1]: 48
1094 11:50:27.321859
1095 11:50:27.322029 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:50:27.325061 [Byte1]: 49
1097 11:50:27.330105
1098 11:50:27.330395 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:50:27.333329 [Byte1]: 50
1100 11:50:27.337123
1101 11:50:27.340322 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:50:27.340426 [Byte1]: 51
1103 11:50:27.344827
1104 11:50:27.344908 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:50:27.348144 [Byte1]: 52
1106 11:50:27.352457
1107 11:50:27.352533 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:50:27.355627 [Byte1]: 53
1109 11:50:27.360287
1110 11:50:27.360395 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:50:27.363550 [Byte1]: 54
1112 11:50:27.367667
1113 11:50:27.367771 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:50:27.371208 [Byte1]: 55
1115 11:50:27.375630
1116 11:50:27.375731 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:50:27.378970 [Byte1]: 56
1118 11:50:27.383758
1119 11:50:27.383838 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:50:27.386877 [Byte1]: 57
1121 11:50:27.390863
1122 11:50:27.390944 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:50:27.394254 [Byte1]: 58
1124 11:50:27.398056
1125 11:50:27.402054 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:50:27.402136 [Byte1]: 59
1127 11:50:27.406279
1128 11:50:27.406360 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:50:27.409639 [Byte1]: 60
1130 11:50:27.414423
1131 11:50:27.414596 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:50:27.416869 [Byte1]: 61
1133 11:50:27.421664
1134 11:50:27.421833 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:50:27.425349 [Byte1]: 62
1136 11:50:27.428723
1137 11:50:27.428846 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:50:27.432177 [Byte1]: 63
1139 11:50:27.436800
1140 11:50:27.436964 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:50:27.440340 [Byte1]: 64
1142 11:50:27.444592
1143 11:50:27.444673 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:50:27.447691 [Byte1]: 65
1145 11:50:27.451694
1146 11:50:27.451808 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:50:27.455320 [Byte1]: 66
1148 11:50:27.460022
1149 11:50:27.460110 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:50:27.463499 [Byte1]: 67
1151 11:50:27.467903
1152 11:50:27.468533 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:50:27.471220 [Byte1]: 68
1154 11:50:27.475071
1155 11:50:27.475662 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:50:27.479002 [Byte1]: 69
1157 11:50:27.483173
1158 11:50:27.483809 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:50:27.486745 [Byte1]: 70
1160 11:50:27.490483
1161 11:50:27.491099 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:50:27.493731 [Byte1]: 71
1163 11:50:27.497620
1164 11:50:27.501073 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:50:27.501724 [Byte1]: 72
1166 11:50:27.505681
1167 11:50:27.506100 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:50:27.509801 [Byte1]: 73
1169 11:50:27.513160
1170 11:50:27.516620 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:50:27.517195 [Byte1]: 74
1172 11:50:27.521720
1173 11:50:27.522145 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:50:27.524103 [Byte1]: 75
1175 11:50:27.528971
1176 11:50:27.529614 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:50:27.532061 [Byte1]: 76
1178 11:50:27.536422
1179 11:50:27.536976 Set Vref, RX VrefLevel [Byte0]: 77
1180 11:50:27.539631 [Byte1]: 77
1181 11:50:27.543965
1182 11:50:27.544353 Set Vref, RX VrefLevel [Byte0]: 78
1183 11:50:27.547330 [Byte1]: 78
1184 11:50:27.551676
1185 11:50:27.552005 Set Vref, RX VrefLevel [Byte0]: 79
1186 11:50:27.554498 [Byte1]: 79
1187 11:50:27.559375
1188 11:50:27.559548 Set Vref, RX VrefLevel [Byte0]: 80
1189 11:50:27.564003 [Byte1]: 80
1190 11:50:27.566761
1191 11:50:27.566933 Set Vref, RX VrefLevel [Byte0]: 81
1192 11:50:27.570129 [Byte1]: 81
1193 11:50:27.574002
1194 11:50:27.574191 Set Vref, RX VrefLevel [Byte0]: 82
1195 11:50:27.578020 [Byte1]: 82
1196 11:50:27.582024
1197 11:50:27.582132 Set Vref, RX VrefLevel [Byte0]: 83
1198 11:50:27.585119 [Byte1]: 83
1199 11:50:27.590167
1200 11:50:27.590250 Final RX Vref Byte 0 = 67 to rank0
1201 11:50:27.593152 Final RX Vref Byte 1 = 57 to rank0
1202 11:50:27.596772 Final RX Vref Byte 0 = 67 to rank1
1203 11:50:27.600656 Final RX Vref Byte 1 = 57 to rank1==
1204 11:50:27.604163 Dram Type= 6, Freq= 0, CH_0, rank 0
1205 11:50:27.608739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 11:50:27.608844 ==
1207 11:50:27.608943 DQS Delay:
1208 11:50:27.611297 DQS0 = 0, DQS1 = 0
1209 11:50:27.611407 DQM Delay:
1210 11:50:27.614450 DQM0 = 88, DQM1 = 75
1211 11:50:27.614558 DQ Delay:
1212 11:50:27.618265 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1213 11:50:27.621998 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1214 11:50:27.625717 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1215 11:50:27.629656 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1216 11:50:27.629801
1217 11:50:27.629936
1218 11:50:27.637064 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1219 11:50:27.640335 CH0 RK0: MR19=606, MR18=4325
1220 11:50:27.644046 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1221 11:50:27.644157
1222 11:50:27.647865 ----->DramcWriteLeveling(PI) begin...
1223 11:50:27.647980 ==
1224 11:50:27.651331 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 11:50:27.695187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 11:50:27.695312 ==
1227 11:50:27.695593 Write leveling (Byte 0): 33 => 33
1228 11:50:27.695699 Write leveling (Byte 1): 32 => 32
1229 11:50:27.695972 DramcWriteLeveling(PI) end<-----
1230 11:50:27.696056
1231 11:50:27.696130 ==
1232 11:50:27.696203 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 11:50:27.696467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 11:50:27.696545 ==
1235 11:50:27.696630 [Gating] SW mode calibration
1236 11:50:27.696898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1237 11:50:27.697261 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1238 11:50:27.697748 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 11:50:27.739396 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1240 11:50:27.739503 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1241 11:50:27.739840 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:50:27.740473 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:50:27.740741 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:50:27.740812 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:50:27.741345 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:50:27.741668 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:50:27.742354 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:50:27.742981 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:50:27.743062 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:50:27.783533 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:50:27.784153 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:50:27.784609 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:50:27.784920 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:50:27.785019 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:50:27.785301 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1256 11:50:27.786199 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1257 11:50:27.786612 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:50:27.787153 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:50:27.787264 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:50:27.827922 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:50:27.828027 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:50:27.828769 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:50:27.829189 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 11:50:27.829277 0 9 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1265 11:50:27.829703 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1266 11:50:27.830090 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 11:50:27.830644 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 11:50:27.830904 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 11:50:27.830974 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 11:50:27.864736 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 11:50:27.865735 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1272 11:50:27.866279 0 10 8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
1273 11:50:27.866907 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1274 11:50:27.867405 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 11:50:27.867931 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 11:50:27.868491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 11:50:27.869070 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 11:50:27.872657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 11:50:27.873124 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1280 11:50:27.879035 0 11 8 | B1->B0 | 2d2d 3b3b | 1 0 | (0 0) (0 0)
1281 11:50:27.882395 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1282 11:50:27.885615 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 11:50:27.892360 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 11:50:27.895640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 11:50:27.898817 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 11:50:27.902375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 11:50:27.908788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 11:50:27.912212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1289 11:50:27.916130 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:50:27.922633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 11:50:27.925401 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 11:50:27.929960 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 11:50:27.935446 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 11:50:27.939089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 11:50:27.942201 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 11:50:27.948790 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 11:50:27.951967 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 11:50:27.955115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 11:50:27.961911 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 11:50:27.965334 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 11:50:27.968615 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 11:50:27.975992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 11:50:27.979864 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1304 11:50:27.981901 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1305 11:50:27.988286 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1306 11:50:27.988840 Total UI for P1: 0, mck2ui 16
1307 11:50:27.995185 best dqsien dly found for B0: ( 0, 14, 8)
1308 11:50:27.995769 Total UI for P1: 0, mck2ui 16
1309 11:50:28.001617 best dqsien dly found for B1: ( 0, 14, 8)
1310 11:50:28.005182 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1311 11:50:28.008258 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1312 11:50:28.008826
1313 11:50:28.011777 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1314 11:50:28.014785 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1315 11:50:28.018721 [Gating] SW calibration Done
1316 11:50:28.018986 ==
1317 11:50:28.021030 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 11:50:28.024561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 11:50:28.024745 ==
1320 11:50:28.028123 RX Vref Scan: 0
1321 11:50:28.028306
1322 11:50:28.028451 RX Vref 0 -> 0, step: 1
1323 11:50:28.028586
1324 11:50:28.031326 RX Delay -130 -> 252, step: 16
1325 11:50:28.037748 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1326 11:50:28.041215 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1327 11:50:28.044247 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1328 11:50:28.048274 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1329 11:50:28.051219 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1330 11:50:28.054365 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1331 11:50:28.061874 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1332 11:50:28.064672 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1333 11:50:28.067601 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1334 11:50:28.070752 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1335 11:50:28.074437 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1336 11:50:28.080924 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1337 11:50:28.084663 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1338 11:50:28.087568 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1339 11:50:28.090987 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1340 11:50:28.097840 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1341 11:50:28.097950 ==
1342 11:50:28.100897 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:50:28.104206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:50:28.104321 ==
1345 11:50:28.104418 DQS Delay:
1346 11:50:28.107804 DQS0 = 0, DQS1 = 0
1347 11:50:28.107886 DQM Delay:
1348 11:50:28.111439 DQM0 = 83, DQM1 = 75
1349 11:50:28.111521 DQ Delay:
1350 11:50:28.114604 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1351 11:50:28.117717 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1352 11:50:28.120946 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1353 11:50:28.124193 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1354 11:50:28.124345
1355 11:50:28.124439
1356 11:50:28.124523 ==
1357 11:50:28.127553 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:50:28.131157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:50:28.131352 ==
1360 11:50:28.131458
1361 11:50:28.131551
1362 11:50:28.134179 TX Vref Scan disable
1363 11:50:28.137719 == TX Byte 0 ==
1364 11:50:28.140803 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1365 11:50:28.144061 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1366 11:50:28.147696 == TX Byte 1 ==
1367 11:50:28.151125 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1368 11:50:28.154024 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1369 11:50:28.154226 ==
1370 11:50:28.157829 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 11:50:28.165257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 11:50:28.165714 ==
1373 11:50:28.176966 TX Vref=22, minBit 5, minWin=27, winSum=444
1374 11:50:28.179662 TX Vref=24, minBit 3, minWin=27, winSum=442
1375 11:50:28.183299 TX Vref=26, minBit 9, minWin=27, winSum=444
1376 11:50:28.185952 TX Vref=28, minBit 9, minWin=27, winSum=444
1377 11:50:28.189663 TX Vref=30, minBit 9, minWin=27, winSum=446
1378 11:50:28.196136 TX Vref=32, minBit 9, minWin=27, winSum=447
1379 11:50:28.200059 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 32
1380 11:50:28.200645
1381 11:50:28.202765 Final TX Range 1 Vref 32
1382 11:50:28.203331
1383 11:50:28.203698 ==
1384 11:50:28.205744 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 11:50:28.209787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 11:50:28.212497 ==
1387 11:50:28.213068
1388 11:50:28.213478
1389 11:50:28.213824 TX Vref Scan disable
1390 11:50:28.216172 == TX Byte 0 ==
1391 11:50:28.219193 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1392 11:50:28.226747 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1393 11:50:28.227307 == TX Byte 1 ==
1394 11:50:28.229569 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1395 11:50:28.236307 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1396 11:50:28.236884
1397 11:50:28.237257 [DATLAT]
1398 11:50:28.237655 Freq=800, CH0 RK1
1399 11:50:28.237992
1400 11:50:28.239071 DATLAT Default: 0xa
1401 11:50:28.242422 0, 0xFFFF, sum = 0
1402 11:50:28.242915 1, 0xFFFF, sum = 0
1403 11:50:28.246045 2, 0xFFFF, sum = 0
1404 11:50:28.246617 3, 0xFFFF, sum = 0
1405 11:50:28.248818 4, 0xFFFF, sum = 0
1406 11:50:28.249284 5, 0xFFFF, sum = 0
1407 11:50:28.252198 6, 0xFFFF, sum = 0
1408 11:50:28.252821 7, 0xFFFF, sum = 0
1409 11:50:28.255603 8, 0xFFFF, sum = 0
1410 11:50:28.256076 9, 0x0, sum = 1
1411 11:50:28.258744 10, 0x0, sum = 2
1412 11:50:28.259213 11, 0x0, sum = 3
1413 11:50:28.262211 12, 0x0, sum = 4
1414 11:50:28.262802 best_step = 10
1415 11:50:28.263174
1416 11:50:28.263516 ==
1417 11:50:28.265522 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 11:50:28.268719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 11:50:28.269285 ==
1420 11:50:28.272114 RX Vref Scan: 0
1421 11:50:28.272577
1422 11:50:28.275327 RX Vref 0 -> 0, step: 1
1423 11:50:28.275791
1424 11:50:28.276156 RX Delay -111 -> 252, step: 8
1425 11:50:28.283334 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1426 11:50:28.286140 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1427 11:50:28.289768 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1428 11:50:28.292606 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1429 11:50:28.300082 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1430 11:50:28.303695 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1431 11:50:28.306162 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1432 11:50:28.309222 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1433 11:50:28.312725 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1434 11:50:28.319267 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1435 11:50:28.322461 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1436 11:50:28.325641 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1437 11:50:28.328959 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1438 11:50:28.331962 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1439 11:50:28.339061 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1440 11:50:28.341715 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1441 11:50:28.342351 ==
1442 11:50:28.345285 Dram Type= 6, Freq= 0, CH_0, rank 1
1443 11:50:28.348402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:50:28.348860 ==
1445 11:50:28.351920 DQS Delay:
1446 11:50:28.352484 DQS0 = 0, DQS1 = 0
1447 11:50:28.353029 DQM Delay:
1448 11:50:28.355003 DQM0 = 85, DQM1 = 77
1449 11:50:28.355532 DQ Delay:
1450 11:50:28.358440 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =80
1451 11:50:28.361883 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1452 11:50:28.365066 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1453 11:50:28.368538 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1454 11:50:28.368958
1455 11:50:28.369284
1456 11:50:28.378624 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
1457 11:50:28.381628 CH0 RK1: MR19=606, MR18=3A02
1458 11:50:28.384746 CH0_RK1: MR19=0x606, MR18=0x3A02, DQSOSC=395, MR23=63, INC=94, DEC=63
1459 11:50:28.388505 [RxdqsGatingPostProcess] freq 800
1460 11:50:28.394955 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1461 11:50:28.399270 Pre-setting of DQS Precalculation
1462 11:50:28.401550 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1463 11:50:28.402101 ==
1464 11:50:28.404713 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 11:50:28.411135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 11:50:28.411435 ==
1467 11:50:28.415105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 11:50:28.421503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 11:50:28.431078 [CA 0] Center 36 (6~67) winsize 62
1470 11:50:28.434225 [CA 1] Center 36 (6~67) winsize 62
1471 11:50:28.437379 [CA 2] Center 34 (4~65) winsize 62
1472 11:50:28.441061 [CA 3] Center 34 (3~65) winsize 63
1473 11:50:28.444314 [CA 4] Center 34 (4~65) winsize 62
1474 11:50:28.447812 [CA 5] Center 34 (3~65) winsize 63
1475 11:50:28.448113
1476 11:50:28.450803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 11:50:28.451122
1478 11:50:28.454471 [CATrainingPosCal] consider 1 rank data
1479 11:50:28.457714 u2DelayCellTimex100 = 270/100 ps
1480 11:50:28.460723 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 11:50:28.464354 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 11:50:28.471191 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 11:50:28.474158 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1484 11:50:28.477128 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 11:50:28.481330 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1486 11:50:28.481759
1487 11:50:28.483771 CA PerBit enable=1, Macro0, CA PI delay=34
1488 11:50:28.484152
1489 11:50:28.487130 [CBTSetCACLKResult] CA Dly = 34
1490 11:50:28.487525 CS Dly: 5 (0~36)
1491 11:50:28.490794 ==
1492 11:50:28.491124 Dram Type= 6, Freq= 0, CH_1, rank 1
1493 11:50:28.497693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 11:50:28.497925 ==
1495 11:50:28.500237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1496 11:50:28.507020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1497 11:50:28.516633 [CA 0] Center 36 (6~67) winsize 62
1498 11:50:28.520397 [CA 1] Center 36 (6~67) winsize 62
1499 11:50:28.523545 [CA 2] Center 34 (4~65) winsize 62
1500 11:50:28.527472 [CA 3] Center 34 (3~65) winsize 63
1501 11:50:28.530482 [CA 4] Center 34 (4~65) winsize 62
1502 11:50:28.533762 [CA 5] Center 34 (3~65) winsize 63
1503 11:50:28.534064
1504 11:50:28.536851 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1505 11:50:28.537118
1506 11:50:28.540421 [CATrainingPosCal] consider 2 rank data
1507 11:50:28.543888 u2DelayCellTimex100 = 270/100 ps
1508 11:50:28.547619 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1509 11:50:28.554143 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1510 11:50:28.557573 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1511 11:50:28.560862 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1512 11:50:28.563978 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1513 11:50:28.567167 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1514 11:50:28.567637
1515 11:50:28.570281 CA PerBit enable=1, Macro0, CA PI delay=34
1516 11:50:28.570755
1517 11:50:28.573988 [CBTSetCACLKResult] CA Dly = 34
1518 11:50:28.574456 CS Dly: 5 (0~37)
1519 11:50:28.574830
1520 11:50:28.576911 ----->DramcWriteLeveling(PI) begin...
1521 11:50:28.580509 ==
1522 11:50:28.583752 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 11:50:28.586631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 11:50:28.587062 ==
1525 11:50:28.590321 Write leveling (Byte 0): 27 => 27
1526 11:50:28.593351 Write leveling (Byte 1): 28 => 28
1527 11:50:28.596687 DramcWriteLeveling(PI) end<-----
1528 11:50:28.597115
1529 11:50:28.597529 ==
1530 11:50:28.600676 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 11:50:28.603633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 11:50:28.604064 ==
1533 11:50:28.606630 [Gating] SW mode calibration
1534 11:50:28.613308 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1535 11:50:28.619897 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1536 11:50:28.623009 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1537 11:50:28.626417 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1538 11:50:28.633725 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1539 11:50:28.636464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:50:28.639620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:50:28.646289 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:50:28.649694 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:50:28.652963 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:50:28.656221 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:50:28.663045 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:50:28.666314 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:50:28.669265 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:50:28.676057 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:50:28.679891 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:50:28.682544 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:50:28.689238 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:50:28.692375 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:50:28.696125 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1554 11:50:28.702683 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:50:28.706284 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:50:28.709372 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:50:28.715896 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:50:28.718988 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:50:28.722776 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:50:28.729556 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 11:50:28.732371 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1562 11:50:28.735628 0 9 8 | B1->B0 | 2c2c 3130 | 1 1 | (1 1) (1 1)
1563 11:50:28.742287 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 11:50:28.745506 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 11:50:28.748646 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 11:50:28.755644 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 11:50:28.759265 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 11:50:28.762437 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1569 11:50:28.768459 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1570 11:50:28.771871 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
1571 11:50:28.775394 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 11:50:28.781843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 11:50:28.785256 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 11:50:28.788863 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 11:50:28.795163 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 11:50:28.798542 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1577 11:50:28.802102 0 11 4 | B1->B0 | 2424 2b2a | 0 1 | (0 0) (0 0)
1578 11:50:28.808929 0 11 8 | B1->B0 | 3737 3d3d | 0 1 | (0 0) (0 0)
1579 11:50:28.812101 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 11:50:28.815753 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 11:50:28.822894 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 11:50:28.825578 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 11:50:28.829343 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 11:50:28.835531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1585 11:50:28.839784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1586 11:50:28.842416 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1587 11:50:28.845546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 11:50:28.852016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 11:50:28.855923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 11:50:28.858762 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 11:50:28.865863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 11:50:28.868687 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 11:50:28.871842 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 11:50:28.878554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 11:50:28.882273 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 11:50:28.885245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 11:50:28.892136 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 11:50:28.895240 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 11:50:28.898425 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 11:50:28.905284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1601 11:50:28.908412 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1602 11:50:28.911611 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1603 11:50:28.915230 Total UI for P1: 0, mck2ui 16
1604 11:50:28.918350 best dqsien dly found for B0: ( 0, 14, 4)
1605 11:50:28.924992 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1606 11:50:28.925605 Total UI for P1: 0, mck2ui 16
1607 11:50:28.931775 best dqsien dly found for B1: ( 0, 14, 8)
1608 11:50:28.935087 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1609 11:50:28.938436 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1610 11:50:28.938960
1611 11:50:28.942025 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1612 11:50:28.945154 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1613 11:50:28.948499 [Gating] SW calibration Done
1614 11:50:28.949063 ==
1615 11:50:28.951942 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 11:50:28.955291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 11:50:28.955865 ==
1618 11:50:28.957998 RX Vref Scan: 0
1619 11:50:28.958466
1620 11:50:28.958877 RX Vref 0 -> 0, step: 1
1621 11:50:28.959242
1622 11:50:28.961303 RX Delay -130 -> 252, step: 16
1623 11:50:28.965185 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1624 11:50:28.971544 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1625 11:50:28.975176 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1626 11:50:28.978291 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1627 11:50:28.981541 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1628 11:50:28.984540 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1629 11:50:28.991450 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1630 11:50:28.994533 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1631 11:50:28.997881 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1632 11:50:29.001583 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1633 11:50:29.007975 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1634 11:50:29.011093 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1635 11:50:29.014379 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1636 11:50:29.017785 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1637 11:50:29.021584 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1638 11:50:29.027597 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1639 11:50:29.028072 ==
1640 11:50:29.031716 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:50:29.034219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:50:29.034690 ==
1643 11:50:29.035063 DQS Delay:
1644 11:50:29.037752 DQS0 = 0, DQS1 = 0
1645 11:50:29.038222 DQM Delay:
1646 11:50:29.041474 DQM0 = 89, DQM1 = 78
1647 11:50:29.041944 DQ Delay:
1648 11:50:29.044455 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1649 11:50:29.047497 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1650 11:50:29.050894 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1651 11:50:29.053974 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1652 11:50:29.054401
1653 11:50:29.054734
1654 11:50:29.055049 ==
1655 11:50:29.057484 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 11:50:29.060766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 11:50:29.061194 ==
1658 11:50:29.064312
1659 11:50:29.064748
1660 11:50:29.065081 TX Vref Scan disable
1661 11:50:29.067946 == TX Byte 0 ==
1662 11:50:29.070713 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1663 11:50:29.074607 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1664 11:50:29.077488 == TX Byte 1 ==
1665 11:50:29.080738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1666 11:50:29.083884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1667 11:50:29.084419 ==
1668 11:50:29.087138 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 11:50:29.093900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 11:50:29.094342 ==
1671 11:50:29.105969 TX Vref=22, minBit 10, minWin=26, winSum=444
1672 11:50:29.109698 TX Vref=24, minBit 8, minWin=27, winSum=445
1673 11:50:29.112958 TX Vref=26, minBit 9, minWin=27, winSum=452
1674 11:50:29.116026 TX Vref=28, minBit 9, minWin=27, winSum=450
1675 11:50:29.119676 TX Vref=30, minBit 11, minWin=27, winSum=450
1676 11:50:29.126210 TX Vref=32, minBit 0, minWin=27, winSum=444
1677 11:50:29.129262 [TxChooseVref] Worse bit 9, Min win 27, Win sum 452, Final Vref 26
1678 11:50:29.129760
1679 11:50:29.132341 Final TX Range 1 Vref 26
1680 11:50:29.132765
1681 11:50:29.133100 ==
1682 11:50:29.135900 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 11:50:29.139877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 11:50:29.142292 ==
1685 11:50:29.142717
1686 11:50:29.143051
1687 11:50:29.143361 TX Vref Scan disable
1688 11:50:29.146305 == TX Byte 0 ==
1689 11:50:29.149687 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1690 11:50:29.156614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1691 11:50:29.157128 == TX Byte 1 ==
1692 11:50:29.159081 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1693 11:50:29.165887 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1694 11:50:29.166388
1695 11:50:29.166807 [DATLAT]
1696 11:50:29.167130 Freq=800, CH1 RK0
1697 11:50:29.167706
1698 11:50:29.169137 DATLAT Default: 0xa
1699 11:50:29.172528 0, 0xFFFF, sum = 0
1700 11:50:29.172954 1, 0xFFFF, sum = 0
1701 11:50:29.175824 2, 0xFFFF, sum = 0
1702 11:50:29.176456 3, 0xFFFF, sum = 0
1703 11:50:29.179141 4, 0xFFFF, sum = 0
1704 11:50:29.179638 5, 0xFFFF, sum = 0
1705 11:50:29.182427 6, 0xFFFF, sum = 0
1706 11:50:29.182870 7, 0xFFFF, sum = 0
1707 11:50:29.186405 8, 0xFFFF, sum = 0
1708 11:50:29.186931 9, 0x0, sum = 1
1709 11:50:29.190157 10, 0x0, sum = 2
1710 11:50:29.190686 11, 0x0, sum = 3
1711 11:50:29.192538 12, 0x0, sum = 4
1712 11:50:29.193063 best_step = 10
1713 11:50:29.193400
1714 11:50:29.193764 ==
1715 11:50:29.195696 Dram Type= 6, Freq= 0, CH_1, rank 0
1716 11:50:29.199418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1717 11:50:29.199941 ==
1718 11:50:29.202562 RX Vref Scan: 1
1719 11:50:29.202987
1720 11:50:29.206116 Set Vref Range= 32 -> 127
1721 11:50:29.206642
1722 11:50:29.206984 RX Vref 32 -> 127, step: 1
1723 11:50:29.207300
1724 11:50:29.209193 RX Delay -95 -> 252, step: 8
1725 11:50:29.209767
1726 11:50:29.212607 Set Vref, RX VrefLevel [Byte0]: 32
1727 11:50:29.215823 [Byte1]: 32
1728 11:50:29.218847
1729 11:50:29.219266 Set Vref, RX VrefLevel [Byte0]: 33
1730 11:50:29.222472 [Byte1]: 33
1731 11:50:29.226625
1732 11:50:29.227356 Set Vref, RX VrefLevel [Byte0]: 34
1733 11:50:29.229671 [Byte1]: 34
1734 11:50:29.233855
1735 11:50:29.234288 Set Vref, RX VrefLevel [Byte0]: 35
1736 11:50:29.237229 [Byte1]: 35
1737 11:50:29.241502
1738 11:50:29.241924 Set Vref, RX VrefLevel [Byte0]: 36
1739 11:50:29.245095 [Byte1]: 36
1740 11:50:29.249322
1741 11:50:29.249774 Set Vref, RX VrefLevel [Byte0]: 37
1742 11:50:29.252660 [Byte1]: 37
1743 11:50:29.256805
1744 11:50:29.257224 Set Vref, RX VrefLevel [Byte0]: 38
1745 11:50:29.261206 [Byte1]: 38
1746 11:50:29.265211
1747 11:50:29.265663 Set Vref, RX VrefLevel [Byte0]: 39
1748 11:50:29.267654 [Byte1]: 39
1749 11:50:29.272528
1750 11:50:29.272944 Set Vref, RX VrefLevel [Byte0]: 40
1751 11:50:29.275372 [Byte1]: 40
1752 11:50:29.279596
1753 11:50:29.280145 Set Vref, RX VrefLevel [Byte0]: 41
1754 11:50:29.282708 [Byte1]: 41
1755 11:50:29.287603
1756 11:50:29.288118 Set Vref, RX VrefLevel [Byte0]: 42
1757 11:50:29.291082 [Byte1]: 42
1758 11:50:29.294957
1759 11:50:29.295376 Set Vref, RX VrefLevel [Byte0]: 43
1760 11:50:29.298096 [Byte1]: 43
1761 11:50:29.302997
1762 11:50:29.303512 Set Vref, RX VrefLevel [Byte0]: 44
1763 11:50:29.306069 [Byte1]: 44
1764 11:50:29.309694
1765 11:50:29.310117 Set Vref, RX VrefLevel [Byte0]: 45
1766 11:50:29.313399 [Byte1]: 45
1767 11:50:29.317542
1768 11:50:29.317966 Set Vref, RX VrefLevel [Byte0]: 46
1769 11:50:29.320776 [Byte1]: 46
1770 11:50:29.324957
1771 11:50:29.325379 Set Vref, RX VrefLevel [Byte0]: 47
1772 11:50:29.328494 [Byte1]: 47
1773 11:50:29.333349
1774 11:50:29.333809 Set Vref, RX VrefLevel [Byte0]: 48
1775 11:50:29.335889 [Byte1]: 48
1776 11:50:29.339966
1777 11:50:29.340526 Set Vref, RX VrefLevel [Byte0]: 49
1778 11:50:29.343379 [Byte1]: 49
1779 11:50:29.347549
1780 11:50:29.348239 Set Vref, RX VrefLevel [Byte0]: 50
1781 11:50:29.351361 [Byte1]: 50
1782 11:50:29.355236
1783 11:50:29.355849 Set Vref, RX VrefLevel [Byte0]: 51
1784 11:50:29.358486 [Byte1]: 51
1785 11:50:29.362674
1786 11:50:29.362815 Set Vref, RX VrefLevel [Byte0]: 52
1787 11:50:29.366108 [Byte1]: 52
1788 11:50:29.370404
1789 11:50:29.370506 Set Vref, RX VrefLevel [Byte0]: 53
1790 11:50:29.373856 [Byte1]: 53
1791 11:50:29.377836
1792 11:50:29.377911 Set Vref, RX VrefLevel [Byte0]: 54
1793 11:50:29.381157 [Byte1]: 54
1794 11:50:29.385392
1795 11:50:29.385525 Set Vref, RX VrefLevel [Byte0]: 55
1796 11:50:29.388723 [Byte1]: 55
1797 11:50:29.392871
1798 11:50:29.392945 Set Vref, RX VrefLevel [Byte0]: 56
1799 11:50:29.396268 [Byte1]: 56
1800 11:50:29.401442
1801 11:50:29.401527 Set Vref, RX VrefLevel [Byte0]: 57
1802 11:50:29.404111 [Byte1]: 57
1803 11:50:29.408495
1804 11:50:29.408596 Set Vref, RX VrefLevel [Byte0]: 58
1805 11:50:29.411684 [Byte1]: 58
1806 11:50:29.416200
1807 11:50:29.416301 Set Vref, RX VrefLevel [Byte0]: 59
1808 11:50:29.419349 [Byte1]: 59
1809 11:50:29.423644
1810 11:50:29.423765 Set Vref, RX VrefLevel [Byte0]: 60
1811 11:50:29.426721 [Byte1]: 60
1812 11:50:29.431136
1813 11:50:29.431270 Set Vref, RX VrefLevel [Byte0]: 61
1814 11:50:29.434427 [Byte1]: 61
1815 11:50:29.438812
1816 11:50:29.438948 Set Vref, RX VrefLevel [Byte0]: 62
1817 11:50:29.442358 [Byte1]: 62
1818 11:50:29.446513
1819 11:50:29.446662 Set Vref, RX VrefLevel [Byte0]: 63
1820 11:50:29.449517 [Byte1]: 63
1821 11:50:29.453761
1822 11:50:29.453895 Set Vref, RX VrefLevel [Byte0]: 64
1823 11:50:29.457296 [Byte1]: 64
1824 11:50:29.461853
1825 11:50:29.461989 Set Vref, RX VrefLevel [Byte0]: 65
1826 11:50:29.464618 [Byte1]: 65
1827 11:50:29.468997
1828 11:50:29.469180 Set Vref, RX VrefLevel [Byte0]: 66
1829 11:50:29.472427 [Byte1]: 66
1830 11:50:29.476680
1831 11:50:29.476814 Set Vref, RX VrefLevel [Byte0]: 67
1832 11:50:29.480448 [Byte1]: 67
1833 11:50:29.484375
1834 11:50:29.484526 Set Vref, RX VrefLevel [Byte0]: 68
1835 11:50:29.487527 [Byte1]: 68
1836 11:50:29.492083
1837 11:50:29.492347 Set Vref, RX VrefLevel [Byte0]: 69
1838 11:50:29.495170 [Byte1]: 69
1839 11:50:29.499658
1840 11:50:29.499929 Set Vref, RX VrefLevel [Byte0]: 70
1841 11:50:29.503271 [Byte1]: 70
1842 11:50:29.506868
1843 11:50:29.507149 Set Vref, RX VrefLevel [Byte0]: 71
1844 11:50:29.510279 [Byte1]: 71
1845 11:50:29.514812
1846 11:50:29.515095 Set Vref, RX VrefLevel [Byte0]: 72
1847 11:50:29.518216 [Byte1]: 72
1848 11:50:29.522610
1849 11:50:29.522811 Set Vref, RX VrefLevel [Byte0]: 73
1850 11:50:29.525634 [Byte1]: 73
1851 11:50:29.530342
1852 11:50:29.530542 Set Vref, RX VrefLevel [Byte0]: 74
1853 11:50:29.534088 [Byte1]: 74
1854 11:50:29.537954
1855 11:50:29.538154 Set Vref, RX VrefLevel [Byte0]: 75
1856 11:50:29.540858 [Byte1]: 75
1857 11:50:29.545326
1858 11:50:29.545669 Set Vref, RX VrefLevel [Byte0]: 76
1859 11:50:29.548453 [Byte1]: 76
1860 11:50:29.553031
1861 11:50:29.553449 Final RX Vref Byte 0 = 63 to rank0
1862 11:50:29.557008 Final RX Vref Byte 1 = 63 to rank0
1863 11:50:29.560470 Final RX Vref Byte 0 = 63 to rank1
1864 11:50:29.563257 Final RX Vref Byte 1 = 63 to rank1==
1865 11:50:29.566445 Dram Type= 6, Freq= 0, CH_1, rank 0
1866 11:50:29.573033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 11:50:29.573583 ==
1868 11:50:29.573923 DQS Delay:
1869 11:50:29.574238 DQS0 = 0, DQS1 = 0
1870 11:50:29.576600 DQM Delay:
1871 11:50:29.577120 DQM0 = 86, DQM1 = 79
1872 11:50:29.580238 DQ Delay:
1873 11:50:29.583062 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1874 11:50:29.586548 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1875 11:50:29.589379 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1876 11:50:29.593458 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =92
1877 11:50:29.593988
1878 11:50:29.594369
1879 11:50:29.600444 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1880 11:50:29.602729 CH1 RK0: MR19=606, MR18=331F
1881 11:50:29.609628 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1882 11:50:29.610165
1883 11:50:29.612587 ----->DramcWriteLeveling(PI) begin...
1884 11:50:29.613166 ==
1885 11:50:29.615923 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 11:50:29.619289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 11:50:29.619851 ==
1888 11:50:29.622490 Write leveling (Byte 0): 27 => 27
1889 11:50:29.626304 Write leveling (Byte 1): 31 => 31
1890 11:50:29.629173 DramcWriteLeveling(PI) end<-----
1891 11:50:29.629773
1892 11:50:29.630306 ==
1893 11:50:29.632424 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 11:50:29.636001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 11:50:29.636552 ==
1896 11:50:29.639125 [Gating] SW mode calibration
1897 11:50:29.645457 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1898 11:50:29.652376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1899 11:50:29.655521 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1900 11:50:29.661988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1901 11:50:29.665437 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:50:29.668722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:50:29.671982 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:50:29.678507 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:50:29.682125 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:50:29.685210 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:50:29.692029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:50:29.695176 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:50:29.698653 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:50:29.705537 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:50:29.708332 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:50:29.712434 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:50:29.718628 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:50:29.721674 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:50:29.725172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:50:29.732336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1917 11:50:29.735190 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1918 11:50:29.738285 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:50:29.744994 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:50:29.748312 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:50:29.751687 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:50:29.758428 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:50:29.762147 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:50:29.765133 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:50:29.771404 0 9 8 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
1926 11:50:29.774702 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 11:50:29.778441 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 11:50:29.784881 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 11:50:29.788353 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 11:50:29.791724 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 11:50:29.798197 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1932 11:50:29.801358 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1933 11:50:29.805031 0 10 8 | B1->B0 | 2525 2d2d | 0 1 | (0 0) (1 0)
1934 11:50:29.811369 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 11:50:29.815350 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 11:50:29.818524 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 11:50:29.824939 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 11:50:29.828158 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 11:50:29.832140 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 11:50:29.837930 0 11 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1941 11:50:29.841949 0 11 8 | B1->B0 | 3d3d 3939 | 0 0 | (0 0) (0 0)
1942 11:50:29.845717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 11:50:29.852082 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 11:50:29.854527 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 11:50:29.857978 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 11:50:29.864783 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 11:50:29.868156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 11:50:29.871493 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1949 11:50:29.877648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1950 11:50:29.881264 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:50:29.884298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:50:29.888114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 11:50:29.894472 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 11:50:29.898091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 11:50:29.900855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 11:50:29.907752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 11:50:29.911230 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 11:50:29.914551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 11:50:29.920915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 11:50:29.924258 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 11:50:29.927835 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 11:50:29.934915 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 11:50:29.938940 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 11:50:29.940749 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1965 11:50:29.944204 Total UI for P1: 0, mck2ui 16
1966 11:50:29.947451 best dqsien dly found for B1: ( 0, 14, 2)
1967 11:50:29.954091 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1968 11:50:29.954564 Total UI for P1: 0, mck2ui 16
1969 11:50:29.961172 best dqsien dly found for B0: ( 0, 14, 4)
1970 11:50:29.963992 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1971 11:50:29.967904 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1972 11:50:29.968372
1973 11:50:29.970972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1974 11:50:29.974541 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1975 11:50:29.977689 [Gating] SW calibration Done
1976 11:50:29.978268 ==
1977 11:50:29.981015 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 11:50:29.984515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 11:50:29.984985 ==
1980 11:50:29.987671 RX Vref Scan: 0
1981 11:50:29.988238
1982 11:50:29.988610 RX Vref 0 -> 0, step: 1
1983 11:50:29.988954
1984 11:50:29.991258 RX Delay -130 -> 252, step: 16
1985 11:50:29.994584 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1986 11:50:30.000782 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1987 11:50:30.004144 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1988 11:50:30.007526 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1989 11:50:30.011487 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1990 11:50:30.014010 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1991 11:50:30.020742 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1992 11:50:30.023724 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1993 11:50:30.027064 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1994 11:50:30.030966 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1995 11:50:30.033903 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1996 11:50:30.041043 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1997 11:50:30.043758 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1998 11:50:30.047512 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1999 11:50:30.050385 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2000 11:50:30.056839 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2001 11:50:30.057361 ==
2002 11:50:30.060599 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 11:50:30.063856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 11:50:30.064286 ==
2005 11:50:30.064679 DQS Delay:
2006 11:50:30.067002 DQS0 = 0, DQS1 = 0
2007 11:50:30.067521 DQM Delay:
2008 11:50:30.070279 DQM0 = 87, DQM1 = 77
2009 11:50:30.070826 DQ Delay:
2010 11:50:30.073187 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
2011 11:50:30.077031 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2012 11:50:30.080033 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
2013 11:50:30.083132 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2014 11:50:30.083560
2015 11:50:30.083915
2016 11:50:30.084335 ==
2017 11:50:30.087193 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:50:30.090409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:50:30.093468 ==
2020 11:50:30.093987
2021 11:50:30.094325
2022 11:50:30.094634 TX Vref Scan disable
2023 11:50:30.096651 == TX Byte 0 ==
2024 11:50:30.100547 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2025 11:50:30.103457 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2026 11:50:30.107117 == TX Byte 1 ==
2027 11:50:30.110212 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2028 11:50:30.113478 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2029 11:50:30.116647 ==
2030 11:50:30.117069 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 11:50:30.123587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 11:50:30.124015 ==
2033 11:50:30.136093 TX Vref=22, minBit 8, minWin=26, winSum=442
2034 11:50:30.139206 TX Vref=24, minBit 8, minWin=26, winSum=447
2035 11:50:30.142527 TX Vref=26, minBit 9, minWin=27, winSum=448
2036 11:50:30.145684 TX Vref=28, minBit 15, minWin=27, winSum=454
2037 11:50:30.148904 TX Vref=30, minBit 8, minWin=27, winSum=451
2038 11:50:30.155840 TX Vref=32, minBit 8, minWin=27, winSum=448
2039 11:50:30.159027 [TxChooseVref] Worse bit 15, Min win 27, Win sum 454, Final Vref 28
2040 11:50:30.159455
2041 11:50:30.162392 Final TX Range 1 Vref 28
2042 11:50:30.162837
2043 11:50:30.163173 ==
2044 11:50:30.165793 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 11:50:30.169005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 11:50:30.169521 ==
2047 11:50:30.172038
2048 11:50:30.172457
2049 11:50:30.172793 TX Vref Scan disable
2050 11:50:30.175475 == TX Byte 0 ==
2051 11:50:30.179546 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2052 11:50:30.185557 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2053 11:50:30.185988 == TX Byte 1 ==
2054 11:50:30.189377 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2055 11:50:30.196036 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2056 11:50:30.196564
2057 11:50:30.196905 [DATLAT]
2058 11:50:30.197217 Freq=800, CH1 RK1
2059 11:50:30.197560
2060 11:50:30.199205 DATLAT Default: 0xa
2061 11:50:30.199719 0, 0xFFFF, sum = 0
2062 11:50:30.202220 1, 0xFFFF, sum = 0
2063 11:50:30.202651 2, 0xFFFF, sum = 0
2064 11:50:30.205487 3, 0xFFFF, sum = 0
2065 11:50:30.205919 4, 0xFFFF, sum = 0
2066 11:50:30.209016 5, 0xFFFF, sum = 0
2067 11:50:30.212190 6, 0xFFFF, sum = 0
2068 11:50:30.212717 7, 0xFFFF, sum = 0
2069 11:50:30.215340 8, 0xFFFF, sum = 0
2070 11:50:30.215769 9, 0x0, sum = 1
2071 11:50:30.216113 10, 0x0, sum = 2
2072 11:50:30.218701 11, 0x0, sum = 3
2073 11:50:30.219128 12, 0x0, sum = 4
2074 11:50:30.222005 best_step = 10
2075 11:50:30.222424
2076 11:50:30.222758 ==
2077 11:50:30.225671 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 11:50:30.228547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 11:50:30.228970 ==
2080 11:50:30.231947 RX Vref Scan: 0
2081 11:50:30.232467
2082 11:50:30.232805 RX Vref 0 -> 0, step: 1
2083 11:50:30.235262
2084 11:50:30.235799 RX Delay -111 -> 252, step: 8
2085 11:50:30.242924 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2086 11:50:30.245856 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2087 11:50:30.248759 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2088 11:50:30.252441 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2089 11:50:30.255771 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2090 11:50:30.262867 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2091 11:50:30.265724 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2092 11:50:30.269181 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2093 11:50:30.272539 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2094 11:50:30.276147 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2095 11:50:30.282878 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2096 11:50:30.285574 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2097 11:50:30.289375 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
2098 11:50:30.292128 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2099 11:50:30.299383 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2100 11:50:30.302248 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2101 11:50:30.302719 ==
2102 11:50:30.305517 Dram Type= 6, Freq= 0, CH_1, rank 1
2103 11:50:30.309374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2104 11:50:30.309985 ==
2105 11:50:30.312187 DQS Delay:
2106 11:50:30.312745 DQS0 = 0, DQS1 = 0
2107 11:50:30.313118 DQM Delay:
2108 11:50:30.315815 DQM0 = 87, DQM1 = 79
2109 11:50:30.316376 DQ Delay:
2110 11:50:30.318955 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2111 11:50:30.322402 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2112 11:50:30.325582 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2113 11:50:30.328974 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2114 11:50:30.329671
2115 11:50:30.330080
2116 11:50:30.338473 [DQSOSCAuto] RK1, (LSB)MR18= 0x1912, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2117 11:50:30.339026 CH1 RK1: MR19=606, MR18=1912
2118 11:50:30.345372 CH1_RK1: MR19=0x606, MR18=0x1912, DQSOSC=403, MR23=63, INC=90, DEC=60
2119 11:50:30.348528 [RxdqsGatingPostProcess] freq 800
2120 11:50:30.355854 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2121 11:50:30.358918 Pre-setting of DQS Precalculation
2122 11:50:30.362151 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2123 11:50:30.369327 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2124 11:50:30.378108 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2125 11:50:30.378657
2126 11:50:30.379027
2127 11:50:30.381984 [Calibration Summary] 1600 Mbps
2128 11:50:30.382452 CH 0, Rank 0
2129 11:50:30.384800 SW Impedance : PASS
2130 11:50:30.385282 DUTY Scan : NO K
2131 11:50:30.388448 ZQ Calibration : PASS
2132 11:50:30.391865 Jitter Meter : NO K
2133 11:50:30.392432 CBT Training : PASS
2134 11:50:30.395260 Write leveling : PASS
2135 11:50:30.398918 RX DQS gating : PASS
2136 11:50:30.399486 RX DQ/DQS(RDDQC) : PASS
2137 11:50:30.401751 TX DQ/DQS : PASS
2138 11:50:30.402220 RX DATLAT : PASS
2139 11:50:30.405007 RX DQ/DQS(Engine): PASS
2140 11:50:30.408950 TX OE : NO K
2141 11:50:30.409569 All Pass.
2142 11:50:30.409953
2143 11:50:30.410298 CH 0, Rank 1
2144 11:50:30.411356 SW Impedance : PASS
2145 11:50:30.415421 DUTY Scan : NO K
2146 11:50:30.415980 ZQ Calibration : PASS
2147 11:50:30.418706 Jitter Meter : NO K
2148 11:50:30.421395 CBT Training : PASS
2149 11:50:30.421910 Write leveling : PASS
2150 11:50:30.425400 RX DQS gating : PASS
2151 11:50:30.428272 RX DQ/DQS(RDDQC) : PASS
2152 11:50:30.428835 TX DQ/DQS : PASS
2153 11:50:30.431738 RX DATLAT : PASS
2154 11:50:30.435739 RX DQ/DQS(Engine): PASS
2155 11:50:30.436306 TX OE : NO K
2156 11:50:30.437821 All Pass.
2157 11:50:30.438285
2158 11:50:30.438653 CH 1, Rank 0
2159 11:50:30.442066 SW Impedance : PASS
2160 11:50:30.442636 DUTY Scan : NO K
2161 11:50:30.444538 ZQ Calibration : PASS
2162 11:50:30.447962 Jitter Meter : NO K
2163 11:50:30.448430 CBT Training : PASS
2164 11:50:30.451280 Write leveling : PASS
2165 11:50:30.455436 RX DQS gating : PASS
2166 11:50:30.455995 RX DQ/DQS(RDDQC) : PASS
2167 11:50:30.458050 TX DQ/DQS : PASS
2168 11:50:30.458521 RX DATLAT : PASS
2169 11:50:30.461860 RX DQ/DQS(Engine): PASS
2170 11:50:30.464738 TX OE : NO K
2171 11:50:30.465207 All Pass.
2172 11:50:30.465623
2173 11:50:30.465970 CH 1, Rank 1
2174 11:50:30.467775 SW Impedance : PASS
2175 11:50:30.471605 DUTY Scan : NO K
2176 11:50:30.472072 ZQ Calibration : PASS
2177 11:50:30.474872 Jitter Meter : NO K
2178 11:50:30.477798 CBT Training : PASS
2179 11:50:30.478265 Write leveling : PASS
2180 11:50:30.481037 RX DQS gating : PASS
2181 11:50:30.484352 RX DQ/DQS(RDDQC) : PASS
2182 11:50:30.484818 TX DQ/DQS : PASS
2183 11:50:30.487814 RX DATLAT : PASS
2184 11:50:30.491586 RX DQ/DQS(Engine): PASS
2185 11:50:30.492106 TX OE : NO K
2186 11:50:30.494564 All Pass.
2187 11:50:30.494987
2188 11:50:30.495322 DramC Write-DBI off
2189 11:50:30.497758 PER_BANK_REFRESH: Hybrid Mode
2190 11:50:30.498180 TX_TRACKING: ON
2191 11:50:30.500757 [GetDramInforAfterCalByMRR] Vendor 6.
2192 11:50:30.508101 [GetDramInforAfterCalByMRR] Revision 606.
2193 11:50:30.512220 [GetDramInforAfterCalByMRR] Revision 2 0.
2194 11:50:30.512740 MR0 0x3b3b
2195 11:50:30.513081 MR8 0x5151
2196 11:50:30.514278 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2197 11:50:30.517320
2198 11:50:30.517776 MR0 0x3b3b
2199 11:50:30.518114 MR8 0x5151
2200 11:50:30.520889 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2201 11:50:30.521313
2202 11:50:30.531364 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2203 11:50:30.534434 [FAST_K] Save calibration result to emmc
2204 11:50:30.537601 [FAST_K] Save calibration result to emmc
2205 11:50:30.540959 dram_init: config_dvfs: 1
2206 11:50:30.544001 dramc_set_vcore_voltage set vcore to 662500
2207 11:50:30.547212 Read voltage for 1200, 2
2208 11:50:30.547635 Vio18 = 0
2209 11:50:30.547968 Vcore = 662500
2210 11:50:30.550610 Vdram = 0
2211 11:50:30.551031 Vddq = 0
2212 11:50:30.551365 Vmddr = 0
2213 11:50:30.557707 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2214 11:50:30.560902 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2215 11:50:30.564131 MEM_TYPE=3, freq_sel=15
2216 11:50:30.567220 sv_algorithm_assistance_LP4_1600
2217 11:50:30.571212 ============ PULL DRAM RESETB DOWN ============
2218 11:50:30.574031 ========== PULL DRAM RESETB DOWN end =========
2219 11:50:30.581113 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2220 11:50:30.584545 ===================================
2221 11:50:30.587733 LPDDR4 DRAM CONFIGURATION
2222 11:50:30.591121 ===================================
2223 11:50:30.591644 EX_ROW_EN[0] = 0x0
2224 11:50:30.593754 EX_ROW_EN[1] = 0x0
2225 11:50:30.594274 LP4Y_EN = 0x0
2226 11:50:30.597724 WORK_FSP = 0x0
2227 11:50:30.598148 WL = 0x4
2228 11:50:30.601087 RL = 0x4
2229 11:50:30.601633 BL = 0x2
2230 11:50:30.604139 RPST = 0x0
2231 11:50:30.604665 RD_PRE = 0x0
2232 11:50:30.607364 WR_PRE = 0x1
2233 11:50:30.607879 WR_PST = 0x0
2234 11:50:30.610312 DBI_WR = 0x0
2235 11:50:30.610727 DBI_RD = 0x0
2236 11:50:30.613937 OTF = 0x1
2237 11:50:30.617621 ===================================
2238 11:50:30.620615 ===================================
2239 11:50:30.621078 ANA top config
2240 11:50:30.624430 ===================================
2241 11:50:30.627726 DLL_ASYNC_EN = 0
2242 11:50:30.630966 ALL_SLAVE_EN = 0
2243 11:50:30.633557 NEW_RANK_MODE = 1
2244 11:50:30.634042 DLL_IDLE_MODE = 1
2245 11:50:30.637185 LP45_APHY_COMB_EN = 1
2246 11:50:30.640739 TX_ODT_DIS = 1
2247 11:50:30.644070 NEW_8X_MODE = 1
2248 11:50:30.646816 ===================================
2249 11:50:30.650481 ===================================
2250 11:50:30.653946 data_rate = 2400
2251 11:50:30.654414 CKR = 1
2252 11:50:30.657555 DQ_P2S_RATIO = 8
2253 11:50:30.660937 ===================================
2254 11:50:30.664174 CA_P2S_RATIO = 8
2255 11:50:30.666822 DQ_CA_OPEN = 0
2256 11:50:30.670138 DQ_SEMI_OPEN = 0
2257 11:50:30.673847 CA_SEMI_OPEN = 0
2258 11:50:30.674504 CA_FULL_RATE = 0
2259 11:50:30.676513 DQ_CKDIV4_EN = 0
2260 11:50:30.680481 CA_CKDIV4_EN = 0
2261 11:50:30.683503 CA_PREDIV_EN = 0
2262 11:50:30.687333 PH8_DLY = 17
2263 11:50:30.690566 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2264 11:50:30.691036 DQ_AAMCK_DIV = 4
2265 11:50:30.693899 CA_AAMCK_DIV = 4
2266 11:50:30.697539 CA_ADMCK_DIV = 4
2267 11:50:30.700098 DQ_TRACK_CA_EN = 0
2268 11:50:30.703521 CA_PICK = 1200
2269 11:50:30.706632 CA_MCKIO = 1200
2270 11:50:30.709500 MCKIO_SEMI = 0
2271 11:50:30.713199 PLL_FREQ = 2366
2272 11:50:30.713716 DQ_UI_PI_RATIO = 32
2273 11:50:30.717218 CA_UI_PI_RATIO = 0
2274 11:50:30.720134 ===================================
2275 11:50:30.723085 ===================================
2276 11:50:30.727672 memory_type:LPDDR4
2277 11:50:30.730108 GP_NUM : 10
2278 11:50:30.730573 SRAM_EN : 1
2279 11:50:30.733076 MD32_EN : 0
2280 11:50:30.736857 ===================================
2281 11:50:30.737461 [ANA_INIT] >>>>>>>>>>>>>>
2282 11:50:30.739520 <<<<<< [CONFIGURE PHASE]: ANA_TX
2283 11:50:30.742723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2284 11:50:30.745996 ===================================
2285 11:50:30.750057 data_rate = 2400,PCW = 0X5b00
2286 11:50:30.752850 ===================================
2287 11:50:30.756378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2288 11:50:30.762907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2289 11:50:30.769159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2290 11:50:30.772237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2291 11:50:30.775984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2292 11:50:30.779602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2293 11:50:30.782817 [ANA_INIT] flow start
2294 11:50:30.783375 [ANA_INIT] PLL >>>>>>>>
2295 11:50:30.785504 [ANA_INIT] PLL <<<<<<<<
2296 11:50:30.789668 [ANA_INIT] MIDPI >>>>>>>>
2297 11:50:30.792711 [ANA_INIT] MIDPI <<<<<<<<
2298 11:50:30.793176 [ANA_INIT] DLL >>>>>>>>
2299 11:50:30.795681 [ANA_INIT] DLL <<<<<<<<
2300 11:50:30.796244 [ANA_INIT] flow end
2301 11:50:30.802431 ============ LP4 DIFF to SE enter ============
2302 11:50:30.806374 ============ LP4 DIFF to SE exit ============
2303 11:50:30.809228 [ANA_INIT] <<<<<<<<<<<<<
2304 11:50:30.812423 [Flow] Enable top DCM control >>>>>
2305 11:50:30.816176 [Flow] Enable top DCM control <<<<<
2306 11:50:30.819457 Enable DLL master slave shuffle
2307 11:50:30.822300 ==============================================================
2308 11:50:30.825471 Gating Mode config
2309 11:50:30.829606 ==============================================================
2310 11:50:30.832318 Config description:
2311 11:50:30.842302 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2312 11:50:30.848826 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2313 11:50:30.852963 SELPH_MODE 0: By rank 1: By Phase
2314 11:50:30.859837 ==============================================================
2315 11:50:30.861987 GAT_TRACK_EN = 1
2316 11:50:30.865562 RX_GATING_MODE = 2
2317 11:50:30.868696 RX_GATING_TRACK_MODE = 2
2318 11:50:30.871980 SELPH_MODE = 1
2319 11:50:30.875340 PICG_EARLY_EN = 1
2320 11:50:30.875820 VALID_LAT_VALUE = 1
2321 11:50:30.882132 ==============================================================
2322 11:50:30.885364 Enter into Gating configuration >>>>
2323 11:50:30.888920 Exit from Gating configuration <<<<
2324 11:50:30.891812 Enter into DVFS_PRE_config >>>>>
2325 11:50:30.901740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2326 11:50:30.905478 Exit from DVFS_PRE_config <<<<<
2327 11:50:30.909243 Enter into PICG configuration >>>>
2328 11:50:30.912182 Exit from PICG configuration <<<<
2329 11:50:30.915289 [RX_INPUT] configuration >>>>>
2330 11:50:30.918807 [RX_INPUT] configuration <<<<<
2331 11:50:30.924885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2332 11:50:30.928485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2333 11:50:30.935198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2334 11:50:30.941401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2335 11:50:30.948448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2336 11:50:30.954723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2337 11:50:30.957915 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2338 11:50:30.961475 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2339 11:50:30.964199 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2340 11:50:30.971278 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2341 11:50:30.974469 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2342 11:50:30.977691 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 11:50:30.981358 ===================================
2344 11:50:30.984851 LPDDR4 DRAM CONFIGURATION
2345 11:50:30.987651 ===================================
2346 11:50:30.988072 EX_ROW_EN[0] = 0x0
2347 11:50:30.991168 EX_ROW_EN[1] = 0x0
2348 11:50:30.994777 LP4Y_EN = 0x0
2349 11:50:30.995199 WORK_FSP = 0x0
2350 11:50:30.997875 WL = 0x4
2351 11:50:30.998301 RL = 0x4
2352 11:50:31.001171 BL = 0x2
2353 11:50:31.001638 RPST = 0x0
2354 11:50:31.004651 RD_PRE = 0x0
2355 11:50:31.005073 WR_PRE = 0x1
2356 11:50:31.007876 WR_PST = 0x0
2357 11:50:31.008489 DBI_WR = 0x0
2358 11:50:31.010871 DBI_RD = 0x0
2359 11:50:31.011295 OTF = 0x1
2360 11:50:31.014356 ===================================
2361 11:50:31.017492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2362 11:50:31.024675 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2363 11:50:31.027567 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2364 11:50:31.030974 ===================================
2365 11:50:31.034488 LPDDR4 DRAM CONFIGURATION
2366 11:50:31.037683 ===================================
2367 11:50:31.037981 EX_ROW_EN[0] = 0x10
2368 11:50:31.040952 EX_ROW_EN[1] = 0x0
2369 11:50:31.041249 LP4Y_EN = 0x0
2370 11:50:31.043880 WORK_FSP = 0x0
2371 11:50:31.044178 WL = 0x4
2372 11:50:31.047168 RL = 0x4
2373 11:50:31.050658 BL = 0x2
2374 11:50:31.050957 RPST = 0x0
2375 11:50:31.053943 RD_PRE = 0x0
2376 11:50:31.054340 WR_PRE = 0x1
2377 11:50:31.057732 WR_PST = 0x0
2378 11:50:31.058123 DBI_WR = 0x0
2379 11:50:31.061368 DBI_RD = 0x0
2380 11:50:31.061700 OTF = 0x1
2381 11:50:31.064708 ===================================
2382 11:50:31.070533 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2383 11:50:31.070841 ==
2384 11:50:31.074004 Dram Type= 6, Freq= 0, CH_0, rank 0
2385 11:50:31.077265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 11:50:31.077635 ==
2387 11:50:31.080256 [Duty_Offset_Calibration]
2388 11:50:31.084536 B0:1 B1:-1 CA:0
2389 11:50:31.084928
2390 11:50:31.086860 [DutyScan_Calibration_Flow] k_type=0
2391 11:50:31.096077
2392 11:50:31.096558 ==CLK 0==
2393 11:50:31.098985 Final CLK duty delay cell = 0
2394 11:50:31.102353 [0] MAX Duty = 5125%(X100), DQS PI = 24
2395 11:50:31.105813 [0] MIN Duty = 4906%(X100), DQS PI = 8
2396 11:50:31.106381 [0] AVG Duty = 5015%(X100)
2397 11:50:31.108907
2398 11:50:31.109364 CH0 CLK Duty spec in!! Max-Min= 219%
2399 11:50:31.115252 [DutyScan_Calibration_Flow] ====Done====
2400 11:50:31.115773
2401 11:50:31.119297 [DutyScan_Calibration_Flow] k_type=1
2402 11:50:31.134115
2403 11:50:31.134600 ==DQS 0 ==
2404 11:50:31.137001 Final DQS duty delay cell = -4
2405 11:50:31.140910 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2406 11:50:31.143919 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2407 11:50:31.148048 [-4] AVG Duty = 4968%(X100)
2408 11:50:31.148567
2409 11:50:31.148899 ==DQS 1 ==
2410 11:50:31.150626 Final DQS duty delay cell = 0
2411 11:50:31.154298 [0] MAX Duty = 5124%(X100), DQS PI = 4
2412 11:50:31.157293 [0] MIN Duty = 5000%(X100), DQS PI = 24
2413 11:50:31.160476 [0] AVG Duty = 5062%(X100)
2414 11:50:31.160940
2415 11:50:31.164034 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2416 11:50:31.164592
2417 11:50:31.167294 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2418 11:50:31.170439 [DutyScan_Calibration_Flow] ====Done====
2419 11:50:31.170906
2420 11:50:31.173965 [DutyScan_Calibration_Flow] k_type=3
2421 11:50:31.191627
2422 11:50:31.192204 ==DQM 0 ==
2423 11:50:31.195140 Final DQM duty delay cell = 0
2424 11:50:31.198455 [0] MAX Duty = 5062%(X100), DQS PI = 38
2425 11:50:31.201685 [0] MIN Duty = 4875%(X100), DQS PI = 6
2426 11:50:31.205400 [0] AVG Duty = 4968%(X100)
2427 11:50:31.206015
2428 11:50:31.206389 ==DQM 1 ==
2429 11:50:31.208304 Final DQM duty delay cell = 4
2430 11:50:31.211172 [4] MAX Duty = 5187%(X100), DQS PI = 14
2431 11:50:31.214791 [4] MIN Duty = 5000%(X100), DQS PI = 22
2432 11:50:31.218116 [4] AVG Duty = 5093%(X100)
2433 11:50:31.218685
2434 11:50:31.221075 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2435 11:50:31.221570
2436 11:50:31.224590 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2437 11:50:31.227930 [DutyScan_Calibration_Flow] ====Done====
2438 11:50:31.228493
2439 11:50:31.231276 [DutyScan_Calibration_Flow] k_type=2
2440 11:50:31.247864
2441 11:50:31.248420 ==DQ 0 ==
2442 11:50:31.250879 Final DQ duty delay cell = -4
2443 11:50:31.254079 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2444 11:50:31.257902 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2445 11:50:31.260399 [-4] AVG Duty = 4969%(X100)
2446 11:50:31.260864
2447 11:50:31.261229 ==DQ 1 ==
2448 11:50:31.263996 Final DQ duty delay cell = 0
2449 11:50:31.267883 [0] MAX Duty = 5093%(X100), DQS PI = 0
2450 11:50:31.271520 [0] MIN Duty = 4969%(X100), DQS PI = 42
2451 11:50:31.274050 [0] AVG Duty = 5031%(X100)
2452 11:50:31.274514
2453 11:50:31.277261 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2454 11:50:31.277798
2455 11:50:31.280608 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2456 11:50:31.283863 [DutyScan_Calibration_Flow] ====Done====
2457 11:50:31.284327 ==
2458 11:50:31.286906 Dram Type= 6, Freq= 0, CH_1, rank 0
2459 11:50:31.290797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 11:50:31.291252 ==
2461 11:50:31.294098 [Duty_Offset_Calibration]
2462 11:50:31.294514 B0:-1 B1:1 CA:2
2463 11:50:31.294842
2464 11:50:31.297657 [DutyScan_Calibration_Flow] k_type=0
2465 11:50:31.307490
2466 11:50:31.308008 ==CLK 0==
2467 11:50:31.310657 Final CLK duty delay cell = 0
2468 11:50:31.314364 [0] MAX Duty = 5156%(X100), DQS PI = 22
2469 11:50:31.317599 [0] MIN Duty = 4969%(X100), DQS PI = 62
2470 11:50:31.318021 [0] AVG Duty = 5062%(X100)
2471 11:50:31.321163
2472 11:50:31.324373 CH1 CLK Duty spec in!! Max-Min= 187%
2473 11:50:31.327448 [DutyScan_Calibration_Flow] ====Done====
2474 11:50:31.327974
2475 11:50:31.330770 [DutyScan_Calibration_Flow] k_type=1
2476 11:50:31.346998
2477 11:50:31.347573 ==DQS 0 ==
2478 11:50:31.350138 Final DQS duty delay cell = 0
2479 11:50:31.353647 [0] MAX Duty = 5156%(X100), DQS PI = 48
2480 11:50:31.357564 [0] MIN Duty = 4875%(X100), DQS PI = 8
2481 11:50:31.358123 [0] AVG Duty = 5015%(X100)
2482 11:50:31.360710
2483 11:50:31.361275 ==DQS 1 ==
2484 11:50:31.363465 Final DQS duty delay cell = 0
2485 11:50:31.368027 [0] MAX Duty = 5094%(X100), DQS PI = 12
2486 11:50:31.370756 [0] MIN Duty = 4969%(X100), DQS PI = 56
2487 11:50:31.373607 [0] AVG Duty = 5031%(X100)
2488 11:50:31.374071
2489 11:50:31.376852 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2490 11:50:31.377460
2491 11:50:31.379888 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2492 11:50:31.383481 [DutyScan_Calibration_Flow] ====Done====
2493 11:50:31.384164
2494 11:50:31.386530 [DutyScan_Calibration_Flow] k_type=3
2495 11:50:31.402680
2496 11:50:31.403239 ==DQM 0 ==
2497 11:50:31.405946 Final DQM duty delay cell = -4
2498 11:50:31.409658 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2499 11:50:31.412940 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2500 11:50:31.415979 [-4] AVG Duty = 4937%(X100)
2501 11:50:31.416626
2502 11:50:31.417110 ==DQM 1 ==
2503 11:50:31.419535 Final DQM duty delay cell = 0
2504 11:50:31.423160 [0] MAX Duty = 5187%(X100), DQS PI = 6
2505 11:50:31.426119 [0] MIN Duty = 4969%(X100), DQS PI = 36
2506 11:50:31.429372 [0] AVG Duty = 5078%(X100)
2507 11:50:31.429990
2508 11:50:31.433154 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2509 11:50:31.433838
2510 11:50:31.435875 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2511 11:50:31.439705 [DutyScan_Calibration_Flow] ====Done====
2512 11:50:31.440327
2513 11:50:31.442161 [DutyScan_Calibration_Flow] k_type=2
2514 11:50:31.459599
2515 11:50:31.460443 ==DQ 0 ==
2516 11:50:31.462459 Final DQ duty delay cell = 0
2517 11:50:31.466019 [0] MAX Duty = 5187%(X100), DQS PI = 30
2518 11:50:31.469213 [0] MIN Duty = 4907%(X100), DQS PI = 6
2519 11:50:31.469833 [0] AVG Duty = 5047%(X100)
2520 11:50:31.470207
2521 11:50:31.472755 ==DQ 1 ==
2522 11:50:31.475917 Final DQ duty delay cell = 0
2523 11:50:31.479718 [0] MAX Duty = 5124%(X100), DQS PI = 10
2524 11:50:31.482509 [0] MIN Duty = 4969%(X100), DQS PI = 0
2525 11:50:31.482974 [0] AVG Duty = 5046%(X100)
2526 11:50:31.483342
2527 11:50:31.486000 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2528 11:50:31.486501
2529 11:50:31.489108 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2530 11:50:31.496052 [DutyScan_Calibration_Flow] ====Done====
2531 11:50:31.499041 nWR fixed to 30
2532 11:50:31.499461 [ModeRegInit_LP4] CH0 RK0
2533 11:50:31.502758 [ModeRegInit_LP4] CH0 RK1
2534 11:50:31.505653 [ModeRegInit_LP4] CH1 RK0
2535 11:50:31.506167 [ModeRegInit_LP4] CH1 RK1
2536 11:50:31.508932 match AC timing 7
2537 11:50:31.512542 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2538 11:50:31.515450 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2539 11:50:31.522297 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2540 11:50:31.525773 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2541 11:50:31.532806 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2542 11:50:31.533372 ==
2543 11:50:31.535685 Dram Type= 6, Freq= 0, CH_0, rank 0
2544 11:50:31.539489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 11:50:31.540061 ==
2546 11:50:31.545668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 11:50:31.551820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 11:50:31.559041 [CA 0] Center 39 (9~70) winsize 62
2549 11:50:31.562193 [CA 1] Center 39 (9~69) winsize 61
2550 11:50:31.565650 [CA 2] Center 35 (5~66) winsize 62
2551 11:50:31.569456 [CA 3] Center 35 (5~66) winsize 62
2552 11:50:31.572496 [CA 4] Center 33 (4~63) winsize 60
2553 11:50:31.575541 [CA 5] Center 33 (3~63) winsize 61
2554 11:50:31.576015
2555 11:50:31.579967 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2556 11:50:31.580438
2557 11:50:31.583022 [CATrainingPosCal] consider 1 rank data
2558 11:50:31.585713 u2DelayCellTimex100 = 270/100 ps
2559 11:50:31.588798 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2560 11:50:31.592799 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2561 11:50:31.599299 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 11:50:31.602781 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 11:50:31.606102 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2564 11:50:31.609733 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2565 11:50:31.610319
2566 11:50:31.612071 CA PerBit enable=1, Macro0, CA PI delay=33
2567 11:50:31.612543
2568 11:50:31.616016 [CBTSetCACLKResult] CA Dly = 33
2569 11:50:31.616580 CS Dly: 8 (0~39)
2570 11:50:31.619257 ==
2571 11:50:31.619821 Dram Type= 6, Freq= 0, CH_0, rank 1
2572 11:50:31.625571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 11:50:31.626136 ==
2574 11:50:31.629322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2575 11:50:31.635153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2576 11:50:31.645204 [CA 0] Center 39 (9~70) winsize 62
2577 11:50:31.648399 [CA 1] Center 39 (9~70) winsize 62
2578 11:50:31.652256 [CA 2] Center 35 (5~66) winsize 62
2579 11:50:31.654453 [CA 3] Center 35 (5~65) winsize 61
2580 11:50:31.657907 [CA 4] Center 33 (3~64) winsize 62
2581 11:50:31.661592 [CA 5] Center 33 (3~63) winsize 61
2582 11:50:31.662152
2583 11:50:31.664501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2584 11:50:31.664970
2585 11:50:31.667931 [CATrainingPosCal] consider 2 rank data
2586 11:50:31.671353 u2DelayCellTimex100 = 270/100 ps
2587 11:50:31.674689 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2588 11:50:31.681269 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2589 11:50:31.684526 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2590 11:50:31.687680 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2591 11:50:31.691063 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2592 11:50:31.694715 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2593 11:50:31.695189
2594 11:50:31.697744 CA PerBit enable=1, Macro0, CA PI delay=33
2595 11:50:31.698217
2596 11:50:31.701214 [CBTSetCACLKResult] CA Dly = 33
2597 11:50:31.701780 CS Dly: 9 (0~41)
2598 11:50:31.705015
2599 11:50:31.707715 ----->DramcWriteLeveling(PI) begin...
2600 11:50:31.708241 ==
2601 11:50:31.711115 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 11:50:31.714053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 11:50:31.714486 ==
2604 11:50:31.717929 Write leveling (Byte 0): 33 => 33
2605 11:50:31.721341 Write leveling (Byte 1): 28 => 28
2606 11:50:31.725330 DramcWriteLeveling(PI) end<-----
2607 11:50:31.725928
2608 11:50:31.726276 ==
2609 11:50:31.727533 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 11:50:31.731264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 11:50:31.731696 ==
2612 11:50:31.733884 [Gating] SW mode calibration
2613 11:50:31.740906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2614 11:50:31.748349 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2615 11:50:31.751055 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2616 11:50:31.754081 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
2617 11:50:31.760977 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 11:50:31.764303 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 11:50:31.767460 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2620 11:50:31.774057 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2621 11:50:31.777246 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2622 11:50:31.781103 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
2623 11:50:31.787643 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 1) (1 0)
2624 11:50:31.790662 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2625 11:50:31.794212 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 11:50:31.800782 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 11:50:31.804057 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 11:50:31.807350 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 11:50:31.810600 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2630 11:50:31.817202 1 0 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
2631 11:50:31.820730 1 1 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2632 11:50:31.824676 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2633 11:50:31.830758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 11:50:31.834186 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 11:50:31.837303 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 11:50:31.843476 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 11:50:31.847218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 11:50:31.850159 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2639 11:50:31.856752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2640 11:50:31.860338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2641 11:50:31.863253 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:50:31.870464 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 11:50:31.873846 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 11:50:31.876643 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 11:50:31.883423 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 11:50:31.886156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 11:50:31.889938 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 11:50:31.896515 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 11:50:31.899995 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 11:50:31.903448 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 11:50:31.909802 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 11:50:31.912927 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 11:50:31.916234 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2654 11:50:31.922797 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2655 11:50:31.926044 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2656 11:50:31.929879 Total UI for P1: 0, mck2ui 16
2657 11:50:31.932631 best dqsien dly found for B0: ( 1, 3, 26)
2658 11:50:31.936112 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2659 11:50:31.939450 Total UI for P1: 0, mck2ui 16
2660 11:50:31.943064 best dqsien dly found for B1: ( 1, 4, 0)
2661 11:50:31.946398 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2662 11:50:31.949764 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2663 11:50:31.950333
2664 11:50:31.956374 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2665 11:50:31.959038 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2666 11:50:31.962459 [Gating] SW calibration Done
2667 11:50:31.963016 ==
2668 11:50:31.965928 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 11:50:31.969755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 11:50:31.970323 ==
2671 11:50:31.970701 RX Vref Scan: 0
2672 11:50:31.971051
2673 11:50:31.973356 RX Vref 0 -> 0, step: 1
2674 11:50:31.974002
2675 11:50:31.975776 RX Delay -40 -> 252, step: 8
2676 11:50:31.979323 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2677 11:50:31.982846 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2678 11:50:31.988900 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2679 11:50:31.992458 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2680 11:50:31.995825 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2681 11:50:31.998835 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2682 11:50:32.002196 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2683 11:50:32.008837 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2684 11:50:32.012705 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2685 11:50:32.015323 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2686 11:50:32.019116 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2687 11:50:32.022293 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2688 11:50:32.028852 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2689 11:50:32.032140 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2690 11:50:32.035881 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2691 11:50:32.038961 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2692 11:50:32.039515 ==
2693 11:50:32.042396 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 11:50:32.045304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 11:50:32.049104 ==
2696 11:50:32.049567 DQS Delay:
2697 11:50:32.049912 DQS0 = 0, DQS1 = 0
2698 11:50:32.052174 DQM Delay:
2699 11:50:32.052613 DQM0 = 119, DQM1 = 107
2700 11:50:32.055299 DQ Delay:
2701 11:50:32.059282 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2702 11:50:32.062085 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2703 11:50:32.065304 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2704 11:50:32.069478 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2705 11:50:32.070018
2706 11:50:32.070386
2707 11:50:32.070709 ==
2708 11:50:32.071883 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 11:50:32.075457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 11:50:32.075891 ==
2711 11:50:32.076232
2712 11:50:32.078645
2713 11:50:32.079069 TX Vref Scan disable
2714 11:50:32.081918 == TX Byte 0 ==
2715 11:50:32.085279 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2716 11:50:32.088687 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2717 11:50:32.092313 == TX Byte 1 ==
2718 11:50:32.095535 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2719 11:50:32.098763 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2720 11:50:32.099190 ==
2721 11:50:32.101980 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 11:50:32.108607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 11:50:32.109173 ==
2724 11:50:32.119587 TX Vref=22, minBit 5, minWin=25, winSum=418
2725 11:50:32.122818 TX Vref=24, minBit 14, minWin=25, winSum=425
2726 11:50:32.125988 TX Vref=26, minBit 5, minWin=26, winSum=432
2727 11:50:32.128987 TX Vref=28, minBit 0, minWin=27, winSum=434
2728 11:50:32.133229 TX Vref=30, minBit 14, minWin=26, winSum=435
2729 11:50:32.139799 TX Vref=32, minBit 4, minWin=26, winSum=433
2730 11:50:32.142845 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 28
2731 11:50:32.143277
2732 11:50:32.145897 Final TX Range 1 Vref 28
2733 11:50:32.146324
2734 11:50:32.146664 ==
2735 11:50:32.149482 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 11:50:32.152778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 11:50:32.155666 ==
2738 11:50:32.156084
2739 11:50:32.156414
2740 11:50:32.156721 TX Vref Scan disable
2741 11:50:32.159724 == TX Byte 0 ==
2742 11:50:32.162806 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2743 11:50:32.169511 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2744 11:50:32.170036 == TX Byte 1 ==
2745 11:50:32.172495 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2746 11:50:32.178914 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2747 11:50:32.179355
2748 11:50:32.179688 [DATLAT]
2749 11:50:32.180000 Freq=1200, CH0 RK0
2750 11:50:32.180300
2751 11:50:32.181964 DATLAT Default: 0xd
2752 11:50:32.185729 0, 0xFFFF, sum = 0
2753 11:50:32.186295 1, 0xFFFF, sum = 0
2754 11:50:32.189350 2, 0xFFFF, sum = 0
2755 11:50:32.189882 3, 0xFFFF, sum = 0
2756 11:50:32.192230 4, 0xFFFF, sum = 0
2757 11:50:32.192799 5, 0xFFFF, sum = 0
2758 11:50:32.195647 6, 0xFFFF, sum = 0
2759 11:50:32.196126 7, 0xFFFF, sum = 0
2760 11:50:32.199385 8, 0xFFFF, sum = 0
2761 11:50:32.199958 9, 0xFFFF, sum = 0
2762 11:50:32.202200 10, 0xFFFF, sum = 0
2763 11:50:32.202681 11, 0xFFFF, sum = 0
2764 11:50:32.205659 12, 0x0, sum = 1
2765 11:50:32.206149 13, 0x0, sum = 2
2766 11:50:32.209204 14, 0x0, sum = 3
2767 11:50:32.209713 15, 0x0, sum = 4
2768 11:50:32.212566 best_step = 13
2769 11:50:32.213079
2770 11:50:32.213453 ==
2771 11:50:32.215729 Dram Type= 6, Freq= 0, CH_0, rank 0
2772 11:50:32.219007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2773 11:50:32.219472 ==
2774 11:50:32.219837 RX Vref Scan: 1
2775 11:50:32.222924
2776 11:50:32.223443 Set Vref Range= 32 -> 127
2777 11:50:32.223780
2778 11:50:32.226403 RX Vref 32 -> 127, step: 1
2779 11:50:32.226922
2780 11:50:32.228869 RX Delay -21 -> 252, step: 4
2781 11:50:32.229385
2782 11:50:32.232132 Set Vref, RX VrefLevel [Byte0]: 32
2783 11:50:32.235710 [Byte1]: 32
2784 11:50:32.236230
2785 11:50:32.238443 Set Vref, RX VrefLevel [Byte0]: 33
2786 11:50:32.242224 [Byte1]: 33
2787 11:50:32.246223
2788 11:50:32.246743 Set Vref, RX VrefLevel [Byte0]: 34
2789 11:50:32.249384 [Byte1]: 34
2790 11:50:32.253794
2791 11:50:32.254254 Set Vref, RX VrefLevel [Byte0]: 35
2792 11:50:32.257196 [Byte1]: 35
2793 11:50:32.261893
2794 11:50:32.262458 Set Vref, RX VrefLevel [Byte0]: 36
2795 11:50:32.265101 [Byte1]: 36
2796 11:50:32.270194
2797 11:50:32.270752 Set Vref, RX VrefLevel [Byte0]: 37
2798 11:50:32.273536 [Byte1]: 37
2799 11:50:32.277907
2800 11:50:32.278368 Set Vref, RX VrefLevel [Byte0]: 38
2801 11:50:32.280867 [Byte1]: 38
2802 11:50:32.285659
2803 11:50:32.286212 Set Vref, RX VrefLevel [Byte0]: 39
2804 11:50:32.288525 [Byte1]: 39
2805 11:50:32.293545
2806 11:50:32.294132 Set Vref, RX VrefLevel [Byte0]: 40
2807 11:50:32.296716 [Byte1]: 40
2808 11:50:32.301383
2809 11:50:32.302236 Set Vref, RX VrefLevel [Byte0]: 41
2810 11:50:32.304843 [Byte1]: 41
2811 11:50:32.309378
2812 11:50:32.310056 Set Vref, RX VrefLevel [Byte0]: 42
2813 11:50:32.312376 [Byte1]: 42
2814 11:50:32.317106
2815 11:50:32.317767 Set Vref, RX VrefLevel [Byte0]: 43
2816 11:50:32.320742 [Byte1]: 43
2817 11:50:32.325087
2818 11:50:32.327992 Set Vref, RX VrefLevel [Byte0]: 44
2819 11:50:32.331657 [Byte1]: 44
2820 11:50:32.332224
2821 11:50:32.334895 Set Vref, RX VrefLevel [Byte0]: 45
2822 11:50:32.337867 [Byte1]: 45
2823 11:50:32.338330
2824 11:50:32.341772 Set Vref, RX VrefLevel [Byte0]: 46
2825 11:50:32.344965 [Byte1]: 46
2826 11:50:32.348701
2827 11:50:32.349165 Set Vref, RX VrefLevel [Byte0]: 47
2828 11:50:32.352280 [Byte1]: 47
2829 11:50:32.357051
2830 11:50:32.357669 Set Vref, RX VrefLevel [Byte0]: 48
2831 11:50:32.360325 [Byte1]: 48
2832 11:50:32.365092
2833 11:50:32.365795 Set Vref, RX VrefLevel [Byte0]: 49
2834 11:50:32.368100 [Byte1]: 49
2835 11:50:32.372453
2836 11:50:32.373013 Set Vref, RX VrefLevel [Byte0]: 50
2837 11:50:32.376077 [Byte1]: 50
2838 11:50:32.380778
2839 11:50:32.381344 Set Vref, RX VrefLevel [Byte0]: 51
2840 11:50:32.384143 [Byte1]: 51
2841 11:50:32.388766
2842 11:50:32.389332 Set Vref, RX VrefLevel [Byte0]: 52
2843 11:50:32.392652 [Byte1]: 52
2844 11:50:32.396946
2845 11:50:32.397564 Set Vref, RX VrefLevel [Byte0]: 53
2846 11:50:32.399805 [Byte1]: 53
2847 11:50:32.404364
2848 11:50:32.404933 Set Vref, RX VrefLevel [Byte0]: 54
2849 11:50:32.407854 [Byte1]: 54
2850 11:50:32.412712
2851 11:50:32.413278 Set Vref, RX VrefLevel [Byte0]: 55
2852 11:50:32.415292 [Byte1]: 55
2853 11:50:32.420338
2854 11:50:32.420799 Set Vref, RX VrefLevel [Byte0]: 56
2855 11:50:32.423658 [Byte1]: 56
2856 11:50:32.428322
2857 11:50:32.428887 Set Vref, RX VrefLevel [Byte0]: 57
2858 11:50:32.431718 [Byte1]: 57
2859 11:50:32.436026
2860 11:50:32.436490 Set Vref, RX VrefLevel [Byte0]: 58
2861 11:50:32.439482 [Byte1]: 58
2862 11:50:32.444027
2863 11:50:32.444586 Set Vref, RX VrefLevel [Byte0]: 59
2864 11:50:32.447120 [Byte1]: 59
2865 11:50:32.452315
2866 11:50:32.452898 Set Vref, RX VrefLevel [Byte0]: 60
2867 11:50:32.456312 [Byte1]: 60
2868 11:50:32.459957
2869 11:50:32.460523 Set Vref, RX VrefLevel [Byte0]: 61
2870 11:50:32.463743 [Byte1]: 61
2871 11:50:32.467797
2872 11:50:32.468362 Set Vref, RX VrefLevel [Byte0]: 62
2873 11:50:32.471653 [Byte1]: 62
2874 11:50:32.476059
2875 11:50:32.476542 Set Vref, RX VrefLevel [Byte0]: 63
2876 11:50:32.479015 [Byte1]: 63
2877 11:50:32.483535
2878 11:50:32.484231 Set Vref, RX VrefLevel [Byte0]: 64
2879 11:50:32.487421 [Byte1]: 64
2880 11:50:32.491502
2881 11:50:32.491984 Set Vref, RX VrefLevel [Byte0]: 65
2882 11:50:32.494954 [Byte1]: 65
2883 11:50:32.500201
2884 11:50:32.500791 Set Vref, RX VrefLevel [Byte0]: 66
2885 11:50:32.503567 [Byte1]: 66
2886 11:50:32.508162
2887 11:50:32.508748 Set Vref, RX VrefLevel [Byte0]: 67
2888 11:50:32.511207 [Byte1]: 67
2889 11:50:32.515239
2890 11:50:32.515845 Set Vref, RX VrefLevel [Byte0]: 68
2891 11:50:32.518976 [Byte1]: 68
2892 11:50:32.523025
2893 11:50:32.526222 Set Vref, RX VrefLevel [Byte0]: 69
2894 11:50:32.530022 [Byte1]: 69
2895 11:50:32.530605
2896 11:50:32.532866 Set Vref, RX VrefLevel [Byte0]: 70
2897 11:50:32.536785 [Byte1]: 70
2898 11:50:32.537269
2899 11:50:32.540286 Set Vref, RX VrefLevel [Byte0]: 71
2900 11:50:32.542928 [Byte1]: 71
2901 11:50:32.547390
2902 11:50:32.547974 Set Vref, RX VrefLevel [Byte0]: 72
2903 11:50:32.550326 [Byte1]: 72
2904 11:50:32.554829
2905 11:50:32.555308 Set Vref, RX VrefLevel [Byte0]: 73
2906 11:50:32.557930 [Byte1]: 73
2907 11:50:32.563285
2908 11:50:32.563881 Set Vref, RX VrefLevel [Byte0]: 74
2909 11:50:32.566362 [Byte1]: 74
2910 11:50:32.570881
2911 11:50:32.571439 Final RX Vref Byte 0 = 62 to rank0
2912 11:50:32.574175 Final RX Vref Byte 1 = 50 to rank0
2913 11:50:32.578053 Final RX Vref Byte 0 = 62 to rank1
2914 11:50:32.580848 Final RX Vref Byte 1 = 50 to rank1==
2915 11:50:32.584539 Dram Type= 6, Freq= 0, CH_0, rank 0
2916 11:50:32.590927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 11:50:32.591481 ==
2918 11:50:32.591860 DQS Delay:
2919 11:50:32.592210 DQS0 = 0, DQS1 = 0
2920 11:50:32.594006 DQM Delay:
2921 11:50:32.594476 DQM0 = 119, DQM1 = 107
2922 11:50:32.597130 DQ Delay:
2923 11:50:32.600798 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =116
2924 11:50:32.604063 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2925 11:50:32.607342 DQ8 =98, DQ9 =92, DQ10 =110, DQ11 =100
2926 11:50:32.610781 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2927 11:50:32.611356
2928 11:50:32.611732
2929 11:50:32.620498 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2930 11:50:32.621061 CH0 RK0: MR19=403, MR18=DF9
2931 11:50:32.627025 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2932 11:50:32.627592
2933 11:50:32.630341 ----->DramcWriteLeveling(PI) begin...
2934 11:50:32.630924 ==
2935 11:50:32.633610 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 11:50:32.636775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 11:50:32.640215 ==
2938 11:50:32.640699 Write leveling (Byte 0): 34 => 34
2939 11:50:32.643795 Write leveling (Byte 1): 29 => 29
2940 11:50:32.646864 DramcWriteLeveling(PI) end<-----
2941 11:50:32.647431
2942 11:50:32.647807 ==
2943 11:50:32.650112 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 11:50:32.657057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 11:50:32.657652 ==
2946 11:50:32.660167 [Gating] SW mode calibration
2947 11:50:32.666619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2948 11:50:32.670437 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2949 11:50:32.676658 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2950 11:50:32.680035 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2951 11:50:32.683653 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 11:50:32.690098 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 11:50:32.694155 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 11:50:32.696898 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 11:50:32.700474 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2956 11:50:32.706591 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2957 11:50:32.710319 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2958 11:50:32.713375 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 11:50:32.720165 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 11:50:32.723447 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 11:50:32.727321 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 11:50:32.733608 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 11:50:32.736939 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 11:50:32.740130 1 0 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
2965 11:50:32.747084 1 1 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2966 11:50:32.750106 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:50:32.753676 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 11:50:32.760125 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 11:50:32.763737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:50:32.766501 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:50:32.773573 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:50:32.777201 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2973 11:50:32.779923 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2974 11:50:32.786323 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2975 11:50:32.789800 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:50:32.792906 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:50:32.799927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:50:32.803426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:50:32.806614 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:50:32.813187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:50:32.816352 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:50:32.820275 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:50:32.826313 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:50:32.830106 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:50:32.833590 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:50:32.840098 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:50:32.843142 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:50:32.846071 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 11:50:32.849662 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2990 11:50:32.852625 Total UI for P1: 0, mck2ui 16
2991 11:50:32.855792 best dqsien dly found for B0: ( 1, 3, 28)
2992 11:50:32.862974 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 11:50:32.866047 Total UI for P1: 0, mck2ui 16
2994 11:50:32.869590 best dqsien dly found for B1: ( 1, 4, 0)
2995 11:50:32.873342 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2996 11:50:32.876359 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2997 11:50:32.876938
2998 11:50:32.879371 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2999 11:50:32.882259 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3000 11:50:32.885689 [Gating] SW calibration Done
3001 11:50:32.886182 ==
3002 11:50:32.890054 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 11:50:32.892404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 11:50:32.892977 ==
3005 11:50:32.895609 RX Vref Scan: 0
3006 11:50:32.896080
3007 11:50:32.900098 RX Vref 0 -> 0, step: 1
3008 11:50:32.900672
3009 11:50:32.901049 RX Delay -40 -> 252, step: 8
3010 11:50:32.905838 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3011 11:50:32.909268 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3012 11:50:32.912376 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3013 11:50:32.916303 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3014 11:50:32.919868 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3015 11:50:32.926295 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3016 11:50:32.929035 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3017 11:50:32.932860 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3018 11:50:32.936010 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3019 11:50:32.938838 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3020 11:50:32.942229 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3021 11:50:32.949538 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3022 11:50:32.952572 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3023 11:50:32.955919 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3024 11:50:32.959007 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3025 11:50:32.965886 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3026 11:50:32.966458 ==
3027 11:50:32.968987 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 11:50:32.972589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 11:50:32.973255 ==
3030 11:50:32.973706 DQS Delay:
3031 11:50:32.975553 DQS0 = 0, DQS1 = 0
3032 11:50:32.976126 DQM Delay:
3033 11:50:32.979714 DQM0 = 117, DQM1 = 108
3034 11:50:32.980310 DQ Delay:
3035 11:50:32.981944 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3036 11:50:32.985545 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3037 11:50:32.989019 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3038 11:50:32.992480 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3039 11:50:32.993055
3040 11:50:32.993472
3041 11:50:32.995605 ==
3042 11:50:32.998501 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 11:50:33.001883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 11:50:33.002508 ==
3045 11:50:33.003150
3046 11:50:33.003528
3047 11:50:33.004949 TX Vref Scan disable
3048 11:50:33.005457 == TX Byte 0 ==
3049 11:50:33.012486 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3050 11:50:33.015390 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3051 11:50:33.015963 == TX Byte 1 ==
3052 11:50:33.021699 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3053 11:50:33.025030 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3054 11:50:33.025642 ==
3055 11:50:33.028333 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 11:50:33.031838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 11:50:33.032419 ==
3058 11:50:33.044678 TX Vref=22, minBit 13, minWin=25, winSum=421
3059 11:50:33.048054 TX Vref=24, minBit 0, minWin=26, winSum=428
3060 11:50:33.051395 TX Vref=26, minBit 1, minWin=26, winSum=431
3061 11:50:33.054281 TX Vref=28, minBit 13, minWin=26, winSum=434
3062 11:50:33.057720 TX Vref=30, minBit 1, minWin=26, winSum=433
3063 11:50:33.064814 TX Vref=32, minBit 1, minWin=26, winSum=431
3064 11:50:33.068208 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 28
3065 11:50:33.068792
3066 11:50:33.071030 Final TX Range 1 Vref 28
3067 11:50:33.071607
3068 11:50:33.071985 ==
3069 11:50:33.074520 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 11:50:33.078402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 11:50:33.078982 ==
3072 11:50:33.080897
3073 11:50:33.081361
3074 11:50:33.081768 TX Vref Scan disable
3075 11:50:33.084455 == TX Byte 0 ==
3076 11:50:33.087549 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3077 11:50:33.094501 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3078 11:50:33.095080 == TX Byte 1 ==
3079 11:50:33.098136 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3080 11:50:33.104432 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3081 11:50:33.105003
3082 11:50:33.105383 [DATLAT]
3083 11:50:33.105793 Freq=1200, CH0 RK1
3084 11:50:33.106137
3085 11:50:33.107253 DATLAT Default: 0xd
3086 11:50:33.107722 0, 0xFFFF, sum = 0
3087 11:50:33.111099 1, 0xFFFF, sum = 0
3088 11:50:33.111577 2, 0xFFFF, sum = 0
3089 11:50:33.114196 3, 0xFFFF, sum = 0
3090 11:50:33.117197 4, 0xFFFF, sum = 0
3091 11:50:33.117775 5, 0xFFFF, sum = 0
3092 11:50:33.120671 6, 0xFFFF, sum = 0
3093 11:50:33.121146 7, 0xFFFF, sum = 0
3094 11:50:33.124243 8, 0xFFFF, sum = 0
3095 11:50:33.124821 9, 0xFFFF, sum = 0
3096 11:50:33.127606 10, 0xFFFF, sum = 0
3097 11:50:33.128186 11, 0xFFFF, sum = 0
3098 11:50:33.131014 12, 0x0, sum = 1
3099 11:50:33.131600 13, 0x0, sum = 2
3100 11:50:33.133969 14, 0x0, sum = 3
3101 11:50:33.134446 15, 0x0, sum = 4
3102 11:50:33.134826 best_step = 13
3103 11:50:33.137556
3104 11:50:33.138130 ==
3105 11:50:33.140863 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 11:50:33.143964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 11:50:33.144444 ==
3108 11:50:33.144820 RX Vref Scan: 0
3109 11:50:33.145169
3110 11:50:33.148033 RX Vref 0 -> 0, step: 1
3111 11:50:33.148501
3112 11:50:33.150979 RX Delay -21 -> 252, step: 4
3113 11:50:33.157006 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3114 11:50:33.161296 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3115 11:50:33.163821 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3116 11:50:33.166837 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3117 11:50:33.170161 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3118 11:50:33.173520 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3119 11:50:33.180100 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3120 11:50:33.183689 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3121 11:50:33.187227 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3122 11:50:33.190724 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3123 11:50:33.193560 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3124 11:50:33.200371 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3125 11:50:33.203834 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3126 11:50:33.206829 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3127 11:50:33.210161 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3128 11:50:33.216390 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3129 11:50:33.216816 ==
3130 11:50:33.219709 Dram Type= 6, Freq= 0, CH_0, rank 1
3131 11:50:33.223676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 11:50:33.224214 ==
3133 11:50:33.224561 DQS Delay:
3134 11:50:33.226546 DQS0 = 0, DQS1 = 0
3135 11:50:33.227078 DQM Delay:
3136 11:50:33.229727 DQM0 = 116, DQM1 = 108
3137 11:50:33.230155 DQ Delay:
3138 11:50:33.233200 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3139 11:50:33.236340 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3140 11:50:33.239593 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3141 11:50:33.242990 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3142 11:50:33.243433
3143 11:50:33.243773
3144 11:50:33.253216 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3145 11:50:33.256733 CH0 RK1: MR19=403, MR18=9E4
3146 11:50:33.259619 CH0_RK1: MR19=0x403, MR18=0x9E4, DQSOSC=406, MR23=63, INC=39, DEC=26
3147 11:50:33.262730 [RxdqsGatingPostProcess] freq 1200
3148 11:50:33.269591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3149 11:50:33.273112 best DQS0 dly(2T, 0.5T) = (0, 11)
3150 11:50:33.276420 best DQS1 dly(2T, 0.5T) = (0, 12)
3151 11:50:33.279538 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3152 11:50:33.283140 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3153 11:50:33.285927 best DQS0 dly(2T, 0.5T) = (0, 11)
3154 11:50:33.289467 best DQS1 dly(2T, 0.5T) = (0, 12)
3155 11:50:33.292418 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3156 11:50:33.296201 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3157 11:50:33.299666 Pre-setting of DQS Precalculation
3158 11:50:33.303356 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3159 11:50:33.303935 ==
3160 11:50:33.306407 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 11:50:33.309144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 11:50:33.309762 ==
3163 11:50:33.315869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 11:50:33.322056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3165 11:50:33.330413 [CA 0] Center 37 (7~68) winsize 62
3166 11:50:33.333826 [CA 1] Center 38 (8~68) winsize 61
3167 11:50:33.337596 [CA 2] Center 34 (4~64) winsize 61
3168 11:50:33.340462 [CA 3] Center 33 (3~64) winsize 62
3169 11:50:33.344571 [CA 4] Center 34 (4~64) winsize 61
3170 11:50:33.346837 [CA 5] Center 33 (3~64) winsize 62
3171 11:50:33.347310
3172 11:50:33.351592 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3173 11:50:33.352174
3174 11:50:33.353543 [CATrainingPosCal] consider 1 rank data
3175 11:50:33.357152 u2DelayCellTimex100 = 270/100 ps
3176 11:50:33.360470 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3177 11:50:33.363709 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3178 11:50:33.370236 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 11:50:33.373727 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 11:50:33.377264 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 11:50:33.380382 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 11:50:33.380852
3183 11:50:33.383887 CA PerBit enable=1, Macro0, CA PI delay=33
3184 11:50:33.384470
3185 11:50:33.387067 [CBTSetCACLKResult] CA Dly = 33
3186 11:50:33.387641 CS Dly: 6 (0~37)
3187 11:50:33.390320 ==
3188 11:50:33.390956 Dram Type= 6, Freq= 0, CH_1, rank 1
3189 11:50:33.397061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 11:50:33.397682 ==
3191 11:50:33.400012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3192 11:50:33.407067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3193 11:50:33.416700 [CA 0] Center 37 (7~68) winsize 62
3194 11:50:33.419611 [CA 1] Center 37 (7~68) winsize 62
3195 11:50:33.423167 [CA 2] Center 34 (4~65) winsize 62
3196 11:50:33.426163 [CA 3] Center 33 (3~64) winsize 62
3197 11:50:33.429795 [CA 4] Center 34 (4~64) winsize 61
3198 11:50:33.432557 [CA 5] Center 33 (3~64) winsize 62
3199 11:50:33.433125
3200 11:50:33.436449 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3201 11:50:33.437020
3202 11:50:33.438995 [CATrainingPosCal] consider 2 rank data
3203 11:50:33.443102 u2DelayCellTimex100 = 270/100 ps
3204 11:50:33.445730 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3205 11:50:33.452316 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3206 11:50:33.456100 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3207 11:50:33.458780 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3208 11:50:33.462763 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 11:50:33.465812 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 11:50:33.466300
3211 11:50:33.468749 CA PerBit enable=1, Macro0, CA PI delay=33
3212 11:50:33.469220
3213 11:50:33.472188 [CBTSetCACLKResult] CA Dly = 33
3214 11:50:33.472657 CS Dly: 7 (0~40)
3215 11:50:33.475744
3216 11:50:33.479022 ----->DramcWriteLeveling(PI) begin...
3217 11:50:33.479500 ==
3218 11:50:33.482277 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 11:50:33.485529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 11:50:33.486003 ==
3221 11:50:33.488660 Write leveling (Byte 0): 25 => 25
3222 11:50:33.492129 Write leveling (Byte 1): 27 => 27
3223 11:50:33.495465 DramcWriteLeveling(PI) end<-----
3224 11:50:33.496055
3225 11:50:33.496438 ==
3226 11:50:33.498975 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 11:50:33.501880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 11:50:33.502352 ==
3229 11:50:33.505695 [Gating] SW mode calibration
3230 11:50:33.512369 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3231 11:50:33.518508 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3232 11:50:33.522238 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3233 11:50:33.525877 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 11:50:33.532255 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 11:50:33.535376 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 11:50:33.538413 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 11:50:33.545737 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 11:50:33.548707 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
3239 11:50:33.552550 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3240 11:50:33.558804 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 11:50:33.562576 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 11:50:33.566060 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 11:50:33.572217 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 11:50:33.574935 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 11:50:33.578340 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 11:50:33.581573 1 0 24 | B1->B0 | 2828 3c3c | 1 1 | (0 0) (0 0)
3247 11:50:33.588523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 11:50:33.591773 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3249 11:50:33.594963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 11:50:33.601736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 11:50:33.604878 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 11:50:33.608371 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 11:50:33.614922 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 11:50:33.618132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3255 11:50:33.621934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3256 11:50:33.628214 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 11:50:33.631560 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 11:50:33.635788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 11:50:33.641865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 11:50:33.644883 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 11:50:33.647836 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 11:50:33.654452 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 11:50:33.657608 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 11:50:33.662344 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 11:50:33.668115 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 11:50:33.671008 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 11:50:33.674256 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 11:50:33.680818 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 11:50:33.684372 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 11:50:33.688655 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3271 11:50:33.694161 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3272 11:50:33.697333 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 11:50:33.701201 Total UI for P1: 0, mck2ui 16
3274 11:50:33.704475 best dqsien dly found for B0: ( 1, 3, 26)
3275 11:50:33.707397 Total UI for P1: 0, mck2ui 16
3276 11:50:33.710545 best dqsien dly found for B1: ( 1, 3, 28)
3277 11:50:33.714349 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3278 11:50:33.717375 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3279 11:50:33.717978
3280 11:50:33.720974 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3281 11:50:33.724425 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3282 11:50:33.727306 [Gating] SW calibration Done
3283 11:50:33.727777 ==
3284 11:50:33.731101 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 11:50:33.733877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 11:50:33.737542 ==
3287 11:50:33.738097 RX Vref Scan: 0
3288 11:50:33.738466
3289 11:50:33.740431 RX Vref 0 -> 0, step: 1
3290 11:50:33.740896
3291 11:50:33.744167 RX Delay -40 -> 252, step: 8
3292 11:50:33.747280 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3293 11:50:33.750566 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3294 11:50:33.753717 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3295 11:50:33.757298 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3296 11:50:33.763755 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3297 11:50:33.767132 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3298 11:50:33.770365 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3299 11:50:33.774051 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3300 11:50:33.776992 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3301 11:50:33.784285 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3302 11:50:33.787165 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3303 11:50:33.790072 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3304 11:50:33.793866 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3305 11:50:33.797525 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3306 11:50:33.803519 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3307 11:50:33.806556 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3308 11:50:33.807027 ==
3309 11:50:33.810190 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 11:50:33.813373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 11:50:33.813895 ==
3312 11:50:33.816521 DQS Delay:
3313 11:50:33.817095 DQS0 = 0, DQS1 = 0
3314 11:50:33.817544 DQM Delay:
3315 11:50:33.819692 DQM0 = 117, DQM1 = 109
3316 11:50:33.820163 DQ Delay:
3317 11:50:33.823143 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3318 11:50:33.826920 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3319 11:50:33.830132 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3320 11:50:33.837461 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3321 11:50:33.838036
3322 11:50:33.838415
3323 11:50:33.838763 ==
3324 11:50:33.839668 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 11:50:33.843005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 11:50:33.843530 ==
3327 11:50:33.843918
3328 11:50:33.844267
3329 11:50:33.846135 TX Vref Scan disable
3330 11:50:33.846604 == TX Byte 0 ==
3331 11:50:33.853199 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3332 11:50:33.856433 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3333 11:50:33.857003 == TX Byte 1 ==
3334 11:50:33.863939 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3335 11:50:33.866196 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3336 11:50:33.866668 ==
3337 11:50:33.869755 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 11:50:33.873155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 11:50:33.873787 ==
3340 11:50:33.885964 TX Vref=22, minBit 11, minWin=24, winSum=418
3341 11:50:33.889566 TX Vref=24, minBit 10, minWin=25, winSum=420
3342 11:50:33.892829 TX Vref=26, minBit 11, minWin=25, winSum=430
3343 11:50:33.895846 TX Vref=28, minBit 11, minWin=25, winSum=433
3344 11:50:33.899097 TX Vref=30, minBit 9, minWin=26, winSum=430
3345 11:50:33.906379 TX Vref=32, minBit 9, minWin=25, winSum=428
3346 11:50:33.909135 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3347 11:50:33.909673
3348 11:50:33.912225 Final TX Range 1 Vref 30
3349 11:50:33.912699
3350 11:50:33.913071 ==
3351 11:50:33.915729 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 11:50:33.918899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 11:50:33.921941 ==
3354 11:50:33.922570
3355 11:50:33.922970
3356 11:50:33.923342 TX Vref Scan disable
3357 11:50:33.925488 == TX Byte 0 ==
3358 11:50:33.929405 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3359 11:50:33.932628 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3360 11:50:33.935535 == TX Byte 1 ==
3361 11:50:33.939142 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3362 11:50:33.945809 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3363 11:50:33.946285
3364 11:50:33.946623 [DATLAT]
3365 11:50:33.946937 Freq=1200, CH1 RK0
3366 11:50:33.947242
3367 11:50:33.948777 DATLAT Default: 0xd
3368 11:50:33.949195 0, 0xFFFF, sum = 0
3369 11:50:33.952399 1, 0xFFFF, sum = 0
3370 11:50:33.952829 2, 0xFFFF, sum = 0
3371 11:50:33.956329 3, 0xFFFF, sum = 0
3372 11:50:33.959353 4, 0xFFFF, sum = 0
3373 11:50:33.959891 5, 0xFFFF, sum = 0
3374 11:50:33.962296 6, 0xFFFF, sum = 0
3375 11:50:33.962725 7, 0xFFFF, sum = 0
3376 11:50:33.965345 8, 0xFFFF, sum = 0
3377 11:50:33.965812 9, 0xFFFF, sum = 0
3378 11:50:33.968864 10, 0xFFFF, sum = 0
3379 11:50:33.969291 11, 0xFFFF, sum = 0
3380 11:50:33.972376 12, 0x0, sum = 1
3381 11:50:33.972922 13, 0x0, sum = 2
3382 11:50:33.976095 14, 0x0, sum = 3
3383 11:50:33.976536 15, 0x0, sum = 4
3384 11:50:33.978694 best_step = 13
3385 11:50:33.979110
3386 11:50:33.979439 ==
3387 11:50:33.981893 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 11:50:33.985584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 11:50:33.986018 ==
3390 11:50:33.986357 RX Vref Scan: 1
3391 11:50:33.986678
3392 11:50:33.988904 Set Vref Range= 32 -> 127
3393 11:50:33.989474
3394 11:50:33.991689 RX Vref 32 -> 127, step: 1
3395 11:50:33.992113
3396 11:50:33.995621 RX Delay -21 -> 252, step: 4
3397 11:50:33.996150
3398 11:50:33.998660 Set Vref, RX VrefLevel [Byte0]: 32
3399 11:50:34.001607 [Byte1]: 32
3400 11:50:34.002227
3401 11:50:34.005363 Set Vref, RX VrefLevel [Byte0]: 33
3402 11:50:34.008343 [Byte1]: 33
3403 11:50:34.012354
3404 11:50:34.012881 Set Vref, RX VrefLevel [Byte0]: 34
3405 11:50:34.015502 [Byte1]: 34
3406 11:50:34.020670
3407 11:50:34.021345 Set Vref, RX VrefLevel [Byte0]: 35
3408 11:50:34.023593 [Byte1]: 35
3409 11:50:34.028238
3410 11:50:34.028779 Set Vref, RX VrefLevel [Byte0]: 36
3411 11:50:34.031796 [Byte1]: 36
3412 11:50:34.036306
3413 11:50:34.036829 Set Vref, RX VrefLevel [Byte0]: 37
3414 11:50:34.039287 [Byte1]: 37
3415 11:50:34.044251
3416 11:50:34.044775 Set Vref, RX VrefLevel [Byte0]: 38
3417 11:50:34.047437 [Byte1]: 38
3418 11:50:34.051836
3419 11:50:34.052358 Set Vref, RX VrefLevel [Byte0]: 39
3420 11:50:34.054808 [Byte1]: 39
3421 11:50:34.060412
3422 11:50:34.060956 Set Vref, RX VrefLevel [Byte0]: 40
3423 11:50:34.063826 [Byte1]: 40
3424 11:50:34.067499
3425 11:50:34.067921 Set Vref, RX VrefLevel [Byte0]: 41
3426 11:50:34.070836 [Byte1]: 41
3427 11:50:34.075971
3428 11:50:34.078418 Set Vref, RX VrefLevel [Byte0]: 42
3429 11:50:34.082052 [Byte1]: 42
3430 11:50:34.082585
3431 11:50:34.085268 Set Vref, RX VrefLevel [Byte0]: 43
3432 11:50:34.089014 [Byte1]: 43
3433 11:50:34.089578
3434 11:50:34.091987 Set Vref, RX VrefLevel [Byte0]: 44
3435 11:50:34.095635 [Byte1]: 44
3436 11:50:34.099598
3437 11:50:34.100125 Set Vref, RX VrefLevel [Byte0]: 45
3438 11:50:34.102626 [Byte1]: 45
3439 11:50:34.107154
3440 11:50:34.107678 Set Vref, RX VrefLevel [Byte0]: 46
3441 11:50:34.111245 [Byte1]: 46
3442 11:50:34.115462
3443 11:50:34.115989 Set Vref, RX VrefLevel [Byte0]: 47
3444 11:50:34.118315 [Byte1]: 47
3445 11:50:34.123194
3446 11:50:34.123618 Set Vref, RX VrefLevel [Byte0]: 48
3447 11:50:34.126325 [Byte1]: 48
3448 11:50:34.131099
3449 11:50:34.131628 Set Vref, RX VrefLevel [Byte0]: 49
3450 11:50:34.134033 [Byte1]: 49
3451 11:50:34.139026
3452 11:50:34.139546 Set Vref, RX VrefLevel [Byte0]: 50
3453 11:50:34.141935 [Byte1]: 50
3454 11:50:34.146850
3455 11:50:34.147378 Set Vref, RX VrefLevel [Byte0]: 51
3456 11:50:34.150199 [Byte1]: 51
3457 11:50:34.154989
3458 11:50:34.155512 Set Vref, RX VrefLevel [Byte0]: 52
3459 11:50:34.158136 [Byte1]: 52
3460 11:50:34.162970
3461 11:50:34.163509 Set Vref, RX VrefLevel [Byte0]: 53
3462 11:50:34.165901 [Byte1]: 53
3463 11:50:34.170458
3464 11:50:34.170882 Set Vref, RX VrefLevel [Byte0]: 54
3465 11:50:34.174500 [Byte1]: 54
3466 11:50:34.178655
3467 11:50:34.179083 Set Vref, RX VrefLevel [Byte0]: 55
3468 11:50:34.181451 [Byte1]: 55
3469 11:50:34.186384
3470 11:50:34.186808 Set Vref, RX VrefLevel [Byte0]: 56
3471 11:50:34.189938 [Byte1]: 56
3472 11:50:34.194129
3473 11:50:34.194554 Set Vref, RX VrefLevel [Byte0]: 57
3474 11:50:34.197487 [Byte1]: 57
3475 11:50:34.202566
3476 11:50:34.203139 Set Vref, RX VrefLevel [Byte0]: 58
3477 11:50:34.205346 [Byte1]: 58
3478 11:50:34.211035
3479 11:50:34.211628 Set Vref, RX VrefLevel [Byte0]: 59
3480 11:50:34.213206 [Byte1]: 59
3481 11:50:34.218014
3482 11:50:34.218484 Set Vref, RX VrefLevel [Byte0]: 60
3483 11:50:34.221641 [Byte1]: 60
3484 11:50:34.225924
3485 11:50:34.226397 Set Vref, RX VrefLevel [Byte0]: 61
3486 11:50:34.229447 [Byte1]: 61
3487 11:50:34.234231
3488 11:50:34.234794 Set Vref, RX VrefLevel [Byte0]: 62
3489 11:50:34.237038 [Byte1]: 62
3490 11:50:34.241718
3491 11:50:34.242190 Set Vref, RX VrefLevel [Byte0]: 63
3492 11:50:34.245133 [Byte1]: 63
3493 11:50:34.249763
3494 11:50:34.250235 Set Vref, RX VrefLevel [Byte0]: 64
3495 11:50:34.252812 [Byte1]: 64
3496 11:50:34.257779
3497 11:50:34.258219 Set Vref, RX VrefLevel [Byte0]: 65
3498 11:50:34.260718 [Byte1]: 65
3499 11:50:34.265896
3500 11:50:34.266458 Set Vref, RX VrefLevel [Byte0]: 66
3501 11:50:34.268781 [Byte1]: 66
3502 11:50:34.273296
3503 11:50:34.276517 Set Vref, RX VrefLevel [Byte0]: 67
3504 11:50:34.279652 [Byte1]: 67
3505 11:50:34.280180
3506 11:50:34.283156 Final RX Vref Byte 0 = 50 to rank0
3507 11:50:34.286291 Final RX Vref Byte 1 = 51 to rank0
3508 11:50:34.290091 Final RX Vref Byte 0 = 50 to rank1
3509 11:50:34.293542 Final RX Vref Byte 1 = 51 to rank1==
3510 11:50:34.296435 Dram Type= 6, Freq= 0, CH_1, rank 0
3511 11:50:34.299712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 11:50:34.300278 ==
3513 11:50:34.300765 DQS Delay:
3514 11:50:34.303040 DQS0 = 0, DQS1 = 0
3515 11:50:34.303469 DQM Delay:
3516 11:50:34.306292 DQM0 = 115, DQM1 = 109
3517 11:50:34.306883 DQ Delay:
3518 11:50:34.309757 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3519 11:50:34.312965 DQ4 =112, DQ5 =126, DQ6 =124, DQ7 =112
3520 11:50:34.316326 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =98
3521 11:50:34.320323 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3522 11:50:34.320855
3523 11:50:34.323290
3524 11:50:34.329861 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3525 11:50:34.332838 CH1 RK0: MR19=403, MR18=F4
3526 11:50:34.336166 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3527 11:50:34.339451
3528 11:50:34.342820 ----->DramcWriteLeveling(PI) begin...
3529 11:50:34.343355 ==
3530 11:50:34.346359 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 11:50:34.349944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 11:50:34.350375 ==
3533 11:50:34.352717 Write leveling (Byte 0): 24 => 24
3534 11:50:34.356248 Write leveling (Byte 1): 27 => 27
3535 11:50:34.359703 DramcWriteLeveling(PI) end<-----
3536 11:50:34.360219
3537 11:50:34.360565 ==
3538 11:50:34.362932 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 11:50:34.365657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 11:50:34.366094 ==
3541 11:50:34.368960 [Gating] SW mode calibration
3542 11:50:34.376399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3543 11:50:34.382316 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3544 11:50:34.385535 0 15 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3545 11:50:34.388937 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3546 11:50:34.395442 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3547 11:50:34.399063 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3548 11:50:34.401724 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 11:50:34.409203 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 11:50:34.412345 0 15 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
3551 11:50:34.416486 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3552 11:50:34.421617 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 11:50:34.424926 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3554 11:50:34.428576 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 11:50:34.434735 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 11:50:34.438312 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 11:50:34.441383 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 11:50:34.447855 1 0 24 | B1->B0 | 4141 2929 | 0 0 | (0 0) (0 0)
3559 11:50:34.451988 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3560 11:50:34.454728 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 11:50:34.461365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 11:50:34.464597 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 11:50:34.467484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 11:50:34.474016 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 11:50:34.478171 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 11:50:34.481007 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3567 11:50:34.488021 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3568 11:50:34.490586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 11:50:34.494406 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 11:50:34.500716 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 11:50:34.504421 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 11:50:34.507220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 11:50:34.514148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 11:50:34.517446 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 11:50:34.520921 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 11:50:34.527105 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 11:50:34.531095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 11:50:34.533808 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 11:50:34.540468 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 11:50:34.544452 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 11:50:34.547191 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 11:50:34.553447 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3583 11:50:34.557056 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3584 11:50:34.560223 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3585 11:50:34.563848 Total UI for P1: 0, mck2ui 16
3586 11:50:34.566766 best dqsien dly found for B0: ( 1, 3, 28)
3587 11:50:34.569949 Total UI for P1: 0, mck2ui 16
3588 11:50:34.573084 best dqsien dly found for B1: ( 1, 3, 26)
3589 11:50:34.576849 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3590 11:50:34.579676 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3591 11:50:34.583149
3592 11:50:34.587122 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3593 11:50:34.589849 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3594 11:50:34.593060 [Gating] SW calibration Done
3595 11:50:34.593681 ==
3596 11:50:34.596825 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 11:50:34.600287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 11:50:34.600864 ==
3599 11:50:34.601240 RX Vref Scan: 0
3600 11:50:34.602766
3601 11:50:34.603237 RX Vref 0 -> 0, step: 1
3602 11:50:34.603614
3603 11:50:34.606481 RX Delay -40 -> 252, step: 8
3604 11:50:34.609793 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3605 11:50:34.613006 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3606 11:50:34.619458 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3607 11:50:34.623268 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3608 11:50:34.626145 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3609 11:50:34.629495 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3610 11:50:34.635717 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3611 11:50:34.640294 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3612 11:50:34.642943 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3613 11:50:34.645877 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3614 11:50:34.649879 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3615 11:50:34.652974 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3616 11:50:34.659187 iDelay=200, Bit 12, Center 123 (48 ~ 199) 152
3617 11:50:34.662164 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3618 11:50:34.667217 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3619 11:50:34.668715 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3620 11:50:34.672624 ==
3621 11:50:34.673197 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 11:50:34.679203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 11:50:34.679756 ==
3624 11:50:34.680143 DQS Delay:
3625 11:50:34.682144 DQS0 = 0, DQS1 = 0
3626 11:50:34.682612 DQM Delay:
3627 11:50:34.685751 DQM0 = 116, DQM1 = 109
3628 11:50:34.686218 DQ Delay:
3629 11:50:34.688380 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3630 11:50:34.692338 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3631 11:50:34.695128 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3632 11:50:34.698743 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3633 11:50:34.699214
3634 11:50:34.699588
3635 11:50:34.699934 ==
3636 11:50:34.701757 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 11:50:34.708325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 11:50:34.708803 ==
3639 11:50:34.709180
3640 11:50:34.709578
3641 11:50:34.709921 TX Vref Scan disable
3642 11:50:34.711916 == TX Byte 0 ==
3643 11:50:34.715879 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3644 11:50:34.721888 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3645 11:50:34.722366 == TX Byte 1 ==
3646 11:50:34.725108 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3647 11:50:34.731672 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3648 11:50:34.732244 ==
3649 11:50:34.734734 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 11:50:34.738057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 11:50:34.738623 ==
3652 11:50:34.749880 TX Vref=22, minBit 8, minWin=25, winSum=427
3653 11:50:34.753386 TX Vref=24, minBit 9, minWin=25, winSum=429
3654 11:50:34.756839 TX Vref=26, minBit 9, minWin=26, winSum=435
3655 11:50:34.760171 TX Vref=28, minBit 9, minWin=26, winSum=437
3656 11:50:34.763321 TX Vref=30, minBit 9, minWin=26, winSum=437
3657 11:50:34.769941 TX Vref=32, minBit 9, minWin=26, winSum=436
3658 11:50:34.772951 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
3659 11:50:34.773471
3660 11:50:34.777202 Final TX Range 1 Vref 28
3661 11:50:34.777816
3662 11:50:34.778196 ==
3663 11:50:34.780730 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 11:50:34.783150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 11:50:34.785927 ==
3666 11:50:34.786398
3667 11:50:34.786774
3668 11:50:34.787120 TX Vref Scan disable
3669 11:50:34.789696 == TX Byte 0 ==
3670 11:50:34.792605 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3671 11:50:34.799894 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3672 11:50:34.800462 == TX Byte 1 ==
3673 11:50:34.802597 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3674 11:50:34.809271 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3675 11:50:34.810000
3676 11:50:34.810393 [DATLAT]
3677 11:50:34.810744 Freq=1200, CH1 RK1
3678 11:50:34.811091
3679 11:50:34.812247 DATLAT Default: 0xd
3680 11:50:34.815821 0, 0xFFFF, sum = 0
3681 11:50:34.816389 1, 0xFFFF, sum = 0
3682 11:50:34.819127 2, 0xFFFF, sum = 0
3683 11:50:34.819605 3, 0xFFFF, sum = 0
3684 11:50:34.822236 4, 0xFFFF, sum = 0
3685 11:50:34.822718 5, 0xFFFF, sum = 0
3686 11:50:34.825382 6, 0xFFFF, sum = 0
3687 11:50:34.826005 7, 0xFFFF, sum = 0
3688 11:50:34.829101 8, 0xFFFF, sum = 0
3689 11:50:34.829733 9, 0xFFFF, sum = 0
3690 11:50:34.832308 10, 0xFFFF, sum = 0
3691 11:50:34.832786 11, 0xFFFF, sum = 0
3692 11:50:34.835752 12, 0x0, sum = 1
3693 11:50:34.836325 13, 0x0, sum = 2
3694 11:50:34.839129 14, 0x0, sum = 3
3695 11:50:34.839713 15, 0x0, sum = 4
3696 11:50:34.842115 best_step = 13
3697 11:50:34.842588
3698 11:50:34.842965 ==
3699 11:50:34.845696 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 11:50:34.848364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 11:50:34.848840 ==
3702 11:50:34.852273 RX Vref Scan: 0
3703 11:50:34.852836
3704 11:50:34.853217 RX Vref 0 -> 0, step: 1
3705 11:50:34.853639
3706 11:50:34.855025 RX Delay -21 -> 252, step: 4
3707 11:50:34.861930 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3708 11:50:34.865311 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3709 11:50:34.868370 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3710 11:50:34.872199 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3711 11:50:34.875141 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3712 11:50:34.882184 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3713 11:50:34.884960 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3714 11:50:34.888327 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3715 11:50:34.891458 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3716 11:50:34.894846 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3717 11:50:34.901621 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3718 11:50:34.904610 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3719 11:50:34.908480 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3720 11:50:34.911379 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3721 11:50:34.918068 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3722 11:50:34.921160 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3723 11:50:34.921800 ==
3724 11:50:34.924576 Dram Type= 6, Freq= 0, CH_1, rank 1
3725 11:50:34.928144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3726 11:50:34.928715 ==
3727 11:50:34.930948 DQS Delay:
3728 11:50:34.931411 DQS0 = 0, DQS1 = 0
3729 11:50:34.931775 DQM Delay:
3730 11:50:34.934208 DQM0 = 116, DQM1 = 109
3731 11:50:34.934768 DQ Delay:
3732 11:50:34.937683 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3733 11:50:34.941541 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3734 11:50:34.947822 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3735 11:50:34.950737 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3736 11:50:34.951226
3737 11:50:34.951606
3738 11:50:34.957339 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3739 11:50:34.960724 CH1 RK1: MR19=303, MR18=F2EE
3740 11:50:34.966936 CH1_RK1: MR19=0x303, MR18=0xF2EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3741 11:50:34.970244 [RxdqsGatingPostProcess] freq 1200
3742 11:50:34.977225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3743 11:50:34.980895 best DQS0 dly(2T, 0.5T) = (0, 11)
3744 11:50:34.981496 best DQS1 dly(2T, 0.5T) = (0, 11)
3745 11:50:34.983231 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3746 11:50:34.987295 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3747 11:50:34.990096 best DQS0 dly(2T, 0.5T) = (0, 11)
3748 11:50:34.993991 best DQS1 dly(2T, 0.5T) = (0, 11)
3749 11:50:34.997025 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3750 11:50:35.000392 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3751 11:50:35.003612 Pre-setting of DQS Precalculation
3752 11:50:35.010278 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3753 11:50:35.016680 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3754 11:50:35.023111 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3755 11:50:35.023658
3756 11:50:35.024028
3757 11:50:35.026169 [Calibration Summary] 2400 Mbps
3758 11:50:35.026632 CH 0, Rank 0
3759 11:50:35.029657 SW Impedance : PASS
3760 11:50:35.033644 DUTY Scan : NO K
3761 11:50:35.034202 ZQ Calibration : PASS
3762 11:50:35.036462 Jitter Meter : NO K
3763 11:50:35.039652 CBT Training : PASS
3764 11:50:35.040210 Write leveling : PASS
3765 11:50:35.042902 RX DQS gating : PASS
3766 11:50:35.046289 RX DQ/DQS(RDDQC) : PASS
3767 11:50:35.046851 TX DQ/DQS : PASS
3768 11:50:35.049371 RX DATLAT : PASS
3769 11:50:35.052624 RX DQ/DQS(Engine): PASS
3770 11:50:35.053196 TX OE : NO K
3771 11:50:35.055980 All Pass.
3772 11:50:35.056449
3773 11:50:35.056821 CH 0, Rank 1
3774 11:50:35.059384 SW Impedance : PASS
3775 11:50:35.059958 DUTY Scan : NO K
3776 11:50:35.062629 ZQ Calibration : PASS
3777 11:50:35.065386 Jitter Meter : NO K
3778 11:50:35.065900 CBT Training : PASS
3779 11:50:35.069015 Write leveling : PASS
3780 11:50:35.072556 RX DQS gating : PASS
3781 11:50:35.073025 RX DQ/DQS(RDDQC) : PASS
3782 11:50:35.076143 TX DQ/DQS : PASS
3783 11:50:35.079213 RX DATLAT : PASS
3784 11:50:35.079685 RX DQ/DQS(Engine): PASS
3785 11:50:35.082446 TX OE : NO K
3786 11:50:35.082919 All Pass.
3787 11:50:35.083293
3788 11:50:35.085570 CH 1, Rank 0
3789 11:50:35.086141 SW Impedance : PASS
3790 11:50:35.089053 DUTY Scan : NO K
3791 11:50:35.089559 ZQ Calibration : PASS
3792 11:50:35.092295 Jitter Meter : NO K
3793 11:50:35.095390 CBT Training : PASS
3794 11:50:35.095974 Write leveling : PASS
3795 11:50:35.099267 RX DQS gating : PASS
3796 11:50:35.101968 RX DQ/DQS(RDDQC) : PASS
3797 11:50:35.102438 TX DQ/DQS : PASS
3798 11:50:35.105128 RX DATLAT : PASS
3799 11:50:35.109138 RX DQ/DQS(Engine): PASS
3800 11:50:35.109762 TX OE : NO K
3801 11:50:35.112036 All Pass.
3802 11:50:35.112504
3803 11:50:35.112878 CH 1, Rank 1
3804 11:50:35.115607 SW Impedance : PASS
3805 11:50:35.116078 DUTY Scan : NO K
3806 11:50:35.118266 ZQ Calibration : PASS
3807 11:50:35.122140 Jitter Meter : NO K
3808 11:50:35.122627 CBT Training : PASS
3809 11:50:35.125117 Write leveling : PASS
3810 11:50:35.129451 RX DQS gating : PASS
3811 11:50:35.129995 RX DQ/DQS(RDDQC) : PASS
3812 11:50:35.131263 TX DQ/DQS : PASS
3813 11:50:35.134601 RX DATLAT : PASS
3814 11:50:35.135160 RX DQ/DQS(Engine): PASS
3815 11:50:35.138102 TX OE : NO K
3816 11:50:35.138634 All Pass.
3817 11:50:35.138983
3818 11:50:35.141261 DramC Write-DBI off
3819 11:50:35.145342 PER_BANK_REFRESH: Hybrid Mode
3820 11:50:35.146019 TX_TRACKING: ON
3821 11:50:35.155146 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3822 11:50:35.157674 [FAST_K] Save calibration result to emmc
3823 11:50:35.161232 dramc_set_vcore_voltage set vcore to 650000
3824 11:50:35.164497 Read voltage for 600, 5
3825 11:50:35.165029 Vio18 = 0
3826 11:50:35.165372 Vcore = 650000
3827 11:50:35.167789 Vdram = 0
3828 11:50:35.168316 Vddq = 0
3829 11:50:35.168660 Vmddr = 0
3830 11:50:35.174414 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3831 11:50:35.177460 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3832 11:50:35.180947 MEM_TYPE=3, freq_sel=19
3833 11:50:35.183897 sv_algorithm_assistance_LP4_1600
3834 11:50:35.187367 ============ PULL DRAM RESETB DOWN ============
3835 11:50:35.193994 ========== PULL DRAM RESETB DOWN end =========
3836 11:50:35.197119 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3837 11:50:35.200712 ===================================
3838 11:50:35.203892 LPDDR4 DRAM CONFIGURATION
3839 11:50:35.207278 ===================================
3840 11:50:35.207809 EX_ROW_EN[0] = 0x0
3841 11:50:35.210941 EX_ROW_EN[1] = 0x0
3842 11:50:35.211477 LP4Y_EN = 0x0
3843 11:50:35.213545 WORK_FSP = 0x0
3844 11:50:35.213971 WL = 0x2
3845 11:50:35.217096 RL = 0x2
3846 11:50:35.217670 BL = 0x2
3847 11:50:35.220737 RPST = 0x0
3848 11:50:35.224700 RD_PRE = 0x0
3849 11:50:35.225228 WR_PRE = 0x1
3850 11:50:35.226745 WR_PST = 0x0
3851 11:50:35.227172 DBI_WR = 0x0
3852 11:50:35.230062 DBI_RD = 0x0
3853 11:50:35.230491 OTF = 0x1
3854 11:50:35.233395 ===================================
3855 11:50:35.236963 ===================================
3856 11:50:35.239895 ANA top config
3857 11:50:35.243429 ===================================
3858 11:50:35.243851 DLL_ASYNC_EN = 0
3859 11:50:35.246416 ALL_SLAVE_EN = 1
3860 11:50:35.249822 NEW_RANK_MODE = 1
3861 11:50:35.253988 DLL_IDLE_MODE = 1
3862 11:50:35.254406 LP45_APHY_COMB_EN = 1
3863 11:50:35.256562 TX_ODT_DIS = 1
3864 11:50:35.260357 NEW_8X_MODE = 1
3865 11:50:35.262910 ===================================
3866 11:50:35.266191 ===================================
3867 11:50:35.269500 data_rate = 1200
3868 11:50:35.272731 CKR = 1
3869 11:50:35.276198 DQ_P2S_RATIO = 8
3870 11:50:35.279459 ===================================
3871 11:50:35.279593 CA_P2S_RATIO = 8
3872 11:50:35.282952 DQ_CA_OPEN = 0
3873 11:50:35.286018 DQ_SEMI_OPEN = 0
3874 11:50:35.289061 CA_SEMI_OPEN = 0
3875 11:50:35.292314 CA_FULL_RATE = 0
3876 11:50:35.295752 DQ_CKDIV4_EN = 1
3877 11:50:35.295948 CA_CKDIV4_EN = 1
3878 11:50:35.299001 CA_PREDIV_EN = 0
3879 11:50:35.302183 PH8_DLY = 0
3880 11:50:35.305705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3881 11:50:35.309519 DQ_AAMCK_DIV = 4
3882 11:50:35.312443 CA_AAMCK_DIV = 4
3883 11:50:35.312552 CA_ADMCK_DIV = 4
3884 11:50:35.315291 DQ_TRACK_CA_EN = 0
3885 11:50:35.318689 CA_PICK = 600
3886 11:50:35.322180 CA_MCKIO = 600
3887 11:50:35.325227 MCKIO_SEMI = 0
3888 11:50:35.328606 PLL_FREQ = 2288
3889 11:50:35.331969 DQ_UI_PI_RATIO = 32
3890 11:50:35.332056 CA_UI_PI_RATIO = 0
3891 11:50:35.335115 ===================================
3892 11:50:35.338413 ===================================
3893 11:50:35.341656 memory_type:LPDDR4
3894 11:50:35.345387 GP_NUM : 10
3895 11:50:35.345482 SRAM_EN : 1
3896 11:50:35.348277 MD32_EN : 0
3897 11:50:35.351929 ===================================
3898 11:50:35.355192 [ANA_INIT] >>>>>>>>>>>>>>
3899 11:50:35.358673 <<<<<< [CONFIGURE PHASE]: ANA_TX
3900 11:50:35.362126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3901 11:50:35.365349 ===================================
3902 11:50:35.368231 data_rate = 1200,PCW = 0X5800
3903 11:50:35.371587 ===================================
3904 11:50:35.375079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3905 11:50:35.378080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3906 11:50:35.385005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3907 11:50:35.388042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3908 11:50:35.391148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3909 11:50:35.394411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3910 11:50:35.398197 [ANA_INIT] flow start
3911 11:50:35.400961 [ANA_INIT] PLL >>>>>>>>
3912 11:50:35.401090 [ANA_INIT] PLL <<<<<<<<
3913 11:50:35.404867 [ANA_INIT] MIDPI >>>>>>>>
3914 11:50:35.407786 [ANA_INIT] MIDPI <<<<<<<<
3915 11:50:35.411057 [ANA_INIT] DLL >>>>>>>>
3916 11:50:35.411242 [ANA_INIT] flow end
3917 11:50:35.414206 ============ LP4 DIFF to SE enter ============
3918 11:50:35.421193 ============ LP4 DIFF to SE exit ============
3919 11:50:35.421437 [ANA_INIT] <<<<<<<<<<<<<
3920 11:50:35.424411 [Flow] Enable top DCM control >>>>>
3921 11:50:35.428098 [Flow] Enable top DCM control <<<<<
3922 11:50:35.431183 Enable DLL master slave shuffle
3923 11:50:35.437851 ==============================================================
3924 11:50:35.438075 Gating Mode config
3925 11:50:35.444437 ==============================================================
3926 11:50:35.447601 Config description:
3927 11:50:35.457485 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3928 11:50:35.464798 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3929 11:50:35.467706 SELPH_MODE 0: By rank 1: By Phase
3930 11:50:35.474563 ==============================================================
3931 11:50:35.477538 GAT_TRACK_EN = 1
3932 11:50:35.481337 RX_GATING_MODE = 2
3933 11:50:35.481837 RX_GATING_TRACK_MODE = 2
3934 11:50:35.483998 SELPH_MODE = 1
3935 11:50:35.487538 PICG_EARLY_EN = 1
3936 11:50:35.490686 VALID_LAT_VALUE = 1
3937 11:50:35.497295 ==============================================================
3938 11:50:35.500986 Enter into Gating configuration >>>>
3939 11:50:35.504021 Exit from Gating configuration <<<<
3940 11:50:35.507627 Enter into DVFS_PRE_config >>>>>
3941 11:50:35.517693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3942 11:50:35.520529 Exit from DVFS_PRE_config <<<<<
3943 11:50:35.523738 Enter into PICG configuration >>>>
3944 11:50:35.527406 Exit from PICG configuration <<<<
3945 11:50:35.530450 [RX_INPUT] configuration >>>>>
3946 11:50:35.533626 [RX_INPUT] configuration <<<<<
3947 11:50:35.537098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3948 11:50:35.543302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3949 11:50:35.550163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3950 11:50:35.557740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3951 11:50:35.563817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3952 11:50:35.566643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3953 11:50:35.573821 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3954 11:50:35.576323 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3955 11:50:35.580695 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3956 11:50:35.583078 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3957 11:50:35.589922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3958 11:50:35.593114 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3959 11:50:35.596010 ===================================
3960 11:50:35.599163 LPDDR4 DRAM CONFIGURATION
3961 11:50:35.603509 ===================================
3962 11:50:35.604069 EX_ROW_EN[0] = 0x0
3963 11:50:35.606064 EX_ROW_EN[1] = 0x0
3964 11:50:35.609736 LP4Y_EN = 0x0
3965 11:50:35.610352 WORK_FSP = 0x0
3966 11:50:35.612525 WL = 0x2
3967 11:50:35.613093 RL = 0x2
3968 11:50:35.615725 BL = 0x2
3969 11:50:35.616184 RPST = 0x0
3970 11:50:35.618969 RD_PRE = 0x0
3971 11:50:35.619540 WR_PRE = 0x1
3972 11:50:35.622285 WR_PST = 0x0
3973 11:50:35.622748 DBI_WR = 0x0
3974 11:50:35.626250 DBI_RD = 0x0
3975 11:50:35.626715 OTF = 0x1
3976 11:50:35.628758 ===================================
3977 11:50:35.632606 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3978 11:50:35.638740 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3979 11:50:35.642377 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3980 11:50:35.645392 ===================================
3981 11:50:35.649236 LPDDR4 DRAM CONFIGURATION
3982 11:50:35.651742 ===================================
3983 11:50:35.652207 EX_ROW_EN[0] = 0x10
3984 11:50:35.655000 EX_ROW_EN[1] = 0x0
3985 11:50:35.658745 LP4Y_EN = 0x0
3986 11:50:35.659210 WORK_FSP = 0x0
3987 11:50:35.662202 WL = 0x2
3988 11:50:35.662663 RL = 0x2
3989 11:50:35.665800 BL = 0x2
3990 11:50:35.666361 RPST = 0x0
3991 11:50:35.668861 RD_PRE = 0x0
3992 11:50:35.669315 WR_PRE = 0x1
3993 11:50:35.672030 WR_PST = 0x0
3994 11:50:35.672533 DBI_WR = 0x0
3995 11:50:35.675443 DBI_RD = 0x0
3996 11:50:35.676005 OTF = 0x1
3997 11:50:35.678713 ===================================
3998 11:50:35.684930 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3999 11:50:35.689273 nWR fixed to 30
4000 11:50:35.693022 [ModeRegInit_LP4] CH0 RK0
4001 11:50:35.693623 [ModeRegInit_LP4] CH0 RK1
4002 11:50:35.695928 [ModeRegInit_LP4] CH1 RK0
4003 11:50:35.699422 [ModeRegInit_LP4] CH1 RK1
4004 11:50:35.699989 match AC timing 17
4005 11:50:35.705933 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4006 11:50:35.709947 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4007 11:50:35.713007 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4008 11:50:35.719141 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4009 11:50:35.722274 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4010 11:50:35.722740 ==
4011 11:50:35.726336 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 11:50:35.729246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 11:50:35.729856 ==
4014 11:50:35.735862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 11:50:35.741930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4016 11:50:35.745636 [CA 0] Center 36 (6~66) winsize 61
4017 11:50:35.748847 [CA 1] Center 36 (6~66) winsize 61
4018 11:50:35.751768 [CA 2] Center 34 (3~65) winsize 63
4019 11:50:35.755289 [CA 3] Center 34 (3~65) winsize 63
4020 11:50:35.758883 [CA 4] Center 33 (3~64) winsize 62
4021 11:50:35.762312 [CA 5] Center 33 (3~64) winsize 62
4022 11:50:35.762872
4023 11:50:35.765142 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4024 11:50:35.765696
4025 11:50:35.768494 [CATrainingPosCal] consider 1 rank data
4026 11:50:35.771798 u2DelayCellTimex100 = 270/100 ps
4027 11:50:35.774841 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4028 11:50:35.778053 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 11:50:35.781400 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4030 11:50:35.788557 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4031 11:50:35.791506 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 11:50:35.794574 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 11:50:35.795209
4034 11:50:35.798550 CA PerBit enable=1, Macro0, CA PI delay=33
4035 11:50:35.799119
4036 11:50:35.801590 [CBTSetCACLKResult] CA Dly = 33
4037 11:50:35.802054 CS Dly: 6 (0~37)
4038 11:50:35.802421 ==
4039 11:50:35.805009 Dram Type= 6, Freq= 0, CH_0, rank 1
4040 11:50:35.811856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 11:50:35.812423 ==
4042 11:50:35.814827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4043 11:50:35.821692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4044 11:50:35.824876 [CA 0] Center 36 (6~66) winsize 61
4045 11:50:35.829595 [CA 1] Center 36 (6~66) winsize 61
4046 11:50:35.831729 [CA 2] Center 33 (3~64) winsize 62
4047 11:50:35.834611 [CA 3] Center 33 (3~64) winsize 62
4048 11:50:35.838023 [CA 4] Center 33 (3~64) winsize 62
4049 11:50:35.841390 [CA 5] Center 33 (2~64) winsize 63
4050 11:50:35.841990
4051 11:50:35.844738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4052 11:50:35.845304
4053 11:50:35.847705 [CATrainingPosCal] consider 2 rank data
4054 11:50:35.851058 u2DelayCellTimex100 = 270/100 ps
4055 11:50:35.854069 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4056 11:50:35.861656 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4057 11:50:35.864915 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4058 11:50:35.867212 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4059 11:50:35.870751 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4060 11:50:35.874789 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4061 11:50:35.875350
4062 11:50:35.877207 CA PerBit enable=1, Macro0, CA PI delay=33
4063 11:50:35.877697
4064 11:50:35.880491 [CBTSetCACLKResult] CA Dly = 33
4065 11:50:35.883960 CS Dly: 6 (0~37)
4066 11:50:35.884422
4067 11:50:35.886965 ----->DramcWriteLeveling(PI) begin...
4068 11:50:35.887541 ==
4069 11:50:35.890606 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 11:50:35.893641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 11:50:35.894196 ==
4072 11:50:35.897062 Write leveling (Byte 0): 31 => 31
4073 11:50:35.900577 Write leveling (Byte 1): 29 => 29
4074 11:50:35.903397 DramcWriteLeveling(PI) end<-----
4075 11:50:35.903859
4076 11:50:35.904224 ==
4077 11:50:35.906764 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 11:50:35.910374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 11:50:35.910939 ==
4080 11:50:35.913341 [Gating] SW mode calibration
4081 11:50:35.920442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4082 11:50:35.926910 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4083 11:50:35.929466 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4084 11:50:35.936709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4085 11:50:35.939736 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4086 11:50:35.943665 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (0 0) (1 1)
4087 11:50:35.950012 0 9 16 | B1->B0 | 2f2f 2929 | 1 1 | (1 0) (1 0)
4088 11:50:35.952845 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 11:50:35.956320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 11:50:35.962920 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 11:50:35.966024 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 11:50:35.969397 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 11:50:35.976128 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 11:50:35.979270 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 11:50:35.982554 0 10 16 | B1->B0 | 3434 3d3d | 1 1 | (0 0) (0 0)
4096 11:50:35.988736 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 11:50:35.992729 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 11:50:35.995740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 11:50:36.002192 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 11:50:36.005812 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 11:50:36.008675 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 11:50:36.015574 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4103 11:50:36.018367 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4104 11:50:36.021639 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 11:50:36.028815 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 11:50:36.032091 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 11:50:36.035185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 11:50:36.041854 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 11:50:36.044921 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 11:50:36.048332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 11:50:36.055660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 11:50:36.057889 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 11:50:36.061591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 11:50:36.067933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 11:50:36.072132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 11:50:36.074491 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 11:50:36.081093 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 11:50:36.085042 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4119 11:50:36.087878 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4120 11:50:36.091513 Total UI for P1: 0, mck2ui 16
4121 11:50:36.094562 best dqsien dly found for B0: ( 0, 13, 12)
4122 11:50:36.101384 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4123 11:50:36.102002 Total UI for P1: 0, mck2ui 16
4124 11:50:36.104639 best dqsien dly found for B1: ( 0, 13, 18)
4125 11:50:36.111284 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4126 11:50:36.114546 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4127 11:50:36.115110
4128 11:50:36.117571 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4129 11:50:36.120666 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4130 11:50:36.124635 [Gating] SW calibration Done
4131 11:50:36.125201 ==
4132 11:50:36.127966 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 11:50:36.131117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 11:50:36.131721 ==
4135 11:50:36.134660 RX Vref Scan: 0
4136 11:50:36.135227
4137 11:50:36.135707 RX Vref 0 -> 0, step: 1
4138 11:50:36.136228
4139 11:50:36.137209 RX Delay -230 -> 252, step: 16
4140 11:50:36.143964 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4141 11:50:36.148135 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4142 11:50:36.151328 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4143 11:50:36.154553 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4144 11:50:36.156982 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4145 11:50:36.163676 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4146 11:50:36.167321 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4147 11:50:36.170572 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4148 11:50:36.173538 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4149 11:50:36.180465 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4150 11:50:36.184105 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4151 11:50:36.187388 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4152 11:50:36.190243 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4153 11:50:36.196669 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4154 11:50:36.200587 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4155 11:50:36.203694 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4156 11:50:36.204163 ==
4157 11:50:36.207213 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 11:50:36.210148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 11:50:36.213264 ==
4160 11:50:36.213865 DQS Delay:
4161 11:50:36.214244 DQS0 = 0, DQS1 = 0
4162 11:50:36.216805 DQM Delay:
4163 11:50:36.217467 DQM0 = 42, DQM1 = 31
4164 11:50:36.220368 DQ Delay:
4165 11:50:36.223560 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4166 11:50:36.224121 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4167 11:50:36.226232 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4168 11:50:36.229713 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4169 11:50:36.233232
4170 11:50:36.233837
4171 11:50:36.234213 ==
4172 11:50:36.236314 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 11:50:36.240348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 11:50:36.240931 ==
4175 11:50:36.241315
4176 11:50:36.241739
4177 11:50:36.243075 TX Vref Scan disable
4178 11:50:36.243545 == TX Byte 0 ==
4179 11:50:36.250017 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4180 11:50:36.253001 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4181 11:50:36.253603 == TX Byte 1 ==
4182 11:50:36.259790 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4183 11:50:36.262721 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4184 11:50:36.263190 ==
4185 11:50:36.266149 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 11:50:36.269538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 11:50:36.270095 ==
4188 11:50:36.270470
4189 11:50:36.270813
4190 11:50:36.272888 TX Vref Scan disable
4191 11:50:36.276464 == TX Byte 0 ==
4192 11:50:36.279648 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4193 11:50:36.285837 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4194 11:50:36.286387 == TX Byte 1 ==
4195 11:50:36.289767 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4196 11:50:36.295800 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4197 11:50:36.296366
4198 11:50:36.296742 [DATLAT]
4199 11:50:36.297103 Freq=600, CH0 RK0
4200 11:50:36.297528
4201 11:50:36.299107 DATLAT Default: 0x9
4202 11:50:36.299642 0, 0xFFFF, sum = 0
4203 11:50:36.302635 1, 0xFFFF, sum = 0
4204 11:50:36.303223 2, 0xFFFF, sum = 0
4205 11:50:36.305856 3, 0xFFFF, sum = 0
4206 11:50:36.309385 4, 0xFFFF, sum = 0
4207 11:50:36.309996 5, 0xFFFF, sum = 0
4208 11:50:36.313643 6, 0xFFFF, sum = 0
4209 11:50:36.314207 7, 0xFFFF, sum = 0
4210 11:50:36.316032 8, 0x0, sum = 1
4211 11:50:36.316597 9, 0x0, sum = 2
4212 11:50:36.316981 10, 0x0, sum = 3
4213 11:50:36.319611 11, 0x0, sum = 4
4214 11:50:36.320019 best_step = 9
4215 11:50:36.320375
4216 11:50:36.320725 ==
4217 11:50:36.322616 Dram Type= 6, Freq= 0, CH_0, rank 0
4218 11:50:36.329541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 11:50:36.330102 ==
4220 11:50:36.330480 RX Vref Scan: 1
4221 11:50:36.330835
4222 11:50:36.332585 RX Vref 0 -> 0, step: 1
4223 11:50:36.333049
4224 11:50:36.335484 RX Delay -195 -> 252, step: 8
4225 11:50:36.336123
4226 11:50:36.338752 Set Vref, RX VrefLevel [Byte0]: 62
4227 11:50:36.342210 [Byte1]: 50
4228 11:50:36.342679
4229 11:50:36.345157 Final RX Vref Byte 0 = 62 to rank0
4230 11:50:36.348957 Final RX Vref Byte 1 = 50 to rank0
4231 11:50:36.352448 Final RX Vref Byte 0 = 62 to rank1
4232 11:50:36.355359 Final RX Vref Byte 1 = 50 to rank1==
4233 11:50:36.359554 Dram Type= 6, Freq= 0, CH_0, rank 0
4234 11:50:36.361806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 11:50:36.365529 ==
4236 11:50:36.366095 DQS Delay:
4237 11:50:36.366473 DQS0 = 0, DQS1 = 0
4238 11:50:36.369967 DQM Delay:
4239 11:50:36.370526 DQM0 = 43, DQM1 = 32
4240 11:50:36.371552 DQ Delay:
4241 11:50:36.372016 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4242 11:50:36.374876 DQ4 =44, DQ5 =36, DQ6 =48, DQ7 =48
4243 11:50:36.378373 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4244 11:50:36.381367 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4245 11:50:36.384811
4246 11:50:36.385277
4247 11:50:36.391668 [DQSOSCAuto] RK0, (LSB)MR18= 0x6037, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4248 11:50:36.395090 CH0 RK0: MR19=808, MR18=6037
4249 11:50:36.401292 CH0_RK0: MR19=0x808, MR18=0x6037, DQSOSC=391, MR23=63, INC=171, DEC=114
4250 11:50:36.401775
4251 11:50:36.404407 ----->DramcWriteLeveling(PI) begin...
4252 11:50:36.404835 ==
4253 11:50:36.407921 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 11:50:36.411373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 11:50:36.411842 ==
4256 11:50:36.414724 Write leveling (Byte 0): 33 => 33
4257 11:50:36.417886 Write leveling (Byte 1): 32 => 32
4258 11:50:36.421286 DramcWriteLeveling(PI) end<-----
4259 11:50:36.421748
4260 11:50:36.422091 ==
4261 11:50:36.424223 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 11:50:36.427824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 11:50:36.428251 ==
4264 11:50:36.430761 [Gating] SW mode calibration
4265 11:50:36.437399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4266 11:50:36.444237 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4267 11:50:36.447822 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4268 11:50:36.454125 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4269 11:50:36.457368 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4270 11:50:36.460743 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4271 11:50:36.467483 0 9 16 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (1 1)
4272 11:50:36.471079 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 11:50:36.473483 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 11:50:36.481222 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 11:50:36.484127 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 11:50:36.487078 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 11:50:36.493748 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 11:50:36.496558 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4279 11:50:36.500398 0 10 16 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4280 11:50:36.506711 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 11:50:36.510200 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 11:50:36.513036 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 11:50:36.519883 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 11:50:36.523080 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 11:50:36.526169 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 11:50:36.533081 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 11:50:36.536499 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4288 11:50:36.540061 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 11:50:36.546087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 11:50:36.549364 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 11:50:36.552820 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 11:50:36.559406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 11:50:36.563045 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 11:50:36.565806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 11:50:36.573078 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 11:50:36.576156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 11:50:36.579356 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 11:50:36.586035 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 11:50:36.589566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 11:50:36.592465 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 11:50:36.599517 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 11:50:36.602220 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4303 11:50:36.605873 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 11:50:36.609297 Total UI for P1: 0, mck2ui 16
4305 11:50:36.612836 best dqsien dly found for B0: ( 0, 13, 14)
4306 11:50:36.615598 Total UI for P1: 0, mck2ui 16
4307 11:50:36.618986 best dqsien dly found for B1: ( 0, 13, 12)
4308 11:50:36.622305 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4309 11:50:36.625766 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4310 11:50:36.626331
4311 11:50:36.632334 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4312 11:50:36.635733 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4313 11:50:36.638979 [Gating] SW calibration Done
4314 11:50:36.639559 ==
4315 11:50:36.642289 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:50:36.645943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:50:36.646513 ==
4318 11:50:36.646892 RX Vref Scan: 0
4319 11:50:36.647244
4320 11:50:36.648982 RX Vref 0 -> 0, step: 1
4321 11:50:36.649596
4322 11:50:36.651920 RX Delay -230 -> 252, step: 16
4323 11:50:36.655665 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4324 11:50:36.659244 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4325 11:50:36.665114 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4326 11:50:36.668837 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4327 11:50:36.671839 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4328 11:50:36.675080 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4329 11:50:36.681670 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4330 11:50:36.685812 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4331 11:50:36.689076 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4332 11:50:36.692380 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4333 11:50:36.698295 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4334 11:50:36.701540 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4335 11:50:36.705296 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4336 11:50:36.708758 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4337 11:50:36.716262 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4338 11:50:36.718061 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4339 11:50:36.718534 ==
4340 11:50:36.722554 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 11:50:36.724500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 11:50:36.724972 ==
4343 11:50:36.728471 DQS Delay:
4344 11:50:36.729030 DQS0 = 0, DQS1 = 0
4345 11:50:36.729404 DQM Delay:
4346 11:50:36.731220 DQM0 = 41, DQM1 = 33
4347 11:50:36.731778 DQ Delay:
4348 11:50:36.734931 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4349 11:50:36.738020 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4350 11:50:36.740969 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4351 11:50:36.744614 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4352 11:50:36.745183
4353 11:50:36.745599
4354 11:50:36.745944 ==
4355 11:50:36.747915 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 11:50:36.754893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 11:50:36.755460 ==
4358 11:50:36.755837
4359 11:50:36.756180
4360 11:50:36.756507 TX Vref Scan disable
4361 11:50:36.757975 == TX Byte 0 ==
4362 11:50:36.761027 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4363 11:50:36.768153 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4364 11:50:36.768622 == TX Byte 1 ==
4365 11:50:36.771167 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4366 11:50:36.777957 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4367 11:50:36.778450 ==
4368 11:50:36.780967 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 11:50:36.784200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 11:50:36.784763 ==
4371 11:50:36.785138
4372 11:50:36.785533
4373 11:50:36.787187 TX Vref Scan disable
4374 11:50:36.790801 == TX Byte 0 ==
4375 11:50:36.794354 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4376 11:50:36.797291 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4377 11:50:36.800921 == TX Byte 1 ==
4378 11:50:36.804304 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4379 11:50:36.807286 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4380 11:50:36.807756
4381 11:50:36.810244 [DATLAT]
4382 11:50:36.810712 Freq=600, CH0 RK1
4383 11:50:36.811083
4384 11:50:36.813559 DATLAT Default: 0x9
4385 11:50:36.814031 0, 0xFFFF, sum = 0
4386 11:50:36.817251 1, 0xFFFF, sum = 0
4387 11:50:36.817903 2, 0xFFFF, sum = 0
4388 11:50:36.820070 3, 0xFFFF, sum = 0
4389 11:50:36.820543 4, 0xFFFF, sum = 0
4390 11:50:36.823878 5, 0xFFFF, sum = 0
4391 11:50:36.824444 6, 0xFFFF, sum = 0
4392 11:50:36.827332 7, 0xFFFF, sum = 0
4393 11:50:36.827805 8, 0x0, sum = 1
4394 11:50:36.830357 9, 0x0, sum = 2
4395 11:50:36.830926 10, 0x0, sum = 3
4396 11:50:36.833452 11, 0x0, sum = 4
4397 11:50:36.833932 best_step = 9
4398 11:50:36.834299
4399 11:50:36.834641 ==
4400 11:50:36.836857 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 11:50:36.840694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 11:50:36.843917 ==
4403 11:50:36.844474 RX Vref Scan: 0
4404 11:50:36.844992
4405 11:50:36.846652 RX Vref 0 -> 0, step: 1
4406 11:50:36.847120
4407 11:50:36.849965 RX Delay -195 -> 252, step: 8
4408 11:50:36.853444 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4409 11:50:36.856719 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4410 11:50:36.863216 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4411 11:50:36.867243 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4412 11:50:36.869828 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4413 11:50:36.873291 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4414 11:50:36.880756 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4415 11:50:36.883009 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4416 11:50:36.886673 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4417 11:50:36.890484 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4418 11:50:36.897094 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4419 11:50:36.900223 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4420 11:50:36.903253 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4421 11:50:36.906202 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4422 11:50:36.913389 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4423 11:50:36.916327 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4424 11:50:36.916879 ==
4425 11:50:36.919161 Dram Type= 6, Freq= 0, CH_0, rank 1
4426 11:50:36.922600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 11:50:36.923073 ==
4428 11:50:36.923451 DQS Delay:
4429 11:50:36.926206 DQS0 = 0, DQS1 = 0
4430 11:50:36.926675 DQM Delay:
4431 11:50:36.930398 DQM0 = 41, DQM1 = 37
4432 11:50:36.930960 DQ Delay:
4433 11:50:36.932413 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4434 11:50:36.936080 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4435 11:50:36.939506 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4436 11:50:36.942489 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4437 11:50:36.943054
4438 11:50:36.943425
4439 11:50:36.952209 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4440 11:50:36.952779 CH0 RK1: MR19=808, MR18=5C10
4441 11:50:36.959177 CH0_RK1: MR19=0x808, MR18=0x5C10, DQSOSC=392, MR23=63, INC=170, DEC=113
4442 11:50:36.963105 [RxdqsGatingPostProcess] freq 600
4443 11:50:36.969537 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4444 11:50:36.972028 Pre-setting of DQS Precalculation
4445 11:50:36.975133 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4446 11:50:36.975661 ==
4447 11:50:36.978746 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 11:50:36.985354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 11:50:36.985871 ==
4450 11:50:36.988822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 11:50:36.995467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4452 11:50:36.998681 [CA 0] Center 35 (5~66) winsize 62
4453 11:50:37.001745 [CA 1] Center 35 (5~66) winsize 62
4454 11:50:37.005207 [CA 2] Center 34 (4~65) winsize 62
4455 11:50:37.008225 [CA 3] Center 33 (3~64) winsize 62
4456 11:50:37.011894 [CA 4] Center 34 (4~64) winsize 61
4457 11:50:37.015134 [CA 5] Center 33 (3~64) winsize 62
4458 11:50:37.015711
4459 11:50:37.018235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4460 11:50:37.018711
4461 11:50:37.021607 [CATrainingPosCal] consider 1 rank data
4462 11:50:37.024826 u2DelayCellTimex100 = 270/100 ps
4463 11:50:37.028323 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 11:50:37.035269 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 11:50:37.037851 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 11:50:37.041626 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 11:50:37.045245 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4468 11:50:37.047980 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 11:50:37.048542
4470 11:50:37.052071 CA PerBit enable=1, Macro0, CA PI delay=33
4471 11:50:37.052646
4472 11:50:37.055301 [CBTSetCACLKResult] CA Dly = 33
4473 11:50:37.058213 CS Dly: 4 (0~35)
4474 11:50:37.058683 ==
4475 11:50:37.061327 Dram Type= 6, Freq= 0, CH_1, rank 1
4476 11:50:37.064463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 11:50:37.065025 ==
4478 11:50:37.070754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4479 11:50:37.074559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4480 11:50:37.078913 [CA 0] Center 35 (5~66) winsize 62
4481 11:50:37.082250 [CA 1] Center 36 (6~66) winsize 61
4482 11:50:37.085127 [CA 2] Center 34 (4~65) winsize 62
4483 11:50:37.088561 [CA 3] Center 34 (3~65) winsize 63
4484 11:50:37.091446 [CA 4] Center 34 (3~65) winsize 63
4485 11:50:37.096251 [CA 5] Center 34 (3~65) winsize 63
4486 11:50:37.096816
4487 11:50:37.098089 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4488 11:50:37.098555
4489 11:50:37.101262 [CATrainingPosCal] consider 2 rank data
4490 11:50:37.105525 u2DelayCellTimex100 = 270/100 ps
4491 11:50:37.108108 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4492 11:50:37.115175 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4493 11:50:37.118007 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4494 11:50:37.121692 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4495 11:50:37.125160 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4496 11:50:37.127843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4497 11:50:37.128316
4498 11:50:37.131296 CA PerBit enable=1, Macro0, CA PI delay=33
4499 11:50:37.131767
4500 11:50:37.134501 [CBTSetCACLKResult] CA Dly = 33
4501 11:50:37.137783 CS Dly: 4 (0~36)
4502 11:50:37.138371
4503 11:50:37.141126 ----->DramcWriteLeveling(PI) begin...
4504 11:50:37.141769 ==
4505 11:50:37.145146 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 11:50:37.148071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 11:50:37.148549 ==
4508 11:50:37.150955 Write leveling (Byte 0): 29 => 29
4509 11:50:37.154424 Write leveling (Byte 1): 32 => 32
4510 11:50:37.157858 DramcWriteLeveling(PI) end<-----
4511 11:50:37.158426
4512 11:50:37.158804 ==
4513 11:50:37.160976 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 11:50:37.163941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 11:50:37.164412 ==
4516 11:50:37.168001 [Gating] SW mode calibration
4517 11:50:37.174747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4518 11:50:37.180517 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4519 11:50:37.183981 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4520 11:50:37.190446 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4521 11:50:37.193573 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4522 11:50:37.197128 0 9 12 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (1 1)
4523 11:50:37.203756 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4524 11:50:37.207591 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 11:50:37.210810 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 11:50:37.213547 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 11:50:37.220230 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 11:50:37.223458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 11:50:37.226682 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4530 11:50:37.234210 0 10 12 | B1->B0 | 2d2d 3737 | 0 0 | (0 0) (0 0)
4531 11:50:37.237256 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 11:50:37.240827 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 11:50:37.247120 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 11:50:37.249610 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 11:50:37.256022 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 11:50:37.259863 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 11:50:37.262667 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 11:50:37.269626 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4539 11:50:37.273356 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 11:50:37.276502 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 11:50:37.280041 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 11:50:37.286150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 11:50:37.289521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 11:50:37.295845 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 11:50:37.299154 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 11:50:37.302339 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 11:50:37.309549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 11:50:37.312242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 11:50:37.315801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 11:50:37.322362 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 11:50:37.325369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 11:50:37.328461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 11:50:37.335533 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 11:50:37.338771 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4555 11:50:37.342131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4556 11:50:37.345326 Total UI for P1: 0, mck2ui 16
4557 11:50:37.348743 best dqsien dly found for B1: ( 0, 13, 14)
4558 11:50:37.354797 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4559 11:50:37.355348 Total UI for P1: 0, mck2ui 16
4560 11:50:37.358453 best dqsien dly found for B0: ( 0, 13, 14)
4561 11:50:37.365062 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4562 11:50:37.368226 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4563 11:50:37.368692
4564 11:50:37.371484 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4565 11:50:37.374717 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4566 11:50:37.378540 [Gating] SW calibration Done
4567 11:50:37.379004 ==
4568 11:50:37.381394 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:50:37.384915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:50:37.385536 ==
4571 11:50:37.388325 RX Vref Scan: 0
4572 11:50:37.388880
4573 11:50:37.389346 RX Vref 0 -> 0, step: 1
4574 11:50:37.389775
4575 11:50:37.391294 RX Delay -230 -> 252, step: 16
4576 11:50:37.398082 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4577 11:50:37.401344 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4578 11:50:37.404459 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4579 11:50:37.408309 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4580 11:50:37.411801 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4581 11:50:37.417386 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4582 11:50:37.421097 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4583 11:50:37.424393 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4584 11:50:37.427520 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4585 11:50:37.434324 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4586 11:50:37.438276 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4587 11:50:37.440927 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4588 11:50:37.444335 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4589 11:50:37.450999 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4590 11:50:37.453741 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4591 11:50:37.457122 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4592 11:50:37.457840 ==
4593 11:50:37.460577 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 11:50:37.463529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 11:50:37.467301 ==
4596 11:50:37.467818 DQS Delay:
4597 11:50:37.468367 DQS0 = 0, DQS1 = 0
4598 11:50:37.470607 DQM Delay:
4599 11:50:37.471221 DQM0 = 48, DQM1 = 38
4600 11:50:37.473892 DQ Delay:
4601 11:50:37.477292 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =41
4602 11:50:37.477811 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4603 11:50:37.480663 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4604 11:50:37.483642 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =57
4605 11:50:37.486831
4606 11:50:37.487295
4607 11:50:37.487660 ==
4608 11:50:37.490402 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 11:50:37.494609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 11:50:37.495135 ==
4611 11:50:37.495476
4612 11:50:37.495788
4613 11:50:37.496939 TX Vref Scan disable
4614 11:50:37.497357 == TX Byte 0 ==
4615 11:50:37.503369 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4616 11:50:37.506864 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4617 11:50:37.507435 == TX Byte 1 ==
4618 11:50:37.513382 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4619 11:50:37.517103 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4620 11:50:37.517677 ==
4621 11:50:37.519535 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 11:50:37.523406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 11:50:37.523932 ==
4624 11:50:37.524268
4625 11:50:37.526756
4626 11:50:37.527408 TX Vref Scan disable
4627 11:50:37.530082 == TX Byte 0 ==
4628 11:50:37.533149 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4629 11:50:37.539631 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4630 11:50:37.540191 == TX Byte 1 ==
4631 11:50:37.543249 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4632 11:50:37.549846 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4633 11:50:37.550271
4634 11:50:37.550606 [DATLAT]
4635 11:50:37.550920 Freq=600, CH1 RK0
4636 11:50:37.551226
4637 11:50:37.553094 DATLAT Default: 0x9
4638 11:50:37.553558 0, 0xFFFF, sum = 0
4639 11:50:37.556291 1, 0xFFFF, sum = 0
4640 11:50:37.559731 2, 0xFFFF, sum = 0
4641 11:50:37.560158 3, 0xFFFF, sum = 0
4642 11:50:37.563019 4, 0xFFFF, sum = 0
4643 11:50:37.563443 5, 0xFFFF, sum = 0
4644 11:50:37.566457 6, 0xFFFF, sum = 0
4645 11:50:37.566960 7, 0xFFFF, sum = 0
4646 11:50:37.569504 8, 0x0, sum = 1
4647 11:50:37.570030 9, 0x0, sum = 2
4648 11:50:37.570375 10, 0x0, sum = 3
4649 11:50:37.573357 11, 0x0, sum = 4
4650 11:50:37.573841 best_step = 9
4651 11:50:37.574180
4652 11:50:37.575936 ==
4653 11:50:37.576356 Dram Type= 6, Freq= 0, CH_1, rank 0
4654 11:50:37.583818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 11:50:37.584384 ==
4656 11:50:37.584728 RX Vref Scan: 1
4657 11:50:37.585044
4658 11:50:37.585850 RX Vref 0 -> 0, step: 1
4659 11:50:37.586270
4660 11:50:37.589507 RX Delay -195 -> 252, step: 8
4661 11:50:37.589936
4662 11:50:37.592693 Set Vref, RX VrefLevel [Byte0]: 50
4663 11:50:37.596093 [Byte1]: 51
4664 11:50:37.596613
4665 11:50:37.599549 Final RX Vref Byte 0 = 50 to rank0
4666 11:50:37.602526 Final RX Vref Byte 1 = 51 to rank0
4667 11:50:37.605839 Final RX Vref Byte 0 = 50 to rank1
4668 11:50:37.609676 Final RX Vref Byte 1 = 51 to rank1==
4669 11:50:37.612587 Dram Type= 6, Freq= 0, CH_1, rank 0
4670 11:50:37.616385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 11:50:37.619441 ==
4672 11:50:37.620193 DQS Delay:
4673 11:50:37.620596 DQS0 = 0, DQS1 = 0
4674 11:50:37.622696 DQM Delay:
4675 11:50:37.623260 DQM0 = 47, DQM1 = 36
4676 11:50:37.626059 DQ Delay:
4677 11:50:37.626526 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4678 11:50:37.629333 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4679 11:50:37.632522 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4680 11:50:37.636010 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4681 11:50:37.636577
4682 11:50:37.639422
4683 11:50:37.645657 [DQSOSCAuto] RK0, (LSB)MR18= 0x482d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4684 11:50:37.650032 CH1 RK0: MR19=808, MR18=482D
4685 11:50:37.655163 CH1_RK0: MR19=0x808, MR18=0x482D, DQSOSC=396, MR23=63, INC=167, DEC=111
4686 11:50:37.655718
4687 11:50:37.659584 ----->DramcWriteLeveling(PI) begin...
4688 11:50:37.660162 ==
4689 11:50:37.662528 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 11:50:37.665543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 11:50:37.666107 ==
4692 11:50:37.669396 Write leveling (Byte 0): 28 => 28
4693 11:50:37.672848 Write leveling (Byte 1): 29 => 29
4694 11:50:37.675032 DramcWriteLeveling(PI) end<-----
4695 11:50:37.675506
4696 11:50:37.675884 ==
4697 11:50:37.678403 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 11:50:37.681785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 11:50:37.682262 ==
4700 11:50:37.684995 [Gating] SW mode calibration
4701 11:50:37.692305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4702 11:50:37.698610 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4703 11:50:37.702090 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4704 11:50:37.708305 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4705 11:50:37.711283 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4706 11:50:37.715125 0 9 12 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
4707 11:50:37.721696 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 11:50:37.725159 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 11:50:37.728383 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 11:50:37.734714 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 11:50:37.737918 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 11:50:37.741648 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 11:50:37.748070 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 11:50:37.751629 0 10 12 | B1->B0 | 3b3b 2828 | 0 0 | (1 1) (0 0)
4715 11:50:37.754826 0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
4716 11:50:37.761136 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 11:50:37.764955 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 11:50:37.768267 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 11:50:37.771285 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 11:50:37.777746 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 11:50:37.780934 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 11:50:37.784935 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 11:50:37.790661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 11:50:37.794375 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 11:50:37.798008 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 11:50:37.804398 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 11:50:37.807297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 11:50:37.810581 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 11:50:37.818004 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 11:50:37.820390 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 11:50:37.824303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 11:50:37.830691 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 11:50:37.833939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 11:50:37.838068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 11:50:37.843479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 11:50:37.846860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 11:50:37.850599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 11:50:37.857160 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4739 11:50:37.860065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4740 11:50:37.863594 Total UI for P1: 0, mck2ui 16
4741 11:50:37.866593 best dqsien dly found for B0: ( 0, 13, 12)
4742 11:50:37.870500 Total UI for P1: 0, mck2ui 16
4743 11:50:37.873240 best dqsien dly found for B1: ( 0, 13, 12)
4744 11:50:37.876739 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4745 11:50:37.881052 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4746 11:50:37.881650
4747 11:50:37.883092 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4748 11:50:37.890217 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4749 11:50:37.890765 [Gating] SW calibration Done
4750 11:50:37.891143 ==
4751 11:50:37.892855 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 11:50:37.899729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 11:50:37.900296 ==
4754 11:50:37.900677 RX Vref Scan: 0
4755 11:50:37.901031
4756 11:50:37.902853 RX Vref 0 -> 0, step: 1
4757 11:50:37.903324
4758 11:50:37.906720 RX Delay -230 -> 252, step: 16
4759 11:50:37.909369 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4760 11:50:37.913048 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4761 11:50:37.919880 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4762 11:50:37.922715 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4763 11:50:37.926421 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4764 11:50:37.929580 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4765 11:50:37.932510 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4766 11:50:37.939681 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4767 11:50:37.942275 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4768 11:50:37.946314 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4769 11:50:37.949247 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4770 11:50:37.956274 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4771 11:50:37.958868 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4772 11:50:37.962101 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4773 11:50:37.965899 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4774 11:50:37.972316 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4775 11:50:37.972888 ==
4776 11:50:37.975833 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 11:50:37.978948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 11:50:37.979424 ==
4779 11:50:37.979797 DQS Delay:
4780 11:50:37.982234 DQS0 = 0, DQS1 = 0
4781 11:50:37.982697 DQM Delay:
4782 11:50:37.985672 DQM0 = 43, DQM1 = 35
4783 11:50:37.986139 DQ Delay:
4784 11:50:37.988969 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4785 11:50:37.992371 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =41
4786 11:50:37.995863 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4787 11:50:37.998636 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4788 11:50:37.999116
4789 11:50:37.999615
4790 11:50:38.000073 ==
4791 11:50:38.002102 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 11:50:38.005144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 11:50:38.008379 ==
4794 11:50:38.008868
4795 11:50:38.009347
4796 11:50:38.009847 TX Vref Scan disable
4797 11:50:38.012161 == TX Byte 0 ==
4798 11:50:38.015174 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4799 11:50:38.021502 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4800 11:50:38.022103 == TX Byte 1 ==
4801 11:50:38.025027 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4802 11:50:38.031493 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4803 11:50:38.032058 ==
4804 11:50:38.034875 Dram Type= 6, Freq= 0, CH_1, rank 1
4805 11:50:38.038505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4806 11:50:38.039086 ==
4807 11:50:38.039578
4808 11:50:38.040029
4809 11:50:38.041139 TX Vref Scan disable
4810 11:50:38.045018 == TX Byte 0 ==
4811 11:50:38.048214 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4812 11:50:38.051488 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4813 11:50:38.054714 == TX Byte 1 ==
4814 11:50:38.058126 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4815 11:50:38.061321 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4816 11:50:38.061932
4817 11:50:38.062418 [DATLAT]
4818 11:50:38.064403 Freq=600, CH1 RK1
4819 11:50:38.064881
4820 11:50:38.068637 DATLAT Default: 0x9
4821 11:50:38.069212 0, 0xFFFF, sum = 0
4822 11:50:38.071314 1, 0xFFFF, sum = 0
4823 11:50:38.071892 2, 0xFFFF, sum = 0
4824 11:50:38.075431 3, 0xFFFF, sum = 0
4825 11:50:38.076012 4, 0xFFFF, sum = 0
4826 11:50:38.077977 5, 0xFFFF, sum = 0
4827 11:50:38.078450 6, 0xFFFF, sum = 0
4828 11:50:38.081471 7, 0xFFFF, sum = 0
4829 11:50:38.081955 8, 0x0, sum = 1
4830 11:50:38.084397 9, 0x0, sum = 2
4831 11:50:38.084978 10, 0x0, sum = 3
4832 11:50:38.087956 11, 0x0, sum = 4
4833 11:50:38.088533 best_step = 9
4834 11:50:38.088907
4835 11:50:38.089247 ==
4836 11:50:38.091721 Dram Type= 6, Freq= 0, CH_1, rank 1
4837 11:50:38.094068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4838 11:50:38.094550 ==
4839 11:50:38.097644 RX Vref Scan: 0
4840 11:50:38.098220
4841 11:50:38.101225 RX Vref 0 -> 0, step: 1
4842 11:50:38.101840
4843 11:50:38.102219 RX Delay -195 -> 252, step: 8
4844 11:50:38.108865 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4845 11:50:38.112488 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4846 11:50:38.115522 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4847 11:50:38.118416 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4848 11:50:38.125506 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4849 11:50:38.128815 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4850 11:50:38.131987 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4851 11:50:38.135192 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4852 11:50:38.138787 iDelay=213, Bit 8, Center 28 (-123 ~ 180) 304
4853 11:50:38.145642 iDelay=213, Bit 9, Center 28 (-123 ~ 180) 304
4854 11:50:38.148988 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4855 11:50:38.151781 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4856 11:50:38.155349 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4857 11:50:38.162113 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4858 11:50:38.164982 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4859 11:50:38.168564 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4860 11:50:38.169128 ==
4861 11:50:38.171424 Dram Type= 6, Freq= 0, CH_1, rank 1
4862 11:50:38.178391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4863 11:50:38.178958 ==
4864 11:50:38.179341 DQS Delay:
4865 11:50:38.181579 DQS0 = 0, DQS1 = 0
4866 11:50:38.182139 DQM Delay:
4867 11:50:38.182515 DQM0 = 45, DQM1 = 38
4868 11:50:38.184688 DQ Delay:
4869 11:50:38.188771 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4870 11:50:38.191100 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4871 11:50:38.194756 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =28
4872 11:50:38.198377 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4873 11:50:38.198942
4874 11:50:38.199323
4875 11:50:38.205329 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4876 11:50:38.208104 CH1 RK1: MR19=808, MR18=2C21
4877 11:50:38.213906 CH1_RK1: MR19=0x808, MR18=0x2C21, DQSOSC=401, MR23=63, INC=163, DEC=108
4878 11:50:38.217196 [RxdqsGatingPostProcess] freq 600
4879 11:50:38.224143 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4880 11:50:38.224726 Pre-setting of DQS Precalculation
4881 11:50:38.230385 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4882 11:50:38.237369 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4883 11:50:38.244637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4884 11:50:38.245273
4885 11:50:38.245724
4886 11:50:38.246616 [Calibration Summary] 1200 Mbps
4887 11:50:38.250774 CH 0, Rank 0
4888 11:50:38.251339 SW Impedance : PASS
4889 11:50:38.254358 DUTY Scan : NO K
4890 11:50:38.256803 ZQ Calibration : PASS
4891 11:50:38.257273 Jitter Meter : NO K
4892 11:50:38.261141 CBT Training : PASS
4893 11:50:38.263686 Write leveling : PASS
4894 11:50:38.264248 RX DQS gating : PASS
4895 11:50:38.266855 RX DQ/DQS(RDDQC) : PASS
4896 11:50:38.267325 TX DQ/DQS : PASS
4897 11:50:38.269959 RX DATLAT : PASS
4898 11:50:38.273716 RX DQ/DQS(Engine): PASS
4899 11:50:38.274292 TX OE : NO K
4900 11:50:38.276505 All Pass.
4901 11:50:38.277063
4902 11:50:38.277480 CH 0, Rank 1
4903 11:50:38.280344 SW Impedance : PASS
4904 11:50:38.280909 DUTY Scan : NO K
4905 11:50:38.283152 ZQ Calibration : PASS
4906 11:50:38.286713 Jitter Meter : NO K
4907 11:50:38.287185 CBT Training : PASS
4908 11:50:38.289876 Write leveling : PASS
4909 11:50:38.293138 RX DQS gating : PASS
4910 11:50:38.293747 RX DQ/DQS(RDDQC) : PASS
4911 11:50:38.296715 TX DQ/DQS : PASS
4912 11:50:38.299455 RX DATLAT : PASS
4913 11:50:38.299927 RX DQ/DQS(Engine): PASS
4914 11:50:38.303117 TX OE : NO K
4915 11:50:38.303688 All Pass.
4916 11:50:38.304067
4917 11:50:38.306128 CH 1, Rank 0
4918 11:50:38.306598 SW Impedance : PASS
4919 11:50:38.309743 DUTY Scan : NO K
4920 11:50:38.313360 ZQ Calibration : PASS
4921 11:50:38.313976 Jitter Meter : NO K
4922 11:50:38.315960 CBT Training : PASS
4923 11:50:38.319870 Write leveling : PASS
4924 11:50:38.320354 RX DQS gating : PASS
4925 11:50:38.322910 RX DQ/DQS(RDDQC) : PASS
4926 11:50:38.326190 TX DQ/DQS : PASS
4927 11:50:38.326723 RX DATLAT : PASS
4928 11:50:38.329099 RX DQ/DQS(Engine): PASS
4929 11:50:38.332559 TX OE : NO K
4930 11:50:38.332992 All Pass.
4931 11:50:38.333333
4932 11:50:38.333777 CH 1, Rank 1
4933 11:50:38.335923 SW Impedance : PASS
4934 11:50:38.339083 DUTY Scan : NO K
4935 11:50:38.339605 ZQ Calibration : PASS
4936 11:50:38.342777 Jitter Meter : NO K
4937 11:50:38.346001 CBT Training : PASS
4938 11:50:38.346430 Write leveling : PASS
4939 11:50:38.348914 RX DQS gating : PASS
4940 11:50:38.349342 RX DQ/DQS(RDDQC) : PASS
4941 11:50:38.352523 TX DQ/DQS : PASS
4942 11:50:38.356017 RX DATLAT : PASS
4943 11:50:38.356463 RX DQ/DQS(Engine): PASS
4944 11:50:38.358817 TX OE : NO K
4945 11:50:38.359247 All Pass.
4946 11:50:38.359587
4947 11:50:38.362510 DramC Write-DBI off
4948 11:50:38.365760 PER_BANK_REFRESH: Hybrid Mode
4949 11:50:38.366280 TX_TRACKING: ON
4950 11:50:38.375861 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4951 11:50:38.378713 [FAST_K] Save calibration result to emmc
4952 11:50:38.381706 dramc_set_vcore_voltage set vcore to 662500
4953 11:50:38.385013 Read voltage for 933, 3
4954 11:50:38.385595 Vio18 = 0
4955 11:50:38.388390 Vcore = 662500
4956 11:50:38.388969 Vdram = 0
4957 11:50:38.389345 Vddq = 0
4958 11:50:38.389745 Vmddr = 0
4959 11:50:38.396209 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4960 11:50:38.401485 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4961 11:50:38.401955 MEM_TYPE=3, freq_sel=17
4962 11:50:38.405092 sv_algorithm_assistance_LP4_1600
4963 11:50:38.411334 ============ PULL DRAM RESETB DOWN ============
4964 11:50:38.414539 ========== PULL DRAM RESETB DOWN end =========
4965 11:50:38.417901 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4966 11:50:38.421264 ===================================
4967 11:50:38.424515 LPDDR4 DRAM CONFIGURATION
4968 11:50:38.428041 ===================================
4969 11:50:38.428604 EX_ROW_EN[0] = 0x0
4970 11:50:38.431047 EX_ROW_EN[1] = 0x0
4971 11:50:38.435219 LP4Y_EN = 0x0
4972 11:50:38.435786 WORK_FSP = 0x0
4973 11:50:38.437880 WL = 0x3
4974 11:50:38.438365 RL = 0x3
4975 11:50:38.441693 BL = 0x2
4976 11:50:38.442251 RPST = 0x0
4977 11:50:38.444466 RD_PRE = 0x0
4978 11:50:38.445033 WR_PRE = 0x1
4979 11:50:38.447907 WR_PST = 0x0
4980 11:50:38.448469 DBI_WR = 0x0
4981 11:50:38.450872 DBI_RD = 0x0
4982 11:50:38.451343 OTF = 0x1
4983 11:50:38.454236 ===================================
4984 11:50:38.457311 ===================================
4985 11:50:38.460835 ANA top config
4986 11:50:38.463972 ===================================
4987 11:50:38.467016 DLL_ASYNC_EN = 0
4988 11:50:38.467488 ALL_SLAVE_EN = 1
4989 11:50:38.471116 NEW_RANK_MODE = 1
4990 11:50:38.473921 DLL_IDLE_MODE = 1
4991 11:50:38.477518 LP45_APHY_COMB_EN = 1
4992 11:50:38.478089 TX_ODT_DIS = 1
4993 11:50:38.480465 NEW_8X_MODE = 1
4994 11:50:38.483933 ===================================
4995 11:50:38.487620 ===================================
4996 11:50:38.490493 data_rate = 1866
4997 11:50:38.493590 CKR = 1
4998 11:50:38.497216 DQ_P2S_RATIO = 8
4999 11:50:38.500456 ===================================
5000 11:50:38.503883 CA_P2S_RATIO = 8
5001 11:50:38.504358 DQ_CA_OPEN = 0
5002 11:50:38.506822 DQ_SEMI_OPEN = 0
5003 11:50:38.510367 CA_SEMI_OPEN = 0
5004 11:50:38.514045 CA_FULL_RATE = 0
5005 11:50:38.516688 DQ_CKDIV4_EN = 1
5006 11:50:38.520244 CA_CKDIV4_EN = 1
5007 11:50:38.520809 CA_PREDIV_EN = 0
5008 11:50:38.523713 PH8_DLY = 0
5009 11:50:38.526827 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5010 11:50:38.531052 DQ_AAMCK_DIV = 4
5011 11:50:38.533176 CA_AAMCK_DIV = 4
5012 11:50:38.537152 CA_ADMCK_DIV = 4
5013 11:50:38.537779 DQ_TRACK_CA_EN = 0
5014 11:50:38.540058 CA_PICK = 933
5015 11:50:38.543339 CA_MCKIO = 933
5016 11:50:38.546560 MCKIO_SEMI = 0
5017 11:50:38.550334 PLL_FREQ = 3732
5018 11:50:38.553368 DQ_UI_PI_RATIO = 32
5019 11:50:38.556639 CA_UI_PI_RATIO = 0
5020 11:50:38.559327 ===================================
5021 11:50:38.562710 ===================================
5022 11:50:38.563193 memory_type:LPDDR4
5023 11:50:38.565988 GP_NUM : 10
5024 11:50:38.569506 SRAM_EN : 1
5025 11:50:38.569941 MD32_EN : 0
5026 11:50:38.572439 ===================================
5027 11:50:38.576019 [ANA_INIT] >>>>>>>>>>>>>>
5028 11:50:38.579437 <<<<<< [CONFIGURE PHASE]: ANA_TX
5029 11:50:38.582655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5030 11:50:38.586007 ===================================
5031 11:50:38.589883 data_rate = 1866,PCW = 0X8f00
5032 11:50:38.592201 ===================================
5033 11:50:38.595810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5034 11:50:38.602097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5035 11:50:38.605330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5036 11:50:38.612160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5037 11:50:38.615381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5038 11:50:38.618360 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5039 11:50:38.618818 [ANA_INIT] flow start
5040 11:50:38.621748 [ANA_INIT] PLL >>>>>>>>
5041 11:50:38.625391 [ANA_INIT] PLL <<<<<<<<
5042 11:50:38.625836 [ANA_INIT] MIDPI >>>>>>>>
5043 11:50:38.628440 [ANA_INIT] MIDPI <<<<<<<<
5044 11:50:38.631810 [ANA_INIT] DLL >>>>>>>>
5045 11:50:38.632231 [ANA_INIT] flow end
5046 11:50:38.638602 ============ LP4 DIFF to SE enter ============
5047 11:50:38.642126 ============ LP4 DIFF to SE exit ============
5048 11:50:38.645491 [ANA_INIT] <<<<<<<<<<<<<
5049 11:50:38.648389 [Flow] Enable top DCM control >>>>>
5050 11:50:38.651887 [Flow] Enable top DCM control <<<<<
5051 11:50:38.652315 Enable DLL master slave shuffle
5052 11:50:38.658153 ==============================================================
5053 11:50:38.661643 Gating Mode config
5054 11:50:38.664737 ==============================================================
5055 11:50:38.668249 Config description:
5056 11:50:38.677895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5057 11:50:38.685018 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5058 11:50:38.688107 SELPH_MODE 0: By rank 1: By Phase
5059 11:50:38.694662 ==============================================================
5060 11:50:38.698059 GAT_TRACK_EN = 1
5061 11:50:38.701230 RX_GATING_MODE = 2
5062 11:50:38.704409 RX_GATING_TRACK_MODE = 2
5063 11:50:38.707729 SELPH_MODE = 1
5064 11:50:38.711356 PICG_EARLY_EN = 1
5065 11:50:38.714155 VALID_LAT_VALUE = 1
5066 11:50:38.717767 ==============================================================
5067 11:50:38.721223 Enter into Gating configuration >>>>
5068 11:50:38.724548 Exit from Gating configuration <<<<
5069 11:50:38.727203 Enter into DVFS_PRE_config >>>>>
5070 11:50:38.740821 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5071 11:50:38.741389 Exit from DVFS_PRE_config <<<<<
5072 11:50:38.743918 Enter into PICG configuration >>>>
5073 11:50:38.747964 Exit from PICG configuration <<<<
5074 11:50:38.750542 [RX_INPUT] configuration >>>>>
5075 11:50:38.753802 [RX_INPUT] configuration <<<<<
5076 11:50:38.760495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5077 11:50:38.764052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5078 11:50:38.770322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5079 11:50:38.777064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5080 11:50:38.783574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5081 11:50:38.789935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5082 11:50:38.794015 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5083 11:50:38.796993 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5084 11:50:38.799999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5085 11:50:38.806701 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5086 11:50:38.810245 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5087 11:50:38.812995 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5088 11:50:38.816827 ===================================
5089 11:50:38.820122 LPDDR4 DRAM CONFIGURATION
5090 11:50:38.824018 ===================================
5091 11:50:38.826770 EX_ROW_EN[0] = 0x0
5092 11:50:38.827373 EX_ROW_EN[1] = 0x0
5093 11:50:38.830038 LP4Y_EN = 0x0
5094 11:50:38.830503 WORK_FSP = 0x0
5095 11:50:38.833286 WL = 0x3
5096 11:50:38.833819 RL = 0x3
5097 11:50:38.836245 BL = 0x2
5098 11:50:38.836713 RPST = 0x0
5099 11:50:38.839816 RD_PRE = 0x0
5100 11:50:38.840379 WR_PRE = 0x1
5101 11:50:38.842982 WR_PST = 0x0
5102 11:50:38.843542 DBI_WR = 0x0
5103 11:50:38.846749 DBI_RD = 0x0
5104 11:50:38.847314 OTF = 0x1
5105 11:50:38.849287 ===================================
5106 11:50:38.856215 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5107 11:50:38.859964 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5108 11:50:38.863487 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5109 11:50:38.866401 ===================================
5110 11:50:38.869489 LPDDR4 DRAM CONFIGURATION
5111 11:50:38.873111 ===================================
5112 11:50:38.875646 EX_ROW_EN[0] = 0x10
5113 11:50:38.876115 EX_ROW_EN[1] = 0x0
5114 11:50:38.879000 LP4Y_EN = 0x0
5115 11:50:38.879467 WORK_FSP = 0x0
5116 11:50:38.882584 WL = 0x3
5117 11:50:38.883158 RL = 0x3
5118 11:50:38.885661 BL = 0x2
5119 11:50:38.886134 RPST = 0x0
5120 11:50:38.889595 RD_PRE = 0x0
5121 11:50:38.890184 WR_PRE = 0x1
5122 11:50:38.892398 WR_PST = 0x0
5123 11:50:38.892958 DBI_WR = 0x0
5124 11:50:38.895829 DBI_RD = 0x0
5125 11:50:38.899078 OTF = 0x1
5126 11:50:38.902384 ===================================
5127 11:50:38.905495 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5128 11:50:38.910689 nWR fixed to 30
5129 11:50:38.913943 [ModeRegInit_LP4] CH0 RK0
5130 11:50:38.914411 [ModeRegInit_LP4] CH0 RK1
5131 11:50:38.917514 [ModeRegInit_LP4] CH1 RK0
5132 11:50:38.920373 [ModeRegInit_LP4] CH1 RK1
5133 11:50:38.920838 match AC timing 9
5134 11:50:38.927031 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5135 11:50:38.931016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5136 11:50:38.934098 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5137 11:50:38.940420 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5138 11:50:38.943734 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5139 11:50:38.944304 ==
5140 11:50:38.946907 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 11:50:38.950047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 11:50:38.950521 ==
5143 11:50:38.957112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5144 11:50:38.963761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5145 11:50:38.966976 [CA 0] Center 37 (7~68) winsize 62
5146 11:50:38.970098 [CA 1] Center 37 (7~68) winsize 62
5147 11:50:38.973362 [CA 2] Center 34 (4~65) winsize 62
5148 11:50:38.976440 [CA 3] Center 35 (5~65) winsize 61
5149 11:50:38.979691 [CA 4] Center 33 (3~64) winsize 62
5150 11:50:38.983529 [CA 5] Center 33 (3~64) winsize 62
5151 11:50:38.983995
5152 11:50:38.986415 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5153 11:50:38.986884
5154 11:50:38.990090 [CATrainingPosCal] consider 1 rank data
5155 11:50:38.993080 u2DelayCellTimex100 = 270/100 ps
5156 11:50:38.996716 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5157 11:50:39.000056 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5158 11:50:39.002907 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5159 11:50:39.006404 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5160 11:50:39.013345 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 11:50:39.016407 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 11:50:39.017013
5163 11:50:39.019747 CA PerBit enable=1, Macro0, CA PI delay=33
5164 11:50:39.020217
5165 11:50:39.023071 [CBTSetCACLKResult] CA Dly = 33
5166 11:50:39.023645 CS Dly: 7 (0~38)
5167 11:50:39.024018 ==
5168 11:50:39.027033 Dram Type= 6, Freq= 0, CH_0, rank 1
5169 11:50:39.033252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 11:50:39.033922 ==
5171 11:50:39.036352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5172 11:50:39.043074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5173 11:50:39.046265 [CA 0] Center 37 (7~68) winsize 62
5174 11:50:39.049982 [CA 1] Center 37 (7~68) winsize 62
5175 11:50:39.052736 [CA 2] Center 34 (4~65) winsize 62
5176 11:50:39.056104 [CA 3] Center 34 (4~65) winsize 62
5177 11:50:39.059134 [CA 4] Center 33 (3~64) winsize 62
5178 11:50:39.062558 [CA 5] Center 33 (3~63) winsize 61
5179 11:50:39.063154
5180 11:50:39.065797 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5181 11:50:39.066262
5182 11:50:39.069813 [CATrainingPosCal] consider 2 rank data
5183 11:50:39.073101 u2DelayCellTimex100 = 270/100 ps
5184 11:50:39.075548 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5185 11:50:39.082673 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5186 11:50:39.085317 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5187 11:50:39.089223 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5188 11:50:39.092255 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5189 11:50:39.095842 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5190 11:50:39.096407
5191 11:50:39.098902 CA PerBit enable=1, Macro0, CA PI delay=33
5192 11:50:39.099468
5193 11:50:39.102227 [CBTSetCACLKResult] CA Dly = 33
5194 11:50:39.105669 CS Dly: 7 (0~39)
5195 11:50:39.106238
5196 11:50:39.109002 ----->DramcWriteLeveling(PI) begin...
5197 11:50:39.109619 ==
5198 11:50:39.112170 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 11:50:39.114968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 11:50:39.115467 ==
5201 11:50:39.119521 Write leveling (Byte 0): 33 => 33
5202 11:50:39.121600 Write leveling (Byte 1): 29 => 29
5203 11:50:39.125344 DramcWriteLeveling(PI) end<-----
5204 11:50:39.125964
5205 11:50:39.126338 ==
5206 11:50:39.128763 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 11:50:39.131979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 11:50:39.132521 ==
5209 11:50:39.134967 [Gating] SW mode calibration
5210 11:50:39.142127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5211 11:50:39.148278 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5212 11:50:39.151518 0 14 0 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
5213 11:50:39.155197 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5214 11:50:39.162280 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5215 11:50:39.165079 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5216 11:50:39.168341 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 11:50:39.174718 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 11:50:39.178172 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 11:50:39.182013 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
5220 11:50:39.187776 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5221 11:50:39.191478 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5222 11:50:39.194303 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5223 11:50:39.200987 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 11:50:39.204468 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 11:50:39.207349 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 11:50:39.214136 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 11:50:39.217272 0 15 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5228 11:50:39.220505 1 0 0 | B1->B0 | 3131 4444 | 1 0 | (0 0) (0 0)
5229 11:50:39.227652 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5230 11:50:39.230803 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5231 11:50:39.233891 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 11:50:39.241032 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 11:50:39.244257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 11:50:39.247260 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 11:50:39.254023 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5236 11:50:39.256809 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5237 11:50:39.263260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5238 11:50:39.266587 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 11:50:39.269659 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 11:50:39.273467 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 11:50:39.279813 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 11:50:39.283878 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 11:50:39.286329 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 11:50:39.293056 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 11:50:39.296542 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 11:50:39.302748 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 11:50:39.306295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 11:50:39.309883 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 11:50:39.316086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 11:50:39.319511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5251 11:50:39.322503 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5252 11:50:39.329253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5253 11:50:39.329904 Total UI for P1: 0, mck2ui 16
5254 11:50:39.332242 best dqsien dly found for B0: ( 1, 2, 26)
5255 11:50:39.339478 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5256 11:50:39.342158 Total UI for P1: 0, mck2ui 16
5257 11:50:39.345662 best dqsien dly found for B1: ( 1, 3, 0)
5258 11:50:39.349185 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5259 11:50:39.352003 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5260 11:50:39.352586
5261 11:50:39.355098 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5262 11:50:39.358574 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5263 11:50:39.362218 [Gating] SW calibration Done
5264 11:50:39.362801 ==
5265 11:50:39.365228 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:50:39.369001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:50:39.369638 ==
5268 11:50:39.371938 RX Vref Scan: 0
5269 11:50:39.372423
5270 11:50:39.375553 RX Vref 0 -> 0, step: 1
5271 11:50:39.376138
5272 11:50:39.376629 RX Delay -80 -> 252, step: 8
5273 11:50:39.381639 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5274 11:50:39.385173 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5275 11:50:39.388394 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5276 11:50:39.391380 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5277 11:50:39.394918 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5278 11:50:39.401635 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5279 11:50:39.404796 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5280 11:50:39.407866 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5281 11:50:39.411909 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5282 11:50:39.414844 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5283 11:50:39.421032 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5284 11:50:39.424190 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5285 11:50:39.428524 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5286 11:50:39.431409 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5287 11:50:39.434219 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5288 11:50:39.440832 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5289 11:50:39.441452 ==
5290 11:50:39.444268 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 11:50:39.447305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 11:50:39.447885 ==
5293 11:50:39.448376 DQS Delay:
5294 11:50:39.451004 DQS0 = 0, DQS1 = 0
5295 11:50:39.451487 DQM Delay:
5296 11:50:39.453975 DQM0 = 97, DQM1 = 85
5297 11:50:39.454457 DQ Delay:
5298 11:50:39.457830 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5299 11:50:39.460848 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5300 11:50:39.464176 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5301 11:50:39.467609 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5302 11:50:39.468185
5303 11:50:39.468675
5304 11:50:39.469130 ==
5305 11:50:39.470633 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 11:50:39.474021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 11:50:39.477170 ==
5308 11:50:39.477815
5309 11:50:39.478324
5310 11:50:39.478779 TX Vref Scan disable
5311 11:50:39.480370 == TX Byte 0 ==
5312 11:50:39.484251 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5313 11:50:39.487001 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5314 11:50:39.490242 == TX Byte 1 ==
5315 11:50:39.493638 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5316 11:50:39.496933 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5317 11:50:39.500761 ==
5318 11:50:39.503600 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 11:50:39.506813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 11:50:39.507403 ==
5321 11:50:39.507900
5322 11:50:39.508355
5323 11:50:39.510300 TX Vref Scan disable
5324 11:50:39.510783 == TX Byte 0 ==
5325 11:50:39.516512 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5326 11:50:39.520002 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5327 11:50:39.520578 == TX Byte 1 ==
5328 11:50:39.526913 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5329 11:50:39.530027 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5330 11:50:39.530513
5331 11:50:39.530995 [DATLAT]
5332 11:50:39.533012 Freq=933, CH0 RK0
5333 11:50:39.533669
5334 11:50:39.534154 DATLAT Default: 0xd
5335 11:50:39.536235 0, 0xFFFF, sum = 0
5336 11:50:39.536725 1, 0xFFFF, sum = 0
5337 11:50:39.539497 2, 0xFFFF, sum = 0
5338 11:50:39.542675 3, 0xFFFF, sum = 0
5339 11:50:39.543166 4, 0xFFFF, sum = 0
5340 11:50:39.546801 5, 0xFFFF, sum = 0
5341 11:50:39.547242 6, 0xFFFF, sum = 0
5342 11:50:39.549647 7, 0xFFFF, sum = 0
5343 11:50:39.550191 8, 0xFFFF, sum = 0
5344 11:50:39.553002 9, 0xFFFF, sum = 0
5345 11:50:39.553602 10, 0x0, sum = 1
5346 11:50:39.556050 11, 0x0, sum = 2
5347 11:50:39.556491 12, 0x0, sum = 3
5348 11:50:39.559459 13, 0x0, sum = 4
5349 11:50:39.559987 best_step = 11
5350 11:50:39.560335
5351 11:50:39.560654 ==
5352 11:50:39.563471 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 11:50:39.566381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 11:50:39.566813 ==
5355 11:50:39.569197 RX Vref Scan: 1
5356 11:50:39.569657
5357 11:50:39.572320 RX Vref 0 -> 0, step: 1
5358 11:50:39.572744
5359 11:50:39.573083 RX Delay -69 -> 252, step: 4
5360 11:50:39.573452
5361 11:50:39.575848 Set Vref, RX VrefLevel [Byte0]: 62
5362 11:50:39.579070 [Byte1]: 50
5363 11:50:39.584034
5364 11:50:39.584456 Final RX Vref Byte 0 = 62 to rank0
5365 11:50:39.587075 Final RX Vref Byte 1 = 50 to rank0
5366 11:50:39.590602 Final RX Vref Byte 0 = 62 to rank1
5367 11:50:39.593913 Final RX Vref Byte 1 = 50 to rank1==
5368 11:50:39.597727 Dram Type= 6, Freq= 0, CH_0, rank 0
5369 11:50:39.603902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:50:39.604224 ==
5371 11:50:39.604416 DQS Delay:
5372 11:50:39.607133 DQS0 = 0, DQS1 = 0
5373 11:50:39.607452 DQM Delay:
5374 11:50:39.607640 DQM0 = 97, DQM1 = 86
5375 11:50:39.610469 DQ Delay:
5376 11:50:39.613527 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5377 11:50:39.616952 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5378 11:50:39.620337 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5379 11:50:39.623084 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =94
5380 11:50:39.623307
5381 11:50:39.623486
5382 11:50:39.630015 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5383 11:50:39.633441 CH0 RK0: MR19=505, MR18=2A11
5384 11:50:39.640109 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5385 11:50:39.640665
5386 11:50:39.643080 ----->DramcWriteLeveling(PI) begin...
5387 11:50:39.643547 ==
5388 11:50:39.646948 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 11:50:39.650104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 11:50:39.650663 ==
5391 11:50:39.653441 Write leveling (Byte 0): 33 => 33
5392 11:50:39.656615 Write leveling (Byte 1): 33 => 33
5393 11:50:39.660459 DramcWriteLeveling(PI) end<-----
5394 11:50:39.660874
5395 11:50:39.661203 ==
5396 11:50:39.663317 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:50:39.666413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:50:39.669966 ==
5399 11:50:39.670381 [Gating] SW mode calibration
5400 11:50:39.679714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5401 11:50:39.683057 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5402 11:50:39.686283 0 14 0 | B1->B0 | 2626 3030 | 1 1 | (1 1) (1 1)
5403 11:50:39.693280 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5404 11:50:39.696706 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5405 11:50:39.699222 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 11:50:39.706242 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 11:50:39.709447 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 11:50:39.712764 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 11:50:39.719622 0 14 28 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
5410 11:50:39.722404 0 15 0 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
5411 11:50:39.725958 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5412 11:50:39.732784 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5413 11:50:39.735807 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 11:50:39.739490 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 11:50:39.745959 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 11:50:39.749593 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 11:50:39.751902 0 15 28 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
5418 11:50:39.758488 1 0 0 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5419 11:50:39.761763 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5420 11:50:39.765660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 11:50:39.771840 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 11:50:39.775013 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 11:50:39.778424 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 11:50:39.784960 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 11:50:39.788661 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 11:50:39.794927 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5427 11:50:39.798360 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 11:50:39.801796 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 11:50:39.808170 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 11:50:39.811656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 11:50:39.815270 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 11:50:39.820923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 11:50:39.824989 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 11:50:39.828324 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 11:50:39.834610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 11:50:39.837608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 11:50:39.840421 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 11:50:39.847244 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 11:50:39.850228 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 11:50:39.853836 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5441 11:50:39.860181 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 11:50:39.864131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5443 11:50:39.866811 Total UI for P1: 0, mck2ui 16
5444 11:50:39.870693 best dqsien dly found for B0: ( 1, 2, 30)
5445 11:50:39.873782 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 11:50:39.876495 Total UI for P1: 0, mck2ui 16
5447 11:50:39.879981 best dqsien dly found for B1: ( 1, 3, 0)
5448 11:50:39.882953 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5449 11:50:39.886460 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5450 11:50:39.886926
5451 11:50:39.892940 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5452 11:50:39.896311 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5453 11:50:39.900050 [Gating] SW calibration Done
5454 11:50:39.900627 ==
5455 11:50:39.902573 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:50:39.906637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:50:39.907215 ==
5458 11:50:39.907594 RX Vref Scan: 0
5459 11:50:39.907944
5460 11:50:39.909464 RX Vref 0 -> 0, step: 1
5461 11:50:39.909938
5462 11:50:39.913162 RX Delay -80 -> 252, step: 8
5463 11:50:39.916278 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5464 11:50:39.919164 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5465 11:50:39.926071 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5466 11:50:39.929369 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5467 11:50:39.932826 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5468 11:50:39.936363 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5469 11:50:39.939309 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5470 11:50:39.942971 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5471 11:50:39.949210 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5472 11:50:39.952643 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5473 11:50:39.955960 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5474 11:50:39.959049 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5475 11:50:39.962334 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5476 11:50:39.968803 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5477 11:50:39.972876 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5478 11:50:39.975193 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5479 11:50:39.975682 ==
5480 11:50:39.979612 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 11:50:39.982311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 11:50:39.982813 ==
5483 11:50:39.985344 DQS Delay:
5484 11:50:39.985858 DQS0 = 0, DQS1 = 0
5485 11:50:39.988336 DQM Delay:
5486 11:50:39.988879 DQM0 = 96, DQM1 = 88
5487 11:50:39.989519 DQ Delay:
5488 11:50:39.991734 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5489 11:50:39.995215 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5490 11:50:39.998492 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5491 11:50:40.001584 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5492 11:50:40.002018
5493 11:50:40.004808
5494 11:50:40.005234 ==
5495 11:50:40.008581 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 11:50:40.011939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 11:50:40.012467 ==
5498 11:50:40.012817
5499 11:50:40.013286
5500 11:50:40.014897 TX Vref Scan disable
5501 11:50:40.015392 == TX Byte 0 ==
5502 11:50:40.021707 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5503 11:50:40.024952 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5504 11:50:40.025539 == TX Byte 1 ==
5505 11:50:40.032061 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5506 11:50:40.035412 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5507 11:50:40.035945 ==
5508 11:50:40.038309 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 11:50:40.041402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 11:50:40.042033 ==
5511 11:50:40.042385
5512 11:50:40.042701
5513 11:50:40.045145 TX Vref Scan disable
5514 11:50:40.048071 == TX Byte 0 ==
5515 11:50:40.051293 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5516 11:50:40.055459 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5517 11:50:40.057997 == TX Byte 1 ==
5518 11:50:40.061355 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5519 11:50:40.064843 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5520 11:50:40.065373
5521 11:50:40.067976 [DATLAT]
5522 11:50:40.068509 Freq=933, CH0 RK1
5523 11:50:40.068855
5524 11:50:40.071281 DATLAT Default: 0xb
5525 11:50:40.071836 0, 0xFFFF, sum = 0
5526 11:50:40.074340 1, 0xFFFF, sum = 0
5527 11:50:40.074775 2, 0xFFFF, sum = 0
5528 11:50:40.077616 3, 0xFFFF, sum = 0
5529 11:50:40.078053 4, 0xFFFF, sum = 0
5530 11:50:40.080876 5, 0xFFFF, sum = 0
5531 11:50:40.081476 6, 0xFFFF, sum = 0
5532 11:50:40.083965 7, 0xFFFF, sum = 0
5533 11:50:40.084504 8, 0xFFFF, sum = 0
5534 11:50:40.087241 9, 0xFFFF, sum = 0
5535 11:50:40.087677 10, 0x0, sum = 1
5536 11:50:40.090888 11, 0x0, sum = 2
5537 11:50:40.091356 12, 0x0, sum = 3
5538 11:50:40.094193 13, 0x0, sum = 4
5539 11:50:40.094622 best_step = 11
5540 11:50:40.094961
5541 11:50:40.095279 ==
5542 11:50:40.097594 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 11:50:40.104210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 11:50:40.104748 ==
5545 11:50:40.105096 RX Vref Scan: 0
5546 11:50:40.105460
5547 11:50:40.107518 RX Vref 0 -> 0, step: 1
5548 11:50:40.108047
5549 11:50:40.110577 RX Delay -61 -> 252, step: 4
5550 11:50:40.113982 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5551 11:50:40.120186 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5552 11:50:40.123889 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5553 11:50:40.126821 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5554 11:50:40.130440 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5555 11:50:40.134665 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5556 11:50:40.137783 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5557 11:50:40.143873 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5558 11:50:40.147048 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5559 11:50:40.150842 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5560 11:50:40.154047 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5561 11:50:40.157776 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5562 11:50:40.163643 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5563 11:50:40.166852 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5564 11:50:40.169940 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5565 11:50:40.173506 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5566 11:50:40.174067 ==
5567 11:50:40.177348 Dram Type= 6, Freq= 0, CH_0, rank 1
5568 11:50:40.182849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 11:50:40.183410 ==
5570 11:50:40.183791 DQS Delay:
5571 11:50:40.186342 DQS0 = 0, DQS1 = 0
5572 11:50:40.186814 DQM Delay:
5573 11:50:40.187191 DQM0 = 95, DQM1 = 86
5574 11:50:40.190236 DQ Delay:
5575 11:50:40.193020 DQ0 =92, DQ1 =98, DQ2 =88, DQ3 =92
5576 11:50:40.196522 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5577 11:50:40.199543 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5578 11:50:40.203605 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =92
5579 11:50:40.204183
5580 11:50:40.204560
5581 11:50:40.210071 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5582 11:50:40.213197 CH0 RK1: MR19=504, MR18=26F6
5583 11:50:40.219528 CH0_RK1: MR19=0x504, MR18=0x26F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5584 11:50:40.222864 [RxdqsGatingPostProcess] freq 933
5585 11:50:40.225993 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5586 11:50:40.229982 best DQS0 dly(2T, 0.5T) = (0, 10)
5587 11:50:40.232762 best DQS1 dly(2T, 0.5T) = (0, 11)
5588 11:50:40.236219 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5589 11:50:40.239543 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5590 11:50:40.242778 best DQS0 dly(2T, 0.5T) = (0, 10)
5591 11:50:40.246645 best DQS1 dly(2T, 0.5T) = (0, 11)
5592 11:50:40.249456 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5593 11:50:40.252878 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5594 11:50:40.256377 Pre-setting of DQS Precalculation
5595 11:50:40.259849 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5596 11:50:40.260429 ==
5597 11:50:40.263642 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 11:50:40.269805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 11:50:40.270385 ==
5600 11:50:40.272820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 11:50:40.279622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 11:50:40.282819 [CA 0] Center 37 (7~67) winsize 61
5603 11:50:40.285858 [CA 1] Center 37 (6~68) winsize 63
5604 11:50:40.289533 [CA 2] Center 34 (4~65) winsize 62
5605 11:50:40.292445 [CA 3] Center 33 (3~64) winsize 62
5606 11:50:40.295976 [CA 4] Center 34 (4~64) winsize 61
5607 11:50:40.299129 [CA 5] Center 33 (3~64) winsize 62
5608 11:50:40.299593
5609 11:50:40.302965 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 11:50:40.303551
5611 11:50:40.306222 [CATrainingPosCal] consider 1 rank data
5612 11:50:40.308947 u2DelayCellTimex100 = 270/100 ps
5613 11:50:40.312338 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5614 11:50:40.319652 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5615 11:50:40.322179 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5616 11:50:40.325987 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5617 11:50:40.329178 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 11:50:40.332183 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 11:50:40.332645
5620 11:50:40.335541 CA PerBit enable=1, Macro0, CA PI delay=33
5621 11:50:40.335965
5622 11:50:40.338679 [CBTSetCACLKResult] CA Dly = 33
5623 11:50:40.342086 CS Dly: 6 (0~37)
5624 11:50:40.342600 ==
5625 11:50:40.346234 Dram Type= 6, Freq= 0, CH_1, rank 1
5626 11:50:40.348896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 11:50:40.349506 ==
5628 11:50:40.354942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5629 11:50:40.358135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5630 11:50:40.362918 [CA 0] Center 37 (7~67) winsize 61
5631 11:50:40.365736 [CA 1] Center 37 (7~67) winsize 61
5632 11:50:40.369526 [CA 2] Center 34 (4~65) winsize 62
5633 11:50:40.372911 [CA 3] Center 34 (3~65) winsize 63
5634 11:50:40.376292 [CA 4] Center 34 (4~65) winsize 62
5635 11:50:40.378612 [CA 5] Center 33 (3~64) winsize 62
5636 11:50:40.379086
5637 11:50:40.382280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5638 11:50:40.382898
5639 11:50:40.385877 [CATrainingPosCal] consider 2 rank data
5640 11:50:40.389015 u2DelayCellTimex100 = 270/100 ps
5641 11:50:40.392350 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5642 11:50:40.399163 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5643 11:50:40.402599 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5644 11:50:40.405306 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5645 11:50:40.408977 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5646 11:50:40.412060 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 11:50:40.412634
5648 11:50:40.415548 CA PerBit enable=1, Macro0, CA PI delay=33
5649 11:50:40.416112
5650 11:50:40.418891 [CBTSetCACLKResult] CA Dly = 33
5651 11:50:40.421956 CS Dly: 7 (0~39)
5652 11:50:40.422519
5653 11:50:40.425086 ----->DramcWriteLeveling(PI) begin...
5654 11:50:40.425745 ==
5655 11:50:40.428198 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 11:50:40.432389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 11:50:40.432955 ==
5658 11:50:40.435178 Write leveling (Byte 0): 28 => 28
5659 11:50:40.438614 Write leveling (Byte 1): 27 => 27
5660 11:50:40.442116 DramcWriteLeveling(PI) end<-----
5661 11:50:40.442680
5662 11:50:40.443050 ==
5663 11:50:40.445103 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 11:50:40.448612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 11:50:40.449178 ==
5666 11:50:40.451868 [Gating] SW mode calibration
5667 11:50:40.458693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5668 11:50:40.464990 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5669 11:50:40.468494 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5670 11:50:40.474364 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5671 11:50:40.477374 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 11:50:40.480565 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 11:50:40.487119 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 11:50:40.490444 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5675 11:50:40.494460 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5676 11:50:40.501081 0 14 28 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
5677 11:50:40.504360 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 11:50:40.507687 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5679 11:50:40.513685 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 11:50:40.517031 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 11:50:40.520209 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 11:50:40.526825 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 11:50:40.530707 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 11:50:40.533808 0 15 28 | B1->B0 | 3333 3838 | 1 0 | (1 1) (1 1)
5685 11:50:40.539828 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 11:50:40.543956 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 11:50:40.546810 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 11:50:40.553216 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 11:50:40.556960 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 11:50:40.560581 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5691 11:50:40.566703 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5692 11:50:40.569799 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 11:50:40.573257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 11:50:40.580196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 11:50:40.583390 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 11:50:40.586605 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 11:50:40.593049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 11:50:40.596318 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:50:40.600449 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 11:50:40.606131 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 11:50:40.609457 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 11:50:40.612598 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 11:50:40.619419 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 11:50:40.622584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 11:50:40.625906 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 11:50:40.632904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 11:50:40.636320 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5708 11:50:40.639820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5709 11:50:40.642754 Total UI for P1: 0, mck2ui 16
5710 11:50:40.646146 best dqsien dly found for B0: ( 1, 2, 24)
5711 11:50:40.652424 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5712 11:50:40.653003 Total UI for P1: 0, mck2ui 16
5713 11:50:40.656692 best dqsien dly found for B1: ( 1, 2, 26)
5714 11:50:40.662383 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5715 11:50:40.666160 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5716 11:50:40.666736
5717 11:50:40.668895 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5718 11:50:40.672915 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5719 11:50:40.675665 [Gating] SW calibration Done
5720 11:50:40.676239 ==
5721 11:50:40.679095 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:50:40.682126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:50:40.682603 ==
5724 11:50:40.686019 RX Vref Scan: 0
5725 11:50:40.686595
5726 11:50:40.686976 RX Vref 0 -> 0, step: 1
5727 11:50:40.687328
5728 11:50:40.689131 RX Delay -80 -> 252, step: 8
5729 11:50:40.692070 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5730 11:50:40.699071 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5731 11:50:40.702381 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5732 11:50:40.705576 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5733 11:50:40.709006 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5734 11:50:40.711466 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5735 11:50:40.715467 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5736 11:50:40.721757 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5737 11:50:40.724754 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5738 11:50:40.728128 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5739 11:50:40.731667 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5740 11:50:40.734847 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5741 11:50:40.741531 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5742 11:50:40.744366 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5743 11:50:40.747898 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5744 11:50:40.751405 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5745 11:50:40.751833 ==
5746 11:50:40.754307 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 11:50:40.757720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 11:50:40.760856 ==
5749 11:50:40.761280 DQS Delay:
5750 11:50:40.761674 DQS0 = 0, DQS1 = 0
5751 11:50:40.764502 DQM Delay:
5752 11:50:40.764928 DQM0 = 102, DQM1 = 91
5753 11:50:40.768573 DQ Delay:
5754 11:50:40.770835 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5755 11:50:40.774380 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5756 11:50:40.777519 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5757 11:50:40.781685 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5758 11:50:40.782113
5759 11:50:40.782451
5760 11:50:40.782767 ==
5761 11:50:40.783923 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 11:50:40.787799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 11:50:40.788228 ==
5764 11:50:40.788568
5765 11:50:40.788881
5766 11:50:40.790998 TX Vref Scan disable
5767 11:50:40.791425 == TX Byte 0 ==
5768 11:50:40.798050 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5769 11:50:40.800638 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5770 11:50:40.801064 == TX Byte 1 ==
5771 11:50:40.807437 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5772 11:50:40.810726 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5773 11:50:40.811169 ==
5774 11:50:40.814618 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 11:50:40.817661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 11:50:40.818193 ==
5777 11:50:40.820728
5778 11:50:40.821153
5779 11:50:40.821538 TX Vref Scan disable
5780 11:50:40.823849 == TX Byte 0 ==
5781 11:50:40.827219 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5782 11:50:40.833678 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5783 11:50:40.834106 == TX Byte 1 ==
5784 11:50:40.836870 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5785 11:50:40.843782 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5786 11:50:40.844349
5787 11:50:40.844698 [DATLAT]
5788 11:50:40.845016 Freq=933, CH1 RK0
5789 11:50:40.845324
5790 11:50:40.846737 DATLAT Default: 0xd
5791 11:50:40.850549 0, 0xFFFF, sum = 0
5792 11:50:40.851087 1, 0xFFFF, sum = 0
5793 11:50:40.853775 2, 0xFFFF, sum = 0
5794 11:50:40.854240 3, 0xFFFF, sum = 0
5795 11:50:40.857514 4, 0xFFFF, sum = 0
5796 11:50:40.857949 5, 0xFFFF, sum = 0
5797 11:50:40.860170 6, 0xFFFF, sum = 0
5798 11:50:40.860688 7, 0xFFFF, sum = 0
5799 11:50:40.863369 8, 0xFFFF, sum = 0
5800 11:50:40.863801 9, 0xFFFF, sum = 0
5801 11:50:40.867280 10, 0x0, sum = 1
5802 11:50:40.867821 11, 0x0, sum = 2
5803 11:50:40.869940 12, 0x0, sum = 3
5804 11:50:40.870371 13, 0x0, sum = 4
5805 11:50:40.873126 best_step = 11
5806 11:50:40.873587
5807 11:50:40.873934 ==
5808 11:50:40.876678 Dram Type= 6, Freq= 0, CH_1, rank 0
5809 11:50:40.880028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 11:50:40.880576 ==
5811 11:50:40.881140 RX Vref Scan: 1
5812 11:50:40.883245
5813 11:50:40.883810 RX Vref 0 -> 0, step: 1
5814 11:50:40.884165
5815 11:50:40.886974 RX Delay -69 -> 252, step: 4
5816 11:50:40.887642
5817 11:50:40.890899 Set Vref, RX VrefLevel [Byte0]: 50
5818 11:50:40.893716 [Byte1]: 51
5819 11:50:40.896522
5820 11:50:40.897045 Final RX Vref Byte 0 = 50 to rank0
5821 11:50:40.900259 Final RX Vref Byte 1 = 51 to rank0
5822 11:50:40.903285 Final RX Vref Byte 0 = 50 to rank1
5823 11:50:40.906264 Final RX Vref Byte 1 = 51 to rank1==
5824 11:50:40.909553 Dram Type= 6, Freq= 0, CH_1, rank 0
5825 11:50:40.916219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 11:50:40.916750 ==
5827 11:50:40.917096 DQS Delay:
5828 11:50:40.919727 DQS0 = 0, DQS1 = 0
5829 11:50:40.920263 DQM Delay:
5830 11:50:40.920610 DQM0 = 101, DQM1 = 93
5831 11:50:40.923021 DQ Delay:
5832 11:50:40.925717 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5833 11:50:40.929136 DQ4 =98, DQ5 =112, DQ6 =112, DQ7 =96
5834 11:50:40.933108 DQ8 =80, DQ9 =86, DQ10 =94, DQ11 =82
5835 11:50:40.936556 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =102
5836 11:50:40.937138
5837 11:50:40.937547
5838 11:50:40.942474 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5839 11:50:40.945864 CH1 RK0: MR19=505, MR18=1909
5840 11:50:40.952625 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5841 11:50:40.953158
5842 11:50:40.956157 ----->DramcWriteLeveling(PI) begin...
5843 11:50:40.956758 ==
5844 11:50:40.959352 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 11:50:40.961940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 11:50:40.965767 ==
5847 11:50:40.966185 Write leveling (Byte 0): 24 => 24
5848 11:50:40.968601 Write leveling (Byte 1): 30 => 30
5849 11:50:40.972333 DramcWriteLeveling(PI) end<-----
5850 11:50:40.973014
5851 11:50:40.973399 ==
5852 11:50:40.976036 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 11:50:40.982197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 11:50:40.982768 ==
5855 11:50:40.985593 [Gating] SW mode calibration
5856 11:50:40.991856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5857 11:50:40.995515 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5858 11:50:41.001817 0 14 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5859 11:50:41.005099 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5860 11:50:41.008532 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 11:50:41.014806 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 11:50:41.018690 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 11:50:41.021725 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 11:50:41.028811 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
5865 11:50:41.031610 0 14 28 | B1->B0 | 2828 3131 | 0 0 | (1 1) (0 1)
5866 11:50:41.034887 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5867 11:50:41.041597 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5868 11:50:41.045048 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 11:50:41.048020 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 11:50:41.054654 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 11:50:41.057814 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 11:50:41.060988 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5873 11:50:41.067818 0 15 28 | B1->B0 | 4141 2625 | 0 1 | (0 0) (0 0)
5874 11:50:41.071348 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5875 11:50:41.073918 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 11:50:41.080777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 11:50:41.084050 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 11:50:41.087786 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 11:50:41.094366 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 11:50:41.097506 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5881 11:50:41.100562 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 11:50:41.107171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 11:50:41.110384 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 11:50:41.114108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 11:50:41.120661 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 11:50:41.124273 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 11:50:41.126777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 11:50:41.133647 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 11:50:41.137188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 11:50:41.140500 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 11:50:41.146451 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 11:50:41.149936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 11:50:41.153678 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 11:50:41.159999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 11:50:41.163221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 11:50:41.166224 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5897 11:50:41.173289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5898 11:50:41.173902 Total UI for P1: 0, mck2ui 16
5899 11:50:41.179973 best dqsien dly found for B1: ( 1, 2, 24)
5900 11:50:41.182699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5901 11:50:41.186672 Total UI for P1: 0, mck2ui 16
5902 11:50:41.190232 best dqsien dly found for B0: ( 1, 2, 26)
5903 11:50:41.193625 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5904 11:50:41.196350 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5905 11:50:41.196936
5906 11:50:41.199649 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5907 11:50:41.202943 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5908 11:50:41.206372 [Gating] SW calibration Done
5909 11:50:41.206941 ==
5910 11:50:41.209709 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 11:50:41.212703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 11:50:41.216263 ==
5913 11:50:41.216866 RX Vref Scan: 0
5914 11:50:41.217238
5915 11:50:41.219431 RX Vref 0 -> 0, step: 1
5916 11:50:41.219993
5917 11:50:41.222572 RX Delay -80 -> 252, step: 8
5918 11:50:41.225930 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5919 11:50:41.229743 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5920 11:50:41.232657 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5921 11:50:41.235657 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5922 11:50:41.238956 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5923 11:50:41.245682 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5924 11:50:41.250013 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5925 11:50:41.252510 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5926 11:50:41.255447 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5927 11:50:41.259156 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5928 11:50:41.265543 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5929 11:50:41.268524 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5930 11:50:41.271905 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5931 11:50:41.275630 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5932 11:50:41.278605 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5933 11:50:41.284959 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5934 11:50:41.285513 ==
5935 11:50:41.288365 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 11:50:41.292139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 11:50:41.292614 ==
5938 11:50:41.292994 DQS Delay:
5939 11:50:41.295392 DQS0 = 0, DQS1 = 0
5940 11:50:41.295862 DQM Delay:
5941 11:50:41.298013 DQM0 = 101, DQM1 = 90
5942 11:50:41.298522 DQ Delay:
5943 11:50:41.302047 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5944 11:50:41.305292 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =95
5945 11:50:41.308377 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =79
5946 11:50:41.311685 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5947 11:50:41.312267
5948 11:50:41.312641
5949 11:50:41.312984 ==
5950 11:50:41.314499 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 11:50:41.318425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 11:50:41.321939 ==
5953 11:50:41.322511
5954 11:50:41.322888
5955 11:50:41.323235 TX Vref Scan disable
5956 11:50:41.324480 == TX Byte 0 ==
5957 11:50:41.327557 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5958 11:50:41.330924 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5959 11:50:41.334301 == TX Byte 1 ==
5960 11:50:41.338461 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5961 11:50:41.344267 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5962 11:50:41.344841 ==
5963 11:50:41.347427 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 11:50:41.350918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 11:50:41.351391 ==
5966 11:50:41.351770
5967 11:50:41.352117
5968 11:50:41.354319 TX Vref Scan disable
5969 11:50:41.354787 == TX Byte 0 ==
5970 11:50:41.360949 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5971 11:50:41.364078 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5972 11:50:41.364666 == TX Byte 1 ==
5973 11:50:41.372038 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5974 11:50:41.374009 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5975 11:50:41.374487
5976 11:50:41.374861 [DATLAT]
5977 11:50:41.377667 Freq=933, CH1 RK1
5978 11:50:41.378139
5979 11:50:41.378513 DATLAT Default: 0xb
5980 11:50:41.381309 0, 0xFFFF, sum = 0
5981 11:50:41.384047 1, 0xFFFF, sum = 0
5982 11:50:41.384734 2, 0xFFFF, sum = 0
5983 11:50:41.387493 3, 0xFFFF, sum = 0
5984 11:50:41.388077 4, 0xFFFF, sum = 0
5985 11:50:41.390370 5, 0xFFFF, sum = 0
5986 11:50:41.390853 6, 0xFFFF, sum = 0
5987 11:50:41.393901 7, 0xFFFF, sum = 0
5988 11:50:41.394381 8, 0xFFFF, sum = 0
5989 11:50:41.397611 9, 0xFFFF, sum = 0
5990 11:50:41.398184 10, 0x0, sum = 1
5991 11:50:41.401194 11, 0x0, sum = 2
5992 11:50:41.401811 12, 0x0, sum = 3
5993 11:50:41.403812 13, 0x0, sum = 4
5994 11:50:41.404383 best_step = 11
5995 11:50:41.404759
5996 11:50:41.405107 ==
5997 11:50:41.406643 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 11:50:41.410044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 11:50:41.410524 ==
6000 11:50:41.413255 RX Vref Scan: 0
6001 11:50:41.413758
6002 11:50:41.417078 RX Vref 0 -> 0, step: 1
6003 11:50:41.417679
6004 11:50:41.418058 RX Delay -61 -> 252, step: 4
6005 11:50:41.425951 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6006 11:50:41.428601 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6007 11:50:41.431947 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6008 11:50:41.434535 iDelay=207, Bit 3, Center 100 (19 ~ 182) 164
6009 11:50:41.438422 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6010 11:50:41.444804 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6011 11:50:41.447993 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6012 11:50:41.450981 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6013 11:50:41.454958 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6014 11:50:41.457839 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6015 11:50:41.464495 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
6016 11:50:41.467434 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6017 11:50:41.471010 iDelay=207, Bit 12, Center 106 (19 ~ 194) 176
6018 11:50:41.474318 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6019 11:50:41.477603 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6020 11:50:41.484777 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6021 11:50:41.485353 ==
6022 11:50:41.487691 Dram Type= 6, Freq= 0, CH_1, rank 1
6023 11:50:41.490342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6024 11:50:41.490817 ==
6025 11:50:41.491192 DQS Delay:
6026 11:50:41.493674 DQS0 = 0, DQS1 = 0
6027 11:50:41.494143 DQM Delay:
6028 11:50:41.497167 DQM0 = 101, DQM1 = 93
6029 11:50:41.497691 DQ Delay:
6030 11:50:41.500900 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =100
6031 11:50:41.503692 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
6032 11:50:41.507288 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
6033 11:50:41.510825 DQ12 =106, DQ13 =100, DQ14 =98, DQ15 =102
6034 11:50:41.511389
6035 11:50:41.511766
6036 11:50:41.520302 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6037 11:50:41.523669 CH1 RK1: MR19=505, MR18=802
6038 11:50:41.527154 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
6039 11:50:41.530077 [RxdqsGatingPostProcess] freq 933
6040 11:50:41.537056 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6041 11:50:41.540578 best DQS0 dly(2T, 0.5T) = (0, 10)
6042 11:50:41.543438 best DQS1 dly(2T, 0.5T) = (0, 10)
6043 11:50:41.546907 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6044 11:50:41.550393 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6045 11:50:41.553970 best DQS0 dly(2T, 0.5T) = (0, 10)
6046 11:50:41.556674 best DQS1 dly(2T, 0.5T) = (0, 10)
6047 11:50:41.560066 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6048 11:50:41.562904 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6049 11:50:41.566722 Pre-setting of DQS Precalculation
6050 11:50:41.570056 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6051 11:50:41.576117 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6052 11:50:41.582818 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6053 11:50:41.583384
6054 11:50:41.583970
6055 11:50:41.586131 [Calibration Summary] 1866 Mbps
6056 11:50:41.590107 CH 0, Rank 0
6057 11:50:41.590671 SW Impedance : PASS
6058 11:50:41.592819 DUTY Scan : NO K
6059 11:50:41.596767 ZQ Calibration : PASS
6060 11:50:41.597330 Jitter Meter : NO K
6061 11:50:41.599772 CBT Training : PASS
6062 11:50:41.602744 Write leveling : PASS
6063 11:50:41.603213 RX DQS gating : PASS
6064 11:50:41.606216 RX DQ/DQS(RDDQC) : PASS
6065 11:50:41.609669 TX DQ/DQS : PASS
6066 11:50:41.610233 RX DATLAT : PASS
6067 11:50:41.612421 RX DQ/DQS(Engine): PASS
6068 11:50:41.616230 TX OE : NO K
6069 11:50:41.616863 All Pass.
6070 11:50:41.617251
6071 11:50:41.617672 CH 0, Rank 1
6072 11:50:41.619600 SW Impedance : PASS
6073 11:50:41.622999 DUTY Scan : NO K
6074 11:50:41.623564 ZQ Calibration : PASS
6075 11:50:41.625989 Jitter Meter : NO K
6076 11:50:41.629521 CBT Training : PASS
6077 11:50:41.629996 Write leveling : PASS
6078 11:50:41.632615 RX DQS gating : PASS
6079 11:50:41.633089 RX DQ/DQS(RDDQC) : PASS
6080 11:50:41.635492 TX DQ/DQS : PASS
6081 11:50:41.638867 RX DATLAT : PASS
6082 11:50:41.639414 RX DQ/DQS(Engine): PASS
6083 11:50:41.642133 TX OE : NO K
6084 11:50:41.642606 All Pass.
6085 11:50:41.642983
6086 11:50:41.645363 CH 1, Rank 0
6087 11:50:41.645861 SW Impedance : PASS
6088 11:50:41.649021 DUTY Scan : NO K
6089 11:50:41.652573 ZQ Calibration : PASS
6090 11:50:41.653132 Jitter Meter : NO K
6091 11:50:41.655177 CBT Training : PASS
6092 11:50:41.659226 Write leveling : PASS
6093 11:50:41.659796 RX DQS gating : PASS
6094 11:50:41.662485 RX DQ/DQS(RDDQC) : PASS
6095 11:50:41.666086 TX DQ/DQS : PASS
6096 11:50:41.666671 RX DATLAT : PASS
6097 11:50:41.668613 RX DQ/DQS(Engine): PASS
6098 11:50:41.672526 TX OE : NO K
6099 11:50:41.673097 All Pass.
6100 11:50:41.673530
6101 11:50:41.673891 CH 1, Rank 1
6102 11:50:41.675178 SW Impedance : PASS
6103 11:50:41.678425 DUTY Scan : NO K
6104 11:50:41.678911 ZQ Calibration : PASS
6105 11:50:41.682420 Jitter Meter : NO K
6106 11:50:41.685806 CBT Training : PASS
6107 11:50:41.686494 Write leveling : PASS
6108 11:50:41.688272 RX DQS gating : PASS
6109 11:50:41.692117 RX DQ/DQS(RDDQC) : PASS
6110 11:50:41.692869 TX DQ/DQS : PASS
6111 11:50:41.695071 RX DATLAT : PASS
6112 11:50:41.698580 RX DQ/DQS(Engine): PASS
6113 11:50:41.699047 TX OE : NO K
6114 11:50:41.699419 All Pass.
6115 11:50:41.701957
6116 11:50:41.702523 DramC Write-DBI off
6117 11:50:41.706275 PER_BANK_REFRESH: Hybrid Mode
6118 11:50:41.706838 TX_TRACKING: ON
6119 11:50:41.715382 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6120 11:50:41.718332 [FAST_K] Save calibration result to emmc
6121 11:50:41.721799 dramc_set_vcore_voltage set vcore to 650000
6122 11:50:41.725112 Read voltage for 400, 6
6123 11:50:41.725705 Vio18 = 0
6124 11:50:41.728091 Vcore = 650000
6125 11:50:41.728689 Vdram = 0
6126 11:50:41.729274 Vddq = 0
6127 11:50:41.729696 Vmddr = 0
6128 11:50:41.734438 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6129 11:50:41.741332 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6130 11:50:41.741936 MEM_TYPE=3, freq_sel=20
6131 11:50:41.744930 sv_algorithm_assistance_LP4_800
6132 11:50:41.748159 ============ PULL DRAM RESETB DOWN ============
6133 11:50:41.754587 ========== PULL DRAM RESETB DOWN end =========
6134 11:50:41.757948 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6135 11:50:41.763075 ===================================
6136 11:50:41.764204 LPDDR4 DRAM CONFIGURATION
6137 11:50:41.767901 ===================================
6138 11:50:41.768398 EX_ROW_EN[0] = 0x0
6139 11:50:41.771725 EX_ROW_EN[1] = 0x0
6140 11:50:41.772194 LP4Y_EN = 0x0
6141 11:50:41.774392 WORK_FSP = 0x0
6142 11:50:41.777950 WL = 0x2
6143 11:50:41.778524 RL = 0x2
6144 11:50:41.781159 BL = 0x2
6145 11:50:41.781797 RPST = 0x0
6146 11:50:41.785011 RD_PRE = 0x0
6147 11:50:41.785784 WR_PRE = 0x1
6148 11:50:41.787988 WR_PST = 0x0
6149 11:50:41.788556 DBI_WR = 0x0
6150 11:50:41.790702 DBI_RD = 0x0
6151 11:50:41.791173 OTF = 0x1
6152 11:50:41.793988 ===================================
6153 11:50:41.797455 ===================================
6154 11:50:41.800521 ANA top config
6155 11:50:41.804379 ===================================
6156 11:50:41.805055 DLL_ASYNC_EN = 0
6157 11:50:41.807330 ALL_SLAVE_EN = 1
6158 11:50:41.811271 NEW_RANK_MODE = 1
6159 11:50:41.814031 DLL_IDLE_MODE = 1
6160 11:50:41.817292 LP45_APHY_COMB_EN = 1
6161 11:50:41.817911 TX_ODT_DIS = 1
6162 11:50:41.820873 NEW_8X_MODE = 1
6163 11:50:41.824328 ===================================
6164 11:50:41.827463 ===================================
6165 11:50:41.830877 data_rate = 800
6166 11:50:41.833535 CKR = 1
6167 11:50:41.836972 DQ_P2S_RATIO = 4
6168 11:50:41.840426 ===================================
6169 11:50:41.840854 CA_P2S_RATIO = 4
6170 11:50:41.843504 DQ_CA_OPEN = 0
6171 11:50:41.846882 DQ_SEMI_OPEN = 1
6172 11:50:41.850184 CA_SEMI_OPEN = 1
6173 11:50:41.853475 CA_FULL_RATE = 0
6174 11:50:41.857049 DQ_CKDIV4_EN = 0
6175 11:50:41.857516 CA_CKDIV4_EN = 1
6176 11:50:41.860127 CA_PREDIV_EN = 0
6177 11:50:41.863346 PH8_DLY = 0
6178 11:50:41.866844 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6179 11:50:41.869978 DQ_AAMCK_DIV = 0
6180 11:50:41.873514 CA_AAMCK_DIV = 0
6181 11:50:41.873944 CA_ADMCK_DIV = 4
6182 11:50:41.877244 DQ_TRACK_CA_EN = 0
6183 11:50:41.880122 CA_PICK = 800
6184 11:50:41.883980 CA_MCKIO = 400
6185 11:50:41.886668 MCKIO_SEMI = 400
6186 11:50:41.890105 PLL_FREQ = 3016
6187 11:50:41.893392 DQ_UI_PI_RATIO = 32
6188 11:50:41.896412 CA_UI_PI_RATIO = 32
6189 11:50:41.900518 ===================================
6190 11:50:41.903389 ===================================
6191 11:50:41.903926 memory_type:LPDDR4
6192 11:50:41.906861 GP_NUM : 10
6193 11:50:41.910084 SRAM_EN : 1
6194 11:50:41.910621 MD32_EN : 0
6195 11:50:41.913230 ===================================
6196 11:50:41.916074 [ANA_INIT] >>>>>>>>>>>>>>
6197 11:50:41.920109 <<<<<< [CONFIGURE PHASE]: ANA_TX
6198 11:50:41.922614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6199 11:50:41.926979 ===================================
6200 11:50:41.929443 data_rate = 800,PCW = 0X7400
6201 11:50:41.933812 ===================================
6202 11:50:41.936012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6203 11:50:41.939721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 11:50:41.953371 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 11:50:41.955744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6206 11:50:41.959491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6207 11:50:41.962398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6208 11:50:41.965954 [ANA_INIT] flow start
6209 11:50:41.969389 [ANA_INIT] PLL >>>>>>>>
6210 11:50:41.970005 [ANA_INIT] PLL <<<<<<<<
6211 11:50:41.972409 [ANA_INIT] MIDPI >>>>>>>>
6212 11:50:41.975776 [ANA_INIT] MIDPI <<<<<<<<
6213 11:50:41.976215 [ANA_INIT] DLL >>>>>>>>
6214 11:50:41.978967 [ANA_INIT] flow end
6215 11:50:41.982699 ============ LP4 DIFF to SE enter ============
6216 11:50:41.985623 ============ LP4 DIFF to SE exit ============
6217 11:50:41.989754 [ANA_INIT] <<<<<<<<<<<<<
6218 11:50:41.992749 [Flow] Enable top DCM control >>>>>
6219 11:50:41.996016 [Flow] Enable top DCM control <<<<<
6220 11:50:41.998900 Enable DLL master slave shuffle
6221 11:50:42.005811 ==============================================================
6222 11:50:42.006378 Gating Mode config
6223 11:50:42.012632 ==============================================================
6224 11:50:42.013196 Config description:
6225 11:50:42.022447 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6226 11:50:42.029446 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6227 11:50:42.035383 SELPH_MODE 0: By rank 1: By Phase
6228 11:50:42.042416 ==============================================================
6229 11:50:42.043004 GAT_TRACK_EN = 0
6230 11:50:42.045716 RX_GATING_MODE = 2
6231 11:50:42.048694 RX_GATING_TRACK_MODE = 2
6232 11:50:42.052216 SELPH_MODE = 1
6233 11:50:42.055533 PICG_EARLY_EN = 1
6234 11:50:42.058958 VALID_LAT_VALUE = 1
6235 11:50:42.065677 ==============================================================
6236 11:50:42.068791 Enter into Gating configuration >>>>
6237 11:50:42.071541 Exit from Gating configuration <<<<
6238 11:50:42.075416 Enter into DVFS_PRE_config >>>>>
6239 11:50:42.084847 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6240 11:50:42.088157 Exit from DVFS_PRE_config <<<<<
6241 11:50:42.092632 Enter into PICG configuration >>>>
6242 11:50:42.095609 Exit from PICG configuration <<<<
6243 11:50:42.098353 [RX_INPUT] configuration >>>>>
6244 11:50:42.101272 [RX_INPUT] configuration <<<<<
6245 11:50:42.105559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6246 11:50:42.111575 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6247 11:50:42.117954 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6248 11:50:42.121490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6249 11:50:42.128116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 11:50:42.134644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 11:50:42.138087 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6252 11:50:42.144801 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6253 11:50:42.147873 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6254 11:50:42.151304 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6255 11:50:42.154373 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6256 11:50:42.161736 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6257 11:50:42.164320 ===================================
6258 11:50:42.164891 LPDDR4 DRAM CONFIGURATION
6259 11:50:42.167519 ===================================
6260 11:50:42.171146 EX_ROW_EN[0] = 0x0
6261 11:50:42.174200 EX_ROW_EN[1] = 0x0
6262 11:50:42.174763 LP4Y_EN = 0x0
6263 11:50:42.177239 WORK_FSP = 0x0
6264 11:50:42.177785 WL = 0x2
6265 11:50:42.180610 RL = 0x2
6266 11:50:42.181172 BL = 0x2
6267 11:50:42.183982 RPST = 0x0
6268 11:50:42.184590 RD_PRE = 0x0
6269 11:50:42.187260 WR_PRE = 0x1
6270 11:50:42.187729 WR_PST = 0x0
6271 11:50:42.190872 DBI_WR = 0x0
6272 11:50:42.191345 DBI_RD = 0x0
6273 11:50:42.193957 OTF = 0x1
6274 11:50:42.197311 ===================================
6275 11:50:42.200372 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6276 11:50:42.204070 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6277 11:50:42.210233 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6278 11:50:42.213877 ===================================
6279 11:50:42.217140 LPDDR4 DRAM CONFIGURATION
6280 11:50:42.220377 ===================================
6281 11:50:42.220942 EX_ROW_EN[0] = 0x10
6282 11:50:42.224187 EX_ROW_EN[1] = 0x0
6283 11:50:42.224749 LP4Y_EN = 0x0
6284 11:50:42.226592 WORK_FSP = 0x0
6285 11:50:42.227059 WL = 0x2
6286 11:50:42.230178 RL = 0x2
6287 11:50:42.230740 BL = 0x2
6288 11:50:42.233393 RPST = 0x0
6289 11:50:42.233951 RD_PRE = 0x0
6290 11:50:42.237125 WR_PRE = 0x1
6291 11:50:42.237751 WR_PST = 0x0
6292 11:50:42.239909 DBI_WR = 0x0
6293 11:50:42.240390 DBI_RD = 0x0
6294 11:50:42.243952 OTF = 0x1
6295 11:50:42.246502 ===================================
6296 11:50:42.253176 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6297 11:50:42.256799 nWR fixed to 30
6298 11:50:42.260007 [ModeRegInit_LP4] CH0 RK0
6299 11:50:42.260636 [ModeRegInit_LP4] CH0 RK1
6300 11:50:42.263182 [ModeRegInit_LP4] CH1 RK0
6301 11:50:42.266611 [ModeRegInit_LP4] CH1 RK1
6302 11:50:42.267175 match AC timing 19
6303 11:50:42.273257 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6304 11:50:42.276377 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6305 11:50:42.279333 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6306 11:50:42.286414 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6307 11:50:42.289855 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6308 11:50:42.290413 ==
6309 11:50:42.293152 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 11:50:42.296744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 11:50:42.297319 ==
6312 11:50:42.303246 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 11:50:42.309869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6314 11:50:42.312873 [CA 0] Center 36 (8~64) winsize 57
6315 11:50:42.316382 [CA 1] Center 36 (8~64) winsize 57
6316 11:50:42.319487 [CA 2] Center 36 (8~64) winsize 57
6317 11:50:42.322488 [CA 3] Center 36 (8~64) winsize 57
6318 11:50:42.326409 [CA 4] Center 36 (8~64) winsize 57
6319 11:50:42.326973 [CA 5] Center 36 (8~64) winsize 57
6320 11:50:42.329548
6321 11:50:42.333090 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6322 11:50:42.333704
6323 11:50:42.336114 [CATrainingPosCal] consider 1 rank data
6324 11:50:42.340135 u2DelayCellTimex100 = 270/100 ps
6325 11:50:42.342193 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 11:50:42.345913 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 11:50:42.349087 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:50:42.352602 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:50:42.356004 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:50:42.358652 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:50:42.359125
6332 11:50:42.362107 CA PerBit enable=1, Macro0, CA PI delay=36
6333 11:50:42.362648
6334 11:50:42.365649 [CBTSetCACLKResult] CA Dly = 36
6335 11:50:42.369064 CS Dly: 1 (0~32)
6336 11:50:42.369670 ==
6337 11:50:42.372182 Dram Type= 6, Freq= 0, CH_0, rank 1
6338 11:50:42.376313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:50:42.376899 ==
6340 11:50:42.382153 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6341 11:50:42.388776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6342 11:50:42.392176 [CA 0] Center 36 (8~64) winsize 57
6343 11:50:42.395321 [CA 1] Center 36 (8~64) winsize 57
6344 11:50:42.395893 [CA 2] Center 36 (8~64) winsize 57
6345 11:50:42.398706 [CA 3] Center 36 (8~64) winsize 57
6346 11:50:42.402095 [CA 4] Center 36 (8~64) winsize 57
6347 11:50:42.405317 [CA 5] Center 36 (8~64) winsize 57
6348 11:50:42.405831
6349 11:50:42.408413 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6350 11:50:42.411807
6351 11:50:42.414867 [CATrainingPosCal] consider 2 rank data
6352 11:50:42.415407 u2DelayCellTimex100 = 270/100 ps
6353 11:50:42.422176 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 11:50:42.425172 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 11:50:42.428645 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 11:50:42.431683 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 11:50:42.435469 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 11:50:42.438121 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 11:50:42.438585
6360 11:50:42.441503 CA PerBit enable=1, Macro0, CA PI delay=36
6361 11:50:42.441967
6362 11:50:42.445005 [CBTSetCACLKResult] CA Dly = 36
6363 11:50:42.448195 CS Dly: 1 (0~32)
6364 11:50:42.448611
6365 11:50:42.451421 ----->DramcWriteLeveling(PI) begin...
6366 11:50:42.451840 ==
6367 11:50:42.454588 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:50:42.457661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:50:42.458078 ==
6370 11:50:42.461018 Write leveling (Byte 0): 40 => 8
6371 11:50:42.465176 Write leveling (Byte 1): 32 => 0
6372 11:50:42.467873 DramcWriteLeveling(PI) end<-----
6373 11:50:42.468391
6374 11:50:42.468723 ==
6375 11:50:42.471297 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 11:50:42.474114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 11:50:42.474533 ==
6378 11:50:42.477762 [Gating] SW mode calibration
6379 11:50:42.484196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6380 11:50:42.491087 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6381 11:50:42.494673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6382 11:50:42.497906 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6383 11:50:42.504010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 11:50:42.507444 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 11:50:42.513853 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6386 11:50:42.517286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 11:50:42.520770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 11:50:42.527156 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 11:50:42.530540 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 11:50:42.534041 Total UI for P1: 0, mck2ui 16
6391 11:50:42.536702 best dqsien dly found for B0: ( 0, 14, 24)
6392 11:50:42.540547 Total UI for P1: 0, mck2ui 16
6393 11:50:42.543569 best dqsien dly found for B1: ( 0, 14, 24)
6394 11:50:42.547193 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6395 11:50:42.551060 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6396 11:50:42.551609
6397 11:50:42.553653 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6398 11:50:42.556855 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6399 11:50:42.559776 [Gating] SW calibration Done
6400 11:50:42.560240 ==
6401 11:50:42.563004 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 11:50:42.566333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 11:50:42.569649 ==
6404 11:50:42.570203 RX Vref Scan: 0
6405 11:50:42.570573
6406 11:50:42.573210 RX Vref 0 -> 0, step: 1
6407 11:50:42.573717
6408 11:50:42.576240 RX Delay -410 -> 252, step: 16
6409 11:50:42.580117 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6410 11:50:42.582996 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6411 11:50:42.586244 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6412 11:50:42.593062 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6413 11:50:42.596431 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6414 11:50:42.599607 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6415 11:50:42.603082 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6416 11:50:42.609841 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6417 11:50:42.612899 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6418 11:50:42.615973 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6419 11:50:42.619393 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6420 11:50:42.626003 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6421 11:50:42.629118 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6422 11:50:42.633207 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6423 11:50:42.639012 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6424 11:50:42.642638 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6425 11:50:42.643103 ==
6426 11:50:42.646098 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 11:50:42.648924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 11:50:42.649393 ==
6429 11:50:42.652786 DQS Delay:
6430 11:50:42.653455 DQS0 = 43, DQS1 = 59
6431 11:50:42.653842 DQM Delay:
6432 11:50:42.655570 DQM0 = 10, DQM1 = 12
6433 11:50:42.656034 DQ Delay:
6434 11:50:42.659765 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6435 11:50:42.662181 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6436 11:50:42.665709 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6437 11:50:42.669127 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6438 11:50:42.669740
6439 11:50:42.670115
6440 11:50:42.670452 ==
6441 11:50:42.672099 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 11:50:42.675626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 11:50:42.678559 ==
6444 11:50:42.679116
6445 11:50:42.679489
6446 11:50:42.679829 TX Vref Scan disable
6447 11:50:42.682108 == TX Byte 0 ==
6448 11:50:42.685326 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 11:50:42.688926 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 11:50:42.692178 == TX Byte 1 ==
6451 11:50:42.694996 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6452 11:50:42.698858 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6453 11:50:42.699382 ==
6454 11:50:42.701940 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 11:50:42.708971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 11:50:42.709646 ==
6457 11:50:42.710033
6458 11:50:42.710378
6459 11:50:42.710709 TX Vref Scan disable
6460 11:50:42.712097 == TX Byte 0 ==
6461 11:50:42.714968 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6462 11:50:42.719343 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6463 11:50:42.721910 == TX Byte 1 ==
6464 11:50:42.724963 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6465 11:50:42.731766 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6466 11:50:42.732290
6467 11:50:42.732631 [DATLAT]
6468 11:50:42.732942 Freq=400, CH0 RK0
6469 11:50:42.733249
6470 11:50:42.734429 DATLAT Default: 0xf
6471 11:50:42.734859 0, 0xFFFF, sum = 0
6472 11:50:42.738056 1, 0xFFFF, sum = 0
6473 11:50:42.741040 2, 0xFFFF, sum = 0
6474 11:50:42.741512 3, 0xFFFF, sum = 0
6475 11:50:42.744382 4, 0xFFFF, sum = 0
6476 11:50:42.744860 5, 0xFFFF, sum = 0
6477 11:50:42.748480 6, 0xFFFF, sum = 0
6478 11:50:42.749008 7, 0xFFFF, sum = 0
6479 11:50:42.751496 8, 0xFFFF, sum = 0
6480 11:50:42.752023 9, 0xFFFF, sum = 0
6481 11:50:42.754281 10, 0xFFFF, sum = 0
6482 11:50:42.754712 11, 0xFFFF, sum = 0
6483 11:50:42.757946 12, 0xFFFF, sum = 0
6484 11:50:42.758375 13, 0x0, sum = 1
6485 11:50:42.760874 14, 0x0, sum = 2
6486 11:50:42.761305 15, 0x0, sum = 3
6487 11:50:42.764489 16, 0x0, sum = 4
6488 11:50:42.764918 best_step = 14
6489 11:50:42.765257
6490 11:50:42.765691 ==
6491 11:50:42.767760 Dram Type= 6, Freq= 0, CH_0, rank 0
6492 11:50:42.774050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:50:42.774475 ==
6494 11:50:42.774812 RX Vref Scan: 1
6495 11:50:42.775127
6496 11:50:42.777638 RX Vref 0 -> 0, step: 1
6497 11:50:42.778077
6498 11:50:42.780461 RX Delay -359 -> 252, step: 8
6499 11:50:42.780885
6500 11:50:42.784619 Set Vref, RX VrefLevel [Byte0]: 62
6501 11:50:42.787327 [Byte1]: 50
6502 11:50:42.787850
6503 11:50:42.791158 Final RX Vref Byte 0 = 62 to rank0
6504 11:50:42.794192 Final RX Vref Byte 1 = 50 to rank0
6505 11:50:42.797221 Final RX Vref Byte 0 = 62 to rank1
6506 11:50:42.800273 Final RX Vref Byte 1 = 50 to rank1==
6507 11:50:42.804382 Dram Type= 6, Freq= 0, CH_0, rank 0
6508 11:50:42.806799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 11:50:42.810495 ==
6510 11:50:42.811016 DQS Delay:
6511 11:50:42.811356 DQS0 = 48, DQS1 = 60
6512 11:50:42.813785 DQM Delay:
6513 11:50:42.814303 DQM0 = 11, DQM1 = 12
6514 11:50:42.817052 DQ Delay:
6515 11:50:42.820357 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6516 11:50:42.820915 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6517 11:50:42.823943 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6518 11:50:42.827826 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6519 11:50:42.828343
6520 11:50:42.831276
6521 11:50:42.836727 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6522 11:50:42.840293 CH0 RK0: MR19=C0C, MR18=BE82
6523 11:50:42.847118 CH0_RK0: MR19=0xC0C, MR18=0xBE82, DQSOSC=386, MR23=63, INC=396, DEC=264
6524 11:50:42.847644 ==
6525 11:50:42.850195 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 11:50:42.853751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 11:50:42.854316 ==
6528 11:50:42.857253 [Gating] SW mode calibration
6529 11:50:42.863160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6530 11:50:42.870536 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6531 11:50:42.873331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6532 11:50:42.876438 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6533 11:50:42.883149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 11:50:42.886446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 11:50:42.889616 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6536 11:50:42.896376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 11:50:42.899795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 11:50:42.903258 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 11:50:42.906687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 11:50:42.910056 Total UI for P1: 0, mck2ui 16
6541 11:50:42.912769 best dqsien dly found for B0: ( 0, 14, 24)
6542 11:50:42.916510 Total UI for P1: 0, mck2ui 16
6543 11:50:42.919627 best dqsien dly found for B1: ( 0, 14, 24)
6544 11:50:42.926244 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6545 11:50:42.929473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6546 11:50:42.929906
6547 11:50:42.932782 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6548 11:50:42.936067 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6549 11:50:42.939306 [Gating] SW calibration Done
6550 11:50:42.939954 ==
6551 11:50:42.942841 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 11:50:42.946119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 11:50:42.946547 ==
6554 11:50:42.949112 RX Vref Scan: 0
6555 11:50:42.949746
6556 11:50:42.950158 RX Vref 0 -> 0, step: 1
6557 11:50:42.950645
6558 11:50:42.952718 RX Delay -410 -> 252, step: 16
6559 11:50:42.959525 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6560 11:50:42.962685 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6561 11:50:42.966121 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6562 11:50:42.969787 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6563 11:50:42.975920 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6564 11:50:42.979670 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6565 11:50:42.982849 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6566 11:50:42.985801 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6567 11:50:42.992582 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6568 11:50:42.995255 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6569 11:50:42.999275 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6570 11:50:43.002310 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6571 11:50:43.009578 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6572 11:50:43.012049 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6573 11:50:43.015219 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6574 11:50:43.021933 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6575 11:50:43.022458 ==
6576 11:50:43.025609 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 11:50:43.028600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 11:50:43.029294 ==
6579 11:50:43.029719 DQS Delay:
6580 11:50:43.032761 DQS0 = 43, DQS1 = 59
6581 11:50:43.033290 DQM Delay:
6582 11:50:43.035597 DQM0 = 10, DQM1 = 16
6583 11:50:43.036119 DQ Delay:
6584 11:50:43.038256 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6585 11:50:43.041736 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6586 11:50:43.044922 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6587 11:50:43.048452 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6588 11:50:43.048978
6589 11:50:43.049318
6590 11:50:43.049694 ==
6591 11:50:43.051436 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 11:50:43.054993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 11:50:43.055421 ==
6594 11:50:43.055756
6595 11:50:43.056068
6596 11:50:43.058235 TX Vref Scan disable
6597 11:50:43.058658 == TX Byte 0 ==
6598 11:50:43.065350 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6599 11:50:43.068322 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6600 11:50:43.068844 == TX Byte 1 ==
6601 11:50:43.075498 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6602 11:50:43.078050 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6603 11:50:43.078492 ==
6604 11:50:43.081308 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 11:50:43.085375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 11:50:43.086008 ==
6607 11:50:43.086358
6608 11:50:43.086673
6609 11:50:43.087935 TX Vref Scan disable
6610 11:50:43.088298 == TX Byte 0 ==
6611 11:50:43.094805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6612 11:50:43.098610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6613 11:50:43.099134 == TX Byte 1 ==
6614 11:50:43.104805 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6615 11:50:43.108152 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6616 11:50:43.108676
6617 11:50:43.109014 [DATLAT]
6618 11:50:43.111558 Freq=400, CH0 RK1
6619 11:50:43.112076
6620 11:50:43.112415 DATLAT Default: 0xe
6621 11:50:43.114846 0, 0xFFFF, sum = 0
6622 11:50:43.115373 1, 0xFFFF, sum = 0
6623 11:50:43.118007 2, 0xFFFF, sum = 0
6624 11:50:43.118434 3, 0xFFFF, sum = 0
6625 11:50:43.121463 4, 0xFFFF, sum = 0
6626 11:50:43.121898 5, 0xFFFF, sum = 0
6627 11:50:43.124171 6, 0xFFFF, sum = 0
6628 11:50:43.127914 7, 0xFFFF, sum = 0
6629 11:50:43.128437 8, 0xFFFF, sum = 0
6630 11:50:43.130662 9, 0xFFFF, sum = 0
6631 11:50:43.131094 10, 0xFFFF, sum = 0
6632 11:50:43.134574 11, 0xFFFF, sum = 0
6633 11:50:43.135096 12, 0xFFFF, sum = 0
6634 11:50:43.137491 13, 0x0, sum = 1
6635 11:50:43.137922 14, 0x0, sum = 2
6636 11:50:43.140735 15, 0x0, sum = 3
6637 11:50:43.141194 16, 0x0, sum = 4
6638 11:50:43.143904 best_step = 14
6639 11:50:43.144324
6640 11:50:43.144658 ==
6641 11:50:43.147665 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 11:50:43.150563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:50:43.151017 ==
6644 11:50:43.151366 RX Vref Scan: 0
6645 11:50:43.151684
6646 11:50:43.153786 RX Vref 0 -> 0, step: 1
6647 11:50:43.154208
6648 11:50:43.157020 RX Delay -359 -> 252, step: 8
6649 11:50:43.164818 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6650 11:50:43.168448 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6651 11:50:43.171409 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6652 11:50:43.174848 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6653 11:50:43.181658 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6654 11:50:43.184753 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6655 11:50:43.187780 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6656 11:50:43.194633 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6657 11:50:43.197527 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6658 11:50:43.201384 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6659 11:50:43.204316 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6660 11:50:43.211038 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6661 11:50:43.215226 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6662 11:50:43.218207 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6663 11:50:43.221019 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6664 11:50:43.228270 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6665 11:50:43.228848 ==
6666 11:50:43.231180 Dram Type= 6, Freq= 0, CH_0, rank 1
6667 11:50:43.234188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:50:43.234653 ==
6669 11:50:43.235022 DQS Delay:
6670 11:50:43.237671 DQS0 = 44, DQS1 = 60
6671 11:50:43.238248 DQM Delay:
6672 11:50:43.241093 DQM0 = 8, DQM1 = 14
6673 11:50:43.241833 DQ Delay:
6674 11:50:43.244389 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6675 11:50:43.247158 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6676 11:50:43.250495 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6677 11:50:43.253868 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6678 11:50:43.254512
6679 11:50:43.254889
6680 11:50:43.263618 [DQSOSCAuto] RK1, (LSB)MR18= 0xb440, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6681 11:50:43.264187 CH0 RK1: MR19=C0C, MR18=B440
6682 11:50:43.269942 CH0_RK1: MR19=0xC0C, MR18=0xB440, DQSOSC=387, MR23=63, INC=394, DEC=262
6683 11:50:43.273224 [RxdqsGatingPostProcess] freq 400
6684 11:50:43.280232 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6685 11:50:43.283255 best DQS0 dly(2T, 0.5T) = (0, 10)
6686 11:50:43.286438 best DQS1 dly(2T, 0.5T) = (0, 10)
6687 11:50:43.289683 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6688 11:50:43.292970 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6689 11:50:43.296274 best DQS0 dly(2T, 0.5T) = (0, 10)
6690 11:50:43.299984 best DQS1 dly(2T, 0.5T) = (0, 10)
6691 11:50:43.302818 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6692 11:50:43.305816 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6693 11:50:43.306382 Pre-setting of DQS Precalculation
6694 11:50:43.312478 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6695 11:50:43.312904 ==
6696 11:50:43.315784 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 11:50:43.318967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 11:50:43.319491 ==
6699 11:50:43.325962 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 11:50:43.332640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6701 11:50:43.335660 [CA 0] Center 36 (8~64) winsize 57
6702 11:50:43.338816 [CA 1] Center 36 (8~64) winsize 57
6703 11:50:43.342791 [CA 2] Center 36 (8~64) winsize 57
6704 11:50:43.345312 [CA 3] Center 36 (8~64) winsize 57
6705 11:50:43.348650 [CA 4] Center 36 (8~64) winsize 57
6706 11:50:43.349074 [CA 5] Center 36 (8~64) winsize 57
6707 11:50:43.352401
6708 11:50:43.356145 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6709 11:50:43.356661
6710 11:50:43.358605 [CATrainingPosCal] consider 1 rank data
6711 11:50:43.362180 u2DelayCellTimex100 = 270/100 ps
6712 11:50:43.365304 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 11:50:43.368390 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 11:50:43.371953 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:50:43.375402 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:50:43.378211 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:50:43.382058 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:50:43.382617
6719 11:50:43.385686 CA PerBit enable=1, Macro0, CA PI delay=36
6720 11:50:43.389178
6721 11:50:43.389827 [CBTSetCACLKResult] CA Dly = 36
6722 11:50:43.391895 CS Dly: 1 (0~32)
6723 11:50:43.392317 ==
6724 11:50:43.395326 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 11:50:43.398495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:50:43.399038 ==
6727 11:50:43.405032 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6728 11:50:43.411537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6729 11:50:43.414957 [CA 0] Center 36 (8~64) winsize 57
6730 11:50:43.417924 [CA 1] Center 36 (8~64) winsize 57
6731 11:50:43.418373 [CA 2] Center 36 (8~64) winsize 57
6732 11:50:43.421894 [CA 3] Center 36 (8~64) winsize 57
6733 11:50:43.425568 [CA 4] Center 36 (8~64) winsize 57
6734 11:50:43.428516 [CA 5] Center 36 (8~64) winsize 57
6735 11:50:43.429039
6736 11:50:43.432510 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6737 11:50:43.433033
6738 11:50:43.438331 [CATrainingPosCal] consider 2 rank data
6739 11:50:43.438872 u2DelayCellTimex100 = 270/100 ps
6740 11:50:43.445143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 11:50:43.448148 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 11:50:43.452347 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 11:50:43.454550 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 11:50:43.458126 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 11:50:43.461977 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 11:50:43.462504
6747 11:50:43.464852 CA PerBit enable=1, Macro0, CA PI delay=36
6748 11:50:43.465375
6749 11:50:43.467974 [CBTSetCACLKResult] CA Dly = 36
6750 11:50:43.471105 CS Dly: 1 (0~32)
6751 11:50:43.471531
6752 11:50:43.474866 ----->DramcWriteLeveling(PI) begin...
6753 11:50:43.475418 ==
6754 11:50:43.477863 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:50:43.481667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:50:43.482253 ==
6757 11:50:43.484178 Write leveling (Byte 0): 40 => 8
6758 11:50:43.487730 Write leveling (Byte 1): 40 => 8
6759 11:50:43.490799 DramcWriteLeveling(PI) end<-----
6760 11:50:43.491219
6761 11:50:43.491554 ==
6762 11:50:43.494479 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 11:50:43.497786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 11:50:43.498214 ==
6765 11:50:43.500777 [Gating] SW mode calibration
6766 11:50:43.507429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6767 11:50:43.514574 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6768 11:50:43.517918 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6769 11:50:43.521240 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6770 11:50:43.527688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 11:50:43.530528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 11:50:43.534407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6773 11:50:43.540301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 11:50:43.543833 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 11:50:43.547976 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 11:50:43.553866 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 11:50:43.557184 Total UI for P1: 0, mck2ui 16
6778 11:50:43.560244 best dqsien dly found for B0: ( 0, 14, 24)
6779 11:50:43.560716 Total UI for P1: 0, mck2ui 16
6780 11:50:43.567133 best dqsien dly found for B1: ( 0, 14, 24)
6781 11:50:43.570355 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6782 11:50:43.573481 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6783 11:50:43.573949
6784 11:50:43.576588 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6785 11:50:43.580074 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6786 11:50:43.583240 [Gating] SW calibration Done
6787 11:50:43.583742 ==
6788 11:50:43.586666 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 11:50:43.590411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 11:50:43.590993 ==
6791 11:50:43.593188 RX Vref Scan: 0
6792 11:50:43.593715
6793 11:50:43.596602 RX Vref 0 -> 0, step: 1
6794 11:50:43.597069
6795 11:50:43.597501 RX Delay -410 -> 252, step: 16
6796 11:50:43.603045 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6797 11:50:43.606767 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6798 11:50:43.610218 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6799 11:50:43.616832 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6800 11:50:43.619876 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6801 11:50:43.624064 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6802 11:50:43.626183 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6803 11:50:43.632856 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6804 11:50:43.637036 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6805 11:50:43.639906 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6806 11:50:43.642717 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6807 11:50:43.649551 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6808 11:50:43.653262 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6809 11:50:43.657111 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6810 11:50:43.659305 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6811 11:50:43.665873 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6812 11:50:43.666509 ==
6813 11:50:43.669493 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 11:50:43.672406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 11:50:43.672939 ==
6816 11:50:43.673316 DQS Delay:
6817 11:50:43.675806 DQS0 = 43, DQS1 = 51
6818 11:50:43.676304 DQM Delay:
6819 11:50:43.679110 DQM0 = 12, DQM1 = 14
6820 11:50:43.679578 DQ Delay:
6821 11:50:43.682596 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6822 11:50:43.685513 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6823 11:50:43.688988 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6824 11:50:43.692292 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6825 11:50:43.692804
6826 11:50:43.693305
6827 11:50:43.693757 ==
6828 11:50:43.695622 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 11:50:43.698957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 11:50:43.699399 ==
6831 11:50:43.699738
6832 11:50:43.701912
6833 11:50:43.702439 TX Vref Scan disable
6834 11:50:43.705693 == TX Byte 0 ==
6835 11:50:43.708735 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 11:50:43.711910 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 11:50:43.715227 == TX Byte 1 ==
6838 11:50:43.718728 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 11:50:43.721885 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 11:50:43.722361 ==
6841 11:50:43.725668 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 11:50:43.728657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 11:50:43.732512 ==
6844 11:50:43.732936
6845 11:50:43.733274
6846 11:50:43.733646 TX Vref Scan disable
6847 11:50:43.736091 == TX Byte 0 ==
6848 11:50:43.738864 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6849 11:50:43.742208 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6850 11:50:43.745686 == TX Byte 1 ==
6851 11:50:43.748644 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6852 11:50:43.751670 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6853 11:50:43.752231
6854 11:50:43.755411 [DATLAT]
6855 11:50:43.755946 Freq=400, CH1 RK0
6856 11:50:43.756288
6857 11:50:43.758421 DATLAT Default: 0xf
6858 11:50:43.758843 0, 0xFFFF, sum = 0
6859 11:50:43.761974 1, 0xFFFF, sum = 0
6860 11:50:43.762403 2, 0xFFFF, sum = 0
6861 11:50:43.765456 3, 0xFFFF, sum = 0
6862 11:50:43.765943 4, 0xFFFF, sum = 0
6863 11:50:43.768094 5, 0xFFFF, sum = 0
6864 11:50:43.768552 6, 0xFFFF, sum = 0
6865 11:50:43.771891 7, 0xFFFF, sum = 0
6866 11:50:43.772316 8, 0xFFFF, sum = 0
6867 11:50:43.774888 9, 0xFFFF, sum = 0
6868 11:50:43.775315 10, 0xFFFF, sum = 0
6869 11:50:43.778126 11, 0xFFFF, sum = 0
6870 11:50:43.778552 12, 0xFFFF, sum = 0
6871 11:50:43.781814 13, 0x0, sum = 1
6872 11:50:43.782240 14, 0x0, sum = 2
6873 11:50:43.784339 15, 0x0, sum = 3
6874 11:50:43.784762 16, 0x0, sum = 4
6875 11:50:43.788062 best_step = 14
6876 11:50:43.788479
6877 11:50:43.788812 ==
6878 11:50:43.791091 Dram Type= 6, Freq= 0, CH_1, rank 0
6879 11:50:43.794577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:50:43.794875 ==
6881 11:50:43.797785 RX Vref Scan: 1
6882 11:50:43.798008
6883 11:50:43.798187 RX Vref 0 -> 0, step: 1
6884 11:50:43.798354
6885 11:50:43.801067 RX Delay -343 -> 252, step: 8
6886 11:50:43.801289
6887 11:50:43.804617 Set Vref, RX VrefLevel [Byte0]: 50
6888 11:50:43.808296 [Byte1]: 51
6889 11:50:43.813206
6890 11:50:43.813464 Final RX Vref Byte 0 = 50 to rank0
6891 11:50:43.816402 Final RX Vref Byte 1 = 51 to rank0
6892 11:50:43.819207 Final RX Vref Byte 0 = 50 to rank1
6893 11:50:43.822667 Final RX Vref Byte 1 = 51 to rank1==
6894 11:50:43.825337 Dram Type= 6, Freq= 0, CH_1, rank 0
6895 11:50:43.832365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 11:50:43.832618 ==
6897 11:50:43.832797 DQS Delay:
6898 11:50:43.835259 DQS0 = 44, DQS1 = 56
6899 11:50:43.835486 DQM Delay:
6900 11:50:43.835664 DQM0 = 7, DQM1 = 11
6901 11:50:43.838549 DQ Delay:
6902 11:50:43.841932 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6903 11:50:43.845340 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6904 11:50:43.845594 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6905 11:50:43.848748 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6906 11:50:43.851599
6907 11:50:43.851822
6908 11:50:43.858991 [DQSOSCAuto] RK0, (LSB)MR18= 0x976d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6909 11:50:43.861525 CH1 RK0: MR19=C0C, MR18=976D
6910 11:50:43.868508 CH1_RK0: MR19=0xC0C, MR18=0x976D, DQSOSC=390, MR23=63, INC=388, DEC=258
6911 11:50:43.868735 ==
6912 11:50:43.871676 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 11:50:43.874758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 11:50:43.874983 ==
6915 11:50:43.878409 [Gating] SW mode calibration
6916 11:50:43.884830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6917 11:50:43.891793 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6918 11:50:43.894779 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 11:50:43.897947 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6920 11:50:43.904838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 11:50:43.907908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 11:50:43.911290 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 11:50:43.917943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 11:50:43.921822 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 11:50:43.924282 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 11:50:43.931940 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 11:50:43.932182 Total UI for P1: 0, mck2ui 16
6928 11:50:43.937633 best dqsien dly found for B0: ( 0, 14, 24)
6929 11:50:43.937858 Total UI for P1: 0, mck2ui 16
6930 11:50:43.944085 best dqsien dly found for B1: ( 0, 14, 24)
6931 11:50:43.947408 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6932 11:50:43.950608 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6933 11:50:43.950889
6934 11:50:43.953773 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 11:50:43.958094 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6936 11:50:43.960745 [Gating] SW calibration Done
6937 11:50:43.961274 ==
6938 11:50:43.964153 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 11:50:43.967783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 11:50:43.968293 ==
6941 11:50:43.970807 RX Vref Scan: 0
6942 11:50:43.971244
6943 11:50:43.973921 RX Vref 0 -> 0, step: 1
6944 11:50:43.974350
6945 11:50:43.974689 RX Delay -410 -> 252, step: 16
6946 11:50:43.980502 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6947 11:50:43.983776 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6948 11:50:43.986908 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6949 11:50:43.993476 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6950 11:50:43.996739 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6951 11:50:44.000277 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6952 11:50:44.003085 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6953 11:50:44.010183 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6954 11:50:44.013082 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6955 11:50:44.016264 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6956 11:50:44.020174 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6957 11:50:44.026661 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6958 11:50:44.029938 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6959 11:50:44.033302 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6960 11:50:44.036568 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6961 11:50:44.043006 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6962 11:50:44.043101 ==
6963 11:50:44.046063 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 11:50:44.049652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 11:50:44.049753 ==
6966 11:50:44.049839 DQS Delay:
6967 11:50:44.052799 DQS0 = 51, DQS1 = 51
6968 11:50:44.052877 DQM Delay:
6969 11:50:44.056088 DQM0 = 20, DQM1 = 13
6970 11:50:44.056172 DQ Delay:
6971 11:50:44.059258 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6972 11:50:44.062707 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6973 11:50:44.065972 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6974 11:50:44.069585 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6975 11:50:44.069669
6976 11:50:44.069734
6977 11:50:44.069794 ==
6978 11:50:44.072653 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 11:50:44.076342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 11:50:44.080134 ==
6981 11:50:44.080559
6982 11:50:44.080895
6983 11:50:44.081205 TX Vref Scan disable
6984 11:50:44.082837 == TX Byte 0 ==
6985 11:50:44.086430 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6986 11:50:44.089802 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6987 11:50:44.092529 == TX Byte 1 ==
6988 11:50:44.096668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6989 11:50:44.099335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6990 11:50:44.099767 ==
6991 11:50:44.102690 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 11:50:44.109195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 11:50:44.109805 ==
6994 11:50:44.110152
6995 11:50:44.110469
6996 11:50:44.110767 TX Vref Scan disable
6997 11:50:44.112699 == TX Byte 0 ==
6998 11:50:44.115818 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6999 11:50:44.119532 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7000 11:50:44.123096 == TX Byte 1 ==
7001 11:50:44.125530 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7002 11:50:44.129852 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7003 11:50:44.130277
7004 11:50:44.132715 [DATLAT]
7005 11:50:44.133154 Freq=400, CH1 RK1
7006 11:50:44.133538
7007 11:50:44.135661 DATLAT Default: 0xe
7008 11:50:44.136203 0, 0xFFFF, sum = 0
7009 11:50:44.138966 1, 0xFFFF, sum = 0
7010 11:50:44.139395 2, 0xFFFF, sum = 0
7011 11:50:44.142624 3, 0xFFFF, sum = 0
7012 11:50:44.143088 4, 0xFFFF, sum = 0
7013 11:50:44.145998 5, 0xFFFF, sum = 0
7014 11:50:44.146423 6, 0xFFFF, sum = 0
7015 11:50:44.149127 7, 0xFFFF, sum = 0
7016 11:50:44.149593 8, 0xFFFF, sum = 0
7017 11:50:44.152097 9, 0xFFFF, sum = 0
7018 11:50:44.152521 10, 0xFFFF, sum = 0
7019 11:50:44.155676 11, 0xFFFF, sum = 0
7020 11:50:44.156104 12, 0xFFFF, sum = 0
7021 11:50:44.159276 13, 0x0, sum = 1
7022 11:50:44.159702 14, 0x0, sum = 2
7023 11:50:44.162945 15, 0x0, sum = 3
7024 11:50:44.163470 16, 0x0, sum = 4
7025 11:50:44.165724 best_step = 14
7026 11:50:44.166141
7027 11:50:44.166472 ==
7028 11:50:44.169067 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 11:50:44.172578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 11:50:44.173104 ==
7031 11:50:44.175752 RX Vref Scan: 0
7032 11:50:44.176351
7033 11:50:44.176711 RX Vref 0 -> 0, step: 1
7034 11:50:44.177025
7035 11:50:44.179611 RX Delay -343 -> 252, step: 8
7036 11:50:44.187245 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7037 11:50:44.190709 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7038 11:50:44.193833 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7039 11:50:44.200110 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7040 11:50:44.203814 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7041 11:50:44.207235 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7042 11:50:44.209932 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7043 11:50:44.216616 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7044 11:50:44.219689 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7045 11:50:44.222874 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7046 11:50:44.226574 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7047 11:50:44.233300 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7048 11:50:44.236373 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7049 11:50:44.239590 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7050 11:50:44.246689 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7051 11:50:44.250351 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7052 11:50:44.250922 ==
7053 11:50:44.253173 Dram Type= 6, Freq= 0, CH_1, rank 1
7054 11:50:44.256391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7055 11:50:44.257026 ==
7056 11:50:44.260044 DQS Delay:
7057 11:50:44.260543 DQS0 = 44, DQS1 = 56
7058 11:50:44.260910 DQM Delay:
7059 11:50:44.262923 DQM0 = 9, DQM1 = 11
7060 11:50:44.263386 DQ Delay:
7061 11:50:44.266015 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7062 11:50:44.269620 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7063 11:50:44.272982 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7064 11:50:44.276001 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7065 11:50:44.276529
7066 11:50:44.276902
7067 11:50:44.282448 [DQSOSCAuto] RK1, (LSB)MR18= 0x6251, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7068 11:50:44.285975 CH1 RK1: MR19=C0C, MR18=6251
7069 11:50:44.292967 CH1_RK1: MR19=0xC0C, MR18=0x6251, DQSOSC=397, MR23=63, INC=374, DEC=249
7070 11:50:44.295863 [RxdqsGatingPostProcess] freq 400
7071 11:50:44.302476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7072 11:50:44.306082 best DQS0 dly(2T, 0.5T) = (0, 10)
7073 11:50:44.309628 best DQS1 dly(2T, 0.5T) = (0, 10)
7074 11:50:44.312811 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7075 11:50:44.315980 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7076 11:50:44.316504 best DQS0 dly(2T, 0.5T) = (0, 10)
7077 11:50:44.318989 best DQS1 dly(2T, 0.5T) = (0, 10)
7078 11:50:44.322369 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7079 11:50:44.326146 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7080 11:50:44.329356 Pre-setting of DQS Precalculation
7081 11:50:44.336276 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7082 11:50:44.342217 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7083 11:50:44.349001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7084 11:50:44.349546
7085 11:50:44.349922
7086 11:50:44.352106 [Calibration Summary] 800 Mbps
7087 11:50:44.352665 CH 0, Rank 0
7088 11:50:44.355109 SW Impedance : PASS
7089 11:50:44.358461 DUTY Scan : NO K
7090 11:50:44.358933 ZQ Calibration : PASS
7091 11:50:44.362909 Jitter Meter : NO K
7092 11:50:44.365552 CBT Training : PASS
7093 11:50:44.366020 Write leveling : PASS
7094 11:50:44.368712 RX DQS gating : PASS
7095 11:50:44.372190 RX DQ/DQS(RDDQC) : PASS
7096 11:50:44.372757 TX DQ/DQS : PASS
7097 11:50:44.375620 RX DATLAT : PASS
7098 11:50:44.378250 RX DQ/DQS(Engine): PASS
7099 11:50:44.378720 TX OE : NO K
7100 11:50:44.381491 All Pass.
7101 11:50:44.381972
7102 11:50:44.382345 CH 0, Rank 1
7103 11:50:44.384929 SW Impedance : PASS
7104 11:50:44.385549 DUTY Scan : NO K
7105 11:50:44.388596 ZQ Calibration : PASS
7106 11:50:44.391613 Jitter Meter : NO K
7107 11:50:44.392082 CBT Training : PASS
7108 11:50:44.394729 Write leveling : NO K
7109 11:50:44.398131 RX DQS gating : PASS
7110 11:50:44.398599 RX DQ/DQS(RDDQC) : PASS
7111 11:50:44.401134 TX DQ/DQS : PASS
7112 11:50:44.405140 RX DATLAT : PASS
7113 11:50:44.405752 RX DQ/DQS(Engine): PASS
7114 11:50:44.408190 TX OE : NO K
7115 11:50:44.408757 All Pass.
7116 11:50:44.409134
7117 11:50:44.412469 CH 1, Rank 0
7118 11:50:44.413085 SW Impedance : PASS
7119 11:50:44.415004 DUTY Scan : NO K
7120 11:50:44.417686 ZQ Calibration : PASS
7121 11:50:44.418246 Jitter Meter : NO K
7122 11:50:44.421344 CBT Training : PASS
7123 11:50:44.424489 Write leveling : PASS
7124 11:50:44.425046 RX DQS gating : PASS
7125 11:50:44.428007 RX DQ/DQS(RDDQC) : PASS
7126 11:50:44.430965 TX DQ/DQS : PASS
7127 11:50:44.431529 RX DATLAT : PASS
7128 11:50:44.434263 RX DQ/DQS(Engine): PASS
7129 11:50:44.434730 TX OE : NO K
7130 11:50:44.437586 All Pass.
7131 11:50:44.438146
7132 11:50:44.438518 CH 1, Rank 1
7133 11:50:44.440592 SW Impedance : PASS
7134 11:50:44.441057 DUTY Scan : NO K
7135 11:50:44.443901 ZQ Calibration : PASS
7136 11:50:44.447625 Jitter Meter : NO K
7137 11:50:44.448094 CBT Training : PASS
7138 11:50:44.451432 Write leveling : NO K
7139 11:50:44.454742 RX DQS gating : PASS
7140 11:50:44.455305 RX DQ/DQS(RDDQC) : PASS
7141 11:50:44.457360 TX DQ/DQS : PASS
7142 11:50:44.460704 RX DATLAT : PASS
7143 11:50:44.461169 RX DQ/DQS(Engine): PASS
7144 11:50:44.464418 TX OE : NO K
7145 11:50:44.465009 All Pass.
7146 11:50:44.465391
7147 11:50:44.467292 DramC Write-DBI off
7148 11:50:44.471551 PER_BANK_REFRESH: Hybrid Mode
7149 11:50:44.472114 TX_TRACKING: ON
7150 11:50:44.480787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7151 11:50:44.483714 [FAST_K] Save calibration result to emmc
7152 11:50:44.487393 dramc_set_vcore_voltage set vcore to 725000
7153 11:50:44.490945 Read voltage for 1600, 0
7154 11:50:44.491509 Vio18 = 0
7155 11:50:44.491888 Vcore = 725000
7156 11:50:44.493646 Vdram = 0
7157 11:50:44.494110 Vddq = 0
7158 11:50:44.494481 Vmddr = 0
7159 11:50:44.500714 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7160 11:50:44.503941 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7161 11:50:44.506811 MEM_TYPE=3, freq_sel=13
7162 11:50:44.510232 sv_algorithm_assistance_LP4_3733
7163 11:50:44.513452 ============ PULL DRAM RESETB DOWN ============
7164 11:50:44.520292 ========== PULL DRAM RESETB DOWN end =========
7165 11:50:44.523780 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 11:50:44.527224 ===================================
7167 11:50:44.530260 LPDDR4 DRAM CONFIGURATION
7168 11:50:44.533492 ===================================
7169 11:50:44.533968 EX_ROW_EN[0] = 0x0
7170 11:50:44.536723 EX_ROW_EN[1] = 0x0
7171 11:50:44.537187 LP4Y_EN = 0x0
7172 11:50:44.540116 WORK_FSP = 0x1
7173 11:50:44.540581 WL = 0x5
7174 11:50:44.543565 RL = 0x5
7175 11:50:44.544033 BL = 0x2
7176 11:50:44.546706 RPST = 0x0
7177 11:50:44.549790 RD_PRE = 0x0
7178 11:50:44.550258 WR_PRE = 0x1
7179 11:50:44.552847 WR_PST = 0x1
7180 11:50:44.553313 DBI_WR = 0x0
7181 11:50:44.556165 DBI_RD = 0x0
7182 11:50:44.556632 OTF = 0x1
7183 11:50:44.559971 ===================================
7184 11:50:44.562997 ===================================
7185 11:50:44.566139 ANA top config
7186 11:50:44.566567 ===================================
7187 11:50:44.569489 DLL_ASYNC_EN = 0
7188 11:50:44.573046 ALL_SLAVE_EN = 0
7189 11:50:44.576559 NEW_RANK_MODE = 1
7190 11:50:44.580507 DLL_IDLE_MODE = 1
7191 11:50:44.581036 LP45_APHY_COMB_EN = 1
7192 11:50:44.582845 TX_ODT_DIS = 0
7193 11:50:44.586324 NEW_8X_MODE = 1
7194 11:50:44.589704 ===================================
7195 11:50:44.593194 ===================================
7196 11:50:44.595757 data_rate = 3200
7197 11:50:44.599248 CKR = 1
7198 11:50:44.603083 DQ_P2S_RATIO = 8
7199 11:50:44.605865 ===================================
7200 11:50:44.606463 CA_P2S_RATIO = 8
7201 11:50:44.609248 DQ_CA_OPEN = 0
7202 11:50:44.612186 DQ_SEMI_OPEN = 0
7203 11:50:44.615835 CA_SEMI_OPEN = 0
7204 11:50:44.618763 CA_FULL_RATE = 0
7205 11:50:44.622273 DQ_CKDIV4_EN = 0
7206 11:50:44.622702 CA_CKDIV4_EN = 0
7207 11:50:44.625344 CA_PREDIV_EN = 0
7208 11:50:44.628490 PH8_DLY = 12
7209 11:50:44.632735 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7210 11:50:44.635656 DQ_AAMCK_DIV = 4
7211 11:50:44.639086 CA_AAMCK_DIV = 4
7212 11:50:44.639406 CA_ADMCK_DIV = 4
7213 11:50:44.642169 DQ_TRACK_CA_EN = 0
7214 11:50:44.645902 CA_PICK = 1600
7215 11:50:44.649777 CA_MCKIO = 1600
7216 11:50:44.651680 MCKIO_SEMI = 0
7217 11:50:44.655551 PLL_FREQ = 3068
7218 11:50:44.658647 DQ_UI_PI_RATIO = 32
7219 11:50:44.662356 CA_UI_PI_RATIO = 0
7220 11:50:44.665481 ===================================
7221 11:50:44.668684 ===================================
7222 11:50:44.669148 memory_type:LPDDR4
7223 11:50:44.671819 GP_NUM : 10
7224 11:50:44.675419 SRAM_EN : 1
7225 11:50:44.676074 MD32_EN : 0
7226 11:50:44.678342 ===================================
7227 11:50:44.681630 [ANA_INIT] >>>>>>>>>>>>>>
7228 11:50:44.685519 <<<<<< [CONFIGURE PHASE]: ANA_TX
7229 11:50:44.688434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7230 11:50:44.692074 ===================================
7231 11:50:44.695085 data_rate = 3200,PCW = 0X7600
7232 11:50:44.698233 ===================================
7233 11:50:44.701552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7234 11:50:44.704939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7235 11:50:44.711249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7236 11:50:44.715132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7237 11:50:44.718563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7238 11:50:44.721898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7239 11:50:44.725038 [ANA_INIT] flow start
7240 11:50:44.728515 [ANA_INIT] PLL >>>>>>>>
7241 11:50:44.729034 [ANA_INIT] PLL <<<<<<<<
7242 11:50:44.731780 [ANA_INIT] MIDPI >>>>>>>>
7243 11:50:44.734469 [ANA_INIT] MIDPI <<<<<<<<
7244 11:50:44.738052 [ANA_INIT] DLL >>>>>>>>
7245 11:50:44.738578 [ANA_INIT] DLL <<<<<<<<
7246 11:50:44.741263 [ANA_INIT] flow end
7247 11:50:44.744484 ============ LP4 DIFF to SE enter ============
7248 11:50:44.748701 ============ LP4 DIFF to SE exit ============
7249 11:50:44.751064 [ANA_INIT] <<<<<<<<<<<<<
7250 11:50:44.754192 [Flow] Enable top DCM control >>>>>
7251 11:50:44.758160 [Flow] Enable top DCM control <<<<<
7252 11:50:44.760861 Enable DLL master slave shuffle
7253 11:50:44.767704 ==============================================================
7254 11:50:44.768172 Gating Mode config
7255 11:50:44.774212 ==============================================================
7256 11:50:44.774684 Config description:
7257 11:50:44.784179 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7258 11:50:44.790812 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7259 11:50:44.797778 SELPH_MODE 0: By rank 1: By Phase
7260 11:50:44.800260 ==============================================================
7261 11:50:44.803645 GAT_TRACK_EN = 1
7262 11:50:44.807492 RX_GATING_MODE = 2
7263 11:50:44.810374 RX_GATING_TRACK_MODE = 2
7264 11:50:44.813784 SELPH_MODE = 1
7265 11:50:44.817736 PICG_EARLY_EN = 1
7266 11:50:44.820203 VALID_LAT_VALUE = 1
7267 11:50:44.827472 ==============================================================
7268 11:50:44.830330 Enter into Gating configuration >>>>
7269 11:50:44.833912 Exit from Gating configuration <<<<
7270 11:50:44.837160 Enter into DVFS_PRE_config >>>>>
7271 11:50:44.846679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7272 11:50:44.850249 Exit from DVFS_PRE_config <<<<<
7273 11:50:44.853173 Enter into PICG configuration >>>>
7274 11:50:44.856902 Exit from PICG configuration <<<<
7275 11:50:44.859925 [RX_INPUT] configuration >>>>>
7276 11:50:44.860492 [RX_INPUT] configuration <<<<<
7277 11:50:44.866409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7278 11:50:44.873848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7279 11:50:44.879458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7280 11:50:44.882660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7281 11:50:44.889378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 11:50:44.896159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 11:50:44.899173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7284 11:50:44.906295 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7285 11:50:44.909592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7286 11:50:44.912530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7287 11:50:44.916411 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7288 11:50:44.922257 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7289 11:50:44.925855 ===================================
7290 11:50:44.926615 LPDDR4 DRAM CONFIGURATION
7291 11:50:44.929354 ===================================
7292 11:50:44.932626 EX_ROW_EN[0] = 0x0
7293 11:50:44.935584 EX_ROW_EN[1] = 0x0
7294 11:50:44.936047 LP4Y_EN = 0x0
7295 11:50:44.938775 WORK_FSP = 0x1
7296 11:50:44.939295 WL = 0x5
7297 11:50:44.941986 RL = 0x5
7298 11:50:44.942448 BL = 0x2
7299 11:50:44.945105 RPST = 0x0
7300 11:50:44.945596 RD_PRE = 0x0
7301 11:50:44.948713 WR_PRE = 0x1
7302 11:50:44.949327 WR_PST = 0x1
7303 11:50:44.952050 DBI_WR = 0x0
7304 11:50:44.952512 DBI_RD = 0x0
7305 11:50:44.955426 OTF = 0x1
7306 11:50:44.958812 ===================================
7307 11:50:44.961620 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7308 11:50:44.965372 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7309 11:50:44.972342 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7310 11:50:44.975679 ===================================
7311 11:50:44.978574 LPDDR4 DRAM CONFIGURATION
7312 11:50:44.981397 ===================================
7313 11:50:44.981915 EX_ROW_EN[0] = 0x10
7314 11:50:44.984646 EX_ROW_EN[1] = 0x0
7315 11:50:44.985109 LP4Y_EN = 0x0
7316 11:50:44.988473 WORK_FSP = 0x1
7317 11:50:44.989037 WL = 0x5
7318 11:50:44.991846 RL = 0x5
7319 11:50:44.992444 BL = 0x2
7320 11:50:44.995192 RPST = 0x0
7321 11:50:44.995756 RD_PRE = 0x0
7322 11:50:44.998019 WR_PRE = 0x1
7323 11:50:44.998550 WR_PST = 0x1
7324 11:50:45.001294 DBI_WR = 0x0
7325 11:50:45.004967 DBI_RD = 0x0
7326 11:50:45.005579 OTF = 0x1
7327 11:50:45.008118 ===================================
7328 11:50:45.015127 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7329 11:50:45.015691 ==
7330 11:50:45.018357 Dram Type= 6, Freq= 0, CH_0, rank 0
7331 11:50:45.021984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 11:50:45.022554 ==
7333 11:50:45.024873 [Duty_Offset_Calibration]
7334 11:50:45.025473 B0:1 B1:-1 CA:0
7335 11:50:45.025856
7336 11:50:45.028396 [DutyScan_Calibration_Flow] k_type=0
7337 11:50:45.039780
7338 11:50:45.040339 ==CLK 0==
7339 11:50:45.042803 Final CLK duty delay cell = 0
7340 11:50:45.046057 [0] MAX Duty = 5125%(X100), DQS PI = 20
7341 11:50:45.049179 [0] MIN Duty = 4907%(X100), DQS PI = 6
7342 11:50:45.052257 [0] AVG Duty = 5016%(X100)
7343 11:50:45.052722
7344 11:50:45.056007 CH0 CLK Duty spec in!! Max-Min= 218%
7345 11:50:45.059180 [DutyScan_Calibration_Flow] ====Done====
7346 11:50:45.059746
7347 11:50:45.061968 [DutyScan_Calibration_Flow] k_type=1
7348 11:50:45.079115
7349 11:50:45.079677 ==DQS 0 ==
7350 11:50:45.081391 Final DQS duty delay cell = -4
7351 11:50:45.085061 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7352 11:50:45.088800 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7353 11:50:45.092005 [-4] AVG Duty = 4922%(X100)
7354 11:50:45.092613
7355 11:50:45.092994 ==DQS 1 ==
7356 11:50:45.094741 Final DQS duty delay cell = 0
7357 11:50:45.098790 [0] MAX Duty = 5156%(X100), DQS PI = 0
7358 11:50:45.101058 [0] MIN Duty = 5031%(X100), DQS PI = 18
7359 11:50:45.104610 [0] AVG Duty = 5093%(X100)
7360 11:50:45.105072
7361 11:50:45.107792 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7362 11:50:45.108259
7363 11:50:45.110860 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7364 11:50:45.115286 [DutyScan_Calibration_Flow] ====Done====
7365 11:50:45.115751
7366 11:50:45.117688 [DutyScan_Calibration_Flow] k_type=3
7367 11:50:45.135909
7368 11:50:45.136417 ==DQM 0 ==
7369 11:50:45.139286 Final DQM duty delay cell = 0
7370 11:50:45.142097 [0] MAX Duty = 5124%(X100), DQS PI = 20
7371 11:50:45.145801 [0] MIN Duty = 4907%(X100), DQS PI = 10
7372 11:50:45.149229 [0] AVG Duty = 5015%(X100)
7373 11:50:45.149977
7374 11:50:45.150628 ==DQM 1 ==
7375 11:50:45.152444 Final DQM duty delay cell = 0
7376 11:50:45.155625 [0] MAX Duty = 5000%(X100), DQS PI = 4
7377 11:50:45.158781 [0] MIN Duty = 4782%(X100), DQS PI = 22
7378 11:50:45.162256 [0] AVG Duty = 4891%(X100)
7379 11:50:45.162676
7380 11:50:45.165719 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7381 11:50:45.166171
7382 11:50:45.168640 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7383 11:50:45.172051 [DutyScan_Calibration_Flow] ====Done====
7384 11:50:45.172474
7385 11:50:45.175597 [DutyScan_Calibration_Flow] k_type=2
7386 11:50:45.191879
7387 11:50:45.192320 ==DQ 0 ==
7388 11:50:45.195420 Final DQ duty delay cell = -4
7389 11:50:45.199110 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7390 11:50:45.202103 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7391 11:50:45.205269 [-4] AVG Duty = 4953%(X100)
7392 11:50:45.205729
7393 11:50:45.206066 ==DQ 1 ==
7394 11:50:45.208547 Final DQ duty delay cell = 0
7395 11:50:45.212289 [0] MAX Duty = 5125%(X100), DQS PI = 48
7396 11:50:45.215812 [0] MIN Duty = 5000%(X100), DQS PI = 38
7397 11:50:45.218737 [0] AVG Duty = 5062%(X100)
7398 11:50:45.219155
7399 11:50:45.222275 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7400 11:50:45.222792
7401 11:50:45.225370 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7402 11:50:45.228530 [DutyScan_Calibration_Flow] ====Done====
7403 11:50:45.229091 ==
7404 11:50:45.232134 Dram Type= 6, Freq= 0, CH_1, rank 0
7405 11:50:45.234878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7406 11:50:45.235301 ==
7407 11:50:45.238385 [Duty_Offset_Calibration]
7408 11:50:45.238895 B0:-1 B1:1 CA:2
7409 11:50:45.239224
7410 11:50:45.241815 [DutyScan_Calibration_Flow] k_type=0
7411 11:50:45.253901
7412 11:50:45.254454 ==CLK 0==
7413 11:50:45.256848 Final CLK duty delay cell = 0
7414 11:50:45.259626 [0] MAX Duty = 5187%(X100), DQS PI = 22
7415 11:50:45.263144 [0] MIN Duty = 4969%(X100), DQS PI = 0
7416 11:50:45.263608 [0] AVG Duty = 5078%(X100)
7417 11:50:45.266153
7418 11:50:45.269639 CH1 CLK Duty spec in!! Max-Min= 218%
7419 11:50:45.272666 [DutyScan_Calibration_Flow] ====Done====
7420 11:50:45.273226
7421 11:50:45.276515 [DutyScan_Calibration_Flow] k_type=1
7422 11:50:45.292703
7423 11:50:45.293272 ==DQS 0 ==
7424 11:50:45.295998 Final DQS duty delay cell = 0
7425 11:50:45.299631 [0] MAX Duty = 5124%(X100), DQS PI = 16
7426 11:50:45.302359 [0] MIN Duty = 4938%(X100), DQS PI = 8
7427 11:50:45.305964 [0] AVG Duty = 5031%(X100)
7428 11:50:45.306530
7429 11:50:45.306903 ==DQS 1 ==
7430 11:50:45.309388 Final DQS duty delay cell = 0
7431 11:50:45.312487 [0] MAX Duty = 5124%(X100), DQS PI = 26
7432 11:50:45.315517 [0] MIN Duty = 4969%(X100), DQS PI = 54
7433 11:50:45.318891 [0] AVG Duty = 5046%(X100)
7434 11:50:45.319353
7435 11:50:45.322392 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7436 11:50:45.322858
7437 11:50:45.325615 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7438 11:50:45.328820 [DutyScan_Calibration_Flow] ====Done====
7439 11:50:45.329287
7440 11:50:45.332737 [DutyScan_Calibration_Flow] k_type=3
7441 11:50:45.349452
7442 11:50:45.350085 ==DQM 0 ==
7443 11:50:45.352799 Final DQM duty delay cell = 0
7444 11:50:45.356543 [0] MAX Duty = 5218%(X100), DQS PI = 18
7445 11:50:45.360044 [0] MIN Duty = 5031%(X100), DQS PI = 8
7446 11:50:45.362501 [0] AVG Duty = 5124%(X100)
7447 11:50:45.362968
7448 11:50:45.363333 ==DQM 1 ==
7449 11:50:45.365996 Final DQM duty delay cell = 0
7450 11:50:45.369758 [0] MAX Duty = 5156%(X100), DQS PI = 0
7451 11:50:45.373253 [0] MIN Duty = 4969%(X100), DQS PI = 32
7452 11:50:45.375594 [0] AVG Duty = 5062%(X100)
7453 11:50:45.376059
7454 11:50:45.379196 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7455 11:50:45.379762
7456 11:50:45.382015 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7457 11:50:45.385304 [DutyScan_Calibration_Flow] ====Done====
7458 11:50:45.385819
7459 11:50:45.389041 [DutyScan_Calibration_Flow] k_type=2
7460 11:50:45.406314
7461 11:50:45.406873 ==DQ 0 ==
7462 11:50:45.409915 Final DQ duty delay cell = 0
7463 11:50:45.412696 [0] MAX Duty = 5156%(X100), DQS PI = 30
7464 11:50:45.416638 [0] MIN Duty = 4906%(X100), DQS PI = 10
7465 11:50:45.419556 [0] AVG Duty = 5031%(X100)
7466 11:50:45.420116
7467 11:50:45.420487 ==DQ 1 ==
7468 11:50:45.422652 Final DQ duty delay cell = 0
7469 11:50:45.426495 [0] MAX Duty = 5156%(X100), DQS PI = 10
7470 11:50:45.429976 [0] MIN Duty = 4969%(X100), DQS PI = 54
7471 11:50:45.430572 [0] AVG Duty = 5062%(X100)
7472 11:50:45.432319
7473 11:50:45.435890 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7474 11:50:45.436503
7475 11:50:45.439067 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7476 11:50:45.442103 [DutyScan_Calibration_Flow] ====Done====
7477 11:50:45.445711 nWR fixed to 30
7478 11:50:45.449109 [ModeRegInit_LP4] CH0 RK0
7479 11:50:45.449712 [ModeRegInit_LP4] CH0 RK1
7480 11:50:45.452320 [ModeRegInit_LP4] CH1 RK0
7481 11:50:45.455652 [ModeRegInit_LP4] CH1 RK1
7482 11:50:45.456216 match AC timing 5
7483 11:50:45.462031 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7484 11:50:45.465831 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7485 11:50:45.468629 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7486 11:50:45.475170 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7487 11:50:45.478783 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7488 11:50:45.479362 [MiockJmeterHQA]
7489 11:50:45.479736
7490 11:50:45.481916 [DramcMiockJmeter] u1RxGatingPI = 0
7491 11:50:45.485197 0 : 4366, 4140
7492 11:50:45.485828 4 : 4363, 4137
7493 11:50:45.488899 8 : 4252, 4027
7494 11:50:45.489372 12 : 4252, 4027
7495 11:50:45.492049 16 : 4253, 4027
7496 11:50:45.492522 20 : 4255, 4029
7497 11:50:45.492898 24 : 4363, 4138
7498 11:50:45.495027 28 : 4252, 4027
7499 11:50:45.495456 32 : 4253, 4027
7500 11:50:45.498074 36 : 4252, 4027
7501 11:50:45.498505 40 : 4252, 4027
7502 11:50:45.501663 44 : 4253, 4026
7503 11:50:45.502093 48 : 4363, 4138
7504 11:50:45.505108 52 : 4363, 4138
7505 11:50:45.505680 56 : 4252, 4027
7506 11:50:45.506031 60 : 4252, 4027
7507 11:50:45.508878 64 : 4253, 4027
7508 11:50:45.509447 68 : 4250, 4027
7509 11:50:45.511994 72 : 4252, 4027
7510 11:50:45.512519 76 : 4361, 4137
7511 11:50:45.515425 80 : 4252, 4027
7512 11:50:45.515950 84 : 4250, 4026
7513 11:50:45.518318 88 : 4250, 4027
7514 11:50:45.518843 92 : 4250, 438
7515 11:50:45.519211 96 : 4250, 0
7516 11:50:45.521681 100 : 4250, 0
7517 11:50:45.522343 104 : 4250, 0
7518 11:50:45.522697 108 : 4361, 0
7519 11:50:45.524949 112 : 4250, 0
7520 11:50:45.525521 116 : 4360, 0
7521 11:50:45.528149 120 : 4250, 0
7522 11:50:45.528675 124 : 4361, 0
7523 11:50:45.529022 128 : 4250, 0
7524 11:50:45.531706 132 : 4250, 0
7525 11:50:45.532228 136 : 4250, 0
7526 11:50:45.535107 140 : 4250, 0
7527 11:50:45.535634 144 : 4253, 0
7528 11:50:45.535981 148 : 4250, 0
7529 11:50:45.537847 152 : 4250, 0
7530 11:50:45.538276 156 : 4253, 0
7531 11:50:45.541583 160 : 4360, 0
7532 11:50:45.542112 164 : 4250, 0
7533 11:50:45.542457 168 : 4360, 0
7534 11:50:45.545634 172 : 4250, 0
7535 11:50:45.546162 176 : 4361, 0
7536 11:50:45.548658 180 : 4361, 0
7537 11:50:45.549128 184 : 4250, 0
7538 11:50:45.549763 188 : 4250, 0
7539 11:50:45.551588 192 : 4250, 0
7540 11:50:45.552020 196 : 4250, 0
7541 11:50:45.552365 200 : 4250, 0
7542 11:50:45.554840 204 : 4250, 0
7543 11:50:45.555357 208 : 4253, 0
7544 11:50:45.557965 212 : 4361, 0
7545 11:50:45.558394 216 : 4361, 0
7546 11:50:45.558733 220 : 4360, 0
7547 11:50:45.561527 224 : 4249, 294
7548 11:50:45.561961 228 : 4250, 3694
7549 11:50:45.564689 232 : 4360, 4137
7550 11:50:45.565119 236 : 4250, 4027
7551 11:50:45.567894 240 : 4249, 4027
7552 11:50:45.568323 244 : 4360, 4138
7553 11:50:45.571078 248 : 4250, 4027
7554 11:50:45.571506 252 : 4252, 4027
7555 11:50:45.574506 256 : 4250, 4027
7556 11:50:45.575063 260 : 4250, 4027
7557 11:50:45.577986 264 : 4250, 4027
7558 11:50:45.578413 268 : 4250, 4027
7559 11:50:45.581076 272 : 4360, 4138
7560 11:50:45.581536 276 : 4250, 4027
7561 11:50:45.581889 280 : 4250, 4027
7562 11:50:45.584079 284 : 4361, 4137
7563 11:50:45.584506 288 : 4250, 4027
7564 11:50:45.587395 292 : 4250, 4027
7565 11:50:45.587889 296 : 4360, 4137
7566 11:50:45.590883 300 : 4250, 4027
7567 11:50:45.591314 304 : 4250, 4027
7568 11:50:45.594098 308 : 4249, 4027
7569 11:50:45.594522 312 : 4250, 4027
7570 11:50:45.597367 316 : 4250, 4027
7571 11:50:45.597844 320 : 4250, 4027
7572 11:50:45.600701 324 : 4360, 4138
7573 11:50:45.601128 328 : 4250, 4027
7574 11:50:45.604207 332 : 4250, 4026
7575 11:50:45.604738 336 : 4361, 3871
7576 11:50:45.607568 340 : 4250, 2107
7577 11:50:45.607998
7578 11:50:45.608331 MIOCK jitter meter ch=0
7579 11:50:45.608644
7580 11:50:45.610623 1T = (340-92) = 248 dly cells
7581 11:50:45.617644 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7582 11:50:45.618165 ==
7583 11:50:45.621133 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 11:50:45.623479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 11:50:45.623933 ==
7586 11:50:45.630136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7587 11:50:45.634194 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7588 11:50:45.636637 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7589 11:50:45.643672 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7590 11:50:45.653819 [CA 0] Center 43 (13~74) winsize 62
7591 11:50:45.657236 [CA 1] Center 43 (13~74) winsize 62
7592 11:50:45.660148 [CA 2] Center 39 (10~69) winsize 60
7593 11:50:45.663537 [CA 3] Center 39 (9~69) winsize 61
7594 11:50:45.666142 [CA 4] Center 37 (8~66) winsize 59
7595 11:50:45.669825 [CA 5] Center 36 (7~66) winsize 60
7596 11:50:45.670573
7597 11:50:45.673157 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7598 11:50:45.673611
7599 11:50:45.679928 [CATrainingPosCal] consider 1 rank data
7600 11:50:45.680398 u2DelayCellTimex100 = 262/100 ps
7601 11:50:45.686403 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 11:50:45.689285 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7603 11:50:45.692761 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7604 11:50:45.696181 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7605 11:50:45.699553 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7606 11:50:45.702782 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7607 11:50:45.703255
7608 11:50:45.705942 CA PerBit enable=1, Macro0, CA PI delay=36
7609 11:50:45.706530
7610 11:50:45.709485 [CBTSetCACLKResult] CA Dly = 36
7611 11:50:45.712601 CS Dly: 12 (0~43)
7612 11:50:45.715953 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7613 11:50:45.719393 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7614 11:50:45.719920 ==
7615 11:50:45.722211 Dram Type= 6, Freq= 0, CH_0, rank 1
7616 11:50:45.729211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:50:45.729783 ==
7618 11:50:45.733468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7619 11:50:45.739423 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7620 11:50:45.742093 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7621 11:50:45.749288 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7622 11:50:45.757309 [CA 0] Center 43 (13~74) winsize 62
7623 11:50:45.761117 [CA 1] Center 44 (14~74) winsize 61
7624 11:50:45.763720 [CA 2] Center 38 (9~68) winsize 60
7625 11:50:45.766686 [CA 3] Center 38 (9~68) winsize 60
7626 11:50:45.769890 [CA 4] Center 36 (7~66) winsize 60
7627 11:50:45.773301 [CA 5] Center 36 (7~66) winsize 60
7628 11:50:45.773826
7629 11:50:45.777120 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7630 11:50:45.777629
7631 11:50:45.783380 [CATrainingPosCal] consider 2 rank data
7632 11:50:45.783931 u2DelayCellTimex100 = 262/100 ps
7633 11:50:45.789882 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7634 11:50:45.793254 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7635 11:50:45.796791 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7636 11:50:45.800049 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7637 11:50:45.803051 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7638 11:50:45.806608 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7639 11:50:45.807171
7640 11:50:45.809513 CA PerBit enable=1, Macro0, CA PI delay=36
7641 11:50:45.810008
7642 11:50:45.813242 [CBTSetCACLKResult] CA Dly = 36
7643 11:50:45.816207 CS Dly: 12 (0~44)
7644 11:50:45.819885 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7645 11:50:45.823197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7646 11:50:45.823674
7647 11:50:45.826123 ----->DramcWriteLeveling(PI) begin...
7648 11:50:45.826597 ==
7649 11:50:45.829393 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:50:45.836151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:50:45.836706 ==
7652 11:50:45.839859 Write leveling (Byte 0): 37 => 37
7653 11:50:45.842606 Write leveling (Byte 1): 27 => 27
7654 11:50:45.845772 DramcWriteLeveling(PI) end<-----
7655 11:50:45.846234
7656 11:50:45.846599 ==
7657 11:50:45.849624 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 11:50:45.852632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 11:50:45.853098 ==
7660 11:50:45.856603 [Gating] SW mode calibration
7661 11:50:45.862830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7662 11:50:45.869650 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7663 11:50:45.872655 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 11:50:45.876540 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 11:50:45.882479 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 11:50:45.885909 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7667 11:50:45.889009 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7668 11:50:45.895808 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7669 11:50:45.898795 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7670 11:50:45.902055 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 11:50:45.908507 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 11:50:45.912198 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 11:50:45.915372 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7674 11:50:45.922209 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7675 11:50:45.925312 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7676 11:50:45.928853 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7677 11:50:45.934916 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7678 11:50:45.938165 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 11:50:45.941665 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 11:50:45.948471 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 11:50:45.951766 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 11:50:45.954445 1 6 12 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7683 11:50:45.961644 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7684 11:50:45.964760 1 6 20 | B1->B0 | 2928 4646 | 1 0 | (0 0) (0 0)
7685 11:50:45.967981 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 11:50:45.974225 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 11:50:45.978169 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 11:50:45.981583 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 11:50:45.988297 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 11:50:45.991438 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 11:50:45.994686 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7692 11:50:45.998077 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 11:50:46.004099 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7694 11:50:46.007683 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 11:50:46.014073 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 11:50:46.017340 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 11:50:46.020554 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 11:50:46.027384 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 11:50:46.030607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 11:50:46.034072 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 11:50:46.040206 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 11:50:46.043280 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 11:50:46.047568 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 11:50:46.053950 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 11:50:46.056905 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 11:50:46.060160 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7707 11:50:46.063128 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7708 11:50:46.066417 Total UI for P1: 0, mck2ui 16
7709 11:50:46.069824 best dqsien dly found for B0: ( 1, 9, 12)
7710 11:50:46.076590 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7711 11:50:46.079874 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7712 11:50:46.083122 Total UI for P1: 0, mck2ui 16
7713 11:50:46.086220 best dqsien dly found for B1: ( 1, 9, 20)
7714 11:50:46.089644 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7715 11:50:46.092631 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7716 11:50:46.092739
7717 11:50:46.096918 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7718 11:50:46.102712 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7719 11:50:46.102796 [Gating] SW calibration Done
7720 11:50:46.105759 ==
7721 11:50:46.109762 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 11:50:46.113232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 11:50:46.113685 ==
7724 11:50:46.114033 RX Vref Scan: 0
7725 11:50:46.114389
7726 11:50:46.116503 RX Vref 0 -> 0, step: 1
7727 11:50:46.116935
7728 11:50:46.119774 RX Delay 0 -> 252, step: 8
7729 11:50:46.123299 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7730 11:50:46.125681 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7731 11:50:46.129595 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7732 11:50:46.135967 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7733 11:50:46.139178 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7734 11:50:46.142501 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7735 11:50:46.145992 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7736 11:50:46.149882 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7737 11:50:46.156115 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7738 11:50:46.159623 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7739 11:50:46.162961 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7740 11:50:46.165562 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7741 11:50:46.172309 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7742 11:50:46.176411 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7743 11:50:46.179020 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7744 11:50:46.182306 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7745 11:50:46.182773 ==
7746 11:50:46.185334 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 11:50:46.192333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 11:50:46.192754 ==
7749 11:50:46.193086 DQS Delay:
7750 11:50:46.193395 DQS0 = 0, DQS1 = 0
7751 11:50:46.196320 DQM Delay:
7752 11:50:46.196841 DQM0 = 136, DQM1 = 126
7753 11:50:46.198520 DQ Delay:
7754 11:50:46.202491 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7755 11:50:46.205265 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7756 11:50:46.208550 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7757 11:50:46.212094 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7758 11:50:46.212531
7759 11:50:46.212967
7760 11:50:46.213375 ==
7761 11:50:46.215107 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 11:50:46.221157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 11:50:46.221778 ==
7764 11:50:46.222253
7765 11:50:46.222663
7766 11:50:46.223067 TX Vref Scan disable
7767 11:50:46.224511 == TX Byte 0 ==
7768 11:50:46.228305 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7769 11:50:46.234480 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7770 11:50:46.234934 == TX Byte 1 ==
7771 11:50:46.237877 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7772 11:50:46.244239 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7773 11:50:46.244751 ==
7774 11:50:46.248312 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 11:50:46.251092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 11:50:46.251572 ==
7777 11:50:46.264733
7778 11:50:46.267856 TX Vref early break, caculate TX vref
7779 11:50:46.271521 TX Vref=16, minBit 6, minWin=22, winSum=369
7780 11:50:46.274379 TX Vref=18, minBit 1, minWin=23, winSum=385
7781 11:50:46.277564 TX Vref=20, minBit 1, minWin=23, winSum=390
7782 11:50:46.280940 TX Vref=22, minBit 1, minWin=24, winSum=404
7783 11:50:46.284196 TX Vref=24, minBit 0, minWin=25, winSum=412
7784 11:50:46.290827 TX Vref=26, minBit 1, minWin=25, winSum=420
7785 11:50:46.295098 TX Vref=28, minBit 0, minWin=25, winSum=416
7786 11:50:46.297496 TX Vref=30, minBit 0, minWin=24, winSum=409
7787 11:50:46.300684 TX Vref=32, minBit 0, minWin=24, winSum=400
7788 11:50:46.303921 TX Vref=34, minBit 7, minWin=23, winSum=390
7789 11:50:46.311101 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 26
7790 11:50:46.311647
7791 11:50:46.313822 Final TX Range 0 Vref 26
7792 11:50:46.314299
7793 11:50:46.314634 ==
7794 11:50:46.317308 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 11:50:46.320673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 11:50:46.321184 ==
7797 11:50:46.321638
7798 11:50:46.321991
7799 11:50:46.324120 TX Vref Scan disable
7800 11:50:46.330344 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7801 11:50:46.330766 == TX Byte 0 ==
7802 11:50:46.333763 u2DelayCellOfst[0]=11 cells (3 PI)
7803 11:50:46.336947 u2DelayCellOfst[1]=14 cells (4 PI)
7804 11:50:46.341039 u2DelayCellOfst[2]=11 cells (3 PI)
7805 11:50:46.343839 u2DelayCellOfst[3]=11 cells (3 PI)
7806 11:50:46.347343 u2DelayCellOfst[4]=11 cells (3 PI)
7807 11:50:46.350329 u2DelayCellOfst[5]=0 cells (0 PI)
7808 11:50:46.353680 u2DelayCellOfst[6]=14 cells (4 PI)
7809 11:50:46.356765 u2DelayCellOfst[7]=18 cells (5 PI)
7810 11:50:46.360315 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7811 11:50:46.363616 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7812 11:50:46.366770 == TX Byte 1 ==
7813 11:50:46.370226 u2DelayCellOfst[8]=0 cells (0 PI)
7814 11:50:46.373316 u2DelayCellOfst[9]=0 cells (0 PI)
7815 11:50:46.376707 u2DelayCellOfst[10]=3 cells (1 PI)
7816 11:50:46.379741 u2DelayCellOfst[11]=0 cells (0 PI)
7817 11:50:46.380187 u2DelayCellOfst[12]=11 cells (3 PI)
7818 11:50:46.383755 u2DelayCellOfst[13]=7 cells (2 PI)
7819 11:50:46.386191 u2DelayCellOfst[14]=14 cells (4 PI)
7820 11:50:46.389789 u2DelayCellOfst[15]=11 cells (3 PI)
7821 11:50:46.396385 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7822 11:50:46.399651 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7823 11:50:46.400132 DramC Write-DBI on
7824 11:50:46.402978 ==
7825 11:50:46.403470 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 11:50:46.409813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 11:50:46.410265 ==
7828 11:50:46.410599
7829 11:50:46.410967
7830 11:50:46.412765 TX Vref Scan disable
7831 11:50:46.413243 == TX Byte 0 ==
7832 11:50:46.419362 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7833 11:50:46.419967 == TX Byte 1 ==
7834 11:50:46.422591 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7835 11:50:46.426309 DramC Write-DBI off
7836 11:50:46.426822
7837 11:50:46.427265 [DATLAT]
7838 11:50:46.429353 Freq=1600, CH0 RK0
7839 11:50:46.429865
7840 11:50:46.430248 DATLAT Default: 0xf
7841 11:50:46.432972 0, 0xFFFF, sum = 0
7842 11:50:46.433481 1, 0xFFFF, sum = 0
7843 11:50:46.435857 2, 0xFFFF, sum = 0
7844 11:50:46.436428 3, 0xFFFF, sum = 0
7845 11:50:46.439369 4, 0xFFFF, sum = 0
7846 11:50:46.439825 5, 0xFFFF, sum = 0
7847 11:50:46.442623 6, 0xFFFF, sum = 0
7848 11:50:46.446250 7, 0xFFFF, sum = 0
7849 11:50:46.446894 8, 0xFFFF, sum = 0
7850 11:50:46.449507 9, 0xFFFF, sum = 0
7851 11:50:46.449981 10, 0xFFFF, sum = 0
7852 11:50:46.452814 11, 0xFFFF, sum = 0
7853 11:50:46.453305 12, 0xFFFF, sum = 0
7854 11:50:46.456513 13, 0xFFFF, sum = 0
7855 11:50:46.457172 14, 0x0, sum = 1
7856 11:50:46.459290 15, 0x0, sum = 2
7857 11:50:46.459872 16, 0x0, sum = 3
7858 11:50:46.462642 17, 0x0, sum = 4
7859 11:50:46.463236 best_step = 15
7860 11:50:46.463752
7861 11:50:46.464236 ==
7862 11:50:46.466051 Dram Type= 6, Freq= 0, CH_0, rank 0
7863 11:50:46.469482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7864 11:50:46.469947 ==
7865 11:50:46.473661 RX Vref Scan: 1
7866 11:50:46.474148
7867 11:50:46.475894 Set Vref Range= 24 -> 127
7868 11:50:46.476371
7869 11:50:46.476737 RX Vref 24 -> 127, step: 1
7870 11:50:46.479152
7871 11:50:46.479623 RX Delay 19 -> 252, step: 4
7872 11:50:46.480288
7873 11:50:46.482374 Set Vref, RX VrefLevel [Byte0]: 24
7874 11:50:46.485670 [Byte1]: 24
7875 11:50:46.489117
7876 11:50:46.489673 Set Vref, RX VrefLevel [Byte0]: 25
7877 11:50:46.492258 [Byte1]: 25
7878 11:50:46.497559
7879 11:50:46.498081 Set Vref, RX VrefLevel [Byte0]: 26
7880 11:50:46.499893 [Byte1]: 26
7881 11:50:46.504130
7882 11:50:46.504549 Set Vref, RX VrefLevel [Byte0]: 27
7883 11:50:46.507603 [Byte1]: 27
7884 11:50:46.511740
7885 11:50:46.512207 Set Vref, RX VrefLevel [Byte0]: 28
7886 11:50:46.516023 [Byte1]: 28
7887 11:50:46.519790
7888 11:50:46.520255 Set Vref, RX VrefLevel [Byte0]: 29
7889 11:50:46.523077 [Byte1]: 29
7890 11:50:46.527354
7891 11:50:46.527826 Set Vref, RX VrefLevel [Byte0]: 30
7892 11:50:46.530426 [Byte1]: 30
7893 11:50:46.534781
7894 11:50:46.535361 Set Vref, RX VrefLevel [Byte0]: 31
7895 11:50:46.537895 [Byte1]: 31
7896 11:50:46.542370
7897 11:50:46.542848 Set Vref, RX VrefLevel [Byte0]: 32
7898 11:50:46.545588 [Byte1]: 32
7899 11:50:46.550484
7900 11:50:46.553050 Set Vref, RX VrefLevel [Byte0]: 33
7901 11:50:46.556209 [Byte1]: 33
7902 11:50:46.556651
7903 11:50:46.559418 Set Vref, RX VrefLevel [Byte0]: 34
7904 11:50:46.562586 [Byte1]: 34
7905 11:50:46.563041
7906 11:50:46.565953 Set Vref, RX VrefLevel [Byte0]: 35
7907 11:50:46.569377 [Byte1]: 35
7908 11:50:46.572578
7909 11:50:46.573005 Set Vref, RX VrefLevel [Byte0]: 36
7910 11:50:46.576079 [Byte1]: 36
7911 11:50:46.579803
7912 11:50:46.580403 Set Vref, RX VrefLevel [Byte0]: 37
7913 11:50:46.586252 [Byte1]: 37
7914 11:50:46.586786
7915 11:50:46.589498 Set Vref, RX VrefLevel [Byte0]: 38
7916 11:50:46.592795 [Byte1]: 38
7917 11:50:46.593275
7918 11:50:46.595927 Set Vref, RX VrefLevel [Byte0]: 39
7919 11:50:46.599908 [Byte1]: 39
7920 11:50:46.602876
7921 11:50:46.603367 Set Vref, RX VrefLevel [Byte0]: 40
7922 11:50:46.605866 [Byte1]: 40
7923 11:50:46.610136
7924 11:50:46.610789 Set Vref, RX VrefLevel [Byte0]: 41
7925 11:50:46.613824 [Byte1]: 41
7926 11:50:46.617929
7927 11:50:46.618418 Set Vref, RX VrefLevel [Byte0]: 42
7928 11:50:46.621293 [Byte1]: 42
7929 11:50:46.625504
7930 11:50:46.625957 Set Vref, RX VrefLevel [Byte0]: 43
7931 11:50:46.628751 [Byte1]: 43
7932 11:50:46.633537
7933 11:50:46.634116 Set Vref, RX VrefLevel [Byte0]: 44
7934 11:50:46.636417 [Byte1]: 44
7935 11:50:46.641091
7936 11:50:46.641698 Set Vref, RX VrefLevel [Byte0]: 45
7937 11:50:46.644124 [Byte1]: 45
7938 11:50:46.648316
7939 11:50:46.648759 Set Vref, RX VrefLevel [Byte0]: 46
7940 11:50:46.651734 [Byte1]: 46
7941 11:50:46.655962
7942 11:50:46.656375 Set Vref, RX VrefLevel [Byte0]: 47
7943 11:50:46.658881 [Byte1]: 47
7944 11:50:46.663119
7945 11:50:46.663540 Set Vref, RX VrefLevel [Byte0]: 48
7946 11:50:46.667054 [Byte1]: 48
7947 11:50:46.670765
7948 11:50:46.671234 Set Vref, RX VrefLevel [Byte0]: 49
7949 11:50:46.674028 [Byte1]: 49
7950 11:50:46.678579
7951 11:50:46.679046 Set Vref, RX VrefLevel [Byte0]: 50
7952 11:50:46.681731 [Byte1]: 50
7953 11:50:46.686176
7954 11:50:46.686649 Set Vref, RX VrefLevel [Byte0]: 51
7955 11:50:46.689503 [Byte1]: 51
7956 11:50:46.693735
7957 11:50:46.694212 Set Vref, RX VrefLevel [Byte0]: 52
7958 11:50:46.697024 [Byte1]: 52
7959 11:50:46.701217
7960 11:50:46.701729 Set Vref, RX VrefLevel [Byte0]: 53
7961 11:50:46.705147 [Byte1]: 53
7962 11:50:46.709171
7963 11:50:46.709757 Set Vref, RX VrefLevel [Byte0]: 54
7964 11:50:46.712510 [Byte1]: 54
7965 11:50:46.716594
7966 11:50:46.717288 Set Vref, RX VrefLevel [Byte0]: 55
7967 11:50:46.719714 [Byte1]: 55
7968 11:50:46.724035
7969 11:50:46.724508 Set Vref, RX VrefLevel [Byte0]: 56
7970 11:50:46.727045 [Byte1]: 56
7971 11:50:46.731581
7972 11:50:46.732184 Set Vref, RX VrefLevel [Byte0]: 57
7973 11:50:46.734960 [Byte1]: 57
7974 11:50:46.739565
7975 11:50:46.740113 Set Vref, RX VrefLevel [Byte0]: 58
7976 11:50:46.742491 [Byte1]: 58
7977 11:50:46.747414
7978 11:50:46.748033 Set Vref, RX VrefLevel [Byte0]: 59
7979 11:50:46.750080 [Byte1]: 59
7980 11:50:46.754170
7981 11:50:46.754592 Set Vref, RX VrefLevel [Byte0]: 60
7982 11:50:46.757751 [Byte1]: 60
7983 11:50:46.761546
7984 11:50:46.762037 Set Vref, RX VrefLevel [Byte0]: 61
7985 11:50:46.765005 [Byte1]: 61
7986 11:50:46.769498
7987 11:50:46.769996 Set Vref, RX VrefLevel [Byte0]: 62
7988 11:50:46.772608 [Byte1]: 62
7989 11:50:46.777125
7990 11:50:46.777675 Set Vref, RX VrefLevel [Byte0]: 63
7991 11:50:46.780422 [Byte1]: 63
7992 11:50:46.784294
7993 11:50:46.785002 Set Vref, RX VrefLevel [Byte0]: 64
7994 11:50:46.788699 [Byte1]: 64
7995 11:50:46.792570
7996 11:50:46.793054 Set Vref, RX VrefLevel [Byte0]: 65
7997 11:50:46.795198 [Byte1]: 65
7998 11:50:46.799965
7999 11:50:46.800457 Set Vref, RX VrefLevel [Byte0]: 66
8000 11:50:46.802968 [Byte1]: 66
8001 11:50:46.807488
8002 11:50:46.808013 Set Vref, RX VrefLevel [Byte0]: 67
8003 11:50:46.810298 [Byte1]: 67
8004 11:50:46.814913
8005 11:50:46.815401 Set Vref, RX VrefLevel [Byte0]: 68
8006 11:50:46.818010 [Byte1]: 68
8007 11:50:46.822615
8008 11:50:46.823074 Set Vref, RX VrefLevel [Byte0]: 69
8009 11:50:46.825719 [Byte1]: 69
8010 11:50:46.829903
8011 11:50:46.830314 Set Vref, RX VrefLevel [Byte0]: 70
8012 11:50:46.834491 [Byte1]: 70
8013 11:50:46.837535
8014 11:50:46.838006 Set Vref, RX VrefLevel [Byte0]: 71
8015 11:50:46.840896 [Byte1]: 71
8016 11:50:46.845353
8017 11:50:46.846047 Set Vref, RX VrefLevel [Byte0]: 72
8018 11:50:46.848542 [Byte1]: 72
8019 11:50:46.852487
8020 11:50:46.852962 Set Vref, RX VrefLevel [Byte0]: 73
8021 11:50:46.856434 [Byte1]: 73
8022 11:50:46.859987
8023 11:50:46.860467 Set Vref, RX VrefLevel [Byte0]: 74
8024 11:50:46.863734 [Byte1]: 74
8025 11:50:46.867574
8026 11:50:46.868140 Set Vref, RX VrefLevel [Byte0]: 75
8027 11:50:46.871025 [Byte1]: 75
8028 11:50:46.876298
8029 11:50:46.876755 Set Vref, RX VrefLevel [Byte0]: 76
8030 11:50:46.878591 [Byte1]: 76
8031 11:50:46.882743
8032 11:50:46.883182 Set Vref, RX VrefLevel [Byte0]: 77
8033 11:50:46.886766 [Byte1]: 77
8034 11:50:46.890532
8035 11:50:46.890986 Set Vref, RX VrefLevel [Byte0]: 78
8036 11:50:46.893961 [Byte1]: 78
8037 11:50:46.898050
8038 11:50:46.898686 Set Vref, RX VrefLevel [Byte0]: 79
8039 11:50:46.901379 [Byte1]: 79
8040 11:50:46.906023
8041 11:50:46.906687 Final RX Vref Byte 0 = 68 to rank0
8042 11:50:46.908957 Final RX Vref Byte 1 = 56 to rank0
8043 11:50:46.912126 Final RX Vref Byte 0 = 68 to rank1
8044 11:50:46.916082 Final RX Vref Byte 1 = 56 to rank1==
8045 11:50:46.918705 Dram Type= 6, Freq= 0, CH_0, rank 0
8046 11:50:46.925193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 11:50:46.925708 ==
8048 11:50:46.926152 DQS Delay:
8049 11:50:46.928835 DQS0 = 0, DQS1 = 0
8050 11:50:46.929319 DQM Delay:
8051 11:50:46.929783 DQM0 = 134, DQM1 = 123
8052 11:50:46.931769 DQ Delay:
8053 11:50:46.935063 DQ0 =132, DQ1 =138, DQ2 =132, DQ3 =132
8054 11:50:46.938905 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =144
8055 11:50:46.942157 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =116
8056 11:50:46.944966 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8057 11:50:46.945391
8058 11:50:46.945761
8059 11:50:46.946125
8060 11:50:46.948497 [DramC_TX_OE_Calibration] TA2
8061 11:50:46.951753 Original DQ_B0 (3 6) =30, OEN = 27
8062 11:50:46.955727 Original DQ_B1 (3 6) =30, OEN = 27
8063 11:50:46.958763 24, 0x0, End_B0=24 End_B1=24
8064 11:50:46.959190 25, 0x0, End_B0=25 End_B1=25
8065 11:50:46.961617 26, 0x0, End_B0=26 End_B1=26
8066 11:50:46.965014 27, 0x0, End_B0=27 End_B1=27
8067 11:50:46.968456 28, 0x0, End_B0=28 End_B1=28
8068 11:50:46.971974 29, 0x0, End_B0=29 End_B1=29
8069 11:50:46.972353 30, 0x0, End_B0=30 End_B1=30
8070 11:50:46.975479 31, 0x4141, End_B0=30 End_B1=30
8071 11:50:46.978476 Byte0 end_step=30 best_step=27
8072 11:50:46.981563 Byte1 end_step=30 best_step=27
8073 11:50:46.985016 Byte0 TX OE(2T, 0.5T) = (3, 3)
8074 11:50:46.988656 Byte1 TX OE(2T, 0.5T) = (3, 3)
8075 11:50:46.989084
8076 11:50:46.989471
8077 11:50:46.994871 [DQSOSCAuto] RK0, (LSB)MR18= 0x2315, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8078 11:50:46.998013 CH0 RK0: MR19=303, MR18=2315
8079 11:50:47.004711 CH0_RK0: MR19=0x303, MR18=0x2315, DQSOSC=392, MR23=63, INC=24, DEC=16
8080 11:50:47.005165
8081 11:50:47.007584 ----->DramcWriteLeveling(PI) begin...
8082 11:50:47.007998 ==
8083 11:50:47.011238 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 11:50:47.014248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 11:50:47.014783 ==
8086 11:50:47.017463 Write leveling (Byte 0): 36 => 36
8087 11:50:47.020617 Write leveling (Byte 1): 29 => 29
8088 11:50:47.024611 DramcWriteLeveling(PI) end<-----
8089 11:50:47.025091
8090 11:50:47.025552 ==
8091 11:50:47.027599 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 11:50:47.033833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 11:50:47.034271 ==
8094 11:50:47.034672 [Gating] SW mode calibration
8095 11:50:47.044276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8096 11:50:47.047270 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8097 11:50:47.053775 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 11:50:47.057892 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 11:50:47.060800 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 11:50:47.063772 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8101 11:50:47.070558 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8102 11:50:47.073721 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8103 11:50:47.076992 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 11:50:47.084007 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 11:50:47.086651 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 11:50:47.090052 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 11:50:47.097048 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 11:50:47.100364 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8109 11:50:47.103781 1 5 16 | B1->B0 | 3434 2525 | 1 1 | (1 0) (1 0)
8110 11:50:47.109524 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
8111 11:50:47.113187 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 11:50:47.120333 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 11:50:47.122946 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 11:50:47.126433 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 11:50:47.129672 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 11:50:47.136673 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8117 11:50:47.139508 1 6 16 | B1->B0 | 2323 4343 | 1 0 | (0 0) (0 0)
8118 11:50:47.143124 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8119 11:50:47.149184 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 11:50:47.153295 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 11:50:47.159626 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 11:50:47.162538 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 11:50:47.165758 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 11:50:47.169014 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 11:50:47.175817 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8126 11:50:47.179763 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8127 11:50:47.182914 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8128 11:50:47.188928 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 11:50:47.192578 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 11:50:47.195931 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 11:50:47.202530 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 11:50:47.205704 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 11:50:47.208863 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 11:50:47.215311 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 11:50:47.218907 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 11:50:47.221988 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 11:50:47.228606 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 11:50:47.231955 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 11:50:47.234907 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 11:50:47.241943 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8141 11:50:47.245470 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8142 11:50:47.248254 Total UI for P1: 0, mck2ui 16
8143 11:50:47.251723 best dqsien dly found for B0: ( 1, 9, 12)
8144 11:50:47.254912 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8145 11:50:47.260957 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 11:50:47.264572 Total UI for P1: 0, mck2ui 16
8147 11:50:47.268010 best dqsien dly found for B1: ( 1, 9, 18)
8148 11:50:47.271133 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8149 11:50:47.274920 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8150 11:50:47.275341
8151 11:50:47.278581 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8152 11:50:47.281471 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8153 11:50:47.284614 [Gating] SW calibration Done
8154 11:50:47.285033 ==
8155 11:50:47.287577 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 11:50:47.291061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 11:50:47.294296 ==
8158 11:50:47.294770 RX Vref Scan: 0
8159 11:50:47.295141
8160 11:50:47.297306 RX Vref 0 -> 0, step: 1
8161 11:50:47.297848
8162 11:50:47.298207 RX Delay 0 -> 252, step: 8
8163 11:50:47.304066 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8164 11:50:47.307514 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8165 11:50:47.310902 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8166 11:50:47.314149 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8167 11:50:47.320830 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8168 11:50:47.323890 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8169 11:50:47.327460 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8170 11:50:47.330751 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8171 11:50:47.334363 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8172 11:50:47.337282 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8173 11:50:47.343881 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8174 11:50:47.347476 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8175 11:50:47.350331 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8176 11:50:47.353574 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8177 11:50:47.360672 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8178 11:50:47.363740 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8179 11:50:47.364185 ==
8180 11:50:47.366911 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 11:50:47.370236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 11:50:47.370748 ==
8183 11:50:47.373599 DQS Delay:
8184 11:50:47.374065 DQS0 = 0, DQS1 = 0
8185 11:50:47.374498 DQM Delay:
8186 11:50:47.376908 DQM0 = 133, DQM1 = 129
8187 11:50:47.377318 DQ Delay:
8188 11:50:47.380808 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8189 11:50:47.383862 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
8190 11:50:47.390282 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8191 11:50:47.393743 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8192 11:50:47.394224
8193 11:50:47.394564
8194 11:50:47.394877 ==
8195 11:50:47.396802 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 11:50:47.400257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 11:50:47.400684 ==
8198 11:50:47.401025
8199 11:50:47.401337
8200 11:50:47.403704 TX Vref Scan disable
8201 11:50:47.404195 == TX Byte 0 ==
8202 11:50:47.410717 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8203 11:50:47.413188 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8204 11:50:47.416662 == TX Byte 1 ==
8205 11:50:47.419631 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8206 11:50:47.423312 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8207 11:50:47.423778 ==
8208 11:50:47.426597 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 11:50:47.429848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 11:50:47.433036 ==
8211 11:50:47.445008
8212 11:50:47.448240 TX Vref early break, caculate TX vref
8213 11:50:47.451095 TX Vref=16, minBit 0, minWin=23, winSum=381
8214 11:50:47.454441 TX Vref=18, minBit 0, minWin=23, winSum=387
8215 11:50:47.458154 TX Vref=20, minBit 1, minWin=23, winSum=400
8216 11:50:47.460877 TX Vref=22, minBit 2, minWin=23, winSum=403
8217 11:50:47.464349 TX Vref=24, minBit 1, minWin=24, winSum=414
8218 11:50:47.471290 TX Vref=26, minBit 1, minWin=24, winSum=416
8219 11:50:47.474254 TX Vref=28, minBit 0, minWin=24, winSum=413
8220 11:50:47.478067 TX Vref=30, minBit 0, minWin=24, winSum=406
8221 11:50:47.480547 TX Vref=32, minBit 0, minWin=24, winSum=399
8222 11:50:47.484512 TX Vref=34, minBit 1, minWin=23, winSum=394
8223 11:50:47.490939 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 26
8224 11:50:47.491513
8225 11:50:47.494144 Final TX Range 0 Vref 26
8226 11:50:47.494564
8227 11:50:47.494950 ==
8228 11:50:47.497149 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 11:50:47.500818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 11:50:47.501277 ==
8231 11:50:47.501666
8232 11:50:47.503981
8233 11:50:47.504341 TX Vref Scan disable
8234 11:50:47.510170 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8235 11:50:47.510681 == TX Byte 0 ==
8236 11:50:47.514231 u2DelayCellOfst[0]=11 cells (3 PI)
8237 11:50:47.517172 u2DelayCellOfst[1]=14 cells (4 PI)
8238 11:50:47.520227 u2DelayCellOfst[2]=11 cells (3 PI)
8239 11:50:47.523405 u2DelayCellOfst[3]=11 cells (3 PI)
8240 11:50:47.526917 u2DelayCellOfst[4]=7 cells (2 PI)
8241 11:50:47.530439 u2DelayCellOfst[5]=0 cells (0 PI)
8242 11:50:47.533729 u2DelayCellOfst[6]=14 cells (4 PI)
8243 11:50:47.536983 u2DelayCellOfst[7]=14 cells (4 PI)
8244 11:50:47.539972 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8245 11:50:47.543314 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8246 11:50:47.546770 == TX Byte 1 ==
8247 11:50:47.549969 u2DelayCellOfst[8]=0 cells (0 PI)
8248 11:50:47.553259 u2DelayCellOfst[9]=3 cells (1 PI)
8249 11:50:47.556831 u2DelayCellOfst[10]=7 cells (2 PI)
8250 11:50:47.560158 u2DelayCellOfst[11]=3 cells (1 PI)
8251 11:50:47.560603 u2DelayCellOfst[12]=14 cells (4 PI)
8252 11:50:47.562998 u2DelayCellOfst[13]=14 cells (4 PI)
8253 11:50:47.566378 u2DelayCellOfst[14]=18 cells (5 PI)
8254 11:50:47.569753 u2DelayCellOfst[15]=11 cells (3 PI)
8255 11:50:47.576508 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8256 11:50:47.579742 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8257 11:50:47.580202 DramC Write-DBI on
8258 11:50:47.582764 ==
8259 11:50:47.586430 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 11:50:47.589710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 11:50:47.590153 ==
8262 11:50:47.590486
8263 11:50:47.590837
8264 11:50:47.592705 TX Vref Scan disable
8265 11:50:47.593124 == TX Byte 0 ==
8266 11:50:47.599309 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8267 11:50:47.599731 == TX Byte 1 ==
8268 11:50:47.602544 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8269 11:50:47.606065 DramC Write-DBI off
8270 11:50:47.606483
8271 11:50:47.606812 [DATLAT]
8272 11:50:47.608879 Freq=1600, CH0 RK1
8273 11:50:47.609476
8274 11:50:47.610010 DATLAT Default: 0xf
8275 11:50:47.612174 0, 0xFFFF, sum = 0
8276 11:50:47.617378 1, 0xFFFF, sum = 0
8277 11:50:47.617842 2, 0xFFFF, sum = 0
8278 11:50:47.619141 3, 0xFFFF, sum = 0
8279 11:50:47.619613 4, 0xFFFF, sum = 0
8280 11:50:47.622275 5, 0xFFFF, sum = 0
8281 11:50:47.622697 6, 0xFFFF, sum = 0
8282 11:50:47.625608 7, 0xFFFF, sum = 0
8283 11:50:47.626066 8, 0xFFFF, sum = 0
8284 11:50:47.628973 9, 0xFFFF, sum = 0
8285 11:50:47.629620 10, 0xFFFF, sum = 0
8286 11:50:47.632015 11, 0xFFFF, sum = 0
8287 11:50:47.632491 12, 0xFFFF, sum = 0
8288 11:50:47.635705 13, 0xFFFF, sum = 0
8289 11:50:47.636129 14, 0x0, sum = 1
8290 11:50:47.638687 15, 0x0, sum = 2
8291 11:50:47.639111 16, 0x0, sum = 3
8292 11:50:47.641991 17, 0x0, sum = 4
8293 11:50:47.642411 best_step = 15
8294 11:50:47.642738
8295 11:50:47.643044 ==
8296 11:50:47.645495 Dram Type= 6, Freq= 0, CH_0, rank 1
8297 11:50:47.651964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 11:50:47.652568 ==
8299 11:50:47.652909 RX Vref Scan: 0
8300 11:50:47.653217
8301 11:50:47.655083 RX Vref 0 -> 0, step: 1
8302 11:50:47.655644
8303 11:50:47.658333 RX Delay 11 -> 252, step: 4
8304 11:50:47.661778 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8305 11:50:47.664871 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8306 11:50:47.672386 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8307 11:50:47.674762 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8308 11:50:47.678412 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8309 11:50:47.681530 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8310 11:50:47.685318 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8311 11:50:47.692264 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8312 11:50:47.694574 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8313 11:50:47.698038 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8314 11:50:47.701599 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8315 11:50:47.704761 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8316 11:50:47.711020 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8317 11:50:47.714871 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8318 11:50:47.718103 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8319 11:50:47.721197 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8320 11:50:47.721870 ==
8321 11:50:47.724387 Dram Type= 6, Freq= 0, CH_0, rank 1
8322 11:50:47.731632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 11:50:47.732106 ==
8324 11:50:47.732532 DQS Delay:
8325 11:50:47.734449 DQS0 = 0, DQS1 = 0
8326 11:50:47.734922 DQM Delay:
8327 11:50:47.735370 DQM0 = 130, DQM1 = 125
8328 11:50:47.737943 DQ Delay:
8329 11:50:47.741141 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8330 11:50:47.744741 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8331 11:50:47.747810 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8332 11:50:47.750849 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8333 11:50:47.751461
8334 11:50:47.751837
8335 11:50:47.752224
8336 11:50:47.754173 [DramC_TX_OE_Calibration] TA2
8337 11:50:47.757354 Original DQ_B0 (3 6) =30, OEN = 27
8338 11:50:47.760519 Original DQ_B1 (3 6) =30, OEN = 27
8339 11:50:47.763832 24, 0x0, End_B0=24 End_B1=24
8340 11:50:47.767409 25, 0x0, End_B0=25 End_B1=25
8341 11:50:47.767839 26, 0x0, End_B0=26 End_B1=26
8342 11:50:47.770269 27, 0x0, End_B0=27 End_B1=27
8343 11:50:47.774265 28, 0x0, End_B0=28 End_B1=28
8344 11:50:47.777240 29, 0x0, End_B0=29 End_B1=29
8345 11:50:47.777766 30, 0x0, End_B0=30 End_B1=30
8346 11:50:47.780278 31, 0x4141, End_B0=30 End_B1=30
8347 11:50:47.783631 Byte0 end_step=30 best_step=27
8348 11:50:47.787127 Byte1 end_step=30 best_step=27
8349 11:50:47.790992 Byte0 TX OE(2T, 0.5T) = (3, 3)
8350 11:50:47.793611 Byte1 TX OE(2T, 0.5T) = (3, 3)
8351 11:50:47.794169
8352 11:50:47.794661
8353 11:50:47.800114 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8354 11:50:47.803609 CH0 RK1: MR19=303, MR18=1F02
8355 11:50:47.810553 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8356 11:50:47.813445 [RxdqsGatingPostProcess] freq 1600
8357 11:50:47.816998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8358 11:50:47.820317 best DQS0 dly(2T, 0.5T) = (1, 1)
8359 11:50:47.823421 best DQS1 dly(2T, 0.5T) = (1, 1)
8360 11:50:47.827235 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8361 11:50:47.830936 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8362 11:50:47.833910 best DQS0 dly(2T, 0.5T) = (1, 1)
8363 11:50:47.836858 best DQS1 dly(2T, 0.5T) = (1, 1)
8364 11:50:47.840340 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8365 11:50:47.843648 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8366 11:50:47.846865 Pre-setting of DQS Precalculation
8367 11:50:47.850110 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8368 11:50:47.850669 ==
8369 11:50:47.853108 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 11:50:47.859676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 11:50:47.860119 ==
8372 11:50:47.863312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8373 11:50:47.870121 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8374 11:50:47.873078 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8375 11:50:47.879434 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8376 11:50:47.887741 [CA 0] Center 41 (12~71) winsize 60
8377 11:50:47.890787 [CA 1] Center 42 (12~72) winsize 61
8378 11:50:47.893680 [CA 2] Center 37 (8~66) winsize 59
8379 11:50:47.897240 [CA 3] Center 35 (6~65) winsize 60
8380 11:50:47.900472 [CA 4] Center 37 (8~66) winsize 59
8381 11:50:47.903625 [CA 5] Center 36 (6~66) winsize 61
8382 11:50:47.904042
8383 11:50:47.907140 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8384 11:50:47.907707
8385 11:50:47.913371 [CATrainingPosCal] consider 1 rank data
8386 11:50:47.913830 u2DelayCellTimex100 = 262/100 ps
8387 11:50:47.920688 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8388 11:50:47.923929 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8389 11:50:47.926894 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8390 11:50:47.929943 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8391 11:50:47.933477 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
8392 11:50:47.936702 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8393 11:50:47.937235
8394 11:50:47.940003 CA PerBit enable=1, Macro0, CA PI delay=35
8395 11:50:47.940645
8396 11:50:47.943483 [CBTSetCACLKResult] CA Dly = 35
8397 11:50:47.946584 CS Dly: 9 (0~40)
8398 11:50:47.951264 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8399 11:50:47.953322 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8400 11:50:47.953801 ==
8401 11:50:47.956818 Dram Type= 6, Freq= 0, CH_1, rank 1
8402 11:50:47.963250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 11:50:47.963700 ==
8404 11:50:47.966138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8405 11:50:47.973518 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8406 11:50:47.976620 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8407 11:50:47.982587 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8408 11:50:47.990862 [CA 0] Center 43 (14~72) winsize 59
8409 11:50:47.993801 [CA 1] Center 43 (13~73) winsize 61
8410 11:50:47.996891 [CA 2] Center 37 (8~67) winsize 60
8411 11:50:48.000751 [CA 3] Center 37 (8~67) winsize 60
8412 11:50:48.003767 [CA 4] Center 37 (8~67) winsize 60
8413 11:50:48.006951 [CA 5] Center 37 (8~66) winsize 59
8414 11:50:48.007368
8415 11:50:48.010250 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8416 11:50:48.010669
8417 11:50:48.013853 [CATrainingPosCal] consider 2 rank data
8418 11:50:48.017269 u2DelayCellTimex100 = 262/100 ps
8419 11:50:48.023518 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8420 11:50:48.026578 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8421 11:50:48.030139 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8422 11:50:48.034048 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8423 11:50:48.036595 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8424 11:50:48.040020 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8425 11:50:48.040555
8426 11:50:48.042978 CA PerBit enable=1, Macro0, CA PI delay=36
8427 11:50:48.043398
8428 11:50:48.046588 [CBTSetCACLKResult] CA Dly = 36
8429 11:50:48.049776 CS Dly: 10 (0~43)
8430 11:50:48.053341 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8431 11:50:48.056365 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8432 11:50:48.056807
8433 11:50:48.060394 ----->DramcWriteLeveling(PI) begin...
8434 11:50:48.060946 ==
8435 11:50:48.063449 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 11:50:48.069489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 11:50:48.070045 ==
8438 11:50:48.072847 Write leveling (Byte 0): 23 => 23
8439 11:50:48.076191 Write leveling (Byte 1): 25 => 25
8440 11:50:48.076750 DramcWriteLeveling(PI) end<-----
8441 11:50:48.079943
8442 11:50:48.080515 ==
8443 11:50:48.083214 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 11:50:48.086368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 11:50:48.086924 ==
8446 11:50:48.090311 [Gating] SW mode calibration
8447 11:50:48.096568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8448 11:50:48.102483 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8449 11:50:48.105898 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 11:50:48.109759 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 11:50:48.112715 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8452 11:50:48.119256 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 11:50:48.122777 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 11:50:48.125872 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 11:50:48.132719 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 11:50:48.135859 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 11:50:48.139019 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 11:50:48.145955 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 11:50:48.148993 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8460 11:50:48.152150 1 5 12 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 0)
8461 11:50:48.158759 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 11:50:48.161857 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 11:50:48.165276 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 11:50:48.172014 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 11:50:48.175135 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 11:50:48.180563 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 11:50:48.185175 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 11:50:48.188604 1 6 12 | B1->B0 | 4140 4444 | 1 0 | (0 0) (0 0)
8469 11:50:48.191856 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 11:50:48.198722 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 11:50:48.201696 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 11:50:48.204618 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 11:50:48.211588 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 11:50:48.214994 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 11:50:48.218455 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 11:50:48.224806 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8477 11:50:48.227870 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8478 11:50:48.231337 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 11:50:48.238372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 11:50:48.241967 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 11:50:48.244771 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 11:50:48.250743 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 11:50:48.254345 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 11:50:48.257756 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 11:50:48.264114 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 11:50:48.267307 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 11:50:48.271005 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:50:48.277395 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 11:50:48.280948 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 11:50:48.284474 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 11:50:48.290809 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8492 11:50:48.293833 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8493 11:50:48.297033 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8494 11:50:48.300751 Total UI for P1: 0, mck2ui 16
8495 11:50:48.303646 best dqsien dly found for B0: ( 1, 9, 10)
8496 11:50:48.310426 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 11:50:48.313998 Total UI for P1: 0, mck2ui 16
8498 11:50:48.317088 best dqsien dly found for B1: ( 1, 9, 12)
8499 11:50:48.321261 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8500 11:50:48.323855 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8501 11:50:48.324282
8502 11:50:48.326719 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8503 11:50:48.330193 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8504 11:50:48.333765 [Gating] SW calibration Done
8505 11:50:48.334282 ==
8506 11:50:48.336767 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 11:50:48.340669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 11:50:48.341188 ==
8509 11:50:48.343781 RX Vref Scan: 0
8510 11:50:48.344241
8511 11:50:48.346572 RX Vref 0 -> 0, step: 1
8512 11:50:48.346988
8513 11:50:48.347320 RX Delay 0 -> 252, step: 8
8514 11:50:48.353028 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8515 11:50:48.356402 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8516 11:50:48.359908 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8517 11:50:48.363108 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8518 11:50:48.366224 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8519 11:50:48.373020 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8520 11:50:48.376315 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8521 11:50:48.379310 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8522 11:50:48.382951 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8523 11:50:48.386000 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8524 11:50:48.392549 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8525 11:50:48.396460 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8526 11:50:48.399282 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8527 11:50:48.402761 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8528 11:50:48.409330 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8529 11:50:48.412852 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8530 11:50:48.413275 ==
8531 11:50:48.416391 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 11:50:48.419524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 11:50:48.419956 ==
8534 11:50:48.422860 DQS Delay:
8535 11:50:48.423285 DQS0 = 0, DQS1 = 0
8536 11:50:48.423622 DQM Delay:
8537 11:50:48.425575 DQM0 = 137, DQM1 = 127
8538 11:50:48.426140 DQ Delay:
8539 11:50:48.429139 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8540 11:50:48.432078 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8541 11:50:48.435806 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
8542 11:50:48.442454 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8543 11:50:48.442877
8544 11:50:48.443207
8545 11:50:48.443515 ==
8546 11:50:48.445671 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 11:50:48.449069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 11:50:48.449658 ==
8549 11:50:48.450214
8550 11:50:48.450698
8551 11:50:48.452013 TX Vref Scan disable
8552 11:50:48.452529 == TX Byte 0 ==
8553 11:50:48.459104 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8554 11:50:48.462473 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8555 11:50:48.462921 == TX Byte 1 ==
8556 11:50:48.468972 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8557 11:50:48.472132 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8558 11:50:48.472551 ==
8559 11:50:48.475447 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 11:50:48.478700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 11:50:48.479121 ==
8562 11:50:48.492849
8563 11:50:48.495899 TX Vref early break, caculate TX vref
8564 11:50:48.499352 TX Vref=16, minBit 0, minWin=21, winSum=372
8565 11:50:48.502718 TX Vref=18, minBit 0, minWin=22, winSum=386
8566 11:50:48.505519 TX Vref=20, minBit 0, minWin=23, winSum=390
8567 11:50:48.509283 TX Vref=22, minBit 0, minWin=23, winSum=401
8568 11:50:48.512433 TX Vref=24, minBit 5, minWin=23, winSum=411
8569 11:50:48.518978 TX Vref=26, minBit 0, minWin=24, winSum=418
8570 11:50:48.522630 TX Vref=28, minBit 0, minWin=24, winSum=419
8571 11:50:48.526161 TX Vref=30, minBit 5, minWin=24, winSum=413
8572 11:50:48.528633 TX Vref=32, minBit 0, minWin=23, winSum=402
8573 11:50:48.532192 TX Vref=34, minBit 5, minWin=22, winSum=390
8574 11:50:48.538465 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 28
8575 11:50:48.538964
8576 11:50:48.541940 Final TX Range 0 Vref 28
8577 11:50:48.542361
8578 11:50:48.542694 ==
8579 11:50:48.545457 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 11:50:48.548648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 11:50:48.549073 ==
8582 11:50:48.549452
8583 11:50:48.549773
8584 11:50:48.551727 TX Vref Scan disable
8585 11:50:48.558476 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8586 11:50:48.558895 == TX Byte 0 ==
8587 11:50:48.562373 u2DelayCellOfst[0]=22 cells (6 PI)
8588 11:50:48.564934 u2DelayCellOfst[1]=14 cells (4 PI)
8589 11:50:48.568139 u2DelayCellOfst[2]=0 cells (0 PI)
8590 11:50:48.571815 u2DelayCellOfst[3]=7 cells (2 PI)
8591 11:50:48.575054 u2DelayCellOfst[4]=11 cells (3 PI)
8592 11:50:48.578120 u2DelayCellOfst[5]=26 cells (7 PI)
8593 11:50:48.581611 u2DelayCellOfst[6]=22 cells (6 PI)
8594 11:50:48.585260 u2DelayCellOfst[7]=7 cells (2 PI)
8595 11:50:48.588263 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8596 11:50:48.591211 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8597 11:50:48.595058 == TX Byte 1 ==
8598 11:50:48.597873 u2DelayCellOfst[8]=0 cells (0 PI)
8599 11:50:48.601050 u2DelayCellOfst[9]=3 cells (1 PI)
8600 11:50:48.604757 u2DelayCellOfst[10]=11 cells (3 PI)
8601 11:50:48.605176 u2DelayCellOfst[11]=3 cells (1 PI)
8602 11:50:48.609020 u2DelayCellOfst[12]=14 cells (4 PI)
8603 11:50:48.611017 u2DelayCellOfst[13]=18 cells (5 PI)
8604 11:50:48.614877 u2DelayCellOfst[14]=18 cells (5 PI)
8605 11:50:48.617991 u2DelayCellOfst[15]=18 cells (5 PI)
8606 11:50:48.625228 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8607 11:50:48.627800 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8608 11:50:48.628363 DramC Write-DBI on
8609 11:50:48.628719 ==
8610 11:50:48.630889 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 11:50:48.638515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 11:50:48.639076 ==
8613 11:50:48.639419
8614 11:50:48.639750
8615 11:50:48.640755 TX Vref Scan disable
8616 11:50:48.641172 == TX Byte 0 ==
8617 11:50:48.647926 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8618 11:50:48.648446 == TX Byte 1 ==
8619 11:50:48.651015 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8620 11:50:48.654129 DramC Write-DBI off
8621 11:50:48.654701
8622 11:50:48.655040 [DATLAT]
8623 11:50:48.657368 Freq=1600, CH1 RK0
8624 11:50:48.657876
8625 11:50:48.658213 DATLAT Default: 0xf
8626 11:50:48.660638 0, 0xFFFF, sum = 0
8627 11:50:48.661164 1, 0xFFFF, sum = 0
8628 11:50:48.663900 2, 0xFFFF, sum = 0
8629 11:50:48.664354 3, 0xFFFF, sum = 0
8630 11:50:48.666837 4, 0xFFFF, sum = 0
8631 11:50:48.667412 5, 0xFFFF, sum = 0
8632 11:50:48.670324 6, 0xFFFF, sum = 0
8633 11:50:48.673880 7, 0xFFFF, sum = 0
8634 11:50:48.674307 8, 0xFFFF, sum = 0
8635 11:50:48.677072 9, 0xFFFF, sum = 0
8636 11:50:48.677631 10, 0xFFFF, sum = 0
8637 11:50:48.680795 11, 0xFFFF, sum = 0
8638 11:50:48.681326 12, 0xFFFF, sum = 0
8639 11:50:48.684028 13, 0xFFFF, sum = 0
8640 11:50:48.684451 14, 0x0, sum = 1
8641 11:50:48.686822 15, 0x0, sum = 2
8642 11:50:48.687275 16, 0x0, sum = 3
8643 11:50:48.690638 17, 0x0, sum = 4
8644 11:50:48.691174 best_step = 15
8645 11:50:48.691554
8646 11:50:48.691901 ==
8647 11:50:48.693924 Dram Type= 6, Freq= 0, CH_1, rank 0
8648 11:50:48.696461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8649 11:50:48.699953 ==
8650 11:50:48.700529 RX Vref Scan: 1
8651 11:50:48.701125
8652 11:50:48.703773 Set Vref Range= 24 -> 127
8653 11:50:48.704189
8654 11:50:48.706678 RX Vref 24 -> 127, step: 1
8655 11:50:48.707094
8656 11:50:48.707426 RX Delay 11 -> 252, step: 4
8657 11:50:48.707739
8658 11:50:48.709971 Set Vref, RX VrefLevel [Byte0]: 24
8659 11:50:48.713546 [Byte1]: 24
8660 11:50:48.717478
8661 11:50:48.717914 Set Vref, RX VrefLevel [Byte0]: 25
8662 11:50:48.720246 [Byte1]: 25
8663 11:50:48.724666
8664 11:50:48.725153 Set Vref, RX VrefLevel [Byte0]: 26
8665 11:50:48.727706 [Byte1]: 26
8666 11:50:48.732184
8667 11:50:48.732601 Set Vref, RX VrefLevel [Byte0]: 27
8668 11:50:48.735629 [Byte1]: 27
8669 11:50:48.739458
8670 11:50:48.740011 Set Vref, RX VrefLevel [Byte0]: 28
8671 11:50:48.743181 [Byte1]: 28
8672 11:50:48.747304
8673 11:50:48.747719 Set Vref, RX VrefLevel [Byte0]: 29
8674 11:50:48.751221 [Byte1]: 29
8675 11:50:48.755205
8676 11:50:48.755686 Set Vref, RX VrefLevel [Byte0]: 30
8677 11:50:48.758816 [Byte1]: 30
8678 11:50:48.762431
8679 11:50:48.762997 Set Vref, RX VrefLevel [Byte0]: 31
8680 11:50:48.766081 [Byte1]: 31
8681 11:50:48.770195
8682 11:50:48.770610 Set Vref, RX VrefLevel [Byte0]: 32
8683 11:50:48.773510 [Byte1]: 32
8684 11:50:48.777915
8685 11:50:48.778355 Set Vref, RX VrefLevel [Byte0]: 33
8686 11:50:48.781132 [Byte1]: 33
8687 11:50:48.786319
8688 11:50:48.786849 Set Vref, RX VrefLevel [Byte0]: 34
8689 11:50:48.788812 [Byte1]: 34
8690 11:50:48.793255
8691 11:50:48.793711 Set Vref, RX VrefLevel [Byte0]: 35
8692 11:50:48.796572 [Byte1]: 35
8693 11:50:48.800549
8694 11:50:48.800971 Set Vref, RX VrefLevel [Byte0]: 36
8695 11:50:48.803812 [Byte1]: 36
8696 11:50:48.808437
8697 11:50:48.808860 Set Vref, RX VrefLevel [Byte0]: 37
8698 11:50:48.812206 [Byte1]: 37
8699 11:50:48.815989
8700 11:50:48.816524 Set Vref, RX VrefLevel [Byte0]: 38
8701 11:50:48.819457 [Byte1]: 38
8702 11:50:48.823664
8703 11:50:48.824234 Set Vref, RX VrefLevel [Byte0]: 39
8704 11:50:48.827233 [Byte1]: 39
8705 11:50:48.831002
8706 11:50:48.831480 Set Vref, RX VrefLevel [Byte0]: 40
8707 11:50:48.834432 [Byte1]: 40
8708 11:50:48.838719
8709 11:50:48.839135 Set Vref, RX VrefLevel [Byte0]: 41
8710 11:50:48.842451 [Byte1]: 41
8711 11:50:48.846238
8712 11:50:48.846652 Set Vref, RX VrefLevel [Byte0]: 42
8713 11:50:48.849573 [Byte1]: 42
8714 11:50:48.853892
8715 11:50:48.854463 Set Vref, RX VrefLevel [Byte0]: 43
8716 11:50:48.857255 [Byte1]: 43
8717 11:50:48.861760
8718 11:50:48.862174 Set Vref, RX VrefLevel [Byte0]: 44
8719 11:50:48.864985 [Byte1]: 44
8720 11:50:48.868857
8721 11:50:48.869539 Set Vref, RX VrefLevel [Byte0]: 45
8722 11:50:48.872502 [Byte1]: 45
8723 11:50:48.876821
8724 11:50:48.877236 Set Vref, RX VrefLevel [Byte0]: 46
8725 11:50:48.880461 [Byte1]: 46
8726 11:50:48.884851
8727 11:50:48.885495 Set Vref, RX VrefLevel [Byte0]: 47
8728 11:50:48.887547 [Byte1]: 47
8729 11:50:48.891992
8730 11:50:48.892406 Set Vref, RX VrefLevel [Byte0]: 48
8731 11:50:48.895236 [Byte1]: 48
8732 11:50:48.899813
8733 11:50:48.900255 Set Vref, RX VrefLevel [Byte0]: 49
8734 11:50:48.902906 [Byte1]: 49
8735 11:50:48.907513
8736 11:50:48.907937 Set Vref, RX VrefLevel [Byte0]: 50
8737 11:50:48.910437 [Byte1]: 50
8738 11:50:48.915465
8739 11:50:48.915892 Set Vref, RX VrefLevel [Byte0]: 51
8740 11:50:48.918245 [Byte1]: 51
8741 11:50:48.922914
8742 11:50:48.923340 Set Vref, RX VrefLevel [Byte0]: 52
8743 11:50:48.925566 [Byte1]: 52
8744 11:50:48.929961
8745 11:50:48.930188 Set Vref, RX VrefLevel [Byte0]: 53
8746 11:50:48.933430 [Byte1]: 53
8747 11:50:48.938012
8748 11:50:48.938194 Set Vref, RX VrefLevel [Byte0]: 54
8749 11:50:48.941869 [Byte1]: 54
8750 11:50:48.945653
8751 11:50:48.945838 Set Vref, RX VrefLevel [Byte0]: 55
8752 11:50:48.948633 [Byte1]: 55
8753 11:50:48.952709
8754 11:50:48.952934 Set Vref, RX VrefLevel [Byte0]: 56
8755 11:50:48.956158 [Byte1]: 56
8756 11:50:48.960129
8757 11:50:48.960318 Set Vref, RX VrefLevel [Byte0]: 57
8758 11:50:48.964430 [Byte1]: 57
8759 11:50:48.967781
8760 11:50:48.968047 Set Vref, RX VrefLevel [Byte0]: 58
8761 11:50:48.971463 [Byte1]: 58
8762 11:50:48.975278
8763 11:50:48.975469 Set Vref, RX VrefLevel [Byte0]: 59
8764 11:50:48.978807 [Byte1]: 59
8765 11:50:48.983416
8766 11:50:48.983600 Set Vref, RX VrefLevel [Byte0]: 60
8767 11:50:48.986311 [Byte1]: 60
8768 11:50:48.991074
8769 11:50:48.991258 Set Vref, RX VrefLevel [Byte0]: 61
8770 11:50:48.994089 [Byte1]: 61
8771 11:50:48.998748
8772 11:50:48.998930 Set Vref, RX VrefLevel [Byte0]: 62
8773 11:50:49.002143 [Byte1]: 62
8774 11:50:49.005878
8775 11:50:49.006062 Set Vref, RX VrefLevel [Byte0]: 63
8776 11:50:49.009281 [Byte1]: 63
8777 11:50:49.014452
8778 11:50:49.014635 Set Vref, RX VrefLevel [Byte0]: 64
8779 11:50:49.016859 [Byte1]: 64
8780 11:50:49.021258
8781 11:50:49.021726 Set Vref, RX VrefLevel [Byte0]: 65
8782 11:50:49.024831 [Byte1]: 65
8783 11:50:49.029216
8784 11:50:49.029741 Set Vref, RX VrefLevel [Byte0]: 66
8785 11:50:49.032665 [Byte1]: 66
8786 11:50:49.036797
8787 11:50:49.037223 Set Vref, RX VrefLevel [Byte0]: 67
8788 11:50:49.039875 [Byte1]: 67
8789 11:50:49.044284
8790 11:50:49.044715 Set Vref, RX VrefLevel [Byte0]: 68
8791 11:50:49.048528 [Byte1]: 68
8792 11:50:49.052104
8793 11:50:49.052628 Set Vref, RX VrefLevel [Byte0]: 69
8794 11:50:49.055319 [Byte1]: 69
8795 11:50:49.059473
8796 11:50:49.059900 Set Vref, RX VrefLevel [Byte0]: 70
8797 11:50:49.063097 [Byte1]: 70
8798 11:50:49.067443
8799 11:50:49.067991 Set Vref, RX VrefLevel [Byte0]: 71
8800 11:50:49.070560 [Byte1]: 71
8801 11:50:49.074622
8802 11:50:49.075201 Set Vref, RX VrefLevel [Byte0]: 72
8803 11:50:49.078065 [Byte1]: 72
8804 11:50:49.082717
8805 11:50:49.083172 Set Vref, RX VrefLevel [Byte0]: 73
8806 11:50:49.085406 [Byte1]: 73
8807 11:50:49.090215
8808 11:50:49.090638 Final RX Vref Byte 0 = 53 to rank0
8809 11:50:49.093206 Final RX Vref Byte 1 = 61 to rank0
8810 11:50:49.097208 Final RX Vref Byte 0 = 53 to rank1
8811 11:50:49.099806 Final RX Vref Byte 1 = 61 to rank1==
8812 11:50:49.102978 Dram Type= 6, Freq= 0, CH_1, rank 0
8813 11:50:49.109817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 11:50:49.110253 ==
8815 11:50:49.110596 DQS Delay:
8816 11:50:49.113297 DQS0 = 0, DQS1 = 0
8817 11:50:49.113769 DQM Delay:
8818 11:50:49.114112 DQM0 = 133, DQM1 = 128
8819 11:50:49.116465 DQ Delay:
8820 11:50:49.119605 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8821 11:50:49.122983 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8822 11:50:49.126429 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8823 11:50:49.129965 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8824 11:50:49.130488
8825 11:50:49.130921
8826 11:50:49.131257
8827 11:50:49.132812 [DramC_TX_OE_Calibration] TA2
8828 11:50:49.136440 Original DQ_B0 (3 6) =30, OEN = 27
8829 11:50:49.139346 Original DQ_B1 (3 6) =30, OEN = 27
8830 11:50:49.142782 24, 0x0, End_B0=24 End_B1=24
8831 11:50:49.143311 25, 0x0, End_B0=25 End_B1=25
8832 11:50:49.146039 26, 0x0, End_B0=26 End_B1=26
8833 11:50:49.149448 27, 0x0, End_B0=27 End_B1=27
8834 11:50:49.152547 28, 0x0, End_B0=28 End_B1=28
8835 11:50:49.155928 29, 0x0, End_B0=29 End_B1=29
8836 11:50:49.156363 30, 0x0, End_B0=30 End_B1=30
8837 11:50:49.159720 31, 0x4141, End_B0=30 End_B1=30
8838 11:50:49.162769 Byte0 end_step=30 best_step=27
8839 11:50:49.165927 Byte1 end_step=30 best_step=27
8840 11:50:49.169009 Byte0 TX OE(2T, 0.5T) = (3, 3)
8841 11:50:49.172421 Byte1 TX OE(2T, 0.5T) = (3, 3)
8842 11:50:49.172849
8843 11:50:49.173185
8844 11:50:49.179323 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8845 11:50:49.182186 CH1 RK0: MR19=303, MR18=1A10
8846 11:50:49.189035 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8847 11:50:49.189497
8848 11:50:49.192101 ----->DramcWriteLeveling(PI) begin...
8849 11:50:49.192535 ==
8850 11:50:49.195516 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 11:50:49.198534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 11:50:49.199047 ==
8853 11:50:49.201871 Write leveling (Byte 0): 24 => 24
8854 11:50:49.205377 Write leveling (Byte 1): 26 => 26
8855 11:50:49.208681 DramcWriteLeveling(PI) end<-----
8856 11:50:49.209236
8857 11:50:49.209837 ==
8858 11:50:49.211763 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 11:50:49.215581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 11:50:49.218368 ==
8861 11:50:49.218787 [Gating] SW mode calibration
8862 11:50:49.229371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8863 11:50:49.231823 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8864 11:50:49.235181 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 11:50:49.241842 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 11:50:49.245521 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 11:50:49.248394 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8868 11:50:49.255227 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 11:50:49.258059 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 11:50:49.261225 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 11:50:49.267952 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 11:50:49.271167 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 11:50:49.274523 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 11:50:49.281632 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8875 11:50:49.285020 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8876 11:50:49.287967 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 11:50:49.294918 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 11:50:49.297861 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 11:50:49.301254 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 11:50:49.307322 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 11:50:49.310731 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 11:50:49.315110 1 6 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8883 11:50:49.320854 1 6 12 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8884 11:50:49.323843 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 11:50:49.327411 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 11:50:49.333675 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 11:50:49.337036 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 11:50:49.340288 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 11:50:49.347133 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 11:50:49.350214 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 11:50:49.353316 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8892 11:50:49.360852 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8893 11:50:49.363691 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 11:50:49.366396 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 11:50:49.373132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 11:50:49.376737 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 11:50:49.380097 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 11:50:49.386397 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 11:50:49.390296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 11:50:49.393244 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 11:50:49.399497 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 11:50:49.403206 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 11:50:49.406218 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 11:50:49.412744 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 11:50:49.416159 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 11:50:49.422772 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8907 11:50:49.425802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8908 11:50:49.429435 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8909 11:50:49.432386 Total UI for P1: 0, mck2ui 16
8910 11:50:49.436477 best dqsien dly found for B0: ( 1, 9, 12)
8911 11:50:49.438679 Total UI for P1: 0, mck2ui 16
8912 11:50:49.443084 best dqsien dly found for B1: ( 1, 9, 10)
8913 11:50:49.445681 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8914 11:50:49.449254 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8915 11:50:49.449715
8916 11:50:49.455378 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8917 11:50:49.458816 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8918 11:50:49.459244 [Gating] SW calibration Done
8919 11:50:49.462143 ==
8920 11:50:49.465187 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 11:50:49.468753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 11:50:49.469176 ==
8923 11:50:49.469561 RX Vref Scan: 0
8924 11:50:49.469884
8925 11:50:49.471907 RX Vref 0 -> 0, step: 1
8926 11:50:49.472332
8927 11:50:49.475238 RX Delay 0 -> 252, step: 8
8928 11:50:49.479612 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8929 11:50:49.482175 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8930 11:50:49.485237 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8931 11:50:49.491715 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8932 11:50:49.494913 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8933 11:50:49.498401 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8934 11:50:49.501711 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8935 11:50:49.504973 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8936 11:50:49.511604 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8937 11:50:49.515273 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8938 11:50:49.518542 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8939 11:50:49.521569 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8940 11:50:49.528236 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8941 11:50:49.531477 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8942 11:50:49.534698 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8943 11:50:49.537989 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8944 11:50:49.538520 ==
8945 11:50:49.541873 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 11:50:49.547882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 11:50:49.548321 ==
8948 11:50:49.548702 DQS Delay:
8949 11:50:49.549016 DQS0 = 0, DQS1 = 0
8950 11:50:49.551277 DQM Delay:
8951 11:50:49.551692 DQM0 = 136, DQM1 = 130
8952 11:50:49.554658 DQ Delay:
8953 11:50:49.558105 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8954 11:50:49.561347 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8955 11:50:49.564708 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8956 11:50:49.568256 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8957 11:50:49.568801
8958 11:50:49.569276
8959 11:50:49.569778 ==
8960 11:50:49.570953 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 11:50:49.574546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 11:50:49.577821 ==
8963 11:50:49.578322
8964 11:50:49.578753
8965 11:50:49.579098 TX Vref Scan disable
8966 11:50:49.581644 == TX Byte 0 ==
8967 11:50:49.584041 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8968 11:50:49.587333 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 11:50:49.590780 == TX Byte 1 ==
8970 11:50:49.593952 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8971 11:50:49.600599 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8972 11:50:49.601084 ==
8973 11:50:49.604409 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 11:50:49.607076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 11:50:49.607521 ==
8976 11:50:49.620310
8977 11:50:49.623879 TX Vref early break, caculate TX vref
8978 11:50:49.626945 TX Vref=16, minBit 1, minWin=22, winSum=387
8979 11:50:49.630588 TX Vref=18, minBit 0, minWin=23, winSum=393
8980 11:50:49.634057 TX Vref=20, minBit 5, minWin=23, winSum=400
8981 11:50:49.637282 TX Vref=22, minBit 1, minWin=24, winSum=409
8982 11:50:49.640762 TX Vref=24, minBit 5, minWin=25, winSum=417
8983 11:50:49.647500 TX Vref=26, minBit 0, minWin=24, winSum=421
8984 11:50:49.650748 TX Vref=28, minBit 0, minWin=25, winSum=423
8985 11:50:49.655047 TX Vref=30, minBit 0, minWin=24, winSum=419
8986 11:50:49.657397 TX Vref=32, minBit 3, minWin=24, winSum=409
8987 11:50:49.660790 TX Vref=34, minBit 0, minWin=23, winSum=401
8988 11:50:49.663837 TX Vref=36, minBit 0, minWin=23, winSum=388
8989 11:50:49.670628 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8990 11:50:49.671136
8991 11:50:49.673835 Final TX Range 0 Vref 28
8992 11:50:49.674257
8993 11:50:49.674588 ==
8994 11:50:49.676874 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 11:50:49.680287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 11:50:49.680762 ==
8997 11:50:49.683385
8998 11:50:49.683802
8999 11:50:49.684130 TX Vref Scan disable
9000 11:50:49.690227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9001 11:50:49.690748 == TX Byte 0 ==
9002 11:50:49.693466 u2DelayCellOfst[0]=26 cells (7 PI)
9003 11:50:49.696617 u2DelayCellOfst[1]=18 cells (5 PI)
9004 11:50:49.700184 u2DelayCellOfst[2]=0 cells (0 PI)
9005 11:50:49.704035 u2DelayCellOfst[3]=11 cells (3 PI)
9006 11:50:49.706382 u2DelayCellOfst[4]=14 cells (4 PI)
9007 11:50:49.709908 u2DelayCellOfst[5]=26 cells (7 PI)
9008 11:50:49.713359 u2DelayCellOfst[6]=26 cells (7 PI)
9009 11:50:49.716414 u2DelayCellOfst[7]=11 cells (3 PI)
9010 11:50:49.719587 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9011 11:50:49.722892 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9012 11:50:49.726855 == TX Byte 1 ==
9013 11:50:49.729902 u2DelayCellOfst[8]=0 cells (0 PI)
9014 11:50:49.732981 u2DelayCellOfst[9]=3 cells (1 PI)
9015 11:50:49.736451 u2DelayCellOfst[10]=11 cells (3 PI)
9016 11:50:49.739700 u2DelayCellOfst[11]=7 cells (2 PI)
9017 11:50:49.743244 u2DelayCellOfst[12]=18 cells (5 PI)
9018 11:50:49.745803 u2DelayCellOfst[13]=18 cells (5 PI)
9019 11:50:49.748943 u2DelayCellOfst[14]=22 cells (6 PI)
9020 11:50:49.749030 u2DelayCellOfst[15]=18 cells (5 PI)
9021 11:50:49.755330 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9022 11:50:49.759000 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9023 11:50:49.762478 DramC Write-DBI on
9024 11:50:49.762573 ==
9025 11:50:49.765480 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 11:50:49.769222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 11:50:49.769325 ==
9028 11:50:49.769416
9029 11:50:49.769497
9030 11:50:49.772067 TX Vref Scan disable
9031 11:50:49.772179 == TX Byte 0 ==
9032 11:50:49.779038 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9033 11:50:49.779162 == TX Byte 1 ==
9034 11:50:49.782319 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9035 11:50:49.785089 DramC Write-DBI off
9036 11:50:49.785195
9037 11:50:49.785262 [DATLAT]
9038 11:50:49.788455 Freq=1600, CH1 RK1
9039 11:50:49.788537
9040 11:50:49.788602 DATLAT Default: 0xf
9041 11:50:49.791842 0, 0xFFFF, sum = 0
9042 11:50:49.791927 1, 0xFFFF, sum = 0
9043 11:50:49.795595 2, 0xFFFF, sum = 0
9044 11:50:49.798670 3, 0xFFFF, sum = 0
9045 11:50:49.798761 4, 0xFFFF, sum = 0
9046 11:50:49.802418 5, 0xFFFF, sum = 0
9047 11:50:49.802850 6, 0xFFFF, sum = 0
9048 11:50:49.805577 7, 0xFFFF, sum = 0
9049 11:50:49.806014 8, 0xFFFF, sum = 0
9050 11:50:49.808822 9, 0xFFFF, sum = 0
9051 11:50:49.809513 10, 0xFFFF, sum = 0
9052 11:50:49.812312 11, 0xFFFF, sum = 0
9053 11:50:49.812742 12, 0xFFFF, sum = 0
9054 11:50:49.815222 13, 0xFFFF, sum = 0
9055 11:50:49.815656 14, 0x0, sum = 1
9056 11:50:49.819564 15, 0x0, sum = 2
9057 11:50:49.820122 16, 0x0, sum = 3
9058 11:50:49.822101 17, 0x0, sum = 4
9059 11:50:49.822612 best_step = 15
9060 11:50:49.823143
9061 11:50:49.823624 ==
9062 11:50:49.825359 Dram Type= 6, Freq= 0, CH_1, rank 1
9063 11:50:49.832424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9064 11:50:49.832899 ==
9065 11:50:49.833294 RX Vref Scan: 0
9066 11:50:49.833725
9067 11:50:49.835479 RX Vref 0 -> 0, step: 1
9068 11:50:49.835901
9069 11:50:49.838382 RX Delay 11 -> 252, step: 4
9070 11:50:49.841861 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9071 11:50:49.845338 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9072 11:50:49.849313 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9073 11:50:49.855094 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9074 11:50:49.858733 iDelay=199, Bit 4, Center 132 (75 ~ 190) 116
9075 11:50:49.861682 iDelay=199, Bit 5, Center 142 (91 ~ 194) 104
9076 11:50:49.864832 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9077 11:50:49.868378 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9078 11:50:49.874846 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9079 11:50:49.878022 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9080 11:50:49.881275 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9081 11:50:49.885483 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9082 11:50:49.891670 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9083 11:50:49.894764 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9084 11:50:49.897810 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9085 11:50:49.900905 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9086 11:50:49.901523 ==
9087 11:50:49.904677 Dram Type= 6, Freq= 0, CH_1, rank 1
9088 11:50:49.910961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9089 11:50:49.911394 ==
9090 11:50:49.911764 DQS Delay:
9091 11:50:49.912105 DQS0 = 0, DQS1 = 0
9092 11:50:49.914690 DQM Delay:
9093 11:50:49.915314 DQM0 = 133, DQM1 = 127
9094 11:50:49.917990 DQ Delay:
9095 11:50:49.921326 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9096 11:50:49.924017 DQ4 =132, DQ5 =142, DQ6 =144, DQ7 =130
9097 11:50:49.927320 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9098 11:50:49.930590 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9099 11:50:49.931006
9100 11:50:49.931334
9101 11:50:49.931638
9102 11:50:49.934496 [DramC_TX_OE_Calibration] TA2
9103 11:50:49.937275 Original DQ_B0 (3 6) =30, OEN = 27
9104 11:50:49.940921 Original DQ_B1 (3 6) =30, OEN = 27
9105 11:50:49.944124 24, 0x0, End_B0=24 End_B1=24
9106 11:50:49.944547 25, 0x0, End_B0=25 End_B1=25
9107 11:50:49.947168 26, 0x0, End_B0=26 End_B1=26
9108 11:50:49.950588 27, 0x0, End_B0=27 End_B1=27
9109 11:50:49.954938 28, 0x0, End_B0=28 End_B1=28
9110 11:50:49.957046 29, 0x0, End_B0=29 End_B1=29
9111 11:50:49.957660 30, 0x0, End_B0=30 End_B1=30
9112 11:50:49.960552 31, 0x4141, End_B0=30 End_B1=30
9113 11:50:49.963666 Byte0 end_step=30 best_step=27
9114 11:50:49.967109 Byte1 end_step=30 best_step=27
9115 11:50:49.971331 Byte0 TX OE(2T, 0.5T) = (3, 3)
9116 11:50:49.973444 Byte1 TX OE(2T, 0.5T) = (3, 3)
9117 11:50:49.973865
9118 11:50:49.974200
9119 11:50:49.979872 [DQSOSCAuto] RK1, (LSB)MR18= 0xa07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9120 11:50:49.983453 CH1 RK1: MR19=303, MR18=A07
9121 11:50:49.989786 CH1_RK1: MR19=0x303, MR18=0xA07, DQSOSC=404, MR23=63, INC=22, DEC=15
9122 11:50:49.993502 [RxdqsGatingPostProcess] freq 1600
9123 11:50:49.996268 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9124 11:50:50.000091 best DQS0 dly(2T, 0.5T) = (1, 1)
9125 11:50:50.003444 best DQS1 dly(2T, 0.5T) = (1, 1)
9126 11:50:50.006987 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9127 11:50:50.010452 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9128 11:50:50.013242 best DQS0 dly(2T, 0.5T) = (1, 1)
9129 11:50:50.016441 best DQS1 dly(2T, 0.5T) = (1, 1)
9130 11:50:50.020152 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9131 11:50:50.022779 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9132 11:50:50.026342 Pre-setting of DQS Precalculation
9133 11:50:50.029642 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9134 11:50:50.039510 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9135 11:50:50.046353 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 11:50:50.046774
9137 11:50:50.047103
9138 11:50:50.049159 [Calibration Summary] 3200 Mbps
9139 11:50:50.049618 CH 0, Rank 0
9140 11:50:50.052837 SW Impedance : PASS
9141 11:50:50.053257 DUTY Scan : NO K
9142 11:50:50.055879 ZQ Calibration : PASS
9143 11:50:50.059204 Jitter Meter : NO K
9144 11:50:50.059695 CBT Training : PASS
9145 11:50:50.062331 Write leveling : PASS
9146 11:50:50.066289 RX DQS gating : PASS
9147 11:50:50.066811 RX DQ/DQS(RDDQC) : PASS
9148 11:50:50.070016 TX DQ/DQS : PASS
9149 11:50:50.072525 RX DATLAT : PASS
9150 11:50:50.073004 RX DQ/DQS(Engine): PASS
9151 11:50:50.076216 TX OE : PASS
9152 11:50:50.076744 All Pass.
9153 11:50:50.077080
9154 11:50:50.079271 CH 0, Rank 1
9155 11:50:50.079692 SW Impedance : PASS
9156 11:50:50.082254 DUTY Scan : NO K
9157 11:50:50.085871 ZQ Calibration : PASS
9158 11:50:50.086296 Jitter Meter : NO K
9159 11:50:50.089443 CBT Training : PASS
9160 11:50:50.089873 Write leveling : PASS
9161 11:50:50.092066 RX DQS gating : PASS
9162 11:50:50.095800 RX DQ/DQS(RDDQC) : PASS
9163 11:50:50.096278 TX DQ/DQS : PASS
9164 11:50:50.099176 RX DATLAT : PASS
9165 11:50:50.102447 RX DQ/DQS(Engine): PASS
9166 11:50:50.102867 TX OE : PASS
9167 11:50:50.105401 All Pass.
9168 11:50:50.105924
9169 11:50:50.106257 CH 1, Rank 0
9170 11:50:50.109060 SW Impedance : PASS
9171 11:50:50.109656 DUTY Scan : NO K
9172 11:50:50.111719 ZQ Calibration : PASS
9173 11:50:50.115111 Jitter Meter : NO K
9174 11:50:50.115653 CBT Training : PASS
9175 11:50:50.118715 Write leveling : PASS
9176 11:50:50.121945 RX DQS gating : PASS
9177 11:50:50.122362 RX DQ/DQS(RDDQC) : PASS
9178 11:50:50.125164 TX DQ/DQS : PASS
9179 11:50:50.128734 RX DATLAT : PASS
9180 11:50:50.129271 RX DQ/DQS(Engine): PASS
9181 11:50:50.132042 TX OE : PASS
9182 11:50:50.132566 All Pass.
9183 11:50:50.132902
9184 11:50:50.135105 CH 1, Rank 1
9185 11:50:50.135522 SW Impedance : PASS
9186 11:50:50.138475 DUTY Scan : NO K
9187 11:50:50.141591 ZQ Calibration : PASS
9188 11:50:50.142154 Jitter Meter : NO K
9189 11:50:50.145086 CBT Training : PASS
9190 11:50:50.148197 Write leveling : PASS
9191 11:50:50.148618 RX DQS gating : PASS
9192 11:50:50.151887 RX DQ/DQS(RDDQC) : PASS
9193 11:50:50.154953 TX DQ/DQS : PASS
9194 11:50:50.155401 RX DATLAT : PASS
9195 11:50:50.157933 RX DQ/DQS(Engine): PASS
9196 11:50:50.161286 TX OE : PASS
9197 11:50:50.161827 All Pass.
9198 11:50:50.162361
9199 11:50:50.162817 DramC Write-DBI on
9200 11:50:50.164536 PER_BANK_REFRESH: Hybrid Mode
9201 11:50:50.168217 TX_TRACKING: ON
9202 11:50:50.174735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9203 11:50:50.185082 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9204 11:50:50.191237 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9205 11:50:50.194390 [FAST_K] Save calibration result to emmc
9206 11:50:50.197394 sync common calibartion params.
9207 11:50:50.200939 sync cbt_mode0:1, 1:1
9208 11:50:50.201599 dram_init: ddr_geometry: 2
9209 11:50:50.204547 dram_init: ddr_geometry: 2
9210 11:50:50.207161 dram_init: ddr_geometry: 2
9211 11:50:50.207244 0:dram_rank_size:100000000
9212 11:50:50.210629 1:dram_rank_size:100000000
9213 11:50:50.217314 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9214 11:50:50.220224 DFS_SHUFFLE_HW_MODE: ON
9215 11:50:50.224096 dramc_set_vcore_voltage set vcore to 725000
9216 11:50:50.224179 Read voltage for 1600, 0
9217 11:50:50.226667 Vio18 = 0
9218 11:50:50.226750 Vcore = 725000
9219 11:50:50.226816 Vdram = 0
9220 11:50:50.230290 Vddq = 0
9221 11:50:50.230372 Vmddr = 0
9222 11:50:50.233601 switch to 3200 Mbps bootup
9223 11:50:50.233687 [DramcRunTimeConfig]
9224 11:50:50.233754 PHYPLL
9225 11:50:50.236907 DPM_CONTROL_AFTERK: ON
9226 11:50:50.240209 PER_BANK_REFRESH: ON
9227 11:50:50.240291 REFRESH_OVERHEAD_REDUCTION: ON
9228 11:50:50.243391 CMD_PICG_NEW_MODE: OFF
9229 11:50:50.247240 XRTWTW_NEW_MODE: ON
9230 11:50:50.247322 XRTRTR_NEW_MODE: ON
9231 11:50:50.250237 TX_TRACKING: ON
9232 11:50:50.250323 RDSEL_TRACKING: OFF
9233 11:50:50.253440 DQS Precalculation for DVFS: ON
9234 11:50:50.256686 RX_TRACKING: OFF
9235 11:50:50.256804 HW_GATING DBG: ON
9236 11:50:50.260180 ZQCS_ENABLE_LP4: ON
9237 11:50:50.260269 RX_PICG_NEW_MODE: ON
9238 11:50:50.263268 TX_PICG_NEW_MODE: ON
9239 11:50:50.263342 ENABLE_RX_DCM_DPHY: ON
9240 11:50:50.266831 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9241 11:50:50.270009 DUMMY_READ_FOR_TRACKING: OFF
9242 11:50:50.273358 !!! SPM_CONTROL_AFTERK: OFF
9243 11:50:50.276814 !!! SPM could not control APHY
9244 11:50:50.276895 IMPEDANCE_TRACKING: ON
9245 11:50:50.279912 TEMP_SENSOR: ON
9246 11:50:50.279995 HW_SAVE_FOR_SR: OFF
9247 11:50:50.283322 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9248 11:50:50.287060 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9249 11:50:50.289624 Read ODT Tracking: ON
9250 11:50:50.292777 Refresh Rate DeBounce: ON
9251 11:50:50.292859 DFS_NO_QUEUE_FLUSH: ON
9252 11:50:50.296419 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9253 11:50:50.299509 ENABLE_DFS_RUNTIME_MRW: OFF
9254 11:50:50.302762 DDR_RESERVE_NEW_MODE: ON
9255 11:50:50.302844 MR_CBT_SWITCH_FREQ: ON
9256 11:50:50.306282 =========================
9257 11:50:50.325037 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9258 11:50:50.328593 dram_init: ddr_geometry: 2
9259 11:50:50.346437 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9260 11:50:50.349515 dram_init: dram init end (result: 0)
9261 11:50:50.356031 DRAM-K: Full calibration passed in 24623 msecs
9262 11:50:50.359829 MRC: failed to locate region type 0.
9263 11:50:50.359916 DRAM rank0 size:0x100000000,
9264 11:50:50.363083 DRAM rank1 size=0x100000000
9265 11:50:50.372737 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9266 11:50:50.379509 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9267 11:50:50.389158 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9268 11:50:50.395829 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9269 11:50:50.395914 DRAM rank0 size:0x100000000,
9270 11:50:50.399384 DRAM rank1 size=0x100000000
9271 11:50:50.399474 CBMEM:
9272 11:50:50.402604 IMD: root @ 0xfffff000 254 entries.
9273 11:50:50.405435 IMD: root @ 0xffffec00 62 entries.
9274 11:50:50.409535 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9275 11:50:50.415682 WARNING: RO_VPD is uninitialized or empty.
9276 11:50:50.418794 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9277 11:50:50.426408 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9278 11:50:50.439500 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9279 11:50:50.450922 BS: romstage times (exec / console): total (unknown) / 24117 ms
9280 11:50:50.451002
9281 11:50:50.451066
9282 11:50:50.460671 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9283 11:50:50.463945 ARM64: Exception handlers installed.
9284 11:50:50.467165 ARM64: Testing exception
9285 11:50:50.470441 ARM64: Done test exception
9286 11:50:50.470544 Enumerating buses...
9287 11:50:50.473826 Show all devs... Before device enumeration.
9288 11:50:50.477307 Root Device: enabled 1
9289 11:50:50.480243 CPU_CLUSTER: 0: enabled 1
9290 11:50:50.480356 CPU: 00: enabled 1
9291 11:50:50.483554 Compare with tree...
9292 11:50:50.483637 Root Device: enabled 1
9293 11:50:50.487123 CPU_CLUSTER: 0: enabled 1
9294 11:50:50.489964 CPU: 00: enabled 1
9295 11:50:50.490064 Root Device scanning...
9296 11:50:50.493647 scan_static_bus for Root Device
9297 11:50:50.496831 CPU_CLUSTER: 0 enabled
9298 11:50:50.500122 scan_static_bus for Root Device done
9299 11:50:50.503736 scan_bus: bus Root Device finished in 8 msecs
9300 11:50:50.503843 done
9301 11:50:50.509769 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9302 11:50:50.513222 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9303 11:50:50.519820 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9304 11:50:50.526101 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9305 11:50:50.526203 Allocating resources...
9306 11:50:50.529959 Reading resources...
9307 11:50:50.532797 Root Device read_resources bus 0 link: 0
9308 11:50:50.536394 DRAM rank0 size:0x100000000,
9309 11:50:50.536499 DRAM rank1 size=0x100000000
9310 11:50:50.542555 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9311 11:50:50.542638 CPU: 00 missing read_resources
9312 11:50:50.549566 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9313 11:50:50.552356 Root Device read_resources bus 0 link: 0 done
9314 11:50:50.556017 Done reading resources.
9315 11:50:50.559207 Show resources in subtree (Root Device)...After reading.
9316 11:50:50.562460 Root Device child on link 0 CPU_CLUSTER: 0
9317 11:50:50.565665 CPU_CLUSTER: 0 child on link 0 CPU: 00
9318 11:50:50.575642 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9319 11:50:50.575764 CPU: 00
9320 11:50:50.581861 Root Device assign_resources, bus 0 link: 0
9321 11:50:50.585606 CPU_CLUSTER: 0 missing set_resources
9322 11:50:50.588551 Root Device assign_resources, bus 0 link: 0 done
9323 11:50:50.592026 Done setting resources.
9324 11:50:50.594925 Show resources in subtree (Root Device)...After assigning values.
9325 11:50:50.601767 Root Device child on link 0 CPU_CLUSTER: 0
9326 11:50:50.604794 CPU_CLUSTER: 0 child on link 0 CPU: 00
9327 11:50:50.611981 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9328 11:50:50.614981 CPU: 00
9329 11:50:50.615064 Done allocating resources.
9330 11:50:50.621775 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9331 11:50:50.621863 Enabling resources...
9332 11:50:50.625139 done.
9333 11:50:50.628006 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9334 11:50:50.631369 Initializing devices...
9335 11:50:50.631453 Root Device init
9336 11:50:50.634695 init hardware done!
9337 11:50:50.638101 0x00000018: ctrlr->caps
9338 11:50:50.638186 52.000 MHz: ctrlr->f_max
9339 11:50:50.641309 0.400 MHz: ctrlr->f_min
9340 11:50:50.644738 0x40ff8080: ctrlr->voltages
9341 11:50:50.644822 sclk: 390625
9342 11:50:50.644887 Bus Width = 1
9343 11:50:50.647826 sclk: 390625
9344 11:50:50.647908 Bus Width = 1
9345 11:50:50.651043 Early init status = 3
9346 11:50:50.654942 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9347 11:50:50.658239 in-header: 03 fc 00 00 01 00 00 00
9348 11:50:50.661367 in-data: 00
9349 11:50:50.664783 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9350 11:50:50.670253 in-header: 03 fd 00 00 00 00 00 00
9351 11:50:50.674373 in-data:
9352 11:50:50.676576 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9353 11:50:50.682207 in-header: 03 fc 00 00 01 00 00 00
9354 11:50:50.685866 in-data: 00
9355 11:50:50.689280 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9356 11:50:50.694979 in-header: 03 fd 00 00 00 00 00 00
9357 11:50:50.698294 in-data:
9358 11:50:50.701191 [SSUSB] Setting up USB HOST controller...
9359 11:50:50.704088 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9360 11:50:50.707518 [SSUSB] phy power-on done.
9361 11:50:50.711060 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9362 11:50:50.717378 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9363 11:50:50.720761 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9364 11:50:50.727500 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9365 11:50:50.733829 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9366 11:50:50.740856 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9367 11:50:50.747097 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9368 11:50:50.753454 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9369 11:50:50.757244 SPM: binary array size = 0x9dc
9370 11:50:50.760236 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9371 11:50:50.767327 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9372 11:50:50.773357 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9373 11:50:50.780309 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9374 11:50:50.783035 configure_display: Starting display init
9375 11:50:50.817637 anx7625_power_on_init: Init interface.
9376 11:50:50.820957 anx7625_disable_pd_protocol: Disabled PD feature.
9377 11:50:50.824490 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9378 11:50:50.852176 anx7625_start_dp_work: Secure OCM version=00
9379 11:50:50.855458 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9380 11:50:50.870001 sp_tx_get_edid_block: EDID Block = 1
9381 11:50:50.973194 Extracted contents:
9382 11:50:50.976306 header: 00 ff ff ff ff ff ff 00
9383 11:50:50.979508 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9384 11:50:50.983519 version: 01 04
9385 11:50:50.986515 basic params: 95 1f 11 78 0a
9386 11:50:50.989397 chroma info: 76 90 94 55 54 90 27 21 50 54
9387 11:50:50.992773 established: 00 00 00
9388 11:50:50.999347 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9389 11:50:51.003451 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9390 11:50:51.009240 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 11:50:51.015796 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9392 11:50:51.022338 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9393 11:50:51.025592 extensions: 00
9394 11:50:51.025837 checksum: fb
9395 11:50:51.026033
9396 11:50:51.032980 Manufacturer: IVO Model 57d Serial Number 0
9397 11:50:51.033378 Made week 0 of 2020
9398 11:50:51.035829 EDID version: 1.4
9399 11:50:51.036221 Digital display
9400 11:50:51.039833 6 bits per primary color channel
9401 11:50:51.040271 DisplayPort interface
9402 11:50:51.042604 Maximum image size: 31 cm x 17 cm
9403 11:50:51.045673 Gamma: 220%
9404 11:50:51.046098 Check DPMS levels
9405 11:50:51.052197 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9406 11:50:51.055507 First detailed timing is preferred timing
9407 11:50:51.055939 Established timings supported:
9408 11:50:51.058645 Standard timings supported:
9409 11:50:51.061985 Detailed timings
9410 11:50:51.065308 Hex of detail: 383680a07038204018303c0035ae10000019
9411 11:50:51.071872 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9412 11:50:51.075395 0780 0798 07c8 0820 hborder 0
9413 11:50:51.078524 0438 043b 0447 0458 vborder 0
9414 11:50:51.082040 -hsync -vsync
9415 11:50:51.082468 Did detailed timing
9416 11:50:51.088592 Hex of detail: 000000000000000000000000000000000000
9417 11:50:51.091859 Manufacturer-specified data, tag 0
9418 11:50:51.094929 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9419 11:50:51.099193 ASCII string: InfoVision
9420 11:50:51.101832 Hex of detail: 000000fe00523134304e574635205248200a
9421 11:50:51.105086 ASCII string: R140NWF5 RH
9422 11:50:51.105312 Checksum
9423 11:50:51.107999 Checksum: 0xfb (valid)
9424 11:50:51.111980 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9425 11:50:51.115079 DSI data_rate: 832800000 bps
9426 11:50:51.121456 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9427 11:50:51.125483 anx7625_parse_edid: pixelclock(138800).
9428 11:50:51.128052 hactive(1920), hsync(48), hfp(24), hbp(88)
9429 11:50:51.131091 vactive(1080), vsync(12), vfp(3), vbp(17)
9430 11:50:51.134464 anx7625_dsi_config: config dsi.
9431 11:50:51.141177 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9432 11:50:51.154977 anx7625_dsi_config: success to config DSI
9433 11:50:51.158346 anx7625_dp_start: MIPI phy setup OK.
9434 11:50:51.161291 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9435 11:50:51.165153 mtk_ddp_mode_set invalid vrefresh 60
9436 11:50:51.167906 main_disp_path_setup
9437 11:50:51.168133 ovl_layer_smi_id_en
9438 11:50:51.171400 ovl_layer_smi_id_en
9439 11:50:51.171630 ccorr_config
9440 11:50:51.171812 aal_config
9441 11:50:51.174921 gamma_config
9442 11:50:51.175150 postmask_config
9443 11:50:51.177895 dither_config
9444 11:50:51.181520 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9445 11:50:51.188048 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9446 11:50:51.191219 Root Device init finished in 555 msecs
9447 11:50:51.194829 CPU_CLUSTER: 0 init
9448 11:50:51.201163 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9449 11:50:51.207535 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9450 11:50:51.207765 APU_MBOX 0x190000b0 = 0x10001
9451 11:50:51.211438 APU_MBOX 0x190001b0 = 0x10001
9452 11:50:51.214937 APU_MBOX 0x190005b0 = 0x10001
9453 11:50:51.217859 APU_MBOX 0x190006b0 = 0x10001
9454 11:50:51.224126 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9455 11:50:51.234101 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9456 11:50:51.246287 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9457 11:50:51.252687 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9458 11:50:51.264460 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9459 11:50:51.273612 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9460 11:50:51.276908 CPU_CLUSTER: 0 init finished in 81 msecs
9461 11:50:51.280093 Devices initialized
9462 11:50:51.283424 Show all devs... After init.
9463 11:50:51.283506 Root Device: enabled 1
9464 11:50:51.287011 CPU_CLUSTER: 0: enabled 1
9465 11:50:51.289897 CPU: 00: enabled 1
9466 11:50:51.293378 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9467 11:50:51.296653 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9468 11:50:51.299813 ELOG: NV offset 0x57f000 size 0x1000
9469 11:50:51.306879 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9470 11:50:51.313183 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9471 11:50:51.316505 ELOG: Event(17) added with size 13 at 2023-11-24 11:50:52 UTC
9472 11:50:51.322990 out: cmd=0x121: 03 db 21 01 00 00 00 00
9473 11:50:51.326526 in-header: 03 c1 00 00 2c 00 00 00
9474 11:50:51.337285 in-data: 9e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9475 11:50:51.343516 ELOG: Event(A1) added with size 10 at 2023-11-24 11:50:52 UTC
9476 11:50:51.349529 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9477 11:50:51.356098 ELOG: Event(A0) added with size 9 at 2023-11-24 11:50:52 UTC
9478 11:50:51.359493 elog_add_boot_reason: Logged dev mode boot
9479 11:50:51.366106 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9480 11:50:51.366349 Finalize devices...
9481 11:50:51.369373 Devices finalized
9482 11:50:51.372820 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9483 11:50:51.376377 Writing coreboot table at 0xffe64000
9484 11:50:51.379715 0. 000000000010a000-0000000000113fff: RAMSTAGE
9485 11:50:51.386876 1. 0000000040000000-00000000400fffff: RAM
9486 11:50:51.389492 2. 0000000040100000-000000004032afff: RAMSTAGE
9487 11:50:51.392811 3. 000000004032b000-00000000545fffff: RAM
9488 11:50:51.396424 4. 0000000054600000-000000005465ffff: BL31
9489 11:50:51.399538 5. 0000000054660000-00000000ffe63fff: RAM
9490 11:50:51.406280 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9491 11:50:51.409555 7. 0000000100000000-000000023fffffff: RAM
9492 11:50:51.412433 Passing 5 GPIOs to payload:
9493 11:50:51.416250 NAME | PORT | POLARITY | VALUE
9494 11:50:51.422464 EC in RW | 0x000000aa | low | undefined
9495 11:50:51.425267 EC interrupt | 0x00000005 | low | undefined
9496 11:50:51.428741 TPM interrupt | 0x000000ab | high | undefined
9497 11:50:51.435670 SD card detect | 0x00000011 | high | undefined
9498 11:50:51.438664 speaker enable | 0x00000093 | high | undefined
9499 11:50:51.442938 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9500 11:50:51.446577 in-header: 03 f9 00 00 02 00 00 00
9501 11:50:51.449914 in-data: 02 00
9502 11:50:51.453461 ADC[4]: Raw value=902291 ID=7
9503 11:50:51.456381 ADC[3]: Raw value=214021 ID=1
9504 11:50:51.456463 RAM Code: 0x71
9505 11:50:51.460000 ADC[6]: Raw value=75036 ID=0
9506 11:50:51.463315 ADC[5]: Raw value=213652 ID=1
9507 11:50:51.463397 SKU Code: 0x1
9508 11:50:51.469941 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9509 11:50:51.470024 coreboot table: 964 bytes.
9510 11:50:51.472856 IMD ROOT 0. 0xfffff000 0x00001000
9511 11:50:51.476897 IMD SMALL 1. 0xffffe000 0x00001000
9512 11:50:51.479869 RO MCACHE 2. 0xffffc000 0x00001104
9513 11:50:51.483066 CONSOLE 3. 0xfff7c000 0x00080000
9514 11:50:51.486256 FMAP 4. 0xfff7b000 0x00000452
9515 11:50:51.489546 TIME STAMP 5. 0xfff7a000 0x00000910
9516 11:50:51.493272 VBOOT WORK 6. 0xfff66000 0x00014000
9517 11:50:51.496443 RAMOOPS 7. 0xffe66000 0x00100000
9518 11:50:51.500497 COREBOOT 8. 0xffe64000 0x00002000
9519 11:50:51.502972 IMD small region:
9520 11:50:51.506147 IMD ROOT 0. 0xffffec00 0x00000400
9521 11:50:51.509555 VPD 1. 0xffffeb80 0x0000006c
9522 11:50:51.513268 MMC STATUS 2. 0xffffeb60 0x00000004
9523 11:50:51.516342 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9524 11:50:51.519666 Probing TPM: done!
9525 11:50:51.523107 Connected to device vid:did:rid of 1ae0:0028:00
9526 11:50:51.534311 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9527 11:50:51.537681 Initialized TPM device CR50 revision 0
9528 11:50:51.541052 Checking cr50 for pending updates
9529 11:50:51.544902 Reading cr50 TPM mode
9530 11:50:51.553736 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9531 11:50:51.560298 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9532 11:50:51.600431 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9533 11:50:51.603522 Checking segment from ROM address 0x40100000
9534 11:50:51.607832 Checking segment from ROM address 0x4010001c
9535 11:50:51.613376 Loading segment from ROM address 0x40100000
9536 11:50:51.613532 code (compression=0)
9537 11:50:51.623225 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9538 11:50:51.630939 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9539 11:50:51.631023 it's not compressed!
9540 11:50:51.636806 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9541 11:50:51.643217 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9542 11:50:51.660961 Loading segment from ROM address 0x4010001c
9543 11:50:51.661047 Entry Point 0x80000000
9544 11:50:51.663938 Loaded segments
9545 11:50:51.667332 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9546 11:50:51.674156 Jumping to boot code at 0x80000000(0xffe64000)
9547 11:50:51.681104 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9548 11:50:51.687757 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9549 11:50:51.695257 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9550 11:50:51.699179 Checking segment from ROM address 0x40100000
9551 11:50:51.701790 Checking segment from ROM address 0x4010001c
9552 11:50:51.708718 Loading segment from ROM address 0x40100000
9553 11:50:51.708821 code (compression=1)
9554 11:50:51.715515 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9555 11:50:51.725278 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9556 11:50:51.725918 using LZMA
9557 11:50:51.733808 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9558 11:50:51.740681 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9559 11:50:51.743990 Loading segment from ROM address 0x4010001c
9560 11:50:51.744425 Entry Point 0x54601000
9561 11:50:51.747663 Loaded segments
9562 11:50:51.750251 NOTICE: MT8192 bl31_setup
9563 11:50:51.757913 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9564 11:50:51.760893 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9565 11:50:51.764193 WARNING: region 0:
9566 11:50:51.767433 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 11:50:51.767863 WARNING: region 1:
9568 11:50:51.774095 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9569 11:50:51.777473 WARNING: region 2:
9570 11:50:51.780761 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9571 11:50:51.784109 WARNING: region 3:
9572 11:50:51.787313 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9573 11:50:51.790689 WARNING: region 4:
9574 11:50:51.797717 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9575 11:50:51.798151 WARNING: region 5:
9576 11:50:51.800950 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9577 11:50:51.803885 WARNING: region 6:
9578 11:50:51.807333 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9579 11:50:51.810921 WARNING: region 7:
9580 11:50:51.814158 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9581 11:50:51.821212 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9582 11:50:51.824316 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9583 11:50:51.827089 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9584 11:50:51.833982 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9585 11:50:51.837296 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9586 11:50:51.843725 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9587 11:50:51.847401 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9588 11:50:51.850537 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9589 11:50:51.856841 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9590 11:50:51.860389 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9591 11:50:51.864068 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9592 11:50:51.871105 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9593 11:50:51.874243 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9594 11:50:51.880726 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9595 11:50:51.883432 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9596 11:50:51.887284 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9597 11:50:51.893916 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9598 11:50:51.896752 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9599 11:50:51.900416 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9600 11:50:51.906907 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9601 11:50:51.910564 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9602 11:50:51.917180 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9603 11:50:51.920058 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9604 11:50:51.923331 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9605 11:50:51.930005 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9606 11:50:51.933255 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9607 11:50:51.939858 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9608 11:50:51.943363 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9609 11:50:51.946368 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9610 11:50:51.952961 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9611 11:50:51.956658 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9612 11:50:51.963626 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9613 11:50:51.966769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9614 11:50:51.969644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9615 11:50:51.973211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9616 11:50:51.979928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9617 11:50:51.982835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9618 11:50:51.986099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9619 11:50:51.990142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9620 11:50:51.995745 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9621 11:50:51.999757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9622 11:50:52.002720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9623 11:50:52.006320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9624 11:50:52.012270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9625 11:50:52.015774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9626 11:50:52.019096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9627 11:50:52.025676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9628 11:50:52.029222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9629 11:50:52.032615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9630 11:50:52.039548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9631 11:50:52.042682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9632 11:50:52.046043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9633 11:50:52.052544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9634 11:50:52.056493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9635 11:50:52.062654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9636 11:50:52.065997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9637 11:50:52.072604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9638 11:50:52.076205 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9639 11:50:52.079071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9640 11:50:52.085701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9641 11:50:52.089231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9642 11:50:52.096237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9643 11:50:52.099360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9644 11:50:52.106012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9645 11:50:52.109754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9646 11:50:52.116058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9647 11:50:52.119309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9648 11:50:52.122418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9649 11:50:52.129243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9650 11:50:52.132368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9651 11:50:52.139025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9652 11:50:52.142323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9653 11:50:52.148651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9654 11:50:52.152148 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9655 11:50:52.155374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9656 11:50:52.162262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9657 11:50:52.165570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9658 11:50:52.171837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9659 11:50:52.175630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9660 11:50:52.182003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9661 11:50:52.185085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9662 11:50:52.191864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9663 11:50:52.194947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9664 11:50:52.201795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9665 11:50:52.204508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9666 11:50:52.207901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9667 11:50:52.214436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9668 11:50:52.218192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9669 11:50:52.224887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9670 11:50:52.227934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9671 11:50:52.234801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9672 11:50:52.238276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9673 11:50:52.241919 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9674 11:50:52.247853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9675 11:50:52.251072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9676 11:50:52.258258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9677 11:50:52.261263 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9678 11:50:52.265045 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9679 11:50:52.271194 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9680 11:50:52.275074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9681 11:50:52.277974 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9682 11:50:52.281934 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9683 11:50:52.287769 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9684 11:50:52.291146 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9685 11:50:52.297517 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9686 11:50:52.300871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9687 11:50:52.307556 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9688 11:50:52.310551 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9689 11:50:52.314110 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9690 11:50:52.321279 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9691 11:50:52.324060 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9692 11:50:52.330725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9693 11:50:52.335433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9694 11:50:52.337639 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9695 11:50:52.344974 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9696 11:50:52.347426 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9697 11:50:52.350975 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9698 11:50:52.358158 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9699 11:50:52.360950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9700 11:50:52.364385 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9701 11:50:52.370833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9702 11:50:52.374901 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9703 11:50:52.377971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9704 11:50:52.380705 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9705 11:50:52.387365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9706 11:50:52.391304 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9707 11:50:52.394147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9708 11:50:52.400972 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9709 11:50:52.404810 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9710 11:50:52.411046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9711 11:50:52.414059 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9712 11:50:52.417035 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9713 11:50:52.423734 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9714 11:50:52.427224 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9715 11:50:52.433658 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9716 11:50:52.436879 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9717 11:50:52.440537 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9718 11:50:52.446966 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9719 11:50:52.450372 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9720 11:50:52.457139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9721 11:50:52.460256 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9722 11:50:52.463785 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9723 11:50:52.470516 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9724 11:50:52.473378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9725 11:50:52.479960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9726 11:50:52.483704 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9727 11:50:52.487043 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9728 11:50:52.493929 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9729 11:50:52.497290 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9730 11:50:52.503650 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9731 11:50:52.506867 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9732 11:50:52.509868 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9733 11:50:52.516561 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9734 11:50:52.520304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9735 11:50:52.527591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9736 11:50:52.529997 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9737 11:50:52.533068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9738 11:50:52.539965 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9739 11:50:52.544020 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9740 11:50:52.546860 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9741 11:50:52.552843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9742 11:50:52.556291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9743 11:50:52.562730 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9744 11:50:52.566066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9745 11:50:52.572729 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9746 11:50:52.576296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9747 11:50:52.579308 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9748 11:50:52.585781 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9749 11:50:52.589294 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9750 11:50:52.595650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9751 11:50:52.598864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9752 11:50:52.602218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9753 11:50:52.608992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9754 11:50:52.612591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9755 11:50:52.615530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9756 11:50:52.622605 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9757 11:50:52.626160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9758 11:50:52.632036 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9759 11:50:52.635745 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9760 11:50:52.639238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9761 11:50:52.645355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9762 11:50:52.649357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9763 11:50:52.655352 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9764 11:50:52.658640 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9765 11:50:52.662393 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9766 11:50:52.668524 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9767 11:50:52.671734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9768 11:50:52.678472 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9769 11:50:52.682020 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9770 11:50:52.688870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9771 11:50:52.691431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9772 11:50:52.695131 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9773 11:50:52.701573 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9774 11:50:52.704936 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9775 11:50:52.711541 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9776 11:50:52.714714 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9777 11:50:52.721531 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9778 11:50:52.724570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9779 11:50:52.727654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9780 11:50:52.734120 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9781 11:50:52.737342 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9782 11:50:52.743978 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9783 11:50:52.747719 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9784 11:50:52.753977 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9785 11:50:52.757249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9786 11:50:52.760852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9787 11:50:52.767319 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9788 11:50:52.770669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9789 11:50:52.777905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9790 11:50:52.780364 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9791 11:50:52.786792 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9792 11:50:52.790197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9793 11:50:52.793615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9794 11:50:52.800219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9795 11:50:52.803846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9796 11:50:52.809726 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9797 11:50:52.813303 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9798 11:50:52.819961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9799 11:50:52.823399 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9800 11:50:52.826913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9801 11:50:52.833373 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9802 11:50:52.836396 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9803 11:50:52.842941 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9804 11:50:52.846541 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9805 11:50:52.852690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9806 11:50:52.856194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9807 11:50:52.859254 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9808 11:50:52.866105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9809 11:50:52.869469 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9810 11:50:52.872410 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9811 11:50:52.878915 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9812 11:50:52.882724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9813 11:50:52.885851 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9814 11:50:52.889051 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9815 11:50:52.895562 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9816 11:50:52.898850 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9817 11:50:52.905565 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9818 11:50:52.909146 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9819 11:50:52.912104 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9820 11:50:52.918742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9821 11:50:52.921922 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9822 11:50:52.928180 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9823 11:50:52.931439 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9824 11:50:52.934977 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9825 11:50:52.941120 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9826 11:50:52.944723 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9827 11:50:52.947910 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9828 11:50:52.954740 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9829 11:50:52.957951 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9830 11:50:52.961441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9831 11:50:52.967625 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9832 11:50:52.972179 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9833 11:50:52.978262 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9834 11:50:52.981336 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9835 11:50:52.984330 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9836 11:50:52.991746 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9837 11:50:52.994523 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9838 11:50:52.998057 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9839 11:50:53.004355 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9840 11:50:53.008003 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9841 11:50:53.014393 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9842 11:50:53.017911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9843 11:50:53.020876 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9844 11:50:53.027814 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9845 11:50:53.031114 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9846 11:50:53.033917 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9847 11:50:53.040778 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9848 11:50:53.043887 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9849 11:50:53.046899 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9850 11:50:53.053393 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9851 11:50:53.056826 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9852 11:50:53.059918 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9853 11:50:53.063412 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9854 11:50:53.066799 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9855 11:50:53.073307 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9856 11:50:53.076720 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9857 11:50:53.079772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9858 11:50:53.086970 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9859 11:50:53.090159 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9860 11:50:53.093208 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9861 11:50:53.099528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9862 11:50:53.102958 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9863 11:50:53.106921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9864 11:50:53.112646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9865 11:50:53.116331 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9866 11:50:53.122605 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9867 11:50:53.125971 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9868 11:50:53.129950 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9869 11:50:53.135900 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9870 11:50:53.139154 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9871 11:50:53.145829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9872 11:50:53.148926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9873 11:50:53.155488 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9874 11:50:53.158749 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9875 11:50:53.162071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9876 11:50:53.168901 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9877 11:50:53.171989 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9878 11:50:53.178890 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9879 11:50:53.182075 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9880 11:50:53.185150 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9881 11:50:53.191754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9882 11:50:53.195248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9883 11:50:53.201899 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9884 11:50:53.205177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9885 11:50:53.211671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9886 11:50:53.215304 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9887 11:50:53.218284 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9888 11:50:53.224915 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9889 11:50:53.228189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9890 11:50:53.234969 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9891 11:50:53.238111 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9892 11:50:53.241281 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9893 11:50:53.248867 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9894 11:50:53.251395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9895 11:50:53.258154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9896 11:50:53.261250 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9897 11:50:53.264617 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9898 11:50:53.271799 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9899 11:50:53.274919 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9900 11:50:53.281345 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9901 11:50:53.284877 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9902 11:50:53.287707 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9903 11:50:53.294399 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9904 11:50:53.298240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9905 11:50:53.304010 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9906 11:50:53.307428 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9907 11:50:53.314033 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9908 11:50:53.317832 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9909 11:50:53.323678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9910 11:50:53.327717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9911 11:50:53.330623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9912 11:50:53.337616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9913 11:50:53.340620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9914 11:50:53.347349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9915 11:50:53.350346 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9916 11:50:53.357145 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9917 11:50:53.360167 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9918 11:50:53.363658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9919 11:50:53.370012 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9920 11:50:53.373636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9921 11:50:53.380197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9922 11:50:53.383346 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9923 11:50:53.386889 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9924 11:50:53.393226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9925 11:50:53.396643 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9926 11:50:53.403027 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9927 11:50:53.406460 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9928 11:50:53.410356 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9929 11:50:53.416498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9930 11:50:53.420098 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9931 11:50:53.426553 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9932 11:50:53.429721 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9933 11:50:53.436201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9934 11:50:53.439555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9935 11:50:53.442954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9936 11:50:53.449366 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9937 11:50:53.452594 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9938 11:50:53.459428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9939 11:50:53.462404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9940 11:50:53.469373 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9941 11:50:53.473291 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9942 11:50:53.475609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9943 11:50:53.482353 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9944 11:50:53.485549 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9945 11:50:53.492197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9946 11:50:53.495931 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9947 11:50:53.502125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9948 11:50:53.505386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9949 11:50:53.512660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9950 11:50:53.516139 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9951 11:50:53.518896 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9952 11:50:53.525166 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9953 11:50:53.528970 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9954 11:50:53.535157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9955 11:50:53.538452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9956 11:50:53.545028 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9957 11:50:53.548445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9958 11:50:53.555188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9959 11:50:53.558622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9960 11:50:53.561533 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9961 11:50:53.568241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9962 11:50:53.571838 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9963 11:50:53.578237 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9964 11:50:53.581239 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9965 11:50:53.588281 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9966 11:50:53.590942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9967 11:50:53.597721 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9968 11:50:53.600953 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9969 11:50:53.604158 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9970 11:50:53.610907 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9971 11:50:53.614350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9972 11:50:53.621170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9973 11:50:53.624987 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9974 11:50:53.631409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9975 11:50:53.634629 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9976 11:50:53.640806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9977 11:50:53.644056 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9978 11:50:53.651351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9979 11:50:53.653798 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9980 11:50:53.657118 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9981 11:50:53.664071 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9982 11:50:53.667337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9983 11:50:53.673743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9984 11:50:53.677151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9985 11:50:53.680466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9986 11:50:53.686776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9987 11:50:53.690181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9988 11:50:53.696688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9989 11:50:53.699659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9990 11:50:53.706267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9991 11:50:53.709282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9992 11:50:53.716000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9993 11:50:53.719607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9994 11:50:53.725911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9995 11:50:53.729317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9996 11:50:53.735902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9997 11:50:53.739500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9998 11:50:53.745858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9999 11:50:53.749367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10000 11:50:53.755590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10001 11:50:53.759092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10002 11:50:53.766050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10003 11:50:53.769115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10004 11:50:53.776191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10005 11:50:53.778862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10006 11:50:53.785664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10007 11:50:53.789109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10008 11:50:53.795613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10009 11:50:53.798777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10010 11:50:53.805592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10011 11:50:53.808494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10012 11:50:53.815376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10013 11:50:53.819283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10014 11:50:53.825035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10015 11:50:53.828415 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10016 11:50:53.831914 INFO: [APUAPC] vio 0
10017 11:50:53.835736 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10018 11:50:53.841947 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10019 11:50:53.845353 INFO: [APUAPC] D0_APC_0: 0x400510
10020 11:50:53.848593 INFO: [APUAPC] D0_APC_1: 0x0
10021 11:50:53.851574 INFO: [APUAPC] D0_APC_2: 0x1540
10022 11:50:53.851658 INFO: [APUAPC] D0_APC_3: 0x0
10023 11:50:53.855141 INFO: [APUAPC] D1_APC_0: 0xffffffff
10024 11:50:53.858588 INFO: [APUAPC] D1_APC_1: 0xffffffff
10025 11:50:53.861452 INFO: [APUAPC] D1_APC_2: 0x3fffff
10026 11:50:53.865275 INFO: [APUAPC] D1_APC_3: 0x0
10027 11:50:53.868297 INFO: [APUAPC] D2_APC_0: 0xffffffff
10028 11:50:53.871822 INFO: [APUAPC] D2_APC_1: 0xffffffff
10029 11:50:53.875258 INFO: [APUAPC] D2_APC_2: 0x3fffff
10030 11:50:53.877937 INFO: [APUAPC] D2_APC_3: 0x0
10031 11:50:53.881348 INFO: [APUAPC] D3_APC_0: 0xffffffff
10032 11:50:53.885030 INFO: [APUAPC] D3_APC_1: 0xffffffff
10033 11:50:53.888553 INFO: [APUAPC] D3_APC_2: 0x3fffff
10034 11:50:53.891213 INFO: [APUAPC] D3_APC_3: 0x0
10035 11:50:53.894896 INFO: [APUAPC] D4_APC_0: 0xffffffff
10036 11:50:53.898016 INFO: [APUAPC] D4_APC_1: 0xffffffff
10037 11:50:53.901900 INFO: [APUAPC] D4_APC_2: 0x3fffff
10038 11:50:53.904989 INFO: [APUAPC] D4_APC_3: 0x0
10039 11:50:53.907590 INFO: [APUAPC] D5_APC_0: 0xffffffff
10040 11:50:53.911141 INFO: [APUAPC] D5_APC_1: 0xffffffff
10041 11:50:53.914432 INFO: [APUAPC] D5_APC_2: 0x3fffff
10042 11:50:53.917534 INFO: [APUAPC] D5_APC_3: 0x0
10043 11:50:53.921011 INFO: [APUAPC] D6_APC_0: 0xffffffff
10044 11:50:53.925042 INFO: [APUAPC] D6_APC_1: 0xffffffff
10045 11:50:53.927444 INFO: [APUAPC] D6_APC_2: 0x3fffff
10046 11:50:53.931877 INFO: [APUAPC] D6_APC_3: 0x0
10047 11:50:53.934112 INFO: [APUAPC] D7_APC_0: 0xffffffff
10048 11:50:53.937612 INFO: [APUAPC] D7_APC_1: 0xffffffff
10049 11:50:53.940817 INFO: [APUAPC] D7_APC_2: 0x3fffff
10050 11:50:53.944288 INFO: [APUAPC] D7_APC_3: 0x0
10051 11:50:53.947641 INFO: [APUAPC] D8_APC_0: 0xffffffff
10052 11:50:53.951381 INFO: [APUAPC] D8_APC_1: 0xffffffff
10053 11:50:53.954497 INFO: [APUAPC] D8_APC_2: 0x3fffff
10054 11:50:53.957698 INFO: [APUAPC] D8_APC_3: 0x0
10055 11:50:53.961062 INFO: [APUAPC] D9_APC_0: 0xffffffff
10056 11:50:53.964292 INFO: [APUAPC] D9_APC_1: 0xffffffff
10057 11:50:53.967762 INFO: [APUAPC] D9_APC_2: 0x3fffff
10058 11:50:53.971031 INFO: [APUAPC] D9_APC_3: 0x0
10059 11:50:53.974154 INFO: [APUAPC] D10_APC_0: 0xffffffff
10060 11:50:53.977690 INFO: [APUAPC] D10_APC_1: 0xffffffff
10061 11:50:53.982253 INFO: [APUAPC] D10_APC_2: 0x3fffff
10062 11:50:53.984854 INFO: [APUAPC] D10_APC_3: 0x0
10063 11:50:53.987550 INFO: [APUAPC] D11_APC_0: 0xffffffff
10064 11:50:53.990737 INFO: [APUAPC] D11_APC_1: 0xffffffff
10065 11:50:53.994007 INFO: [APUAPC] D11_APC_2: 0x3fffff
10066 11:50:53.997360 INFO: [APUAPC] D11_APC_3: 0x0
10067 11:50:54.000749 INFO: [APUAPC] D12_APC_0: 0xffffffff
10068 11:50:54.003990 INFO: [APUAPC] D12_APC_1: 0xffffffff
10069 11:50:54.007458 INFO: [APUAPC] D12_APC_2: 0x3fffff
10070 11:50:54.010829 INFO: [APUAPC] D12_APC_3: 0x0
10071 11:50:54.013933 INFO: [APUAPC] D13_APC_0: 0xffffffff
10072 11:50:54.017320 INFO: [APUAPC] D13_APC_1: 0xffffffff
10073 11:50:54.020563 INFO: [APUAPC] D13_APC_2: 0x3fffff
10074 11:50:54.023790 INFO: [APUAPC] D13_APC_3: 0x0
10075 11:50:54.027170 INFO: [APUAPC] D14_APC_0: 0xffffffff
10076 11:50:54.030604 INFO: [APUAPC] D14_APC_1: 0xffffffff
10077 11:50:54.033984 INFO: [APUAPC] D14_APC_2: 0x3fffff
10078 11:50:54.037483 INFO: [APUAPC] D14_APC_3: 0x0
10079 11:50:54.040840 INFO: [APUAPC] D15_APC_0: 0xffffffff
10080 11:50:54.045444 INFO: [APUAPC] D15_APC_1: 0xffffffff
10081 11:50:54.047221 INFO: [APUAPC] D15_APC_2: 0x3fffff
10082 11:50:54.050292 INFO: [APUAPC] D15_APC_3: 0x0
10083 11:50:54.053517 INFO: [APUAPC] APC_CON: 0x4
10084 11:50:54.056806 INFO: [NOCDAPC] D0_APC_0: 0x0
10085 11:50:54.060056 INFO: [NOCDAPC] D0_APC_1: 0x0
10086 11:50:54.060584 INFO: [NOCDAPC] D1_APC_0: 0x0
10087 11:50:54.063435 INFO: [NOCDAPC] D1_APC_1: 0xfff
10088 11:50:54.066814 INFO: [NOCDAPC] D2_APC_0: 0x0
10089 11:50:54.070050 INFO: [NOCDAPC] D2_APC_1: 0xfff
10090 11:50:54.073707 INFO: [NOCDAPC] D3_APC_0: 0x0
10091 11:50:54.076993 INFO: [NOCDAPC] D3_APC_1: 0xfff
10092 11:50:54.080398 INFO: [NOCDAPC] D4_APC_0: 0x0
10093 11:50:54.083442 INFO: [NOCDAPC] D4_APC_1: 0xfff
10094 11:50:54.087142 INFO: [NOCDAPC] D5_APC_0: 0x0
10095 11:50:54.090187 INFO: [NOCDAPC] D5_APC_1: 0xfff
10096 11:50:54.093882 INFO: [NOCDAPC] D6_APC_0: 0x0
10097 11:50:54.097215 INFO: [NOCDAPC] D6_APC_1: 0xfff
10098 11:50:54.097676 INFO: [NOCDAPC] D7_APC_0: 0x0
10099 11:50:54.100113 INFO: [NOCDAPC] D7_APC_1: 0xfff
10100 11:50:54.103326 INFO: [NOCDAPC] D8_APC_0: 0x0
10101 11:50:54.106904 INFO: [NOCDAPC] D8_APC_1: 0xfff
10102 11:50:54.110274 INFO: [NOCDAPC] D9_APC_0: 0x0
10103 11:50:54.113897 INFO: [NOCDAPC] D9_APC_1: 0xfff
10104 11:50:54.116726 INFO: [NOCDAPC] D10_APC_0: 0x0
10105 11:50:54.120178 INFO: [NOCDAPC] D10_APC_1: 0xfff
10106 11:50:54.123467 INFO: [NOCDAPC] D11_APC_0: 0x0
10107 11:50:54.127425 INFO: [NOCDAPC] D11_APC_1: 0xfff
10108 11:50:54.129796 INFO: [NOCDAPC] D12_APC_0: 0x0
10109 11:50:54.133074 INFO: [NOCDAPC] D12_APC_1: 0xfff
10110 11:50:54.136396 INFO: [NOCDAPC] D13_APC_0: 0x0
10111 11:50:54.139965 INFO: [NOCDAPC] D13_APC_1: 0xfff
10112 11:50:54.140493 INFO: [NOCDAPC] D14_APC_0: 0x0
10113 11:50:54.143068 INFO: [NOCDAPC] D14_APC_1: 0xfff
10114 11:50:54.147060 INFO: [NOCDAPC] D15_APC_0: 0x0
10115 11:50:54.149777 INFO: [NOCDAPC] D15_APC_1: 0xfff
10116 11:50:54.153480 INFO: [NOCDAPC] APC_CON: 0x4
10117 11:50:54.156592 INFO: [APUAPC] set_apusys_apc done
10118 11:50:54.159767 INFO: [DEVAPC] devapc_init done
10119 11:50:54.163012 INFO: GICv3 without legacy support detected.
10120 11:50:54.169914 INFO: ARM GICv3 driver initialized in EL3
10121 11:50:54.172819 INFO: Maximum SPI INTID supported: 639
10122 11:50:54.176351 INFO: BL31: Initializing runtime services
10123 11:50:54.182710 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10124 11:50:54.183400 INFO: SPM: enable CPC mode
10125 11:50:54.189326 INFO: mcdi ready for mcusys-off-idle and system suspend
10126 11:50:54.192463 INFO: BL31: Preparing for EL3 exit to normal world
10127 11:50:54.199054 INFO: Entry point address = 0x80000000
10128 11:50:54.199661 INFO: SPSR = 0x8
10129 11:50:54.205654
10130 11:50:54.206146
10131 11:50:54.206515
10132 11:50:54.209592 Starting depthcharge on Spherion...
10133 11:50:54.210059
10134 11:50:54.210426 Wipe memory regions:
10135 11:50:54.210769
10136 11:50:54.213470 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10137 11:50:54.213974 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10138 11:50:54.214375 Setting prompt string to ['asurada:']
10139 11:50:54.214780 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10140 11:50:54.215439 [0x00000040000000, 0x00000054600000)
10141 11:50:54.335071
10142 11:50:54.335564 [0x00000054660000, 0x00000080000000)
10143 11:50:54.595172
10144 11:50:54.595698 [0x000000821a7280, 0x000000ffe64000)
10145 11:50:55.340083
10146 11:50:55.340647 [0x00000100000000, 0x00000240000000)
10147 11:50:57.231190
10148 11:50:57.233204 Initializing XHCI USB controller at 0x11200000.
10149 11:50:58.214579
10150 11:50:58.215261 R8152: Initializing
10151 11:50:58.215692
10152 11:50:58.217276 Version 9 (ocp_data = 6010)
10153 11:50:58.217764
10154 11:50:58.221135 R8152: Done initializing
10155 11:50:58.221785
10156 11:50:58.222341 Adding net device
10157 11:50:58.742971
10158 11:50:58.746363 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10159 11:50:58.746673
10160 11:50:58.746913
10161 11:50:58.747136
10162 11:50:58.747725 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10164 11:50:58.848408 asurada: tftpboot 192.168.201.1 12074064/tftp-deploy-1je_ui1h/kernel/image.itb 12074064/tftp-deploy-1je_ui1h/kernel/cmdline
10165 11:50:58.848666 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10166 11:50:58.848841 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10167 11:50:58.853343 tftpboot 192.168.201.1 12074064/tftp-deploy-1je_ui1h/kernel/image.itp-deploy-1je_ui1h/kernel/cmdline
10168 11:50:58.853569
10169 11:50:58.853794 Waiting for link
10170 11:50:59.056204
10171 11:50:59.056797 done.
10172 11:50:59.057179
10173 11:50:59.057590 MAC: f4:f5:e8:50:de:0a
10174 11:50:59.057994
10175 11:50:59.059815 Sending DHCP discover... done.
10176 11:50:59.060385
10177 11:50:59.062818 Waiting for reply... done.
10178 11:50:59.063291
10179 11:50:59.066412 Sending DHCP request... done.
10180 11:50:59.066882
10181 11:50:59.071742 Waiting for reply... done.
10182 11:50:59.072211
10183 11:50:59.072584 My ip is 192.168.201.14
10184 11:50:59.072929
10185 11:50:59.075143 The DHCP server ip is 192.168.201.1
10186 11:50:59.075715
10187 11:50:59.081616 TFTP server IP predefined by user: 192.168.201.1
10188 11:50:59.082189
10189 11:50:59.088341 Bootfile predefined by user: 12074064/tftp-deploy-1je_ui1h/kernel/image.itb
10190 11:50:59.088920
10191 11:50:59.091354 Sending tftp read request... done.
10192 11:50:59.091824
10193 11:50:59.098222 Waiting for the transfer...
10194 11:50:59.098826
10195 11:50:59.440765 00000000 ################################################################
10196 11:50:59.440935
10197 11:50:59.676715 00080000 ################################################################
10198 11:50:59.676852
10199 11:50:59.920304 00100000 ################################################################
10200 11:50:59.920444
10201 11:51:00.160693 00180000 ################################################################
10202 11:51:00.160837
10203 11:51:00.387866 00200000 ################################################################
10204 11:51:00.388005
10205 11:51:00.613934 00280000 ################################################################
10206 11:51:00.614102
10207 11:51:00.843636 00300000 ################################################################
10208 11:51:00.843769
10209 11:51:01.082536 00380000 ################################################################
10210 11:51:01.082684
10211 11:51:01.315888 00400000 ################################################################
10212 11:51:01.316025
10213 11:51:01.547107 00480000 ################################################################
10214 11:51:01.547251
10215 11:51:01.774170 00500000 ################################################################
10216 11:51:01.774321
10217 11:51:02.001032 00580000 ################################################################
10218 11:51:02.001174
10219 11:51:02.246119 00600000 ################################################################
10220 11:51:02.246254
10221 11:51:02.475887 00680000 ################################################################
10222 11:51:02.476032
10223 11:51:02.725686 00700000 ################################################################
10224 11:51:02.725832
10225 11:51:02.972160 00780000 ################################################################
10226 11:51:02.972304
10227 11:51:03.229657 00800000 ################################################################
10228 11:51:03.229838
10229 11:51:03.471492 00880000 ################################################################
10230 11:51:03.471632
10231 11:51:03.696751 00900000 ################################################################
10232 11:51:03.696891
10233 11:51:03.924604 00980000 ################################################################
10234 11:51:03.924775
10235 11:51:04.169403 00a00000 ################################################################
10236 11:51:04.169572
10237 11:51:04.396431 00a80000 ################################################################
10238 11:51:04.396569
10239 11:51:04.623701 00b00000 ################################################################
10240 11:51:04.623866
10241 11:51:04.849635 00b80000 ################################################################
10242 11:51:04.849783
10243 11:51:05.080433 00c00000 ################################################################
10244 11:51:05.080571
10245 11:51:05.312493 00c80000 ################################################################
10246 11:51:05.312629
10247 11:51:05.539114 00d00000 ################################################################
10248 11:51:05.539255
10249 11:51:05.774001 00d80000 ################################################################
10250 11:51:05.774224
10251 11:51:06.003623 00e00000 ################################################################
10252 11:51:06.003766
10253 11:51:06.230719 00e80000 ################################################################
10254 11:51:06.230857
10255 11:51:06.457804 00f00000 ################################################################
10256 11:51:06.457971
10257 11:51:06.698226 00f80000 ################################################################
10258 11:51:06.698361
10259 11:51:06.940539 01000000 ################################################################
10260 11:51:06.940708
10261 11:51:07.175014 01080000 ################################################################
10262 11:51:07.175147
10263 11:51:07.405782 01100000 ################################################################
10264 11:51:07.405931
10265 11:51:07.669345 01180000 ################################################################
10266 11:51:07.669539
10267 11:51:07.932917 01200000 ################################################################
10268 11:51:07.933061
10269 11:51:08.186871 01280000 ################################################################
10270 11:51:08.187016
10271 11:51:08.443460 01300000 ################################################################
10272 11:51:08.443596
10273 11:51:08.700880 01380000 ################################################################
10274 11:51:08.701015
10275 11:51:08.956597 01400000 ################################################################
10276 11:51:08.956733
10277 11:51:09.209223 01480000 ################################################################
10278 11:51:09.209374
10279 11:51:09.436710 01500000 ################################################################
10280 11:51:09.436850
10281 11:51:09.669710 01580000 ################################################################
10282 11:51:09.669847
10283 11:51:09.912163 01600000 ################################################################
10284 11:51:09.912300
10285 11:51:10.140575 01680000 ################################################################
10286 11:51:10.140713
10287 11:51:10.367085 01700000 ################################################################
10288 11:51:10.367230
10289 11:51:10.594018 01780000 ################################################################
10290 11:51:10.594153
10291 11:51:10.820991 01800000 ################################################################
10292 11:51:10.821125
10293 11:51:11.048019 01880000 ################################################################
10294 11:51:11.048154
10295 11:51:11.274392 01900000 ################################################################
10296 11:51:11.274530
10297 11:51:11.500166 01980000 ################################################################
10298 11:51:11.500310
10299 11:51:11.729351 01a00000 ################################################################
10300 11:51:11.729519
10301 11:51:11.969748 01a80000 ################################################################
10302 11:51:11.969889
10303 11:51:12.202091 01b00000 ################################################################
10304 11:51:12.202228
10305 11:51:12.227015 01b80000 ####### done.
10306 11:51:12.227101
10307 11:51:12.229741 The bootfile was 28892418 bytes long.
10308 11:51:12.229831
10309 11:51:12.233347 Sending tftp read request... done.
10310 11:51:12.233452
10311 11:51:12.233530 Waiting for the transfer...
10312 11:51:12.233601
10313 11:51:12.236848 00000000 # done.
10314 11:51:12.236945
10315 11:51:12.243925 Command line loaded dynamically from TFTP file: 12074064/tftp-deploy-1je_ui1h/kernel/cmdline
10316 11:51:12.244132
10317 11:51:12.266703 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10318 11:51:12.266975
10319 11:51:12.267127 Loading FIT.
10320 11:51:12.267266
10321 11:51:12.269842 Image ramdisk-1 has 17794859 bytes.
10322 11:51:12.270057
10323 11:51:12.273670 Image fdt-1 has 47278 bytes.
10324 11:51:12.273998
10325 11:51:12.276758 Image kernel-1 has 11048246 bytes.
10326 11:51:12.277086
10327 11:51:12.286943 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10328 11:51:12.287434
10329 11:51:12.303064 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10330 11:51:12.303642
10331 11:51:12.309672 Choosing best match conf-1 for compat google,spherion-rev2.
10332 11:51:12.310143
10333 11:51:12.317128 Connected to device vid:did:rid of 1ae0:0028:00
10334 11:51:12.323917
10335 11:51:12.327157 tpm_get_response: command 0x17b, return code 0x0
10336 11:51:12.327772
10337 11:51:12.330858 ec_init: CrosEC protocol v3 supported (256, 248)
10338 11:51:12.335015
10339 11:51:12.338205 tpm_cleanup: add release locality here.
10340 11:51:12.338686
10341 11:51:12.339344 Shutting down all USB controllers.
10342 11:51:12.342211
10343 11:51:12.342680 Removing current net device
10344 11:51:12.343009
10345 11:51:12.348385 Exiting depthcharge with code 4 at timestamp: 47564641
10346 11:51:12.348935
10347 11:51:12.351576 LZMA decompressing kernel-1 to 0x821a6718
10348 11:51:12.352000
10349 11:51:12.355533 LZMA decompressing kernel-1 to 0x40000000
10350 11:51:13.744135
10351 11:51:13.744710 jumping to kernel
10352 11:51:13.746419 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
10353 11:51:13.746986 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10354 11:51:13.747397 Setting prompt string to ['Linux version [0-9]']
10355 11:51:13.747772 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10356 11:51:13.748160 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10357 11:51:13.826195
10358 11:51:13.829171 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10359 11:51:13.832917 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10360 11:51:13.833540 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10361 11:51:13.833951 Setting prompt string to []
10362 11:51:13.834368 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10363 11:51:13.834769 Using line separator: #'\n'#
10364 11:51:13.835108 No login prompt set.
10365 11:51:13.835454 Parsing kernel messages
10366 11:51:13.835769 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10367 11:51:13.836335 [login-action] Waiting for messages, (timeout 00:04:05)
10368 11:51:13.852241 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10369 11:51:13.855434 [ 0.000000] random: crng init done
10370 11:51:13.862135 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10371 11:51:13.866522 [ 0.000000] efi: UEFI not found.
10372 11:51:13.871730 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10373 11:51:13.882382 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10374 11:51:13.892211 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10375 11:51:13.898472 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10376 11:51:13.904751 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10377 11:51:13.912099 [ 0.000000] printk: bootconsole [mtk8250] enabled
10378 11:51:13.918355 [ 0.000000] NUMA: No NUMA configuration found
10379 11:51:13.924814 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10380 11:51:13.931532 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10381 11:51:13.932115 [ 0.000000] Zone ranges:
10382 11:51:13.937772 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10383 11:51:13.941226 [ 0.000000] DMA32 empty
10384 11:51:13.947599 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10385 11:51:13.951535 [ 0.000000] Movable zone start for each node
10386 11:51:13.954373 [ 0.000000] Early memory node ranges
10387 11:51:13.961389 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10388 11:51:13.968059 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10389 11:51:13.974168 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10390 11:51:13.980913 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10391 11:51:13.987765 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10392 11:51:13.994481 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10393 11:51:14.050486 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10394 11:51:14.057147 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10395 11:51:14.063684 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10396 11:51:14.067051 [ 0.000000] psci: probing for conduit method from DT.
10397 11:51:14.073310 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10398 11:51:14.076764 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10399 11:51:14.083690 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10400 11:51:14.087020 [ 0.000000] psci: SMC Calling Convention v1.2
10401 11:51:14.093707 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10402 11:51:14.096109 [ 0.000000] Detected VIPT I-cache on CPU0
10403 11:51:14.102710 [ 0.000000] CPU features: detected: GIC system register CPU interface
10404 11:51:14.109843 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10405 11:51:14.116468 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10406 11:51:14.122832 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10407 11:51:14.132542 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10408 11:51:14.139540 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10409 11:51:14.141720 [ 0.000000] alternatives: applying boot alternatives
10410 11:51:14.149885 [ 0.000000] Fallback order for Node 0: 0
10411 11:51:14.156876 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10412 11:51:14.158925 [ 0.000000] Policy zone: Normal
10413 11:51:14.182074 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10414 11:51:14.192110 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10415 11:51:14.204231 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10416 11:51:14.213364 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10417 11:51:14.220732 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10418 11:51:14.223707 <6>[ 0.000000] software IO TLB: area num 8.
10419 11:51:14.280434 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10420 11:51:14.429575 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10421 11:51:14.435533 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10422 11:51:14.441915 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10423 11:51:14.445442 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10424 11:51:14.452027 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10425 11:51:14.458288 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10426 11:51:14.465252 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10427 11:51:14.471852 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10428 11:51:14.478708 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10429 11:51:14.484699 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10430 11:51:14.491523 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10431 11:51:14.494657 <6>[ 0.000000] GICv3: 608 SPIs implemented
10432 11:51:14.498025 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10433 11:51:14.504325 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10434 11:51:14.508391 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10435 11:51:14.514176 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10436 11:51:14.527488 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10437 11:51:14.540793 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10438 11:51:14.547134 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10439 11:51:14.555441 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10440 11:51:14.568466 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10441 11:51:14.575038 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10442 11:51:14.581811 <6>[ 0.009179] Console: colour dummy device 80x25
10443 11:51:14.592257 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10444 11:51:14.598520 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10445 11:51:14.601898 <6>[ 0.029314] LSM: Security Framework initializing
10446 11:51:14.608376 <6>[ 0.034251] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 11:51:14.618340 <6>[ 0.042112] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 11:51:14.628147 <6>[ 0.051575] cblist_init_generic: Setting adjustable number of callback queues.
10449 11:51:14.635006 <6>[ 0.059017] cblist_init_generic: Setting shift to 3 and lim to 1.
10450 11:51:14.642240 <6>[ 0.065394] cblist_init_generic: Setting adjustable number of callback queues.
10451 11:51:14.648583 <6>[ 0.072867] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 11:51:14.651887 <6>[ 0.079306] rcu: Hierarchical SRCU implementation.
10453 11:51:14.658136 <6>[ 0.084322] rcu: Max phase no-delay instances is 1000.
10454 11:51:14.664557 <6>[ 0.091377] EFI services will not be available.
10455 11:51:14.668214 <6>[ 0.096328] smp: Bringing up secondary CPUs ...
10456 11:51:14.676712 <6>[ 0.101373] Detected VIPT I-cache on CPU1
10457 11:51:14.683584 <6>[ 0.101442] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10458 11:51:14.689898 <6>[ 0.101473] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10459 11:51:14.693542 <6>[ 0.101816] Detected VIPT I-cache on CPU2
10460 11:51:14.702678 <6>[ 0.101869] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10461 11:51:14.709790 <6>[ 0.101886] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10462 11:51:14.713584 <6>[ 0.102150] Detected VIPT I-cache on CPU3
10463 11:51:14.718909 <6>[ 0.102196] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10464 11:51:14.725809 <6>[ 0.102209] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10465 11:51:14.733505 <6>[ 0.102513] CPU features: detected: Spectre-v4
10466 11:51:14.735657 <6>[ 0.102519] CPU features: detected: Spectre-BHB
10467 11:51:14.739445 <6>[ 0.102524] Detected PIPT I-cache on CPU4
10468 11:51:14.745483 <6>[ 0.102581] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10469 11:51:14.755824 <6>[ 0.102597] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10470 11:51:14.758615 <6>[ 0.102892] Detected PIPT I-cache on CPU5
10471 11:51:14.766623 <6>[ 0.102954] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10472 11:51:14.772054 <6>[ 0.102970] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10473 11:51:14.775215 <6>[ 0.103249] Detected PIPT I-cache on CPU6
10474 11:51:14.785165 <6>[ 0.103314] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10475 11:51:14.791725 <6>[ 0.103330] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10476 11:51:14.794945 <6>[ 0.103626] Detected PIPT I-cache on CPU7
10477 11:51:14.802129 <6>[ 0.103690] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10478 11:51:14.808467 <6>[ 0.103706] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10479 11:51:14.811012 <6>[ 0.103753] smp: Brought up 1 node, 8 CPUs
10480 11:51:14.817821 <6>[ 0.245092] SMP: Total of 8 processors activated.
10481 11:51:14.824623 <6>[ 0.250013] CPU features: detected: 32-bit EL0 Support
10482 11:51:14.831202 <6>[ 0.255373] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10483 11:51:14.838145 <6>[ 0.264170] CPU features: detected: Common not Private translations
10484 11:51:14.843963 <6>[ 0.270653] CPU features: detected: CRC32 instructions
10485 11:51:14.850589 <6>[ 0.276006] CPU features: detected: RCpc load-acquire (LDAPR)
10486 11:51:14.854255 <6>[ 0.281964] CPU features: detected: LSE atomic instructions
10487 11:51:14.860951 <6>[ 0.287745] CPU features: detected: Privileged Access Never
10488 11:51:14.867677 <6>[ 0.293561] CPU features: detected: RAS Extension Support
10489 11:51:14.875501 <6>[ 0.299172] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10490 11:51:14.877452 <6>[ 0.306438] CPU: All CPU(s) started at EL2
10491 11:51:14.883991 <6>[ 0.310755] alternatives: applying system-wide alternatives
10492 11:51:14.895127 <6>[ 0.321507] devtmpfs: initialized
10493 11:51:14.910233 <6>[ 0.330490] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10494 11:51:14.916533 <6>[ 0.340452] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10495 11:51:14.923814 <6>[ 0.348675] pinctrl core: initialized pinctrl subsystem
10496 11:51:14.927457 <6>[ 0.355341] DMI not present or invalid.
10497 11:51:14.933343 <6>[ 0.359692] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10498 11:51:14.942607 <6>[ 0.366591] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10499 11:51:14.949644 <6>[ 0.374170] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10500 11:51:14.959179 <6>[ 0.382393] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10501 11:51:14.962699 <6>[ 0.390636] audit: initializing netlink subsys (disabled)
10502 11:51:14.973206 <5>[ 0.396328] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10503 11:51:14.979435 <6>[ 0.397029] thermal_sys: Registered thermal governor 'step_wise'
10504 11:51:14.985906 <6>[ 0.404294] thermal_sys: Registered thermal governor 'power_allocator'
10505 11:51:14.988899 <6>[ 0.410553] cpuidle: using governor menu
10506 11:51:14.995418 <6>[ 0.421516] NET: Registered PF_QIPCRTR protocol family
10507 11:51:15.002082 <6>[ 0.426981] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10508 11:51:15.008805 <6>[ 0.434087] ASID allocator initialised with 32768 entries
10509 11:51:15.012874 <6>[ 0.440655] Serial: AMBA PL011 UART driver
10510 11:51:15.022152 <4>[ 0.449458] Trying to register duplicate clock ID: 134
10511 11:51:15.078327 <6>[ 0.508997] KASLR enabled
10512 11:51:15.093052 <6>[ 0.516705] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10513 11:51:15.099504 <6>[ 0.523720] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10514 11:51:15.106064 <6>[ 0.530208] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10515 11:51:15.112694 <6>[ 0.537214] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10516 11:51:15.119485 <6>[ 0.543700] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10517 11:51:15.126060 <6>[ 0.550704] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10518 11:51:15.133088 <6>[ 0.557192] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10519 11:51:15.138899 <6>[ 0.564196] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10520 11:51:15.142077 <6>[ 0.571687] ACPI: Interpreter disabled.
10521 11:51:15.152450 <6>[ 0.578055] iommu: Default domain type: Translated
10522 11:51:15.157623 <6>[ 0.583167] iommu: DMA domain TLB invalidation policy: strict mode
10523 11:51:15.160352 <5>[ 0.589825] SCSI subsystem initialized
10524 11:51:15.167408 <6>[ 0.593991] usbcore: registered new interface driver usbfs
10525 11:51:15.173990 <6>[ 0.599723] usbcore: registered new interface driver hub
10526 11:51:15.177372 <6>[ 0.605276] usbcore: registered new device driver usb
10527 11:51:15.184126 <6>[ 0.611377] pps_core: LinuxPPS API ver. 1 registered
10528 11:51:15.194666 <6>[ 0.616570] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10529 11:51:15.197534 <6>[ 0.625918] PTP clock support registered
10530 11:51:15.200538 <6>[ 0.630162] EDAC MC: Ver: 3.0.0
10531 11:51:15.208175 <6>[ 0.635329] FPGA manager framework
10532 11:51:15.215070 <6>[ 0.639011] Advanced Linux Sound Architecture Driver Initialized.
10533 11:51:15.218506 <6>[ 0.645787] vgaarb: loaded
10534 11:51:15.225028 <6>[ 0.648964] clocksource: Switched to clocksource arch_sys_counter
10535 11:51:15.228377 <5>[ 0.655402] VFS: Disk quotas dquot_6.6.0
10536 11:51:15.234430 <6>[ 0.659587] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10537 11:51:15.237793 <6>[ 0.666775] pnp: PnP ACPI: disabled
10538 11:51:15.246592 <6>[ 0.673432] NET: Registered PF_INET protocol family
10539 11:51:15.255788 <6>[ 0.679025] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10540 11:51:15.267849 <6>[ 0.691341] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10541 11:51:15.277403 <6>[ 0.700156] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10542 11:51:15.283763 <6>[ 0.708127] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10543 11:51:15.293462 <6>[ 0.716824] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10544 11:51:15.300493 <6>[ 0.726571] TCP: Hash tables configured (established 65536 bind 65536)
10545 11:51:15.306796 <6>[ 0.733435] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 11:51:15.317118 <6>[ 0.740633] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10547 11:51:15.323495 <6>[ 0.748329] NET: Registered PF_UNIX/PF_LOCAL protocol family
10548 11:51:15.326783 <6>[ 0.754499] RPC: Registered named UNIX socket transport module.
10549 11:51:15.334124 <6>[ 0.760653] RPC: Registered udp transport module.
10550 11:51:15.336503 <6>[ 0.765586] RPC: Registered tcp transport module.
10551 11:51:15.346566 <6>[ 0.770516] RPC: Registered tcp NFSv4.1 backchannel transport module.
10552 11:51:15.350052 <6>[ 0.777187] PCI: CLS 0 bytes, default 64
10553 11:51:15.354214 <6>[ 0.781574] Unpacking initramfs...
10554 11:51:15.369695 <6>[ 0.793550] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10555 11:51:15.379563 <6>[ 0.802208] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10556 11:51:15.383918 <6>[ 0.811061] kvm [1]: IPA Size Limit: 40 bits
10557 11:51:15.389272 <6>[ 0.815589] kvm [1]: GICv3: no GICV resource entry
10558 11:51:15.392598 <6>[ 0.820609] kvm [1]: disabling GICv2 emulation
10559 11:51:15.399393 <6>[ 0.825298] kvm [1]: GIC system register CPU interface enabled
10560 11:51:15.402246 <6>[ 0.831463] kvm [1]: vgic interrupt IRQ18
10561 11:51:15.409202 <6>[ 0.835817] kvm [1]: VHE mode initialized successfully
10562 11:51:15.415632 <5>[ 0.842313] Initialise system trusted keyrings
10563 11:51:15.422613 <6>[ 0.847119] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10564 11:51:15.430002 <6>[ 0.857235] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10565 11:51:15.436357 <5>[ 0.863652] NFS: Registering the id_resolver key type
10566 11:51:15.440518 <5>[ 0.868962] Key type id_resolver registered
10567 11:51:15.446286 <5>[ 0.873379] Key type id_legacy registered
10568 11:51:15.453518 <6>[ 0.877656] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10569 11:51:15.459973 <6>[ 0.884579] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10570 11:51:15.466394 <6>[ 0.892291] 9p: Installing v9fs 9p2000 file system support
10571 11:51:15.502317 <5>[ 0.929644] Key type asymmetric registered
10572 11:51:15.505684 <5>[ 0.933975] Asymmetric key parser 'x509' registered
10573 11:51:15.515614 <6>[ 0.939118] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10574 11:51:15.518996 <6>[ 0.946736] io scheduler mq-deadline registered
10575 11:51:15.522209 <6>[ 0.951524] io scheduler kyber registered
10576 11:51:15.541352 <6>[ 0.968721] EINJ: ACPI disabled.
10577 11:51:15.574669 <4>[ 0.994759] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 11:51:15.584218 <4>[ 1.005421] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 11:51:15.599725 <6>[ 1.026293] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10580 11:51:15.606941 <6>[ 1.034388] printk: console [ttyS0] disabled
10581 11:51:15.634960 <6>[ 1.059038] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10582 11:51:15.641686 <6>[ 1.068514] printk: console [ttyS0] enabled
10583 11:51:15.644799 <6>[ 1.068514] printk: console [ttyS0] enabled
10584 11:51:15.651186 <6>[ 1.077415] printk: bootconsole [mtk8250] disabled
10585 11:51:15.654475 <6>[ 1.077415] printk: bootconsole [mtk8250] disabled
10586 11:51:15.661080 <6>[ 1.088702] SuperH (H)SCI(F) driver initialized
10587 11:51:15.664761 <6>[ 1.093971] msm_serial: driver initialized
10588 11:51:15.678436 <6>[ 1.102972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10589 11:51:15.689047 <6>[ 1.111519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10590 11:51:15.695553 <6>[ 1.120062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10591 11:51:15.705167 <6>[ 1.128692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10592 11:51:15.715832 <6>[ 1.137399] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10593 11:51:15.721535 <6>[ 1.146118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10594 11:51:15.731944 <6>[ 1.154666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10595 11:51:15.741433 <6>[ 1.163473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10596 11:51:15.747648 <6>[ 1.172017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10597 11:51:15.760653 <6>[ 1.187661] loop: module loaded
10598 11:51:15.766804 <6>[ 1.193648] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10599 11:51:15.790280 <4>[ 1.217104] mtk-pmic-keys: Failed to locate of_node [id: -1]
10600 11:51:15.796777 <6>[ 1.223961] megasas: 07.719.03.00-rc1
10601 11:51:15.806130 <6>[ 1.233549] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10602 11:51:15.818050 <6>[ 1.244333] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10603 11:51:15.833894 <6>[ 1.260690] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10604 11:51:15.893476 <6>[ 1.314012] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10605 11:51:16.095640 <6>[ 1.522198] Freeing initrd memory: 17372K
10606 11:51:16.105568 <6>[ 1.532599] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10607 11:51:16.117271 <6>[ 1.543595] tun: Universal TUN/TAP device driver, 1.6
10608 11:51:16.120333 <6>[ 1.549681] thunder_xcv, ver 1.0
10609 11:51:16.122773 <6>[ 1.553189] thunder_bgx, ver 1.0
10610 11:51:16.126197 <6>[ 1.556678] nicpf, ver 1.0
10611 11:51:16.137134 <6>[ 1.560702] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10612 11:51:16.140009 <6>[ 1.568178] hns3: Copyright (c) 2017 Huawei Corporation.
10613 11:51:16.147289 <6>[ 1.573768] hclge is initializing
10614 11:51:16.150032 <6>[ 1.577343] e1000: Intel(R) PRO/1000 Network Driver
10615 11:51:16.156877 <6>[ 1.582472] e1000: Copyright (c) 1999-2006 Intel Corporation.
10616 11:51:16.160769 <6>[ 1.588483] e1000e: Intel(R) PRO/1000 Network Driver
10617 11:51:16.166716 <6>[ 1.593699] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10618 11:51:16.173034 <6>[ 1.599883] igb: Intel(R) Gigabit Ethernet Network Driver
10619 11:51:16.179997 <6>[ 1.605533] igb: Copyright (c) 2007-2014 Intel Corporation.
10620 11:51:16.186358 <6>[ 1.611368] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10621 11:51:16.192803 <6>[ 1.617886] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10622 11:51:16.196432 <6>[ 1.624356] sky2: driver version 1.30
10623 11:51:16.202671 <6>[ 1.629356] VFIO - User Level meta-driver version: 0.3
10624 11:51:16.210471 <6>[ 1.637607] usbcore: registered new interface driver usb-storage
10625 11:51:16.216852 <6>[ 1.644051] usbcore: registered new device driver onboard-usb-hub
10626 11:51:16.226392 <6>[ 1.653243] mt6397-rtc mt6359-rtc: registered as rtc0
10627 11:51:16.235984 <6>[ 1.658711] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:51:16 UTC (1700826676)
10628 11:51:16.238857 <6>[ 1.668283] i2c_dev: i2c /dev entries driver
10629 11:51:16.255937 <6>[ 1.680027] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10630 11:51:16.275571 <6>[ 1.703016] cpu cpu0: EM: created perf domain
10631 11:51:16.279182 <6>[ 1.707949] cpu cpu4: EM: created perf domain
10632 11:51:16.286302 <6>[ 1.713582] sdhci: Secure Digital Host Controller Interface driver
10633 11:51:16.293273 <6>[ 1.720014] sdhci: Copyright(c) Pierre Ossman
10634 11:51:16.300482 <6>[ 1.724962] Synopsys Designware Multimedia Card Interface Driver
10635 11:51:16.306257 <6>[ 1.731599] sdhci-pltfm: SDHCI platform and OF driver helper
10636 11:51:16.309567 <6>[ 1.731650] mmc0: CQHCI version 5.10
10637 11:51:16.316248 <6>[ 1.741685] ledtrig-cpu: registered to indicate activity on CPUs
10638 11:51:16.322832 <6>[ 1.748733] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10639 11:51:16.329465 <6>[ 1.755792] usbcore: registered new interface driver usbhid
10640 11:51:16.333151 <6>[ 1.761616] usbhid: USB HID core driver
10641 11:51:16.339129 <6>[ 1.765809] spi_master spi0: will run message pump with realtime priority
10642 11:51:16.386401 <6>[ 1.807167] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10643 11:51:16.405575 <6>[ 1.822278] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10644 11:51:16.408630 <6>[ 1.836931] mmc0: Command Queue Engine enabled
10645 11:51:16.415875 <6>[ 1.841667] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10646 11:51:16.422126 <6>[ 1.841781] cros-ec-spi spi0.0: Chrome EC device registered
10647 11:51:16.425201 <6>[ 1.848846] mmcblk0: mmc0:0001 DA4128 116 GiB
10648 11:51:16.437522 <6>[ 1.864501] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10649 11:51:16.444760 <6>[ 1.871975] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10650 11:51:16.451698 <6>[ 1.877859] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10651 11:51:16.457751 <6>[ 1.883768] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10652 11:51:16.471625 <6>[ 1.895598] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10653 11:51:16.478773 <6>[ 1.906123] NET: Registered PF_PACKET protocol family
10654 11:51:16.482160 <6>[ 1.911519] 9pnet: Installing 9P2000 support
10655 11:51:16.489542 <5>[ 1.916083] Key type dns_resolver registered
10656 11:51:16.492927 <6>[ 1.921054] registered taskstats version 1
10657 11:51:16.498825 <5>[ 1.925446] Loading compiled-in X.509 certificates
10658 11:51:16.529507 <4>[ 1.949780] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 11:51:16.539205 <4>[ 1.960598] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10660 11:51:16.545668 <3>[ 1.971152] debugfs: File 'uA_load' in directory '/' already present!
10661 11:51:16.552430 <3>[ 1.977861] debugfs: File 'min_uV' in directory '/' already present!
10662 11:51:16.559431 <3>[ 1.984472] debugfs: File 'max_uV' in directory '/' already present!
10663 11:51:16.566197 <3>[ 1.991082] debugfs: File 'constraint_flags' in directory '/' already present!
10664 11:51:16.577027 <3>[ 2.000826] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10665 11:51:16.586379 <6>[ 2.013397] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10666 11:51:16.592975 <6>[ 2.020149] xhci-mtk 11200000.usb: xHCI Host Controller
10667 11:51:16.600090 <6>[ 2.025655] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10668 11:51:16.609676 <6>[ 2.033512] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10669 11:51:16.616750 <6>[ 2.042931] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10670 11:51:16.622894 <6>[ 2.048987] xhci-mtk 11200000.usb: xHCI Host Controller
10671 11:51:16.630302 <6>[ 2.054463] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10672 11:51:16.636488 <6>[ 2.062108] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10673 11:51:16.642723 <6>[ 2.069800] hub 1-0:1.0: USB hub found
10674 11:51:16.646543 <6>[ 2.073809] hub 1-0:1.0: 1 port detected
10675 11:51:16.652929 <6>[ 2.078078] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10676 11:51:16.659570 <6>[ 2.086632] hub 2-0:1.0: USB hub found
10677 11:51:16.662855 <6>[ 2.090641] hub 2-0:1.0: 1 port detected
10678 11:51:16.671979 <6>[ 2.099005] mtk-msdc 11f70000.mmc: Got CD GPIO
10679 11:51:16.681782 <6>[ 2.105997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10680 11:51:16.688644 <6>[ 2.114023] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10681 11:51:16.698572 <4>[ 2.122000] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10682 11:51:16.708270 <6>[ 2.131537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10683 11:51:16.714882 <6>[ 2.139638] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10684 11:51:16.724786 <6>[ 2.147806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10685 11:51:16.731612 <6>[ 2.155741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10686 11:51:16.738056 <6>[ 2.163562] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10687 11:51:16.747888 <6>[ 2.171385] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10688 11:51:16.758773 <6>[ 2.181791] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10689 11:51:16.764731 <6>[ 2.190169] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10690 11:51:16.774536 <6>[ 2.198508] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10691 11:51:16.781853 <6>[ 2.206846] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10692 11:51:16.791304 <6>[ 2.215185] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10693 11:51:16.801490 <6>[ 2.223524] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10694 11:51:16.808893 <6>[ 2.231863] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10695 11:51:16.817874 <6>[ 2.240202] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10696 11:51:16.824151 <6>[ 2.248541] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10697 11:51:16.834325 <6>[ 2.256888] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10698 11:51:16.840923 <6>[ 2.265227] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10699 11:51:16.850813 <6>[ 2.273566] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10700 11:51:16.857512 <6>[ 2.281904] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10701 11:51:16.867202 <6>[ 2.290245] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10702 11:51:16.874252 <6>[ 2.298583] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10703 11:51:16.881117 <6>[ 2.307304] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10704 11:51:16.887481 <6>[ 2.314457] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10705 11:51:16.894052 <6>[ 2.321230] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10706 11:51:16.904394 <6>[ 2.327998] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10707 11:51:16.910399 <6>[ 2.334934] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10708 11:51:16.917223 <6>[ 2.341778] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10709 11:51:16.927100 <6>[ 2.350904] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10710 11:51:16.937353 <6>[ 2.360022] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10711 11:51:16.947118 <6>[ 2.369323] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10712 11:51:16.956358 <6>[ 2.378798] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10713 11:51:16.967039 <6>[ 2.388265] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10714 11:51:16.973436 <6>[ 2.397385] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10715 11:51:16.982777 <6>[ 2.406852] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10716 11:51:16.993093 <6>[ 2.415970] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10717 11:51:17.003326 <6>[ 2.425263] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10718 11:51:17.012646 <6>[ 2.435424] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10719 11:51:17.022927 <6>[ 2.446935] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10720 11:51:17.029229 <6>[ 2.456532] Trying to probe devices needed for running init ...
10721 11:51:17.053589 <6>[ 2.477522] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10722 11:51:17.081642 <6>[ 2.508718] hub 2-1:1.0: USB hub found
10723 11:51:17.084644 <6>[ 2.513206] hub 2-1:1.0: 3 ports detected
10724 11:51:17.093209 <6>[ 2.520323] hub 2-1:1.0: USB hub found
10725 11:51:17.096843 <6>[ 2.524689] hub 2-1:1.0: 3 ports detected
10726 11:51:17.205327 <6>[ 2.629253] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10727 11:51:17.360495 <6>[ 2.787526] hub 1-1:1.0: USB hub found
10728 11:51:17.363644 <6>[ 2.792043] hub 1-1:1.0: 4 ports detected
10729 11:51:17.373804 <6>[ 2.801293] hub 1-1:1.0: USB hub found
10730 11:51:17.377773 <6>[ 2.805828] hub 1-1:1.0: 4 ports detected
10731 11:51:17.697772 <6>[ 3.121264] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10732 11:51:17.828613 <6>[ 3.255335] hub 1-1.1:1.0: USB hub found
10733 11:51:17.830833 <6>[ 3.259666] hub 1-1.1:1.0: 4 ports detected
10734 11:51:17.946064 <6>[ 3.369346] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10735 11:51:18.077543 <6>[ 3.504719] hub 1-1.4:1.0: USB hub found
10736 11:51:18.081381 <6>[ 3.509370] hub 1-1.4:1.0: 2 ports detected
10737 11:51:18.090432 <6>[ 3.517637] hub 1-1.4:1.0: USB hub found
10738 11:51:18.093395 <6>[ 3.522259] hub 1-1.4:1.0: 2 ports detected
10739 11:51:18.157579 <6>[ 3.581234] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10740 11:51:18.344666 <6>[ 3.769101] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10741 11:51:18.430365 <3>[ 3.857465] usb 1-1.1.4: device descriptor read/64, error -32
10742 11:51:18.622368 <3>[ 4.049459] usb 1-1.1.4: device descriptor read/64, error -32
10743 11:51:18.817689 <6>[ 4.241277] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10744 11:51:18.901994 <3>[ 4.329458] usb 1-1.1.4: device descriptor read/64, error -32
10745 11:51:19.094080 <3>[ 4.521456] usb 1-1.1.4: device descriptor read/64, error -32
10746 11:51:19.206200 <6>[ 4.633686] usb 1-1.1-port4: attempt power cycle
10747 11:51:19.288867 <6>[ 4.713275] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10748 11:51:19.480931 <6>[ 4.905234] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10749 11:51:19.877081 <6>[ 5.301276] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10750 11:51:19.883924 <4>[ 5.308757] usb 1-1.1.4: Device not responding to setup address.
10751 11:51:20.093208 <4>[ 5.521307] usb 1-1.1.4: Device not responding to setup address.
10752 11:51:20.305780 <3>[ 5.733313] usb 1-1.1.4: device not accepting address 10, error -71
10753 11:51:20.392854 <6>[ 5.817279] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10754 11:51:20.399244 <4>[ 5.824683] usb 1-1.1.4: Device not responding to setup address.
10755 11:51:20.609658 <4>[ 6.037536] usb 1-1.1.4: Device not responding to setup address.
10756 11:51:20.821330 <3>[ 6.249268] usb 1-1.1.4: device not accepting address 11, error -71
10757 11:51:20.828581 <3>[ 6.256301] usb 1-1.1-port4: unable to enumerate USB device
10758 11:51:29.302319 <6>[ 14.734244] ALSA device list:
10759 11:51:29.308716 <6>[ 14.737531] No soundcards found.
10760 11:51:29.316684 <6>[ 14.745455] Freeing unused kernel memory: 8384K
10761 11:51:29.320216 <6>[ 14.750447] Run /init as init process
10762 11:51:29.331305 Loading, please wait...
10763 11:51:29.352261 Starting version 247.3-7+deb11u2
10764 11:51:29.577296 <6>[ 15.002824] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10765 11:51:29.608054 <3>[ 15.033584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 11:51:29.614772 <3>[ 15.041795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 11:51:29.621991 <6>[ 15.046117] remoteproc remoteproc0: scp is available
10768 11:51:29.628274 <3>[ 15.049891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 11:51:29.637530 <3>[ 15.058150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 11:51:29.640989 <6>[ 15.063301] remoteproc remoteproc0: powering up scp
10771 11:51:29.651043 <3>[ 15.071363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 11:51:29.654751 <6>[ 15.074278] mc: Linux media interface: v0.10
10773 11:51:29.664928 <6>[ 15.076472] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10774 11:51:29.670795 <4>[ 15.081721] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10775 11:51:29.677809 <4>[ 15.081870] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10776 11:51:29.687814 <6>[ 15.081933] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10777 11:51:29.694326 <6>[ 15.081961] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10778 11:51:29.704047 <6>[ 15.081971] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10779 11:51:29.710993 <3>[ 15.084543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 11:51:29.717840 <6>[ 15.089090] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10781 11:51:29.724028 <6>[ 15.093328] videodev: Linux video capture interface: v2.00
10782 11:51:29.730537 <3>[ 15.097500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 11:51:29.737252 <6>[ 15.102840] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10784 11:51:29.744122 <6>[ 15.124329] usbcore: registered new interface driver r8152
10785 11:51:29.753787 <3>[ 15.128355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 11:51:29.760764 <3>[ 15.128414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 11:51:29.767361 <4>[ 15.141266] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10788 11:51:29.774548 <4>[ 15.141266] Fallback method does not support PEC.
10789 11:51:29.780480 <3>[ 15.145227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 11:51:29.790567 <3>[ 15.167538] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10791 11:51:29.800372 <3>[ 15.172263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 11:51:29.807076 <3>[ 15.172267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 11:51:29.814020 <3>[ 15.172314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 11:51:29.823785 <6>[ 15.188129] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10795 11:51:29.833678 <3>[ 15.194166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 11:51:29.841106 <3>[ 15.194170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 11:51:29.850061 <3>[ 15.194176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 11:51:29.856819 <3>[ 15.194179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 11:51:29.866931 <3>[ 15.194201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 11:51:29.874033 <3>[ 15.199587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 11:51:29.879632 <6>[ 15.201176] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10802 11:51:29.886208 <6>[ 15.202235] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10803 11:51:29.892990 <6>[ 15.202240] pci_bus 0000:00: root bus resource [bus 00-ff]
10804 11:51:29.900135 <6>[ 15.202244] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10805 11:51:29.909748 <6>[ 15.202247] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10806 11:51:29.916130 <6>[ 15.202274] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10807 11:51:29.926038 <6>[ 15.202287] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10808 11:51:29.929649 <6>[ 15.202360] pci 0000:00:00.0: supports D1 D2
10809 11:51:29.936010 <6>[ 15.202363] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10810 11:51:29.942510 <6>[ 15.203292] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10811 11:51:29.949402 <6>[ 15.203379] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10812 11:51:29.959080 <6>[ 15.203404] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10813 11:51:29.966013 <6>[ 15.203422] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10814 11:51:29.972383 <6>[ 15.203437] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10815 11:51:29.979055 <6>[ 15.203546] pci 0000:01:00.0: supports D1 D2
10816 11:51:29.985477 <6>[ 15.203548] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10817 11:51:29.995628 <6>[ 15.216713] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10818 11:51:30.002081 <6>[ 15.217113] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10819 11:51:30.008753 <6>[ 15.217137] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10820 11:51:30.018647 <6>[ 15.217140] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10821 11:51:30.025347 <6>[ 15.217148] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10822 11:51:30.031975 <6>[ 15.217160] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10823 11:51:30.041577 <6>[ 15.217173] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10824 11:51:30.045704 <6>[ 15.217185] pci 0000:00:00.0: PCI bridge to [bus 01]
10825 11:51:30.054895 <6>[ 15.217190] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10826 11:51:30.062005 <6>[ 15.217317] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10827 11:51:30.067942 <6>[ 15.217770] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10828 11:51:30.071511 <6>[ 15.218382] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10829 11:51:30.082093 <6>[ 15.230478] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10830 11:51:30.088181 <6>[ 15.232811] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10831 11:51:30.097617 <6>[ 15.233917] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10832 11:51:30.104811 <6>[ 15.262074] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10833 11:51:30.112323 <6>[ 15.266743] remoteproc remoteproc0: remote processor scp is now up
10834 11:51:30.117492 <6>[ 15.266975] usbcore: registered new interface driver cdc_ether
10835 11:51:30.124434 <6>[ 15.275365] usbcore: registered new interface driver r8153_ecm
10836 11:51:30.131002 <5>[ 15.280539] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10837 11:51:30.140439 <6>[ 15.280714] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10838 11:51:30.144097 <6>[ 15.291674] Bluetooth: Core ver 2.22
10839 11:51:30.150606 <6>[ 15.292533] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10840 11:51:30.157201 <5>[ 15.293608] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10841 11:51:30.167569 <4>[ 15.293698] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10842 11:51:30.171248 <6>[ 15.293708] cfg80211: failed to load regulatory.db
10843 11:51:30.183520 <6>[ 15.293854] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10844 11:51:30.190309 <6>[ 15.294002] usbcore: registered new interface driver uvcvideo
10845 11:51:30.197007 <6>[ 15.322407] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10846 11:51:30.203399 <6>[ 15.327554] NET: Registered PF_BLUETOOTH protocol family
10847 11:51:30.213499 <4>[ 15.369113] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10848 11:51:30.220008 <6>[ 15.369625] Bluetooth: HCI device and connection manager initialized
10849 11:51:30.227114 <4>[ 15.377913] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10850 11:51:30.233186 <6>[ 15.384159] Bluetooth: HCI socket layer initialized
10851 11:51:30.240156 <6>[ 15.396387] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10852 11:51:30.242737 <6>[ 15.399108] Bluetooth: L2CAP socket layer initialized
10853 11:51:30.249465 <6>[ 15.406662] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10854 11:51:30.256197 <6>[ 15.411097] Bluetooth: SCO socket layer initialized
10855 11:51:30.262772 <6>[ 15.437138] mt7921e 0000:01:00.0: ASIC revision: 79610010
10856 11:51:30.266056 <6>[ 15.453119] r8152 1-1.1.1:1.0 eth0: v1.12.13
10857 11:51:30.272634 <6>[ 15.480831] usbcore: registered new interface driver btusb
10858 11:51:30.283056 <4>[ 15.481546] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10859 11:51:30.289286 <3>[ 15.481559] Bluetooth: hci0: Failed to load firmware file (-2)
10860 11:51:30.292721 <3>[ 15.481564] Bluetooth: hci0: Failed to set up firmware (-2)
10861 11:51:30.306054 <4>[ 15.481569] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10862 11:51:30.309175 <6>[ 15.496478] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10863 11:51:30.322632 <4>[ 15.552107] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10864 11:51:30.342456 Begin: Loading essential drivers ... done.
10865 11:51:30.345935 Begin: Running /scripts/init-premount ... done.
10866 11:51:30.352398 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10867 11:51:30.362166 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10868 11:51:30.365498 Device /sys/class/net/enxf4f5e850de0a found
10869 11:51:30.366013 done.
10870 11:51:30.423642 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10871 11:51:30.442442 <4>[ 15.864653] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 11:51:30.560088 <4>[ 15.982423] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10873 11:51:30.676704 <4>[ 16.098300] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10874 11:51:30.792001 <4>[ 16.214153] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10875 11:51:30.907814 <4>[ 16.330024] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10876 11:51:31.023871 <4>[ 16.446060] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10877 11:51:31.140438 <4>[ 16.562309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10878 11:51:31.255805 <4>[ 16.678069] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10879 11:51:31.371209 <4>[ 16.793950] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10880 11:51:31.478722 <3>[ 16.907769] mt7921e 0000:01:00.0: hardware init failed
10881 11:51:31.686309 <6>[ 17.115613] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10882 11:51:31.729656 IP-Config: no response after 2 secs - giving up
10883 11:51:31.771297 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10884 11:51:31.774583 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10885 11:51:31.784422 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10886 11:51:31.790872 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10887 11:51:31.797788 host : mt8192-asurada-spherion-r0-cbg-9
10888 11:51:31.804183 domain : lava-rack
10889 11:51:31.808075 rootserver: 192.168.201.1 rootpath:
10890 11:51:31.808156 filename :
10891 11:51:31.850733 done.
10892 11:51:31.857843 Begin: Running /scripts/nfs-bottom ... done.
10893 11:51:31.877472 Begin: Running /scripts/init-bottom ... done.
10894 11:51:33.093753 <6>[ 18.523410] NET: Registered PF_INET6 protocol family
10895 11:51:33.101294 <6>[ 18.530910] Segment Routing with IPv6
10896 11:51:33.104940 <6>[ 18.534954] In-situ OAM (IOAM) with IPv6
10897 11:51:33.228811 <30>[ 18.638011] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10898 11:51:33.231887 <30>[ 18.662385] systemd[1]: Detected architecture arm64.
10899 11:51:33.254478
10900 11:51:33.258061 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10901 11:51:33.258527
10902 11:51:33.274726 <30>[ 18.703946] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10903 11:51:34.157293 <30>[ 19.583579] systemd[1]: Queued start job for default target Graphical Interface.
10904 11:51:34.198151 <30>[ 19.627726] systemd[1]: Created slice system-getty.slice.
10905 11:51:34.204539 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10906 11:51:34.221144 <30>[ 19.650719] systemd[1]: Created slice system-modprobe.slice.
10907 11:51:34.228727 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10908 11:51:34.245985 <30>[ 19.675206] systemd[1]: Created slice system-serial\x2dgetty.slice.
10909 11:51:34.256776 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10910 11:51:34.268897 <30>[ 19.698315] systemd[1]: Created slice User and Session Slice.
10911 11:51:34.275487 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10912 11:51:34.296592 <30>[ 19.722091] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10913 11:51:34.306181 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10914 11:51:34.324408 <30>[ 19.750004] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10915 11:51:34.333551 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10916 11:51:34.354916 <30>[ 19.777387] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10917 11:51:34.361011 <30>[ 19.789539] systemd[1]: Reached target Local Encrypted Volumes.
10918 11:51:34.367810 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10919 11:51:34.384779 <30>[ 19.813816] systemd[1]: Reached target Paths.
10920 11:51:34.387674 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10921 11:51:34.404218 <30>[ 19.833253] systemd[1]: Reached target Remote File Systems.
10922 11:51:34.410890 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10923 11:51:34.428459 <30>[ 19.857609] systemd[1]: Reached target Slices.
10924 11:51:34.434876 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10925 11:51:34.448534 <30>[ 19.877282] systemd[1]: Reached target Swap.
10926 11:51:34.451581 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10927 11:51:34.471948 <30>[ 19.897741] systemd[1]: Listening on initctl Compatibility Named Pipe.
10928 11:51:34.478747 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10929 11:51:34.484932 <30>[ 19.913911] systemd[1]: Listening on Journal Audit Socket.
10930 11:51:34.491514 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10931 11:51:34.509478 <30>[ 19.938788] systemd[1]: Listening on Journal Socket (/dev/log).
10932 11:51:34.516059 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10933 11:51:34.532367 <30>[ 19.961800] systemd[1]: Listening on Journal Socket.
10934 11:51:34.539078 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10935 11:51:34.557470 <30>[ 19.982839] systemd[1]: Listening on Network Service Netlink Socket.
10936 11:51:34.563328 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10937 11:51:34.579063 <30>[ 20.008221] systemd[1]: Listening on udev Control Socket.
10938 11:51:34.585449 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10939 11:51:34.600218 <30>[ 20.029682] systemd[1]: Listening on udev Kernel Socket.
10940 11:51:34.607485 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10941 11:51:34.683929 <30>[ 20.113471] systemd[1]: Mounting Huge Pages File System...
10942 11:51:34.690503 Mounting [0;1;39mHuge Pages File System[0m...
10943 11:51:34.708598 <30>[ 20.137561] systemd[1]: Mounting POSIX Message Queue File System...
10944 11:51:34.715118 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10945 11:51:34.736338 <30>[ 20.165551] systemd[1]: Mounting Kernel Debug File System...
10946 11:51:34.742275 Mounting [0;1;39mKernel Debug File System[0m...
10947 11:51:34.759014 <30>[ 20.185797] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10948 11:51:34.780760 <30>[ 20.206867] systemd[1]: Starting Create list of static device nodes for the current kernel...
10949 11:51:34.787049 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10950 11:51:34.840548 <30>[ 20.269981] systemd[1]: Starting Load Kernel Module configfs...
10951 11:51:34.846999 Starting [0;1;39mLoad Kernel Module configfs[0m...
10952 11:51:34.867020 <30>[ 20.295874] systemd[1]: Starting Load Kernel Module drm...
10953 11:51:34.873065 Starting [0;1;39mLoad Kernel Module drm[0m...
10954 11:51:34.896215 <30>[ 20.325803] systemd[1]: Starting Load Kernel Module fuse...
10955 11:51:34.903034 Starting [0;1;39mLoad Kernel Module fuse[0m...
10956 11:51:34.926528 <30>[ 20.351614] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10957 11:51:34.944102 <30>[ 20.373728] systemd[1]: Starting Journal Service...
10958 11:51:34.951245 Starting [0;1;39mJournal Service[0m...
10959 11:51:34.957784 <6>[ 20.386475] fuse: init (API version 7.37)
10960 11:51:34.977919 <30>[ 20.407080] systemd[1]: Starting Load Kernel Modules...
10961 11:51:34.984393 Starting [0;1;39mLoad Kernel Modules[0m...
10962 11:51:35.009236 <30>[ 20.435241] systemd[1]: Starting Remount Root and Kernel File Systems...
10963 11:51:35.015488 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10964 11:51:35.034545 <30>[ 20.464082] systemd[1]: Starting Coldplug All udev Devices...
10965 11:51:35.041207 Starting [0;1;39mColdplug All udev Devices[0m...
10966 11:51:35.059585 <30>[ 20.489050] systemd[1]: Mounted Huge Pages File System.
10967 11:51:35.066007 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10968 11:51:35.080611 <30>[ 20.510122] systemd[1]: Mounted POSIX Message Queue File System.
10969 11:51:35.086952 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10970 11:51:35.108763 <30>[ 20.537941] systemd[1]: Mounted Kernel Debug File System.
10971 11:51:35.118473 <3>[ 20.539116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:51:35.125287 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10973 11:51:35.145173 <30>[ 20.571121] systemd[1]: Finished Create list of static device nodes for the current kernel.
10974 11:51:35.154948 <3>[ 20.576332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 11:51:35.162904 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10976 11:51:35.177147 <30>[ 20.606403] systemd[1]: modprobe@configfs.service: Succeeded.
10977 11:51:35.183779 <30>[ 20.613216] systemd[1]: Finished Load Kernel Module configfs.
10978 11:51:35.191266 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10979 11:51:35.200923 <3>[ 20.626870] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 11:51:35.208873 <30>[ 20.638309] systemd[1]: modprobe@drm.service: Succeeded.
10981 11:51:35.215547 <30>[ 20.644717] systemd[1]: Finished Load Kernel Module drm.
10982 11:51:35.222056 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10983 11:51:35.234809 <3>[ 20.661320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 11:51:35.242079 <30>[ 20.671467] systemd[1]: modprobe@fuse.service: Succeeded.
10985 11:51:35.248789 <30>[ 20.677981] systemd[1]: Finished Load Kernel Module fuse.
10986 11:51:35.254886 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10987 11:51:35.271251 <3>[ 20.697501] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 11:51:35.278862 <30>[ 20.708434] systemd[1]: Finished Load Kernel Modules.
10989 11:51:35.285325 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10990 11:51:35.301975 <30>[ 20.730965] systemd[1]: Finished Remount Root and Kernel File Systems.
10991 11:51:35.312385 <3>[ 20.733926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 11:51:35.318316 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10993 11:51:35.346368 <3>[ 20.772507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 11:51:35.381622 <3>[ 20.807523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 11:51:35.391380 <30>[ 20.820986] systemd[1]: Mounting FUSE Control File System...
10996 11:51:35.398196 Mounting [0;1;39mFUSE Control File System[0m...
10997 11:51:35.415719 <3>[ 20.841546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 11:51:35.421810 <30>[ 20.843740] systemd[1]: Mounting Kernel Configuration File System...
10999 11:51:35.428691 Mounting [0;1;39mKernel Configuration File System[0m...
11000 11:51:35.450018 <3>[ 20.875483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 11:51:35.462020 <30>[ 20.887885] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
11002 11:51:35.471766 <30>[ 20.896878] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
11003 11:51:35.501282 <30>[ 20.930049] systemd[1]: Starting Load/Save Random Seed...
11004 11:51:35.507816 Starting [0;1;39mLoad/Save Random Seed[0m...
11005 11:51:35.522269 <30>[ 20.951599] systemd[1]: Starting Apply Kernel Variables...
11006 11:51:35.529111 Starting [0;1;39mApply Kernel Variables[0m...
11007 11:51:35.548181 <30>[ 20.977721] systemd[1]: Starting Create System Users...
11008 11:51:35.554813 Starting [0;1;39mCreate System Users[0m...
11009 11:51:35.571099 <30>[ 21.000119] systemd[1]: Started Journal Service.
11010 11:51:35.588947 <4>[ 21.004637] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11011 11:51:35.597385 [[0;32m OK [<3>[ 21.021557] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11012 11:51:35.600877 0m] Started [0;1;39mJournal Service[0m.
11013 11:51:35.620748 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
11014 11:51:35.635720 See 'systemctl status systemd-udev-trigger.service' for details.
11015 11:51:35.653347 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
11016 11:51:35.668724 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11017 11:51:35.685815 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11018 11:51:35.702175 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11019 11:51:35.722437 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11020 11:51:35.769342 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11021 11:51:35.786860 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11022 11:51:35.831081 <46>[ 21.257602] systemd-journald[298]: Received client request to flush runtime journal.
11023 11:51:35.866944 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11024 11:51:35.880159 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11025 11:51:35.896555 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11026 11:51:35.947455 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11027 11:51:37.238390 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11028 11:51:37.272380 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11029 11:51:37.311351 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11030 11:51:37.365059 Starting [0;1;39mNetwork Service[0m...
11031 11:51:37.691108 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11032 11:51:37.716993 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11033 11:51:37.770839 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11034 11:51:38.064420 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11035 11:51:38.082745 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11036 11:51:38.099604 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11037 11:51:38.120247 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11038 11:51:38.136353 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11039 11:51:38.224912 Starting [0;1;39mNetwork Name Resolution[0m...
11040 11:51:38.243137 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11041 11:51:38.268954 Starting [0;1;39mNetwork Time Synchronization[0m...
11042 11:51:38.288967 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11043 11:51:38.306042 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11044 11:51:38.404298 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11045 11:51:38.703952 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11046 11:51:38.719670 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11047 11:51:38.738864 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11048 11:51:38.751403 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11049 11:51:38.766956 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11050 11:51:38.814319 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11051 11:51:38.836810 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11052 11:51:38.857426 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11053 11:51:38.877335 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11054 11:51:38.892117 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11055 11:51:38.912464 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11056 11:51:38.927360 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11057 11:51:38.943445 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11058 11:51:38.981671 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11059 11:51:39.089025 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11060 11:51:39.169506 Starting [0;1;39mUser Login Management[0m...
11061 11:51:39.184958 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11062 11:51:39.205141 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11063 11:51:39.222819 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11064 11:51:39.259845 Starting [0;1;39mPermit User Sessions[0m...
11065 11:51:39.318989 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11066 11:51:39.360494 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11067 11:51:39.408067 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11068 11:51:39.423886 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11069 11:51:39.445506 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11070 11:51:39.457817 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11071 11:51:39.482187 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11072 11:51:39.500220 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11073 11:51:39.541498 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11074 11:51:39.594750 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11075 11:51:39.680747
11076 11:51:39.681285
11077 11:51:39.684070 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11078 11:51:39.684518
11079 11:51:39.688257 debian-bullseye-arm64 login: root (automatic login)
11080 11:51:39.688822
11081 11:51:39.689172
11082 11:51:40.054781 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11083 11:51:40.055389
11084 11:51:40.061254 The programs included with the Debian GNU/Linux system are free software;
11085 11:51:40.068469 the exact distribution terms for each program are described in the
11086 11:51:40.070983 individual files in /usr/share/doc/*/copyright.
11087 11:51:40.071450
11088 11:51:40.078115 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11089 11:51:40.080791 permitted by applicable law.
11090 11:51:41.068220 Matched prompt #10: / #
11092 11:51:41.068738 Setting prompt string to ['/ #']
11093 11:51:41.068921 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11095 11:51:41.069325 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11096 11:51:41.069526 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11097 11:51:41.069676 Setting prompt string to ['/ #']
11098 11:51:41.069806 Forcing a shell prompt, looking for ['/ #']
11100 11:51:41.120235 / #
11101 11:51:41.120987 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11102 11:51:41.121459 Waiting using forced prompt support (timeout 00:02:30)
11103 11:51:41.127307
11104 11:51:41.128251 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11105 11:51:41.128802 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11107 11:51:41.230277 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5'
11108 11:51:41.236995 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074064/extract-nfsrootfs-o8l93lg5'
11110 11:51:41.338867 / # export NFS_SERVER_IP='192.168.201.1'
11111 11:51:41.345047 export NFS_SERVER_IP='192.168.201.1'
11112 11:51:41.346039 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11113 11:51:41.346578 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11114 11:51:41.347094 end: 2 depthcharge-action (duration 00:01:22) [common]
11115 11:51:41.347605 start: 3 lava-test-retry (timeout 00:07:54) [common]
11116 11:51:41.348106 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
11117 11:51:41.348519 Using namespace: common
11119 11:51:41.449769 / # #
11120 11:51:41.450440 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11121 11:51:41.456247 #
11122 11:51:41.457149 Using /lava-12074064
11124 11:51:41.558351 / # export SHELL=/bin/bash
11125 11:51:41.565196 export SHELL=/bin/bash
11127 11:51:41.667145 / # . /lava-12074064/environment
11128 11:51:41.673980 . /lava-12074064/environment
11130 11:51:41.782327 / # /lava-12074064/bin/lava-test-runner /lava-12074064/0
11131 11:51:41.783102 Test shell timeout: 10s (minimum of the action and connection timeout)
11132 11:51:41.788696 /lava-12074064/bin/lava-test-runner /lava-12074064/0
11133 11:51:42.073452 + export TESTRUN_ID=0_timesync-off
11134 11:51:42.076808 + TESTRUN_ID=0_timesync-off
11135 11:51:42.080431 + cd /lava-12074064/0/tests/0_timesync-off
11136 11:51:42.083422 ++ cat uuid
11137 11:51:42.086612 + UUID=12074064_1.6.2.3.1
11138 11:51:42.086696 + set +x
11139 11:51:42.093258 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12074064_1.6.2.3.1>
11140 11:51:42.093550 Received signal: <STARTRUN> 0_timesync-off 12074064_1.6.2.3.1
11141 11:51:42.093630 Starting test lava.0_timesync-off (12074064_1.6.2.3.1)
11142 11:51:42.093723 Skipping test definition patterns.
11143 11:51:42.096498 + systemctl stop systemd-timesyncd
11144 11:51:42.147941 + set +x
11145 11:51:42.150967 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12074064_1.6.2.3.1>
11146 11:51:42.151234 Received signal: <ENDRUN> 0_timesync-off 12074064_1.6.2.3.1
11147 11:51:42.151326 Ending use of test pattern.
11148 11:51:42.151394 Ending test lava.0_timesync-off (12074064_1.6.2.3.1), duration 0.06
11150 11:51:42.213679 + export TESTRUN_ID=1_kselftest-rtc
11151 11:51:42.218322 + TESTRUN_ID=1_kselftest-rtc
11152 11:51:42.220565 + cd /lava-12074064/0/tests/1_kselftest-rtc
11153 11:51:42.223415 ++ cat uuid
11154 11:51:42.226901 + UUID=12074064_1.6.2.3.5
11155 11:51:42.226985 + set +x
11156 11:51:42.233731 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12074064_1.6.2.3.5>
11157 11:51:42.233986 Received signal: <STARTRUN> 1_kselftest-rtc 12074064_1.6.2.3.5
11158 11:51:42.234061 Starting test lava.1_kselftest-rtc (12074064_1.6.2.3.5)
11159 11:51:42.234141 Skipping test definition patterns.
11160 11:51:42.236826 + cd ./automated/linux/kselftest/
11161 11:51:42.263710 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11162 11:51:42.299745 INFO: install_deps skipped
11163 11:51:42.412557 --2023-11-24 11:51:42-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11164 11:51:42.428645 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11165 11:51:42.563270 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11166 11:51:42.695376 HTTP request sent, awaiting response... 200 OK
11167 11:51:42.698966 Length: 2961876 (2.8M) [application/octet-stream]
11168 11:51:42.701924 Saving to: 'kselftest.tar.xz'
11169 11:51:42.702397
11170 11:51:42.702769
11171 11:51:42.961588 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11172 11:51:43.229485 kselftest.tar.xz 1%[ ] 47.81K 185KB/s
11173 11:51:43.676279 kselftest.tar.xz 7%[> ] 217.50K 419KB/s
11174 11:51:43.948710 kselftest.tar.xz 27%[====> ] 804.33K 841KB/s
11175 11:51:44.041379 kselftest.tar.xz 79%[==============> ] 2.25M 1.84MB/s
11176 11:51:44.047225 kselftest.tar.xz 100%[===================>] 2.82M 2.15MB/s in 1.3s
11177 11:51:44.047846
11178 11:51:44.304789 2023-11-24 11:51:44 (2.15 MB/s) - 'kselftest.tar.xz' saved [2961876/2961876]
11179 11:51:44.304954
11180 11:51:50.362806 skiplist:
11181 11:51:50.365938 ========================================
11182 11:51:50.369031 ========================================
11183 11:51:50.423443 rtc:rtctest
11184 11:51:50.444324 ============== Tests to run ===============
11185 11:51:50.444767 rtc:rtctest
11186 11:51:50.451093 ===========End Tests to run ===============
11187 11:51:50.454459 shardfile-rtc pass
11188 11:51:50.561259 <12>[ 35.992746] kselftest: Running tests in rtc
11189 11:51:50.570814 TAP version 13
11190 11:51:50.583426 1..1
11191 11:51:50.616848 # selftests: rtc: rtctest
11192 11:51:51.078877 # TAP version 13
11193 11:51:51.079446 # 1..8
11194 11:51:51.082107 # # Starting 8 tests from 2 test cases.
11195 11:51:51.085169 # # RUN rtc.date_read ...
11196 11:51:51.092319 # # rtctest.c:49:date_read:Current RTC date/time is 24/11/2023 11:51:50.
11197 11:51:51.095247 # # OK rtc.date_read
11198 11:51:51.098676 # ok 1 rtc.date_read
11199 11:51:51.102095 # # RUN rtc.date_read_loop ...
11200 11:51:51.111976 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11201 11:52:00.992361 <6>[ 46.427875] vpu: disabling
11202 11:52:00.995631 <6>[ 46.430981] vproc2: disabling
11203 11:52:00.998884 <6>[ 46.434870] vproc1: disabling
11204 11:52:01.004134 <6>[ 46.438991] vaud18: disabling
11205 11:52:01.010179 <6>[ 46.442734] vsram_others: disabling
11206 11:52:01.013664 <6>[ 46.446937] va09: disabling
11207 11:52:01.017067 <6>[ 46.450345] vsram_md: disabling
11208 11:52:01.019933 <6>[ 46.454136] Vgpu: disabling
11209 11:52:20.773134 # # rtctest.c:115:date_read_loop:Performed 2596 RTC time reads.
11210 11:52:20.776329 # # OK rtc.date_read_loop
11211 11:52:20.779279 # ok 2 rtc.date_read_loop
11212 11:52:20.782757 # # RUN rtc.uie_read ...
11213 11:52:23.754655 # # OK rtc.uie_read
11214 11:52:23.757923 # ok 3 rtc.uie_read
11215 11:52:23.761108 # # RUN rtc.uie_select ...
11216 11:52:26.754541 # # OK rtc.uie_select
11217 11:52:26.757172 # ok 4 rtc.uie_select
11218 11:52:26.760386 # # RUN rtc.alarm_alm_set ...
11219 11:52:26.767497 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:52:30.
11220 11:52:26.770579 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11221 11:52:26.777337 # # alarm_alm_set: Test terminated by assertion
11222 11:52:26.780440 # # FAIL rtc.alarm_alm_set
11223 11:52:26.784103 # not ok 5 rtc.alarm_alm_set
11224 11:52:26.787157 # # RUN rtc.alarm_wkalm_set ...
11225 11:52:26.793993 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 24/11/2023 11:52:30.
11226 11:52:29.756510 # # OK rtc.alarm_wkalm_set
11227 11:52:29.757071 # ok 6 rtc.alarm_wkalm_set
11228 11:52:29.763537 # # RUN rtc.alarm_alm_set_minute ...
11229 11:52:29.766298 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:53:00.
11230 11:52:29.772967 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11231 11:52:29.779218 # # alarm_alm_set_minute: Test terminated by assertion
11232 11:52:29.783292 # # FAIL rtc.alarm_alm_set_minute
11233 11:52:29.785966 # not ok 7 rtc.alarm_alm_set_minute
11234 11:52:29.789487 # # RUN rtc.alarm_wkalm_set_minute ...
11235 11:52:29.795996 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 24/11/2023 11:53:00.
11236 11:52:59.752886 # # OK rtc.alarm_wkalm_set_minute
11237 11:52:59.756464 # ok 8 rtc.alarm_wkalm_set_minute
11238 11:52:59.759535 # # FAILED: 6 / 8 tests passed.
11239 11:52:59.762849 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11240 11:52:59.767123 not ok 1 selftests: rtc: rtctest # exit=1
11241 11:53:00.387414 rtc_rtctest_rtc_date_read pass
11242 11:53:00.390221 rtc_rtctest_rtc_date_read_loop pass
11243 11:53:00.393993 rtc_rtctest_rtc_uie_read pass
11244 11:53:00.397159 rtc_rtctest_rtc_uie_select pass
11245 11:53:00.400298 rtc_rtctest_rtc_alarm_alm_set fail
11246 11:53:00.403940 rtc_rtctest_rtc_alarm_wkalm_set pass
11247 11:53:00.406867 rtc_rtctest_rtc_alarm_alm_set_minute fail
11248 11:53:00.410076 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11249 11:53:00.414011 rtc_rtctest fail
11250 11:53:00.420741 + ../../utils/send-to-lava.sh ./output/result.txt
11251 11:53:00.501932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11252 11:53:00.502716 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11254 11:53:00.566727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11255 11:53:00.567448 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11257 11:53:00.631655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11258 11:53:00.632498 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11260 11:53:00.689579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11261 11:53:00.690354 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11263 11:53:00.747356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11264 11:53:00.748089 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11266 11:53:00.809571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11267 11:53:00.809866 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11269 11:53:00.872385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11270 11:53:00.873122 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11272 11:53:00.932429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11273 11:53:00.932787 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11275 11:53:00.993230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11276 11:53:00.994063 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11278 11:53:01.049013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11279 11:53:01.049498 + set +x
11280 11:53:01.050102 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11282 11:53:01.056044 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12074064_1.6.2.3.5>
11283 11:53:01.056765 Received signal: <ENDRUN> 1_kselftest-rtc 12074064_1.6.2.3.5
11284 11:53:01.057144 Ending use of test pattern.
11285 11:53:01.057510 Ending test lava.1_kselftest-rtc (12074064_1.6.2.3.5), duration 78.82
11287 11:53:01.059017 ok: lava_test_shell seems to have completed
11288 11:53:01.060414 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11289 11:53:01.060900 end: 3.1 lava-test-shell (duration 00:01:20) [common]
11290 11:53:01.061508 end: 3 lava-test-retry (duration 00:01:20) [common]
11291 11:53:01.062308 start: 4 finalize (timeout 00:06:34) [common]
11292 11:53:01.062935 start: 4.1 power-off (timeout 00:00:30) [common]
11293 11:53:01.064330 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11294 11:53:01.151555 >> Command sent successfully.
11295 11:53:01.156045 Returned 0 in 0 seconds
11296 11:53:01.257108 end: 4.1 power-off (duration 00:00:00) [common]
11298 11:53:01.258843 start: 4.2 read-feedback (timeout 00:06:34) [common]
11300 11:53:01.261208 Listened to connection for namespace 'common' for up to 1s
11301 11:53:02.260734 Finalising connection for namespace 'common'
11302 11:53:02.261543 Disconnecting from shell: Finalise
11303 11:53:02.262094 / #
11304 11:53:02.363248 end: 4.2 read-feedback (duration 00:00:01) [common]
11305 11:53:02.363953 end: 4 finalize (duration 00:00:01) [common]
11306 11:53:02.364564 Cleaning after the job
11307 11:53:02.365100 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/ramdisk
11308 11:53:02.378642 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/kernel
11309 11:53:02.413034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/dtb
11310 11:53:02.413312 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/nfsrootfs
11311 11:53:02.507305 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074064/tftp-deploy-1je_ui1h/modules
11312 11:53:02.514563 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074064
11313 11:53:03.151760 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074064
11314 11:53:03.151946 Job finished correctly