Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 38
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:49:00.385450 lava-dispatcher, installed at version: 2023.10
2 11:49:00.385735 start: 0 validate
3 11:49:00.385878 Start time: 2023-11-24 11:49:00.385869+00:00 (UTC)
4 11:49:00.386012 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:49:00.386146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:49:00.653059 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:49:00.653244 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:49:00.919044 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:49:00.919239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:49:01.175897 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:49:01.176095 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:49:01.440928 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:49:01.441116 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:49:01.707792 validate duration: 1.32
16 11:49:01.708129 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:49:01.708240 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:49:01.708344 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:49:01.708491 Not decompressing ramdisk as can be used compressed.
20 11:49:01.708615 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 11:49:01.708692 saving as /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/ramdisk/initrd.cpio.gz
22 11:49:01.708780 total size: 4665398 (4 MB)
23 11:49:01.710420 progress 0 % (0 MB)
24 11:49:01.714277 progress 5 % (0 MB)
25 11:49:01.715616 progress 10 % (0 MB)
26 11:49:01.716899 progress 15 % (0 MB)
27 11:49:01.718217 progress 20 % (0 MB)
28 11:49:01.719457 progress 25 % (1 MB)
29 11:49:01.738365 progress 30 % (1 MB)
30 11:49:01.749424 progress 35 % (1 MB)
31 11:49:01.754963 progress 40 % (1 MB)
32 11:49:01.764419 progress 45 % (2 MB)
33 11:49:01.765781 progress 50 % (2 MB)
34 11:49:01.771315 progress 55 % (2 MB)
35 11:49:01.772594 progress 60 % (2 MB)
36 11:49:01.773902 progress 65 % (2 MB)
37 11:49:01.775172 progress 70 % (3 MB)
38 11:49:01.776467 progress 75 % (3 MB)
39 11:49:01.777803 progress 80 % (3 MB)
40 11:49:01.779278 progress 85 % (3 MB)
41 11:49:01.780591 progress 90 % (4 MB)
42 11:49:01.781905 progress 95 % (4 MB)
43 11:49:01.783340 progress 100 % (4 MB)
44 11:49:01.783522 4 MB downloaded in 0.07 s (59.53 MB/s)
45 11:49:01.783696 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:49:01.783972 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:49:01.784077 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:49:01.784179 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:49:01.784359 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:49:01.784463 saving as /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/kernel/Image
52 11:49:01.784563 total size: 49107456 (46 MB)
53 11:49:01.784663 No compression specified
54 11:49:01.786350 progress 0 % (0 MB)
55 11:49:01.799057 progress 5 % (2 MB)
56 11:49:01.811977 progress 10 % (4 MB)
57 11:49:01.825182 progress 15 % (7 MB)
58 11:49:01.838424 progress 20 % (9 MB)
59 11:49:01.851420 progress 25 % (11 MB)
60 11:49:01.864335 progress 30 % (14 MB)
61 11:49:01.877550 progress 35 % (16 MB)
62 11:49:01.890616 progress 40 % (18 MB)
63 11:49:01.903396 progress 45 % (21 MB)
64 11:49:01.916310 progress 50 % (23 MB)
65 11:49:01.929286 progress 55 % (25 MB)
66 11:49:01.942415 progress 60 % (28 MB)
67 11:49:01.955605 progress 65 % (30 MB)
68 11:49:01.969333 progress 70 % (32 MB)
69 11:49:01.982617 progress 75 % (35 MB)
70 11:49:01.995709 progress 80 % (37 MB)
71 11:49:02.008721 progress 85 % (39 MB)
72 11:49:02.021902 progress 90 % (42 MB)
73 11:49:02.034671 progress 95 % (44 MB)
74 11:49:02.047376 progress 100 % (46 MB)
75 11:49:02.047635 46 MB downloaded in 0.26 s (178.02 MB/s)
76 11:49:02.047787 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:49:02.048016 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:49:02.048108 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:49:02.048207 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:49:02.048352 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:49:02.048422 saving as /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/dtb/mt8192-asurada-spherion-r0.dtb
83 11:49:02.048484 total size: 47278 (0 MB)
84 11:49:02.048545 No compression specified
85 11:49:02.049700 progress 69 % (0 MB)
86 11:49:02.049979 progress 100 % (0 MB)
87 11:49:02.050136 0 MB downloaded in 0.00 s (27.34 MB/s)
88 11:49:02.050259 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:49:02.050481 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:49:02.050571 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:49:02.050654 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:49:02.050889 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 11:49:02.051014 saving as /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/nfsrootfs/full.rootfs.tar
95 11:49:02.051120 total size: 89451516 (85 MB)
96 11:49:02.051217 Using unxz to decompress xz
97 11:49:02.058691 progress 0 % (0 MB)
98 11:49:02.278882 progress 5 % (4 MB)
99 11:49:02.505256 progress 10 % (8 MB)
100 11:49:02.769745 progress 15 % (12 MB)
101 11:49:02.970236 progress 20 % (17 MB)
102 11:49:03.066066 progress 25 % (21 MB)
103 11:49:03.314594 progress 30 % (25 MB)
104 11:49:03.601160 progress 35 % (29 MB)
105 11:49:03.868155 progress 40 % (34 MB)
106 11:49:04.136033 progress 45 % (38 MB)
107 11:49:04.387239 progress 50 % (42 MB)
108 11:49:04.655733 progress 55 % (46 MB)
109 11:49:04.913270 progress 60 % (51 MB)
110 11:49:05.182904 progress 65 % (55 MB)
111 11:49:05.477318 progress 70 % (59 MB)
112 11:49:05.778894 progress 75 % (64 MB)
113 11:49:06.075945 progress 80 % (68 MB)
114 11:49:06.330001 progress 85 % (72 MB)
115 11:49:06.569369 progress 90 % (76 MB)
116 11:49:06.844859 progress 95 % (81 MB)
117 11:49:07.109465 progress 100 % (85 MB)
118 11:49:07.115994 85 MB downloaded in 5.06 s (16.84 MB/s)
119 11:49:07.116282 end: 1.4.1 http-download (duration 00:00:05) [common]
121 11:49:07.116553 end: 1.4 download-retry (duration 00:00:05) [common]
122 11:49:07.116646 start: 1.5 download-retry (timeout 00:09:55) [common]
123 11:49:07.116735 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 11:49:07.116890 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:49:07.116964 saving as /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/modules/modules.tar
126 11:49:07.117026 total size: 8624756 (8 MB)
127 11:49:07.117119 Using unxz to decompress xz
128 11:49:07.121456 progress 0 % (0 MB)
129 11:49:07.142525 progress 5 % (0 MB)
130 11:49:07.166166 progress 10 % (0 MB)
131 11:49:07.189446 progress 15 % (1 MB)
132 11:49:07.212588 progress 20 % (1 MB)
133 11:49:07.236259 progress 25 % (2 MB)
134 11:49:07.261681 progress 30 % (2 MB)
135 11:49:07.287827 progress 35 % (2 MB)
136 11:49:07.311048 progress 40 % (3 MB)
137 11:49:07.335116 progress 45 % (3 MB)
138 11:49:07.360084 progress 50 % (4 MB)
139 11:49:07.384013 progress 55 % (4 MB)
140 11:49:07.408494 progress 60 % (4 MB)
141 11:49:07.435539 progress 65 % (5 MB)
142 11:49:07.460043 progress 70 % (5 MB)
143 11:49:07.483277 progress 75 % (6 MB)
144 11:49:07.510340 progress 80 % (6 MB)
145 11:49:07.536004 progress 85 % (7 MB)
146 11:49:07.560878 progress 90 % (7 MB)
147 11:49:07.592171 progress 95 % (7 MB)
148 11:49:07.619633 progress 100 % (8 MB)
149 11:49:07.624501 8 MB downloaded in 0.51 s (16.21 MB/s)
150 11:49:07.624763 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:49:07.625062 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:49:07.625171 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 11:49:07.625283 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 11:49:09.368812 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m
156 11:49:09.369009 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:49:09.369127 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 11:49:09.369311 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy
159 11:49:09.369463 makedir: /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin
160 11:49:09.369614 makedir: /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/tests
161 11:49:09.369734 makedir: /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/results
162 11:49:09.369853 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-add-keys
163 11:49:09.370048 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-add-sources
164 11:49:09.370227 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-background-process-start
165 11:49:09.370400 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-background-process-stop
166 11:49:09.370546 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-common-functions
167 11:49:09.370692 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-echo-ipv4
168 11:49:09.370841 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-install-packages
169 11:49:09.371014 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-installed-packages
170 11:49:09.371183 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-os-build
171 11:49:09.371330 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-probe-channel
172 11:49:09.371479 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-probe-ip
173 11:49:09.371651 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-target-ip
174 11:49:09.371824 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-target-mac
175 11:49:09.371995 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-target-storage
176 11:49:09.372158 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-case
177 11:49:09.372334 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-event
178 11:49:09.372502 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-feedback
179 11:49:09.372649 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-raise
180 11:49:09.372795 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-reference
181 11:49:09.372945 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-runner
182 11:49:09.373118 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-set
183 11:49:09.373265 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-test-shell
184 11:49:09.373412 Updating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-install-packages (oe)
185 11:49:09.373852 Updating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/bin/lava-installed-packages (oe)
186 11:49:09.374026 Creating /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/environment
187 11:49:09.374145 LAVA metadata
188 11:49:09.374226 - LAVA_JOB_ID=12074027
189 11:49:09.374306 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:49:09.374457 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 11:49:09.374557 skipped lava-vland-overlay
192 11:49:09.374657 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:49:09.374757 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 11:49:09.374853 skipped lava-multinode-overlay
195 11:49:09.374971 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:49:09.375093 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 11:49:09.375203 Loading test definitions
198 11:49:09.375341 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 11:49:09.375424 Using /lava-12074027 at stage 0
200 11:49:09.375845 uuid=12074027_1.6.2.3.1 testdef=None
201 11:49:09.375971 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:49:09.376100 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 11:49:09.376798 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:49:09.377161 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 11:49:09.377800 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:49:09.378058 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 11:49:09.378666 runner path: /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/0/tests/0_lc-compliance test_uuid 12074027_1.6.2.3.1
210 11:49:09.378837 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:49:09.379065 Creating lava-test-runner.conf files
213 11:49:09.379147 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074027/lava-overlay-bafip5hy/lava-12074027/0 for stage 0
214 11:49:09.379265 - 0_lc-compliance
215 11:49:09.379404 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:49:09.379529 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 11:49:09.385388 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:49:09.385499 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 11:49:09.385666 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:49:09.385769 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:49:09.385872 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 11:49:09.506814 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:49:09.507209 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 11:49:09.507348 extracting modules file /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m
225 11:49:09.729956 extracting modules file /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074027/extract-overlay-ramdisk-7anhqt45/ramdisk
226 11:49:09.962005 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:49:09.962175 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 11:49:09.962316 [common] Applying overlay to NFS
229 11:49:09.962402 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074027/compress-overlay-hquahjsr/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m
230 11:49:09.970452 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:49:09.970581 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 11:49:09.970684 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:49:09.970793 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 11:49:09.970882 Building ramdisk /var/lib/lava/dispatcher/tmp/12074027/extract-overlay-ramdisk-7anhqt45/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074027/extract-overlay-ramdisk-7anhqt45/ramdisk
235 11:49:10.306697 >> 119398 blocks
236 11:49:12.329379 rename /var/lib/lava/dispatcher/tmp/12074027/extract-overlay-ramdisk-7anhqt45/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/ramdisk/ramdisk.cpio.gz
237 11:49:12.329937 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:49:12.330118 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 11:49:12.330274 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 11:49:12.330444 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/kernel/Image'
241 11:49:24.959364 Returned 0 in 12 seconds
242 11:49:25.060008 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/kernel/image.itb
243 11:49:25.433257 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:49:25.433677 output: Created: Fri Nov 24 11:49:25 2023
245 11:49:25.433762 output: Image 0 (kernel-1)
246 11:49:25.433829 output: Description:
247 11:49:25.433906 output: Created: Fri Nov 24 11:49:25 2023
248 11:49:25.433975 output: Type: Kernel Image
249 11:49:25.434038 output: Compression: lzma compressed
250 11:49:25.434098 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
251 11:49:25.434179 output: Architecture: AArch64
252 11:49:25.434242 output: OS: Linux
253 11:49:25.434304 output: Load Address: 0x00000000
254 11:49:25.434366 output: Entry Point: 0x00000000
255 11:49:25.434446 output: Hash algo: crc32
256 11:49:25.434510 output: Hash value: 43cfb6ad
257 11:49:25.434571 output: Image 1 (fdt-1)
258 11:49:25.434628 output: Description: mt8192-asurada-spherion-r0
259 11:49:25.434700 output: Created: Fri Nov 24 11:49:25 2023
260 11:49:25.434756 output: Type: Flat Device Tree
261 11:49:25.434812 output: Compression: uncompressed
262 11:49:25.434866 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 11:49:25.434938 output: Architecture: AArch64
264 11:49:25.434995 output: Hash algo: crc32
265 11:49:25.435050 output: Hash value: cc4352de
266 11:49:25.435104 output: Image 2 (ramdisk-1)
267 11:49:25.435158 output: Description: unavailable
268 11:49:25.435231 output: Created: Fri Nov 24 11:49:25 2023
269 11:49:25.435286 output: Type: RAMDisk Image
270 11:49:25.435341 output: Compression: Unknown Compression
271 11:49:25.435410 output: Data Size: 17793440 Bytes = 17376.41 KiB = 16.97 MiB
272 11:49:25.435468 output: Architecture: AArch64
273 11:49:25.435523 output: OS: Linux
274 11:49:25.435577 output: Load Address: unavailable
275 11:49:25.435641 output: Entry Point: unavailable
276 11:49:25.435729 output: Hash algo: crc32
277 11:49:25.435812 output: Hash value: 4faa68c9
278 11:49:25.435904 output: Default Configuration: 'conf-1'
279 11:49:25.435990 output: Configuration 0 (conf-1)
280 11:49:25.436074 output: Description: mt8192-asurada-spherion-r0
281 11:49:25.436157 output: Kernel: kernel-1
282 11:49:25.436257 output: Init Ramdisk: ramdisk-1
283 11:49:25.436317 output: FDT: fdt-1
284 11:49:25.436372 output: Loadables: kernel-1
285 11:49:25.436441 output:
286 11:49:25.436661 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 11:49:25.436769 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 11:49:25.436888 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 11:49:25.437007 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 11:49:25.437095 No LXC device requested
291 11:49:25.437211 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:49:25.437334 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 11:49:25.437456 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:49:25.437558 Checking files for TFTP limit of 4294967296 bytes.
295 11:49:25.438112 end: 1 tftp-deploy (duration 00:00:24) [common]
296 11:49:25.438233 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:49:25.438333 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:49:25.438474 substitutions:
299 11:49:25.438546 - {DTB}: 12074027/tftp-deploy-7eni79v0/dtb/mt8192-asurada-spherion-r0.dtb
300 11:49:25.438612 - {INITRD}: 12074027/tftp-deploy-7eni79v0/ramdisk/ramdisk.cpio.gz
301 11:49:25.438693 - {KERNEL}: 12074027/tftp-deploy-7eni79v0/kernel/Image
302 11:49:25.438755 - {LAVA_MAC}: None
303 11:49:25.438814 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m
304 11:49:25.438872 - {NFS_SERVER_IP}: 192.168.201.1
305 11:49:25.438949 - {PRESEED_CONFIG}: None
306 11:49:25.439007 - {PRESEED_LOCAL}: None
307 11:49:25.439063 - {RAMDISK}: 12074027/tftp-deploy-7eni79v0/ramdisk/ramdisk.cpio.gz
308 11:49:25.439119 - {ROOT_PART}: None
309 11:49:25.439193 - {ROOT}: None
310 11:49:25.439251 - {SERVER_IP}: 192.168.201.1
311 11:49:25.439306 - {TEE}: None
312 11:49:25.439362 Parsed boot commands:
313 11:49:25.439424 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:49:25.439627 Parsed boot commands: tftpboot 192.168.201.1 12074027/tftp-deploy-7eni79v0/kernel/image.itb 12074027/tftp-deploy-7eni79v0/kernel/cmdline
315 11:49:25.439744 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:49:25.439862 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:49:25.439998 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:49:25.440120 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:49:25.440220 Not connected, no need to disconnect.
320 11:49:25.440328 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:49:25.440446 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:49:25.440545 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 11:49:25.444789 Setting prompt string to ['lava-test: # ']
324 11:49:25.445194 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:49:25.445309 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:49:25.445420 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:49:25.445550 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:49:25.445788 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
329 11:49:30.585118 >> Command sent successfully.
330 11:49:30.587623 Returned 0 in 5 seconds
331 11:49:30.688034 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 11:49:30.688362 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 11:49:30.688466 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 11:49:30.688559 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:49:30.688628 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:49:30.688697 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:49:30.689012 [Enter `^Ec?' for help]
339 11:49:30.861164
340 11:49:30.861309
341 11:49:30.861383 F0: 102B 0000
342 11:49:30.861451
343 11:49:30.861512 F3: 1001 0000 [0200]
344 11:49:30.861572
345 11:49:30.864984 F3: 1001 0000
346 11:49:30.865068
347 11:49:30.865135 F7: 102D 0000
348 11:49:30.865198
349 11:49:30.865257 F1: 0000 0000
350 11:49:30.868373
351 11:49:30.868488 V0: 0000 0000 [0001]
352 11:49:30.868590
353 11:49:30.868682 00: 0007 8000
354 11:49:30.868751
355 11:49:30.872101 01: 0000 0000
356 11:49:30.872220
357 11:49:30.872318 BP: 0C00 0209 [0000]
358 11:49:30.872412
359 11:49:30.876115 G0: 1182 0000
360 11:49:30.876234
361 11:49:30.876331 EC: 0000 0021 [4000]
362 11:49:30.876423
363 11:49:30.879342 S7: 0000 0000 [0000]
364 11:49:30.879442
365 11:49:30.879533 CC: 0000 0000 [0001]
366 11:49:30.879636
367 11:49:30.882542 T0: 0000 0040 [010F]
368 11:49:30.882647
369 11:49:30.882740 Jump to BL
370 11:49:30.882841
371 11:49:30.907930
372 11:49:30.908046
373 11:49:30.908141
374 11:49:30.915821 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 11:49:30.919596 ARM64: Exception handlers installed.
376 11:49:30.922745 ARM64: Testing exception
377 11:49:30.927239 ARM64: Done test exception
378 11:49:30.930916 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 11:49:30.941983 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 11:49:30.948658 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 11:49:30.958669 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 11:49:30.965102 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 11:49:30.975983 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 11:49:30.985817 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 11:49:30.992412 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 11:49:31.010698 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 11:49:31.013974 WDT: Last reset was cold boot
388 11:49:31.017354 SPI1(PAD0) initialized at 2873684 Hz
389 11:49:31.020632 SPI5(PAD0) initialized at 992727 Hz
390 11:49:31.024408 VBOOT: Loading verstage.
391 11:49:31.031029 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 11:49:31.034109 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 11:49:31.037750 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 11:49:31.040552 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 11:49:31.047981 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 11:49:31.054469 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 11:49:31.066071 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 11:49:31.066192
399 11:49:31.066291
400 11:49:31.076203 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 11:49:31.079616 ARM64: Exception handlers installed.
402 11:49:31.079725 ARM64: Testing exception
403 11:49:31.082986 ARM64: Done test exception
404 11:49:31.086481 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 11:49:31.093028 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 11:49:31.106531 Probing TPM: . done!
407 11:49:31.106619 TPM ready after 0 ms
408 11:49:31.113503 Connected to device vid:did:rid of 1ae0:0028:00
409 11:49:31.120331 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 11:49:31.180404 Initialized TPM device CR50 revision 0
411 11:49:31.191649 tlcl_send_startup: Startup return code is 0
412 11:49:31.191745 TPM: setup succeeded
413 11:49:31.203468 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 11:49:31.212217 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 11:49:31.224598 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 11:49:31.234215 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 11:49:31.238195 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 11:49:31.241443 in-header: 03 07 00 00 08 00 00 00
419 11:49:31.245361 in-data: aa e4 47 04 13 02 00 00
420 11:49:31.248546 Chrome EC: UHEPI supported
421 11:49:31.252471 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 11:49:31.256849 in-header: 03 95 00 00 08 00 00 00
423 11:49:31.260509 in-data: 18 20 20 08 00 00 00 00
424 11:49:31.260667 Phase 1
425 11:49:31.264352 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 11:49:31.272282 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 11:49:31.279334 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 11:49:31.279446 Recovery requested (1009000e)
429 11:49:31.290026 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:49:31.295526 tlcl_extend: response is 0
431 11:49:31.305164 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:49:31.310239 tlcl_extend: response is 0
433 11:49:31.317135 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:49:31.336849 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 11:49:31.344044 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:49:31.344153
437 11:49:31.344251
438 11:49:31.353725 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:49:31.357035 ARM64: Exception handlers installed.
440 11:49:31.360299 ARM64: Testing exception
441 11:49:31.360403 ARM64: Done test exception
442 11:49:31.383183 pmic_efuse_setting: Set efuses in 11 msecs
443 11:49:31.386120 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:49:31.393116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:49:31.396901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:49:31.400068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:49:31.407470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:49:31.410698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:49:31.414500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:49:31.421713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:49:31.425725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:49:31.429478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:49:31.436557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:49:31.440473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:49:31.444141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:49:31.447439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:49:31.454619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:49:31.462319 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:49:31.466227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:49:31.473893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:49:31.477084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:49:31.484721 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:49:31.488699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:49:31.495884 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:49:31.499605 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:49:31.506921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:49:31.510610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:49:31.514958 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:49:31.521954 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:49:31.529403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:49:31.533279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:49:31.536448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:49:31.540345 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:49:31.547776 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:49:31.551183 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:49:31.555105 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:49:31.562057 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:49:31.566110 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:49:31.573690 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:49:31.576724 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:49:31.580723 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:49:31.584770 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:49:31.591804 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:49:31.595975 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:49:31.599155 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:49:31.603074 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:49:31.606970 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:49:31.613822 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:49:31.617757 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:49:31.621505 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:49:31.625307 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:49:31.628896 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:49:31.632742 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:49:31.639753 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:49:31.647417 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 11:49:31.654684 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:49:31.657919 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:49:31.665918 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:49:31.676458 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:49:31.680907 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:49:31.684272 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:49:31.687639 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:49:31.696127 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 11:49:31.699757 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:49:31.707686 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 11:49:31.710955 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:49:31.720627 [RTC]rtc_get_frequency_meter,154: input=15, output=759
508 11:49:31.729775 [RTC]rtc_get_frequency_meter,154: input=23, output=942
509 11:49:31.739263 [RTC]rtc_get_frequency_meter,154: input=19, output=850
510 11:49:31.749038 [RTC]rtc_get_frequency_meter,154: input=17, output=806
511 11:49:31.758311 [RTC]rtc_get_frequency_meter,154: input=16, output=780
512 11:49:31.768024 [RTC]rtc_get_frequency_meter,154: input=16, output=780
513 11:49:31.777472 [RTC]rtc_get_frequency_meter,154: input=17, output=804
514 11:49:31.780513 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 11:49:31.788316 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
516 11:49:31.792388 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 11:49:31.796224 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 11:49:31.799523 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 11:49:31.803477 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 11:49:31.807321 ADC[4]: Raw value=905465 ID=7
521 11:49:31.807406 ADC[3]: Raw value=213441 ID=1
522 11:49:31.810962 RAM Code: 0x71
523 11:49:31.814554 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 11:49:31.818293 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 11:49:31.829224 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 11:49:31.837169 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 11:49:31.837256 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 11:49:31.840907 in-header: 03 07 00 00 08 00 00 00
529 11:49:31.844544 in-data: aa e4 47 04 13 02 00 00
530 11:49:31.848373 Chrome EC: UHEPI supported
531 11:49:31.855708 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 11:49:31.858868 in-header: 03 95 00 00 08 00 00 00
533 11:49:31.862695 in-data: 18 20 20 08 00 00 00 00
534 11:49:31.862805 MRC: failed to locate region type 0.
535 11:49:31.869921 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 11:49:31.873684 DRAM-K: Running full calibration
537 11:49:31.881465 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 11:49:31.881622 header.status = 0x0
539 11:49:31.885445 header.version = 0x6 (expected: 0x6)
540 11:49:31.888612 header.size = 0xd00 (expected: 0xd00)
541 11:49:31.892469 header.flags = 0x0
542 11:49:31.896109 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 11:49:31.915273 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 11:49:31.922800 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 11:49:31.922952 dram_init: ddr_geometry: 2
546 11:49:31.926464 [EMI] MDL number = 2
547 11:49:31.926572 [EMI] Get MDL freq = 0
548 11:49:31.930372 dram_init: ddr_type: 0
549 11:49:31.934338 is_discrete_lpddr4: 1
550 11:49:31.934447 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 11:49:31.934543
552 11:49:31.938280
553 11:49:31.938400 [Bian_co] ETT version 0.0.0.1
554 11:49:31.941462 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 11:49:31.941567
556 11:49:31.946037 dramc_set_vcore_voltage set vcore to 650000
557 11:49:31.949536 Read voltage for 800, 4
558 11:49:31.949660 Vio18 = 0
559 11:49:31.953343 Vcore = 650000
560 11:49:31.953459 Vdram = 0
561 11:49:31.953564 Vddq = 0
562 11:49:31.953692 Vmddr = 0
563 11:49:31.957312 dram_init: config_dvfs: 1
564 11:49:31.961196 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 11:49:31.968316 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 11:49:31.972276 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 11:49:31.976250 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 11:49:31.979276 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 11:49:31.982853 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 11:49:31.985809 MEM_TYPE=3, freq_sel=18
571 11:49:31.985918 sv_algorithm_assistance_LP4_1600
572 11:49:31.992888 ============ PULL DRAM RESETB DOWN ============
573 11:49:31.996855 ========== PULL DRAM RESETB DOWN end =========
574 11:49:31.999946 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 11:49:32.004053 ===================================
576 11:49:32.007616 LPDDR4 DRAM CONFIGURATION
577 11:49:32.011462 ===================================
578 11:49:32.011576 EX_ROW_EN[0] = 0x0
579 11:49:32.015492 EX_ROW_EN[1] = 0x0
580 11:49:32.015622 LP4Y_EN = 0x0
581 11:49:32.015717 WORK_FSP = 0x0
582 11:49:32.019042 WL = 0x2
583 11:49:32.021937 RL = 0x2
584 11:49:32.022015 BL = 0x2
585 11:49:32.025474 RPST = 0x0
586 11:49:32.025584 RD_PRE = 0x0
587 11:49:32.028907 WR_PRE = 0x1
588 11:49:32.029012 WR_PST = 0x0
589 11:49:32.032286 DBI_WR = 0x0
590 11:49:32.032391 DBI_RD = 0x0
591 11:49:32.035389 OTF = 0x1
592 11:49:32.039283 ===================================
593 11:49:32.039394 ===================================
594 11:49:32.042569 ANA top config
595 11:49:32.045876 ===================================
596 11:49:32.049784 DLL_ASYNC_EN = 0
597 11:49:32.049887 ALL_SLAVE_EN = 1
598 11:49:32.053067 NEW_RANK_MODE = 1
599 11:49:32.056043 DLL_IDLE_MODE = 1
600 11:49:32.059216 LP45_APHY_COMB_EN = 1
601 11:49:32.059326 TX_ODT_DIS = 1
602 11:49:32.063110 NEW_8X_MODE = 1
603 11:49:32.066362 ===================================
604 11:49:32.070312 ===================================
605 11:49:32.073391 data_rate = 1600
606 11:49:32.076560 CKR = 1
607 11:49:32.079851 DQ_P2S_RATIO = 8
608 11:49:32.083072 ===================================
609 11:49:32.083183 CA_P2S_RATIO = 8
610 11:49:32.086339 DQ_CA_OPEN = 0
611 11:49:32.090154 DQ_SEMI_OPEN = 0
612 11:49:32.093144 CA_SEMI_OPEN = 0
613 11:49:32.096239 CA_FULL_RATE = 0
614 11:49:32.100075 DQ_CKDIV4_EN = 1
615 11:49:32.100189 CA_CKDIV4_EN = 1
616 11:49:32.103358 CA_PREDIV_EN = 0
617 11:49:32.106645 PH8_DLY = 0
618 11:49:32.109842 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 11:49:32.113237 DQ_AAMCK_DIV = 4
620 11:49:32.116273 CA_AAMCK_DIV = 4
621 11:49:32.116376 CA_ADMCK_DIV = 4
622 11:49:32.120092 DQ_TRACK_CA_EN = 0
623 11:49:32.123255 CA_PICK = 800
624 11:49:32.126971 CA_MCKIO = 800
625 11:49:32.130931 MCKIO_SEMI = 0
626 11:49:32.131044 PLL_FREQ = 3068
627 11:49:32.134250 DQ_UI_PI_RATIO = 32
628 11:49:32.137466 CA_UI_PI_RATIO = 0
629 11:49:32.141207 ===================================
630 11:49:32.144840 ===================================
631 11:49:32.144941 memory_type:LPDDR4
632 11:49:32.148586 GP_NUM : 10
633 11:49:32.152072 SRAM_EN : 1
634 11:49:32.152191 MD32_EN : 0
635 11:49:32.155892 ===================================
636 11:49:32.159680 [ANA_INIT] >>>>>>>>>>>>>>
637 11:49:32.163358 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 11:49:32.163461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 11:49:32.167084 ===================================
640 11:49:32.170218 data_rate = 1600,PCW = 0X7600
641 11:49:32.173545 ===================================
642 11:49:32.176672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 11:49:32.183907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:49:32.186973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 11:49:32.193483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 11:49:32.197168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:49:32.200394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 11:49:32.203522 [ANA_INIT] flow start
649 11:49:32.203605 [ANA_INIT] PLL >>>>>>>>
650 11:49:32.207310 [ANA_INIT] PLL <<<<<<<<
651 11:49:32.210391 [ANA_INIT] MIDPI >>>>>>>>
652 11:49:32.210474 [ANA_INIT] MIDPI <<<<<<<<
653 11:49:32.213695 [ANA_INIT] DLL >>>>>>>>
654 11:49:32.216916 [ANA_INIT] flow end
655 11:49:32.220108 ============ LP4 DIFF to SE enter ============
656 11:49:32.223442 ============ LP4 DIFF to SE exit ============
657 11:49:32.227002 [ANA_INIT] <<<<<<<<<<<<<
658 11:49:32.230279 [Flow] Enable top DCM control >>>>>
659 11:49:32.233837 [Flow] Enable top DCM control <<<<<
660 11:49:32.237235 Enable DLL master slave shuffle
661 11:49:32.240398 ==============================================================
662 11:49:32.243644 Gating Mode config
663 11:49:32.247546 ==============================================================
664 11:49:32.250650 Config description:
665 11:49:32.260449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 11:49:32.267617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 11:49:32.270647 SELPH_MODE 0: By rank 1: By Phase
668 11:49:32.276984 ==============================================================
669 11:49:32.280819 GAT_TRACK_EN = 1
670 11:49:32.283651 RX_GATING_MODE = 2
671 11:49:32.287268 RX_GATING_TRACK_MODE = 2
672 11:49:32.287352 SELPH_MODE = 1
673 11:49:32.290749 PICG_EARLY_EN = 1
674 11:49:32.293991 VALID_LAT_VALUE = 1
675 11:49:32.300559 ==============================================================
676 11:49:32.303701 Enter into Gating configuration >>>>
677 11:49:32.307437 Exit from Gating configuration <<<<
678 11:49:32.310629 Enter into DVFS_PRE_config >>>>>
679 11:49:32.320879 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 11:49:32.323818 Exit from DVFS_PRE_config <<<<<
681 11:49:32.327728 Enter into PICG configuration >>>>
682 11:49:32.330901 Exit from PICG configuration <<<<
683 11:49:32.334075 [RX_INPUT] configuration >>>>>
684 11:49:32.337268 [RX_INPUT] configuration <<<<<
685 11:49:32.340975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 11:49:32.347549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 11:49:32.354331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 11:49:32.360874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 11:49:32.364220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 11:49:32.370726 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 11:49:32.374222 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 11:49:32.380763 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 11:49:32.384836 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 11:49:32.387563 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 11:49:32.391188 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 11:49:32.397745 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:49:32.400981 ===================================
698 11:49:32.401062 LPDDR4 DRAM CONFIGURATION
699 11:49:32.404722 ===================================
700 11:49:32.407672 EX_ROW_EN[0] = 0x0
701 11:49:32.407753 EX_ROW_EN[1] = 0x0
702 11:49:32.410809 LP4Y_EN = 0x0
703 11:49:32.410889 WORK_FSP = 0x0
704 11:49:32.414562 WL = 0x2
705 11:49:32.417844 RL = 0x2
706 11:49:32.417925 BL = 0x2
707 11:49:32.421484 RPST = 0x0
708 11:49:32.421560 RD_PRE = 0x0
709 11:49:32.424730 WR_PRE = 0x1
710 11:49:32.424801 WR_PST = 0x0
711 11:49:32.427587 DBI_WR = 0x0
712 11:49:32.427662 DBI_RD = 0x0
713 11:49:32.430966 OTF = 0x1
714 11:49:32.434256 ===================================
715 11:49:32.438156 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 11:49:32.441409 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 11:49:32.444420 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 11:49:32.448258 ===================================
719 11:49:32.450871 LPDDR4 DRAM CONFIGURATION
720 11:49:32.454743 ===================================
721 11:49:32.458043 EX_ROW_EN[0] = 0x10
722 11:49:32.458171 EX_ROW_EN[1] = 0x0
723 11:49:32.461188 LP4Y_EN = 0x0
724 11:49:32.461287 WORK_FSP = 0x0
725 11:49:32.464573 WL = 0x2
726 11:49:32.464673 RL = 0x2
727 11:49:32.467778 BL = 0x2
728 11:49:32.467869 RPST = 0x0
729 11:49:32.471644 RD_PRE = 0x0
730 11:49:32.471733 WR_PRE = 0x1
731 11:49:32.474722 WR_PST = 0x0
732 11:49:32.474817 DBI_WR = 0x0
733 11:49:32.477876 DBI_RD = 0x0
734 11:49:32.481101 OTF = 0x1
735 11:49:32.481180 ===================================
736 11:49:32.488049 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 11:49:32.492947 nWR fixed to 40
738 11:49:32.496342 [ModeRegInit_LP4] CH0 RK0
739 11:49:32.496444 [ModeRegInit_LP4] CH0 RK1
740 11:49:32.499550 [ModeRegInit_LP4] CH1 RK0
741 11:49:32.502742 [ModeRegInit_LP4] CH1 RK1
742 11:49:32.502828 match AC timing 13
743 11:49:32.509274 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 11:49:32.512535 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 11:49:32.515990 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 11:49:32.522889 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 11:49:32.526576 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 11:49:32.526660 [EMI DOE] emi_dcm 0
749 11:49:32.532812 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 11:49:32.532932 ==
751 11:49:32.536457 Dram Type= 6, Freq= 0, CH_0, rank 0
752 11:49:32.539598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 11:49:32.539717 ==
754 11:49:32.546593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 11:49:32.549988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 11:49:32.560327 [CA 0] Center 36 (6~67) winsize 62
757 11:49:32.563756 [CA 1] Center 36 (6~67) winsize 62
758 11:49:32.566941 [CA 2] Center 34 (4~65) winsize 62
759 11:49:32.570407 [CA 3] Center 34 (4~64) winsize 61
760 11:49:32.573206 [CA 4] Center 33 (2~64) winsize 63
761 11:49:32.576936 [CA 5] Center 32 (2~62) winsize 61
762 11:49:32.577046
763 11:49:32.580439 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 11:49:32.580524
765 11:49:32.583652 [CATrainingPosCal] consider 1 rank data
766 11:49:32.586870 u2DelayCellTimex100 = 270/100 ps
767 11:49:32.590092 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 11:49:32.593315 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 11:49:32.600002 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 11:49:32.603308 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
771 11:49:32.606657 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
772 11:49:32.610096 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
773 11:49:32.610180
774 11:49:32.613452 CA PerBit enable=1, Macro0, CA PI delay=32
775 11:49:32.613598
776 11:49:32.616603 [CBTSetCACLKResult] CA Dly = 32
777 11:49:32.616682 CS Dly: 4 (0~35)
778 11:49:32.619776 ==
779 11:49:32.623481 Dram Type= 6, Freq= 0, CH_0, rank 1
780 11:49:32.626604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 11:49:32.626705 ==
782 11:49:32.630092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 11:49:32.636466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 11:49:32.646552 [CA 0] Center 36 (6~67) winsize 62
785 11:49:32.649560 [CA 1] Center 36 (6~67) winsize 62
786 11:49:32.653136 [CA 2] Center 34 (4~65) winsize 62
787 11:49:32.656759 [CA 3] Center 33 (3~64) winsize 62
788 11:49:32.659865 [CA 4] Center 32 (2~63) winsize 62
789 11:49:32.663267 [CA 5] Center 32 (2~63) winsize 62
790 11:49:32.663386
791 11:49:32.666371 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 11:49:32.666476
793 11:49:32.669927 [CATrainingPosCal] consider 2 rank data
794 11:49:32.673156 u2DelayCellTimex100 = 270/100 ps
795 11:49:32.676546 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 11:49:32.680012 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 11:49:32.683244 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 11:49:32.689931 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
799 11:49:32.693362 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
800 11:49:32.696452 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
801 11:49:32.696572
802 11:49:32.700174 CA PerBit enable=1, Macro0, CA PI delay=32
803 11:49:32.700270
804 11:49:32.703545 [CBTSetCACLKResult] CA Dly = 32
805 11:49:32.703633 CS Dly: 4 (0~36)
806 11:49:32.703724
807 11:49:32.707552 ----->DramcWriteLeveling(PI) begin...
808 11:49:32.707637 ==
809 11:49:32.710897 Dram Type= 6, Freq= 0, CH_0, rank 0
810 11:49:32.714452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:49:32.714556 ==
812 11:49:32.718445 Write leveling (Byte 0): 32 => 32
813 11:49:32.721083 Write leveling (Byte 1): 30 => 30
814 11:49:32.724581 DramcWriteLeveling(PI) end<-----
815 11:49:32.724666
816 11:49:32.724754 ==
817 11:49:32.727949 Dram Type= 6, Freq= 0, CH_0, rank 0
818 11:49:32.731024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 11:49:32.734922 ==
820 11:49:32.735004 [Gating] SW mode calibration
821 11:49:32.741620 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 11:49:32.748350 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 11:49:32.751689 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:49:32.755371 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 11:49:32.762067 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
826 11:49:32.765279 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:49:32.768514 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:49:32.775477 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:49:32.778637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:49:32.782200 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:49:32.788752 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:49:32.791976 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:49:32.795360 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:49:32.801960 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:49:32.805697 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:49:32.808754 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:49:32.815586 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:49:32.818790 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:49:32.822166 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:49:32.825333 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 11:49:32.832339 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 11:49:32.835453 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:49:32.839081 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:49:32.846016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:49:32.849220 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:49:32.852055 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:49:32.858922 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:49:32.862595 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:49:32.865727 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
850 11:49:32.872377 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
851 11:49:32.875695 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:49:32.878790 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:49:32.885444 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:49:32.888800 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:49:32.892239 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 11:49:32.895933 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
857 11:49:32.902184 0 10 8 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 0)
858 11:49:32.906137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:49:32.908698 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:49:32.915746 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:49:32.919084 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:49:32.922400 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:49:32.929281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:49:32.932580 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
865 11:49:32.935795 0 11 8 | B1->B0 | 2727 4343 | 1 0 | (0 0) (0 0)
866 11:49:32.942459 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
867 11:49:32.946086 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:49:32.949383 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:49:32.956076 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:49:32.959305 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:49:32.962985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:49:32.965958 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 11:49:32.972684 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 11:49:32.975926 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 11:49:32.979356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:49:32.986269 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:49:32.989375 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:49:32.993069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:49:32.999686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:49:33.003338 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:49:33.006327 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:49:33.013078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:49:33.016466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:49:33.019652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:49:33.026338 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:49:33.029725 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:49:33.032882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:49:33.036216 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 11:49:33.043110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
890 11:49:33.046321 Total UI for P1: 0, mck2ui 16
891 11:49:33.050245 best dqsien dly found for B0: ( 0, 14, 4)
892 11:49:33.053537 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:49:33.056799 Total UI for P1: 0, mck2ui 16
894 11:49:33.060192 best dqsien dly found for B1: ( 0, 14, 10)
895 11:49:33.063499 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
896 11:49:33.066971 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 11:49:33.067049
898 11:49:33.070584 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
899 11:49:33.073863 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 11:49:33.077084 [Gating] SW calibration Done
901 11:49:33.077164 ==
902 11:49:33.080376 Dram Type= 6, Freq= 0, CH_0, rank 0
903 11:49:33.083947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 11:49:33.084030 ==
905 11:49:33.086919 RX Vref Scan: 0
906 11:49:33.087028
907 11:49:33.090544 RX Vref 0 -> 0, step: 1
908 11:49:33.090620
909 11:49:33.090708 RX Delay -130 -> 252, step: 16
910 11:49:33.097193 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
911 11:49:33.100864 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
912 11:49:33.104352 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
913 11:49:33.107635 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
914 11:49:33.110728 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
915 11:49:33.114560 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
916 11:49:33.120654 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
917 11:49:33.123906 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
918 11:49:33.127666 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
919 11:49:33.130856 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
920 11:49:33.134043 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
921 11:49:33.140690 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
922 11:49:33.144611 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
923 11:49:33.147318 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
924 11:49:33.150708 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
925 11:49:33.154187 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
926 11:49:33.157435 ==
927 11:49:33.160776 Dram Type= 6, Freq= 0, CH_0, rank 0
928 11:49:33.164838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 11:49:33.164926 ==
930 11:49:33.165015 DQS Delay:
931 11:49:33.167730 DQS0 = 0, DQS1 = 0
932 11:49:33.167826 DQM Delay:
933 11:49:33.170874 DQM0 = 88, DQM1 = 81
934 11:49:33.170962 DQ Delay:
935 11:49:33.174722 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
936 11:49:33.178275 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
937 11:49:33.181211 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
938 11:49:33.184686 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
939 11:49:33.184808
940 11:49:33.184917
941 11:49:33.185011 ==
942 11:49:33.188347 Dram Type= 6, Freq= 0, CH_0, rank 0
943 11:49:33.191289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 11:49:33.191409 ==
945 11:49:33.191518
946 11:49:33.191623
947 11:49:33.194625 TX Vref Scan disable
948 11:49:33.197906 == TX Byte 0 ==
949 11:49:33.201758 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 11:49:33.204559 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 11:49:33.207805 == TX Byte 1 ==
952 11:49:33.210908 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
953 11:49:33.214656 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
954 11:49:33.214763 ==
955 11:49:33.218054 Dram Type= 6, Freq= 0, CH_0, rank 0
956 11:49:33.221383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 11:49:33.221464 ==
958 11:49:33.235620 TX Vref=22, minBit 10, minWin=27, winSum=450
959 11:49:33.239089 TX Vref=24, minBit 9, minWin=27, winSum=453
960 11:49:33.242157 TX Vref=26, minBit 9, minWin=27, winSum=451
961 11:49:33.245295 TX Vref=28, minBit 0, minWin=28, winSum=457
962 11:49:33.249077 TX Vref=30, minBit 8, minWin=28, winSum=458
963 11:49:33.252468 TX Vref=32, minBit 8, minWin=28, winSum=457
964 11:49:33.258912 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
965 11:49:33.259003
966 11:49:33.262245 Final TX Range 1 Vref 30
967 11:49:33.262324
968 11:49:33.262401 ==
969 11:49:33.265658 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:49:33.269039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:49:33.269148 ==
972 11:49:33.269254
973 11:49:33.272316
974 11:49:33.272411 TX Vref Scan disable
975 11:49:33.275734 == TX Byte 0 ==
976 11:49:33.279063 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 11:49:33.282123 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 11:49:33.285408 == TX Byte 1 ==
979 11:49:33.289119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 11:49:33.292553 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 11:49:33.295670
982 11:49:33.295756 [DATLAT]
983 11:49:33.295824 Freq=800, CH0 RK0
984 11:49:33.295888
985 11:49:33.298805 DATLAT Default: 0xa
986 11:49:33.298891 0, 0xFFFF, sum = 0
987 11:49:33.302077 1, 0xFFFF, sum = 0
988 11:49:33.302168 2, 0xFFFF, sum = 0
989 11:49:33.305244 3, 0xFFFF, sum = 0
990 11:49:33.305330 4, 0xFFFF, sum = 0
991 11:49:33.309154 5, 0xFFFF, sum = 0
992 11:49:33.312534 6, 0xFFFF, sum = 0
993 11:49:33.312621 7, 0xFFFF, sum = 0
994 11:49:33.315609 8, 0xFFFF, sum = 0
995 11:49:33.315697 9, 0x0, sum = 1
996 11:49:33.315766 10, 0x0, sum = 2
997 11:49:33.318908 11, 0x0, sum = 3
998 11:49:33.319018 12, 0x0, sum = 4
999 11:49:33.322248 best_step = 10
1000 11:49:33.322333
1001 11:49:33.322410 ==
1002 11:49:33.325466 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 11:49:33.329122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 11:49:33.329206 ==
1005 11:49:33.332241 RX Vref Scan: 1
1006 11:49:33.332348
1007 11:49:33.332460 Set Vref Range= 32 -> 127
1008 11:49:33.332564
1009 11:49:33.335853 RX Vref 32 -> 127, step: 1
1010 11:49:33.335938
1011 11:49:33.339125 RX Delay -95 -> 252, step: 8
1012 11:49:33.339240
1013 11:49:33.342300 Set Vref, RX VrefLevel [Byte0]: 32
1014 11:49:33.345825 [Byte1]: 32
1015 11:49:33.345915
1016 11:49:33.349356 Set Vref, RX VrefLevel [Byte0]: 33
1017 11:49:33.352184 [Byte1]: 33
1018 11:49:33.356212
1019 11:49:33.356300 Set Vref, RX VrefLevel [Byte0]: 34
1020 11:49:33.358859 [Byte1]: 34
1021 11:49:33.363366
1022 11:49:33.363481 Set Vref, RX VrefLevel [Byte0]: 35
1023 11:49:33.367036 [Byte1]: 35
1024 11:49:33.371886
1025 11:49:33.371987 Set Vref, RX VrefLevel [Byte0]: 36
1026 11:49:33.375077 [Byte1]: 36
1027 11:49:33.378904
1028 11:49:33.378994 Set Vref, RX VrefLevel [Byte0]: 37
1029 11:49:33.382795 [Byte1]: 37
1030 11:49:33.386234
1031 11:49:33.386319 Set Vref, RX VrefLevel [Byte0]: 38
1032 11:49:33.389827 [Byte1]: 38
1033 11:49:33.394753
1034 11:49:33.394864 Set Vref, RX VrefLevel [Byte0]: 39
1035 11:49:33.397293 [Byte1]: 39
1036 11:49:33.401777
1037 11:49:33.401860 Set Vref, RX VrefLevel [Byte0]: 40
1038 11:49:33.404964 [Byte1]: 40
1039 11:49:33.408905
1040 11:49:33.409000 Set Vref, RX VrefLevel [Byte0]: 41
1041 11:49:33.412871 [Byte1]: 41
1042 11:49:33.416536
1043 11:49:33.416624 Set Vref, RX VrefLevel [Byte0]: 42
1044 11:49:33.419741 [Byte1]: 42
1045 11:49:33.424075
1046 11:49:33.424154 Set Vref, RX VrefLevel [Byte0]: 43
1047 11:49:33.427255 [Byte1]: 43
1048 11:49:33.431753
1049 11:49:33.431863 Set Vref, RX VrefLevel [Byte0]: 44
1050 11:49:33.434938 [Byte1]: 44
1051 11:49:33.439447
1052 11:49:33.439528 Set Vref, RX VrefLevel [Byte0]: 45
1053 11:49:33.443113 [Byte1]: 45
1054 11:49:33.446829
1055 11:49:33.446919 Set Vref, RX VrefLevel [Byte0]: 46
1056 11:49:33.450184 [Byte1]: 46
1057 11:49:33.454700
1058 11:49:33.454786 Set Vref, RX VrefLevel [Byte0]: 47
1059 11:49:33.458061 [Byte1]: 47
1060 11:49:33.462652
1061 11:49:33.462757 Set Vref, RX VrefLevel [Byte0]: 48
1062 11:49:33.465733 [Byte1]: 48
1063 11:49:33.469955
1064 11:49:33.470047 Set Vref, RX VrefLevel [Byte0]: 49
1065 11:49:33.473333 [Byte1]: 49
1066 11:49:33.477337
1067 11:49:33.477460 Set Vref, RX VrefLevel [Byte0]: 50
1068 11:49:33.480666 [Byte1]: 50
1069 11:49:33.484701
1070 11:49:33.484790 Set Vref, RX VrefLevel [Byte0]: 51
1071 11:49:33.488151 [Byte1]: 51
1072 11:49:33.492785
1073 11:49:33.492890 Set Vref, RX VrefLevel [Byte0]: 52
1074 11:49:33.495956 [Byte1]: 52
1075 11:49:33.500255
1076 11:49:33.500345 Set Vref, RX VrefLevel [Byte0]: 53
1077 11:49:33.503433 [Byte1]: 53
1078 11:49:33.508077
1079 11:49:33.508161 Set Vref, RX VrefLevel [Byte0]: 54
1080 11:49:33.511261 [Byte1]: 54
1081 11:49:33.515338
1082 11:49:33.515423 Set Vref, RX VrefLevel [Byte0]: 55
1083 11:49:33.518655 [Byte1]: 55
1084 11:49:33.523072
1085 11:49:33.523164 Set Vref, RX VrefLevel [Byte0]: 56
1086 11:49:33.526304 [Byte1]: 56
1087 11:49:33.530666
1088 11:49:33.530789 Set Vref, RX VrefLevel [Byte0]: 57
1089 11:49:33.533623 [Byte1]: 57
1090 11:49:33.538129
1091 11:49:33.538236 Set Vref, RX VrefLevel [Byte0]: 58
1092 11:49:33.541313 [Byte1]: 58
1093 11:49:33.545699
1094 11:49:33.545786 Set Vref, RX VrefLevel [Byte0]: 59
1095 11:49:33.548861 [Byte1]: 59
1096 11:49:33.553284
1097 11:49:33.553390 Set Vref, RX VrefLevel [Byte0]: 60
1098 11:49:33.556577 [Byte1]: 60
1099 11:49:33.561242
1100 11:49:33.561320 Set Vref, RX VrefLevel [Byte0]: 61
1101 11:49:33.564332 [Byte1]: 61
1102 11:49:33.569101
1103 11:49:33.569177 Set Vref, RX VrefLevel [Byte0]: 62
1104 11:49:33.572342 [Byte1]: 62
1105 11:49:33.576166
1106 11:49:33.576264 Set Vref, RX VrefLevel [Byte0]: 63
1107 11:49:33.579551 [Byte1]: 63
1108 11:49:33.583739
1109 11:49:33.583822 Set Vref, RX VrefLevel [Byte0]: 64
1110 11:49:33.586928 [Byte1]: 64
1111 11:49:33.591568
1112 11:49:33.591658 Set Vref, RX VrefLevel [Byte0]: 65
1113 11:49:33.594757 [Byte1]: 65
1114 11:49:33.598917
1115 11:49:33.598995 Set Vref, RX VrefLevel [Byte0]: 66
1116 11:49:33.602160 [Byte1]: 66
1117 11:49:33.606912
1118 11:49:33.607000 Set Vref, RX VrefLevel [Byte0]: 67
1119 11:49:33.610111 [Byte1]: 67
1120 11:49:33.614116
1121 11:49:33.614192 Set Vref, RX VrefLevel [Byte0]: 68
1122 11:49:33.617439 [Byte1]: 68
1123 11:49:33.621999
1124 11:49:33.622078 Set Vref, RX VrefLevel [Byte0]: 69
1125 11:49:33.625253 [Byte1]: 69
1126 11:49:33.629127
1127 11:49:33.629208 Set Vref, RX VrefLevel [Byte0]: 70
1128 11:49:33.632402 [Byte1]: 70
1129 11:49:33.637080
1130 11:49:33.637193 Set Vref, RX VrefLevel [Byte0]: 71
1131 11:49:33.640172 [Byte1]: 71
1132 11:49:33.645023
1133 11:49:33.645101 Set Vref, RX VrefLevel [Byte0]: 72
1134 11:49:33.647645 [Byte1]: 72
1135 11:49:33.652104
1136 11:49:33.652177 Set Vref, RX VrefLevel [Byte0]: 73
1137 11:49:33.655405 [Byte1]: 73
1138 11:49:33.659677
1139 11:49:33.659766 Set Vref, RX VrefLevel [Byte0]: 74
1140 11:49:33.663070 [Byte1]: 74
1141 11:49:33.667181
1142 11:49:33.667263 Set Vref, RX VrefLevel [Byte0]: 75
1143 11:49:33.670827 [Byte1]: 75
1144 11:49:33.675485
1145 11:49:33.675602 Set Vref, RX VrefLevel [Byte0]: 76
1146 11:49:33.678081 [Byte1]: 76
1147 11:49:33.682606
1148 11:49:33.682696 Set Vref, RX VrefLevel [Byte0]: 77
1149 11:49:33.685845 [Byte1]: 77
1150 11:49:33.690295
1151 11:49:33.690380 Set Vref, RX VrefLevel [Byte0]: 78
1152 11:49:33.693681 [Byte1]: 78
1153 11:49:33.698292
1154 11:49:33.698383 Set Vref, RX VrefLevel [Byte0]: 79
1155 11:49:33.700892 [Byte1]: 79
1156 11:49:33.705552
1157 11:49:33.705648 Final RX Vref Byte 0 = 57 to rank0
1158 11:49:33.708916 Final RX Vref Byte 1 = 61 to rank0
1159 11:49:33.712041 Final RX Vref Byte 0 = 57 to rank1
1160 11:49:33.715671 Final RX Vref Byte 1 = 61 to rank1==
1161 11:49:33.718709 Dram Type= 6, Freq= 0, CH_0, rank 0
1162 11:49:33.725436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 11:49:33.725559 ==
1164 11:49:33.725684 DQS Delay:
1165 11:49:33.725753 DQS0 = 0, DQS1 = 0
1166 11:49:33.728421 DQM Delay:
1167 11:49:33.728505 DQM0 = 92, DQM1 = 85
1168 11:49:33.732315 DQ Delay:
1169 11:49:33.735542 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1170 11:49:33.735661 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1171 11:49:33.738913 DQ8 =76, DQ9 =80, DQ10 =84, DQ11 =76
1172 11:49:33.745521 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1173 11:49:33.745643
1174 11:49:33.745711
1175 11:49:33.752054 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1176 11:49:33.755738 CH0 RK0: MR19=606, MR18=493F
1177 11:49:33.762144 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1178 11:49:33.762232
1179 11:49:33.765916 ----->DramcWriteLeveling(PI) begin...
1180 11:49:33.766001 ==
1181 11:49:33.769162 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 11:49:33.772446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 11:49:33.772557 ==
1184 11:49:33.775573 Write leveling (Byte 0): 33 => 33
1185 11:49:33.778948 Write leveling (Byte 1): 30 => 30
1186 11:49:33.782402 DramcWriteLeveling(PI) end<-----
1187 11:49:33.782487
1188 11:49:33.782553 ==
1189 11:49:33.826406 Dram Type= 6, Freq= 0, CH_0, rank 1
1190 11:49:33.826506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 11:49:33.826764 ==
1192 11:49:33.826833 [Gating] SW mode calibration
1193 11:49:33.826895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1194 11:49:33.826955 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1195 11:49:33.827026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1196 11:49:33.827086 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1197 11:49:33.827144 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1198 11:49:33.827200 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1199 11:49:33.827792 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:49:33.840478 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:49:33.840784 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:49:33.843394 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:49:33.843478 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:49:33.846779 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:49:33.853820 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:49:33.856909 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:49:33.860500 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:49:33.867333 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:49:33.870655 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:49:33.873832 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:49:33.880080 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:49:33.883478 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1213 11:49:33.886815 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1214 11:49:33.893440 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:49:33.897329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:49:33.900584 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:49:33.907206 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:49:33.910469 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:49:33.913626 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:49:33.917053 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:49:33.924047 0 9 8 | B1->B0 | 2d2d 2828 | 0 1 | (0 0) (1 1)
1222 11:49:33.927435 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 11:49:33.930553 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 11:49:33.937017 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 11:49:33.940708 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 11:49:33.943861 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 11:49:33.950904 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 11:49:33.954802 0 10 4 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
1229 11:49:33.958505 0 10 8 | B1->B0 | 2525 2727 | 0 0 | (1 0) (0 1)
1230 11:49:33.961978 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:49:33.965633 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:49:33.972098 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:49:33.975492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:49:33.979814 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:49:33.983442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:49:33.989870 0 11 4 | B1->B0 | 2626 2524 | 0 1 | (0 0) (0 0)
1237 11:49:33.993821 0 11 8 | B1->B0 | 3e3e 3c3c | 0 0 | (0 0) (0 0)
1238 11:49:33.997025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 11:49:34.003382 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 11:49:34.007040 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 11:49:34.010313 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 11:49:34.017110 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 11:49:34.020422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 11:49:34.023691 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 11:49:34.030261 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1246 11:49:34.033621 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 11:49:34.037018 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 11:49:34.040322 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:49:34.046734 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:49:34.049875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 11:49:34.053274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 11:49:34.060145 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 11:49:34.063465 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 11:49:34.066555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 11:49:34.073511 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 11:49:34.076483 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 11:49:34.080577 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 11:49:34.087131 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 11:49:34.090082 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:49:34.093309 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:49:34.099913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1262 11:49:34.103408 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:49:34.106990 Total UI for P1: 0, mck2ui 16
1264 11:49:34.110423 best dqsien dly found for B0: ( 0, 14, 8)
1265 11:49:34.113357 Total UI for P1: 0, mck2ui 16
1266 11:49:34.116819 best dqsien dly found for B1: ( 0, 14, 8)
1267 11:49:34.120141 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1268 11:49:34.123296 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1269 11:49:34.123374
1270 11:49:34.126527 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1271 11:49:34.130391 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1272 11:49:34.133586 [Gating] SW calibration Done
1273 11:49:34.133660 ==
1274 11:49:34.136854 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:49:34.140186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:49:34.140263 ==
1277 11:49:34.143396 RX Vref Scan: 0
1278 11:49:34.143476
1279 11:49:34.146582 RX Vref 0 -> 0, step: 1
1280 11:49:34.146655
1281 11:49:34.146717 RX Delay -130 -> 252, step: 16
1282 11:49:34.153456 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1283 11:49:34.156679 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1284 11:49:34.159918 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1285 11:49:34.163190 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1286 11:49:34.166446 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1287 11:49:34.173467 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1288 11:49:34.176802 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1289 11:49:34.180033 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1290 11:49:34.183221 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1291 11:49:34.186702 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1292 11:49:34.193246 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1293 11:49:34.196425 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1294 11:49:34.200072 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1295 11:49:34.203177 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1296 11:49:34.206536 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1297 11:49:34.213361 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1298 11:49:34.213436 ==
1299 11:49:34.217101 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:49:34.219828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:49:34.219904 ==
1302 11:49:34.219974 DQS Delay:
1303 11:49:34.223437 DQS0 = 0, DQS1 = 0
1304 11:49:34.223513 DQM Delay:
1305 11:49:34.226907 DQM0 = 91, DQM1 = 83
1306 11:49:34.226987 DQ Delay:
1307 11:49:34.230352 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1308 11:49:34.233256 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1309 11:49:34.237074 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1310 11:49:34.240351 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1311 11:49:34.240423
1312 11:49:34.240484
1313 11:49:34.240541 ==
1314 11:49:34.243551 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 11:49:34.246750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 11:49:34.246823 ==
1317 11:49:34.246884
1318 11:49:34.250142
1319 11:49:34.250265 TX Vref Scan disable
1320 11:49:34.253656 == TX Byte 0 ==
1321 11:49:34.256840 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1322 11:49:34.260132 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1323 11:49:34.263611 == TX Byte 1 ==
1324 11:49:34.267443 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1325 11:49:34.270628 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1326 11:49:34.270711 ==
1327 11:49:34.273623 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:49:34.280376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:49:34.280455 ==
1330 11:49:34.292522 TX Vref=22, minBit 8, minWin=27, winSum=447
1331 11:49:34.295771 TX Vref=24, minBit 3, minWin=28, winSum=453
1332 11:49:34.299095 TX Vref=26, minBit 11, minWin=27, winSum=457
1333 11:49:34.302417 TX Vref=28, minBit 1, minWin=28, winSum=454
1334 11:49:34.305477 TX Vref=30, minBit 4, minWin=28, winSum=456
1335 11:49:34.309126 TX Vref=32, minBit 4, minWin=28, winSum=454
1336 11:49:34.315479 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 30
1337 11:49:34.315563
1338 11:49:34.318884 Final TX Range 1 Vref 30
1339 11:49:34.318967
1340 11:49:34.319031 ==
1341 11:49:34.322612 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 11:49:34.326087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 11:49:34.326202 ==
1344 11:49:34.326280
1345 11:49:34.328761
1346 11:49:34.328851 TX Vref Scan disable
1347 11:49:34.332298 == TX Byte 0 ==
1348 11:49:34.335974 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1349 11:49:34.342230 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1350 11:49:34.342342 == TX Byte 1 ==
1351 11:49:34.345754 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1352 11:49:34.352360 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1353 11:49:34.352505
1354 11:49:34.352615 [DATLAT]
1355 11:49:34.352705 Freq=800, CH0 RK1
1356 11:49:34.352826
1357 11:49:34.355741 DATLAT Default: 0xa
1358 11:49:34.355837 0, 0xFFFF, sum = 0
1359 11:49:34.358921 1, 0xFFFF, sum = 0
1360 11:49:34.359052 2, 0xFFFF, sum = 0
1361 11:49:34.362732 3, 0xFFFF, sum = 0
1362 11:49:34.362868 4, 0xFFFF, sum = 0
1363 11:49:34.366028 5, 0xFFFF, sum = 0
1364 11:49:34.369226 6, 0xFFFF, sum = 0
1365 11:49:34.369304 7, 0xFFFF, sum = 0
1366 11:49:34.372477 8, 0xFFFF, sum = 0
1367 11:49:34.372554 9, 0x0, sum = 1
1368 11:49:34.372641 10, 0x0, sum = 2
1369 11:49:34.375948 11, 0x0, sum = 3
1370 11:49:34.376076 12, 0x0, sum = 4
1371 11:49:34.378792 best_step = 10
1372 11:49:34.378869
1373 11:49:34.378933 ==
1374 11:49:34.382186 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 11:49:34.385583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 11:49:34.385662 ==
1377 11:49:34.389335 RX Vref Scan: 0
1378 11:49:34.389417
1379 11:49:34.389518 RX Vref 0 -> 0, step: 1
1380 11:49:34.389618
1381 11:49:34.392051 RX Delay -79 -> 252, step: 8
1382 11:49:34.398857 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1383 11:49:34.402350 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1384 11:49:34.405615 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1385 11:49:34.408926 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1386 11:49:34.412262 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1387 11:49:34.419181 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1388 11:49:34.422404 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1389 11:49:34.425871 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1390 11:49:34.428998 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1391 11:49:34.432780 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1392 11:49:34.439514 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1393 11:49:34.442642 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1394 11:49:34.445786 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1395 11:49:34.449444 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1396 11:49:34.452696 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1397 11:49:34.459479 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1398 11:49:34.459563 ==
1399 11:49:34.462443 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 11:49:34.465979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 11:49:34.466065 ==
1402 11:49:34.466160 DQS Delay:
1403 11:49:34.469582 DQS0 = 0, DQS1 = 0
1404 11:49:34.469686 DQM Delay:
1405 11:49:34.473064 DQM0 = 93, DQM1 = 84
1406 11:49:34.473150 DQ Delay:
1407 11:49:34.476000 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1408 11:49:34.479387 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1409 11:49:34.482590 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1410 11:49:34.486603 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1411 11:49:34.486712
1412 11:49:34.486806
1413 11:49:34.493135 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1414 11:49:34.496332 CH0 RK1: MR19=606, MR18=4111
1415 11:49:34.502866 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1416 11:49:34.506155 [RxdqsGatingPostProcess] freq 800
1417 11:49:34.513030 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1418 11:49:34.513135 Pre-setting of DQS Precalculation
1419 11:49:34.519589 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1420 11:49:34.519676 ==
1421 11:49:34.522786 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 11:49:34.526864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 11:49:34.526952 ==
1424 11:49:34.533164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 11:49:34.539805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 11:49:34.547311 [CA 0] Center 36 (6~67) winsize 62
1427 11:49:34.550938 [CA 1] Center 37 (6~68) winsize 63
1428 11:49:34.554260 [CA 2] Center 35 (4~66) winsize 63
1429 11:49:34.557335 [CA 3] Center 34 (4~65) winsize 62
1430 11:49:34.560593 [CA 4] Center 35 (5~65) winsize 61
1431 11:49:34.564489 [CA 5] Center 34 (4~64) winsize 61
1432 11:49:34.564566
1433 11:49:34.567541 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 11:49:34.567624
1435 11:49:34.570625 [CATrainingPosCal] consider 1 rank data
1436 11:49:34.574419 u2DelayCellTimex100 = 270/100 ps
1437 11:49:34.577595 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1438 11:49:34.580872 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1439 11:49:34.587353 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1440 11:49:34.590709 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 11:49:34.593990 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 11:49:34.597486 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1443 11:49:34.597609
1444 11:49:34.600800 CA PerBit enable=1, Macro0, CA PI delay=34
1445 11:49:34.600911
1446 11:49:34.604221 [CBTSetCACLKResult] CA Dly = 34
1447 11:49:34.604325 CS Dly: 6 (0~37)
1448 11:49:34.604417 ==
1449 11:49:34.607743 Dram Type= 6, Freq= 0, CH_1, rank 1
1450 11:49:34.614202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 11:49:34.614289 ==
1452 11:49:34.618279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 11:49:34.624954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 11:49:34.634299 [CA 0] Center 36 (6~67) winsize 62
1455 11:49:34.638210 [CA 1] Center 37 (6~68) winsize 63
1456 11:49:34.642052 [CA 2] Center 35 (5~66) winsize 62
1457 11:49:34.645597 [CA 3] Center 35 (5~65) winsize 61
1458 11:49:34.649466 [CA 4] Center 35 (5~66) winsize 62
1459 11:49:34.649551 [CA 5] Center 34 (4~65) winsize 62
1460 11:49:34.649629
1461 11:49:34.655817 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 11:49:34.655913
1463 11:49:34.659710 [CATrainingPosCal] consider 2 rank data
1464 11:49:34.659798 u2DelayCellTimex100 = 270/100 ps
1465 11:49:34.666217 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 11:49:34.669551 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1467 11:49:34.672629 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1468 11:49:34.676202 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 11:49:34.679539 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1470 11:49:34.682991 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1471 11:49:34.683081
1472 11:49:34.686675 CA PerBit enable=1, Macro0, CA PI delay=34
1473 11:49:34.686768
1474 11:49:34.689314 [CBTSetCACLKResult] CA Dly = 34
1475 11:49:34.692577 CS Dly: 6 (0~38)
1476 11:49:34.692682
1477 11:49:34.696650 ----->DramcWriteLeveling(PI) begin...
1478 11:49:34.696753 ==
1479 11:49:34.699518 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 11:49:34.703114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 11:49:34.703218 ==
1482 11:49:34.706020 Write leveling (Byte 0): 26 => 26
1483 11:49:34.709424 Write leveling (Byte 1): 26 => 26
1484 11:49:34.712710 DramcWriteLeveling(PI) end<-----
1485 11:49:34.712819
1486 11:49:34.712911 ==
1487 11:49:34.716707 Dram Type= 6, Freq= 0, CH_1, rank 0
1488 11:49:34.719389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1489 11:49:34.719473 ==
1490 11:49:34.722758 [Gating] SW mode calibration
1491 11:49:34.729512 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1492 11:49:34.736767 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1493 11:49:34.740118 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1494 11:49:34.743432 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1495 11:49:34.746672 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:49:34.753423 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:49:34.756608 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:49:34.759666 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:49:34.766108 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:49:34.769717 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:49:34.772615 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:49:34.779415 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:49:34.782737 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:49:34.786069 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:49:34.792984 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:49:34.796071 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:49:34.799448 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:49:34.806614 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:49:34.809827 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1510 11:49:34.812890 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1511 11:49:34.819810 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:49:34.823304 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:49:34.826749 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:49:34.833186 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:49:34.836407 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:49:34.839702 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:49:34.843059 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:49:34.850277 0 9 4 | B1->B0 | 2323 2727 | 1 1 | (1 1) (1 1)
1519 11:49:34.853610 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 11:49:34.856877 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 11:49:34.863250 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 11:49:34.866948 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 11:49:34.870027 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 11:49:34.876927 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 11:49:34.880106 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 11:49:34.883337 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 0)
1527 11:49:34.890568 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1528 11:49:34.893449 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:49:34.896647 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:49:34.900408 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:49:34.907140 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:49:34.910125 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:49:34.913411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:49:34.920376 0 11 4 | B1->B0 | 2828 3534 | 1 1 | (0 0) (0 0)
1535 11:49:34.923658 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1536 11:49:34.926963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 11:49:34.933405 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 11:49:34.937151 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 11:49:34.940176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 11:49:34.947025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 11:49:34.950581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1542 11:49:34.953754 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1543 11:49:34.960859 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 11:49:34.964137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 11:49:34.967233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:49:34.973555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:49:34.977389 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:49:34.980480 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:49:34.983691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:49:34.990705 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:49:34.993787 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 11:49:34.997003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:49:35.003775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 11:49:35.007013 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 11:49:35.010843 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 11:49:35.017347 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:49:35.020282 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1558 11:49:35.023992 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1559 11:49:35.030440 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:49:35.030523 Total UI for P1: 0, mck2ui 16
1561 11:49:35.037546 best dqsien dly found for B0: ( 0, 14, 4)
1562 11:49:35.037652 Total UI for P1: 0, mck2ui 16
1563 11:49:35.040887 best dqsien dly found for B1: ( 0, 14, 2)
1564 11:49:35.047320 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1565 11:49:35.051023 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1566 11:49:35.051115
1567 11:49:35.053872 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1568 11:49:35.057111 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1569 11:49:35.060791 [Gating] SW calibration Done
1570 11:49:35.060875 ==
1571 11:49:35.064621 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 11:49:35.067210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 11:49:35.067296 ==
1574 11:49:35.070340 RX Vref Scan: 0
1575 11:49:35.070424
1576 11:49:35.070489 RX Vref 0 -> 0, step: 1
1577 11:49:35.070551
1578 11:49:35.073701 RX Delay -130 -> 252, step: 16
1579 11:49:35.077372 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1580 11:49:35.084225 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1581 11:49:35.087516 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1582 11:49:35.090635 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1583 11:49:35.093677 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1584 11:49:35.097334 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1585 11:49:35.100728 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1586 11:49:35.107188 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1587 11:49:35.111191 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1588 11:49:35.113872 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1589 11:49:35.117068 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1590 11:49:35.120941 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1591 11:49:35.127300 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1592 11:49:35.131134 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1593 11:49:35.134172 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1594 11:49:35.137277 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1595 11:49:35.137355 ==
1596 11:49:35.140627 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:49:35.147663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:49:35.147749 ==
1599 11:49:35.147819 DQS Delay:
1600 11:49:35.147881 DQS0 = 0, DQS1 = 0
1601 11:49:35.151202 DQM Delay:
1602 11:49:35.151287 DQM0 = 94, DQM1 = 89
1603 11:49:35.154218 DQ Delay:
1604 11:49:35.157997 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1605 11:49:35.161160 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1606 11:49:35.164437 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1607 11:49:35.167607 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1608 11:49:35.167687
1609 11:49:35.167751
1610 11:49:35.167811 ==
1611 11:49:35.170840 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 11:49:35.173854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 11:49:35.173939 ==
1614 11:49:35.174012
1615 11:49:35.174074
1616 11:49:35.177310 TX Vref Scan disable
1617 11:49:35.177419 == TX Byte 0 ==
1618 11:49:35.183990 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1619 11:49:35.187234 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1620 11:49:35.187311 == TX Byte 1 ==
1621 11:49:35.194405 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1622 11:49:35.198351 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1623 11:49:35.198439 ==
1624 11:49:35.201303 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:49:35.204521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:49:35.204606 ==
1627 11:49:35.218087 TX Vref=22, minBit 0, minWin=26, winSum=434
1628 11:49:35.221371 TX Vref=24, minBit 1, minWin=26, winSum=439
1629 11:49:35.224131 TX Vref=26, minBit 1, minWin=27, winSum=444
1630 11:49:35.227854 TX Vref=28, minBit 1, minWin=27, winSum=442
1631 11:49:35.231212 TX Vref=30, minBit 1, minWin=27, winSum=444
1632 11:49:35.238209 TX Vref=32, minBit 2, minWin=26, winSum=442
1633 11:49:35.240795 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 26
1634 11:49:35.240873
1635 11:49:35.244327 Final TX Range 1 Vref 26
1636 11:49:35.244410
1637 11:49:35.244482 ==
1638 11:49:35.247573 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 11:49:35.250845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 11:49:35.250926 ==
1641 11:49:35.254250
1642 11:49:35.254323
1643 11:49:35.254385 TX Vref Scan disable
1644 11:49:35.257457 == TX Byte 0 ==
1645 11:49:35.261069 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1646 11:49:35.264488 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1647 11:49:35.267625 == TX Byte 1 ==
1648 11:49:35.270962 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1649 11:49:35.274275 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1650 11:49:35.277729
1651 11:49:35.277808 [DATLAT]
1652 11:49:35.277891 Freq=800, CH1 RK0
1653 11:49:35.277970
1654 11:49:35.281074 DATLAT Default: 0xa
1655 11:49:35.281177 0, 0xFFFF, sum = 0
1656 11:49:35.284400 1, 0xFFFF, sum = 0
1657 11:49:35.284486 2, 0xFFFF, sum = 0
1658 11:49:35.287556 3, 0xFFFF, sum = 0
1659 11:49:35.287634 4, 0xFFFF, sum = 0
1660 11:49:35.290897 5, 0xFFFF, sum = 0
1661 11:49:35.290973 6, 0xFFFF, sum = 0
1662 11:49:35.294349 7, 0xFFFF, sum = 0
1663 11:49:35.297833 8, 0xFFFF, sum = 0
1664 11:49:35.297915 9, 0x0, sum = 1
1665 11:49:35.297980 10, 0x0, sum = 2
1666 11:49:35.301358 11, 0x0, sum = 3
1667 11:49:35.301438 12, 0x0, sum = 4
1668 11:49:35.304218 best_step = 10
1669 11:49:35.304289
1670 11:49:35.304350 ==
1671 11:49:35.307961 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 11:49:35.311394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1673 11:49:35.311465 ==
1674 11:49:35.314542 RX Vref Scan: 1
1675 11:49:35.314615
1676 11:49:35.314676 Set Vref Range= 32 -> 127
1677 11:49:35.314746
1678 11:49:35.317781 RX Vref 32 -> 127, step: 1
1679 11:49:35.317904
1680 11:49:35.321367 RX Delay -63 -> 252, step: 8
1681 11:49:35.321461
1682 11:49:35.324632 Set Vref, RX VrefLevel [Byte0]: 32
1683 11:49:35.327584 [Byte1]: 32
1684 11:49:35.327665
1685 11:49:35.331277 Set Vref, RX VrefLevel [Byte0]: 33
1686 11:49:35.334652 [Byte1]: 33
1687 11:49:35.338040
1688 11:49:35.338123 Set Vref, RX VrefLevel [Byte0]: 34
1689 11:49:35.341089 [Byte1]: 34
1690 11:49:35.345705
1691 11:49:35.345788 Set Vref, RX VrefLevel [Byte0]: 35
1692 11:49:35.348863 [Byte1]: 35
1693 11:49:35.352669
1694 11:49:35.352750 Set Vref, RX VrefLevel [Byte0]: 36
1695 11:49:35.356159 [Byte1]: 36
1696 11:49:35.360162
1697 11:49:35.360239 Set Vref, RX VrefLevel [Byte0]: 37
1698 11:49:35.363362 [Byte1]: 37
1699 11:49:35.367741
1700 11:49:35.367825 Set Vref, RX VrefLevel [Byte0]: 38
1701 11:49:35.371034 [Byte1]: 38
1702 11:49:35.375599
1703 11:49:35.375713 Set Vref, RX VrefLevel [Byte0]: 39
1704 11:49:35.378886 [Byte1]: 39
1705 11:49:35.382843
1706 11:49:35.382924 Set Vref, RX VrefLevel [Byte0]: 40
1707 11:49:35.386308 [Byte1]: 40
1708 11:49:35.390276
1709 11:49:35.390350 Set Vref, RX VrefLevel [Byte0]: 41
1710 11:49:35.393572 [Byte1]: 41
1711 11:49:35.397551
1712 11:49:35.397633 Set Vref, RX VrefLevel [Byte0]: 42
1713 11:49:35.400948 [Byte1]: 42
1714 11:49:35.405535
1715 11:49:35.405630 Set Vref, RX VrefLevel [Byte0]: 43
1716 11:49:35.408990 [Byte1]: 43
1717 11:49:35.412856
1718 11:49:35.412934 Set Vref, RX VrefLevel [Byte0]: 44
1719 11:49:35.416308 [Byte1]: 44
1720 11:49:35.420114
1721 11:49:35.420196 Set Vref, RX VrefLevel [Byte0]: 45
1722 11:49:35.423826 [Byte1]: 45
1723 11:49:35.427493
1724 11:49:35.427570 Set Vref, RX VrefLevel [Byte0]: 46
1725 11:49:35.430830 [Byte1]: 46
1726 11:49:35.435167
1727 11:49:35.435301 Set Vref, RX VrefLevel [Byte0]: 47
1728 11:49:35.438529 [Byte1]: 47
1729 11:49:35.443132
1730 11:49:35.443220 Set Vref, RX VrefLevel [Byte0]: 48
1731 11:49:35.446181 [Byte1]: 48
1732 11:49:35.450093
1733 11:49:35.450189 Set Vref, RX VrefLevel [Byte0]: 49
1734 11:49:35.453554 [Byte1]: 49
1735 11:49:35.457664
1736 11:49:35.457767 Set Vref, RX VrefLevel [Byte0]: 50
1737 11:49:35.460927 [Byte1]: 50
1738 11:49:35.465157
1739 11:49:35.465272 Set Vref, RX VrefLevel [Byte0]: 51
1740 11:49:35.468393 [Byte1]: 51
1741 11:49:35.472606
1742 11:49:35.472689 Set Vref, RX VrefLevel [Byte0]: 52
1743 11:49:35.476417 [Byte1]: 52
1744 11:49:35.480359
1745 11:49:35.480476 Set Vref, RX VrefLevel [Byte0]: 53
1746 11:49:35.483737 [Byte1]: 53
1747 11:49:35.488026
1748 11:49:35.488139 Set Vref, RX VrefLevel [Byte0]: 54
1749 11:49:35.491383 [Byte1]: 54
1750 11:49:35.495442
1751 11:49:35.495547 Set Vref, RX VrefLevel [Byte0]: 55
1752 11:49:35.498576 [Byte1]: 55
1753 11:49:35.502747
1754 11:49:35.502828 Set Vref, RX VrefLevel [Byte0]: 56
1755 11:49:35.506162 [Byte1]: 56
1756 11:49:35.510379
1757 11:49:35.510456 Set Vref, RX VrefLevel [Byte0]: 57
1758 11:49:35.513563 [Byte1]: 57
1759 11:49:35.517987
1760 11:49:35.518105 Set Vref, RX VrefLevel [Byte0]: 58
1761 11:49:35.520786 [Byte1]: 58
1762 11:49:35.525396
1763 11:49:35.525473 Set Vref, RX VrefLevel [Byte0]: 59
1764 11:49:35.528662 [Byte1]: 59
1765 11:49:35.532527
1766 11:49:35.532601 Set Vref, RX VrefLevel [Byte0]: 60
1767 11:49:35.536010 [Byte1]: 60
1768 11:49:35.540287
1769 11:49:35.540366 Set Vref, RX VrefLevel [Byte0]: 61
1770 11:49:35.543833 [Byte1]: 61
1771 11:49:35.547581
1772 11:49:35.547665 Set Vref, RX VrefLevel [Byte0]: 62
1773 11:49:35.550829 [Byte1]: 62
1774 11:49:35.555205
1775 11:49:35.555281 Set Vref, RX VrefLevel [Byte0]: 63
1776 11:49:35.558290 [Byte1]: 63
1777 11:49:35.562734
1778 11:49:35.562809 Set Vref, RX VrefLevel [Byte0]: 64
1779 11:49:35.566237 [Byte1]: 64
1780 11:49:35.570547
1781 11:49:35.570618 Set Vref, RX VrefLevel [Byte0]: 65
1782 11:49:35.573566 [Byte1]: 65
1783 11:49:35.577744
1784 11:49:35.577822 Set Vref, RX VrefLevel [Byte0]: 66
1785 11:49:35.580905 [Byte1]: 66
1786 11:49:35.585245
1787 11:49:35.585326 Set Vref, RX VrefLevel [Byte0]: 67
1788 11:49:35.588605 [Byte1]: 67
1789 11:49:35.592638
1790 11:49:35.592724 Set Vref, RX VrefLevel [Byte0]: 68
1791 11:49:35.596249 [Byte1]: 68
1792 11:49:35.600182
1793 11:49:35.600294 Set Vref, RX VrefLevel [Byte0]: 69
1794 11:49:35.603485 [Byte1]: 69
1795 11:49:35.608078
1796 11:49:35.608183 Set Vref, RX VrefLevel [Byte0]: 70
1797 11:49:35.611221 [Byte1]: 70
1798 11:49:35.615177
1799 11:49:35.615256 Set Vref, RX VrefLevel [Byte0]: 71
1800 11:49:35.618462 [Byte1]: 71
1801 11:49:35.623021
1802 11:49:35.623101 Set Vref, RX VrefLevel [Byte0]: 72
1803 11:49:35.625704 [Byte1]: 72
1804 11:49:35.630550
1805 11:49:35.630635 Set Vref, RX VrefLevel [Byte0]: 73
1806 11:49:35.633242 [Byte1]: 73
1807 11:49:35.637863
1808 11:49:35.637940 Final RX Vref Byte 0 = 59 to rank0
1809 11:49:35.641203 Final RX Vref Byte 1 = 54 to rank0
1810 11:49:35.644652 Final RX Vref Byte 0 = 59 to rank1
1811 11:49:35.647939 Final RX Vref Byte 1 = 54 to rank1==
1812 11:49:35.651072 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 11:49:35.657537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 11:49:35.657628 ==
1815 11:49:35.657701 DQS Delay:
1816 11:49:35.657767 DQS0 = 0, DQS1 = 0
1817 11:49:35.660838 DQM Delay:
1818 11:49:35.660910 DQM0 = 95, DQM1 = 90
1819 11:49:35.664149 DQ Delay:
1820 11:49:35.667520 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1821 11:49:35.670832 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
1822 11:49:35.674248 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1823 11:49:35.677614 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1824 11:49:35.677699
1825 11:49:35.677766
1826 11:49:35.684297 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1827 11:49:35.688144 CH1 RK0: MR19=606, MR18=2F4B
1828 11:49:35.694759 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1829 11:49:35.694863
1830 11:49:35.697911 ----->DramcWriteLeveling(PI) begin...
1831 11:49:35.697999 ==
1832 11:49:35.701300 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 11:49:35.704321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:49:35.704403 ==
1835 11:49:35.707951 Write leveling (Byte 0): 27 => 27
1836 11:49:35.711229 Write leveling (Byte 1): 29 => 29
1837 11:49:35.714334 DramcWriteLeveling(PI) end<-----
1838 11:49:35.714417
1839 11:49:35.714481 ==
1840 11:49:35.718091 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 11:49:35.721270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 11:49:35.721381 ==
1843 11:49:35.724448 [Gating] SW mode calibration
1844 11:49:35.731406 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 11:49:35.738397 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 11:49:35.741712 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 11:49:35.745036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1848 11:49:35.751644 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:49:35.755059 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:49:35.758172 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:49:35.761421 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:49:35.768199 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:49:35.771529 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:49:35.774754 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:49:35.781521 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:49:35.784847 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:49:35.788241 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:49:35.794813 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:49:35.798087 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:49:35.801819 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:49:35.808109 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:49:35.811742 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1863 11:49:35.815014 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1864 11:49:35.821954 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:49:35.825091 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:49:35.828204 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:49:35.835246 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:49:35.838700 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:49:35.841891 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:49:35.844940 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:49:35.851774 0 9 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1872 11:49:35.855122 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 11:49:35.858297 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 11:49:35.864960 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 11:49:35.868852 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 11:49:35.872074 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 11:49:35.878547 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 11:49:35.881667 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1879 11:49:35.884991 0 10 4 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 0)
1880 11:49:35.891715 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1881 11:49:35.894910 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:49:35.898363 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:49:35.905431 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:49:35.908619 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:49:35.911817 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:49:35.918395 0 11 0 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
1887 11:49:35.921691 0 11 4 | B1->B0 | 3838 2b2b | 0 0 | (0 0) (0 0)
1888 11:49:35.925440 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 11:49:35.931601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 11:49:35.935447 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 11:49:35.938725 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 11:49:35.941784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 11:49:35.948688 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 11:49:35.951952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1895 11:49:35.955184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1896 11:49:35.961734 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1897 11:49:35.965085 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 11:49:35.969049 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:49:35.975278 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:49:35.978788 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:49:35.981766 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:49:35.988684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:49:35.992003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 11:49:35.995383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:49:36.001801 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:49:36.005101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:49:36.008408 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:49:36.015151 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:49:36.018945 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:49:36.022000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1911 11:49:36.025194 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1912 11:49:36.032004 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:49:36.035037 Total UI for P1: 0, mck2ui 16
1914 11:49:36.038564 best dqsien dly found for B0: ( 0, 14, 2)
1915 11:49:36.042118 Total UI for P1: 0, mck2ui 16
1916 11:49:36.045331 best dqsien dly found for B1: ( 0, 14, 6)
1917 11:49:36.048337 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1918 11:49:36.051470 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1919 11:49:36.051543
1920 11:49:36.055204 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1921 11:49:36.058528 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1922 11:49:36.061565 [Gating] SW calibration Done
1923 11:49:36.061682 ==
1924 11:49:36.064844 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 11:49:36.068632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 11:49:36.068715 ==
1927 11:49:36.071668 RX Vref Scan: 0
1928 11:49:36.071751
1929 11:49:36.071832 RX Vref 0 -> 0, step: 1
1930 11:49:36.074723
1931 11:49:36.074810 RX Delay -130 -> 252, step: 16
1932 11:49:36.081844 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1933 11:49:36.084803 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1934 11:49:36.088297 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1935 11:49:36.091560 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1936 11:49:36.094819 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1937 11:49:36.098367 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1938 11:49:36.105281 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1939 11:49:36.108593 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1940 11:49:36.111832 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1941 11:49:36.115022 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1942 11:49:36.118275 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1943 11:49:36.124714 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1944 11:49:36.128315 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1945 11:49:36.131365 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1946 11:49:36.135213 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1947 11:49:36.141678 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1948 11:49:36.141759 ==
1949 11:49:36.144739 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 11:49:36.148474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 11:49:36.148589 ==
1952 11:49:36.148690 DQS Delay:
1953 11:49:36.151383 DQS0 = 0, DQS1 = 0
1954 11:49:36.151469 DQM Delay:
1955 11:49:36.155328 DQM0 = 91, DQM1 = 88
1956 11:49:36.155406 DQ Delay:
1957 11:49:36.158530 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1958 11:49:36.161571 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1959 11:49:36.164937 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1960 11:49:36.168137 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1961 11:49:36.168207
1962 11:49:36.168268
1963 11:49:36.168325 ==
1964 11:49:36.171962 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 11:49:36.175057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 11:49:36.175133 ==
1967 11:49:36.175202
1968 11:49:36.178047
1969 11:49:36.178114 TX Vref Scan disable
1970 11:49:36.181877 == TX Byte 0 ==
1971 11:49:36.185101 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 11:49:36.188346 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 11:49:36.191531 == TX Byte 1 ==
1974 11:49:36.194848 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1975 11:49:36.198537 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1976 11:49:36.198613 ==
1977 11:49:36.201635 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 11:49:36.207985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 11:49:36.208061 ==
1980 11:49:36.219717 TX Vref=22, minBit 1, minWin=26, winSum=443
1981 11:49:36.223062 TX Vref=24, minBit 1, minWin=26, winSum=445
1982 11:49:36.226672 TX Vref=26, minBit 0, minWin=27, winSum=446
1983 11:49:36.229896 TX Vref=28, minBit 0, minWin=27, winSum=448
1984 11:49:36.233109 TX Vref=30, minBit 2, minWin=27, winSum=451
1985 11:49:36.236385 TX Vref=32, minBit 2, minWin=27, winSum=449
1986 11:49:36.243063 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1987 11:49:36.243149
1988 11:49:36.246400 Final TX Range 1 Vref 30
1989 11:49:36.246478
1990 11:49:36.246549 ==
1991 11:49:36.249713 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 11:49:36.253302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 11:49:36.253379 ==
1994 11:49:36.253444
1995 11:49:36.256351
1996 11:49:36.256420 TX Vref Scan disable
1997 11:49:36.259919 == TX Byte 0 ==
1998 11:49:36.263258 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1999 11:49:36.266368 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2000 11:49:36.269525 == TX Byte 1 ==
2001 11:49:36.273112 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2002 11:49:36.276350 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2003 11:49:36.279653
2004 11:49:36.279737 [DATLAT]
2005 11:49:36.279801 Freq=800, CH1 RK1
2006 11:49:36.279863
2007 11:49:36.283189 DATLAT Default: 0xa
2008 11:49:36.283272 0, 0xFFFF, sum = 0
2009 11:49:36.286319 1, 0xFFFF, sum = 0
2010 11:49:36.286404 2, 0xFFFF, sum = 0
2011 11:49:36.290213 3, 0xFFFF, sum = 0
2012 11:49:36.290298 4, 0xFFFF, sum = 0
2013 11:49:36.293493 5, 0xFFFF, sum = 0
2014 11:49:36.296710 6, 0xFFFF, sum = 0
2015 11:49:36.296795 7, 0xFFFF, sum = 0
2016 11:49:36.299947 8, 0xFFFF, sum = 0
2017 11:49:36.300032 9, 0x0, sum = 1
2018 11:49:36.300100 10, 0x0, sum = 2
2019 11:49:36.303322 11, 0x0, sum = 3
2020 11:49:36.303406 12, 0x0, sum = 4
2021 11:49:36.306615 best_step = 10
2022 11:49:36.306698
2023 11:49:36.306764 ==
2024 11:49:36.309862 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 11:49:36.313138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 11:49:36.313222 ==
2027 11:49:36.316325 RX Vref Scan: 0
2028 11:49:36.316409
2029 11:49:36.316474 RX Vref 0 -> 0, step: 1
2030 11:49:36.316535
2031 11:49:36.320136 RX Delay -79 -> 252, step: 8
2032 11:49:36.326592 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2033 11:49:36.329611 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2034 11:49:36.333155 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2035 11:49:36.336508 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2036 11:49:36.339776 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2037 11:49:36.343323 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2038 11:49:36.349529 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2039 11:49:36.353271 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2040 11:49:36.356406 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2041 11:49:36.359614 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2042 11:49:36.363507 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2043 11:49:36.370191 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2044 11:49:36.373076 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2045 11:49:36.376636 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2046 11:49:36.379611 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2047 11:49:36.383560 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2048 11:49:36.386675 ==
2049 11:49:36.386759 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 11:49:36.393567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 11:49:36.393660 ==
2052 11:49:36.393726 DQS Delay:
2053 11:49:36.396772 DQS0 = 0, DQS1 = 0
2054 11:49:36.396855 DQM Delay:
2055 11:49:36.399979 DQM0 = 97, DQM1 = 91
2056 11:49:36.400063 DQ Delay:
2057 11:49:36.403255 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2058 11:49:36.406489 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2059 11:49:36.409738 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2060 11:49:36.412868 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2061 11:49:36.412951
2062 11:49:36.413016
2063 11:49:36.420053 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2064 11:49:36.422984 CH1 RK1: MR19=606, MR18=4A15
2065 11:49:36.429587 CH1_RK1: MR19=0x606, MR18=0x4A15, DQSOSC=391, MR23=63, INC=96, DEC=64
2066 11:49:36.433482 [RxdqsGatingPostProcess] freq 800
2067 11:49:36.440117 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2068 11:49:36.440205 Pre-setting of DQS Precalculation
2069 11:49:36.446443 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2070 11:49:36.452970 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2071 11:49:36.459944 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2072 11:49:36.460026
2073 11:49:36.460091
2074 11:49:36.463252 [Calibration Summary] 1600 Mbps
2075 11:49:36.466609 CH 0, Rank 0
2076 11:49:36.466691 SW Impedance : PASS
2077 11:49:36.469870 DUTY Scan : NO K
2078 11:49:36.469967 ZQ Calibration : PASS
2079 11:49:36.473512 Jitter Meter : NO K
2080 11:49:36.476857 CBT Training : PASS
2081 11:49:36.476940 Write leveling : PASS
2082 11:49:36.479781 RX DQS gating : PASS
2083 11:49:36.483355 RX DQ/DQS(RDDQC) : PASS
2084 11:49:36.483437 TX DQ/DQS : PASS
2085 11:49:36.486985 RX DATLAT : PASS
2086 11:49:36.489819 RX DQ/DQS(Engine): PASS
2087 11:49:36.489901 TX OE : NO K
2088 11:49:36.493285 All Pass.
2089 11:49:36.493366
2090 11:49:36.493430 CH 0, Rank 1
2091 11:49:36.496800 SW Impedance : PASS
2092 11:49:36.496913 DUTY Scan : NO K
2093 11:49:36.499681 ZQ Calibration : PASS
2094 11:49:36.503332 Jitter Meter : NO K
2095 11:49:36.503414 CBT Training : PASS
2096 11:49:36.506740 Write leveling : PASS
2097 11:49:36.506823 RX DQS gating : PASS
2098 11:49:36.509969 RX DQ/DQS(RDDQC) : PASS
2099 11:49:36.513312 TX DQ/DQS : PASS
2100 11:49:36.513394 RX DATLAT : PASS
2101 11:49:36.516779 RX DQ/DQS(Engine): PASS
2102 11:49:36.520339 TX OE : NO K
2103 11:49:36.520438 All Pass.
2104 11:49:36.520504
2105 11:49:36.520601 CH 1, Rank 0
2106 11:49:36.523584 SW Impedance : PASS
2107 11:49:36.526747 DUTY Scan : NO K
2108 11:49:36.526831 ZQ Calibration : PASS
2109 11:49:36.530041 Jitter Meter : NO K
2110 11:49:36.533315 CBT Training : PASS
2111 11:49:36.533397 Write leveling : PASS
2112 11:49:36.536740 RX DQS gating : PASS
2113 11:49:36.539942 RX DQ/DQS(RDDQC) : PASS
2114 11:49:36.540024 TX DQ/DQS : PASS
2115 11:49:36.543216 RX DATLAT : PASS
2116 11:49:36.546568 RX DQ/DQS(Engine): PASS
2117 11:49:36.546653 TX OE : NO K
2118 11:49:36.546718 All Pass.
2119 11:49:36.549786
2120 11:49:36.549867 CH 1, Rank 1
2121 11:49:36.553682 SW Impedance : PASS
2122 11:49:36.553763 DUTY Scan : NO K
2123 11:49:36.556773 ZQ Calibration : PASS
2124 11:49:36.556854 Jitter Meter : NO K
2125 11:49:36.559784 CBT Training : PASS
2126 11:49:36.563209 Write leveling : PASS
2127 11:49:36.563291 RX DQS gating : PASS
2128 11:49:36.566895 RX DQ/DQS(RDDQC) : PASS
2129 11:49:36.569864 TX DQ/DQS : PASS
2130 11:49:36.569947 RX DATLAT : PASS
2131 11:49:36.573753 RX DQ/DQS(Engine): PASS
2132 11:49:36.577026 TX OE : NO K
2133 11:49:36.577112 All Pass.
2134 11:49:36.577177
2135 11:49:36.577236 DramC Write-DBI off
2136 11:49:36.579862 PER_BANK_REFRESH: Hybrid Mode
2137 11:49:36.583239 TX_TRACKING: ON
2138 11:49:36.586578 [GetDramInforAfterCalByMRR] Vendor 6.
2139 11:49:36.590067 [GetDramInforAfterCalByMRR] Revision 606.
2140 11:49:36.593516 [GetDramInforAfterCalByMRR] Revision 2 0.
2141 11:49:36.593635 MR0 0x3b3b
2142 11:49:36.596355 MR8 0x5151
2143 11:49:36.600268 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2144 11:49:36.600349
2145 11:49:36.600413 MR0 0x3b3b
2146 11:49:36.600472 MR8 0x5151
2147 11:49:36.606546 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 11:49:36.606628
2149 11:49:36.613316 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2150 11:49:36.616624 [FAST_K] Save calibration result to emmc
2151 11:49:36.620317 [FAST_K] Save calibration result to emmc
2152 11:49:36.623457 dram_init: config_dvfs: 1
2153 11:49:36.626689 dramc_set_vcore_voltage set vcore to 662500
2154 11:49:36.629837 Read voltage for 1200, 2
2155 11:49:36.629919 Vio18 = 0
2156 11:49:36.633558 Vcore = 662500
2157 11:49:36.633646 Vdram = 0
2158 11:49:36.633710 Vddq = 0
2159 11:49:36.633770 Vmddr = 0
2160 11:49:36.640286 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2161 11:49:36.646800 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2162 11:49:36.646881 MEM_TYPE=3, freq_sel=15
2163 11:49:36.650024 sv_algorithm_assistance_LP4_1600
2164 11:49:36.653290 ============ PULL DRAM RESETB DOWN ============
2165 11:49:36.659835 ========== PULL DRAM RESETB DOWN end =========
2166 11:49:36.663574 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 11:49:36.666953 ===================================
2168 11:49:36.670131 LPDDR4 DRAM CONFIGURATION
2169 11:49:36.673352 ===================================
2170 11:49:36.673434 EX_ROW_EN[0] = 0x0
2171 11:49:36.676571 EX_ROW_EN[1] = 0x0
2172 11:49:36.676653 LP4Y_EN = 0x0
2173 11:49:36.680256 WORK_FSP = 0x0
2174 11:49:36.680338 WL = 0x4
2175 11:49:36.683568 RL = 0x4
2176 11:49:36.683649 BL = 0x2
2177 11:49:36.686706 RPST = 0x0
2178 11:49:36.686787 RD_PRE = 0x0
2179 11:49:36.690347 WR_PRE = 0x1
2180 11:49:36.690428 WR_PST = 0x0
2181 11:49:36.693419 DBI_WR = 0x0
2182 11:49:36.696488 DBI_RD = 0x0
2183 11:49:36.696569 OTF = 0x1
2184 11:49:36.700110 ===================================
2185 11:49:36.703681 ===================================
2186 11:49:36.703762 ANA top config
2187 11:49:36.706793 ===================================
2188 11:49:36.710418 DLL_ASYNC_EN = 0
2189 11:49:36.713421 ALL_SLAVE_EN = 0
2190 11:49:36.716969 NEW_RANK_MODE = 1
2191 11:49:36.717052 DLL_IDLE_MODE = 1
2192 11:49:36.719937 LP45_APHY_COMB_EN = 1
2193 11:49:36.723690 TX_ODT_DIS = 1
2194 11:49:36.726611 NEW_8X_MODE = 1
2195 11:49:36.729996 ===================================
2196 11:49:36.733199 ===================================
2197 11:49:36.736750 data_rate = 2400
2198 11:49:36.740259 CKR = 1
2199 11:49:36.740342 DQ_P2S_RATIO = 8
2200 11:49:36.743374 ===================================
2201 11:49:36.746497 CA_P2S_RATIO = 8
2202 11:49:36.749862 DQ_CA_OPEN = 0
2203 11:49:36.753650 DQ_SEMI_OPEN = 0
2204 11:49:36.756995 CA_SEMI_OPEN = 0
2205 11:49:36.757077 CA_FULL_RATE = 0
2206 11:49:36.760293 DQ_CKDIV4_EN = 0
2207 11:49:36.763559 CA_CKDIV4_EN = 0
2208 11:49:36.766782 CA_PREDIV_EN = 0
2209 11:49:36.769883 PH8_DLY = 17
2210 11:49:36.773762 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2211 11:49:36.773858 DQ_AAMCK_DIV = 4
2212 11:49:36.777081 CA_AAMCK_DIV = 4
2213 11:49:36.780296 CA_ADMCK_DIV = 4
2214 11:49:36.784003 DQ_TRACK_CA_EN = 0
2215 11:49:36.787227 CA_PICK = 1200
2216 11:49:36.790445 CA_MCKIO = 1200
2217 11:49:36.790527 MCKIO_SEMI = 0
2218 11:49:36.793837 PLL_FREQ = 2366
2219 11:49:36.797046 DQ_UI_PI_RATIO = 32
2220 11:49:36.800750 CA_UI_PI_RATIO = 0
2221 11:49:36.803932 ===================================
2222 11:49:36.807160 ===================================
2223 11:49:36.810160 memory_type:LPDDR4
2224 11:49:36.810241 GP_NUM : 10
2225 11:49:36.813721 SRAM_EN : 1
2226 11:49:36.816939 MD32_EN : 0
2227 11:49:36.820790 ===================================
2228 11:49:36.820872 [ANA_INIT] >>>>>>>>>>>>>>
2229 11:49:36.823815 <<<<<< [CONFIGURE PHASE]: ANA_TX
2230 11:49:36.827182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2231 11:49:36.830330 ===================================
2232 11:49:36.834199 data_rate = 2400,PCW = 0X5b00
2233 11:49:36.837372 ===================================
2234 11:49:36.840323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2235 11:49:36.847398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 11:49:36.851001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 11:49:36.857334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2238 11:49:36.860665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2239 11:49:36.863801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2240 11:49:36.863883 [ANA_INIT] flow start
2241 11:49:36.867188 [ANA_INIT] PLL >>>>>>>>
2242 11:49:36.870920 [ANA_INIT] PLL <<<<<<<<
2243 11:49:36.871002 [ANA_INIT] MIDPI >>>>>>>>
2244 11:49:36.874130 [ANA_INIT] MIDPI <<<<<<<<
2245 11:49:36.877431 [ANA_INIT] DLL >>>>>>>>
2246 11:49:36.877513 [ANA_INIT] DLL <<<<<<<<
2247 11:49:36.880745 [ANA_INIT] flow end
2248 11:49:36.884043 ============ LP4 DIFF to SE enter ============
2249 11:49:36.887661 ============ LP4 DIFF to SE exit ============
2250 11:49:36.890898 [ANA_INIT] <<<<<<<<<<<<<
2251 11:49:36.894084 [Flow] Enable top DCM control >>>>>
2252 11:49:36.897267 [Flow] Enable top DCM control <<<<<
2253 11:49:36.900576 Enable DLL master slave shuffle
2254 11:49:36.907300 ==============================================================
2255 11:49:36.907382 Gating Mode config
2256 11:49:36.914492 ==============================================================
2257 11:49:36.914574 Config description:
2258 11:49:36.924306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2259 11:49:36.930803 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2260 11:49:36.937461 SELPH_MODE 0: By rank 1: By Phase
2261 11:49:36.941323 ==============================================================
2262 11:49:36.943961 GAT_TRACK_EN = 1
2263 11:49:36.947328 RX_GATING_MODE = 2
2264 11:49:36.950463 RX_GATING_TRACK_MODE = 2
2265 11:49:36.954357 SELPH_MODE = 1
2266 11:49:36.957750 PICG_EARLY_EN = 1
2267 11:49:36.960901 VALID_LAT_VALUE = 1
2268 11:49:36.964206 ==============================================================
2269 11:49:36.967744 Enter into Gating configuration >>>>
2270 11:49:36.970980 Exit from Gating configuration <<<<
2271 11:49:36.973842 Enter into DVFS_PRE_config >>>>>
2272 11:49:36.987382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2273 11:49:36.990617 Exit from DVFS_PRE_config <<<<<
2274 11:49:36.994238 Enter into PICG configuration >>>>
2275 11:49:36.994310 Exit from PICG configuration <<<<
2276 11:49:36.997361 [RX_INPUT] configuration >>>>>
2277 11:49:37.000730 [RX_INPUT] configuration <<<<<
2278 11:49:37.007912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2279 11:49:37.010910 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2280 11:49:37.017734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 11:49:37.024170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 11:49:37.031179 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 11:49:37.037798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 11:49:37.041664 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2285 11:49:37.044787 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2286 11:49:37.047695 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2287 11:49:37.054423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2288 11:49:37.058169 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2289 11:49:37.061350 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 11:49:37.064527 ===================================
2291 11:49:37.067779 LPDDR4 DRAM CONFIGURATION
2292 11:49:37.070939 ===================================
2293 11:49:37.071021 EX_ROW_EN[0] = 0x0
2294 11:49:37.074352 EX_ROW_EN[1] = 0x0
2295 11:49:37.077557 LP4Y_EN = 0x0
2296 11:49:37.077664 WORK_FSP = 0x0
2297 11:49:37.081484 WL = 0x4
2298 11:49:37.081615 RL = 0x4
2299 11:49:37.084437 BL = 0x2
2300 11:49:37.084519 RPST = 0x0
2301 11:49:37.088046 RD_PRE = 0x0
2302 11:49:37.088127 WR_PRE = 0x1
2303 11:49:37.091423 WR_PST = 0x0
2304 11:49:37.091504 DBI_WR = 0x0
2305 11:49:37.094605 DBI_RD = 0x0
2306 11:49:37.094687 OTF = 0x1
2307 11:49:37.098024 ===================================
2308 11:49:37.101127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2309 11:49:37.108005 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2310 11:49:37.111262 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 11:49:37.114561 ===================================
2312 11:49:37.117630 LPDDR4 DRAM CONFIGURATION
2313 11:49:37.121238 ===================================
2314 11:49:37.121335 EX_ROW_EN[0] = 0x10
2315 11:49:37.124423 EX_ROW_EN[1] = 0x0
2316 11:49:37.124511 LP4Y_EN = 0x0
2317 11:49:37.127651 WORK_FSP = 0x0
2318 11:49:37.127733 WL = 0x4
2319 11:49:37.130922 RL = 0x4
2320 11:49:37.131015 BL = 0x2
2321 11:49:37.134566 RPST = 0x0
2322 11:49:37.134647 RD_PRE = 0x0
2323 11:49:37.137759 WR_PRE = 0x1
2324 11:49:37.141485 WR_PST = 0x0
2325 11:49:37.141566 DBI_WR = 0x0
2326 11:49:37.144705 DBI_RD = 0x0
2327 11:49:37.144786 OTF = 0x1
2328 11:49:37.147904 ===================================
2329 11:49:37.154322 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2330 11:49:37.154422 ==
2331 11:49:37.157884 Dram Type= 6, Freq= 0, CH_0, rank 0
2332 11:49:37.160902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2333 11:49:37.160983 ==
2334 11:49:37.164382 [Duty_Offset_Calibration]
2335 11:49:37.164462 B0:2 B1:1 CA:1
2336 11:49:37.164526
2337 11:49:37.168055 [DutyScan_Calibration_Flow] k_type=0
2338 11:49:37.178771
2339 11:49:37.178853 ==CLK 0==
2340 11:49:37.182109 Final CLK duty delay cell = 0
2341 11:49:37.185322 [0] MAX Duty = 5187%(X100), DQS PI = 24
2342 11:49:37.189234 [0] MIN Duty = 4875%(X100), DQS PI = 0
2343 11:49:37.189315 [0] AVG Duty = 5031%(X100)
2344 11:49:37.189378
2345 11:49:37.192498 CH0 CLK Duty spec in!! Max-Min= 312%
2346 11:49:37.198726 [DutyScan_Calibration_Flow] ====Done====
2347 11:49:37.198807
2348 11:49:37.202392 [DutyScan_Calibration_Flow] k_type=1
2349 11:49:37.216188
2350 11:49:37.216268 ==DQS 0 ==
2351 11:49:37.219704 Final DQS duty delay cell = -4
2352 11:49:37.223365 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2353 11:49:37.226604 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2354 11:49:37.230129 [-4] AVG Duty = 4953%(X100)
2355 11:49:37.230210
2356 11:49:37.230274 ==DQS 1 ==
2357 11:49:37.233375 Final DQS duty delay cell = -4
2358 11:49:37.236721 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2359 11:49:37.239791 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2360 11:49:37.243296 [-4] AVG Duty = 4906%(X100)
2361 11:49:37.243377
2362 11:49:37.246429 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2363 11:49:37.246510
2364 11:49:37.250216 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2365 11:49:37.253381 [DutyScan_Calibration_Flow] ====Done====
2366 11:49:37.253462
2367 11:49:37.256617 [DutyScan_Calibration_Flow] k_type=3
2368 11:49:37.273635
2369 11:49:37.273716 ==DQM 0 ==
2370 11:49:37.276809 Final DQM duty delay cell = 0
2371 11:49:37.280039 [0] MAX Duty = 5156%(X100), DQS PI = 30
2372 11:49:37.283809 [0] MIN Duty = 4938%(X100), DQS PI = 0
2373 11:49:37.283891 [0] AVG Duty = 5047%(X100)
2374 11:49:37.287163
2375 11:49:37.287244 ==DQM 1 ==
2376 11:49:37.290409 Final DQM duty delay cell = 0
2377 11:49:37.293567 [0] MAX Duty = 5093%(X100), DQS PI = 0
2378 11:49:37.297485 [0] MIN Duty = 5031%(X100), DQS PI = 36
2379 11:49:37.297565 [0] AVG Duty = 5062%(X100)
2380 11:49:37.297669
2381 11:49:37.300856 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2382 11:49:37.304026
2383 11:49:37.307689 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2384 11:49:37.310907 [DutyScan_Calibration_Flow] ====Done====
2385 11:49:37.310988
2386 11:49:37.314196 [DutyScan_Calibration_Flow] k_type=2
2387 11:49:37.329880
2388 11:49:37.329962 ==DQ 0 ==
2389 11:49:37.333424 Final DQ duty delay cell = 0
2390 11:49:37.336790 [0] MAX Duty = 5062%(X100), DQS PI = 32
2391 11:49:37.340082 [0] MIN Duty = 4844%(X100), DQS PI = 62
2392 11:49:37.340163 [0] AVG Duty = 4953%(X100)
2393 11:49:37.340226
2394 11:49:37.343396 ==DQ 1 ==
2395 11:49:37.346814 Final DQ duty delay cell = 0
2396 11:49:37.350046 [0] MAX Duty = 5093%(X100), DQS PI = 24
2397 11:49:37.353434 [0] MIN Duty = 4969%(X100), DQS PI = 16
2398 11:49:37.353515 [0] AVG Duty = 5031%(X100)
2399 11:49:37.353599
2400 11:49:37.356758 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2401 11:49:37.356839
2402 11:49:37.359868 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2403 11:49:37.366332 [DutyScan_Calibration_Flow] ====Done====
2404 11:49:37.366412 ==
2405 11:49:37.370218 Dram Type= 6, Freq= 0, CH_1, rank 0
2406 11:49:37.373379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2407 11:49:37.373459 ==
2408 11:49:37.376627 [Duty_Offset_Calibration]
2409 11:49:37.376707 B0:1 B1:0 CA:0
2410 11:49:37.376770
2411 11:49:37.379726 [DutyScan_Calibration_Flow] k_type=0
2412 11:49:37.389423
2413 11:49:37.389505 ==CLK 0==
2414 11:49:37.392719 Final CLK duty delay cell = -4
2415 11:49:37.396107 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2416 11:49:37.399161 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2417 11:49:37.402447 [-4] AVG Duty = 4953%(X100)
2418 11:49:37.402529
2419 11:49:37.406366 CH1 CLK Duty spec in!! Max-Min= 156%
2420 11:49:37.409437 [DutyScan_Calibration_Flow] ====Done====
2421 11:49:37.409518
2422 11:49:37.412662 [DutyScan_Calibration_Flow] k_type=1
2423 11:49:37.429047
2424 11:49:37.429130 ==DQS 0 ==
2425 11:49:37.432155 Final DQS duty delay cell = 0
2426 11:49:37.435398 [0] MAX Duty = 5094%(X100), DQS PI = 24
2427 11:49:37.439351 [0] MIN Duty = 4875%(X100), DQS PI = 0
2428 11:49:37.439432 [0] AVG Duty = 4984%(X100)
2429 11:49:37.442009
2430 11:49:37.442090 ==DQS 1 ==
2431 11:49:37.445570 Final DQS duty delay cell = 0
2432 11:49:37.448685 [0] MAX Duty = 5187%(X100), DQS PI = 20
2433 11:49:37.452004 [0] MIN Duty = 4938%(X100), DQS PI = 58
2434 11:49:37.452079 [0] AVG Duty = 5062%(X100)
2435 11:49:37.455431
2436 11:49:37.458660 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2437 11:49:37.458736
2438 11:49:37.462470 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2439 11:49:37.465439 [DutyScan_Calibration_Flow] ====Done====
2440 11:49:37.465535
2441 11:49:37.468732 [DutyScan_Calibration_Flow] k_type=3
2442 11:49:37.485447
2443 11:49:37.485558 ==DQM 0 ==
2444 11:49:37.488733 Final DQM duty delay cell = 0
2445 11:49:37.492415 [0] MAX Duty = 5156%(X100), DQS PI = 6
2446 11:49:37.495429 [0] MIN Duty = 5031%(X100), DQS PI = 0
2447 11:49:37.495500 [0] AVG Duty = 5093%(X100)
2448 11:49:37.495561
2449 11:49:37.498678 ==DQM 1 ==
2450 11:49:37.502549 Final DQM duty delay cell = 0
2451 11:49:37.505602 [0] MAX Duty = 5031%(X100), DQS PI = 16
2452 11:49:37.508889 [0] MIN Duty = 4907%(X100), DQS PI = 36
2453 11:49:37.508986 [0] AVG Duty = 4969%(X100)
2454 11:49:37.509075
2455 11:49:37.515259 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2456 11:49:37.515336
2457 11:49:37.519141 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2458 11:49:37.522333 [DutyScan_Calibration_Flow] ====Done====
2459 11:49:37.522413
2460 11:49:37.525551 [DutyScan_Calibration_Flow] k_type=2
2461 11:49:37.541192
2462 11:49:37.541294 ==DQ 0 ==
2463 11:49:37.544428 Final DQ duty delay cell = -4
2464 11:49:37.547622 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2465 11:49:37.550950 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2466 11:49:37.554990 [-4] AVG Duty = 5000%(X100)
2467 11:49:37.555062
2468 11:49:37.555123 ==DQ 1 ==
2469 11:49:37.558095 Final DQ duty delay cell = 0
2470 11:49:37.561449 [0] MAX Duty = 5125%(X100), DQS PI = 20
2471 11:49:37.564586 [0] MIN Duty = 4938%(X100), DQS PI = 34
2472 11:49:37.564683 [0] AVG Duty = 5031%(X100)
2473 11:49:37.567571
2474 11:49:37.570951 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2475 11:49:37.571019
2476 11:49:37.574228 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2477 11:49:37.578211 [DutyScan_Calibration_Flow] ====Done====
2478 11:49:37.581315 nWR fixed to 30
2479 11:49:37.581446 [ModeRegInit_LP4] CH0 RK0
2480 11:49:37.584656 [ModeRegInit_LP4] CH0 RK1
2481 11:49:37.588165 [ModeRegInit_LP4] CH1 RK0
2482 11:49:37.588267 [ModeRegInit_LP4] CH1 RK1
2483 11:49:37.591077 match AC timing 7
2484 11:49:37.594928 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2485 11:49:37.597733 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2486 11:49:37.604888 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2487 11:49:37.607841 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2488 11:49:37.614873 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2489 11:49:37.614969 ==
2490 11:49:37.617999 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 11:49:37.621260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 11:49:37.621332 ==
2493 11:49:37.627958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 11:49:37.631862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 11:49:37.641166 [CA 0] Center 39 (8~70) winsize 63
2496 11:49:37.644733 [CA 1] Center 39 (8~70) winsize 63
2497 11:49:37.647993 [CA 2] Center 35 (5~66) winsize 62
2498 11:49:37.651987 [CA 3] Center 34 (4~65) winsize 62
2499 11:49:37.654836 [CA 4] Center 33 (3~64) winsize 62
2500 11:49:37.658470 [CA 5] Center 32 (3~62) winsize 60
2501 11:49:37.658551
2502 11:49:37.661872 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2503 11:49:37.661952
2504 11:49:37.665083 [CATrainingPosCal] consider 1 rank data
2505 11:49:37.668384 u2DelayCellTimex100 = 270/100 ps
2506 11:49:37.671618 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2507 11:49:37.675106 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2508 11:49:37.681859 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2509 11:49:37.684872 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2510 11:49:37.688422 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2511 11:49:37.691456 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2512 11:49:37.691537
2513 11:49:37.694653 CA PerBit enable=1, Macro0, CA PI delay=32
2514 11:49:37.694735
2515 11:49:37.698259 [CBTSetCACLKResult] CA Dly = 32
2516 11:49:37.698355 CS Dly: 6 (0~37)
2517 11:49:37.698449 ==
2518 11:49:37.701364 Dram Type= 6, Freq= 0, CH_0, rank 1
2519 11:49:37.707890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 11:49:37.707971 ==
2521 11:49:37.711831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 11:49:37.718377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 11:49:37.727267 [CA 0] Center 38 (8~69) winsize 62
2524 11:49:37.730391 [CA 1] Center 38 (8~69) winsize 62
2525 11:49:37.733599 [CA 2] Center 35 (4~66) winsize 63
2526 11:49:37.737011 [CA 3] Center 34 (4~65) winsize 62
2527 11:49:37.740791 [CA 4] Center 33 (3~64) winsize 62
2528 11:49:37.743894 [CA 5] Center 32 (3~62) winsize 60
2529 11:49:37.744000
2530 11:49:37.746906 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 11:49:37.746987
2532 11:49:37.750630 [CATrainingPosCal] consider 2 rank data
2533 11:49:37.753815 u2DelayCellTimex100 = 270/100 ps
2534 11:49:37.757093 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2535 11:49:37.760311 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2536 11:49:37.767409 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2537 11:49:37.770577 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2538 11:49:37.773825 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2539 11:49:37.777076 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2540 11:49:37.777157
2541 11:49:37.780310 CA PerBit enable=1, Macro0, CA PI delay=32
2542 11:49:37.780391
2543 11:49:37.784289 [CBTSetCACLKResult] CA Dly = 32
2544 11:49:37.784370 CS Dly: 6 (0~38)
2545 11:49:37.784434
2546 11:49:37.787259 ----->DramcWriteLeveling(PI) begin...
2547 11:49:37.790353 ==
2548 11:49:37.794102 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 11:49:37.797165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 11:49:37.797255 ==
2551 11:49:37.800692 Write leveling (Byte 0): 32 => 32
2552 11:49:37.803863 Write leveling (Byte 1): 30 => 30
2553 11:49:37.807185 DramcWriteLeveling(PI) end<-----
2554 11:49:37.807266
2555 11:49:37.807329 ==
2556 11:49:37.810949 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 11:49:37.814225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 11:49:37.814306 ==
2559 11:49:37.817380 [Gating] SW mode calibration
2560 11:49:37.823925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2561 11:49:37.827596 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2562 11:49:37.833994 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2563 11:49:37.837381 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2564 11:49:37.840482 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 11:49:37.847424 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 11:49:37.850398 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 11:49:37.853908 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 11:49:37.860319 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2569 11:49:37.863684 0 15 28 | B1->B0 | 3333 2424 | 0 0 | (0 0) (1 0)
2570 11:49:37.866926 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2571 11:49:37.874148 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 11:49:37.877385 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 11:49:37.880697 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 11:49:37.887646 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 11:49:37.891001 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 11:49:37.894207 1 0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2577 11:49:37.897331 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2578 11:49:37.904329 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2579 11:49:37.907327 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 11:49:37.910985 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 11:49:37.917550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 11:49:37.920793 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 11:49:37.923986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 11:49:37.931226 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 11:49:37.934501 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 11:49:37.937733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2587 11:49:37.944427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 11:49:37.947406 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 11:49:37.951120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:49:37.957479 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:49:37.960932 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:49:37.964208 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:49:37.967452 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:49:37.974690 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 11:49:37.977912 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:49:37.981338 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:49:37.987847 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:49:37.990858 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:49:37.994757 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:49:38.001065 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:49:38.004260 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2602 11:49:38.008223 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 11:49:38.011371 Total UI for P1: 0, mck2ui 16
2604 11:49:38.014328 best dqsien dly found for B0: ( 1, 3, 28)
2605 11:49:38.021124 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:49:38.021206 Total UI for P1: 0, mck2ui 16
2607 11:49:38.027647 best dqsien dly found for B1: ( 1, 4, 0)
2608 11:49:38.031041 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2609 11:49:38.034426 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2610 11:49:38.034528
2611 11:49:38.037708 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2612 11:49:38.040927 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2613 11:49:38.044700 [Gating] SW calibration Done
2614 11:49:38.044780 ==
2615 11:49:38.047932 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 11:49:38.051405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 11:49:38.051487 ==
2618 11:49:38.054460 RX Vref Scan: 0
2619 11:49:38.054552
2620 11:49:38.054627 RX Vref 0 -> 0, step: 1
2621 11:49:38.054690
2622 11:49:38.057787 RX Delay -40 -> 252, step: 8
2623 11:49:38.061505 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2624 11:49:38.064639 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2625 11:49:38.071206 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2626 11:49:38.074959 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2627 11:49:38.078119 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2628 11:49:38.081306 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2629 11:49:38.084517 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2630 11:49:38.091343 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2631 11:49:38.094775 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2632 11:49:38.097736 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2633 11:49:38.101253 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2634 11:49:38.104776 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2635 11:49:38.111521 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2636 11:49:38.114755 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2637 11:49:38.117857 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2638 11:49:38.121427 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2639 11:49:38.121509 ==
2640 11:49:38.124490 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 11:49:38.128221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 11:49:38.131393 ==
2643 11:49:38.131474 DQS Delay:
2644 11:49:38.131539 DQS0 = 0, DQS1 = 0
2645 11:49:38.134402 DQM Delay:
2646 11:49:38.134484 DQM0 = 121, DQM1 = 113
2647 11:49:38.137973 DQ Delay:
2648 11:49:38.141605 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2649 11:49:38.144828 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2650 11:49:38.148147 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2651 11:49:38.151422 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2652 11:49:38.151503
2653 11:49:38.151567
2654 11:49:38.151626 ==
2655 11:49:38.154636 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 11:49:38.157744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 11:49:38.157827 ==
2658 11:49:38.157890
2659 11:49:38.161052
2660 11:49:38.161132 TX Vref Scan disable
2661 11:49:38.164898 == TX Byte 0 ==
2662 11:49:38.168064 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2663 11:49:38.171358 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2664 11:49:38.174549 == TX Byte 1 ==
2665 11:49:38.177843 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2666 11:49:38.181706 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2667 11:49:38.181787 ==
2668 11:49:38.184452 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 11:49:38.191387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 11:49:38.191468 ==
2671 11:49:38.201614 TX Vref=22, minBit 0, minWin=25, winSum=411
2672 11:49:38.205054 TX Vref=24, minBit 0, minWin=25, winSum=414
2673 11:49:38.208116 TX Vref=26, minBit 0, minWin=26, winSum=421
2674 11:49:38.211371 TX Vref=28, minBit 0, minWin=26, winSum=423
2675 11:49:38.215288 TX Vref=30, minBit 1, minWin=26, winSum=427
2676 11:49:38.218421 TX Vref=32, minBit 0, minWin=26, winSum=425
2677 11:49:38.225283 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2678 11:49:38.225365
2679 11:49:38.228785 Final TX Range 1 Vref 30
2680 11:49:38.228866
2681 11:49:38.228930 ==
2682 11:49:38.231399 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:49:38.234974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:49:38.235056 ==
2685 11:49:38.235120
2686 11:49:38.238304
2687 11:49:38.238385 TX Vref Scan disable
2688 11:49:38.241787 == TX Byte 0 ==
2689 11:49:38.245185 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2690 11:49:38.248619 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2691 11:49:38.251827 == TX Byte 1 ==
2692 11:49:38.254974 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2693 11:49:38.258703 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2694 11:49:38.258784
2695 11:49:38.261533 [DATLAT]
2696 11:49:38.261664 Freq=1200, CH0 RK0
2697 11:49:38.261732
2698 11:49:38.265328 DATLAT Default: 0xd
2699 11:49:38.265403 0, 0xFFFF, sum = 0
2700 11:49:38.268608 1, 0xFFFF, sum = 0
2701 11:49:38.268708 2, 0xFFFF, sum = 0
2702 11:49:38.271675 3, 0xFFFF, sum = 0
2703 11:49:38.271786 4, 0xFFFF, sum = 0
2704 11:49:38.275134 5, 0xFFFF, sum = 0
2705 11:49:38.275213 6, 0xFFFF, sum = 0
2706 11:49:38.278378 7, 0xFFFF, sum = 0
2707 11:49:38.278458 8, 0xFFFF, sum = 0
2708 11:49:38.281734 9, 0xFFFF, sum = 0
2709 11:49:38.281847 10, 0xFFFF, sum = 0
2710 11:49:38.285080 11, 0xFFFF, sum = 0
2711 11:49:38.285185 12, 0x0, sum = 1
2712 11:49:38.288174 13, 0x0, sum = 2
2713 11:49:38.288280 14, 0x0, sum = 3
2714 11:49:38.292030 15, 0x0, sum = 4
2715 11:49:38.292133 best_step = 13
2716 11:49:38.292221
2717 11:49:38.292318 ==
2718 11:49:38.295393 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 11:49:38.301828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 11:49:38.301906 ==
2721 11:49:38.301970 RX Vref Scan: 1
2722 11:49:38.302034
2723 11:49:38.305019 Set Vref Range= 32 -> 127
2724 11:49:38.305119
2725 11:49:38.308378 RX Vref 32 -> 127, step: 1
2726 11:49:38.308476
2727 11:49:38.312046 RX Delay -13 -> 252, step: 4
2728 11:49:38.312144
2729 11:49:38.315326 Set Vref, RX VrefLevel [Byte0]: 32
2730 11:49:38.318587 [Byte1]: 32
2731 11:49:38.318686
2732 11:49:38.321875 Set Vref, RX VrefLevel [Byte0]: 33
2733 11:49:38.325207 [Byte1]: 33
2734 11:49:38.325317
2735 11:49:38.328518 Set Vref, RX VrefLevel [Byte0]: 34
2736 11:49:38.331746 [Byte1]: 34
2737 11:49:38.335564
2738 11:49:38.335664 Set Vref, RX VrefLevel [Byte0]: 35
2739 11:49:38.338956 [Byte1]: 35
2740 11:49:38.343251
2741 11:49:38.343343 Set Vref, RX VrefLevel [Byte0]: 36
2742 11:49:38.346934 [Byte1]: 36
2743 11:49:38.351380
2744 11:49:38.351482 Set Vref, RX VrefLevel [Byte0]: 37
2745 11:49:38.354568 [Byte1]: 37
2746 11:49:38.359148
2747 11:49:38.359248 Set Vref, RX VrefLevel [Byte0]: 38
2748 11:49:38.362401 [Byte1]: 38
2749 11:49:38.367356
2750 11:49:38.367453 Set Vref, RX VrefLevel [Byte0]: 39
2751 11:49:38.370327 [Byte1]: 39
2752 11:49:38.375291
2753 11:49:38.375368 Set Vref, RX VrefLevel [Byte0]: 40
2754 11:49:38.378463 [Byte1]: 40
2755 11:49:38.383215
2756 11:49:38.383313 Set Vref, RX VrefLevel [Byte0]: 41
2757 11:49:38.386072 [Byte1]: 41
2758 11:49:38.390994
2759 11:49:38.391122 Set Vref, RX VrefLevel [Byte0]: 42
2760 11:49:38.394031 [Byte1]: 42
2761 11:49:38.398827
2762 11:49:38.398951 Set Vref, RX VrefLevel [Byte0]: 43
2763 11:49:38.401927 [Byte1]: 43
2764 11:49:38.406645
2765 11:49:38.406727 Set Vref, RX VrefLevel [Byte0]: 44
2766 11:49:38.410002 [Byte1]: 44
2767 11:49:38.414436
2768 11:49:38.414518 Set Vref, RX VrefLevel [Byte0]: 45
2769 11:49:38.417712 [Byte1]: 45
2770 11:49:38.422319
2771 11:49:38.422401 Set Vref, RX VrefLevel [Byte0]: 46
2772 11:49:38.425713 [Byte1]: 46
2773 11:49:38.430236
2774 11:49:38.430318 Set Vref, RX VrefLevel [Byte0]: 47
2775 11:49:38.433667 [Byte1]: 47
2776 11:49:38.438399
2777 11:49:38.438506 Set Vref, RX VrefLevel [Byte0]: 48
2778 11:49:38.441511 [Byte1]: 48
2779 11:49:38.446231
2780 11:49:38.446330 Set Vref, RX VrefLevel [Byte0]: 49
2781 11:49:38.449407 [Byte1]: 49
2782 11:49:38.453733
2783 11:49:38.453834 Set Vref, RX VrefLevel [Byte0]: 50
2784 11:49:38.457275 [Byte1]: 50
2785 11:49:38.461877
2786 11:49:38.461965 Set Vref, RX VrefLevel [Byte0]: 51
2787 11:49:38.465228 [Byte1]: 51
2788 11:49:38.469713
2789 11:49:38.469786 Set Vref, RX VrefLevel [Byte0]: 52
2790 11:49:38.472965 [Byte1]: 52
2791 11:49:38.477314
2792 11:49:38.477427 Set Vref, RX VrefLevel [Byte0]: 53
2793 11:49:38.481328 [Byte1]: 53
2794 11:49:38.485948
2795 11:49:38.486052 Set Vref, RX VrefLevel [Byte0]: 54
2796 11:49:38.489226 [Byte1]: 54
2797 11:49:38.493666
2798 11:49:38.493740 Set Vref, RX VrefLevel [Byte0]: 55
2799 11:49:38.496703 [Byte1]: 55
2800 11:49:38.501164
2801 11:49:38.501264 Set Vref, RX VrefLevel [Byte0]: 56
2802 11:49:38.504419 [Byte1]: 56
2803 11:49:38.509203
2804 11:49:38.509302 Set Vref, RX VrefLevel [Byte0]: 57
2805 11:49:38.512231 [Byte1]: 57
2806 11:49:38.517316
2807 11:49:38.517423 Set Vref, RX VrefLevel [Byte0]: 58
2808 11:49:38.520346 [Byte1]: 58
2809 11:49:38.524930
2810 11:49:38.525009 Set Vref, RX VrefLevel [Byte0]: 59
2811 11:49:38.528569 [Byte1]: 59
2812 11:49:38.532825
2813 11:49:38.532899 Set Vref, RX VrefLevel [Byte0]: 60
2814 11:49:38.536281 [Byte1]: 60
2815 11:49:38.540788
2816 11:49:38.540891 Set Vref, RX VrefLevel [Byte0]: 61
2817 11:49:38.544502 [Byte1]: 61
2818 11:49:38.548495
2819 11:49:38.548594 Set Vref, RX VrefLevel [Byte0]: 62
2820 11:49:38.552357 [Byte1]: 62
2821 11:49:38.556438
2822 11:49:38.556511 Set Vref, RX VrefLevel [Byte0]: 63
2823 11:49:38.560077 [Byte1]: 63
2824 11:49:38.564320
2825 11:49:38.564428 Set Vref, RX VrefLevel [Byte0]: 64
2826 11:49:38.567882 [Byte1]: 64
2827 11:49:38.572283
2828 11:49:38.572381 Set Vref, RX VrefLevel [Byte0]: 65
2829 11:49:38.575535 [Byte1]: 65
2830 11:49:38.580155
2831 11:49:38.580261 Set Vref, RX VrefLevel [Byte0]: 66
2832 11:49:38.583267 [Byte1]: 66
2833 11:49:38.588359
2834 11:49:38.588469 Set Vref, RX VrefLevel [Byte0]: 67
2835 11:49:38.591752 [Byte1]: 67
2836 11:49:38.596189
2837 11:49:38.596286 Set Vref, RX VrefLevel [Byte0]: 68
2838 11:49:38.599467 [Byte1]: 68
2839 11:49:38.603989
2840 11:49:38.604089 Set Vref, RX VrefLevel [Byte0]: 69
2841 11:49:38.607157 [Byte1]: 69
2842 11:49:38.611879
2843 11:49:38.611985 Final RX Vref Byte 0 = 56 to rank0
2844 11:49:38.615051 Final RX Vref Byte 1 = 47 to rank0
2845 11:49:38.618795 Final RX Vref Byte 0 = 56 to rank1
2846 11:49:38.622032 Final RX Vref Byte 1 = 47 to rank1==
2847 11:49:38.625284 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 11:49:38.628373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 11:49:38.632311 ==
2850 11:49:38.632440 DQS Delay:
2851 11:49:38.632543 DQS0 = 0, DQS1 = 0
2852 11:49:38.635109 DQM Delay:
2853 11:49:38.635246 DQM0 = 120, DQM1 = 111
2854 11:49:38.638483 DQ Delay:
2855 11:49:38.642046 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2856 11:49:38.645078 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2857 11:49:38.648533 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
2858 11:49:38.652157 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2859 11:49:38.652262
2860 11:49:38.652352
2861 11:49:38.658540 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2862 11:49:38.661862 CH0 RK0: MR19=404, MR18=120B
2863 11:49:38.668828 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2864 11:49:38.668907
2865 11:49:38.671879 ----->DramcWriteLeveling(PI) begin...
2866 11:49:38.671954 ==
2867 11:49:38.675531 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 11:49:38.678494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 11:49:38.678577 ==
2870 11:49:38.681777 Write leveling (Byte 0): 35 => 35
2871 11:49:38.685046 Write leveling (Byte 1): 30 => 30
2872 11:49:38.688803 DramcWriteLeveling(PI) end<-----
2873 11:49:38.688884
2874 11:49:38.688948 ==
2875 11:49:38.692180 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 11:49:38.698735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 11:49:38.698817 ==
2878 11:49:38.698882 [Gating] SW mode calibration
2879 11:49:38.708680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 11:49:38.711891 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 11:49:38.715475 0 15 0 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
2882 11:49:38.722260 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 11:49:38.725564 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 11:49:38.728639 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 11:49:38.735749 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 11:49:38.738922 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 11:49:38.742014 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 11:49:38.748671 0 15 28 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
2889 11:49:38.752019 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 11:49:38.755929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 11:49:38.762283 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 11:49:38.765466 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 11:49:38.769238 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 11:49:38.772390 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 11:49:38.778867 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2896 11:49:38.782566 1 0 28 | B1->B0 | 3f3f 3f3e | 0 1 | (0 0) (1 1)
2897 11:49:38.785397 1 1 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
2898 11:49:38.792256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 11:49:38.795901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 11:49:38.799110 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 11:49:38.805518 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 11:49:38.809274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 11:49:38.812516 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 11:49:38.818922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2905 11:49:38.822452 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2906 11:49:38.826180 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 11:49:38.832459 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 11:49:38.835807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 11:49:38.838907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 11:49:38.842300 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 11:49:38.849160 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 11:49:38.852266 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 11:49:38.855965 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 11:49:38.862697 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 11:49:38.865875 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 11:49:38.869176 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 11:49:38.876312 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 11:49:38.879047 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 11:49:38.882785 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:49:38.889473 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2921 11:49:38.892741 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:49:38.895831 Total UI for P1: 0, mck2ui 16
2923 11:49:38.899598 best dqsien dly found for B0: ( 1, 3, 28)
2924 11:49:38.902925 Total UI for P1: 0, mck2ui 16
2925 11:49:38.906472 best dqsien dly found for B1: ( 1, 3, 28)
2926 11:49:38.909744 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2927 11:49:38.912510 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2928 11:49:38.912591
2929 11:49:38.915713 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2930 11:49:38.919398 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2931 11:49:38.922358 [Gating] SW calibration Done
2932 11:49:38.922462 ==
2933 11:49:38.926211 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 11:49:38.929028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 11:49:38.929109 ==
2936 11:49:38.933014 RX Vref Scan: 0
2937 11:49:38.933095
2938 11:49:38.935789 RX Vref 0 -> 0, step: 1
2939 11:49:38.935870
2940 11:49:38.935934 RX Delay -40 -> 252, step: 8
2941 11:49:38.942637 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2942 11:49:38.945851 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 11:49:38.949162 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2944 11:49:38.953051 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2945 11:49:38.956228 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2946 11:49:38.962895 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2947 11:49:38.965870 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 11:49:38.969420 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2949 11:49:38.972538 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2950 11:49:38.975955 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2951 11:49:38.982473 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2952 11:49:38.986238 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2953 11:49:38.989503 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2954 11:49:38.992643 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2955 11:49:38.996019 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2956 11:49:39.002609 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2957 11:49:39.002691 ==
2958 11:49:39.005894 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 11:49:39.009179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 11:49:39.009261 ==
2961 11:49:39.009326 DQS Delay:
2962 11:49:39.012522 DQS0 = 0, DQS1 = 0
2963 11:49:39.012603 DQM Delay:
2964 11:49:39.016414 DQM0 = 121, DQM1 = 112
2965 11:49:39.016496 DQ Delay:
2966 11:49:39.019678 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2967 11:49:39.022734 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2968 11:49:39.025892 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2969 11:49:39.029233 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2970 11:49:39.029338
2971 11:49:39.029427
2972 11:49:39.029534 ==
2973 11:49:39.032628 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 11:49:39.039150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 11:49:39.039251 ==
2976 11:49:39.039350
2977 11:49:39.039437
2978 11:49:39.039529 TX Vref Scan disable
2979 11:49:39.043041 == TX Byte 0 ==
2980 11:49:39.046719 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2981 11:49:39.052958 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2982 11:49:39.053065 == TX Byte 1 ==
2983 11:49:39.056507 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2984 11:49:39.059734 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2985 11:49:39.063044 ==
2986 11:49:39.066612 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 11:49:39.070062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 11:49:39.070145 ==
2989 11:49:39.081818 TX Vref=22, minBit 1, minWin=25, winSum=416
2990 11:49:39.085211 TX Vref=24, minBit 3, minWin=25, winSum=420
2991 11:49:39.088172 TX Vref=26, minBit 3, minWin=25, winSum=426
2992 11:49:39.091394 TX Vref=28, minBit 5, minWin=25, winSum=430
2993 11:49:39.095384 TX Vref=30, minBit 5, minWin=25, winSum=428
2994 11:49:39.098067 TX Vref=32, minBit 0, minWin=25, winSum=425
2995 11:49:39.105410 [TxChooseVref] Worse bit 5, Min win 25, Win sum 430, Final Vref 28
2996 11:49:39.105526
2997 11:49:39.108723 Final TX Range 1 Vref 28
2998 11:49:39.108843
2999 11:49:39.108907 ==
3000 11:49:39.112008 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 11:49:39.115260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 11:49:39.115424 ==
3003 11:49:39.115495
3004 11:49:39.115556
3005 11:49:39.118480 TX Vref Scan disable
3006 11:49:39.121725 == TX Byte 0 ==
3007 11:49:39.124921 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3008 11:49:39.128174 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3009 11:49:39.131347 == TX Byte 1 ==
3010 11:49:39.135260 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3011 11:49:39.138458 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3012 11:49:39.138532
3013 11:49:39.141800 [DATLAT]
3014 11:49:39.141871 Freq=1200, CH0 RK1
3015 11:49:39.141944
3016 11:49:39.145084 DATLAT Default: 0xd
3017 11:49:39.145188 0, 0xFFFF, sum = 0
3018 11:49:39.148356 1, 0xFFFF, sum = 0
3019 11:49:39.148462 2, 0xFFFF, sum = 0
3020 11:49:39.151544 3, 0xFFFF, sum = 0
3021 11:49:39.151616 4, 0xFFFF, sum = 0
3022 11:49:39.154901 5, 0xFFFF, sum = 0
3023 11:49:39.154973 6, 0xFFFF, sum = 0
3024 11:49:39.158121 7, 0xFFFF, sum = 0
3025 11:49:39.158198 8, 0xFFFF, sum = 0
3026 11:49:39.161696 9, 0xFFFF, sum = 0
3027 11:49:39.165264 10, 0xFFFF, sum = 0
3028 11:49:39.165346 11, 0xFFFF, sum = 0
3029 11:49:39.168112 12, 0x0, sum = 1
3030 11:49:39.168194 13, 0x0, sum = 2
3031 11:49:39.168273 14, 0x0, sum = 3
3032 11:49:39.171766 15, 0x0, sum = 4
3033 11:49:39.171848 best_step = 13
3034 11:49:39.171913
3035 11:49:39.174983 ==
3036 11:49:39.175069 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 11:49:39.181805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 11:49:39.181894 ==
3039 11:49:39.181958 RX Vref Scan: 0
3040 11:49:39.182019
3041 11:49:39.185073 RX Vref 0 -> 0, step: 1
3042 11:49:39.185157
3043 11:49:39.188302 RX Delay -13 -> 252, step: 4
3044 11:49:39.191619 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3045 11:49:39.194966 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3046 11:49:39.201874 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3047 11:49:39.205176 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3048 11:49:39.208613 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3049 11:49:39.211510 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3050 11:49:39.215139 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3051 11:49:39.221955 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3052 11:49:39.225163 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3053 11:49:39.228495 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3054 11:49:39.231617 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3055 11:49:39.235377 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3056 11:49:39.241872 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3057 11:49:39.245599 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3058 11:49:39.248983 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3059 11:49:39.252212 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3060 11:49:39.252294 ==
3061 11:49:39.255389 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 11:49:39.258622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 11:49:39.262025 ==
3064 11:49:39.262122 DQS Delay:
3065 11:49:39.262201 DQS0 = 0, DQS1 = 0
3066 11:49:39.265318 DQM Delay:
3067 11:49:39.265399 DQM0 = 121, DQM1 = 109
3068 11:49:39.269088 DQ Delay:
3069 11:49:39.272439 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3070 11:49:39.275530 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3071 11:49:39.278735 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3072 11:49:39.281860 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3073 11:49:39.282003
3074 11:49:39.282118
3075 11:49:39.288439 [DQSOSCAuto] RK1, (LSB)MR18= 0xdef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3076 11:49:39.292229 CH0 RK1: MR19=403, MR18=DEF
3077 11:49:39.298629 CH0_RK1: MR19=0x403, MR18=0xDEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3078 11:49:39.301946 [RxdqsGatingPostProcess] freq 1200
3079 11:49:39.308527 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 11:49:39.308629 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 11:49:39.312276 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 11:49:39.315693 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 11:49:39.318985 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 11:49:39.322130 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 11:49:39.325509 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 11:49:39.328465 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 11:49:39.331778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 11:49:39.335345 Pre-setting of DQS Precalculation
3089 11:49:39.338703 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 11:49:39.338811 ==
3091 11:49:39.342053 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 11:49:39.348743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 11:49:39.348834 ==
3094 11:49:39.351823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 11:49:39.358381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 11:49:39.367485 [CA 0] Center 37 (7~68) winsize 62
3097 11:49:39.370808 [CA 1] Center 37 (7~68) winsize 62
3098 11:49:39.374693 [CA 2] Center 35 (5~65) winsize 61
3099 11:49:39.377949 [CA 3] Center 34 (5~64) winsize 60
3100 11:49:39.381119 [CA 4] Center 34 (4~64) winsize 61
3101 11:49:39.384398 [CA 5] Center 33 (3~63) winsize 61
3102 11:49:39.384496
3103 11:49:39.387492 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 11:49:39.387571
3105 11:49:39.391440 [CATrainingPosCal] consider 1 rank data
3106 11:49:39.394526 u2DelayCellTimex100 = 270/100 ps
3107 11:49:39.397837 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 11:49:39.401092 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 11:49:39.404349 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 11:49:39.411355 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3111 11:49:39.414625 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 11:49:39.417721 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3113 11:49:39.417797
3114 11:49:39.421367 CA PerBit enable=1, Macro0, CA PI delay=33
3115 11:49:39.421444
3116 11:49:39.424808 [CBTSetCACLKResult] CA Dly = 33
3117 11:49:39.424911 CS Dly: 8 (0~39)
3118 11:49:39.424992 ==
3119 11:49:39.428002 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 11:49:39.434576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 11:49:39.434655 ==
3122 11:49:39.437782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 11:49:39.444219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3124 11:49:39.453030 [CA 0] Center 37 (7~68) winsize 62
3125 11:49:39.456469 [CA 1] Center 37 (7~68) winsize 62
3126 11:49:39.460074 [CA 2] Center 35 (5~65) winsize 61
3127 11:49:39.463075 [CA 3] Center 34 (4~65) winsize 62
3128 11:49:39.466599 [CA 4] Center 34 (4~65) winsize 62
3129 11:49:39.469942 [CA 5] Center 34 (4~64) winsize 61
3130 11:49:39.470016
3131 11:49:39.473754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3132 11:49:39.473830
3133 11:49:39.476507 [CATrainingPosCal] consider 2 rank data
3134 11:49:39.479491 u2DelayCellTimex100 = 270/100 ps
3135 11:49:39.483541 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 11:49:39.486549 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 11:49:39.492978 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 11:49:39.496803 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3139 11:49:39.500139 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 11:49:39.503386 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3141 11:49:39.503462
3142 11:49:39.506615 CA PerBit enable=1, Macro0, CA PI delay=33
3143 11:49:39.506691
3144 11:49:39.509805 [CBTSetCACLKResult] CA Dly = 33
3145 11:49:39.509877 CS Dly: 8 (0~40)
3146 11:49:39.509956
3147 11:49:39.512962 ----->DramcWriteLeveling(PI) begin...
3148 11:49:39.516831 ==
3149 11:49:39.516907 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 11:49:39.523349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 11:49:39.523426 ==
3152 11:49:39.526543 Write leveling (Byte 0): 25 => 25
3153 11:49:39.530204 Write leveling (Byte 1): 27 => 27
3154 11:49:39.533137 DramcWriteLeveling(PI) end<-----
3155 11:49:39.533210
3156 11:49:39.533291 ==
3157 11:49:39.536721 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 11:49:39.540029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 11:49:39.540103 ==
3160 11:49:39.543304 [Gating] SW mode calibration
3161 11:49:39.549721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 11:49:39.553755 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 11:49:39.560217 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 11:49:39.563534 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 11:49:39.566506 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 11:49:39.573475 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 11:49:39.576355 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 11:49:39.579754 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 11:49:39.586985 0 15 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
3170 11:49:39.589753 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3171 11:49:39.593211 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 11:49:39.599725 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 11:49:39.603184 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 11:49:39.606958 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 11:49:39.613381 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 11:49:39.617058 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 11:49:39.620079 1 0 24 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (0 0)
3178 11:49:39.623359 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 11:49:39.629980 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 11:49:39.633803 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 11:49:39.636930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 11:49:39.643859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 11:49:39.647109 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 11:49:39.650251 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 11:49:39.656774 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3186 11:49:39.660574 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3187 11:49:39.663942 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 11:49:39.670309 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 11:49:39.673464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 11:49:39.677450 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 11:49:39.680547 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 11:49:39.687005 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 11:49:39.690670 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 11:49:39.693896 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 11:49:39.700486 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 11:49:39.704030 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 11:49:39.707254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 11:49:39.714019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 11:49:39.717481 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 11:49:39.720554 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 11:49:39.727433 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3202 11:49:39.730804 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3203 11:49:39.733627 Total UI for P1: 0, mck2ui 16
3204 11:49:39.737086 best dqsien dly found for B1: ( 1, 3, 24)
3205 11:49:39.740752 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:49:39.744068 Total UI for P1: 0, mck2ui 16
3207 11:49:39.747073 best dqsien dly found for B0: ( 1, 3, 26)
3208 11:49:39.750585 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3209 11:49:39.753978 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3210 11:49:39.754053
3211 11:49:39.757263 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3212 11:49:39.763754 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3213 11:49:39.763834 [Gating] SW calibration Done
3214 11:49:39.763898 ==
3215 11:49:39.767702 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 11:49:39.774243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 11:49:39.774324 ==
3218 11:49:39.774406 RX Vref Scan: 0
3219 11:49:39.774483
3220 11:49:39.777446 RX Vref 0 -> 0, step: 1
3221 11:49:39.777520
3222 11:49:39.780605 RX Delay -40 -> 252, step: 8
3223 11:49:39.784484 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3224 11:49:39.787648 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3225 11:49:39.790855 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3226 11:49:39.797683 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3227 11:49:39.801209 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3228 11:49:39.804299 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3229 11:49:39.807533 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3230 11:49:39.811292 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3231 11:49:39.814159 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3232 11:49:39.820652 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3233 11:49:39.824407 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3234 11:49:39.827586 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3235 11:49:39.830841 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3236 11:49:39.837320 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3237 11:49:39.840778 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3238 11:49:39.843846 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3239 11:49:39.843921 ==
3240 11:49:39.847326 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 11:49:39.850698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 11:49:39.850776 ==
3243 11:49:39.854200 DQS Delay:
3244 11:49:39.854275 DQS0 = 0, DQS1 = 0
3245 11:49:39.854359 DQM Delay:
3246 11:49:39.857559 DQM0 = 120, DQM1 = 116
3247 11:49:39.857642 DQ Delay:
3248 11:49:39.860932 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3249 11:49:39.864380 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3250 11:49:39.871072 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3251 11:49:39.874405 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3252 11:49:39.874477
3253 11:49:39.874577
3254 11:49:39.874682 ==
3255 11:49:39.877632 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 11:49:39.880862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 11:49:39.880944 ==
3258 11:49:39.881028
3259 11:49:39.881105
3260 11:49:39.884180 TX Vref Scan disable
3261 11:49:39.884271 == TX Byte 0 ==
3262 11:49:39.890637 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3263 11:49:39.893865 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3264 11:49:39.893947 == TX Byte 1 ==
3265 11:49:39.900634 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3266 11:49:39.904329 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3267 11:49:39.904406 ==
3268 11:49:39.907615 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 11:49:39.910918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 11:49:39.910992 ==
3271 11:49:39.923909 TX Vref=22, minBit 9, minWin=24, winSum=410
3272 11:49:39.926938 TX Vref=24, minBit 9, minWin=25, winSum=417
3273 11:49:39.930329 TX Vref=26, minBit 9, minWin=25, winSum=418
3274 11:49:39.933639 TX Vref=28, minBit 9, minWin=25, winSum=425
3275 11:49:39.936887 TX Vref=30, minBit 2, minWin=26, winSum=434
3276 11:49:39.940075 TX Vref=32, minBit 10, minWin=25, winSum=433
3277 11:49:39.947055 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 30
3278 11:49:39.947137
3279 11:49:39.950282 Final TX Range 1 Vref 30
3280 11:49:39.950355
3281 11:49:39.950436 ==
3282 11:49:39.954139 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 11:49:39.957191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 11:49:39.957264 ==
3285 11:49:39.957344
3286 11:49:39.957420
3287 11:49:39.960605 TX Vref Scan disable
3288 11:49:39.963856 == TX Byte 0 ==
3289 11:49:39.966971 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3290 11:49:39.970713 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3291 11:49:39.974109 == TX Byte 1 ==
3292 11:49:39.977302 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3293 11:49:39.980509 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3294 11:49:39.980610
3295 11:49:39.984143 [DATLAT]
3296 11:49:39.984223 Freq=1200, CH1 RK0
3297 11:49:39.984317
3298 11:49:39.987369 DATLAT Default: 0xd
3299 11:49:39.987451 0, 0xFFFF, sum = 0
3300 11:49:39.990574 1, 0xFFFF, sum = 0
3301 11:49:39.990657 2, 0xFFFF, sum = 0
3302 11:49:39.993822 3, 0xFFFF, sum = 0
3303 11:49:39.993904 4, 0xFFFF, sum = 0
3304 11:49:39.997033 5, 0xFFFF, sum = 0
3305 11:49:39.997115 6, 0xFFFF, sum = 0
3306 11:49:40.000327 7, 0xFFFF, sum = 0
3307 11:49:40.000409 8, 0xFFFF, sum = 0
3308 11:49:40.004275 9, 0xFFFF, sum = 0
3309 11:49:40.004357 10, 0xFFFF, sum = 0
3310 11:49:40.007201 11, 0xFFFF, sum = 0
3311 11:49:40.007284 12, 0x0, sum = 1
3312 11:49:40.010463 13, 0x0, sum = 2
3313 11:49:40.010545 14, 0x0, sum = 3
3314 11:49:40.013741 15, 0x0, sum = 4
3315 11:49:40.013824 best_step = 13
3316 11:49:40.013888
3317 11:49:40.013948 ==
3318 11:49:40.017729 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 11:49:40.024255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 11:49:40.024335 ==
3321 11:49:40.024420 RX Vref Scan: 1
3322 11:49:40.024500
3323 11:49:40.027163 Set Vref Range= 32 -> 127
3324 11:49:40.027239
3325 11:49:40.030579 RX Vref 32 -> 127, step: 1
3326 11:49:40.030657
3327 11:49:40.030774 RX Delay -5 -> 252, step: 4
3328 11:49:40.030849
3329 11:49:40.034333 Set Vref, RX VrefLevel [Byte0]: 32
3330 11:49:40.037416 [Byte1]: 32
3331 11:49:40.041953
3332 11:49:40.042033 Set Vref, RX VrefLevel [Byte0]: 33
3333 11:49:40.045214 [Byte1]: 33
3334 11:49:40.049781
3335 11:49:40.049852 Set Vref, RX VrefLevel [Byte0]: 34
3336 11:49:40.053062 [Byte1]: 34
3337 11:49:40.057343
3338 11:49:40.057417 Set Vref, RX VrefLevel [Byte0]: 35
3339 11:49:40.060891 [Byte1]: 35
3340 11:49:40.065431
3341 11:49:40.065534 Set Vref, RX VrefLevel [Byte0]: 36
3342 11:49:40.068720 [Byte1]: 36
3343 11:49:40.072728
3344 11:49:40.072799 Set Vref, RX VrefLevel [Byte0]: 37
3345 11:49:40.076049 [Byte1]: 37
3346 11:49:40.081126
3347 11:49:40.081206 Set Vref, RX VrefLevel [Byte0]: 38
3348 11:49:40.084236 [Byte1]: 38
3349 11:49:40.088694
3350 11:49:40.088775 Set Vref, RX VrefLevel [Byte0]: 39
3351 11:49:40.091934 [Byte1]: 39
3352 11:49:40.097079
3353 11:49:40.097159 Set Vref, RX VrefLevel [Byte0]: 40
3354 11:49:40.099714 [Byte1]: 40
3355 11:49:40.104256
3356 11:49:40.104336 Set Vref, RX VrefLevel [Byte0]: 41
3357 11:49:40.107681 [Byte1]: 41
3358 11:49:40.112141
3359 11:49:40.112220 Set Vref, RX VrefLevel [Byte0]: 42
3360 11:49:40.115856 [Byte1]: 42
3361 11:49:40.120255
3362 11:49:40.120335 Set Vref, RX VrefLevel [Byte0]: 43
3363 11:49:40.123486 [Byte1]: 43
3364 11:49:40.128003
3365 11:49:40.128083 Set Vref, RX VrefLevel [Byte0]: 44
3366 11:49:40.131235 [Byte1]: 44
3367 11:49:40.135821
3368 11:49:40.135900 Set Vref, RX VrefLevel [Byte0]: 45
3369 11:49:40.139648 [Byte1]: 45
3370 11:49:40.144189
3371 11:49:40.144269 Set Vref, RX VrefLevel [Byte0]: 46
3372 11:49:40.147174 [Byte1]: 46
3373 11:49:40.151631
3374 11:49:40.151711 Set Vref, RX VrefLevel [Byte0]: 47
3375 11:49:40.154994 [Byte1]: 47
3376 11:49:40.159161
3377 11:49:40.159241 Set Vref, RX VrefLevel [Byte0]: 48
3378 11:49:40.162887 [Byte1]: 48
3379 11:49:40.167471
3380 11:49:40.167552 Set Vref, RX VrefLevel [Byte0]: 49
3381 11:49:40.170780 [Byte1]: 49
3382 11:49:40.175253
3383 11:49:40.175332 Set Vref, RX VrefLevel [Byte0]: 50
3384 11:49:40.178491 [Byte1]: 50
3385 11:49:40.182987
3386 11:49:40.183068 Set Vref, RX VrefLevel [Byte0]: 51
3387 11:49:40.186333 [Byte1]: 51
3388 11:49:40.190766
3389 11:49:40.190845 Set Vref, RX VrefLevel [Byte0]: 52
3390 11:49:40.193977 [Byte1]: 52
3391 11:49:40.198379
3392 11:49:40.198458 Set Vref, RX VrefLevel [Byte0]: 53
3393 11:49:40.202104 [Byte1]: 53
3394 11:49:40.206508
3395 11:49:40.206588 Set Vref, RX VrefLevel [Byte0]: 54
3396 11:49:40.210109 [Byte1]: 54
3397 11:49:40.214275
3398 11:49:40.214355 Set Vref, RX VrefLevel [Byte0]: 55
3399 11:49:40.217772 [Byte1]: 55
3400 11:49:40.222232
3401 11:49:40.222324 Set Vref, RX VrefLevel [Byte0]: 56
3402 11:49:40.225611 [Byte1]: 56
3403 11:49:40.230195
3404 11:49:40.230275 Set Vref, RX VrefLevel [Byte0]: 57
3405 11:49:40.233094 [Byte1]: 57
3406 11:49:40.237761
3407 11:49:40.237841 Set Vref, RX VrefLevel [Byte0]: 58
3408 11:49:40.241606 [Byte1]: 58
3409 11:49:40.246102
3410 11:49:40.246182 Set Vref, RX VrefLevel [Byte0]: 59
3411 11:49:40.249181 [Byte1]: 59
3412 11:49:40.254045
3413 11:49:40.254124 Set Vref, RX VrefLevel [Byte0]: 60
3414 11:49:40.256910 [Byte1]: 60
3415 11:49:40.261350
3416 11:49:40.261431 Set Vref, RX VrefLevel [Byte0]: 61
3417 11:49:40.265025 [Byte1]: 61
3418 11:49:40.269206
3419 11:49:40.269287 Set Vref, RX VrefLevel [Byte0]: 62
3420 11:49:40.272851 [Byte1]: 62
3421 11:49:40.276937
3422 11:49:40.277017 Set Vref, RX VrefLevel [Byte0]: 63
3423 11:49:40.280233 [Byte1]: 63
3424 11:49:40.285380
3425 11:49:40.285461 Set Vref, RX VrefLevel [Byte0]: 64
3426 11:49:40.288642 [Byte1]: 64
3427 11:49:40.293096
3428 11:49:40.293175 Set Vref, RX VrefLevel [Byte0]: 65
3429 11:49:40.296308 [Byte1]: 65
3430 11:49:40.300839
3431 11:49:40.300919 Set Vref, RX VrefLevel [Byte0]: 66
3432 11:49:40.304166 [Byte1]: 66
3433 11:49:40.308507
3434 11:49:40.308587 Set Vref, RX VrefLevel [Byte0]: 67
3435 11:49:40.312238 [Byte1]: 67
3436 11:49:40.316693
3437 11:49:40.316773 Set Vref, RX VrefLevel [Byte0]: 68
3438 11:49:40.319813 [Byte1]: 68
3439 11:49:40.324384
3440 11:49:40.324465 Set Vref, RX VrefLevel [Byte0]: 69
3441 11:49:40.327577 [Byte1]: 69
3442 11:49:40.332192
3443 11:49:40.332272 Final RX Vref Byte 0 = 53 to rank0
3444 11:49:40.335808 Final RX Vref Byte 1 = 54 to rank0
3445 11:49:40.339162 Final RX Vref Byte 0 = 53 to rank1
3446 11:49:40.342526 Final RX Vref Byte 1 = 54 to rank1==
3447 11:49:40.345399 Dram Type= 6, Freq= 0, CH_1, rank 0
3448 11:49:40.348916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 11:49:40.352440 ==
3450 11:49:40.352521 DQS Delay:
3451 11:49:40.352584 DQS0 = 0, DQS1 = 0
3452 11:49:40.356011 DQM Delay:
3453 11:49:40.356092 DQM0 = 120, DQM1 = 117
3454 11:49:40.358938 DQ Delay:
3455 11:49:40.362640 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3456 11:49:40.366325 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3457 11:49:40.369409 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3458 11:49:40.372424 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3459 11:49:40.372504
3460 11:49:40.372568
3461 11:49:40.379620 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3462 11:49:40.382420 CH1 RK0: MR19=404, MR18=114
3463 11:49:40.389445 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3464 11:49:40.389552
3465 11:49:40.392769 ----->DramcWriteLeveling(PI) begin...
3466 11:49:40.392851 ==
3467 11:49:40.396005 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 11:49:40.399239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 11:49:40.399321 ==
3470 11:49:40.402445 Write leveling (Byte 0): 27 => 27
3471 11:49:40.405824 Write leveling (Byte 1): 29 => 29
3472 11:49:40.409046 DramcWriteLeveling(PI) end<-----
3473 11:49:40.409127
3474 11:49:40.409191 ==
3475 11:49:40.412654 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 11:49:40.415685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 11:49:40.419026 ==
3478 11:49:40.419106 [Gating] SW mode calibration
3479 11:49:40.425992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3480 11:49:40.432439 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3481 11:49:40.435668 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 11:49:40.442886 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 11:49:40.445975 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 11:49:40.449113 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 11:49:40.456345 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 11:49:40.459361 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3487 11:49:40.462757 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (1 0) (1 0)
3488 11:49:40.466468 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3489 11:49:40.472871 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 11:49:40.476352 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 11:49:40.479443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 11:49:40.485864 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 11:49:40.489357 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 11:49:40.492746 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3495 11:49:40.499378 1 0 24 | B1->B0 | 4141 2e2e | 0 0 | (0 0) (0 0)
3496 11:49:40.502554 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 11:49:40.505855 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 11:49:40.512410 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 11:49:40.516160 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 11:49:40.519308 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 11:49:40.526199 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 11:49:40.529471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 11:49:40.532710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3504 11:49:40.539259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3505 11:49:40.542438 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 11:49:40.545561 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 11:49:40.552606 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 11:49:40.555925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 11:49:40.558957 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 11:49:40.565568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 11:49:40.569307 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 11:49:40.572348 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 11:49:40.578851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 11:49:40.582461 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 11:49:40.585957 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 11:49:40.589015 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 11:49:40.595849 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:49:40.598817 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3519 11:49:40.602288 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3520 11:49:40.609067 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3521 11:49:40.612174 Total UI for P1: 0, mck2ui 16
3522 11:49:40.615459 best dqsien dly found for B1: ( 1, 3, 22)
3523 11:49:40.618760 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:49:40.621984 Total UI for P1: 0, mck2ui 16
3525 11:49:40.625735 best dqsien dly found for B0: ( 1, 3, 26)
3526 11:49:40.628998 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3527 11:49:40.631948 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3528 11:49:40.632029
3529 11:49:40.635831 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3530 11:49:40.638945 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3531 11:49:40.642158 [Gating] SW calibration Done
3532 11:49:40.642238 ==
3533 11:49:40.645454 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 11:49:40.652468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 11:49:40.652553 ==
3536 11:49:40.652617 RX Vref Scan: 0
3537 11:49:40.652678
3538 11:49:40.655675 RX Vref 0 -> 0, step: 1
3539 11:49:40.655756
3540 11:49:40.658896 RX Delay -40 -> 252, step: 8
3541 11:49:40.662303 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3542 11:49:40.665352 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3543 11:49:40.668630 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3544 11:49:40.671911 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3545 11:49:40.678586 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3546 11:49:40.681681 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3547 11:49:40.685479 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3548 11:49:40.688736 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3549 11:49:40.691808 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3550 11:49:40.698790 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3551 11:49:40.701952 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3552 11:49:40.705227 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3553 11:49:40.708351 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3554 11:49:40.715307 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3555 11:49:40.718833 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3556 11:49:40.722060 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3557 11:49:40.722158 ==
3558 11:49:40.725076 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 11:49:40.728761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 11:49:40.728843 ==
3561 11:49:40.732086 DQS Delay:
3562 11:49:40.732169 DQS0 = 0, DQS1 = 0
3563 11:49:40.732234 DQM Delay:
3564 11:49:40.735256 DQM0 = 121, DQM1 = 118
3565 11:49:40.735336 DQ Delay:
3566 11:49:40.738291 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3567 11:49:40.741972 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3568 11:49:40.748408 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3569 11:49:40.752199 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3570 11:49:40.752280
3571 11:49:40.752344
3572 11:49:40.752402 ==
3573 11:49:40.755317 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 11:49:40.758596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 11:49:40.758693 ==
3576 11:49:40.758773
3577 11:49:40.758857
3578 11:49:40.761848 TX Vref Scan disable
3579 11:49:40.761929 == TX Byte 0 ==
3580 11:49:40.768372 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 11:49:40.771523 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 11:49:40.774666 == TX Byte 1 ==
3583 11:49:40.778743 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 11:49:40.781912 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 11:49:40.781993 ==
3586 11:49:40.784929 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:49:40.788722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:49:40.788804 ==
3589 11:49:40.801521 TX Vref=22, minBit 10, minWin=25, winSum=420
3590 11:49:40.804626 TX Vref=24, minBit 9, minWin=25, winSum=424
3591 11:49:40.808335 TX Vref=26, minBit 2, minWin=26, winSum=430
3592 11:49:40.811524 TX Vref=28, minBit 9, minWin=26, winSum=435
3593 11:49:40.814812 TX Vref=30, minBit 9, minWin=26, winSum=436
3594 11:49:40.821254 TX Vref=32, minBit 9, minWin=26, winSum=435
3595 11:49:40.824378 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3596 11:49:40.824460
3597 11:49:40.827895 Final TX Range 1 Vref 30
3598 11:49:40.827978
3599 11:49:40.828042 ==
3600 11:49:40.831284 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 11:49:40.834732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 11:49:40.834816 ==
3603 11:49:40.837474
3604 11:49:40.837571
3605 11:49:40.837654 TX Vref Scan disable
3606 11:49:40.840839 == TX Byte 0 ==
3607 11:49:40.844375 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3608 11:49:40.847864 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3609 11:49:40.850960 == TX Byte 1 ==
3610 11:49:40.854579 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3611 11:49:40.857880 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3612 11:49:40.860915
3613 11:49:40.860996 [DATLAT]
3614 11:49:40.861059 Freq=1200, CH1 RK1
3615 11:49:40.861118
3616 11:49:40.864300 DATLAT Default: 0xd
3617 11:49:40.864381 0, 0xFFFF, sum = 0
3618 11:49:40.867589 1, 0xFFFF, sum = 0
3619 11:49:40.867672 2, 0xFFFF, sum = 0
3620 11:49:40.870827 3, 0xFFFF, sum = 0
3621 11:49:40.870909 4, 0xFFFF, sum = 0
3622 11:49:40.874195 5, 0xFFFF, sum = 0
3623 11:49:40.877723 6, 0xFFFF, sum = 0
3624 11:49:40.877806 7, 0xFFFF, sum = 0
3625 11:49:40.881016 8, 0xFFFF, sum = 0
3626 11:49:40.881099 9, 0xFFFF, sum = 0
3627 11:49:40.884360 10, 0xFFFF, sum = 0
3628 11:49:40.884443 11, 0xFFFF, sum = 0
3629 11:49:40.887624 12, 0x0, sum = 1
3630 11:49:40.887706 13, 0x0, sum = 2
3631 11:49:40.890786 14, 0x0, sum = 3
3632 11:49:40.890868 15, 0x0, sum = 4
3633 11:49:40.890956 best_step = 13
3634 11:49:40.894329
3635 11:49:40.894409 ==
3636 11:49:40.897431 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 11:49:40.900686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 11:49:40.900768 ==
3639 11:49:40.900832 RX Vref Scan: 0
3640 11:49:40.900891
3641 11:49:40.904247 RX Vref 0 -> 0, step: 1
3642 11:49:40.904328
3643 11:49:40.907423 RX Delay -5 -> 252, step: 4
3644 11:49:40.911193 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3645 11:49:40.917777 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3646 11:49:40.921029 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3647 11:49:40.924290 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3648 11:49:40.927467 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3649 11:49:40.930712 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3650 11:49:40.937792 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3651 11:49:40.940854 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3652 11:49:40.943856 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3653 11:49:40.947436 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3654 11:49:40.950672 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3655 11:49:40.957451 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3656 11:49:40.960785 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3657 11:49:40.964139 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3658 11:49:40.967458 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3659 11:49:40.970622 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3660 11:49:40.973948 ==
3661 11:49:40.974029 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 11:49:40.981190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 11:49:40.981277 ==
3664 11:49:40.981342 DQS Delay:
3665 11:49:40.984258 DQS0 = 0, DQS1 = 0
3666 11:49:40.984339 DQM Delay:
3667 11:49:40.987443 DQM0 = 120, DQM1 = 118
3668 11:49:40.987524 DQ Delay:
3669 11:49:40.990775 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3670 11:49:40.994044 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3671 11:49:40.997118 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3672 11:49:41.000788 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3673 11:49:41.000870
3674 11:49:41.000932
3675 11:49:41.011049 [DQSOSCAuto] RK1, (LSB)MR18= 0x15f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 401 ps
3676 11:49:41.011132 CH1 RK1: MR19=403, MR18=15F2
3677 11:49:41.017249 CH1_RK1: MR19=0x403, MR18=0x15F2, DQSOSC=401, MR23=63, INC=40, DEC=27
3678 11:49:41.020960 [RxdqsGatingPostProcess] freq 1200
3679 11:49:41.027346 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3680 11:49:41.030618 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 11:49:41.033915 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 11:49:41.037221 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 11:49:41.040905 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 11:49:41.044132 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 11:49:41.047341 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 11:49:41.050774 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 11:49:41.050856 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 11:49:41.053923 Pre-setting of DQS Precalculation
3689 11:49:41.060593 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3690 11:49:41.067426 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3691 11:49:41.074282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3692 11:49:41.074365
3693 11:49:41.074428
3694 11:49:41.077113 [Calibration Summary] 2400 Mbps
3695 11:49:41.080340 CH 0, Rank 0
3696 11:49:41.080422 SW Impedance : PASS
3697 11:49:41.083683 DUTY Scan : NO K
3698 11:49:41.087531 ZQ Calibration : PASS
3699 11:49:41.087614 Jitter Meter : NO K
3700 11:49:41.090626 CBT Training : PASS
3701 11:49:41.090707 Write leveling : PASS
3702 11:49:41.093804 RX DQS gating : PASS
3703 11:49:41.097079 RX DQ/DQS(RDDQC) : PASS
3704 11:49:41.097160 TX DQ/DQS : PASS
3705 11:49:41.100302 RX DATLAT : PASS
3706 11:49:41.104007 RX DQ/DQS(Engine): PASS
3707 11:49:41.104118 TX OE : NO K
3708 11:49:41.107267 All Pass.
3709 11:49:41.107348
3710 11:49:41.107411 CH 0, Rank 1
3711 11:49:41.110433 SW Impedance : PASS
3712 11:49:41.110514 DUTY Scan : NO K
3713 11:49:41.113675 ZQ Calibration : PASS
3714 11:49:41.116949 Jitter Meter : NO K
3715 11:49:41.117030 CBT Training : PASS
3716 11:49:41.120534 Write leveling : PASS
3717 11:49:41.123596 RX DQS gating : PASS
3718 11:49:41.123713 RX DQ/DQS(RDDQC) : PASS
3719 11:49:41.127219 TX DQ/DQS : PASS
3720 11:49:41.130217 RX DATLAT : PASS
3721 11:49:41.130298 RX DQ/DQS(Engine): PASS
3722 11:49:41.133467 TX OE : NO K
3723 11:49:41.133583 All Pass.
3724 11:49:41.133664
3725 11:49:41.137380 CH 1, Rank 0
3726 11:49:41.137460 SW Impedance : PASS
3727 11:49:41.140053 DUTY Scan : NO K
3728 11:49:41.143744 ZQ Calibration : PASS
3729 11:49:41.143825 Jitter Meter : NO K
3730 11:49:41.147031 CBT Training : PASS
3731 11:49:41.147143 Write leveling : PASS
3732 11:49:41.150465 RX DQS gating : PASS
3733 11:49:41.153416 RX DQ/DQS(RDDQC) : PASS
3734 11:49:41.153497 TX DQ/DQS : PASS
3735 11:49:41.156911 RX DATLAT : PASS
3736 11:49:41.160104 RX DQ/DQS(Engine): PASS
3737 11:49:41.160185 TX OE : NO K
3738 11:49:41.163312 All Pass.
3739 11:49:41.163392
3740 11:49:41.163456 CH 1, Rank 1
3741 11:49:41.166551 SW Impedance : PASS
3742 11:49:41.166632 DUTY Scan : NO K
3743 11:49:41.170416 ZQ Calibration : PASS
3744 11:49:41.173543 Jitter Meter : NO K
3745 11:49:41.173660 CBT Training : PASS
3746 11:49:41.176763 Write leveling : PASS
3747 11:49:41.179900 RX DQS gating : PASS
3748 11:49:41.179981 RX DQ/DQS(RDDQC) : PASS
3749 11:49:41.183209 TX DQ/DQS : PASS
3750 11:49:41.187098 RX DATLAT : PASS
3751 11:49:41.187180 RX DQ/DQS(Engine): PASS
3752 11:49:41.189868 TX OE : NO K
3753 11:49:41.189949 All Pass.
3754 11:49:41.190013
3755 11:49:41.193545 DramC Write-DBI off
3756 11:49:41.196865 PER_BANK_REFRESH: Hybrid Mode
3757 11:49:41.196946 TX_TRACKING: ON
3758 11:49:41.206355 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3759 11:49:41.210019 [FAST_K] Save calibration result to emmc
3760 11:49:41.213374 dramc_set_vcore_voltage set vcore to 650000
3761 11:49:41.216689 Read voltage for 600, 5
3762 11:49:41.216770 Vio18 = 0
3763 11:49:41.216835 Vcore = 650000
3764 11:49:41.219934 Vdram = 0
3765 11:49:41.220015 Vddq = 0
3766 11:49:41.220079 Vmddr = 0
3767 11:49:41.226577 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3768 11:49:41.229540 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3769 11:49:41.233257 MEM_TYPE=3, freq_sel=19
3770 11:49:41.236210 sv_algorithm_assistance_LP4_1600
3771 11:49:41.239392 ============ PULL DRAM RESETB DOWN ============
3772 11:49:41.243149 ========== PULL DRAM RESETB DOWN end =========
3773 11:49:41.249530 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 11:49:41.252690 ===================================
3775 11:49:41.252771 LPDDR4 DRAM CONFIGURATION
3776 11:49:41.255993 ===================================
3777 11:49:41.259262 EX_ROW_EN[0] = 0x0
3778 11:49:41.262975 EX_ROW_EN[1] = 0x0
3779 11:49:41.263056 LP4Y_EN = 0x0
3780 11:49:41.265820 WORK_FSP = 0x0
3781 11:49:41.265901 WL = 0x2
3782 11:49:41.269475 RL = 0x2
3783 11:49:41.269587 BL = 0x2
3784 11:49:41.272811 RPST = 0x0
3785 11:49:41.272894 RD_PRE = 0x0
3786 11:49:41.275990 WR_PRE = 0x1
3787 11:49:41.276071 WR_PST = 0x0
3788 11:49:41.279372 DBI_WR = 0x0
3789 11:49:41.279453 DBI_RD = 0x0
3790 11:49:41.282490 OTF = 0x1
3791 11:49:41.286035 ===================================
3792 11:49:41.289373 ===================================
3793 11:49:41.289454 ANA top config
3794 11:49:41.292689 ===================================
3795 11:49:41.295970 DLL_ASYNC_EN = 0
3796 11:49:41.299340 ALL_SLAVE_EN = 1
3797 11:49:41.302442 NEW_RANK_MODE = 1
3798 11:49:41.302524 DLL_IDLE_MODE = 1
3799 11:49:41.306053 LP45_APHY_COMB_EN = 1
3800 11:49:41.308960 TX_ODT_DIS = 1
3801 11:49:41.312673 NEW_8X_MODE = 1
3802 11:49:41.315628 ===================================
3803 11:49:41.319238 ===================================
3804 11:49:41.322087 data_rate = 1200
3805 11:49:41.322192 CKR = 1
3806 11:49:41.325427 DQ_P2S_RATIO = 8
3807 11:49:41.329234 ===================================
3808 11:49:41.332287 CA_P2S_RATIO = 8
3809 11:49:41.335811 DQ_CA_OPEN = 0
3810 11:49:41.338906 DQ_SEMI_OPEN = 0
3811 11:49:41.342162 CA_SEMI_OPEN = 0
3812 11:49:41.342241 CA_FULL_RATE = 0
3813 11:49:41.345527 DQ_CKDIV4_EN = 1
3814 11:49:41.349237 CA_CKDIV4_EN = 1
3815 11:49:41.352400 CA_PREDIV_EN = 0
3816 11:49:41.355498 PH8_DLY = 0
3817 11:49:41.358845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3818 11:49:41.358926 DQ_AAMCK_DIV = 4
3819 11:49:41.362045 CA_AAMCK_DIV = 4
3820 11:49:41.365351 CA_ADMCK_DIV = 4
3821 11:49:41.369046 DQ_TRACK_CA_EN = 0
3822 11:49:41.372254 CA_PICK = 600
3823 11:49:41.375644 CA_MCKIO = 600
3824 11:49:41.375725 MCKIO_SEMI = 0
3825 11:49:41.379120 PLL_FREQ = 2288
3826 11:49:41.382393 DQ_UI_PI_RATIO = 32
3827 11:49:41.385436 CA_UI_PI_RATIO = 0
3828 11:49:41.388505 ===================================
3829 11:49:41.391852 ===================================
3830 11:49:41.395719 memory_type:LPDDR4
3831 11:49:41.395800 GP_NUM : 10
3832 11:49:41.398389 SRAM_EN : 1
3833 11:49:41.402386 MD32_EN : 0
3834 11:49:41.405522 ===================================
3835 11:49:41.405656 [ANA_INIT] >>>>>>>>>>>>>>
3836 11:49:41.408721 <<<<<< [CONFIGURE PHASE]: ANA_TX
3837 11:49:41.411877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3838 11:49:41.415125 ===================================
3839 11:49:41.418352 data_rate = 1200,PCW = 0X5800
3840 11:49:41.422193 ===================================
3841 11:49:41.425523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3842 11:49:41.431911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 11:49:41.435420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 11:49:41.441925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3845 11:49:41.445253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3846 11:49:41.448420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3847 11:49:41.448502 [ANA_INIT] flow start
3848 11:49:41.451951 [ANA_INIT] PLL >>>>>>>>
3849 11:49:41.455486 [ANA_INIT] PLL <<<<<<<<
3850 11:49:41.458648 [ANA_INIT] MIDPI >>>>>>>>
3851 11:49:41.458751 [ANA_INIT] MIDPI <<<<<<<<
3852 11:49:41.461890 [ANA_INIT] DLL >>>>>>>>
3853 11:49:41.461966 [ANA_INIT] flow end
3854 11:49:41.468385 ============ LP4 DIFF to SE enter ============
3855 11:49:41.472111 ============ LP4 DIFF to SE exit ============
3856 11:49:41.475520 [ANA_INIT] <<<<<<<<<<<<<
3857 11:49:41.478495 [Flow] Enable top DCM control >>>>>
3858 11:49:41.481896 [Flow] Enable top DCM control <<<<<
3859 11:49:41.485060 Enable DLL master slave shuffle
3860 11:49:41.488868 ==============================================================
3861 11:49:41.491968 Gating Mode config
3862 11:49:41.495188 ==============================================================
3863 11:49:41.498559 Config description:
3864 11:49:41.508336 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3865 11:49:41.515069 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3866 11:49:41.518371 SELPH_MODE 0: By rank 1: By Phase
3867 11:49:41.525299 ==============================================================
3868 11:49:41.528443 GAT_TRACK_EN = 1
3869 11:49:41.531733 RX_GATING_MODE = 2
3870 11:49:41.535055 RX_GATING_TRACK_MODE = 2
3871 11:49:41.538276 SELPH_MODE = 1
3872 11:49:41.538364 PICG_EARLY_EN = 1
3873 11:49:41.541454 VALID_LAT_VALUE = 1
3874 11:49:41.548120 ==============================================================
3875 11:49:41.551796 Enter into Gating configuration >>>>
3876 11:49:41.554796 Exit from Gating configuration <<<<
3877 11:49:41.558393 Enter into DVFS_PRE_config >>>>>
3878 11:49:41.568141 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3879 11:49:41.571765 Exit from DVFS_PRE_config <<<<<
3880 11:49:41.574769 Enter into PICG configuration >>>>
3881 11:49:41.578260 Exit from PICG configuration <<<<
3882 11:49:41.581692 [RX_INPUT] configuration >>>>>
3883 11:49:41.584608 [RX_INPUT] configuration <<<<<
3884 11:49:41.588195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3885 11:49:41.594679 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3886 11:49:41.601322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 11:49:41.608483 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 11:49:41.615098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 11:49:41.618138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 11:49:41.625023 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3891 11:49:41.628257 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3892 11:49:41.631392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3893 11:49:41.634693 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3894 11:49:41.641357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3895 11:49:41.645040 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 11:49:41.648220 ===================================
3897 11:49:41.651499 LPDDR4 DRAM CONFIGURATION
3898 11:49:41.654722 ===================================
3899 11:49:41.654803 EX_ROW_EN[0] = 0x0
3900 11:49:41.658586 EX_ROW_EN[1] = 0x0
3901 11:49:41.658667 LP4Y_EN = 0x0
3902 11:49:41.661725 WORK_FSP = 0x0
3903 11:49:41.661806 WL = 0x2
3904 11:49:41.665061 RL = 0x2
3905 11:49:41.665141 BL = 0x2
3906 11:49:41.668538 RPST = 0x0
3907 11:49:41.668641 RD_PRE = 0x0
3908 11:49:41.671440 WR_PRE = 0x1
3909 11:49:41.671521 WR_PST = 0x0
3910 11:49:41.674662 DBI_WR = 0x0
3911 11:49:41.674743 DBI_RD = 0x0
3912 11:49:41.678460 OTF = 0x1
3913 11:49:41.681627 ===================================
3914 11:49:41.684811 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3915 11:49:41.687875 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3916 11:49:41.694626 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 11:49:41.698093 ===================================
3918 11:49:41.698196 LPDDR4 DRAM CONFIGURATION
3919 11:49:41.701504 ===================================
3920 11:49:41.704929 EX_ROW_EN[0] = 0x10
3921 11:49:41.707864 EX_ROW_EN[1] = 0x0
3922 11:49:41.707973 LP4Y_EN = 0x0
3923 11:49:41.711677 WORK_FSP = 0x0
3924 11:49:41.711796 WL = 0x2
3925 11:49:41.714372 RL = 0x2
3926 11:49:41.714472 BL = 0x2
3927 11:49:41.718239 RPST = 0x0
3928 11:49:41.718339 RD_PRE = 0x0
3929 11:49:41.721497 WR_PRE = 0x1
3930 11:49:41.721641 WR_PST = 0x0
3931 11:49:41.724670 DBI_WR = 0x0
3932 11:49:41.724782 DBI_RD = 0x0
3933 11:49:41.727907 OTF = 0x1
3934 11:49:41.731172 ===================================
3935 11:49:41.737969 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3936 11:49:41.741313 nWR fixed to 30
3937 11:49:41.744543 [ModeRegInit_LP4] CH0 RK0
3938 11:49:41.744650 [ModeRegInit_LP4] CH0 RK1
3939 11:49:41.747819 [ModeRegInit_LP4] CH1 RK0
3940 11:49:41.750908 [ModeRegInit_LP4] CH1 RK1
3941 11:49:41.750980 match AC timing 17
3942 11:49:41.758162 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3943 11:49:41.761346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3944 11:49:41.764506 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3945 11:49:41.771443 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3946 11:49:41.774606 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3947 11:49:41.774680 ==
3948 11:49:41.777745 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 11:49:41.780840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 11:49:41.780938 ==
3951 11:49:41.787870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 11:49:41.794735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3953 11:49:41.797961 [CA 0] Center 35 (5~66) winsize 62
3954 11:49:41.801070 [CA 1] Center 36 (5~67) winsize 63
3955 11:49:41.804365 [CA 2] Center 34 (3~65) winsize 63
3956 11:49:41.807530 [CA 3] Center 33 (2~64) winsize 63
3957 11:49:41.811111 [CA 4] Center 33 (2~64) winsize 63
3958 11:49:41.814638 [CA 5] Center 32 (2~63) winsize 62
3959 11:49:41.814721
3960 11:49:41.817534 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3961 11:49:41.817626
3962 11:49:41.821219 [CATrainingPosCal] consider 1 rank data
3963 11:49:41.824484 u2DelayCellTimex100 = 270/100 ps
3964 11:49:41.828128 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3965 11:49:41.831331 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3966 11:49:41.834683 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3967 11:49:41.837934 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3968 11:49:41.841268 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3969 11:49:41.844331 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3970 11:49:41.844403
3971 11:49:41.851263 CA PerBit enable=1, Macro0, CA PI delay=32
3972 11:49:41.851341
3973 11:49:41.851404 [CBTSetCACLKResult] CA Dly = 32
3974 11:49:41.854427 CS Dly: 4 (0~35)
3975 11:49:41.854501 ==
3976 11:49:41.857508 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 11:49:41.861400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 11:49:41.861515 ==
3979 11:49:41.867873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 11:49:41.874346 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3981 11:49:41.877556 [CA 0] Center 36 (5~67) winsize 63
3982 11:49:41.881329 [CA 1] Center 36 (5~67) winsize 63
3983 11:49:41.884467 [CA 2] Center 34 (3~65) winsize 63
3984 11:49:41.887491 [CA 3] Center 34 (3~65) winsize 63
3985 11:49:41.891269 [CA 4] Center 33 (2~64) winsize 63
3986 11:49:41.894278 [CA 5] Center 32 (2~63) winsize 62
3987 11:49:41.894351
3988 11:49:41.897742 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3989 11:49:41.897815
3990 11:49:41.901088 [CATrainingPosCal] consider 2 rank data
3991 11:49:41.904228 u2DelayCellTimex100 = 270/100 ps
3992 11:49:41.907306 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3993 11:49:41.910592 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3994 11:49:41.914473 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3995 11:49:41.917506 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3996 11:49:41.920677 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3997 11:49:41.927509 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3998 11:49:41.927611
3999 11:49:41.930519 CA PerBit enable=1, Macro0, CA PI delay=32
4000 11:49:41.930591
4001 11:49:41.934177 [CBTSetCACLKResult] CA Dly = 32
4002 11:49:41.934256 CS Dly: 4 (0~36)
4003 11:49:41.934318
4004 11:49:41.937077 ----->DramcWriteLeveling(PI) begin...
4005 11:49:41.937146 ==
4006 11:49:41.940417 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 11:49:41.943617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 11:49:41.946961 ==
4009 11:49:41.950663 Write leveling (Byte 0): 34 => 34
4010 11:49:41.950742 Write leveling (Byte 1): 30 => 30
4011 11:49:41.953828 DramcWriteLeveling(PI) end<-----
4012 11:49:41.953898
4013 11:49:41.953963 ==
4014 11:49:41.957543 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 11:49:41.964056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 11:49:41.964131 ==
4017 11:49:41.967281 [Gating] SW mode calibration
4018 11:49:41.973717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4019 11:49:41.977544 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4020 11:49:41.980932 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 11:49:41.987492 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 11:49:41.990597 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 11:49:41.993827 0 9 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
4024 11:49:42.000875 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
4025 11:49:42.003775 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 11:49:42.007486 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 11:49:42.013723 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 11:49:42.017081 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 11:49:42.020881 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 11:49:42.027341 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 11:49:42.030524 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4032 11:49:42.033976 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4033 11:49:42.040401 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 11:49:42.043498 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 11:49:42.047161 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 11:49:42.053695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 11:49:42.056855 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 11:49:42.060589 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 11:49:42.066837 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4040 11:49:42.069936 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4041 11:49:42.073287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 11:49:42.080255 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 11:49:42.083464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 11:49:42.086677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 11:49:42.093168 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 11:49:42.097002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 11:49:42.100035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 11:49:42.106326 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 11:49:42.109497 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 11:49:42.113218 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 11:49:42.120034 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 11:49:42.123296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:49:42.126376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:49:42.133367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:49:42.136636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4056 11:49:42.139930 Total UI for P1: 0, mck2ui 16
4057 11:49:42.143253 best dqsien dly found for B0: ( 0, 13, 10)
4058 11:49:42.146400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4059 11:49:42.152906 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:49:42.152988 Total UI for P1: 0, mck2ui 16
4061 11:49:42.156059 best dqsien dly found for B1: ( 0, 13, 14)
4062 11:49:42.162843 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4063 11:49:42.166277 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4064 11:49:42.166358
4065 11:49:42.169651 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4066 11:49:42.172801 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4067 11:49:42.176624 [Gating] SW calibration Done
4068 11:49:42.176704 ==
4069 11:49:42.179428 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 11:49:42.182906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 11:49:42.182987 ==
4072 11:49:42.186197 RX Vref Scan: 0
4073 11:49:42.186278
4074 11:49:42.186342 RX Vref 0 -> 0, step: 1
4075 11:49:42.186402
4076 11:49:42.189302 RX Delay -230 -> 252, step: 16
4077 11:49:42.192594 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4078 11:49:42.199500 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4079 11:49:42.202682 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4080 11:49:42.205725 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4081 11:49:42.209567 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4082 11:49:42.216079 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4083 11:49:42.219128 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4084 11:49:42.222580 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4085 11:49:42.226132 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4086 11:49:42.229249 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4087 11:49:42.235875 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4088 11:49:42.239612 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4089 11:49:42.242900 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4090 11:49:42.246226 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4091 11:49:42.252740 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4092 11:49:42.256010 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4093 11:49:42.256092 ==
4094 11:49:42.259217 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 11:49:42.262244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 11:49:42.262326 ==
4097 11:49:42.265951 DQS Delay:
4098 11:49:42.266032 DQS0 = 0, DQS1 = 0
4099 11:49:42.266096 DQM Delay:
4100 11:49:42.269394 DQM0 = 50, DQM1 = 46
4101 11:49:42.269475 DQ Delay:
4102 11:49:42.272624 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4103 11:49:42.275764 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4104 11:49:42.279386 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4105 11:49:42.282433 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4106 11:49:42.282515
4107 11:49:42.282579
4108 11:49:42.282638 ==
4109 11:49:42.285646 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 11:49:42.292094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 11:49:42.292177 ==
4112 11:49:42.292242
4113 11:49:42.292301
4114 11:49:42.292359 TX Vref Scan disable
4115 11:49:42.296289 == TX Byte 0 ==
4116 11:49:42.299110 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4117 11:49:42.305980 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4118 11:49:42.306062 == TX Byte 1 ==
4119 11:49:42.309142 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4120 11:49:42.315668 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4121 11:49:42.315751 ==
4122 11:49:42.319479 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:49:42.322752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:49:42.322834 ==
4125 11:49:42.322899
4126 11:49:42.322959
4127 11:49:42.325908 TX Vref Scan disable
4128 11:49:42.328999 == TX Byte 0 ==
4129 11:49:42.332623 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4130 11:49:42.336208 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4131 11:49:42.339222 == TX Byte 1 ==
4132 11:49:42.342686 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 11:49:42.345681 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 11:49:42.345764
4135 11:49:42.345828 [DATLAT]
4136 11:49:42.349496 Freq=600, CH0 RK0
4137 11:49:42.349584
4138 11:49:42.349690 DATLAT Default: 0x9
4139 11:49:42.352673 0, 0xFFFF, sum = 0
4140 11:49:42.356019 1, 0xFFFF, sum = 0
4141 11:49:42.356101 2, 0xFFFF, sum = 0
4142 11:49:42.359402 3, 0xFFFF, sum = 0
4143 11:49:42.359487 4, 0xFFFF, sum = 0
4144 11:49:42.362522 5, 0xFFFF, sum = 0
4145 11:49:42.362605 6, 0xFFFF, sum = 0
4146 11:49:42.365643 7, 0xFFFF, sum = 0
4147 11:49:42.365725 8, 0x0, sum = 1
4148 11:49:42.368848 9, 0x0, sum = 2
4149 11:49:42.368929 10, 0x0, sum = 3
4150 11:49:42.368992 11, 0x0, sum = 4
4151 11:49:42.372191 best_step = 9
4152 11:49:42.372271
4153 11:49:42.372333 ==
4154 11:49:42.376183 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 11:49:42.379356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 11:49:42.379440 ==
4157 11:49:42.382576 RX Vref Scan: 1
4158 11:49:42.382656
4159 11:49:42.382719 RX Vref 0 -> 0, step: 1
4160 11:49:42.385878
4161 11:49:42.385957 RX Delay -163 -> 252, step: 8
4162 11:49:42.386020
4163 11:49:42.389272 Set Vref, RX VrefLevel [Byte0]: 56
4164 11:49:42.392369 [Byte1]: 47
4165 11:49:42.396724
4166 11:49:42.396804 Final RX Vref Byte 0 = 56 to rank0
4167 11:49:42.399755 Final RX Vref Byte 1 = 47 to rank0
4168 11:49:42.403161 Final RX Vref Byte 0 = 56 to rank1
4169 11:49:42.406499 Final RX Vref Byte 1 = 47 to rank1==
4170 11:49:42.409843 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 11:49:42.416202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 11:49:42.416282 ==
4173 11:49:42.416345 DQS Delay:
4174 11:49:42.416403 DQS0 = 0, DQS1 = 0
4175 11:49:42.419762 DQM Delay:
4176 11:49:42.419841 DQM0 = 53, DQM1 = 48
4177 11:49:42.422801 DQ Delay:
4178 11:49:42.426508 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4179 11:49:42.429353 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4180 11:49:42.429454 DQ8 =36, DQ9 =40, DQ10 =52, DQ11 =40
4181 11:49:42.436464 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4182 11:49:42.436544
4183 11:49:42.436607
4184 11:49:42.442810 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4185 11:49:42.446347 CH0 RK0: MR19=808, MR18=7366
4186 11:49:42.453083 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4187 11:49:42.453164
4188 11:49:42.456197 ----->DramcWriteLeveling(PI) begin...
4189 11:49:42.456279 ==
4190 11:49:42.459357 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 11:49:42.462713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 11:49:42.462794 ==
4193 11:49:42.465865 Write leveling (Byte 0): 34 => 34
4194 11:49:42.469714 Write leveling (Byte 1): 34 => 34
4195 11:49:42.472997 DramcWriteLeveling(PI) end<-----
4196 11:49:42.473077
4197 11:49:42.473140 ==
4198 11:49:42.476263 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 11:49:42.479451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 11:49:42.479542 ==
4201 11:49:42.482699 [Gating] SW mode calibration
4202 11:49:42.489771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4203 11:49:42.496355 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4204 11:49:42.499558 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 11:49:42.506102 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 11:49:42.509327 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 11:49:42.512582 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 11:49:42.516379 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (1 1) (0 0)
4209 11:49:42.522593 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 11:49:42.526358 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 11:49:42.529504 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 11:49:42.535859 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 11:49:42.539409 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 11:49:42.542581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 11:49:42.549265 0 10 12 | B1->B0 | 2a2a 2b2b | 0 0 | (0 0) (0 0)
4216 11:49:42.552534 0 10 16 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
4217 11:49:42.555924 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 11:49:42.562616 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 11:49:42.565820 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 11:49:42.569369 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 11:49:42.575820 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 11:49:42.579094 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 11:49:42.582271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 11:49:42.588710 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 11:49:42.592035 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 11:49:42.596014 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 11:49:42.602449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 11:49:42.605769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 11:49:42.609029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 11:49:42.615568 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 11:49:42.618762 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 11:49:42.622033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:49:42.629119 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 11:49:42.632195 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:49:42.635409 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:49:42.642435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:49:42.645692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:49:42.649397 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:49:42.652013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:49:42.659310 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4241 11:49:42.662363 Total UI for P1: 0, mck2ui 16
4242 11:49:42.665571 best dqsien dly found for B1: ( 0, 13, 14)
4243 11:49:42.669220 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:49:42.672181 Total UI for P1: 0, mck2ui 16
4245 11:49:42.675596 best dqsien dly found for B0: ( 0, 13, 16)
4246 11:49:42.678694 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4247 11:49:42.682171 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4248 11:49:42.682251
4249 11:49:42.685512 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4250 11:49:42.688819 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4251 11:49:42.692239 [Gating] SW calibration Done
4252 11:49:42.692333 ==
4253 11:49:42.695689 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 11:49:42.702142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 11:49:42.702223 ==
4256 11:49:42.702287 RX Vref Scan: 0
4257 11:49:42.702345
4258 11:49:42.705422 RX Vref 0 -> 0, step: 1
4259 11:49:42.705502
4260 11:49:42.708564 RX Delay -230 -> 252, step: 16
4261 11:49:42.711961 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4262 11:49:42.715258 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4263 11:49:42.718562 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4264 11:49:42.725476 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4265 11:49:42.728635 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4266 11:49:42.731819 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4267 11:49:42.735545 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4268 11:49:42.741901 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4269 11:49:42.745152 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4270 11:49:42.748291 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4271 11:49:42.751480 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4272 11:49:42.758677 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4273 11:49:42.761942 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4274 11:49:42.764808 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4275 11:49:42.768373 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4276 11:49:42.771531 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4277 11:49:42.775425 ==
4278 11:49:42.778164 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 11:49:42.782174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 11:49:42.782255 ==
4281 11:49:42.782344 DQS Delay:
4282 11:49:42.785185 DQS0 = 0, DQS1 = 0
4283 11:49:42.785265 DQM Delay:
4284 11:49:42.788267 DQM0 = 51, DQM1 = 43
4285 11:49:42.788346 DQ Delay:
4286 11:49:42.791614 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4287 11:49:42.794864 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4288 11:49:42.798398 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4289 11:49:42.801258 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4290 11:49:42.801338
4291 11:49:42.801401
4292 11:49:42.801460 ==
4293 11:49:42.804742 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 11:49:42.808112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 11:49:42.808193 ==
4296 11:49:42.808257
4297 11:49:42.808316
4298 11:49:42.811517 TX Vref Scan disable
4299 11:49:42.814677 == TX Byte 0 ==
4300 11:49:42.817881 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4301 11:49:42.821347 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4302 11:49:42.825231 == TX Byte 1 ==
4303 11:49:42.828468 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4304 11:49:42.831671 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4305 11:49:42.831751 ==
4306 11:49:42.834794 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 11:49:42.838267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 11:49:42.841515 ==
4309 11:49:42.841634
4310 11:49:42.841697
4311 11:49:42.841755 TX Vref Scan disable
4312 11:49:42.845232 == TX Byte 0 ==
4313 11:49:42.849215 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4314 11:49:42.855434 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4315 11:49:42.855515 == TX Byte 1 ==
4316 11:49:42.858617 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4317 11:49:42.861986 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4318 11:49:42.865187
4319 11:49:42.865266 [DATLAT]
4320 11:49:42.865329 Freq=600, CH0 RK1
4321 11:49:42.865388
4322 11:49:42.869069 DATLAT Default: 0x9
4323 11:49:42.869149 0, 0xFFFF, sum = 0
4324 11:49:42.872174 1, 0xFFFF, sum = 0
4325 11:49:42.872256 2, 0xFFFF, sum = 0
4326 11:49:42.875778 3, 0xFFFF, sum = 0
4327 11:49:42.875859 4, 0xFFFF, sum = 0
4328 11:49:42.878639 5, 0xFFFF, sum = 0
4329 11:49:42.882182 6, 0xFFFF, sum = 0
4330 11:49:42.882263 7, 0xFFFF, sum = 0
4331 11:49:42.882327 8, 0x0, sum = 1
4332 11:49:42.885467 9, 0x0, sum = 2
4333 11:49:42.885551 10, 0x0, sum = 3
4334 11:49:42.888769 11, 0x0, sum = 4
4335 11:49:42.888851 best_step = 9
4336 11:49:42.888915
4337 11:49:42.888974 ==
4338 11:49:42.892019 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 11:49:42.898753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 11:49:42.898835 ==
4341 11:49:42.898899 RX Vref Scan: 0
4342 11:49:42.898979
4343 11:49:42.902225 RX Vref 0 -> 0, step: 1
4344 11:49:42.902306
4345 11:49:42.905243 RX Delay -163 -> 252, step: 8
4346 11:49:42.908663 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4347 11:49:42.915518 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4348 11:49:42.918538 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4349 11:49:42.921960 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4350 11:49:42.925554 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4351 11:49:42.928571 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4352 11:49:42.931818 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4353 11:49:42.938747 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4354 11:49:42.941907 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4355 11:49:42.945323 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4356 11:49:42.949012 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4357 11:49:42.952209 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4358 11:49:42.958557 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4359 11:49:42.962120 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4360 11:49:42.965466 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4361 11:49:42.968595 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4362 11:49:42.968676 ==
4363 11:49:42.971939 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 11:49:42.978405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 11:49:42.978486 ==
4366 11:49:42.978550 DQS Delay:
4367 11:49:42.981596 DQS0 = 0, DQS1 = 0
4368 11:49:42.981677 DQM Delay:
4369 11:49:42.981741 DQM0 = 53, DQM1 = 47
4370 11:49:42.985615 DQ Delay:
4371 11:49:42.988514 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4372 11:49:42.991778 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4373 11:49:42.995553 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4374 11:49:42.998788 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4375 11:49:42.998868
4376 11:49:42.998932
4377 11:49:43.005236 [DQSOSCAuto] RK1, (LSB)MR18= 0x6929, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4378 11:49:43.008746 CH0 RK1: MR19=808, MR18=6929
4379 11:49:43.015274 CH0_RK1: MR19=0x808, MR18=0x6929, DQSOSC=390, MR23=63, INC=172, DEC=114
4380 11:49:43.018490 [RxdqsGatingPostProcess] freq 600
4381 11:49:43.021683 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4382 11:49:43.025298 Pre-setting of DQS Precalculation
4383 11:49:43.032123 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4384 11:49:43.032207 ==
4385 11:49:43.035194 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 11:49:43.038741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 11:49:43.038823 ==
4388 11:49:43.045190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4389 11:49:43.052373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4390 11:49:43.055238 [CA 0] Center 36 (5~67) winsize 63
4391 11:49:43.058253 [CA 1] Center 36 (5~67) winsize 63
4392 11:49:43.061893 [CA 2] Center 34 (4~65) winsize 62
4393 11:49:43.065182 [CA 3] Center 34 (4~65) winsize 62
4394 11:49:43.068426 [CA 4] Center 34 (4~65) winsize 62
4395 11:49:43.071597 [CA 5] Center 34 (3~65) winsize 63
4396 11:49:43.071672
4397 11:49:43.074976 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4398 11:49:43.075052
4399 11:49:43.078240 [CATrainingPosCal] consider 1 rank data
4400 11:49:43.081369 u2DelayCellTimex100 = 270/100 ps
4401 11:49:43.084708 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4402 11:49:43.087919 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4403 11:49:43.091829 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4404 11:49:43.095097 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 11:49:43.098429 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 11:49:43.101443 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4407 11:49:43.101515
4408 11:49:43.104546 CA PerBit enable=1, Macro0, CA PI delay=34
4409 11:49:43.107758
4410 11:49:43.107838 [CBTSetCACLKResult] CA Dly = 34
4411 11:49:43.111629 CS Dly: 6 (0~37)
4412 11:49:43.111701 ==
4413 11:49:43.114596 Dram Type= 6, Freq= 0, CH_1, rank 1
4414 11:49:43.118150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 11:49:43.118230 ==
4416 11:49:43.124770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 11:49:43.131204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4418 11:49:43.134532 [CA 0] Center 36 (5~67) winsize 63
4419 11:49:43.138198 [CA 1] Center 36 (5~67) winsize 63
4420 11:49:43.141454 [CA 2] Center 34 (4~65) winsize 62
4421 11:49:43.145018 [CA 3] Center 34 (4~65) winsize 62
4422 11:49:43.147958 [CA 4] Center 34 (4~65) winsize 62
4423 11:49:43.151509 [CA 5] Center 34 (3~65) winsize 63
4424 11:49:43.151590
4425 11:49:43.154615 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4426 11:49:43.154696
4427 11:49:43.157780 [CATrainingPosCal] consider 2 rank data
4428 11:49:43.161449 u2DelayCellTimex100 = 270/100 ps
4429 11:49:43.164538 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4430 11:49:43.168187 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4431 11:49:43.171155 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4432 11:49:43.174845 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4433 11:49:43.178228 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4434 11:49:43.181261 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4435 11:49:43.181342
4436 11:49:43.187767 CA PerBit enable=1, Macro0, CA PI delay=34
4437 11:49:43.187848
4438 11:49:43.187913 [CBTSetCACLKResult] CA Dly = 34
4439 11:49:43.191668 CS Dly: 6 (0~38)
4440 11:49:43.191749
4441 11:49:43.194780 ----->DramcWriteLeveling(PI) begin...
4442 11:49:43.194862 ==
4443 11:49:43.198011 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 11:49:43.201179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 11:49:43.201261 ==
4446 11:49:43.204383 Write leveling (Byte 0): 31 => 31
4447 11:49:43.208285 Write leveling (Byte 1): 31 => 31
4448 11:49:43.211120 DramcWriteLeveling(PI) end<-----
4449 11:49:43.211201
4450 11:49:43.211267 ==
4451 11:49:43.214192 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 11:49:43.221237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 11:49:43.221317 ==
4454 11:49:43.221382 [Gating] SW mode calibration
4455 11:49:43.230723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4456 11:49:43.234403 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4457 11:49:43.237700 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 11:49:43.244590 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 11:49:43.247955 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 11:49:43.251194 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
4461 11:49:43.257817 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 11:49:43.260981 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 11:49:43.264403 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 11:49:43.271259 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 11:49:43.274184 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 11:49:43.277979 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 11:49:43.284223 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 11:49:43.287386 0 10 12 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0)
4469 11:49:43.291305 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 11:49:43.297768 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 11:49:43.300943 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 11:49:43.304142 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 11:49:43.310693 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 11:49:43.314069 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 11:49:43.317331 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 11:49:43.320695 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 11:49:43.327817 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 11:49:43.330916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 11:49:43.334614 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 11:49:43.341079 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 11:49:43.344381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 11:49:43.347743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 11:49:43.354445 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 11:49:43.357692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 11:49:43.360861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 11:49:43.367257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 11:49:43.371012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:49:43.374173 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:49:43.380765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:49:43.383773 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:49:43.387577 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:49:43.393761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 11:49:43.393848 Total UI for P1: 0, mck2ui 16
4494 11:49:43.400822 best dqsien dly found for B0: ( 0, 13, 10)
4495 11:49:43.400922 Total UI for P1: 0, mck2ui 16
4496 11:49:43.407440 best dqsien dly found for B1: ( 0, 13, 10)
4497 11:49:43.410715 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4498 11:49:43.413832 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4499 11:49:43.413929
4500 11:49:43.417093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4501 11:49:43.421011 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4502 11:49:43.424322 [Gating] SW calibration Done
4503 11:49:43.424417 ==
4504 11:49:43.427393 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 11:49:43.430701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 11:49:43.430775 ==
4507 11:49:43.433841 RX Vref Scan: 0
4508 11:49:43.433937
4509 11:49:43.434024 RX Vref 0 -> 0, step: 1
4510 11:49:43.434118
4511 11:49:43.437183 RX Delay -230 -> 252, step: 16
4512 11:49:43.440691 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4513 11:49:43.447336 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4514 11:49:43.450925 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4515 11:49:43.453934 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 11:49:43.457289 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 11:49:43.463683 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4518 11:49:43.466861 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4519 11:49:43.470400 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 11:49:43.473532 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4521 11:49:43.477112 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4522 11:49:43.483591 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4523 11:49:43.487268 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4524 11:49:43.490144 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4525 11:49:43.493399 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4526 11:49:43.500193 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4527 11:49:43.503640 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4528 11:49:43.503720 ==
4529 11:49:43.506693 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 11:49:43.510423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 11:49:43.510505 ==
4532 11:49:43.513596 DQS Delay:
4533 11:49:43.513690 DQS0 = 0, DQS1 = 0
4534 11:49:43.513754 DQM Delay:
4535 11:49:43.516879 DQM0 = 50, DQM1 = 50
4536 11:49:43.516977 DQ Delay:
4537 11:49:43.520212 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4538 11:49:43.523460 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4539 11:49:43.526766 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4540 11:49:43.530023 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4541 11:49:43.530105
4542 11:49:43.530168
4543 11:49:43.530245 ==
4544 11:49:43.533306 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 11:49:43.539684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 11:49:43.539765 ==
4547 11:49:43.539830
4548 11:49:43.539888
4549 11:49:43.539945 TX Vref Scan disable
4550 11:49:43.543451 == TX Byte 0 ==
4551 11:49:43.546663 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 11:49:43.553361 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 11:49:43.553443 == TX Byte 1 ==
4554 11:49:43.556595 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 11:49:43.560427 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 11:49:43.563713 ==
4557 11:49:43.566752 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 11:49:43.570383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 11:49:43.570471 ==
4560 11:49:43.570572
4561 11:49:43.570635
4562 11:49:43.573673 TX Vref Scan disable
4563 11:49:43.573742 == TX Byte 0 ==
4564 11:49:43.579909 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4565 11:49:43.583777 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4566 11:49:43.583858 == TX Byte 1 ==
4567 11:49:43.590214 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4568 11:49:43.593379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4569 11:49:43.593486
4570 11:49:43.593583 [DATLAT]
4571 11:49:43.597079 Freq=600, CH1 RK0
4572 11:49:43.597159
4573 11:49:43.597221 DATLAT Default: 0x9
4574 11:49:43.600033 0, 0xFFFF, sum = 0
4575 11:49:43.600115 1, 0xFFFF, sum = 0
4576 11:49:43.603276 2, 0xFFFF, sum = 0
4577 11:49:43.603357 3, 0xFFFF, sum = 0
4578 11:49:43.607126 4, 0xFFFF, sum = 0
4579 11:49:43.610276 5, 0xFFFF, sum = 0
4580 11:49:43.610358 6, 0xFFFF, sum = 0
4581 11:49:43.613225 7, 0xFFFF, sum = 0
4582 11:49:43.613306 8, 0x0, sum = 1
4583 11:49:43.613370 9, 0x0, sum = 2
4584 11:49:43.616413 10, 0x0, sum = 3
4585 11:49:43.616494 11, 0x0, sum = 4
4586 11:49:43.620089 best_step = 9
4587 11:49:43.620169
4588 11:49:43.620231 ==
4589 11:49:43.623254 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 11:49:43.626525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 11:49:43.626606 ==
4592 11:49:43.630374 RX Vref Scan: 1
4593 11:49:43.630454
4594 11:49:43.630517 RX Vref 0 -> 0, step: 1
4595 11:49:43.630576
4596 11:49:43.633503 RX Delay -163 -> 252, step: 8
4597 11:49:43.633647
4598 11:49:43.636739 Set Vref, RX VrefLevel [Byte0]: 53
4599 11:49:43.640081 [Byte1]: 54
4600 11:49:43.644022
4601 11:49:43.644102 Final RX Vref Byte 0 = 53 to rank0
4602 11:49:43.647208 Final RX Vref Byte 1 = 54 to rank0
4603 11:49:43.650394 Final RX Vref Byte 0 = 53 to rank1
4604 11:49:43.654143 Final RX Vref Byte 1 = 54 to rank1==
4605 11:49:43.657263 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 11:49:43.663483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 11:49:43.663564 ==
4608 11:49:43.663627 DQS Delay:
4609 11:49:43.663686 DQS0 = 0, DQS1 = 0
4610 11:49:43.667305 DQM Delay:
4611 11:49:43.667385 DQM0 = 48, DQM1 = 45
4612 11:49:43.670575 DQ Delay:
4613 11:49:43.673714 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4614 11:49:43.676962 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4615 11:49:43.677042 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4616 11:49:43.683400 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4617 11:49:43.683480
4618 11:49:43.683542
4619 11:49:43.690510 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4620 11:49:43.693776 CH1 RK0: MR19=808, MR18=476C
4621 11:49:43.700328 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4622 11:49:43.700409
4623 11:49:43.703959 ----->DramcWriteLeveling(PI) begin...
4624 11:49:43.704040 ==
4625 11:49:43.706633 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 11:49:43.710172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 11:49:43.710254 ==
4628 11:49:43.713448 Write leveling (Byte 0): 31 => 31
4629 11:49:43.717051 Write leveling (Byte 1): 31 => 31
4630 11:49:43.719889 DramcWriteLeveling(PI) end<-----
4631 11:49:43.719969
4632 11:49:43.720032 ==
4633 11:49:43.723470 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 11:49:43.726561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 11:49:43.726642 ==
4636 11:49:43.730231 [Gating] SW mode calibration
4637 11:49:43.736900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 11:49:43.743398 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 11:49:43.746575 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 11:49:43.749847 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 11:49:43.756808 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 11:49:43.760062 0 9 12 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
4643 11:49:43.763701 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 11:49:43.770040 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 11:49:43.773239 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 11:49:43.776510 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 11:49:43.783595 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 11:49:43.786739 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 11:49:43.790027 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 11:49:43.796467 0 10 12 | B1->B0 | 3c3c 3939 | 0 0 | (1 1) (0 0)
4651 11:49:43.800194 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4652 11:49:43.803327 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 11:49:43.809790 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 11:49:43.813118 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 11:49:43.816381 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 11:49:43.823394 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 11:49:43.826669 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 11:49:43.830212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4659 11:49:43.836764 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4660 11:49:43.839698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 11:49:43.843503 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 11:49:43.850100 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 11:49:43.853515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 11:49:43.856649 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 11:49:43.859754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 11:49:43.866603 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 11:49:43.869887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 11:49:43.873361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 11:49:43.879577 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 11:49:43.883415 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:49:43.886678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:49:43.893133 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:49:43.896507 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:49:43.899592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4675 11:49:43.903391 Total UI for P1: 0, mck2ui 16
4676 11:49:43.906434 best dqsien dly found for B1: ( 0, 13, 10)
4677 11:49:43.913239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 11:49:43.913320 Total UI for P1: 0, mck2ui 16
4679 11:49:43.919697 best dqsien dly found for B0: ( 0, 13, 12)
4680 11:49:43.922909 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4681 11:49:43.926678 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4682 11:49:43.926758
4683 11:49:43.929719 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4684 11:49:43.932874 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4685 11:49:43.936516 [Gating] SW calibration Done
4686 11:49:43.936597 ==
4687 11:49:43.939520 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 11:49:43.943018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 11:49:43.943136 ==
4690 11:49:43.946148 RX Vref Scan: 0
4691 11:49:43.946228
4692 11:49:43.946292 RX Vref 0 -> 0, step: 1
4693 11:49:43.949341
4694 11:49:43.949435 RX Delay -230 -> 252, step: 16
4695 11:49:43.956089 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4696 11:49:43.959753 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4697 11:49:43.962762 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4698 11:49:43.966474 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4699 11:49:43.972920 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4700 11:49:43.976089 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4701 11:49:43.979800 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4702 11:49:43.982785 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4703 11:49:43.985946 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4704 11:49:43.992529 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4705 11:49:43.996341 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4706 11:49:43.999699 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4707 11:49:44.002943 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4708 11:49:44.009155 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4709 11:49:44.012939 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4710 11:49:44.015970 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4711 11:49:44.016051 ==
4712 11:49:44.019688 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 11:49:44.022817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 11:49:44.022898 ==
4715 11:49:44.026150 DQS Delay:
4716 11:49:44.026231 DQS0 = 0, DQS1 = 0
4717 11:49:44.029305 DQM Delay:
4718 11:49:44.029386 DQM0 = 49, DQM1 = 48
4719 11:49:44.029471 DQ Delay:
4720 11:49:44.032480 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4721 11:49:44.036193 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4722 11:49:44.039422 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4723 11:49:44.042696 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4724 11:49:44.042776
4725 11:49:44.042840
4726 11:49:44.045905 ==
4727 11:49:44.049473 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 11:49:44.052413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 11:49:44.052494 ==
4730 11:49:44.052557
4731 11:49:44.052615
4732 11:49:44.056184 TX Vref Scan disable
4733 11:49:44.056264 == TX Byte 0 ==
4734 11:49:44.059069 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4735 11:49:44.065760 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4736 11:49:44.065841 == TX Byte 1 ==
4737 11:49:44.069344 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4738 11:49:44.075740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4739 11:49:44.075820 ==
4740 11:49:44.079035 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 11:49:44.082552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 11:49:44.082720 ==
4743 11:49:44.082787
4744 11:49:44.082847
4745 11:49:44.085533 TX Vref Scan disable
4746 11:49:44.089164 == TX Byte 0 ==
4747 11:49:44.092354 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4748 11:49:44.095733 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4749 11:49:44.099493 == TX Byte 1 ==
4750 11:49:44.102782 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4751 11:49:44.106131 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4752 11:49:44.106231
4753 11:49:44.109363 [DATLAT]
4754 11:49:44.109448 Freq=600, CH1 RK1
4755 11:49:44.109512
4756 11:49:44.112464 DATLAT Default: 0x9
4757 11:49:44.112544 0, 0xFFFF, sum = 0
4758 11:49:44.115627 1, 0xFFFF, sum = 0
4759 11:49:44.115710 2, 0xFFFF, sum = 0
4760 11:49:44.119412 3, 0xFFFF, sum = 0
4761 11:49:44.119494 4, 0xFFFF, sum = 0
4762 11:49:44.122532 5, 0xFFFF, sum = 0
4763 11:49:44.122622 6, 0xFFFF, sum = 0
4764 11:49:44.126034 7, 0xFFFF, sum = 0
4765 11:49:44.126141 8, 0x0, sum = 1
4766 11:49:44.129012 9, 0x0, sum = 2
4767 11:49:44.129094 10, 0x0, sum = 3
4768 11:49:44.132640 11, 0x0, sum = 4
4769 11:49:44.132723 best_step = 9
4770 11:49:44.132787
4771 11:49:44.132847 ==
4772 11:49:44.135822 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 11:49:44.139105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 11:49:44.142441 ==
4775 11:49:44.142540 RX Vref Scan: 0
4776 11:49:44.142619
4777 11:49:44.145803 RX Vref 0 -> 0, step: 1
4778 11:49:44.145884
4779 11:49:44.145949 RX Delay -163 -> 252, step: 8
4780 11:49:44.154031 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4781 11:49:44.157134 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4782 11:49:44.160497 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4783 11:49:44.163658 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4784 11:49:44.167343 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4785 11:49:44.174052 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4786 11:49:44.177147 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4787 11:49:44.180405 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4788 11:49:44.183557 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4789 11:49:44.190231 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4790 11:49:44.193590 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4791 11:49:44.196809 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4792 11:49:44.200205 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4793 11:49:44.203664 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4794 11:49:44.209927 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4795 11:49:44.213545 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4796 11:49:44.213674 ==
4797 11:49:44.216755 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 11:49:44.219913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 11:49:44.219995 ==
4800 11:49:44.223773 DQS Delay:
4801 11:49:44.223853 DQS0 = 0, DQS1 = 0
4802 11:49:44.223917 DQM Delay:
4803 11:49:44.226967 DQM0 = 48, DQM1 = 46
4804 11:49:44.227048 DQ Delay:
4805 11:49:44.230269 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4806 11:49:44.233180 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4807 11:49:44.236825 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4808 11:49:44.239851 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4809 11:49:44.239933
4810 11:49:44.239996
4811 11:49:44.250423 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4812 11:49:44.250510 CH1 RK1: MR19=808, MR18=6B22
4813 11:49:44.256409 CH1_RK1: MR19=0x808, MR18=0x6B22, DQSOSC=389, MR23=63, INC=173, DEC=115
4814 11:49:44.260188 [RxdqsGatingPostProcess] freq 600
4815 11:49:44.266671 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 11:49:44.269922 Pre-setting of DQS Precalculation
4817 11:49:44.273221 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 11:49:44.279927 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 11:49:44.290149 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 11:49:44.290234
4821 11:49:44.290298
4822 11:49:44.293333 [Calibration Summary] 1200 Mbps
4823 11:49:44.293415 CH 0, Rank 0
4824 11:49:44.296455 SW Impedance : PASS
4825 11:49:44.296537 DUTY Scan : NO K
4826 11:49:44.299691 ZQ Calibration : PASS
4827 11:49:44.302856 Jitter Meter : NO K
4828 11:49:44.302937 CBT Training : PASS
4829 11:49:44.306706 Write leveling : PASS
4830 11:49:44.306788 RX DQS gating : PASS
4831 11:49:44.309392 RX DQ/DQS(RDDQC) : PASS
4832 11:49:44.312908 TX DQ/DQS : PASS
4833 11:49:44.312991 RX DATLAT : PASS
4834 11:49:44.316443 RX DQ/DQS(Engine): PASS
4835 11:49:44.319901 TX OE : NO K
4836 11:49:44.319983 All Pass.
4837 11:49:44.320047
4838 11:49:44.320107 CH 0, Rank 1
4839 11:49:44.323065 SW Impedance : PASS
4840 11:49:44.326555 DUTY Scan : NO K
4841 11:49:44.326636 ZQ Calibration : PASS
4842 11:49:44.329866 Jitter Meter : NO K
4843 11:49:44.332906 CBT Training : PASS
4844 11:49:44.332977 Write leveling : PASS
4845 11:49:44.336266 RX DQS gating : PASS
4846 11:49:44.339356 RX DQ/DQS(RDDQC) : PASS
4847 11:49:44.339438 TX DQ/DQS : PASS
4848 11:49:44.343299 RX DATLAT : PASS
4849 11:49:44.346492 RX DQ/DQS(Engine): PASS
4850 11:49:44.346573 TX OE : NO K
4851 11:49:44.346639 All Pass.
4852 11:49:44.349495
4853 11:49:44.349634 CH 1, Rank 0
4854 11:49:44.352982 SW Impedance : PASS
4855 11:49:44.353063 DUTY Scan : NO K
4856 11:49:44.356007 ZQ Calibration : PASS
4857 11:49:44.359495 Jitter Meter : NO K
4858 11:49:44.359611 CBT Training : PASS
4859 11:49:44.362597 Write leveling : PASS
4860 11:49:44.362679 RX DQS gating : PASS
4861 11:49:44.366540 RX DQ/DQS(RDDQC) : PASS
4862 11:49:44.369730 TX DQ/DQS : PASS
4863 11:49:44.369812 RX DATLAT : PASS
4864 11:49:44.373019 RX DQ/DQS(Engine): PASS
4865 11:49:44.376180 TX OE : NO K
4866 11:49:44.376262 All Pass.
4867 11:49:44.376327
4868 11:49:44.376386 CH 1, Rank 1
4869 11:49:44.379418 SW Impedance : PASS
4870 11:49:44.382718 DUTY Scan : NO K
4871 11:49:44.382800 ZQ Calibration : PASS
4872 11:49:44.385930 Jitter Meter : NO K
4873 11:49:44.389155 CBT Training : PASS
4874 11:49:44.389236 Write leveling : PASS
4875 11:49:44.392844 RX DQS gating : PASS
4876 11:49:44.395698 RX DQ/DQS(RDDQC) : PASS
4877 11:49:44.395780 TX DQ/DQS : PASS
4878 11:49:44.399139 RX DATLAT : PASS
4879 11:49:44.402625 RX DQ/DQS(Engine): PASS
4880 11:49:44.402707 TX OE : NO K
4881 11:49:44.402771 All Pass.
4882 11:49:44.405801
4883 11:49:44.405882 DramC Write-DBI off
4884 11:49:44.409060 PER_BANK_REFRESH: Hybrid Mode
4885 11:49:44.409141 TX_TRACKING: ON
4886 11:49:44.419366 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 11:49:44.422649 [FAST_K] Save calibration result to emmc
4888 11:49:44.425841 dramc_set_vcore_voltage set vcore to 662500
4889 11:49:44.429434 Read voltage for 933, 3
4890 11:49:44.429514 Vio18 = 0
4891 11:49:44.432514 Vcore = 662500
4892 11:49:44.432595 Vdram = 0
4893 11:49:44.432660 Vddq = 0
4894 11:49:44.432720 Vmddr = 0
4895 11:49:44.439187 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 11:49:44.446019 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 11:49:44.446101 MEM_TYPE=3, freq_sel=17
4898 11:49:44.449386 sv_algorithm_assistance_LP4_1600
4899 11:49:44.452669 ============ PULL DRAM RESETB DOWN ============
4900 11:49:44.459106 ========== PULL DRAM RESETB DOWN end =========
4901 11:49:44.462370 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 11:49:44.465651 ===================================
4903 11:49:44.468673 LPDDR4 DRAM CONFIGURATION
4904 11:49:44.472169 ===================================
4905 11:49:44.472252 EX_ROW_EN[0] = 0x0
4906 11:49:44.475826 EX_ROW_EN[1] = 0x0
4907 11:49:44.475949 LP4Y_EN = 0x0
4908 11:49:44.478913 WORK_FSP = 0x0
4909 11:49:44.478995 WL = 0x3
4910 11:49:44.482145 RL = 0x3
4911 11:49:44.482258 BL = 0x2
4912 11:49:44.485431 RPST = 0x0
4913 11:49:44.485540 RD_PRE = 0x0
4914 11:49:44.489302 WR_PRE = 0x1
4915 11:49:44.492547 WR_PST = 0x0
4916 11:49:44.492655 DBI_WR = 0x0
4917 11:49:44.495902 DBI_RD = 0x0
4918 11:49:44.496001 OTF = 0x1
4919 11:49:44.498943 ===================================
4920 11:49:44.502267 ===================================
4921 11:49:44.502373 ANA top config
4922 11:49:44.505970 ===================================
4923 11:49:44.509049 DLL_ASYNC_EN = 0
4924 11:49:44.512449 ALL_SLAVE_EN = 1
4925 11:49:44.515751 NEW_RANK_MODE = 1
4926 11:49:44.518885 DLL_IDLE_MODE = 1
4927 11:49:44.518986 LP45_APHY_COMB_EN = 1
4928 11:49:44.522635 TX_ODT_DIS = 1
4929 11:49:44.525856 NEW_8X_MODE = 1
4930 11:49:44.529274 ===================================
4931 11:49:44.532308 ===================================
4932 11:49:44.535417 data_rate = 1866
4933 11:49:44.539305 CKR = 1
4934 11:49:44.539408 DQ_P2S_RATIO = 8
4935 11:49:44.542529 ===================================
4936 11:49:44.545603 CA_P2S_RATIO = 8
4937 11:49:44.548826 DQ_CA_OPEN = 0
4938 11:49:44.552503 DQ_SEMI_OPEN = 0
4939 11:49:44.555679 CA_SEMI_OPEN = 0
4940 11:49:44.559157 CA_FULL_RATE = 0
4941 11:49:44.559232 DQ_CKDIV4_EN = 1
4942 11:49:44.562515 CA_CKDIV4_EN = 1
4943 11:49:44.565620 CA_PREDIV_EN = 0
4944 11:49:44.568727 PH8_DLY = 0
4945 11:49:44.572434 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 11:49:44.575444 DQ_AAMCK_DIV = 4
4947 11:49:44.575529 CA_AAMCK_DIV = 4
4948 11:49:44.579315 CA_ADMCK_DIV = 4
4949 11:49:44.582210 DQ_TRACK_CA_EN = 0
4950 11:49:44.585149 CA_PICK = 933
4951 11:49:44.588934 CA_MCKIO = 933
4952 11:49:44.592222 MCKIO_SEMI = 0
4953 11:49:44.595438 PLL_FREQ = 3732
4954 11:49:44.595521 DQ_UI_PI_RATIO = 32
4955 11:49:44.598750 CA_UI_PI_RATIO = 0
4956 11:49:44.601849 ===================================
4957 11:49:44.605836 ===================================
4958 11:49:44.608964 memory_type:LPDDR4
4959 11:49:44.612207 GP_NUM : 10
4960 11:49:44.612290 SRAM_EN : 1
4961 11:49:44.615450 MD32_EN : 0
4962 11:49:44.618759 ===================================
4963 11:49:44.618841 [ANA_INIT] >>>>>>>>>>>>>>
4964 11:49:44.622408 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 11:49:44.625136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 11:49:44.628647 ===================================
4967 11:49:44.631883 data_rate = 1866,PCW = 0X8f00
4968 11:49:44.635143 ===================================
4969 11:49:44.638984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 11:49:44.645014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 11:49:44.651980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 11:49:44.655307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 11:49:44.658521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 11:49:44.661600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 11:49:44.665378 [ANA_INIT] flow start
4976 11:49:44.665459 [ANA_INIT] PLL >>>>>>>>
4977 11:49:44.668433 [ANA_INIT] PLL <<<<<<<<
4978 11:49:44.671852 [ANA_INIT] MIDPI >>>>>>>>
4979 11:49:44.671933 [ANA_INIT] MIDPI <<<<<<<<
4980 11:49:44.674991 [ANA_INIT] DLL >>>>>>>>
4981 11:49:44.678516 [ANA_INIT] flow end
4982 11:49:44.681831 ============ LP4 DIFF to SE enter ============
4983 11:49:44.684775 ============ LP4 DIFF to SE exit ============
4984 11:49:44.688626 [ANA_INIT] <<<<<<<<<<<<<
4985 11:49:44.691638 [Flow] Enable top DCM control >>>>>
4986 11:49:44.695140 [Flow] Enable top DCM control <<<<<
4987 11:49:44.698295 Enable DLL master slave shuffle
4988 11:49:44.701405 ==============================================================
4989 11:49:44.704634 Gating Mode config
4990 11:49:44.711290 ==============================================================
4991 11:49:44.711372 Config description:
4992 11:49:44.721432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 11:49:44.727918 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 11:49:44.731663 SELPH_MODE 0: By rank 1: By Phase
4995 11:49:44.737964 ==============================================================
4996 11:49:44.741519 GAT_TRACK_EN = 1
4997 11:49:44.744819 RX_GATING_MODE = 2
4998 11:49:44.748052 RX_GATING_TRACK_MODE = 2
4999 11:49:44.751378 SELPH_MODE = 1
5000 11:49:44.754698 PICG_EARLY_EN = 1
5001 11:49:44.757817 VALID_LAT_VALUE = 1
5002 11:49:44.761214 ==============================================================
5003 11:49:44.764503 Enter into Gating configuration >>>>
5004 11:49:44.768278 Exit from Gating configuration <<<<
5005 11:49:44.770974 Enter into DVFS_PRE_config >>>>>
5006 11:49:44.784542 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 11:49:44.784626 Exit from DVFS_PRE_config <<<<<
5008 11:49:44.788317 Enter into PICG configuration >>>>
5009 11:49:44.791342 Exit from PICG configuration <<<<
5010 11:49:44.794580 [RX_INPUT] configuration >>>>>
5011 11:49:44.798151 [RX_INPUT] configuration <<<<<
5012 11:49:44.804763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 11:49:44.808228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 11:49:44.814377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 11:49:44.821370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 11:49:44.827828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 11:49:44.834344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 11:49:44.838142 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 11:49:44.841320 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 11:49:44.844615 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 11:49:44.851106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 11:49:44.854606 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 11:49:44.857483 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 11:49:44.860984 ===================================
5025 11:49:44.864226 LPDDR4 DRAM CONFIGURATION
5026 11:49:44.867251 ===================================
5027 11:49:44.867332 EX_ROW_EN[0] = 0x0
5028 11:49:44.870755 EX_ROW_EN[1] = 0x0
5029 11:49:44.874235 LP4Y_EN = 0x0
5030 11:49:44.874317 WORK_FSP = 0x0
5031 11:49:44.877346 WL = 0x3
5032 11:49:44.877426 RL = 0x3
5033 11:49:44.880978 BL = 0x2
5034 11:49:44.881059 RPST = 0x0
5035 11:49:44.884332 RD_PRE = 0x0
5036 11:49:44.884413 WR_PRE = 0x1
5037 11:49:44.887537 WR_PST = 0x0
5038 11:49:44.887618 DBI_WR = 0x0
5039 11:49:44.890950 DBI_RD = 0x0
5040 11:49:44.891070 OTF = 0x1
5041 11:49:44.894134 ===================================
5042 11:49:44.897335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 11:49:44.904506 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 11:49:44.907513 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 11:49:44.910578 ===================================
5046 11:49:44.914371 LPDDR4 DRAM CONFIGURATION
5047 11:49:44.917877 ===================================
5048 11:49:44.917958 EX_ROW_EN[0] = 0x10
5049 11:49:44.920625 EX_ROW_EN[1] = 0x0
5050 11:49:44.920706 LP4Y_EN = 0x0
5051 11:49:44.924220 WORK_FSP = 0x0
5052 11:49:44.927481 WL = 0x3
5053 11:49:44.927563 RL = 0x3
5054 11:49:44.930739 BL = 0x2
5055 11:49:44.930820 RPST = 0x0
5056 11:49:44.933843 RD_PRE = 0x0
5057 11:49:44.933925 WR_PRE = 0x1
5058 11:49:44.937398 WR_PST = 0x0
5059 11:49:44.937480 DBI_WR = 0x0
5060 11:49:44.940584 DBI_RD = 0x0
5061 11:49:44.940666 OTF = 0x1
5062 11:49:44.943835 ===================================
5063 11:49:44.950423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 11:49:44.954833 nWR fixed to 30
5065 11:49:44.958135 [ModeRegInit_LP4] CH0 RK0
5066 11:49:44.958216 [ModeRegInit_LP4] CH0 RK1
5067 11:49:44.961349 [ModeRegInit_LP4] CH1 RK0
5068 11:49:44.964547 [ModeRegInit_LP4] CH1 RK1
5069 11:49:44.964629 match AC timing 9
5070 11:49:44.971239 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 11:49:44.974391 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 11:49:44.977643 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 11:49:44.984624 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 11:49:44.987771 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 11:49:44.987853 ==
5076 11:49:44.991133 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 11:49:44.994448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 11:49:44.994532 ==
5079 11:49:45.000900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 11:49:45.007542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5081 11:49:45.011309 [CA 0] Center 37 (6~68) winsize 63
5082 11:49:45.014671 [CA 1] Center 37 (7~68) winsize 62
5083 11:49:45.017647 [CA 2] Center 34 (4~65) winsize 62
5084 11:49:45.020868 [CA 3] Center 33 (3~64) winsize 62
5085 11:49:45.024654 [CA 4] Center 33 (3~64) winsize 62
5086 11:49:45.027823 [CA 5] Center 32 (2~62) winsize 61
5087 11:49:45.027905
5088 11:49:45.031041 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5089 11:49:45.031123
5090 11:49:45.034224 [CATrainingPosCal] consider 1 rank data
5091 11:49:45.037535 u2DelayCellTimex100 = 270/100 ps
5092 11:49:45.041188 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5093 11:49:45.044121 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5094 11:49:45.047440 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5095 11:49:45.050891 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5096 11:49:45.054631 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5097 11:49:45.057785 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5098 11:49:45.061088
5099 11:49:45.064372 CA PerBit enable=1, Macro0, CA PI delay=32
5100 11:49:45.064454
5101 11:49:45.067622 [CBTSetCACLKResult] CA Dly = 32
5102 11:49:45.067704 CS Dly: 5 (0~36)
5103 11:49:45.067770 ==
5104 11:49:45.070827 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 11:49:45.074626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 11:49:45.074709 ==
5107 11:49:45.081234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 11:49:45.087633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 11:49:45.090966 [CA 0] Center 37 (7~68) winsize 62
5110 11:49:45.094034 [CA 1] Center 37 (7~68) winsize 62
5111 11:49:45.097313 [CA 2] Center 34 (4~65) winsize 62
5112 11:49:45.100873 [CA 3] Center 34 (3~65) winsize 63
5113 11:49:45.103852 [CA 4] Center 33 (3~63) winsize 61
5114 11:49:45.107214 [CA 5] Center 32 (2~62) winsize 61
5115 11:49:45.107296
5116 11:49:45.110522 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 11:49:45.110647
5118 11:49:45.113885 [CATrainingPosCal] consider 2 rank data
5119 11:49:45.117567 u2DelayCellTimex100 = 270/100 ps
5120 11:49:45.120738 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5121 11:49:45.124069 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5122 11:49:45.127365 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5123 11:49:45.130778 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5124 11:49:45.134259 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5125 11:49:45.140373 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5126 11:49:45.140455
5127 11:49:45.144273 CA PerBit enable=1, Macro0, CA PI delay=32
5128 11:49:45.144355
5129 11:49:45.147486 [CBTSetCACLKResult] CA Dly = 32
5130 11:49:45.147568 CS Dly: 5 (0~37)
5131 11:49:45.147633
5132 11:49:45.150750 ----->DramcWriteLeveling(PI) begin...
5133 11:49:45.150833 ==
5134 11:49:45.153940 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 11:49:45.157012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 11:49:45.160322 ==
5137 11:49:45.164014 Write leveling (Byte 0): 32 => 32
5138 11:49:45.164100 Write leveling (Byte 1): 31 => 31
5139 11:49:45.167076 DramcWriteLeveling(PI) end<-----
5140 11:49:45.167157
5141 11:49:45.167221 ==
5142 11:49:45.170548 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 11:49:45.177213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 11:49:45.177295 ==
5145 11:49:45.180374 [Gating] SW mode calibration
5146 11:49:45.187504 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 11:49:45.190790 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 11:49:45.197202 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5149 11:49:45.200537 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 11:49:45.204311 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 11:49:45.207413 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 11:49:45.213881 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 11:49:45.216890 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 11:49:45.220811 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5155 11:49:45.227367 0 14 28 | B1->B0 | 3131 2727 | 0 0 | (0 0) (0 0)
5156 11:49:45.230363 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5157 11:49:45.234108 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 11:49:45.240432 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 11:49:45.243782 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 11:49:45.247136 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 11:49:45.253540 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 11:49:45.257322 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5163 11:49:45.260652 0 15 28 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
5164 11:49:45.267084 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5165 11:49:45.270350 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 11:49:45.273663 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 11:49:45.279954 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 11:49:45.283545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 11:49:45.286553 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 11:49:45.293472 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5171 11:49:45.296646 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 11:49:45.299965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 11:49:45.306604 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 11:49:45.309730 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 11:49:45.313079 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 11:49:45.320115 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 11:49:45.323079 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 11:49:45.326988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 11:49:45.333390 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 11:49:45.336477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 11:49:45.340497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 11:49:45.346963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 11:49:45.350108 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 11:49:45.353199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:49:45.359829 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:49:45.363256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 11:49:45.366549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5188 11:49:45.370039 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 11:49:45.373351 Total UI for P1: 0, mck2ui 16
5190 11:49:45.376736 best dqsien dly found for B0: ( 1, 2, 26)
5191 11:49:45.383101 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:49:45.386283 Total UI for P1: 0, mck2ui 16
5193 11:49:45.389560 best dqsien dly found for B1: ( 1, 3, 0)
5194 11:49:45.393242 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5195 11:49:45.396271 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5196 11:49:45.396353
5197 11:49:45.399806 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5198 11:49:45.402773 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5199 11:49:45.406514 [Gating] SW calibration Done
5200 11:49:45.406596 ==
5201 11:49:45.409743 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 11:49:45.412914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 11:49:45.412996 ==
5204 11:49:45.416267 RX Vref Scan: 0
5205 11:49:45.416349
5206 11:49:45.416413 RX Vref 0 -> 0, step: 1
5207 11:49:45.419437
5208 11:49:45.419518 RX Delay -80 -> 252, step: 8
5209 11:49:45.425885 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5210 11:49:45.429555 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5211 11:49:45.432697 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5212 11:49:45.435976 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5213 11:49:45.439180 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5214 11:49:45.442590 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5215 11:49:45.449586 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5216 11:49:45.452755 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5217 11:49:45.456074 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5218 11:49:45.459308 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5219 11:49:45.462488 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5220 11:49:45.465743 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5221 11:49:45.472904 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5222 11:49:45.476003 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5223 11:49:45.479014 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5224 11:49:45.482590 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5225 11:49:45.482672 ==
5226 11:49:45.485800 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 11:49:45.489043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 11:49:45.492316 ==
5229 11:49:45.492399 DQS Delay:
5230 11:49:45.492463 DQS0 = 0, DQS1 = 0
5231 11:49:45.495899 DQM Delay:
5232 11:49:45.495980 DQM0 = 104, DQM1 = 93
5233 11:49:45.499098 DQ Delay:
5234 11:49:45.502764 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5235 11:49:45.505850 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =115
5236 11:49:45.509354 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5237 11:49:45.512630 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5238 11:49:45.512712
5239 11:49:45.512777
5240 11:49:45.512837 ==
5241 11:49:45.515493 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:49:45.519102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:49:45.519216 ==
5244 11:49:45.519281
5245 11:49:45.519340
5246 11:49:45.522263 TX Vref Scan disable
5247 11:49:45.522346 == TX Byte 0 ==
5248 11:49:45.529357 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5249 11:49:45.532557 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5250 11:49:45.532639 == TX Byte 1 ==
5251 11:49:45.538895 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5252 11:49:45.542243 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5253 11:49:45.542325 ==
5254 11:49:45.545871 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 11:49:45.548781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 11:49:45.548926 ==
5257 11:49:45.549012
5258 11:49:45.552603
5259 11:49:45.552684 TX Vref Scan disable
5260 11:49:45.555874 == TX Byte 0 ==
5261 11:49:45.559139 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5262 11:49:45.562392 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5263 11:49:45.565715 == TX Byte 1 ==
5264 11:49:45.568870 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5265 11:49:45.572147 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5266 11:49:45.575234
5267 11:49:45.575316 [DATLAT]
5268 11:49:45.575379 Freq=933, CH0 RK0
5269 11:49:45.575440
5270 11:49:45.578698 DATLAT Default: 0xd
5271 11:49:45.578780 0, 0xFFFF, sum = 0
5272 11:49:45.582468 1, 0xFFFF, sum = 0
5273 11:49:45.582551 2, 0xFFFF, sum = 0
5274 11:49:45.585821 3, 0xFFFF, sum = 0
5275 11:49:45.585903 4, 0xFFFF, sum = 0
5276 11:49:45.588855 5, 0xFFFF, sum = 0
5277 11:49:45.588939 6, 0xFFFF, sum = 0
5278 11:49:45.592179 7, 0xFFFF, sum = 0
5279 11:49:45.595315 8, 0xFFFF, sum = 0
5280 11:49:45.595398 9, 0xFFFF, sum = 0
5281 11:49:45.598467 10, 0x0, sum = 1
5282 11:49:45.598550 11, 0x0, sum = 2
5283 11:49:45.598615 12, 0x0, sum = 3
5284 11:49:45.602305 13, 0x0, sum = 4
5285 11:49:45.602387 best_step = 11
5286 11:49:45.602451
5287 11:49:45.602511 ==
5288 11:49:45.605493 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 11:49:45.611969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 11:49:45.612058 ==
5291 11:49:45.612123 RX Vref Scan: 1
5292 11:49:45.612183
5293 11:49:45.615105 RX Vref 0 -> 0, step: 1
5294 11:49:45.615186
5295 11:49:45.618749 RX Delay -53 -> 252, step: 4
5296 11:49:45.618831
5297 11:49:45.622304 Set Vref, RX VrefLevel [Byte0]: 56
5298 11:49:45.625130 [Byte1]: 47
5299 11:49:45.625212
5300 11:49:45.628523 Final RX Vref Byte 0 = 56 to rank0
5301 11:49:45.631740 Final RX Vref Byte 1 = 47 to rank0
5302 11:49:45.635519 Final RX Vref Byte 0 = 56 to rank1
5303 11:49:45.638616 Final RX Vref Byte 1 = 47 to rank1==
5304 11:49:45.642297 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 11:49:45.645259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 11:49:45.645340 ==
5307 11:49:45.648786 DQS Delay:
5308 11:49:45.648867 DQS0 = 0, DQS1 = 0
5309 11:49:45.651760 DQM Delay:
5310 11:49:45.651841 DQM0 = 104, DQM1 = 94
5311 11:49:45.651905 DQ Delay:
5312 11:49:45.655388 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5313 11:49:45.658553 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5314 11:49:45.662466 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5315 11:49:45.668410 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5316 11:49:45.668492
5317 11:49:45.668557
5318 11:49:45.674972 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5319 11:49:45.678277 CH0 RK0: MR19=505, MR18=2F26
5320 11:49:45.684867 CH0_RK0: MR19=0x505, MR18=0x2F26, DQSOSC=407, MR23=63, INC=65, DEC=43
5321 11:49:45.684950
5322 11:49:45.688847 ----->DramcWriteLeveling(PI) begin...
5323 11:49:45.688930 ==
5324 11:49:45.692002 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 11:49:45.695307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:49:45.695390 ==
5327 11:49:45.698491 Write leveling (Byte 0): 31 => 31
5328 11:49:45.701611 Write leveling (Byte 1): 28 => 28
5329 11:49:45.704637 DramcWriteLeveling(PI) end<-----
5330 11:49:45.704718
5331 11:49:45.704781 ==
5332 11:49:45.708708 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 11:49:45.711437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 11:49:45.711519 ==
5335 11:49:45.715377 [Gating] SW mode calibration
5336 11:49:45.721633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5337 11:49:45.728252 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5338 11:49:45.731329 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5339 11:49:45.738193 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 11:49:45.741232 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 11:49:45.744213 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 11:49:45.751531 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 11:49:45.754224 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 11:49:45.757476 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (0 0) (1 1)
5345 11:49:45.764220 0 14 28 | B1->B0 | 2c2c 2b2b | 0 0 | (0 0) (1 0)
5346 11:49:45.767446 0 15 0 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
5347 11:49:45.770902 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 11:49:45.777756 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 11:49:45.781087 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 11:49:45.784335 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 11:49:45.790887 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 11:49:45.794001 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5353 11:49:45.797425 0 15 28 | B1->B0 | 3636 3838 | 0 0 | (0 0) (1 1)
5354 11:49:45.803767 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 11:49:45.807552 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 11:49:45.810574 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 11:49:45.817357 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 11:49:45.820736 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 11:49:45.823932 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 11:49:45.830454 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5361 11:49:45.833749 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5362 11:49:45.837110 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 11:49:45.844008 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 11:49:45.846998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 11:49:45.850164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:49:45.853453 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:49:45.860639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:49:45.863930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:49:45.866818 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:49:45.873436 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:49:45.877024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:49:45.880033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:49:45.886742 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:49:45.889976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:49:45.893283 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:49:45.900058 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:49:45.903095 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5378 11:49:45.906991 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 11:49:45.910176 Total UI for P1: 0, mck2ui 16
5380 11:49:45.913386 best dqsien dly found for B0: ( 1, 2, 28)
5381 11:49:45.916527 Total UI for P1: 0, mck2ui 16
5382 11:49:45.919832 best dqsien dly found for B1: ( 1, 2, 30)
5383 11:49:45.923438 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5384 11:49:45.927226 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5385 11:49:45.927308
5386 11:49:45.933317 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5387 11:49:45.936798 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5388 11:49:45.936880 [Gating] SW calibration Done
5389 11:49:45.939928 ==
5390 11:49:45.943117 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 11:49:45.946980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 11:49:45.947063 ==
5393 11:49:45.947127 RX Vref Scan: 0
5394 11:49:45.947188
5395 11:49:45.950092 RX Vref 0 -> 0, step: 1
5396 11:49:45.950173
5397 11:49:45.953071 RX Delay -80 -> 252, step: 8
5398 11:49:45.956483 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5399 11:49:45.960340 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5400 11:49:45.963565 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5401 11:49:45.970068 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5402 11:49:45.973245 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5403 11:49:45.976500 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5404 11:49:45.980216 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5405 11:49:45.983412 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5406 11:49:45.986691 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5407 11:49:45.993288 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5408 11:49:45.996992 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5409 11:49:45.999827 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5410 11:49:46.003306 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5411 11:49:46.006620 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5412 11:49:46.009887 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5413 11:49:46.016408 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5414 11:49:46.016491 ==
5415 11:49:46.019662 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 11:49:46.022832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 11:49:46.022915 ==
5418 11:49:46.022979 DQS Delay:
5419 11:49:46.026611 DQS0 = 0, DQS1 = 0
5420 11:49:46.026693 DQM Delay:
5421 11:49:46.029695 DQM0 = 104, DQM1 = 93
5422 11:49:46.029803 DQ Delay:
5423 11:49:46.032920 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5424 11:49:46.036642 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5425 11:49:46.039594 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5426 11:49:46.042807 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5427 11:49:46.042889
5428 11:49:46.042952
5429 11:49:46.043012 ==
5430 11:49:46.046076 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:49:46.052723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:49:46.052804 ==
5433 11:49:46.052909
5434 11:49:46.052969
5435 11:49:46.053027 TX Vref Scan disable
5436 11:49:46.056081 == TX Byte 0 ==
5437 11:49:46.059757 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5438 11:49:46.066329 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5439 11:49:46.066411 == TX Byte 1 ==
5440 11:49:46.069420 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5441 11:49:46.076512 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5442 11:49:46.076593 ==
5443 11:49:46.079741 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 11:49:46.082910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 11:49:46.082992 ==
5446 11:49:46.083057
5447 11:49:46.083117
5448 11:49:46.085953 TX Vref Scan disable
5449 11:49:46.086038 == TX Byte 0 ==
5450 11:49:46.092535 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5451 11:49:46.095797 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5452 11:49:46.095879 == TX Byte 1 ==
5453 11:49:46.102685 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5454 11:49:46.106373 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5455 11:49:46.106454
5456 11:49:46.106519 [DATLAT]
5457 11:49:46.109536 Freq=933, CH0 RK1
5458 11:49:46.109642
5459 11:49:46.109707 DATLAT Default: 0xb
5460 11:49:46.112816 0, 0xFFFF, sum = 0
5461 11:49:46.112899 1, 0xFFFF, sum = 0
5462 11:49:46.115719 2, 0xFFFF, sum = 0
5463 11:49:46.115802 3, 0xFFFF, sum = 0
5464 11:49:46.119427 4, 0xFFFF, sum = 0
5465 11:49:46.122325 5, 0xFFFF, sum = 0
5466 11:49:46.122408 6, 0xFFFF, sum = 0
5467 11:49:46.125717 7, 0xFFFF, sum = 0
5468 11:49:46.125800 8, 0xFFFF, sum = 0
5469 11:49:46.129382 9, 0xFFFF, sum = 0
5470 11:49:46.129466 10, 0x0, sum = 1
5471 11:49:46.132530 11, 0x0, sum = 2
5472 11:49:46.132613 12, 0x0, sum = 3
5473 11:49:46.132678 13, 0x0, sum = 4
5474 11:49:46.136192 best_step = 11
5475 11:49:46.136273
5476 11:49:46.136337 ==
5477 11:49:46.139128 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 11:49:46.142952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 11:49:46.143035 ==
5480 11:49:46.145902 RX Vref Scan: 0
5481 11:49:46.145983
5482 11:49:46.146048 RX Vref 0 -> 0, step: 1
5483 11:49:46.149378
5484 11:49:46.149459 RX Delay -45 -> 252, step: 4
5485 11:49:46.156701 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5486 11:49:46.159978 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5487 11:49:46.163245 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5488 11:49:46.166481 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5489 11:49:46.170163 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5490 11:49:46.176383 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5491 11:49:46.180048 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5492 11:49:46.183292 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5493 11:49:46.186525 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5494 11:49:46.189707 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5495 11:49:46.196539 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5496 11:49:46.199818 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5497 11:49:46.203184 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5498 11:49:46.206182 iDelay=199, Bit 13, Center 96 (11 ~ 182) 172
5499 11:49:46.209906 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5500 11:49:46.216218 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5501 11:49:46.216301 ==
5502 11:49:46.219552 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 11:49:46.222730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 11:49:46.222812 ==
5505 11:49:46.222876 DQS Delay:
5506 11:49:46.225994 DQS0 = 0, DQS1 = 0
5507 11:49:46.226075 DQM Delay:
5508 11:49:46.229899 DQM0 = 104, DQM1 = 94
5509 11:49:46.230006 DQ Delay:
5510 11:49:46.232790 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5511 11:49:46.236341 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =110
5512 11:49:46.239392 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5513 11:49:46.242729 DQ12 =100, DQ13 =96, DQ14 =104, DQ15 =102
5514 11:49:46.242810
5515 11:49:46.242874
5516 11:49:46.252966 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5517 11:49:46.253050 CH0 RK1: MR19=505, MR18=2D05
5518 11:49:46.259827 CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43
5519 11:49:46.262755 [RxdqsGatingPostProcess] freq 933
5520 11:49:46.269212 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5521 11:49:46.272863 best DQS0 dly(2T, 0.5T) = (0, 10)
5522 11:49:46.276183 best DQS1 dly(2T, 0.5T) = (0, 11)
5523 11:49:46.279252 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5524 11:49:46.282289 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5525 11:49:46.285956 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 11:49:46.289190 best DQS1 dly(2T, 0.5T) = (0, 10)
5527 11:49:46.292522 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 11:49:46.296266 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5529 11:49:46.296348 Pre-setting of DQS Precalculation
5530 11:49:46.302703 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5531 11:49:46.302785 ==
5532 11:49:46.305982 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 11:49:46.309369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 11:49:46.309452 ==
5535 11:49:46.315847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 11:49:46.322330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5537 11:49:46.325521 [CA 0] Center 36 (6~67) winsize 62
5538 11:49:46.328658 [CA 1] Center 37 (6~68) winsize 63
5539 11:49:46.331934 [CA 2] Center 34 (4~65) winsize 62
5540 11:49:46.335787 [CA 3] Center 34 (4~65) winsize 62
5541 11:49:46.338927 [CA 4] Center 34 (4~64) winsize 61
5542 11:49:46.342123 [CA 5] Center 33 (3~64) winsize 62
5543 11:49:46.342204
5544 11:49:46.345249 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5545 11:49:46.345331
5546 11:49:46.348865 [CATrainingPosCal] consider 1 rank data
5547 11:49:46.351867 u2DelayCellTimex100 = 270/100 ps
5548 11:49:46.355466 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 11:49:46.358532 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5550 11:49:46.362293 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 11:49:46.365422 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 11:49:46.368595 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 11:49:46.371829 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 11:49:46.375557
5555 11:49:46.378477 CA PerBit enable=1, Macro0, CA PI delay=33
5556 11:49:46.378559
5557 11:49:46.381859 [CBTSetCACLKResult] CA Dly = 33
5558 11:49:46.381941 CS Dly: 6 (0~37)
5559 11:49:46.382007 ==
5560 11:49:46.385440 Dram Type= 6, Freq= 0, CH_1, rank 1
5561 11:49:46.388724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 11:49:46.388807 ==
5563 11:49:46.395259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 11:49:46.402133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5565 11:49:46.405292 [CA 0] Center 37 (6~68) winsize 63
5566 11:49:46.408495 [CA 1] Center 37 (6~68) winsize 63
5567 11:49:46.411760 [CA 2] Center 35 (5~66) winsize 62
5568 11:49:46.414901 [CA 3] Center 34 (4~65) winsize 62
5569 11:49:46.418653 [CA 4] Center 34 (4~65) winsize 62
5570 11:49:46.421621 [CA 5] Center 34 (4~64) winsize 61
5571 11:49:46.421703
5572 11:49:46.424905 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5573 11:49:46.424986
5574 11:49:46.428213 [CATrainingPosCal] consider 2 rank data
5575 11:49:46.431621 u2DelayCellTimex100 = 270/100 ps
5576 11:49:46.434855 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5577 11:49:46.438066 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5578 11:49:46.441725 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5579 11:49:46.444955 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5580 11:49:46.448084 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 11:49:46.455266 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5582 11:49:46.455348
5583 11:49:46.458172 CA PerBit enable=1, Macro0, CA PI delay=34
5584 11:49:46.458254
5585 11:49:46.461764 [CBTSetCACLKResult] CA Dly = 34
5586 11:49:46.461846 CS Dly: 7 (0~40)
5587 11:49:46.461912
5588 11:49:46.464789 ----->DramcWriteLeveling(PI) begin...
5589 11:49:46.464871 ==
5590 11:49:46.468475 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 11:49:46.471782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 11:49:46.474879 ==
5593 11:49:46.478167 Write leveling (Byte 0): 26 => 26
5594 11:49:46.478248 Write leveling (Byte 1): 28 => 28
5595 11:49:46.481316 DramcWriteLeveling(PI) end<-----
5596 11:49:46.481398
5597 11:49:46.481462 ==
5598 11:49:46.485076 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 11:49:46.491365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 11:49:46.491448 ==
5601 11:49:46.495118 [Gating] SW mode calibration
5602 11:49:46.501548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5603 11:49:46.505033 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5604 11:49:46.511211 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 11:49:46.514652 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 11:49:46.517900 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 11:49:46.524516 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 11:49:46.527983 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 11:49:46.531171 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 11:49:46.537701 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5611 11:49:46.540985 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
5612 11:49:46.544942 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 11:49:46.551281 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 11:49:46.554430 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 11:49:46.557605 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 11:49:46.564669 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 11:49:46.567591 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 11:49:46.570760 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5619 11:49:46.574528 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5620 11:49:46.580894 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 11:49:46.584154 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 11:49:46.587559 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 11:49:46.594085 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 11:49:46.598160 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 11:49:46.601327 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 11:49:46.607456 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5627 11:49:46.610709 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 11:49:46.614699 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 11:49:46.620718 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 11:49:46.624377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 11:49:46.627815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 11:49:46.634152 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 11:49:46.637900 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 11:49:46.640933 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 11:49:46.647574 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 11:49:46.650742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 11:49:46.654668 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 11:49:46.660950 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 11:49:46.664073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:49:46.667811 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:49:46.674022 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:49:46.677821 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 11:49:46.680935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5644 11:49:46.684246 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 11:49:46.687445 Total UI for P1: 0, mck2ui 16
5646 11:49:46.690638 best dqsien dly found for B0: ( 1, 2, 26)
5647 11:49:46.694451 Total UI for P1: 0, mck2ui 16
5648 11:49:46.697556 best dqsien dly found for B1: ( 1, 2, 26)
5649 11:49:46.700888 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5650 11:49:46.704086 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5651 11:49:46.707383
5652 11:49:46.711225 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5653 11:49:46.714210 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5654 11:49:46.717491 [Gating] SW calibration Done
5655 11:49:46.717572 ==
5656 11:49:46.720765 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 11:49:46.724144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 11:49:46.724226 ==
5659 11:49:46.724291 RX Vref Scan: 0
5660 11:49:46.724350
5661 11:49:46.727356 RX Vref 0 -> 0, step: 1
5662 11:49:46.727438
5663 11:49:46.730438 RX Delay -80 -> 252, step: 8
5664 11:49:46.734344 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5665 11:49:46.737487 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5666 11:49:46.743775 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5667 11:49:46.747734 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5668 11:49:46.750485 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5669 11:49:46.754065 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5670 11:49:46.757323 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5671 11:49:46.760237 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5672 11:49:46.767381 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5673 11:49:46.770647 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5674 11:49:46.773639 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5675 11:49:46.777383 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5676 11:49:46.780781 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5677 11:49:46.783787 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5678 11:49:46.790576 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5679 11:49:46.793822 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5680 11:49:46.793903 ==
5681 11:49:46.796964 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 11:49:46.800111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 11:49:46.800192 ==
5684 11:49:46.803301 DQS Delay:
5685 11:49:46.803381 DQS0 = 0, DQS1 = 0
5686 11:49:46.806570 DQM Delay:
5687 11:49:46.806651 DQM0 = 102, DQM1 = 98
5688 11:49:46.806715 DQ Delay:
5689 11:49:46.810202 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5690 11:49:46.813880 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5691 11:49:46.817067 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5692 11:49:46.820079 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5693 11:49:46.823332
5694 11:49:46.823413
5695 11:49:46.823480 ==
5696 11:49:46.826644 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:49:46.829883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:49:46.829964 ==
5699 11:49:46.830029
5700 11:49:46.830088
5701 11:49:46.833107 TX Vref Scan disable
5702 11:49:46.833188 == TX Byte 0 ==
5703 11:49:46.840077 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5704 11:49:46.843255 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5705 11:49:46.843340 == TX Byte 1 ==
5706 11:49:46.849762 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 11:49:46.853542 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 11:49:46.853665 ==
5709 11:49:46.856654 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 11:49:46.859932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 11:49:46.860014 ==
5712 11:49:46.860078
5713 11:49:46.860137
5714 11:49:46.863129 TX Vref Scan disable
5715 11:49:46.866787 == TX Byte 0 ==
5716 11:49:46.870048 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5717 11:49:46.872905 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5718 11:49:46.876475 == TX Byte 1 ==
5719 11:49:46.879860 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5720 11:49:46.883133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5721 11:49:46.883214
5722 11:49:46.886414 [DATLAT]
5723 11:49:46.886532 Freq=933, CH1 RK0
5724 11:49:46.886635
5725 11:49:46.889896 DATLAT Default: 0xd
5726 11:49:46.889978 0, 0xFFFF, sum = 0
5727 11:49:46.892830 1, 0xFFFF, sum = 0
5728 11:49:46.892912 2, 0xFFFF, sum = 0
5729 11:49:46.896118 3, 0xFFFF, sum = 0
5730 11:49:46.896201 4, 0xFFFF, sum = 0
5731 11:49:46.899354 5, 0xFFFF, sum = 0
5732 11:49:46.899437 6, 0xFFFF, sum = 0
5733 11:49:46.903208 7, 0xFFFF, sum = 0
5734 11:49:46.903291 8, 0xFFFF, sum = 0
5735 11:49:46.906374 9, 0xFFFF, sum = 0
5736 11:49:46.906456 10, 0x0, sum = 1
5737 11:49:46.909532 11, 0x0, sum = 2
5738 11:49:46.909666 12, 0x0, sum = 3
5739 11:49:46.912751 13, 0x0, sum = 4
5740 11:49:46.912833 best_step = 11
5741 11:49:46.912897
5742 11:49:46.912956 ==
5743 11:49:46.916086 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 11:49:46.922497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 11:49:46.922585 ==
5746 11:49:46.922651 RX Vref Scan: 1
5747 11:49:46.922712
5748 11:49:46.926168 RX Vref 0 -> 0, step: 1
5749 11:49:46.926249
5750 11:49:46.929373 RX Delay -45 -> 252, step: 4
5751 11:49:46.929454
5752 11:49:46.932703 Set Vref, RX VrefLevel [Byte0]: 53
5753 11:49:46.936110 [Byte1]: 54
5754 11:49:46.936191
5755 11:49:46.939134 Final RX Vref Byte 0 = 53 to rank0
5756 11:49:46.943129 Final RX Vref Byte 1 = 54 to rank0
5757 11:49:46.946481 Final RX Vref Byte 0 = 53 to rank1
5758 11:49:46.949530 Final RX Vref Byte 1 = 54 to rank1==
5759 11:49:46.952839 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 11:49:46.956131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 11:49:46.956212 ==
5762 11:49:46.959227 DQS Delay:
5763 11:49:46.959308 DQS0 = 0, DQS1 = 0
5764 11:49:46.959372 DQM Delay:
5765 11:49:46.962394 DQM0 = 103, DQM1 = 99
5766 11:49:46.962474 DQ Delay:
5767 11:49:46.966451 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5768 11:49:46.969679 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5769 11:49:46.972830 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =92
5770 11:49:46.979174 DQ12 =104, DQ13 =106, DQ14 =106, DQ15 =106
5771 11:49:46.979255
5772 11:49:46.979318
5773 11:49:46.985953 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5774 11:49:46.988956 CH1 RK0: MR19=505, MR18=1A31
5775 11:49:46.995528 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5776 11:49:46.995612
5777 11:49:46.998878 ----->DramcWriteLeveling(PI) begin...
5778 11:49:46.999006 ==
5779 11:49:47.002595 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 11:49:47.005469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:49:47.005551 ==
5782 11:49:47.009110 Write leveling (Byte 0): 27 => 27
5783 11:49:47.012501 Write leveling (Byte 1): 27 => 27
5784 11:49:47.015649 DramcWriteLeveling(PI) end<-----
5785 11:49:47.015731
5786 11:49:47.015796 ==
5787 11:49:47.019044 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 11:49:47.022327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 11:49:47.022410 ==
5790 11:49:47.026247 [Gating] SW mode calibration
5791 11:49:47.032614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5792 11:49:47.038752 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5793 11:49:47.042034 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 11:49:47.049007 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 11:49:47.052234 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 11:49:47.055310 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 11:49:47.059105 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 11:49:47.065739 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5799 11:49:47.068921 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5800 11:49:47.072270 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
5801 11:49:47.078631 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 11:49:47.082393 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 11:49:47.085391 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 11:49:47.091956 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 11:49:47.095605 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 11:49:47.098888 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 11:49:47.105561 0 15 24 | B1->B0 | 3b3a 2e2e | 1 0 | (0 0) (0 0)
5808 11:49:47.108674 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
5809 11:49:47.112291 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 11:49:47.118890 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 11:49:47.121817 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 11:49:47.125552 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 11:49:47.132347 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 11:49:47.135505 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 11:49:47.138629 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5816 11:49:47.145338 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5817 11:49:47.148566 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 11:49:47.151758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 11:49:47.158500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 11:49:47.162041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 11:49:47.165221 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 11:49:47.171692 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 11:49:47.175633 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 11:49:47.178807 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 11:49:47.182108 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 11:49:47.188459 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 11:49:47.192236 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 11:49:47.195274 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 11:49:47.202075 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 11:49:47.205613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5831 11:49:47.208807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5832 11:49:47.215442 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5833 11:49:47.215524 Total UI for P1: 0, mck2ui 16
5834 11:49:47.221968 best dqsien dly found for B0: ( 1, 2, 26)
5835 11:49:47.225130 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 11:49:47.228209 Total UI for P1: 0, mck2ui 16
5837 11:49:47.231381 best dqsien dly found for B1: ( 1, 2, 24)
5838 11:49:47.234784 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5839 11:49:47.238209 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5840 11:49:47.238291
5841 11:49:47.241923 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5842 11:49:47.244842 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5843 11:49:47.248521 [Gating] SW calibration Done
5844 11:49:47.248602 ==
5845 11:49:47.251448 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 11:49:47.254920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 11:49:47.258092 ==
5848 11:49:47.258173 RX Vref Scan: 0
5849 11:49:47.258237
5850 11:49:47.261501 RX Vref 0 -> 0, step: 1
5851 11:49:47.261610
5852 11:49:47.264666 RX Delay -80 -> 252, step: 8
5853 11:49:47.268316 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5854 11:49:47.271555 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5855 11:49:47.274754 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5856 11:49:47.278181 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5857 11:49:47.281465 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5858 11:49:47.287958 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5859 11:49:47.291475 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5860 11:49:47.294693 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5861 11:49:47.298364 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5862 11:49:47.301456 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5863 11:49:47.304681 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5864 11:49:47.311329 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5865 11:49:47.314458 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5866 11:49:47.318215 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5867 11:49:47.321144 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5868 11:49:47.324815 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5869 11:49:47.324897 ==
5870 11:49:47.327970 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 11:49:47.334517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 11:49:47.334598 ==
5873 11:49:47.334662 DQS Delay:
5874 11:49:47.337801 DQS0 = 0, DQS1 = 0
5875 11:49:47.337882 DQM Delay:
5876 11:49:47.341073 DQM0 = 103, DQM1 = 98
5877 11:49:47.341155 DQ Delay:
5878 11:49:47.344307 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5879 11:49:47.347958 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5880 11:49:47.351131 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5881 11:49:47.354684 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5882 11:49:47.354766
5883 11:49:47.354831
5884 11:49:47.354891 ==
5885 11:49:47.357747 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 11:49:47.361214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 11:49:47.361296 ==
5888 11:49:47.361361
5889 11:49:47.361421
5890 11:49:47.364473 TX Vref Scan disable
5891 11:49:47.367659 == TX Byte 0 ==
5892 11:49:47.371560 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5893 11:49:47.374634 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5894 11:49:47.377788 == TX Byte 1 ==
5895 11:49:47.381583 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5896 11:49:47.385025 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5897 11:49:47.385107 ==
5898 11:49:47.388211 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 11:49:47.394694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 11:49:47.394780 ==
5901 11:49:47.394845
5902 11:49:47.394905
5903 11:49:47.394962 TX Vref Scan disable
5904 11:49:47.398455 == TX Byte 0 ==
5905 11:49:47.401727 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5906 11:49:47.405376 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5907 11:49:47.408402 == TX Byte 1 ==
5908 11:49:47.411721 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5909 11:49:47.414865 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5910 11:49:47.418402
5911 11:49:47.418483 [DATLAT]
5912 11:49:47.418547 Freq=933, CH1 RK1
5913 11:49:47.418608
5914 11:49:47.421394 DATLAT Default: 0xb
5915 11:49:47.421476 0, 0xFFFF, sum = 0
5916 11:49:47.425110 1, 0xFFFF, sum = 0
5917 11:49:47.425194 2, 0xFFFF, sum = 0
5918 11:49:47.428075 3, 0xFFFF, sum = 0
5919 11:49:47.428158 4, 0xFFFF, sum = 0
5920 11:49:47.431835 5, 0xFFFF, sum = 0
5921 11:49:47.435060 6, 0xFFFF, sum = 0
5922 11:49:47.435143 7, 0xFFFF, sum = 0
5923 11:49:47.438282 8, 0xFFFF, sum = 0
5924 11:49:47.438365 9, 0xFFFF, sum = 0
5925 11:49:47.441608 10, 0x0, sum = 1
5926 11:49:47.441691 11, 0x0, sum = 2
5927 11:49:47.441757 12, 0x0, sum = 3
5928 11:49:47.444815 13, 0x0, sum = 4
5929 11:49:47.444898 best_step = 11
5930 11:49:47.444962
5931 11:49:47.445022 ==
5932 11:49:47.448007 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 11:49:47.454884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 11:49:47.454966 ==
5935 11:49:47.455031 RX Vref Scan: 0
5936 11:49:47.455092
5937 11:49:47.458529 RX Vref 0 -> 0, step: 1
5938 11:49:47.458611
5939 11:49:47.461884 RX Delay -45 -> 252, step: 4
5940 11:49:47.465107 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5941 11:49:47.471805 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5942 11:49:47.474778 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5943 11:49:47.478168 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5944 11:49:47.481400 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5945 11:49:47.484924 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5946 11:49:47.488122 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5947 11:49:47.495179 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5948 11:49:47.498277 iDelay=203, Bit 8, Center 86 (3 ~ 170) 168
5949 11:49:47.501492 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5950 11:49:47.504719 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5951 11:49:47.508092 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5952 11:49:47.514782 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5953 11:49:47.518150 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5954 11:49:47.521875 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5955 11:49:47.524996 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5956 11:49:47.525120 ==
5957 11:49:47.528084 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 11:49:47.531566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 11:49:47.535121 ==
5960 11:49:47.535203 DQS Delay:
5961 11:49:47.535268 DQS0 = 0, DQS1 = 0
5962 11:49:47.538196 DQM Delay:
5963 11:49:47.538278 DQM0 = 105, DQM1 = 99
5964 11:49:47.541327 DQ Delay:
5965 11:49:47.545216 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5966 11:49:47.548379 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5967 11:49:47.551571 DQ8 =86, DQ9 =90, DQ10 =100, DQ11 =92
5968 11:49:47.554825 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5969 11:49:47.554907
5970 11:49:47.554972
5971 11:49:47.561201 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5972 11:49:47.565004 CH1 RK1: MR19=505, MR18=2C01
5973 11:49:47.571486 CH1_RK1: MR19=0x505, MR18=0x2C01, DQSOSC=408, MR23=63, INC=65, DEC=43
5974 11:49:47.574778 [RxdqsGatingPostProcess] freq 933
5975 11:49:47.581287 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5976 11:49:47.584503 best DQS0 dly(2T, 0.5T) = (0, 10)
5977 11:49:47.584589 best DQS1 dly(2T, 0.5T) = (0, 10)
5978 11:49:47.588307 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5979 11:49:47.591424 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5980 11:49:47.594579 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 11:49:47.598090 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 11:49:47.601301 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 11:49:47.604275 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 11:49:47.607524 Pre-setting of DQS Precalculation
5985 11:49:47.614704 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5986 11:49:47.621338 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5987 11:49:47.627722 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5988 11:49:47.627804
5989 11:49:47.627869
5990 11:49:47.630885 [Calibration Summary] 1866 Mbps
5991 11:49:47.630967 CH 0, Rank 0
5992 11:49:47.634055 SW Impedance : PASS
5993 11:49:47.637072 DUTY Scan : NO K
5994 11:49:47.637154 ZQ Calibration : PASS
5995 11:49:47.640647 Jitter Meter : NO K
5996 11:49:47.644246 CBT Training : PASS
5997 11:49:47.644327 Write leveling : PASS
5998 11:49:47.647235 RX DQS gating : PASS
5999 11:49:47.650595 RX DQ/DQS(RDDQC) : PASS
6000 11:49:47.650677 TX DQ/DQS : PASS
6001 11:49:47.653914 RX DATLAT : PASS
6002 11:49:47.653995 RX DQ/DQS(Engine): PASS
6003 11:49:47.657714 TX OE : NO K
6004 11:49:47.657796 All Pass.
6005 11:49:47.657860
6006 11:49:47.660717 CH 0, Rank 1
6007 11:49:47.660798 SW Impedance : PASS
6008 11:49:47.664172 DUTY Scan : NO K
6009 11:49:47.667248 ZQ Calibration : PASS
6010 11:49:47.667329 Jitter Meter : NO K
6011 11:49:47.670386 CBT Training : PASS
6012 11:49:47.674132 Write leveling : PASS
6013 11:49:47.674213 RX DQS gating : PASS
6014 11:49:47.677469 RX DQ/DQS(RDDQC) : PASS
6015 11:49:47.680705 TX DQ/DQS : PASS
6016 11:49:47.680787 RX DATLAT : PASS
6017 11:49:47.683925 RX DQ/DQS(Engine): PASS
6018 11:49:47.687249 TX OE : NO K
6019 11:49:47.687331 All Pass.
6020 11:49:47.687394
6021 11:49:47.687454 CH 1, Rank 0
6022 11:49:47.690374 SW Impedance : PASS
6023 11:49:47.694243 DUTY Scan : NO K
6024 11:49:47.694325 ZQ Calibration : PASS
6025 11:49:47.697626 Jitter Meter : NO K
6026 11:49:47.700776 CBT Training : PASS
6027 11:49:47.700857 Write leveling : PASS
6028 11:49:47.703969 RX DQS gating : PASS
6029 11:49:47.704051 RX DQ/DQS(RDDQC) : PASS
6030 11:49:47.707096 TX DQ/DQS : PASS
6031 11:49:47.710816 RX DATLAT : PASS
6032 11:49:47.710898 RX DQ/DQS(Engine): PASS
6033 11:49:47.713879 TX OE : NO K
6034 11:49:47.713961 All Pass.
6035 11:49:47.714025
6036 11:49:47.716946 CH 1, Rank 1
6037 11:49:47.717028 SW Impedance : PASS
6038 11:49:47.720667 DUTY Scan : NO K
6039 11:49:47.723633 ZQ Calibration : PASS
6040 11:49:47.723715 Jitter Meter : NO K
6041 11:49:47.727217 CBT Training : PASS
6042 11:49:47.730420 Write leveling : PASS
6043 11:49:47.730501 RX DQS gating : PASS
6044 11:49:47.733763 RX DQ/DQS(RDDQC) : PASS
6045 11:49:47.736977 TX DQ/DQS : PASS
6046 11:49:47.737059 RX DATLAT : PASS
6047 11:49:47.740790 RX DQ/DQS(Engine): PASS
6048 11:49:47.743820 TX OE : NO K
6049 11:49:47.743902 All Pass.
6050 11:49:47.743967
6051 11:49:47.744027 DramC Write-DBI off
6052 11:49:47.747094 PER_BANK_REFRESH: Hybrid Mode
6053 11:49:47.750217 TX_TRACKING: ON
6054 11:49:47.756911 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6055 11:49:47.760304 [FAST_K] Save calibration result to emmc
6056 11:49:47.767075 dramc_set_vcore_voltage set vcore to 650000
6057 11:49:47.767158 Read voltage for 400, 6
6058 11:49:47.770422 Vio18 = 0
6059 11:49:47.770504 Vcore = 650000
6060 11:49:47.770568 Vdram = 0
6061 11:49:47.770628 Vddq = 0
6062 11:49:47.773427 Vmddr = 0
6063 11:49:47.777019 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6064 11:49:47.783655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6065 11:49:47.786930 MEM_TYPE=3, freq_sel=20
6066 11:49:47.787011 sv_algorithm_assistance_LP4_800
6067 11:49:47.793339 ============ PULL DRAM RESETB DOWN ============
6068 11:49:47.796628 ========== PULL DRAM RESETB DOWN end =========
6069 11:49:47.800468 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6070 11:49:47.803755 ===================================
6071 11:49:47.806903 LPDDR4 DRAM CONFIGURATION
6072 11:49:47.810189 ===================================
6073 11:49:47.813321 EX_ROW_EN[0] = 0x0
6074 11:49:47.813420 EX_ROW_EN[1] = 0x0
6075 11:49:47.817043 LP4Y_EN = 0x0
6076 11:49:47.817124 WORK_FSP = 0x0
6077 11:49:47.820162 WL = 0x2
6078 11:49:47.820244 RL = 0x2
6079 11:49:47.823308 BL = 0x2
6080 11:49:47.823390 RPST = 0x0
6081 11:49:47.826594 RD_PRE = 0x0
6082 11:49:47.826675 WR_PRE = 0x1
6083 11:49:47.829861 WR_PST = 0x0
6084 11:49:47.829942 DBI_WR = 0x0
6085 11:49:47.833723 DBI_RD = 0x0
6086 11:49:47.833804 OTF = 0x1
6087 11:49:47.836960 ===================================
6088 11:49:47.840276 ===================================
6089 11:49:47.843536 ANA top config
6090 11:49:47.846607 ===================================
6091 11:49:47.849859 DLL_ASYNC_EN = 0
6092 11:49:47.849941 ALL_SLAVE_EN = 1
6093 11:49:47.853310 NEW_RANK_MODE = 1
6094 11:49:47.856862 DLL_IDLE_MODE = 1
6095 11:49:47.860178 LP45_APHY_COMB_EN = 1
6096 11:49:47.860259 TX_ODT_DIS = 1
6097 11:49:47.863593 NEW_8X_MODE = 1
6098 11:49:47.866820 ===================================
6099 11:49:47.870276 ===================================
6100 11:49:47.873718 data_rate = 800
6101 11:49:47.876935 CKR = 1
6102 11:49:47.880074 DQ_P2S_RATIO = 4
6103 11:49:47.883433 ===================================
6104 11:49:47.886761 CA_P2S_RATIO = 4
6105 11:49:47.886866 DQ_CA_OPEN = 0
6106 11:49:47.890015 DQ_SEMI_OPEN = 1
6107 11:49:47.893247 CA_SEMI_OPEN = 1
6108 11:49:47.897138 CA_FULL_RATE = 0
6109 11:49:47.900169 DQ_CKDIV4_EN = 0
6110 11:49:47.903477 CA_CKDIV4_EN = 1
6111 11:49:47.903560 CA_PREDIV_EN = 0
6112 11:49:47.906685 PH8_DLY = 0
6113 11:49:47.910571 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6114 11:49:47.913796 DQ_AAMCK_DIV = 0
6115 11:49:47.917084 CA_AAMCK_DIV = 0
6116 11:49:47.917165 CA_ADMCK_DIV = 4
6117 11:49:47.920189 DQ_TRACK_CA_EN = 0
6118 11:49:47.923425 CA_PICK = 800
6119 11:49:47.927181 CA_MCKIO = 400
6120 11:49:47.930413 MCKIO_SEMI = 400
6121 11:49:47.933751 PLL_FREQ = 3016
6122 11:49:47.936910 DQ_UI_PI_RATIO = 32
6123 11:49:47.940164 CA_UI_PI_RATIO = 32
6124 11:49:47.943331 ===================================
6125 11:49:47.946614 ===================================
6126 11:49:47.946696 memory_type:LPDDR4
6127 11:49:47.949834 GP_NUM : 10
6128 11:49:47.953532 SRAM_EN : 1
6129 11:49:47.953637 MD32_EN : 0
6130 11:49:47.956939 ===================================
6131 11:49:47.960292 [ANA_INIT] >>>>>>>>>>>>>>
6132 11:49:47.963503 <<<<<< [CONFIGURE PHASE]: ANA_TX
6133 11:49:47.966530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6134 11:49:47.970232 ===================================
6135 11:49:47.973267 data_rate = 800,PCW = 0X7400
6136 11:49:47.976967 ===================================
6137 11:49:47.980194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6138 11:49:47.983412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 11:49:47.996542 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6140 11:49:48.000166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6141 11:49:48.003616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6142 11:49:48.006713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6143 11:49:48.010249 [ANA_INIT] flow start
6144 11:49:48.010331 [ANA_INIT] PLL >>>>>>>>
6145 11:49:48.013545 [ANA_INIT] PLL <<<<<<<<
6146 11:49:48.016474 [ANA_INIT] MIDPI >>>>>>>>
6147 11:49:48.016556 [ANA_INIT] MIDPI <<<<<<<<
6148 11:49:48.019930 [ANA_INIT] DLL >>>>>>>>
6149 11:49:48.023415 [ANA_INIT] flow end
6150 11:49:48.026328 ============ LP4 DIFF to SE enter ============
6151 11:49:48.029971 ============ LP4 DIFF to SE exit ============
6152 11:49:48.033180 [ANA_INIT] <<<<<<<<<<<<<
6153 11:49:48.036317 [Flow] Enable top DCM control >>>>>
6154 11:49:48.039626 [Flow] Enable top DCM control <<<<<
6155 11:49:48.043355 Enable DLL master slave shuffle
6156 11:49:48.046691 ==============================================================
6157 11:49:48.049960 Gating Mode config
6158 11:49:48.056606 ==============================================================
6159 11:49:48.056689 Config description:
6160 11:49:48.066650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6161 11:49:48.073218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6162 11:49:48.080018 SELPH_MODE 0: By rank 1: By Phase
6163 11:49:48.082893 ==============================================================
6164 11:49:48.086672 GAT_TRACK_EN = 0
6165 11:49:48.089939 RX_GATING_MODE = 2
6166 11:49:48.093187 RX_GATING_TRACK_MODE = 2
6167 11:49:48.096419 SELPH_MODE = 1
6168 11:49:48.099560 PICG_EARLY_EN = 1
6169 11:49:48.102857 VALID_LAT_VALUE = 1
6170 11:49:48.106561 ==============================================================
6171 11:49:48.109789 Enter into Gating configuration >>>>
6172 11:49:48.112990 Exit from Gating configuration <<<<
6173 11:49:48.116361 Enter into DVFS_PRE_config >>>>>
6174 11:49:48.129332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6175 11:49:48.132777 Exit from DVFS_PRE_config <<<<<
6176 11:49:48.132859 Enter into PICG configuration >>>>
6177 11:49:48.136013 Exit from PICG configuration <<<<
6178 11:49:48.139803 [RX_INPUT] configuration >>>>>
6179 11:49:48.142794 [RX_INPUT] configuration <<<<<
6180 11:49:48.149628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6181 11:49:48.152581 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6182 11:49:48.159401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 11:49:48.166016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 11:49:48.172703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 11:49:48.179840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 11:49:48.182930 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6187 11:49:48.186147 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6188 11:49:48.189181 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6189 11:49:48.196226 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6190 11:49:48.199341 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6191 11:49:48.202686 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 11:49:48.205957 ===================================
6193 11:49:48.209220 LPDDR4 DRAM CONFIGURATION
6194 11:49:48.213140 ===================================
6195 11:49:48.213222 EX_ROW_EN[0] = 0x0
6196 11:49:48.216314 EX_ROW_EN[1] = 0x0
6197 11:49:48.219587 LP4Y_EN = 0x0
6198 11:49:48.219669 WORK_FSP = 0x0
6199 11:49:48.222838 WL = 0x2
6200 11:49:48.222920 RL = 0x2
6201 11:49:48.226026 BL = 0x2
6202 11:49:48.226107 RPST = 0x0
6203 11:49:48.229278 RD_PRE = 0x0
6204 11:49:48.229359 WR_PRE = 0x1
6205 11:49:48.233092 WR_PST = 0x0
6206 11:49:48.233173 DBI_WR = 0x0
6207 11:49:48.236223 DBI_RD = 0x0
6208 11:49:48.236305 OTF = 0x1
6209 11:49:48.239356 ===================================
6210 11:49:48.243246 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6211 11:49:48.249429 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6212 11:49:48.252666 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 11:49:48.256277 ===================================
6214 11:49:48.259784 LPDDR4 DRAM CONFIGURATION
6215 11:49:48.262840 ===================================
6216 11:49:48.262921 EX_ROW_EN[0] = 0x10
6217 11:49:48.266263 EX_ROW_EN[1] = 0x0
6218 11:49:48.266344 LP4Y_EN = 0x0
6219 11:49:48.269450 WORK_FSP = 0x0
6220 11:49:48.269557 WL = 0x2
6221 11:49:48.272839 RL = 0x2
6222 11:49:48.272920 BL = 0x2
6223 11:49:48.276190 RPST = 0x0
6224 11:49:48.279382 RD_PRE = 0x0
6225 11:49:48.279463 WR_PRE = 0x1
6226 11:49:48.282787 WR_PST = 0x0
6227 11:49:48.282868 DBI_WR = 0x0
6228 11:49:48.286336 DBI_RD = 0x0
6229 11:49:48.286432 OTF = 0x1
6230 11:49:48.289858 ===================================
6231 11:49:48.296240 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6232 11:49:48.299838 nWR fixed to 30
6233 11:49:48.302832 [ModeRegInit_LP4] CH0 RK0
6234 11:49:48.302913 [ModeRegInit_LP4] CH0 RK1
6235 11:49:48.306530 [ModeRegInit_LP4] CH1 RK0
6236 11:49:48.309845 [ModeRegInit_LP4] CH1 RK1
6237 11:49:48.309927 match AC timing 19
6238 11:49:48.316564 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6239 11:49:48.319568 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6240 11:49:48.322964 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6241 11:49:48.329548 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6242 11:49:48.332758 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6243 11:49:48.332866 ==
6244 11:49:48.336653 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 11:49:48.339756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 11:49:48.339839 ==
6247 11:49:48.346126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 11:49:48.353309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6249 11:49:48.356480 [CA 0] Center 36 (8~64) winsize 57
6250 11:49:48.359633 [CA 1] Center 36 (8~64) winsize 57
6251 11:49:48.362769 [CA 2] Center 36 (8~64) winsize 57
6252 11:49:48.366131 [CA 3] Center 36 (8~64) winsize 57
6253 11:49:48.366213 [CA 4] Center 36 (8~64) winsize 57
6254 11:49:48.369935 [CA 5] Center 36 (8~64) winsize 57
6255 11:49:48.370042
6256 11:49:48.376281 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6257 11:49:48.376363
6258 11:49:48.379318 [CATrainingPosCal] consider 1 rank data
6259 11:49:48.382992 u2DelayCellTimex100 = 270/100 ps
6260 11:49:48.386147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 11:49:48.389426 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 11:49:48.392631 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 11:49:48.396176 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 11:49:48.399206 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 11:49:48.402853 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 11:49:48.402935
6267 11:49:48.405915 CA PerBit enable=1, Macro0, CA PI delay=36
6268 11:49:48.405997
6269 11:49:48.409557 [CBTSetCACLKResult] CA Dly = 36
6270 11:49:48.412887 CS Dly: 1 (0~32)
6271 11:49:48.412968 ==
6272 11:49:48.415991 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 11:49:48.419447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 11:49:48.419529 ==
6275 11:49:48.425765 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 11:49:48.429466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6277 11:49:48.432644 [CA 0] Center 36 (8~64) winsize 57
6278 11:49:48.436014 [CA 1] Center 36 (8~64) winsize 57
6279 11:49:48.439378 [CA 2] Center 36 (8~64) winsize 57
6280 11:49:48.442505 [CA 3] Center 36 (8~64) winsize 57
6281 11:49:48.445887 [CA 4] Center 36 (8~64) winsize 57
6282 11:49:48.449231 [CA 5] Center 36 (8~64) winsize 57
6283 11:49:48.449313
6284 11:49:48.452531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6285 11:49:48.452612
6286 11:49:48.455796 [CATrainingPosCal] consider 2 rank data
6287 11:49:48.459025 u2DelayCellTimex100 = 270/100 ps
6288 11:49:48.462284 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:49:48.466117 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:49:48.472727 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:49:48.475814 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:49:48.478961 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:49:48.482265 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:49:48.482352
6295 11:49:48.485857 CA PerBit enable=1, Macro0, CA PI delay=36
6296 11:49:48.485938
6297 11:49:48.488938 [CBTSetCACLKResult] CA Dly = 36
6298 11:49:48.489020 CS Dly: 1 (0~32)
6299 11:49:48.489084
6300 11:49:48.492754 ----->DramcWriteLeveling(PI) begin...
6301 11:49:48.496023 ==
6302 11:49:48.496105 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 11:49:48.502339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 11:49:48.502423 ==
6305 11:49:48.505470 Write leveling (Byte 0): 40 => 8
6306 11:49:48.509432 Write leveling (Byte 1): 40 => 8
6307 11:49:48.509529 DramcWriteLeveling(PI) end<-----
6308 11:49:48.512669
6309 11:49:48.512762 ==
6310 11:49:48.515952 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 11:49:48.519184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 11:49:48.519265 ==
6313 11:49:48.522227 [Gating] SW mode calibration
6314 11:49:48.528852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6315 11:49:48.532368 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6316 11:49:48.539154 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 11:49:48.542381 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6318 11:49:48.545362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 11:49:48.552449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 11:49:48.555625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 11:49:48.558932 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 11:49:48.565885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 11:49:48.569191 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 11:49:48.572306 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 11:49:48.575592 Total UI for P1: 0, mck2ui 16
6326 11:49:48.578784 best dqsien dly found for B0: ( 0, 14, 24)
6327 11:49:48.581939 Total UI for P1: 0, mck2ui 16
6328 11:49:48.585173 best dqsien dly found for B1: ( 0, 14, 24)
6329 11:49:48.588467 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6330 11:49:48.592187 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6331 11:49:48.592271
6332 11:49:48.599164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 11:49:48.602271 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6334 11:49:48.605530 [Gating] SW calibration Done
6335 11:49:48.605654 ==
6336 11:49:48.608601 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 11:49:48.612434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 11:49:48.612536 ==
6339 11:49:48.612626 RX Vref Scan: 0
6340 11:49:48.612715
6341 11:49:48.615650 RX Vref 0 -> 0, step: 1
6342 11:49:48.615749
6343 11:49:48.618801 RX Delay -410 -> 252, step: 16
6344 11:49:48.622186 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6345 11:49:48.628505 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6346 11:49:48.631785 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6347 11:49:48.635574 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6348 11:49:48.638630 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6349 11:49:48.642377 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6350 11:49:48.648780 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6351 11:49:48.652192 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6352 11:49:48.655256 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6353 11:49:48.658874 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6354 11:49:48.665098 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6355 11:49:48.668747 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6356 11:49:48.672148 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6357 11:49:48.675059 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6358 11:49:48.681943 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6359 11:49:48.685014 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6360 11:49:48.685095 ==
6361 11:49:48.688782 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 11:49:48.692002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 11:49:48.692084 ==
6364 11:49:48.695333 DQS Delay:
6365 11:49:48.695417 DQS0 = 27, DQS1 = 35
6366 11:49:48.698426 DQM Delay:
6367 11:49:48.698507 DQM0 = 10, DQM1 = 11
6368 11:49:48.701978 DQ Delay:
6369 11:49:48.702061 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6370 11:49:48.705012 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6371 11:49:48.708220 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6372 11:49:48.711386 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6373 11:49:48.711467
6374 11:49:48.711530
6375 11:49:48.711589 ==
6376 11:49:48.714522 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 11:49:48.721718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 11:49:48.721799 ==
6379 11:49:48.721862
6380 11:49:48.721921
6381 11:49:48.724942 TX Vref Scan disable
6382 11:49:48.725023 == TX Byte 0 ==
6383 11:49:48.728173 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 11:49:48.731468 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 11:49:48.734597 == TX Byte 1 ==
6386 11:49:48.738438 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 11:49:48.741560 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 11:49:48.741681 ==
6389 11:49:48.744981 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 11:49:48.751431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 11:49:48.751513 ==
6392 11:49:48.751578
6393 11:49:48.751637
6394 11:49:48.751695 TX Vref Scan disable
6395 11:49:48.755159 == TX Byte 0 ==
6396 11:49:48.758318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 11:49:48.761326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 11:49:48.765011 == TX Byte 1 ==
6399 11:49:48.768391 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 11:49:48.771563 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 11:49:48.771645
6402 11:49:48.774658 [DATLAT]
6403 11:49:48.774739 Freq=400, CH0 RK0
6404 11:49:48.774804
6405 11:49:48.778407 DATLAT Default: 0xf
6406 11:49:48.778489 0, 0xFFFF, sum = 0
6407 11:49:48.781539 1, 0xFFFF, sum = 0
6408 11:49:48.781668 2, 0xFFFF, sum = 0
6409 11:49:48.784997 3, 0xFFFF, sum = 0
6410 11:49:48.785080 4, 0xFFFF, sum = 0
6411 11:49:48.788405 5, 0xFFFF, sum = 0
6412 11:49:48.788488 6, 0xFFFF, sum = 0
6413 11:49:48.791244 7, 0xFFFF, sum = 0
6414 11:49:48.794941 8, 0xFFFF, sum = 0
6415 11:49:48.795025 9, 0xFFFF, sum = 0
6416 11:49:48.798153 10, 0xFFFF, sum = 0
6417 11:49:48.798236 11, 0xFFFF, sum = 0
6418 11:49:48.801447 12, 0xFFFF, sum = 0
6419 11:49:48.801557 13, 0x0, sum = 1
6420 11:49:48.804696 14, 0x0, sum = 2
6421 11:49:48.804779 15, 0x0, sum = 3
6422 11:49:48.808378 16, 0x0, sum = 4
6423 11:49:48.808461 best_step = 14
6424 11:49:48.808525
6425 11:49:48.808586 ==
6426 11:49:48.811411 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 11:49:48.814424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 11:49:48.814507 ==
6429 11:49:48.817797 RX Vref Scan: 1
6430 11:49:48.817893
6431 11:49:48.820956 RX Vref 0 -> 0, step: 1
6432 11:49:48.821057
6433 11:49:48.821158 RX Delay -311 -> 252, step: 8
6434 11:49:48.821247
6435 11:49:48.824707 Set Vref, RX VrefLevel [Byte0]: 56
6436 11:49:48.827970 [Byte1]: 47
6437 11:49:48.833281
6438 11:49:48.833390 Final RX Vref Byte 0 = 56 to rank0
6439 11:49:48.836436 Final RX Vref Byte 1 = 47 to rank0
6440 11:49:48.839671 Final RX Vref Byte 0 = 56 to rank1
6441 11:49:48.843618 Final RX Vref Byte 1 = 47 to rank1==
6442 11:49:48.846663 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 11:49:48.849901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 11:49:48.853186 ==
6445 11:49:48.853286 DQS Delay:
6446 11:49:48.853388 DQS0 = 28, DQS1 = 36
6447 11:49:48.856359 DQM Delay:
6448 11:49:48.856455 DQM0 = 10, DQM1 = 12
6449 11:49:48.860095 DQ Delay:
6450 11:49:48.863279 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6451 11:49:48.863368 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6452 11:49:48.866485 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6453 11:49:48.869666 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6454 11:49:48.869767
6455 11:49:48.873105
6456 11:49:48.880087 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6457 11:49:48.882660 CH0 RK0: MR19=C0C, MR18=CCB8
6458 11:49:48.889301 CH0_RK0: MR19=0xC0C, MR18=0xCCB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6459 11:49:48.889410 ==
6460 11:49:48.893179 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 11:49:48.896401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 11:49:48.896499 ==
6463 11:49:48.899757 [Gating] SW mode calibration
6464 11:49:48.906022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6465 11:49:48.912697 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6466 11:49:48.915819 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 11:49:48.919535 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6468 11:49:48.925871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 11:49:48.929560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 11:49:48.932490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 11:49:48.939099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 11:49:48.942649 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 11:49:48.945851 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 11:49:48.949092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 11:49:48.952159 Total UI for P1: 0, mck2ui 16
6476 11:49:48.955926 best dqsien dly found for B0: ( 0, 14, 24)
6477 11:49:48.959225 Total UI for P1: 0, mck2ui 16
6478 11:49:48.962315 best dqsien dly found for B1: ( 0, 14, 24)
6479 11:49:48.966183 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6480 11:49:48.972740 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6481 11:49:48.972813
6482 11:49:48.975968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 11:49:48.979082 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6484 11:49:48.982252 [Gating] SW calibration Done
6485 11:49:48.982327 ==
6486 11:49:48.985560 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 11:49:48.988827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 11:49:48.988923 ==
6489 11:49:48.992670 RX Vref Scan: 0
6490 11:49:48.992753
6491 11:49:48.992815 RX Vref 0 -> 0, step: 1
6492 11:49:48.992875
6493 11:49:48.995981 RX Delay -410 -> 252, step: 16
6494 11:49:48.999206 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6495 11:49:49.005564 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6496 11:49:49.008718 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6497 11:49:49.012081 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6498 11:49:49.015876 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6499 11:49:49.022332 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6500 11:49:49.025508 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6501 11:49:49.028898 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6502 11:49:49.032521 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6503 11:49:49.039096 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6504 11:49:49.042327 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6505 11:49:49.045813 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6506 11:49:49.048915 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6507 11:49:49.055671 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6508 11:49:49.059049 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6509 11:49:49.062137 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6510 11:49:49.062212 ==
6511 11:49:49.065631 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 11:49:49.071943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 11:49:49.072028 ==
6514 11:49:49.072093 DQS Delay:
6515 11:49:49.075341 DQS0 = 27, DQS1 = 35
6516 11:49:49.075422 DQM Delay:
6517 11:49:49.075528 DQM0 = 11, DQM1 = 11
6518 11:49:49.078477 DQ Delay:
6519 11:49:49.078559 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6520 11:49:49.082353 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6521 11:49:49.085417 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6522 11:49:49.088579 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6523 11:49:49.088662
6524 11:49:49.088726
6525 11:49:49.092040 ==
6526 11:49:49.092123 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 11:49:49.099294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 11:49:49.099377 ==
6529 11:49:49.099467
6530 11:49:49.099567
6531 11:49:49.102445 TX Vref Scan disable
6532 11:49:49.102526 == TX Byte 0 ==
6533 11:49:49.105055 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6534 11:49:49.112266 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6535 11:49:49.112348 == TX Byte 1 ==
6536 11:49:49.115368 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6537 11:49:49.118642 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6538 11:49:49.121932 ==
6539 11:49:49.125237 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 11:49:49.128407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 11:49:49.128489 ==
6542 11:49:49.128554
6543 11:49:49.128614
6544 11:49:49.131636 TX Vref Scan disable
6545 11:49:49.131744 == TX Byte 0 ==
6546 11:49:49.135345 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6547 11:49:49.141695 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6548 11:49:49.141777 == TX Byte 1 ==
6549 11:49:49.144915 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6550 11:49:49.152104 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6551 11:49:49.152186
6552 11:49:49.152249 [DATLAT]
6553 11:49:49.152308 Freq=400, CH0 RK1
6554 11:49:49.152366
6555 11:49:49.155330 DATLAT Default: 0xe
6556 11:49:49.155428 0, 0xFFFF, sum = 0
6557 11:49:49.158706 1, 0xFFFF, sum = 0
6558 11:49:49.161831 2, 0xFFFF, sum = 0
6559 11:49:49.161914 3, 0xFFFF, sum = 0
6560 11:49:49.164873 4, 0xFFFF, sum = 0
6561 11:49:49.164956 5, 0xFFFF, sum = 0
6562 11:49:49.168874 6, 0xFFFF, sum = 0
6563 11:49:49.168957 7, 0xFFFF, sum = 0
6564 11:49:49.171711 8, 0xFFFF, sum = 0
6565 11:49:49.171793 9, 0xFFFF, sum = 0
6566 11:49:49.175457 10, 0xFFFF, sum = 0
6567 11:49:49.175540 11, 0xFFFF, sum = 0
6568 11:49:49.178594 12, 0xFFFF, sum = 0
6569 11:49:49.178676 13, 0x0, sum = 1
6570 11:49:49.181573 14, 0x0, sum = 2
6571 11:49:49.181694 15, 0x0, sum = 3
6572 11:49:49.185009 16, 0x0, sum = 4
6573 11:49:49.185126 best_step = 14
6574 11:49:49.185191
6575 11:49:49.185251 ==
6576 11:49:49.188470 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 11:49:49.191254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 11:49:49.194961 ==
6579 11:49:49.195043 RX Vref Scan: 0
6580 11:49:49.195108
6581 11:49:49.198465 RX Vref 0 -> 0, step: 1
6582 11:49:49.198547
6583 11:49:49.201491 RX Delay -311 -> 252, step: 8
6584 11:49:49.204689 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6585 11:49:49.211516 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6586 11:49:49.214652 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6587 11:49:49.218419 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6588 11:49:49.221155 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6589 11:49:49.228113 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6590 11:49:49.231375 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6591 11:49:49.234531 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6592 11:49:49.238241 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6593 11:49:49.244523 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6594 11:49:49.247796 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6595 11:49:49.251564 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6596 11:49:49.254335 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6597 11:49:49.261511 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6598 11:49:49.264781 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6599 11:49:49.268219 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6600 11:49:49.268301 ==
6601 11:49:49.271629 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 11:49:49.275154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 11:49:49.277831 ==
6604 11:49:49.277913 DQS Delay:
6605 11:49:49.277978 DQS0 = 24, DQS1 = 36
6606 11:49:49.281535 DQM Delay:
6607 11:49:49.281658 DQM0 = 7, DQM1 = 12
6608 11:49:49.284846 DQ Delay:
6609 11:49:49.284927 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6610 11:49:49.288092 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6611 11:49:49.291726 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6612 11:49:49.294878 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6613 11:49:49.294960
6614 11:49:49.295024
6615 11:49:49.304376 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6616 11:49:49.308441 CH0 RK1: MR19=C0C, MR18=BE5E
6617 11:49:49.311253 CH0_RK1: MR19=0xC0C, MR18=0xBE5E, DQSOSC=386, MR23=63, INC=396, DEC=264
6618 11:49:49.314837 [RxdqsGatingPostProcess] freq 400
6619 11:49:49.320992 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6620 11:49:49.324721 best DQS0 dly(2T, 0.5T) = (0, 10)
6621 11:49:49.327801 best DQS1 dly(2T, 0.5T) = (0, 10)
6622 11:49:49.331023 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6623 11:49:49.334312 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6624 11:49:49.337832 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 11:49:49.341149 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 11:49:49.344421 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 11:49:49.347853 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 11:49:49.351194 Pre-setting of DQS Precalculation
6629 11:49:49.354340 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6630 11:49:49.354423 ==
6631 11:49:49.357725 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 11:49:49.360862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 11:49:49.360944 ==
6634 11:49:49.368209 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 11:49:49.374681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6636 11:49:49.377955 [CA 0] Center 36 (8~64) winsize 57
6637 11:49:49.381239 [CA 1] Center 36 (8~64) winsize 57
6638 11:49:49.384449 [CA 2] Center 36 (8~64) winsize 57
6639 11:49:49.387719 [CA 3] Center 36 (8~64) winsize 57
6640 11:49:49.390944 [CA 4] Center 36 (8~64) winsize 57
6641 11:49:49.391025 [CA 5] Center 36 (8~64) winsize 57
6642 11:49:49.394051
6643 11:49:49.397949 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6644 11:49:49.398031
6645 11:49:49.400778 [CATrainingPosCal] consider 1 rank data
6646 11:49:49.403956 u2DelayCellTimex100 = 270/100 ps
6647 11:49:49.407866 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 11:49:49.410971 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 11:49:49.413988 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 11:49:49.417798 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 11:49:49.420892 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 11:49:49.424171 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 11:49:49.424252
6654 11:49:49.427393 CA PerBit enable=1, Macro0, CA PI delay=36
6655 11:49:49.427475
6656 11:49:49.431047 [CBTSetCACLKResult] CA Dly = 36
6657 11:49:49.434159 CS Dly: 1 (0~32)
6658 11:49:49.434241 ==
6659 11:49:49.437459 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 11:49:49.440552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:49:49.440634 ==
6662 11:49:49.447873 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 11:49:49.454356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6664 11:49:49.457505 [CA 0] Center 36 (8~64) winsize 57
6665 11:49:49.457613 [CA 1] Center 36 (8~64) winsize 57
6666 11:49:49.460861 [CA 2] Center 36 (8~64) winsize 57
6667 11:49:49.464220 [CA 3] Center 36 (8~64) winsize 57
6668 11:49:49.467318 [CA 4] Center 36 (8~64) winsize 57
6669 11:49:49.470458 [CA 5] Center 36 (8~64) winsize 57
6670 11:49:49.470540
6671 11:49:49.474353 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6672 11:49:49.474435
6673 11:49:49.477520 [CATrainingPosCal] consider 2 rank data
6674 11:49:49.480804 u2DelayCellTimex100 = 270/100 ps
6675 11:49:49.484067 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:49:49.490387 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:49:49.493714 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:49:49.497426 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:49:49.500780 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:49:49.503862 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:49:49.503944
6682 11:49:49.507082 CA PerBit enable=1, Macro0, CA PI delay=36
6683 11:49:49.507164
6684 11:49:49.510407 [CBTSetCACLKResult] CA Dly = 36
6685 11:49:49.510488 CS Dly: 1 (0~32)
6686 11:49:49.510553
6687 11:49:49.513692 ----->DramcWriteLeveling(PI) begin...
6688 11:49:49.517414 ==
6689 11:49:49.520554 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 11:49:49.523653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 11:49:49.523736 ==
6692 11:49:49.527544 Write leveling (Byte 0): 40 => 8
6693 11:49:49.530798 Write leveling (Byte 1): 40 => 8
6694 11:49:49.533927 DramcWriteLeveling(PI) end<-----
6695 11:49:49.534009
6696 11:49:49.534072 ==
6697 11:49:49.537524 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 11:49:49.540397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 11:49:49.540479 ==
6700 11:49:49.543706 [Gating] SW mode calibration
6701 11:49:49.550612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6702 11:49:49.553925 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6703 11:49:49.560525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 11:49:49.563737 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6705 11:49:49.567229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 11:49:49.573789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 11:49:49.576869 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 11:49:49.580457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 11:49:49.587185 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 11:49:49.590379 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 11:49:49.593772 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 11:49:49.596973 Total UI for P1: 0, mck2ui 16
6713 11:49:49.600156 best dqsien dly found for B0: ( 0, 14, 24)
6714 11:49:49.604210 Total UI for P1: 0, mck2ui 16
6715 11:49:49.607469 best dqsien dly found for B1: ( 0, 14, 24)
6716 11:49:49.610540 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6717 11:49:49.613473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6718 11:49:49.613589
6719 11:49:49.620875 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 11:49:49.624159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6721 11:49:49.627319 [Gating] SW calibration Done
6722 11:49:49.627401 ==
6723 11:49:49.630856 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 11:49:49.634278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 11:49:49.634361 ==
6726 11:49:49.634426 RX Vref Scan: 0
6727 11:49:49.634487
6728 11:49:49.637097 RX Vref 0 -> 0, step: 1
6729 11:49:49.637179
6730 11:49:49.640349 RX Delay -410 -> 252, step: 16
6731 11:49:49.643824 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6732 11:49:49.647233 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6733 11:49:49.653922 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6734 11:49:49.657103 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6735 11:49:49.660361 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6736 11:49:49.663737 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6737 11:49:49.670898 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6738 11:49:49.674265 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6739 11:49:49.677325 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6740 11:49:49.680299 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6741 11:49:49.687041 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6742 11:49:49.690793 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6743 11:49:49.693377 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6744 11:49:49.699991 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6745 11:49:49.703367 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6746 11:49:49.707079 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6747 11:49:49.707183 ==
6748 11:49:49.709994 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 11:49:49.713876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 11:49:49.713966 ==
6751 11:49:49.717080 DQS Delay:
6752 11:49:49.717156 DQS0 = 27, DQS1 = 35
6753 11:49:49.720486 DQM Delay:
6754 11:49:49.720587 DQM0 = 10, DQM1 = 12
6755 11:49:49.723549 DQ Delay:
6756 11:49:49.723622 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6757 11:49:49.726674 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6758 11:49:49.730175 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6759 11:49:49.733279 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6760 11:49:49.733377
6761 11:49:49.733465
6762 11:49:49.733551 ==
6763 11:49:49.736871 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 11:49:49.743177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 11:49:49.743256 ==
6766 11:49:49.743333
6767 11:49:49.743425
6768 11:49:49.743542 TX Vref Scan disable
6769 11:49:49.746483 == TX Byte 0 ==
6770 11:49:49.749979 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 11:49:49.753210 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 11:49:49.756927 == TX Byte 1 ==
6773 11:49:49.759869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 11:49:49.763129 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 11:49:49.766493 ==
6776 11:49:49.766598 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 11:49:49.773190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 11:49:49.773288 ==
6779 11:49:49.773387
6780 11:49:49.773474
6781 11:49:49.776472 TX Vref Scan disable
6782 11:49:49.776573 == TX Byte 0 ==
6783 11:49:49.779825 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 11:49:49.786477 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 11:49:49.786583 == TX Byte 1 ==
6786 11:49:49.789829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 11:49:49.792929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 11:49:49.796669
6789 11:49:49.796774 [DATLAT]
6790 11:49:49.796883 Freq=400, CH1 RK0
6791 11:49:49.796946
6792 11:49:49.799755 DATLAT Default: 0xf
6793 11:49:49.799858 0, 0xFFFF, sum = 0
6794 11:49:49.803270 1, 0xFFFF, sum = 0
6795 11:49:49.803423 2, 0xFFFF, sum = 0
6796 11:49:49.806325 3, 0xFFFF, sum = 0
6797 11:49:49.806427 4, 0xFFFF, sum = 0
6798 11:49:49.810089 5, 0xFFFF, sum = 0
6799 11:49:49.810165 6, 0xFFFF, sum = 0
6800 11:49:49.813117 7, 0xFFFF, sum = 0
6801 11:49:49.816231 8, 0xFFFF, sum = 0
6802 11:49:49.816342 9, 0xFFFF, sum = 0
6803 11:49:49.819944 10, 0xFFFF, sum = 0
6804 11:49:49.820045 11, 0xFFFF, sum = 0
6805 11:49:49.822829 12, 0xFFFF, sum = 0
6806 11:49:49.822934 13, 0x0, sum = 1
6807 11:49:49.826090 14, 0x0, sum = 2
6808 11:49:49.826164 15, 0x0, sum = 3
6809 11:49:49.829952 16, 0x0, sum = 4
6810 11:49:49.830055 best_step = 14
6811 11:49:49.830153
6812 11:49:49.830242 ==
6813 11:49:49.832989 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 11:49:49.836249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 11:49:49.836347 ==
6816 11:49:49.839597 RX Vref Scan: 1
6817 11:49:49.839669
6818 11:49:49.842672 RX Vref 0 -> 0, step: 1
6819 11:49:49.842774
6820 11:49:49.842855 RX Delay -311 -> 252, step: 8
6821 11:49:49.846293
6822 11:49:49.846374 Set Vref, RX VrefLevel [Byte0]: 53
6823 11:49:49.849483 [Byte1]: 54
6824 11:49:49.854716
6825 11:49:49.854819 Final RX Vref Byte 0 = 53 to rank0
6826 11:49:49.858087 Final RX Vref Byte 1 = 54 to rank0
6827 11:49:49.861321 Final RX Vref Byte 0 = 53 to rank1
6828 11:49:49.864703 Final RX Vref Byte 1 = 54 to rank1==
6829 11:49:49.867798 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 11:49:49.874881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 11:49:49.874961 ==
6832 11:49:49.875027 DQS Delay:
6833 11:49:49.878204 DQS0 = 32, DQS1 = 32
6834 11:49:49.878290 DQM Delay:
6835 11:49:49.878357 DQM0 = 13, DQM1 = 9
6836 11:49:49.881732 DQ Delay:
6837 11:49:49.885044 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6838 11:49:49.885128 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6839 11:49:49.888437 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6840 11:49:49.891156 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6841 11:49:49.894326
6842 11:49:49.894410
6843 11:49:49.901291 [DQSOSCAuto] RK0, (LSB)MR18= 0x91ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6844 11:49:49.904995 CH1 RK0: MR19=C0C, MR18=91CA
6845 11:49:49.911419 CH1_RK0: MR19=0xC0C, MR18=0x91CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6846 11:49:49.911505 ==
6847 11:49:49.914425 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 11:49:49.917500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 11:49:49.917615 ==
6850 11:49:49.920858 [Gating] SW mode calibration
6851 11:49:49.927554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6852 11:49:49.934180 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6853 11:49:49.937949 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 11:49:49.941258 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6855 11:49:49.947594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 11:49:49.950787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 11:49:49.954350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 11:49:49.960703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 11:49:49.964078 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 11:49:49.967296 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 11:49:49.971200 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 11:49:49.974116 Total UI for P1: 0, mck2ui 16
6863 11:49:49.977920 best dqsien dly found for B0: ( 0, 14, 24)
6864 11:49:49.981288 Total UI for P1: 0, mck2ui 16
6865 11:49:49.984569 best dqsien dly found for B1: ( 0, 14, 24)
6866 11:49:49.987387 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6867 11:49:49.994454 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6868 11:49:49.994538
6869 11:49:49.997774 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 11:49:50.001092 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6871 11:49:50.004351 [Gating] SW calibration Done
6872 11:49:50.004434 ==
6873 11:49:50.007682 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 11:49:50.010869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 11:49:50.010951 ==
6876 11:49:50.014089 RX Vref Scan: 0
6877 11:49:50.014189
6878 11:49:50.014257 RX Vref 0 -> 0, step: 1
6879 11:49:50.014319
6880 11:49:50.017466 RX Delay -410 -> 252, step: 16
6881 11:49:50.020658 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6882 11:49:50.027082 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6883 11:49:50.030594 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6884 11:49:50.033806 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6885 11:49:50.037315 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6886 11:49:50.044281 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6887 11:49:50.047024 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6888 11:49:50.050596 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6889 11:49:50.053909 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6890 11:49:50.060434 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6891 11:49:50.063553 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6892 11:49:50.067158 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6893 11:49:50.070437 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6894 11:49:50.077357 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6895 11:49:50.080338 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6896 11:49:50.083851 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6897 11:49:50.083933 ==
6898 11:49:50.087131 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 11:49:50.093637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 11:49:50.093748 ==
6901 11:49:50.093863 DQS Delay:
6902 11:49:50.097045 DQS0 = 35, DQS1 = 35
6903 11:49:50.097158 DQM Delay:
6904 11:49:50.097224 DQM0 = 17, DQM1 = 14
6905 11:49:50.100412 DQ Delay:
6906 11:49:50.103575 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6907 11:49:50.106811 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6908 11:49:50.110182 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6909 11:49:50.113371 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6910 11:49:50.113452
6911 11:49:50.113516
6912 11:49:50.113582 ==
6913 11:49:50.117353 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 11:49:50.120558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 11:49:50.120641 ==
6916 11:49:50.120705
6917 11:49:50.120765
6918 11:49:50.123844 TX Vref Scan disable
6919 11:49:50.123925 == TX Byte 0 ==
6920 11:49:50.127058 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6921 11:49:50.133368 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6922 11:49:50.133450 == TX Byte 1 ==
6923 11:49:50.137151 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6924 11:49:50.143839 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6925 11:49:50.143921 ==
6926 11:49:50.146954 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 11:49:50.150277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 11:49:50.150384 ==
6929 11:49:50.150451
6930 11:49:50.150512
6931 11:49:50.153757 TX Vref Scan disable
6932 11:49:50.153837 == TX Byte 0 ==
6933 11:49:50.156891 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6934 11:49:50.163621 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6935 11:49:50.163702 == TX Byte 1 ==
6936 11:49:50.166573 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6937 11:49:50.173373 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6938 11:49:50.173455
6939 11:49:50.173519 [DATLAT]
6940 11:49:50.176373 Freq=400, CH1 RK1
6941 11:49:50.176514
6942 11:49:50.176611 DATLAT Default: 0xe
6943 11:49:50.179959 0, 0xFFFF, sum = 0
6944 11:49:50.180041 1, 0xFFFF, sum = 0
6945 11:49:50.183311 2, 0xFFFF, sum = 0
6946 11:49:50.183392 3, 0xFFFF, sum = 0
6947 11:49:50.186580 4, 0xFFFF, sum = 0
6948 11:49:50.186688 5, 0xFFFF, sum = 0
6949 11:49:50.190048 6, 0xFFFF, sum = 0
6950 11:49:50.190150 7, 0xFFFF, sum = 0
6951 11:49:50.193742 8, 0xFFFF, sum = 0
6952 11:49:50.193841 9, 0xFFFF, sum = 0
6953 11:49:50.196432 10, 0xFFFF, sum = 0
6954 11:49:50.196541 11, 0xFFFF, sum = 0
6955 11:49:50.199859 12, 0xFFFF, sum = 0
6956 11:49:50.199942 13, 0x0, sum = 1
6957 11:49:50.203151 14, 0x0, sum = 2
6958 11:49:50.203233 15, 0x0, sum = 3
6959 11:49:50.206970 16, 0x0, sum = 4
6960 11:49:50.207052 best_step = 14
6961 11:49:50.207116
6962 11:49:50.207174 ==
6963 11:49:50.210238 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 11:49:50.216784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 11:49:50.216866 ==
6966 11:49:50.216931 RX Vref Scan: 0
6967 11:49:50.216992
6968 11:49:50.220105 RX Vref 0 -> 0, step: 1
6969 11:49:50.220186
6970 11:49:50.223283 RX Delay -311 -> 252, step: 8
6971 11:49:50.229484 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6972 11:49:50.233208 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6973 11:49:50.236277 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6974 11:49:50.239984 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6975 11:49:50.246339 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6976 11:49:50.250072 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6977 11:49:50.253204 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6978 11:49:50.256387 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6979 11:49:50.262831 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6980 11:49:50.266553 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6981 11:49:50.270057 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6982 11:49:50.272689 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6983 11:49:50.279621 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6984 11:49:50.283099 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6985 11:49:50.286264 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6986 11:49:50.289910 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6987 11:49:50.290017 ==
6988 11:49:50.292740 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 11:49:50.299724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 11:49:50.299833 ==
6991 11:49:50.299925 DQS Delay:
6992 11:49:50.303011 DQS0 = 28, DQS1 = 36
6993 11:49:50.303097 DQM Delay:
6994 11:49:50.306860 DQM0 = 11, DQM1 = 15
6995 11:49:50.306940 DQ Delay:
6996 11:49:50.309514 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6997 11:49:50.313365 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6998 11:49:50.313447 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6999 11:49:50.319449 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7000 11:49:50.319530
7001 11:49:50.319594
7002 11:49:50.326397 [DQSOSCAuto] RK1, (LSB)MR18= 0xc356, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7003 11:49:50.329747 CH1 RK1: MR19=C0C, MR18=C356
7004 11:49:50.336091 CH1_RK1: MR19=0xC0C, MR18=0xC356, DQSOSC=385, MR23=63, INC=398, DEC=265
7005 11:49:50.339298 [RxdqsGatingPostProcess] freq 400
7006 11:49:50.342779 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7007 11:49:50.346108 best DQS0 dly(2T, 0.5T) = (0, 10)
7008 11:49:50.349240 best DQS1 dly(2T, 0.5T) = (0, 10)
7009 11:49:50.352380 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7010 11:49:50.356103 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7011 11:49:50.359216 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 11:49:50.362632 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 11:49:50.365712 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 11:49:50.368995 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 11:49:50.372333 Pre-setting of DQS Precalculation
7016 11:49:50.375573 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7017 11:49:50.385732 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7018 11:49:50.392857 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7019 11:49:50.392938
7020 11:49:50.393001
7021 11:49:50.396183 [Calibration Summary] 800 Mbps
7022 11:49:50.396264 CH 0, Rank 0
7023 11:49:50.399345 SW Impedance : PASS
7024 11:49:50.399426 DUTY Scan : NO K
7025 11:49:50.402529 ZQ Calibration : PASS
7026 11:49:50.405615 Jitter Meter : NO K
7027 11:49:50.405711 CBT Training : PASS
7028 11:49:50.409329 Write leveling : PASS
7029 11:49:50.409436 RX DQS gating : PASS
7030 11:49:50.412655 RX DQ/DQS(RDDQC) : PASS
7031 11:49:50.415896 TX DQ/DQS : PASS
7032 11:49:50.415977 RX DATLAT : PASS
7033 11:49:50.419042 RX DQ/DQS(Engine): PASS
7034 11:49:50.422611 TX OE : NO K
7035 11:49:50.422693 All Pass.
7036 11:49:50.422757
7037 11:49:50.422817 CH 0, Rank 1
7038 11:49:50.425941 SW Impedance : PASS
7039 11:49:50.429236 DUTY Scan : NO K
7040 11:49:50.429316 ZQ Calibration : PASS
7041 11:49:50.432213 Jitter Meter : NO K
7042 11:49:50.435570 CBT Training : PASS
7043 11:49:50.435670 Write leveling : NO K
7044 11:49:50.439327 RX DQS gating : PASS
7045 11:49:50.442447 RX DQ/DQS(RDDQC) : PASS
7046 11:49:50.442528 TX DQ/DQS : PASS
7047 11:49:50.445501 RX DATLAT : PASS
7048 11:49:50.449434 RX DQ/DQS(Engine): PASS
7049 11:49:50.449516 TX OE : NO K
7050 11:49:50.449586 All Pass.
7051 11:49:50.452589
7052 11:49:50.452698 CH 1, Rank 0
7053 11:49:50.455661 SW Impedance : PASS
7054 11:49:50.455743 DUTY Scan : NO K
7055 11:49:50.459277 ZQ Calibration : PASS
7056 11:49:50.462322 Jitter Meter : NO K
7057 11:49:50.462403 CBT Training : PASS
7058 11:49:50.465486 Write leveling : PASS
7059 11:49:50.465568 RX DQS gating : PASS
7060 11:49:50.468770 RX DQ/DQS(RDDQC) : PASS
7061 11:49:50.472638 TX DQ/DQS : PASS
7062 11:49:50.472719 RX DATLAT : PASS
7063 11:49:50.475721 RX DQ/DQS(Engine): PASS
7064 11:49:50.478924 TX OE : NO K
7065 11:49:50.479005 All Pass.
7066 11:49:50.479069
7067 11:49:50.479129 CH 1, Rank 1
7068 11:49:50.482154 SW Impedance : PASS
7069 11:49:50.485316 DUTY Scan : NO K
7070 11:49:50.485396 ZQ Calibration : PASS
7071 11:49:50.489157 Jitter Meter : NO K
7072 11:49:50.492308 CBT Training : PASS
7073 11:49:50.492389 Write leveling : NO K
7074 11:49:50.495558 RX DQS gating : PASS
7075 11:49:50.498799 RX DQ/DQS(RDDQC) : PASS
7076 11:49:50.498880 TX DQ/DQS : PASS
7077 11:49:50.502583 RX DATLAT : PASS
7078 11:49:50.502664 RX DQ/DQS(Engine): PASS
7079 11:49:50.505723 TX OE : NO K
7080 11:49:50.505805 All Pass.
7081 11:49:50.505869
7082 11:49:50.508845 DramC Write-DBI off
7083 11:49:50.512547 PER_BANK_REFRESH: Hybrid Mode
7084 11:49:50.512628 TX_TRACKING: ON
7085 11:49:50.522331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7086 11:49:50.525502 [FAST_K] Save calibration result to emmc
7087 11:49:50.528691 dramc_set_vcore_voltage set vcore to 725000
7088 11:49:50.532047 Read voltage for 1600, 0
7089 11:49:50.532128 Vio18 = 0
7090 11:49:50.535341 Vcore = 725000
7091 11:49:50.535422 Vdram = 0
7092 11:49:50.535486 Vddq = 0
7093 11:49:50.535545 Vmddr = 0
7094 11:49:50.542094 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7095 11:49:50.548788 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7096 11:49:50.548902 MEM_TYPE=3, freq_sel=13
7097 11:49:50.552298 sv_algorithm_assistance_LP4_3733
7098 11:49:50.555591 ============ PULL DRAM RESETB DOWN ============
7099 11:49:50.561914 ========== PULL DRAM RESETB DOWN end =========
7100 11:49:50.565514 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7101 11:49:50.568883 ===================================
7102 11:49:50.572161 LPDDR4 DRAM CONFIGURATION
7103 11:49:50.575357 ===================================
7104 11:49:50.575439 EX_ROW_EN[0] = 0x0
7105 11:49:50.578993 EX_ROW_EN[1] = 0x0
7106 11:49:50.579075 LP4Y_EN = 0x0
7107 11:49:50.581921 WORK_FSP = 0x1
7108 11:49:50.582001 WL = 0x5
7109 11:49:50.585335 RL = 0x5
7110 11:49:50.585416 BL = 0x2
7111 11:49:50.588894 RPST = 0x0
7112 11:49:50.588975 RD_PRE = 0x0
7113 11:49:50.592172 WR_PRE = 0x1
7114 11:49:50.595328 WR_PST = 0x1
7115 11:49:50.595409 DBI_WR = 0x0
7116 11:49:50.598618 DBI_RD = 0x0
7117 11:49:50.598699 OTF = 0x1
7118 11:49:50.601942 ===================================
7119 11:49:50.605374 ===================================
7120 11:49:50.605455 ANA top config
7121 11:49:50.608549 ===================================
7122 11:49:50.611806 DLL_ASYNC_EN = 0
7123 11:49:50.615045 ALL_SLAVE_EN = 0
7124 11:49:50.618645 NEW_RANK_MODE = 1
7125 11:49:50.622040 DLL_IDLE_MODE = 1
7126 11:49:50.622121 LP45_APHY_COMB_EN = 1
7127 11:49:50.625136 TX_ODT_DIS = 0
7128 11:49:50.628439 NEW_8X_MODE = 1
7129 11:49:50.631580 ===================================
7130 11:49:50.635511 ===================================
7131 11:49:50.638672 data_rate = 3200
7132 11:49:50.641908 CKR = 1
7133 11:49:50.641990 DQ_P2S_RATIO = 8
7134 11:49:50.645091 ===================================
7135 11:49:50.648339 CA_P2S_RATIO = 8
7136 11:49:50.652052 DQ_CA_OPEN = 0
7137 11:49:50.655295 DQ_SEMI_OPEN = 0
7138 11:49:50.658560 CA_SEMI_OPEN = 0
7139 11:49:50.661607 CA_FULL_RATE = 0
7140 11:49:50.661688 DQ_CKDIV4_EN = 0
7141 11:49:50.665461 CA_CKDIV4_EN = 0
7142 11:49:50.668378 CA_PREDIV_EN = 0
7143 11:49:50.671442 PH8_DLY = 12
7144 11:49:50.675119 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7145 11:49:50.678371 DQ_AAMCK_DIV = 4
7146 11:49:50.678452 CA_AAMCK_DIV = 4
7147 11:49:50.682124 CA_ADMCK_DIV = 4
7148 11:49:50.685118 DQ_TRACK_CA_EN = 0
7149 11:49:50.688760 CA_PICK = 1600
7150 11:49:50.691828 CA_MCKIO = 1600
7151 11:49:50.695142 MCKIO_SEMI = 0
7152 11:49:50.698450 PLL_FREQ = 3068
7153 11:49:50.698531 DQ_UI_PI_RATIO = 32
7154 11:49:50.701692 CA_UI_PI_RATIO = 0
7155 11:49:50.704887 ===================================
7156 11:49:50.708254 ===================================
7157 11:49:50.711959 memory_type:LPDDR4
7158 11:49:50.715292 GP_NUM : 10
7159 11:49:50.715389 SRAM_EN : 1
7160 11:49:50.718434 MD32_EN : 0
7161 11:49:50.721475 ===================================
7162 11:49:50.725308 [ANA_INIT] >>>>>>>>>>>>>>
7163 11:49:50.725405 <<<<<< [CONFIGURE PHASE]: ANA_TX
7164 11:49:50.728440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7165 11:49:50.731718 ===================================
7166 11:49:50.735048 data_rate = 3200,PCW = 0X7600
7167 11:49:50.738082 ===================================
7168 11:49:50.741350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7169 11:49:50.748234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 11:49:50.754559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7171 11:49:50.758299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7172 11:49:50.761667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7173 11:49:50.764955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7174 11:49:50.768097 [ANA_INIT] flow start
7175 11:49:50.768194 [ANA_INIT] PLL >>>>>>>>
7176 11:49:50.771208 [ANA_INIT] PLL <<<<<<<<
7177 11:49:50.774956 [ANA_INIT] MIDPI >>>>>>>>
7178 11:49:50.775057 [ANA_INIT] MIDPI <<<<<<<<
7179 11:49:50.777865 [ANA_INIT] DLL >>>>>>>>
7180 11:49:50.781347 [ANA_INIT] DLL <<<<<<<<
7181 11:49:50.781445 [ANA_INIT] flow end
7182 11:49:50.788241 ============ LP4 DIFF to SE enter ============
7183 11:49:50.791556 ============ LP4 DIFF to SE exit ============
7184 11:49:50.794648 [ANA_INIT] <<<<<<<<<<<<<
7185 11:49:50.798012 [Flow] Enable top DCM control >>>>>
7186 11:49:50.801258 [Flow] Enable top DCM control <<<<<
7187 11:49:50.801367 Enable DLL master slave shuffle
7188 11:49:50.807707 ==============================================================
7189 11:49:50.811348 Gating Mode config
7190 11:49:50.814875 ==============================================================
7191 11:49:50.817725 Config description:
7192 11:49:50.828084 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7193 11:49:50.834757 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7194 11:49:50.838024 SELPH_MODE 0: By rank 1: By Phase
7195 11:49:50.844311 ==============================================================
7196 11:49:50.847510 GAT_TRACK_EN = 1
7197 11:49:50.851320 RX_GATING_MODE = 2
7198 11:49:50.854432 RX_GATING_TRACK_MODE = 2
7199 11:49:50.857584 SELPH_MODE = 1
7200 11:49:50.857694 PICG_EARLY_EN = 1
7201 11:49:50.860784 VALID_LAT_VALUE = 1
7202 11:49:50.867827 ==============================================================
7203 11:49:50.871146 Enter into Gating configuration >>>>
7204 11:49:50.874427 Exit from Gating configuration <<<<
7205 11:49:50.877484 Enter into DVFS_PRE_config >>>>>
7206 11:49:50.887681 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7207 11:49:50.891249 Exit from DVFS_PRE_config <<<<<
7208 11:49:50.894486 Enter into PICG configuration >>>>
7209 11:49:50.897699 Exit from PICG configuration <<<<
7210 11:49:50.900826 [RX_INPUT] configuration >>>>>
7211 11:49:50.904646 [RX_INPUT] configuration <<<<<
7212 11:49:50.907718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7213 11:49:50.914165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7214 11:49:50.921122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 11:49:50.927572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 11:49:50.933908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 11:49:50.937480 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 11:49:50.944209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7219 11:49:50.947226 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7220 11:49:50.950776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7221 11:49:50.954083 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7222 11:49:50.960466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7223 11:49:50.963635 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 11:49:50.967057 ===================================
7225 11:49:50.970869 LPDDR4 DRAM CONFIGURATION
7226 11:49:50.973968 ===================================
7227 11:49:50.974076 EX_ROW_EN[0] = 0x0
7228 11:49:50.977256 EX_ROW_EN[1] = 0x0
7229 11:49:50.977340 LP4Y_EN = 0x0
7230 11:49:50.980559 WORK_FSP = 0x1
7231 11:49:50.980666 WL = 0x5
7232 11:49:50.983776 RL = 0x5
7233 11:49:50.983882 BL = 0x2
7234 11:49:50.986935 RPST = 0x0
7235 11:49:50.990421 RD_PRE = 0x0
7236 11:49:50.990502 WR_PRE = 0x1
7237 11:49:50.993488 WR_PST = 0x1
7238 11:49:50.993570 DBI_WR = 0x0
7239 11:49:50.996799 DBI_RD = 0x0
7240 11:49:50.996880 OTF = 0x1
7241 11:49:51.000419 ===================================
7242 11:49:51.003459 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7243 11:49:51.007295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7244 11:49:51.013481 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 11:49:51.016937 ===================================
7246 11:49:51.020345 LPDDR4 DRAM CONFIGURATION
7247 11:49:51.023556 ===================================
7248 11:49:51.023638 EX_ROW_EN[0] = 0x10
7249 11:49:51.026670 EX_ROW_EN[1] = 0x0
7250 11:49:51.026750 LP4Y_EN = 0x0
7251 11:49:51.030337 WORK_FSP = 0x1
7252 11:49:51.030418 WL = 0x5
7253 11:49:51.033686 RL = 0x5
7254 11:49:51.033767 BL = 0x2
7255 11:49:51.036901 RPST = 0x0
7256 11:49:51.037011 RD_PRE = 0x0
7257 11:49:51.040147 WR_PRE = 0x1
7258 11:49:51.040227 WR_PST = 0x1
7259 11:49:51.043378 DBI_WR = 0x0
7260 11:49:51.046590 DBI_RD = 0x0
7261 11:49:51.046671 OTF = 0x1
7262 11:49:51.050320 ===================================
7263 11:49:51.056799 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7264 11:49:51.056907 ==
7265 11:49:51.059749 Dram Type= 6, Freq= 0, CH_0, rank 0
7266 11:49:51.063209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7267 11:49:51.063291 ==
7268 11:49:51.066712 [Duty_Offset_Calibration]
7269 11:49:51.066794 B0:2 B1:1 CA:1
7270 11:49:51.066857
7271 11:49:51.069740 [DutyScan_Calibration_Flow] k_type=0
7272 11:49:51.081304
7273 11:49:51.081385 ==CLK 0==
7274 11:49:51.084499 Final CLK duty delay cell = 0
7275 11:49:51.088380 [0] MAX Duty = 5156%(X100), DQS PI = 22
7276 11:49:51.091662 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 11:49:51.091743 [0] AVG Duty = 5031%(X100)
7278 11:49:51.094855
7279 11:49:51.094936 CH0 CLK Duty spec in!! Max-Min= 249%
7280 11:49:51.101306 [DutyScan_Calibration_Flow] ====Done====
7281 11:49:51.101389
7282 11:49:51.104785 [DutyScan_Calibration_Flow] k_type=1
7283 11:49:51.120736
7284 11:49:51.120818 ==DQS 0 ==
7285 11:49:51.123992 Final DQS duty delay cell = -4
7286 11:49:51.127180 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7287 11:49:51.130370 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7288 11:49:51.133461 [-4] AVG Duty = 4906%(X100)
7289 11:49:51.133544
7290 11:49:51.133633 ==DQS 1 ==
7291 11:49:51.137202 Final DQS duty delay cell = 0
7292 11:49:51.140481 [0] MAX Duty = 5187%(X100), DQS PI = 4
7293 11:49:51.143822 [0] MIN Duty = 5062%(X100), DQS PI = 34
7294 11:49:51.146840 [0] AVG Duty = 5124%(X100)
7295 11:49:51.146921
7296 11:49:51.150285 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7297 11:49:51.150366
7298 11:49:51.153497 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7299 11:49:51.156845 [DutyScan_Calibration_Flow] ====Done====
7300 11:49:51.156925
7301 11:49:51.159930 [DutyScan_Calibration_Flow] k_type=3
7302 11:49:51.177206
7303 11:49:51.177287 ==DQM 0 ==
7304 11:49:51.180146 Final DQM duty delay cell = 0
7305 11:49:51.183606 [0] MAX Duty = 5187%(X100), DQS PI = 32
7306 11:49:51.186689 [0] MIN Duty = 4907%(X100), DQS PI = 0
7307 11:49:51.186771 [0] AVG Duty = 5047%(X100)
7308 11:49:51.190063
7309 11:49:51.190143 ==DQM 1 ==
7310 11:49:51.193877 Final DQM duty delay cell = -4
7311 11:49:51.197180 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7312 11:49:51.200363 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7313 11:49:51.203435 [-4] AVG Duty = 4922%(X100)
7314 11:49:51.203516
7315 11:49:51.206650 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7316 11:49:51.206731
7317 11:49:51.210368 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7318 11:49:51.213458 [DutyScan_Calibration_Flow] ====Done====
7319 11:49:51.213555
7320 11:49:51.216499 [DutyScan_Calibration_Flow] k_type=2
7321 11:49:51.234592
7322 11:49:51.234673 ==DQ 0 ==
7323 11:49:51.237493 Final DQ duty delay cell = 0
7324 11:49:51.241197 [0] MAX Duty = 5062%(X100), DQS PI = 24
7325 11:49:51.244363 [0] MIN Duty = 4907%(X100), DQS PI = 0
7326 11:49:51.244445 [0] AVG Duty = 4984%(X100)
7327 11:49:51.244509
7328 11:49:51.248271 ==DQ 1 ==
7329 11:49:51.250976 Final DQ duty delay cell = 0
7330 11:49:51.254229 [0] MAX Duty = 5156%(X100), DQS PI = 22
7331 11:49:51.258057 [0] MIN Duty = 4938%(X100), DQS PI = 34
7332 11:49:51.258138 [0] AVG Duty = 5047%(X100)
7333 11:49:51.258201
7334 11:49:51.261266 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7335 11:49:51.261370
7336 11:49:51.264657 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7337 11:49:51.271226 [DutyScan_Calibration_Flow] ====Done====
7338 11:49:51.271331 ==
7339 11:49:51.274579 Dram Type= 6, Freq= 0, CH_1, rank 0
7340 11:49:51.277830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 11:49:51.277911 ==
7342 11:49:51.281210 [Duty_Offset_Calibration]
7343 11:49:51.281317 B0:1 B1:0 CA:0
7344 11:49:51.281410
7345 11:49:51.284176 [DutyScan_Calibration_Flow] k_type=0
7346 11:49:51.293982
7347 11:49:51.294074 ==CLK 0==
7348 11:49:51.297488 Final CLK duty delay cell = -4
7349 11:49:51.300439 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7350 11:49:51.303814 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7351 11:49:51.307472 [-4] AVG Duty = 4922%(X100)
7352 11:49:51.307552
7353 11:49:51.310676 CH1 CLK Duty spec in!! Max-Min= 156%
7354 11:49:51.313903 [DutyScan_Calibration_Flow] ====Done====
7355 11:49:51.313983
7356 11:49:51.316903 [DutyScan_Calibration_Flow] k_type=1
7357 11:49:51.334214
7358 11:49:51.334294 ==DQS 0 ==
7359 11:49:51.337275 Final DQS duty delay cell = 0
7360 11:49:51.340438 [0] MAX Duty = 5094%(X100), DQS PI = 14
7361 11:49:51.343915 [0] MIN Duty = 4844%(X100), DQS PI = 48
7362 11:49:51.343995 [0] AVG Duty = 4969%(X100)
7363 11:49:51.347194
7364 11:49:51.347274 ==DQS 1 ==
7365 11:49:51.350980 Final DQS duty delay cell = 0
7366 11:49:51.354370 [0] MAX Duty = 5249%(X100), DQS PI = 16
7367 11:49:51.357469 [0] MIN Duty = 4969%(X100), DQS PI = 6
7368 11:49:51.357581 [0] AVG Duty = 5109%(X100)
7369 11:49:51.360762
7370 11:49:51.363954 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7371 11:49:51.364034
7372 11:49:51.367299 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7373 11:49:51.370649 [DutyScan_Calibration_Flow] ====Done====
7374 11:49:51.370729
7375 11:49:51.373927 [DutyScan_Calibration_Flow] k_type=3
7376 11:49:51.391207
7377 11:49:51.391286 ==DQM 0 ==
7378 11:49:51.394109 Final DQM duty delay cell = 0
7379 11:49:51.397666 [0] MAX Duty = 5218%(X100), DQS PI = 18
7380 11:49:51.400576 [0] MIN Duty = 4969%(X100), DQS PI = 48
7381 11:49:51.404234 [0] AVG Duty = 5093%(X100)
7382 11:49:51.404315
7383 11:49:51.404378 ==DQM 1 ==
7384 11:49:51.407251 Final DQM duty delay cell = 0
7385 11:49:51.410615 [0] MAX Duty = 5093%(X100), DQS PI = 16
7386 11:49:51.413677 [0] MIN Duty = 4907%(X100), DQS PI = 34
7387 11:49:51.417268 [0] AVG Duty = 5000%(X100)
7388 11:49:51.417374
7389 11:49:51.420469 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7390 11:49:51.420549
7391 11:49:51.423648 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7392 11:49:51.427554 [DutyScan_Calibration_Flow] ====Done====
7393 11:49:51.427634
7394 11:49:51.430762 [DutyScan_Calibration_Flow] k_type=2
7395 11:49:51.447273
7396 11:49:51.447354 ==DQ 0 ==
7397 11:49:51.450491 Final DQ duty delay cell = -4
7398 11:49:51.453385 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7399 11:49:51.456845 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7400 11:49:51.460247 [-4] AVG Duty = 4968%(X100)
7401 11:49:51.460327
7402 11:49:51.460390 ==DQ 1 ==
7403 11:49:51.463794 Final DQ duty delay cell = 0
7404 11:49:51.467190 [0] MAX Duty = 5093%(X100), DQS PI = 16
7405 11:49:51.470331 [0] MIN Duty = 4938%(X100), DQS PI = 8
7406 11:49:51.470412 [0] AVG Duty = 5015%(X100)
7407 11:49:51.473589
7408 11:49:51.476785 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7409 11:49:51.476865
7410 11:49:51.480111 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7411 11:49:51.483333 [DutyScan_Calibration_Flow] ====Done====
7412 11:49:51.487108 nWR fixed to 30
7413 11:49:51.487188 [ModeRegInit_LP4] CH0 RK0
7414 11:49:51.490340 [ModeRegInit_LP4] CH0 RK1
7415 11:49:51.493621 [ModeRegInit_LP4] CH1 RK0
7416 11:49:51.496680 [ModeRegInit_LP4] CH1 RK1
7417 11:49:51.496762 match AC timing 5
7418 11:49:51.503791 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7419 11:49:51.506860 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7420 11:49:51.510193 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7421 11:49:51.516758 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7422 11:49:51.520253 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7423 11:49:51.520369 [MiockJmeterHQA]
7424 11:49:51.520462
7425 11:49:51.523260 [DramcMiockJmeter] u1RxGatingPI = 0
7426 11:49:51.526952 0 : 4252, 4027
7427 11:49:51.527034 4 : 4252, 4027
7428 11:49:51.530377 8 : 4252, 4027
7429 11:49:51.530483 12 : 4252, 4027
7430 11:49:51.530614 16 : 4255, 4029
7431 11:49:51.533207 20 : 4363, 4138
7432 11:49:51.533312 24 : 4253, 4027
7433 11:49:51.536916 28 : 4253, 4026
7434 11:49:51.537022 32 : 4252, 4027
7435 11:49:51.540011 36 : 4254, 4029
7436 11:49:51.540095 40 : 4252, 4027
7437 11:49:51.540175 44 : 4363, 4138
7438 11:49:51.543228 48 : 4363, 4138
7439 11:49:51.543379 52 : 4255, 4029
7440 11:49:51.546618 56 : 4252, 4027
7441 11:49:51.546720 60 : 4252, 4027
7442 11:49:51.549915 64 : 4252, 4027
7443 11:49:51.550015 68 : 4252, 4030
7444 11:49:51.553139 72 : 4360, 4138
7445 11:49:51.553235 76 : 4250, 4027
7446 11:49:51.553328 80 : 4250, 4027
7447 11:49:51.556631 84 : 4252, 4027
7448 11:49:51.556730 88 : 4253, 292
7449 11:49:51.559795 92 : 4250, 0
7450 11:49:51.559894 96 : 4252, 0
7451 11:49:51.559996 100 : 4250, 0
7452 11:49:51.563615 104 : 4250, 0
7453 11:49:51.563687 108 : 4252, 0
7454 11:49:51.566585 112 : 4255, 0
7455 11:49:51.566685 116 : 4252, 0
7456 11:49:51.566778 120 : 4252, 0
7457 11:49:51.570315 124 : 4250, 0
7458 11:49:51.570417 128 : 4253, 0
7459 11:49:51.573164 132 : 4360, 0
7460 11:49:51.573261 136 : 4361, 0
7461 11:49:51.573354 140 : 4250, 0
7462 11:49:51.576353 144 : 4250, 0
7463 11:49:51.576453 148 : 4250, 0
7464 11:49:51.579708 152 : 4250, 0
7465 11:49:51.579786 156 : 4252, 0
7466 11:49:51.579851 160 : 4250, 0
7467 11:49:51.582907 164 : 4361, 0
7468 11:49:51.582979 168 : 4360, 0
7469 11:49:51.583045 172 : 4250, 0
7470 11:49:51.586702 176 : 4252, 0
7471 11:49:51.586777 180 : 4250, 0
7472 11:49:51.590148 184 : 4252, 0
7473 11:49:51.590223 188 : 4250, 0
7474 11:49:51.590290 192 : 4361, 0
7475 11:49:51.593318 196 : 4250, 0
7476 11:49:51.593413 200 : 4361, 0
7477 11:49:51.596682 204 : 4250, 872
7478 11:49:51.596786 208 : 4250, 3958
7479 11:49:51.599829 212 : 4250, 4027
7480 11:49:51.599933 216 : 4250, 4027
7481 11:49:51.600028 220 : 4250, 4026
7482 11:49:51.603050 224 : 4252, 4027
7483 11:49:51.603128 228 : 4360, 4138
7484 11:49:51.606416 232 : 4251, 4027
7485 11:49:51.606509 236 : 4250, 4026
7486 11:49:51.609836 240 : 4360, 4137
7487 11:49:51.609911 244 : 4250, 4027
7488 11:49:51.612942 248 : 4250, 4027
7489 11:49:51.613043 252 : 4363, 4140
7490 11:49:51.616178 256 : 4250, 4026
7491 11:49:51.616284 260 : 4250, 4027
7492 11:49:51.619851 264 : 4250, 4027
7493 11:49:51.619954 268 : 4252, 4029
7494 11:49:51.623131 272 : 4250, 4027
7495 11:49:51.623204 276 : 4250, 4027
7496 11:49:51.623266 280 : 4360, 4138
7497 11:49:51.626307 284 : 4250, 4027
7498 11:49:51.626379 288 : 4250, 4026
7499 11:49:51.629951 292 : 4361, 4137
7500 11:49:51.630026 296 : 4250, 4027
7501 11:49:51.633016 300 : 4250, 4027
7502 11:49:51.633115 304 : 4363, 4140
7503 11:49:51.636627 308 : 4250, 4008
7504 11:49:51.636728 312 : 4250, 2410
7505 11:49:51.639560 316 : 4250, 12
7506 11:49:51.639635
7507 11:49:51.639696 MIOCK jitter meter ch=0
7508 11:49:51.639754
7509 11:49:51.643215 1T = (316-88) = 228 dly cells
7510 11:49:51.649750 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7511 11:49:51.649855 ==
7512 11:49:51.653170 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 11:49:51.656169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 11:49:51.656268 ==
7515 11:49:51.662717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 11:49:51.666650 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 11:49:51.669752 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 11:49:51.675816 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 11:49:51.685859 [CA 0] Center 42 (12~73) winsize 62
7520 11:49:51.689203 [CA 1] Center 43 (12~74) winsize 63
7521 11:49:51.692443 [CA 2] Center 38 (9~68) winsize 60
7522 11:49:51.695624 [CA 3] Center 37 (8~67) winsize 60
7523 11:49:51.699573 [CA 4] Center 36 (7~66) winsize 60
7524 11:49:51.702409 [CA 5] Center 35 (6~65) winsize 60
7525 11:49:51.702515
7526 11:49:51.705964 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 11:49:51.706039
7528 11:49:51.709277 [CATrainingPosCal] consider 1 rank data
7529 11:49:51.712504 u2DelayCellTimex100 = 285/100 ps
7530 11:49:51.715674 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7531 11:49:51.722636 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7532 11:49:51.725632 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7533 11:49:51.728935 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7534 11:49:51.732629 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7535 11:49:51.735834 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7536 11:49:51.735929
7537 11:49:51.739591 CA PerBit enable=1, Macro0, CA PI delay=35
7538 11:49:51.739661
7539 11:49:51.742914 [CBTSetCACLKResult] CA Dly = 35
7540 11:49:51.742983 CS Dly: 9 (0~40)
7541 11:49:51.749495 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 11:49:51.752653 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 11:49:51.752748 ==
7544 11:49:51.755853 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 11:49:51.759159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 11:49:51.759253 ==
7547 11:49:51.766001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 11:49:51.769453 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 11:49:51.775988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 11:49:51.779128 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 11:49:51.789360 [CA 0] Center 42 (12~73) winsize 62
7552 11:49:51.792551 [CA 1] Center 42 (12~73) winsize 62
7553 11:49:51.795771 [CA 2] Center 38 (8~68) winsize 61
7554 11:49:51.798979 [CA 3] Center 37 (8~67) winsize 60
7555 11:49:51.802288 [CA 4] Center 36 (6~66) winsize 61
7556 11:49:51.805503 [CA 5] Center 34 (5~64) winsize 60
7557 11:49:51.805635
7558 11:49:51.808830 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 11:49:51.808909
7560 11:49:51.812594 [CATrainingPosCal] consider 2 rank data
7561 11:49:51.815856 u2DelayCellTimex100 = 285/100 ps
7562 11:49:51.819056 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7563 11:49:51.825487 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7564 11:49:51.828591 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7565 11:49:51.832387 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7566 11:49:51.835615 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7567 11:49:51.838859 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7568 11:49:51.838960
7569 11:49:51.841930 CA PerBit enable=1, Macro0, CA PI delay=35
7570 11:49:51.841999
7571 11:49:51.845606 [CBTSetCACLKResult] CA Dly = 35
7572 11:49:51.848720 CS Dly: 10 (0~42)
7573 11:49:51.852213 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 11:49:51.855550 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 11:49:51.855625
7576 11:49:51.858606 ----->DramcWriteLeveling(PI) begin...
7577 11:49:51.858705 ==
7578 11:49:51.862275 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 11:49:51.868210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 11:49:51.868287 ==
7581 11:49:51.871996 Write leveling (Byte 0): 38 => 38
7582 11:49:51.875407 Write leveling (Byte 1): 27 => 27
7583 11:49:51.875506 DramcWriteLeveling(PI) end<-----
7584 11:49:51.875595
7585 11:49:51.878534 ==
7586 11:49:51.882031 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 11:49:51.884975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 11:49:51.885048 ==
7589 11:49:51.888348 [Gating] SW mode calibration
7590 11:49:51.895094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 11:49:51.898264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 11:49:51.904973 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 11:49:51.908255 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 11:49:51.912002 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7595 11:49:51.918425 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7596 11:49:51.921623 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7597 11:49:51.924937 1 4 20 | B1->B0 | 3232 3535 | 1 0 | (0 0) (0 0)
7598 11:49:51.931562 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 11:49:51.934862 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 11:49:51.938478 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7601 11:49:51.945091 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7602 11:49:51.948283 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7603 11:49:51.951933 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7604 11:49:51.958210 1 5 16 | B1->B0 | 3434 2828 | 0 0 | (0 1) (0 0)
7605 11:49:51.961677 1 5 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
7606 11:49:51.964850 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7607 11:49:51.968574 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7608 11:49:51.975201 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 11:49:51.978458 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7610 11:49:51.981559 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7611 11:49:51.988207 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7612 11:49:51.991529 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7613 11:49:51.995168 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 11:49:52.001460 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7615 11:49:52.004554 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 11:49:52.008232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 11:49:52.015185 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 11:49:52.018492 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 11:49:52.021286 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 11:49:52.027938 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7621 11:49:52.031377 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 11:49:52.034663 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7623 11:49:52.041141 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:49:52.044850 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:49:52.048212 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:49:52.054737 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 11:49:52.057789 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 11:49:52.061490 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 11:49:52.067703 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:49:52.071513 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 11:49:52.074536 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 11:49:52.081031 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 11:49:52.084808 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 11:49:52.088136 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 11:49:52.094630 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 11:49:52.097709 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7637 11:49:52.101362 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 11:49:52.104680 Total UI for P1: 0, mck2ui 16
7639 11:49:52.107941 best dqsien dly found for B0: ( 1, 9, 12)
7640 11:49:52.111132 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 11:49:52.114331 Total UI for P1: 0, mck2ui 16
7642 11:49:52.118216 best dqsien dly found for B1: ( 1, 9, 18)
7643 11:49:52.121416 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7644 11:49:52.124452 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7645 11:49:52.127676
7646 11:49:52.131127 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7647 11:49:52.134302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7648 11:49:52.137964 [Gating] SW calibration Done
7649 11:49:52.138045 ==
7650 11:49:52.140917 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 11:49:52.144230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 11:49:52.144312 ==
7653 11:49:52.144376 RX Vref Scan: 0
7654 11:49:52.147970
7655 11:49:52.148050 RX Vref 0 -> 0, step: 1
7656 11:49:52.148114
7657 11:49:52.151164 RX Delay 0 -> 252, step: 8
7658 11:49:52.154337 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7659 11:49:52.157536 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7660 11:49:52.164589 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7661 11:49:52.167660 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7662 11:49:52.171222 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7663 11:49:52.174313 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7664 11:49:52.178148 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7665 11:49:52.181118 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7666 11:49:52.188196 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7667 11:49:52.191313 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7668 11:49:52.194627 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7669 11:49:52.197856 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7670 11:49:52.201175 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7671 11:49:52.207344 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7672 11:49:52.210995 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7673 11:49:52.214261 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7674 11:49:52.214341 ==
7675 11:49:52.217572 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 11:49:52.220755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 11:49:52.224624 ==
7678 11:49:52.224705 DQS Delay:
7679 11:49:52.224769 DQS0 = 0, DQS1 = 0
7680 11:49:52.227841 DQM Delay:
7681 11:49:52.227921 DQM0 = 137, DQM1 = 130
7682 11:49:52.231166 DQ Delay:
7683 11:49:52.234250 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7684 11:49:52.237398 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7685 11:49:52.240799 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7686 11:49:52.243929 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7687 11:49:52.244010
7688 11:49:52.244074
7689 11:49:52.244132 ==
7690 11:49:52.247590 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 11:49:52.251121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 11:49:52.251203 ==
7693 11:49:52.251266
7694 11:49:52.254150
7695 11:49:52.254230 TX Vref Scan disable
7696 11:49:52.257343 == TX Byte 0 ==
7697 11:49:52.260741 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7698 11:49:52.264047 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7699 11:49:52.267224 == TX Byte 1 ==
7700 11:49:52.270517 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7701 11:49:52.273741 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7702 11:49:52.273831 ==
7703 11:49:52.277362 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 11:49:52.284008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 11:49:52.284089 ==
7706 11:49:52.296745
7707 11:49:52.299892 TX Vref early break, caculate TX vref
7708 11:49:52.303194 TX Vref=16, minBit 0, minWin=22, winSum=375
7709 11:49:52.306395 TX Vref=18, minBit 0, minWin=22, winSum=383
7710 11:49:52.309533 TX Vref=20, minBit 0, minWin=23, winSum=399
7711 11:49:52.313299 TX Vref=22, minBit 3, minWin=24, winSum=406
7712 11:49:52.316540 TX Vref=24, minBit 0, minWin=24, winSum=415
7713 11:49:52.323218 TX Vref=26, minBit 2, minWin=25, winSum=422
7714 11:49:52.326743 TX Vref=28, minBit 0, minWin=25, winSum=421
7715 11:49:52.329941 TX Vref=30, minBit 6, minWin=24, winSum=409
7716 11:49:52.333192 TX Vref=32, minBit 1, minWin=24, winSum=402
7717 11:49:52.336287 TX Vref=34, minBit 0, minWin=23, winSum=392
7718 11:49:52.342900 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 26
7719 11:49:52.342982
7720 11:49:52.346511 Final TX Range 0 Vref 26
7721 11:49:52.346610
7722 11:49:52.346675 ==
7723 11:49:52.349547 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 11:49:52.353370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 11:49:52.353451 ==
7726 11:49:52.353514
7727 11:49:52.353573
7728 11:49:52.356709 TX Vref Scan disable
7729 11:49:52.362870 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7730 11:49:52.362952 == TX Byte 0 ==
7731 11:49:52.366064 u2DelayCellOfst[0]=13 cells (4 PI)
7732 11:49:52.369445 u2DelayCellOfst[1]=17 cells (5 PI)
7733 11:49:52.372714 u2DelayCellOfst[2]=13 cells (4 PI)
7734 11:49:52.376666 u2DelayCellOfst[3]=10 cells (3 PI)
7735 11:49:52.379834 u2DelayCellOfst[4]=10 cells (3 PI)
7736 11:49:52.382846 u2DelayCellOfst[5]=0 cells (0 PI)
7737 11:49:52.385935 u2DelayCellOfst[6]=17 cells (5 PI)
7738 11:49:52.389539 u2DelayCellOfst[7]=17 cells (5 PI)
7739 11:49:52.392656 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7740 11:49:52.396329 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7741 11:49:52.399556 == TX Byte 1 ==
7742 11:49:52.402758 u2DelayCellOfst[8]=0 cells (0 PI)
7743 11:49:52.402842 u2DelayCellOfst[9]=0 cells (0 PI)
7744 11:49:52.406029 u2DelayCellOfst[10]=10 cells (3 PI)
7745 11:49:52.409536 u2DelayCellOfst[11]=3 cells (1 PI)
7746 11:49:52.412618 u2DelayCellOfst[12]=10 cells (3 PI)
7747 11:49:52.415787 u2DelayCellOfst[13]=13 cells (4 PI)
7748 11:49:52.419331 u2DelayCellOfst[14]=13 cells (4 PI)
7749 11:49:52.422619 u2DelayCellOfst[15]=10 cells (3 PI)
7750 11:49:52.425894 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7751 11:49:52.432799 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7752 11:49:52.432880 DramC Write-DBI on
7753 11:49:52.432944 ==
7754 11:49:52.436032 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 11:49:52.442383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 11:49:52.442465 ==
7757 11:49:52.442530
7758 11:49:52.442589
7759 11:49:52.442646 TX Vref Scan disable
7760 11:49:52.446358 == TX Byte 0 ==
7761 11:49:52.449972 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7762 11:49:52.453163 == TX Byte 1 ==
7763 11:49:52.456412 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7764 11:49:52.456525 DramC Write-DBI off
7765 11:49:52.460186
7766 11:49:52.460297 [DATLAT]
7767 11:49:52.460391 Freq=1600, CH0 RK0
7768 11:49:52.460479
7769 11:49:52.463391 DATLAT Default: 0xf
7770 11:49:52.463488 0, 0xFFFF, sum = 0
7771 11:49:52.466572 1, 0xFFFF, sum = 0
7772 11:49:52.466648 2, 0xFFFF, sum = 0
7773 11:49:52.469869 3, 0xFFFF, sum = 0
7774 11:49:52.473117 4, 0xFFFF, sum = 0
7775 11:49:52.473216 5, 0xFFFF, sum = 0
7776 11:49:52.476785 6, 0xFFFF, sum = 0
7777 11:49:52.476885 7, 0xFFFF, sum = 0
7778 11:49:52.479666 8, 0xFFFF, sum = 0
7779 11:49:52.479767 9, 0xFFFF, sum = 0
7780 11:49:52.483305 10, 0xFFFF, sum = 0
7781 11:49:52.483404 11, 0xFFFF, sum = 0
7782 11:49:52.486387 12, 0xFFFF, sum = 0
7783 11:49:52.486483 13, 0xFFFF, sum = 0
7784 11:49:52.489514 14, 0x0, sum = 1
7785 11:49:52.489616 15, 0x0, sum = 2
7786 11:49:52.493158 16, 0x0, sum = 3
7787 11:49:52.493255 17, 0x0, sum = 4
7788 11:49:52.496086 best_step = 15
7789 11:49:52.496181
7790 11:49:52.496272 ==
7791 11:49:52.499698 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 11:49:52.502917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 11:49:52.502994 ==
7794 11:49:52.503087 RX Vref Scan: 1
7795 11:49:52.506546
7796 11:49:52.506642 Set Vref Range= 24 -> 127
7797 11:49:52.506729
7798 11:49:52.509361 RX Vref 24 -> 127, step: 1
7799 11:49:52.509454
7800 11:49:52.513100 RX Delay 27 -> 252, step: 4
7801 11:49:52.513193
7802 11:49:52.516487 Set Vref, RX VrefLevel [Byte0]: 24
7803 11:49:52.519603 [Byte1]: 24
7804 11:49:52.519698
7805 11:49:52.523173 Set Vref, RX VrefLevel [Byte0]: 25
7806 11:49:52.526308 [Byte1]: 25
7807 11:49:52.526405
7808 11:49:52.529537 Set Vref, RX VrefLevel [Byte0]: 26
7809 11:49:52.532749 [Byte1]: 26
7810 11:49:52.536458
7811 11:49:52.536531 Set Vref, RX VrefLevel [Byte0]: 27
7812 11:49:52.539729 [Byte1]: 27
7813 11:49:52.544226
7814 11:49:52.544327 Set Vref, RX VrefLevel [Byte0]: 28
7815 11:49:52.547431 [Byte1]: 28
7816 11:49:52.551811
7817 11:49:52.551892 Set Vref, RX VrefLevel [Byte0]: 29
7818 11:49:52.555020 [Byte1]: 29
7819 11:49:52.559318
7820 11:49:52.559401 Set Vref, RX VrefLevel [Byte0]: 30
7821 11:49:52.562600 [Byte1]: 30
7822 11:49:52.567135
7823 11:49:52.567215 Set Vref, RX VrefLevel [Byte0]: 31
7824 11:49:52.570157 [Byte1]: 31
7825 11:49:52.574112
7826 11:49:52.574192 Set Vref, RX VrefLevel [Byte0]: 32
7827 11:49:52.577452 [Byte1]: 32
7828 11:49:52.582002
7829 11:49:52.582083 Set Vref, RX VrefLevel [Byte0]: 33
7830 11:49:52.585110 [Byte1]: 33
7831 11:49:52.589310
7832 11:49:52.589393 Set Vref, RX VrefLevel [Byte0]: 34
7833 11:49:52.592966 [Byte1]: 34
7834 11:49:52.596987
7835 11:49:52.597085 Set Vref, RX VrefLevel [Byte0]: 35
7836 11:49:52.600121 [Byte1]: 35
7837 11:49:52.604360
7838 11:49:52.604440 Set Vref, RX VrefLevel [Byte0]: 36
7839 11:49:52.607845 [Byte1]: 36
7840 11:49:52.612053
7841 11:49:52.612133 Set Vref, RX VrefLevel [Byte0]: 37
7842 11:49:52.615100 [Byte1]: 37
7843 11:49:52.619591
7844 11:49:52.619672 Set Vref, RX VrefLevel [Byte0]: 38
7845 11:49:52.622773 [Byte1]: 38
7846 11:49:52.627177
7847 11:49:52.627258 Set Vref, RX VrefLevel [Byte0]: 39
7848 11:49:52.630164 [Byte1]: 39
7849 11:49:52.634580
7850 11:49:52.634660 Set Vref, RX VrefLevel [Byte0]: 40
7851 11:49:52.637555 [Byte1]: 40
7852 11:49:52.642022
7853 11:49:52.642130 Set Vref, RX VrefLevel [Byte0]: 41
7854 11:49:52.645388 [Byte1]: 41
7855 11:49:52.649817
7856 11:49:52.649906 Set Vref, RX VrefLevel [Byte0]: 42
7857 11:49:52.652973 [Byte1]: 42
7858 11:49:52.657249
7859 11:49:52.657360 Set Vref, RX VrefLevel [Byte0]: 43
7860 11:49:52.660890 [Byte1]: 43
7861 11:49:52.664557
7862 11:49:52.664664 Set Vref, RX VrefLevel [Byte0]: 44
7863 11:49:52.667829 [Byte1]: 44
7864 11:49:52.672464
7865 11:49:52.672562 Set Vref, RX VrefLevel [Byte0]: 45
7866 11:49:52.675648 [Byte1]: 45
7867 11:49:52.679715
7868 11:49:52.679812 Set Vref, RX VrefLevel [Byte0]: 46
7869 11:49:52.682845 [Byte1]: 46
7870 11:49:52.687416
7871 11:49:52.687488 Set Vref, RX VrefLevel [Byte0]: 47
7872 11:49:52.690712 [Byte1]: 47
7873 11:49:52.694706
7874 11:49:52.694803 Set Vref, RX VrefLevel [Byte0]: 48
7875 11:49:52.697849 [Byte1]: 48
7876 11:49:52.702261
7877 11:49:52.702336 Set Vref, RX VrefLevel [Byte0]: 49
7878 11:49:52.705860 [Byte1]: 49
7879 11:49:52.709833
7880 11:49:52.709913 Set Vref, RX VrefLevel [Byte0]: 50
7881 11:49:52.713081 [Byte1]: 50
7882 11:49:52.717480
7883 11:49:52.717584 Set Vref, RX VrefLevel [Byte0]: 51
7884 11:49:52.720811 [Byte1]: 51
7885 11:49:52.724789
7886 11:49:52.724891 Set Vref, RX VrefLevel [Byte0]: 52
7887 11:49:52.728401 [Byte1]: 52
7888 11:49:52.732649
7889 11:49:52.732746 Set Vref, RX VrefLevel [Byte0]: 53
7890 11:49:52.735669 [Byte1]: 53
7891 11:49:52.740146
7892 11:49:52.740220 Set Vref, RX VrefLevel [Byte0]: 54
7893 11:49:52.743181 [Byte1]: 54
7894 11:49:52.747465
7895 11:49:52.747627 Set Vref, RX VrefLevel [Byte0]: 55
7896 11:49:52.750643 [Byte1]: 55
7897 11:49:52.755203
7898 11:49:52.755283 Set Vref, RX VrefLevel [Byte0]: 56
7899 11:49:52.761586 [Byte1]: 56
7900 11:49:52.761680
7901 11:49:52.764786 Set Vref, RX VrefLevel [Byte0]: 57
7902 11:49:52.767909 [Byte1]: 57
7903 11:49:52.767990
7904 11:49:52.771805 Set Vref, RX VrefLevel [Byte0]: 58
7905 11:49:52.774992 [Byte1]: 58
7906 11:49:52.775074
7907 11:49:52.778170 Set Vref, RX VrefLevel [Byte0]: 59
7908 11:49:52.781331 [Byte1]: 59
7909 11:49:52.785259
7910 11:49:52.785358 Set Vref, RX VrefLevel [Byte0]: 60
7911 11:49:52.788484 [Byte1]: 60
7912 11:49:52.793061
7913 11:49:52.793165 Set Vref, RX VrefLevel [Byte0]: 61
7914 11:49:52.796381 [Byte1]: 61
7915 11:49:52.800181
7916 11:49:52.800290 Set Vref, RX VrefLevel [Byte0]: 62
7917 11:49:52.803423 [Byte1]: 62
7918 11:49:52.807975
7919 11:49:52.808077 Set Vref, RX VrefLevel [Byte0]: 63
7920 11:49:52.811224 [Byte1]: 63
7921 11:49:52.815094
7922 11:49:52.815189 Set Vref, RX VrefLevel [Byte0]: 64
7923 11:49:52.818772 [Byte1]: 64
7924 11:49:52.822602
7925 11:49:52.822673 Set Vref, RX VrefLevel [Byte0]: 65
7926 11:49:52.826324 [Byte1]: 65
7927 11:49:52.830252
7928 11:49:52.830329 Set Vref, RX VrefLevel [Byte0]: 66
7929 11:49:52.833504 [Byte1]: 66
7930 11:49:52.837599
7931 11:49:52.837711 Set Vref, RX VrefLevel [Byte0]: 67
7932 11:49:52.840949 [Byte1]: 67
7933 11:49:52.845536
7934 11:49:52.845653 Set Vref, RX VrefLevel [Byte0]: 68
7935 11:49:52.849004 [Byte1]: 68
7936 11:49:52.852918
7937 11:49:52.853019 Set Vref, RX VrefLevel [Byte0]: 69
7938 11:49:52.856354 [Byte1]: 69
7939 11:49:52.860801
7940 11:49:52.860898 Set Vref, RX VrefLevel [Byte0]: 70
7941 11:49:52.863678 [Byte1]: 70
7942 11:49:52.867819
7943 11:49:52.867919 Set Vref, RX VrefLevel [Byte0]: 71
7944 11:49:52.871403 [Byte1]: 71
7945 11:49:52.875634
7946 11:49:52.875714 Set Vref, RX VrefLevel [Byte0]: 72
7947 11:49:52.878831 [Byte1]: 72
7948 11:49:52.883390
7949 11:49:52.883471 Set Vref, RX VrefLevel [Byte0]: 73
7950 11:49:52.886556 [Byte1]: 73
7951 11:49:52.890441
7952 11:49:52.890547 Set Vref, RX VrefLevel [Byte0]: 74
7953 11:49:52.894228 [Byte1]: 74
7954 11:49:52.898136
7955 11:49:52.898212 Final RX Vref Byte 0 = 59 to rank0
7956 11:49:52.901344 Final RX Vref Byte 1 = 62 to rank0
7957 11:49:52.904627 Final RX Vref Byte 0 = 59 to rank1
7958 11:49:52.908454 Final RX Vref Byte 1 = 62 to rank1==
7959 11:49:52.911765 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 11:49:52.918131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 11:49:52.918232 ==
7962 11:49:52.918330 DQS Delay:
7963 11:49:52.918418 DQS0 = 0, DQS1 = 0
7964 11:49:52.921355 DQM Delay:
7965 11:49:52.921452 DQM0 = 134, DQM1 = 127
7966 11:49:52.925144 DQ Delay:
7967 11:49:52.928381 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7968 11:49:52.931652 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7969 11:49:52.934666 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7970 11:49:52.938460 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7971 11:49:52.938551
7972 11:49:52.938614
7973 11:49:52.938673
7974 11:49:52.941610 [DramC_TX_OE_Calibration] TA2
7975 11:49:52.945128 Original DQ_B0 (3 6) =30, OEN = 27
7976 11:49:52.948350 Original DQ_B1 (3 6) =30, OEN = 27
7977 11:49:52.951426 24, 0x0, End_B0=24 End_B1=24
7978 11:49:52.951502 25, 0x0, End_B0=25 End_B1=25
7979 11:49:52.955030 26, 0x0, End_B0=26 End_B1=26
7980 11:49:52.958023 27, 0x0, End_B0=27 End_B1=27
7981 11:49:52.961473 28, 0x0, End_B0=28 End_B1=28
7982 11:49:52.961615 29, 0x0, End_B0=29 End_B1=29
7983 11:49:52.964828 30, 0x0, End_B0=30 End_B1=30
7984 11:49:52.968173 31, 0x4141, End_B0=30 End_B1=30
7985 11:49:52.971193 Byte0 end_step=30 best_step=27
7986 11:49:52.974385 Byte1 end_step=30 best_step=27
7987 11:49:52.977913 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 11:49:52.981119 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 11:49:52.981212
7990 11:49:52.981303
7991 11:49:52.987672 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7992 11:49:52.991523 CH0 RK0: MR19=303, MR18=2723
7993 11:49:52.997952 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
7994 11:49:52.998060
7995 11:49:53.000970 ----->DramcWriteLeveling(PI) begin...
7996 11:49:53.001087 ==
7997 11:49:53.004293 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 11:49:53.008203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 11:49:53.008303 ==
8000 11:49:53.011365 Write leveling (Byte 0): 36 => 36
8001 11:49:53.014606 Write leveling (Byte 1): 25 => 25
8002 11:49:53.017781 DramcWriteLeveling(PI) end<-----
8003 11:49:53.017848
8004 11:49:53.017908 ==
8005 11:49:53.021254 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 11:49:53.024952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 11:49:53.025041 ==
8008 11:49:53.028174 [Gating] SW mode calibration
8009 11:49:53.034322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 11:49:53.041269 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 11:49:53.044388 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8012 11:49:53.047616 1 4 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8013 11:49:53.054126 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 11:49:53.057977 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
8015 11:49:53.061312 1 4 16 | B1->B0 | 2a2a 3939 | 1 1 | (1 1) (0 0)
8016 11:49:53.067502 1 4 20 | B1->B0 | 3434 3d3c | 1 1 | (1 1) (1 1)
8017 11:49:53.071349 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
8018 11:49:53.074452 1 4 28 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
8019 11:49:53.081130 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8020 11:49:53.084352 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8021 11:49:53.087510 1 5 8 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8022 11:49:53.094379 1 5 12 | B1->B0 | 3434 3737 | 1 1 | (1 0) (1 0)
8023 11:49:53.097792 1 5 16 | B1->B0 | 2c2c 3231 | 0 1 | (0 1) (1 0)
8024 11:49:53.100734 1 5 20 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8025 11:49:53.107349 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
8026 11:49:53.110818 1 5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8027 11:49:53.114154 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8028 11:49:53.121115 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8029 11:49:53.124133 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8030 11:49:53.127626 1 6 12 | B1->B0 | 2828 3a3a | 1 1 | (0 0) (0 0)
8031 11:49:53.134020 1 6 16 | B1->B0 | 3e3e 4645 | 0 1 | (0 0) (0 0)
8032 11:49:53.137257 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8033 11:49:53.140452 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8034 11:49:53.147433 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 11:49:53.150335 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 11:49:53.154223 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 11:49:53.160270 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 11:49:53.163626 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8039 11:49:53.167343 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8040 11:49:53.173773 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:49:53.177013 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:49:53.180166 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:49:53.183845 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:49:53.190710 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:49:53.193727 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:49:53.196858 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:49:53.203921 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:49:53.207192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:49:53.210265 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:49:53.216723 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:49:53.219972 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:49:53.223253 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:49:53.229930 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8054 11:49:53.233442 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8055 11:49:53.236611 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8056 11:49:53.243342 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 11:49:53.246868 Total UI for P1: 0, mck2ui 16
8058 11:49:53.250044 best dqsien dly found for B0: ( 1, 9, 12)
8059 11:49:53.250117 Total UI for P1: 0, mck2ui 16
8060 11:49:53.256931 best dqsien dly found for B1: ( 1, 9, 12)
8061 11:49:53.259898 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8062 11:49:53.263186 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8063 11:49:53.263289
8064 11:49:53.267099 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8065 11:49:53.270296 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8066 11:49:53.273340 [Gating] SW calibration Done
8067 11:49:53.273409 ==
8068 11:49:53.277134 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 11:49:53.280446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 11:49:53.280524 ==
8071 11:49:53.283481 RX Vref Scan: 0
8072 11:49:53.283552
8073 11:49:53.283611 RX Vref 0 -> 0, step: 1
8074 11:49:53.283669
8075 11:49:53.286803 RX Delay 0 -> 252, step: 8
8076 11:49:53.290326 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8077 11:49:53.296511 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8078 11:49:53.300033 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8079 11:49:53.303200 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8080 11:49:53.307208 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8081 11:49:53.309758 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8082 11:49:53.316717 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8083 11:49:53.319945 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8084 11:49:53.323166 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8085 11:49:53.326606 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8086 11:49:53.329697 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8087 11:49:53.336965 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8088 11:49:53.339635 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8089 11:49:53.343318 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8090 11:49:53.346417 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8091 11:49:53.349623 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8092 11:49:53.353205 ==
8093 11:49:53.356622 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 11:49:53.360082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 11:49:53.360193 ==
8096 11:49:53.360284 DQS Delay:
8097 11:49:53.362958 DQS0 = 0, DQS1 = 0
8098 11:49:53.363055 DQM Delay:
8099 11:49:53.366580 DQM0 = 137, DQM1 = 129
8100 11:49:53.366657 DQ Delay:
8101 11:49:53.369856 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8102 11:49:53.373114 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8103 11:49:53.376390 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8104 11:49:53.379484 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8105 11:49:53.379560
8106 11:49:53.379633
8107 11:49:53.379699 ==
8108 11:49:53.382762 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:49:53.390010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:49:53.390087 ==
8111 11:49:53.390169
8112 11:49:53.390230
8113 11:49:53.390287 TX Vref Scan disable
8114 11:49:53.393430 == TX Byte 0 ==
8115 11:49:53.396448 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8116 11:49:53.403427 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8117 11:49:53.403511 == TX Byte 1 ==
8118 11:49:53.406418 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8119 11:49:53.413028 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8120 11:49:53.413109 ==
8121 11:49:53.416870 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 11:49:53.420148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 11:49:53.420229 ==
8124 11:49:53.435047
8125 11:49:53.438296 TX Vref early break, caculate TX vref
8126 11:49:53.441477 TX Vref=16, minBit 1, minWin=23, winSum=383
8127 11:49:53.444703 TX Vref=18, minBit 3, minWin=23, winSum=394
8128 11:49:53.448064 TX Vref=20, minBit 3, minWin=24, winSum=406
8129 11:49:53.451201 TX Vref=22, minBit 0, minWin=25, winSum=411
8130 11:49:53.454974 TX Vref=24, minBit 1, minWin=25, winSum=419
8131 11:49:53.461353 TX Vref=26, minBit 3, minWin=25, winSum=426
8132 11:49:53.464539 TX Vref=28, minBit 0, minWin=25, winSum=424
8133 11:49:53.468121 TX Vref=30, minBit 0, minWin=25, winSum=415
8134 11:49:53.471077 TX Vref=32, minBit 4, minWin=24, winSum=411
8135 11:49:53.474826 TX Vref=34, minBit 0, minWin=24, winSum=407
8136 11:49:53.478042 TX Vref=36, minBit 0, minWin=24, winSum=393
8137 11:49:53.484904 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 26
8138 11:49:53.484979
8139 11:49:53.488157 Final TX Range 0 Vref 26
8140 11:49:53.488229
8141 11:49:53.488289 ==
8142 11:49:53.491371 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 11:49:53.494377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 11:49:53.494474 ==
8145 11:49:53.494562
8146 11:49:53.494654
8147 11:49:53.497966 TX Vref Scan disable
8148 11:49:53.504702 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8149 11:49:53.504812 == TX Byte 0 ==
8150 11:49:53.507848 u2DelayCellOfst[0]=10 cells (3 PI)
8151 11:49:53.510863 u2DelayCellOfst[1]=13 cells (4 PI)
8152 11:49:53.514714 u2DelayCellOfst[2]=10 cells (3 PI)
8153 11:49:53.517834 u2DelayCellOfst[3]=10 cells (3 PI)
8154 11:49:53.520840 u2DelayCellOfst[4]=6 cells (2 PI)
8155 11:49:53.524724 u2DelayCellOfst[5]=0 cells (0 PI)
8156 11:49:53.527705 u2DelayCellOfst[6]=13 cells (4 PI)
8157 11:49:53.531072 u2DelayCellOfst[7]=13 cells (4 PI)
8158 11:49:53.534128 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8159 11:49:53.537961 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8160 11:49:53.541245 == TX Byte 1 ==
8161 11:49:53.544592 u2DelayCellOfst[8]=3 cells (1 PI)
8162 11:49:53.547895 u2DelayCellOfst[9]=0 cells (0 PI)
8163 11:49:53.547977 u2DelayCellOfst[10]=6 cells (2 PI)
8164 11:49:53.551168 u2DelayCellOfst[11]=3 cells (1 PI)
8165 11:49:53.554359 u2DelayCellOfst[12]=10 cells (3 PI)
8166 11:49:53.557987 u2DelayCellOfst[13]=10 cells (3 PI)
8167 11:49:53.561235 u2DelayCellOfst[14]=17 cells (5 PI)
8168 11:49:53.564549 u2DelayCellOfst[15]=10 cells (3 PI)
8169 11:49:53.567740 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8170 11:49:53.574216 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8171 11:49:53.574319 DramC Write-DBI on
8172 11:49:53.574409 ==
8173 11:49:53.577896 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 11:49:53.584383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 11:49:53.584460 ==
8176 11:49:53.584525
8177 11:49:53.584612
8178 11:49:53.584696 TX Vref Scan disable
8179 11:49:53.588301 == TX Byte 0 ==
8180 11:49:53.591459 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8181 11:49:53.594681 == TX Byte 1 ==
8182 11:49:53.598629 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8183 11:49:53.601535 DramC Write-DBI off
8184 11:49:53.601666
8185 11:49:53.601765 [DATLAT]
8186 11:49:53.601830 Freq=1600, CH0 RK1
8187 11:49:53.601889
8188 11:49:53.604611 DATLAT Default: 0xf
8189 11:49:53.608120 0, 0xFFFF, sum = 0
8190 11:49:53.608197 1, 0xFFFF, sum = 0
8191 11:49:53.611448 2, 0xFFFF, sum = 0
8192 11:49:53.611556 3, 0xFFFF, sum = 0
8193 11:49:53.614532 4, 0xFFFF, sum = 0
8194 11:49:53.614632 5, 0xFFFF, sum = 0
8195 11:49:53.618279 6, 0xFFFF, sum = 0
8196 11:49:53.618382 7, 0xFFFF, sum = 0
8197 11:49:53.621534 8, 0xFFFF, sum = 0
8198 11:49:53.621670 9, 0xFFFF, sum = 0
8199 11:49:53.624650 10, 0xFFFF, sum = 0
8200 11:49:53.624720 11, 0xFFFF, sum = 0
8201 11:49:53.628268 12, 0xFFFF, sum = 0
8202 11:49:53.628350 13, 0xFFFF, sum = 0
8203 11:49:53.631232 14, 0x0, sum = 1
8204 11:49:53.631314 15, 0x0, sum = 2
8205 11:49:53.634405 16, 0x0, sum = 3
8206 11:49:53.634486 17, 0x0, sum = 4
8207 11:49:53.637837 best_step = 15
8208 11:49:53.637950
8209 11:49:53.638042 ==
8210 11:49:53.641514 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 11:49:53.644577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 11:49:53.644687 ==
8213 11:49:53.647893 RX Vref Scan: 0
8214 11:49:53.647990
8215 11:49:53.648078 RX Vref 0 -> 0, step: 1
8216 11:49:53.648173
8217 11:49:53.651143 RX Delay 19 -> 252, step: 4
8218 11:49:53.658240 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8219 11:49:53.661351 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8220 11:49:53.664707 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8221 11:49:53.667990 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8222 11:49:53.671216 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8223 11:49:53.674480 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8224 11:49:53.681009 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8225 11:49:53.684240 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8226 11:49:53.688212 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8227 11:49:53.691224 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8228 11:49:53.694120 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8229 11:49:53.701014 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8230 11:49:53.704261 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8231 11:49:53.707519 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8232 11:49:53.710642 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8233 11:49:53.717779 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8234 11:49:53.717878 ==
8235 11:49:53.720909 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 11:49:53.724529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 11:49:53.724630 ==
8238 11:49:53.724720 DQS Delay:
8239 11:49:53.727615 DQS0 = 0, DQS1 = 0
8240 11:49:53.727711 DQM Delay:
8241 11:49:53.730843 DQM0 = 134, DQM1 = 127
8242 11:49:53.730939 DQ Delay:
8243 11:49:53.734529 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8244 11:49:53.737496 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8245 11:49:53.740860 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8246 11:49:53.744118 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8247 11:49:53.744190
8248 11:49:53.744262
8249 11:49:53.744322
8250 11:49:53.747346 [DramC_TX_OE_Calibration] TA2
8251 11:49:53.750776 Original DQ_B0 (3 6) =30, OEN = 27
8252 11:49:53.754536 Original DQ_B1 (3 6) =30, OEN = 27
8253 11:49:53.757566 24, 0x0, End_B0=24 End_B1=24
8254 11:49:53.760830 25, 0x0, End_B0=25 End_B1=25
8255 11:49:53.760903 26, 0x0, End_B0=26 End_B1=26
8256 11:49:53.764103 27, 0x0, End_B0=27 End_B1=27
8257 11:49:53.767427 28, 0x0, End_B0=28 End_B1=28
8258 11:49:53.770786 29, 0x0, End_B0=29 End_B1=29
8259 11:49:53.774003 30, 0x0, End_B0=30 End_B1=30
8260 11:49:53.774085 31, 0x4141, End_B0=30 End_B1=30
8261 11:49:53.777191 Byte0 end_step=30 best_step=27
8262 11:49:53.780972 Byte1 end_step=30 best_step=27
8263 11:49:53.784277 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 11:49:53.787618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 11:49:53.787700
8266 11:49:53.787763
8267 11:49:53.794144 [DQSOSCAuto] RK1, (LSB)MR18= 0x230b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8268 11:49:53.797337 CH0 RK1: MR19=303, MR18=230B
8269 11:49:53.804021 CH0_RK1: MR19=0x303, MR18=0x230B, DQSOSC=392, MR23=63, INC=24, DEC=16
8270 11:49:53.807399 [RxdqsGatingPostProcess] freq 1600
8271 11:49:53.814063 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 11:49:53.814141 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 11:49:53.817324 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 11:49:53.820572 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 11:49:53.823759 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 11:49:53.826809 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 11:49:53.830310 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 11:49:53.833602 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 11:49:53.836792 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 11:49:53.840755 Pre-setting of DQS Precalculation
8281 11:49:53.844011 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 11:49:53.844108 ==
8283 11:49:53.847177 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 11:49:53.853458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 11:49:53.853555 ==
8286 11:49:53.857339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 11:49:53.863645 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 11:49:53.867216 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 11:49:53.873714 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 11:49:53.881521 [CA 0] Center 42 (12~72) winsize 61
8291 11:49:53.884392 [CA 1] Center 42 (12~72) winsize 61
8292 11:49:53.888317 [CA 2] Center 38 (9~68) winsize 60
8293 11:49:53.891166 [CA 3] Center 38 (9~67) winsize 59
8294 11:49:53.894539 [CA 4] Center 37 (8~67) winsize 60
8295 11:49:53.898333 [CA 5] Center 37 (8~67) winsize 60
8296 11:49:53.898440
8297 11:49:53.901713 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 11:49:53.901810
8299 11:49:53.904946 [CATrainingPosCal] consider 1 rank data
8300 11:49:53.908324 u2DelayCellTimex100 = 285/100 ps
8301 11:49:53.911461 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8302 11:49:53.918002 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8303 11:49:53.921466 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8304 11:49:53.924506 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8305 11:49:53.928328 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8306 11:49:53.931399 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8307 11:49:53.931495
8308 11:49:53.934660 CA PerBit enable=1, Macro0, CA PI delay=37
8309 11:49:53.934739
8310 11:49:53.938180 [CBTSetCACLKResult] CA Dly = 37
8311 11:49:53.941362 CS Dly: 10 (0~41)
8312 11:49:53.944572 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 11:49:53.947750 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 11:49:53.947857 ==
8315 11:49:53.950988 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 11:49:53.954224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 11:49:53.957407 ==
8318 11:49:53.961273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 11:49:53.964478 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 11:49:53.971360 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 11:49:53.974448 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 11:49:53.984581 [CA 0] Center 42 (12~72) winsize 61
8323 11:49:53.987771 [CA 1] Center 42 (12~72) winsize 61
8324 11:49:53.990977 [CA 2] Center 38 (9~68) winsize 60
8325 11:49:53.994581 [CA 3] Center 38 (8~68) winsize 61
8326 11:49:53.998145 [CA 4] Center 38 (8~68) winsize 61
8327 11:49:54.000941 [CA 5] Center 37 (8~67) winsize 60
8328 11:49:54.001046
8329 11:49:54.004565 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 11:49:54.004662
8331 11:49:54.007502 [CATrainingPosCal] consider 2 rank data
8332 11:49:54.011302 u2DelayCellTimex100 = 285/100 ps
8333 11:49:54.014554 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8334 11:49:54.020965 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8335 11:49:54.024132 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8336 11:49:54.028142 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8337 11:49:54.031137 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8338 11:49:54.034616 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8339 11:49:54.034708
8340 11:49:54.037985 CA PerBit enable=1, Macro0, CA PI delay=37
8341 11:49:54.038054
8342 11:49:54.041121 [CBTSetCACLKResult] CA Dly = 37
8343 11:49:54.044584 CS Dly: 12 (0~45)
8344 11:49:54.047475 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 11:49:54.051433 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 11:49:54.051530
8347 11:49:54.054538 ----->DramcWriteLeveling(PI) begin...
8348 11:49:54.054608 ==
8349 11:49:54.057666 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 11:49:54.060841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 11:49:54.064105 ==
8352 11:49:54.064208 Write leveling (Byte 0): 26 => 26
8353 11:49:54.067960 Write leveling (Byte 1): 28 => 28
8354 11:49:54.071240 DramcWriteLeveling(PI) end<-----
8355 11:49:54.071348
8356 11:49:54.071439 ==
8357 11:49:54.074351 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 11:49:54.080896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 11:49:54.080998 ==
8360 11:49:54.084138 [Gating] SW mode calibration
8361 11:49:54.090572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 11:49:54.093906 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 11:49:54.100539 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 11:49:54.104278 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 11:49:54.107288 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8366 11:49:54.114125 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8367 11:49:54.117750 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 11:49:54.120707 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 11:49:54.123961 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 11:49:54.131088 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 11:49:54.134381 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 11:49:54.137201 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 11:49:54.144128 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8374 11:49:54.147259 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
8375 11:49:54.150428 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:49:54.157506 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 11:49:54.160470 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 11:49:54.164025 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:49:54.171024 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:49:54.174157 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 11:49:54.177390 1 6 8 | B1->B0 | 2828 3c3c | 0 1 | (0 0) (0 0)
8382 11:49:54.184346 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8383 11:49:54.187230 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:49:54.190653 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 11:49:54.197509 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 11:49:54.200907 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 11:49:54.204153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:49:54.210413 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:49:54.214239 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8390 11:49:54.217443 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 11:49:54.223866 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 11:49:54.227574 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:49:54.230498 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:49:54.234134 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:49:54.240659 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:49:54.243866 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:49:54.250518 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:49:54.253597 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:49:54.257067 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:49:54.260220 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:49:54.266786 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:49:54.270396 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:49:54.273222 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:49:54.280340 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:49:54.283575 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 11:49:54.286665 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8407 11:49:54.293226 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8408 11:49:54.296893 Total UI for P1: 0, mck2ui 16
8409 11:49:54.300026 best dqsien dly found for B0: ( 1, 9, 10)
8410 11:49:54.303404 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:49:54.306921 Total UI for P1: 0, mck2ui 16
8412 11:49:54.310304 best dqsien dly found for B1: ( 1, 9, 12)
8413 11:49:54.313365 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8414 11:49:54.316941 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8415 11:49:54.317013
8416 11:49:54.320271 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8417 11:49:54.323484 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8418 11:49:54.326687 [Gating] SW calibration Done
8419 11:49:54.326757 ==
8420 11:49:54.330081 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 11:49:54.336629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 11:49:54.336728 ==
8423 11:49:54.336817 RX Vref Scan: 0
8424 11:49:54.336904
8425 11:49:54.340386 RX Vref 0 -> 0, step: 1
8426 11:49:54.340460
8427 11:49:54.343743 RX Delay 0 -> 252, step: 8
8428 11:49:54.346602 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8429 11:49:54.350263 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8430 11:49:54.353594 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8431 11:49:54.357077 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8432 11:49:54.363820 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8433 11:49:54.366959 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8434 11:49:54.370133 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8435 11:49:54.373379 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8436 11:49:54.376626 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8437 11:49:54.379821 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8438 11:49:54.386878 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8439 11:49:54.389896 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8440 11:49:54.392995 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8441 11:49:54.396393 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8442 11:49:54.403476 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8443 11:49:54.406630 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8444 11:49:54.406704 ==
8445 11:49:54.409921 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 11:49:54.413364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 11:49:54.413460 ==
8448 11:49:54.413549 DQS Delay:
8449 11:49:54.416685 DQS0 = 0, DQS1 = 0
8450 11:49:54.416756 DQM Delay:
8451 11:49:54.419938 DQM0 = 136, DQM1 = 132
8452 11:49:54.420008 DQ Delay:
8453 11:49:54.423415 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8454 11:49:54.426325 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8455 11:49:54.430223 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8456 11:49:54.433351 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8457 11:49:54.436557
8458 11:49:54.436627
8459 11:49:54.436686 ==
8460 11:49:54.439684 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 11:49:54.442936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 11:49:54.443037 ==
8463 11:49:54.443136
8464 11:49:54.443221
8465 11:49:54.446960 TX Vref Scan disable
8466 11:49:54.447065 == TX Byte 0 ==
8467 11:49:54.452957 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8468 11:49:54.456323 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 11:49:54.456397 == TX Byte 1 ==
8470 11:49:54.462880 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8471 11:49:54.466335 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 11:49:54.466433 ==
8473 11:49:54.469840 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 11:49:54.472737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 11:49:54.472834 ==
8476 11:49:54.486674
8477 11:49:54.489777 TX Vref early break, caculate TX vref
8478 11:49:54.492790 TX Vref=16, minBit 0, minWin=22, winSum=375
8479 11:49:54.496387 TX Vref=18, minBit 1, minWin=23, winSum=384
8480 11:49:54.500144 TX Vref=20, minBit 0, minWin=24, winSum=393
8481 11:49:54.502796 TX Vref=22, minBit 0, minWin=25, winSum=409
8482 11:49:54.506553 TX Vref=24, minBit 0, minWin=25, winSum=416
8483 11:49:54.513197 TX Vref=26, minBit 0, minWin=25, winSum=424
8484 11:49:54.516296 TX Vref=28, minBit 1, minWin=25, winSum=430
8485 11:49:54.519509 TX Vref=30, minBit 0, minWin=24, winSum=415
8486 11:49:54.522749 TX Vref=32, minBit 0, minWin=24, winSum=411
8487 11:49:54.526507 TX Vref=34, minBit 0, minWin=24, winSum=404
8488 11:49:54.533229 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 28
8489 11:49:54.533331
8490 11:49:54.536591 Final TX Range 0 Vref 28
8491 11:49:54.536692
8492 11:49:54.536784 ==
8493 11:49:54.539513 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 11:49:54.542893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 11:49:54.543001 ==
8496 11:49:54.543121
8497 11:49:54.543207
8498 11:49:54.546086 TX Vref Scan disable
8499 11:49:54.552659 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8500 11:49:54.552759 == TX Byte 0 ==
8501 11:49:54.556059 u2DelayCellOfst[0]=17 cells (5 PI)
8502 11:49:54.559719 u2DelayCellOfst[1]=10 cells (3 PI)
8503 11:49:54.562871 u2DelayCellOfst[2]=0 cells (0 PI)
8504 11:49:54.565999 u2DelayCellOfst[3]=6 cells (2 PI)
8505 11:49:54.569764 u2DelayCellOfst[4]=10 cells (3 PI)
8506 11:49:54.572660 u2DelayCellOfst[5]=17 cells (5 PI)
8507 11:49:54.576262 u2DelayCellOfst[6]=17 cells (5 PI)
8508 11:49:54.576363 u2DelayCellOfst[7]=3 cells (1 PI)
8509 11:49:54.582951 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8510 11:49:54.586299 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8511 11:49:54.586373 == TX Byte 1 ==
8512 11:49:54.589283 u2DelayCellOfst[8]=0 cells (0 PI)
8513 11:49:54.592590 u2DelayCellOfst[9]=3 cells (1 PI)
8514 11:49:54.596429 u2DelayCellOfst[10]=10 cells (3 PI)
8515 11:49:54.599782 u2DelayCellOfst[11]=6 cells (2 PI)
8516 11:49:54.602714 u2DelayCellOfst[12]=17 cells (5 PI)
8517 11:49:54.606294 u2DelayCellOfst[13]=17 cells (5 PI)
8518 11:49:54.609470 u2DelayCellOfst[14]=17 cells (5 PI)
8519 11:49:54.613467 u2DelayCellOfst[15]=17 cells (5 PI)
8520 11:49:54.616159 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8521 11:49:54.619336 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 11:49:54.623167 DramC Write-DBI on
8523 11:49:54.623234 ==
8524 11:49:54.626426 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 11:49:54.629622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 11:49:54.629690 ==
8527 11:49:54.629749
8528 11:49:54.632877
8529 11:49:54.632970 TX Vref Scan disable
8530 11:49:54.636147 == TX Byte 0 ==
8531 11:49:54.639244 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8532 11:49:54.642384 == TX Byte 1 ==
8533 11:49:54.645839 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8534 11:49:54.645942 DramC Write-DBI off
8535 11:49:54.646017
8536 11:49:54.649663 [DATLAT]
8537 11:49:54.649749 Freq=1600, CH1 RK0
8538 11:49:54.649810
8539 11:49:54.652611 DATLAT Default: 0xf
8540 11:49:54.652694 0, 0xFFFF, sum = 0
8541 11:49:54.655975 1, 0xFFFF, sum = 0
8542 11:49:54.656073 2, 0xFFFF, sum = 0
8543 11:49:54.659371 3, 0xFFFF, sum = 0
8544 11:49:54.659482 4, 0xFFFF, sum = 0
8545 11:49:54.662514 5, 0xFFFF, sum = 0
8546 11:49:54.665683 6, 0xFFFF, sum = 0
8547 11:49:54.665759 7, 0xFFFF, sum = 0
8548 11:49:54.668911 8, 0xFFFF, sum = 0
8549 11:49:54.669009 9, 0xFFFF, sum = 0
8550 11:49:54.672163 10, 0xFFFF, sum = 0
8551 11:49:54.672261 11, 0xFFFF, sum = 0
8552 11:49:54.676054 12, 0xFFFF, sum = 0
8553 11:49:54.676157 13, 0xFFFF, sum = 0
8554 11:49:54.679260 14, 0x0, sum = 1
8555 11:49:54.679365 15, 0x0, sum = 2
8556 11:49:54.682225 16, 0x0, sum = 3
8557 11:49:54.682295 17, 0x0, sum = 4
8558 11:49:54.685701 best_step = 15
8559 11:49:54.685774
8560 11:49:54.685836 ==
8561 11:49:54.688785 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 11:49:54.692415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 11:49:54.692512 ==
8564 11:49:54.692606 RX Vref Scan: 1
8565 11:49:54.695420
8566 11:49:54.695493 Set Vref Range= 24 -> 127
8567 11:49:54.695555
8568 11:49:54.699110 RX Vref 24 -> 127, step: 1
8569 11:49:54.699179
8570 11:49:54.702101 RX Delay 27 -> 252, step: 4
8571 11:49:54.702175
8572 11:49:54.705729 Set Vref, RX VrefLevel [Byte0]: 24
8573 11:49:54.708886 [Byte1]: 24
8574 11:49:54.708983
8575 11:49:54.711920 Set Vref, RX VrefLevel [Byte0]: 25
8576 11:49:54.715658 [Byte1]: 25
8577 11:49:54.715757
8578 11:49:54.718746 Set Vref, RX VrefLevel [Byte0]: 26
8579 11:49:54.721956 [Byte1]: 26
8580 11:49:54.725825
8581 11:49:54.725909 Set Vref, RX VrefLevel [Byte0]: 27
8582 11:49:54.728916 [Byte1]: 27
8583 11:49:54.733396
8584 11:49:54.733491 Set Vref, RX VrefLevel [Byte0]: 28
8585 11:49:54.736507 [Byte1]: 28
8586 11:49:54.741179
8587 11:49:54.741276 Set Vref, RX VrefLevel [Byte0]: 29
8588 11:49:54.744302 [Byte1]: 29
8589 11:49:54.748203
8590 11:49:54.748301 Set Vref, RX VrefLevel [Byte0]: 30
8591 11:49:54.751821 [Byte1]: 30
8592 11:49:54.756052
8593 11:49:54.756133 Set Vref, RX VrefLevel [Byte0]: 31
8594 11:49:54.759737 [Byte1]: 31
8595 11:49:54.763660
8596 11:49:54.763740 Set Vref, RX VrefLevel [Byte0]: 32
8597 11:49:54.766837 [Byte1]: 32
8598 11:49:54.771373
8599 11:49:54.771453 Set Vref, RX VrefLevel [Byte0]: 33
8600 11:49:54.774687 [Byte1]: 33
8601 11:49:54.778626
8602 11:49:54.778706 Set Vref, RX VrefLevel [Byte0]: 34
8603 11:49:54.781893 [Byte1]: 34
8604 11:49:54.786466
8605 11:49:54.786546 Set Vref, RX VrefLevel [Byte0]: 35
8606 11:49:54.789601 [Byte1]: 35
8607 11:49:54.793788
8608 11:49:54.793868 Set Vref, RX VrefLevel [Byte0]: 36
8609 11:49:54.796841 [Byte1]: 36
8610 11:49:54.801385
8611 11:49:54.804045 Set Vref, RX VrefLevel [Byte0]: 37
8612 11:49:54.807563 [Byte1]: 37
8613 11:49:54.807643
8614 11:49:54.811242 Set Vref, RX VrefLevel [Byte0]: 38
8615 11:49:54.814550 [Byte1]: 38
8616 11:49:54.814623
8617 11:49:54.817502 Set Vref, RX VrefLevel [Byte0]: 39
8618 11:49:54.821185 [Byte1]: 39
8619 11:49:54.821257
8620 11:49:54.824115 Set Vref, RX VrefLevel [Byte0]: 40
8621 11:49:54.827254 [Byte1]: 40
8622 11:49:54.831527
8623 11:49:54.831602 Set Vref, RX VrefLevel [Byte0]: 41
8624 11:49:54.834676 [Byte1]: 41
8625 11:49:54.839095
8626 11:49:54.839170 Set Vref, RX VrefLevel [Byte0]: 42
8627 11:49:54.842296 [Byte1]: 42
8628 11:49:54.846196
8629 11:49:54.846270 Set Vref, RX VrefLevel [Byte0]: 43
8630 11:49:54.849512 [Byte1]: 43
8631 11:49:54.853922
8632 11:49:54.854022 Set Vref, RX VrefLevel [Byte0]: 44
8633 11:49:54.857002 [Byte1]: 44
8634 11:49:54.861316
8635 11:49:54.861418 Set Vref, RX VrefLevel [Byte0]: 45
8636 11:49:54.864996 [Byte1]: 45
8637 11:49:54.868754
8638 11:49:54.868854 Set Vref, RX VrefLevel [Byte0]: 46
8639 11:49:54.872282 [Byte1]: 46
8640 11:49:54.876717
8641 11:49:54.876797 Set Vref, RX VrefLevel [Byte0]: 47
8642 11:49:54.879962 [Byte1]: 47
8643 11:49:54.883844
8644 11:49:54.883924 Set Vref, RX VrefLevel [Byte0]: 48
8645 11:49:54.887564 [Byte1]: 48
8646 11:49:54.891388
8647 11:49:54.891470 Set Vref, RX VrefLevel [Byte0]: 49
8648 11:49:54.894662 [Byte1]: 49
8649 11:49:54.899160
8650 11:49:54.899241 Set Vref, RX VrefLevel [Byte0]: 50
8651 11:49:54.902466 [Byte1]: 50
8652 11:49:54.906837
8653 11:49:54.906918 Set Vref, RX VrefLevel [Byte0]: 51
8654 11:49:54.909748 [Byte1]: 51
8655 11:49:54.914260
8656 11:49:54.914336 Set Vref, RX VrefLevel [Byte0]: 52
8657 11:49:54.917376 [Byte1]: 52
8658 11:49:54.921502
8659 11:49:54.921636 Set Vref, RX VrefLevel [Byte0]: 53
8660 11:49:54.925365 [Byte1]: 53
8661 11:49:54.929170
8662 11:49:54.929275 Set Vref, RX VrefLevel [Byte0]: 54
8663 11:49:54.932668 [Byte1]: 54
8664 11:49:54.936856
8665 11:49:54.936953 Set Vref, RX VrefLevel [Byte0]: 55
8666 11:49:54.940328 [Byte1]: 55
8667 11:49:54.944456
8668 11:49:54.944531 Set Vref, RX VrefLevel [Byte0]: 56
8669 11:49:54.947362 [Byte1]: 56
8670 11:49:54.952184
8671 11:49:54.952261 Set Vref, RX VrefLevel [Byte0]: 57
8672 11:49:54.955408 [Byte1]: 57
8673 11:49:54.959219
8674 11:49:54.959300 Set Vref, RX VrefLevel [Byte0]: 58
8675 11:49:54.962442 [Byte1]: 58
8676 11:49:54.966818
8677 11:49:54.966899 Set Vref, RX VrefLevel [Byte0]: 59
8678 11:49:54.969965 [Byte1]: 59
8679 11:49:54.974481
8680 11:49:54.974561 Set Vref, RX VrefLevel [Byte0]: 60
8681 11:49:54.977964 [Byte1]: 60
8682 11:49:54.982267
8683 11:49:54.982348 Set Vref, RX VrefLevel [Byte0]: 61
8684 11:49:54.985550 [Byte1]: 61
8685 11:49:54.989361
8686 11:49:54.989441 Set Vref, RX VrefLevel [Byte0]: 62
8687 11:49:54.993145 [Byte1]: 62
8688 11:49:54.997047
8689 11:49:54.997128 Set Vref, RX VrefLevel [Byte0]: 63
8690 11:49:55.000290 [Byte1]: 63
8691 11:49:55.004635
8692 11:49:55.004717 Set Vref, RX VrefLevel [Byte0]: 64
8693 11:49:55.008133 [Byte1]: 64
8694 11:49:55.012038
8695 11:49:55.012152 Set Vref, RX VrefLevel [Byte0]: 65
8696 11:49:55.015240 [Byte1]: 65
8697 11:49:55.019536
8698 11:49:55.019642 Set Vref, RX VrefLevel [Byte0]: 66
8699 11:49:55.023125 [Byte1]: 66
8700 11:49:55.027149
8701 11:49:55.027224 Set Vref, RX VrefLevel [Byte0]: 67
8702 11:49:55.030204 [Byte1]: 67
8703 11:49:55.034434
8704 11:49:55.034532 Set Vref, RX VrefLevel [Byte0]: 68
8705 11:49:55.038109 [Byte1]: 68
8706 11:49:55.042384
8707 11:49:55.042458 Set Vref, RX VrefLevel [Byte0]: 69
8708 11:49:55.045393 [Byte1]: 69
8709 11:49:55.049649
8710 11:49:55.049740 Set Vref, RX VrefLevel [Byte0]: 70
8711 11:49:55.052824 [Byte1]: 70
8712 11:49:55.057209
8713 11:49:55.057308 Set Vref, RX VrefLevel [Byte0]: 71
8714 11:49:55.060764 [Byte1]: 71
8715 11:49:55.065134
8716 11:49:55.065236 Set Vref, RX VrefLevel [Byte0]: 72
8717 11:49:55.068374 [Byte1]: 72
8718 11:49:55.072088
8719 11:49:55.072163 Set Vref, RX VrefLevel [Byte0]: 73
8720 11:49:55.075616 [Byte1]: 73
8721 11:49:55.079629
8722 11:49:55.079730 Set Vref, RX VrefLevel [Byte0]: 74
8723 11:49:55.083295 [Byte1]: 74
8724 11:49:55.087555
8725 11:49:55.087632 Set Vref, RX VrefLevel [Byte0]: 75
8726 11:49:55.090720 [Byte1]: 75
8727 11:49:55.095252
8728 11:49:55.095351 Set Vref, RX VrefLevel [Byte0]: 76
8729 11:49:55.098520 [Byte1]: 76
8730 11:49:55.102327
8731 11:49:55.102431 Final RX Vref Byte 0 = 61 to rank0
8732 11:49:55.106075 Final RX Vref Byte 1 = 58 to rank0
8733 11:49:55.109333 Final RX Vref Byte 0 = 61 to rank1
8734 11:49:55.112587 Final RX Vref Byte 1 = 58 to rank1==
8735 11:49:55.115764 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 11:49:55.122476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 11:49:55.122553 ==
8738 11:49:55.122616 DQS Delay:
8739 11:49:55.122682 DQS0 = 0, DQS1 = 0
8740 11:49:55.125602 DQM Delay:
8741 11:49:55.125708 DQM0 = 133, DQM1 = 131
8742 11:49:55.129296 DQ Delay:
8743 11:49:55.132602 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8744 11:49:55.135433 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8745 11:49:55.139134 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8746 11:49:55.142272 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8747 11:49:55.142347
8748 11:49:55.142412
8749 11:49:55.142471
8750 11:49:55.145430 [DramC_TX_OE_Calibration] TA2
8751 11:49:55.149262 Original DQ_B0 (3 6) =30, OEN = 27
8752 11:49:55.152229 Original DQ_B1 (3 6) =30, OEN = 27
8753 11:49:55.155793 24, 0x0, End_B0=24 End_B1=24
8754 11:49:55.155895 25, 0x0, End_B0=25 End_B1=25
8755 11:49:55.158746 26, 0x0, End_B0=26 End_B1=26
8756 11:49:55.162304 27, 0x0, End_B0=27 End_B1=27
8757 11:49:55.165738 28, 0x0, End_B0=28 End_B1=28
8758 11:49:55.165810 29, 0x0, End_B0=29 End_B1=29
8759 11:49:55.168793 30, 0x0, End_B0=30 End_B1=30
8760 11:49:55.172409 31, 0x4141, End_B0=30 End_B1=30
8761 11:49:55.175295 Byte0 end_step=30 best_step=27
8762 11:49:55.178830 Byte1 end_step=30 best_step=27
8763 11:49:55.181959 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 11:49:55.182037 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 11:49:55.185570
8766 11:49:55.185662
8767 11:49:55.192312 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8768 11:49:55.195350 CH1 RK0: MR19=303, MR18=1826
8769 11:49:55.202387 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8770 11:49:55.202489
8771 11:49:55.205701 ----->DramcWriteLeveling(PI) begin...
8772 11:49:55.205789 ==
8773 11:49:55.209061 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 11:49:55.212259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 11:49:55.212335 ==
8776 11:49:55.215507 Write leveling (Byte 0): 26 => 26
8777 11:49:55.218732 Write leveling (Byte 1): 28 => 28
8778 11:49:55.222069 DramcWriteLeveling(PI) end<-----
8779 11:49:55.222143
8780 11:49:55.222208 ==
8781 11:49:55.225858 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 11:49:55.229149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:49:55.229249 ==
8784 11:49:55.232299 [Gating] SW mode calibration
8785 11:49:55.238750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 11:49:55.245544 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 11:49:55.249233 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 11:49:55.252287 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:49:55.259245 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8790 11:49:55.262515 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8791 11:49:55.265512 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 11:49:55.272773 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 11:49:55.275990 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 11:49:55.279130 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 11:49:55.285865 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 11:49:55.289451 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8797 11:49:55.292386 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8798 11:49:55.295902 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 1)
8799 11:49:55.302473 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 11:49:55.305505 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 11:49:55.308795 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 11:49:55.315796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 11:49:55.319017 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 11:49:55.322277 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8805 11:49:55.328789 1 6 8 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
8806 11:49:55.332665 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 11:49:55.335876 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 11:49:55.342267 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 11:49:55.345429 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 11:49:55.349201 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 11:49:55.355742 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 11:49:55.358882 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:49:55.361906 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8814 11:49:55.368871 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8815 11:49:55.372070 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8816 11:49:55.375122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:49:55.382267 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:49:55.385759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:49:55.388727 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 11:49:55.395608 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:49:55.398625 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:49:55.402098 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 11:49:55.408576 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:49:55.412223 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:49:55.415220 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:49:55.419104 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:49:55.425770 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:49:55.428853 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 11:49:55.432131 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8830 11:49:55.438589 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8831 11:49:55.441842 Total UI for P1: 0, mck2ui 16
8832 11:49:55.445043 best dqsien dly found for B1: ( 1, 9, 8)
8833 11:49:55.448957 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 11:49:55.452180 Total UI for P1: 0, mck2ui 16
8835 11:49:55.455572 best dqsien dly found for B0: ( 1, 9, 12)
8836 11:49:55.458713 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8837 11:49:55.461873 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8838 11:49:55.461979
8839 11:49:55.465392 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8840 11:49:55.468590 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8841 11:49:55.472103 [Gating] SW calibration Done
8842 11:49:55.472202 ==
8843 11:49:55.475210 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 11:49:55.482106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 11:49:55.482205 ==
8846 11:49:55.482294 RX Vref Scan: 0
8847 11:49:55.482390
8848 11:49:55.485083 RX Vref 0 -> 0, step: 1
8849 11:49:55.485182
8850 11:49:55.488785 RX Delay 0 -> 252, step: 8
8851 11:49:55.491933 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8852 11:49:55.495111 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8853 11:49:55.498776 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8854 11:49:55.502112 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8855 11:49:55.508318 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8856 11:49:55.511444 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8857 11:49:55.514955 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8858 11:49:55.518566 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8859 11:49:55.521512 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8860 11:49:55.528554 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8861 11:49:55.531838 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8862 11:49:55.535160 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8863 11:49:55.538310 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8864 11:49:55.541542 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8865 11:49:55.548496 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8866 11:49:55.551873 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8867 11:49:55.551954 ==
8868 11:49:55.555113 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 11:49:55.558257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 11:49:55.558339 ==
8871 11:49:55.561697 DQS Delay:
8872 11:49:55.561778 DQS0 = 0, DQS1 = 0
8873 11:49:55.561841 DQM Delay:
8874 11:49:55.565020 DQM0 = 136, DQM1 = 133
8875 11:49:55.565100 DQ Delay:
8876 11:49:55.568174 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8877 11:49:55.571229 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8878 11:49:55.574803 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8879 11:49:55.581532 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8880 11:49:55.581649
8881 11:49:55.581713
8882 11:49:55.581772 ==
8883 11:49:55.585030 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 11:49:55.588160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 11:49:55.588251 ==
8886 11:49:55.588315
8887 11:49:55.588374
8888 11:49:55.591383 TX Vref Scan disable
8889 11:49:55.591463 == TX Byte 0 ==
8890 11:49:55.598213 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8891 11:49:55.601523 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8892 11:49:55.601660 == TX Byte 1 ==
8893 11:49:55.608323 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8894 11:49:55.611484 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8895 11:49:55.611565 ==
8896 11:49:55.614520 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 11:49:55.618170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 11:49:55.618277 ==
8899 11:49:55.631865
8900 11:49:55.634853 TX Vref early break, caculate TX vref
8901 11:49:55.638020 TX Vref=16, minBit 1, minWin=23, winSum=381
8902 11:49:55.641999 TX Vref=18, minBit 6, minWin=23, winSum=390
8903 11:49:55.644688 TX Vref=20, minBit 6, minWin=23, winSum=398
8904 11:49:55.648439 TX Vref=22, minBit 0, minWin=25, winSum=409
8905 11:49:55.651614 TX Vref=24, minBit 0, minWin=25, winSum=419
8906 11:49:55.658247 TX Vref=26, minBit 0, minWin=25, winSum=425
8907 11:49:55.661401 TX Vref=28, minBit 0, minWin=25, winSum=426
8908 11:49:55.665237 TX Vref=30, minBit 0, minWin=25, winSum=419
8909 11:49:55.668464 TX Vref=32, minBit 0, minWin=25, winSum=414
8910 11:49:55.671574 TX Vref=34, minBit 0, minWin=24, winSum=402
8911 11:49:55.678564 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8912 11:49:55.678640
8913 11:49:55.681684 Final TX Range 0 Vref 28
8914 11:49:55.681772
8915 11:49:55.681833 ==
8916 11:49:55.684688 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:49:55.688397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:49:55.688502 ==
8919 11:49:55.688591
8920 11:49:55.688676
8921 11:49:55.691661 TX Vref Scan disable
8922 11:49:55.698289 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8923 11:49:55.698364 == TX Byte 0 ==
8924 11:49:55.701473 u2DelayCellOfst[0]=17 cells (5 PI)
8925 11:49:55.704423 u2DelayCellOfst[1]=10 cells (3 PI)
8926 11:49:55.708199 u2DelayCellOfst[2]=0 cells (0 PI)
8927 11:49:55.711479 u2DelayCellOfst[3]=6 cells (2 PI)
8928 11:49:55.714553 u2DelayCellOfst[4]=6 cells (2 PI)
8929 11:49:55.717797 u2DelayCellOfst[5]=17 cells (5 PI)
8930 11:49:55.721423 u2DelayCellOfst[6]=17 cells (5 PI)
8931 11:49:55.721497 u2DelayCellOfst[7]=6 cells (2 PI)
8932 11:49:55.727530 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8933 11:49:55.730887 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8934 11:49:55.730987 == TX Byte 1 ==
8935 11:49:55.734606 u2DelayCellOfst[8]=0 cells (0 PI)
8936 11:49:55.737539 u2DelayCellOfst[9]=3 cells (1 PI)
8937 11:49:55.741064 u2DelayCellOfst[10]=10 cells (3 PI)
8938 11:49:55.744700 u2DelayCellOfst[11]=3 cells (1 PI)
8939 11:49:55.747774 u2DelayCellOfst[12]=13 cells (4 PI)
8940 11:49:55.750885 u2DelayCellOfst[13]=13 cells (4 PI)
8941 11:49:55.754824 u2DelayCellOfst[14]=17 cells (5 PI)
8942 11:49:55.758078 u2DelayCellOfst[15]=17 cells (5 PI)
8943 11:49:55.761336 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8944 11:49:55.767712 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8945 11:49:55.767815 DramC Write-DBI on
8946 11:49:55.767905 ==
8947 11:49:55.771038 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 11:49:55.774285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 11:49:55.774358 ==
8950 11:49:55.778038
8951 11:49:55.778133
8952 11:49:55.778220 TX Vref Scan disable
8953 11:49:55.781352 == TX Byte 0 ==
8954 11:49:55.784512 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8955 11:49:55.787644 == TX Byte 1 ==
8956 11:49:55.790874 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8957 11:49:55.790947 DramC Write-DBI off
8958 11:49:55.791010
8959 11:49:55.794763 [DATLAT]
8960 11:49:55.794863 Freq=1600, CH1 RK1
8961 11:49:55.794952
8962 11:49:55.798084 DATLAT Default: 0xf
8963 11:49:55.798176 0, 0xFFFF, sum = 0
8964 11:49:55.800990 1, 0xFFFF, sum = 0
8965 11:49:55.801084 2, 0xFFFF, sum = 0
8966 11:49:55.804534 3, 0xFFFF, sum = 0
8967 11:49:55.804635 4, 0xFFFF, sum = 0
8968 11:49:55.807555 5, 0xFFFF, sum = 0
8969 11:49:55.811096 6, 0xFFFF, sum = 0
8970 11:49:55.811173 7, 0xFFFF, sum = 0
8971 11:49:55.814144 8, 0xFFFF, sum = 0
8972 11:49:55.814219 9, 0xFFFF, sum = 0
8973 11:49:55.817378 10, 0xFFFF, sum = 0
8974 11:49:55.817487 11, 0xFFFF, sum = 0
8975 11:49:55.821256 12, 0xFFFF, sum = 0
8976 11:49:55.821369 13, 0xFFFF, sum = 0
8977 11:49:55.824192 14, 0x0, sum = 1
8978 11:49:55.824297 15, 0x0, sum = 2
8979 11:49:55.827493 16, 0x0, sum = 3
8980 11:49:55.827568 17, 0x0, sum = 4
8981 11:49:55.831213 best_step = 15
8982 11:49:55.831285
8983 11:49:55.831346 ==
8984 11:49:55.834197 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 11:49:55.837400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 11:49:55.837501 ==
8987 11:49:55.837632 RX Vref Scan: 0
8988 11:49:55.840659
8989 11:49:55.840748 RX Vref 0 -> 0, step: 1
8990 11:49:55.840809
8991 11:49:55.844430 RX Delay 19 -> 252, step: 4
8992 11:49:55.847446 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8993 11:49:55.853871 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8994 11:49:55.857526 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8995 11:49:55.860742 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8996 11:49:55.864000 iDelay=195, Bit 4, Center 128 (79 ~ 178) 100
8997 11:49:55.867358 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8998 11:49:55.870666 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8999 11:49:55.877426 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9000 11:49:55.880699 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9001 11:49:55.883935 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9002 11:49:55.887309 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9003 11:49:55.890692 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9004 11:49:55.897227 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9005 11:49:55.900492 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9006 11:49:55.903876 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9007 11:49:55.907128 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9008 11:49:55.907202 ==
9009 11:49:55.910374 Dram Type= 6, Freq= 0, CH_1, rank 1
9010 11:49:55.917408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9011 11:49:55.917522 ==
9012 11:49:55.917648 DQS Delay:
9013 11:49:55.920699 DQS0 = 0, DQS1 = 0
9014 11:49:55.920781 DQM Delay:
9015 11:49:55.923998 DQM0 = 134, DQM1 = 130
9016 11:49:55.924078 DQ Delay:
9017 11:49:55.927587 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9018 11:49:55.930654 DQ4 =128, DQ5 =146, DQ6 =144, DQ7 =134
9019 11:49:55.934434 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9020 11:49:55.937528 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9021 11:49:55.937661
9022 11:49:55.937725
9023 11:49:55.937784
9024 11:49:55.940484 [DramC_TX_OE_Calibration] TA2
9025 11:49:55.943971 Original DQ_B0 (3 6) =30, OEN = 27
9026 11:49:55.947450 Original DQ_B1 (3 6) =30, OEN = 27
9027 11:49:55.950672 24, 0x0, End_B0=24 End_B1=24
9028 11:49:55.950792 25, 0x0, End_B0=25 End_B1=25
9029 11:49:55.953914 26, 0x0, End_B0=26 End_B1=26
9030 11:49:55.957322 27, 0x0, End_B0=27 End_B1=27
9031 11:49:55.960746 28, 0x0, End_B0=28 End_B1=28
9032 11:49:55.964398 29, 0x0, End_B0=29 End_B1=29
9033 11:49:55.964557 30, 0x0, End_B0=30 End_B1=30
9034 11:49:55.967209 31, 0x4545, End_B0=30 End_B1=30
9035 11:49:55.970921 Byte0 end_step=30 best_step=27
9036 11:49:55.974385 Byte1 end_step=30 best_step=27
9037 11:49:55.977523 Byte0 TX OE(2T, 0.5T) = (3, 3)
9038 11:49:55.980799 Byte1 TX OE(2T, 0.5T) = (3, 3)
9039 11:49:55.980971
9040 11:49:55.981069
9041 11:49:55.987457 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9042 11:49:55.990958 CH1 RK1: MR19=303, MR18=2207
9043 11:49:55.997032 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9044 11:49:56.000833 [RxdqsGatingPostProcess] freq 1600
9045 11:49:56.004041 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9046 11:49:56.007205 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 11:49:56.010423 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 11:49:56.013969 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 11:49:56.017462 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 11:49:56.020686 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 11:49:56.023751 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 11:49:56.026968 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 11:49:56.030360 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 11:49:56.034310 Pre-setting of DQS Precalculation
9055 11:49:56.037282 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9056 11:49:56.043899 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9057 11:49:56.053704 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9058 11:49:56.054128
9059 11:49:56.054457
9060 11:49:56.056802 [Calibration Summary] 3200 Mbps
9061 11:49:56.057220 CH 0, Rank 0
9062 11:49:56.060558 SW Impedance : PASS
9063 11:49:56.061072 DUTY Scan : NO K
9064 11:49:56.064160 ZQ Calibration : PASS
9065 11:49:56.067250 Jitter Meter : NO K
9066 11:49:56.067754 CBT Training : PASS
9067 11:49:56.070311 Write leveling : PASS
9068 11:49:56.070774 RX DQS gating : PASS
9069 11:49:56.073720 RX DQ/DQS(RDDQC) : PASS
9070 11:49:56.076813 TX DQ/DQS : PASS
9071 11:49:56.077278 RX DATLAT : PASS
9072 11:49:56.080270 RX DQ/DQS(Engine): PASS
9073 11:49:56.084123 TX OE : PASS
9074 11:49:56.084641 All Pass.
9075 11:49:56.084974
9076 11:49:56.085303 CH 0, Rank 1
9077 11:49:56.087145 SW Impedance : PASS
9078 11:49:56.090370 DUTY Scan : NO K
9079 11:49:56.090884 ZQ Calibration : PASS
9080 11:49:56.093608 Jitter Meter : NO K
9081 11:49:56.097381 CBT Training : PASS
9082 11:49:56.097954 Write leveling : PASS
9083 11:49:56.100378 RX DQS gating : PASS
9084 11:49:56.103246 RX DQ/DQS(RDDQC) : PASS
9085 11:49:56.103664 TX DQ/DQS : PASS
9086 11:49:56.106950 RX DATLAT : PASS
9087 11:49:56.110049 RX DQ/DQS(Engine): PASS
9088 11:49:56.110470 TX OE : PASS
9089 11:49:56.113404 All Pass.
9090 11:49:56.113852
9091 11:49:56.114186 CH 1, Rank 0
9092 11:49:56.116574 SW Impedance : PASS
9093 11:49:56.116988 DUTY Scan : NO K
9094 11:49:56.119892 ZQ Calibration : PASS
9095 11:49:56.122982 Jitter Meter : NO K
9096 11:49:56.123418 CBT Training : PASS
9097 11:49:56.126218 Write leveling : PASS
9098 11:49:56.130033 RX DQS gating : PASS
9099 11:49:56.130450 RX DQ/DQS(RDDQC) : PASS
9100 11:49:56.132726 TX DQ/DQS : PASS
9101 11:49:56.133144 RX DATLAT : PASS
9102 11:49:56.136644 RX DQ/DQS(Engine): PASS
9103 11:49:56.139759 TX OE : PASS
9104 11:49:56.140426 All Pass.
9105 11:49:56.140967
9106 11:49:56.141479 CH 1, Rank 1
9107 11:49:56.143027 SW Impedance : PASS
9108 11:49:56.146571 DUTY Scan : NO K
9109 11:49:56.146989 ZQ Calibration : PASS
9110 11:49:56.149860 Jitter Meter : NO K
9111 11:49:56.152965 CBT Training : PASS
9112 11:49:56.153380 Write leveling : PASS
9113 11:49:56.156653 RX DQS gating : PASS
9114 11:49:56.160405 RX DQ/DQS(RDDQC) : PASS
9115 11:49:56.160919 TX DQ/DQS : PASS
9116 11:49:56.163249 RX DATLAT : PASS
9117 11:49:56.166507 RX DQ/DQS(Engine): PASS
9118 11:49:56.166922 TX OE : PASS
9119 11:49:56.169836 All Pass.
9120 11:49:56.170253
9121 11:49:56.170583 DramC Write-DBI on
9122 11:49:56.172660 PER_BANK_REFRESH: Hybrid Mode
9123 11:49:56.173077 TX_TRACKING: ON
9124 11:49:56.183226 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9125 11:49:56.189986 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9126 11:49:56.199953 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9127 11:49:56.202921 [FAST_K] Save calibration result to emmc
9128 11:49:56.206130 sync common calibartion params.
9129 11:49:56.206546 sync cbt_mode0:1, 1:1
9130 11:49:56.209965 dram_init: ddr_geometry: 2
9131 11:49:56.213403 dram_init: ddr_geometry: 2
9132 11:49:56.213973 dram_init: ddr_geometry: 2
9133 11:49:56.216536 0:dram_rank_size:100000000
9134 11:49:56.220373 1:dram_rank_size:100000000
9135 11:49:56.222973 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9136 11:49:56.226719 DFS_SHUFFLE_HW_MODE: ON
9137 11:49:56.230027 dramc_set_vcore_voltage set vcore to 725000
9138 11:49:56.233478 Read voltage for 1600, 0
9139 11:49:56.234002 Vio18 = 0
9140 11:49:56.236877 Vcore = 725000
9141 11:49:56.237389 Vdram = 0
9142 11:49:56.237780 Vddq = 0
9143 11:49:56.238094 Vmddr = 0
9144 11:49:56.239866 switch to 3200 Mbps bootup
9145 11:49:56.243001 [DramcRunTimeConfig]
9146 11:49:56.243418 PHYPLL
9147 11:49:56.246088 DPM_CONTROL_AFTERK: ON
9148 11:49:56.246504 PER_BANK_REFRESH: ON
9149 11:49:56.249991 REFRESH_OVERHEAD_REDUCTION: ON
9150 11:49:56.253483 CMD_PICG_NEW_MODE: OFF
9151 11:49:56.254064 XRTWTW_NEW_MODE: ON
9152 11:49:56.256450 XRTRTR_NEW_MODE: ON
9153 11:49:56.256865 TX_TRACKING: ON
9154 11:49:56.259696 RDSEL_TRACKING: OFF
9155 11:49:56.263035 DQS Precalculation for DVFS: ON
9156 11:49:56.263566 RX_TRACKING: OFF
9157 11:49:56.263902 HW_GATING DBG: ON
9158 11:49:56.266845 ZQCS_ENABLE_LP4: ON
9159 11:49:56.269945 RX_PICG_NEW_MODE: ON
9160 11:49:56.270363 TX_PICG_NEW_MODE: ON
9161 11:49:56.272985 ENABLE_RX_DCM_DPHY: ON
9162 11:49:56.276029 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9163 11:49:56.276539 DUMMY_READ_FOR_TRACKING: OFF
9164 11:49:56.279348 !!! SPM_CONTROL_AFTERK: OFF
9165 11:49:56.283253 !!! SPM could not control APHY
9166 11:49:56.286512 IMPEDANCE_TRACKING: ON
9167 11:49:56.287029 TEMP_SENSOR: ON
9168 11:49:56.289436 HW_SAVE_FOR_SR: OFF
9169 11:49:56.293006 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9170 11:49:56.296083 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9171 11:49:56.296601 Read ODT Tracking: ON
9172 11:49:56.299847 Refresh Rate DeBounce: ON
9173 11:49:56.303041 DFS_NO_QUEUE_FLUSH: ON
9174 11:49:56.305916 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9175 11:49:56.306332 ENABLE_DFS_RUNTIME_MRW: OFF
9176 11:49:56.309548 DDR_RESERVE_NEW_MODE: ON
9177 11:49:56.312951 MR_CBT_SWITCH_FREQ: ON
9178 11:49:56.313403 =========================
9179 11:49:56.332813 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9180 11:49:56.336432 dram_init: ddr_geometry: 2
9181 11:49:56.354484 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9182 11:49:56.357411 dram_init: dram init end (result: 0)
9183 11:49:56.363904 DRAM-K: Full calibration passed in 24477 msecs
9184 11:49:56.367943 MRC: failed to locate region type 0.
9185 11:49:56.368506 DRAM rank0 size:0x100000000,
9186 11:49:56.370713 DRAM rank1 size=0x100000000
9187 11:49:56.381004 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9188 11:49:56.387466 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9189 11:49:56.394052 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9190 11:49:56.401008 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9191 11:49:56.403963 DRAM rank0 size:0x100000000,
9192 11:49:56.406949 DRAM rank1 size=0x100000000
9193 11:49:56.407632 CBMEM:
9194 11:49:56.410664 IMD: root @ 0xfffff000 254 entries.
9195 11:49:56.413918 IMD: root @ 0xffffec00 62 entries.
9196 11:49:56.417148 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9197 11:49:56.420815 WARNING: RO_VPD is uninitialized or empty.
9198 11:49:56.427010 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9199 11:49:56.434199 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9200 11:49:56.447163 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9201 11:49:56.458371 BS: romstage times (exec / console): total (unknown) / 24008 ms
9202 11:49:56.459042
9203 11:49:56.459425
9204 11:49:56.468857 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9205 11:49:56.472095 ARM64: Exception handlers installed.
9206 11:49:56.475448 ARM64: Testing exception
9207 11:49:56.478500 ARM64: Done test exception
9208 11:49:56.478960 Enumerating buses...
9209 11:49:56.481880 Show all devs... Before device enumeration.
9210 11:49:56.485513 Root Device: enabled 1
9211 11:49:56.488782 CPU_CLUSTER: 0: enabled 1
9212 11:49:56.489240 CPU: 00: enabled 1
9213 11:49:56.492247 Compare with tree...
9214 11:49:56.492807 Root Device: enabled 1
9215 11:49:56.495384 CPU_CLUSTER: 0: enabled 1
9216 11:49:56.498349 CPU: 00: enabled 1
9217 11:49:56.498810 Root Device scanning...
9218 11:49:56.501694 scan_static_bus for Root Device
9219 11:49:56.505148 CPU_CLUSTER: 0 enabled
9220 11:49:56.508060 scan_static_bus for Root Device done
9221 11:49:56.511562 scan_bus: bus Root Device finished in 8 msecs
9222 11:49:56.512025 done
9223 11:49:56.518142 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9224 11:49:56.521749 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9225 11:49:56.528147 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9226 11:49:56.531620 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9227 11:49:56.534943 Allocating resources...
9228 11:49:56.538536 Reading resources...
9229 11:49:56.541205 Root Device read_resources bus 0 link: 0
9230 11:49:56.541834 DRAM rank0 size:0x100000000,
9231 11:49:56.544793 DRAM rank1 size=0x100000000
9232 11:49:56.547730 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9233 11:49:56.550830 CPU: 00 missing read_resources
9234 11:49:56.557771 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9235 11:49:56.561632 Root Device read_resources bus 0 link: 0 done
9236 11:49:56.562148 Done reading resources.
9237 11:49:56.568215 Show resources in subtree (Root Device)...After reading.
9238 11:49:56.571044 Root Device child on link 0 CPU_CLUSTER: 0
9239 11:49:56.574426 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 11:49:56.585093 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 11:49:56.585694 CPU: 00
9242 11:49:56.588117 Root Device assign_resources, bus 0 link: 0
9243 11:49:56.591533 CPU_CLUSTER: 0 missing set_resources
9244 11:49:56.594527 Root Device assign_resources, bus 0 link: 0 done
9245 11:49:56.598157 Done setting resources.
9246 11:49:56.604691 Show resources in subtree (Root Device)...After assigning values.
9247 11:49:56.607972 Root Device child on link 0 CPU_CLUSTER: 0
9248 11:49:56.611129 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 11:49:56.620888 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 11:49:56.621307 CPU: 00
9251 11:49:56.624116 Done allocating resources.
9252 11:49:56.627964 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9253 11:49:56.631412 Enabling resources...
9254 11:49:56.631927 done.
9255 11:49:56.637647 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9256 11:49:56.638343 Initializing devices...
9257 11:49:56.641502 Root Device init
9258 11:49:56.642129 init hardware done!
9259 11:49:56.644471 0x00000018: ctrlr->caps
9260 11:49:56.648026 52.000 MHz: ctrlr->f_max
9261 11:49:56.648456 0.400 MHz: ctrlr->f_min
9262 11:49:56.651099 0x40ff8080: ctrlr->voltages
9263 11:49:56.651518 sclk: 390625
9264 11:49:56.654922 Bus Width = 1
9265 11:49:56.655333 sclk: 390625
9266 11:49:56.657525 Bus Width = 1
9267 11:49:56.658002 Early init status = 3
9268 11:49:56.664520 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9269 11:49:56.668050 in-header: 03 fc 00 00 01 00 00 00
9270 11:49:56.671017 in-data: 00
9271 11:49:56.674406 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9272 11:49:56.679179 in-header: 03 fd 00 00 00 00 00 00
9273 11:49:56.682609 in-data:
9274 11:49:56.685726 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9275 11:49:56.690352 in-header: 03 fc 00 00 01 00 00 00
9276 11:49:56.693665 in-data: 00
9277 11:49:56.697289 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9278 11:49:56.702255 in-header: 03 fd 00 00 00 00 00 00
9279 11:49:56.705686 in-data:
9280 11:49:56.709132 [SSUSB] Setting up USB HOST controller...
9281 11:49:56.712254 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9282 11:49:56.715676 [SSUSB] phy power-on done.
9283 11:49:56.719131 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9284 11:49:56.725957 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9285 11:49:56.728752 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9286 11:49:56.735862 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9287 11:49:56.742260 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9288 11:49:56.748883 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9289 11:49:56.755975 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9290 11:49:56.762179 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9291 11:49:56.765291 SPM: binary array size = 0x9dc
9292 11:49:56.769028 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9293 11:49:56.775398 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9294 11:49:56.781711 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9295 11:49:56.786148 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9296 11:49:56.791952 configure_display: Starting display init
9297 11:49:56.825679 anx7625_power_on_init: Init interface.
9298 11:49:56.828696 anx7625_disable_pd_protocol: Disabled PD feature.
9299 11:49:56.832524 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9300 11:49:56.860111 anx7625_start_dp_work: Secure OCM version=00
9301 11:49:56.863610 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9302 11:49:56.878463 sp_tx_get_edid_block: EDID Block = 1
9303 11:49:56.981100 Extracted contents:
9304 11:49:56.983867 header: 00 ff ff ff ff ff ff 00
9305 11:49:56.987700 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9306 11:49:56.990795 version: 01 04
9307 11:49:56.994299 basic params: 95 1f 11 78 0a
9308 11:49:56.997298 chroma info: 76 90 94 55 54 90 27 21 50 54
9309 11:49:57.000843 established: 00 00 00
9310 11:49:57.007406 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9311 11:49:57.010634 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9312 11:49:57.017569 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9313 11:49:57.023483 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9314 11:49:57.030600 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9315 11:49:57.033673 extensions: 00
9316 11:49:57.034194 checksum: fb
9317 11:49:57.034531
9318 11:49:57.037023 Manufacturer: IVO Model 57d Serial Number 0
9319 11:49:57.040178 Made week 0 of 2020
9320 11:49:57.040598 EDID version: 1.4
9321 11:49:57.043882 Digital display
9322 11:49:57.047121 6 bits per primary color channel
9323 11:49:57.047548 DisplayPort interface
9324 11:49:57.050457 Maximum image size: 31 cm x 17 cm
9325 11:49:57.053992 Gamma: 220%
9326 11:49:57.054506 Check DPMS levels
9327 11:49:57.057158 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9328 11:49:57.060053 First detailed timing is preferred timing
9329 11:49:57.063405 Established timings supported:
9330 11:49:57.066982 Standard timings supported:
9331 11:49:57.070407 Detailed timings
9332 11:49:57.073256 Hex of detail: 383680a07038204018303c0035ae10000019
9333 11:49:57.076727 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9334 11:49:57.083389 0780 0798 07c8 0820 hborder 0
9335 11:49:57.087277 0438 043b 0447 0458 vborder 0
9336 11:49:57.090381 -hsync -vsync
9337 11:49:57.090795 Did detailed timing
9338 11:49:57.093632 Hex of detail: 000000000000000000000000000000000000
9339 11:49:57.096904 Manufacturer-specified data, tag 0
9340 11:49:57.103665 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9341 11:49:57.106732 ASCII string: InfoVision
9342 11:49:57.109874 Hex of detail: 000000fe00523134304e574635205248200a
9343 11:49:57.113120 ASCII string: R140NWF5 RH
9344 11:49:57.113527 Checksum
9345 11:49:57.117085 Checksum: 0xfb (valid)
9346 11:49:57.120257 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9347 11:49:57.123145 DSI data_rate: 832800000 bps
9348 11:49:57.126252 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9349 11:49:57.133517 anx7625_parse_edid: pixelclock(138800).
9350 11:49:57.136495 hactive(1920), hsync(48), hfp(24), hbp(88)
9351 11:49:57.139734 vactive(1080), vsync(12), vfp(3), vbp(17)
9352 11:49:57.143073 anx7625_dsi_config: config dsi.
9353 11:49:57.149671 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9354 11:49:57.163002 anx7625_dsi_config: success to config DSI
9355 11:49:57.166180 anx7625_dp_start: MIPI phy setup OK.
9356 11:49:57.169746 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9357 11:49:57.172725 mtk_ddp_mode_set invalid vrefresh 60
9358 11:49:57.176014 main_disp_path_setup
9359 11:49:57.176655 ovl_layer_smi_id_en
9360 11:49:57.179077 ovl_layer_smi_id_en
9361 11:49:57.179517 ccorr_config
9362 11:49:57.179850 aal_config
9363 11:49:57.182502 gamma_config
9364 11:49:57.182917 postmask_config
9365 11:49:57.185854 dither_config
9366 11:49:57.188988 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9367 11:49:57.195675 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9368 11:49:57.199268 Root Device init finished in 555 msecs
9369 11:49:57.202217 CPU_CLUSTER: 0 init
9370 11:49:57.209096 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9371 11:49:57.212497 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9372 11:49:57.215676 APU_MBOX 0x190000b0 = 0x10001
9373 11:49:57.219307 APU_MBOX 0x190001b0 = 0x10001
9374 11:49:57.222402 APU_MBOX 0x190005b0 = 0x10001
9375 11:49:57.225712 APU_MBOX 0x190006b0 = 0x10001
9376 11:49:57.228986 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9377 11:49:57.241775 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9378 11:49:57.254147 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9379 11:49:57.261200 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9380 11:49:57.272335 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9381 11:49:57.281546 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9382 11:49:57.284752 CPU_CLUSTER: 0 init finished in 81 msecs
9383 11:49:57.288218 Devices initialized
9384 11:49:57.291121 Show all devs... After init.
9385 11:49:57.291554 Root Device: enabled 1
9386 11:49:57.294983 CPU_CLUSTER: 0: enabled 1
9387 11:49:57.298189 CPU: 00: enabled 1
9388 11:49:57.301747 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9389 11:49:57.304750 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9390 11:49:57.308729 ELOG: NV offset 0x57f000 size 0x1000
9391 11:49:57.314817 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9392 11:49:57.321320 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9393 11:49:57.324767 ELOG: Event(17) added with size 13 at 2023-11-24 11:47:46 UTC
9394 11:49:57.327842 out: cmd=0x121: 03 db 21 01 00 00 00 00
9395 11:49:57.331779 in-header: 03 c7 00 00 2c 00 00 00
9396 11:49:57.344885 in-data: 98 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 11:49:57.351889 ELOG: Event(A1) added with size 10 at 2023-11-24 11:47:46 UTC
9398 11:49:57.358393 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9399 11:49:57.361432 ELOG: Event(A0) added with size 9 at 2023-11-24 11:47:46 UTC
9400 11:49:57.368855 elog_add_boot_reason: Logged dev mode boot
9401 11:49:57.372125 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9402 11:49:57.375200 Finalize devices...
9403 11:49:57.375619 Devices finalized
9404 11:49:57.381682 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9405 11:49:57.385137 Writing coreboot table at 0xffe64000
9406 11:49:57.388741 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 11:49:57.391995 1. 0000000040000000-00000000400fffff: RAM
9408 11:49:57.395169 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 11:49:57.401704 3. 000000004032b000-00000000545fffff: RAM
9410 11:49:57.404947 4. 0000000054600000-000000005465ffff: BL31
9411 11:49:57.408280 5. 0000000054660000-00000000ffe63fff: RAM
9412 11:49:57.411571 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 11:49:57.418122 7. 0000000100000000-000000023fffffff: RAM
9414 11:49:57.418726 Passing 5 GPIOs to payload:
9415 11:49:57.424990 NAME | PORT | POLARITY | VALUE
9416 11:49:57.427926 EC in RW | 0x000000aa | low | undefined
9417 11:49:57.435115 EC interrupt | 0x00000005 | low | undefined
9418 11:49:57.438351 TPM interrupt | 0x000000ab | high | undefined
9419 11:49:57.442049 SD card detect | 0x00000011 | high | undefined
9420 11:49:57.448012 speaker enable | 0x00000093 | high | undefined
9421 11:49:57.451569 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 11:49:57.454416 in-header: 03 f9 00 00 02 00 00 00
9423 11:49:57.455004 in-data: 02 00
9424 11:49:57.458305 ADC[4]: Raw value=904357 ID=7
9425 11:49:57.461698 ADC[3]: Raw value=213441 ID=1
9426 11:49:57.462236 RAM Code: 0x71
9427 11:49:57.465019 ADC[6]: Raw value=75332 ID=0
9428 11:49:57.468230 ADC[5]: Raw value=213072 ID=1
9429 11:49:57.468730 SKU Code: 0x1
9430 11:49:57.474528 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2e6b
9431 11:49:57.478556 coreboot table: 964 bytes.
9432 11:49:57.481811 IMD ROOT 0. 0xfffff000 0x00001000
9433 11:49:57.485123 IMD SMALL 1. 0xffffe000 0x00001000
9434 11:49:57.488200 RO MCACHE 2. 0xffffc000 0x00001104
9435 11:49:57.491569 CONSOLE 3. 0xfff7c000 0x00080000
9436 11:49:57.494555 FMAP 4. 0xfff7b000 0x00000452
9437 11:49:57.498200 TIME STAMP 5. 0xfff7a000 0x00000910
9438 11:49:57.501159 VBOOT WORK 6. 0xfff66000 0x00014000
9439 11:49:57.504222 RAMOOPS 7. 0xffe66000 0x00100000
9440 11:49:57.508606 COREBOOT 8. 0xffe64000 0x00002000
9441 11:49:57.509135 IMD small region:
9442 11:49:57.511369 IMD ROOT 0. 0xffffec00 0x00000400
9443 11:49:57.514660 VPD 1. 0xffffeb80 0x0000006c
9444 11:49:57.518020 MMC STATUS 2. 0xffffeb60 0x00000004
9445 11:49:57.524973 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 11:49:57.525479 Probing TPM: done!
9447 11:49:57.531534 Connected to device vid:did:rid of 1ae0:0028:00
9448 11:49:57.538179 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9449 11:49:57.541691 Initialized TPM device CR50 revision 0
9450 11:49:57.544660 Checking cr50 for pending updates
9451 11:49:57.551026 Reading cr50 TPM mode
9452 11:49:57.559501 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9453 11:49:57.567065 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 11:49:57.606550 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9455 11:49:57.610033 Checking segment from ROM address 0x40100000
9456 11:49:57.612904 Checking segment from ROM address 0x4010001c
9457 11:49:57.619948 Loading segment from ROM address 0x40100000
9458 11:49:57.620464 code (compression=0)
9459 11:49:57.627276 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 11:49:57.637067 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 11:49:57.637744 it's not compressed!
9462 11:49:57.643664 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 11:49:57.646797 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 11:49:57.666914 Loading segment from ROM address 0x4010001c
9465 11:49:57.667405 Entry Point 0x80000000
9466 11:49:57.670102 Loaded segments
9467 11:49:57.673947 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9468 11:49:57.680242 Jumping to boot code at 0x80000000(0xffe64000)
9469 11:49:57.686898 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 11:49:57.694223 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 11:49:57.701261 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9472 11:49:57.704415 Checking segment from ROM address 0x40100000
9473 11:49:57.707794 Checking segment from ROM address 0x4010001c
9474 11:49:57.714262 Loading segment from ROM address 0x40100000
9475 11:49:57.714809 code (compression=1)
9476 11:49:57.721345 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 11:49:57.731340 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 11:49:57.731932 using LZMA
9479 11:49:57.740053 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 11:49:57.746112 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 11:49:57.749794 Loading segment from ROM address 0x4010001c
9482 11:49:57.750400 Entry Point 0x54601000
9483 11:49:57.752684 Loaded segments
9484 11:49:57.756441 NOTICE: MT8192 bl31_setup
9485 11:49:57.763446 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 11:49:57.766740 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 11:49:57.769714 WARNING: region 0:
9488 11:49:57.772932 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 11:49:57.773409 WARNING: region 1:
9490 11:49:57.779995 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 11:49:57.783288 WARNING: region 2:
9492 11:49:57.786368 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 11:49:57.789746 WARNING: region 3:
9494 11:49:57.793491 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 11:49:57.796660 WARNING: region 4:
9496 11:49:57.802944 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 11:49:57.803473 WARNING: region 5:
9498 11:49:57.806928 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 11:49:57.810268 WARNING: region 6:
9500 11:49:57.813390 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 11:49:57.816691 WARNING: region 7:
9502 11:49:57.819811 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 11:49:57.826910 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 11:49:57.829887 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 11:49:57.833418 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 11:49:57.840088 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 11:49:57.843597 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 11:49:57.846571 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 11:49:57.853028 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 11:49:57.856823 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 11:49:57.863067 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 11:49:57.866473 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 11:49:57.870062 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 11:49:57.876420 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 11:49:57.880490 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 11:49:57.883547 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 11:49:57.890297 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 11:49:57.893478 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 11:49:57.897123 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 11:49:57.903971 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 11:49:57.906888 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 11:49:57.910158 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 11:49:57.916879 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 11:49:57.920133 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 11:49:57.927172 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 11:49:57.930506 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 11:49:57.933688 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 11:49:57.940227 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 11:49:57.943333 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 11:49:57.950286 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 11:49:57.953780 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 11:49:57.956799 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 11:49:57.963610 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 11:49:57.967342 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 11:49:57.970968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 11:49:57.977023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 11:49:57.980680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 11:49:57.983355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 11:49:57.986799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 11:49:57.993378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 11:49:57.996839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 11:49:58.000463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 11:49:58.003848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 11:49:58.010198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 11:49:58.013614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 11:49:58.016707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 11:49:58.020716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 11:49:58.026731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 11:49:58.030260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 11:49:58.033507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 11:49:58.040050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 11:49:58.043921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 11:49:58.047054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 11:49:58.054432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 11:49:58.056849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 11:49:58.064215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 11:49:58.067175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 11:49:58.073817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 11:49:58.077247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 11:49:58.080455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 11:49:58.087371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 11:49:58.090476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 11:49:58.097253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 11:49:58.100559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 11:49:58.106946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 11:49:58.110674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 11:49:58.113521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 11:49:58.120620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 11:49:58.123925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 11:49:58.130476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 11:49:58.134177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 11:49:58.140443 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 11:49:58.143967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 11:49:58.147124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 11:49:58.154236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 11:49:58.157327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 11:49:58.164463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 11:49:58.167629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 11:49:58.174143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 11:49:58.177333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 11:49:58.180764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 11:49:58.187042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 11:49:58.190434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 11:49:58.197678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 11:49:58.200794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 11:49:58.207360 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 11:49:58.211027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 11:49:58.214154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 11:49:58.221362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 11:49:58.224641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 11:49:58.230998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 11:49:58.234055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 11:49:58.237481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 11:49:58.243977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 11:49:58.247595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 11:49:58.254006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 11:49:58.257739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 11:49:58.263956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 11:49:58.267737 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 11:49:58.270616 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 11:49:58.273992 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 11:49:58.280750 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 11:49:58.283986 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 11:49:58.287129 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 11:49:58.294487 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 11:49:58.297689 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 11:49:58.304589 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 11:49:58.307709 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 11:49:58.310942 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 11:49:58.317457 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 11:49:58.320532 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 11:49:58.327317 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 11:49:58.331095 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 11:49:58.334416 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 11:49:58.341042 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 11:49:58.344277 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 11:49:58.350661 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 11:49:58.354156 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 11:49:58.357255 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 11:49:58.361181 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 11:49:58.367511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 11:49:58.371092 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 11:49:58.374046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 11:49:58.377721 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 11:49:58.384077 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 11:49:58.387653 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 11:49:58.390803 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 11:49:58.397765 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 11:49:58.400829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 11:49:58.407775 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 11:49:58.411064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 11:49:58.414453 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 11:49:58.420992 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 11:49:58.424123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 11:49:58.427392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 11:49:58.434272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 11:49:58.437493 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 11:49:58.444481 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 11:49:58.447683 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 11:49:58.451014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 11:49:58.457540 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 11:49:58.460727 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 11:49:58.467784 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 11:49:58.470869 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 11:49:58.474005 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 11:49:58.480672 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 11:49:58.484446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 11:49:58.487753 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 11:49:58.494347 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 11:49:58.497523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 11:49:58.504009 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 11:49:58.507719 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 11:49:58.510881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 11:49:58.517611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 11:49:58.520696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 11:49:58.524394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 11:49:58.531296 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 11:49:58.534737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 11:49:58.541189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 11:49:58.544939 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 11:49:58.547944 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 11:49:58.554639 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 11:49:58.557706 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 11:49:58.561636 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 11:49:58.567902 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 11:49:58.571084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 11:49:58.577483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 11:49:58.581086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 11:49:58.584728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 11:49:58.591639 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 11:49:58.594741 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 11:49:58.600895 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 11:49:58.604114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 11:49:58.607244 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 11:49:58.614451 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 11:49:58.617509 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 11:49:58.624134 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 11:49:58.627333 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 11:49:58.630379 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 11:49:58.636988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 11:49:58.640609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 11:49:58.647307 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 11:49:58.650395 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 11:49:58.653860 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 11:49:58.660347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 11:49:58.663472 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 11:49:58.670664 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 11:49:58.673860 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 11:49:58.677067 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 11:49:58.683547 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 11:49:58.686771 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 11:49:58.693605 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 11:49:58.696932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 11:49:58.700313 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 11:49:58.706988 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 11:49:58.710381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 11:49:58.717234 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 11:49:58.720362 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 11:49:58.723631 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 11:49:58.730169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 11:49:58.733644 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 11:49:58.740275 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 11:49:58.743672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 11:49:58.747007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 11:49:58.753469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 11:49:58.757311 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 11:49:58.763642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 11:49:58.766938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 11:49:58.773896 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 11:49:58.776964 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 11:49:58.780256 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 11:49:58.786894 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 11:49:58.790165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 11:49:58.796993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 11:49:58.800255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 11:49:58.807067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 11:49:58.810456 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 11:49:58.813450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 11:49:58.819806 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 11:49:58.823858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 11:49:58.830248 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 11:49:58.833398 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 11:49:58.837081 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 11:49:58.843255 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 11:49:58.847048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 11:49:58.853556 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 11:49:58.856768 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 11:49:58.863513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 11:49:58.866602 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 11:49:58.869691 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 11:49:58.876341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 11:49:58.879705 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 11:49:58.883428 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 11:49:58.886473 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 11:49:58.893287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 11:49:58.896382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 11:49:58.900131 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 11:49:58.906499 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 11:49:58.909843 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 11:49:58.913305 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 11:49:58.920204 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 11:49:58.923079 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 11:49:58.926242 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 11:49:58.933334 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 11:49:58.935929 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 11:49:58.939746 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 11:49:58.946270 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 11:49:58.949592 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 11:49:58.956208 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 11:49:58.959681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 11:49:58.962840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 11:49:58.969546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 11:49:58.972657 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 11:49:58.975962 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 11:49:58.982565 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 11:49:58.985863 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 11:49:58.989627 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 11:49:58.996153 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 11:49:58.999296 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 11:49:59.006019 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 11:49:59.009207 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 11:49:59.012685 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 11:49:59.019344 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 11:49:59.022594 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 11:49:59.025895 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 11:49:59.032892 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 11:49:59.035777 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 11:49:59.042411 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 11:49:59.045931 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 11:49:59.048855 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 11:49:59.055489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 11:49:59.059024 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 11:49:59.062171 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 11:49:59.065466 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 11:49:59.068687 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 11:49:59.075578 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 11:49:59.078890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 11:49:59.082265 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 11:49:59.085617 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 11:49:59.092167 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 11:49:59.095317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 11:49:59.098766 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 11:49:59.102656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 11:49:59.109258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 11:49:59.112261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 11:49:59.118768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 11:49:59.121878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 11:49:59.125666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 11:49:59.132244 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 11:49:59.135430 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 11:49:59.142111 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 11:49:59.145526 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 11:49:59.148683 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 11:49:59.155297 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 11:49:59.158214 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 11:49:59.165460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 11:49:59.168309 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 11:49:59.175360 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 11:49:59.178462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 11:49:59.181695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 11:49:59.188356 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 11:49:59.192058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 11:49:59.198499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 11:49:59.201768 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 11:49:59.205105 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 11:49:59.211889 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 11:49:59.215404 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 11:49:59.218328 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 11:49:59.225096 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 11:49:59.228382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 11:49:59.235364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 11:49:59.238521 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 11:49:59.245206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 11:49:59.248298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 11:49:59.251909 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 11:49:59.258712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 11:49:59.261823 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 11:49:59.268383 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 11:49:59.271663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 11:49:59.274965 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 11:49:59.281928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 11:49:59.285017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 11:49:59.291584 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 11:49:59.295003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 11:49:59.298962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 11:49:59.305150 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 11:49:59.308231 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 11:49:59.314798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 11:49:59.318007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 11:49:59.324547 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 11:49:59.328295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 11:49:59.331599 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 11:49:59.337993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 11:49:59.341208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 11:49:59.348144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 11:49:59.351485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 11:49:59.354906 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 11:49:59.361020 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 11:49:59.364782 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 11:49:59.371280 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 11:49:59.374936 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 11:49:59.377627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 11:49:59.384899 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 11:49:59.388266 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 11:49:59.394674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 11:49:59.398024 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 11:49:59.404854 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 11:49:59.407576 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 11:49:59.411113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 11:49:59.418008 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 11:49:59.421371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 11:49:59.424714 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 11:49:59.431878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 11:49:59.435101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 11:49:59.441185 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 11:49:59.444987 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 11:49:59.451307 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 11:49:59.454238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 11:49:59.458346 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 11:49:59.464907 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 11:49:59.468196 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 11:49:59.474790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 11:49:59.477878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 11:49:59.484317 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 11:49:59.487606 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 11:49:59.491398 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 11:49:59.497901 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 11:49:59.501333 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 11:49:59.507733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 11:49:59.511209 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 11:49:59.517751 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 11:49:59.521157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 11:49:59.524546 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 11:49:59.530999 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 11:49:59.534086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 11:49:59.541469 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 11:49:59.544300 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 11:49:59.551005 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 11:49:59.553912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 11:49:59.557101 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 11:49:59.564156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 11:49:59.567423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 11:49:59.574012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 11:49:59.577261 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 11:49:59.583889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 11:49:59.587071 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 11:49:59.594034 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 11:49:59.596953 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 11:49:59.600616 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 11:49:59.607143 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 11:49:59.610551 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 11:49:59.617134 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 11:49:59.620470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 11:49:59.627173 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 11:49:59.630524 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 11:49:59.633811 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 11:49:59.640139 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 11:49:59.643439 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 11:49:59.650250 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 11:49:59.653676 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 11:49:59.660543 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 11:49:59.663690 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 11:49:59.670120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 11:49:59.673267 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 11:49:59.676992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 11:49:59.683478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 11:49:59.686808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 11:49:59.693730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 11:49:59.696726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 11:49:59.703596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 11:49:59.706465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 11:49:59.713571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 11:49:59.716559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 11:49:59.720099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 11:49:59.726495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 11:49:59.729838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 11:49:59.736530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 11:49:59.740371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 11:49:59.746786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 11:49:59.750236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 11:49:59.756870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 11:49:59.760294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 11:49:59.766587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 11:49:59.769753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 11:49:59.776746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 11:49:59.780117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 11:49:59.786695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 11:49:59.790409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 11:49:59.797020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 11:49:59.800014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 11:49:59.806813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 11:49:59.810293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 11:49:59.816849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 11:49:59.819900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 11:49:59.826396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 11:49:59.830284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 11:49:59.833406 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 11:49:59.836405 INFO: [APUAPC] vio 0
9939 11:49:59.843009 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 11:49:59.846151 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 11:49:59.850104 INFO: [APUAPC] D0_APC_0: 0x400510
9942 11:49:59.853448 INFO: [APUAPC] D0_APC_1: 0x0
9943 11:49:59.856850 INFO: [APUAPC] D0_APC_2: 0x1540
9944 11:49:59.860082 INFO: [APUAPC] D0_APC_3: 0x0
9945 11:49:59.863391 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 11:49:59.866821 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 11:49:59.870102 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 11:49:59.870329 INFO: [APUAPC] D1_APC_3: 0x0
9949 11:49:59.876558 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 11:49:59.879746 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 11:49:59.882972 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 11:49:59.883198 INFO: [APUAPC] D2_APC_3: 0x0
9953 11:49:59.886305 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 11:49:59.892930 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 11:49:59.893158 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 11:49:59.896277 INFO: [APUAPC] D3_APC_3: 0x0
9957 11:49:59.900117 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 11:49:59.902755 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 11:49:59.906728 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 11:49:59.909863 INFO: [APUAPC] D4_APC_3: 0x0
9961 11:49:59.913094 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 11:49:59.916346 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 11:49:59.919770 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 11:49:59.922906 INFO: [APUAPC] D5_APC_3: 0x0
9965 11:49:59.926153 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 11:49:59.929753 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 11:49:59.932772 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 11:49:59.936560 INFO: [APUAPC] D6_APC_3: 0x0
9969 11:49:59.939897 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 11:49:59.942623 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 11:49:59.946041 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 11:49:59.949789 INFO: [APUAPC] D7_APC_3: 0x0
9973 11:49:59.953038 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 11:49:59.956054 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 11:49:59.959652 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 11:49:59.962691 INFO: [APUAPC] D8_APC_3: 0x0
9977 11:49:59.966636 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 11:49:59.969239 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 11:49:59.972684 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 11:49:59.976028 INFO: [APUAPC] D9_APC_3: 0x0
9981 11:49:59.979428 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 11:49:59.982876 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 11:49:59.986675 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 11:49:59.989568 INFO: [APUAPC] D10_APC_3: 0x0
9985 11:49:59.992976 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 11:49:59.996247 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 11:49:59.999538 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 11:50:00.002626 INFO: [APUAPC] D11_APC_3: 0x0
9989 11:50:00.005823 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 11:50:00.009786 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 11:50:00.013035 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 11:50:00.016218 INFO: [APUAPC] D12_APC_3: 0x0
9993 11:50:00.019340 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 11:50:00.023069 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 11:50:00.026333 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 11:50:00.029743 INFO: [APUAPC] D13_APC_3: 0x0
9997 11:50:00.033074 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 11:50:00.036206 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 11:50:00.039652 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 11:50:00.043192 INFO: [APUAPC] D14_APC_3: 0x0
10001 11:50:00.046228 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 11:50:00.049753 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 11:50:00.052800 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 11:50:00.056139 INFO: [APUAPC] D15_APC_3: 0x0
10005 11:50:00.059773 INFO: [APUAPC] APC_CON: 0x4
10006 11:50:00.062784 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 11:50:00.066062 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 11:50:00.066630 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 11:50:00.069644 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 11:50:00.072471 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 11:50:00.075965 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 11:50:00.079294 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 11:50:00.082701 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 11:50:00.086546 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 11:50:00.089553 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 11:50:00.092380 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 11:50:00.095978 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 11:50:00.099234 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 11:50:00.099786 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 11:50:00.102528 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 11:50:00.105747 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 11:50:00.109617 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 11:50:00.113069 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 11:50:00.116149 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 11:50:00.119557 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 11:50:00.122622 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 11:50:00.125999 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 11:50:00.129068 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 11:50:00.132336 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 11:50:00.135707 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 11:50:00.136272 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 11:50:00.138854 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 11:50:00.142706 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 11:50:00.145905 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 11:50:00.148881 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 11:50:00.152295 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 11:50:00.155604 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 11:50:00.158796 INFO: [NOCDAPC] APC_CON: 0x4
10039 11:50:00.162170 INFO: [APUAPC] set_apusys_apc done
10040 11:50:00.165838 INFO: [DEVAPC] devapc_init done
10041 11:50:00.168939 INFO: GICv3 without legacy support detected.
10042 11:50:00.172379 INFO: ARM GICv3 driver initialized in EL3
10043 11:50:00.175765 INFO: Maximum SPI INTID supported: 639
10044 11:50:00.182207 INFO: BL31: Initializing runtime services
10045 11:50:00.185732 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 11:50:00.188615 INFO: SPM: enable CPC mode
10047 11:50:00.195425 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 11:50:00.198874 INFO: BL31: Preparing for EL3 exit to normal world
10049 11:50:00.202039 INFO: Entry point address = 0x80000000
10050 11:50:00.205437 INFO: SPSR = 0x8
10051 11:50:00.210907
10052 11:50:00.211057
10053 11:50:00.211181
10054 11:50:00.214176 Starting depthcharge on Spherion...
10055 11:50:00.214327
10056 11:50:00.214447 Wipe memory regions:
10057 11:50:00.214561
10058 11:50:00.215584 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10059 11:50:00.215767 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 11:50:00.215918 Setting prompt string to ['asurada:']
10061 11:50:00.216069 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 11:50:00.217008 [0x00000040000000, 0x00000054600000)
10063 11:50:00.340409
10064 11:50:00.340967 [0x00000054660000, 0x00000080000000)
10065 11:50:00.600082
10066 11:50:00.602739 [0x000000821a7280, 0x000000ffe64000)
10067 11:50:01.344341
10068 11:50:01.344846 [0x00000100000000, 0x00000240000000)
10069 11:50:03.232751
10070 11:50:03.235768 Initializing XHCI USB controller at 0x11200000.
10071 11:50:04.273161
10072 11:50:04.276493 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10073 11:50:04.276706
10074 11:50:04.276867
10075 11:50:04.277015
10076 11:50:04.277516 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 11:50:04.378314 asurada: tftpboot 192.168.201.1 12074027/tftp-deploy-7eni79v0/kernel/image.itb 12074027/tftp-deploy-7eni79v0/kernel/cmdline
10079 11:50:04.378921 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 11:50:04.379472 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 11:50:04.384107 tftpboot 192.168.201.1 12074027/tftp-deploy-7eni79v0/kernel/image.itp-deploy-7eni79v0/kernel/cmdline
10082 11:50:04.384480
10083 11:50:04.384785 Waiting for link
10084 11:50:04.544548
10085 11:50:04.545035 R8152: Initializing
10086 11:50:04.545377
10087 11:50:04.547786 Version 9 (ocp_data = 6010)
10088 11:50:04.548319
10089 11:50:04.550933 R8152: Done initializing
10090 11:50:04.551455
10091 11:50:04.551935 Adding net device
10092 11:50:06.421536
10093 11:50:06.421738 done.
10094 11:50:06.421837
10095 11:50:06.421923 MAC: 00:e0:4c:78:7a:aa
10096 11:50:06.422004
10097 11:50:06.424534 Sending DHCP discover... done.
10098 11:50:06.424655
10099 11:50:06.428241 Waiting for reply... done.
10100 11:50:06.428355
10101 11:50:06.431092 Sending DHCP request... done.
10102 11:50:06.431215
10103 11:50:06.431312 Waiting for reply... done.
10104 11:50:06.431402
10105 11:50:06.434925 My ip is 192.168.201.12
10106 11:50:06.435145
10107 11:50:06.438051 The DHCP server ip is 192.168.201.1
10108 11:50:06.438271
10109 11:50:06.440968 TFTP server IP predefined by user: 192.168.201.1
10110 11:50:06.441148
10111 11:50:06.447882 Bootfile predefined by user: 12074027/tftp-deploy-7eni79v0/kernel/image.itb
10112 11:50:06.448066
10113 11:50:06.450965 Sending tftp read request... done.
10114 11:50:06.451169
10115 11:50:06.454430 Waiting for the transfer...
10116 11:50:06.454516
10117 11:50:06.719095 00000000 ################################################################
10118 11:50:06.719232
10119 11:50:06.982953 00080000 ################################################################
10120 11:50:06.983090
10121 11:50:07.247900 00100000 ################################################################
10122 11:50:07.248036
10123 11:50:07.506238 00180000 ################################################################
10124 11:50:07.506376
10125 11:50:07.763203 00200000 ################################################################
10126 11:50:07.763341
10127 11:50:08.020437 00280000 ################################################################
10128 11:50:08.020575
10129 11:50:08.277836 00300000 ################################################################
10130 11:50:08.277966
10131 11:50:08.536681 00380000 ################################################################
10132 11:50:08.536817
10133 11:50:08.798361 00400000 ################################################################
10134 11:50:08.798499
10135 11:50:09.064398 00480000 ################################################################
10136 11:50:09.064536
10137 11:50:09.326257 00500000 ################################################################
10138 11:50:09.326391
10139 11:50:09.585540 00580000 ################################################################
10140 11:50:09.585732
10141 11:50:09.848100 00600000 ################################################################
10142 11:50:09.848236
10143 11:50:10.106591 00680000 ################################################################
10144 11:50:10.106734
10145 11:50:10.363186 00700000 ################################################################
10146 11:50:10.363331
10147 11:50:10.630088 00780000 ################################################################
10148 11:50:10.630225
10149 11:50:10.901703 00800000 ################################################################
10150 11:50:10.901838
10151 11:50:11.156042 00880000 ################################################################
10152 11:50:11.156191
10153 11:50:11.425092 00900000 ################################################################
10154 11:50:11.425239
10155 11:50:11.685851 00980000 ################################################################
10156 11:50:11.685985
10157 11:50:11.945584 00a00000 ################################################################
10158 11:50:11.945722
10159 11:50:12.226546 00a80000 ################################################################
10160 11:50:12.226687
10161 11:50:12.479885 00b00000 ################################################################
10162 11:50:12.480020
10163 11:50:12.752447 00b80000 ################################################################
10164 11:50:12.752587
10165 11:50:13.015066 00c00000 ################################################################
10166 11:50:13.015209
10167 11:50:13.274330 00c80000 ################################################################
10168 11:50:13.274461
10169 11:50:13.525841 00d00000 ################################################################
10170 11:50:13.525995
10171 11:50:13.790203 00d80000 ################################################################
10172 11:50:13.790353
10173 11:50:14.048296 00e00000 ################################################################
10174 11:50:14.048444
10175 11:50:14.318933 00e80000 ################################################################
10176 11:50:14.319082
10177 11:50:14.572519 00f00000 ################################################################
10178 11:50:14.572662
10179 11:50:14.823034 00f80000 ################################################################
10180 11:50:14.823178
10181 11:50:15.080300 01000000 ################################################################
10182 11:50:15.080473
10183 11:50:15.332028 01080000 ################################################################
10184 11:50:15.332187
10185 11:50:15.583255 01100000 ################################################################
10186 11:50:15.583438
10187 11:50:15.833366 01180000 ################################################################
10188 11:50:15.833516
10189 11:50:16.086241 01200000 ################################################################
10190 11:50:16.086381
10191 11:50:16.340290 01280000 ################################################################
10192 11:50:16.340441
10193 11:50:16.601032 01300000 ################################################################
10194 11:50:16.601182
10195 11:50:16.852749 01380000 ################################################################
10196 11:50:16.852895
10197 11:50:17.108954 01400000 ################################################################
10198 11:50:17.109101
10199 11:50:17.361352 01480000 ################################################################
10200 11:50:17.361500
10201 11:50:17.614835 01500000 ################################################################
10202 11:50:17.614991
10203 11:50:17.869771 01580000 ################################################################
10204 11:50:17.869919
10205 11:50:18.121364 01600000 ################################################################
10206 11:50:18.121534
10207 11:50:18.371091 01680000 ################################################################
10208 11:50:18.371237
10209 11:50:18.623738 01700000 ################################################################
10210 11:50:18.623872
10211 11:50:18.885799 01780000 ################################################################
10212 11:50:18.885945
10213 11:50:19.136532 01800000 ################################################################
10214 11:50:19.136711
10215 11:50:19.390596 01880000 ################################################################
10216 11:50:19.390775
10217 11:50:19.646600 01900000 ################################################################
10218 11:50:19.646744
10219 11:50:19.897088 01980000 ################################################################
10220 11:50:19.897236
10221 11:50:20.152670 01a00000 ################################################################
10222 11:50:20.152814
10223 11:50:20.409824 01a80000 ################################################################
10224 11:50:20.409981
10225 11:50:20.669031 01b00000 ################################################################
10226 11:50:20.669192
10227 11:50:20.697728 01b80000 ####### done.
10228 11:50:20.697824
10229 11:50:20.700880 The bootfile was 28890998 bytes long.
10230 11:50:20.700964
10231 11:50:20.701028 Sending tftp read request... done.
10232 11:50:20.704440
10233 11:50:20.704522 Waiting for the transfer...
10234 11:50:20.704586
10235 11:50:20.707493 00000000 # done.
10236 11:50:20.707580
10237 11:50:20.714235 Command line loaded dynamically from TFTP file: 12074027/tftp-deploy-7eni79v0/kernel/cmdline
10238 11:50:20.714316
10239 11:50:20.737338 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 11:50:20.737466
10241 11:50:20.737626 Loading FIT.
10242 11:50:20.737772
10243 11:50:20.740979 Image ramdisk-1 has 17793440 bytes.
10244 11:50:20.741111
10245 11:50:20.743909 Image fdt-1 has 47278 bytes.
10246 11:50:20.744042
10247 11:50:20.747775 Image kernel-1 has 11048246 bytes.
10248 11:50:20.747923
10249 11:50:20.754449 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 11:50:20.757572
10251 11:50:20.774454 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 11:50:20.774919
10253 11:50:20.777717 Choosing best match conf-1 for compat google,spherion-rev2.
10254 11:50:20.783043
10255 11:50:20.787652 Connected to device vid:did:rid of 1ae0:0028:00
10256 11:50:20.795841
10257 11:50:20.799247 tpm_get_response: command 0x17b, return code 0x0
10258 11:50:20.799673
10259 11:50:20.802395 ec_init: CrosEC protocol v3 supported (256, 248)
10260 11:50:20.806441
10261 11:50:20.809935 tpm_cleanup: add release locality here.
10262 11:50:20.810358
10263 11:50:20.810691 Shutting down all USB controllers.
10264 11:50:20.811004
10265 11:50:20.813505 Removing current net device
10266 11:50:20.813954
10267 11:50:20.819982 Exiting depthcharge with code 4 at timestamp: 49907661
10268 11:50:20.820411
10269 11:50:20.823347 LZMA decompressing kernel-1 to 0x821a6718
10270 11:50:20.823769
10271 11:50:20.826589 LZMA decompressing kernel-1 to 0x40000000
10272 11:50:22.215134
10273 11:50:22.215349 jumping to kernel
10274 11:50:22.216013 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10275 11:50:22.216193 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10276 11:50:22.216337 Setting prompt string to ['Linux version [0-9]']
10277 11:50:22.216464 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 11:50:22.216588 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 11:50:22.297096
10280 11:50:22.300157 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 11:50:22.304003 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10282 11:50:22.304255 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 11:50:22.304433 Setting prompt string to []
10284 11:50:22.304602 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 11:50:22.304763 Using line separator: #'\n'#
10286 11:50:22.304929 No login prompt set.
10287 11:50:22.305090 Parsing kernel messages
10288 11:50:22.305236 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 11:50:22.305504 [login-action] Waiting for messages, (timeout 00:04:03)
10290 11:50:22.323756 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10291 11:50:22.326867 [ 0.000000] random: crng init done
10292 11:50:22.333292 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10293 11:50:22.337077 [ 0.000000] efi: UEFI not found.
10294 11:50:22.343356 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10295 11:50:22.350551 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10296 11:50:22.360015 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10297 11:50:22.370007 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10298 11:50:22.376506 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10299 11:50:22.382975 [ 0.000000] printk: bootconsole [mtk8250] enabled
10300 11:50:22.390021 [ 0.000000] NUMA: No NUMA configuration found
10301 11:50:22.396520 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10302 11:50:22.399730 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10303 11:50:22.402593 [ 0.000000] Zone ranges:
10304 11:50:22.409895 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10305 11:50:22.412849 [ 0.000000] DMA32 empty
10306 11:50:22.419388 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10307 11:50:22.422929 [ 0.000000] Movable zone start for each node
10308 11:50:22.425954 [ 0.000000] Early memory node ranges
10309 11:50:22.432825 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10310 11:50:22.439488 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10311 11:50:22.445869 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10312 11:50:22.452613 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10313 11:50:22.458915 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10314 11:50:22.465763 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10315 11:50:22.521920 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10316 11:50:22.528164 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10317 11:50:22.535117 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10318 11:50:22.538402 [ 0.000000] psci: probing for conduit method from DT.
10319 11:50:22.544736 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10320 11:50:22.548291 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10321 11:50:22.554486 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10322 11:50:22.558227 [ 0.000000] psci: SMC Calling Convention v1.2
10323 11:50:22.564666 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10324 11:50:22.568123 [ 0.000000] Detected VIPT I-cache on CPU0
10325 11:50:22.574551 [ 0.000000] CPU features: detected: GIC system register CPU interface
10326 11:50:22.581037 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10327 11:50:22.587583 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10328 11:50:22.594999 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10329 11:50:22.601078 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10330 11:50:22.610814 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10331 11:50:22.614253 [ 0.000000] alternatives: applying boot alternatives
10332 11:50:22.620782 [ 0.000000] Fallback order for Node 0: 0
10333 11:50:22.627937 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10334 11:50:22.630920 [ 0.000000] Policy zone: Normal
10335 11:50:22.653863 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10336 11:50:22.664180 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10337 11:50:22.674422 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10338 11:50:22.684370 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10339 11:50:22.691039 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10340 11:50:22.694563 <6>[ 0.000000] software IO TLB: area num 8.
10341 11:50:22.751798 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10342 11:50:22.901483 <6>[ 0.000000] Memory: 7952240K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400528K reserved, 32768K cma-reserved)
10343 11:50:22.907853 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10344 11:50:22.914560 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10345 11:50:22.917735 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10346 11:50:22.924229 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10347 11:50:22.931453 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10348 11:50:22.934151 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10349 11:50:22.944291 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10350 11:50:22.951206 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10351 11:50:22.954361 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10352 11:50:22.962142 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10353 11:50:22.965744 <6>[ 0.000000] GICv3: 608 SPIs implemented
10354 11:50:22.972395 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10355 11:50:22.975484 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10356 11:50:22.978581 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10357 11:50:22.988631 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10358 11:50:22.998936 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10359 11:50:23.012109 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10360 11:50:23.018728 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10361 11:50:23.027551 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10362 11:50:23.040981 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10363 11:50:23.047317 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10364 11:50:23.053830 <6>[ 0.009186] Console: colour dummy device 80x25
10365 11:50:23.064078 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10366 11:50:23.071017 <6>[ 0.024421] pid_max: default: 32768 minimum: 301
10367 11:50:23.074296 <6>[ 0.029293] LSM: Security Framework initializing
10368 11:50:23.080253 <6>[ 0.034230] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 11:50:23.090713 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 11:50:23.097007 <6>[ 0.051501] cblist_init_generic: Setting adjustable number of callback queues.
10371 11:50:23.103494 <6>[ 0.058943] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 11:50:23.113510 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10373 11:50:23.119890 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 11:50:23.123854 <6>[ 0.079150] rcu: Hierarchical SRCU implementation.
10375 11:50:23.129956 <6>[ 0.084166] rcu: Max phase no-delay instances is 1000.
10376 11:50:23.137036 <6>[ 0.091185] EFI services will not be available.
10377 11:50:23.140273 <6>[ 0.096165] smp: Bringing up secondary CPUs ...
10378 11:50:23.148348 <6>[ 0.101211] Detected VIPT I-cache on CPU1
10379 11:50:23.154851 <6>[ 0.101283] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 11:50:23.162159 <6>[ 0.101313] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 11:50:23.165284 <6>[ 0.101657] Detected VIPT I-cache on CPU2
10382 11:50:23.171446 <6>[ 0.101709] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 11:50:23.181229 <6>[ 0.101726] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 11:50:23.184565 <6>[ 0.101988] Detected VIPT I-cache on CPU3
10385 11:50:23.191468 <6>[ 0.102035] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 11:50:23.197830 <6>[ 0.102048] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 11:50:23.201406 <6>[ 0.102353] CPU features: detected: Spectre-v4
10388 11:50:23.207989 <6>[ 0.102360] CPU features: detected: Spectre-BHB
10389 11:50:23.211045 <6>[ 0.102364] Detected PIPT I-cache on CPU4
10390 11:50:23.217771 <6>[ 0.102421] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 11:50:23.224791 <6>[ 0.102437] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 11:50:23.231447 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10393 11:50:23.237861 <6>[ 0.102791] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 11:50:23.244939 <6>[ 0.102807] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 11:50:23.248225 <6>[ 0.103088] Detected PIPT I-cache on CPU6
10396 11:50:23.254121 <6>[ 0.103151] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 11:50:23.261419 <6>[ 0.103167] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 11:50:23.267544 <6>[ 0.103463] Detected PIPT I-cache on CPU7
10399 11:50:23.274524 <6>[ 0.103528] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 11:50:23.280936 <6>[ 0.103544] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 11:50:23.284671 <6>[ 0.103592] smp: Brought up 1 node, 8 CPUs
10402 11:50:23.290828 <6>[ 0.245003] SMP: Total of 8 processors activated.
10403 11:50:23.294448 <6>[ 0.249954] CPU features: detected: 32-bit EL0 Support
10404 11:50:23.304608 <6>[ 0.255317] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 11:50:23.311028 <6>[ 0.264173] CPU features: detected: Common not Private translations
10406 11:50:23.314346 <6>[ 0.270648] CPU features: detected: CRC32 instructions
10407 11:50:23.320702 <6>[ 0.275999] CPU features: detected: RCpc load-acquire (LDAPR)
10408 11:50:23.327849 <6>[ 0.281996] CPU features: detected: LSE atomic instructions
10409 11:50:23.334047 <6>[ 0.287812] CPU features: detected: Privileged Access Never
10410 11:50:23.337820 <6>[ 0.293628] CPU features: detected: RAS Extension Support
10411 11:50:23.363702 <6>[ 0.299236] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 11:50:23.364264 <6>[ 0.306455] CPU: All CPU(s) started at EL2
10413 11:50:23.364636 <6>[ 0.310772] alternatives: applying system-wide alternatives
10414 11:50:23.365906 <6>[ 0.321477] devtmpfs: initialized
10415 11:50:23.378641 <6>[ 0.330410] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 11:50:23.388520 <6>[ 0.340378] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 11:50:23.395005 <6>[ 0.348405] pinctrl core: initialized pinctrl subsystem
10418 11:50:23.398117 <6>[ 0.355074] DMI not present or invalid.
10419 11:50:23.405056 <6>[ 0.359487] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 11:50:23.412035 <6>[ 0.366366] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 11:50:23.421854 <6>[ 0.373952] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 11:50:23.428236 <6>[ 0.382172] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 11:50:23.435154 <6>[ 0.390418] audit: initializing netlink subsys (disabled)
10424 11:50:23.445258 <5>[ 0.396109] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10425 11:50:23.448481 <6>[ 0.396812] thermal_sys: Registered thermal governor 'step_wise'
10426 11:50:23.455170 <6>[ 0.404078] thermal_sys: Registered thermal governor 'power_allocator'
10427 11:50:23.461572 <6>[ 0.410334] cpuidle: using governor menu
10428 11:50:23.464847 <6>[ 0.421299] NET: Registered PF_QIPCRTR protocol family
10429 11:50:23.471660 <6>[ 0.426801] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 11:50:23.478293 <6>[ 0.433906] ASID allocator initialised with 32768 entries
10431 11:50:23.484882 <6>[ 0.440479] Serial: AMBA PL011 UART driver
10432 11:50:23.493483 <4>[ 0.449258] Trying to register duplicate clock ID: 134
10433 11:50:23.549630 <6>[ 0.508768] KASLR enabled
10434 11:50:23.564192 <6>[ 0.516480] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 11:50:23.570574 <6>[ 0.523497] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 11:50:23.576952 <6>[ 0.529990] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 11:50:23.583605 <6>[ 0.536997] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 11:50:23.590664 <6>[ 0.543487] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 11:50:23.597088 <6>[ 0.550494] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 11:50:23.603660 <6>[ 0.556985] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 11:50:23.610135 <6>[ 0.563992] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 11:50:23.613723 <6>[ 0.571496] ACPI: Interpreter disabled.
10443 11:50:23.621860 <6>[ 0.577901] iommu: Default domain type: Translated
10444 11:50:23.628789 <6>[ 0.583017] iommu: DMA domain TLB invalidation policy: strict mode
10445 11:50:23.631813 <5>[ 0.589674] SCSI subsystem initialized
10446 11:50:23.638569 <6>[ 0.593839] usbcore: registered new interface driver usbfs
10447 11:50:23.645509 <6>[ 0.599573] usbcore: registered new interface driver hub
10448 11:50:23.648617 <6>[ 0.605126] usbcore: registered new device driver usb
10449 11:50:23.655443 <6>[ 0.611222] pps_core: LinuxPPS API ver. 1 registered
10450 11:50:23.665439 <6>[ 0.616417] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 11:50:23.668404 <6>[ 0.625770] PTP clock support registered
10452 11:50:23.671844 <6>[ 0.630012] EDAC MC: Ver: 3.0.0
10453 11:50:23.679500 <6>[ 0.635166] FPGA manager framework
10454 11:50:23.685635 <6>[ 0.638845] Advanced Linux Sound Architecture Driver Initialized.
10455 11:50:23.688776 <6>[ 0.645622] vgaarb: loaded
10456 11:50:23.695575 <6>[ 0.648807] clocksource: Switched to clocksource arch_sys_counter
10457 11:50:23.699338 <5>[ 0.655246] VFS: Disk quotas dquot_6.6.0
10458 11:50:23.705330 <6>[ 0.659431] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 11:50:23.708949 <6>[ 0.666621] pnp: PnP ACPI: disabled
10460 11:50:23.717234 <6>[ 0.673302] NET: Registered PF_INET protocol family
10461 11:50:23.723898 <6>[ 0.678906] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 11:50:23.738681 <6>[ 0.691227] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 11:50:23.748356 <6>[ 0.700042] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 11:50:23.754869 <6>[ 0.708015] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 11:50:23.761531 <6>[ 0.716714] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 11:50:23.773971 <6>[ 0.726455] TCP: Hash tables configured (established 65536 bind 65536)
10467 11:50:23.780652 <6>[ 0.733316] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 11:50:23.786793 <6>[ 0.740516] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 11:50:23.793618 <6>[ 0.748217] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 11:50:23.800429 <6>[ 0.754387] RPC: Registered named UNIX socket transport module.
10471 11:50:23.803534 <6>[ 0.760545] RPC: Registered udp transport module.
10472 11:50:23.810582 <6>[ 0.765479] RPC: Registered tcp transport module.
10473 11:50:23.817333 <6>[ 0.770413] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 11:50:23.820339 <6>[ 0.777085] PCI: CLS 0 bytes, default 64
10475 11:50:23.823565 <6>[ 0.781479] Unpacking initramfs...
10476 11:50:23.848323 <6>[ 0.800922] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 11:50:23.858485 <6>[ 0.809581] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 11:50:23.861581 <6>[ 0.818429] kvm [1]: IPA Size Limit: 40 bits
10479 11:50:23.868333 <6>[ 0.822958] kvm [1]: GICv3: no GICV resource entry
10480 11:50:23.871219 <6>[ 0.827980] kvm [1]: disabling GICv2 emulation
10481 11:50:23.878144 <6>[ 0.832673] kvm [1]: GIC system register CPU interface enabled
10482 11:50:23.881205 <6>[ 0.838853] kvm [1]: vgic interrupt IRQ18
10483 11:50:23.887943 <6>[ 0.843207] kvm [1]: VHE mode initialized successfully
10484 11:50:23.894816 <5>[ 0.849620] Initialise system trusted keyrings
10485 11:50:23.901337 <6>[ 0.854447] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 11:50:23.908586 <6>[ 0.864416] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 11:50:23.915338 <5>[ 0.870801] NFS: Registering the id_resolver key type
10488 11:50:23.918467 <5>[ 0.876111] Key type id_resolver registered
10489 11:50:23.925196 <5>[ 0.880527] Key type id_legacy registered
10490 11:50:23.931967 <6>[ 0.884817] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 11:50:23.938179 <6>[ 0.891744] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 11:50:23.945116 <6>[ 0.899470] 9p: Installing v9fs 9p2000 file system support
10493 11:50:23.981776 <5>[ 0.937540] Key type asymmetric registered
10494 11:50:23.984951 <5>[ 0.941889] Asymmetric key parser 'x509' registered
10495 11:50:23.995176 <6>[ 0.947042] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 11:50:23.998634 <6>[ 0.954660] io scheduler mq-deadline registered
10497 11:50:24.001549 <6>[ 0.959426] io scheduler kyber registered
10498 11:50:24.020764 <6>[ 0.976686] EINJ: ACPI disabled.
10499 11:50:24.053231 <4>[ 1.002712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 11:50:24.063589 <4>[ 1.013355] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 11:50:24.078345 <6>[ 1.034226] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 11:50:24.086201 <6>[ 1.042287] printk: console [ttyS0] disabled
10503 11:50:24.114559 <6>[ 1.066932] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 11:50:24.121225 <6>[ 1.076416] printk: console [ttyS0] enabled
10505 11:50:24.124260 <6>[ 1.076416] printk: console [ttyS0] enabled
10506 11:50:24.131099 <6>[ 1.085314] printk: bootconsole [mtk8250] disabled
10507 11:50:24.134097 <6>[ 1.085314] printk: bootconsole [mtk8250] disabled
10508 11:50:24.140624 <6>[ 1.096442] SuperH (H)SCI(F) driver initialized
10509 11:50:24.143796 <6>[ 1.101721] msm_serial: driver initialized
10510 11:50:24.158096 <6>[ 1.110669] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10511 11:50:24.167975 <6>[ 1.119215] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10512 11:50:24.174634 <6>[ 1.127756] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10513 11:50:24.184620 <6>[ 1.136386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10514 11:50:24.191437 <6>[ 1.145094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10515 11:50:24.201495 <6>[ 1.153807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10516 11:50:24.211342 <6>[ 1.162353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10517 11:50:24.217503 <6>[ 1.171169] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10518 11:50:24.227455 <6>[ 1.179712] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10519 11:50:24.239764 <6>[ 1.195346] loop: module loaded
10520 11:50:24.245994 <6>[ 1.201368] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10521 11:50:24.269354 <4>[ 1.225029] mtk-pmic-keys: Failed to locate of_node [id: -1]
10522 11:50:24.276072 <6>[ 1.231915] megasas: 07.719.03.00-rc1
10523 11:50:24.285470 <6>[ 1.241468] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10524 11:50:24.292326 <6>[ 1.248201] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 11:50:24.309341 <6>[ 1.264996] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 11:50:24.366042 <6>[ 1.315330] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10527 11:50:24.563975 <6>[ 1.519565] Freeing initrd memory: 17372K
10528 11:50:24.574429 <6>[ 1.530085] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10529 11:50:24.585396 <6>[ 1.541046] tun: Universal TUN/TAP device driver, 1.6
10530 11:50:24.588655 <6>[ 1.547101] thunder_xcv, ver 1.0
10531 11:50:24.592121 <6>[ 1.550601] thunder_bgx, ver 1.0
10532 11:50:24.595777 <6>[ 1.554097] nicpf, ver 1.0
10533 11:50:24.606068 <6>[ 1.558102] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10534 11:50:24.609618 <6>[ 1.565578] hns3: Copyright (c) 2017 Huawei Corporation.
10535 11:50:24.615645 <6>[ 1.571170] hclge is initializing
10536 11:50:24.619608 <6>[ 1.574750] e1000: Intel(R) PRO/1000 Network Driver
10537 11:50:24.625881 <6>[ 1.579879] e1000: Copyright (c) 1999-2006 Intel Corporation.
10538 11:50:24.629458 <6>[ 1.585890] e1000e: Intel(R) PRO/1000 Network Driver
10539 11:50:24.635429 <6>[ 1.591106] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10540 11:50:24.642395 <6>[ 1.597291] igb: Intel(R) Gigabit Ethernet Network Driver
10541 11:50:24.649384 <6>[ 1.602942] igb: Copyright (c) 2007-2014 Intel Corporation.
10542 11:50:24.655905 <6>[ 1.608781] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10543 11:50:24.662555 <6>[ 1.615300] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10544 11:50:24.666248 <6>[ 1.621771] sky2: driver version 1.30
10545 11:50:24.672510 <6>[ 1.626758] VFIO - User Level meta-driver version: 0.3
10546 11:50:24.679787 <6>[ 1.634986] usbcore: registered new interface driver usb-storage
10547 11:50:24.685997 <6>[ 1.641432] usbcore: registered new device driver onboard-usb-hub
10548 11:50:24.695265 <6>[ 1.650569] mt6397-rtc mt6359-rtc: registered as rtc0
10549 11:50:24.704962 <6>[ 1.656034] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:48:13 UTC (1700826493)
10550 11:50:24.708483 <6>[ 1.665598] i2c_dev: i2c /dev entries driver
10551 11:50:24.725486 <6>[ 1.677287] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10552 11:50:24.744852 <6>[ 1.700261] cpu cpu0: EM: created perf domain
10553 11:50:24.748317 <6>[ 1.705202] cpu cpu4: EM: created perf domain
10554 11:50:24.755672 <6>[ 1.710794] sdhci: Secure Digital Host Controller Interface driver
10555 11:50:24.761766 <6>[ 1.717226] sdhci: Copyright(c) Pierre Ossman
10556 11:50:24.769136 <6>[ 1.722178] Synopsys Designware Multimedia Card Interface Driver
10557 11:50:24.775480 <6>[ 1.728819] sdhci-pltfm: SDHCI platform and OF driver helper
10558 11:50:24.778554 <6>[ 1.728865] mmc0: CQHCI version 5.10
10559 11:50:24.785492 <6>[ 1.739171] ledtrig-cpu: registered to indicate activity on CPUs
10560 11:50:24.791597 <6>[ 1.746217] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10561 11:50:24.798614 <6>[ 1.753272] usbcore: registered new interface driver usbhid
10562 11:50:24.801875 <6>[ 1.759098] usbhid: USB HID core driver
10563 11:50:24.808909 <6>[ 1.763293] spi_master spi0: will run message pump with realtime priority
10564 11:50:24.858664 <6>[ 1.807649] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10565 11:50:24.878455 <6>[ 1.823286] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10566 11:50:24.881440 <6>[ 1.836970] mmc0: Command Queue Engine enabled
10567 11:50:24.888156 <6>[ 1.838540] cros-ec-spi spi0.0: Chrome EC device registered
10568 11:50:24.891861 <6>[ 1.841726] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10569 11:50:24.899886 <6>[ 1.854941] mmcblk0: mmc0:0001 DA4128 116 GiB
10570 11:50:24.910908 <6>[ 1.862914] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10571 11:50:24.917369 <6>[ 1.867118] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10572 11:50:24.923886 <6>[ 1.873178] NET: Registered PF_PACKET protocol family
10573 11:50:24.927270 <6>[ 1.879122] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10574 11:50:24.933930 <6>[ 1.883510] 9pnet: Installing 9P2000 support
10575 11:50:24.937104 <6>[ 1.889490] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10576 11:50:24.943873 <5>[ 1.893237] Key type dns_resolver registered
10577 11:50:24.947584 <6>[ 1.899009] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10578 11:50:24.953727 <6>[ 1.903413] registered taskstats version 1
10579 11:50:24.957427 <5>[ 1.913859] Loading compiled-in X.509 certificates
10580 11:50:24.987331 <4>[ 1.936118] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 11:50:24.997325 <4>[ 1.946876] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 11:50:25.004101 <3>[ 1.957439] debugfs: File 'uA_load' in directory '/' already present!
10583 11:50:25.011310 <3>[ 1.964153] debugfs: File 'min_uV' in directory '/' already present!
10584 11:50:25.017331 <3>[ 1.970814] debugfs: File 'max_uV' in directory '/' already present!
10585 11:50:25.024034 <3>[ 1.977429] debugfs: File 'constraint_flags' in directory '/' already present!
10586 11:50:25.034755 <3>[ 1.987098] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 11:50:25.044887 <6>[ 2.000074] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 11:50:25.051271 <6>[ 2.006919] xhci-mtk 11200000.usb: xHCI Host Controller
10589 11:50:25.058114 <6>[ 2.012410] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 11:50:25.067775 <6>[ 2.020282] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 11:50:25.074560 <6>[ 2.029702] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 11:50:25.081325 <6>[ 2.035764] xhci-mtk 11200000.usb: xHCI Host Controller
10593 11:50:25.088137 <6>[ 2.041240] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 11:50:25.094680 <6>[ 2.048886] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 11:50:25.101421 <6>[ 2.056517] hub 1-0:1.0: USB hub found
10596 11:50:25.105049 <6>[ 2.060539] hub 1-0:1.0: 1 port detected
10597 11:50:25.112051 <6>[ 2.064803] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 11:50:25.117953 <6>[ 2.073344] hub 2-0:1.0: USB hub found
10599 11:50:25.121392 <6>[ 2.077362] hub 2-0:1.0: 1 port detected
10600 11:50:25.129722 <6>[ 2.085007] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 11:50:25.139349 <6>[ 2.091449] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 11:50:25.145728 <6>[ 2.099469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 11:50:25.156056 <4>[ 2.107370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 11:50:25.162643 <6>[ 2.116900] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 11:50:25.172587 <6>[ 2.124980] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 11:50:25.179572 <6>[ 2.133004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 11:50:25.189475 <6>[ 2.140948] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 11:50:25.196165 <6>[ 2.148772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 11:50:25.206247 <6>[ 2.156599] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 11:50:25.216514 <6>[ 2.166950] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 11:50:25.222932 <6>[ 2.175315] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 11:50:25.233527 <6>[ 2.183660] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 11:50:25.239172 <6>[ 2.191999] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 11:50:25.249364 <6>[ 2.200337] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 11:50:25.256408 <6>[ 2.208676] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 11:50:25.266464 <6>[ 2.217015] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 11:50:25.272343 <6>[ 2.225354] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 11:50:25.282607 <6>[ 2.233692] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 11:50:25.289246 <6>[ 2.242031] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 11:50:25.299419 <6>[ 2.250373] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 11:50:25.306251 <6>[ 2.258712] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 11:50:25.316305 <6>[ 2.267050] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 11:50:25.322566 <6>[ 2.275389] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 11:50:25.332638 <6>[ 2.283727] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 11:50:25.339201 <6>[ 2.292551] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 11:50:25.346056 <6>[ 2.299813] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 11:50:25.353197 <6>[ 2.306736] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 11:50:25.359818 <6>[ 2.313569] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 11:50:25.366263 <6>[ 2.320531] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 11:50:25.376392 <6>[ 2.327403] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 11:50:25.386047 <6>[ 2.336532] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 11:50:25.392481 <6>[ 2.345650] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 11:50:25.402467 <6>[ 2.354944] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 11:50:25.412775 <6>[ 2.364414] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 11:50:25.422608 <6>[ 2.373883] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 11:50:25.432439 <6>[ 2.383003] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 11:50:25.442508 <6>[ 2.392470] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 11:50:25.449284 <6>[ 2.401588] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 11:50:25.458870 <6>[ 2.410893] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 11:50:25.468879 <6>[ 2.421054] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 11:50:25.480894 <6>[ 2.433033] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 11:50:25.487080 <6>[ 2.442764] Trying to probe devices needed for running init ...
10643 11:50:25.537266 <6>[ 2.489080] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10644 11:50:25.691114 <6>[ 2.646572] hub 1-1:1.0: USB hub found
10645 11:50:25.693960 <6>[ 2.651111] hub 1-1:1.0: 4 ports detected
10646 11:50:25.703784 <6>[ 2.659239] hub 1-1:1.0: USB hub found
10647 11:50:25.706911 <6>[ 2.663583] hub 1-1:1.0: 4 ports detected
10648 11:50:25.817460 <6>[ 2.769425] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10649 11:50:25.843653 <6>[ 2.798860] hub 2-1:1.0: USB hub found
10650 11:50:25.846885 <6>[ 2.803355] hub 2-1:1.0: 3 ports detected
10651 11:50:25.856030 <6>[ 2.811502] hub 2-1:1.0: USB hub found
10652 11:50:25.858862 <6>[ 2.815959] hub 2-1:1.0: 3 ports detected
10653 11:50:26.033032 <6>[ 2.985062] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 11:50:26.165680 <6>[ 3.120926] hub 1-1.4:1.0: USB hub found
10655 11:50:26.168274 <6>[ 3.125608] hub 1-1.4:1.0: 2 ports detected
10656 11:50:26.177780 <6>[ 3.133474] hub 1-1.4:1.0: USB hub found
10657 11:50:26.181226 <6>[ 3.137998] hub 1-1.4:1.0: 2 ports detected
10658 11:50:26.248427 <6>[ 3.201210] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10659 11:50:26.476348 <6>[ 3.429117] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10660 11:50:26.668396 <6>[ 3.621091] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10661 11:50:37.774271 <6>[ 14.734082] ALSA device list:
10662 11:50:37.780812 <6>[ 14.737373] No soundcards found.
10663 11:50:37.788742 <6>[ 14.745330] Freeing unused kernel memory: 8384K
10664 11:50:37.791575 <6>[ 14.750314] Run /init as init process
10665 11:50:37.803043 Loading, please wait...
10666 11:50:37.823361 Starting version 247.3-7+deb11u2
10667 11:50:38.051612 <6>[ 15.005266] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 11:50:38.058240 <6>[ 15.013632] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10669 11:50:38.068649 <4>[ 15.022066] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10670 11:50:38.075647 <6>[ 15.023203] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10671 11:50:38.081752 <6>[ 15.025072] remoteproc remoteproc0: scp is available
10672 11:50:38.085627 <6>[ 15.025147] remoteproc remoteproc0: powering up scp
10673 11:50:38.095277 <6>[ 15.025153] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10674 11:50:38.101735 <6>[ 15.025176] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10675 11:50:38.108529 <4>[ 15.044208] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10676 11:50:38.118385 <6>[ 15.048669] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10677 11:50:38.121447 <6>[ 15.059079] mc: Linux media interface: v0.10
10678 11:50:38.128271 <3>[ 15.060285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 11:50:38.138365 <3>[ 15.060301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 11:50:38.144893 <3>[ 15.060310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 11:50:38.154518 <3>[ 15.065454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 11:50:38.161358 <6>[ 15.076070] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10683 11:50:38.168587 <3>[ 15.078623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 11:50:38.177975 <3>[ 15.078631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 11:50:38.185172 <3>[ 15.078636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 11:50:38.194802 <3>[ 15.078641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 11:50:38.201572 <3>[ 15.080021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:50:38.211901 <4>[ 15.099144] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10689 11:50:38.215343 <4>[ 15.099144] Fallback method does not support PEC.
10690 11:50:38.222290 <3>[ 15.099965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:50:38.228677 <6>[ 15.103069] usbcore: registered new interface driver r8152
10692 11:50:38.238837 <3>[ 15.124649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10693 11:50:38.245304 <3>[ 15.131529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 11:50:38.252276 <6>[ 15.150550] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10695 11:50:38.262025 <6>[ 15.150582] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10696 11:50:38.268431 <6>[ 15.150590] remoteproc remoteproc0: remote processor scp is now up
10697 11:50:38.275552 <3>[ 15.155650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 11:50:38.285222 <3>[ 15.155717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 11:50:38.295137 <6>[ 15.168255] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10700 11:50:38.301568 <3>[ 15.172805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10701 11:50:38.311196 <3>[ 15.177382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 11:50:38.317997 <3>[ 15.177385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 11:50:38.328182 <3>[ 15.177394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 11:50:38.334453 <6>[ 15.189107] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10705 11:50:38.341209 <3>[ 15.191199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 11:50:38.351211 <3>[ 15.191248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 11:50:38.358051 <6>[ 15.194195] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10708 11:50:38.361140 <6>[ 15.194202] pci_bus 0000:00: root bus resource [bus 00-ff]
10709 11:50:38.368240 <6>[ 15.194210] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10710 11:50:38.378331 <6>[ 15.194214] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10711 11:50:38.384835 <6>[ 15.194252] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10712 11:50:38.394326 <6>[ 15.194277] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10713 11:50:38.397933 <6>[ 15.194379] pci 0000:00:00.0: supports D1 D2
10714 11:50:38.404700 <6>[ 15.194383] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10715 11:50:38.414262 <6>[ 15.196079] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10716 11:50:38.417733 <6>[ 15.196181] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10717 11:50:38.427458 <6>[ 15.196211] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10718 11:50:38.434034 <6>[ 15.196230] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10719 11:50:38.441087 <6>[ 15.196249] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10720 11:50:38.447811 <6>[ 15.196362] pci 0000:01:00.0: supports D1 D2
10721 11:50:38.454524 <6>[ 15.196365] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 11:50:38.464386 <6>[ 15.203144] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10723 11:50:38.471161 <6>[ 15.209101] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10724 11:50:38.477826 <6>[ 15.215561] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10725 11:50:38.487223 <4>[ 15.219826] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10726 11:50:38.497410 <4>[ 15.219835] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10727 11:50:38.504129 <6>[ 15.223635] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10728 11:50:38.510963 <6>[ 15.223640] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10729 11:50:38.520610 <6>[ 15.223648] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10730 11:50:38.526907 <6>[ 15.223661] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10731 11:50:38.537172 <6>[ 15.223674] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10732 11:50:38.544098 <6>[ 15.239763] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10733 11:50:38.550266 <6>[ 15.246990] pci 0000:00:00.0: PCI bridge to [bus 01]
10734 11:50:38.553676 <6>[ 15.247122] videodev: Linux video capture interface: v2.00
10735 11:50:38.560004 <6>[ 15.256106] usbcore: registered new interface driver cdc_ether
10736 11:50:38.570713 <6>[ 15.264409] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10737 11:50:38.573759 <6>[ 15.273554] Bluetooth: Core ver 2.22
10738 11:50:38.580751 <6>[ 15.280807] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10739 11:50:38.586941 <6>[ 15.281217] usbcore: registered new interface driver r8153_ecm
10740 11:50:38.590339 <6>[ 15.288726] NET: Registered PF_BLUETOOTH protocol family
10741 11:50:38.600203 <6>[ 15.288783] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10742 11:50:38.603902 <6>[ 15.295914] r8152 2-1.3:1.0 eth0: v1.12.13
10743 11:50:38.610172 <6>[ 15.296905] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10744 11:50:38.617405 <6>[ 15.297221] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10745 11:50:38.623561 <6>[ 15.303848] Bluetooth: HCI device and connection manager initialized
10746 11:50:38.627031 <6>[ 15.303865] Bluetooth: HCI socket layer initialized
10747 11:50:38.633256 <6>[ 15.303871] Bluetooth: L2CAP socket layer initialized
10748 11:50:38.639992 <5>[ 15.314528] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10749 11:50:38.647043 <6>[ 15.318822] Bluetooth: SCO socket layer initialized
10750 11:50:38.653488 <6>[ 15.320720] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10751 11:50:38.659969 <6>[ 15.320732] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10752 11:50:38.666967 <5>[ 15.334265] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10753 11:50:38.679558 <6>[ 15.343493] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10754 11:50:38.682890 <6>[ 15.357367] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10755 11:50:38.689380 <6>[ 15.360277] usbcore: registered new interface driver uvcvideo
10756 11:50:38.696367 <6>[ 15.376080] usbcore: registered new interface driver btusb
10757 11:50:38.706135 <4>[ 15.376696] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10758 11:50:38.712864 <3>[ 15.376706] Bluetooth: hci0: Failed to load firmware file (-2)
10759 11:50:38.719401 <3>[ 15.376709] Bluetooth: hci0: Failed to set up firmware (-2)
10760 11:50:38.729499 <4>[ 15.376713] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10761 11:50:38.739545 <4>[ 15.693288] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 11:50:38.746082 <6>[ 15.702169] cfg80211: failed to load regulatory.db
10763 11:50:38.782369 <6>[ 15.736337] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 11:50:38.788785 <6>[ 15.743832] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 11:50:38.813386 <6>[ 15.770462] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 11:50:38.917720 <4>[ 15.868071] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 11:50:38.920643 Begin: Loading essential drivers ... done.
10768 11:50:38.927300 Begin: Running /scripts/init-premount ... done.
10769 11:50:38.934739 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10770 11:50:38.944428 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10771 11:50:38.947557 Device /sys/class/net/enx00e04c787aaa found
10772 11:50:38.948015 done.
10773 11:50:39.007470 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10774 11:50:39.036819 <4>[ 15.987369] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 11:50:39.151796 <4>[ 16.102372] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 11:50:39.267917 <4>[ 16.218197] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:50:39.383473 <4>[ 16.334124] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 11:50:39.499631 <4>[ 16.450027] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 11:50:39.615123 <4>[ 16.565913] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 11:50:39.731419 <4>[ 16.681903] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 11:50:39.847475 <4>[ 16.797833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 11:50:39.963084 <4>[ 16.913835] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 11:50:40.001265 <6>[ 16.957954] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10784 11:50:40.070462 <3>[ 17.027664] mt7921e 0000:01:00.0: hardware init failed
10785 11:50:40.198960 IP-Config: no response after 2 secs - giving up
10786 11:50:40.235814 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10787 11:50:40.242634 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10788 11:50:40.249884 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10789 11:50:40.256443 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10790 11:50:40.262571 host : mt8192-asurada-spherion-r0-cbg-0
10791 11:50:40.269627 domain : lava-rack
10792 11:50:40.272493 rootserver: 192.168.201.1 rootpath:
10793 11:50:40.276147 filename :
10794 11:50:40.399642 done.
10795 11:50:40.406286 Begin: Running /scripts/nfs-bottom ... done.
10796 11:50:40.423699 Begin: Running /scripts/init-bottom ... done.
10797 11:50:41.621041 <6>[ 18.579108] NET: Registered PF_INET6 protocol family
10798 11:50:41.628724 <6>[ 18.586384] Segment Routing with IPv6
10799 11:50:41.631834 <6>[ 18.590416] In-situ OAM (IOAM) with IPv6
10800 11:50:41.755931 <30>[ 18.693532] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10801 11:50:41.758830 <30>[ 18.717956] systemd[1]: Detected architecture arm64.
10802 11:50:41.780394
10803 11:50:41.783458 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10804 11:50:41.783630
10805 11:50:41.801741 <30>[ 18.759397] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10806 11:50:42.548305 <30>[ 19.503060] systemd[1]: Queued start job for default target Graphical Interface.
10807 11:50:42.577498 <30>[ 19.535421] systemd[1]: Created slice system-getty.slice.
10808 11:50:42.583826 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10809 11:50:42.600202 <30>[ 19.558478] systemd[1]: Created slice system-modprobe.slice.
10810 11:50:42.606890 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10811 11:50:42.624219 <30>[ 19.582303] systemd[1]: Created slice system-serial\x2dgetty.slice.
10812 11:50:42.634132 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10813 11:50:42.648253 <30>[ 19.606128] systemd[1]: Created slice User and Session Slice.
10814 11:50:42.654473 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10815 11:50:42.675404 <30>[ 19.629947] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10816 11:50:42.685098 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10817 11:50:42.702952 <30>[ 19.657855] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10818 11:50:42.709718 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10819 11:50:42.733684 <30>[ 19.685227] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10820 11:50:42.740519 <30>[ 19.697390] systemd[1]: Reached target Local Encrypted Volumes.
10821 11:50:42.746738 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10822 11:50:42.763595 <30>[ 19.721577] systemd[1]: Reached target Paths.
10823 11:50:42.766607 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10824 11:50:42.783309 <30>[ 19.741095] systemd[1]: Reached target Remote File Systems.
10825 11:50:42.789512 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10826 11:50:42.807178 <30>[ 19.765450] systemd[1]: Reached target Slices.
10827 11:50:42.813834 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10828 11:50:42.827040 <30>[ 19.785135] systemd[1]: Reached target Swap.
10829 11:50:42.830452 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10830 11:50:42.850896 <30>[ 19.805588] systemd[1]: Listening on initctl Compatibility Named Pipe.
10831 11:50:42.857417 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10832 11:50:42.864315 <30>[ 19.821569] systemd[1]: Listening on Journal Audit Socket.
10833 11:50:42.870671 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10834 11:50:42.888056 <30>[ 19.846274] systemd[1]: Listening on Journal Socket (/dev/log).
10835 11:50:42.894701 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10836 11:50:42.912231 <30>[ 19.870277] systemd[1]: Listening on Journal Socket.
10837 11:50:42.918798 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10838 11:50:42.935597 <30>[ 19.890650] systemd[1]: Listening on Network Service Netlink Socket.
10839 11:50:42.942102 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10840 11:50:42.957354 <30>[ 19.915498] systemd[1]: Listening on udev Control Socket.
10841 11:50:42.964557 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10842 11:50:42.979079 <30>[ 19.937535] systemd[1]: Listening on udev Kernel Socket.
10843 11:50:42.985810 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10844 11:50:43.039306 <30>[ 19.997330] systemd[1]: Mounting Huge Pages File System...
10845 11:50:43.046008 Mounting [0;1;39mHuge Pages File System[0m...
10846 11:50:43.063472 <30>[ 20.021429] systemd[1]: Mounting POSIX Message Queue File System...
10847 11:50:43.070326 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10848 11:50:43.123262 <30>[ 20.081413] systemd[1]: Mounting Kernel Debug File System...
10849 11:50:43.130074 Mounting [0;1;39mKernel Debug File System[0m...
10850 11:50:43.146533 <30>[ 20.101598] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10851 11:50:43.160067 <30>[ 20.114937] systemd[1]: Starting Create list of static device nodes for the current kernel...
10852 11:50:43.166821 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10853 11:50:43.187367 <30>[ 20.145615] systemd[1]: Starting Load Kernel Module configfs...
10854 11:50:43.193856 Starting [0;1;39mLoad Kernel Module configfs[0m...
10855 11:50:43.211537 <30>[ 20.169693] systemd[1]: Starting Load Kernel Module drm...
10856 11:50:43.218227 Starting [0;1;39mLoad Kernel Module drm[0m...
10857 11:50:43.235600 <30>[ 20.193971] systemd[1]: Starting Load Kernel Module fuse...
10858 11:50:43.242845 Starting [0;1;39mLoad Kernel Module fuse[0m...
10859 11:50:43.275156 <30>[ 20.230158] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10860 11:50:43.282232 <6>[ 20.230888] fuse: init (API version 7.37)
10861 11:50:43.323323 <30>[ 20.281565] systemd[1]: Starting Journal Service...
10862 11:50:43.326502 Starting [0;1;39mJournal Service[0m...
10863 11:50:43.349078 <30>[ 20.307180] systemd[1]: Starting Load Kernel Modules...
10864 11:50:43.355677 Starting [0;1;39mLoad Kernel Modules[0m...
10865 11:50:43.380013 <30>[ 20.334776] systemd[1]: Starting Remount Root and Kernel File Systems...
10866 11:50:43.386800 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10867 11:50:43.405096 <30>[ 20.363093] systemd[1]: Starting Coldplug All udev Devices...
10868 11:50:43.411701 Starting [0;1;39mColdplug All udev Devices[0m...
10869 11:50:43.436300 <30>[ 20.393931] systemd[1]: Mounted Huge Pages File System.
10870 11:50:43.450477 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.<3>[ 20.404304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 11:50:43.450606
10872 11:50:43.458657 <30>[ 20.416565] systemd[1]: Mounted POSIX Message Queue File System.
10873 11:50:43.465437 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10874 11:50:43.482822 <3>[ 20.437517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 11:50:43.489509 <30>[ 20.447197] systemd[1]: Mounted Kernel Debug File System.
10876 11:50:43.496144 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10877 11:50:43.516148 <30>[ 20.470802] systemd[1]: Finished Create list of static device nodes for the current kernel.
10878 11:50:43.523552 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10879 11:50:43.533753 <3>[ 20.488586] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 11:50:43.540479 <30>[ 20.498513] systemd[1]: modprobe@configfs.service: Succeeded.
10881 11:50:43.547756 <30>[ 20.505825] systemd[1]: Finished Load Kernel Module configfs.
10882 11:50:43.554697 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10883 11:50:43.567314 <3>[ 20.522072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 11:50:43.573833 <30>[ 20.531871] systemd[1]: modprobe@drm.service: Succeeded.
10885 11:50:43.580435 <30>[ 20.538235] systemd[1]: Finished Load Kernel Module drm.
10886 11:50:43.587284 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10887 11:50:43.598373 <3>[ 20.553446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 11:50:43.605677 <30>[ 20.563896] systemd[1]: modprobe@fuse.service: Succeeded.
10889 11:50:43.612254 <30>[ 20.570623] systemd[1]: Finished Load Kernel Module fuse.
10890 11:50:43.620203 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10891 11:50:43.630082 <3>[ 20.584107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 11:50:43.636716 <30>[ 20.594784] systemd[1]: Finished Load Kernel Modules.
10893 11:50:43.643491 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10894 11:50:43.659069 <3>[ 20.613635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 11:50:43.665324 <30>[ 20.615310] systemd[1]: Finished Remount Root and Kernel File Systems.
10896 11:50:43.671864 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10897 11:50:43.691072 <3>[ 20.645498] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 11:50:43.723376 <3>[ 20.678022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 11:50:43.736402 <30>[ 20.694629] systemd[1]: Mounting FUSE Control File System...
10900 11:50:43.743176 Mounting [0;1;39mFUSE Control File System[0m...
10901 11:50:43.754411 <3>[ 20.709089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 11:50:43.766512 <30>[ 20.721032] systemd[1]: Mounting Kernel Configuration File System...
10903 11:50:43.769875 Mounting [0;1;39mKernel Configuration File System[0m...
10904 11:50:43.795409 <30>[ 20.749359] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10905 11:50:43.804785 <30>[ 20.758551] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10906 11:50:43.815327 <30>[ 20.773669] systemd[1]: Starting Load/Save Random Seed...
10907 11:50:43.822158 Starting [0;1;39mLoad/Save Random Seed[0m...
10908 11:50:43.840870 <30>[ 20.798763] systemd[1]: Starting Apply Kernel Variables...
10909 11:50:43.847407 Starting [0;1;39mApply Kernel Variables[0m...
10910 11:50:43.869412 <30>[ 20.827397] systemd[1]: Starting Create System Users...
10911 11:50:43.876540 Starting [0;1;39mCreate System Users[0m...
10912 11:50:43.893839 <4>[ 20.841684] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10913 11:50:43.903813 <3>[ 20.857486] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10914 11:50:43.906680 <30>[ 20.860393] systemd[1]: Started Journal Service.
10915 11:50:43.913455 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10916 11:50:43.933721 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10917 11:50:43.947128 See 'systemctl status systemd-udev-trigger.service' for details.
10918 11:50:43.964184 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10919 11:50:43.979954 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10920 11:50:43.996721 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10921 11:50:44.012836 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10922 11:50:44.028635 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10923 11:50:44.076409 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10924 11:50:44.093334 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10925 11:50:44.121326 <46>[ 21.076218] systemd-journald[298]: Received client request to flush runtime journal.
10926 11:50:44.155519 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10927 11:50:44.171510 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10928 11:50:44.187199 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10929 11:50:44.236067 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10930 11:50:45.514171 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10931 11:50:45.555882 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10932 11:50:45.575123 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10933 11:50:45.647857 Starting [0;1;39mNetwork Service[0m...
10934 11:50:45.964379 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10935 11:50:45.984709 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10936 11:50:46.044240 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10937 11:50:46.291170 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10938 11:50:46.307108 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10939 11:50:46.326947 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10940 11:50:46.372087 Starting [0;1;39mNetwork Time Synchronization[0m...
10941 11:50:46.391819 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10942 11:50:46.408528 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10943 11:50:46.428594 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10944 11:50:46.503507 Starting [0;1;39mNetwork Name Resolution[0m...
10945 11:50:46.522407 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10946 11:50:46.539420 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10947 11:50:46.556361 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10948 11:50:46.575619 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10949 11:50:46.595681 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10950 11:50:46.620060 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10951 11:50:46.639890 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10952 11:50:47.317507 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10953 11:50:47.340476 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10954 11:50:47.660405 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10955 11:50:47.690502 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10956 11:50:47.710088 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10957 11:50:47.722340 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10958 11:50:47.748699 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10959 11:50:47.762302 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10960 11:50:47.782228 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10961 11:50:47.847554 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10962 11:50:48.006984 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10963 11:50:48.143088 Starting [0;1;39mUser Login Management[0m...
10964 11:50:48.359883 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10965 11:50:48.374884 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10966 11:50:48.393781 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10967 11:50:48.455596 Starting [0;1;39mPermit User Sessions[0m...
10968 11:50:48.479939 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10969 11:50:48.502519 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10970 11:50:48.520248 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10971 11:50:48.568313 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10972 11:50:48.588854 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10973 11:50:48.607812 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10974 11:50:48.622528 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10975 11:50:48.639252 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10976 11:50:48.695624 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10977 11:50:48.728709 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10978 11:50:48.767401
10979 11:50:48.767530
10980 11:50:48.770272 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10981 11:50:48.770353
10982 11:50:48.773573 debian-bullseye-arm64 login: root (automatic login)
10983 11:50:48.773689
10984 11:50:48.773782
10985 11:50:49.054003 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
10986 11:50:49.054226
10987 11:50:49.060416 The programs included with the Debian GNU/Linux system are free software;
10988 11:50:49.066750 the exact distribution terms for each program are described in the
10989 11:50:49.069884 individual files in /usr/share/doc/*/copyright.
10990 11:50:49.069966
10991 11:50:49.076826 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10992 11:50:49.079850 permitted by applicable law.
10993 11:50:49.137900 Matched prompt #10: / #
10995 11:50:49.138181 Setting prompt string to ['/ #']
10996 11:50:49.138278 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10998 11:50:49.138473 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10999 11:50:49.138562 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11000 11:50:49.138630 Setting prompt string to ['/ #']
11001 11:50:49.138691 Forcing a shell prompt, looking for ['/ #']
11003 11:50:49.188913 / #
11004 11:50:49.189061 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11005 11:50:49.189141 Waiting using forced prompt support (timeout 00:02:30)
11006 11:50:49.194157
11007 11:50:49.194446 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 11:50:49.194540 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11010 11:50:49.294876 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m'
11011 11:50:49.300642 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074027/extract-nfsrootfs-4u6xys6m'
11013 11:50:49.401205 / # export NFS_SERVER_IP='192.168.201.1'
11014 11:50:49.406266 export NFS_SERVER_IP='192.168.201.1'
11015 11:50:49.406557 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11016 11:50:49.406655 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11017 11:50:49.406740 end: 2 depthcharge-action (duration 00:01:24) [common]
11018 11:50:49.406830 start: 3 lava-test-retry (timeout 00:30:00) [common]
11019 11:50:49.406914 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11020 11:50:49.406990 Using namespace: common
11022 11:50:49.507349 / # #
11023 11:50:49.507527 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11024 11:50:49.513409 #
11025 11:50:49.513686 Using /lava-12074027
11027 11:50:49.614049 / # export SHELL=/bin/sh
11028 11:50:49.619512 export SHELL=/bin/sh
11030 11:50:49.720071 / # . /lava-12074027/environment
11031 11:50:49.725738 . /lava-12074027/environment
11033 11:50:49.831273 / # /lava-12074027/bin/lava-test-runner /lava-12074027/0
11034 11:50:49.831444 Test shell timeout: 10s (minimum of the action and connection timeout)
11035 11:50:49.836980 /lava-12074027/bin/lava-test-runner /lava-12074027/0
11036 11:50:50.050675 + export TESTRUN_ID=0_lc-compliance
11037 11:50:50.056638 + cd /lava-12074027/0/tests/0_lc-compliance
11038 11:50:50.056737 + cat uuid
11039 11:50:50.061219 + UUID=12074027_1.6.2.3.1
11040 11:50:50.061305 + set +x
11041 11:50:50.068024 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12074027_1.6.2.3.1>
11042 11:50:50.068290 Received signal: <STARTRUN> 0_lc-compliance 12074027_1.6.2.3.1
11043 11:50:50.068373 Starting test lava.0_lc-compliance (12074027_1.6.2.3.1)
11044 11:50:50.068483 Skipping test definition patterns.
11045 11:50:50.071235 + /usr/bin/lc-compliance-parser.sh
11046 11:50:51.253819 [0:00:28.092975001] [407] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11047 11:50:51.257125 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11048 11:50:51.271978 [0:00:28.111841385] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11049 11:50:51.316756 [==========] Running 120 tests from 1 test suite.
11050 11:50:51.327201 [0:00:28.168820924] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11051 11:50:51.370561 [----------] Global test environment set-up.
11052 11:50:51.384386 [0:00:28.223954539] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11053 11:50:51.427127 [----------] 120 tests from CaptureTests/SingleStream
11054 11:50:51.441290 [0:00:28.280552847] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11055 11:50:51.480963 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11056 11:50:51.522357 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11057 11:50:51.522660 Received signal: <TESTSET> START CaptureTests/SingleStream
11058 11:50:51.522748 Starting test_set CaptureTests/SingleStream
11059 11:50:51.525845 Camera needs 4 requests, can't test only 1
11060 11:50:51.582723 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11061 11:50:51.639542
11062 11:50:51.704572 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (57 ms)
11063 11:50:51.784893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11064 11:50:51.785216 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11066 11:50:51.800786 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11067 11:50:51.836327 Camera needs 4 requests, can't test only 2
11068 11:50:51.903227 [0:00:28.742617770] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11069 11:50:51.911358 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11070 11:50:51.966684
11071 11:50:52.028223 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (55 ms)
11072 11:50:52.087028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11073 11:50:52.087309 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11075 11:50:52.100128 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11076 11:50:52.138613 Camera needs 4 requests, can't test only 3
11077 11:50:52.194057 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11078 11:50:52.242831
11079 11:50:52.309117 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (56 ms)
11080 11:50:52.368372 [0:00:29.207985385] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11081 11:50:52.385014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11082 11:50:52.385291 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11084 11:50:52.396137 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11085 11:50:52.435273 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (463 ms)
11086 11:50:52.494897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11087 11:50:52.495207 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11089 11:50:52.505491 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11090 11:50:52.542157 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (465 ms)
11091 11:50:52.606958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11092 11:50:52.607270 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11094 11:50:52.618512 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11095 11:50:53.057902 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (698 ms)
11096 11:50:53.067886 [0:00:29.906561770] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 11:50:53.133795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11098 11:50:53.134118 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11100 11:50:53.148431 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11101 11:50:53.955703 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (898 ms)
11102 11:50:53.965744 [0:00:30.804774924] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 11:50:54.036832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11104 11:50:54.037159 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11106 11:50:54.049238 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11107 11:50:55.354375 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1398 ms)
11108 11:50:55.364295 [0:00:32.202881385] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 11:50:55.437131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11110 11:50:55.437501 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11112 11:50:55.453017 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11113 11:50:57.449479 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2096 ms)
11114 11:50:57.459491 [0:00:34.298558232] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 11:50:57.531427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11116 11:50:57.531749 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11118 11:50:57.545563 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11119 11:51:00.711202 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3262 ms)
11120 11:51:00.720961 [0:00:37.560492924] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 11:51:00.774956 [0:00:37.615610616] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11122 11:51:00.795373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11123 11:51:00.795656 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11125 11:51:00.808408 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11126 11:51:00.828102 [0:00:37.668686463] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 11:51:00.850776 Camera needs 4 requests, can't test only 1
11128 11:51:00.883190 [0:00:37.723910232] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 11:51:00.918790 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11130 11:51:00.979832
11131 11:51:01.045035 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11132 11:51:01.126690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11133 11:51:01.126992 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11135 11:51:01.142898 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11136 11:51:01.187588 Camera needs 4 requests, can't test only 2
11137 11:51:01.248084 [0:00:38.088736617] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11138 11:51:01.251799 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11139 11:51:01.308476
11140 11:51:01.375071 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (54 ms)
11141 11:51:01.447202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11142 11:51:01.447506 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11144 11:51:01.461040 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11145 11:51:01.497816 Camera needs 4 requests, can't test only 3
11146 11:51:01.555342 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11147 11:51:01.614360
11148 11:51:01.686756 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (53 ms)
11149 11:51:01.714235 [0:00:38.555249617] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11150 11:51:01.760956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11151 11:51:01.761263 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11153 11:51:01.774116 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11154 11:51:01.813012 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (366 ms)
11155 11:51:01.879348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11156 11:51:01.879699 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11158 11:51:01.891025 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11159 11:51:01.930282 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (466 ms)
11160 11:51:01.998621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11161 11:51:01.998972 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11163 11:51:02.009433 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11164 11:51:02.401525 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (696 ms)
11165 11:51:02.414928 [0:00:39.251616540] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 11:51:02.476488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11167 11:51:02.476862 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11169 11:51:02.489424 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11170 11:51:03.301955 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (900 ms)
11171 11:51:03.315111 [0:00:40.151897847] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 11:51:03.388711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11173 11:51:03.389033 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11175 11:51:03.402290 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11176 11:51:04.700064 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1399 ms)
11177 11:51:04.713473 [0:00:41.550240847] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 11:51:04.784802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11179 11:51:04.785128 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11181 11:51:04.796238 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11182 11:51:06.798350 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2098 ms)
11183 11:51:06.811527 [0:00:43.648848540] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 11:51:06.886621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11185 11:51:06.886963 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11187 11:51:06.900271 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11188 11:51:09.192740 <6>[ 46.157069] vpu: disabling
11189 11:51:09.196458 <6>[ 46.160176] vproc2: disabling
11190 11:51:09.199665 <6>[ 46.163911] vproc1: disabling
11191 11:51:09.203554 <6>[ 46.167977] vaud18: disabling
11192 11:51:09.210861 <6>[ 46.171716] vsram_others: disabling
11193 11:51:09.214126 <6>[ 46.175903] va09: disabling
11194 11:51:09.217372 <6>[ 46.179320] vsram_md: disabling
11195 11:51:09.220606 <6>[ 46.183117] Vgpu: disabling
11196 11:51:10.029133 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3231 ms)
11197 11:51:10.042104 [0:00:46.879398386] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 11:51:10.094880 [0:00:46.936573232] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11199 11:51:10.115881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11200 11:51:10.116263 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11202 11:51:10.128517 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11203 11:51:10.150378 [0:00:46.991795771] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11204 11:51:10.170164 Camera needs 4 requests, can't test only 1
11205 11:51:10.204720 [0:00:47.046212617] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 11:51:10.224267 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11207 11:51:10.280298
11208 11:51:10.334819 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
11209 11:51:10.406071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11210 11:51:10.406398 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11212 11:51:10.420557 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11213 11:51:10.466624 Camera needs 4 requests, can't test only 2
11214 11:51:10.537742 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11215 11:51:10.598075
11216 11:51:10.665891 [0:00:47.507044002] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 11:51:10.672327 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)
11218 11:51:10.736278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11219 11:51:10.736595 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11221 11:51:10.749301 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11222 11:51:10.793164 Camera needs 4 requests, can't test only 3
11223 11:51:10.859284 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11224 11:51:10.920610
11225 11:51:10.996761 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11226 11:51:11.076569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11227 11:51:11.076896 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11229 11:51:11.089790 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11230 11:51:11.132524 [0:00:47.973868232] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 11:51:11.141049 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (461 ms)
11232 11:51:11.214313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11233 11:51:11.214636 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11235 11:51:11.225514 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11236 11:51:11.264480 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (465 ms)
11237 11:51:11.327742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11238 11:51:11.328110 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11240 11:51:11.343008 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11241 11:51:11.855032 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (732 ms)
11242 11:51:11.868079 [0:00:48.705514309] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 11:51:11.925687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11244 11:51:11.926065 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11246 11:51:11.938193 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11247 11:51:12.754264 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (900 ms)
11248 11:51:12.767388 [0:00:49.604930002] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 11:51:12.827737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11250 11:51:12.828068 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11252 11:51:12.840640 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11253 11:51:14.152131 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1397 ms)
11254 11:51:14.165314 [0:00:51.003229387] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 11:51:14.226596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11256 11:51:14.226930 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11258 11:51:14.237782 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11259 11:51:16.218421 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2066 ms)
11260 11:51:16.231288 [0:00:53.069135617] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 11:51:16.290171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11262 11:51:16.290623 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11264 11:51:16.303351 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11265 11:51:19.478833 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3261 ms)
11266 11:51:19.491866 [0:00:56.330475128] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 11:51:19.544282 [0:00:56.386916171] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 11:51:19.562011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11269 11:51:19.562352 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11271 11:51:19.574370 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11272 11:51:19.599633 [0:00:56.442025288] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 11:51:19.619627 Camera needs 4 requests, can't test only 1
11274 11:51:19.653125 [0:00:56.495735569] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 11:51:19.683626 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11276 11:51:19.743206
11277 11:51:19.799640 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11278 11:51:19.861958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11279 11:51:19.862305 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11281 11:51:19.875078 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11282 11:51:19.912459 Camera needs 4 requests, can't test only 2
11283 11:51:19.969971 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11284 11:51:20.019719 [0:00:56.862441208] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 11:51:20.035721
11286 11:51:20.088478 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11287 11:51:20.156391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11288 11:51:20.156718 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11290 11:51:20.168441 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11291 11:51:20.210848 Camera needs 4 requests, can't test only 3
11292 11:51:20.261492 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11293 11:51:20.320807
11294 11:51:20.388541 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11295 11:51:20.463320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11296 11:51:20.463713 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11298 11:51:20.477402 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11299 11:51:20.487309 [0:00:57.328755831] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 11:51:20.525745 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (366 ms)
11301 11:51:20.591702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11302 11:51:20.592030 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11304 11:51:20.604307 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11305 11:51:20.641485 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (467 ms)
11306 11:51:20.712350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11307 11:51:20.712676 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11309 11:51:20.725183 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11310 11:51:21.206623 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (728 ms)
11311 11:51:21.219647 [0:00:58.057818785] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 11:51:21.281834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11313 11:51:21.282159 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11315 11:51:21.293423 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11316 11:51:22.103947 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (898 ms)
11317 11:51:22.117087 [0:00:58.955160976] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 11:51:22.183722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11319 11:51:22.184046 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11321 11:51:22.196978 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11322 11:51:23.499575 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1395 ms)
11323 11:51:23.512520 [0:01:00.352156269] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 11:51:23.574390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11325 11:51:23.574737 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11327 11:51:23.585454 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11328 11:51:25.596793 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2097 ms)
11329 11:51:25.609893 [0:01:02.449006629] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 11:51:25.663425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11331 11:51:25.663754 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11333 11:51:25.673782 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11334 11:51:28.795122 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3199 ms)
11335 11:51:28.808420 [0:01:05.648122761] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 11:51:28.859363 [0:01:05.701515022] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11337 11:51:28.868362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11338 11:51:28.868692 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11340 11:51:28.879355 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11341 11:51:28.912635 [0:01:05.754547637] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 11:51:28.923959 Camera needs 4 requests, can't test only 1
11343 11:51:28.970211 [0:01:05.812268961] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11344 11:51:28.985287 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11345 11:51:29.042051
11346 11:51:29.110852 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (55 ms)
11347 11:51:29.181464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11348 11:51:29.181799 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11350 11:51:29.195368 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11351 11:51:29.237497 Camera needs 4 requests, can't test only 2
11352 11:51:29.295342 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11353 11:51:29.349852
11354 11:51:29.408295 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11355 11:51:29.474178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11356 11:51:29.474559 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11358 11:51:29.485092 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11359 11:51:29.525933 Camera needs 4 requests, can't test only 3
11360 11:51:29.585283 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11361 11:51:29.637535
11362 11:51:29.698361 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (58 ms)
11363 11:51:29.766759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11364 11:51:29.767084 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11366 11:51:29.780525 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11367 11:51:30.145381 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1182 ms)
11368 11:51:30.158437 [0:01:06.995863541] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 11:51:30.212758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11370 11:51:30.213092 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11372 11:51:30.222550 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11373 11:51:31.530215 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1385 ms)
11374 11:51:31.543091 [0:01:08.383178440] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 11:51:31.599415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11376 11:51:31.599749 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11378 11:51:31.612788 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11379 11:51:33.644869 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2114 ms)
11380 11:51:33.657725 [0:01:10.496891639] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 11:51:33.710825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11382 11:51:33.711165 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11384 11:51:33.722077 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11385 11:51:36.427435 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2783 ms)
11386 11:51:36.440519 [0:01:13.279944456] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 11:51:36.490772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11388 11:51:36.491133 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11390 11:51:36.501789 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11391 11:51:40.543105 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4116 ms)
11392 11:51:40.556575 [0:01:17.396210190] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 11:51:40.608148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11394 11:51:40.608475 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11396 11:51:40.619236 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11397 11:51:46.888372 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6345 ms)
11398 11:51:46.901016 [0:01:23.740256399] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 11:51:46.959016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11400 11:51:46.959649 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11402 11:51:46.971727 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11403 11:51:56.567274 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9680 ms)
11404 11:51:56.580873 [0:01:33.422107501] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 11:51:56.632839 [0:01:33.476095909] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 11:51:56.642995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11407 11:51:56.643303 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11409 11:51:56.653470 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11410 11:51:56.686836 [0:01:33.530655150] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 11:51:56.695434 Camera needs 4 requests, can't test only 1
11412 11:51:56.742111 [0:01:33.585474079] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 11:51:56.749547 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11414 11:51:56.806089
11415 11:51:56.866337 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (55 ms)
11416 11:51:56.937101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11417 11:51:56.937402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11419 11:51:56.947825 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11420 11:51:56.988226 Camera needs 4 requests, can't test only 2
11421 11:51:57.049223 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11422 11:51:57.106183
11423 11:51:57.175232 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11424 11:51:57.239912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11425 11:51:57.240235 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11427 11:51:57.248390 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11428 11:51:57.284045 Camera needs 4 requests, can't test only 3
11429 11:51:57.342869 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11430 11:51:57.396037
11431 11:51:57.459251 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (55 ms)
11432 11:51:57.521483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11433 11:51:57.521824 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11435 11:51:57.533840 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11436 11:51:57.890061 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1153 ms)
11437 11:51:57.900042 [0:01:34.739331986] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 11:51:57.958068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11439 11:51:57.958366 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11441 11:51:57.965029 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11442 11:51:59.276132 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1386 ms)
11443 11:51:59.285874 [0:01:36.127494600] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 11:51:59.345395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11445 11:51:59.345725 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11447 11:51:59.353245 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11448 11:52:01.451641 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2176 ms)
11449 11:52:01.461785 [0:01:38.303202288] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 11:52:01.521362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11451 11:52:01.521672 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11453 11:52:01.529787 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11454 11:52:04.142524 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2686 ms)
11455 11:52:04.147988 [0:01:40.989580069] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 11:52:04.206185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11457 11:52:04.206486 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11459 11:52:04.214365 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11460 11:52:08.254816 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4118 ms)
11461 11:52:08.264726 [0:01:45.106560592] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 11:52:08.324973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11463 11:52:08.325266 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11465 11:52:08.333256 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11466 11:52:14.627522 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6373 ms)
11467 11:52:14.637204 [0:01:51.479873787] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 11:52:14.697276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11469 11:52:14.697584 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11471 11:52:14.706821 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11472 11:52:24.368761 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9742 ms)
11473 11:52:24.378484 [0:02:01.222131245] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 11:52:24.429425 [0:02:01.274870385] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11475 11:52:24.444094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11476 11:52:24.444441 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11478 11:52:24.453282 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11479 11:52:24.482994 [0:02:01.329347019] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 11:52:24.498592 Camera needs 4 requests, can't test only 1
11481 11:52:24.538543 [0:02:01.384146881] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11482 11:52:24.561171 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11483 11:52:24.611016
11484 11:52:24.674778 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (55 ms)
11485 11:52:24.736982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11486 11:52:24.737301 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11488 11:52:24.744570 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11489 11:52:24.786927 Camera needs 4 requests, can't test only 2
11490 11:52:24.840561 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11491 11:52:24.899943
11492 11:52:24.966244 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (54 ms)
11493 11:52:25.027937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11494 11:52:25.028279 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11496 11:52:25.034190 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11497 11:52:25.075350 Camera needs 4 requests, can't test only 3
11498 11:52:25.131313 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11499 11:52:25.184425
11500 11:52:25.249880 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (55 ms)
11501 11:52:25.317310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11502 11:52:25.317608 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11504 11:52:25.326298 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11505 11:52:25.620720 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1088 ms)
11506 11:52:25.630170 [0:02:02.471963961] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 11:52:25.688461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11508 11:52:25.688795 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11510 11:52:25.696104 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11511 11:52:27.012238 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1391 ms)
11512 11:52:27.022027 [0:02:03.865491193] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 11:52:27.080964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11514 11:52:27.081293 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11516 11:52:27.088933 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11517 11:52:29.129367 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2117 ms)
11518 11:52:29.139245 [0:02:05.982145040] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 11:52:29.194862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11520 11:52:29.195154 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11522 11:52:29.203892 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11523 11:52:31.815250 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2685 ms)
11524 11:52:31.824963 [0:02:08.667484551] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 11:52:31.883611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11526 11:52:31.883906 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11528 11:52:31.892412 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11529 11:52:35.999215 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4184 ms)
11530 11:52:36.009122 [0:02:12.851452586] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 11:52:36.066567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11532 11:52:36.066904 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11534 11:52:36.074444 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11535 11:52:42.313669 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6314 ms)
11536 11:52:42.323438 [0:02:19.165699000] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 11:52:42.407291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11538 11:52:42.407611 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11540 11:52:42.420778 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11541 11:52:51.959808 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9646 ms)
11542 11:52:51.969903 [0:02:28.810806672] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 11:52:52.020811 [0:02:28.864993299] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 11:52:52.078191 [0:02:28.922297766] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 11:52:52.084644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11546 11:52:52.085226 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11548 11:52:52.092823 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11549 11:52:52.133890 [0:02:28.977959734] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 11:52:52.151884 Camera needs 4 requests, can't test only 1
11551 11:52:52.225410 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11552 11:52:52.288000
11553 11:52:52.368616 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (55 ms)
11554 11:52:52.448422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11555 11:52:52.448735 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11557 11:52:52.460671 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11558 11:52:52.507631 Camera needs 4 requests, can't test only 2
11559 11:52:52.596803 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11560 11:52:52.670771
11561 11:52:52.740988 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11562 11:52:52.806756 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11564 11:52:52.809404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11565 11:52:52.823336 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11566 11:52:52.875474 Camera needs 4 requests, can't test only 3
11567 11:52:52.955689 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11568 11:52:53.027261
11569 11:52:53.107270 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (56 ms)
11570 11:52:53.184932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11571 11:52:53.185239 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11573 11:52:53.195385 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11574 11:52:53.248480 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1119 ms)
11575 11:52:53.257993 [0:02:30.098149655] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 11:52:53.323477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11577 11:52:53.323773 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11579 11:52:53.332382 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11580 11:52:54.639135 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1391 ms)
11581 11:52:54.649485 [0:02:31.491126180] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 11:52:54.713531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11583 11:52:54.713850 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11585 11:52:54.721901 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11586 11:52:56.821054 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2181 ms)
11587 11:52:56.830583 [0:02:33.671802873] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 11:52:56.902793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11589 11:52:56.903544 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11591 11:52:56.913488 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11592 11:52:59.505196 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2685 ms)
11593 11:52:59.515417 [0:02:36.357546433] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 11:52:59.595995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11595 11:52:59.596724 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11597 11:52:59.609692 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11598 11:53:03.623197 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4115 ms)
11599 11:53:03.632777 [0:02:40.474339116] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 11:53:03.713704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11601 11:53:03.714444 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11603 11:53:03.726248 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11604 11:53:09.969068 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6346 ms)
11605 11:53:09.978022 [0:02:46.819973479] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 11:53:10.044136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11607 11:53:10.044626 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11609 11:53:10.052945 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11610 11:53:19.710641 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9743 ms)
11611 11:53:19.720748 [0:02:56.562963090] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 11:53:19.797657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11613 11:53:19.798345 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11615 11:53:19.809438 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11616 11:53:20.006854 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (298 ms)
11617 11:53:20.016387 [0:02:56.859491507] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 11:53:20.100324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11619 11:53:20.101065 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11621 11:53:20.116868 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11622 11:53:20.272621 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (266 ms)
11623 11:53:20.285437 [0:02:57.125342039] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 11:53:20.369239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11625 11:53:20.370009 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11627 11:53:20.385240 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11628 11:53:20.570245 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (298 ms)
11629 11:53:20.583444 [0:02:57.423400321] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 11:53:20.673231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11631 11:53:20.673615 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11633 11:53:20.688772 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11634 11:53:20.935777 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (365 ms)
11635 11:53:20.945385 [0:02:57.788659995] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 11:53:21.038649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11637 11:53:21.039376 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11639 11:53:21.055311 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11640 11:53:21.403069 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (468 ms)
11641 11:53:21.412708 [0:02:58.256131244] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 11:53:21.498690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11643 11:53:21.499420 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11645 11:53:21.516808 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11646 11:53:22.132459 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (729 ms)
11647 11:53:22.145402 [0:02:58.985533728] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 11:53:22.228128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11649 11:53:22.228851 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11651 11:53:22.244153 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11652 11:53:23.031686 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (899 ms)
11653 11:53:23.044607 [0:02:59.884860314] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 11:53:23.135250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11655 11:53:23.136007 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11657 11:53:23.152708 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11658 11:53:24.427243 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1397 ms)
11659 11:53:24.440619 [0:03:01.282531278] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 11:53:24.543983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11661 11:53:24.544846 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11663 11:53:24.561359 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11664 11:53:26.555736 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2128 ms)
11665 11:53:26.568838 [0:03:03.411156238] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 11:53:26.640491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11667 11:53:26.640942 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11669 11:53:26.655904 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11670 11:53:29.818416 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3261 ms)
11671 11:53:29.830160 [0:03:06.671954403] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 11:53:29.918877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11673 11:53:29.919158 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11675 11:53:29.935267 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11676 11:53:30.149506 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (330 ms)
11677 11:53:30.158808 [0:03:06.999979176] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 11:53:30.229350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11679 11:53:30.229697 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11681 11:53:30.239517 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11682 11:53:30.415392 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (265 ms)
11683 11:53:30.424757 [0:03:07.265541857] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 11:53:30.513643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11685 11:53:30.514396 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11687 11:53:30.524815 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11688 11:53:30.713262 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (298 ms)
11689 11:53:30.723146 [0:03:07.563767200] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 11:53:30.814783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11691 11:53:30.815556 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11693 11:53:30.827662 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11694 11:53:31.077559 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (365 ms)
11695 11:53:31.087654 [0:03:07.928282491] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 11:53:31.171633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11697 11:53:31.172344 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11699 11:53:31.182957 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11700 11:53:31.545277 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (467 ms)
11701 11:53:31.555320 [0:03:08.395609605] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 11:53:31.625386 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11704 11:53:31.628799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11705 11:53:31.639061 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11706 11:53:32.274460 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (730 ms)
11707 11:53:32.284393 [0:03:09.125044412] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 11:53:32.364169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11709 11:53:32.364897 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11711 11:53:32.376919 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11712 11:53:33.173088 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (898 ms)
11713 11:53:33.182732 [0:03:10.023815451] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 11:53:33.274583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11715 11:53:33.275348 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11717 11:53:33.286144 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11718 11:53:34.568804 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1396 ms)
11719 11:53:34.578905 [0:03:11.421204329] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 11:53:34.662530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11721 11:53:34.663361 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11723 11:53:34.674950 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11724 11:53:36.699124 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2130 ms)
11725 11:53:36.709212 [0:03:13.551569574] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 11:53:36.787078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11727 11:53:36.787481 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11729 11:53:36.799708 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11730 11:53:39.962077 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3263 ms)
11731 11:53:39.971969 [0:03:16.814697132] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 11:53:40.054640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11733 11:53:40.055000 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11735 11:53:40.067591 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11736 11:53:40.293647 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (331 ms)
11737 11:53:40.303147 [0:03:17.144255056] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 11:53:40.393470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11739 11:53:40.393816 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11741 11:53:40.406132 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11742 11:53:40.560879 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (268 ms)
11743 11:53:40.570582 [0:03:17.412244871] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 11:53:40.667193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11745 11:53:40.667927 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11747 11:53:40.683278 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11748 11:53:40.859492 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (298 ms)
11749 11:53:40.869479 [0:03:17.710563852] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 11:53:40.949301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11751 11:53:40.950106 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11753 11:53:40.961568 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11754 11:53:41.224213 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (365 ms)
11755 11:53:41.234235 [0:03:18.075609704] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 11:53:41.326414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11757 11:53:41.327138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11759 11:53:41.340783 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11760 11:53:41.689339 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (465 ms)
11761 11:53:41.698911 [0:03:18.540781461] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 11:53:41.772298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11763 11:53:41.772609 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11765 11:53:41.782494 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11766 11:53:42.386155 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (697 ms)
11767 11:53:42.396163 [0:03:19.237533986] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 11:53:42.465184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11769 11:53:42.465500 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11771 11:53:42.476262 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11772 11:53:43.284762 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (899 ms)
11773 11:53:43.294415 [0:03:20.135878318] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 11:53:43.371120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11775 11:53:43.371444 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11777 11:53:43.380903 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11778 11:53:44.680447 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1395 ms)
11779 11:53:44.690176 [0:03:21.533680721] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 11:53:44.750839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11781 11:53:44.751126 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11783 11:53:44.758971 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11784 11:53:46.777583 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2097 ms)
11785 11:53:46.787367 [0:03:23.631292552] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 11:53:46.854745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11787 11:53:46.855038 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11789 11:53:46.865499 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11790 11:53:50.040821 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3263 ms)
11791 11:53:50.049903 [0:03:26.894294192] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 11:53:50.124053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11793 11:53:50.124382 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11795 11:53:50.133790 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11796 11:53:50.371746 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (332 ms)
11797 11:53:50.381772 [0:03:27.224194498] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 11:53:50.444559 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11800 11:53:50.447627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11801 11:53:50.458441 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11802 11:53:50.639259 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (267 ms)
11803 11:53:50.649084 [0:03:27.491254625] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 11:53:50.720340 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11806 11:53:50.723497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11807 11:53:50.733180 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11808 11:53:50.937598 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (298 ms)
11809 11:53:50.947194 [0:03:27.789889565] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 11:53:51.009982 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11812 11:53:51.013146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11813 11:53:51.022011 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11814 11:53:51.302733 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (365 ms)
11815 11:53:51.312278 [0:03:28.154989664] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 11:53:51.376337 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11818 11:53:51.379895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11819 11:53:51.388888 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11820 11:53:51.768313 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (465 ms)
11821 11:53:51.777791 [0:03:28.620338967] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 11:53:51.840132 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11824 11:53:51.843657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11825 11:53:51.852608 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11826 11:53:52.465205 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (697 ms)
11827 11:53:52.475129 [0:03:29.317257436] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 11:53:52.531299 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11830 11:53:52.534046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11831 11:53:52.541710 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11832 11:53:53.362641 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (898 ms)
11833 11:53:53.372709 [0:03:30.215231184] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 11:53:53.424310 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11836 11:53:53.427428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11837 11:53:53.435124 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11838 11:53:54.759066 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1396 ms)
11839 11:53:54.769027 [0:03:31.613175968] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 11:53:54.827904 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11842 11:53:54.831377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11843 11:53:54.839190 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11844 11:53:56.856546 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2098 ms)
11845 11:53:56.866611 [0:03:33.710856708] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11846 11:53:56.929373 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11848 11:53:56.932567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11849 11:53:56.944469 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11850 11:54:00.053747 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3198 ms)
11851 11:54:00.118985 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11853 11:54:00.121622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11854 11:54:00.129375 [----------] 120 tests from CaptureTests/SingleStream (188795 ms total)
11855 11:54:00.184113
11856 11:54:00.248544 [----------] Global test environment tear-down
11857 11:54:00.307146 [==========] 120 tests from 1 test suite ran. (188796 ms total)
11858 11:54:00.368768 <LAVA_SIGNAL_TESTSET STOP>
11859 11:54:00.369126 Received signal: <TESTSET> STOP
11860 11:54:00.369214 Closing test_set CaptureTests/SingleStream
11861 11:54:00.378383 + set +x
11862 11:54:00.381945 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12074027_1.6.2.3.1>
11863 11:54:00.382199 Received signal: <ENDRUN> 0_lc-compliance 12074027_1.6.2.3.1
11864 11:54:00.382283 Ending use of test pattern.
11865 11:54:00.382347 Ending test lava.0_lc-compliance (12074027_1.6.2.3.1), duration 190.31
11867 11:54:00.385426 <LAVA_TEST_RUNNER EXIT>
11868 11:54:00.385704 ok: lava_test_shell seems to have completed
11869 11:54:00.387504 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11870 11:54:00.387679 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11871 11:54:00.387770 end: 3 lava-test-retry (duration 00:03:11) [common]
11872 11:54:00.387857 start: 4 finalize (timeout 00:10:00) [common]
11873 11:54:00.387946 start: 4.1 power-off (timeout 00:00:30) [common]
11874 11:54:00.388099 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11875 11:54:00.464221 >> Command sent successfully.
11876 11:54:00.466892 Returned 0 in 0 seconds
11877 11:54:00.567332 end: 4.1 power-off (duration 00:00:00) [common]
11879 11:54:00.567675 start: 4.2 read-feedback (timeout 00:10:00) [common]
11880 11:54:00.567952 Listened to connection for namespace 'common' for up to 1s
11881 11:54:01.569073 Finalising connection for namespace 'common'
11882 11:54:01.569851 Disconnecting from shell: Finalise
11883 11:54:01.570282 / #
11884 11:54:01.671267 end: 4.2 read-feedback (duration 00:00:01) [common]
11885 11:54:01.671915 end: 4 finalize (duration 00:00:01) [common]
11886 11:54:01.672457 Cleaning after the job
11887 11:54:01.673032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/ramdisk
11888 11:54:01.684672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/kernel
11889 11:54:01.719169 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/dtb
11890 11:54:01.719457 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/nfsrootfs
11891 11:54:01.780109 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074027/tftp-deploy-7eni79v0/modules
11892 11:54:01.787476 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074027
11893 11:54:02.101690 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074027
11894 11:54:02.101874 Job finished correctly