Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 35
- Kernel Warnings: 26
- Boot result: PASS
- Errors: 1
1 11:46:20.385979 lava-dispatcher, installed at version: 2023.10
2 11:46:20.386187 start: 0 validate
3 11:46:20.386318 Start time: 2023-11-24 11:46:20.386309+00:00 (UTC)
4 11:46:20.386438 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:46:20.386568 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:46:20.651226 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:46:20.651402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:46:21.419602 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:46:21.420444 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:46:21.683973 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:46:21.684662 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:46:26.942030 validate duration: 6.56
14 11:46:26.942302 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:46:26.942399 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:46:26.942489 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:46:26.942615 Not decompressing ramdisk as can be used compressed.
18 11:46:26.942703 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 11:46:26.942771 saving as /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/ramdisk/rootfs.cpio.gz
20 11:46:26.942856 total size: 26246609 (25 MB)
21 11:46:26.944048 progress 0 % (0 MB)
22 11:46:26.951449 progress 5 % (1 MB)
23 11:46:26.958399 progress 10 % (2 MB)
24 11:46:26.965567 progress 15 % (3 MB)
25 11:46:26.972596 progress 20 % (5 MB)
26 11:46:26.979736 progress 25 % (6 MB)
27 11:46:26.986903 progress 30 % (7 MB)
28 11:46:26.993873 progress 35 % (8 MB)
29 11:46:27.000698 progress 40 % (10 MB)
30 11:46:27.007681 progress 45 % (11 MB)
31 11:46:27.014570 progress 50 % (12 MB)
32 11:46:27.021610 progress 55 % (13 MB)
33 11:46:27.028526 progress 60 % (15 MB)
34 11:46:27.035768 progress 65 % (16 MB)
35 11:46:27.042973 progress 70 % (17 MB)
36 11:46:27.050635 progress 75 % (18 MB)
37 11:46:27.057908 progress 80 % (20 MB)
38 11:46:27.065381 progress 85 % (21 MB)
39 11:46:27.073101 progress 90 % (22 MB)
40 11:46:27.080342 progress 95 % (23 MB)
41 11:46:27.087676 progress 100 % (25 MB)
42 11:46:27.087960 25 MB downloaded in 0.15 s (172.50 MB/s)
43 11:46:27.088184 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:46:27.088426 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:46:27.088514 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:46:27.088600 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:46:27.088772 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:46:27.088845 saving as /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/kernel/Image
50 11:46:27.088907 total size: 49107456 (46 MB)
51 11:46:27.089006 No compression specified
52 11:46:27.090217 progress 0 % (0 MB)
53 11:46:27.103678 progress 5 % (2 MB)
54 11:46:27.116747 progress 10 % (4 MB)
55 11:46:27.129871 progress 15 % (7 MB)
56 11:46:27.142959 progress 20 % (9 MB)
57 11:46:27.155978 progress 25 % (11 MB)
58 11:46:27.168950 progress 30 % (14 MB)
59 11:46:27.182020 progress 35 % (16 MB)
60 11:46:27.195088 progress 40 % (18 MB)
61 11:46:27.208058 progress 45 % (21 MB)
62 11:46:27.221052 progress 50 % (23 MB)
63 11:46:27.234039 progress 55 % (25 MB)
64 11:46:27.247029 progress 60 % (28 MB)
65 11:46:27.260183 progress 65 % (30 MB)
66 11:46:27.273295 progress 70 % (32 MB)
67 11:46:27.286374 progress 75 % (35 MB)
68 11:46:27.299563 progress 80 % (37 MB)
69 11:46:27.312750 progress 85 % (39 MB)
70 11:46:27.325885 progress 90 % (42 MB)
71 11:46:27.338721 progress 95 % (44 MB)
72 11:46:27.351436 progress 100 % (46 MB)
73 11:46:27.351689 46 MB downloaded in 0.26 s (178.22 MB/s)
74 11:46:27.351854 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:46:27.352097 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:46:27.352188 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:46:27.352285 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:46:27.352431 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:46:27.352502 saving as /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/dtb/mt8192-asurada-spherion-r0.dtb
81 11:46:27.352564 total size: 47278 (0 MB)
82 11:46:27.352629 No compression specified
83 11:46:27.353785 progress 69 % (0 MB)
84 11:46:27.354068 progress 100 % (0 MB)
85 11:46:27.354228 0 MB downloaded in 0.00 s (27.14 MB/s)
86 11:46:27.354357 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:46:27.354583 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:46:27.354671 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:46:27.354756 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:46:27.354881 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:46:27.354955 saving as /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/modules/modules.tar
93 11:46:27.355018 total size: 8624756 (8 MB)
94 11:46:27.355082 Using unxz to decompress xz
95 11:46:27.359922 progress 0 % (0 MB)
96 11:46:27.381617 progress 5 % (0 MB)
97 11:46:27.406337 progress 10 % (0 MB)
98 11:46:27.431585 progress 15 % (1 MB)
99 11:46:27.456585 progress 20 % (1 MB)
100 11:46:27.481782 progress 25 % (2 MB)
101 11:46:27.508864 progress 30 % (2 MB)
102 11:46:27.537964 progress 35 % (2 MB)
103 11:46:27.562402 progress 40 % (3 MB)
104 11:46:27.589318 progress 45 % (3 MB)
105 11:46:27.616505 progress 50 % (4 MB)
106 11:46:27.642946 progress 55 % (4 MB)
107 11:46:27.668464 progress 60 % (4 MB)
108 11:46:27.697119 progress 65 % (5 MB)
109 11:46:27.723000 progress 70 % (5 MB)
110 11:46:27.748752 progress 75 % (6 MB)
111 11:46:27.778864 progress 80 % (6 MB)
112 11:46:27.805926 progress 85 % (7 MB)
113 11:46:27.833615 progress 90 % (7 MB)
114 11:46:27.866245 progress 95 % (7 MB)
115 11:46:27.895999 progress 100 % (8 MB)
116 11:46:27.901196 8 MB downloaded in 0.55 s (15.06 MB/s)
117 11:46:27.901477 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:46:27.901789 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:46:27.901888 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:46:27.901993 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:46:27.902078 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:46:27.902186 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:46:27.902428 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8
125 11:46:27.902571 makedir: /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin
126 11:46:27.902696 makedir: /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/tests
127 11:46:27.902803 makedir: /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/results
128 11:46:27.902928 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-add-keys
129 11:46:27.903087 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-add-sources
130 11:46:27.903241 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-background-process-start
131 11:46:27.903379 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-background-process-stop
132 11:46:27.903509 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-common-functions
133 11:46:27.903653 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-echo-ipv4
134 11:46:27.903787 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-install-packages
135 11:46:27.903917 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-installed-packages
136 11:46:27.904043 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-os-build
137 11:46:27.904186 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-probe-channel
138 11:46:27.904318 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-probe-ip
139 11:46:27.904448 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-target-ip
140 11:46:27.904576 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-target-mac
141 11:46:27.904721 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-target-storage
142 11:46:27.904859 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-case
143 11:46:27.904991 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-event
144 11:46:27.905118 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-feedback
145 11:46:27.905269 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-raise
146 11:46:27.905419 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-reference
147 11:46:27.905597 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-runner
148 11:46:27.905741 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-set
149 11:46:27.905875 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-test-shell
150 11:46:27.906010 Updating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-install-packages (oe)
151 11:46:27.906187 Updating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/bin/lava-installed-packages (oe)
152 11:46:27.906316 Creating /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/environment
153 11:46:27.906422 LAVA metadata
154 11:46:27.906499 - LAVA_JOB_ID=12074018
155 11:46:27.906564 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:46:27.906688 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:46:27.906761 skipped lava-vland-overlay
158 11:46:27.906838 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:46:27.906959 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:46:27.907074 skipped lava-multinode-overlay
161 11:46:27.907190 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:46:27.907289 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:46:27.907373 Loading test definitions
164 11:46:27.907472 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:46:27.907553 Using /lava-12074018 at stage 0
166 11:46:27.907886 uuid=12074018_1.5.2.3.1 testdef=None
167 11:46:27.907977 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:46:27.908070 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:46:27.908616 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:46:27.908861 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:46:27.909521 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:46:27.909792 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:46:27.910473 runner path: /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/0/tests/0_v4l2-compliance-uvc test_uuid 12074018_1.5.2.3.1
176 11:46:27.910637 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:46:27.910870 Creating lava-test-runner.conf files
179 11:46:27.910935 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074018/lava-overlay-dzys9wf8/lava-12074018/0 for stage 0
180 11:46:27.911027 - 0_v4l2-compliance-uvc
181 11:46:27.911131 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:46:27.911237 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:46:27.918553 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:46:27.918686 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:46:27.918792 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:46:27.918883 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:46:27.918979 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:46:28.664105 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:46:28.664529 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:46:28.664683 extracting modules file /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074018/extract-overlay-ramdisk-w8wcm2ua/ramdisk
191 11:46:28.919529 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:46:28.919703 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:46:28.919806 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074018/compress-overlay-7tex0f94/overlay-1.5.2.4.tar.gz to ramdisk
194 11:46:28.919877 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074018/compress-overlay-7tex0f94/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074018/extract-overlay-ramdisk-w8wcm2ua/ramdisk
195 11:46:28.926699 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:46:28.926847 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:46:28.926962 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:46:28.927074 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:46:28.927172 Building ramdisk /var/lib/lava/dispatcher/tmp/12074018/extract-overlay-ramdisk-w8wcm2ua/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074018/extract-overlay-ramdisk-w8wcm2ua/ramdisk
200 11:46:29.541643 >> 228427 blocks
201 11:46:33.762696 rename /var/lib/lava/dispatcher/tmp/12074018/extract-overlay-ramdisk-w8wcm2ua/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/ramdisk/ramdisk.cpio.gz
202 11:46:33.763153 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:46:33.763278 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:46:33.763389 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:46:33.763501 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/kernel/Image'
206 11:46:47.599662 Returned 0 in 13 seconds
207 11:46:47.700402 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/kernel/image.itb
208 11:46:48.340343 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:46:48.340841 output: Created: Fri Nov 24 11:46:48 2023
210 11:46:48.340956 output: Image 0 (kernel-1)
211 11:46:48.341059 output: Description:
212 11:46:48.341158 output: Created: Fri Nov 24 11:46:48 2023
213 11:46:48.341257 output: Type: Kernel Image
214 11:46:48.341355 output: Compression: lzma compressed
215 11:46:48.341451 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
216 11:46:48.341545 output: Architecture: AArch64
217 11:46:48.341684 output: OS: Linux
218 11:46:48.341777 output: Load Address: 0x00000000
219 11:46:48.341872 output: Entry Point: 0x00000000
220 11:46:48.341967 output: Hash algo: crc32
221 11:46:48.342058 output: Hash value: 43cfb6ad
222 11:46:48.342150 output: Image 1 (fdt-1)
223 11:46:48.342240 output: Description: mt8192-asurada-spherion-r0
224 11:46:48.342329 output: Created: Fri Nov 24 11:46:48 2023
225 11:46:48.342418 output: Type: Flat Device Tree
226 11:46:48.342509 output: Compression: uncompressed
227 11:46:48.342598 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:46:48.342687 output: Architecture: AArch64
229 11:46:48.342812 output: Hash algo: crc32
230 11:46:48.342900 output: Hash value: cc4352de
231 11:46:48.342989 output: Image 2 (ramdisk-1)
232 11:46:48.343077 output: Description: unavailable
233 11:46:48.343166 output: Created: Fri Nov 24 11:46:48 2023
234 11:46:48.343255 output: Type: RAMDisk Image
235 11:46:48.343346 output: Compression: Unknown Compression
236 11:46:48.343434 output: Data Size: 39353498 Bytes = 38431.15 KiB = 37.53 MiB
237 11:46:48.343523 output: Architecture: AArch64
238 11:46:48.343611 output: OS: Linux
239 11:46:48.343700 output: Load Address: unavailable
240 11:46:48.343790 output: Entry Point: unavailable
241 11:46:48.343879 output: Hash algo: crc32
242 11:46:48.343967 output: Hash value: 8735f2f6
243 11:46:48.344055 output: Default Configuration: 'conf-1'
244 11:46:48.344143 output: Configuration 0 (conf-1)
245 11:46:48.344231 output: Description: mt8192-asurada-spherion-r0
246 11:46:48.344319 output: Kernel: kernel-1
247 11:46:48.344407 output: Init Ramdisk: ramdisk-1
248 11:46:48.344496 output: FDT: fdt-1
249 11:46:48.344584 output: Loadables: kernel-1
250 11:46:48.344672 output:
251 11:46:48.344948 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:46:48.345099 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:46:48.345256 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:46:48.345400 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:46:48.345520 No LXC device requested
256 11:46:48.345687 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:46:48.345818 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:46:48.345939 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:46:48.346048 Checking files for TFTP limit of 4294967296 bytes.
260 11:46:48.346786 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:46:48.346932 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:46:48.347065 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:46:48.347237 substitutions:
264 11:46:48.347338 - {DTB}: 12074018/tftp-deploy-i3e52gb4/dtb/mt8192-asurada-spherion-r0.dtb
265 11:46:48.347437 - {INITRD}: 12074018/tftp-deploy-i3e52gb4/ramdisk/ramdisk.cpio.gz
266 11:46:48.347531 - {KERNEL}: 12074018/tftp-deploy-i3e52gb4/kernel/Image
267 11:46:48.347623 - {LAVA_MAC}: None
268 11:46:48.347713 - {PRESEED_CONFIG}: None
269 11:46:48.347805 - {PRESEED_LOCAL}: None
270 11:46:48.347896 - {RAMDISK}: 12074018/tftp-deploy-i3e52gb4/ramdisk/ramdisk.cpio.gz
271 11:46:48.347988 - {ROOT_PART}: None
272 11:46:48.348078 - {ROOT}: None
273 11:46:48.348167 - {SERVER_IP}: 192.168.201.1
274 11:46:48.348256 - {TEE}: None
275 11:46:48.348343 Parsed boot commands:
276 11:46:48.348430 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:46:48.348680 Parsed boot commands: tftpboot 192.168.201.1 12074018/tftp-deploy-i3e52gb4/kernel/image.itb 12074018/tftp-deploy-i3e52gb4/kernel/cmdline
278 11:46:48.348846 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:46:48.348983 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:46:48.349125 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:46:48.349262 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:46:48.349375 Not connected, no need to disconnect.
283 11:46:48.349490 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:46:48.349654 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:46:48.349759 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 11:46:48.354549 Setting prompt string to ['lava-test: # ']
287 11:46:48.355083 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:46:48.355245 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:46:48.355416 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:46:48.355557 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:46:48.355867 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 11:46:53.485617 >> Command sent successfully.
293 11:46:53.488098 Returned 0 in 5 seconds
294 11:46:53.588515 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:46:53.588838 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:46:53.588941 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:46:53.589032 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:46:53.589098 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:46:53.589166 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:46:53.589436 [Enter `^Ec?' for help]
302 11:46:53.763603
303 11:46:53.763759
304 11:46:53.763832 F0: 102B 0000
305 11:46:53.763898
306 11:46:53.763959 F3: 1001 0000 [0200]
307 11:46:53.766653
308 11:46:53.766742 F3: 1001 0000
309 11:46:53.766809
310 11:46:53.766885 F7: 102D 0000
311 11:46:53.766947
312 11:46:53.769787 F1: 0000 0000
313 11:46:53.769876
314 11:46:53.769943 V0: 0000 0000 [0001]
315 11:46:53.770009
316 11:46:53.773093 00: 0007 8000
317 11:46:53.773211
318 11:46:53.773276 01: 0000 0000
319 11:46:53.773338
320 11:46:53.776424 BP: 0C00 0209 [0000]
321 11:46:53.776513
322 11:46:53.776579 G0: 1182 0000
323 11:46:53.776641
324 11:46:53.780124 EC: 0000 0021 [4000]
325 11:46:53.780222
326 11:46:53.780289 S7: 0000 0000 [0000]
327 11:46:53.780351
328 11:46:53.783863 CC: 0000 0000 [0001]
329 11:46:53.783967
330 11:46:53.784037 T0: 0000 0040 [010F]
331 11:46:53.784099
332 11:46:53.784160 Jump to BL
333 11:46:53.784218
334 11:46:53.810040
335 11:46:53.810180
336 11:46:53.810247
337 11:46:53.817411 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:46:53.821029 ARM64: Exception handlers installed.
339 11:46:53.824747 ARM64: Testing exception
340 11:46:53.828021 ARM64: Done test exception
341 11:46:53.834551 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:46:53.844833 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:46:53.851795 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:46:53.861579 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:46:53.868569 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:46:53.874965 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:46:53.887213 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:46:53.894009 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:46:53.912896 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:46:53.916643 WDT: Last reset was cold boot
351 11:46:53.919615 SPI1(PAD0) initialized at 2873684 Hz
352 11:46:53.923170 SPI5(PAD0) initialized at 992727 Hz
353 11:46:53.926606 VBOOT: Loading verstage.
354 11:46:53.933224 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:46:53.937496 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:46:53.940759 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:46:53.943939 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:46:53.951082 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:46:53.957256 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:46:53.968384 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:46:53.968479
362 11:46:53.968544
363 11:46:53.978741 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:46:53.981986 ARM64: Exception handlers installed.
365 11:46:53.985130 ARM64: Testing exception
366 11:46:53.985211 ARM64: Done test exception
367 11:46:53.991617 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:46:53.995195 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:46:54.008917 Probing TPM: . done!
370 11:46:54.009006 TPM ready after 0 ms
371 11:46:54.015971 Connected to device vid:did:rid of 1ae0:0028:00
372 11:46:54.022702 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:46:54.082084 Initialized TPM device CR50 revision 0
374 11:46:54.094224 tlcl_send_startup: Startup return code is 0
375 11:46:54.094375 TPM: setup succeeded
376 11:46:54.105380 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:46:54.114489 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:46:54.126435 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:46:54.136726 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:46:54.139942 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:46:54.143322 in-header: 03 07 00 00 08 00 00 00
382 11:46:54.147159 in-data: aa e4 47 04 13 02 00 00
383 11:46:54.150822 Chrome EC: UHEPI supported
384 11:46:54.154280 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:46:54.159691 in-header: 03 95 00 00 08 00 00 00
386 11:46:54.163441 in-data: 18 20 20 08 00 00 00 00
387 11:46:54.163619 Phase 1
388 11:46:54.166902 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:46:54.174716 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:46:54.182077 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:46:54.182386 Recovery requested (1009000e)
392 11:46:54.195250 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:46:54.198389 tlcl_extend: response is 0
394 11:46:54.208108 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:46:54.213219 tlcl_extend: response is 0
396 11:46:54.219677 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:46:54.239933 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:46:54.246398 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:46:54.246813
400 11:46:54.247119
401 11:46:54.256999 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:46:54.259877 ARM64: Exception handlers installed.
403 11:46:54.263600 ARM64: Testing exception
404 11:46:54.264131 ARM64: Done test exception
405 11:46:54.285743 pmic_efuse_setting: Set efuses in 11 msecs
406 11:46:54.288930 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:46:54.295805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:46:54.299143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:46:54.306311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:46:54.309473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:46:54.313673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:46:54.317089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:46:54.324391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:46:54.328180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:46:54.332225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:46:54.339314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:46:54.343447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:46:54.347093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:46:54.350426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:46:54.357509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:46:54.365554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:46:54.368678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:46:54.376546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:46:54.380176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:46:54.387592 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:46:54.391277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:46:54.398749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:46:54.402635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:46:54.409626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:46:54.413301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:46:54.420777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:46:54.424196 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:46:54.431730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:46:54.435535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:46:54.438994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:46:54.446115 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:46:54.450161 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:46:54.453371 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:46:54.461255 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:46:54.464525 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:46:54.468776 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:46:54.476347 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:46:54.479404 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:46:54.483306 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:46:54.490654 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:46:54.494568 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:46:54.497550 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:46:54.501858 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:46:54.505446 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:46:54.509285 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:46:54.516300 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:46:54.520146 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:46:54.523508 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:46:54.527560 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:46:54.531675 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:46:54.535522 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:46:54.538922 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:46:54.550272 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:46:54.557648 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:46:54.561548 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:46:54.568247 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:46:54.579051 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:46:54.583148 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:46:54.587073 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:46:54.590296 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:46:54.599417 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:46:54.602727 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:46:54.610952 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:46:54.614107 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:46:54.623210 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 11:46:54.633200 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 11:46:54.642099 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 11:46:54.651867 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 11:46:54.660900 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 11:46:54.670920 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 11:46:54.680531 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 11:46:54.684362 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:46:54.687629 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:46:54.691468 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:46:54.699066 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:46:54.703014 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:46:54.707460 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:46:54.707897 ADC[4]: Raw value=906573 ID=7
484 11:46:54.711049 ADC[3]: Raw value=213441 ID=1
485 11:46:54.711158 RAM Code: 0x71
486 11:46:54.718781 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:46:54.722575 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:46:54.730122 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:46:54.737194 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:46:54.741095 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:46:54.744998 in-header: 03 07 00 00 08 00 00 00
492 11:46:54.748714 in-data: aa e4 47 04 13 02 00 00
493 11:46:54.748791 Chrome EC: UHEPI supported
494 11:46:54.755653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:46:54.760619 in-header: 03 95 00 00 08 00 00 00
496 11:46:54.763848 in-data: 18 20 20 08 00 00 00 00
497 11:46:54.767606 MRC: failed to locate region type 0.
498 11:46:54.774933 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:46:54.778725 DRAM-K: Running full calibration
500 11:46:54.782295 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:46:54.786299 header.status = 0x0
502 11:46:54.789514 header.version = 0x6 (expected: 0x6)
503 11:46:54.793352 header.size = 0xd00 (expected: 0xd00)
504 11:46:54.793430 header.flags = 0x0
505 11:46:54.800620 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:46:54.817977 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 11:46:54.825859 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:46:54.829169 dram_init: ddr_geometry: 2
509 11:46:54.829246 [EMI] MDL number = 2
510 11:46:54.833098 [EMI] Get MDL freq = 0
511 11:46:54.833171 dram_init: ddr_type: 0
512 11:46:54.836953 is_discrete_lpddr4: 1
513 11:46:54.840513 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:46:54.840613
515 11:46:54.840704
516 11:46:54.840803 [Bian_co] ETT version 0.0.0.1
517 11:46:54.848415 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:46:54.848516
519 11:46:54.852214 dramc_set_vcore_voltage set vcore to 650000
520 11:46:54.852320 Read voltage for 800, 4
521 11:46:54.852412 Vio18 = 0
522 11:46:54.855978 Vcore = 650000
523 11:46:54.856074 Vdram = 0
524 11:46:54.856171 Vddq = 0
525 11:46:54.859729 Vmddr = 0
526 11:46:54.859828 dram_init: config_dvfs: 1
527 11:46:54.867234 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:46:54.870469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:46:54.874543 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 11:46:54.878074 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 11:46:54.881693 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 11:46:54.885662 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 11:46:54.888833 MEM_TYPE=3, freq_sel=18
534 11:46:54.891748 sv_algorithm_assistance_LP4_1600
535 11:46:54.895664 ============ PULL DRAM RESETB DOWN ============
536 11:46:54.898956 ========== PULL DRAM RESETB DOWN end =========
537 11:46:54.905509 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:46:54.909263 ===================================
539 11:46:54.909361 LPDDR4 DRAM CONFIGURATION
540 11:46:54.913259 ===================================
541 11:46:54.916510 EX_ROW_EN[0] = 0x0
542 11:46:54.916626 EX_ROW_EN[1] = 0x0
543 11:46:54.920556 LP4Y_EN = 0x0
544 11:46:54.920653 WORK_FSP = 0x0
545 11:46:54.920743 WL = 0x2
546 11:46:54.924556 RL = 0x2
547 11:46:54.924656 BL = 0x2
548 11:46:54.927696 RPST = 0x0
549 11:46:54.927774 RD_PRE = 0x0
550 11:46:54.930929 WR_PRE = 0x1
551 11:46:54.931030 WR_PST = 0x0
552 11:46:54.934790 DBI_WR = 0x0
553 11:46:54.934865 DBI_RD = 0x0
554 11:46:54.937978 OTF = 0x1
555 11:46:54.941454 ===================================
556 11:46:54.944564 ===================================
557 11:46:54.944660 ANA top config
558 11:46:54.947817 ===================================
559 11:46:54.951020 DLL_ASYNC_EN = 0
560 11:46:54.954551 ALL_SLAVE_EN = 1
561 11:46:54.957902 NEW_RANK_MODE = 1
562 11:46:54.958002 DLL_IDLE_MODE = 1
563 11:46:54.961168 LP45_APHY_COMB_EN = 1
564 11:46:54.964421 TX_ODT_DIS = 1
565 11:46:54.968950 NEW_8X_MODE = 1
566 11:46:54.969051 ===================================
567 11:46:54.972073 ===================================
568 11:46:54.975147 data_rate = 1600
569 11:46:54.978396 CKR = 1
570 11:46:54.982164 DQ_P2S_RATIO = 8
571 11:46:54.985113 ===================================
572 11:46:54.988723 CA_P2S_RATIO = 8
573 11:46:54.991880 DQ_CA_OPEN = 0
574 11:46:54.991977 DQ_SEMI_OPEN = 0
575 11:46:54.995712 CA_SEMI_OPEN = 0
576 11:46:54.998807 CA_FULL_RATE = 0
577 11:46:55.001739 DQ_CKDIV4_EN = 1
578 11:46:55.005447 CA_CKDIV4_EN = 1
579 11:46:55.008534 CA_PREDIV_EN = 0
580 11:46:55.008634 PH8_DLY = 0
581 11:46:55.011788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:46:55.015027 DQ_AAMCK_DIV = 4
583 11:46:55.018905 CA_AAMCK_DIV = 4
584 11:46:55.022109 CA_ADMCK_DIV = 4
585 11:46:55.025390 DQ_TRACK_CA_EN = 0
586 11:46:55.025489 CA_PICK = 800
587 11:46:55.029255 CA_MCKIO = 800
588 11:46:55.032616 MCKIO_SEMI = 0
589 11:46:55.036509 PLL_FREQ = 3068
590 11:46:55.036583 DQ_UI_PI_RATIO = 32
591 11:46:55.040524 CA_UI_PI_RATIO = 0
592 11:46:55.043863 ===================================
593 11:46:55.047888 ===================================
594 11:46:55.051221 memory_type:LPDDR4
595 11:46:55.051292 GP_NUM : 10
596 11:46:55.055204 SRAM_EN : 1
597 11:46:55.055279 MD32_EN : 0
598 11:46:55.059177 ===================================
599 11:46:55.062885 [ANA_INIT] >>>>>>>>>>>>>>
600 11:46:55.065915 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:46:55.069521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:46:55.072838 ===================================
603 11:46:55.072946 data_rate = 1600,PCW = 0X7600
604 11:46:55.075906 ===================================
605 11:46:55.079755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:46:55.085962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:46:55.092915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:46:55.095890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:46:55.099256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:46:55.102589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:46:55.106417 [ANA_INIT] flow start
612 11:46:55.106497 [ANA_INIT] PLL >>>>>>>>
613 11:46:55.109444 [ANA_INIT] PLL <<<<<<<<
614 11:46:55.112504 [ANA_INIT] MIDPI >>>>>>>>
615 11:46:55.116023 [ANA_INIT] MIDPI <<<<<<<<
616 11:46:55.116121 [ANA_INIT] DLL >>>>>>>>
617 11:46:55.119386 [ANA_INIT] flow end
618 11:46:55.122633 ============ LP4 DIFF to SE enter ============
619 11:46:55.126386 ============ LP4 DIFF to SE exit ============
620 11:46:55.129571 [ANA_INIT] <<<<<<<<<<<<<
621 11:46:55.132771 [Flow] Enable top DCM control >>>>>
622 11:46:55.136039 [Flow] Enable top DCM control <<<<<
623 11:46:55.139395 Enable DLL master slave shuffle
624 11:46:55.142751 ==============================================================
625 11:46:55.146493 Gating Mode config
626 11:46:55.153031 ==============================================================
627 11:46:55.153127 Config description:
628 11:46:55.163306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:46:55.169816 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:46:55.173054 SELPH_MODE 0: By rank 1: By Phase
631 11:46:55.179804 ==============================================================
632 11:46:55.183249 GAT_TRACK_EN = 1
633 11:46:55.186846 RX_GATING_MODE = 2
634 11:46:55.190181 RX_GATING_TRACK_MODE = 2
635 11:46:55.192931 SELPH_MODE = 1
636 11:46:55.196219 PICG_EARLY_EN = 1
637 11:46:55.200095 VALID_LAT_VALUE = 1
638 11:46:55.203082 ==============================================================
639 11:46:55.206643 Enter into Gating configuration >>>>
640 11:46:55.209718 Exit from Gating configuration <<<<
641 11:46:55.213463 Enter into DVFS_PRE_config >>>>>
642 11:46:55.223283 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:46:55.226757 Exit from DVFS_PRE_config <<<<<
644 11:46:55.230420 Enter into PICG configuration >>>>
645 11:46:55.233606 Exit from PICG configuration <<<<
646 11:46:55.236670 [RX_INPUT] configuration >>>>>
647 11:46:55.239812 [RX_INPUT] configuration <<<<<
648 11:46:55.243117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:46:55.250250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:46:55.256797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:46:55.263233 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:46:55.270485 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:46:55.273817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:46:55.280290 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:46:55.283468 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:46:55.286762 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:46:55.289941 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:46:55.296892 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:46:55.299997 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:46:55.303832 ===================================
661 11:46:55.306897 LPDDR4 DRAM CONFIGURATION
662 11:46:55.310274 ===================================
663 11:46:55.310358 EX_ROW_EN[0] = 0x0
664 11:46:55.313541 EX_ROW_EN[1] = 0x0
665 11:46:55.313654 LP4Y_EN = 0x0
666 11:46:55.316818 WORK_FSP = 0x0
667 11:46:55.316922 WL = 0x2
668 11:46:55.320008 RL = 0x2
669 11:46:55.320108 BL = 0x2
670 11:46:55.323445 RPST = 0x0
671 11:46:55.323518 RD_PRE = 0x0
672 11:46:55.326902 WR_PRE = 0x1
673 11:46:55.327004 WR_PST = 0x0
674 11:46:55.330463 DBI_WR = 0x0
675 11:46:55.330536 DBI_RD = 0x0
676 11:46:55.333948 OTF = 0x1
677 11:46:55.336877 ===================================
678 11:46:55.340129 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:46:55.343859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:46:55.350414 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:46:55.353739 ===================================
682 11:46:55.353812 LPDDR4 DRAM CONFIGURATION
683 11:46:55.357743 ===================================
684 11:46:55.360335 EX_ROW_EN[0] = 0x10
685 11:46:55.363643 EX_ROW_EN[1] = 0x0
686 11:46:55.363743 LP4Y_EN = 0x0
687 11:46:55.367624 WORK_FSP = 0x0
688 11:46:55.367714 WL = 0x2
689 11:46:55.370804 RL = 0x2
690 11:46:55.370908 BL = 0x2
691 11:46:55.374204 RPST = 0x0
692 11:46:55.374276 RD_PRE = 0x0
693 11:46:55.377508 WR_PRE = 0x1
694 11:46:55.377646 WR_PST = 0x0
695 11:46:55.380699 DBI_WR = 0x0
696 11:46:55.380794 DBI_RD = 0x0
697 11:46:55.383904 OTF = 0x1
698 11:46:55.387204 ===================================
699 11:46:55.390946 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:46:55.396647 nWR fixed to 40
701 11:46:55.399908 [ModeRegInit_LP4] CH0 RK0
702 11:46:55.400009 [ModeRegInit_LP4] CH0 RK1
703 11:46:55.402996 [ModeRegInit_LP4] CH1 RK0
704 11:46:55.406610 [ModeRegInit_LP4] CH1 RK1
705 11:46:55.406699 match AC timing 13
706 11:46:55.413145 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:46:55.416497 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:46:55.419572 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:46:55.426419 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:46:55.429856 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:46:55.429932 [EMI DOE] emi_dcm 0
712 11:46:55.436168 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:46:55.436269 ==
714 11:46:55.439519 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:46:55.442904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:46:55.442991 ==
717 11:46:55.450026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:46:55.452982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:46:55.463906 [CA 0] Center 36 (6~67) winsize 62
720 11:46:55.467095 [CA 1] Center 36 (6~67) winsize 62
721 11:46:55.470100 [CA 2] Center 34 (4~65) winsize 62
722 11:46:55.473860 [CA 3] Center 33 (3~64) winsize 62
723 11:46:55.477105 [CA 4] Center 33 (3~63) winsize 61
724 11:46:55.480276 [CA 5] Center 32 (3~62) winsize 60
725 11:46:55.480386
726 11:46:55.483515 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:46:55.483616
728 11:46:55.486852 [CATrainingPosCal] consider 1 rank data
729 11:46:55.490676 u2DelayCellTimex100 = 270/100 ps
730 11:46:55.493842 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 11:46:55.497496 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 11:46:55.500796 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 11:46:55.507424 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 11:46:55.510447 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 11:46:55.514380 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 11:46:55.514483
737 11:46:55.517669 CA PerBit enable=1, Macro0, CA PI delay=32
738 11:46:55.517770
739 11:46:55.520917 [CBTSetCACLKResult] CA Dly = 32
740 11:46:55.520994 CS Dly: 4 (0~35)
741 11:46:55.521086 ==
742 11:46:55.524129 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:46:55.530546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:46:55.530648 ==
745 11:46:55.533815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:46:55.540702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:46:55.549522 [CA 0] Center 36 (6~67) winsize 62
748 11:46:55.552966 [CA 1] Center 36 (6~67) winsize 62
749 11:46:55.556288 [CA 2] Center 34 (3~65) winsize 63
750 11:46:55.559839 [CA 3] Center 34 (3~65) winsize 63
751 11:46:55.563252 [CA 4] Center 33 (3~63) winsize 61
752 11:46:55.566584 [CA 5] Center 32 (2~63) winsize 62
753 11:46:55.566659
754 11:46:55.569637 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:46:55.569748
756 11:46:55.573079 [CATrainingPosCal] consider 2 rank data
757 11:46:55.576695 u2DelayCellTimex100 = 270/100 ps
758 11:46:55.579920 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 11:46:55.583120 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 11:46:55.589964 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 11:46:55.593116 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 11:46:55.596490 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 11:46:55.599697 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 11:46:55.599798
765 11:46:55.603447 CA PerBit enable=1, Macro0, CA PI delay=32
766 11:46:55.603544
767 11:46:55.606616 [CBTSetCACLKResult] CA Dly = 32
768 11:46:55.606687 CS Dly: 5 (0~37)
769 11:46:55.606748
770 11:46:55.610580 ----->DramcWriteLeveling(PI) begin...
771 11:46:55.610654 ==
772 11:46:55.614491 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:46:55.617664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:46:55.617769 ==
775 11:46:55.621487 Write leveling (Byte 0): 31 => 31
776 11:46:55.625350 Write leveling (Byte 1): 30 => 30
777 11:46:55.628700 DramcWriteLeveling(PI) end<-----
778 11:46:55.628807
779 11:46:55.628898 ==
780 11:46:55.632017 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:46:55.635162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:46:55.635234 ==
783 11:46:55.638850 [Gating] SW mode calibration
784 11:46:55.645439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:46:55.652495 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:46:55.655980 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:46:55.659157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:46:55.665579 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:46:55.669489 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:46:55.672472 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:46:55.678965 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:46:55.682871 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:46:55.685963 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:46:55.689086 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:46:55.695668 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:46:55.699321 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:46:55.702598 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:46:55.709042 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:46:55.713025 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:46:55.716150 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:46:55.722523 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:46:55.726314 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:46:55.729538 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:46:55.736147 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
805 11:46:55.739299 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 11:46:55.742658 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:46:55.748879 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:46:55.752410 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:46:55.755676 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:46:55.762835 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:46:55.766106 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
812 11:46:55.769105 0 9 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
813 11:46:55.775958 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 11:46:55.779112 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:46:55.782687 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:46:55.786154 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:46:55.792561 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:46:55.795743 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:46:55.799437 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 11:46:55.806488 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
821 11:46:55.809322 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:46:55.812648 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:46:55.819086 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:46:55.822434 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:46:55.826344 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:46:55.832501 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:46:55.836461 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
828 11:46:55.839683 0 11 8 | B1->B0 | 2c2c 3f3f | 0 1 | (0 0) (0 0)
829 11:46:55.842973 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
830 11:46:55.849635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:46:55.852728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:46:55.856402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:46:55.863047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:46:55.866509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:46:55.869431 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:46:55.876447 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 11:46:55.879411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 11:46:55.883383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:46:55.889608 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:46:55.893297 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:46:55.896312 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:46:55.903604 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:46:55.906539 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:46:55.909752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:46:55.916486 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:46:55.920103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:46:55.923612 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:46:55.926599 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:46:55.933131 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:46:55.936873 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:46:55.940165 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:46:55.946691 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:46:55.946791 Total UI for P1: 0, mck2ui 16
854 11:46:55.953277 best dqsien dly found for B0: ( 0, 14, 4)
855 11:46:55.956584 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:46:55.959813 Total UI for P1: 0, mck2ui 16
857 11:46:55.963645 best dqsien dly found for B1: ( 0, 14, 8)
858 11:46:55.967363 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:46:55.970606 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:46:55.970684
861 11:46:55.974104 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:46:55.977552 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:46:55.980630 [Gating] SW calibration Done
864 11:46:55.980735 ==
865 11:46:55.984282 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:46:55.987256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:46:55.987355 ==
868 11:46:55.990620 RX Vref Scan: 0
869 11:46:55.990688
870 11:46:55.990752 RX Vref 0 -> 0, step: 1
871 11:46:55.990811
872 11:46:55.994516 RX Delay -130 -> 252, step: 16
873 11:46:55.997680 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 11:46:56.004503 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 11:46:56.007531 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 11:46:56.011339 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 11:46:56.014239 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 11:46:56.017529 iDelay=222, Bit 5, Center 85 (-18 ~ 189) 208
879 11:46:56.024299 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:46:56.027829 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 11:46:56.030780 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 11:46:56.034772 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 11:46:56.038124 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 11:46:56.044479 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 11:46:56.047924 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 11:46:56.051180 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 11:46:56.054603 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 11:46:56.057915 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 11:46:56.058014 ==
890 11:46:56.061181 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:46:56.067549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:46:56.067650 ==
893 11:46:56.067742 DQS Delay:
894 11:46:56.071435 DQS0 = 0, DQS1 = 0
895 11:46:56.071506 DQM Delay:
896 11:46:56.071565 DQM0 = 94, DQM1 = 86
897 11:46:56.074704 DQ Delay:
898 11:46:56.077973 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 11:46:56.081116 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
900 11:46:56.085054 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 11:46:56.088072 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 11:46:56.088172
903 11:46:56.088261
904 11:46:56.088347 ==
905 11:46:56.106731 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:46:56.106848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:46:56.106918 ==
908 11:46:56.106993
909 11:46:56.107081
910 11:46:56.107168 TX Vref Scan disable
911 11:46:56.107256 == TX Byte 0 ==
912 11:46:56.107341 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 11:46:56.108171 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 11:46:56.108265 == TX Byte 1 ==
915 11:46:56.114739 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 11:46:56.117990 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 11:46:56.118092 ==
918 11:46:56.121560 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:46:56.124724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:46:56.124799 ==
921 11:46:56.138557 TX Vref=22, minBit 7, minWin=27, winSum=443
922 11:46:56.141852 TX Vref=24, minBit 8, minWin=27, winSum=452
923 11:46:56.145692 TX Vref=26, minBit 0, minWin=28, winSum=456
924 11:46:56.148830 TX Vref=28, minBit 8, minWin=28, winSum=459
925 11:46:56.152091 TX Vref=30, minBit 8, minWin=28, winSum=459
926 11:46:56.155457 TX Vref=32, minBit 8, minWin=28, winSum=456
927 11:46:56.162720 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
928 11:46:56.162829
929 11:46:56.165401 Final TX Range 1 Vref 28
930 11:46:56.165500
931 11:46:56.165633 ==
932 11:46:56.168733 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:46:56.172529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:46:56.172636 ==
935 11:46:56.172728
936 11:46:56.172814
937 11:46:56.175877 TX Vref Scan disable
938 11:46:56.179016 == TX Byte 0 ==
939 11:46:56.182456 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 11:46:56.185686 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 11:46:56.189029 == TX Byte 1 ==
942 11:46:56.192201 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 11:46:56.195517 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 11:46:56.195620
945 11:46:56.198824 [DATLAT]
946 11:46:56.198950 Freq=800, CH0 RK0
947 11:46:56.199046
948 11:46:56.202167 DATLAT Default: 0xa
949 11:46:56.202272 0, 0xFFFF, sum = 0
950 11:46:56.205373 1, 0xFFFF, sum = 0
951 11:46:56.205557 2, 0xFFFF, sum = 0
952 11:46:56.208573 3, 0xFFFF, sum = 0
953 11:46:56.208674 4, 0xFFFF, sum = 0
954 11:46:56.212135 5, 0xFFFF, sum = 0
955 11:46:56.212236 6, 0xFFFF, sum = 0
956 11:46:56.215349 7, 0xFFFF, sum = 0
957 11:46:56.215449 8, 0xFFFF, sum = 0
958 11:46:56.219130 9, 0x0, sum = 1
959 11:46:56.219228 10, 0x0, sum = 2
960 11:46:56.222566 11, 0x0, sum = 3
961 11:46:56.222637 12, 0x0, sum = 4
962 11:46:56.225852 best_step = 10
963 11:46:56.225937
964 11:46:56.225999 ==
965 11:46:56.228833 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:46:56.232535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:46:56.232634 ==
968 11:46:56.235531 RX Vref Scan: 1
969 11:46:56.235630
970 11:46:56.235729 Set Vref Range= 32 -> 127
971 11:46:56.235817
972 11:46:56.239077 RX Vref 32 -> 127, step: 1
973 11:46:56.239184
974 11:46:56.242090 RX Delay -79 -> 252, step: 8
975 11:46:56.242160
976 11:46:56.245612 Set Vref, RX VrefLevel [Byte0]: 32
977 11:46:56.248798 [Byte1]: 32
978 11:46:56.248896
979 11:46:56.252570 Set Vref, RX VrefLevel [Byte0]: 33
980 11:46:56.255684 [Byte1]: 33
981 11:46:56.258929
982 11:46:56.259034 Set Vref, RX VrefLevel [Byte0]: 34
983 11:46:56.262162 [Byte1]: 34
984 11:46:56.266646
985 11:46:56.266721 Set Vref, RX VrefLevel [Byte0]: 35
986 11:46:56.269925 [Byte1]: 35
987 11:46:56.274567
988 11:46:56.274666 Set Vref, RX VrefLevel [Byte0]: 36
989 11:46:56.278255 [Byte1]: 36
990 11:46:56.281630
991 11:46:56.281702 Set Vref, RX VrefLevel [Byte0]: 37
992 11:46:56.285651 [Byte1]: 37
993 11:46:56.289721
994 11:46:56.289793 Set Vref, RX VrefLevel [Byte0]: 38
995 11:46:56.293204 [Byte1]: 38
996 11:46:56.296900
997 11:46:56.297022 Set Vref, RX VrefLevel [Byte0]: 39
998 11:46:56.300068 [Byte1]: 39
999 11:46:56.304756
1000 11:46:56.304831 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:46:56.307992 [Byte1]: 40
1002 11:46:56.311947
1003 11:46:56.312048 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:46:56.315235 [Byte1]: 41
1005 11:46:56.319008
1006 11:46:56.319102 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:46:56.322807 [Byte1]: 42
1008 11:46:56.326587
1009 11:46:56.326681 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:46:56.330496 [Byte1]: 43
1011 11:46:56.334458
1012 11:46:56.334525 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:46:56.337430 [Byte1]: 44
1014 11:46:56.342108
1015 11:46:56.342179 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:46:56.345227 [Byte1]: 45
1017 11:46:56.349279
1018 11:46:56.349348 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:46:56.352904 [Byte1]: 46
1020 11:46:56.356997
1021 11:46:56.357063 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:46:56.360498 [Byte1]: 47
1023 11:46:56.364788
1024 11:46:56.364868 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:46:56.367888 [Byte1]: 48
1026 11:46:56.372448
1027 11:46:56.372546 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:46:56.375566 [Byte1]: 49
1029 11:46:56.379332
1030 11:46:56.379436 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:46:56.383161 [Byte1]: 50
1032 11:46:56.387226
1033 11:46:56.387324 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:46:56.390592 [Byte1]: 51
1035 11:46:56.394476
1036 11:46:56.394574 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:46:56.398412 [Byte1]: 52
1038 11:46:56.402174
1039 11:46:56.402277 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:46:56.406079 [Byte1]: 53
1041 11:46:56.409719
1042 11:46:56.409824 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:46:56.413169 [Byte1]: 54
1044 11:46:56.417667
1045 11:46:56.417762 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:46:56.420615 [Byte1]: 55
1047 11:46:56.425083
1048 11:46:56.425189 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:46:56.428242 [Byte1]: 56
1050 11:46:56.432951
1051 11:46:56.433074 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:46:56.436092 [Byte1]: 57
1053 11:46:56.440026
1054 11:46:56.440134 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:46:56.443149 [Byte1]: 58
1056 11:46:56.447479
1057 11:46:56.447587 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:46:56.450650 [Byte1]: 59
1059 11:46:56.455501
1060 11:46:56.455608 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:46:56.458516 [Byte1]: 60
1062 11:46:56.462839
1063 11:46:56.462938 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:46:56.465942 [Byte1]: 61
1065 11:46:56.470362
1066 11:46:56.470469 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:46:56.473536 [Byte1]: 62
1068 11:46:56.477784
1069 11:46:56.477884 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:46:56.480842 [Byte1]: 63
1071 11:46:56.485625
1072 11:46:56.485735 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:46:56.488880 [Byte1]: 64
1074 11:46:56.492797
1075 11:46:56.492898 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:46:56.496051 [Byte1]: 65
1077 11:46:56.500616
1078 11:46:56.500724 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:46:56.503975 [Byte1]: 66
1080 11:46:56.507770
1081 11:46:56.507866 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:46:56.511588 [Byte1]: 67
1083 11:46:56.515710
1084 11:46:56.515811 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:46:56.519021 [Byte1]: 68
1086 11:46:56.522996
1087 11:46:56.523094 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:46:56.526630 [Byte1]: 69
1089 11:46:56.530592
1090 11:46:56.530688 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:46:56.534234 [Byte1]: 70
1092 11:46:56.538258
1093 11:46:56.538345 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:46:56.541408 [Byte1]: 71
1095 11:46:56.545694
1096 11:46:56.545763 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:46:56.548947 [Byte1]: 72
1098 11:46:56.553492
1099 11:46:56.553606 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:46:56.556572 [Byte1]: 73
1101 11:46:56.560859
1102 11:46:56.560953 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:46:56.563858 [Byte1]: 74
1104 11:46:56.568566
1105 11:46:56.568668 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:46:56.571788 [Byte1]: 75
1107 11:46:56.576245
1108 11:46:56.576320 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:46:56.579468 [Byte1]: 76
1110 11:46:56.583303
1111 11:46:56.583397 Set Vref, RX VrefLevel [Byte0]: 77
1112 11:46:56.586910 [Byte1]: 77
1113 11:46:56.591009
1114 11:46:56.591078 Set Vref, RX VrefLevel [Byte0]: 78
1115 11:46:56.594399 [Byte1]: 78
1116 11:46:56.598391
1117 11:46:56.598458 Set Vref, RX VrefLevel [Byte0]: 79
1118 11:46:56.602030 [Byte1]: 79
1119 11:46:56.605914
1120 11:46:56.605982 Final RX Vref Byte 0 = 55 to rank0
1121 11:46:56.610002 Final RX Vref Byte 1 = 56 to rank0
1122 11:46:56.612969 Final RX Vref Byte 0 = 55 to rank1
1123 11:46:56.616399 Final RX Vref Byte 1 = 56 to rank1==
1124 11:46:56.619706 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 11:46:56.626287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 11:46:56.626370 ==
1127 11:46:56.626433 DQS Delay:
1128 11:46:56.626492 DQS0 = 0, DQS1 = 0
1129 11:46:56.629415 DQM Delay:
1130 11:46:56.629512 DQM0 = 92, DQM1 = 85
1131 11:46:56.633316 DQ Delay:
1132 11:46:56.636365 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 11:46:56.636441 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 11:46:56.639654 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =80
1135 11:46:56.642920 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 11:46:56.646084
1137 11:46:56.646169
1138 11:46:56.653066 [DQSOSCAuto] RK0, (LSB)MR18= 0x5147, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1139 11:46:56.656221 CH0 RK0: MR19=606, MR18=5147
1140 11:46:56.663192 CH0_RK0: MR19=0x606, MR18=0x5147, DQSOSC=389, MR23=63, INC=97, DEC=65
1141 11:46:56.663301
1142 11:46:56.666420 ----->DramcWriteLeveling(PI) begin...
1143 11:46:56.666510 ==
1144 11:46:56.670161 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 11:46:56.673231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 11:46:56.673338 ==
1147 11:46:56.676896 Write leveling (Byte 0): 34 => 34
1148 11:46:56.679907 Write leveling (Byte 1): 31 => 31
1149 11:46:56.683137 DramcWriteLeveling(PI) end<-----
1150 11:46:56.683254
1151 11:46:56.683364 ==
1152 11:46:56.727190 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 11:46:56.727314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 11:46:56.727407 ==
1155 11:46:56.727807 [Gating] SW mode calibration
1156 11:46:56.728088 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 11:46:56.728193 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 11:46:56.728305 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 11:46:56.728409 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1160 11:46:56.728517 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 11:46:56.728606 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:46:56.729168 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:46:56.742734 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:46:56.743061 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:46:56.746018 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:46:56.746117 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:46:56.749248 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:46:56.752941 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:46:56.759255 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:46:56.762928 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:46:56.766183 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:46:56.769527 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:46:56.776662 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:46:56.779897 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:46:56.782877 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:46:56.789699 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 11:46:56.792899 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:46:56.796202 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:46:56.803227 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:46:56.806598 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:46:56.809748 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:46:56.816970 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:46:56.819512 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:46:56.822906 0 9 8 | B1->B0 | 2f2f 2f2e | 1 1 | (1 1) (0 0)
1185 11:46:56.830016 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:46:56.833054 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:46:56.836410 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:46:56.843183 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 11:46:56.846211 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 11:46:56.849931 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 11:46:56.853427 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1192 11:46:56.860814 0 10 8 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
1193 11:46:56.864656 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:46:56.867773 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:46:56.871115 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:46:56.877542 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:46:56.881287 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:46:56.885196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:46:56.888446 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1200 11:46:56.895247 0 11 8 | B1->B0 | 3e3e 4040 | 0 0 | (1 1) (0 0)
1201 11:46:56.898460 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:46:56.901682 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:46:56.908254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:46:56.911443 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:46:56.915404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 11:46:56.921999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:46:56.925325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:46:56.928583 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 11:46:56.935265 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:46:56.938468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:46:56.941690 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:46:56.945087 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:46:56.952231 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:46:56.955348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:46:56.958960 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:46:56.965059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:46:56.968773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:46:56.972185 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:46:56.978426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:46:56.982300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:46:56.985534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:46:56.992467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:46:56.995672 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:46:56.998723 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 11:46:57.005415 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 11:46:57.005537 Total UI for P1: 0, mck2ui 16
1227 11:46:57.009234 best dqsien dly found for B0: ( 0, 14, 8)
1228 11:46:57.012547 Total UI for P1: 0, mck2ui 16
1229 11:46:57.015682 best dqsien dly found for B1: ( 0, 14, 8)
1230 11:46:57.019053 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 11:46:57.022292 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 11:46:57.025533
1233 11:46:57.028858 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 11:46:57.032277 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 11:46:57.035465 [Gating] SW calibration Done
1236 11:46:57.035569 ==
1237 11:46:57.039200 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 11:46:57.042647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 11:46:57.042730 ==
1240 11:46:57.042792 RX Vref Scan: 0
1241 11:46:57.042850
1242 11:46:57.045910 RX Vref 0 -> 0, step: 1
1243 11:46:57.046003
1244 11:46:57.049102 RX Delay -130 -> 252, step: 16
1245 11:46:57.052394 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1246 11:46:57.055742 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 11:46:57.062290 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1248 11:46:57.066065 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1249 11:46:57.069352 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 11:46:57.072449 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1251 11:46:57.075541 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1252 11:46:57.082236 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1253 11:46:57.086019 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1254 11:46:57.089181 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1255 11:46:57.092433 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1256 11:46:57.095798 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 11:46:57.099081 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1258 11:46:57.106168 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1259 11:46:57.108968 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 11:46:57.112542 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1261 11:46:57.112641 ==
1262 11:46:57.115747 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 11:46:57.119243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 11:46:57.122358 ==
1265 11:46:57.122457 DQS Delay:
1266 11:46:57.122556 DQS0 = 0, DQS1 = 0
1267 11:46:57.126159 DQM Delay:
1268 11:46:57.126261 DQM0 = 90, DQM1 = 80
1269 11:46:57.129498 DQ Delay:
1270 11:46:57.129567 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1271 11:46:57.132719 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1272 11:46:57.136006 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1273 11:46:57.139169 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1274 11:46:57.139238
1275 11:46:57.142643
1276 11:46:57.142709 ==
1277 11:46:57.145827 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 11:46:57.149766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 11:46:57.149833 ==
1280 11:46:57.149890
1281 11:46:57.149945
1282 11:46:57.152871 TX Vref Scan disable
1283 11:46:57.152964 == TX Byte 0 ==
1284 11:46:57.159774 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1285 11:46:57.162757 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1286 11:46:57.162824 == TX Byte 1 ==
1287 11:46:57.169248 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1288 11:46:57.172475 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1289 11:46:57.172578 ==
1290 11:46:57.176486 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:46:57.179045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:46:57.179114 ==
1293 11:46:57.193151 TX Vref=22, minBit 12, minWin=26, winSum=448
1294 11:46:57.196483 TX Vref=24, minBit 10, minWin=27, winSum=452
1295 11:46:57.199738 TX Vref=26, minBit 1, minWin=28, winSum=455
1296 11:46:57.202812 TX Vref=28, minBit 3, minWin=28, winSum=454
1297 11:46:57.206036 TX Vref=30, minBit 10, minWin=27, winSum=452
1298 11:46:57.213031 TX Vref=32, minBit 8, minWin=27, winSum=450
1299 11:46:57.216387 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 26
1300 11:46:57.216490
1301 11:46:57.219547 Final TX Range 1 Vref 26
1302 11:46:57.219644
1303 11:46:57.219741 ==
1304 11:46:57.223423 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 11:46:57.226311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 11:46:57.226412 ==
1307 11:46:57.229760
1308 11:46:57.229841
1309 11:46:57.229903 TX Vref Scan disable
1310 11:46:57.233191 == TX Byte 0 ==
1311 11:46:57.236672 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1312 11:46:57.239937 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1313 11:46:57.243102 == TX Byte 1 ==
1314 11:46:57.246501 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1315 11:46:57.249826 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1316 11:46:57.253074
1317 11:46:57.253169 [DATLAT]
1318 11:46:57.253258 Freq=800, CH0 RK1
1319 11:46:57.253343
1320 11:46:57.256349 DATLAT Default: 0xa
1321 11:46:57.256444 0, 0xFFFF, sum = 0
1322 11:46:57.260259 1, 0xFFFF, sum = 0
1323 11:46:57.260356 2, 0xFFFF, sum = 0
1324 11:46:57.263599 3, 0xFFFF, sum = 0
1325 11:46:57.263692 4, 0xFFFF, sum = 0
1326 11:46:57.266755 5, 0xFFFF, sum = 0
1327 11:46:57.266822 6, 0xFFFF, sum = 0
1328 11:46:57.270052 7, 0xFFFF, sum = 0
1329 11:46:57.273231 8, 0xFFFF, sum = 0
1330 11:46:57.273306 9, 0x0, sum = 1
1331 11:46:57.273367 10, 0x0, sum = 2
1332 11:46:57.276395 11, 0x0, sum = 3
1333 11:46:57.276471 12, 0x0, sum = 4
1334 11:46:57.279518 best_step = 10
1335 11:46:57.279589
1336 11:46:57.279653 ==
1337 11:46:57.282880 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 11:46:57.286612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 11:46:57.286712 ==
1340 11:46:57.289908 RX Vref Scan: 0
1341 11:46:57.289979
1342 11:46:57.290039 RX Vref 0 -> 0, step: 1
1343 11:46:57.290096
1344 11:46:57.293062 RX Delay -95 -> 252, step: 8
1345 11:46:57.299677 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 11:46:57.302898 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 11:46:57.306271 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 11:46:57.310000 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 11:46:57.312992 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 11:46:57.319586 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1351 11:46:57.323290 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 11:46:57.326710 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 11:46:57.329932 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1354 11:46:57.333031 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1355 11:46:57.339676 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 11:46:57.343417 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 11:46:57.346386 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1358 11:46:57.350070 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1359 11:46:57.353055 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 11:46:57.359976 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 11:46:57.360080 ==
1362 11:46:57.363526 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:46:57.366481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:46:57.366558 ==
1365 11:46:57.366638 DQS Delay:
1366 11:46:57.370076 DQS0 = 0, DQS1 = 0
1367 11:46:57.370151 DQM Delay:
1368 11:46:57.373467 DQM0 = 93, DQM1 = 84
1369 11:46:57.373567 DQ Delay:
1370 11:46:57.376833 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1371 11:46:57.379913 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1372 11:46:57.383137 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1373 11:46:57.386877 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1374 11:46:57.386973
1375 11:46:57.387062
1376 11:46:57.393012 [DQSOSCAuto] RK1, (LSB)MR18= 0x4616, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1377 11:46:57.396823 CH0 RK1: MR19=606, MR18=4616
1378 11:46:57.403648 CH0_RK1: MR19=0x606, MR18=0x4616, DQSOSC=392, MR23=63, INC=96, DEC=64
1379 11:46:57.406826 [RxdqsGatingPostProcess] freq 800
1380 11:46:57.413441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 11:46:57.416683 Pre-setting of DQS Precalculation
1382 11:46:57.419900 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 11:46:57.419995 ==
1384 11:46:57.423610 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 11:46:57.426893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 11:46:57.426998 ==
1387 11:46:57.433683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 11:46:57.440091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 11:46:57.447955 [CA 0] Center 36 (6~67) winsize 62
1390 11:46:57.451387 [CA 1] Center 36 (6~67) winsize 62
1391 11:46:57.454905 [CA 2] Center 34 (4~65) winsize 62
1392 11:46:57.457994 [CA 3] Center 34 (4~65) winsize 62
1393 11:46:57.461855 [CA 4] Center 35 (5~65) winsize 61
1394 11:46:57.464830 [CA 5] Center 34 (4~65) winsize 62
1395 11:46:57.464935
1396 11:46:57.468075 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 11:46:57.468177
1398 11:46:57.471231 [CATrainingPosCal] consider 1 rank data
1399 11:46:57.474690 u2DelayCellTimex100 = 270/100 ps
1400 11:46:57.478131 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 11:46:57.481156 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 11:46:57.487820 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 11:46:57.491417 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 11:46:57.494624 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1405 11:46:57.498442 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 11:46:57.498541
1407 11:46:57.501762 CA PerBit enable=1, Macro0, CA PI delay=34
1408 11:46:57.501847
1409 11:46:57.504849 [CBTSetCACLKResult] CA Dly = 34
1410 11:46:57.504946 CS Dly: 6 (0~37)
1411 11:46:57.505044 ==
1412 11:46:57.508187 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 11:46:57.515380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 11:46:57.515478 ==
1415 11:46:57.518581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 11:46:57.525396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 11:46:57.534359 [CA 0] Center 36 (6~67) winsize 62
1418 11:46:57.538475 [CA 1] Center 36 (6~67) winsize 62
1419 11:46:57.541748 [CA 2] Center 35 (4~66) winsize 63
1420 11:46:57.545221 [CA 3] Center 34 (4~65) winsize 62
1421 11:46:57.549177 [CA 4] Center 35 (5~65) winsize 61
1422 11:46:57.553077 [CA 5] Center 34 (4~65) winsize 62
1423 11:46:57.553171
1424 11:46:57.556240 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 11:46:57.556340
1426 11:46:57.559302 [CATrainingPosCal] consider 2 rank data
1427 11:46:57.562768 u2DelayCellTimex100 = 270/100 ps
1428 11:46:57.566094 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 11:46:57.569481 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 11:46:57.572775 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 11:46:57.576231 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 11:46:57.579204 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 11:46:57.582617 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 11:46:57.582715
1435 11:46:57.586429 CA PerBit enable=1, Macro0, CA PI delay=34
1436 11:46:57.586498
1437 11:46:57.589506 [CBTSetCACLKResult] CA Dly = 34
1438 11:46:57.592651 CS Dly: 6 (0~38)
1439 11:46:57.592746
1440 11:46:57.596309 ----->DramcWriteLeveling(PI) begin...
1441 11:46:57.596405 ==
1442 11:46:57.599986 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:46:57.603169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:46:57.603276 ==
1445 11:46:57.606319 Write leveling (Byte 0): 24 => 24
1446 11:46:57.609728 Write leveling (Byte 1): 26 => 26
1447 11:46:57.612996 DramcWriteLeveling(PI) end<-----
1448 11:46:57.613090
1449 11:46:57.613178 ==
1450 11:46:57.616216 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 11:46:57.619545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 11:46:57.619641 ==
1453 11:46:57.622931 [Gating] SW mode calibration
1454 11:46:57.629892 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 11:46:57.636349 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 11:46:57.639640 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 11:46:57.646252 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:46:57.649614 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:46:57.652957 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:46:57.656157 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:46:57.662765 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:46:57.666089 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:46:57.669863 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:46:57.676201 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:46:57.679274 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:46:57.682837 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:46:57.689468 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:46:57.692988 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:46:57.696268 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:46:57.703001 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:46:57.706285 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:46:57.709408 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1473 11:46:57.716251 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1474 11:46:57.719726 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:46:57.722597 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:46:57.729358 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:46:57.732594 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:46:57.736463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:46:57.739871 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:46:57.746289 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:46:57.749406 0 9 4 | B1->B0 | 2323 2424 | 1 1 | (1 1) (1 1)
1482 11:46:57.752555 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1483 11:46:57.759698 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:46:57.762819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:46:57.766094 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 11:46:57.772601 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 11:46:57.776547 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 11:46:57.779812 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1489 11:46:57.786288 0 10 4 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
1490 11:46:57.789589 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1491 11:46:57.793435 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:46:57.799770 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:46:57.802659 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:46:57.806031 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:46:57.813032 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:46:57.816482 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:46:57.819644 0 11 4 | B1->B0 | 2828 3535 | 0 0 | (0 0) (1 1)
1498 11:46:57.822865 0 11 8 | B1->B0 | 4040 4545 | 0 0 | (1 1) (0 0)
1499 11:46:57.829507 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:46:57.832943 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:46:57.836220 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:46:57.843041 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 11:46:57.846392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 11:46:57.850007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:46:57.856587 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 11:46:57.859623 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:46:57.863514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:46:57.869858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:46:57.873129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:46:57.876412 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:46:57.883539 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:46:57.886811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:46:57.890086 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:46:57.893397 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:46:57.899943 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:46:57.903183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:46:57.906386 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:46:57.913275 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:46:57.917052 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:46:57.920168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:46:57.926774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1522 11:46:57.929933 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 11:46:57.933898 Total UI for P1: 0, mck2ui 16
1524 11:46:57.937181 best dqsien dly found for B0: ( 0, 14, 4)
1525 11:46:57.939948 Total UI for P1: 0, mck2ui 16
1526 11:46:57.943814 best dqsien dly found for B1: ( 0, 14, 4)
1527 11:46:57.946996 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1528 11:46:57.950159 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1529 11:46:57.950241
1530 11:46:57.953371 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1531 11:46:57.957064 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1532 11:46:57.959970 [Gating] SW calibration Done
1533 11:46:57.960070 ==
1534 11:46:57.963567 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 11:46:57.967030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 11:46:57.967106 ==
1537 11:46:57.970055 RX Vref Scan: 0
1538 11:46:57.970127
1539 11:46:57.973432 RX Vref 0 -> 0, step: 1
1540 11:46:57.973533
1541 11:46:57.973666 RX Delay -130 -> 252, step: 16
1542 11:46:57.980319 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1543 11:46:57.983610 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1544 11:46:57.986953 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1545 11:46:57.989972 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1546 11:46:57.994006 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1547 11:46:58.000510 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1548 11:46:58.003803 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1549 11:46:58.006855 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1550 11:46:58.010112 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1551 11:46:58.013442 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1552 11:46:58.020374 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1553 11:46:58.023824 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1554 11:46:58.026905 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1555 11:46:58.030565 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1556 11:46:58.033856 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1557 11:46:58.040453 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1558 11:46:58.040539 ==
1559 11:46:58.043739 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 11:46:58.047543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 11:46:58.047625 ==
1562 11:46:58.047693 DQS Delay:
1563 11:46:58.050550 DQS0 = 0, DQS1 = 0
1564 11:46:58.050652 DQM Delay:
1565 11:46:58.053917 DQM0 = 93, DQM1 = 87
1566 11:46:58.054017 DQ Delay:
1567 11:46:58.057075 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1568 11:46:58.060426 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1569 11:46:58.064230 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1570 11:46:58.067668 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1571 11:46:58.067769
1572 11:46:58.067858
1573 11:46:58.067943 ==
1574 11:46:58.070702 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 11:46:58.074290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 11:46:58.074375 ==
1577 11:46:58.074436
1578 11:46:58.074493
1579 11:46:58.077396 TX Vref Scan disable
1580 11:46:58.081199 == TX Byte 0 ==
1581 11:46:58.084092 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1582 11:46:58.087783 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1583 11:46:58.091142 == TX Byte 1 ==
1584 11:46:58.094282 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1585 11:46:58.097819 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1586 11:46:58.097892 ==
1587 11:46:58.101157 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 11:46:58.104509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 11:46:58.104620 ==
1590 11:46:58.118623 TX Vref=22, minBit 1, minWin=26, winSum=437
1591 11:46:58.121861 TX Vref=24, minBit 0, minWin=27, winSum=439
1592 11:46:58.125688 TX Vref=26, minBit 1, minWin=27, winSum=447
1593 11:46:58.128887 TX Vref=28, minBit 0, minWin=27, winSum=449
1594 11:46:58.132195 TX Vref=30, minBit 0, minWin=27, winSum=448
1595 11:46:58.135523 TX Vref=32, minBit 0, minWin=27, winSum=446
1596 11:46:58.142122 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 28
1597 11:46:58.142209
1598 11:46:58.145697 Final TX Range 1 Vref 28
1599 11:46:58.145820
1600 11:46:58.145881 ==
1601 11:46:58.149035 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 11:46:58.152040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 11:46:58.152146 ==
1604 11:46:58.152236
1605 11:46:58.152330
1606 11:46:58.155690 TX Vref Scan disable
1607 11:46:58.158831 == TX Byte 0 ==
1608 11:46:58.162173 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1609 11:46:58.165887 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1610 11:46:58.169238 == TX Byte 1 ==
1611 11:46:58.172391 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1612 11:46:58.175657 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1613 11:46:58.175755
1614 11:46:58.179283 [DATLAT]
1615 11:46:58.179356 Freq=800, CH1 RK0
1616 11:46:58.179417
1617 11:46:58.182299 DATLAT Default: 0xa
1618 11:46:58.182371 0, 0xFFFF, sum = 0
1619 11:46:58.186159 1, 0xFFFF, sum = 0
1620 11:46:58.186235 2, 0xFFFF, sum = 0
1621 11:46:58.189386 3, 0xFFFF, sum = 0
1622 11:46:58.189458 4, 0xFFFF, sum = 0
1623 11:46:58.192380 5, 0xFFFF, sum = 0
1624 11:46:58.192453 6, 0xFFFF, sum = 0
1625 11:46:58.196067 7, 0xFFFF, sum = 0
1626 11:46:58.196138 8, 0xFFFF, sum = 0
1627 11:46:58.199103 9, 0x0, sum = 1
1628 11:46:58.199169 10, 0x0, sum = 2
1629 11:46:58.202554 11, 0x0, sum = 3
1630 11:46:58.202636 12, 0x0, sum = 4
1631 11:46:58.205723 best_step = 10
1632 11:46:58.205801
1633 11:46:58.205863 ==
1634 11:46:58.209386 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 11:46:58.212838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 11:46:58.212924 ==
1637 11:46:58.216043 RX Vref Scan: 1
1638 11:46:58.216151
1639 11:46:58.216241 Set Vref Range= 32 -> 127
1640 11:46:58.216328
1641 11:46:58.219045 RX Vref 32 -> 127, step: 1
1642 11:46:58.219144
1643 11:46:58.222331 RX Delay -79 -> 252, step: 8
1644 11:46:58.222430
1645 11:46:58.226211 Set Vref, RX VrefLevel [Byte0]: 32
1646 11:46:58.229501 [Byte1]: 32
1647 11:46:58.229635
1648 11:46:58.232923 Set Vref, RX VrefLevel [Byte0]: 33
1649 11:46:58.236281 [Byte1]: 33
1650 11:46:58.236380
1651 11:46:58.239637 Set Vref, RX VrefLevel [Byte0]: 34
1652 11:46:58.242890 [Byte1]: 34
1653 11:46:58.246229
1654 11:46:58.246307 Set Vref, RX VrefLevel [Byte0]: 35
1655 11:46:58.249395 [Byte1]: 35
1656 11:46:58.253718
1657 11:46:58.253927 Set Vref, RX VrefLevel [Byte0]: 36
1658 11:46:58.257478 [Byte1]: 36
1659 11:46:58.261263
1660 11:46:58.261476 Set Vref, RX VrefLevel [Byte0]: 37
1661 11:46:58.264954 [Byte1]: 37
1662 11:46:58.268871
1663 11:46:58.268944 Set Vref, RX VrefLevel [Byte0]: 38
1664 11:46:58.272098 [Byte1]: 38
1665 11:46:58.276792
1666 11:46:58.276897 Set Vref, RX VrefLevel [Byte0]: 39
1667 11:46:58.280175 [Byte1]: 39
1668 11:46:58.283956
1669 11:46:58.284057 Set Vref, RX VrefLevel [Byte0]: 40
1670 11:46:58.287105 [Byte1]: 40
1671 11:46:58.292001
1672 11:46:58.292134 Set Vref, RX VrefLevel [Byte0]: 41
1673 11:46:58.294969 [Byte1]: 41
1674 11:46:58.298927
1675 11:46:58.298993 Set Vref, RX VrefLevel [Byte0]: 42
1676 11:46:58.302804 [Byte1]: 42
1677 11:46:58.306591
1678 11:46:58.306665 Set Vref, RX VrefLevel [Byte0]: 43
1679 11:46:58.310220 [Byte1]: 43
1680 11:46:58.314048
1681 11:46:58.314115 Set Vref, RX VrefLevel [Byte0]: 44
1682 11:46:58.317331 [Byte1]: 44
1683 11:46:58.321839
1684 11:46:58.321935 Set Vref, RX VrefLevel [Byte0]: 45
1685 11:46:58.325113 [Byte1]: 45
1686 11:46:58.329291
1687 11:46:58.329397 Set Vref, RX VrefLevel [Byte0]: 46
1688 11:46:58.332700 [Byte1]: 46
1689 11:46:58.336636
1690 11:46:58.336706 Set Vref, RX VrefLevel [Byte0]: 47
1691 11:46:58.340007 [Byte1]: 47
1692 11:46:58.344515
1693 11:46:58.344609 Set Vref, RX VrefLevel [Byte0]: 48
1694 11:46:58.347928 [Byte1]: 48
1695 11:46:58.352342
1696 11:46:58.352432 Set Vref, RX VrefLevel [Byte0]: 49
1697 11:46:58.355642 [Byte1]: 49
1698 11:46:58.359389
1699 11:46:58.359479 Set Vref, RX VrefLevel [Byte0]: 50
1700 11:46:58.362626 [Byte1]: 50
1701 11:46:58.367493
1702 11:46:58.367560 Set Vref, RX VrefLevel [Byte0]: 51
1703 11:46:58.370540 [Byte1]: 51
1704 11:46:58.374700
1705 11:46:58.374765 Set Vref, RX VrefLevel [Byte0]: 52
1706 11:46:58.377926 [Byte1]: 52
1707 11:46:58.382256
1708 11:46:58.382349 Set Vref, RX VrefLevel [Byte0]: 53
1709 11:46:58.385778 [Byte1]: 53
1710 11:46:58.390036
1711 11:46:58.390124 Set Vref, RX VrefLevel [Byte0]: 54
1712 11:46:58.393167 [Byte1]: 54
1713 11:46:58.397195
1714 11:46:58.397288 Set Vref, RX VrefLevel [Byte0]: 55
1715 11:46:58.400789 [Byte1]: 55
1716 11:46:58.405107
1717 11:46:58.405216 Set Vref, RX VrefLevel [Byte0]: 56
1718 11:46:58.408463 [Byte1]: 56
1719 11:46:58.412214
1720 11:46:58.412316 Set Vref, RX VrefLevel [Byte0]: 57
1721 11:46:58.416012 [Byte1]: 57
1722 11:46:58.420363
1723 11:46:58.420469 Set Vref, RX VrefLevel [Byte0]: 58
1724 11:46:58.423023 [Byte1]: 58
1725 11:46:58.427455
1726 11:46:58.427560 Set Vref, RX VrefLevel [Byte0]: 59
1727 11:46:58.430728 [Byte1]: 59
1728 11:46:58.435262
1729 11:46:58.435365 Set Vref, RX VrefLevel [Byte0]: 60
1730 11:46:58.438471 [Byte1]: 60
1731 11:46:58.442688
1732 11:46:58.442773 Set Vref, RX VrefLevel [Byte0]: 61
1733 11:46:58.446132 [Byte1]: 61
1734 11:46:58.450447
1735 11:46:58.450553 Set Vref, RX VrefLevel [Byte0]: 62
1736 11:46:58.453752 [Byte1]: 62
1737 11:46:58.457584
1738 11:46:58.457678 Set Vref, RX VrefLevel [Byte0]: 63
1739 11:46:58.460835 [Byte1]: 63
1740 11:46:58.465430
1741 11:46:58.465529 Set Vref, RX VrefLevel [Byte0]: 64
1742 11:46:58.468459 [Byte1]: 64
1743 11:46:58.472897
1744 11:46:58.472999 Set Vref, RX VrefLevel [Byte0]: 65
1745 11:46:58.476354 [Byte1]: 65
1746 11:46:58.480386
1747 11:46:58.480489 Set Vref, RX VrefLevel [Byte0]: 66
1748 11:46:58.483699 [Byte1]: 66
1749 11:46:58.487673
1750 11:46:58.487770 Set Vref, RX VrefLevel [Byte0]: 67
1751 11:46:58.491423 [Byte1]: 67
1752 11:46:58.495454
1753 11:46:58.495523 Set Vref, RX VrefLevel [Byte0]: 68
1754 11:46:58.498917 [Byte1]: 68
1755 11:46:58.503276
1756 11:46:58.503385 Set Vref, RX VrefLevel [Byte0]: 69
1757 11:46:58.506576 [Byte1]: 69
1758 11:46:58.510167
1759 11:46:58.510272 Set Vref, RX VrefLevel [Byte0]: 70
1760 11:46:58.514127 [Byte1]: 70
1761 11:46:58.517938
1762 11:46:58.518036 Set Vref, RX VrefLevel [Byte0]: 71
1763 11:46:58.521139 [Byte1]: 71
1764 11:46:58.525481
1765 11:46:58.525601 Final RX Vref Byte 0 = 57 to rank0
1766 11:46:58.528940 Final RX Vref Byte 1 = 58 to rank0
1767 11:46:58.532130 Final RX Vref Byte 0 = 57 to rank1
1768 11:46:58.536135 Final RX Vref Byte 1 = 58 to rank1==
1769 11:46:58.539346 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 11:46:58.542637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 11:46:58.545861 ==
1772 11:46:58.545933 DQS Delay:
1773 11:46:58.545994 DQS0 = 0, DQS1 = 0
1774 11:46:58.549120 DQM Delay:
1775 11:46:58.549216 DQM0 = 95, DQM1 = 89
1776 11:46:58.552234 DQ Delay:
1777 11:46:58.552331 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1778 11:46:58.556073 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1779 11:46:58.558965 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1780 11:46:58.562528 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 11:46:58.565752
1782 11:46:58.565824
1783 11:46:58.572217 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1784 11:46:58.576087 CH1 RK0: MR19=606, MR18=314E
1785 11:46:58.582661 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1786 11:46:58.582763
1787 11:46:58.585793 ----->DramcWriteLeveling(PI) begin...
1788 11:46:58.585892 ==
1789 11:46:58.589044 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 11:46:58.592353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 11:46:58.592450 ==
1792 11:46:58.595634 Write leveling (Byte 0): 25 => 25
1793 11:46:58.599506 Write leveling (Byte 1): 29 => 29
1794 11:46:58.602596 DramcWriteLeveling(PI) end<-----
1795 11:46:58.602697
1796 11:46:58.602786 ==
1797 11:46:58.605615 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 11:46:58.609447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 11:46:58.609551 ==
1800 11:46:58.612430 [Gating] SW mode calibration
1801 11:46:58.619275 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 11:46:58.625767 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 11:46:58.629426 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 11:46:58.632607 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1805 11:46:58.639383 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:46:58.642482 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:46:58.645837 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:46:58.652929 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:46:58.656050 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:46:58.659333 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:46:58.662579 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:46:58.669147 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:46:58.672747 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:46:58.676077 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:46:58.682846 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:46:58.686369 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:46:58.689452 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:46:58.696274 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:46:58.699394 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1820 11:46:58.702779 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 11:46:58.709385 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:46:58.712546 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:46:58.716129 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:46:58.722777 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:46:58.726089 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:46:58.729406 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:46:58.736535 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:46:58.739544 0 9 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
1829 11:46:58.743061 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1830 11:46:58.746434 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:46:58.753048 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:46:58.756274 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:46:58.759486 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 11:46:58.766091 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 11:46:58.769928 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1836 11:46:58.773172 0 10 4 | B1->B0 | 2b2b 2f2f | 1 1 | (1 0) (1 0)
1837 11:46:58.779953 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:46:58.783120 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:46:58.786255 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:46:58.792832 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:46:58.796050 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:46:58.799303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:46:58.806247 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:46:58.809695 0 11 4 | B1->B0 | 3737 2a2a | 0 1 | (1 1) (0 0)
1845 11:46:58.812892 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1846 11:46:58.819508 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:46:58.822850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:46:58.826378 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:46:58.829561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:46:58.836201 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:46:58.839840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1852 11:46:58.842832 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 11:46:58.849750 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:46:58.853512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:46:58.856787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:46:58.863208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:46:58.866639 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:46:58.869834 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:46:58.876608 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:46:58.879856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:46:58.883348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:46:58.889882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:46:58.893258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:46:58.896479 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:46:58.899856 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:46:58.906811 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:46:58.909868 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:46:58.912994 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 11:46:58.916567 Total UI for P1: 0, mck2ui 16
1870 11:46:58.919950 best dqsien dly found for B0: ( 0, 14, 2)
1871 11:46:58.923398 Total UI for P1: 0, mck2ui 16
1872 11:46:58.926834 best dqsien dly found for B1: ( 0, 14, 2)
1873 11:46:58.929768 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1874 11:46:58.933456 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1875 11:46:58.933555
1876 11:46:58.939835 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1877 11:46:58.943600 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1878 11:46:58.943674 [Gating] SW calibration Done
1879 11:46:58.946731 ==
1880 11:46:58.949805 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 11:46:58.953600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 11:46:58.953698 ==
1883 11:46:58.953780 RX Vref Scan: 0
1884 11:46:58.953843
1885 11:46:58.956287 RX Vref 0 -> 0, step: 1
1886 11:46:58.956356
1887 11:46:58.959672 RX Delay -130 -> 252, step: 16
1888 11:46:58.963204 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1889 11:46:58.966380 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1890 11:46:58.973470 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1891 11:46:58.976619 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1892 11:46:58.979969 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1893 11:46:58.983380 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1894 11:46:58.986655 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1895 11:46:58.989841 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1896 11:46:58.996563 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1897 11:46:58.999889 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1898 11:46:59.003190 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1899 11:46:59.006507 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1900 11:46:59.010483 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1901 11:46:59.016995 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1902 11:46:59.020148 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1903 11:46:59.023415 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1904 11:46:59.023490 ==
1905 11:46:59.026654 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 11:46:59.030356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 11:46:59.030432 ==
1908 11:46:59.033816 DQS Delay:
1909 11:46:59.033892 DQS0 = 0, DQS1 = 0
1910 11:46:59.036875 DQM Delay:
1911 11:46:59.036979 DQM0 = 93, DQM1 = 91
1912 11:46:59.037070 DQ Delay:
1913 11:46:59.040510 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1914 11:46:59.043902 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1915 11:46:59.047218 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1916 11:46:59.049951 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1917 11:46:59.050025
1918 11:46:59.053521
1919 11:46:59.053633 ==
1920 11:46:59.056966 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 11:46:59.060059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 11:46:59.060134 ==
1923 11:46:59.060196
1924 11:46:59.060259
1925 11:46:59.063800 TX Vref Scan disable
1926 11:46:59.063872 == TX Byte 0 ==
1927 11:46:59.070442 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1928 11:46:59.073302 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1929 11:46:59.073401 == TX Byte 1 ==
1930 11:46:59.080309 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 11:46:59.083709 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 11:46:59.083785 ==
1933 11:46:59.086909 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 11:46:59.090220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 11:46:59.090326 ==
1936 11:46:59.103542 TX Vref=22, minBit 2, minWin=26, winSum=440
1937 11:46:59.106978 TX Vref=24, minBit 1, minWin=26, winSum=440
1938 11:46:59.110851 TX Vref=26, minBit 5, minWin=26, winSum=444
1939 11:46:59.114120 TX Vref=28, minBit 0, minWin=27, winSum=448
1940 11:46:59.117433 TX Vref=30, minBit 0, minWin=27, winSum=451
1941 11:46:59.120875 TX Vref=32, minBit 2, minWin=27, winSum=448
1942 11:46:59.127496 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 30
1943 11:46:59.127634
1944 11:46:59.130750 Final TX Range 1 Vref 30
1945 11:46:59.130834
1946 11:46:59.130897 ==
1947 11:46:59.133980 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 11:46:59.137357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 11:46:59.137458 ==
1950 11:46:59.137550
1951 11:46:59.137678
1952 11:46:59.140475 TX Vref Scan disable
1953 11:46:59.143732 == TX Byte 0 ==
1954 11:46:59.147641 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1955 11:46:59.150932 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1956 11:46:59.153881 == TX Byte 1 ==
1957 11:46:59.157472 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 11:46:59.160430 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 11:46:59.160507
1960 11:46:59.163863 [DATLAT]
1961 11:46:59.163936 Freq=800, CH1 RK1
1962 11:46:59.163997
1963 11:46:59.166938 DATLAT Default: 0xa
1964 11:46:59.167011 0, 0xFFFF, sum = 0
1965 11:46:59.170578 1, 0xFFFF, sum = 0
1966 11:46:59.170677 2, 0xFFFF, sum = 0
1967 11:46:59.173808 3, 0xFFFF, sum = 0
1968 11:46:59.173912 4, 0xFFFF, sum = 0
1969 11:46:59.177128 5, 0xFFFF, sum = 0
1970 11:46:59.177234 6, 0xFFFF, sum = 0
1971 11:46:59.180816 7, 0xFFFF, sum = 0
1972 11:46:59.180903 8, 0xFFFF, sum = 0
1973 11:46:59.183823 9, 0x0, sum = 1
1974 11:46:59.183921 10, 0x0, sum = 2
1975 11:46:59.187441 11, 0x0, sum = 3
1976 11:46:59.187546 12, 0x0, sum = 4
1977 11:46:59.191046 best_step = 10
1978 11:46:59.191154
1979 11:46:59.191220 ==
1980 11:46:59.194065 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 11:46:59.197272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 11:46:59.197374 ==
1983 11:46:59.200783 RX Vref Scan: 0
1984 11:46:59.200888
1985 11:46:59.200980 RX Vref 0 -> 0, step: 1
1986 11:46:59.201070
1987 11:46:59.203733 RX Delay -63 -> 252, step: 8
1988 11:46:59.210603 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1989 11:46:59.213903 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1990 11:46:59.217449 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1991 11:46:59.220596 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1992 11:46:59.223996 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1993 11:46:59.227265 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1994 11:46:59.233643 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1995 11:46:59.237161 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1996 11:46:59.240290 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1997 11:46:59.243752 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1998 11:46:59.247610 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1999 11:46:59.253600 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2000 11:46:59.257031 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2001 11:46:59.260825 iDelay=209, Bit 13, Center 100 (1 ~ 200) 200
2002 11:46:59.263815 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2003 11:46:59.267291 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2004 11:46:59.267370 ==
2005 11:46:59.270512 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 11:46:59.277012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 11:46:59.277092 ==
2008 11:46:59.277157 DQS Delay:
2009 11:46:59.280476 DQS0 = 0, DQS1 = 0
2010 11:46:59.280551 DQM Delay:
2011 11:46:59.280613 DQM0 = 97, DQM1 = 91
2012 11:46:59.283644 DQ Delay:
2013 11:46:59.287374 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2014 11:46:59.290720 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2015 11:46:59.294171 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2016 11:46:59.297532 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =96
2017 11:46:59.297633
2018 11:46:59.297698
2019 11:46:59.303885 [DQSOSCAuto] RK1, (LSB)MR18= 0x4812, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2020 11:46:59.307371 CH1 RK1: MR19=606, MR18=4812
2021 11:46:59.313903 CH1_RK1: MR19=0x606, MR18=0x4812, DQSOSC=391, MR23=63, INC=96, DEC=64
2022 11:46:59.317205 [RxdqsGatingPostProcess] freq 800
2023 11:46:59.320598 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 11:46:59.324113 Pre-setting of DQS Precalculation
2025 11:46:59.330813 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 11:46:59.337051 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 11:46:59.343726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 11:46:59.343831
2029 11:46:59.343932
2030 11:46:59.347561 [Calibration Summary] 1600 Mbps
2031 11:46:59.347648 CH 0, Rank 0
2032 11:46:59.350669 SW Impedance : PASS
2033 11:46:59.354026 DUTY Scan : NO K
2034 11:46:59.354104 ZQ Calibration : PASS
2035 11:46:59.357293 Jitter Meter : NO K
2036 11:46:59.360671 CBT Training : PASS
2037 11:46:59.360773 Write leveling : PASS
2038 11:46:59.363902 RX DQS gating : PASS
2039 11:46:59.367738 RX DQ/DQS(RDDQC) : PASS
2040 11:46:59.367840 TX DQ/DQS : PASS
2041 11:46:59.370879 RX DATLAT : PASS
2042 11:46:59.370948 RX DQ/DQS(Engine): PASS
2043 11:46:59.374242 TX OE : NO K
2044 11:46:59.374337 All Pass.
2045 11:46:59.374427
2046 11:46:59.377537 CH 0, Rank 1
2047 11:46:59.377647 SW Impedance : PASS
2048 11:46:59.381030 DUTY Scan : NO K
2049 11:46:59.384085 ZQ Calibration : PASS
2050 11:46:59.384196 Jitter Meter : NO K
2051 11:46:59.387484 CBT Training : PASS
2052 11:46:59.391256 Write leveling : PASS
2053 11:46:59.391354 RX DQS gating : PASS
2054 11:46:59.394591 RX DQ/DQS(RDDQC) : PASS
2055 11:46:59.397676 TX DQ/DQS : PASS
2056 11:46:59.397774 RX DATLAT : PASS
2057 11:46:59.401344 RX DQ/DQS(Engine): PASS
2058 11:46:59.401440 TX OE : NO K
2059 11:46:59.404802 All Pass.
2060 11:46:59.404902
2061 11:46:59.404995 CH 1, Rank 0
2062 11:46:59.407602 SW Impedance : PASS
2063 11:46:59.407690 DUTY Scan : NO K
2064 11:46:59.410920 ZQ Calibration : PASS
2065 11:46:59.414466 Jitter Meter : NO K
2066 11:46:59.414566 CBT Training : PASS
2067 11:46:59.418065 Write leveling : PASS
2068 11:46:59.421307 RX DQS gating : PASS
2069 11:46:59.421405 RX DQ/DQS(RDDQC) : PASS
2070 11:46:59.424241 TX DQ/DQS : PASS
2071 11:46:59.427677 RX DATLAT : PASS
2072 11:46:59.427805 RX DQ/DQS(Engine): PASS
2073 11:46:59.431242 TX OE : NO K
2074 11:46:59.431326 All Pass.
2075 11:46:59.431391
2076 11:46:59.434489 CH 1, Rank 1
2077 11:46:59.434559 SW Impedance : PASS
2078 11:46:59.437590 DUTY Scan : NO K
2079 11:46:59.440945 ZQ Calibration : PASS
2080 11:46:59.441014 Jitter Meter : NO K
2081 11:46:59.444984 CBT Training : PASS
2082 11:46:59.445106 Write leveling : PASS
2083 11:46:59.448353 RX DQS gating : PASS
2084 11:46:59.450963 RX DQ/DQS(RDDQC) : PASS
2085 11:46:59.451066 TX DQ/DQS : PASS
2086 11:46:59.454781 RX DATLAT : PASS
2087 11:46:59.458202 RX DQ/DQS(Engine): PASS
2088 11:46:59.458279 TX OE : NO K
2089 11:46:59.461460 All Pass.
2090 11:46:59.461532
2091 11:46:59.461600 DramC Write-DBI off
2092 11:46:59.464728 PER_BANK_REFRESH: Hybrid Mode
2093 11:46:59.464798 TX_TRACKING: ON
2094 11:46:59.467883 [GetDramInforAfterCalByMRR] Vendor 6.
2095 11:46:59.474445 [GetDramInforAfterCalByMRR] Revision 606.
2096 11:46:59.478128 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 11:46:59.478235 MR0 0x3b3b
2098 11:46:59.478329 MR8 0x5151
2099 11:46:59.481292 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 11:46:59.481391
2101 11:46:59.484558 MR0 0x3b3b
2102 11:46:59.484656 MR8 0x5151
2103 11:46:59.488273 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 11:46:59.488374
2105 11:46:59.498406 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 11:46:59.501569 [FAST_K] Save calibration result to emmc
2107 11:46:59.504966 [FAST_K] Save calibration result to emmc
2108 11:46:59.508236 dram_init: config_dvfs: 1
2109 11:46:59.511417 dramc_set_vcore_voltage set vcore to 662500
2110 11:46:59.514947 Read voltage for 1200, 2
2111 11:46:59.515050 Vio18 = 0
2112 11:46:59.515147 Vcore = 662500
2113 11:46:59.518067 Vdram = 0
2114 11:46:59.518136 Vddq = 0
2115 11:46:59.518202 Vmddr = 0
2116 11:46:59.525056 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 11:46:59.527872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 11:46:59.531392 MEM_TYPE=3, freq_sel=15
2119 11:46:59.534632 sv_algorithm_assistance_LP4_1600
2120 11:46:59.537960 ============ PULL DRAM RESETB DOWN ============
2121 11:46:59.541603 ========== PULL DRAM RESETB DOWN end =========
2122 11:46:59.548078 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 11:46:59.551559 ===================================
2124 11:46:59.551681 LPDDR4 DRAM CONFIGURATION
2125 11:46:59.554823 ===================================
2126 11:46:59.558055 EX_ROW_EN[0] = 0x0
2127 11:46:59.558167 EX_ROW_EN[1] = 0x0
2128 11:46:59.561485 LP4Y_EN = 0x0
2129 11:46:59.564884 WORK_FSP = 0x0
2130 11:46:59.564991 WL = 0x4
2131 11:46:59.568052 RL = 0x4
2132 11:46:59.568153 BL = 0x2
2133 11:46:59.571408 RPST = 0x0
2134 11:46:59.571481 RD_PRE = 0x0
2135 11:46:59.575196 WR_PRE = 0x1
2136 11:46:59.575294 WR_PST = 0x0
2137 11:46:59.578420 DBI_WR = 0x0
2138 11:46:59.578493 DBI_RD = 0x0
2139 11:46:59.581513 OTF = 0x1
2140 11:46:59.584836 ===================================
2141 11:46:59.588035 ===================================
2142 11:46:59.588136 ANA top config
2143 11:46:59.591418 ===================================
2144 11:46:59.595171 DLL_ASYNC_EN = 0
2145 11:46:59.598222 ALL_SLAVE_EN = 0
2146 11:46:59.598294 NEW_RANK_MODE = 1
2147 11:46:59.601723 DLL_IDLE_MODE = 1
2148 11:46:59.604986 LP45_APHY_COMB_EN = 1
2149 11:46:59.608399 TX_ODT_DIS = 1
2150 11:46:59.611459 NEW_8X_MODE = 1
2151 11:46:59.611535 ===================================
2152 11:46:59.614758 ===================================
2153 11:46:59.617985 data_rate = 2400
2154 11:46:59.621694 CKR = 1
2155 11:46:59.625120 DQ_P2S_RATIO = 8
2156 11:46:59.628488 ===================================
2157 11:46:59.664064 CA_P2S_RATIO = 8
2158 11:46:59.664159 DQ_CA_OPEN = 0
2159 11:46:59.664234 DQ_SEMI_OPEN = 0
2160 11:46:59.664333 CA_SEMI_OPEN = 0
2161 11:46:59.664422 CA_FULL_RATE = 0
2162 11:46:59.664509 DQ_CKDIV4_EN = 0
2163 11:46:59.664595 CA_CKDIV4_EN = 0
2164 11:46:59.664654 CA_PREDIV_EN = 0
2165 11:46:59.664710 PH8_DLY = 17
2166 11:46:59.664765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 11:46:59.664821 DQ_AAMCK_DIV = 4
2168 11:46:59.664908 CA_AAMCK_DIV = 4
2169 11:46:59.665338 CA_ADMCK_DIV = 4
2170 11:46:59.668395 DQ_TRACK_CA_EN = 0
2171 11:46:59.668508 CA_PICK = 1200
2172 11:46:59.671555 CA_MCKIO = 1200
2173 11:46:59.674935 MCKIO_SEMI = 0
2174 11:46:59.678188 PLL_FREQ = 2366
2175 11:46:59.681484 DQ_UI_PI_RATIO = 32
2176 11:46:59.685303 CA_UI_PI_RATIO = 0
2177 11:46:59.688494 ===================================
2178 11:46:59.691803 ===================================
2179 11:46:59.691897 memory_type:LPDDR4
2180 11:46:59.695107 GP_NUM : 10
2181 11:46:59.698281 SRAM_EN : 1
2182 11:46:59.698402 MD32_EN : 0
2183 11:46:59.701600 ===================================
2184 11:46:59.704876 [ANA_INIT] >>>>>>>>>>>>>>
2185 11:46:59.708224 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 11:46:59.711695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 11:46:59.715084 ===================================
2188 11:46:59.718278 data_rate = 2400,PCW = 0X5b00
2189 11:46:59.722167 ===================================
2190 11:46:59.724840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 11:46:59.728843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 11:46:59.735365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 11:46:59.738446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 11:46:59.741697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 11:46:59.745446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 11:46:59.748826 [ANA_INIT] flow start
2197 11:46:59.751801 [ANA_INIT] PLL >>>>>>>>
2198 11:46:59.751890 [ANA_INIT] PLL <<<<<<<<
2199 11:46:59.754989 [ANA_INIT] MIDPI >>>>>>>>
2200 11:46:59.758872 [ANA_INIT] MIDPI <<<<<<<<
2201 11:46:59.761892 [ANA_INIT] DLL >>>>>>>>
2202 11:46:59.761984 [ANA_INIT] DLL <<<<<<<<
2203 11:46:59.765058 [ANA_INIT] flow end
2204 11:46:59.768953 ============ LP4 DIFF to SE enter ============
2205 11:46:59.771912 ============ LP4 DIFF to SE exit ============
2206 11:46:59.775478 [ANA_INIT] <<<<<<<<<<<<<
2207 11:46:59.778474 [Flow] Enable top DCM control >>>>>
2208 11:46:59.781904 [Flow] Enable top DCM control <<<<<
2209 11:46:59.785306 Enable DLL master slave shuffle
2210 11:46:59.788475 ==============================================================
2211 11:46:59.792361 Gating Mode config
2212 11:46:59.798881 ==============================================================
2213 11:46:59.798967 Config description:
2214 11:46:59.808866 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 11:46:59.815287 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 11:46:59.818808 SELPH_MODE 0: By rank 1: By Phase
2217 11:46:59.825151 ==============================================================
2218 11:46:59.829165 GAT_TRACK_EN = 1
2219 11:46:59.831847 RX_GATING_MODE = 2
2220 11:46:59.835236 RX_GATING_TRACK_MODE = 2
2221 11:46:59.838975 SELPH_MODE = 1
2222 11:46:59.841835 PICG_EARLY_EN = 1
2223 11:46:59.845543 VALID_LAT_VALUE = 1
2224 11:46:59.848492 ==============================================================
2225 11:46:59.852337 Enter into Gating configuration >>>>
2226 11:46:59.855341 Exit from Gating configuration <<<<
2227 11:46:59.858565 Enter into DVFS_PRE_config >>>>>
2228 11:46:59.868810 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 11:46:59.872161 Exit from DVFS_PRE_config <<<<<
2230 11:46:59.875345 Enter into PICG configuration >>>>
2231 11:46:59.878602 Exit from PICG configuration <<<<
2232 11:46:59.881747 [RX_INPUT] configuration >>>>>
2233 11:46:59.884892 [RX_INPUT] configuration <<<<<
2234 11:46:59.892033 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 11:46:59.895371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 11:46:59.902167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 11:46:59.908691 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 11:46:59.915407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 11:46:59.921612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 11:46:59.925368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 11:46:59.928450 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 11:46:59.932110 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 11:46:59.938604 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 11:46:59.941797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 11:46:59.945198 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 11:46:59.948451 ===================================
2247 11:46:59.952362 LPDDR4 DRAM CONFIGURATION
2248 11:46:59.955531 ===================================
2249 11:46:59.955633 EX_ROW_EN[0] = 0x0
2250 11:46:59.958623 EX_ROW_EN[1] = 0x0
2251 11:46:59.958704 LP4Y_EN = 0x0
2252 11:46:59.962420 WORK_FSP = 0x0
2253 11:46:59.962507 WL = 0x4
2254 11:46:59.965307 RL = 0x4
2255 11:46:59.965403 BL = 0x2
2256 11:46:59.968478 RPST = 0x0
2257 11:46:59.968558 RD_PRE = 0x0
2258 11:46:59.971997 WR_PRE = 0x1
2259 11:46:59.975339 WR_PST = 0x0
2260 11:46:59.975420 DBI_WR = 0x0
2261 11:46:59.978566 DBI_RD = 0x0
2262 11:46:59.978646 OTF = 0x1
2263 11:46:59.981803 ===================================
2264 11:46:59.985288 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 11:46:59.988369 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 11:46:59.995566 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 11:46:59.998811 ===================================
2268 11:47:00.003272 LPDDR4 DRAM CONFIGURATION
2269 11:47:00.003359 ===================================
2270 11:47:00.005541 EX_ROW_EN[0] = 0x10
2271 11:47:00.008703 EX_ROW_EN[1] = 0x0
2272 11:47:00.008803 LP4Y_EN = 0x0
2273 11:47:00.012567 WORK_FSP = 0x0
2274 11:47:00.012697 WL = 0x4
2275 11:47:00.015322 RL = 0x4
2276 11:47:00.015426 BL = 0x2
2277 11:47:00.018506 RPST = 0x0
2278 11:47:00.018611 RD_PRE = 0x0
2279 11:47:00.022663 WR_PRE = 0x1
2280 11:47:00.022815 WR_PST = 0x0
2281 11:47:00.025454 DBI_WR = 0x0
2282 11:47:00.025570 DBI_RD = 0x0
2283 11:47:00.028696 OTF = 0x1
2284 11:47:00.032366 ===================================
2285 11:47:00.038975 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 11:47:00.039103 ==
2287 11:47:00.042042 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 11:47:00.045406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 11:47:00.045512 ==
2290 11:47:00.048715 [Duty_Offset_Calibration]
2291 11:47:00.048795 B0:2 B1:1 CA:1
2292 11:47:00.048860
2293 11:47:00.052432 [DutyScan_Calibration_Flow] k_type=0
2294 11:47:00.062603
2295 11:47:00.062690 ==CLK 0==
2296 11:47:00.065632 Final CLK duty delay cell = 0
2297 11:47:00.069213 [0] MAX Duty = 5187%(X100), DQS PI = 24
2298 11:47:00.072742 [0] MIN Duty = 4844%(X100), DQS PI = 48
2299 11:47:00.072844 [0] AVG Duty = 5015%(X100)
2300 11:47:00.075892
2301 11:47:00.075997 CH0 CLK Duty spec in!! Max-Min= 343%
2302 11:47:00.082632 [DutyScan_Calibration_Flow] ====Done====
2303 11:47:00.082709
2304 11:47:00.085989 [DutyScan_Calibration_Flow] k_type=1
2305 11:47:00.100080
2306 11:47:00.100158 ==DQS 0 ==
2307 11:47:00.103427 Final DQS duty delay cell = -4
2308 11:47:00.106985 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2309 11:47:00.110604 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2310 11:47:00.113702 [-4] AVG Duty = 4953%(X100)
2311 11:47:00.113789
2312 11:47:00.113862 ==DQS 1 ==
2313 11:47:00.116961 Final DQS duty delay cell = -4
2314 11:47:00.120244 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2315 11:47:00.123442 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2316 11:47:00.126929 [-4] AVG Duty = 4922%(X100)
2317 11:47:00.127006
2318 11:47:00.130487 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2319 11:47:00.130573
2320 11:47:00.133733 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2321 11:47:00.136907 [DutyScan_Calibration_Flow] ====Done====
2322 11:47:00.137000
2323 11:47:00.140125 [DutyScan_Calibration_Flow] k_type=3
2324 11:47:00.157293
2325 11:47:00.157378 ==DQM 0 ==
2326 11:47:00.160688 Final DQM duty delay cell = 0
2327 11:47:00.164475 [0] MAX Duty = 5156%(X100), DQS PI = 30
2328 11:47:00.167610 [0] MIN Duty = 4907%(X100), DQS PI = 58
2329 11:47:00.170816 [0] AVG Duty = 5031%(X100)
2330 11:47:00.170897
2331 11:47:00.170960 ==DQM 1 ==
2332 11:47:00.173944 Final DQM duty delay cell = 0
2333 11:47:00.177669 [0] MAX Duty = 5125%(X100), DQS PI = 60
2334 11:47:00.180693 [0] MIN Duty = 5031%(X100), DQS PI = 34
2335 11:47:00.180773 [0] AVG Duty = 5078%(X100)
2336 11:47:00.184291
2337 11:47:00.187706 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2338 11:47:00.187793
2339 11:47:00.190934 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2340 11:47:00.194045 [DutyScan_Calibration_Flow] ====Done====
2341 11:47:00.194179
2342 11:47:00.197854 [DutyScan_Calibration_Flow] k_type=2
2343 11:47:00.214115
2344 11:47:00.214200 ==DQ 0 ==
2345 11:47:00.217312 Final DQ duty delay cell = 0
2346 11:47:00.220515 [0] MAX Duty = 5062%(X100), DQS PI = 32
2347 11:47:00.224218 [0] MIN Duty = 4875%(X100), DQS PI = 62
2348 11:47:00.224324 [0] AVG Duty = 4968%(X100)
2349 11:47:00.224421
2350 11:47:00.227479 ==DQ 1 ==
2351 11:47:00.230664 Final DQ duty delay cell = 0
2352 11:47:00.233938 [0] MAX Duty = 5093%(X100), DQS PI = 10
2353 11:47:00.237774 [0] MIN Duty = 4969%(X100), DQS PI = 14
2354 11:47:00.237857 [0] AVG Duty = 5031%(X100)
2355 11:47:00.237920
2356 11:47:00.240884 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2357 11:47:00.244118
2358 11:47:00.247240 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2359 11:47:00.250536 [DutyScan_Calibration_Flow] ====Done====
2360 11:47:00.250617 ==
2361 11:47:00.253783 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 11:47:00.257172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 11:47:00.257270 ==
2364 11:47:00.260913 [Duty_Offset_Calibration]
2365 11:47:00.260992 B0:1 B1:0 CA:0
2366 11:47:00.261055
2367 11:47:00.264140 [DutyScan_Calibration_Flow] k_type=0
2368 11:47:00.273112
2369 11:47:00.273209 ==CLK 0==
2370 11:47:00.276360 Final CLK duty delay cell = -4
2371 11:47:00.280211 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2372 11:47:00.283455 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2373 11:47:00.286610 [-4] AVG Duty = 4953%(X100)
2374 11:47:00.286691
2375 11:47:00.289810 CH1 CLK Duty spec in!! Max-Min= 156%
2376 11:47:00.293373 [DutyScan_Calibration_Flow] ====Done====
2377 11:47:00.293454
2378 11:47:00.296959 [DutyScan_Calibration_Flow] k_type=1
2379 11:47:00.312860
2380 11:47:00.312947 ==DQS 0 ==
2381 11:47:00.316731 Final DQS duty delay cell = 0
2382 11:47:00.319876 [0] MAX Duty = 5062%(X100), DQS PI = 12
2383 11:47:00.323184 [0] MIN Duty = 4875%(X100), DQS PI = 0
2384 11:47:00.323291 [0] AVG Duty = 4968%(X100)
2385 11:47:00.326476
2386 11:47:00.326580 ==DQS 1 ==
2387 11:47:00.329719 Final DQS duty delay cell = 0
2388 11:47:00.332862 [0] MAX Duty = 5187%(X100), DQS PI = 20
2389 11:47:00.336213 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 11:47:00.336356 [0] AVG Duty = 5078%(X100)
2391 11:47:00.339971
2392 11:47:00.342937 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2393 11:47:00.343038
2394 11:47:00.346857 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2395 11:47:00.349619 [DutyScan_Calibration_Flow] ====Done====
2396 11:47:00.349716
2397 11:47:00.353341 [DutyScan_Calibration_Flow] k_type=3
2398 11:47:00.369793
2399 11:47:00.369895 ==DQM 0 ==
2400 11:47:00.373146 Final DQM duty delay cell = 0
2401 11:47:00.376340 [0] MAX Duty = 5156%(X100), DQS PI = 6
2402 11:47:00.379663 [0] MIN Duty = 5031%(X100), DQS PI = 0
2403 11:47:00.379745 [0] AVG Duty = 5093%(X100)
2404 11:47:00.379826
2405 11:47:00.382784 ==DQM 1 ==
2406 11:47:00.386196 Final DQM duty delay cell = 0
2407 11:47:00.389563 [0] MAX Duty = 5031%(X100), DQS PI = 26
2408 11:47:00.392877 [0] MIN Duty = 4907%(X100), DQS PI = 36
2409 11:47:00.392957 [0] AVG Duty = 4969%(X100)
2410 11:47:00.393021
2411 11:47:00.399820 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2412 11:47:00.399901
2413 11:47:00.402918 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 11:47:00.406318 [DutyScan_Calibration_Flow] ====Done====
2415 11:47:00.406419
2416 11:47:00.409827 [DutyScan_Calibration_Flow] k_type=2
2417 11:47:00.425364
2418 11:47:00.425448 ==DQ 0 ==
2419 11:47:00.428595 Final DQ duty delay cell = -4
2420 11:47:00.432170 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2421 11:47:00.435432 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2422 11:47:00.435532 [-4] AVG Duty = 5000%(X100)
2423 11:47:00.438714
2424 11:47:00.438797 ==DQ 1 ==
2425 11:47:00.441856 Final DQ duty delay cell = 0
2426 11:47:00.445788 [0] MAX Duty = 5125%(X100), DQS PI = 20
2427 11:47:00.449338 [0] MIN Duty = 4938%(X100), DQS PI = 34
2428 11:47:00.449439 [0] AVG Duty = 5031%(X100)
2429 11:47:00.449534
2430 11:47:00.452484 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2431 11:47:00.455817
2432 11:47:00.459100 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2433 11:47:00.462333 [DutyScan_Calibration_Flow] ====Done====
2434 11:47:00.465358 nWR fixed to 30
2435 11:47:00.465442 [ModeRegInit_LP4] CH0 RK0
2436 11:47:00.468555 [ModeRegInit_LP4] CH0 RK1
2437 11:47:00.471964 [ModeRegInit_LP4] CH1 RK0
2438 11:47:00.472048 [ModeRegInit_LP4] CH1 RK1
2439 11:47:00.475247 match AC timing 7
2440 11:47:00.478584 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 11:47:00.481901 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 11:47:00.489255 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 11:47:00.491967 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 11:47:00.498661 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 11:47:00.498745 ==
2446 11:47:00.502480 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 11:47:00.505729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 11:47:00.505841 ==
2449 11:47:00.511994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 11:47:00.515581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2451 11:47:00.525178 [CA 0] Center 38 (8~69) winsize 62
2452 11:47:00.529042 [CA 1] Center 39 (8~70) winsize 63
2453 11:47:00.532264 [CA 2] Center 35 (4~66) winsize 63
2454 11:47:00.535571 [CA 3] Center 34 (4~65) winsize 62
2455 11:47:00.538879 [CA 4] Center 33 (3~64) winsize 62
2456 11:47:00.542334 [CA 5] Center 32 (3~62) winsize 60
2457 11:47:00.542421
2458 11:47:00.545206 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2459 11:47:00.545292
2460 11:47:00.549417 [CATrainingPosCal] consider 1 rank data
2461 11:47:00.552219 u2DelayCellTimex100 = 270/100 ps
2462 11:47:00.555401 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2463 11:47:00.558768 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 11:47:00.565509 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2465 11:47:00.568516 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 11:47:00.572112 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2467 11:47:00.575670 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2468 11:47:00.575793
2469 11:47:00.578631 CA PerBit enable=1, Macro0, CA PI delay=32
2470 11:47:00.578712
2471 11:47:00.582032 [CBTSetCACLKResult] CA Dly = 32
2472 11:47:00.582114 CS Dly: 6 (0~37)
2473 11:47:00.582178 ==
2474 11:47:00.585314 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 11:47:00.592527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 11:47:00.592618 ==
2477 11:47:00.595842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 11:47:00.602097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2479 11:47:00.611461 [CA 0] Center 38 (8~69) winsize 62
2480 11:47:00.614743 [CA 1] Center 38 (8~69) winsize 62
2481 11:47:00.618094 [CA 2] Center 35 (4~66) winsize 63
2482 11:47:00.621286 [CA 3] Center 34 (4~65) winsize 62
2483 11:47:00.624424 [CA 4] Center 33 (3~64) winsize 62
2484 11:47:00.628370 [CA 5] Center 32 (3~62) winsize 60
2485 11:47:00.628480
2486 11:47:00.631398 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 11:47:00.631479
2488 11:47:00.634513 [CATrainingPosCal] consider 2 rank data
2489 11:47:00.638148 u2DelayCellTimex100 = 270/100 ps
2490 11:47:00.641492 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 11:47:00.644823 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 11:47:00.651634 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2493 11:47:00.654687 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 11:47:00.658008 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2495 11:47:00.661711 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2496 11:47:00.661792
2497 11:47:00.664887 CA PerBit enable=1, Macro0, CA PI delay=32
2498 11:47:00.664966
2499 11:47:00.667900 [CBTSetCACLKResult] CA Dly = 32
2500 11:47:00.667984 CS Dly: 6 (0~38)
2501 11:47:00.668048
2502 11:47:00.671498 ----->DramcWriteLeveling(PI) begin...
2503 11:47:00.671615 ==
2504 11:47:00.674500 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 11:47:00.681753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 11:47:00.681837 ==
2507 11:47:00.684628 Write leveling (Byte 0): 34 => 34
2508 11:47:00.688129 Write leveling (Byte 1): 29 => 29
2509 11:47:00.688205 DramcWriteLeveling(PI) end<-----
2510 11:47:00.691468
2511 11:47:00.691548 ==
2512 11:47:00.694753 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:47:00.697991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:47:00.698097 ==
2515 11:47:00.701426 [Gating] SW mode calibration
2516 11:47:00.707998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 11:47:00.712011 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 11:47:00.717981 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2519 11:47:00.721359 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2520 11:47:00.725314 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 11:47:00.731717 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 11:47:00.734988 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 11:47:00.738235 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 11:47:00.745273 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2525 11:47:00.748104 0 15 28 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
2526 11:47:00.751939 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2527 11:47:00.755244 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 11:47:00.761525 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 11:47:00.765406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 11:47:00.768139 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 11:47:00.775395 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:47:00.778403 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
2533 11:47:00.781828 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2534 11:47:00.788426 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2535 11:47:00.791585 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 11:47:00.795300 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 11:47:00.801751 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 11:47:00.805048 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 11:47:00.808388 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:47:00.815371 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 11:47:00.818862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 11:47:00.822164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2543 11:47:00.828686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:47:00.831942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:47:00.835348 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:47:00.838541 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:47:00.845704 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:47:00.848942 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:47:00.852541 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:47:00.858804 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:47:00.862283 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:47:00.865284 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:47:00.872341 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:47:00.875351 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:47:00.878668 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:47:00.885470 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:47:00.888612 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 11:47:00.892335 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 11:47:00.895281 Total UI for P1: 0, mck2ui 16
2560 11:47:00.898432 best dqsien dly found for B0: ( 1, 3, 28)
2561 11:47:00.902067 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 11:47:00.905507 Total UI for P1: 0, mck2ui 16
2563 11:47:00.908784 best dqsien dly found for B1: ( 1, 4, 0)
2564 11:47:00.912072 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 11:47:00.918831 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 11:47:00.918913
2567 11:47:00.922025 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 11:47:00.925527 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 11:47:00.929333 [Gating] SW calibration Done
2570 11:47:00.929415 ==
2571 11:47:00.932734 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 11:47:00.935987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 11:47:00.936064 ==
2574 11:47:00.936138 RX Vref Scan: 0
2575 11:47:00.936198
2576 11:47:00.939378 RX Vref 0 -> 0, step: 1
2577 11:47:00.939457
2578 11:47:00.942711 RX Delay -40 -> 252, step: 8
2579 11:47:00.945698 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 11:47:00.948814 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 11:47:00.956199 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 11:47:00.958994 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 11:47:00.962533 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 11:47:00.965662 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 11:47:00.968785 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 11:47:00.972401 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 11:47:00.979149 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 11:47:00.982309 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 11:47:00.985549 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 11:47:00.988913 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 11:47:00.992239 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 11:47:00.998856 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 11:47:01.002420 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 11:47:01.005536 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 11:47:01.005641 ==
2596 11:47:01.009029 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 11:47:01.012508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 11:47:01.012601 ==
2599 11:47:01.015928 DQS Delay:
2600 11:47:01.016004 DQS0 = 0, DQS1 = 0
2601 11:47:01.018931 DQM Delay:
2602 11:47:01.019006 DQM0 = 121, DQM1 = 113
2603 11:47:01.022797 DQ Delay:
2604 11:47:01.025906 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 11:47:01.029082 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 11:47:01.032342 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 11:47:01.035698 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2608 11:47:01.035776
2609 11:47:01.035843
2610 11:47:01.035921 ==
2611 11:47:01.038925 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 11:47:01.042258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 11:47:01.042331 ==
2614 11:47:01.042397
2615 11:47:01.042468
2616 11:47:01.045494 TX Vref Scan disable
2617 11:47:01.049440 == TX Byte 0 ==
2618 11:47:01.052557 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2619 11:47:01.055788 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2620 11:47:01.059153 == TX Byte 1 ==
2621 11:47:01.062427 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2622 11:47:01.065674 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2623 11:47:01.065764 ==
2624 11:47:01.068988 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 11:47:01.072287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 11:47:01.075586 ==
2627 11:47:01.086061 TX Vref=22, minBit 0, minWin=24, winSum=411
2628 11:47:01.089572 TX Vref=24, minBit 0, minWin=25, winSum=418
2629 11:47:01.092652 TX Vref=26, minBit 4, minWin=25, winSum=422
2630 11:47:01.096236 TX Vref=28, minBit 0, minWin=26, winSum=425
2631 11:47:01.099706 TX Vref=30, minBit 0, minWin=26, winSum=423
2632 11:47:01.102659 TX Vref=32, minBit 12, minWin=25, winSum=423
2633 11:47:01.109721 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
2634 11:47:01.109821
2635 11:47:01.112771 Final TX Range 1 Vref 28
2636 11:47:01.112856
2637 11:47:01.112947 ==
2638 11:47:01.115863 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 11:47:01.119704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 11:47:01.119824 ==
2641 11:47:01.119928
2642 11:47:01.122689
2643 11:47:01.122771 TX Vref Scan disable
2644 11:47:01.126209 == TX Byte 0 ==
2645 11:47:01.129226 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2646 11:47:01.132704 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2647 11:47:01.136586 == TX Byte 1 ==
2648 11:47:01.139693 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2649 11:47:01.142480 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2650 11:47:01.142553
2651 11:47:01.146146 [DATLAT]
2652 11:47:01.146222 Freq=1200, CH0 RK0
2653 11:47:01.146285
2654 11:47:01.149425 DATLAT Default: 0xd
2655 11:47:01.149502 0, 0xFFFF, sum = 0
2656 11:47:01.152801 1, 0xFFFF, sum = 0
2657 11:47:01.152881 2, 0xFFFF, sum = 0
2658 11:47:01.156583 3, 0xFFFF, sum = 0
2659 11:47:01.156658 4, 0xFFFF, sum = 0
2660 11:47:01.159724 5, 0xFFFF, sum = 0
2661 11:47:01.159797 6, 0xFFFF, sum = 0
2662 11:47:01.162882 7, 0xFFFF, sum = 0
2663 11:47:01.162953 8, 0xFFFF, sum = 0
2664 11:47:01.166210 9, 0xFFFF, sum = 0
2665 11:47:01.166289 10, 0xFFFF, sum = 0
2666 11:47:01.169519 11, 0xFFFF, sum = 0
2667 11:47:01.172798 12, 0x0, sum = 1
2668 11:47:01.172889 13, 0x0, sum = 2
2669 11:47:01.172978 14, 0x0, sum = 3
2670 11:47:01.176048 15, 0x0, sum = 4
2671 11:47:01.176130 best_step = 13
2672 11:47:01.176194
2673 11:47:01.176277 ==
2674 11:47:01.179338 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:47:01.186704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:47:01.186820 ==
2677 11:47:01.186886 RX Vref Scan: 1
2678 11:47:01.186960
2679 11:47:01.189937 Set Vref Range= 32 -> 127
2680 11:47:01.190017
2681 11:47:01.193162 RX Vref 32 -> 127, step: 1
2682 11:47:01.193240
2683 11:47:01.196446 RX Delay -13 -> 252, step: 4
2684 11:47:01.196522
2685 11:47:01.199774 Set Vref, RX VrefLevel [Byte0]: 32
2686 11:47:01.203067 [Byte1]: 32
2687 11:47:01.203141
2688 11:47:01.205974 Set Vref, RX VrefLevel [Byte0]: 33
2689 11:47:01.209859 [Byte1]: 33
2690 11:47:01.209941
2691 11:47:01.212806 Set Vref, RX VrefLevel [Byte0]: 34
2692 11:47:01.216394 [Byte1]: 34
2693 11:47:01.220353
2694 11:47:01.220431 Set Vref, RX VrefLevel [Byte0]: 35
2695 11:47:01.223543 [Byte1]: 35
2696 11:47:01.228358
2697 11:47:01.228459 Set Vref, RX VrefLevel [Byte0]: 36
2698 11:47:01.231412 [Byte1]: 36
2699 11:47:01.236212
2700 11:47:01.236287 Set Vref, RX VrefLevel [Byte0]: 37
2701 11:47:01.239399 [Byte1]: 37
2702 11:47:01.243717
2703 11:47:01.243839 Set Vref, RX VrefLevel [Byte0]: 38
2704 11:47:01.247036 [Byte1]: 38
2705 11:47:01.251897
2706 11:47:01.252001 Set Vref, RX VrefLevel [Byte0]: 39
2707 11:47:01.255244 [Byte1]: 39
2708 11:47:01.259979
2709 11:47:01.260082 Set Vref, RX VrefLevel [Byte0]: 40
2710 11:47:01.263191 [Byte1]: 40
2711 11:47:01.267667
2712 11:47:01.267751 Set Vref, RX VrefLevel [Byte0]: 41
2713 11:47:01.270933 [Byte1]: 41
2714 11:47:01.275425
2715 11:47:01.275503 Set Vref, RX VrefLevel [Byte0]: 42
2716 11:47:01.279346 [Byte1]: 42
2717 11:47:01.282895
2718 11:47:01.282971 Set Vref, RX VrefLevel [Byte0]: 43
2719 11:47:01.286893 [Byte1]: 43
2720 11:47:01.291070
2721 11:47:01.291149 Set Vref, RX VrefLevel [Byte0]: 44
2722 11:47:01.294334 [Byte1]: 44
2723 11:47:01.298820
2724 11:47:01.298894 Set Vref, RX VrefLevel [Byte0]: 45
2725 11:47:01.302694 [Byte1]: 45
2726 11:47:01.306833
2727 11:47:01.306914 Set Vref, RX VrefLevel [Byte0]: 46
2728 11:47:01.310102 [Byte1]: 46
2729 11:47:01.314711
2730 11:47:01.314808 Set Vref, RX VrefLevel [Byte0]: 47
2731 11:47:01.317870 [Byte1]: 47
2732 11:47:01.322612
2733 11:47:01.322716 Set Vref, RX VrefLevel [Byte0]: 48
2734 11:47:01.325729 [Byte1]: 48
2735 11:47:01.330630
2736 11:47:01.330738 Set Vref, RX VrefLevel [Byte0]: 49
2737 11:47:01.333812 [Byte1]: 49
2738 11:47:01.338827
2739 11:47:01.338907 Set Vref, RX VrefLevel [Byte0]: 50
2740 11:47:01.341903 [Byte1]: 50
2741 11:47:01.346502
2742 11:47:01.346613 Set Vref, RX VrefLevel [Byte0]: 51
2743 11:47:01.349390 [Byte1]: 51
2744 11:47:01.354429
2745 11:47:01.354514 Set Vref, RX VrefLevel [Byte0]: 52
2746 11:47:01.357924 [Byte1]: 52
2747 11:47:01.361922
2748 11:47:01.362039 Set Vref, RX VrefLevel [Byte0]: 53
2749 11:47:01.365550 [Byte1]: 53
2750 11:47:01.370338
2751 11:47:01.370438 Set Vref, RX VrefLevel [Byte0]: 54
2752 11:47:01.373564 [Byte1]: 54
2753 11:47:01.377921
2754 11:47:01.378002 Set Vref, RX VrefLevel [Byte0]: 55
2755 11:47:01.381187 [Byte1]: 55
2756 11:47:01.385856
2757 11:47:01.385937 Set Vref, RX VrefLevel [Byte0]: 56
2758 11:47:01.389270 [Byte1]: 56
2759 11:47:01.393947
2760 11:47:01.394028 Set Vref, RX VrefLevel [Byte0]: 57
2761 11:47:01.397276 [Byte1]: 57
2762 11:47:01.401710
2763 11:47:01.401791 Set Vref, RX VrefLevel [Byte0]: 58
2764 11:47:01.405013 [Byte1]: 58
2765 11:47:01.409622
2766 11:47:01.409726 Set Vref, RX VrefLevel [Byte0]: 59
2767 11:47:01.412893 [Byte1]: 59
2768 11:47:01.417517
2769 11:47:01.417647 Set Vref, RX VrefLevel [Byte0]: 60
2770 11:47:01.420802 [Byte1]: 60
2771 11:47:01.425158
2772 11:47:01.425267 Set Vref, RX VrefLevel [Byte0]: 61
2773 11:47:01.428899 [Byte1]: 61
2774 11:47:01.433164
2775 11:47:01.433248 Set Vref, RX VrefLevel [Byte0]: 62
2776 11:47:01.436427 [Byte1]: 62
2777 11:47:01.441026
2778 11:47:01.441109 Set Vref, RX VrefLevel [Byte0]: 63
2779 11:47:01.444772 [Byte1]: 63
2780 11:47:01.449265
2781 11:47:01.449348 Set Vref, RX VrefLevel [Byte0]: 64
2782 11:47:01.452569 [Byte1]: 64
2783 11:47:01.456927
2784 11:47:01.457012 Set Vref, RX VrefLevel [Byte0]: 65
2785 11:47:01.460578 [Byte1]: 65
2786 11:47:01.465029
2787 11:47:01.465112 Set Vref, RX VrefLevel [Byte0]: 66
2788 11:47:01.468071 [Byte1]: 66
2789 11:47:01.472844
2790 11:47:01.472926 Set Vref, RX VrefLevel [Byte0]: 67
2791 11:47:01.475716 [Byte1]: 67
2792 11:47:01.480536
2793 11:47:01.480619 Set Vref, RX VrefLevel [Byte0]: 68
2794 11:47:01.483674 [Byte1]: 68
2795 11:47:01.488697
2796 11:47:01.488780 Set Vref, RX VrefLevel [Byte0]: 69
2797 11:47:01.492031 [Byte1]: 69
2798 11:47:01.496093
2799 11:47:01.496175 Final RX Vref Byte 0 = 54 to rank0
2800 11:47:01.499445 Final RX Vref Byte 1 = 58 to rank0
2801 11:47:01.503374 Final RX Vref Byte 0 = 54 to rank1
2802 11:47:01.506652 Final RX Vref Byte 1 = 58 to rank1==
2803 11:47:01.509976 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 11:47:01.513418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 11:47:01.516369 ==
2806 11:47:01.516451 DQS Delay:
2807 11:47:01.516515 DQS0 = 0, DQS1 = 0
2808 11:47:01.519690 DQM Delay:
2809 11:47:01.519772 DQM0 = 120, DQM1 = 114
2810 11:47:01.523474 DQ Delay:
2811 11:47:01.526785 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2812 11:47:01.530095 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2813 11:47:01.533119 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2814 11:47:01.536832 DQ12 =120, DQ13 =120, DQ14 =128, DQ15 =124
2815 11:47:01.536914
2816 11:47:01.536978
2817 11:47:01.543395 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2818 11:47:01.546519 CH0 RK0: MR19=404, MR18=150E
2819 11:47:01.553178 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2820 11:47:01.553261
2821 11:47:01.556388 ----->DramcWriteLeveling(PI) begin...
2822 11:47:01.556470 ==
2823 11:47:01.559608 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 11:47:01.562878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 11:47:01.566674 ==
2826 11:47:01.566754 Write leveling (Byte 0): 33 => 33
2827 11:47:01.569790 Write leveling (Byte 1): 31 => 31
2828 11:47:01.573300 DramcWriteLeveling(PI) end<-----
2829 11:47:01.573380
2830 11:47:01.573443 ==
2831 11:47:01.576413 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 11:47:01.583187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 11:47:01.583269 ==
2834 11:47:01.583333 [Gating] SW mode calibration
2835 11:47:01.593320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 11:47:01.596250 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 11:47:01.599422 0 15 0 | B1->B0 | 3333 302f | 0 1 | (0 0) (0 0)
2838 11:47:01.606620 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 11:47:01.609866 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:47:01.613085 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 11:47:01.619665 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 11:47:01.623098 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 11:47:01.626486 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 11:47:01.632864 0 15 28 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 0)
2845 11:47:01.636641 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 11:47:01.639815 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 11:47:01.646831 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:47:01.650140 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:47:01.653307 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:47:01.659972 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 11:47:01.663103 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 11:47:01.666425 1 0 28 | B1->B0 | 3d3d 3f3e | 0 1 | (0 0) (0 0)
2853 11:47:01.673513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 11:47:01.676714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 11:47:01.679760 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:47:01.683381 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:47:01.690095 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:47:01.693768 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:47:01.696893 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:47:01.703864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2861 11:47:01.706717 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 11:47:01.710421 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:47:01.716736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:47:01.720073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:47:01.723345 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:47:01.730045 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:47:01.733897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:47:01.737346 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:47:01.740480 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:47:01.746799 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:47:01.750547 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:47:01.753600 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:47:01.760681 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:47:01.763760 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:47:01.766860 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:47:01.773491 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:47:01.777408 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 11:47:01.780765 Total UI for P1: 0, mck2ui 16
2879 11:47:01.784096 best dqsien dly found for B0: ( 1, 3, 30)
2880 11:47:01.787242 Total UI for P1: 0, mck2ui 16
2881 11:47:01.790251 best dqsien dly found for B1: ( 1, 3, 30)
2882 11:47:01.793920 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2883 11:47:01.796872 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2884 11:47:01.796943
2885 11:47:01.800614 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2886 11:47:01.803950 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2887 11:47:01.806875 [Gating] SW calibration Done
2888 11:47:01.806952 ==
2889 11:47:01.810203 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 11:47:01.814089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 11:47:01.814168 ==
2892 11:47:01.817098 RX Vref Scan: 0
2893 11:47:01.817169
2894 11:47:01.820109 RX Vref 0 -> 0, step: 1
2895 11:47:01.820207
2896 11:47:01.820285 RX Delay -40 -> 252, step: 8
2897 11:47:01.827376 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2898 11:47:01.830583 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2899 11:47:01.834084 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2900 11:47:01.837125 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2901 11:47:01.840445 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2902 11:47:01.847408 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2903 11:47:01.850519 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2904 11:47:01.853867 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2905 11:47:01.857022 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
2906 11:47:01.860957 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2907 11:47:01.867577 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2908 11:47:01.870611 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2909 11:47:01.873729 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2910 11:47:01.877506 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2911 11:47:01.880848 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2912 11:47:01.887539 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2913 11:47:01.887620 ==
2914 11:47:01.890821 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 11:47:01.893980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 11:47:01.894074 ==
2917 11:47:01.894137 DQS Delay:
2918 11:47:01.897143 DQS0 = 0, DQS1 = 0
2919 11:47:01.897223 DQM Delay:
2920 11:47:01.900861 DQM0 = 121, DQM1 = 114
2921 11:47:01.900956 DQ Delay:
2922 11:47:01.903976 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2923 11:47:01.907604 DQ4 =127, DQ5 =119, DQ6 =123, DQ7 =127
2924 11:47:01.910587 DQ8 =107, DQ9 =99, DQ10 =115, DQ11 =107
2925 11:47:01.913907 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2926 11:47:01.914004
2927 11:47:01.914098
2928 11:47:01.914172 ==
2929 11:47:01.917685 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:47:01.924048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:47:01.924146 ==
2932 11:47:01.924240
2933 11:47:01.924314
2934 11:47:01.924414 TX Vref Scan disable
2935 11:47:01.927860 == TX Byte 0 ==
2936 11:47:01.930918 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2937 11:47:01.934440 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2938 11:47:01.937798 == TX Byte 1 ==
2939 11:47:01.940992 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2940 11:47:01.944686 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2941 11:47:01.948064 ==
2942 11:47:01.951199 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 11:47:01.954439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 11:47:01.954521 ==
2945 11:47:01.965777 TX Vref=22, minBit 1, minWin=25, winSum=414
2946 11:47:01.969016 TX Vref=24, minBit 1, minWin=25, winSum=420
2947 11:47:01.972851 TX Vref=26, minBit 3, minWin=25, winSum=424
2948 11:47:01.975966 TX Vref=28, minBit 0, minWin=26, winSum=426
2949 11:47:01.979097 TX Vref=30, minBit 13, minWin=25, winSum=424
2950 11:47:01.983030 TX Vref=32, minBit 0, minWin=26, winSum=427
2951 11:47:01.989436 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 32
2952 11:47:01.989518
2953 11:47:01.992750 Final TX Range 1 Vref 32
2954 11:47:01.992831
2955 11:47:01.992895 ==
2956 11:47:01.995952 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:47:01.999252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:47:01.999333 ==
2959 11:47:01.999397
2960 11:47:01.999455
2961 11:47:02.002507 TX Vref Scan disable
2962 11:47:02.006486 == TX Byte 0 ==
2963 11:47:02.009196 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2964 11:47:02.012683 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2965 11:47:02.016488 == TX Byte 1 ==
2966 11:47:02.019639 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2967 11:47:02.023393 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2968 11:47:02.023475
2969 11:47:02.026287 [DATLAT]
2970 11:47:02.026368 Freq=1200, CH0 RK1
2971 11:47:02.026433
2972 11:47:02.029844 DATLAT Default: 0xd
2973 11:47:02.029927 0, 0xFFFF, sum = 0
2974 11:47:02.033053 1, 0xFFFF, sum = 0
2975 11:47:02.033136 2, 0xFFFF, sum = 0
2976 11:47:02.036222 3, 0xFFFF, sum = 0
2977 11:47:02.036305 4, 0xFFFF, sum = 0
2978 11:47:02.039541 5, 0xFFFF, sum = 0
2979 11:47:02.039625 6, 0xFFFF, sum = 0
2980 11:47:02.043460 7, 0xFFFF, sum = 0
2981 11:47:02.043543 8, 0xFFFF, sum = 0
2982 11:47:02.046368 9, 0xFFFF, sum = 0
2983 11:47:02.046466 10, 0xFFFF, sum = 0
2984 11:47:02.050043 11, 0xFFFF, sum = 0
2985 11:47:02.050136 12, 0x0, sum = 1
2986 11:47:02.053027 13, 0x0, sum = 2
2987 11:47:02.053109 14, 0x0, sum = 3
2988 11:47:02.056455 15, 0x0, sum = 4
2989 11:47:02.056553 best_step = 13
2990 11:47:02.056631
2991 11:47:02.056707 ==
2992 11:47:02.059474 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 11:47:02.066128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 11:47:02.066207 ==
2995 11:47:02.066271 RX Vref Scan: 0
2996 11:47:02.066331
2997 11:47:02.069593 RX Vref 0 -> 0, step: 1
2998 11:47:02.069683
2999 11:47:02.072921 RX Delay -13 -> 252, step: 4
3000 11:47:02.076183 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3001 11:47:02.079441 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3002 11:47:02.086320 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3003 11:47:02.089497 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3004 11:47:02.092672 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3005 11:47:02.096745 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3006 11:47:02.099945 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3007 11:47:02.103231 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3008 11:47:02.109935 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3009 11:47:02.113203 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3010 11:47:02.116221 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3011 11:47:02.120000 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3012 11:47:02.123244 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3013 11:47:02.129710 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3014 11:47:02.132897 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3015 11:47:02.136394 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3016 11:47:02.136478 ==
3017 11:47:02.139822 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 11:47:02.142955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 11:47:02.146268 ==
3020 11:47:02.146350 DQS Delay:
3021 11:47:02.146414 DQS0 = 0, DQS1 = 0
3022 11:47:02.149568 DQM Delay:
3023 11:47:02.149686 DQM0 = 121, DQM1 = 112
3024 11:47:02.153313 DQ Delay:
3025 11:47:02.156458 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3026 11:47:02.159547 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3027 11:47:02.162890 DQ8 =102, DQ9 =98, DQ10 =112, DQ11 =106
3028 11:47:02.166571 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3029 11:47:02.166667
3030 11:47:02.166731
3031 11:47:02.172957 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3032 11:47:02.176317 CH0 RK1: MR19=403, MR18=DEE
3033 11:47:02.183161 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3034 11:47:02.186764 [RxdqsGatingPostProcess] freq 1200
3035 11:47:02.189859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 11:47:02.193115 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 11:47:02.196757 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 11:47:02.200006 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 11:47:02.203310 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 11:47:02.206453 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 11:47:02.209729 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 11:47:02.213198 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 11:47:02.217065 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 11:47:02.219891 Pre-setting of DQS Precalculation
3045 11:47:02.223616 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 11:47:02.223699 ==
3047 11:47:02.227061 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 11:47:02.233525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 11:47:02.233646 ==
3050 11:47:02.236858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 11:47:02.243206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3052 11:47:02.252239 [CA 0] Center 37 (7~68) winsize 62
3053 11:47:02.255146 [CA 1] Center 37 (7~68) winsize 62
3054 11:47:02.259009 [CA 2] Center 35 (5~65) winsize 61
3055 11:47:02.262356 [CA 3] Center 34 (4~64) winsize 61
3056 11:47:02.265500 [CA 4] Center 34 (4~64) winsize 61
3057 11:47:02.268815 [CA 5] Center 33 (3~63) winsize 61
3058 11:47:02.268896
3059 11:47:02.272007 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 11:47:02.272088
3061 11:47:02.275520 [CATrainingPosCal] consider 1 rank data
3062 11:47:02.279021 u2DelayCellTimex100 = 270/100 ps
3063 11:47:02.282054 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 11:47:02.285727 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 11:47:02.288741 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 11:47:02.295417 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3067 11:47:02.298800 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 11:47:02.302610 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3069 11:47:02.302693
3070 11:47:02.305391 CA PerBit enable=1, Macro0, CA PI delay=33
3071 11:47:02.305472
3072 11:47:02.308953 [CBTSetCACLKResult] CA Dly = 33
3073 11:47:02.309036 CS Dly: 7 (0~38)
3074 11:47:02.309100 ==
3075 11:47:02.312069 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 11:47:02.318795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 11:47:02.318879 ==
3078 11:47:02.322080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 11:47:02.328780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3080 11:47:02.337435 [CA 0] Center 37 (7~68) winsize 62
3081 11:47:02.340734 [CA 1] Center 38 (8~68) winsize 61
3082 11:47:02.344515 [CA 2] Center 35 (5~65) winsize 61
3083 11:47:02.347743 [CA 3] Center 34 (4~65) winsize 62
3084 11:47:02.351078 [CA 4] Center 35 (5~65) winsize 61
3085 11:47:02.354291 [CA 5] Center 34 (4~64) winsize 61
3086 11:47:02.354373
3087 11:47:02.357943 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 11:47:02.358025
3089 11:47:02.360903 [CATrainingPosCal] consider 2 rank data
3090 11:47:02.364530 u2DelayCellTimex100 = 270/100 ps
3091 11:47:02.367506 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 11:47:02.371210 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 11:47:02.377833 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 11:47:02.381040 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 11:47:02.384044 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3096 11:47:02.387356 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3097 11:47:02.387467
3098 11:47:02.390578 CA PerBit enable=1, Macro0, CA PI delay=33
3099 11:47:02.390660
3100 11:47:02.394686 [CBTSetCACLKResult] CA Dly = 33
3101 11:47:02.394842 CS Dly: 8 (0~41)
3102 11:47:02.395065
3103 11:47:02.397830 ----->DramcWriteLeveling(PI) begin...
3104 11:47:02.400856 ==
3105 11:47:02.400962 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 11:47:02.407884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 11:47:02.407967 ==
3108 11:47:02.410719 Write leveling (Byte 0): 26 => 26
3109 11:47:02.414388 Write leveling (Byte 1): 28 => 28
3110 11:47:02.414470 DramcWriteLeveling(PI) end<-----
3111 11:47:02.417527
3112 11:47:02.417650 ==
3113 11:47:02.421310 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:47:02.424251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:47:02.424335 ==
3116 11:47:02.427898 [Gating] SW mode calibration
3117 11:47:02.434518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 11:47:02.437589 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 11:47:02.444408 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 11:47:02.447787 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 11:47:02.450974 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 11:47:02.457449 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:47:02.461146 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 11:47:02.464376 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 11:47:02.471300 0 15 24 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
3126 11:47:02.474514 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 11:47:02.477494 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 11:47:02.484575 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 11:47:02.487693 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:47:02.491433 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:47:02.494631 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:47:02.501198 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:47:02.504574 1 0 24 | B1->B0 | 2c2c 3737 | 1 0 | (0 0) (0 0)
3134 11:47:02.507682 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 11:47:02.514787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 11:47:02.517881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:47:02.521016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:47:02.527745 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:47:02.531190 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:47:02.534584 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:47:02.541290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 11:47:02.544514 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 11:47:02.548164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:47:02.554657 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:47:02.557947 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:47:02.561130 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:47:02.568024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:47:02.571262 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:47:02.575157 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:47:02.578366 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:47:02.585195 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:47:02.588470 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:47:02.591727 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:47:02.598073 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:47:02.601753 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:47:02.605104 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:47:02.611596 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 11:47:02.614756 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 11:47:02.618531 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 11:47:02.621757 Total UI for P1: 0, mck2ui 16
3161 11:47:02.624874 best dqsien dly found for B0: ( 1, 3, 26)
3162 11:47:02.628265 Total UI for P1: 0, mck2ui 16
3163 11:47:02.631609 best dqsien dly found for B1: ( 1, 3, 26)
3164 11:47:02.634676 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3165 11:47:02.637999 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 11:47:02.638080
3167 11:47:02.641723 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 11:47:02.648510 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 11:47:02.648592 [Gating] SW calibration Done
3170 11:47:02.648656 ==
3171 11:47:02.651320 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:47:02.658742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:47:02.658826 ==
3174 11:47:02.658893 RX Vref Scan: 0
3175 11:47:02.658958
3176 11:47:02.661472 RX Vref 0 -> 0, step: 1
3177 11:47:02.661601
3178 11:47:02.664879 RX Delay -40 -> 252, step: 8
3179 11:47:02.668506 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 11:47:02.671609 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 11:47:02.674681 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 11:47:02.681726 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3183 11:47:02.684949 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3184 11:47:02.688086 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3185 11:47:02.691825 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3186 11:47:02.694748 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3187 11:47:02.701386 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3188 11:47:02.705128 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3189 11:47:02.708340 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 11:47:02.711548 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3191 11:47:02.714877 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 11:47:02.721855 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3193 11:47:02.725009 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3194 11:47:02.728324 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3195 11:47:02.728405 ==
3196 11:47:02.731636 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:47:02.734891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:47:02.734973 ==
3199 11:47:02.738195 DQS Delay:
3200 11:47:02.738276 DQS0 = 0, DQS1 = 0
3201 11:47:02.741505 DQM Delay:
3202 11:47:02.741633 DQM0 = 119, DQM1 = 116
3203 11:47:02.741713 DQ Delay:
3204 11:47:02.745114 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3205 11:47:02.751527 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3206 11:47:02.754672 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3207 11:47:02.757955 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3208 11:47:02.758036
3209 11:47:02.758098
3210 11:47:02.758157 ==
3211 11:47:02.761786 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:47:02.764838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:47:02.764975 ==
3214 11:47:02.765066
3215 11:47:02.765153
3216 11:47:02.768410 TX Vref Scan disable
3217 11:47:02.771617 == TX Byte 0 ==
3218 11:47:02.774642 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3219 11:47:02.778070 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3220 11:47:02.781536 == TX Byte 1 ==
3221 11:47:02.785001 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3222 11:47:02.787863 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3223 11:47:02.787945 ==
3224 11:47:02.791693 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 11:47:02.795128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 11:47:02.795211 ==
3227 11:47:02.807959 TX Vref=22, minBit 11, minWin=24, winSum=413
3228 11:47:02.811215 TX Vref=24, minBit 9, minWin=24, winSum=417
3229 11:47:02.814505 TX Vref=26, minBit 0, minWin=26, winSum=424
3230 11:47:02.817685 TX Vref=28, minBit 1, minWin=26, winSum=426
3231 11:47:02.821648 TX Vref=30, minBit 2, minWin=26, winSum=432
3232 11:47:02.824710 TX Vref=32, minBit 9, minWin=26, winSum=433
3233 11:47:02.831730 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3234 11:47:02.831813
3235 11:47:02.835054 Final TX Range 1 Vref 32
3236 11:47:02.835136
3237 11:47:02.835199 ==
3238 11:47:02.838375 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:47:02.841444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:47:02.841526 ==
3241 11:47:02.841631
3242 11:47:02.841692
3243 11:47:02.844867 TX Vref Scan disable
3244 11:47:02.848059 == TX Byte 0 ==
3245 11:47:02.851217 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3246 11:47:02.854573 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3247 11:47:02.857775 == TX Byte 1 ==
3248 11:47:02.861687 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3249 11:47:02.864890 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3250 11:47:02.864972
3251 11:47:02.868256 [DATLAT]
3252 11:47:02.868337 Freq=1200, CH1 RK0
3253 11:47:02.868401
3254 11:47:02.871320 DATLAT Default: 0xd
3255 11:47:02.871402 0, 0xFFFF, sum = 0
3256 11:47:02.874763 1, 0xFFFF, sum = 0
3257 11:47:02.874846 2, 0xFFFF, sum = 0
3258 11:47:02.878398 3, 0xFFFF, sum = 0
3259 11:47:02.878481 4, 0xFFFF, sum = 0
3260 11:47:02.881740 5, 0xFFFF, sum = 0
3261 11:47:02.881822 6, 0xFFFF, sum = 0
3262 11:47:02.884924 7, 0xFFFF, sum = 0
3263 11:47:02.885038 8, 0xFFFF, sum = 0
3264 11:47:02.888202 9, 0xFFFF, sum = 0
3265 11:47:02.888284 10, 0xFFFF, sum = 0
3266 11:47:02.891405 11, 0xFFFF, sum = 0
3267 11:47:02.891487 12, 0x0, sum = 1
3268 11:47:02.894596 13, 0x0, sum = 2
3269 11:47:02.894679 14, 0x0, sum = 3
3270 11:47:02.898248 15, 0x0, sum = 4
3271 11:47:02.898330 best_step = 13
3272 11:47:02.898395
3273 11:47:02.898454 ==
3274 11:47:02.901508 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 11:47:02.908209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 11:47:02.908324 ==
3277 11:47:02.908387 RX Vref Scan: 1
3278 11:47:02.908446
3279 11:47:02.911496 Set Vref Range= 32 -> 127
3280 11:47:02.911579
3281 11:47:02.915004 RX Vref 32 -> 127, step: 1
3282 11:47:02.915085
3283 11:47:02.915149 RX Delay -5 -> 252, step: 4
3284 11:47:02.918543
3285 11:47:02.918624 Set Vref, RX VrefLevel [Byte0]: 32
3286 11:47:02.921801 [Byte1]: 32
3287 11:47:02.926192
3288 11:47:02.926274 Set Vref, RX VrefLevel [Byte0]: 33
3289 11:47:02.929144 [Byte1]: 33
3290 11:47:02.933807
3291 11:47:02.933888 Set Vref, RX VrefLevel [Byte0]: 34
3292 11:47:02.937196 [Byte1]: 34
3293 11:47:02.941761
3294 11:47:02.941842 Set Vref, RX VrefLevel [Byte0]: 35
3295 11:47:02.945065 [Byte1]: 35
3296 11:47:02.949685
3297 11:47:02.949767 Set Vref, RX VrefLevel [Byte0]: 36
3298 11:47:02.952981 [Byte1]: 36
3299 11:47:02.957524
3300 11:47:02.957626 Set Vref, RX VrefLevel [Byte0]: 37
3301 11:47:02.960769 [Byte1]: 37
3302 11:47:02.965522
3303 11:47:02.965646 Set Vref, RX VrefLevel [Byte0]: 38
3304 11:47:02.968791 [Byte1]: 38
3305 11:47:02.973420
3306 11:47:02.973526 Set Vref, RX VrefLevel [Byte0]: 39
3307 11:47:02.976846 [Byte1]: 39
3308 11:47:02.981101
3309 11:47:02.981182 Set Vref, RX VrefLevel [Byte0]: 40
3310 11:47:02.984474 [Byte1]: 40
3311 11:47:02.988744
3312 11:47:02.988840 Set Vref, RX VrefLevel [Byte0]: 41
3313 11:47:02.992101 [Byte1]: 41
3314 11:47:02.996675
3315 11:47:02.996756 Set Vref, RX VrefLevel [Byte0]: 42
3316 11:47:02.999966 [Byte1]: 42
3317 11:47:03.004486
3318 11:47:03.004567 Set Vref, RX VrefLevel [Byte0]: 43
3319 11:47:03.007582 [Byte1]: 43
3320 11:47:03.012111
3321 11:47:03.012192 Set Vref, RX VrefLevel [Byte0]: 44
3322 11:47:03.015750 [Byte1]: 44
3323 11:47:03.020454
3324 11:47:03.020535 Set Vref, RX VrefLevel [Byte0]: 45
3325 11:47:03.023788 [Byte1]: 45
3326 11:47:03.028200
3327 11:47:03.028313 Set Vref, RX VrefLevel [Byte0]: 46
3328 11:47:03.031255 [Byte1]: 46
3329 11:47:03.036155
3330 11:47:03.036293 Set Vref, RX VrefLevel [Byte0]: 47
3331 11:47:03.039073 [Byte1]: 47
3332 11:47:03.043555
3333 11:47:03.043636 Set Vref, RX VrefLevel [Byte0]: 48
3334 11:47:03.047049 [Byte1]: 48
3335 11:47:03.051604
3336 11:47:03.051685 Set Vref, RX VrefLevel [Byte0]: 49
3337 11:47:03.054757 [Byte1]: 49
3338 11:47:03.059794
3339 11:47:03.059878 Set Vref, RX VrefLevel [Byte0]: 50
3340 11:47:03.062973 [Byte1]: 50
3341 11:47:03.067646
3342 11:47:03.067733 Set Vref, RX VrefLevel [Byte0]: 51
3343 11:47:03.070867 [Byte1]: 51
3344 11:47:03.074990
3345 11:47:03.075072 Set Vref, RX VrefLevel [Byte0]: 52
3346 11:47:03.078713 [Byte1]: 52
3347 11:47:03.083390
3348 11:47:03.083472 Set Vref, RX VrefLevel [Byte0]: 53
3349 11:47:03.086621 [Byte1]: 53
3350 11:47:03.091119
3351 11:47:03.091200 Set Vref, RX VrefLevel [Byte0]: 54
3352 11:47:03.094379 [Byte1]: 54
3353 11:47:03.099071
3354 11:47:03.099156 Set Vref, RX VrefLevel [Byte0]: 55
3355 11:47:03.102399 [Byte1]: 55
3356 11:47:03.106907
3357 11:47:03.107007 Set Vref, RX VrefLevel [Byte0]: 56
3358 11:47:03.110281 [Byte1]: 56
3359 11:47:03.114598
3360 11:47:03.114708 Set Vref, RX VrefLevel [Byte0]: 57
3361 11:47:03.117536 [Byte1]: 57
3362 11:47:03.122617
3363 11:47:03.122699 Set Vref, RX VrefLevel [Byte0]: 58
3364 11:47:03.125499 [Byte1]: 58
3365 11:47:03.129944
3366 11:47:03.130026 Set Vref, RX VrefLevel [Byte0]: 59
3367 11:47:03.133297 [Byte1]: 59
3368 11:47:03.137805
3369 11:47:03.137887 Set Vref, RX VrefLevel [Byte0]: 60
3370 11:47:03.141088 [Byte1]: 60
3371 11:47:03.145955
3372 11:47:03.146037 Set Vref, RX VrefLevel [Byte0]: 61
3373 11:47:03.149186 [Byte1]: 61
3374 11:47:03.153543
3375 11:47:03.153656 Set Vref, RX VrefLevel [Byte0]: 62
3376 11:47:03.156922 [Byte1]: 62
3377 11:47:03.161249
3378 11:47:03.161330 Set Vref, RX VrefLevel [Byte0]: 63
3379 11:47:03.164816 [Byte1]: 63
3380 11:47:03.169425
3381 11:47:03.169505 Set Vref, RX VrefLevel [Byte0]: 64
3382 11:47:03.172510 [Byte1]: 64
3383 11:47:03.177215
3384 11:47:03.177296 Set Vref, RX VrefLevel [Byte0]: 65
3385 11:47:03.180845 [Byte1]: 65
3386 11:47:03.185106
3387 11:47:03.185188 Set Vref, RX VrefLevel [Byte0]: 66
3388 11:47:03.188080 [Byte1]: 66
3389 11:47:03.193280
3390 11:47:03.193361 Set Vref, RX VrefLevel [Byte0]: 67
3391 11:47:03.196380 [Byte1]: 67
3392 11:47:03.201121
3393 11:47:03.201204 Set Vref, RX VrefLevel [Byte0]: 68
3394 11:47:03.204139 [Byte1]: 68
3395 11:47:03.208742
3396 11:47:03.208823 Final RX Vref Byte 0 = 55 to rank0
3397 11:47:03.211994 Final RX Vref Byte 1 = 48 to rank0
3398 11:47:03.215146 Final RX Vref Byte 0 = 55 to rank1
3399 11:47:03.218398 Final RX Vref Byte 1 = 48 to rank1==
3400 11:47:03.221737 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 11:47:03.225439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 11:47:03.228823 ==
3403 11:47:03.228906 DQS Delay:
3404 11:47:03.228969 DQS0 = 0, DQS1 = 0
3405 11:47:03.232107 DQM Delay:
3406 11:47:03.232188 DQM0 = 120, DQM1 = 116
3407 11:47:03.235527 DQ Delay:
3408 11:47:03.238594 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3409 11:47:03.241885 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3410 11:47:03.245277 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3411 11:47:03.248576 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3412 11:47:03.248658
3413 11:47:03.248722
3414 11:47:03.255426 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3415 11:47:03.258578 CH1 RK0: MR19=404, MR18=417
3416 11:47:03.265199 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3417 11:47:03.265282
3418 11:47:03.269022 ----->DramcWriteLeveling(PI) begin...
3419 11:47:03.269105 ==
3420 11:47:03.272177 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 11:47:03.275440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 11:47:03.275522 ==
3423 11:47:03.278547 Write leveling (Byte 0): 25 => 25
3424 11:47:03.282216 Write leveling (Byte 1): 27 => 27
3425 11:47:03.285313 DramcWriteLeveling(PI) end<-----
3426 11:47:03.285394
3427 11:47:03.285458 ==
3428 11:47:03.288779 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 11:47:03.291919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 11:47:03.295213 ==
3431 11:47:03.295294 [Gating] SW mode calibration
3432 11:47:03.302302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 11:47:03.308724 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 11:47:03.312151 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 11:47:03.319096 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 11:47:03.322365 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 11:47:03.325543 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 11:47:03.332207 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 11:47:03.335595 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3440 11:47:03.338754 0 15 24 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 0)
3441 11:47:03.345455 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3442 11:47:03.348993 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 11:47:03.352672 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 11:47:03.355965 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 11:47:03.362432 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 11:47:03.365795 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 11:47:03.368937 1 0 20 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3448 11:47:03.375658 1 0 24 | B1->B0 | 4242 2b2b | 0 1 | (0 0) (0 0)
3449 11:47:03.378939 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 11:47:03.382466 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 11:47:03.388852 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 11:47:03.392096 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:47:03.395918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 11:47:03.402434 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:47:03.405605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3456 11:47:03.408648 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3457 11:47:03.415117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 11:47:03.419149 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 11:47:03.421913 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:47:03.429034 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:47:03.432365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:47:03.435494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:47:03.442149 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:47:03.445365 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:47:03.449228 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:47:03.455713 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:47:03.458863 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:47:03.462547 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:47:03.465285 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:47:03.472112 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:47:03.475375 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3472 11:47:03.478643 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3473 11:47:03.481912 Total UI for P1: 0, mck2ui 16
3474 11:47:03.485766 best dqsien dly found for B1: ( 1, 3, 20)
3475 11:47:03.492155 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3476 11:47:03.495408 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:47:03.498588 Total UI for P1: 0, mck2ui 16
3478 11:47:03.501864 best dqsien dly found for B0: ( 1, 3, 26)
3479 11:47:03.505279 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3480 11:47:03.508527 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3481 11:47:03.508608
3482 11:47:03.512362 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3483 11:47:03.515214 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3484 11:47:03.519003 [Gating] SW calibration Done
3485 11:47:03.519085 ==
3486 11:47:03.522369 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:47:03.525501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:47:03.528883 ==
3489 11:47:03.528968 RX Vref Scan: 0
3490 11:47:03.529031
3491 11:47:03.532013 RX Vref 0 -> 0, step: 1
3492 11:47:03.532094
3493 11:47:03.535195 RX Delay -40 -> 252, step: 8
3494 11:47:03.538915 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3495 11:47:03.541967 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3496 11:47:03.545606 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 11:47:03.548476 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3498 11:47:03.555016 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3499 11:47:03.558322 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 11:47:03.562099 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 11:47:03.565241 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 11:47:03.568552 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3503 11:47:03.575230 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 11:47:03.578091 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 11:47:03.581573 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 11:47:03.585464 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 11:47:03.588188 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 11:47:03.595406 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3509 11:47:03.598672 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3510 11:47:03.598770 ==
3511 11:47:03.601764 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 11:47:03.604932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 11:47:03.605030 ==
3514 11:47:03.608195 DQS Delay:
3515 11:47:03.608293 DQS0 = 0, DQS1 = 0
3516 11:47:03.608372 DQM Delay:
3517 11:47:03.611559 DQM0 = 119, DQM1 = 118
3518 11:47:03.611678 DQ Delay:
3519 11:47:03.614856 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3520 11:47:03.618749 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3521 11:47:03.621836 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3522 11:47:03.628589 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3523 11:47:03.628672
3524 11:47:03.628767
3525 11:47:03.628842 ==
3526 11:47:03.631842 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 11:47:03.635453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 11:47:03.635568 ==
3529 11:47:03.635663
3530 11:47:03.635737
3531 11:47:03.638815 TX Vref Scan disable
3532 11:47:03.638913 == TX Byte 0 ==
3533 11:47:03.645288 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3534 11:47:03.648536 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3535 11:47:03.648639 == TX Byte 1 ==
3536 11:47:03.655405 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3537 11:47:03.658727 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3538 11:47:03.658825 ==
3539 11:47:03.661745 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:47:03.664726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:47:03.664822 ==
3542 11:47:03.677838 TX Vref=22, minBit 9, minWin=25, winSum=420
3543 11:47:03.681112 TX Vref=24, minBit 1, minWin=26, winSum=424
3544 11:47:03.684447 TX Vref=26, minBit 2, minWin=26, winSum=431
3545 11:47:03.687534 TX Vref=28, minBit 2, minWin=26, winSum=430
3546 11:47:03.690790 TX Vref=30, minBit 9, minWin=26, winSum=435
3547 11:47:03.697723 TX Vref=32, minBit 13, minWin=26, winSum=432
3548 11:47:03.700900 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3549 11:47:03.701001
3550 11:47:03.704072 Final TX Range 1 Vref 30
3551 11:47:03.704167
3552 11:47:03.704246 ==
3553 11:47:03.707747 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 11:47:03.711180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 11:47:03.711279 ==
3556 11:47:03.714356
3557 11:47:03.714458
3558 11:47:03.714522 TX Vref Scan disable
3559 11:47:03.717693 == TX Byte 0 ==
3560 11:47:03.721068 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 11:47:03.727588 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 11:47:03.727684 == TX Byte 1 ==
3563 11:47:03.730584 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3564 11:47:03.734171 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3565 11:47:03.737804
3566 11:47:03.737885 [DATLAT]
3567 11:47:03.737948 Freq=1200, CH1 RK1
3568 11:47:03.738007
3569 11:47:03.740839 DATLAT Default: 0xd
3570 11:47:03.740920 0, 0xFFFF, sum = 0
3571 11:47:03.744115 1, 0xFFFF, sum = 0
3572 11:47:03.744224 2, 0xFFFF, sum = 0
3573 11:47:03.747320 3, 0xFFFF, sum = 0
3574 11:47:03.750423 4, 0xFFFF, sum = 0
3575 11:47:03.750507 5, 0xFFFF, sum = 0
3576 11:47:03.754563 6, 0xFFFF, sum = 0
3577 11:47:03.754661 7, 0xFFFF, sum = 0
3578 11:47:03.757518 8, 0xFFFF, sum = 0
3579 11:47:03.757656 9, 0xFFFF, sum = 0
3580 11:47:03.760763 10, 0xFFFF, sum = 0
3581 11:47:03.760845 11, 0xFFFF, sum = 0
3582 11:47:03.764038 12, 0x0, sum = 1
3583 11:47:03.764138 13, 0x0, sum = 2
3584 11:47:03.767263 14, 0x0, sum = 3
3585 11:47:03.767408 15, 0x0, sum = 4
3586 11:47:03.767474 best_step = 13
3587 11:47:03.770418
3588 11:47:03.770515 ==
3589 11:47:03.774339 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 11:47:03.777457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 11:47:03.777588 ==
3592 11:47:03.777686 RX Vref Scan: 0
3593 11:47:03.777783
3594 11:47:03.780787 RX Vref 0 -> 0, step: 1
3595 11:47:03.780885
3596 11:47:03.783868 RX Delay -5 -> 252, step: 4
3597 11:47:03.787086 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 11:47:03.793850 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 11:47:03.797192 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 11:47:03.800662 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3601 11:47:03.804305 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 11:47:03.807329 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3603 11:47:03.813730 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 11:47:03.817316 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 11:47:03.820492 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3606 11:47:03.823808 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3607 11:47:03.827123 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3608 11:47:03.833709 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3609 11:47:03.837005 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 11:47:03.840718 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 11:47:03.843585 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3612 11:47:03.846879 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3613 11:47:03.850245 ==
3614 11:47:03.850318 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:47:03.857348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:47:03.857431 ==
3617 11:47:03.857496 DQS Delay:
3618 11:47:03.860462 DQS0 = 0, DQS1 = 0
3619 11:47:03.860552 DQM Delay:
3620 11:47:03.863727 DQM0 = 120, DQM1 = 116
3621 11:47:03.863810 DQ Delay:
3622 11:47:03.867076 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3623 11:47:03.870430 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3624 11:47:03.873514 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3625 11:47:03.876854 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3626 11:47:03.876933
3627 11:47:03.877001
3628 11:47:03.887136 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3629 11:47:03.887215 CH1 RK1: MR19=403, MR18=12EE
3630 11:47:03.893506 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 11:47:03.896963 [RxdqsGatingPostProcess] freq 1200
3632 11:47:03.903970 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 11:47:03.907287 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 11:47:03.910664 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 11:47:03.913498 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 11:47:03.917211 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 11:47:03.920660 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 11:47:03.923519 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 11:47:03.923609 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 11:47:03.927202 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 11:47:03.930190 Pre-setting of DQS Precalculation
3642 11:47:03.937212 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 11:47:03.944012 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 11:47:03.950163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 11:47:03.950244
3646 11:47:03.950306
3647 11:47:03.953727 [Calibration Summary] 2400 Mbps
3648 11:47:03.956949 CH 0, Rank 0
3649 11:47:03.957031 SW Impedance : PASS
3650 11:47:03.960108 DUTY Scan : NO K
3651 11:47:03.963345 ZQ Calibration : PASS
3652 11:47:03.963445 Jitter Meter : NO K
3653 11:47:03.967138 CBT Training : PASS
3654 11:47:03.967237 Write leveling : PASS
3655 11:47:03.970285 RX DQS gating : PASS
3656 11:47:03.973591 RX DQ/DQS(RDDQC) : PASS
3657 11:47:03.973689 TX DQ/DQS : PASS
3658 11:47:03.976630 RX DATLAT : PASS
3659 11:47:03.979881 RX DQ/DQS(Engine): PASS
3660 11:47:03.979981 TX OE : NO K
3661 11:47:03.983664 All Pass.
3662 11:47:03.983745
3663 11:47:03.983826 CH 0, Rank 1
3664 11:47:03.986806 SW Impedance : PASS
3665 11:47:03.986914 DUTY Scan : NO K
3666 11:47:03.990080 ZQ Calibration : PASS
3667 11:47:03.993409 Jitter Meter : NO K
3668 11:47:03.993507 CBT Training : PASS
3669 11:47:03.996613 Write leveling : PASS
3670 11:47:03.999926 RX DQS gating : PASS
3671 11:47:04.000026 RX DQ/DQS(RDDQC) : PASS
3672 11:47:04.003143 TX DQ/DQS : PASS
3673 11:47:04.006442 RX DATLAT : PASS
3674 11:47:04.006532 RX DQ/DQS(Engine): PASS
3675 11:47:04.009762 TX OE : NO K
3676 11:47:04.009890 All Pass.
3677 11:47:04.010019
3678 11:47:04.013761 CH 1, Rank 0
3679 11:47:04.013881 SW Impedance : PASS
3680 11:47:04.016987 DUTY Scan : NO K
3681 11:47:04.017074 ZQ Calibration : PASS
3682 11:47:04.020527 Jitter Meter : NO K
3683 11:47:04.023461 CBT Training : PASS
3684 11:47:04.023559 Write leveling : PASS
3685 11:47:04.026621 RX DQS gating : PASS
3686 11:47:04.030172 RX DQ/DQS(RDDQC) : PASS
3687 11:47:04.030271 TX DQ/DQS : PASS
3688 11:47:04.033675 RX DATLAT : PASS
3689 11:47:04.036665 RX DQ/DQS(Engine): PASS
3690 11:47:04.036778 TX OE : NO K
3691 11:47:04.040234 All Pass.
3692 11:47:04.040320
3693 11:47:04.040418 CH 1, Rank 1
3694 11:47:04.043195 SW Impedance : PASS
3695 11:47:04.043293 DUTY Scan : NO K
3696 11:47:04.046876 ZQ Calibration : PASS
3697 11:47:04.049914 Jitter Meter : NO K
3698 11:47:04.050013 CBT Training : PASS
3699 11:47:04.053483 Write leveling : PASS
3700 11:47:04.056793 RX DQS gating : PASS
3701 11:47:04.056891 RX DQ/DQS(RDDQC) : PASS
3702 11:47:04.060040 TX DQ/DQS : PASS
3703 11:47:04.060139 RX DATLAT : PASS
3704 11:47:04.063520 RX DQ/DQS(Engine): PASS
3705 11:47:04.066540 TX OE : NO K
3706 11:47:04.066639 All Pass.
3707 11:47:04.066737
3708 11:47:04.070014 DramC Write-DBI off
3709 11:47:04.070115 PER_BANK_REFRESH: Hybrid Mode
3710 11:47:04.073636 TX_TRACKING: ON
3711 11:47:04.080610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 11:47:04.087144 [FAST_K] Save calibration result to emmc
3713 11:47:04.090392 dramc_set_vcore_voltage set vcore to 650000
3714 11:47:04.090490 Read voltage for 600, 5
3715 11:47:04.093582 Vio18 = 0
3716 11:47:04.093713 Vcore = 650000
3717 11:47:04.093810 Vdram = 0
3718 11:47:04.096839 Vddq = 0
3719 11:47:04.096941 Vmddr = 0
3720 11:47:04.100061 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 11:47:04.107233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 11:47:04.110564 MEM_TYPE=3, freq_sel=19
3723 11:47:04.113829 sv_algorithm_assistance_LP4_1600
3724 11:47:04.117122 ============ PULL DRAM RESETB DOWN ============
3725 11:47:04.120486 ========== PULL DRAM RESETB DOWN end =========
3726 11:47:04.123722 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 11:47:04.126843 ===================================
3728 11:47:04.130665 LPDDR4 DRAM CONFIGURATION
3729 11:47:04.133965 ===================================
3730 11:47:04.137075 EX_ROW_EN[0] = 0x0
3731 11:47:04.137174 EX_ROW_EN[1] = 0x0
3732 11:47:04.140139 LP4Y_EN = 0x0
3733 11:47:04.140238 WORK_FSP = 0x0
3734 11:47:04.143306 WL = 0x2
3735 11:47:04.143405 RL = 0x2
3736 11:47:04.147037 BL = 0x2
3737 11:47:04.147135 RPST = 0x0
3738 11:47:04.149945 RD_PRE = 0x0
3739 11:47:04.150044 WR_PRE = 0x1
3740 11:47:04.153279 WR_PST = 0x0
3741 11:47:04.153361 DBI_WR = 0x0
3742 11:47:04.156595 DBI_RD = 0x0
3743 11:47:04.160275 OTF = 0x1
3744 11:47:04.163383 ===================================
3745 11:47:04.163484 ===================================
3746 11:47:04.166928 ANA top config
3747 11:47:04.170001 ===================================
3748 11:47:04.173554 DLL_ASYNC_EN = 0
3749 11:47:04.173695 ALL_SLAVE_EN = 1
3750 11:47:04.176768 NEW_RANK_MODE = 1
3751 11:47:04.180230 DLL_IDLE_MODE = 1
3752 11:47:04.183458 LP45_APHY_COMB_EN = 1
3753 11:47:04.186686 TX_ODT_DIS = 1
3754 11:47:04.186786 NEW_8X_MODE = 1
3755 11:47:04.190269 ===================================
3756 11:47:04.193440 ===================================
3757 11:47:04.196831 data_rate = 1200
3758 11:47:04.200134 CKR = 1
3759 11:47:04.203367 DQ_P2S_RATIO = 8
3760 11:47:04.207249 ===================================
3761 11:47:04.209868 CA_P2S_RATIO = 8
3762 11:47:04.213218 DQ_CA_OPEN = 0
3763 11:47:04.213343 DQ_SEMI_OPEN = 0
3764 11:47:04.216710 CA_SEMI_OPEN = 0
3765 11:47:04.220043 CA_FULL_RATE = 0
3766 11:47:04.223252 DQ_CKDIV4_EN = 1
3767 11:47:04.226440 CA_CKDIV4_EN = 1
3768 11:47:04.230035 CA_PREDIV_EN = 0
3769 11:47:04.230118 PH8_DLY = 0
3770 11:47:04.233210 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 11:47:04.236526 DQ_AAMCK_DIV = 4
3772 11:47:04.239893 CA_AAMCK_DIV = 4
3773 11:47:04.242958 CA_ADMCK_DIV = 4
3774 11:47:04.246696 DQ_TRACK_CA_EN = 0
3775 11:47:04.246780 CA_PICK = 600
3776 11:47:04.249910 CA_MCKIO = 600
3777 11:47:04.253242 MCKIO_SEMI = 0
3778 11:47:04.256275 PLL_FREQ = 2288
3779 11:47:04.260038 DQ_UI_PI_RATIO = 32
3780 11:47:04.263490 CA_UI_PI_RATIO = 0
3781 11:47:04.266770 ===================================
3782 11:47:04.269911 ===================================
3783 11:47:04.269995 memory_type:LPDDR4
3784 11:47:04.272943 GP_NUM : 10
3785 11:47:04.276673 SRAM_EN : 1
3786 11:47:04.276756 MD32_EN : 0
3787 11:47:04.279723 ===================================
3788 11:47:04.282910 [ANA_INIT] >>>>>>>>>>>>>>
3789 11:47:04.286203 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 11:47:04.289935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 11:47:04.293060 ===================================
3792 11:47:04.296774 data_rate = 1200,PCW = 0X5800
3793 11:47:04.299563 ===================================
3794 11:47:04.302943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 11:47:04.306089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 11:47:04.313139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 11:47:04.316275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 11:47:04.319639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 11:47:04.322854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 11:47:04.326212 [ANA_INIT] flow start
3801 11:47:04.329468 [ANA_INIT] PLL >>>>>>>>
3802 11:47:04.329608 [ANA_INIT] PLL <<<<<<<<
3803 11:47:04.332717 [ANA_INIT] MIDPI >>>>>>>>
3804 11:47:04.336477 [ANA_INIT] MIDPI <<<<<<<<
3805 11:47:04.339646 [ANA_INIT] DLL >>>>>>>>
3806 11:47:04.339729 [ANA_INIT] flow end
3807 11:47:04.343186 ============ LP4 DIFF to SE enter ============
3808 11:47:04.349705 ============ LP4 DIFF to SE exit ============
3809 11:47:04.349788 [ANA_INIT] <<<<<<<<<<<<<
3810 11:47:04.352719 [Flow] Enable top DCM control >>>>>
3811 11:47:04.355967 [Flow] Enable top DCM control <<<<<
3812 11:47:04.359254 Enable DLL master slave shuffle
3813 11:47:04.365699 ==============================================================
3814 11:47:04.365799 Gating Mode config
3815 11:47:04.372539 ==============================================================
3816 11:47:04.375650 Config description:
3817 11:47:04.385993 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 11:47:04.392504 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 11:47:04.396271 SELPH_MODE 0: By rank 1: By Phase
3820 11:47:04.402815 ==============================================================
3821 11:47:04.406136 GAT_TRACK_EN = 1
3822 11:47:04.406246 RX_GATING_MODE = 2
3823 11:47:04.409286 RX_GATING_TRACK_MODE = 2
3824 11:47:04.412589 SELPH_MODE = 1
3825 11:47:04.415618 PICG_EARLY_EN = 1
3826 11:47:04.419177 VALID_LAT_VALUE = 1
3827 11:47:04.426013 ==============================================================
3828 11:47:04.429043 Enter into Gating configuration >>>>
3829 11:47:04.432735 Exit from Gating configuration <<<<
3830 11:47:04.435692 Enter into DVFS_PRE_config >>>>>
3831 11:47:04.445920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 11:47:04.449144 Exit from DVFS_PRE_config <<<<<
3833 11:47:04.452419 Enter into PICG configuration >>>>
3834 11:47:04.455758 Exit from PICG configuration <<<<
3835 11:47:04.458772 [RX_INPUT] configuration >>>>>
3836 11:47:04.462328 [RX_INPUT] configuration <<<<<
3837 11:47:04.465495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 11:47:04.472125 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 11:47:04.478779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 11:47:04.482007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 11:47:04.488765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 11:47:04.495655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 11:47:04.498743 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 11:47:04.505162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 11:47:04.508543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 11:47:04.511850 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 11:47:04.515741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 11:47:04.522320 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 11:47:04.524986 ===================================
3850 11:47:04.525069 LPDDR4 DRAM CONFIGURATION
3851 11:47:04.528281 ===================================
3852 11:47:04.531983 EX_ROW_EN[0] = 0x0
3853 11:47:04.535194 EX_ROW_EN[1] = 0x0
3854 11:47:04.535304 LP4Y_EN = 0x0
3855 11:47:04.538824 WORK_FSP = 0x0
3856 11:47:04.538906 WL = 0x2
3857 11:47:04.542269 RL = 0x2
3858 11:47:04.542365 BL = 0x2
3859 11:47:04.545301 RPST = 0x0
3860 11:47:04.545407 RD_PRE = 0x0
3861 11:47:04.548741 WR_PRE = 0x1
3862 11:47:04.548822 WR_PST = 0x0
3863 11:47:04.552080 DBI_WR = 0x0
3864 11:47:04.552161 DBI_RD = 0x0
3865 11:47:04.555072 OTF = 0x1
3866 11:47:04.558783 ===================================
3867 11:47:04.561982 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 11:47:04.565059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 11:47:04.572139 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 11:47:04.575390 ===================================
3871 11:47:04.575472 LPDDR4 DRAM CONFIGURATION
3872 11:47:04.578714 ===================================
3873 11:47:04.581957 EX_ROW_EN[0] = 0x10
3874 11:47:04.582038 EX_ROW_EN[1] = 0x0
3875 11:47:04.585104 LP4Y_EN = 0x0
3876 11:47:04.585185 WORK_FSP = 0x0
3877 11:47:04.588834 WL = 0x2
3878 11:47:04.592015 RL = 0x2
3879 11:47:04.592098 BL = 0x2
3880 11:47:04.595362 RPST = 0x0
3881 11:47:04.595443 RD_PRE = 0x0
3882 11:47:04.598452 WR_PRE = 0x1
3883 11:47:04.598534 WR_PST = 0x0
3884 11:47:04.601741 DBI_WR = 0x0
3885 11:47:04.601822 DBI_RD = 0x0
3886 11:47:04.605110 OTF = 0x1
3887 11:47:04.608195 ===================================
3888 11:47:04.615303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 11:47:04.618596 nWR fixed to 30
3890 11:47:04.618682 [ModeRegInit_LP4] CH0 RK0
3891 11:47:04.621903 [ModeRegInit_LP4] CH0 RK1
3892 11:47:04.625259 [ModeRegInit_LP4] CH1 RK0
3893 11:47:04.625366 [ModeRegInit_LP4] CH1 RK1
3894 11:47:04.628517 match AC timing 17
3895 11:47:04.631792 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 11:47:04.634789 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 11:47:04.641432 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 11:47:04.644859 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 11:47:04.652047 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 11:47:04.652131 ==
3901 11:47:04.654942 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 11:47:04.658089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 11:47:04.658172 ==
3904 11:47:04.664940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 11:47:04.668360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3906 11:47:04.672983 [CA 0] Center 36 (5~67) winsize 63
3907 11:47:04.675776 [CA 1] Center 36 (5~67) winsize 63
3908 11:47:04.679012 [CA 2] Center 34 (3~65) winsize 63
3909 11:47:04.682816 [CA 3] Center 34 (3~65) winsize 63
3910 11:47:04.685841 [CA 4] Center 33 (2~64) winsize 63
3911 11:47:04.689329 [CA 5] Center 32 (2~63) winsize 62
3912 11:47:04.689410
3913 11:47:04.692490 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3914 11:47:04.692571
3915 11:47:04.695542 [CATrainingPosCal] consider 1 rank data
3916 11:47:04.699372 u2DelayCellTimex100 = 270/100 ps
3917 11:47:04.702662 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3918 11:47:04.705787 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3919 11:47:04.712633 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3920 11:47:04.715664 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
3921 11:47:04.719284 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 11:47:04.722616 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 11:47:04.722699
3924 11:47:04.725898 CA PerBit enable=1, Macro0, CA PI delay=32
3925 11:47:04.725982
3926 11:47:04.729445 [CBTSetCACLKResult] CA Dly = 32
3927 11:47:04.729552 CS Dly: 4 (0~35)
3928 11:47:04.732538 ==
3929 11:47:04.732646 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 11:47:04.739067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 11:47:04.739155 ==
3932 11:47:04.742432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 11:47:04.749213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 11:47:04.753173 [CA 0] Center 35 (5~66) winsize 62
3935 11:47:04.756444 [CA 1] Center 35 (5~66) winsize 62
3936 11:47:04.759640 [CA 2] Center 34 (3~65) winsize 63
3937 11:47:04.762780 [CA 3] Center 34 (3~65) winsize 63
3938 11:47:04.765964 [CA 4] Center 33 (2~64) winsize 63
3939 11:47:04.769310 [CA 5] Center 32 (2~63) winsize 62
3940 11:47:04.769391
3941 11:47:04.773148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 11:47:04.773230
3943 11:47:04.776331 [CATrainingPosCal] consider 2 rank data
3944 11:47:04.779605 u2DelayCellTimex100 = 270/100 ps
3945 11:47:04.782703 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 11:47:04.786288 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 11:47:04.792744 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3948 11:47:04.795918 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
3949 11:47:04.799291 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 11:47:04.803048 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 11:47:04.803129
3952 11:47:04.805853 CA PerBit enable=1, Macro0, CA PI delay=32
3953 11:47:04.805934
3954 11:47:04.809426 [CBTSetCACLKResult] CA Dly = 32
3955 11:47:04.809535 CS Dly: 4 (0~36)
3956 11:47:04.812600
3957 11:47:04.816054 ----->DramcWriteLeveling(PI) begin...
3958 11:47:04.816139 ==
3959 11:47:04.819287 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:47:04.822701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:47:04.822783 ==
3962 11:47:04.826048 Write leveling (Byte 0): 32 => 32
3963 11:47:04.828912 Write leveling (Byte 1): 31 => 31
3964 11:47:04.832376 DramcWriteLeveling(PI) end<-----
3965 11:47:04.832494
3966 11:47:04.832559 ==
3967 11:47:04.836205 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 11:47:04.839012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 11:47:04.839094 ==
3970 11:47:04.842615 [Gating] SW mode calibration
3971 11:47:04.849105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 11:47:04.855732 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 11:47:04.858990 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 11:47:04.862363 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 11:47:04.869086 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 11:47:04.872122 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
3977 11:47:04.875468 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3978 11:47:04.882400 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:47:04.885673 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:47:04.889077 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:47:04.895520 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:47:04.898791 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 11:47:04.901898 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:47:04.908624 0 10 12 | B1->B0 | 2424 3232 | 1 0 | (0 0) (1 1)
3985 11:47:04.912401 0 10 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3986 11:47:04.915294 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:47:04.918782 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:47:04.925459 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:47:04.928529 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:47:04.932192 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:47:04.938504 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:47:04.941908 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3993 11:47:04.945356 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 11:47:04.951836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:47:04.955262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:47:04.958577 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:47:04.965131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:47:04.968969 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:47:04.971617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:47:04.978511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:47:04.981833 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:47:04.985386 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:47:04.991969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:47:04.995092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:47:04.998368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:47:05.005453 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:47:05.008617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:47:05.011828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:47:05.015819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 11:47:05.018970 Total UI for P1: 0, mck2ui 16
4011 11:47:05.022164 best dqsien dly found for B0: ( 0, 13, 14)
4012 11:47:05.025200 Total UI for P1: 0, mck2ui 16
4013 11:47:05.029076 best dqsien dly found for B1: ( 0, 13, 14)
4014 11:47:05.031945 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4015 11:47:05.038620 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4016 11:47:05.038705
4017 11:47:05.041898 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 11:47:05.045465 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4019 11:47:05.049162 [Gating] SW calibration Done
4020 11:47:05.049256 ==
4021 11:47:05.052270 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 11:47:05.055777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 11:47:05.055859 ==
4024 11:47:05.055924 RX Vref Scan: 0
4025 11:47:05.058479
4026 11:47:05.058576 RX Vref 0 -> 0, step: 1
4027 11:47:05.058660
4028 11:47:05.061986 RX Delay -230 -> 252, step: 16
4029 11:47:05.065497 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4030 11:47:05.072287 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4031 11:47:05.075534 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4032 11:47:05.078818 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4033 11:47:05.082132 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4034 11:47:05.085411 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4035 11:47:05.092365 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4036 11:47:05.095790 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4037 11:47:05.098957 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4038 11:47:05.102278 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4039 11:47:05.105679 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4040 11:47:05.112156 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4041 11:47:05.115445 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4042 11:47:05.118569 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4043 11:47:05.122311 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4044 11:47:05.128715 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4045 11:47:05.128797 ==
4046 11:47:05.131809 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 11:47:05.135535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 11:47:05.135617 ==
4049 11:47:05.135681 DQS Delay:
4050 11:47:05.138642 DQS0 = 0, DQS1 = 0
4051 11:47:05.138723 DQM Delay:
4052 11:47:05.142326 DQM0 = 52, DQM1 = 47
4053 11:47:05.142408 DQ Delay:
4054 11:47:05.145140 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4055 11:47:05.148799 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4056 11:47:05.151870 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4057 11:47:05.155183 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4058 11:47:05.155264
4059 11:47:05.155328
4060 11:47:05.155387 ==
4061 11:47:05.158593 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 11:47:05.161689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 11:47:05.161771 ==
4064 11:47:05.164997
4065 11:47:05.165102
4066 11:47:05.165193 TX Vref Scan disable
4067 11:47:05.168774 == TX Byte 0 ==
4068 11:47:05.171768 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4069 11:47:05.174881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4070 11:47:05.178461 == TX Byte 1 ==
4071 11:47:05.181528 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4072 11:47:05.185001 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4073 11:47:05.185085 ==
4074 11:47:05.188816 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 11:47:05.195120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 11:47:05.195202 ==
4077 11:47:05.195266
4078 11:47:05.195325
4079 11:47:05.198475 TX Vref Scan disable
4080 11:47:05.198556 == TX Byte 0 ==
4081 11:47:05.204893 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4082 11:47:05.208271 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4083 11:47:05.208353 == TX Byte 1 ==
4084 11:47:05.215269 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4085 11:47:05.218315 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4086 11:47:05.218397
4087 11:47:05.218460 [DATLAT]
4088 11:47:05.221537 Freq=600, CH0 RK0
4089 11:47:05.221667
4090 11:47:05.221732 DATLAT Default: 0x9
4091 11:47:05.224849 0, 0xFFFF, sum = 0
4092 11:47:05.224931 1, 0xFFFF, sum = 0
4093 11:47:05.227964 2, 0xFFFF, sum = 0
4094 11:47:05.228046 3, 0xFFFF, sum = 0
4095 11:47:05.231824 4, 0xFFFF, sum = 0
4096 11:47:05.231906 5, 0xFFFF, sum = 0
4097 11:47:05.235165 6, 0xFFFF, sum = 0
4098 11:47:05.235248 7, 0xFFFF, sum = 0
4099 11:47:05.238491 8, 0x0, sum = 1
4100 11:47:05.238574 9, 0x0, sum = 2
4101 11:47:05.241806 10, 0x0, sum = 3
4102 11:47:05.241888 11, 0x0, sum = 4
4103 11:47:05.244994 best_step = 9
4104 11:47:05.245075
4105 11:47:05.245138 ==
4106 11:47:05.247914 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 11:47:05.251441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 11:47:05.251567 ==
4109 11:47:05.254539 RX Vref Scan: 1
4110 11:47:05.254621
4111 11:47:05.254701 RX Vref 0 -> 0, step: 1
4112 11:47:05.254775
4113 11:47:05.258062 RX Delay -163 -> 252, step: 8
4114 11:47:05.258158
4115 11:47:05.261938 Set Vref, RX VrefLevel [Byte0]: 54
4116 11:47:05.264944 [Byte1]: 58
4117 11:47:05.268490
4118 11:47:05.268571 Final RX Vref Byte 0 = 54 to rank0
4119 11:47:05.271795 Final RX Vref Byte 1 = 58 to rank0
4120 11:47:05.274957 Final RX Vref Byte 0 = 54 to rank1
4121 11:47:05.278622 Final RX Vref Byte 1 = 58 to rank1==
4122 11:47:05.281524 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:47:05.288621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:47:05.288731 ==
4125 11:47:05.288795 DQS Delay:
4126 11:47:05.288855 DQS0 = 0, DQS1 = 0
4127 11:47:05.291681 DQM Delay:
4128 11:47:05.291788 DQM0 = 53, DQM1 = 49
4129 11:47:05.294676 DQ Delay:
4130 11:47:05.298443 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4131 11:47:05.298525 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4132 11:47:05.301606 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =44
4133 11:47:05.308178 DQ12 =56, DQ13 =56, DQ14 =60, DQ15 =56
4134 11:47:05.308260
4135 11:47:05.308324
4136 11:47:05.314996 [DQSOSCAuto] RK0, (LSB)MR18= 0x7264, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4137 11:47:05.318372 CH0 RK0: MR19=808, MR18=7264
4138 11:47:05.324637 CH0_RK0: MR19=0x808, MR18=0x7264, DQSOSC=388, MR23=63, INC=174, DEC=116
4139 11:47:05.324720
4140 11:47:05.328040 ----->DramcWriteLeveling(PI) begin...
4141 11:47:05.328153 ==
4142 11:47:05.331216 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 11:47:05.335136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 11:47:05.335219 ==
4145 11:47:05.337924 Write leveling (Byte 0): 35 => 35
4146 11:47:05.341144 Write leveling (Byte 1): 33 => 33
4147 11:47:05.344490 DramcWriteLeveling(PI) end<-----
4148 11:47:05.344602
4149 11:47:05.344668 ==
4150 11:47:05.347748 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 11:47:05.351264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:47:05.351346 ==
4153 11:47:05.354545 [Gating] SW mode calibration
4154 11:47:05.361503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4155 11:47:05.368093 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4156 11:47:05.371349 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 11:47:05.375022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 11:47:05.381434 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 11:47:05.384687 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
4160 11:47:05.388244 0 9 16 | B1->B0 | 2a2a 2c2c | 1 0 | (1 0) (0 0)
4161 11:47:05.394623 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 11:47:05.397887 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 11:47:05.401769 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 11:47:05.407901 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:47:05.411361 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 11:47:05.415032 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:47:05.421462 0 10 12 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
4168 11:47:05.424873 0 10 16 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (1 1)
4169 11:47:05.427904 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 11:47:05.435167 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 11:47:05.438161 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 11:47:05.441809 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:47:05.448438 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 11:47:05.451554 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:47:05.454851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4176 11:47:05.461303 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 11:47:05.464532 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 11:47:05.467769 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:47:05.471044 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:47:05.478280 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:47:05.481288 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:47:05.484933 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:47:05.491151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:47:05.494367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:47:05.497952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:47:05.504440 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:47:05.507602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:47:05.511024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:47:05.517901 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:47:05.521095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:47:05.524238 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4192 11:47:05.531617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4193 11:47:05.531716 Total UI for P1: 0, mck2ui 16
4194 11:47:05.538193 best dqsien dly found for B0: ( 0, 13, 12)
4195 11:47:05.541360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 11:47:05.544369 Total UI for P1: 0, mck2ui 16
4197 11:47:05.547731 best dqsien dly found for B1: ( 0, 13, 16)
4198 11:47:05.551083 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4199 11:47:05.554338 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4200 11:47:05.554420
4201 11:47:05.558158 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4202 11:47:05.561674 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4203 11:47:05.564494 [Gating] SW calibration Done
4204 11:47:05.564608 ==
4205 11:47:05.568030 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 11:47:05.570911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 11:47:05.574692 ==
4208 11:47:05.574774 RX Vref Scan: 0
4209 11:47:05.574837
4210 11:47:05.577963 RX Vref 0 -> 0, step: 1
4211 11:47:05.578044
4212 11:47:05.581030 RX Delay -230 -> 252, step: 16
4213 11:47:05.584109 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 11:47:05.587390 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 11:47:05.591095 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 11:47:05.597718 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 11:47:05.601020 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4218 11:47:05.604027 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4219 11:47:05.607890 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4220 11:47:05.611048 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4221 11:47:05.617557 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4222 11:47:05.621216 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 11:47:05.624456 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 11:47:05.627823 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 11:47:05.631014 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 11:47:05.638031 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 11:47:05.641353 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4228 11:47:05.644384 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 11:47:05.644491 ==
4230 11:47:05.647319 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 11:47:05.653962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 11:47:05.654049 ==
4233 11:47:05.654115 DQS Delay:
4234 11:47:05.654175 DQS0 = 0, DQS1 = 0
4235 11:47:05.657416 DQM Delay:
4236 11:47:05.657522 DQM0 = 54, DQM1 = 43
4237 11:47:05.661154 DQ Delay:
4238 11:47:05.664370 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 11:47:05.664451 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4240 11:47:05.667650 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4241 11:47:05.674184 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4242 11:47:05.674265
4243 11:47:05.674329
4244 11:47:05.674389 ==
4245 11:47:05.677370 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 11:47:05.681094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 11:47:05.681178 ==
4248 11:47:05.681242
4249 11:47:05.681301
4250 11:47:05.684357 TX Vref Scan disable
4251 11:47:05.684438 == TX Byte 0 ==
4252 11:47:05.690653 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4253 11:47:05.694465 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4254 11:47:05.694547 == TX Byte 1 ==
4255 11:47:05.700654 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4256 11:47:05.704212 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4257 11:47:05.704294 ==
4258 11:47:05.707762 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:47:05.710738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:47:05.710820 ==
4261 11:47:05.710884
4262 11:47:05.710943
4263 11:47:05.714249 TX Vref Scan disable
4264 11:47:05.717272 == TX Byte 0 ==
4265 11:47:05.721082 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 11:47:05.724359 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 11:47:05.727583 == TX Byte 1 ==
4268 11:47:05.730754 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4269 11:47:05.734109 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4270 11:47:05.734233
4271 11:47:05.737352 [DATLAT]
4272 11:47:05.737458 Freq=600, CH0 RK1
4273 11:47:05.737551
4274 11:47:05.740846 DATLAT Default: 0x9
4275 11:47:05.740927 0, 0xFFFF, sum = 0
4276 11:47:05.744191 1, 0xFFFF, sum = 0
4277 11:47:05.744273 2, 0xFFFF, sum = 0
4278 11:47:05.747448 3, 0xFFFF, sum = 0
4279 11:47:05.747530 4, 0xFFFF, sum = 0
4280 11:47:05.750581 5, 0xFFFF, sum = 0
4281 11:47:05.750664 6, 0xFFFF, sum = 0
4282 11:47:05.753846 7, 0xFFFF, sum = 0
4283 11:47:05.753930 8, 0x0, sum = 1
4284 11:47:05.757059 9, 0x0, sum = 2
4285 11:47:05.757141 10, 0x0, sum = 3
4286 11:47:05.760850 11, 0x0, sum = 4
4287 11:47:05.760933 best_step = 9
4288 11:47:05.760997
4289 11:47:05.761056 ==
4290 11:47:05.763971 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 11:47:05.770765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 11:47:05.770847 ==
4293 11:47:05.770911 RX Vref Scan: 0
4294 11:47:05.770970
4295 11:47:05.774058 RX Vref 0 -> 0, step: 1
4296 11:47:05.774139
4297 11:47:05.777282 RX Delay -163 -> 252, step: 8
4298 11:47:05.780353 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 11:47:05.784190 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4300 11:47:05.790832 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 11:47:05.793940 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 11:47:05.797140 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4303 11:47:05.800350 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 11:47:05.803707 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4305 11:47:05.810510 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4306 11:47:05.813614 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4307 11:47:05.817430 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4308 11:47:05.820523 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 11:47:05.827037 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 11:47:05.830231 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4311 11:47:05.833878 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4312 11:47:05.837093 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4313 11:47:05.840275 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4314 11:47:05.840356 ==
4315 11:47:05.843679 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:47:05.850712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:47:05.850794 ==
4318 11:47:05.850858 DQS Delay:
4319 11:47:05.853910 DQS0 = 0, DQS1 = 0
4320 11:47:05.853991 DQM Delay:
4321 11:47:05.854084 DQM0 = 53, DQM1 = 46
4322 11:47:05.857596 DQ Delay:
4323 11:47:05.860653 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4324 11:47:05.863983 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4325 11:47:05.867274 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4326 11:47:05.870520 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4327 11:47:05.870595
4328 11:47:05.870656
4329 11:47:05.876899 [DQSOSCAuto] RK1, (LSB)MR18= 0x6727, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4330 11:47:05.880099 CH0 RK1: MR19=808, MR18=6727
4331 11:47:05.887076 CH0_RK1: MR19=0x808, MR18=0x6727, DQSOSC=390, MR23=63, INC=172, DEC=114
4332 11:47:05.890353 [RxdqsGatingPostProcess] freq 600
4333 11:47:05.893497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 11:47:05.897094 Pre-setting of DQS Precalculation
4335 11:47:05.903671 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 11:47:05.903756 ==
4337 11:47:05.906835 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 11:47:05.910062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:47:05.910149 ==
4340 11:47:05.917161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 11:47:05.923527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4342 11:47:05.927239 [CA 0] Center 36 (5~67) winsize 63
4343 11:47:05.930262 [CA 1] Center 36 (6~67) winsize 62
4344 11:47:05.933410 [CA 2] Center 35 (4~66) winsize 63
4345 11:47:05.937086 [CA 3] Center 34 (4~65) winsize 62
4346 11:47:05.940009 [CA 4] Center 34 (4~65) winsize 62
4347 11:47:05.940091 [CA 5] Center 34 (3~65) winsize 63
4348 11:47:05.943473
4349 11:47:05.946600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4350 11:47:05.946681
4351 11:47:05.949855 [CATrainingPosCal] consider 1 rank data
4352 11:47:05.953730 u2DelayCellTimex100 = 270/100 ps
4353 11:47:05.956973 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4354 11:47:05.960241 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4355 11:47:05.963372 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4356 11:47:05.966578 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 11:47:05.970284 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 11:47:05.973651 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4359 11:47:05.973733
4360 11:47:05.976876 CA PerBit enable=1, Macro0, CA PI delay=34
4361 11:47:05.980024
4362 11:47:05.980105 [CBTSetCACLKResult] CA Dly = 34
4363 11:47:05.983343 CS Dly: 6 (0~37)
4364 11:47:05.983424 ==
4365 11:47:05.986904 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 11:47:05.990011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 11:47:05.990119 ==
4368 11:47:05.996641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 11:47:06.003547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 11:47:06.006573 [CA 0] Center 36 (6~67) winsize 62
4371 11:47:06.009708 [CA 1] Center 36 (6~67) winsize 62
4372 11:47:06.013414 [CA 2] Center 35 (4~66) winsize 63
4373 11:47:06.016748 [CA 3] Center 35 (4~66) winsize 63
4374 11:47:06.019824 [CA 4] Center 35 (4~66) winsize 63
4375 11:47:06.023641 [CA 5] Center 34 (4~65) winsize 62
4376 11:47:06.023769
4377 11:47:06.026747 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 11:47:06.026829
4379 11:47:06.029808 [CATrainingPosCal] consider 2 rank data
4380 11:47:06.033024 u2DelayCellTimex100 = 270/100 ps
4381 11:47:06.036886 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4382 11:47:06.039609 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4383 11:47:06.042809 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4384 11:47:06.046753 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 11:47:06.049860 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 11:47:06.052810 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4387 11:47:06.052892
4388 11:47:06.059411 CA PerBit enable=1, Macro0, CA PI delay=34
4389 11:47:06.059493
4390 11:47:06.063369 [CBTSetCACLKResult] CA Dly = 34
4391 11:47:06.063451 CS Dly: 6 (0~38)
4392 11:47:06.063516
4393 11:47:06.066323 ----->DramcWriteLeveling(PI) begin...
4394 11:47:06.066406 ==
4395 11:47:06.069550 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:47:06.073160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:47:06.073242 ==
4398 11:47:06.076206 Write leveling (Byte 0): 27 => 27
4399 11:47:06.079568 Write leveling (Byte 1): 30 => 30
4400 11:47:06.083286 DramcWriteLeveling(PI) end<-----
4401 11:47:06.083367
4402 11:47:06.083431 ==
4403 11:47:06.086514 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 11:47:06.089797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:47:06.092910 ==
4406 11:47:06.092991 [Gating] SW mode calibration
4407 11:47:06.103488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 11:47:06.106637 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 11:47:06.109988 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 11:47:06.116819 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 11:47:06.119802 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 11:47:06.122945 0 9 12 | B1->B0 | 2f2f 2b2b | 0 1 | (0 1) (1 0)
4413 11:47:06.129973 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4414 11:47:06.133094 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:47:06.136346 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:47:06.143277 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:47:06.146552 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:47:06.149826 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:47:06.153199 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4420 11:47:06.159762 0 10 12 | B1->B0 | 3232 4343 | 1 0 | (0 0) (1 1)
4421 11:47:06.162957 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:47:06.166764 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:47:06.172879 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:47:06.176118 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:47:06.179384 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:47:06.186233 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:47:06.189667 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4428 11:47:06.192775 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:47:06.199917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:47:06.203059 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:47:06.206349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:47:06.212631 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:47:06.216123 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:47:06.219347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:47:06.226233 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:47:06.229554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:47:06.232790 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:47:06.239294 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:47:06.242995 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:47:06.246116 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:47:06.252565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:47:06.256456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:47:06.259699 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:47:06.266357 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4445 11:47:06.269760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 11:47:06.273100 Total UI for P1: 0, mck2ui 16
4447 11:47:06.276334 best dqsien dly found for B0: ( 0, 13, 12)
4448 11:47:06.279571 Total UI for P1: 0, mck2ui 16
4449 11:47:06.282724 best dqsien dly found for B1: ( 0, 13, 12)
4450 11:47:06.285815 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4451 11:47:06.289636 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4452 11:47:06.289744
4453 11:47:06.292523 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 11:47:06.295785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 11:47:06.299251 [Gating] SW calibration Done
4456 11:47:06.299353 ==
4457 11:47:06.302933 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 11:47:06.306247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 11:47:06.306345 ==
4460 11:47:06.309612 RX Vref Scan: 0
4461 11:47:06.309693
4462 11:47:06.312663 RX Vref 0 -> 0, step: 1
4463 11:47:06.312740
4464 11:47:06.312804 RX Delay -230 -> 252, step: 16
4465 11:47:06.319254 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4466 11:47:06.323047 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4467 11:47:06.326250 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4468 11:47:06.329249 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 11:47:06.336044 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 11:47:06.339448 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4471 11:47:06.342972 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4472 11:47:06.345755 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4473 11:47:06.349697 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4474 11:47:06.356245 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4475 11:47:06.359671 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4476 11:47:06.362982 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4477 11:47:06.366150 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4478 11:47:06.372868 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4479 11:47:06.376249 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4480 11:47:06.379548 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4481 11:47:06.379629 ==
4482 11:47:06.382758 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 11:47:06.386197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:47:06.389438 ==
4485 11:47:06.389521 DQS Delay:
4486 11:47:06.389596 DQS0 = 0, DQS1 = 0
4487 11:47:06.392649 DQM Delay:
4488 11:47:06.392730 DQM0 = 47, DQM1 = 46
4489 11:47:06.395807 DQ Delay:
4490 11:47:06.399070 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4491 11:47:06.399191 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4492 11:47:06.402266 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4493 11:47:06.405612 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4494 11:47:06.408931
4495 11:47:06.409012
4496 11:47:06.409075 ==
4497 11:47:06.412578 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 11:47:06.415431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 11:47:06.415513 ==
4500 11:47:06.415592
4501 11:47:06.415666
4502 11:47:06.418818 TX Vref Scan disable
4503 11:47:06.418914 == TX Byte 0 ==
4504 11:47:06.425404 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4505 11:47:06.429114 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4506 11:47:06.429220 == TX Byte 1 ==
4507 11:47:06.435614 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 11:47:06.439368 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 11:47:06.439445 ==
4510 11:47:06.442327 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 11:47:06.445959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 11:47:06.446068 ==
4513 11:47:06.446135
4514 11:47:06.446196
4515 11:47:06.449116 TX Vref Scan disable
4516 11:47:06.452012 == TX Byte 0 ==
4517 11:47:06.455638 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4518 11:47:06.458858 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4519 11:47:06.462165 == TX Byte 1 ==
4520 11:47:06.465730 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 11:47:06.469082 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 11:47:06.469185
4523 11:47:06.472508 [DATLAT]
4524 11:47:06.472609 Freq=600, CH1 RK0
4525 11:47:06.472699
4526 11:47:06.475811 DATLAT Default: 0x9
4527 11:47:06.475906 0, 0xFFFF, sum = 0
4528 11:47:06.478990 1, 0xFFFF, sum = 0
4529 11:47:06.479067 2, 0xFFFF, sum = 0
4530 11:47:06.482340 3, 0xFFFF, sum = 0
4531 11:47:06.482441 4, 0xFFFF, sum = 0
4532 11:47:06.485501 5, 0xFFFF, sum = 0
4533 11:47:06.485643 6, 0xFFFF, sum = 0
4534 11:47:06.488867 7, 0xFFFF, sum = 0
4535 11:47:06.488947 8, 0x0, sum = 1
4536 11:47:06.492102 9, 0x0, sum = 2
4537 11:47:06.492178 10, 0x0, sum = 3
4538 11:47:06.495850 11, 0x0, sum = 4
4539 11:47:06.495954 best_step = 9
4540 11:47:06.496045
4541 11:47:06.496131 ==
4542 11:47:06.499168 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 11:47:06.505720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 11:47:06.505830 ==
4545 11:47:06.505925 RX Vref Scan: 1
4546 11:47:06.506025
4547 11:47:06.508884 RX Vref 0 -> 0, step: 1
4548 11:47:06.508993
4549 11:47:06.512331 RX Delay -163 -> 252, step: 8
4550 11:47:06.512442
4551 11:47:06.515596 Set Vref, RX VrefLevel [Byte0]: 55
4552 11:47:06.519036 [Byte1]: 48
4553 11:47:06.519120
4554 11:47:06.522107 Final RX Vref Byte 0 = 55 to rank0
4555 11:47:06.525391 Final RX Vref Byte 1 = 48 to rank0
4556 11:47:06.528937 Final RX Vref Byte 0 = 55 to rank1
4557 11:47:06.532131 Final RX Vref Byte 1 = 48 to rank1==
4558 11:47:06.535188 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 11:47:06.538694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:47:06.538806 ==
4561 11:47:06.541739 DQS Delay:
4562 11:47:06.541821 DQS0 = 0, DQS1 = 0
4563 11:47:06.541886 DQM Delay:
4564 11:47:06.545040 DQM0 = 49, DQM1 = 45
4565 11:47:06.545121 DQ Delay:
4566 11:47:06.548730 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4567 11:47:06.552213 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4568 11:47:06.555180 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4569 11:47:06.558905 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4570 11:47:06.558988
4571 11:47:06.559052
4572 11:47:06.568729 [DQSOSCAuto] RK0, (LSB)MR18= 0x486d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4573 11:47:06.568815 CH1 RK0: MR19=808, MR18=486D
4574 11:47:06.575101 CH1_RK0: MR19=0x808, MR18=0x486D, DQSOSC=389, MR23=63, INC=173, DEC=115
4575 11:47:06.575200
4576 11:47:06.578558 ----->DramcWriteLeveling(PI) begin...
4577 11:47:06.582083 ==
4578 11:47:06.582165 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 11:47:06.588630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 11:47:06.588713 ==
4581 11:47:06.591951 Write leveling (Byte 0): 30 => 30
4582 11:47:06.595310 Write leveling (Byte 1): 31 => 31
4583 11:47:06.595392 DramcWriteLeveling(PI) end<-----
4584 11:47:06.598593
4585 11:47:06.598674 ==
4586 11:47:06.601768 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 11:47:06.605506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 11:47:06.605646 ==
4589 11:47:06.608790 [Gating] SW mode calibration
4590 11:47:06.615237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 11:47:06.620047 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 11:47:06.625200 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 11:47:06.628377 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 11:47:06.632173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 11:47:06.638274 0 9 12 | B1->B0 | 2c2c 2f2f | 1 0 | (1 0) (0 0)
4596 11:47:06.641429 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 11:47:06.645183 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 11:47:06.651608 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:47:06.655419 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:47:06.658210 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:47:06.664852 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:47:06.668394 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 11:47:06.671342 0 10 12 | B1->B0 | 3a3a 3737 | 0 0 | (1 1) (0 0)
4604 11:47:06.678230 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 11:47:06.681410 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:47:06.684653 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:47:06.691232 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:47:06.694963 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:47:06.698305 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:47:06.704861 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4611 11:47:06.707887 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 11:47:06.711825 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:47:06.718194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:47:06.721426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:47:06.724828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:47:06.728250 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:47:06.734858 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:47:06.738131 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:47:06.741318 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:47:06.747704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:47:06.751681 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:47:06.754757 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:47:06.760918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:47:06.764351 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:47:06.767871 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:47:06.774567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:47:06.777739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4628 11:47:06.781165 Total UI for P1: 0, mck2ui 16
4629 11:47:06.784623 best dqsien dly found for B1: ( 0, 13, 10)
4630 11:47:06.787561 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 11:47:06.790897 Total UI for P1: 0, mck2ui 16
4632 11:47:06.794139 best dqsien dly found for B0: ( 0, 13, 12)
4633 11:47:06.797878 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4634 11:47:06.800957 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4635 11:47:06.804320
4636 11:47:06.808067 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 11:47:06.810762 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 11:47:06.814588 [Gating] SW calibration Done
4639 11:47:06.814669 ==
4640 11:47:06.817816 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:47:06.821174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:47:06.821256 ==
4643 11:47:06.821321 RX Vref Scan: 0
4644 11:47:06.821381
4645 11:47:06.824093 RX Vref 0 -> 0, step: 1
4646 11:47:06.824174
4647 11:47:06.827472 RX Delay -230 -> 252, step: 16
4648 11:47:06.830766 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4649 11:47:06.837834 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 11:47:06.841143 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4651 11:47:06.844506 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 11:47:06.847686 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 11:47:06.850630 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 11:47:06.857825 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4655 11:47:06.861066 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 11:47:06.863859 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 11:47:06.867813 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4658 11:47:06.870993 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 11:47:06.877286 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 11:47:06.880948 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 11:47:06.883885 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4662 11:47:06.887386 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 11:47:06.894166 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 11:47:06.894249 ==
4665 11:47:06.897170 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:47:06.900534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:47:06.900616 ==
4668 11:47:06.900681 DQS Delay:
4669 11:47:06.904185 DQS0 = 0, DQS1 = 0
4670 11:47:06.904266 DQM Delay:
4671 11:47:06.907298 DQM0 = 50, DQM1 = 46
4672 11:47:06.907379 DQ Delay:
4673 11:47:06.910523 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4674 11:47:06.914177 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4675 11:47:06.917423 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4676 11:47:06.920677 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4677 11:47:06.920755
4678 11:47:06.920819
4679 11:47:06.920878 ==
4680 11:47:06.923817 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 11:47:06.927024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 11:47:06.930253 ==
4683 11:47:06.930337
4684 11:47:06.930402
4685 11:47:06.930463 TX Vref Scan disable
4686 11:47:06.934161 == TX Byte 0 ==
4687 11:47:06.936782 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 11:47:06.940725 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 11:47:06.944026 == TX Byte 1 ==
4690 11:47:06.947190 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 11:47:06.950490 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 11:47:06.953830 ==
4693 11:47:06.956826 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 11:47:06.960314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 11:47:06.960398 ==
4696 11:47:06.960464
4697 11:47:06.960525
4698 11:47:06.963568 TX Vref Scan disable
4699 11:47:06.963650 == TX Byte 0 ==
4700 11:47:06.970279 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 11:47:06.973528 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 11:47:06.973618 == TX Byte 1 ==
4703 11:47:06.980133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 11:47:06.983280 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 11:47:06.983388
4706 11:47:06.983484 [DATLAT]
4707 11:47:06.986924 Freq=600, CH1 RK1
4708 11:47:06.987029
4709 11:47:06.987121 DATLAT Default: 0x9
4710 11:47:06.989884 0, 0xFFFF, sum = 0
4711 11:47:06.989994 1, 0xFFFF, sum = 0
4712 11:47:06.993647 2, 0xFFFF, sum = 0
4713 11:47:06.996616 3, 0xFFFF, sum = 0
4714 11:47:06.996721 4, 0xFFFF, sum = 0
4715 11:47:06.999764 5, 0xFFFF, sum = 0
4716 11:47:06.999872 6, 0xFFFF, sum = 0
4717 11:47:07.003400 7, 0xFFFF, sum = 0
4718 11:47:07.003486 8, 0x0, sum = 1
4719 11:47:07.003553 9, 0x0, sum = 2
4720 11:47:07.006823 10, 0x0, sum = 3
4721 11:47:07.006895 11, 0x0, sum = 4
4722 11:47:07.010176 best_step = 9
4723 11:47:07.010260
4724 11:47:07.010326 ==
4725 11:47:07.013180 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 11:47:07.016762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 11:47:07.016846 ==
4728 11:47:07.020014 RX Vref Scan: 0
4729 11:47:07.020098
4730 11:47:07.020163 RX Vref 0 -> 0, step: 1
4731 11:47:07.020223
4732 11:47:07.023177 RX Delay -163 -> 252, step: 8
4733 11:47:07.030346 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4734 11:47:07.034085 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 11:47:07.037174 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 11:47:07.040858 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4737 11:47:07.043619 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4738 11:47:07.050706 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 11:47:07.053963 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 11:47:07.057176 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 11:47:07.060531 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 11:47:07.063616 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4743 11:47:07.070504 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 11:47:07.073761 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4745 11:47:07.077161 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4746 11:47:07.080307 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 11:47:07.086802 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4748 11:47:07.090606 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4749 11:47:07.090715 ==
4750 11:47:07.093714 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 11:47:07.096805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 11:47:07.096886 ==
4753 11:47:07.100544 DQS Delay:
4754 11:47:07.100626 DQS0 = 0, DQS1 = 0
4755 11:47:07.100691 DQM Delay:
4756 11:47:07.103669 DQM0 = 50, DQM1 = 45
4757 11:47:07.103750 DQ Delay:
4758 11:47:07.106899 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4759 11:47:07.110821 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4760 11:47:07.113816 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4761 11:47:07.117092 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4762 11:47:07.117174
4763 11:47:07.117239
4764 11:47:07.126821 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4765 11:47:07.126906 CH1 RK1: MR19=808, MR18=6E24
4766 11:47:07.133768 CH1_RK1: MR19=0x808, MR18=0x6E24, DQSOSC=389, MR23=63, INC=173, DEC=115
4767 11:47:07.137483 [RxdqsGatingPostProcess] freq 600
4768 11:47:07.143738 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 11:47:07.146826 Pre-setting of DQS Precalculation
4770 11:47:07.150442 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 11:47:07.157257 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 11:47:07.167077 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 11:47:07.167185
4774 11:47:07.167290
4775 11:47:07.167382 [Calibration Summary] 1200 Mbps
4776 11:47:07.170332 CH 0, Rank 0
4777 11:47:07.170422 SW Impedance : PASS
4778 11:47:07.173300 DUTY Scan : NO K
4779 11:47:07.177110 ZQ Calibration : PASS
4780 11:47:07.177211 Jitter Meter : NO K
4781 11:47:07.180220 CBT Training : PASS
4782 11:47:07.183508 Write leveling : PASS
4783 11:47:07.183584 RX DQS gating : PASS
4784 11:47:07.186684 RX DQ/DQS(RDDQC) : PASS
4785 11:47:07.189997 TX DQ/DQS : PASS
4786 11:47:07.190078 RX DATLAT : PASS
4787 11:47:07.193440 RX DQ/DQS(Engine): PASS
4788 11:47:07.197005 TX OE : NO K
4789 11:47:07.197086 All Pass.
4790 11:47:07.197150
4791 11:47:07.197210 CH 0, Rank 1
4792 11:47:07.200008 SW Impedance : PASS
4793 11:47:07.203251 DUTY Scan : NO K
4794 11:47:07.203332 ZQ Calibration : PASS
4795 11:47:07.206956 Jitter Meter : NO K
4796 11:47:07.210299 CBT Training : PASS
4797 11:47:07.210380 Write leveling : PASS
4798 11:47:07.213471 RX DQS gating : PASS
4799 11:47:07.216785 RX DQ/DQS(RDDQC) : PASS
4800 11:47:07.216867 TX DQ/DQS : PASS
4801 11:47:07.220263 RX DATLAT : PASS
4802 11:47:07.220381 RX DQ/DQS(Engine): PASS
4803 11:47:07.223379 TX OE : NO K
4804 11:47:07.223492 All Pass.
4805 11:47:07.223559
4806 11:47:07.226660 CH 1, Rank 0
4807 11:47:07.226771 SW Impedance : PASS
4808 11:47:07.230038 DUTY Scan : NO K
4809 11:47:07.233131 ZQ Calibration : PASS
4810 11:47:07.233226 Jitter Meter : NO K
4811 11:47:07.236794 CBT Training : PASS
4812 11:47:07.239941 Write leveling : PASS
4813 11:47:07.240083 RX DQS gating : PASS
4814 11:47:07.243632 RX DQ/DQS(RDDQC) : PASS
4815 11:47:07.246307 TX DQ/DQS : PASS
4816 11:47:07.246435 RX DATLAT : PASS
4817 11:47:07.249892 RX DQ/DQS(Engine): PASS
4818 11:47:07.253080 TX OE : NO K
4819 11:47:07.253183 All Pass.
4820 11:47:07.253286
4821 11:47:07.253390 CH 1, Rank 1
4822 11:47:07.256883 SW Impedance : PASS
4823 11:47:07.260080 DUTY Scan : NO K
4824 11:47:07.260187 ZQ Calibration : PASS
4825 11:47:07.263181 Jitter Meter : NO K
4826 11:47:07.266534 CBT Training : PASS
4827 11:47:07.266643 Write leveling : PASS
4828 11:47:07.269904 RX DQS gating : PASS
4829 11:47:07.270005 RX DQ/DQS(RDDQC) : PASS
4830 11:47:07.273227 TX DQ/DQS : PASS
4831 11:47:07.276646 RX DATLAT : PASS
4832 11:47:07.276738 RX DQ/DQS(Engine): PASS
4833 11:47:07.279870 TX OE : NO K
4834 11:47:07.279972 All Pass.
4835 11:47:07.280066
4836 11:47:07.283438 DramC Write-DBI off
4837 11:47:07.286511 PER_BANK_REFRESH: Hybrid Mode
4838 11:47:07.286661 TX_TRACKING: ON
4839 11:47:07.296511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 11:47:07.299859 [FAST_K] Save calibration result to emmc
4841 11:47:07.303048 dramc_set_vcore_voltage set vcore to 662500
4842 11:47:07.306197 Read voltage for 933, 3
4843 11:47:07.306291 Vio18 = 0
4844 11:47:07.306357 Vcore = 662500
4845 11:47:07.309521 Vdram = 0
4846 11:47:07.309635 Vddq = 0
4847 11:47:07.309698 Vmddr = 0
4848 11:47:07.315983 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 11:47:07.319445 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 11:47:07.322724 MEM_TYPE=3, freq_sel=17
4851 11:47:07.326601 sv_algorithm_assistance_LP4_1600
4852 11:47:07.329563 ============ PULL DRAM RESETB DOWN ============
4853 11:47:07.336608 ========== PULL DRAM RESETB DOWN end =========
4854 11:47:07.339893 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 11:47:07.343091 ===================================
4856 11:47:07.346323 LPDDR4 DRAM CONFIGURATION
4857 11:47:07.349192 ===================================
4858 11:47:07.349297 EX_ROW_EN[0] = 0x0
4859 11:47:07.353063 EX_ROW_EN[1] = 0x0
4860 11:47:07.353164 LP4Y_EN = 0x0
4861 11:47:07.356336 WORK_FSP = 0x0
4862 11:47:07.356445 WL = 0x3
4863 11:47:07.359363 RL = 0x3
4864 11:47:07.359438 BL = 0x2
4865 11:47:07.362688 RPST = 0x0
4866 11:47:07.362764 RD_PRE = 0x0
4867 11:47:07.366449 WR_PRE = 0x1
4868 11:47:07.366547 WR_PST = 0x0
4869 11:47:07.369765 DBI_WR = 0x0
4870 11:47:07.369841 DBI_RD = 0x0
4871 11:47:07.372700 OTF = 0x1
4872 11:47:07.376332 ===================================
4873 11:47:07.379423 ===================================
4874 11:47:07.379538 ANA top config
4875 11:47:07.382727 ===================================
4876 11:47:07.386071 DLL_ASYNC_EN = 0
4877 11:47:07.389764 ALL_SLAVE_EN = 1
4878 11:47:07.392845 NEW_RANK_MODE = 1
4879 11:47:07.392952 DLL_IDLE_MODE = 1
4880 11:47:07.395985 LP45_APHY_COMB_EN = 1
4881 11:47:07.399318 TX_ODT_DIS = 1
4882 11:47:07.402638 NEW_8X_MODE = 1
4883 11:47:07.406376 ===================================
4884 11:47:07.409530 ===================================
4885 11:47:07.412841 data_rate = 1866
4886 11:47:07.412944 CKR = 1
4887 11:47:07.415969 DQ_P2S_RATIO = 8
4888 11:47:07.419632 ===================================
4889 11:47:07.422709 CA_P2S_RATIO = 8
4890 11:47:07.425912 DQ_CA_OPEN = 0
4891 11:47:07.429128 DQ_SEMI_OPEN = 0
4892 11:47:07.432825 CA_SEMI_OPEN = 0
4893 11:47:07.432925 CA_FULL_RATE = 0
4894 11:47:07.435920 DQ_CKDIV4_EN = 1
4895 11:47:07.439029 CA_CKDIV4_EN = 1
4896 11:47:07.442406 CA_PREDIV_EN = 0
4897 11:47:07.445723 PH8_DLY = 0
4898 11:47:07.449537 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 11:47:07.449630 DQ_AAMCK_DIV = 4
4900 11:47:07.452768 CA_AAMCK_DIV = 4
4901 11:47:07.456062 CA_ADMCK_DIV = 4
4902 11:47:07.459121 DQ_TRACK_CA_EN = 0
4903 11:47:07.462746 CA_PICK = 933
4904 11:47:07.466086 CA_MCKIO = 933
4905 11:47:07.469365 MCKIO_SEMI = 0
4906 11:47:07.469466 PLL_FREQ = 3732
4907 11:47:07.472696 DQ_UI_PI_RATIO = 32
4908 11:47:07.475730 CA_UI_PI_RATIO = 0
4909 11:47:07.479364 ===================================
4910 11:47:07.482534 ===================================
4911 11:47:07.485565 memory_type:LPDDR4
4912 11:47:07.485681 GP_NUM : 10
4913 11:47:07.489118 SRAM_EN : 1
4914 11:47:07.492247 MD32_EN : 0
4915 11:47:07.495465 ===================================
4916 11:47:07.495569 [ANA_INIT] >>>>>>>>>>>>>>
4917 11:47:07.498698 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 11:47:07.502455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 11:47:07.505755 ===================================
4920 11:47:07.508834 data_rate = 1866,PCW = 0X8f00
4921 11:47:07.512085 ===================================
4922 11:47:07.515900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 11:47:07.522407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 11:47:07.525487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 11:47:07.532993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 11:47:07.536157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 11:47:07.539278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 11:47:07.539382 [ANA_INIT] flow start
4929 11:47:07.542272 [ANA_INIT] PLL >>>>>>>>
4930 11:47:07.545959 [ANA_INIT] PLL <<<<<<<<
4931 11:47:07.549266 [ANA_INIT] MIDPI >>>>>>>>
4932 11:47:07.549366 [ANA_INIT] MIDPI <<<<<<<<
4933 11:47:07.552479 [ANA_INIT] DLL >>>>>>>>
4934 11:47:07.555783 [ANA_INIT] flow end
4935 11:47:07.559058 ============ LP4 DIFF to SE enter ============
4936 11:47:07.562232 ============ LP4 DIFF to SE exit ============
4937 11:47:07.565438 [ANA_INIT] <<<<<<<<<<<<<
4938 11:47:07.568632 [Flow] Enable top DCM control >>>>>
4939 11:47:07.571931 [Flow] Enable top DCM control <<<<<
4940 11:47:07.575950 Enable DLL master slave shuffle
4941 11:47:07.578808 ==============================================================
4942 11:47:07.581980 Gating Mode config
4943 11:47:07.585438 ==============================================================
4944 11:47:07.588922 Config description:
4945 11:47:07.598705 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 11:47:07.605591 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 11:47:07.608569 SELPH_MODE 0: By rank 1: By Phase
4948 11:47:07.615593 ==============================================================
4949 11:47:07.618892 GAT_TRACK_EN = 1
4950 11:47:07.622085 RX_GATING_MODE = 2
4951 11:47:07.625344 RX_GATING_TRACK_MODE = 2
4952 11:47:07.628653 SELPH_MODE = 1
4953 11:47:07.631862 PICG_EARLY_EN = 1
4954 11:47:07.635562 VALID_LAT_VALUE = 1
4955 11:47:07.638609 ==============================================================
4956 11:47:07.641717 Enter into Gating configuration >>>>
4957 11:47:07.645236 Exit from Gating configuration <<<<
4958 11:47:07.648566 Enter into DVFS_PRE_config >>>>>
4959 11:47:07.658897 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 11:47:07.662224 Exit from DVFS_PRE_config <<<<<
4961 11:47:07.665522 Enter into PICG configuration >>>>
4962 11:47:07.668626 Exit from PICG configuration <<<<
4963 11:47:07.671970 [RX_INPUT] configuration >>>>>
4964 11:47:07.675218 [RX_INPUT] configuration <<<<<
4965 11:47:07.678405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 11:47:07.684922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 11:47:07.691883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 11:47:07.698269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 11:47:07.704919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 11:47:07.712203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 11:47:07.714795 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 11:47:07.717790 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 11:47:07.721793 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 11:47:07.728255 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 11:47:07.731533 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 11:47:07.734815 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 11:47:07.738101 ===================================
4978 11:47:07.741275 LPDDR4 DRAM CONFIGURATION
4979 11:47:07.744506 ===================================
4980 11:47:07.744619 EX_ROW_EN[0] = 0x0
4981 11:47:07.748263 EX_ROW_EN[1] = 0x0
4982 11:47:07.748365 LP4Y_EN = 0x0
4983 11:47:07.751000 WORK_FSP = 0x0
4984 11:47:07.754592 WL = 0x3
4985 11:47:07.754698 RL = 0x3
4986 11:47:07.757869 BL = 0x2
4987 11:47:07.757974 RPST = 0x0
4988 11:47:07.761161 RD_PRE = 0x0
4989 11:47:07.761261 WR_PRE = 0x1
4990 11:47:07.764495 WR_PST = 0x0
4991 11:47:07.764567 DBI_WR = 0x0
4992 11:47:07.767873 DBI_RD = 0x0
4993 11:47:07.767947 OTF = 0x1
4994 11:47:07.770983 ===================================
4995 11:47:07.774920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 11:47:07.781380 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 11:47:07.784651 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 11:47:07.787965 ===================================
4999 11:47:07.791149 LPDDR4 DRAM CONFIGURATION
5000 11:47:07.794388 ===================================
5001 11:47:07.794491 EX_ROW_EN[0] = 0x10
5002 11:47:07.797694 EX_ROW_EN[1] = 0x0
5003 11:47:07.797796 LP4Y_EN = 0x0
5004 11:47:07.801000 WORK_FSP = 0x0
5005 11:47:07.801098 WL = 0x3
5006 11:47:07.804708 RL = 0x3
5007 11:47:07.804811 BL = 0x2
5008 11:47:07.807950 RPST = 0x0
5009 11:47:07.811239 RD_PRE = 0x0
5010 11:47:07.811344 WR_PRE = 0x1
5011 11:47:07.814310 WR_PST = 0x0
5012 11:47:07.814387 DBI_WR = 0x0
5013 11:47:07.817607 DBI_RD = 0x0
5014 11:47:07.817685 OTF = 0x1
5015 11:47:07.820851 ===================================
5016 11:47:07.827936 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 11:47:07.831525 nWR fixed to 30
5018 11:47:07.834903 [ModeRegInit_LP4] CH0 RK0
5019 11:47:07.835006 [ModeRegInit_LP4] CH0 RK1
5020 11:47:07.837802 [ModeRegInit_LP4] CH1 RK0
5021 11:47:07.841233 [ModeRegInit_LP4] CH1 RK1
5022 11:47:07.841337 match AC timing 9
5023 11:47:07.848290 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 11:47:07.851336 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 11:47:07.854514 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 11:47:07.861272 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 11:47:07.865041 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 11:47:07.865150 ==
5029 11:47:07.868051 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 11:47:07.871254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 11:47:07.871358 ==
5032 11:47:07.878320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 11:47:07.884891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5034 11:47:07.888121 [CA 0] Center 37 (7~68) winsize 62
5035 11:47:07.891390 [CA 1] Center 37 (7~68) winsize 62
5036 11:47:07.894712 [CA 2] Center 34 (4~65) winsize 62
5037 11:47:07.898051 [CA 3] Center 34 (3~65) winsize 63
5038 11:47:07.901282 [CA 4] Center 33 (3~63) winsize 61
5039 11:47:07.904487 [CA 5] Center 32 (2~62) winsize 61
5040 11:47:07.904587
5041 11:47:07.907613 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5042 11:47:07.907713
5043 11:47:07.911072 [CATrainingPosCal] consider 1 rank data
5044 11:47:07.914725 u2DelayCellTimex100 = 270/100 ps
5045 11:47:07.917912 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 11:47:07.921319 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 11:47:07.924882 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 11:47:07.927866 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5049 11:47:07.931279 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5050 11:47:07.937799 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 11:47:07.937902
5052 11:47:07.940866 CA PerBit enable=1, Macro0, CA PI delay=32
5053 11:47:07.940973
5054 11:47:07.944449 [CBTSetCACLKResult] CA Dly = 32
5055 11:47:07.944548 CS Dly: 5 (0~36)
5056 11:47:07.944651 ==
5057 11:47:07.947399 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 11:47:07.951232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 11:47:07.954063 ==
5060 11:47:07.957605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 11:47:07.964371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 11:47:07.967791 [CA 0] Center 37 (6~68) winsize 63
5063 11:47:07.970836 [CA 1] Center 37 (6~68) winsize 63
5064 11:47:07.973998 [CA 2] Center 34 (4~65) winsize 62
5065 11:47:07.977523 [CA 3] Center 34 (3~65) winsize 63
5066 11:47:07.980538 [CA 4] Center 32 (2~63) winsize 62
5067 11:47:07.984047 [CA 5] Center 32 (2~62) winsize 61
5068 11:47:07.984152
5069 11:47:07.987306 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 11:47:07.987407
5071 11:47:07.990579 [CATrainingPosCal] consider 2 rank data
5072 11:47:07.994463 u2DelayCellTimex100 = 270/100 ps
5073 11:47:07.997712 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 11:47:08.000933 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 11:47:08.004295 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 11:47:08.007535 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5077 11:47:08.013956 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 11:47:08.017856 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 11:47:08.017960
5080 11:47:08.020587 CA PerBit enable=1, Macro0, CA PI delay=32
5081 11:47:08.020692
5082 11:47:08.024452 [CBTSetCACLKResult] CA Dly = 32
5083 11:47:08.024554 CS Dly: 5 (0~37)
5084 11:47:08.024648
5085 11:47:08.027731 ----->DramcWriteLeveling(PI) begin...
5086 11:47:08.027834 ==
5087 11:47:08.030797 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:47:08.037505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:47:08.037621 ==
5090 11:47:08.040511 Write leveling (Byte 0): 35 => 35
5091 11:47:08.040620 Write leveling (Byte 1): 29 => 29
5092 11:47:08.043783 DramcWriteLeveling(PI) end<-----
5093 11:47:08.043885
5094 11:47:08.047130 ==
5095 11:47:08.047237 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 11:47:08.053989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:47:08.054095 ==
5098 11:47:08.057524 [Gating] SW mode calibration
5099 11:47:08.063875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 11:47:08.067662 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 11:47:08.073899 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5102 11:47:08.077686 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 11:47:08.080585 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:47:08.087533 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:47:08.090648 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:47:08.094145 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:47:08.097435 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5108 11:47:08.104075 0 14 28 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
5109 11:47:08.107372 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5110 11:47:08.110775 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:47:08.117338 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:47:08.120611 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:47:08.123834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:47:08.130438 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:47:08.133710 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5116 11:47:08.137060 0 15 28 | B1->B0 | 2626 403f | 0 1 | (0 0) (0 0)
5117 11:47:08.143703 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5118 11:47:08.147307 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:47:08.150201 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:47:08.157158 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:47:08.160372 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:47:08.163379 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:47:08.170275 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 11:47:08.173390 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 11:47:08.177055 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 11:47:08.183716 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:47:08.186864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:47:08.189909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:47:08.196451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:47:08.200347 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:47:08.203389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:47:08.210345 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:47:08.212812 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:47:08.216412 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:47:08.223308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:47:08.226578 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:47:08.229832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:47:08.236327 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:47:08.239602 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 11:47:08.242816 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 11:47:08.246018 Total UI for P1: 0, mck2ui 16
5142 11:47:08.249382 best dqsien dly found for B0: ( 1, 2, 24)
5143 11:47:08.256382 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 11:47:08.259265 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 11:47:08.262693 Total UI for P1: 0, mck2ui 16
5146 11:47:08.266344 best dqsien dly found for B1: ( 1, 2, 30)
5147 11:47:08.269504 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5148 11:47:08.272967 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 11:47:08.273050
5150 11:47:08.276149 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5151 11:47:08.279411 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 11:47:08.282418 [Gating] SW calibration Done
5153 11:47:08.282519 ==
5154 11:47:08.286185 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 11:47:08.289170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 11:47:08.292859 ==
5157 11:47:08.292942 RX Vref Scan: 0
5158 11:47:08.293045
5159 11:47:08.295865 RX Vref 0 -> 0, step: 1
5160 11:47:08.295947
5161 11:47:08.296031 RX Delay -80 -> 252, step: 8
5162 11:47:08.303042 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 11:47:08.306209 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 11:47:08.309562 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 11:47:08.312880 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5166 11:47:08.316115 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 11:47:08.322601 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 11:47:08.326556 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5169 11:47:08.329346 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 11:47:08.332805 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 11:47:08.335982 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5172 11:47:08.339321 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 11:47:08.345808 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 11:47:08.349205 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 11:47:08.352941 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5176 11:47:08.356143 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5177 11:47:08.359518 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 11:47:08.359601 ==
5179 11:47:08.362762 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:47:08.369711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:47:08.369795 ==
5182 11:47:08.369860 DQS Delay:
5183 11:47:08.372627 DQS0 = 0, DQS1 = 0
5184 11:47:08.372714 DQM Delay:
5185 11:47:08.372779 DQM0 = 105, DQM1 = 95
5186 11:47:08.375899 DQ Delay:
5187 11:47:08.379054 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5188 11:47:08.382787 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5189 11:47:08.385763 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5190 11:47:08.389440 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5191 11:47:08.389548
5192 11:47:08.389631
5193 11:47:08.389692 ==
5194 11:47:08.392668 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 11:47:08.395784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 11:47:08.395886 ==
5197 11:47:08.395975
5198 11:47:08.396072
5199 11:47:08.398903 TX Vref Scan disable
5200 11:47:08.402537 == TX Byte 0 ==
5201 11:47:08.405807 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5202 11:47:08.408981 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5203 11:47:08.412267 == TX Byte 1 ==
5204 11:47:08.415545 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5205 11:47:08.418863 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5206 11:47:08.418940 ==
5207 11:47:08.422787 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:47:08.429073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:47:08.429173 ==
5210 11:47:08.429272
5211 11:47:08.429360
5212 11:47:08.429446 TX Vref Scan disable
5213 11:47:08.432873 == TX Byte 0 ==
5214 11:47:08.436574 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5215 11:47:08.442764 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5216 11:47:08.442866 == TX Byte 1 ==
5217 11:47:08.446371 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5218 11:47:08.452996 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5219 11:47:08.453095
5220 11:47:08.453185 [DATLAT]
5221 11:47:08.453282 Freq=933, CH0 RK0
5222 11:47:08.453370
5223 11:47:08.456289 DATLAT Default: 0xd
5224 11:47:08.456359 0, 0xFFFF, sum = 0
5225 11:47:08.459452 1, 0xFFFF, sum = 0
5226 11:47:08.459550 2, 0xFFFF, sum = 0
5227 11:47:08.462755 3, 0xFFFF, sum = 0
5228 11:47:08.466116 4, 0xFFFF, sum = 0
5229 11:47:08.466200 5, 0xFFFF, sum = 0
5230 11:47:08.469475 6, 0xFFFF, sum = 0
5231 11:47:08.469571 7, 0xFFFF, sum = 0
5232 11:47:08.472736 8, 0xFFFF, sum = 0
5233 11:47:08.472833 9, 0xFFFF, sum = 0
5234 11:47:08.476570 10, 0x0, sum = 1
5235 11:47:08.476678 11, 0x0, sum = 2
5236 11:47:08.476778 12, 0x0, sum = 3
5237 11:47:08.479853 13, 0x0, sum = 4
5238 11:47:08.479957 best_step = 11
5239 11:47:08.480046
5240 11:47:08.480133 ==
5241 11:47:08.483466 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:47:08.489642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:47:08.489744 ==
5244 11:47:08.489834 RX Vref Scan: 1
5245 11:47:08.489920
5246 11:47:08.492955 RX Vref 0 -> 0, step: 1
5247 11:47:08.493054
5248 11:47:08.496149 RX Delay -45 -> 252, step: 4
5249 11:47:08.496252
5250 11:47:08.499777 Set Vref, RX VrefLevel [Byte0]: 54
5251 11:47:08.502615 [Byte1]: 58
5252 11:47:08.502715
5253 11:47:08.505902 Final RX Vref Byte 0 = 54 to rank0
5254 11:47:08.509114 Final RX Vref Byte 1 = 58 to rank0
5255 11:47:08.512807 Final RX Vref Byte 0 = 54 to rank1
5256 11:47:08.516039 Final RX Vref Byte 1 = 58 to rank1==
5257 11:47:08.519221 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:47:08.522506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:47:08.522610 ==
5260 11:47:08.525777 DQS Delay:
5261 11:47:08.525873 DQS0 = 0, DQS1 = 0
5262 11:47:08.529652 DQM Delay:
5263 11:47:08.529749 DQM0 = 104, DQM1 = 97
5264 11:47:08.529823 DQ Delay:
5265 11:47:08.532652 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5266 11:47:08.535818 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5267 11:47:08.542966 DQ8 =86, DQ9 =88, DQ10 =100, DQ11 =92
5268 11:47:08.545726 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5269 11:47:08.545831
5270 11:47:08.545927
5271 11:47:08.552679 [DQSOSCAuto] RK0, (LSB)MR18= 0x352d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
5272 11:47:08.555784 CH0 RK0: MR19=505, MR18=352D
5273 11:47:08.562415 CH0_RK0: MR19=0x505, MR18=0x352D, DQSOSC=405, MR23=63, INC=66, DEC=44
5274 11:47:08.562571
5275 11:47:08.566360 ----->DramcWriteLeveling(PI) begin...
5276 11:47:08.566476 ==
5277 11:47:08.569544 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 11:47:08.572868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:47:08.572972 ==
5280 11:47:08.576218 Write leveling (Byte 0): 30 => 30
5281 11:47:08.579645 Write leveling (Byte 1): 30 => 30
5282 11:47:08.582774 DramcWriteLeveling(PI) end<-----
5283 11:47:08.582876
5284 11:47:08.582969 ==
5285 11:47:08.586180 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:47:08.589206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:47:08.589316 ==
5288 11:47:08.592511 [Gating] SW mode calibration
5289 11:47:08.599231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 11:47:08.606184 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 11:47:08.609420 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5292 11:47:08.615571 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:47:08.619012 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:47:08.622410 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:47:08.629177 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 11:47:08.632599 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 11:47:08.635712 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 11:47:08.642108 0 14 28 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (1 1)
5299 11:47:08.645384 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5300 11:47:08.648713 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 11:47:08.652022 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:47:08.659181 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:47:08.662470 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:47:08.665538 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 11:47:08.672065 0 15 24 | B1->B0 | 2828 2626 | 0 0 | (1 1) (0 0)
5306 11:47:08.675897 0 15 28 | B1->B0 | 3b3b 3939 | 1 1 | (0 0) (0 0)
5307 11:47:08.678534 1 0 0 | B1->B0 | 4545 4343 | 0 1 | (0 0) (0 0)
5308 11:47:08.685776 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:47:08.688526 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:47:08.692282 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:47:08.698783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 11:47:08.702042 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:47:08.705292 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5314 11:47:08.712273 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 11:47:08.715443 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:47:08.718656 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:47:08.725608 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:47:08.728763 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:47:08.732173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:47:08.738685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:47:08.742164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:47:08.745431 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:47:08.752218 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:47:08.755050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:47:08.758629 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:47:08.765655 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:47:08.768859 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:47:08.772166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:47:08.775129 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:47:08.781767 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 11:47:08.785377 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:47:08.788494 Total UI for P1: 0, mck2ui 16
5333 11:47:08.791891 best dqsien dly found for B0: ( 1, 2, 28)
5334 11:47:08.795190 Total UI for P1: 0, mck2ui 16
5335 11:47:08.798479 best dqsien dly found for B1: ( 1, 2, 28)
5336 11:47:08.801857 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 11:47:08.805125 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 11:47:08.805212
5339 11:47:08.808388 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 11:47:08.814853 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 11:47:08.814930 [Gating] SW calibration Done
5342 11:47:08.814992 ==
5343 11:47:08.818471 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:47:08.824763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:47:08.824851 ==
5346 11:47:08.824919 RX Vref Scan: 0
5347 11:47:08.824980
5348 11:47:08.828593 RX Vref 0 -> 0, step: 1
5349 11:47:08.828734
5350 11:47:08.831646 RX Delay -80 -> 252, step: 8
5351 11:47:08.834864 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5352 11:47:08.838053 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 11:47:08.841953 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5354 11:47:08.845103 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 11:47:08.852043 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 11:47:08.855134 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5357 11:47:08.858283 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5358 11:47:08.861542 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5359 11:47:08.864966 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5360 11:47:08.868382 iDelay=208, Bit 9, Center 83 (0 ~ 167) 168
5361 11:47:08.875147 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 11:47:08.878533 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 11:47:08.881899 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5364 11:47:08.885259 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 11:47:08.888422 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5366 11:47:08.894943 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5367 11:47:08.895022 ==
5368 11:47:08.898191 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:47:08.901867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:47:08.901951 ==
5371 11:47:08.902014 DQS Delay:
5372 11:47:08.904626 DQS0 = 0, DQS1 = 0
5373 11:47:08.904698 DQM Delay:
5374 11:47:08.908439 DQM0 = 104, DQM1 = 95
5375 11:47:08.908513 DQ Delay:
5376 11:47:08.911778 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5377 11:47:08.915069 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5378 11:47:08.918292 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5379 11:47:08.921596 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5380 11:47:08.921685
5381 11:47:08.921749
5382 11:47:08.921807 ==
5383 11:47:08.924755 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:47:08.931352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:47:08.931431 ==
5386 11:47:08.931522
5387 11:47:08.931609
5388 11:47:08.931696 TX Vref Scan disable
5389 11:47:08.934536 == TX Byte 0 ==
5390 11:47:08.937894 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5391 11:47:08.944761 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5392 11:47:08.944867 == TX Byte 1 ==
5393 11:47:08.947955 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5394 11:47:08.954686 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5395 11:47:08.954763 ==
5396 11:47:08.957756 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:47:08.961315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:47:08.961419 ==
5399 11:47:08.961510
5400 11:47:08.961610
5401 11:47:08.964597 TX Vref Scan disable
5402 11:47:08.964671 == TX Byte 0 ==
5403 11:47:08.971045 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5404 11:47:08.974724 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5405 11:47:08.974834 == TX Byte 1 ==
5406 11:47:08.981348 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5407 11:47:08.984318 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5408 11:47:08.984424
5409 11:47:08.984514 [DATLAT]
5410 11:47:08.987715 Freq=933, CH0 RK1
5411 11:47:08.987822
5412 11:47:08.987916 DATLAT Default: 0xb
5413 11:47:08.991031 0, 0xFFFF, sum = 0
5414 11:47:08.991132 1, 0xFFFF, sum = 0
5415 11:47:08.994313 2, 0xFFFF, sum = 0
5416 11:47:08.994415 3, 0xFFFF, sum = 0
5417 11:47:08.997698 4, 0xFFFF, sum = 0
5418 11:47:09.001670 5, 0xFFFF, sum = 0
5419 11:47:09.001772 6, 0xFFFF, sum = 0
5420 11:47:09.004836 7, 0xFFFF, sum = 0
5421 11:47:09.004937 8, 0xFFFF, sum = 0
5422 11:47:09.008111 9, 0xFFFF, sum = 0
5423 11:47:09.008185 10, 0x0, sum = 1
5424 11:47:09.011084 11, 0x0, sum = 2
5425 11:47:09.011155 12, 0x0, sum = 3
5426 11:47:09.011215 13, 0x0, sum = 4
5427 11:47:09.014948 best_step = 11
5428 11:47:09.015059
5429 11:47:09.015156 ==
5430 11:47:09.017539 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:47:09.021164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:47:09.021270 ==
5433 11:47:09.024445 RX Vref Scan: 0
5434 11:47:09.024522
5435 11:47:09.024585 RX Vref 0 -> 0, step: 1
5436 11:47:09.027623
5437 11:47:09.027695 RX Delay -45 -> 252, step: 4
5438 11:47:09.035656 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5439 11:47:09.038320 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5440 11:47:09.042123 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 11:47:09.045121 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5442 11:47:09.048594 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 11:47:09.055298 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 11:47:09.058575 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5445 11:47:09.061409 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 11:47:09.065271 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5447 11:47:09.068384 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5448 11:47:09.075040 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5449 11:47:09.078393 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5450 11:47:09.081584 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5451 11:47:09.084822 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5452 11:47:09.088512 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5453 11:47:09.095367 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5454 11:47:09.095470 ==
5455 11:47:09.098679 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:47:09.102008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:47:09.102078 ==
5458 11:47:09.102175 DQS Delay:
5459 11:47:09.105120 DQS0 = 0, DQS1 = 0
5460 11:47:09.105211 DQM Delay:
5461 11:47:09.108455 DQM0 = 104, DQM1 = 96
5462 11:47:09.108524 DQ Delay:
5463 11:47:09.111698 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5464 11:47:09.115006 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5465 11:47:09.118269 DQ8 =86, DQ9 =86, DQ10 =98, DQ11 =90
5466 11:47:09.121544 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5467 11:47:09.121680
5468 11:47:09.121751
5469 11:47:09.131451 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5470 11:47:09.135066 CH0 RK1: MR19=505, MR18=2A02
5471 11:47:09.138316 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 11:47:09.141601 [RxdqsGatingPostProcess] freq 933
5473 11:47:09.148314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 11:47:09.151681 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 11:47:09.154901 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 11:47:09.157839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 11:47:09.161585 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 11:47:09.164770 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 11:47:09.168350 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 11:47:09.168447 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 11:47:09.171788 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 11:47:09.174695 Pre-setting of DQS Precalculation
5483 11:47:09.181340 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 11:47:09.181422 ==
5485 11:47:09.184745 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 11:47:09.188058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:47:09.188134 ==
5488 11:47:09.194964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 11:47:09.201683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 11:47:09.204838 [CA 0] Center 36 (6~67) winsize 62
5491 11:47:09.208173 [CA 1] Center 37 (6~68) winsize 63
5492 11:47:09.211448 [CA 2] Center 34 (4~65) winsize 62
5493 11:47:09.214477 [CA 3] Center 34 (4~65) winsize 62
5494 11:47:09.217914 [CA 4] Center 34 (4~65) winsize 62
5495 11:47:09.221680 [CA 5] Center 33 (3~64) winsize 62
5496 11:47:09.221763
5497 11:47:09.224359 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 11:47:09.224454
5499 11:47:09.228195 [CATrainingPosCal] consider 1 rank data
5500 11:47:09.231387 u2DelayCellTimex100 = 270/100 ps
5501 11:47:09.234849 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 11:47:09.238078 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5503 11:47:09.241514 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 11:47:09.244428 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 11:47:09.248213 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 11:47:09.251553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 11:47:09.251625
5508 11:47:09.258056 CA PerBit enable=1, Macro0, CA PI delay=33
5509 11:47:09.258132
5510 11:47:09.258195 [CBTSetCACLKResult] CA Dly = 33
5511 11:47:09.261218 CS Dly: 6 (0~37)
5512 11:47:09.261312 ==
5513 11:47:09.264309 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 11:47:09.267828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:47:09.267930 ==
5516 11:47:09.274163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 11:47:09.280948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 11:47:09.284742 [CA 0] Center 36 (6~67) winsize 62
5519 11:47:09.287709 [CA 1] Center 37 (6~68) winsize 63
5520 11:47:09.291189 [CA 2] Center 35 (4~66) winsize 63
5521 11:47:09.294445 [CA 3] Center 34 (4~65) winsize 62
5522 11:47:09.298157 [CA 4] Center 34 (4~65) winsize 62
5523 11:47:09.301111 [CA 5] Center 34 (4~64) winsize 61
5524 11:47:09.301218
5525 11:47:09.304457 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 11:47:09.304555
5527 11:47:09.308067 [CATrainingPosCal] consider 2 rank data
5528 11:47:09.311225 u2DelayCellTimex100 = 270/100 ps
5529 11:47:09.314378 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5530 11:47:09.317789 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5531 11:47:09.321115 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5532 11:47:09.324367 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5533 11:47:09.327621 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5534 11:47:09.330798 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5535 11:47:09.330874
5536 11:47:09.337225 CA PerBit enable=1, Macro0, CA PI delay=34
5537 11:47:09.337334
5538 11:47:09.337450 [CBTSetCACLKResult] CA Dly = 34
5539 11:47:09.341280 CS Dly: 7 (0~39)
5540 11:47:09.341381
5541 11:47:09.344361 ----->DramcWriteLeveling(PI) begin...
5542 11:47:09.344458 ==
5543 11:47:09.347786 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 11:47:09.350918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:47:09.350993 ==
5546 11:47:09.354476 Write leveling (Byte 0): 26 => 26
5547 11:47:09.357531 Write leveling (Byte 1): 29 => 29
5548 11:47:09.360667 DramcWriteLeveling(PI) end<-----
5549 11:47:09.360752
5550 11:47:09.360813 ==
5551 11:47:09.364175 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:47:09.367305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:47:09.370522 ==
5554 11:47:09.370614 [Gating] SW mode calibration
5555 11:47:09.380955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 11:47:09.384141 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 11:47:09.387680 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 11:47:09.394423 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:47:09.397494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:47:09.400657 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:47:09.407284 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:47:09.410390 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 11:47:09.413973 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
5564 11:47:09.420822 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5565 11:47:09.423637 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 11:47:09.427587 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:47:09.434130 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:47:09.437341 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:47:09.440592 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:47:09.447011 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:47:09.450387 0 15 24 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
5572 11:47:09.453647 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5573 11:47:09.460720 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:47:09.463722 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:47:09.467327 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:47:09.474364 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:47:09.477383 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:47:09.480473 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:47:09.484491 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 11:47:09.490299 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5581 11:47:09.494107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:47:09.497021 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:47:09.503948 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:47:09.507024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:47:09.510773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:47:09.516969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:47:09.520748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:47:09.523942 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:47:09.530143 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:47:09.533874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:47:09.537054 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:47:09.543996 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:47:09.547263 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:47:09.550543 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:47:09.557055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:47:09.560508 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 11:47:09.563669 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 11:47:09.567096 Total UI for P1: 0, mck2ui 16
5599 11:47:09.570502 best dqsien dly found for B0: ( 1, 2, 28)
5600 11:47:09.573613 Total UI for P1: 0, mck2ui 16
5601 11:47:09.577357 best dqsien dly found for B1: ( 1, 2, 28)
5602 11:47:09.580469 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5603 11:47:09.583914 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5604 11:47:09.584026
5605 11:47:09.587270 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5606 11:47:09.593639 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5607 11:47:09.593748 [Gating] SW calibration Done
5608 11:47:09.593816 ==
5609 11:47:09.596878 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 11:47:09.603617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 11:47:09.603722 ==
5612 11:47:09.603818 RX Vref Scan: 0
5613 11:47:09.603907
5614 11:47:09.607057 RX Vref 0 -> 0, step: 1
5615 11:47:09.607159
5616 11:47:09.610208 RX Delay -80 -> 252, step: 8
5617 11:47:09.613485 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5618 11:47:09.617092 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 11:47:09.620146 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5620 11:47:09.623415 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5621 11:47:09.630444 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5622 11:47:09.633488 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5623 11:47:09.636890 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5624 11:47:09.640582 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5625 11:47:09.643420 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5626 11:47:09.647303 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5627 11:47:09.653882 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5628 11:47:09.657098 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5629 11:47:09.660516 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5630 11:47:09.663759 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5631 11:47:09.667155 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5632 11:47:09.673690 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5633 11:47:09.673776 ==
5634 11:47:09.676953 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:47:09.680299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:47:09.680375 ==
5637 11:47:09.680437 DQS Delay:
5638 11:47:09.683480 DQS0 = 0, DQS1 = 0
5639 11:47:09.683580 DQM Delay:
5640 11:47:09.686877 DQM0 = 103, DQM1 = 98
5641 11:47:09.686953 DQ Delay:
5642 11:47:09.690035 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5643 11:47:09.693316 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5644 11:47:09.696581 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5645 11:47:09.700392 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5646 11:47:09.700493
5647 11:47:09.700593
5648 11:47:09.700681 ==
5649 11:47:09.703371 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 11:47:09.710278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 11:47:09.710384 ==
5652 11:47:09.710478
5653 11:47:09.710575
5654 11:47:09.710652 TX Vref Scan disable
5655 11:47:09.713337 == TX Byte 0 ==
5656 11:47:09.716788 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5657 11:47:09.723535 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5658 11:47:09.723649 == TX Byte 1 ==
5659 11:47:09.726654 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5660 11:47:09.729787 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5661 11:47:09.733370 ==
5662 11:47:09.736848 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 11:47:09.740059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 11:47:09.740169 ==
5665 11:47:09.740269
5666 11:47:09.740372
5667 11:47:09.743269 TX Vref Scan disable
5668 11:47:09.743450 == TX Byte 0 ==
5669 11:47:09.749808 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5670 11:47:09.753146 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5671 11:47:09.753242 == TX Byte 1 ==
5672 11:47:09.759957 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5673 11:47:09.763008 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5674 11:47:09.763080
5675 11:47:09.763152 [DATLAT]
5676 11:47:09.766345 Freq=933, CH1 RK0
5677 11:47:09.766447
5678 11:47:09.766535 DATLAT Default: 0xd
5679 11:47:09.769537 0, 0xFFFF, sum = 0
5680 11:47:09.769644 1, 0xFFFF, sum = 0
5681 11:47:09.773610 2, 0xFFFF, sum = 0
5682 11:47:09.773721 3, 0xFFFF, sum = 0
5683 11:47:09.776294 4, 0xFFFF, sum = 0
5684 11:47:09.776395 5, 0xFFFF, sum = 0
5685 11:47:09.780190 6, 0xFFFF, sum = 0
5686 11:47:09.783580 7, 0xFFFF, sum = 0
5687 11:47:09.783691 8, 0xFFFF, sum = 0
5688 11:47:09.786190 9, 0xFFFF, sum = 0
5689 11:47:09.786259 10, 0x0, sum = 1
5690 11:47:09.786320 11, 0x0, sum = 2
5691 11:47:09.789546 12, 0x0, sum = 3
5692 11:47:09.789649 13, 0x0, sum = 4
5693 11:47:09.792876 best_step = 11
5694 11:47:09.792969
5695 11:47:09.793056 ==
5696 11:47:09.796315 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:47:09.799704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:47:09.799811 ==
5699 11:47:09.802856 RX Vref Scan: 1
5700 11:47:09.802996
5701 11:47:09.803094 RX Vref 0 -> 0, step: 1
5702 11:47:09.806164
5703 11:47:09.806295 RX Delay -45 -> 252, step: 4
5704 11:47:09.806420
5705 11:47:09.809500 Set Vref, RX VrefLevel [Byte0]: 55
5706 11:47:09.812849 [Byte1]: 48
5707 11:47:09.817469
5708 11:47:09.817567 Final RX Vref Byte 0 = 55 to rank0
5709 11:47:09.820647 Final RX Vref Byte 1 = 48 to rank0
5710 11:47:09.823835 Final RX Vref Byte 0 = 55 to rank1
5711 11:47:09.827321 Final RX Vref Byte 1 = 48 to rank1==
5712 11:47:09.830134 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:47:09.836918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:47:09.837032 ==
5715 11:47:09.837133 DQS Delay:
5716 11:47:09.837237 DQS0 = 0, DQS1 = 0
5717 11:47:09.840625 DQM Delay:
5718 11:47:09.840730 DQM0 = 103, DQM1 = 98
5719 11:47:09.843612 DQ Delay:
5720 11:47:09.847244 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5721 11:47:09.850383 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5722 11:47:09.853621 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5723 11:47:09.856801 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =108
5724 11:47:09.856915
5725 11:47:09.857011
5726 11:47:09.863679 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5727 11:47:09.866761 CH1 RK0: MR19=505, MR18=162D
5728 11:47:09.873788 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5729 11:47:09.873868
5730 11:47:09.876583 ----->DramcWriteLeveling(PI) begin...
5731 11:47:09.876681 ==
5732 11:47:09.880391 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 11:47:09.883589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 11:47:09.883667 ==
5735 11:47:09.886650 Write leveling (Byte 0): 28 => 28
5736 11:47:09.890560 Write leveling (Byte 1): 28 => 28
5737 11:47:09.893669 DramcWriteLeveling(PI) end<-----
5738 11:47:09.893786
5739 11:47:09.893878 ==
5740 11:47:09.896829 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 11:47:09.900111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 11:47:09.903954 ==
5743 11:47:09.904038 [Gating] SW mode calibration
5744 11:47:09.913842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 11:47:09.917046 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 11:47:09.920354 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 11:47:09.926796 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:47:09.930186 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:47:09.933190 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:47:09.939882 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:47:09.943519 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:47:09.946545 0 14 24 | B1->B0 | 2e2e 3232 | 1 1 | (1 1) (1 1)
5753 11:47:09.953039 0 14 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5754 11:47:09.956912 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 11:47:09.959641 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:47:09.966841 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:47:09.969968 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:47:09.973242 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:47:09.980336 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:47:09.983414 0 15 24 | B1->B0 | 3737 2d2c | 0 1 | (1 1) (0 0)
5761 11:47:09.986579 0 15 28 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
5762 11:47:09.993209 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 11:47:09.996503 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:47:09.999577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:47:10.006243 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:47:10.009972 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:47:10.013347 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:47:10.019828 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 11:47:10.023186 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 11:47:10.026504 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 11:47:10.033115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:47:10.036410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:47:10.040275 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:47:10.043405 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:47:10.049964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:47:10.053047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:47:10.056546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:47:10.063140 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:47:10.066374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:47:10.069516 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:47:10.076602 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:47:10.079674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:47:10.083227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:47:10.089663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 11:47:10.093003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5786 11:47:10.096614 Total UI for P1: 0, mck2ui 16
5787 11:47:10.099977 best dqsien dly found for B1: ( 1, 2, 24)
5788 11:47:10.103066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 11:47:10.106176 Total UI for P1: 0, mck2ui 16
5790 11:47:10.109597 best dqsien dly found for B0: ( 1, 2, 26)
5791 11:47:10.113325 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5792 11:47:10.116288 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5793 11:47:10.116365
5794 11:47:10.122895 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5795 11:47:10.126180 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5796 11:47:10.126258 [Gating] SW calibration Done
5797 11:47:10.129597 ==
5798 11:47:10.132866 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 11:47:10.136146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:47:10.136229 ==
5801 11:47:10.136311 RX Vref Scan: 0
5802 11:47:10.136400
5803 11:47:10.139382 RX Vref 0 -> 0, step: 1
5804 11:47:10.139464
5805 11:47:10.142568 RX Delay -80 -> 252, step: 8
5806 11:47:10.146434 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5807 11:47:10.149644 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5808 11:47:10.152835 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5809 11:47:10.159450 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5810 11:47:10.162985 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5811 11:47:10.165900 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5812 11:47:10.169519 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5813 11:47:10.172724 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5814 11:47:10.176051 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5815 11:47:10.182689 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5816 11:47:10.185937 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5817 11:47:10.189176 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5818 11:47:10.192757 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5819 11:47:10.195766 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5820 11:47:10.202513 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5821 11:47:10.206010 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5822 11:47:10.206097 ==
5823 11:47:10.209294 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 11:47:10.212497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 11:47:10.212591 ==
5826 11:47:10.216224 DQS Delay:
5827 11:47:10.216303 DQS0 = 0, DQS1 = 0
5828 11:47:10.216368 DQM Delay:
5829 11:47:10.219460 DQM0 = 104, DQM1 = 98
5830 11:47:10.219538 DQ Delay:
5831 11:47:10.222507 DQ0 =111, DQ1 =103, DQ2 =91, DQ3 =103
5832 11:47:10.225780 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =103
5833 11:47:10.229593 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5834 11:47:10.233079 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5835 11:47:10.233160
5836 11:47:10.233227
5837 11:47:10.236083 ==
5838 11:47:10.239354 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 11:47:10.242646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 11:47:10.242736 ==
5841 11:47:10.242801
5842 11:47:10.242863
5843 11:47:10.245795 TX Vref Scan disable
5844 11:47:10.245872 == TX Byte 0 ==
5845 11:47:10.249097 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5846 11:47:10.256277 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5847 11:47:10.256362 == TX Byte 1 ==
5848 11:47:10.259539 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5849 11:47:10.266284 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5850 11:47:10.266368 ==
5851 11:47:10.269418 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 11:47:10.273092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 11:47:10.273174 ==
5854 11:47:10.273239
5855 11:47:10.273298
5856 11:47:10.276049 TX Vref Scan disable
5857 11:47:10.279557 == TX Byte 0 ==
5858 11:47:10.283387 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5859 11:47:10.286610 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5860 11:47:10.289844 == TX Byte 1 ==
5861 11:47:10.292591 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5862 11:47:10.295936 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5863 11:47:10.296018
5864 11:47:10.296081 [DATLAT]
5865 11:47:10.299732 Freq=933, CH1 RK1
5866 11:47:10.299814
5867 11:47:10.302733 DATLAT Default: 0xb
5868 11:47:10.302825 0, 0xFFFF, sum = 0
5869 11:47:10.306327 1, 0xFFFF, sum = 0
5870 11:47:10.306408 2, 0xFFFF, sum = 0
5871 11:47:10.309315 3, 0xFFFF, sum = 0
5872 11:47:10.309391 4, 0xFFFF, sum = 0
5873 11:47:10.312612 5, 0xFFFF, sum = 0
5874 11:47:10.312695 6, 0xFFFF, sum = 0
5875 11:47:10.316156 7, 0xFFFF, sum = 0
5876 11:47:10.316234 8, 0xFFFF, sum = 0
5877 11:47:10.319603 9, 0xFFFF, sum = 0
5878 11:47:10.319687 10, 0x0, sum = 1
5879 11:47:10.323188 11, 0x0, sum = 2
5880 11:47:10.323318 12, 0x0, sum = 3
5881 11:47:10.326382 13, 0x0, sum = 4
5882 11:47:10.326458 best_step = 11
5883 11:47:10.326527
5884 11:47:10.326592 ==
5885 11:47:10.329219 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 11:47:10.332543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 11:47:10.332625 ==
5888 11:47:10.336256 RX Vref Scan: 0
5889 11:47:10.336340
5890 11:47:10.339415 RX Vref 0 -> 0, step: 1
5891 11:47:10.339496
5892 11:47:10.339569 RX Delay -53 -> 252, step: 4
5893 11:47:10.347075 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5894 11:47:10.350426 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5895 11:47:10.353486 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5896 11:47:10.356716 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5897 11:47:10.360651 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5898 11:47:10.367471 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5899 11:47:10.370167 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5900 11:47:10.373505 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5901 11:47:10.376773 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5902 11:47:10.380538 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5903 11:47:10.386593 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5904 11:47:10.390137 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5905 11:47:10.393327 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5906 11:47:10.397363 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5907 11:47:10.400556 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5908 11:47:10.407177 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5909 11:47:10.407254 ==
5910 11:47:10.410304 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 11:47:10.413339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 11:47:10.413417 ==
5913 11:47:10.413480 DQS Delay:
5914 11:47:10.416592 DQS0 = 0, DQS1 = 0
5915 11:47:10.416667 DQM Delay:
5916 11:47:10.419837 DQM0 = 105, DQM1 = 99
5917 11:47:10.419915 DQ Delay:
5918 11:47:10.423676 DQ0 =108, DQ1 =102, DQ2 =94, DQ3 =100
5919 11:47:10.426646 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5920 11:47:10.430222 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5921 11:47:10.433757 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5922 11:47:10.433832
5923 11:47:10.433894
5924 11:47:10.443137 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5925 11:47:10.446747 CH1 RK1: MR19=505, MR18=2D00
5926 11:47:10.449912 CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43
5927 11:47:10.453175 [RxdqsGatingPostProcess] freq 933
5928 11:47:10.460175 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5929 11:47:10.463184 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 11:47:10.467083 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 11:47:10.470232 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 11:47:10.473566 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 11:47:10.476845 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 11:47:10.480150 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 11:47:10.483296 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 11:47:10.486561 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 11:47:10.486630 Pre-setting of DQS Precalculation
5938 11:47:10.493503 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5939 11:47:10.500122 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5940 11:47:10.506374 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5941 11:47:10.506458
5942 11:47:10.506555
5943 11:47:10.509588 [Calibration Summary] 1866 Mbps
5944 11:47:10.513523 CH 0, Rank 0
5945 11:47:10.513622 SW Impedance : PASS
5946 11:47:10.516564 DUTY Scan : NO K
5947 11:47:10.520333 ZQ Calibration : PASS
5948 11:47:10.520413 Jitter Meter : NO K
5949 11:47:10.523566 CBT Training : PASS
5950 11:47:10.523739 Write leveling : PASS
5951 11:47:10.526734 RX DQS gating : PASS
5952 11:47:10.530052 RX DQ/DQS(RDDQC) : PASS
5953 11:47:10.530132 TX DQ/DQS : PASS
5954 11:47:10.533145 RX DATLAT : PASS
5955 11:47:10.536987 RX DQ/DQS(Engine): PASS
5956 11:47:10.537090 TX OE : NO K
5957 11:47:10.540079 All Pass.
5958 11:47:10.540158
5959 11:47:10.540232 CH 0, Rank 1
5960 11:47:10.543262 SW Impedance : PASS
5961 11:47:10.543342 DUTY Scan : NO K
5962 11:47:10.546853 ZQ Calibration : PASS
5963 11:47:10.550039 Jitter Meter : NO K
5964 11:47:10.550132 CBT Training : PASS
5965 11:47:10.553712 Write leveling : PASS
5966 11:47:10.556537 RX DQS gating : PASS
5967 11:47:10.556657 RX DQ/DQS(RDDQC) : PASS
5968 11:47:10.560206 TX DQ/DQS : PASS
5969 11:47:10.563543 RX DATLAT : PASS
5970 11:47:10.563653 RX DQ/DQS(Engine): PASS
5971 11:47:10.566792 TX OE : NO K
5972 11:47:10.566914 All Pass.
5973 11:47:10.567019
5974 11:47:10.567105 CH 1, Rank 0
5975 11:47:10.570445 SW Impedance : PASS
5976 11:47:10.573197 DUTY Scan : NO K
5977 11:47:10.573293 ZQ Calibration : PASS
5978 11:47:10.576570 Jitter Meter : NO K
5979 11:47:10.580209 CBT Training : PASS
5980 11:47:10.580284 Write leveling : PASS
5981 11:47:10.583560 RX DQS gating : PASS
5982 11:47:10.586874 RX DQ/DQS(RDDQC) : PASS
5983 11:47:10.586959 TX DQ/DQS : PASS
5984 11:47:10.589938 RX DATLAT : PASS
5985 11:47:10.593260 RX DQ/DQS(Engine): PASS
5986 11:47:10.593348 TX OE : NO K
5987 11:47:10.596956 All Pass.
5988 11:47:10.597076
5989 11:47:10.597163 CH 1, Rank 1
5990 11:47:10.600154 SW Impedance : PASS
5991 11:47:10.600273 DUTY Scan : NO K
5992 11:47:10.603459 ZQ Calibration : PASS
5993 11:47:10.607127 Jitter Meter : NO K
5994 11:47:10.607246 CBT Training : PASS
5995 11:47:10.610249 Write leveling : PASS
5996 11:47:10.610342 RX DQS gating : PASS
5997 11:47:10.613361 RX DQ/DQS(RDDQC) : PASS
5998 11:47:10.616820 TX DQ/DQS : PASS
5999 11:47:10.616941 RX DATLAT : PASS
6000 11:47:10.619850 RX DQ/DQS(Engine): PASS
6001 11:47:10.623567 TX OE : NO K
6002 11:47:10.623715 All Pass.
6003 11:47:10.623803
6004 11:47:10.626930 DramC Write-DBI off
6005 11:47:10.627020 PER_BANK_REFRESH: Hybrid Mode
6006 11:47:10.630034 TX_TRACKING: ON
6007 11:47:10.636569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6008 11:47:10.643840 [FAST_K] Save calibration result to emmc
6009 11:47:10.646977 dramc_set_vcore_voltage set vcore to 650000
6010 11:47:10.647082 Read voltage for 400, 6
6011 11:47:10.650069 Vio18 = 0
6012 11:47:10.650171 Vcore = 650000
6013 11:47:10.650243 Vdram = 0
6014 11:47:10.653203 Vddq = 0
6015 11:47:10.653283 Vmddr = 0
6016 11:47:10.656553 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6017 11:47:10.663395 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6018 11:47:10.666929 MEM_TYPE=3, freq_sel=20
6019 11:47:10.670025 sv_algorithm_assistance_LP4_800
6020 11:47:10.673258 ============ PULL DRAM RESETB DOWN ============
6021 11:47:10.676523 ========== PULL DRAM RESETB DOWN end =========
6022 11:47:10.680313 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6023 11:47:10.683579 ===================================
6024 11:47:10.686405 LPDDR4 DRAM CONFIGURATION
6025 11:47:10.690088 ===================================
6026 11:47:10.693110 EX_ROW_EN[0] = 0x0
6027 11:47:10.693243 EX_ROW_EN[1] = 0x0
6028 11:47:10.696792 LP4Y_EN = 0x0
6029 11:47:10.696884 WORK_FSP = 0x0
6030 11:47:10.700042 WL = 0x2
6031 11:47:10.700122 RL = 0x2
6032 11:47:10.703454 BL = 0x2
6033 11:47:10.703556 RPST = 0x0
6034 11:47:10.706777 RD_PRE = 0x0
6035 11:47:10.706851 WR_PRE = 0x1
6036 11:47:10.709740 WR_PST = 0x0
6037 11:47:10.709819 DBI_WR = 0x0
6038 11:47:10.713037 DBI_RD = 0x0
6039 11:47:10.716312 OTF = 0x1
6040 11:47:10.720084 ===================================
6041 11:47:10.720170 ===================================
6042 11:47:10.723419 ANA top config
6043 11:47:10.726672 ===================================
6044 11:47:10.729966 DLL_ASYNC_EN = 0
6045 11:47:10.730046 ALL_SLAVE_EN = 1
6046 11:47:10.733222 NEW_RANK_MODE = 1
6047 11:47:10.736454 DLL_IDLE_MODE = 1
6048 11:47:10.739826 LP45_APHY_COMB_EN = 1
6049 11:47:10.743470 TX_ODT_DIS = 1
6050 11:47:10.743593 NEW_8X_MODE = 1
6051 11:47:10.746654 ===================================
6052 11:47:10.749864 ===================================
6053 11:47:10.753125 data_rate = 800
6054 11:47:10.756231 CKR = 1
6055 11:47:10.759886 DQ_P2S_RATIO = 4
6056 11:47:10.763162 ===================================
6057 11:47:10.766302 CA_P2S_RATIO = 4
6058 11:47:10.769537 DQ_CA_OPEN = 0
6059 11:47:10.769651 DQ_SEMI_OPEN = 1
6060 11:47:10.773383 CA_SEMI_OPEN = 1
6061 11:47:10.776400 CA_FULL_RATE = 0
6062 11:47:10.779915 DQ_CKDIV4_EN = 0
6063 11:47:10.783007 CA_CKDIV4_EN = 1
6064 11:47:10.786181 CA_PREDIV_EN = 0
6065 11:47:10.786276 PH8_DLY = 0
6066 11:47:10.790076 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6067 11:47:10.793355 DQ_AAMCK_DIV = 0
6068 11:47:10.796400 CA_AAMCK_DIV = 0
6069 11:47:10.799603 CA_ADMCK_DIV = 4
6070 11:47:10.799690 DQ_TRACK_CA_EN = 0
6071 11:47:10.803110 CA_PICK = 800
6072 11:47:10.806639 CA_MCKIO = 400
6073 11:47:10.809565 MCKIO_SEMI = 400
6074 11:47:10.813132 PLL_FREQ = 3016
6075 11:47:10.816247 DQ_UI_PI_RATIO = 32
6076 11:47:10.819527 CA_UI_PI_RATIO = 32
6077 11:47:10.823185 ===================================
6078 11:47:10.826288 ===================================
6079 11:47:10.826372 memory_type:LPDDR4
6080 11:47:10.829632 GP_NUM : 10
6081 11:47:10.832692 SRAM_EN : 1
6082 11:47:10.832772 MD32_EN : 0
6083 11:47:10.836177 ===================================
6084 11:47:10.839253 [ANA_INIT] >>>>>>>>>>>>>>
6085 11:47:10.843067 <<<<<< [CONFIGURE PHASE]: ANA_TX
6086 11:47:10.846256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6087 11:47:10.849534 ===================================
6088 11:47:10.852820 data_rate = 800,PCW = 0X7400
6089 11:47:10.856047 ===================================
6090 11:47:10.859920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6091 11:47:10.863052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 11:47:10.876502 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 11:47:10.879750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6094 11:47:10.882513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6095 11:47:10.886111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6096 11:47:10.889443 [ANA_INIT] flow start
6097 11:47:10.892914 [ANA_INIT] PLL >>>>>>>>
6098 11:47:10.893019 [ANA_INIT] PLL <<<<<<<<
6099 11:47:10.896107 [ANA_INIT] MIDPI >>>>>>>>
6100 11:47:10.899230 [ANA_INIT] MIDPI <<<<<<<<
6101 11:47:10.899314 [ANA_INIT] DLL >>>>>>>>
6102 11:47:10.902507 [ANA_INIT] flow end
6103 11:47:10.906338 ============ LP4 DIFF to SE enter ============
6104 11:47:10.909481 ============ LP4 DIFF to SE exit ============
6105 11:47:10.912344 [ANA_INIT] <<<<<<<<<<<<<
6106 11:47:10.916219 [Flow] Enable top DCM control >>>>>
6107 11:47:10.919319 [Flow] Enable top DCM control <<<<<
6108 11:47:10.922329 Enable DLL master slave shuffle
6109 11:47:10.929073 ==============================================================
6110 11:47:10.929159 Gating Mode config
6111 11:47:10.935886 ==============================================================
6112 11:47:10.935970 Config description:
6113 11:47:10.945993 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6114 11:47:10.952135 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6115 11:47:10.959138 SELPH_MODE 0: By rank 1: By Phase
6116 11:47:10.962248 ==============================================================
6117 11:47:10.965497 GAT_TRACK_EN = 0
6118 11:47:10.969244 RX_GATING_MODE = 2
6119 11:47:10.972238 RX_GATING_TRACK_MODE = 2
6120 11:47:10.975381 SELPH_MODE = 1
6121 11:47:10.978680 PICG_EARLY_EN = 1
6122 11:47:10.982412 VALID_LAT_VALUE = 1
6123 11:47:10.989245 ==============================================================
6124 11:47:10.992549 Enter into Gating configuration >>>>
6125 11:47:10.995687 Exit from Gating configuration <<<<
6126 11:47:10.998770 Enter into DVFS_PRE_config >>>>>
6127 11:47:11.008785 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6128 11:47:11.012406 Exit from DVFS_PRE_config <<<<<
6129 11:47:11.015574 Enter into PICG configuration >>>>
6130 11:47:11.019277 Exit from PICG configuration <<<<
6131 11:47:11.019387 [RX_INPUT] configuration >>>>>
6132 11:47:11.022169 [RX_INPUT] configuration <<<<<
6133 11:47:11.029564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6134 11:47:11.035669 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6135 11:47:11.039055 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 11:47:11.045658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 11:47:11.051801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 11:47:11.058673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 11:47:11.062321 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6140 11:47:11.065665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6141 11:47:11.072146 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6142 11:47:11.075353 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6143 11:47:11.078519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6144 11:47:11.085289 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6145 11:47:11.085400 ===================================
6146 11:47:11.088630 LPDDR4 DRAM CONFIGURATION
6147 11:47:11.091799 ===================================
6148 11:47:11.095163 EX_ROW_EN[0] = 0x0
6149 11:47:11.095241 EX_ROW_EN[1] = 0x0
6150 11:47:11.098428 LP4Y_EN = 0x0
6151 11:47:11.098531 WORK_FSP = 0x0
6152 11:47:11.101780 WL = 0x2
6153 11:47:11.101868 RL = 0x2
6154 11:47:11.104944 BL = 0x2
6155 11:47:11.105051 RPST = 0x0
6156 11:47:11.108686 RD_PRE = 0x0
6157 11:47:11.111798 WR_PRE = 0x1
6158 11:47:11.111874 WR_PST = 0x0
6159 11:47:11.115353 DBI_WR = 0x0
6160 11:47:11.115425 DBI_RD = 0x0
6161 11:47:11.118279 OTF = 0x1
6162 11:47:11.121815 ===================================
6163 11:47:11.125072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6164 11:47:11.128728 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6165 11:47:11.131721 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 11:47:11.134883 ===================================
6167 11:47:11.138695 LPDDR4 DRAM CONFIGURATION
6168 11:47:11.141867 ===================================
6169 11:47:11.144906 EX_ROW_EN[0] = 0x10
6170 11:47:11.144994 EX_ROW_EN[1] = 0x0
6171 11:47:11.148055 LP4Y_EN = 0x0
6172 11:47:11.148157 WORK_FSP = 0x0
6173 11:47:11.151376 WL = 0x2
6174 11:47:11.151451 RL = 0x2
6175 11:47:11.155091 BL = 0x2
6176 11:47:11.155199 RPST = 0x0
6177 11:47:11.158211 RD_PRE = 0x0
6178 11:47:11.158297 WR_PRE = 0x1
6179 11:47:11.161373 WR_PST = 0x0
6180 11:47:11.164753 DBI_WR = 0x0
6181 11:47:11.164864 DBI_RD = 0x0
6182 11:47:11.168320 OTF = 0x1
6183 11:47:11.171371 ===================================
6184 11:47:11.174552 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6185 11:47:11.179818 nWR fixed to 30
6186 11:47:11.183038 [ModeRegInit_LP4] CH0 RK0
6187 11:47:11.183112 [ModeRegInit_LP4] CH0 RK1
6188 11:47:11.186711 [ModeRegInit_LP4] CH1 RK0
6189 11:47:11.189736 [ModeRegInit_LP4] CH1 RK1
6190 11:47:11.189808 match AC timing 19
6191 11:47:11.196160 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6192 11:47:11.200064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6193 11:47:11.203275 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6194 11:47:11.209805 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6195 11:47:11.213056 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6196 11:47:11.213155 ==
6197 11:47:11.216341 Dram Type= 6, Freq= 0, CH_0, rank 0
6198 11:47:11.220039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6199 11:47:11.220114 ==
6200 11:47:11.226515 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6201 11:47:11.233106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6202 11:47:11.236469 [CA 0] Center 36 (8~64) winsize 57
6203 11:47:11.239609 [CA 1] Center 36 (8~64) winsize 57
6204 11:47:11.243252 [CA 2] Center 36 (8~64) winsize 57
6205 11:47:11.246501 [CA 3] Center 36 (8~64) winsize 57
6206 11:47:11.246574 [CA 4] Center 36 (8~64) winsize 57
6207 11:47:11.249445 [CA 5] Center 36 (8~64) winsize 57
6208 11:47:11.249540
6209 11:47:11.256623 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6210 11:47:11.256729
6211 11:47:11.259866 [CATrainingPosCal] consider 1 rank data
6212 11:47:11.263116 u2DelayCellTimex100 = 270/100 ps
6213 11:47:11.266347 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:47:11.269628 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:47:11.273468 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:47:11.276512 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:47:11.279751 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:47:11.283242 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 11:47:11.283322
6220 11:47:11.286310 CA PerBit enable=1, Macro0, CA PI delay=36
6221 11:47:11.286390
6222 11:47:11.289935 [CBTSetCACLKResult] CA Dly = 36
6223 11:47:11.293195 CS Dly: 1 (0~32)
6224 11:47:11.293288 ==
6225 11:47:11.296249 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 11:47:11.299839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 11:47:11.299924 ==
6228 11:47:11.306258 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 11:47:11.309554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 11:47:11.312878 [CA 0] Center 36 (8~64) winsize 57
6231 11:47:11.316082 [CA 1] Center 36 (8~64) winsize 57
6232 11:47:11.320023 [CA 2] Center 36 (8~64) winsize 57
6233 11:47:11.323276 [CA 3] Center 36 (8~64) winsize 57
6234 11:47:11.326463 [CA 4] Center 36 (8~64) winsize 57
6235 11:47:11.329782 [CA 5] Center 36 (8~64) winsize 57
6236 11:47:11.329853
6237 11:47:11.332869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 11:47:11.332948
6239 11:47:11.336660 [CATrainingPosCal] consider 2 rank data
6240 11:47:11.339634 u2DelayCellTimex100 = 270/100 ps
6241 11:47:11.343215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:47:11.346183 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:47:11.349769 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:47:11.356215 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:47:11.359728 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:47:11.362713 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:47:11.362813
6248 11:47:11.366219 CA PerBit enable=1, Macro0, CA PI delay=36
6249 11:47:11.366301
6250 11:47:11.369305 [CBTSetCACLKResult] CA Dly = 36
6251 11:47:11.369400 CS Dly: 1 (0~32)
6252 11:47:11.369487
6253 11:47:11.372638 ----->DramcWriteLeveling(PI) begin...
6254 11:47:11.372734 ==
6255 11:47:11.376519 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 11:47:11.382892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 11:47:11.382983 ==
6258 11:47:11.386098 Write leveling (Byte 0): 40 => 8
6259 11:47:11.386194 Write leveling (Byte 1): 40 => 8
6260 11:47:11.389393 DramcWriteLeveling(PI) end<-----
6261 11:47:11.389485
6262 11:47:11.393199 ==
6263 11:47:11.393300 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 11:47:11.399963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 11:47:11.400069 ==
6266 11:47:11.402932 [Gating] SW mode calibration
6267 11:47:11.409460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6268 11:47:11.412643 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6269 11:47:11.419195 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 11:47:11.423140 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 11:47:11.426373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 11:47:11.432785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 11:47:11.436068 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 11:47:11.439235 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:47:11.446134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:47:11.449128 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 11:47:11.452607 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 11:47:11.455829 Total UI for P1: 0, mck2ui 16
6279 11:47:11.459179 best dqsien dly found for B0: ( 0, 14, 24)
6280 11:47:11.462379 Total UI for P1: 0, mck2ui 16
6281 11:47:11.465613 best dqsien dly found for B1: ( 0, 14, 24)
6282 11:47:11.469286 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6283 11:47:11.472262 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6284 11:47:11.472341
6285 11:47:11.475867 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 11:47:11.483033 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 11:47:11.483113 [Gating] SW calibration Done
6288 11:47:11.483197 ==
6289 11:47:11.486164 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 11:47:11.493043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 11:47:11.493123 ==
6292 11:47:11.493187 RX Vref Scan: 0
6293 11:47:11.493245
6294 11:47:11.496393 RX Vref 0 -> 0, step: 1
6295 11:47:11.496471
6296 11:47:11.499683 RX Delay -410 -> 252, step: 16
6297 11:47:11.502883 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6298 11:47:11.506127 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6299 11:47:11.512652 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6300 11:47:11.516206 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6301 11:47:11.519636 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6302 11:47:11.522932 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6303 11:47:11.529397 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6304 11:47:11.532517 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6305 11:47:11.536395 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6306 11:47:11.539668 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6307 11:47:11.542948 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6308 11:47:11.549545 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6309 11:47:11.552574 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6310 11:47:11.556249 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6311 11:47:11.562646 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6312 11:47:11.566148 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6313 11:47:11.566221 ==
6314 11:47:11.569103 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 11:47:11.572618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:47:11.572713 ==
6317 11:47:11.575905 DQS Delay:
6318 11:47:11.575999 DQS0 = 27, DQS1 = 35
6319 11:47:11.576093 DQM Delay:
6320 11:47:11.578993 DQM0 = 10, DQM1 = 12
6321 11:47:11.579092 DQ Delay:
6322 11:47:11.582366 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6323 11:47:11.586066 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6324 11:47:11.589181 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6325 11:47:11.592843 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6326 11:47:11.592915
6327 11:47:11.592975
6328 11:47:11.593031 ==
6329 11:47:11.595893 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:47:11.599514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:47:11.599593 ==
6332 11:47:11.602679
6333 11:47:11.602764
6334 11:47:11.602826 TX Vref Scan disable
6335 11:47:11.605951 == TX Byte 0 ==
6336 11:47:11.609177 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 11:47:11.612681 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 11:47:11.615957 == TX Byte 1 ==
6339 11:47:11.619273 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 11:47:11.622482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 11:47:11.622558 ==
6342 11:47:11.625788 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 11:47:11.629417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 11:47:11.629543 ==
6345 11:47:11.632635
6346 11:47:11.632708
6347 11:47:11.632774 TX Vref Scan disable
6348 11:47:11.636067 == TX Byte 0 ==
6349 11:47:11.639016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 11:47:11.642513 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 11:47:11.646151 == TX Byte 1 ==
6352 11:47:11.649292 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 11:47:11.652665 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 11:47:11.652743
6355 11:47:11.652803 [DATLAT]
6356 11:47:11.655762 Freq=400, CH0 RK0
6357 11:47:11.655841
6358 11:47:11.658840 DATLAT Default: 0xf
6359 11:47:11.658919 0, 0xFFFF, sum = 0
6360 11:47:11.661979 1, 0xFFFF, sum = 0
6361 11:47:11.662060 2, 0xFFFF, sum = 0
6362 11:47:11.665314 3, 0xFFFF, sum = 0
6363 11:47:11.665420 4, 0xFFFF, sum = 0
6364 11:47:11.668585 5, 0xFFFF, sum = 0
6365 11:47:11.668660 6, 0xFFFF, sum = 0
6366 11:47:11.672487 7, 0xFFFF, sum = 0
6367 11:47:11.672567 8, 0xFFFF, sum = 0
6368 11:47:11.675661 9, 0xFFFF, sum = 0
6369 11:47:11.675741 10, 0xFFFF, sum = 0
6370 11:47:11.678597 11, 0xFFFF, sum = 0
6371 11:47:11.678682 12, 0xFFFF, sum = 0
6372 11:47:11.682403 13, 0x0, sum = 1
6373 11:47:11.682487 14, 0x0, sum = 2
6374 11:47:11.685874 15, 0x0, sum = 3
6375 11:47:11.685953 16, 0x0, sum = 4
6376 11:47:11.689117 best_step = 14
6377 11:47:11.689197
6378 11:47:11.689258 ==
6379 11:47:11.692308 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 11:47:11.695397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 11:47:11.695475 ==
6382 11:47:11.698720 RX Vref Scan: 1
6383 11:47:11.698799
6384 11:47:11.698861 RX Vref 0 -> 0, step: 1
6385 11:47:11.698918
6386 11:47:11.701857 RX Delay -311 -> 252, step: 8
6387 11:47:11.701935
6388 11:47:11.705379 Set Vref, RX VrefLevel [Byte0]: 54
6389 11:47:11.708933 [Byte1]: 58
6390 11:47:11.713296
6391 11:47:11.713402 Final RX Vref Byte 0 = 54 to rank0
6392 11:47:11.716704 Final RX Vref Byte 1 = 58 to rank0
6393 11:47:11.720102 Final RX Vref Byte 0 = 54 to rank1
6394 11:47:11.723237 Final RX Vref Byte 1 = 58 to rank1==
6395 11:47:11.726640 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 11:47:11.733120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 11:47:11.733202 ==
6398 11:47:11.733265 DQS Delay:
6399 11:47:11.736468 DQS0 = 28, DQS1 = 36
6400 11:47:11.736592 DQM Delay:
6401 11:47:11.736696 DQM0 = 11, DQM1 = 14
6402 11:47:11.740137 DQ Delay:
6403 11:47:11.743435 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6404 11:47:11.743514 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6405 11:47:11.746631 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6406 11:47:11.749808 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6407 11:47:11.749887
6408 11:47:11.749950
6409 11:47:11.759668 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6410 11:47:11.763349 CH0 RK0: MR19=C0C, MR18=CCB8
6411 11:47:11.770010 CH0_RK0: MR19=0xC0C, MR18=0xCCB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6412 11:47:11.770092 ==
6413 11:47:11.773254 Dram Type= 6, Freq= 0, CH_0, rank 1
6414 11:47:11.776460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 11:47:11.776542 ==
6416 11:47:11.779648 [Gating] SW mode calibration
6417 11:47:11.786710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6418 11:47:11.792926 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6419 11:47:11.796024 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 11:47:11.799792 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 11:47:11.802945 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 11:47:11.809380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 11:47:11.812706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 11:47:11.815988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:47:11.822698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:47:11.826034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:47:11.829483 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 11:47:11.832741 Total UI for P1: 0, mck2ui 16
6429 11:47:11.836042 best dqsien dly found for B0: ( 0, 14, 24)
6430 11:47:11.839431 Total UI for P1: 0, mck2ui 16
6431 11:47:11.843106 best dqsien dly found for B1: ( 0, 14, 24)
6432 11:47:11.846424 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6433 11:47:11.853020 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6434 11:47:11.853100
6435 11:47:11.856152 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 11:47:11.859363 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 11:47:11.862632 [Gating] SW calibration Done
6438 11:47:11.862718 ==
6439 11:47:11.866192 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 11:47:11.869109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 11:47:11.869196 ==
6442 11:47:11.869260 RX Vref Scan: 0
6443 11:47:11.872878
6444 11:47:11.872957 RX Vref 0 -> 0, step: 1
6445 11:47:11.873020
6446 11:47:11.875893 RX Delay -410 -> 252, step: 16
6447 11:47:11.879140 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6448 11:47:11.886185 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6449 11:47:11.888885 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6450 11:47:11.892703 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6451 11:47:11.895734 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6452 11:47:11.902311 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6453 11:47:11.906087 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6454 11:47:11.909206 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6455 11:47:11.912089 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6456 11:47:11.919104 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6457 11:47:11.922601 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6458 11:47:11.925885 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6459 11:47:11.929003 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6460 11:47:11.935735 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6461 11:47:11.939176 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6462 11:47:11.942262 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6463 11:47:11.942367 ==
6464 11:47:11.945309 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 11:47:11.949110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 11:47:11.952344 ==
6467 11:47:11.952441 DQS Delay:
6468 11:47:11.952537 DQS0 = 27, DQS1 = 35
6469 11:47:11.955516 DQM Delay:
6470 11:47:11.955612 DQM0 = 18, DQM1 = 15
6471 11:47:11.958766 DQ Delay:
6472 11:47:11.961973 DQ0 =16, DQ1 =24, DQ2 =16, DQ3 =16
6473 11:47:11.962068 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6474 11:47:11.965722 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =0
6475 11:47:11.969029 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6476 11:47:11.969099
6477 11:47:11.969160
6478 11:47:11.972178 ==
6479 11:47:11.975843 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 11:47:11.978849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 11:47:11.978931 ==
6482 11:47:11.978994
6483 11:47:11.979053
6484 11:47:11.982244 TX Vref Scan disable
6485 11:47:11.982325 == TX Byte 0 ==
6486 11:47:11.985494 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6487 11:47:11.992229 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6488 11:47:11.992310 == TX Byte 1 ==
6489 11:47:11.995408 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6490 11:47:12.001759 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6491 11:47:12.001840 ==
6492 11:47:12.005446 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 11:47:12.008808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 11:47:12.008890 ==
6495 11:47:12.008954
6496 11:47:12.009013
6497 11:47:12.011851 TX Vref Scan disable
6498 11:47:12.011932 == TX Byte 0 ==
6499 11:47:12.015213 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6500 11:47:12.021973 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6501 11:47:12.022057 == TX Byte 1 ==
6502 11:47:12.025287 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6503 11:47:12.031660 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6504 11:47:12.031749
6505 11:47:12.031818 [DATLAT]
6506 11:47:12.031877 Freq=400, CH0 RK1
6507 11:47:12.031935
6508 11:47:12.034935 DATLAT Default: 0xe
6509 11:47:12.038081 0, 0xFFFF, sum = 0
6510 11:47:12.038163 1, 0xFFFF, sum = 0
6511 11:47:12.041444 2, 0xFFFF, sum = 0
6512 11:47:12.041551 3, 0xFFFF, sum = 0
6513 11:47:12.044771 4, 0xFFFF, sum = 0
6514 11:47:12.044851 5, 0xFFFF, sum = 0
6515 11:47:12.048552 6, 0xFFFF, sum = 0
6516 11:47:12.048657 7, 0xFFFF, sum = 0
6517 11:47:12.051504 8, 0xFFFF, sum = 0
6518 11:47:12.051585 9, 0xFFFF, sum = 0
6519 11:47:12.054754 10, 0xFFFF, sum = 0
6520 11:47:12.054835 11, 0xFFFF, sum = 0
6521 11:47:12.057978 12, 0xFFFF, sum = 0
6522 11:47:12.058060 13, 0x0, sum = 1
6523 11:47:12.061489 14, 0x0, sum = 2
6524 11:47:12.061623 15, 0x0, sum = 3
6525 11:47:12.064907 16, 0x0, sum = 4
6526 11:47:12.064986 best_step = 14
6527 11:47:12.065049
6528 11:47:12.065109 ==
6529 11:47:12.068105 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 11:47:12.071505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 11:47:12.074778 ==
6532 11:47:12.074877 RX Vref Scan: 0
6533 11:47:12.074970
6534 11:47:12.078082 RX Vref 0 -> 0, step: 1
6535 11:47:12.078162
6536 11:47:12.081296 RX Delay -311 -> 252, step: 8
6537 11:47:12.088412 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6538 11:47:12.091505 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6539 11:47:12.095022 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6540 11:47:12.097752 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6541 11:47:12.104809 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6542 11:47:12.107953 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6543 11:47:12.111340 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6544 11:47:12.114813 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6545 11:47:12.117817 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6546 11:47:12.124622 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6547 11:47:12.127590 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6548 11:47:12.131327 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6549 11:47:12.137906 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6550 11:47:12.141174 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6551 11:47:12.144481 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6552 11:47:12.147825 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6553 11:47:12.147932 ==
6554 11:47:12.151216 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 11:47:12.157902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 11:47:12.158035 ==
6557 11:47:12.158135 DQS Delay:
6558 11:47:12.161130 DQS0 = 24, DQS1 = 32
6559 11:47:12.161228 DQM Delay:
6560 11:47:12.164164 DQM0 = 8, DQM1 = 10
6561 11:47:12.164264 DQ Delay:
6562 11:47:12.167324 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6563 11:47:12.170816 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6564 11:47:12.170898 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6565 11:47:12.174154 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6566 11:47:12.177790
6567 11:47:12.177883
6568 11:47:12.184392 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6569 11:47:12.187651 CH0 RK1: MR19=C0C, MR18=BE5C
6570 11:47:12.194276 CH0_RK1: MR19=0xC0C, MR18=0xBE5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6571 11:47:12.197545 [RxdqsGatingPostProcess] freq 400
6572 11:47:12.200790 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6573 11:47:12.204016 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 11:47:12.207198 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 11:47:12.210793 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 11:47:12.214168 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 11:47:12.217176 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 11:47:12.221100 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 11:47:12.224355 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 11:47:12.227422 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 11:47:12.230876 Pre-setting of DQS Precalculation
6582 11:47:12.234450 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6583 11:47:12.234571 ==
6584 11:47:12.237186 Dram Type= 6, Freq= 0, CH_1, rank 0
6585 11:47:12.244075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 11:47:12.244176 ==
6587 11:47:12.247191 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6588 11:47:12.254394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6589 11:47:12.257529 [CA 0] Center 36 (8~64) winsize 57
6590 11:47:12.260790 [CA 1] Center 36 (8~64) winsize 57
6591 11:47:12.264034 [CA 2] Center 36 (8~64) winsize 57
6592 11:47:12.267504 [CA 3] Center 36 (8~64) winsize 57
6593 11:47:12.270579 [CA 4] Center 36 (8~64) winsize 57
6594 11:47:12.273826 [CA 5] Center 36 (8~64) winsize 57
6595 11:47:12.273899
6596 11:47:12.277643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6597 11:47:12.277711
6598 11:47:12.280575 [CATrainingPosCal] consider 1 rank data
6599 11:47:12.284117 u2DelayCellTimex100 = 270/100 ps
6600 11:47:12.287177 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:47:12.290885 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:47:12.293954 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:47:12.297144 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:47:12.300495 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:47:12.303916 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 11:47:12.304023
6607 11:47:12.310548 CA PerBit enable=1, Macro0, CA PI delay=36
6608 11:47:12.310634
6609 11:47:12.310699 [CBTSetCACLKResult] CA Dly = 36
6610 11:47:12.313716 CS Dly: 1 (0~32)
6611 11:47:12.313812 ==
6612 11:47:12.316913 Dram Type= 6, Freq= 0, CH_1, rank 1
6613 11:47:12.320780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 11:47:12.320883 ==
6615 11:47:12.327247 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 11:47:12.333846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6617 11:47:12.337111 [CA 0] Center 36 (8~64) winsize 57
6618 11:47:12.340965 [CA 1] Center 36 (8~64) winsize 57
6619 11:47:12.343975 [CA 2] Center 36 (8~64) winsize 57
6620 11:47:12.344055 [CA 3] Center 36 (8~64) winsize 57
6621 11:47:12.347015 [CA 4] Center 36 (8~64) winsize 57
6622 11:47:12.350747 [CA 5] Center 36 (8~64) winsize 57
6623 11:47:12.350847
6624 11:47:12.353933 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6625 11:47:12.357184
6626 11:47:12.360373 [CATrainingPosCal] consider 2 rank data
6627 11:47:12.360448 u2DelayCellTimex100 = 270/100 ps
6628 11:47:12.367152 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:47:12.370588 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:47:12.373715 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:47:12.377154 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:47:12.380339 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:47:12.383714 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:47:12.383808
6635 11:47:12.386764 CA PerBit enable=1, Macro0, CA PI delay=36
6636 11:47:12.386837
6637 11:47:12.390609 [CBTSetCACLKResult] CA Dly = 36
6638 11:47:12.393836 CS Dly: 1 (0~32)
6639 11:47:12.393921
6640 11:47:12.396818 ----->DramcWriteLeveling(PI) begin...
6641 11:47:12.396915 ==
6642 11:47:12.400471 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 11:47:12.403953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 11:47:12.404031 ==
6645 11:47:12.407208 Write leveling (Byte 0): 40 => 8
6646 11:47:12.410621 Write leveling (Byte 1): 40 => 8
6647 11:47:12.413765 DramcWriteLeveling(PI) end<-----
6648 11:47:12.413846
6649 11:47:12.413909 ==
6650 11:47:12.416941 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 11:47:12.420318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 11:47:12.420419 ==
6653 11:47:12.423534 [Gating] SW mode calibration
6654 11:47:12.430138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6655 11:47:12.436724 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6656 11:47:12.440277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:47:12.443162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 11:47:12.449934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 11:47:12.453722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 11:47:12.456795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:47:12.463367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:47:12.466657 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:47:12.470262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 11:47:12.477003 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 11:47:12.477131 Total UI for P1: 0, mck2ui 16
6666 11:47:12.480092 best dqsien dly found for B0: ( 0, 14, 24)
6667 11:47:12.483452 Total UI for P1: 0, mck2ui 16
6668 11:47:12.486828 best dqsien dly found for B1: ( 0, 14, 24)
6669 11:47:12.493347 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6670 11:47:12.496376 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6671 11:47:12.496478
6672 11:47:12.499904 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 11:47:12.503367 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 11:47:12.506541 [Gating] SW calibration Done
6675 11:47:12.506614 ==
6676 11:47:12.510235 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 11:47:12.513201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 11:47:12.513282 ==
6679 11:47:12.516817 RX Vref Scan: 0
6680 11:47:12.516921
6681 11:47:12.517038 RX Vref 0 -> 0, step: 1
6682 11:47:12.517137
6683 11:47:12.519986 RX Delay -410 -> 252, step: 16
6684 11:47:12.523122 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6685 11:47:12.529716 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6686 11:47:12.533172 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6687 11:47:12.536314 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6688 11:47:12.539745 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6689 11:47:12.546807 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6690 11:47:12.549839 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6691 11:47:12.553564 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6692 11:47:12.556521 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6693 11:47:12.563356 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6694 11:47:12.566689 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6695 11:47:12.569857 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6696 11:47:12.573194 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6697 11:47:12.579493 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6698 11:47:12.582775 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6699 11:47:12.586132 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6700 11:47:12.586212 ==
6701 11:47:12.589795 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 11:47:12.596279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:47:12.596359 ==
6704 11:47:12.596468 DQS Delay:
6705 11:47:12.599677 DQS0 = 35, DQS1 = 35
6706 11:47:12.599756 DQM Delay:
6707 11:47:12.599820 DQM0 = 20, DQM1 = 17
6708 11:47:12.602800 DQ Delay:
6709 11:47:12.606321 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6710 11:47:12.609961 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6711 11:47:12.610056 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6712 11:47:12.613104 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6713 11:47:12.616675
6714 11:47:12.616755
6715 11:47:12.616817 ==
6716 11:47:12.619602 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:47:12.622529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:47:12.622609 ==
6719 11:47:12.622672
6720 11:47:12.622729
6721 11:47:12.626131 TX Vref Scan disable
6722 11:47:12.626244 == TX Byte 0 ==
6723 11:47:12.629701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 11:47:12.636023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 11:47:12.636130 == TX Byte 1 ==
6726 11:47:12.639380 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 11:47:12.645760 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 11:47:12.645841 ==
6729 11:47:12.649544 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 11:47:12.652788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 11:47:12.652890 ==
6732 11:47:12.652988
6733 11:47:12.653065
6734 11:47:12.656083 TX Vref Scan disable
6735 11:47:12.656304 == TX Byte 0 ==
6736 11:47:12.662890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 11:47:12.665991 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 11:47:12.666074 == TX Byte 1 ==
6739 11:47:12.669101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 11:47:12.675585 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 11:47:12.675666
6742 11:47:12.675734 [DATLAT]
6743 11:47:12.678873 Freq=400, CH1 RK0
6744 11:47:12.678952
6745 11:47:12.679016 DATLAT Default: 0xf
6746 11:47:12.682665 0, 0xFFFF, sum = 0
6747 11:47:12.682746 1, 0xFFFF, sum = 0
6748 11:47:12.685999 2, 0xFFFF, sum = 0
6749 11:47:12.686080 3, 0xFFFF, sum = 0
6750 11:47:12.689256 4, 0xFFFF, sum = 0
6751 11:47:12.689363 5, 0xFFFF, sum = 0
6752 11:47:12.692564 6, 0xFFFF, sum = 0
6753 11:47:12.692671 7, 0xFFFF, sum = 0
6754 11:47:12.695490 8, 0xFFFF, sum = 0
6755 11:47:12.695604 9, 0xFFFF, sum = 0
6756 11:47:12.698804 10, 0xFFFF, sum = 0
6757 11:47:12.698884 11, 0xFFFF, sum = 0
6758 11:47:12.702567 12, 0xFFFF, sum = 0
6759 11:47:12.702648 13, 0x0, sum = 1
6760 11:47:12.705768 14, 0x0, sum = 2
6761 11:47:12.705848 15, 0x0, sum = 3
6762 11:47:12.709229 16, 0x0, sum = 4
6763 11:47:12.709310 best_step = 14
6764 11:47:12.709372
6765 11:47:12.709431 ==
6766 11:47:12.712317 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 11:47:12.719053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 11:47:12.719138 ==
6769 11:47:12.719207 RX Vref Scan: 1
6770 11:47:12.719266
6771 11:47:12.722451 RX Vref 0 -> 0, step: 1
6772 11:47:12.722530
6773 11:47:12.725688 RX Delay -311 -> 252, step: 8
6774 11:47:12.725768
6775 11:47:12.728814 Set Vref, RX VrefLevel [Byte0]: 55
6776 11:47:12.732027 [Byte1]: 48
6777 11:47:12.732137
6778 11:47:12.735647 Final RX Vref Byte 0 = 55 to rank0
6779 11:47:12.738813 Final RX Vref Byte 1 = 48 to rank0
6780 11:47:12.742014 Final RX Vref Byte 0 = 55 to rank1
6781 11:47:12.745555 Final RX Vref Byte 1 = 48 to rank1==
6782 11:47:12.748626 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 11:47:12.752244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 11:47:12.755633 ==
6785 11:47:12.755721 DQS Delay:
6786 11:47:12.755786 DQS0 = 28, DQS1 = 32
6787 11:47:12.759106 DQM Delay:
6788 11:47:12.759255 DQM0 = 9, DQM1 = 11
6789 11:47:12.762225 DQ Delay:
6790 11:47:12.762306 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6791 11:47:12.765560 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6792 11:47:12.768423 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6793 11:47:12.771670 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6794 11:47:12.771744
6795 11:47:12.771806
6796 11:47:12.782097 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6797 11:47:12.785180 CH1 RK0: MR19=C0C, MR18=94CD
6798 11:47:12.791993 CH1_RK0: MR19=0xC0C, MR18=0x94CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6799 11:47:12.792075 ==
6800 11:47:12.795261 Dram Type= 6, Freq= 0, CH_1, rank 1
6801 11:47:12.798438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 11:47:12.798544 ==
6803 11:47:12.801904 [Gating] SW mode calibration
6804 11:47:12.808621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6805 11:47:12.811856 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6806 11:47:12.817988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 11:47:12.821889 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 11:47:12.825226 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 11:47:12.831569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 11:47:12.834718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 11:47:12.838363 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:47:12.845055 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:47:12.848316 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 11:47:12.851576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 11:47:12.854739 Total UI for P1: 0, mck2ui 16
6816 11:47:12.857875 best dqsien dly found for B0: ( 0, 14, 24)
6817 11:47:12.861542 Total UI for P1: 0, mck2ui 16
6818 11:47:12.864519 best dqsien dly found for B1: ( 0, 14, 24)
6819 11:47:12.868030 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6820 11:47:12.871742 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6821 11:47:12.871851
6822 11:47:12.878187 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 11:47:12.881419 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 11:47:12.881502 [Gating] SW calibration Done
6825 11:47:12.885032 ==
6826 11:47:12.888274 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 11:47:12.891572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 11:47:12.891657 ==
6829 11:47:12.891722 RX Vref Scan: 0
6830 11:47:12.891783
6831 11:47:12.894955 RX Vref 0 -> 0, step: 1
6832 11:47:12.895038
6833 11:47:12.897676 RX Delay -410 -> 252, step: 16
6834 11:47:12.900943 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6835 11:47:12.907600 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6836 11:47:12.910924 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6837 11:47:12.914333 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6838 11:47:12.917535 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6839 11:47:12.920906 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6840 11:47:12.927836 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6841 11:47:12.931330 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6842 11:47:12.934539 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6843 11:47:12.937774 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6844 11:47:12.944326 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6845 11:47:12.948083 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6846 11:47:12.950925 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6847 11:47:12.957281 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6848 11:47:12.961274 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6849 11:47:12.963944 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6850 11:47:12.964028 ==
6851 11:47:12.967761 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 11:47:12.970849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 11:47:12.970935 ==
6854 11:47:12.974398 DQS Delay:
6855 11:47:12.974481 DQS0 = 27, DQS1 = 35
6856 11:47:12.977262 DQM Delay:
6857 11:47:12.977376 DQM0 = 11, DQM1 = 13
6858 11:47:12.980885 DQ Delay:
6859 11:47:12.980999 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6860 11:47:12.984285 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6861 11:47:12.987530 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6862 11:47:12.991050 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6863 11:47:12.991137
6864 11:47:12.991203
6865 11:47:12.991274 ==
6866 11:47:12.994028 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 11:47:13.000538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 11:47:13.000652 ==
6869 11:47:13.000745
6870 11:47:13.000841
6871 11:47:13.000909 TX Vref Scan disable
6872 11:47:13.004130 == TX Byte 0 ==
6873 11:47:13.007337 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6874 11:47:13.010525 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6875 11:47:13.013959 == TX Byte 1 ==
6876 11:47:13.017293 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6877 11:47:13.020464 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6878 11:47:13.020567 ==
6879 11:47:13.023845 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 11:47:13.030400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 11:47:13.030491 ==
6882 11:47:13.030558
6883 11:47:13.030619
6884 11:47:13.030677 TX Vref Scan disable
6885 11:47:13.034308 == TX Byte 0 ==
6886 11:47:13.036893 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6887 11:47:13.040913 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6888 11:47:13.043519 == TX Byte 1 ==
6889 11:47:13.047128 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6890 11:47:13.050278 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6891 11:47:13.050370
6892 11:47:13.053912 [DATLAT]
6893 11:47:13.054002 Freq=400, CH1 RK1
6894 11:47:13.054091
6895 11:47:13.056826 DATLAT Default: 0xe
6896 11:47:13.056910 0, 0xFFFF, sum = 0
6897 11:47:13.060446 1, 0xFFFF, sum = 0
6898 11:47:13.060530 2, 0xFFFF, sum = 0
6899 11:47:13.063460 3, 0xFFFF, sum = 0
6900 11:47:13.063549 4, 0xFFFF, sum = 0
6901 11:47:13.067130 5, 0xFFFF, sum = 0
6902 11:47:13.067239 6, 0xFFFF, sum = 0
6903 11:47:13.070406 7, 0xFFFF, sum = 0
6904 11:47:13.070486 8, 0xFFFF, sum = 0
6905 11:47:13.073743 9, 0xFFFF, sum = 0
6906 11:47:13.076880 10, 0xFFFF, sum = 0
6907 11:47:13.076966 11, 0xFFFF, sum = 0
6908 11:47:13.080183 12, 0xFFFF, sum = 0
6909 11:47:13.080269 13, 0x0, sum = 1
6910 11:47:13.083341 14, 0x0, sum = 2
6911 11:47:13.083423 15, 0x0, sum = 3
6912 11:47:13.086641 16, 0x0, sum = 4
6913 11:47:13.086731 best_step = 14
6914 11:47:13.086795
6915 11:47:13.086854 ==
6916 11:47:13.090503 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 11:47:13.093484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 11:47:13.093593 ==
6919 11:47:13.096618 RX Vref Scan: 0
6920 11:47:13.096701
6921 11:47:13.100116 RX Vref 0 -> 0, step: 1
6922 11:47:13.100203
6923 11:47:13.100285 RX Delay -311 -> 252, step: 8
6924 11:47:13.108884 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6925 11:47:13.111729 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6926 11:47:13.115311 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6927 11:47:13.118931 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6928 11:47:13.125033 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6929 11:47:13.128432 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6930 11:47:13.131699 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6931 11:47:13.135084 iDelay=217, Bit 7, Center -20 (-247 ~ 208) 456
6932 11:47:13.141907 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6933 11:47:13.145359 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6934 11:47:13.148577 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6935 11:47:13.151986 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6936 11:47:13.158786 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6937 11:47:13.161767 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6938 11:47:13.165583 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6939 11:47:13.171848 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6940 11:47:13.171956 ==
6941 11:47:13.175373 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 11:47:13.178726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 11:47:13.178810 ==
6944 11:47:13.178888 DQS Delay:
6945 11:47:13.181983 DQS0 = 28, DQS1 = 36
6946 11:47:13.182063 DQM Delay:
6947 11:47:13.185252 DQM0 = 10, DQM1 = 15
6948 11:47:13.185361 DQ Delay:
6949 11:47:13.188518 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6950 11:47:13.191750 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6951 11:47:13.195077 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6952 11:47:13.198282 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6953 11:47:13.198364
6954 11:47:13.198443
6955 11:47:13.204721 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6956 11:47:13.208251 CH1 RK1: MR19=C0C, MR18=C456
6957 11:47:13.215182 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6958 11:47:13.218520 [RxdqsGatingPostProcess] freq 400
6959 11:47:13.221750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6960 11:47:13.225190 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 11:47:13.228400 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 11:47:13.231360 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 11:47:13.235029 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 11:47:13.238175 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 11:47:13.241623 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 11:47:13.245132 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 11:47:13.248026 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 11:47:13.251786 Pre-setting of DQS Precalculation
6969 11:47:13.255274 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6970 11:47:13.265174 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6971 11:47:13.271790 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6972 11:47:13.271909
6973 11:47:13.272010
6974 11:47:13.274946 [Calibration Summary] 800 Mbps
6975 11:47:13.275022 CH 0, Rank 0
6976 11:47:13.278266 SW Impedance : PASS
6977 11:47:13.278352 DUTY Scan : NO K
6978 11:47:13.281247 ZQ Calibration : PASS
6979 11:47:13.284539 Jitter Meter : NO K
6980 11:47:13.284644 CBT Training : PASS
6981 11:47:13.287946 Write leveling : PASS
6982 11:47:13.291162 RX DQS gating : PASS
6983 11:47:13.291273 RX DQ/DQS(RDDQC) : PASS
6984 11:47:13.294468 TX DQ/DQS : PASS
6985 11:47:13.297867 RX DATLAT : PASS
6986 11:47:13.297953 RX DQ/DQS(Engine): PASS
6987 11:47:13.301267 TX OE : NO K
6988 11:47:13.301376 All Pass.
6989 11:47:13.301471
6990 11:47:13.304550 CH 0, Rank 1
6991 11:47:13.304657 SW Impedance : PASS
6992 11:47:13.308120 DUTY Scan : NO K
6993 11:47:13.311428 ZQ Calibration : PASS
6994 11:47:13.311529 Jitter Meter : NO K
6995 11:47:13.314715 CBT Training : PASS
6996 11:47:13.314832 Write leveling : NO K
6997 11:47:13.317892 RX DQS gating : PASS
6998 11:47:13.321027 RX DQ/DQS(RDDQC) : PASS
6999 11:47:13.321130 TX DQ/DQS : PASS
7000 11:47:13.324350 RX DATLAT : PASS
7001 11:47:13.327759 RX DQ/DQS(Engine): PASS
7002 11:47:13.327866 TX OE : NO K
7003 11:47:13.330922 All Pass.
7004 11:47:13.331036
7005 11:47:13.331129 CH 1, Rank 0
7006 11:47:13.334458 SW Impedance : PASS
7007 11:47:13.334564 DUTY Scan : NO K
7008 11:47:13.337876 ZQ Calibration : PASS
7009 11:47:13.341165 Jitter Meter : NO K
7010 11:47:13.341271 CBT Training : PASS
7011 11:47:13.344506 Write leveling : PASS
7012 11:47:13.347912 RX DQS gating : PASS
7013 11:47:13.348016 RX DQ/DQS(RDDQC) : PASS
7014 11:47:13.351111 TX DQ/DQS : PASS
7015 11:47:13.354711 RX DATLAT : PASS
7016 11:47:13.354825 RX DQ/DQS(Engine): PASS
7017 11:47:13.357739 TX OE : NO K
7018 11:47:13.357811 All Pass.
7019 11:47:13.357908
7020 11:47:13.360859 CH 1, Rank 1
7021 11:47:13.360930 SW Impedance : PASS
7022 11:47:13.364312 DUTY Scan : NO K
7023 11:47:13.367893 ZQ Calibration : PASS
7024 11:47:13.367975 Jitter Meter : NO K
7025 11:47:13.370961 CBT Training : PASS
7026 11:47:13.371063 Write leveling : NO K
7027 11:47:13.374776 RX DQS gating : PASS
7028 11:47:13.377870 RX DQ/DQS(RDDQC) : PASS
7029 11:47:13.377979 TX DQ/DQS : PASS
7030 11:47:13.381076 RX DATLAT : PASS
7031 11:47:13.384536 RX DQ/DQS(Engine): PASS
7032 11:47:13.384647 TX OE : NO K
7033 11:47:13.387578 All Pass.
7034 11:47:13.387660
7035 11:47:13.387724 DramC Write-DBI off
7036 11:47:13.390800 PER_BANK_REFRESH: Hybrid Mode
7037 11:47:13.394101 TX_TRACKING: ON
7038 11:47:13.401291 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7039 11:47:13.404748 [FAST_K] Save calibration result to emmc
7040 11:47:13.407498 dramc_set_vcore_voltage set vcore to 725000
7041 11:47:13.410911 Read voltage for 1600, 0
7042 11:47:13.410989 Vio18 = 0
7043 11:47:13.414801 Vcore = 725000
7044 11:47:13.414908 Vdram = 0
7045 11:47:13.415000 Vddq = 0
7046 11:47:13.417873 Vmddr = 0
7047 11:47:13.421323 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7048 11:47:13.427684 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7049 11:47:13.427800 MEM_TYPE=3, freq_sel=13
7050 11:47:13.431304 sv_algorithm_assistance_LP4_3733
7051 11:47:13.434344 ============ PULL DRAM RESETB DOWN ============
7052 11:47:13.441166 ========== PULL DRAM RESETB DOWN end =========
7053 11:47:13.444389 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7054 11:47:13.447935 ===================================
7055 11:47:13.451077 LPDDR4 DRAM CONFIGURATION
7056 11:47:13.454557 ===================================
7057 11:47:13.454640 EX_ROW_EN[0] = 0x0
7058 11:47:13.457776 EX_ROW_EN[1] = 0x0
7059 11:47:13.461075 LP4Y_EN = 0x0
7060 11:47:13.461158 WORK_FSP = 0x1
7061 11:47:13.464538 WL = 0x5
7062 11:47:13.464633 RL = 0x5
7063 11:47:13.467678 BL = 0x2
7064 11:47:13.467762 RPST = 0x0
7065 11:47:13.471456 RD_PRE = 0x0
7066 11:47:13.471542 WR_PRE = 0x1
7067 11:47:13.474537 WR_PST = 0x1
7068 11:47:13.474620 DBI_WR = 0x0
7069 11:47:13.477850 DBI_RD = 0x0
7070 11:47:13.477936 OTF = 0x1
7071 11:47:13.481101 ===================================
7072 11:47:13.484212 ===================================
7073 11:47:13.487667 ANA top config
7074 11:47:13.490978 ===================================
7075 11:47:13.491062 DLL_ASYNC_EN = 0
7076 11:47:13.494363 ALL_SLAVE_EN = 0
7077 11:47:13.498036 NEW_RANK_MODE = 1
7078 11:47:13.501146 DLL_IDLE_MODE = 1
7079 11:47:13.501231 LP45_APHY_COMB_EN = 1
7080 11:47:13.504291 TX_ODT_DIS = 0
7081 11:47:13.507567 NEW_8X_MODE = 1
7082 11:47:13.511064 ===================================
7083 11:47:13.514390 ===================================
7084 11:47:13.517584 data_rate = 3200
7085 11:47:13.520963 CKR = 1
7086 11:47:13.524502 DQ_P2S_RATIO = 8
7087 11:47:13.527732 ===================================
7088 11:47:13.527817 CA_P2S_RATIO = 8
7089 11:47:13.531216 DQ_CA_OPEN = 0
7090 11:47:13.534294 DQ_SEMI_OPEN = 0
7091 11:47:13.537614 CA_SEMI_OPEN = 0
7092 11:47:13.540753 CA_FULL_RATE = 0
7093 11:47:13.544033 DQ_CKDIV4_EN = 0
7094 11:47:13.544137 CA_CKDIV4_EN = 0
7095 11:47:13.547945 CA_PREDIV_EN = 0
7096 11:47:13.551166 PH8_DLY = 12
7097 11:47:13.554373 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7098 11:47:13.557650 DQ_AAMCK_DIV = 4
7099 11:47:13.560990 CA_AAMCK_DIV = 4
7100 11:47:13.561092 CA_ADMCK_DIV = 4
7101 11:47:13.564229 DQ_TRACK_CA_EN = 0
7102 11:47:13.567446 CA_PICK = 1600
7103 11:47:13.570754 CA_MCKIO = 1600
7104 11:47:13.574122 MCKIO_SEMI = 0
7105 11:47:13.577476 PLL_FREQ = 3068
7106 11:47:13.580826 DQ_UI_PI_RATIO = 32
7107 11:47:13.580900 CA_UI_PI_RATIO = 0
7108 11:47:13.584630 ===================================
7109 11:47:13.587796 ===================================
7110 11:47:13.590667 memory_type:LPDDR4
7111 11:47:13.594500 GP_NUM : 10
7112 11:47:13.594626 SRAM_EN : 1
7113 11:47:13.597423 MD32_EN : 0
7114 11:47:13.601036 ===================================
7115 11:47:13.603981 [ANA_INIT] >>>>>>>>>>>>>>
7116 11:47:13.604094 <<<<<< [CONFIGURE PHASE]: ANA_TX
7117 11:47:13.610591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7118 11:47:13.614080 ===================================
7119 11:47:13.614169 data_rate = 3200,PCW = 0X7600
7120 11:47:13.617455 ===================================
7121 11:47:13.620930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7122 11:47:13.627692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 11:47:13.634318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 11:47:13.637483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7125 11:47:13.640719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7126 11:47:13.643952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7127 11:47:13.647080 [ANA_INIT] flow start
7128 11:47:13.647191 [ANA_INIT] PLL >>>>>>>>
7129 11:47:13.650926 [ANA_INIT] PLL <<<<<<<<
7130 11:47:13.654033 [ANA_INIT] MIDPI >>>>>>>>
7131 11:47:13.656995 [ANA_INIT] MIDPI <<<<<<<<
7132 11:47:13.657098 [ANA_INIT] DLL >>>>>>>>
7133 11:47:13.660774 [ANA_INIT] DLL <<<<<<<<
7134 11:47:13.660852 [ANA_INIT] flow end
7135 11:47:13.667598 ============ LP4 DIFF to SE enter ============
7136 11:47:13.670180 ============ LP4 DIFF to SE exit ============
7137 11:47:13.673490 [ANA_INIT] <<<<<<<<<<<<<
7138 11:47:13.677611 [Flow] Enable top DCM control >>>>>
7139 11:47:13.680285 [Flow] Enable top DCM control <<<<<
7140 11:47:13.683618 Enable DLL master slave shuffle
7141 11:47:13.687004 ==============================================================
7142 11:47:13.690186 Gating Mode config
7143 11:47:13.693512 ==============================================================
7144 11:47:13.696915 Config description:
7145 11:47:13.707366 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7146 11:47:13.713932 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7147 11:47:13.716638 SELPH_MODE 0: By rank 1: By Phase
7148 11:47:13.723691 ==============================================================
7149 11:47:13.726799 GAT_TRACK_EN = 1
7150 11:47:13.730335 RX_GATING_MODE = 2
7151 11:47:13.733619 RX_GATING_TRACK_MODE = 2
7152 11:47:13.736757 SELPH_MODE = 1
7153 11:47:13.740000 PICG_EARLY_EN = 1
7154 11:47:13.740116 VALID_LAT_VALUE = 1
7155 11:47:13.746832 ==============================================================
7156 11:47:13.750523 Enter into Gating configuration >>>>
7157 11:47:13.753666 Exit from Gating configuration <<<<
7158 11:47:13.756749 Enter into DVFS_PRE_config >>>>>
7159 11:47:13.766864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7160 11:47:13.770263 Exit from DVFS_PRE_config <<<<<
7161 11:47:13.773476 Enter into PICG configuration >>>>
7162 11:47:13.776836 Exit from PICG configuration <<<<
7163 11:47:13.780386 [RX_INPUT] configuration >>>>>
7164 11:47:13.783294 [RX_INPUT] configuration <<<<<
7165 11:47:13.786629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7166 11:47:13.793183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7167 11:47:13.799902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 11:47:13.806385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 11:47:13.813388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 11:47:13.819622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 11:47:13.822911 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7172 11:47:13.826299 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7173 11:47:13.829583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7174 11:47:13.836273 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7175 11:47:13.839507 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7176 11:47:13.842890 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7177 11:47:13.846400 ===================================
7178 11:47:13.849861 LPDDR4 DRAM CONFIGURATION
7179 11:47:13.852931 ===================================
7180 11:47:13.853045 EX_ROW_EN[0] = 0x0
7181 11:47:13.856364 EX_ROW_EN[1] = 0x0
7182 11:47:13.856470 LP4Y_EN = 0x0
7183 11:47:13.859888 WORK_FSP = 0x1
7184 11:47:13.859991 WL = 0x5
7185 11:47:13.862789 RL = 0x5
7186 11:47:13.862888 BL = 0x2
7187 11:47:13.866085 RPST = 0x0
7188 11:47:13.869787 RD_PRE = 0x0
7189 11:47:13.869870 WR_PRE = 0x1
7190 11:47:13.873007 WR_PST = 0x1
7191 11:47:13.873110 DBI_WR = 0x0
7192 11:47:13.876279 DBI_RD = 0x0
7193 11:47:13.876382 OTF = 0x1
7194 11:47:13.879557 ===================================
7195 11:47:13.883035 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7196 11:47:13.889783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7197 11:47:13.893089 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 11:47:13.896461 ===================================
7199 11:47:13.899808 LPDDR4 DRAM CONFIGURATION
7200 11:47:13.903214 ===================================
7201 11:47:13.903317 EX_ROW_EN[0] = 0x10
7202 11:47:13.906010 EX_ROW_EN[1] = 0x0
7203 11:47:13.906081 LP4Y_EN = 0x0
7204 11:47:13.909348 WORK_FSP = 0x1
7205 11:47:13.909444 WL = 0x5
7206 11:47:13.913081 RL = 0x5
7207 11:47:13.913178 BL = 0x2
7208 11:47:13.916403 RPST = 0x0
7209 11:47:13.916500 RD_PRE = 0x0
7210 11:47:13.919886 WR_PRE = 0x1
7211 11:47:13.919985 WR_PST = 0x1
7212 11:47:13.922870 DBI_WR = 0x0
7213 11:47:13.926295 DBI_RD = 0x0
7214 11:47:13.926413 OTF = 0x1
7215 11:47:13.929283 ===================================
7216 11:47:13.936454 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7217 11:47:13.936559 ==
7218 11:47:13.939929 Dram Type= 6, Freq= 0, CH_0, rank 0
7219 11:47:13.942659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7220 11:47:13.942770 ==
7221 11:47:13.946024 [Duty_Offset_Calibration]
7222 11:47:13.946128 B0:2 B1:1 CA:1
7223 11:47:13.946233
7224 11:47:13.949189 [DutyScan_Calibration_Flow] k_type=0
7225 11:47:13.960660
7226 11:47:13.960763 ==CLK 0==
7227 11:47:13.964295 Final CLK duty delay cell = 0
7228 11:47:13.967556 [0] MAX Duty = 5156%(X100), DQS PI = 22
7229 11:47:13.970812 [0] MIN Duty = 4907%(X100), DQS PI = 0
7230 11:47:13.970889 [0] AVG Duty = 5031%(X100)
7231 11:47:13.974002
7232 11:47:13.977462 CH0 CLK Duty spec in!! Max-Min= 249%
7233 11:47:13.980747 [DutyScan_Calibration_Flow] ====Done====
7234 11:47:13.980850
7235 11:47:13.983912 [DutyScan_Calibration_Flow] k_type=1
7236 11:47:13.999779
7237 11:47:13.999889 ==DQS 0 ==
7238 11:47:14.003275 Final DQS duty delay cell = -4
7239 11:47:14.006455 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7240 11:47:14.009594 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7241 11:47:14.013007 [-4] AVG Duty = 4906%(X100)
7242 11:47:14.013087
7243 11:47:14.013152 ==DQS 1 ==
7244 11:47:14.016301 Final DQS duty delay cell = 0
7245 11:47:14.020013 [0] MAX Duty = 5187%(X100), DQS PI = 20
7246 11:47:14.023062 [0] MIN Duty = 5031%(X100), DQS PI = 52
7247 11:47:14.026369 [0] AVG Duty = 5109%(X100)
7248 11:47:14.026473
7249 11:47:14.029507 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7250 11:47:14.029628
7251 11:47:14.033103 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7252 11:47:14.036372 [DutyScan_Calibration_Flow] ====Done====
7253 11:47:14.036476
7254 11:47:14.040007 [DutyScan_Calibration_Flow] k_type=3
7255 11:47:14.056572
7256 11:47:14.056683 ==DQM 0 ==
7257 11:47:14.059679 Final DQM duty delay cell = 0
7258 11:47:14.063180 [0] MAX Duty = 5218%(X100), DQS PI = 34
7259 11:47:14.066249 [0] MIN Duty = 4907%(X100), DQS PI = 54
7260 11:47:14.066331 [0] AVG Duty = 5062%(X100)
7261 11:47:14.069791
7262 11:47:14.069900 ==DQM 1 ==
7263 11:47:14.073050 Final DQM duty delay cell = -4
7264 11:47:14.076173 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7265 11:47:14.079995 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7266 11:47:14.083245 [-4] AVG Duty = 4906%(X100)
7267 11:47:14.083320
7268 11:47:14.086546 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7269 11:47:14.086618
7270 11:47:14.090005 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7271 11:47:14.093190 [DutyScan_Calibration_Flow] ====Done====
7272 11:47:14.093297
7273 11:47:14.096600 [DutyScan_Calibration_Flow] k_type=2
7274 11:47:14.114376
7275 11:47:14.114485 ==DQ 0 ==
7276 11:47:14.117277 Final DQ duty delay cell = 0
7277 11:47:14.120872 [0] MAX Duty = 5062%(X100), DQS PI = 24
7278 11:47:14.124339 [0] MIN Duty = 4907%(X100), DQS PI = 0
7279 11:47:14.124414 [0] AVG Duty = 4984%(X100)
7280 11:47:14.124490
7281 11:47:14.127690 ==DQ 1 ==
7282 11:47:14.130803 Final DQ duty delay cell = 0
7283 11:47:14.134002 [0] MAX Duty = 5156%(X100), DQS PI = 22
7284 11:47:14.137611 [0] MIN Duty = 4907%(X100), DQS PI = 34
7285 11:47:14.137737 [0] AVG Duty = 5031%(X100)
7286 11:47:14.137851
7287 11:47:14.140540 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7288 11:47:14.140668
7289 11:47:14.147177 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7290 11:47:14.150961 [DutyScan_Calibration_Flow] ====Done====
7291 11:47:14.151038 ==
7292 11:47:14.154305 Dram Type= 6, Freq= 0, CH_1, rank 0
7293 11:47:14.157637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 11:47:14.157723 ==
7295 11:47:14.160980 [Duty_Offset_Calibration]
7296 11:47:14.161093 B0:1 B1:0 CA:0
7297 11:47:14.161182
7298 11:47:14.164463 [DutyScan_Calibration_Flow] k_type=0
7299 11:47:14.173524
7300 11:47:14.173635 ==CLK 0==
7301 11:47:14.176538 Final CLK duty delay cell = -4
7302 11:47:14.180048 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7303 11:47:14.183604 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7304 11:47:14.186689 [-4] AVG Duty = 4922%(X100)
7305 11:47:14.186787
7306 11:47:14.190010 CH1 CLK Duty spec in!! Max-Min= 156%
7307 11:47:14.193445 [DutyScan_Calibration_Flow] ====Done====
7308 11:47:14.193545
7309 11:47:14.196711 [DutyScan_Calibration_Flow] k_type=1
7310 11:47:14.213417
7311 11:47:14.213532 ==DQS 0 ==
7312 11:47:14.216572 Final DQS duty delay cell = 0
7313 11:47:14.220343 [0] MAX Duty = 5094%(X100), DQS PI = 16
7314 11:47:14.223607 [0] MIN Duty = 4844%(X100), DQS PI = 50
7315 11:47:14.223761 [0] AVG Duty = 4969%(X100)
7316 11:47:14.226819
7317 11:47:14.226922 ==DQS 1 ==
7318 11:47:14.230067 Final DQS duty delay cell = 0
7319 11:47:14.233317 [0] MAX Duty = 5281%(X100), DQS PI = 18
7320 11:47:14.236452 [0] MIN Duty = 4938%(X100), DQS PI = 8
7321 11:47:14.240222 [0] AVG Duty = 5109%(X100)
7322 11:47:14.240325
7323 11:47:14.243188 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7324 11:47:14.243291
7325 11:47:14.246736 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7326 11:47:14.250478 [DutyScan_Calibration_Flow] ====Done====
7327 11:47:14.250581
7328 11:47:14.253080 [DutyScan_Calibration_Flow] k_type=3
7329 11:47:14.270462
7330 11:47:14.270593 ==DQM 0 ==
7331 11:47:14.273912 Final DQM duty delay cell = 0
7332 11:47:14.277224 [0] MAX Duty = 5218%(X100), DQS PI = 18
7333 11:47:14.280563 [0] MIN Duty = 4969%(X100), DQS PI = 48
7334 11:47:14.283823 [0] AVG Duty = 5093%(X100)
7335 11:47:14.283923
7336 11:47:14.284029 ==DQM 1 ==
7337 11:47:14.286778 Final DQM duty delay cell = 0
7338 11:47:14.289896 [0] MAX Duty = 5093%(X100), DQS PI = 16
7339 11:47:14.293415 [0] MIN Duty = 4907%(X100), DQS PI = 34
7340 11:47:14.296478 [0] AVG Duty = 5000%(X100)
7341 11:47:14.296581
7342 11:47:14.300513 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7343 11:47:14.300622
7344 11:47:14.303234 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7345 11:47:14.306722 [DutyScan_Calibration_Flow] ====Done====
7346 11:47:14.306824
7347 11:47:14.310037 [DutyScan_Calibration_Flow] k_type=2
7348 11:47:14.326681
7349 11:47:14.326790 ==DQ 0 ==
7350 11:47:14.329524 Final DQ duty delay cell = -4
7351 11:47:14.333298 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7352 11:47:14.336665 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7353 11:47:14.339850 [-4] AVG Duty = 4968%(X100)
7354 11:47:14.339954
7355 11:47:14.340048 ==DQ 1 ==
7356 11:47:14.343053 Final DQ duty delay cell = 0
7357 11:47:14.346388 [0] MAX Duty = 5124%(X100), DQS PI = 18
7358 11:47:14.350224 [0] MIN Duty = 4938%(X100), DQS PI = 10
7359 11:47:14.353467 [0] AVG Duty = 5031%(X100)
7360 11:47:14.353549
7361 11:47:14.356819 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7362 11:47:14.356901
7363 11:47:14.359916 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7364 11:47:14.362778 [DutyScan_Calibration_Flow] ====Done====
7365 11:47:14.366492 nWR fixed to 30
7366 11:47:14.369515 [ModeRegInit_LP4] CH0 RK0
7367 11:47:14.369606 [ModeRegInit_LP4] CH0 RK1
7368 11:47:14.372989 [ModeRegInit_LP4] CH1 RK0
7369 11:47:14.376639 [ModeRegInit_LP4] CH1 RK1
7370 11:47:14.376715 match AC timing 5
7371 11:47:14.383214 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7372 11:47:14.386264 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7373 11:47:14.389483 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7374 11:47:14.396528 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7375 11:47:14.399519 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7376 11:47:14.399613 [MiockJmeterHQA]
7377 11:47:14.399684
7378 11:47:14.403116 [DramcMiockJmeter] u1RxGatingPI = 0
7379 11:47:14.406717 0 : 4255, 4027
7380 11:47:14.406799 4 : 4252, 4027
7381 11:47:14.409454 8 : 4255, 4027
7382 11:47:14.409561 12 : 4258, 4029
7383 11:47:14.409654 16 : 4367, 4140
7384 11:47:14.413068 20 : 4252, 4027
7385 11:47:14.413148 24 : 4252, 4027
7386 11:47:14.416372 28 : 4252, 4027
7387 11:47:14.416450 32 : 4252, 4027
7388 11:47:14.419487 36 : 4363, 4137
7389 11:47:14.419564 40 : 4252, 4027
7390 11:47:14.422759 44 : 4255, 4029
7391 11:47:14.422842 48 : 4252, 4027
7392 11:47:14.422911 52 : 4252, 4027
7393 11:47:14.426553 56 : 4253, 4026
7394 11:47:14.426635 60 : 4363, 4138
7395 11:47:14.429674 64 : 4363, 4137
7396 11:47:14.429801 68 : 4252, 4027
7397 11:47:14.433071 72 : 4253, 4027
7398 11:47:14.433171 76 : 4250, 4026
7399 11:47:14.436164 80 : 4252, 4029
7400 11:47:14.436266 84 : 4249, 4027
7401 11:47:14.436369 88 : 4361, 179
7402 11:47:14.439789 92 : 4249, 0
7403 11:47:14.439901 96 : 4252, 0
7404 11:47:14.439991 100 : 4250, 0
7405 11:47:14.442888 104 : 4250, 0
7406 11:47:14.442993 108 : 4249, 0
7407 11:47:14.446272 112 : 4360, 0
7408 11:47:14.446352 116 : 4250, 0
7409 11:47:14.446448 120 : 4360, 0
7410 11:47:14.449571 124 : 4250, 0
7411 11:47:14.449685 128 : 4360, 0
7412 11:47:14.452757 132 : 4361, 0
7413 11:47:14.452827 136 : 4250, 0
7414 11:47:14.452900 140 : 4250, 0
7415 11:47:14.456080 144 : 4250, 0
7416 11:47:14.456190 148 : 4253, 0
7417 11:47:14.456284 152 : 4249, 0
7418 11:47:14.459393 156 : 4250, 0
7419 11:47:14.459467 160 : 4249, 0
7420 11:47:14.462884 164 : 4360, 0
7421 11:47:14.462966 168 : 4250, 0
7422 11:47:14.463029 172 : 4250, 0
7423 11:47:14.466073 176 : 4250, 0
7424 11:47:14.466159 180 : 4250, 0
7425 11:47:14.469496 184 : 4250, 0
7426 11:47:14.469588 188 : 4250, 0
7427 11:47:14.469666 192 : 4250, 0
7428 11:47:14.473072 196 : 4250, 0
7429 11:47:14.473151 200 : 4249, 0
7430 11:47:14.476347 204 : 4250, 946
7431 11:47:14.476427 208 : 4249, 3937
7432 11:47:14.479451 212 : 4249, 4027
7433 11:47:14.479531 216 : 4250, 4026
7434 11:47:14.479594 220 : 4361, 4137
7435 11:47:14.482729 224 : 4249, 4027
7436 11:47:14.482834 228 : 4250, 4026
7437 11:47:14.486102 232 : 4361, 4137
7438 11:47:14.486214 236 : 4250, 4027
7439 11:47:14.489257 240 : 4250, 4027
7440 11:47:14.489336 244 : 4360, 4137
7441 11:47:14.492861 248 : 4250, 4026
7442 11:47:14.492940 252 : 4250, 4027
7443 11:47:14.495810 256 : 4250, 4027
7444 11:47:14.495890 260 : 4249, 4027
7445 11:47:14.499477 264 : 4250, 4026
7446 11:47:14.499557 268 : 4250, 4027
7447 11:47:14.502552 272 : 4360, 4138
7448 11:47:14.502631 276 : 4249, 4027
7449 11:47:14.505742 280 : 4250, 4026
7450 11:47:14.505836 284 : 4361, 4137
7451 11:47:14.505901 288 : 4252, 4027
7452 11:47:14.509230 292 : 4250, 4027
7453 11:47:14.509310 296 : 4360, 4137
7454 11:47:14.512677 300 : 4250, 4026
7455 11:47:14.512757 304 : 4250, 4026
7456 11:47:14.515553 308 : 4250, 4015
7457 11:47:14.515634 312 : 4249, 2165
7458 11:47:14.519291 316 : 4250, 10
7459 11:47:14.519372
7460 11:47:14.519434 MIOCK jitter meter ch=0
7461 11:47:14.519492
7462 11:47:14.522720 1T = (316-88) = 228 dly cells
7463 11:47:14.528842 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7464 11:47:14.528927 ==
7465 11:47:14.532563 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 11:47:14.535734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 11:47:14.535817 ==
7468 11:47:14.542086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 11:47:14.545826 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 11:47:14.549449 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 11:47:14.555942 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 11:47:14.565211 [CA 0] Center 42 (12~73) winsize 62
7473 11:47:14.569271 [CA 1] Center 42 (12~73) winsize 62
7474 11:47:14.571896 [CA 2] Center 38 (8~68) winsize 61
7475 11:47:14.575749 [CA 3] Center 37 (8~67) winsize 60
7476 11:47:14.579071 [CA 4] Center 36 (6~66) winsize 61
7477 11:47:14.582339 [CA 5] Center 35 (6~64) winsize 59
7478 11:47:14.582419
7479 11:47:14.585371 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7480 11:47:14.585450
7481 11:47:14.588658 [CATrainingPosCal] consider 1 rank data
7482 11:47:14.592465 u2DelayCellTimex100 = 285/100 ps
7483 11:47:14.595941 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7484 11:47:14.602375 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7485 11:47:14.605801 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7486 11:47:14.608893 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7487 11:47:14.612136 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7488 11:47:14.615222 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7489 11:47:14.615301
7490 11:47:14.619122 CA PerBit enable=1, Macro0, CA PI delay=35
7491 11:47:14.619216
7492 11:47:14.622387 [CBTSetCACLKResult] CA Dly = 35
7493 11:47:14.625568 CS Dly: 9 (0~40)
7494 11:47:14.628891 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 11:47:14.632019 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 11:47:14.632112 ==
7497 11:47:14.635146 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 11:47:14.638676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 11:47:14.638760 ==
7500 11:47:14.645183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 11:47:14.648737 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 11:47:14.655404 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 11:47:14.658841 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 11:47:14.669065 [CA 0] Center 42 (12~73) winsize 62
7505 11:47:14.672169 [CA 1] Center 42 (12~73) winsize 62
7506 11:47:14.675604 [CA 2] Center 37 (8~67) winsize 60
7507 11:47:14.678913 [CA 3] Center 37 (7~68) winsize 62
7508 11:47:14.682205 [CA 4] Center 35 (6~65) winsize 60
7509 11:47:14.685653 [CA 5] Center 35 (5~65) winsize 61
7510 11:47:14.685776
7511 11:47:14.688756 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7512 11:47:14.688838
7513 11:47:14.692050 [CATrainingPosCal] consider 2 rank data
7514 11:47:14.695307 u2DelayCellTimex100 = 285/100 ps
7515 11:47:14.698809 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7516 11:47:14.705384 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7517 11:47:14.708431 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 11:47:14.711721 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7519 11:47:14.715469 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7520 11:47:14.718668 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7521 11:47:14.718760
7522 11:47:14.721914 CA PerBit enable=1, Macro0, CA PI delay=35
7523 11:47:14.722014
7524 11:47:14.725252 [CBTSetCACLKResult] CA Dly = 35
7525 11:47:14.728624 CS Dly: 10 (0~42)
7526 11:47:14.732057 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 11:47:14.735604 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 11:47:14.735716
7529 11:47:14.738863 ----->DramcWriteLeveling(PI) begin...
7530 11:47:14.738945 ==
7531 11:47:14.742016 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 11:47:14.745465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 11:47:14.748800 ==
7534 11:47:14.748882 Write leveling (Byte 0): 34 => 34
7535 11:47:14.751643 Write leveling (Byte 1): 27 => 27
7536 11:47:14.754932 DramcWriteLeveling(PI) end<-----
7537 11:47:14.755015
7538 11:47:14.755079 ==
7539 11:47:14.758465 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 11:47:14.765105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 11:47:14.765188 ==
7542 11:47:14.765254 [Gating] SW mode calibration
7543 11:47:14.775248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 11:47:14.778513 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 11:47:14.781818 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7546 11:47:14.788851 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7547 11:47:14.792033 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7548 11:47:14.794975 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7549 11:47:14.801633 1 4 16 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
7550 11:47:14.805181 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7551 11:47:14.808426 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7552 11:47:14.814876 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7553 11:47:14.817995 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7554 11:47:14.821514 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7555 11:47:14.828515 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7556 11:47:14.831661 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7557 11:47:14.834959 1 5 16 | B1->B0 | 3434 2525 | 0 1 | (0 0) (0 0)
7558 11:47:14.841533 1 5 20 | B1->B0 | 2525 2525 | 0 0 | (1 0) (0 0)
7559 11:47:14.844838 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7560 11:47:14.848004 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7561 11:47:14.855092 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7562 11:47:14.858400 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7563 11:47:14.861698 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7564 11:47:14.868068 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7565 11:47:14.871432 1 6 16 | B1->B0 | 2929 4645 | 0 1 | (0 0) (0 0)
7566 11:47:14.874630 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7567 11:47:14.881168 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 11:47:14.884516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 11:47:14.887856 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 11:47:14.894624 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 11:47:14.898230 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 11:47:14.901050 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 11:47:14.908273 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7574 11:47:14.911052 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 11:47:14.914697 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 11:47:14.920985 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 11:47:14.924700 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:47:14.928176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:47:14.931539 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:47:14.938044 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:47:14.941127 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:47:14.944599 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:47:14.951016 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:47:14.954987 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:47:14.958236 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:47:14.964805 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:47:14.967566 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 11:47:14.970981 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 11:47:14.977778 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 11:47:14.981099 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 11:47:14.984527 Total UI for P1: 0, mck2ui 16
7592 11:47:14.987818 best dqsien dly found for B0: ( 1, 9, 12)
7593 11:47:14.990795 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 11:47:14.994188 Total UI for P1: 0, mck2ui 16
7595 11:47:14.997483 best dqsien dly found for B1: ( 1, 9, 20)
7596 11:47:15.000806 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7597 11:47:15.004266 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7598 11:47:15.004364
7599 11:47:15.011166 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7600 11:47:15.014540 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7601 11:47:15.017316 [Gating] SW calibration Done
7602 11:47:15.017398 ==
7603 11:47:15.021256 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 11:47:15.024417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 11:47:15.024501 ==
7606 11:47:15.024565 RX Vref Scan: 0
7607 11:47:15.024624
7608 11:47:15.027403 RX Vref 0 -> 0, step: 1
7609 11:47:15.027485
7610 11:47:15.031179 RX Delay 0 -> 252, step: 8
7611 11:47:15.033865 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7612 11:47:15.037288 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7613 11:47:15.044092 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7614 11:47:15.047636 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7615 11:47:15.050847 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7616 11:47:15.053892 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7617 11:47:15.057621 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7618 11:47:15.060537 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7619 11:47:15.067539 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7620 11:47:15.070471 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7621 11:47:15.074205 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7622 11:47:15.077809 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7623 11:47:15.080585 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7624 11:47:15.087258 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7625 11:47:15.090438 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7626 11:47:15.093809 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7627 11:47:15.093917 ==
7628 11:47:15.097063 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 11:47:15.100399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 11:47:15.103780 ==
7631 11:47:15.103862 DQS Delay:
7632 11:47:15.103927 DQS0 = 0, DQS1 = 0
7633 11:47:15.107038 DQM Delay:
7634 11:47:15.107119 DQM0 = 137, DQM1 = 130
7635 11:47:15.110360 DQ Delay:
7636 11:47:15.113982 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7637 11:47:15.116955 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7638 11:47:15.120899 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7639 11:47:15.124091 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7640 11:47:15.124172
7641 11:47:15.124262
7642 11:47:15.124327 ==
7643 11:47:15.127362 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 11:47:15.130628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 11:47:15.130711 ==
7646 11:47:15.130775
7647 11:47:15.133733
7648 11:47:15.133815 TX Vref Scan disable
7649 11:47:15.136791 == TX Byte 0 ==
7650 11:47:15.140337 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7651 11:47:15.143888 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7652 11:47:15.147040 == TX Byte 1 ==
7653 11:47:15.150305 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7654 11:47:15.153514 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7655 11:47:15.153604 ==
7656 11:47:15.156795 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 11:47:15.163413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 11:47:15.163495 ==
7659 11:47:15.175076
7660 11:47:15.178335 TX Vref early break, caculate TX vref
7661 11:47:15.181434 TX Vref=16, minBit 0, minWin=23, winSum=384
7662 11:47:15.184669 TX Vref=18, minBit 0, minWin=24, winSum=391
7663 11:47:15.188603 TX Vref=20, minBit 7, minWin=24, winSum=401
7664 11:47:15.191814 TX Vref=22, minBit 1, minWin=25, winSum=411
7665 11:47:15.194950 TX Vref=24, minBit 0, minWin=26, winSum=422
7666 11:47:15.201894 TX Vref=26, minBit 7, minWin=25, winSum=428
7667 11:47:15.204831 TX Vref=28, minBit 0, minWin=26, winSum=427
7668 11:47:15.207891 TX Vref=30, minBit 1, minWin=25, winSum=413
7669 11:47:15.211581 TX Vref=32, minBit 1, minWin=23, winSum=403
7670 11:47:15.217866 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
7671 11:47:15.217951
7672 11:47:15.221058 Final TX Range 0 Vref 28
7673 11:47:15.221160
7674 11:47:15.221262 ==
7675 11:47:15.224612 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 11:47:15.228169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 11:47:15.228278 ==
7678 11:47:15.228393
7679 11:47:15.228485
7680 11:47:15.231403 TX Vref Scan disable
7681 11:47:15.234638 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7682 11:47:15.238373 == TX Byte 0 ==
7683 11:47:15.241472 u2DelayCellOfst[0]=10 cells (3 PI)
7684 11:47:15.244703 u2DelayCellOfst[1]=13 cells (4 PI)
7685 11:47:15.247760 u2DelayCellOfst[2]=10 cells (3 PI)
7686 11:47:15.251142 u2DelayCellOfst[3]=10 cells (3 PI)
7687 11:47:15.254982 u2DelayCellOfst[4]=10 cells (3 PI)
7688 11:47:15.255065 u2DelayCellOfst[5]=0 cells (0 PI)
7689 11:47:15.258137 u2DelayCellOfst[6]=17 cells (5 PI)
7690 11:47:15.261369 u2DelayCellOfst[7]=20 cells (6 PI)
7691 11:47:15.268096 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7692 11:47:15.271429 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7693 11:47:15.271512 == TX Byte 1 ==
7694 11:47:15.274689 u2DelayCellOfst[8]=0 cells (0 PI)
7695 11:47:15.277842 u2DelayCellOfst[9]=3 cells (1 PI)
7696 11:47:15.281110 u2DelayCellOfst[10]=10 cells (3 PI)
7697 11:47:15.284294 u2DelayCellOfst[11]=3 cells (1 PI)
7698 11:47:15.288066 u2DelayCellOfst[12]=13 cells (4 PI)
7699 11:47:15.291344 u2DelayCellOfst[13]=10 cells (3 PI)
7700 11:47:15.294656 u2DelayCellOfst[14]=13 cells (4 PI)
7701 11:47:15.297951 u2DelayCellOfst[15]=10 cells (3 PI)
7702 11:47:15.301213 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7703 11:47:15.304459 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7704 11:47:15.307790 DramC Write-DBI on
7705 11:47:15.307877 ==
7706 11:47:15.311076 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 11:47:15.314139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 11:47:15.314221 ==
7709 11:47:15.314285
7710 11:47:15.314344
7711 11:47:15.317850 TX Vref Scan disable
7712 11:47:15.321135 == TX Byte 0 ==
7713 11:47:15.324307 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7714 11:47:15.327420 == TX Byte 1 ==
7715 11:47:15.330932 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7716 11:47:15.331059 DramC Write-DBI off
7717 11:47:15.331151
7718 11:47:15.334116 [DATLAT]
7719 11:47:15.334219 Freq=1600, CH0 RK0
7720 11:47:15.334308
7721 11:47:15.337743 DATLAT Default: 0xf
7722 11:47:15.337815 0, 0xFFFF, sum = 0
7723 11:47:15.340580 1, 0xFFFF, sum = 0
7724 11:47:15.340679 2, 0xFFFF, sum = 0
7725 11:47:15.344085 3, 0xFFFF, sum = 0
7726 11:47:15.344184 4, 0xFFFF, sum = 0
7727 11:47:15.347235 5, 0xFFFF, sum = 0
7728 11:47:15.347335 6, 0xFFFF, sum = 0
7729 11:47:15.351178 7, 0xFFFF, sum = 0
7730 11:47:15.351284 8, 0xFFFF, sum = 0
7731 11:47:15.354218 9, 0xFFFF, sum = 0
7732 11:47:15.357508 10, 0xFFFF, sum = 0
7733 11:47:15.357631 11, 0xFFFF, sum = 0
7734 11:47:15.361280 12, 0xFFFF, sum = 0
7735 11:47:15.361376 13, 0xFFFF, sum = 0
7736 11:47:15.364355 14, 0x0, sum = 1
7737 11:47:15.364497 15, 0x0, sum = 2
7738 11:47:15.367411 16, 0x0, sum = 3
7739 11:47:15.367538 17, 0x0, sum = 4
7740 11:47:15.367619 best_step = 15
7741 11:47:15.370715
7742 11:47:15.370799 ==
7743 11:47:15.374310 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:47:15.377282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:47:15.377367 ==
7746 11:47:15.377447 RX Vref Scan: 1
7747 11:47:15.377509
7748 11:47:15.380556 Set Vref Range= 24 -> 127
7749 11:47:15.380639
7750 11:47:15.383941 RX Vref 24 -> 127, step: 1
7751 11:47:15.384070
7752 11:47:15.387238 RX Delay 27 -> 252, step: 4
7753 11:47:15.387335
7754 11:47:15.390807 Set Vref, RX VrefLevel [Byte0]: 24
7755 11:47:15.394093 [Byte1]: 24
7756 11:47:15.394174
7757 11:47:15.397348 Set Vref, RX VrefLevel [Byte0]: 25
7758 11:47:15.401150 [Byte1]: 25
7759 11:47:15.401271
7760 11:47:15.403893 Set Vref, RX VrefLevel [Byte0]: 26
7761 11:47:15.407214 [Byte1]: 26
7762 11:47:15.410593
7763 11:47:15.410674 Set Vref, RX VrefLevel [Byte0]: 27
7764 11:47:15.413999 [Byte1]: 27
7765 11:47:15.418593
7766 11:47:15.418689 Set Vref, RX VrefLevel [Byte0]: 28
7767 11:47:15.421288 [Byte1]: 28
7768 11:47:15.425741
7769 11:47:15.425839 Set Vref, RX VrefLevel [Byte0]: 29
7770 11:47:15.428964 [Byte1]: 29
7771 11:47:15.433414
7772 11:47:15.433526 Set Vref, RX VrefLevel [Byte0]: 30
7773 11:47:15.436296 [Byte1]: 30
7774 11:47:15.440596
7775 11:47:15.440678 Set Vref, RX VrefLevel [Byte0]: 31
7776 11:47:15.443864 [Byte1]: 31
7777 11:47:15.448379
7778 11:47:15.448455 Set Vref, RX VrefLevel [Byte0]: 32
7779 11:47:15.451517 [Byte1]: 32
7780 11:47:15.456372
7781 11:47:15.456454 Set Vref, RX VrefLevel [Byte0]: 33
7782 11:47:15.459602 [Byte1]: 33
7783 11:47:15.463476
7784 11:47:15.463557 Set Vref, RX VrefLevel [Byte0]: 34
7785 11:47:15.466778 [Byte1]: 34
7786 11:47:15.471154
7787 11:47:15.471237 Set Vref, RX VrefLevel [Byte0]: 35
7788 11:47:15.474565 [Byte1]: 35
7789 11:47:15.478866
7790 11:47:15.478948 Set Vref, RX VrefLevel [Byte0]: 36
7791 11:47:15.481806 [Byte1]: 36
7792 11:47:15.486246
7793 11:47:15.486328 Set Vref, RX VrefLevel [Byte0]: 37
7794 11:47:15.489417 [Byte1]: 37
7795 11:47:15.493465
7796 11:47:15.493549 Set Vref, RX VrefLevel [Byte0]: 38
7797 11:47:15.499920 [Byte1]: 38
7798 11:47:15.500002
7799 11:47:15.503468 Set Vref, RX VrefLevel [Byte0]: 39
7800 11:47:15.506712 [Byte1]: 39
7801 11:47:15.506795
7802 11:47:15.510173 Set Vref, RX VrefLevel [Byte0]: 40
7803 11:47:15.513419 [Byte1]: 40
7804 11:47:15.513501
7805 11:47:15.516435 Set Vref, RX VrefLevel [Byte0]: 41
7806 11:47:15.520125 [Byte1]: 41
7807 11:47:15.523966
7808 11:47:15.524047 Set Vref, RX VrefLevel [Byte0]: 42
7809 11:47:15.527208 [Byte1]: 42
7810 11:47:15.531163
7811 11:47:15.531244 Set Vref, RX VrefLevel [Byte0]: 43
7812 11:47:15.534513 [Byte1]: 43
7813 11:47:15.538979
7814 11:47:15.539061 Set Vref, RX VrefLevel [Byte0]: 44
7815 11:47:15.542047 [Byte1]: 44
7816 11:47:15.546159
7817 11:47:15.546259 Set Vref, RX VrefLevel [Byte0]: 45
7818 11:47:15.549841 [Byte1]: 45
7819 11:47:15.553783
7820 11:47:15.553864 Set Vref, RX VrefLevel [Byte0]: 46
7821 11:47:15.557068 [Byte1]: 46
7822 11:47:15.561154
7823 11:47:15.561235 Set Vref, RX VrefLevel [Byte0]: 47
7824 11:47:15.565100 [Byte1]: 47
7825 11:47:15.568905
7826 11:47:15.568986 Set Vref, RX VrefLevel [Byte0]: 48
7827 11:47:15.572197 [Byte1]: 48
7828 11:47:15.576262
7829 11:47:15.576369 Set Vref, RX VrefLevel [Byte0]: 49
7830 11:47:15.579579 [Byte1]: 49
7831 11:47:15.584081
7832 11:47:15.584185 Set Vref, RX VrefLevel [Byte0]: 50
7833 11:47:15.587444 [Byte1]: 50
7834 11:47:15.591443
7835 11:47:15.591546 Set Vref, RX VrefLevel [Byte0]: 51
7836 11:47:15.594611 [Byte1]: 51
7837 11:47:15.599198
7838 11:47:15.599298 Set Vref, RX VrefLevel [Byte0]: 52
7839 11:47:15.602412 [Byte1]: 52
7840 11:47:15.606336
7841 11:47:15.606439 Set Vref, RX VrefLevel [Byte0]: 53
7842 11:47:15.610201 [Byte1]: 53
7843 11:47:15.613792
7844 11:47:15.613901 Set Vref, RX VrefLevel [Byte0]: 54
7845 11:47:15.617431 [Byte1]: 54
7846 11:47:15.621504
7847 11:47:15.621641 Set Vref, RX VrefLevel [Byte0]: 55
7848 11:47:15.625065 [Byte1]: 55
7849 11:47:15.628921
7850 11:47:15.629037 Set Vref, RX VrefLevel [Byte0]: 56
7851 11:47:15.632621 [Byte1]: 56
7852 11:47:15.636863
7853 11:47:15.637022 Set Vref, RX VrefLevel [Byte0]: 57
7854 11:47:15.639919 [Byte1]: 57
7855 11:47:15.644202
7856 11:47:15.644305 Set Vref, RX VrefLevel [Byte0]: 58
7857 11:47:15.647155 [Byte1]: 58
7858 11:47:15.652018
7859 11:47:15.652126 Set Vref, RX VrefLevel [Byte0]: 59
7860 11:47:15.655026 [Byte1]: 59
7861 11:47:15.659130
7862 11:47:15.659235 Set Vref, RX VrefLevel [Byte0]: 60
7863 11:47:15.662860 [Byte1]: 60
7864 11:47:15.666715
7865 11:47:15.666800 Set Vref, RX VrefLevel [Byte0]: 61
7866 11:47:15.670406 [Byte1]: 61
7867 11:47:15.674456
7868 11:47:15.674570 Set Vref, RX VrefLevel [Byte0]: 62
7869 11:47:15.677830 [Byte1]: 62
7870 11:47:15.681522
7871 11:47:15.681627 Set Vref, RX VrefLevel [Byte0]: 63
7872 11:47:15.685105 [Byte1]: 63
7873 11:47:15.689875
7874 11:47:15.689954 Set Vref, RX VrefLevel [Byte0]: 64
7875 11:47:15.692534 [Byte1]: 64
7876 11:47:15.697349
7877 11:47:15.697445 Set Vref, RX VrefLevel [Byte0]: 65
7878 11:47:15.700520 [Byte1]: 65
7879 11:47:15.704575
7880 11:47:15.704672 Set Vref, RX VrefLevel [Byte0]: 66
7881 11:47:15.707889 [Byte1]: 66
7882 11:47:15.712045
7883 11:47:15.712126 Set Vref, RX VrefLevel [Byte0]: 67
7884 11:47:15.715259 [Byte1]: 67
7885 11:47:15.719365
7886 11:47:15.719476 Set Vref, RX VrefLevel [Byte0]: 68
7887 11:47:15.723174 [Byte1]: 68
7888 11:47:15.727187
7889 11:47:15.727269 Set Vref, RX VrefLevel [Byte0]: 69
7890 11:47:15.730578 [Byte1]: 69
7891 11:47:15.734601
7892 11:47:15.734689 Set Vref, RX VrefLevel [Byte0]: 70
7893 11:47:15.737856 [Byte1]: 70
7894 11:47:15.742307
7895 11:47:15.742389 Set Vref, RX VrefLevel [Byte0]: 71
7896 11:47:15.745458 [Byte1]: 71
7897 11:47:15.749396
7898 11:47:15.749487 Set Vref, RX VrefLevel [Byte0]: 72
7899 11:47:15.753021 [Byte1]: 72
7900 11:47:15.756911
7901 11:47:15.757024 Set Vref, RX VrefLevel [Byte0]: 73
7902 11:47:15.760237 [Byte1]: 73
7903 11:47:15.764913
7904 11:47:15.765006 Set Vref, RX VrefLevel [Byte0]: 74
7905 11:47:15.768150 [Byte1]: 74
7906 11:47:15.772426
7907 11:47:15.772525 Final RX Vref Byte 0 = 55 to rank0
7908 11:47:15.775357 Final RX Vref Byte 1 = 63 to rank0
7909 11:47:15.778851 Final RX Vref Byte 0 = 55 to rank1
7910 11:47:15.782509 Final RX Vref Byte 1 = 63 to rank1==
7911 11:47:15.785405 Dram Type= 6, Freq= 0, CH_0, rank 0
7912 11:47:15.792129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7913 11:47:15.792210 ==
7914 11:47:15.792275 DQS Delay:
7915 11:47:15.792347 DQS0 = 0, DQS1 = 0
7916 11:47:15.795387 DQM Delay:
7917 11:47:15.795465 DQM0 = 133, DQM1 = 128
7918 11:47:15.798595 DQ Delay:
7919 11:47:15.801943 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7920 11:47:15.805806 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7921 11:47:15.809272 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7922 11:47:15.812454 DQ12 =132, DQ13 =134, DQ14 =140, DQ15 =136
7923 11:47:15.812541
7924 11:47:15.812610
7925 11:47:15.812674
7926 11:47:15.815761 [DramC_TX_OE_Calibration] TA2
7927 11:47:15.819089 Original DQ_B0 (3 6) =30, OEN = 27
7928 11:47:15.822466 Original DQ_B1 (3 6) =30, OEN = 27
7929 11:47:15.825821 24, 0x0, End_B0=24 End_B1=24
7930 11:47:15.825908 25, 0x0, End_B0=25 End_B1=25
7931 11:47:15.828929 26, 0x0, End_B0=26 End_B1=26
7932 11:47:15.832334 27, 0x0, End_B0=27 End_B1=27
7933 11:47:15.835705 28, 0x0, End_B0=28 End_B1=28
7934 11:47:15.835787 29, 0x0, End_B0=29 End_B1=29
7935 11:47:15.839197 30, 0x0, End_B0=30 End_B1=30
7936 11:47:15.842575 31, 0x4141, End_B0=30 End_B1=30
7937 11:47:15.846112 Byte0 end_step=30 best_step=27
7938 11:47:15.849074 Byte1 end_step=30 best_step=27
7939 11:47:15.852284 Byte0 TX OE(2T, 0.5T) = (3, 3)
7940 11:47:15.852360 Byte1 TX OE(2T, 0.5T) = (3, 3)
7941 11:47:15.852423
7942 11:47:15.855440
7943 11:47:15.862163 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7944 11:47:15.865550 CH0 RK0: MR19=303, MR18=241F
7945 11:47:15.872567 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7946 11:47:15.872653
7947 11:47:15.875855 ----->DramcWriteLeveling(PI) begin...
7948 11:47:15.875941 ==
7949 11:47:15.879045 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 11:47:15.882404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 11:47:15.882486 ==
7952 11:47:15.885501 Write leveling (Byte 0): 34 => 34
7953 11:47:15.888825 Write leveling (Byte 1): 26 => 26
7954 11:47:15.892053 DramcWriteLeveling(PI) end<-----
7955 11:47:15.892136
7956 11:47:15.892200 ==
7957 11:47:15.895768 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 11:47:15.898924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 11:47:15.899006 ==
7960 11:47:15.902373 [Gating] SW mode calibration
7961 11:47:15.908936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7962 11:47:15.915457 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7963 11:47:15.918976 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 11:47:15.922108 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 11:47:15.928605 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 11:47:15.931789 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7967 11:47:15.934931 1 4 16 | B1->B0 | 2e2e 3535 | 1 1 | (1 1) (1 1)
7968 11:47:15.941693 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7969 11:47:15.944876 1 4 24 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7970 11:47:15.948319 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7971 11:47:15.954966 1 5 0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7972 11:47:15.958612 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7973 11:47:15.961998 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 0)
7974 11:47:15.968209 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7975 11:47:15.971903 1 5 16 | B1->B0 | 2c2c 2525 | 1 0 | (1 0) (1 0)
7976 11:47:15.975048 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7977 11:47:15.981603 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7978 11:47:15.984858 1 5 28 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7979 11:47:15.988268 1 6 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7980 11:47:15.995242 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7981 11:47:15.997884 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7982 11:47:16.001261 1 6 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7983 11:47:16.008349 1 6 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7984 11:47:16.011667 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 11:47:16.014581 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7986 11:47:16.018508 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 11:47:16.025307 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 11:47:16.028619 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 11:47:16.031276 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 11:47:16.037785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7991 11:47:16.041497 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7992 11:47:16.044450 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 11:47:16.051430 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 11:47:16.054541 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 11:47:16.058082 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 11:47:16.064247 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 11:47:16.067603 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 11:47:16.071754 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:47:16.078100 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:47:16.081252 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:47:16.084619 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:47:16.091150 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:47:16.094476 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:47:16.097804 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:47:16.104500 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:47:16.107898 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8007 11:47:16.111040 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8008 11:47:16.117920 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 11:47:16.118013 Total UI for P1: 0, mck2ui 16
8010 11:47:16.124522 best dqsien dly found for B0: ( 1, 9, 14)
8011 11:47:16.124605 Total UI for P1: 0, mck2ui 16
8012 11:47:16.131272 best dqsien dly found for B1: ( 1, 9, 14)
8013 11:47:16.134609 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8014 11:47:16.138003 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8015 11:47:16.138088
8016 11:47:16.141248 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8017 11:47:16.144475 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8018 11:47:16.147476 [Gating] SW calibration Done
8019 11:47:16.147578 ==
8020 11:47:16.150899 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 11:47:16.154122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 11:47:16.154206 ==
8023 11:47:16.157485 RX Vref Scan: 0
8024 11:47:16.157567
8025 11:47:16.157645 RX Vref 0 -> 0, step: 1
8026 11:47:16.157709
8027 11:47:16.160839 RX Delay 0 -> 252, step: 8
8028 11:47:16.164159 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8029 11:47:16.171087 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8030 11:47:16.174292 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8031 11:47:16.177906 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8032 11:47:16.180870 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8033 11:47:16.184420 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8034 11:47:16.191135 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8035 11:47:16.194248 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8036 11:47:16.197312 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8037 11:47:16.200593 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8038 11:47:16.204198 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8039 11:47:16.210625 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8040 11:47:16.213758 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8041 11:47:16.217820 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8042 11:47:16.221096 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8043 11:47:16.224376 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8044 11:47:16.227719 ==
8045 11:47:16.227802 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 11:47:16.234196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 11:47:16.234320 ==
8048 11:47:16.234390 DQS Delay:
8049 11:47:16.237545 DQS0 = 0, DQS1 = 0
8050 11:47:16.237636 DQM Delay:
8051 11:47:16.240860 DQM0 = 137, DQM1 = 130
8052 11:47:16.240942 DQ Delay:
8053 11:47:16.244282 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8054 11:47:16.247363 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8055 11:47:16.250814 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8056 11:47:16.253903 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8057 11:47:16.253991
8058 11:47:16.254074
8059 11:47:16.254136 ==
8060 11:47:16.257604 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 11:47:16.264177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 11:47:16.264265 ==
8063 11:47:16.264333
8064 11:47:16.264393
8065 11:47:16.264451 TX Vref Scan disable
8066 11:47:16.267356 == TX Byte 0 ==
8067 11:47:16.270571 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8068 11:47:16.274305 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8069 11:47:16.277514 == TX Byte 1 ==
8070 11:47:16.280766 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8071 11:47:16.283968 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8072 11:47:16.287307 ==
8073 11:47:16.290695 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 11:47:16.293915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 11:47:16.293999 ==
8076 11:47:16.307220
8077 11:47:16.310705 TX Vref early break, caculate TX vref
8078 11:47:16.314345 TX Vref=16, minBit 1, minWin=22, winSum=385
8079 11:47:16.317093 TX Vref=18, minBit 0, minWin=24, winSum=399
8080 11:47:16.320822 TX Vref=20, minBit 1, minWin=24, winSum=409
8081 11:47:16.323683 TX Vref=22, minBit 1, minWin=24, winSum=412
8082 11:47:16.327434 TX Vref=24, minBit 1, minWin=25, winSum=427
8083 11:47:16.333761 TX Vref=26, minBit 1, minWin=25, winSum=430
8084 11:47:16.337058 TX Vref=28, minBit 7, minWin=25, winSum=425
8085 11:47:16.340302 TX Vref=30, minBit 0, minWin=25, winSum=416
8086 11:47:16.343971 TX Vref=32, minBit 0, minWin=24, winSum=412
8087 11:47:16.347300 TX Vref=34, minBit 6, minWin=24, winSum=404
8088 11:47:16.353950 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8089 11:47:16.354033
8090 11:47:16.357396 Final TX Range 0 Vref 26
8091 11:47:16.357476
8092 11:47:16.357539 ==
8093 11:47:16.360645 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 11:47:16.363558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 11:47:16.363653 ==
8096 11:47:16.363728
8097 11:47:16.363785
8098 11:47:16.367318 TX Vref Scan disable
8099 11:47:16.373769 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8100 11:47:16.373859 == TX Byte 0 ==
8101 11:47:16.376782 u2DelayCellOfst[0]=13 cells (4 PI)
8102 11:47:16.380626 u2DelayCellOfst[1]=17 cells (5 PI)
8103 11:47:16.383924 u2DelayCellOfst[2]=10 cells (3 PI)
8104 11:47:16.387160 u2DelayCellOfst[3]=6 cells (2 PI)
8105 11:47:16.390466 u2DelayCellOfst[4]=6 cells (2 PI)
8106 11:47:16.393802 u2DelayCellOfst[5]=0 cells (0 PI)
8107 11:47:16.397128 u2DelayCellOfst[6]=17 cells (5 PI)
8108 11:47:16.400368 u2DelayCellOfst[7]=13 cells (4 PI)
8109 11:47:16.403745 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8110 11:47:16.406910 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8111 11:47:16.406992 == TX Byte 1 ==
8112 11:47:16.410099 u2DelayCellOfst[8]=0 cells (0 PI)
8113 11:47:16.413883 u2DelayCellOfst[9]=0 cells (0 PI)
8114 11:47:16.417123 u2DelayCellOfst[10]=3 cells (1 PI)
8115 11:47:16.420528 u2DelayCellOfst[11]=0 cells (0 PI)
8116 11:47:16.423789 u2DelayCellOfst[12]=6 cells (2 PI)
8117 11:47:16.427128 u2DelayCellOfst[13]=6 cells (2 PI)
8118 11:47:16.430399 u2DelayCellOfst[14]=13 cells (4 PI)
8119 11:47:16.433523 u2DelayCellOfst[15]=6 cells (2 PI)
8120 11:47:16.436658 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8121 11:47:16.440335 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8122 11:47:16.443761 DramC Write-DBI on
8123 11:47:16.443859 ==
8124 11:47:16.447145 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 11:47:16.449885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 11:47:16.449985 ==
8127 11:47:16.450050
8128 11:47:16.454010
8129 11:47:16.454107 TX Vref Scan disable
8130 11:47:16.456460 == TX Byte 0 ==
8131 11:47:16.460231 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8132 11:47:16.463456 == TX Byte 1 ==
8133 11:47:16.466526 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8134 11:47:16.466607 DramC Write-DBI off
8135 11:47:16.469766
8136 11:47:16.469863 [DATLAT]
8137 11:47:16.469943 Freq=1600, CH0 RK1
8138 11:47:16.470061
8139 11:47:16.473084 DATLAT Default: 0xf
8140 11:47:16.473193 0, 0xFFFF, sum = 0
8141 11:47:16.476575 1, 0xFFFF, sum = 0
8142 11:47:16.476679 2, 0xFFFF, sum = 0
8143 11:47:16.480217 3, 0xFFFF, sum = 0
8144 11:47:16.480301 4, 0xFFFF, sum = 0
8145 11:47:16.483513 5, 0xFFFF, sum = 0
8146 11:47:16.486611 6, 0xFFFF, sum = 0
8147 11:47:16.486714 7, 0xFFFF, sum = 0
8148 11:47:16.490059 8, 0xFFFF, sum = 0
8149 11:47:16.490183 9, 0xFFFF, sum = 0
8150 11:47:16.492851 10, 0xFFFF, sum = 0
8151 11:47:16.492970 11, 0xFFFF, sum = 0
8152 11:47:16.496296 12, 0xFFFF, sum = 0
8153 11:47:16.496410 13, 0xFFFF, sum = 0
8154 11:47:16.499638 14, 0x0, sum = 1
8155 11:47:16.499743 15, 0x0, sum = 2
8156 11:47:16.502919 16, 0x0, sum = 3
8157 11:47:16.503026 17, 0x0, sum = 4
8158 11:47:16.506500 best_step = 15
8159 11:47:16.506608
8160 11:47:16.506732 ==
8161 11:47:16.509826 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 11:47:16.513137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 11:47:16.513212 ==
8164 11:47:16.513275 RX Vref Scan: 0
8165 11:47:16.516239
8166 11:47:16.516319 RX Vref 0 -> 0, step: 1
8167 11:47:16.516382
8168 11:47:16.519444 RX Delay 19 -> 252, step: 4
8169 11:47:16.522815 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8170 11:47:16.529324 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8171 11:47:16.533172 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8172 11:47:16.536178 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8173 11:47:16.539336 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8174 11:47:16.542523 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8175 11:47:16.549672 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8176 11:47:16.552767 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8177 11:47:16.556031 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8178 11:47:16.559286 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8179 11:47:16.562532 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8180 11:47:16.569245 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8181 11:47:16.572453 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8182 11:47:16.576143 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8183 11:47:16.579250 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8184 11:47:16.582646 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8185 11:47:16.586080 ==
8186 11:47:16.589352 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 11:47:16.592708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 11:47:16.592786 ==
8189 11:47:16.592851 DQS Delay:
8190 11:47:16.596207 DQS0 = 0, DQS1 = 0
8191 11:47:16.596276 DQM Delay:
8192 11:47:16.599175 DQM0 = 134, DQM1 = 126
8193 11:47:16.599256 DQ Delay:
8194 11:47:16.602730 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8195 11:47:16.606128 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8196 11:47:16.609265 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8197 11:47:16.612457 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8198 11:47:16.612539
8199 11:47:16.612608
8200 11:47:16.612666
8201 11:47:16.616011 [DramC_TX_OE_Calibration] TA2
8202 11:47:16.619287 Original DQ_B0 (3 6) =30, OEN = 27
8203 11:47:16.622289 Original DQ_B1 (3 6) =30, OEN = 27
8204 11:47:16.626153 24, 0x0, End_B0=24 End_B1=24
8205 11:47:16.629373 25, 0x0, End_B0=25 End_B1=25
8206 11:47:16.629454 26, 0x0, End_B0=26 End_B1=26
8207 11:47:16.632817 27, 0x0, End_B0=27 End_B1=27
8208 11:47:16.635516 28, 0x0, End_B0=28 End_B1=28
8209 11:47:16.639345 29, 0x0, End_B0=29 End_B1=29
8210 11:47:16.639425 30, 0x0, End_B0=30 End_B1=30
8211 11:47:16.642466 31, 0x4141, End_B0=30 End_B1=30
8212 11:47:16.645816 Byte0 end_step=30 best_step=27
8213 11:47:16.649137 Byte1 end_step=30 best_step=27
8214 11:47:16.652472 Byte0 TX OE(2T, 0.5T) = (3, 3)
8215 11:47:16.655515 Byte1 TX OE(2T, 0.5T) = (3, 3)
8216 11:47:16.655593
8217 11:47:16.655661
8218 11:47:16.662531 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8219 11:47:16.665762 CH0 RK1: MR19=303, MR18=220B
8220 11:47:16.672868 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8221 11:47:16.676067 [RxdqsGatingPostProcess] freq 1600
8222 11:47:16.679345 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8223 11:47:16.682525 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 11:47:16.685815 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 11:47:16.688948 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 11:47:16.692857 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 11:47:16.696088 best DQS0 dly(2T, 0.5T) = (1, 1)
8228 11:47:16.699345 best DQS1 dly(2T, 0.5T) = (1, 1)
8229 11:47:16.702475 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8230 11:47:16.706038 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8231 11:47:16.709069 Pre-setting of DQS Precalculation
8232 11:47:16.712776 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8233 11:47:16.712860 ==
8234 11:47:16.715644 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 11:47:16.719082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 11:47:16.722801 ==
8237 11:47:16.726208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8238 11:47:16.729044 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8239 11:47:16.736068 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8240 11:47:16.742341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8241 11:47:16.749306 [CA 0] Center 42 (12~72) winsize 61
8242 11:47:16.752616 [CA 1] Center 42 (13~72) winsize 60
8243 11:47:16.755840 [CA 2] Center 39 (10~68) winsize 59
8244 11:47:16.759109 [CA 3] Center 38 (9~67) winsize 59
8245 11:47:16.762819 [CA 4] Center 38 (9~68) winsize 60
8246 11:47:16.766241 [CA 5] Center 37 (8~67) winsize 60
8247 11:47:16.766323
8248 11:47:16.769229 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8249 11:47:16.769309
8250 11:47:16.772890 [CATrainingPosCal] consider 1 rank data
8251 11:47:16.776228 u2DelayCellTimex100 = 285/100 ps
8252 11:47:16.782641 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8253 11:47:16.785852 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8254 11:47:16.789115 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8255 11:47:16.792481 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8256 11:47:16.796135 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8257 11:47:16.799304 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8258 11:47:16.799380
8259 11:47:16.802596 CA PerBit enable=1, Macro0, CA PI delay=37
8260 11:47:16.802679
8261 11:47:16.805896 [CBTSetCACLKResult] CA Dly = 37
8262 11:47:16.809086 CS Dly: 11 (0~42)
8263 11:47:16.812292 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8264 11:47:16.815609 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8265 11:47:16.815750 ==
8266 11:47:16.818915 Dram Type= 6, Freq= 0, CH_1, rank 1
8267 11:47:16.822673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 11:47:16.825933 ==
8269 11:47:16.829303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8270 11:47:16.832451 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8271 11:47:16.838997 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8272 11:47:16.842335 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8273 11:47:16.852639 [CA 0] Center 41 (12~71) winsize 60
8274 11:47:16.856121 [CA 1] Center 42 (12~72) winsize 61
8275 11:47:16.859382 [CA 2] Center 38 (9~68) winsize 60
8276 11:47:16.863061 [CA 3] Center 38 (8~68) winsize 61
8277 11:47:16.866009 [CA 4] Center 38 (8~68) winsize 61
8278 11:47:16.869478 [CA 5] Center 36 (7~66) winsize 60
8279 11:47:16.869591
8280 11:47:16.873072 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8281 11:47:16.873153
8282 11:47:16.876277 [CATrainingPosCal] consider 2 rank data
8283 11:47:16.879578 u2DelayCellTimex100 = 285/100 ps
8284 11:47:16.882630 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8285 11:47:16.889513 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8286 11:47:16.892710 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8287 11:47:16.895999 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8288 11:47:16.899836 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8289 11:47:16.902910 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8290 11:47:16.902983
8291 11:47:16.906334 CA PerBit enable=1, Macro0, CA PI delay=37
8292 11:47:16.906409
8293 11:47:16.909486 [CBTSetCACLKResult] CA Dly = 37
8294 11:47:16.912790 CS Dly: 12 (0~45)
8295 11:47:16.916371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8296 11:47:16.919697 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8297 11:47:16.919820
8298 11:47:16.923070 ----->DramcWriteLeveling(PI) begin...
8299 11:47:16.923147 ==
8300 11:47:16.926234 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 11:47:16.929436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 11:47:16.932681 ==
8303 11:47:16.932756 Write leveling (Byte 0): 27 => 27
8304 11:47:16.936063 Write leveling (Byte 1): 28 => 28
8305 11:47:16.939287 DramcWriteLeveling(PI) end<-----
8306 11:47:16.939366
8307 11:47:16.939430 ==
8308 11:47:16.942519 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 11:47:16.949028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 11:47:16.949109 ==
8311 11:47:16.952336 [Gating] SW mode calibration
8312 11:47:16.958935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8313 11:47:16.962757 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8314 11:47:16.969196 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 11:47:16.972286 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 11:47:16.975950 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8317 11:47:16.979556 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8318 11:47:16.986210 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 11:47:16.989524 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 11:47:16.992635 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 11:47:16.999135 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 11:47:17.002503 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 11:47:17.005705 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 11:47:17.012396 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8325 11:47:17.015545 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
8326 11:47:17.018808 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 11:47:17.026079 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 11:47:17.028954 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 11:47:17.032618 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 11:47:17.038694 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 11:47:17.042581 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:47:17.045786 1 6 8 | B1->B0 | 2525 3131 | 0 1 | (0 0) (0 0)
8333 11:47:17.052396 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8334 11:47:17.055506 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 11:47:17.058735 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 11:47:17.065354 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 11:47:17.068620 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 11:47:17.071843 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 11:47:17.078953 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 11:47:17.082239 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8341 11:47:17.085357 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8342 11:47:17.092052 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 11:47:17.095664 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 11:47:17.098785 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 11:47:17.105506 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 11:47:17.108782 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 11:47:17.112022 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 11:47:17.115469 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:47:17.122353 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:47:17.125793 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:47:17.128738 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:47:17.135495 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:47:17.138690 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:47:17.142246 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:47:17.148783 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:47:17.152524 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8357 11:47:17.155392 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8358 11:47:17.162137 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 11:47:17.162234 Total UI for P1: 0, mck2ui 16
8360 11:47:17.168475 best dqsien dly found for B0: ( 1, 9, 10)
8361 11:47:17.168592 Total UI for P1: 0, mck2ui 16
8362 11:47:17.175157 best dqsien dly found for B1: ( 1, 9, 10)
8363 11:47:17.178566 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8364 11:47:17.181909 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8365 11:47:17.182026
8366 11:47:17.184910 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8367 11:47:17.188332 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8368 11:47:17.192328 [Gating] SW calibration Done
8369 11:47:17.192406 ==
8370 11:47:17.195498 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 11:47:17.198680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 11:47:17.198798 ==
8373 11:47:17.201682 RX Vref Scan: 0
8374 11:47:17.201760
8375 11:47:17.201849 RX Vref 0 -> 0, step: 1
8376 11:47:17.201926
8377 11:47:17.205189 RX Delay 0 -> 252, step: 8
8378 11:47:17.208552 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8379 11:47:17.215189 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8380 11:47:17.218357 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8381 11:47:17.222139 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8382 11:47:17.225408 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8383 11:47:17.228503 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8384 11:47:17.234833 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8385 11:47:17.238147 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8386 11:47:17.241522 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8387 11:47:17.244998 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8388 11:47:17.248081 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8389 11:47:17.254646 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8390 11:47:17.258032 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8391 11:47:17.261770 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8392 11:47:17.264919 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8393 11:47:17.268196 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8394 11:47:17.271540 ==
8395 11:47:17.274620 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 11:47:17.278166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 11:47:17.278277 ==
8398 11:47:17.278344 DQS Delay:
8399 11:47:17.281418 DQS0 = 0, DQS1 = 0
8400 11:47:17.281492 DQM Delay:
8401 11:47:17.285072 DQM0 = 136, DQM1 = 133
8402 11:47:17.285159 DQ Delay:
8403 11:47:17.288048 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8404 11:47:17.291396 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8405 11:47:17.294592 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8406 11:47:17.298130 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8407 11:47:17.298209
8408 11:47:17.298292
8409 11:47:17.298387 ==
8410 11:47:17.301271 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 11:47:17.308072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 11:47:17.308187 ==
8413 11:47:17.308289
8414 11:47:17.308391
8415 11:47:17.308480 TX Vref Scan disable
8416 11:47:17.311502 == TX Byte 0 ==
8417 11:47:17.314722 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8418 11:47:17.318152 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8419 11:47:17.321401 == TX Byte 1 ==
8420 11:47:17.324880 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8421 11:47:17.328175 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8422 11:47:17.331561 ==
8423 11:47:17.335036 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 11:47:17.338155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 11:47:17.338243 ==
8426 11:47:17.350353
8427 11:47:17.353332 TX Vref early break, caculate TX vref
8428 11:47:17.357227 TX Vref=16, minBit 0, minWin=23, winSum=379
8429 11:47:17.360579 TX Vref=18, minBit 0, minWin=23, winSum=382
8430 11:47:17.363828 TX Vref=20, minBit 0, minWin=24, winSum=398
8431 11:47:17.367130 TX Vref=22, minBit 0, minWin=25, winSum=408
8432 11:47:17.370340 TX Vref=24, minBit 0, minWin=25, winSum=417
8433 11:47:17.376902 TX Vref=26, minBit 0, minWin=25, winSum=420
8434 11:47:17.380163 TX Vref=28, minBit 2, minWin=25, winSum=426
8435 11:47:17.383553 TX Vref=30, minBit 0, minWin=25, winSum=420
8436 11:47:17.386926 TX Vref=32, minBit 6, minWin=24, winSum=411
8437 11:47:17.390151 TX Vref=34, minBit 2, minWin=23, winSum=397
8438 11:47:17.396942 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 28
8439 11:47:17.397020
8440 11:47:17.399906 Final TX Range 0 Vref 28
8441 11:47:17.400007
8442 11:47:17.400096 ==
8443 11:47:17.403637 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 11:47:17.406631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 11:47:17.406730 ==
8446 11:47:17.406831
8447 11:47:17.406919
8448 11:47:17.410093 TX Vref Scan disable
8449 11:47:17.416670 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8450 11:47:17.416748 == TX Byte 0 ==
8451 11:47:17.420187 u2DelayCellOfst[0]=17 cells (5 PI)
8452 11:47:17.423181 u2DelayCellOfst[1]=10 cells (3 PI)
8453 11:47:17.426616 u2DelayCellOfst[2]=0 cells (0 PI)
8454 11:47:17.429683 u2DelayCellOfst[3]=6 cells (2 PI)
8455 11:47:17.432954 u2DelayCellOfst[4]=6 cells (2 PI)
8456 11:47:17.436578 u2DelayCellOfst[5]=17 cells (5 PI)
8457 11:47:17.439779 u2DelayCellOfst[6]=17 cells (5 PI)
8458 11:47:17.439886 u2DelayCellOfst[7]=6 cells (2 PI)
8459 11:47:17.446569 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8460 11:47:17.449848 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8461 11:47:17.449966 == TX Byte 1 ==
8462 11:47:17.453090 u2DelayCellOfst[8]=0 cells (0 PI)
8463 11:47:17.456270 u2DelayCellOfst[9]=3 cells (1 PI)
8464 11:47:17.459997 u2DelayCellOfst[10]=13 cells (4 PI)
8465 11:47:17.463116 u2DelayCellOfst[11]=6 cells (2 PI)
8466 11:47:17.466501 u2DelayCellOfst[12]=17 cells (5 PI)
8467 11:47:17.469796 u2DelayCellOfst[13]=17 cells (5 PI)
8468 11:47:17.473113 u2DelayCellOfst[14]=17 cells (5 PI)
8469 11:47:17.476545 u2DelayCellOfst[15]=17 cells (5 PI)
8470 11:47:17.479552 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8471 11:47:17.486845 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 11:47:17.486929 DramC Write-DBI on
8473 11:47:17.486994 ==
8474 11:47:17.490016 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 11:47:17.493273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 11:47:17.493356 ==
8477 11:47:17.493420
8478 11:47:17.496623
8479 11:47:17.496704 TX Vref Scan disable
8480 11:47:17.499825 == TX Byte 0 ==
8481 11:47:17.503121 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8482 11:47:17.506866 == TX Byte 1 ==
8483 11:47:17.509998 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8484 11:47:17.510129 DramC Write-DBI off
8485 11:47:17.510195
8486 11:47:17.513225 [DATLAT]
8487 11:47:17.513305 Freq=1600, CH1 RK0
8488 11:47:17.513369
8489 11:47:17.516587 DATLAT Default: 0xf
8490 11:47:17.516668 0, 0xFFFF, sum = 0
8491 11:47:17.519890 1, 0xFFFF, sum = 0
8492 11:47:17.519972 2, 0xFFFF, sum = 0
8493 11:47:17.523346 3, 0xFFFF, sum = 0
8494 11:47:17.523429 4, 0xFFFF, sum = 0
8495 11:47:17.526405 5, 0xFFFF, sum = 0
8496 11:47:17.526488 6, 0xFFFF, sum = 0
8497 11:47:17.529533 7, 0xFFFF, sum = 0
8498 11:47:17.529653 8, 0xFFFF, sum = 0
8499 11:47:17.532770 9, 0xFFFF, sum = 0
8500 11:47:17.536568 10, 0xFFFF, sum = 0
8501 11:47:17.536654 11, 0xFFFF, sum = 0
8502 11:47:17.539804 12, 0xFFFF, sum = 0
8503 11:47:17.539887 13, 0xFFFF, sum = 0
8504 11:47:17.543197 14, 0x0, sum = 1
8505 11:47:17.543282 15, 0x0, sum = 2
8506 11:47:17.546462 16, 0x0, sum = 3
8507 11:47:17.546545 17, 0x0, sum = 4
8508 11:47:17.546610 best_step = 15
8509 11:47:17.549548
8510 11:47:17.549656 ==
8511 11:47:17.552777 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 11:47:17.556433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 11:47:17.556515 ==
8514 11:47:17.556580 RX Vref Scan: 1
8515 11:47:17.556640
8516 11:47:17.559592 Set Vref Range= 24 -> 127
8517 11:47:17.559688
8518 11:47:17.563064 RX Vref 24 -> 127, step: 1
8519 11:47:17.563160
8520 11:47:17.566477 RX Delay 27 -> 252, step: 4
8521 11:47:17.566557
8522 11:47:17.569595 Set Vref, RX VrefLevel [Byte0]: 24
8523 11:47:17.573105 [Byte1]: 24
8524 11:47:17.573187
8525 11:47:17.576093 Set Vref, RX VrefLevel [Byte0]: 25
8526 11:47:17.579840 [Byte1]: 25
8527 11:47:17.579922
8528 11:47:17.583086 Set Vref, RX VrefLevel [Byte0]: 26
8529 11:47:17.586309 [Byte1]: 26
8530 11:47:17.589516
8531 11:47:17.589636 Set Vref, RX VrefLevel [Byte0]: 27
8532 11:47:17.592731 [Byte1]: 27
8533 11:47:17.597380
8534 11:47:17.597461 Set Vref, RX VrefLevel [Byte0]: 28
8535 11:47:17.600623 [Byte1]: 28
8536 11:47:17.604521
8537 11:47:17.604606 Set Vref, RX VrefLevel [Byte0]: 29
8538 11:47:17.607756 [Byte1]: 29
8539 11:47:17.612123
8540 11:47:17.612204 Set Vref, RX VrefLevel [Byte0]: 30
8541 11:47:17.615506 [Byte1]: 30
8542 11:47:17.619409
8543 11:47:17.619491 Set Vref, RX VrefLevel [Byte0]: 31
8544 11:47:17.623172 [Byte1]: 31
8545 11:47:17.626994
8546 11:47:17.627107 Set Vref, RX VrefLevel [Byte0]: 32
8547 11:47:17.630381 [Byte1]: 32
8548 11:47:17.634768
8549 11:47:17.634850 Set Vref, RX VrefLevel [Byte0]: 33
8550 11:47:17.638291 [Byte1]: 33
8551 11:47:17.642199
8552 11:47:17.642280 Set Vref, RX VrefLevel [Byte0]: 34
8553 11:47:17.645511 [Byte1]: 34
8554 11:47:17.649552
8555 11:47:17.649676 Set Vref, RX VrefLevel [Byte0]: 35
8556 11:47:17.653168 [Byte1]: 35
8557 11:47:17.657361
8558 11:47:17.657455 Set Vref, RX VrefLevel [Byte0]: 36
8559 11:47:17.660625 [Byte1]: 36
8560 11:47:17.665269
8561 11:47:17.665345 Set Vref, RX VrefLevel [Byte0]: 37
8562 11:47:17.668440 [Byte1]: 37
8563 11:47:17.672683
8564 11:47:17.672777 Set Vref, RX VrefLevel [Byte0]: 38
8565 11:47:17.675840 [Byte1]: 38
8566 11:47:17.679925
8567 11:47:17.680009 Set Vref, RX VrefLevel [Byte0]: 39
8568 11:47:17.683343 [Byte1]: 39
8569 11:47:17.687398
8570 11:47:17.687504 Set Vref, RX VrefLevel [Byte0]: 40
8571 11:47:17.690456 [Byte1]: 40
8572 11:47:17.694762
8573 11:47:17.694847 Set Vref, RX VrefLevel [Byte0]: 41
8574 11:47:17.698081 [Byte1]: 41
8575 11:47:17.702260
8576 11:47:17.702362 Set Vref, RX VrefLevel [Byte0]: 42
8577 11:47:17.705837 [Byte1]: 42
8578 11:47:17.710497
8579 11:47:17.710575 Set Vref, RX VrefLevel [Byte0]: 43
8580 11:47:17.713474 [Byte1]: 43
8581 11:47:17.717854
8582 11:47:17.717930 Set Vref, RX VrefLevel [Byte0]: 44
8583 11:47:17.721242 [Byte1]: 44
8584 11:47:17.724925
8585 11:47:17.724997 Set Vref, RX VrefLevel [Byte0]: 45
8586 11:47:17.728260 [Byte1]: 45
8587 11:47:17.732889
8588 11:47:17.732981 Set Vref, RX VrefLevel [Byte0]: 46
8589 11:47:17.735658 [Byte1]: 46
8590 11:47:17.740221
8591 11:47:17.740310 Set Vref, RX VrefLevel [Byte0]: 47
8592 11:47:17.743603 [Byte1]: 47
8593 11:47:17.747532
8594 11:47:17.747606 Set Vref, RX VrefLevel [Byte0]: 48
8595 11:47:17.751439 [Byte1]: 48
8596 11:47:17.755269
8597 11:47:17.755341 Set Vref, RX VrefLevel [Byte0]: 49
8598 11:47:17.758267 [Byte1]: 49
8599 11:47:17.762945
8600 11:47:17.763022 Set Vref, RX VrefLevel [Byte0]: 50
8601 11:47:17.766198 [Byte1]: 50
8602 11:47:17.770173
8603 11:47:17.770254 Set Vref, RX VrefLevel [Byte0]: 51
8604 11:47:17.773323 [Byte1]: 51
8605 11:47:17.777589
8606 11:47:17.777684 Set Vref, RX VrefLevel [Byte0]: 52
8607 11:47:17.781475 [Byte1]: 52
8608 11:47:17.785420
8609 11:47:17.785512 Set Vref, RX VrefLevel [Byte0]: 53
8610 11:47:17.788756 [Byte1]: 53
8611 11:47:17.792638
8612 11:47:17.792785 Set Vref, RX VrefLevel [Byte0]: 54
8613 11:47:17.796279 [Byte1]: 54
8614 11:47:17.800379
8615 11:47:17.800486 Set Vref, RX VrefLevel [Byte0]: 55
8616 11:47:17.803519 [Byte1]: 55
8617 11:47:17.808067
8618 11:47:17.808157 Set Vref, RX VrefLevel [Byte0]: 56
8619 11:47:17.811087 [Byte1]: 56
8620 11:47:17.815161
8621 11:47:17.815269 Set Vref, RX VrefLevel [Byte0]: 57
8622 11:47:17.818703 [Byte1]: 57
8623 11:47:17.823544
8624 11:47:17.823645 Set Vref, RX VrefLevel [Byte0]: 58
8625 11:47:17.826218 [Byte1]: 58
8626 11:47:17.830460
8627 11:47:17.830565 Set Vref, RX VrefLevel [Byte0]: 59
8628 11:47:17.833676 [Byte1]: 59
8629 11:47:17.838210
8630 11:47:17.838297 Set Vref, RX VrefLevel [Byte0]: 60
8631 11:47:17.841091 [Byte1]: 60
8632 11:47:17.845606
8633 11:47:17.845690 Set Vref, RX VrefLevel [Byte0]: 61
8634 11:47:17.848907 [Byte1]: 61
8635 11:47:17.853399
8636 11:47:17.853481 Set Vref, RX VrefLevel [Byte0]: 62
8637 11:47:17.856751 [Byte1]: 62
8638 11:47:17.860427
8639 11:47:17.860527 Set Vref, RX VrefLevel [Byte0]: 63
8640 11:47:17.863732 [Byte1]: 63
8641 11:47:17.868115
8642 11:47:17.868224 Set Vref, RX VrefLevel [Byte0]: 64
8643 11:47:17.871341 [Byte1]: 64
8644 11:47:17.875823
8645 11:47:17.875925 Set Vref, RX VrefLevel [Byte0]: 65
8646 11:47:17.879160 [Byte1]: 65
8647 11:47:17.883581
8648 11:47:17.883687 Set Vref, RX VrefLevel [Byte0]: 66
8649 11:47:17.886748 [Byte1]: 66
8650 11:47:17.890745
8651 11:47:17.890826 Set Vref, RX VrefLevel [Byte0]: 67
8652 11:47:17.893987 [Byte1]: 67
8653 11:47:17.898524
8654 11:47:17.898597 Set Vref, RX VrefLevel [Byte0]: 68
8655 11:47:17.904452 [Byte1]: 68
8656 11:47:17.904553
8657 11:47:17.907935 Set Vref, RX VrefLevel [Byte0]: 69
8658 11:47:17.911052 [Byte1]: 69
8659 11:47:17.911128
8660 11:47:17.914937 Set Vref, RX VrefLevel [Byte0]: 70
8661 11:47:17.917982 [Byte1]: 70
8662 11:47:17.918101
8663 11:47:17.921081 Set Vref, RX VrefLevel [Byte0]: 71
8664 11:47:17.924443 [Byte1]: 71
8665 11:47:17.928358
8666 11:47:17.928457 Set Vref, RX VrefLevel [Byte0]: 72
8667 11:47:17.932146 [Byte1]: 72
8668 11:47:17.935967
8669 11:47:17.936080 Set Vref, RX VrefLevel [Byte0]: 73
8670 11:47:17.939115 [Byte1]: 73
8671 11:47:17.943576
8672 11:47:17.943648 Set Vref, RX VrefLevel [Byte0]: 74
8673 11:47:17.947281 [Byte1]: 74
8674 11:47:17.951056
8675 11:47:17.951151 Final RX Vref Byte 0 = 57 to rank0
8676 11:47:17.954275 Final RX Vref Byte 1 = 59 to rank0
8677 11:47:17.957733 Final RX Vref Byte 0 = 57 to rank1
8678 11:47:17.961128 Final RX Vref Byte 1 = 59 to rank1==
8679 11:47:17.964084 Dram Type= 6, Freq= 0, CH_1, rank 0
8680 11:47:17.970818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8681 11:47:17.970914 ==
8682 11:47:17.970977 DQS Delay:
8683 11:47:17.974584 DQS0 = 0, DQS1 = 0
8684 11:47:17.974665 DQM Delay:
8685 11:47:17.974729 DQM0 = 134, DQM1 = 131
8686 11:47:17.977812 DQ Delay:
8687 11:47:17.980953 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8688 11:47:17.984288 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8689 11:47:17.987416 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8690 11:47:17.990534 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8691 11:47:17.990605
8692 11:47:17.990666
8693 11:47:17.990724
8694 11:47:17.993889 [DramC_TX_OE_Calibration] TA2
8695 11:47:17.997264 Original DQ_B0 (3 6) =30, OEN = 27
8696 11:47:18.001093 Original DQ_B1 (3 6) =30, OEN = 27
8697 11:47:18.004379 24, 0x0, End_B0=24 End_B1=24
8698 11:47:18.004447 25, 0x0, End_B0=25 End_B1=25
8699 11:47:18.007745 26, 0x0, End_B0=26 End_B1=26
8700 11:47:18.010984 27, 0x0, End_B0=27 End_B1=27
8701 11:47:18.014071 28, 0x0, End_B0=28 End_B1=28
8702 11:47:18.017130 29, 0x0, End_B0=29 End_B1=29
8703 11:47:18.017214 30, 0x0, End_B0=30 End_B1=30
8704 11:47:18.020619 31, 0x4141, End_B0=30 End_B1=30
8705 11:47:18.024345 Byte0 end_step=30 best_step=27
8706 11:47:18.027214 Byte1 end_step=30 best_step=27
8707 11:47:18.030927 Byte0 TX OE(2T, 0.5T) = (3, 3)
8708 11:47:18.034145 Byte1 TX OE(2T, 0.5T) = (3, 3)
8709 11:47:18.034228
8710 11:47:18.034294
8711 11:47:18.040611 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8712 11:47:18.043787 CH1 RK0: MR19=303, MR18=1725
8713 11:47:18.051028 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8714 11:47:18.051109
8715 11:47:18.054258 ----->DramcWriteLeveling(PI) begin...
8716 11:47:18.054359 ==
8717 11:47:18.057437 Dram Type= 6, Freq= 0, CH_1, rank 1
8718 11:47:18.060479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 11:47:18.060562 ==
8720 11:47:18.064304 Write leveling (Byte 0): 26 => 26
8721 11:47:18.067350 Write leveling (Byte 1): 29 => 29
8722 11:47:18.070447 DramcWriteLeveling(PI) end<-----
8723 11:47:18.070531
8724 11:47:18.070595 ==
8725 11:47:18.074319 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 11:47:18.077407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 11:47:18.077492 ==
8728 11:47:18.080445 [Gating] SW mode calibration
8729 11:47:18.086872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8730 11:47:18.093678 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8731 11:47:18.096821 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 11:47:18.100124 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 11:47:18.106724 1 4 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
8734 11:47:18.110017 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8735 11:47:18.113919 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 11:47:18.120313 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 11:47:18.123556 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 11:47:18.127176 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 11:47:18.133871 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 11:47:18.136886 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8741 11:47:18.140493 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
8742 11:47:18.146926 1 5 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8743 11:47:18.150298 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 11:47:18.153728 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 11:47:18.160435 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 11:47:18.163670 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 11:47:18.166960 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 11:47:18.173836 1 6 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8749 11:47:18.177173 1 6 8 | B1->B0 | 3838 2323 | 1 0 | (0 0) (0 0)
8750 11:47:18.180355 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8751 11:47:18.186815 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 11:47:18.190468 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 11:47:18.193766 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 11:47:18.200238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 11:47:18.203634 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 11:47:18.207017 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 11:47:18.210065 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8758 11:47:18.217119 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8759 11:47:18.220310 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8760 11:47:18.223335 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 11:47:18.230232 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 11:47:18.233285 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 11:47:18.237015 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 11:47:18.243324 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 11:47:18.246907 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:47:18.249856 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:47:18.256369 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 11:47:18.259611 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 11:47:18.263296 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 11:47:18.269562 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 11:47:18.272958 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 11:47:18.276759 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8773 11:47:18.283254 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8774 11:47:18.286458 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8775 11:47:18.289874 Total UI for P1: 0, mck2ui 16
8776 11:47:18.293207 best dqsien dly found for B1: ( 1, 9, 6)
8777 11:47:18.296571 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8778 11:47:18.303342 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 11:47:18.303420 Total UI for P1: 0, mck2ui 16
8780 11:47:18.309988 best dqsien dly found for B0: ( 1, 9, 14)
8781 11:47:18.313005 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8782 11:47:18.316973 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8783 11:47:18.317051
8784 11:47:18.319770 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8785 11:47:18.323144 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8786 11:47:18.326538 [Gating] SW calibration Done
8787 11:47:18.326624 ==
8788 11:47:18.329908 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 11:47:18.332681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 11:47:18.332756 ==
8791 11:47:18.336360 RX Vref Scan: 0
8792 11:47:18.336445
8793 11:47:18.336510 RX Vref 0 -> 0, step: 1
8794 11:47:18.336581
8795 11:47:18.339407 RX Delay 0 -> 252, step: 8
8796 11:47:18.343011 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8797 11:47:18.349504 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8798 11:47:18.353141 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8799 11:47:18.356124 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8800 11:47:18.359611 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8801 11:47:18.363044 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8802 11:47:18.369499 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8803 11:47:18.372904 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8804 11:47:18.376069 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8805 11:47:18.379431 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8806 11:47:18.382669 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8807 11:47:18.389657 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8808 11:47:18.392885 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8809 11:47:18.395583 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8810 11:47:18.399494 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8811 11:47:18.402740 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8812 11:47:18.405996 ==
8813 11:47:18.409251 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 11:47:18.412404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 11:47:18.412513 ==
8816 11:47:18.412583 DQS Delay:
8817 11:47:18.415715 DQS0 = 0, DQS1 = 0
8818 11:47:18.415794 DQM Delay:
8819 11:47:18.418793 DQM0 = 136, DQM1 = 133
8820 11:47:18.418892 DQ Delay:
8821 11:47:18.422117 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8822 11:47:18.425455 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8823 11:47:18.428808 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8824 11:47:18.432597 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8825 11:47:18.432706
8826 11:47:18.432802
8827 11:47:18.432901 ==
8828 11:47:18.435864 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 11:47:18.442644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 11:47:18.442732 ==
8831 11:47:18.442797
8832 11:47:18.442856
8833 11:47:18.442913 TX Vref Scan disable
8834 11:47:18.446247 == TX Byte 0 ==
8835 11:47:18.449096 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8836 11:47:18.456011 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8837 11:47:18.456096 == TX Byte 1 ==
8838 11:47:18.459273 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8839 11:47:18.465935 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8840 11:47:18.466019 ==
8841 11:47:18.469501 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 11:47:18.472787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 11:47:18.472869 ==
8844 11:47:18.484652
8845 11:47:18.488396 TX Vref early break, caculate TX vref
8846 11:47:18.491543 TX Vref=16, minBit 0, minWin=22, winSum=384
8847 11:47:18.494839 TX Vref=18, minBit 6, minWin=23, winSum=391
8848 11:47:18.498103 TX Vref=20, minBit 0, minWin=24, winSum=402
8849 11:47:18.501372 TX Vref=22, minBit 0, minWin=23, winSum=406
8850 11:47:18.504592 TX Vref=24, minBit 0, minWin=25, winSum=417
8851 11:47:18.511132 TX Vref=26, minBit 0, minWin=25, winSum=425
8852 11:47:18.514809 TX Vref=28, minBit 6, minWin=25, winSum=425
8853 11:47:18.518143 TX Vref=30, minBit 1, minWin=25, winSum=420
8854 11:47:18.521147 TX Vref=32, minBit 6, minWin=24, winSum=408
8855 11:47:18.524357 TX Vref=34, minBit 0, minWin=24, winSum=399
8856 11:47:18.531554 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8857 11:47:18.531637
8858 11:47:18.534740 Final TX Range 0 Vref 26
8859 11:47:18.534822
8860 11:47:18.534886 ==
8861 11:47:18.538103 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 11:47:18.541322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 11:47:18.541405 ==
8864 11:47:18.541470
8865 11:47:18.541529
8866 11:47:18.544564 TX Vref Scan disable
8867 11:47:18.550947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8868 11:47:18.551036 == TX Byte 0 ==
8869 11:47:18.554304 u2DelayCellOfst[0]=17 cells (5 PI)
8870 11:47:18.558200 u2DelayCellOfst[1]=10 cells (3 PI)
8871 11:47:18.561320 u2DelayCellOfst[2]=0 cells (0 PI)
8872 11:47:18.564413 u2DelayCellOfst[3]=6 cells (2 PI)
8873 11:47:18.567839 u2DelayCellOfst[4]=6 cells (2 PI)
8874 11:47:18.571218 u2DelayCellOfst[5]=17 cells (5 PI)
8875 11:47:18.574645 u2DelayCellOfst[6]=20 cells (6 PI)
8876 11:47:18.574726 u2DelayCellOfst[7]=6 cells (2 PI)
8877 11:47:18.581168 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8878 11:47:18.584445 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8879 11:47:18.584527 == TX Byte 1 ==
8880 11:47:18.587638 u2DelayCellOfst[8]=0 cells (0 PI)
8881 11:47:18.590954 u2DelayCellOfst[9]=6 cells (2 PI)
8882 11:47:18.594529 u2DelayCellOfst[10]=13 cells (4 PI)
8883 11:47:18.597619 u2DelayCellOfst[11]=6 cells (2 PI)
8884 11:47:18.601162 u2DelayCellOfst[12]=17 cells (5 PI)
8885 11:47:18.604687 u2DelayCellOfst[13]=17 cells (5 PI)
8886 11:47:18.607897 u2DelayCellOfst[14]=20 cells (6 PI)
8887 11:47:18.611275 u2DelayCellOfst[15]=20 cells (6 PI)
8888 11:47:18.614639 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8889 11:47:18.621111 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8890 11:47:18.621194 DramC Write-DBI on
8891 11:47:18.621258 ==
8892 11:47:18.624320 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 11:47:18.627571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 11:47:18.627657 ==
8895 11:47:18.630783
8896 11:47:18.630864
8897 11:47:18.630928 TX Vref Scan disable
8898 11:47:18.634047 == TX Byte 0 ==
8899 11:47:18.637380 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8900 11:47:18.640737 == TX Byte 1 ==
8901 11:47:18.644101 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8902 11:47:18.644184 DramC Write-DBI off
8903 11:47:18.647312
8904 11:47:18.647394 [DATLAT]
8905 11:47:18.647458 Freq=1600, CH1 RK1
8906 11:47:18.647517
8907 11:47:18.651256 DATLAT Default: 0xf
8908 11:47:18.651341 0, 0xFFFF, sum = 0
8909 11:47:18.654271 1, 0xFFFF, sum = 0
8910 11:47:18.654353 2, 0xFFFF, sum = 0
8911 11:47:18.657532 3, 0xFFFF, sum = 0
8912 11:47:18.660898 4, 0xFFFF, sum = 0
8913 11:47:18.660981 5, 0xFFFF, sum = 0
8914 11:47:18.664018 6, 0xFFFF, sum = 0
8915 11:47:18.664101 7, 0xFFFF, sum = 0
8916 11:47:18.667476 8, 0xFFFF, sum = 0
8917 11:47:18.667559 9, 0xFFFF, sum = 0
8918 11:47:18.670620 10, 0xFFFF, sum = 0
8919 11:47:18.670702 11, 0xFFFF, sum = 0
8920 11:47:18.673803 12, 0xFFFF, sum = 0
8921 11:47:18.673886 13, 0xFFFF, sum = 0
8922 11:47:18.677035 14, 0x0, sum = 1
8923 11:47:18.677111 15, 0x0, sum = 2
8924 11:47:18.680455 16, 0x0, sum = 3
8925 11:47:18.680525 17, 0x0, sum = 4
8926 11:47:18.684075 best_step = 15
8927 11:47:18.684156
8928 11:47:18.684229 ==
8929 11:47:18.687119 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:47:18.690324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:47:18.690406 ==
8932 11:47:18.690470 RX Vref Scan: 0
8933 11:47:18.694119
8934 11:47:18.694199 RX Vref 0 -> 0, step: 1
8935 11:47:18.694264
8936 11:47:18.697393 RX Delay 19 -> 252, step: 4
8937 11:47:18.700525 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8938 11:47:18.707102 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8939 11:47:18.710534 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8940 11:47:18.714047 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8941 11:47:18.717040 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8942 11:47:18.720142 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8943 11:47:18.723831 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8944 11:47:18.730298 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8945 11:47:18.733726 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8946 11:47:18.737300 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8947 11:47:18.740662 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8948 11:47:18.743775 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8949 11:47:18.750354 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8950 11:47:18.753766 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8951 11:47:18.756926 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8952 11:47:18.760174 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8953 11:47:18.760248 ==
8954 11:47:18.763317 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 11:47:18.770575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 11:47:18.770658 ==
8957 11:47:18.770722 DQS Delay:
8958 11:47:18.773899 DQS0 = 0, DQS1 = 0
8959 11:47:18.773981 DQM Delay:
8960 11:47:18.777042 DQM0 = 133, DQM1 = 130
8961 11:47:18.777123 DQ Delay:
8962 11:47:18.780273 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8963 11:47:18.783472 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8964 11:47:18.786614 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8965 11:47:18.789836 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8966 11:47:18.789922
8967 11:47:18.789987
8968 11:47:18.790047
8969 11:47:18.793503 [DramC_TX_OE_Calibration] TA2
8970 11:47:18.796696 Original DQ_B0 (3 6) =30, OEN = 27
8971 11:47:18.800450 Original DQ_B1 (3 6) =30, OEN = 27
8972 11:47:18.803536 24, 0x0, End_B0=24 End_B1=24
8973 11:47:18.806790 25, 0x0, End_B0=25 End_B1=25
8974 11:47:18.806876 26, 0x0, End_B0=26 End_B1=26
8975 11:47:18.810151 27, 0x0, End_B0=27 End_B1=27
8976 11:47:18.813453 28, 0x0, End_B0=28 End_B1=28
8977 11:47:18.816725 29, 0x0, End_B0=29 End_B1=29
8978 11:47:18.816808 30, 0x0, End_B0=30 End_B1=30
8979 11:47:18.819973 31, 0x4141, End_B0=30 End_B1=30
8980 11:47:18.823864 Byte0 end_step=30 best_step=27
8981 11:47:18.826858 Byte1 end_step=30 best_step=27
8982 11:47:18.830331 Byte0 TX OE(2T, 0.5T) = (3, 3)
8983 11:47:18.833759 Byte1 TX OE(2T, 0.5T) = (3, 3)
8984 11:47:18.833842
8985 11:47:18.833906
8986 11:47:18.839962 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8987 11:47:18.843241 CH1 RK1: MR19=303, MR18=2308
8988 11:47:18.850024 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
8989 11:47:18.853299 [RxdqsGatingPostProcess] freq 1600
8990 11:47:18.856581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8991 11:47:18.860168 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 11:47:18.863351 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 11:47:18.867053 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 11:47:18.870495 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 11:47:18.873734 best DQS0 dly(2T, 0.5T) = (1, 1)
8996 11:47:18.876923 best DQS1 dly(2T, 0.5T) = (1, 1)
8997 11:47:18.880019 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8998 11:47:18.883488 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8999 11:47:18.886605 Pre-setting of DQS Precalculation
9000 11:47:18.889921 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9001 11:47:18.896419 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9002 11:47:18.906360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9003 11:47:18.906444
9004 11:47:18.906506
9005 11:47:18.906564 [Calibration Summary] 3200 Mbps
9006 11:47:18.910049 CH 0, Rank 0
9007 11:47:18.910129 SW Impedance : PASS
9008 11:47:18.913344 DUTY Scan : NO K
9009 11:47:18.916602 ZQ Calibration : PASS
9010 11:47:18.916682 Jitter Meter : NO K
9011 11:47:18.919642 CBT Training : PASS
9012 11:47:18.923496 Write leveling : PASS
9013 11:47:18.923576 RX DQS gating : PASS
9014 11:47:18.926857 RX DQ/DQS(RDDQC) : PASS
9015 11:47:18.929516 TX DQ/DQS : PASS
9016 11:47:18.929619 RX DATLAT : PASS
9017 11:47:18.933472 RX DQ/DQS(Engine): PASS
9018 11:47:18.936788 TX OE : PASS
9019 11:47:18.936868 All Pass.
9020 11:47:18.936931
9021 11:47:18.936989 CH 0, Rank 1
9022 11:47:18.939910 SW Impedance : PASS
9023 11:47:18.942993 DUTY Scan : NO K
9024 11:47:18.943103 ZQ Calibration : PASS
9025 11:47:18.946226 Jitter Meter : NO K
9026 11:47:18.949719 CBT Training : PASS
9027 11:47:18.949799 Write leveling : PASS
9028 11:47:18.952854 RX DQS gating : PASS
9029 11:47:18.956596 RX DQ/DQS(RDDQC) : PASS
9030 11:47:18.956676 TX DQ/DQS : PASS
9031 11:47:18.959887 RX DATLAT : PASS
9032 11:47:18.959983 RX DQ/DQS(Engine): PASS
9033 11:47:18.962841 TX OE : PASS
9034 11:47:18.962921 All Pass.
9035 11:47:18.962984
9036 11:47:18.966752 CH 1, Rank 0
9037 11:47:18.966831 SW Impedance : PASS
9038 11:47:18.970024 DUTY Scan : NO K
9039 11:47:18.973487 ZQ Calibration : PASS
9040 11:47:18.973568 Jitter Meter : NO K
9041 11:47:18.976684 CBT Training : PASS
9042 11:47:18.980126 Write leveling : PASS
9043 11:47:18.980247 RX DQS gating : PASS
9044 11:47:18.983018 RX DQ/DQS(RDDQC) : PASS
9045 11:47:18.986180 TX DQ/DQS : PASS
9046 11:47:18.986254 RX DATLAT : PASS
9047 11:47:18.989553 RX DQ/DQS(Engine): PASS
9048 11:47:18.992867 TX OE : PASS
9049 11:47:18.992948 All Pass.
9050 11:47:18.993037
9051 11:47:18.993103 CH 1, Rank 1
9052 11:47:18.996117 SW Impedance : PASS
9053 11:47:18.999484 DUTY Scan : NO K
9054 11:47:18.999564 ZQ Calibration : PASS
9055 11:47:19.002831 Jitter Meter : NO K
9056 11:47:19.005890 CBT Training : PASS
9057 11:47:19.005971 Write leveling : PASS
9058 11:47:19.009812 RX DQS gating : PASS
9059 11:47:19.012950 RX DQ/DQS(RDDQC) : PASS
9060 11:47:19.013030 TX DQ/DQS : PASS
9061 11:47:19.016008 RX DATLAT : PASS
9062 11:47:19.016088 RX DQ/DQS(Engine): PASS
9063 11:47:19.019202 TX OE : PASS
9064 11:47:19.019282 All Pass.
9065 11:47:19.019346
9066 11:47:19.023016 DramC Write-DBI on
9067 11:47:19.026229 PER_BANK_REFRESH: Hybrid Mode
9068 11:47:19.026310 TX_TRACKING: ON
9069 11:47:19.036017 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9070 11:47:19.042565 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9071 11:47:19.052707 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 11:47:19.055789 [FAST_K] Save calibration result to emmc
9073 11:47:19.055874 sync common calibartion params.
9074 11:47:19.058934 sync cbt_mode0:1, 1:1
9075 11:47:19.062700 dram_init: ddr_geometry: 2
9076 11:47:19.065780 dram_init: ddr_geometry: 2
9077 11:47:19.065863 dram_init: ddr_geometry: 2
9078 11:47:19.069385 0:dram_rank_size:100000000
9079 11:47:19.072615 1:dram_rank_size:100000000
9080 11:47:19.076141 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9081 11:47:19.079111 DFS_SHUFFLE_HW_MODE: ON
9082 11:47:19.082469 dramc_set_vcore_voltage set vcore to 725000
9083 11:47:19.085915 Read voltage for 1600, 0
9084 11:47:19.085997 Vio18 = 0
9085 11:47:19.089338 Vcore = 725000
9086 11:47:19.089420 Vdram = 0
9087 11:47:19.089484 Vddq = 0
9088 11:47:19.089544 Vmddr = 0
9089 11:47:19.092645 switch to 3200 Mbps bootup
9090 11:47:19.095994 [DramcRunTimeConfig]
9091 11:47:19.096077 PHYPLL
9092 11:47:19.096142 DPM_CONTROL_AFTERK: ON
9093 11:47:19.099315 PER_BANK_REFRESH: ON
9094 11:47:19.102675 REFRESH_OVERHEAD_REDUCTION: ON
9095 11:47:19.106185 CMD_PICG_NEW_MODE: OFF
9096 11:47:19.106268 XRTWTW_NEW_MODE: ON
9097 11:47:19.109479 XRTRTR_NEW_MODE: ON
9098 11:47:19.109560 TX_TRACKING: ON
9099 11:47:19.112495 RDSEL_TRACKING: OFF
9100 11:47:19.112576 DQS Precalculation for DVFS: ON
9101 11:47:19.115843 RX_TRACKING: OFF
9102 11:47:19.115925 HW_GATING DBG: ON
9103 11:47:19.119450 ZQCS_ENABLE_LP4: ON
9104 11:47:19.119532 RX_PICG_NEW_MODE: ON
9105 11:47:19.122525 TX_PICG_NEW_MODE: ON
9106 11:47:19.126140 ENABLE_RX_DCM_DPHY: ON
9107 11:47:19.129328 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9108 11:47:19.129409 DUMMY_READ_FOR_TRACKING: OFF
9109 11:47:19.132617 !!! SPM_CONTROL_AFTERK: OFF
9110 11:47:19.135796 !!! SPM could not control APHY
9111 11:47:19.139092 IMPEDANCE_TRACKING: ON
9112 11:47:19.139176 TEMP_SENSOR: ON
9113 11:47:19.142352 HW_SAVE_FOR_SR: OFF
9114 11:47:19.142431 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9115 11:47:19.149609 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9116 11:47:19.149729 Read ODT Tracking: ON
9117 11:47:19.152673 Refresh Rate DeBounce: ON
9118 11:47:19.152757 DFS_NO_QUEUE_FLUSH: ON
9119 11:47:19.155799 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9120 11:47:19.159461 ENABLE_DFS_RUNTIME_MRW: OFF
9121 11:47:19.162815 DDR_RESERVE_NEW_MODE: ON
9122 11:47:19.162896 MR_CBT_SWITCH_FREQ: ON
9123 11:47:19.165826 =========================
9124 11:47:19.185265 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9125 11:47:19.188599 dram_init: ddr_geometry: 2
9126 11:47:19.206643 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9127 11:47:19.210077 dram_init: dram init end (result: 0)
9128 11:47:19.216607 DRAM-K: Full calibration passed in 24427 msecs
9129 11:47:19.220125 MRC: failed to locate region type 0.
9130 11:47:19.220206 DRAM rank0 size:0x100000000,
9131 11:47:19.223575 DRAM rank1 size=0x100000000
9132 11:47:19.233706 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9133 11:47:19.240334 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9134 11:47:19.246809 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9135 11:47:19.253192 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9136 11:47:19.257140 DRAM rank0 size:0x100000000,
9137 11:47:19.260368 DRAM rank1 size=0x100000000
9138 11:47:19.260449 CBMEM:
9139 11:47:19.263381 IMD: root @ 0xfffff000 254 entries.
9140 11:47:19.266805 IMD: root @ 0xffffec00 62 entries.
9141 11:47:19.269964 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9142 11:47:19.273160 WARNING: RO_VPD is uninitialized or empty.
9143 11:47:19.279634 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9144 11:47:19.286913 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9145 11:47:19.299509 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9146 11:47:19.310960 BS: romstage times (exec / console): total (unknown) / 23968 ms
9147 11:47:19.311057
9148 11:47:19.311119
9149 11:47:19.320928 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9150 11:47:19.324065 ARM64: Exception handlers installed.
9151 11:47:19.327426 ARM64: Testing exception
9152 11:47:19.331251 ARM64: Done test exception
9153 11:47:19.331332 Enumerating buses...
9154 11:47:19.334312 Show all devs... Before device enumeration.
9155 11:47:19.337748 Root Device: enabled 1
9156 11:47:19.340813 CPU_CLUSTER: 0: enabled 1
9157 11:47:19.340895 CPU: 00: enabled 1
9158 11:47:19.344373 Compare with tree...
9159 11:47:19.344454 Root Device: enabled 1
9160 11:47:19.347220 CPU_CLUSTER: 0: enabled 1
9161 11:47:19.351128 CPU: 00: enabled 1
9162 11:47:19.351253 Root Device scanning...
9163 11:47:19.353832 scan_static_bus for Root Device
9164 11:47:19.357209 CPU_CLUSTER: 0 enabled
9165 11:47:19.361165 scan_static_bus for Root Device done
9166 11:47:19.364490 scan_bus: bus Root Device finished in 8 msecs
9167 11:47:19.364571 done
9168 11:47:19.371162 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9169 11:47:19.374078 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9170 11:47:19.380489 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9171 11:47:19.383785 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9172 11:47:19.387739 Allocating resources...
9173 11:47:19.390679 Reading resources...
9174 11:47:19.393885 Root Device read_resources bus 0 link: 0
9175 11:47:19.393967 DRAM rank0 size:0x100000000,
9176 11:47:19.396985 DRAM rank1 size=0x100000000
9177 11:47:19.400871 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9178 11:47:19.404076 CPU: 00 missing read_resources
9179 11:47:19.407356 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9180 11:47:19.413827 Root Device read_resources bus 0 link: 0 done
9181 11:47:19.413925 Done reading resources.
9182 11:47:19.420595 Show resources in subtree (Root Device)...After reading.
9183 11:47:19.423651 Root Device child on link 0 CPU_CLUSTER: 0
9184 11:47:19.427149 CPU_CLUSTER: 0 child on link 0 CPU: 00
9185 11:47:19.437286 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9186 11:47:19.437375 CPU: 00
9187 11:47:19.440562 Root Device assign_resources, bus 0 link: 0
9188 11:47:19.443720 CPU_CLUSTER: 0 missing set_resources
9189 11:47:19.449993 Root Device assign_resources, bus 0 link: 0 done
9190 11:47:19.450075 Done setting resources.
9191 11:47:19.457209 Show resources in subtree (Root Device)...After assigning values.
9192 11:47:19.460314 Root Device child on link 0 CPU_CLUSTER: 0
9193 11:47:19.463795 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 11:47:19.473556 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 11:47:19.473665 CPU: 00
9196 11:47:19.476807 Done allocating resources.
9197 11:47:19.479856 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9198 11:47:19.483496 Enabling resources...
9199 11:47:19.483576 done.
9200 11:47:19.489753 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9201 11:47:19.489861 Initializing devices...
9202 11:47:19.493498 Root Device init
9203 11:47:19.493646 init hardware done!
9204 11:47:19.496661 0x00000018: ctrlr->caps
9205 11:47:19.499612 52.000 MHz: ctrlr->f_max
9206 11:47:19.499730 0.400 MHz: ctrlr->f_min
9207 11:47:19.503238 0x40ff8080: ctrlr->voltages
9208 11:47:19.506459 sclk: 390625
9209 11:47:19.506560 Bus Width = 1
9210 11:47:19.506660 sclk: 390625
9211 11:47:19.509875 Bus Width = 1
9212 11:47:19.509957 Early init status = 3
9213 11:47:19.516359 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9214 11:47:19.519617 in-header: 03 fc 00 00 01 00 00 00
9215 11:47:19.522953 in-data: 00
9216 11:47:19.526145 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9217 11:47:19.531904 in-header: 03 fd 00 00 00 00 00 00
9218 11:47:19.535482 in-data:
9219 11:47:19.538456 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9220 11:47:19.542467 in-header: 03 fc 00 00 01 00 00 00
9221 11:47:19.546341 in-data: 00
9222 11:47:19.549370 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9223 11:47:19.554915 in-header: 03 fd 00 00 00 00 00 00
9224 11:47:19.558684 in-data:
9225 11:47:19.561310 [SSUSB] Setting up USB HOST controller...
9226 11:47:19.565212 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9227 11:47:19.568543 [SSUSB] phy power-on done.
9228 11:47:19.571854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9229 11:47:19.577881 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9230 11:47:19.581483 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9231 11:47:19.588070 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9232 11:47:19.594666 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9233 11:47:19.601525 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9234 11:47:19.607857 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9235 11:47:19.615084 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9236 11:47:19.618334 SPM: binary array size = 0x9dc
9237 11:47:19.621547 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9238 11:47:19.627939 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9239 11:47:19.634548 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9240 11:47:19.637770 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9241 11:47:19.644632 configure_display: Starting display init
9242 11:47:19.677894 anx7625_power_on_init: Init interface.
9243 11:47:19.681847 anx7625_disable_pd_protocol: Disabled PD feature.
9244 11:47:19.684463 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9245 11:47:19.712844 anx7625_start_dp_work: Secure OCM version=00
9246 11:47:19.716033 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9247 11:47:19.730446 sp_tx_get_edid_block: EDID Block = 1
9248 11:47:19.833414 Extracted contents:
9249 11:47:19.836549 header: 00 ff ff ff ff ff ff 00
9250 11:47:19.839880 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9251 11:47:19.843136 version: 01 04
9252 11:47:19.846529 basic params: 95 1f 11 78 0a
9253 11:47:19.850122 chroma info: 76 90 94 55 54 90 27 21 50 54
9254 11:47:19.853100 established: 00 00 00
9255 11:47:19.859607 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9256 11:47:19.863171 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9257 11:47:19.870059 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9258 11:47:19.876389 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9259 11:47:19.882953 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9260 11:47:19.886351 extensions: 00
9261 11:47:19.886432 checksum: fb
9262 11:47:19.886496
9263 11:47:19.889534 Manufacturer: IVO Model 57d Serial Number 0
9264 11:47:19.892914 Made week 0 of 2020
9265 11:47:19.893020 EDID version: 1.4
9266 11:47:19.896174 Digital display
9267 11:47:19.899423 6 bits per primary color channel
9268 11:47:19.899506 DisplayPort interface
9269 11:47:19.903122 Maximum image size: 31 cm x 17 cm
9270 11:47:19.906501 Gamma: 220%
9271 11:47:19.906582 Check DPMS levels
9272 11:47:19.909470 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9273 11:47:19.913150 First detailed timing is preferred timing
9274 11:47:19.916481 Established timings supported:
9275 11:47:19.919785 Standard timings supported:
9276 11:47:19.922748 Detailed timings
9277 11:47:19.926046 Hex of detail: 383680a07038204018303c0035ae10000019
9278 11:47:19.929965 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9279 11:47:19.935864 0780 0798 07c8 0820 hborder 0
9280 11:47:19.939826 0438 043b 0447 0458 vborder 0
9281 11:47:19.943129 -hsync -vsync
9282 11:47:19.943237 Did detailed timing
9283 11:47:19.946290 Hex of detail: 000000000000000000000000000000000000
9284 11:47:19.949694 Manufacturer-specified data, tag 0
9285 11:47:19.956372 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9286 11:47:19.956454 ASCII string: InfoVision
9287 11:47:19.962820 Hex of detail: 000000fe00523134304e574635205248200a
9288 11:47:19.965951 ASCII string: R140NWF5 RH
9289 11:47:19.966065 Checksum
9290 11:47:19.966129 Checksum: 0xfb (valid)
9291 11:47:19.972928 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9292 11:47:19.975808 DSI data_rate: 832800000 bps
9293 11:47:19.979408 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9294 11:47:19.986441 anx7625_parse_edid: pixelclock(138800).
9295 11:47:19.989385 hactive(1920), hsync(48), hfp(24), hbp(88)
9296 11:47:19.992567 vactive(1080), vsync(12), vfp(3), vbp(17)
9297 11:47:19.995866 anx7625_dsi_config: config dsi.
9298 11:47:20.002490 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9299 11:47:20.015195 anx7625_dsi_config: success to config DSI
9300 11:47:20.018473 anx7625_dp_start: MIPI phy setup OK.
9301 11:47:20.021521 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9302 11:47:20.024789 mtk_ddp_mode_set invalid vrefresh 60
9303 11:47:20.028463 main_disp_path_setup
9304 11:47:20.028588 ovl_layer_smi_id_en
9305 11:47:20.031791 ovl_layer_smi_id_en
9306 11:47:20.031871 ccorr_config
9307 11:47:20.031935 aal_config
9308 11:47:20.035065 gamma_config
9309 11:47:20.035144 postmask_config
9310 11:47:20.038321 dither_config
9311 11:47:20.041480 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9312 11:47:20.048177 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9313 11:47:20.051452 Root Device init finished in 555 msecs
9314 11:47:20.054779 CPU_CLUSTER: 0 init
9315 11:47:20.061880 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9316 11:47:20.065115 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9317 11:47:20.068288 APU_MBOX 0x190000b0 = 0x10001
9318 11:47:20.071378 APU_MBOX 0x190001b0 = 0x10001
9319 11:47:20.074863 APU_MBOX 0x190005b0 = 0x10001
9320 11:47:20.078448 APU_MBOX 0x190006b0 = 0x10001
9321 11:47:20.081545 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9322 11:47:20.093919 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9323 11:47:20.106867 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9324 11:47:20.113255 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9325 11:47:20.124845 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9326 11:47:20.134261 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9327 11:47:20.137356 CPU_CLUSTER: 0 init finished in 81 msecs
9328 11:47:20.140646 Devices initialized
9329 11:47:20.144008 Show all devs... After init.
9330 11:47:20.144088 Root Device: enabled 1
9331 11:47:20.147659 CPU_CLUSTER: 0: enabled 1
9332 11:47:20.150808 CPU: 00: enabled 1
9333 11:47:20.153845 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9334 11:47:20.157540 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9335 11:47:20.160976 ELOG: NV offset 0x57f000 size 0x1000
9336 11:47:20.167626 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9337 11:47:20.174203 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9338 11:47:20.177479 ELOG: Event(17) added with size 13 at 2023-11-24 11:45:08 UTC
9339 11:47:20.180682 out: cmd=0x121: 03 db 21 01 00 00 00 00
9340 11:47:20.184253 in-header: 03 fb 00 00 2c 00 00 00
9341 11:47:20.197980 in-data: 64 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 11:47:20.204072 ELOG: Event(A1) added with size 10 at 2023-11-24 11:45:08 UTC
9343 11:47:20.211094 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9344 11:47:20.214401 ELOG: Event(A0) added with size 9 at 2023-11-24 11:45:08 UTC
9345 11:47:20.221197 elog_add_boot_reason: Logged dev mode boot
9346 11:47:20.224466 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9347 11:47:20.227806 Finalize devices...
9348 11:47:20.227963 Devices finalized
9349 11:47:20.234203 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9350 11:47:20.237586 Writing coreboot table at 0xffe64000
9351 11:47:20.241266 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 11:47:20.244532 1. 0000000040000000-00000000400fffff: RAM
9353 11:47:20.247816 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 11:47:20.254086 3. 000000004032b000-00000000545fffff: RAM
9355 11:47:20.257816 4. 0000000054600000-000000005465ffff: BL31
9356 11:47:20.260954 5. 0000000054660000-00000000ffe63fff: RAM
9357 11:47:20.264894 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 11:47:20.271429 7. 0000000100000000-000000023fffffff: RAM
9359 11:47:20.271525 Passing 5 GPIOs to payload:
9360 11:47:20.277919 NAME | PORT | POLARITY | VALUE
9361 11:47:20.281153 EC in RW | 0x000000aa | low | undefined
9362 11:47:20.284285 EC interrupt | 0x00000005 | low | undefined
9363 11:47:20.290780 TPM interrupt | 0x000000ab | high | undefined
9364 11:47:20.294329 SD card detect | 0x00000011 | high | undefined
9365 11:47:20.301089 speaker enable | 0x00000093 | high | undefined
9366 11:47:20.304396 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 11:47:20.307684 in-header: 03 f9 00 00 02 00 00 00
9368 11:47:20.307812 in-data: 02 00
9369 11:47:20.311026 ADC[4]: Raw value=904726 ID=7
9370 11:47:20.314318 ADC[3]: Raw value=213441 ID=1
9371 11:47:20.314410 RAM Code: 0x71
9372 11:47:20.317371 ADC[6]: Raw value=75701 ID=0
9373 11:47:20.321118 ADC[5]: Raw value=212703 ID=1
9374 11:47:20.321261 SKU Code: 0x1
9375 11:47:20.327310 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2e6b
9376 11:47:20.331076 coreboot table: 964 bytes.
9377 11:47:20.334153 IMD ROOT 0. 0xfffff000 0x00001000
9378 11:47:20.337279 IMD SMALL 1. 0xffffe000 0x00001000
9379 11:47:20.340712 RO MCACHE 2. 0xffffc000 0x00001104
9380 11:47:20.344116 CONSOLE 3. 0xfff7c000 0x00080000
9381 11:47:20.347630 FMAP 4. 0xfff7b000 0x00000452
9382 11:47:20.350704 TIME STAMP 5. 0xfff7a000 0x00000910
9383 11:47:20.354011 VBOOT WORK 6. 0xfff66000 0x00014000
9384 11:47:20.357661 RAMOOPS 7. 0xffe66000 0x00100000
9385 11:47:20.360812 COREBOOT 8. 0xffe64000 0x00002000
9386 11:47:20.360948 IMD small region:
9387 11:47:20.363756 IMD ROOT 0. 0xffffec00 0x00000400
9388 11:47:20.367585 VPD 1. 0xffffeb80 0x0000006c
9389 11:47:20.370822 MMC STATUS 2. 0xffffeb60 0x00000004
9390 11:47:20.377333 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 11:47:20.380659 Probing TPM: done!
9392 11:47:20.383931 Connected to device vid:did:rid of 1ae0:0028:00
9393 11:47:20.394261 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9394 11:47:20.397420 Initialized TPM device CR50 revision 0
9395 11:47:20.397519 Checking cr50 for pending updates
9396 11:47:20.404604 Reading cr50 TPM mode
9397 11:47:20.412687 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9398 11:47:20.419293 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9399 11:47:20.459560 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9400 11:47:20.462938 Checking segment from ROM address 0x40100000
9401 11:47:20.466373 Checking segment from ROM address 0x4010001c
9402 11:47:20.473082 Loading segment from ROM address 0x40100000
9403 11:47:20.473186 code (compression=0)
9404 11:47:20.479657 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9405 11:47:20.489827 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9406 11:47:20.489948 it's not compressed!
9407 11:47:20.496501 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9408 11:47:20.499746 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9409 11:47:20.520177 Loading segment from ROM address 0x4010001c
9410 11:47:20.520285 Entry Point 0x80000000
9411 11:47:20.523444 Loaded segments
9412 11:47:20.526700 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9413 11:47:20.533638 Jumping to boot code at 0x80000000(0xffe64000)
9414 11:47:20.540061 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9415 11:47:20.546578 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9416 11:47:20.554447 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9417 11:47:20.557712 Checking segment from ROM address 0x40100000
9418 11:47:20.560843 Checking segment from ROM address 0x4010001c
9419 11:47:20.568081 Loading segment from ROM address 0x40100000
9420 11:47:20.568190 code (compression=1)
9421 11:47:20.574627 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9422 11:47:20.584765 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9423 11:47:20.584876 using LZMA
9424 11:47:20.592821 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9425 11:47:20.599637 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9426 11:47:20.602879 Loading segment from ROM address 0x4010001c
9427 11:47:20.602978 Entry Point 0x54601000
9428 11:47:20.606452 Loaded segments
9429 11:47:20.609769 NOTICE: MT8192 bl31_setup
9430 11:47:20.616535 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9431 11:47:20.619752 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9432 11:47:20.623244 WARNING: region 0:
9433 11:47:20.626661 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 11:47:20.626810 WARNING: region 1:
9435 11:47:20.633496 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9436 11:47:20.636728 WARNING: region 2:
9437 11:47:20.639937 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9438 11:47:20.643244 WARNING: region 3:
9439 11:47:20.646492 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 11:47:20.649664 WARNING: region 4:
9441 11:47:20.653445 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9442 11:47:20.656729 WARNING: region 5:
9443 11:47:20.660075 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 11:47:20.663284 WARNING: region 6:
9445 11:47:20.666529 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 11:47:20.666610 WARNING: region 7:
9447 11:47:20.673732 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 11:47:20.680269 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9449 11:47:20.683459 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9450 11:47:20.686786 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9451 11:47:20.690094 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9452 11:47:20.696608 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9453 11:47:20.700242 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9454 11:47:20.706805 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9455 11:47:20.710070 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9456 11:47:20.713723 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9457 11:47:20.719977 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9458 11:47:20.723548 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9459 11:47:20.727159 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9460 11:47:20.733685 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9461 11:47:20.736693 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9462 11:47:20.743663 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9463 11:47:20.746804 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9464 11:47:20.750532 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9465 11:47:20.757239 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9466 11:47:20.760209 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9467 11:47:20.763360 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9468 11:47:20.770193 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9469 11:47:20.773572 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9470 11:47:20.780169 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9471 11:47:20.783375 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9472 11:47:20.787385 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9473 11:47:20.793915 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9474 11:47:20.797158 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9475 11:47:20.803638 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9476 11:47:20.807268 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9477 11:47:20.810550 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9478 11:47:20.816927 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9479 11:47:20.820187 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9480 11:47:20.823849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9481 11:47:20.830488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9482 11:47:20.833680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9483 11:47:20.836972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9484 11:47:20.840389 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9485 11:47:20.846915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9486 11:47:20.850609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9487 11:47:20.853828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9488 11:47:20.856936 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9489 11:47:20.863861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9490 11:47:20.866888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9491 11:47:20.870574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9492 11:47:20.874004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9493 11:47:20.880398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9494 11:47:20.883663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9495 11:47:20.886733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9496 11:47:20.893322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9497 11:47:20.897092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9498 11:47:20.900348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9499 11:47:20.906832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9500 11:47:20.910072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9501 11:47:20.917199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9502 11:47:20.920427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9503 11:47:20.927074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9504 11:47:20.930271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9505 11:47:20.933758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9506 11:47:20.940278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9507 11:47:20.943422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9508 11:47:20.950086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9509 11:47:20.953418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9510 11:47:20.960420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9511 11:47:20.963627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9512 11:47:20.967039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9513 11:47:20.974059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9514 11:47:20.977135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9515 11:47:20.983744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9516 11:47:20.987121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9517 11:47:20.993963 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9518 11:47:20.996921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9519 11:47:21.000598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9520 11:47:21.006781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9521 11:47:21.010568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9522 11:47:21.016923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9523 11:47:21.020519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9524 11:47:21.026870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9525 11:47:21.030753 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9526 11:47:21.034109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9527 11:47:21.040605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9528 11:47:21.043881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9529 11:47:21.050607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9530 11:47:21.053769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9531 11:47:21.060269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9532 11:47:21.063496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9533 11:47:21.067311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9534 11:47:21.073831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9535 11:47:21.077091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9536 11:47:21.083664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9537 11:47:21.087017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9538 11:47:21.093594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9539 11:47:21.097481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9540 11:47:21.100681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9541 11:47:21.107417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9542 11:47:21.110172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9543 11:47:21.116801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9544 11:47:21.120722 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9545 11:47:21.123996 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9546 11:47:21.130516 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9547 11:47:21.133831 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9548 11:47:21.137394 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9549 11:47:21.140280 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9550 11:47:21.147080 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9551 11:47:21.150142 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9552 11:47:21.156717 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9553 11:47:21.160609 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9554 11:47:21.163626 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9555 11:47:21.170389 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9556 11:47:21.173956 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9557 11:47:21.180233 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9558 11:47:21.183830 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9559 11:47:21.186985 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9560 11:47:21.193449 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9561 11:47:21.197388 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9562 11:47:21.203862 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9563 11:47:21.207061 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9564 11:47:21.210325 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9565 11:47:21.216754 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9566 11:47:21.220638 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9567 11:47:21.223813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9568 11:47:21.227024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9569 11:47:21.230239 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9570 11:47:21.237274 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9571 11:47:21.240494 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9572 11:47:21.243777 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9573 11:47:21.250906 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9574 11:47:21.253849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9575 11:47:21.260707 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9576 11:47:21.263726 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9577 11:47:21.267480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9578 11:47:21.273598 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9579 11:47:21.277352 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9580 11:47:21.280433 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9581 11:47:21.286960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9582 11:47:21.290447 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9583 11:47:21.297125 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9584 11:47:21.300763 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9585 11:47:21.303960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9586 11:47:21.310592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9587 11:47:21.313798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9588 11:47:21.320340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9589 11:47:21.323702 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9590 11:47:21.327789 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9591 11:47:21.334225 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9592 11:47:21.337432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9593 11:47:21.340779 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9594 11:47:21.347345 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9595 11:47:21.350579 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9596 11:47:21.357293 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9597 11:47:21.360627 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9598 11:47:21.363834 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9599 11:47:21.370792 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9600 11:47:21.374494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9601 11:47:21.381147 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9602 11:47:21.384409 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9603 11:47:21.387607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9604 11:47:21.394569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9605 11:47:21.397272 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9606 11:47:21.400432 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9607 11:47:21.407201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9608 11:47:21.410507 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9609 11:47:21.417285 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9610 11:47:21.420623 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9611 11:47:21.424091 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9612 11:47:21.430720 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9613 11:47:21.433937 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9614 11:47:21.440525 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9615 11:47:21.443797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9616 11:47:21.447178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9617 11:47:21.454127 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9618 11:47:21.457178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9619 11:47:21.463754 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9620 11:47:21.467123 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9621 11:47:21.470403 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9622 11:47:21.477341 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9623 11:47:21.480441 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9624 11:47:21.483658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9625 11:47:21.490784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9626 11:47:21.494178 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9627 11:47:21.500381 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9628 11:47:21.503631 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9629 11:47:21.507417 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9630 11:47:21.514041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9631 11:47:21.517089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9632 11:47:21.523882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9633 11:47:21.527357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9634 11:47:21.530770 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9635 11:47:21.537344 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9636 11:47:21.540541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9637 11:47:21.543779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9638 11:47:21.550800 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9639 11:47:21.553797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9640 11:47:21.560635 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9641 11:47:21.563944 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9642 11:47:21.570358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9643 11:47:21.573542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9644 11:47:21.576799 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9645 11:47:21.583788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9646 11:47:21.586961 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9647 11:47:21.593567 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9648 11:47:21.596858 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9649 11:47:21.600255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9650 11:47:21.607003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9651 11:47:21.610286 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9652 11:47:21.617234 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9653 11:47:21.620566 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9654 11:47:21.626790 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9655 11:47:21.630722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9656 11:47:21.633821 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9657 11:47:21.640079 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9658 11:47:21.643892 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9659 11:47:21.650368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9660 11:47:21.653951 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9661 11:47:21.656763 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9662 11:47:21.663646 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9663 11:47:21.666756 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9664 11:47:21.673490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9665 11:47:21.676612 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9666 11:47:21.683720 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9667 11:47:21.686985 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9668 11:47:21.690111 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9669 11:47:21.696565 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9670 11:47:21.700364 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9671 11:47:21.706948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9672 11:47:21.710032 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9673 11:47:21.713148 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9674 11:47:21.719684 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9675 11:47:21.723003 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9676 11:47:21.729596 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9677 11:47:21.733388 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9678 11:47:21.736464 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9679 11:47:21.740051 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9680 11:47:21.746627 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9681 11:47:21.749730 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9682 11:47:21.752960 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9683 11:47:21.759531 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9684 11:47:21.763345 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9685 11:47:21.766585 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9686 11:47:21.773078 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9687 11:47:21.776192 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9688 11:47:21.779555 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9689 11:47:21.786215 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9690 11:47:21.789427 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9691 11:47:21.792903 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9692 11:47:21.799998 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9693 11:47:21.803266 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9694 11:47:21.809790 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9695 11:47:21.813047 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9696 11:47:21.816178 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9697 11:47:21.823194 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9698 11:47:21.826211 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9699 11:47:21.829619 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9700 11:47:21.836100 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9701 11:47:21.839570 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9702 11:47:21.843138 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9703 11:47:21.849266 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9704 11:47:21.852942 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9705 11:47:21.859391 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9706 11:47:21.863297 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9707 11:47:21.866229 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9708 11:47:21.872818 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9709 11:47:21.876090 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9710 11:47:21.879434 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9711 11:47:21.886540 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9712 11:47:21.889789 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9713 11:47:21.892770 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9714 11:47:21.899466 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9715 11:47:21.903098 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9716 11:47:21.906105 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9717 11:47:21.913146 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9718 11:47:21.916394 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9719 11:47:21.919694 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9720 11:47:21.922826 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9721 11:47:21.925809 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9722 11:47:21.932898 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9723 11:47:21.936286 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9724 11:47:21.939440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9725 11:47:21.945886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9726 11:47:21.949195 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9727 11:47:21.952545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9728 11:47:21.956285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9729 11:47:21.962683 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9730 11:47:21.965824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9731 11:47:21.972858 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9732 11:47:21.976202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9733 11:47:21.979178 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9734 11:47:21.985550 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9735 11:47:21.988841 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9736 11:47:21.996070 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9737 11:47:21.999354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9738 11:47:22.002401 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9739 11:47:22.008755 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9740 11:47:22.012674 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9741 11:47:22.018823 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9742 11:47:22.022303 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9743 11:47:22.029136 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9744 11:47:22.032171 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9745 11:47:22.035332 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9746 11:47:22.042302 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9747 11:47:22.045572 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9748 11:47:22.048905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9749 11:47:22.055489 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9750 11:47:22.058739 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9751 11:47:22.065186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9752 11:47:22.068393 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9753 11:47:22.075056 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9754 11:47:22.078596 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9755 11:47:22.081831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9756 11:47:22.088951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9757 11:47:22.091766 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9758 11:47:22.098665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9759 11:47:22.101823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9760 11:47:22.108690 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9761 11:47:22.111699 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9762 11:47:22.115509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9763 11:47:22.121934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9764 11:47:22.125217 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9765 11:47:22.128274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9766 11:47:22.134994 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9767 11:47:22.138681 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9768 11:47:22.145310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9769 11:47:22.148459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9770 11:47:22.151654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9771 11:47:22.158303 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9772 11:47:22.161498 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9773 11:47:22.168649 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9774 11:47:22.171871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9775 11:47:22.178448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9776 11:47:22.181534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9777 11:47:22.184697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9778 11:47:22.191800 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9779 11:47:22.195194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9780 11:47:22.201109 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9781 11:47:22.204922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9782 11:47:22.207833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9783 11:47:22.214693 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9784 11:47:22.217689 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9785 11:47:22.224579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9786 11:47:22.227938 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9787 11:47:22.231034 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9788 11:47:22.237863 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9789 11:47:22.241143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9790 11:47:22.247606 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9791 11:47:22.251383 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9792 11:47:22.257890 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9793 11:47:22.261075 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9794 11:47:22.264432 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9795 11:47:22.271281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9796 11:47:22.274559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9797 11:47:22.281043 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9798 11:47:22.284196 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9799 11:47:22.287830 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9800 11:47:22.294108 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9801 11:47:22.297392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9802 11:47:22.304058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9803 11:47:22.307350 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9804 11:47:22.311212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9805 11:47:22.317361 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9806 11:47:22.320873 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9807 11:47:22.327599 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9808 11:47:22.330639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9809 11:47:22.337289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9810 11:47:22.341011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9811 11:47:22.344215 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9812 11:47:22.350602 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9813 11:47:22.354531 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9814 11:47:22.360708 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9815 11:47:22.364331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9816 11:47:22.370513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9817 11:47:22.374171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9818 11:47:22.377394 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9819 11:47:22.383894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9820 11:47:22.387319 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9821 11:47:22.394337 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9822 11:47:22.397438 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9823 11:47:22.404216 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9824 11:47:22.407623 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9825 11:47:22.410788 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9826 11:47:22.417308 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9827 11:47:22.420539 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9828 11:47:22.427660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9829 11:47:22.430568 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9830 11:47:22.437111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9831 11:47:22.440668 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9832 11:47:22.447618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9833 11:47:22.450613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9834 11:47:22.453967 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9835 11:47:22.460442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9836 11:47:22.464451 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9837 11:47:22.470762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9838 11:47:22.473937 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9839 11:47:22.480351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9840 11:47:22.483890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9841 11:47:22.487309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9842 11:47:22.493699 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9843 11:47:22.497562 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9844 11:47:22.503991 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9845 11:47:22.507224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9846 11:47:22.513835 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9847 11:47:22.517078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9848 11:47:22.523549 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9849 11:47:22.526893 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9850 11:47:22.530518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9851 11:47:22.537035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9852 11:47:22.540177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9853 11:47:22.547157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9854 11:47:22.550142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9855 11:47:22.556831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9856 11:47:22.560262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9857 11:47:22.566709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9858 11:47:22.569853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9859 11:47:22.573154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9860 11:47:22.579814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9861 11:47:22.583506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9862 11:47:22.589735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9863 11:47:22.593219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9864 11:47:22.599833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9865 11:47:22.603708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9866 11:47:22.610248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9867 11:47:22.613385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9868 11:47:22.619976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9869 11:47:22.623265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9870 11:47:22.630362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9871 11:47:22.633498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9872 11:47:22.639688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9873 11:47:22.643457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9874 11:47:22.649848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9875 11:47:22.653354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9876 11:47:22.660017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9877 11:47:22.663010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9878 11:47:22.669514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9879 11:47:22.672876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9880 11:47:22.679688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9881 11:47:22.683461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9882 11:47:22.686871 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9883 11:47:22.690157 INFO: [APUAPC] vio 0
9884 11:47:22.696641 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9885 11:47:22.699763 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9886 11:47:22.703368 INFO: [APUAPC] D0_APC_0: 0x400510
9887 11:47:22.706867 INFO: [APUAPC] D0_APC_1: 0x0
9888 11:47:22.709728 INFO: [APUAPC] D0_APC_2: 0x1540
9889 11:47:22.712947 INFO: [APUAPC] D0_APC_3: 0x0
9890 11:47:22.716394 INFO: [APUAPC] D1_APC_0: 0xffffffff
9891 11:47:22.719530 INFO: [APUAPC] D1_APC_1: 0xffffffff
9892 11:47:22.723484 INFO: [APUAPC] D1_APC_2: 0x3fffff
9893 11:47:22.726730 INFO: [APUAPC] D1_APC_3: 0x0
9894 11:47:22.730030 INFO: [APUAPC] D2_APC_0: 0xffffffff
9895 11:47:22.733378 INFO: [APUAPC] D2_APC_1: 0xffffffff
9896 11:47:22.736602 INFO: [APUAPC] D2_APC_2: 0x3fffff
9897 11:47:22.736698 INFO: [APUAPC] D2_APC_3: 0x0
9898 11:47:22.742878 INFO: [APUAPC] D3_APC_0: 0xffffffff
9899 11:47:22.746498 INFO: [APUAPC] D3_APC_1: 0xffffffff
9900 11:47:22.749951 INFO: [APUAPC] D3_APC_2: 0x3fffff
9901 11:47:22.750034 INFO: [APUAPC] D3_APC_3: 0x0
9902 11:47:22.753229 INFO: [APUAPC] D4_APC_0: 0xffffffff
9903 11:47:22.756434 INFO: [APUAPC] D4_APC_1: 0xffffffff
9904 11:47:22.759692 INFO: [APUAPC] D4_APC_2: 0x3fffff
9905 11:47:22.762958 INFO: [APUAPC] D4_APC_3: 0x0
9906 11:47:22.766167 INFO: [APUAPC] D5_APC_0: 0xffffffff
9907 11:47:22.769514 INFO: [APUAPC] D5_APC_1: 0xffffffff
9908 11:47:22.773217 INFO: [APUAPC] D5_APC_2: 0x3fffff
9909 11:47:22.776160 INFO: [APUAPC] D5_APC_3: 0x0
9910 11:47:22.779743 INFO: [APUAPC] D6_APC_0: 0xffffffff
9911 11:47:22.783365 INFO: [APUAPC] D6_APC_1: 0xffffffff
9912 11:47:22.786395 INFO: [APUAPC] D6_APC_2: 0x3fffff
9913 11:47:22.789697 INFO: [APUAPC] D6_APC_3: 0x0
9914 11:47:22.793343 INFO: [APUAPC] D7_APC_0: 0xffffffff
9915 11:47:22.796547 INFO: [APUAPC] D7_APC_1: 0xffffffff
9916 11:47:22.799866 INFO: [APUAPC] D7_APC_2: 0x3fffff
9917 11:47:22.803047 INFO: [APUAPC] D7_APC_3: 0x0
9918 11:47:22.806152 INFO: [APUAPC] D8_APC_0: 0xffffffff
9919 11:47:22.809446 INFO: [APUAPC] D8_APC_1: 0xffffffff
9920 11:47:22.812777 INFO: [APUAPC] D8_APC_2: 0x3fffff
9921 11:47:22.816054 INFO: [APUAPC] D8_APC_3: 0x0
9922 11:47:22.819871 INFO: [APUAPC] D9_APC_0: 0xffffffff
9923 11:47:22.823044 INFO: [APUAPC] D9_APC_1: 0xffffffff
9924 11:47:22.825953 INFO: [APUAPC] D9_APC_2: 0x3fffff
9925 11:47:22.829517 INFO: [APUAPC] D9_APC_3: 0x0
9926 11:47:22.832973 INFO: [APUAPC] D10_APC_0: 0xffffffff
9927 11:47:22.836396 INFO: [APUAPC] D10_APC_1: 0xffffffff
9928 11:47:22.839659 INFO: [APUAPC] D10_APC_2: 0x3fffff
9929 11:47:22.842934 INFO: [APUAPC] D10_APC_3: 0x0
9930 11:47:22.846208 INFO: [APUAPC] D11_APC_0: 0xffffffff
9931 11:47:22.849342 INFO: [APUAPC] D11_APC_1: 0xffffffff
9932 11:47:22.852567 INFO: [APUAPC] D11_APC_2: 0x3fffff
9933 11:47:22.855588 INFO: [APUAPC] D11_APC_3: 0x0
9934 11:47:22.858685 INFO: [APUAPC] D12_APC_0: 0xffffffff
9935 11:47:22.862259 INFO: [APUAPC] D12_APC_1: 0xffffffff
9936 11:47:22.865470 INFO: [APUAPC] D12_APC_2: 0x3fffff
9937 11:47:22.868895 INFO: [APUAPC] D12_APC_3: 0x0
9938 11:47:22.872086 INFO: [APUAPC] D13_APC_0: 0xffffffff
9939 11:47:22.875421 INFO: [APUAPC] D13_APC_1: 0xffffffff
9940 11:47:22.878621 INFO: [APUAPC] D13_APC_2: 0x3fffff
9941 11:47:22.882141 INFO: [APUAPC] D13_APC_3: 0x0
9942 11:47:22.885361 INFO: [APUAPC] D14_APC_0: 0xffffffff
9943 11:47:22.888691 INFO: [APUAPC] D14_APC_1: 0xffffffff
9944 11:47:22.891789 INFO: [APUAPC] D14_APC_2: 0x3fffff
9945 11:47:22.895511 INFO: [APUAPC] D14_APC_3: 0x0
9946 11:47:22.898402 INFO: [APUAPC] D15_APC_0: 0xffffffff
9947 11:47:22.901721 INFO: [APUAPC] D15_APC_1: 0xffffffff
9948 11:47:22.905474 INFO: [APUAPC] D15_APC_2: 0x3fffff
9949 11:47:22.908314 INFO: [APUAPC] D15_APC_3: 0x0
9950 11:47:22.911648 INFO: [APUAPC] APC_CON: 0x4
9951 11:47:22.915348 INFO: [NOCDAPC] D0_APC_0: 0x0
9952 11:47:22.918591 INFO: [NOCDAPC] D0_APC_1: 0x0
9953 11:47:22.921797 INFO: [NOCDAPC] D1_APC_0: 0x0
9954 11:47:22.925114 INFO: [NOCDAPC] D1_APC_1: 0xfff
9955 11:47:22.928241 INFO: [NOCDAPC] D2_APC_0: 0x0
9956 11:47:22.928316 INFO: [NOCDAPC] D2_APC_1: 0xfff
9957 11:47:22.931382 INFO: [NOCDAPC] D3_APC_0: 0x0
9958 11:47:22.935244 INFO: [NOCDAPC] D3_APC_1: 0xfff
9959 11:47:22.938414 INFO: [NOCDAPC] D4_APC_0: 0x0
9960 11:47:22.941802 INFO: [NOCDAPC] D4_APC_1: 0xfff
9961 11:47:22.944827 INFO: [NOCDAPC] D5_APC_0: 0x0
9962 11:47:22.947836 INFO: [NOCDAPC] D5_APC_1: 0xfff
9963 11:47:22.951529 INFO: [NOCDAPC] D6_APC_0: 0x0
9964 11:47:22.954849 INFO: [NOCDAPC] D6_APC_1: 0xfff
9965 11:47:22.958235 INFO: [NOCDAPC] D7_APC_0: 0x0
9966 11:47:22.961420 INFO: [NOCDAPC] D7_APC_1: 0xfff
9967 11:47:22.961496 INFO: [NOCDAPC] D8_APC_0: 0x0
9968 11:47:22.964661 INFO: [NOCDAPC] D8_APC_1: 0xfff
9969 11:47:22.968157 INFO: [NOCDAPC] D9_APC_0: 0x0
9970 11:47:22.971702 INFO: [NOCDAPC] D9_APC_1: 0xfff
9971 11:47:22.974699 INFO: [NOCDAPC] D10_APC_0: 0x0
9972 11:47:22.977974 INFO: [NOCDAPC] D10_APC_1: 0xfff
9973 11:47:22.981485 INFO: [NOCDAPC] D11_APC_0: 0x0
9974 11:47:22.984475 INFO: [NOCDAPC] D11_APC_1: 0xfff
9975 11:47:22.988111 INFO: [NOCDAPC] D12_APC_0: 0x0
9976 11:47:22.991270 INFO: [NOCDAPC] D12_APC_1: 0xfff
9977 11:47:22.994564 INFO: [NOCDAPC] D13_APC_0: 0x0
9978 11:47:22.997826 INFO: [NOCDAPC] D13_APC_1: 0xfff
9979 11:47:23.001127 INFO: [NOCDAPC] D14_APC_0: 0x0
9980 11:47:23.004792 INFO: [NOCDAPC] D14_APC_1: 0xfff
9981 11:47:23.004868 INFO: [NOCDAPC] D15_APC_0: 0x0
9982 11:47:23.007933 INFO: [NOCDAPC] D15_APC_1: 0xfff
9983 11:47:23.011300 INFO: [NOCDAPC] APC_CON: 0x4
9984 11:47:23.014688 INFO: [APUAPC] set_apusys_apc done
9985 11:47:23.017713 INFO: [DEVAPC] devapc_init done
9986 11:47:23.024142 INFO: GICv3 without legacy support detected.
9987 11:47:23.027538 INFO: ARM GICv3 driver initialized in EL3
9988 11:47:23.030852 INFO: Maximum SPI INTID supported: 639
9989 11:47:23.034422 INFO: BL31: Initializing runtime services
9990 11:47:23.041022 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9991 11:47:23.044475 INFO: SPM: enable CPC mode
9992 11:47:23.047702 INFO: mcdi ready for mcusys-off-idle and system suspend
9993 11:47:23.054396 INFO: BL31: Preparing for EL3 exit to normal world
9994 11:47:23.057492 INFO: Entry point address = 0x80000000
9995 11:47:23.057640 INFO: SPSR = 0x8
9996 11:47:23.064261
9997 11:47:23.064350
9998 11:47:23.064424
9999 11:47:23.067636 Starting depthcharge on Spherion...
10000 11:47:23.067717
10001 11:47:23.067781 Wipe memory regions:
10002 11:47:23.067846
10003 11:47:23.068525 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10004 11:47:23.068633 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10005 11:47:23.068716 Setting prompt string to ['asurada:']
10006 11:47:23.068796 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10007 11:47:23.070799 [0x00000040000000, 0x00000054600000)
10008 11:47:23.193450
10009 11:47:23.193649 [0x00000054660000, 0x00000080000000)
10010 11:47:23.454000
10011 11:47:23.454175 [0x000000821a7280, 0x000000ffe64000)
10012 11:47:24.198777
10013 11:47:24.198990 [0x00000100000000, 0x00000240000000)
10014 11:47:26.088729
10015 11:47:26.092014 Initializing XHCI USB controller at 0x11200000.
10016 11:47:27.130357
10017 11:47:27.133461 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10018 11:47:27.133602
10019 11:47:27.133686
10020 11:47:27.133748
10021 11:47:27.134042 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 11:47:27.234358 asurada: tftpboot 192.168.201.1 12074018/tftp-deploy-i3e52gb4/kernel/image.itb 12074018/tftp-deploy-i3e52gb4/kernel/cmdline
10024 11:47:27.234529 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 11:47:27.234646 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10026 11:47:27.239482 tftpboot 192.168.201.1 12074018/tftp-deploy-i3e52gb4/kernel/image.ittp-deploy-i3e52gb4/kernel/cmdline
10027 11:47:27.239567
10028 11:47:27.239636 Waiting for link
10029 11:47:27.399722
10030 11:47:27.399893 R8152: Initializing
10031 11:47:27.399965
10032 11:47:27.402850 Version 9 (ocp_data = 6010)
10033 11:47:27.402933
10034 11:47:27.406574 R8152: Done initializing
10035 11:47:27.406654
10036 11:47:27.406720 Adding net device
10037 11:47:29.352284
10038 11:47:29.352464 done.
10039 11:47:29.352537
10040 11:47:29.352602 MAC: 00:e0:4c:78:7a:aa
10041 11:47:29.352662
10042 11:47:29.355586 Sending DHCP discover... done.
10043 11:47:29.355673
10044 11:47:29.358953 Waiting for reply... done.
10045 11:47:29.359039
10046 11:47:29.362190 Sending DHCP request... done.
10047 11:47:29.362270
10048 11:47:29.362335 Waiting for reply... done.
10049 11:47:29.362398
10050 11:47:29.365365 My ip is 192.168.201.12
10051 11:47:29.365482
10052 11:47:29.368539 The DHCP server ip is 192.168.201.1
10053 11:47:29.368634
10054 11:47:29.372162 TFTP server IP predefined by user: 192.168.201.1
10055 11:47:29.372241
10056 11:47:29.378167 Bootfile predefined by user: 12074018/tftp-deploy-i3e52gb4/kernel/image.itb
10057 11:47:29.378255
10058 11:47:29.381891 Sending tftp read request... done.
10059 11:47:29.381969
10060 11:47:29.385009 Waiting for the transfer...
10061 11:47:29.385094
10062 11:47:29.646441 00000000 ################################################################
10063 11:47:29.646581
10064 11:47:29.908035 00080000 ################################################################
10065 11:47:29.908234
10066 11:47:30.167655 00100000 ################################################################
10067 11:47:30.167798
10068 11:47:30.420268 00180000 ################################################################
10069 11:47:30.420429
10070 11:47:30.673557 00200000 ################################################################
10071 11:47:30.673732
10072 11:47:30.933141 00280000 ################################################################
10073 11:47:30.933281
10074 11:47:31.185373 00300000 ################################################################
10075 11:47:31.185515
10076 11:47:31.438044 00380000 ################################################################
10077 11:47:31.438180
10078 11:47:31.691081 00400000 ################################################################
10079 11:47:31.691226
10080 11:47:31.952395 00480000 ################################################################
10081 11:47:31.952567
10082 11:47:32.203605 00500000 ################################################################
10083 11:47:32.203752
10084 11:47:32.454631 00580000 ################################################################
10085 11:47:32.454772
10086 11:47:32.705186 00600000 ################################################################
10087 11:47:32.705329
10088 11:47:32.964922 00680000 ################################################################
10089 11:47:32.965070
10090 11:47:33.220318 00700000 ################################################################
10091 11:47:33.220467
10092 11:47:33.494663 00780000 ################################################################
10093 11:47:33.494822
10094 11:47:33.749942 00800000 ################################################################
10095 11:47:33.750109
10096 11:47:34.006755 00880000 ################################################################
10097 11:47:34.006887
10098 11:47:34.258458 00900000 ################################################################
10099 11:47:34.258635
10100 11:47:34.518209 00980000 ################################################################
10101 11:47:34.518348
10102 11:47:34.778628 00a00000 ################################################################
10103 11:47:34.778761
10104 11:47:35.028403 00a80000 ################################################################
10105 11:47:35.028544
10106 11:47:35.280186 00b00000 ################################################################
10107 11:47:35.280351
10108 11:47:35.530407 00b80000 ################################################################
10109 11:47:35.530538
10110 11:47:35.794571 00c00000 ################################################################
10111 11:47:35.794706
10112 11:47:36.075858 00c80000 ################################################################
10113 11:47:36.076006
10114 11:47:36.345280 00d00000 ################################################################
10115 11:47:36.345411
10116 11:47:36.597770 00d80000 ################################################################
10117 11:47:36.597900
10118 11:47:36.851583 00e00000 ################################################################
10119 11:47:36.851714
10120 11:47:37.103304 00e80000 ################################################################
10121 11:47:37.103434
10122 11:47:37.352714 00f00000 ################################################################
10123 11:47:37.352843
10124 11:47:37.604154 00f80000 ################################################################
10125 11:47:37.604282
10126 11:47:37.858610 01000000 ################################################################
10127 11:47:37.858742
10128 11:47:38.119577 01080000 ################################################################
10129 11:47:38.119708
10130 11:47:38.401765 01100000 ################################################################
10131 11:47:38.401898
10132 11:47:38.694709 01180000 ################################################################
10133 11:47:38.694850
10134 11:47:38.979402 01200000 ################################################################
10135 11:47:38.979573
10136 11:47:39.261305 01280000 ################################################################
10137 11:47:39.261446
10138 11:47:39.517470 01300000 ################################################################
10139 11:47:39.517627
10140 11:47:39.772439 01380000 ################################################################
10141 11:47:39.772588
10142 11:47:40.032372 01400000 ################################################################
10143 11:47:40.032513
10144 11:47:40.285977 01480000 ################################################################
10145 11:47:40.286140
10146 11:47:40.542564 01500000 ################################################################
10147 11:47:40.542727
10148 11:47:40.822236 01580000 ################################################################
10149 11:47:40.822399
10150 11:47:41.105660 01600000 ################################################################
10151 11:47:41.105799
10152 11:47:41.359334 01680000 ################################################################
10153 11:47:41.359515
10154 11:47:41.611519 01700000 ################################################################
10155 11:47:41.611659
10156 11:47:41.863598 01780000 ################################################################
10157 11:47:41.863733
10158 11:47:42.118930 01800000 ################################################################
10159 11:47:42.119089
10160 11:47:42.394275 01880000 ################################################################
10161 11:47:42.394430
10162 11:47:42.665339 01900000 ################################################################
10163 11:47:42.665468
10164 11:47:42.914596 01980000 ################################################################
10165 11:47:42.914760
10166 11:47:43.183566 01a00000 ################################################################
10167 11:47:43.183705
10168 11:47:43.450534 01a80000 ################################################################
10169 11:47:43.450701
10170 11:47:43.709091 01b00000 ################################################################
10171 11:47:43.709221
10172 11:47:43.960036 01b80000 ################################################################
10173 11:47:43.960205
10174 11:47:44.220935 01c00000 ################################################################
10175 11:47:44.221079
10176 11:47:44.482651 01c80000 ################################################################
10177 11:47:44.482794
10178 11:47:44.748356 01d00000 ################################################################
10179 11:47:44.748490
10180 11:47:45.011862 01d80000 ################################################################
10181 11:47:45.012025
10182 11:47:45.269476 01e00000 ################################################################
10183 11:47:45.269672
10184 11:47:45.523871 01e80000 ################################################################
10185 11:47:45.524033
10186 11:47:45.783549 01f00000 ################################################################
10187 11:47:45.783695
10188 11:47:46.038040 01f80000 ################################################################
10189 11:47:46.038178
10190 11:47:46.299407 02000000 ################################################################
10191 11:47:46.299580
10192 11:47:46.556022 02080000 ################################################################
10193 11:47:46.556201
10194 11:47:46.826472 02100000 ################################################################
10195 11:47:46.826602
10196 11:47:47.076178 02180000 ################################################################
10197 11:47:47.076333
10198 11:47:47.330046 02200000 ################################################################
10199 11:47:47.330181
10200 11:47:47.591190 02280000 ################################################################
10201 11:47:47.591339
10202 11:47:47.845687 02300000 ################################################################
10203 11:47:47.845817
10204 11:47:48.106517 02380000 ################################################################
10205 11:47:48.106649
10206 11:47:48.357229 02400000 ################################################################
10207 11:47:48.357365
10208 11:47:48.606420 02480000 ################################################################
10209 11:47:48.606554
10210 11:47:48.859349 02500000 ################################################################
10211 11:47:48.859486
10212 11:47:49.110459 02580000 ################################################################
10213 11:47:49.110594
10214 11:47:49.363389 02600000 ################################################################
10215 11:47:49.363525
10216 11:47:49.611818 02680000 ################################################################
10217 11:47:49.611954
10218 11:47:49.863337 02700000 ################################################################
10219 11:47:49.863474
10220 11:47:50.118337 02780000 ################################################################
10221 11:47:50.118473
10222 11:47:50.382796 02800000 ################################################################
10223 11:47:50.382929
10224 11:47:50.639691 02880000 ################################################################
10225 11:47:50.639857
10226 11:47:50.894617 02900000 ################################################################
10227 11:47:50.894758
10228 11:47:51.148476 02980000 ################################################################
10229 11:47:51.148612
10230 11:47:51.408168 02a00000 ################################################################
10231 11:47:51.408301
10232 11:47:51.667483 02a80000 ################################################################
10233 11:47:51.667621
10234 11:47:51.925142 02b00000 ################################################################
10235 11:47:51.925278
10236 11:47:52.181887 02b80000 ################################################################
10237 11:47:52.182021
10238 11:47:52.454878 02c00000 ################################################################
10239 11:47:52.455015
10240 11:47:52.708185 02c80000 ################################################################
10241 11:47:52.708348
10242 11:47:52.970362 02d00000 ################################################################
10243 11:47:52.970494
10244 11:47:53.232598 02d80000 ################################################################
10245 11:47:53.232732
10246 11:47:53.494530 02e00000 ################################################################
10247 11:47:53.494693
10248 11:47:53.749712 02e80000 ################################################################
10249 11:47:53.749863
10250 11:47:54.003126 02f00000 ################################################################
10251 11:47:54.003284
10252 11:47:54.258292 02f80000 ################################################################
10253 11:47:54.258430
10254 11:47:54.320528 03000000 ############### done.
10255 11:47:54.320661
10256 11:47:54.324089 The bootfile was 50451058 bytes long.
10257 11:47:54.324190
10258 11:47:54.327242 Sending tftp read request... done.
10259 11:47:54.327331
10260 11:47:54.330425 Waiting for the transfer...
10261 11:47:54.330523
10262 11:47:54.334036 00000000 # done.
10263 11:47:54.334131
10264 11:47:54.340460 Command line loaded dynamically from TFTP file: 12074018/tftp-deploy-i3e52gb4/kernel/cmdline
10265 11:47:54.340572
10266 11:47:54.353607 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10267 11:47:54.353793
10268 11:47:54.353939 Loading FIT.
10269 11:47:54.356818
10270 11:47:54.356973 Image ramdisk-1 has 39353498 bytes.
10271 11:47:54.357132
10272 11:47:54.360295 Image fdt-1 has 47278 bytes.
10273 11:47:54.360472
10274 11:47:54.363638 Image kernel-1 has 11048246 bytes.
10275 11:47:54.363816
10276 11:47:54.373310 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10277 11:47:54.373561
10278 11:47:54.390542 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10279 11:47:54.391204
10280 11:47:54.396720 Choosing best match conf-1 for compat google,spherion-rev2.
10281 11:47:54.400829
10282 11:47:54.404953 Connected to device vid:did:rid of 1ae0:0028:00
10283 11:47:54.413397
10284 11:47:54.416736 tpm_get_response: command 0x17b, return code 0x0
10285 11:47:54.417159
10286 11:47:54.419858 ec_init: CrosEC protocol v3 supported (256, 248)
10287 11:47:54.424225
10288 11:47:54.428177 tpm_cleanup: add release locality here.
10289 11:47:54.428667
10290 11:47:54.429001 Shutting down all USB controllers.
10291 11:47:54.429312
10292 11:47:54.431386 Removing current net device
10293 11:47:54.431803
10294 11:47:54.438171 Exiting depthcharge with code 4 at timestamp: 60623404
10295 11:47:54.438592
10296 11:47:54.440962 LZMA decompressing kernel-1 to 0x821a6718
10297 11:47:54.441383
10298 11:47:54.444469 LZMA decompressing kernel-1 to 0x40000000
10299 11:47:55.833148
10300 11:47:55.833671 jumping to kernel
10301 11:47:55.835608 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10302 11:47:55.836133 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10303 11:47:55.836523 Setting prompt string to ['Linux version [0-9]']
10304 11:47:55.836878 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10305 11:47:55.837221 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10306 11:47:55.916684
10307 11:47:55.919864 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10308 11:47:55.923137 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10309 11:47:55.923583 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10310 11:47:55.923941 Setting prompt string to []
10311 11:47:55.924329 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10312 11:47:55.924686 Using line separator: #'\n'#
10313 11:47:55.925009 No login prompt set.
10314 11:47:55.925462 Parsing kernel messages
10315 11:47:55.925863 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10316 11:47:55.926392 [login-action] Waiting for messages, (timeout 00:03:52)
10317 11:47:55.942920 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10318 11:47:55.946065 [ 0.000000] random: crng init done
10319 11:47:55.950121 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10320 11:47:55.952951 [ 0.000000] efi: UEFI not found.
10321 11:47:55.963155 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10322 11:47:55.969418 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10323 11:47:55.979662 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10324 11:47:55.989108 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10325 11:47:55.996229 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10326 11:47:56.002495 [ 0.000000] printk: bootconsole [mtk8250] enabled
10327 11:47:56.009028 [ 0.000000] NUMA: No NUMA configuration found
10328 11:47:56.015445 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10329 11:47:56.018827 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10330 11:47:56.022091 [ 0.000000] Zone ranges:
10331 11:47:56.029289 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10332 11:47:56.032083 [ 0.000000] DMA32 empty
10333 11:47:56.038899 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10334 11:47:56.041939 [ 0.000000] Movable zone start for each node
10335 11:47:56.045408 [ 0.000000] Early memory node ranges
10336 11:47:56.051839 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10337 11:47:56.058831 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10338 11:47:56.065101 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10339 11:47:56.071950 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10340 11:47:56.075087 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10341 11:47:56.084357 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10342 11:47:56.140521 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10343 11:47:56.147007 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10344 11:47:56.153839 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10345 11:47:56.156937 [ 0.000000] psci: probing for conduit method from DT.
10346 11:47:56.163388 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10347 11:47:56.166758 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10348 11:47:56.173497 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10349 11:47:56.176503 [ 0.000000] psci: SMC Calling Convention v1.2
10350 11:47:56.183183 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10351 11:47:56.186844 [ 0.000000] Detected VIPT I-cache on CPU0
10352 11:47:56.193409 [ 0.000000] CPU features: detected: GIC system register CPU interface
10353 11:47:56.199897 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10354 11:47:56.206601 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10355 11:47:56.213530 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10356 11:47:56.222800 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10357 11:47:56.229926 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10358 11:47:56.233142 [ 0.000000] alternatives: applying boot alternatives
10359 11:47:56.239630 [ 0.000000] Fallback order for Node 0: 0
10360 11:47:56.245905 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10361 11:47:56.249669 [ 0.000000] Policy zone: Normal
10362 11:47:56.262742 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10363 11:47:56.272252 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10364 11:47:56.284744 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10365 11:47:56.294945 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10366 11:47:56.301484 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10367 11:47:56.304929 <6>[ 0.000000] software IO TLB: area num 8.
10368 11:47:56.362638 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10369 11:47:56.511080 <6>[ 0.000000] Memory: 7931188K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 421580K reserved, 32768K cma-reserved)
10370 11:47:56.518177 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10371 11:47:56.525165 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10372 11:47:56.528115 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10373 11:47:56.534381 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10374 11:47:56.541248 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10375 11:47:56.544521 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10376 11:47:56.554500 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10377 11:47:56.560961 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10378 11:47:56.567610 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10379 11:47:56.574297 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10380 11:47:56.577444 <6>[ 0.000000] GICv3: 608 SPIs implemented
10381 11:47:56.580661 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10382 11:47:56.587322 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10383 11:47:56.590670 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10384 11:47:56.597274 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10385 11:47:56.610822 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10386 11:47:56.620696 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10387 11:47:56.630556 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10388 11:47:56.637813 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10389 11:47:56.650881 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10390 11:47:56.657970 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10391 11:47:56.664657 <6>[ 0.009183] Console: colour dummy device 80x25
10392 11:47:56.674745 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10393 11:47:56.681356 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10394 11:47:56.684119 <6>[ 0.029253] LSM: Security Framework initializing
10395 11:47:56.691293 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 11:47:56.700783 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10397 11:47:56.707848 <6>[ 0.051411] cblist_init_generic: Setting adjustable number of callback queues.
10398 11:47:56.714546 <6>[ 0.058854] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 11:47:56.723934 <6>[ 0.065231] cblist_init_generic: Setting adjustable number of callback queues.
10400 11:47:56.730673 <6>[ 0.072658] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 11:47:56.733882 <6>[ 0.079057] rcu: Hierarchical SRCU implementation.
10402 11:47:56.740905 <6>[ 0.084102] rcu: Max phase no-delay instances is 1000.
10403 11:47:56.747267 <6>[ 0.091126] EFI services will not be available.
10404 11:47:56.750316 <6>[ 0.096076] smp: Bringing up secondary CPUs ...
10405 11:47:56.758328 <6>[ 0.101123] Detected VIPT I-cache on CPU1
10406 11:47:56.765618 <6>[ 0.101192] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10407 11:47:56.771785 <6>[ 0.101224] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10408 11:47:56.774994 <6>[ 0.101562] Detected VIPT I-cache on CPU2
10409 11:47:56.782100 <6>[ 0.101613] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10410 11:47:56.791530 <6>[ 0.101629] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10411 11:47:56.794930 <6>[ 0.101891] Detected VIPT I-cache on CPU3
10412 11:47:56.801525 <6>[ 0.101938] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10413 11:47:56.808048 <6>[ 0.101952] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10414 11:47:56.811327 <6>[ 0.102255] CPU features: detected: Spectre-v4
10415 11:47:56.817993 <6>[ 0.102262] CPU features: detected: Spectre-BHB
10416 11:47:56.820985 <6>[ 0.102267] Detected PIPT I-cache on CPU4
10417 11:47:56.827793 <6>[ 0.102324] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10418 11:47:56.834507 <6>[ 0.102340] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10419 11:47:56.841152 <6>[ 0.102634] Detected PIPT I-cache on CPU5
10420 11:47:56.847577 <6>[ 0.102697] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10421 11:47:56.854072 <6>[ 0.102713] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10422 11:47:56.857479 <6>[ 0.102994] Detected PIPT I-cache on CPU6
10423 11:47:56.864402 <6>[ 0.103058] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10424 11:47:56.870691 <6>[ 0.103074] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10425 11:47:56.877415 <6>[ 0.103369] Detected PIPT I-cache on CPU7
10426 11:47:56.884059 <6>[ 0.103434] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10427 11:47:56.890489 <6>[ 0.103450] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10428 11:47:56.894207 <6>[ 0.103497] smp: Brought up 1 node, 8 CPUs
10429 11:47:56.900275 <6>[ 0.244956] SMP: Total of 8 processors activated.
10430 11:47:56.903746 <6>[ 0.249877] CPU features: detected: 32-bit EL0 Support
10431 11:47:56.914224 <6>[ 0.255240] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10432 11:47:56.920445 <6>[ 0.264040] CPU features: detected: Common not Private translations
10433 11:47:56.927240 <6>[ 0.270556] CPU features: detected: CRC32 instructions
10434 11:47:56.930288 <6>[ 0.275941] CPU features: detected: RCpc load-acquire (LDAPR)
10435 11:47:56.936886 <6>[ 0.281900] CPU features: detected: LSE atomic instructions
10436 11:47:56.943487 <6>[ 0.287682] CPU features: detected: Privileged Access Never
10437 11:47:56.950083 <6>[ 0.293461] CPU features: detected: RAS Extension Support
10438 11:47:56.956745 <6>[ 0.299070] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10439 11:47:56.960410 <6>[ 0.306334] CPU: All CPU(s) started at EL2
10440 11:47:56.966767 <6>[ 0.310650] alternatives: applying system-wide alternatives
10441 11:47:56.975896 <6>[ 0.321357] devtmpfs: initialized
10442 11:47:56.991522 <6>[ 0.330199] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10443 11:47:56.997997 <6>[ 0.340161] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10444 11:47:57.004947 <6>[ 0.348387] pinctrl core: initialized pinctrl subsystem
10445 11:47:57.008032 <6>[ 0.355053] DMI not present or invalid.
10446 11:47:57.014346 <6>[ 0.359467] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10447 11:47:57.024424 <6>[ 0.366346] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10448 11:47:57.030992 <6>[ 0.373923] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10449 11:47:57.040816 <6>[ 0.382146] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10450 11:47:57.043984 <6>[ 0.390390] audit: initializing netlink subsys (disabled)
10451 11:47:57.054529 <5>[ 0.396083] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10452 11:47:57.060724 <6>[ 0.396785] thermal_sys: Registered thermal governor 'step_wise'
10453 11:47:57.067164 <6>[ 0.404050] thermal_sys: Registered thermal governor 'power_allocator'
10454 11:47:57.070430 <6>[ 0.410303] cpuidle: using governor menu
10455 11:47:57.077506 <6>[ 0.421264] NET: Registered PF_QIPCRTR protocol family
10456 11:47:57.083826 <6>[ 0.426745] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10457 11:47:57.090275 <6>[ 0.433848] ASID allocator initialised with 32768 entries
10458 11:47:57.093468 <6>[ 0.440405] Serial: AMBA PL011 UART driver
10459 11:47:57.103843 <4>[ 0.449172] Trying to register duplicate clock ID: 134
10460 11:47:57.157802 <6>[ 0.506459] KASLR enabled
10461 11:47:57.172430 <6>[ 0.514137] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10462 11:47:57.178763 <6>[ 0.521153] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10463 11:47:57.185787 <6>[ 0.527645] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10464 11:47:57.192123 <6>[ 0.534651] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10465 11:47:57.198829 <6>[ 0.541139] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10466 11:47:57.205476 <6>[ 0.548145] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10467 11:47:57.211905 <6>[ 0.554631] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10468 11:47:57.219088 <6>[ 0.561638] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10469 11:47:57.222127 <6>[ 0.569138] ACPI: Interpreter disabled.
10470 11:47:57.230452 <6>[ 0.575531] iommu: Default domain type: Translated
10471 11:47:57.236907 <6>[ 0.580645] iommu: DMA domain TLB invalidation policy: strict mode
10472 11:47:57.239970 <5>[ 0.587295] SCSI subsystem initialized
10473 11:47:57.246860 <6>[ 0.591459] usbcore: registered new interface driver usbfs
10474 11:47:57.253536 <6>[ 0.597191] usbcore: registered new interface driver hub
10475 11:47:57.256707 <6>[ 0.602743] usbcore: registered new device driver usb
10476 11:47:57.263413 <6>[ 0.608838] pps_core: LinuxPPS API ver. 1 registered
10477 11:47:57.273822 <6>[ 0.614032] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10478 11:47:57.276787 <6>[ 0.623379] PTP clock support registered
10479 11:47:57.280290 <6>[ 0.627620] EDAC MC: Ver: 3.0.0
10480 11:47:57.287688 <6>[ 0.632771] FPGA manager framework
10481 11:47:57.291133 <6>[ 0.636448] Advanced Linux Sound Architecture Driver Initialized.
10482 11:47:57.294647 <6>[ 0.643213] vgaarb: loaded
10483 11:47:57.301159 <6>[ 0.646382] clocksource: Switched to clocksource arch_sys_counter
10484 11:47:57.307842 <5>[ 0.652813] VFS: Disk quotas dquot_6.6.0
10485 11:47:57.314492 <6>[ 0.656994] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10486 11:47:57.317476 <6>[ 0.664174] pnp: PnP ACPI: disabled
10487 11:47:57.325288 <6>[ 0.670795] NET: Registered PF_INET protocol family
10488 11:47:57.335573 <6>[ 0.676381] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10489 11:47:57.346491 <6>[ 0.688684] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10490 11:47:57.356787 <6>[ 0.697498] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10491 11:47:57.363306 <6>[ 0.705467] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10492 11:47:57.370358 <6>[ 0.714170] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10493 11:47:57.381867 <6>[ 0.723924] TCP: Hash tables configured (established 65536 bind 65536)
10494 11:47:57.388793 <6>[ 0.730785] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 11:47:57.395161 <6>[ 0.737983] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10496 11:47:57.402016 <6>[ 0.745686] NET: Registered PF_UNIX/PF_LOCAL protocol family
10497 11:47:57.408320 <6>[ 0.751850] RPC: Registered named UNIX socket transport module.
10498 11:47:57.411931 <6>[ 0.758003] RPC: Registered udp transport module.
10499 11:47:57.418218 <6>[ 0.762937] RPC: Registered tcp transport module.
10500 11:47:57.425323 <6>[ 0.767867] RPC: Registered tcp NFSv4.1 backchannel transport module.
10501 11:47:57.428451 <6>[ 0.774534] PCI: CLS 0 bytes, default 64
10502 11:47:57.431629 <6>[ 0.778931] Unpacking initramfs...
10503 11:47:57.456325 <6>[ 0.798486] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10504 11:47:57.466126 <6>[ 0.807142] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10505 11:47:57.469964 <6>[ 0.815993] kvm [1]: IPA Size Limit: 40 bits
10506 11:47:57.476312 <6>[ 0.820525] kvm [1]: GICv3: no GICV resource entry
10507 11:47:57.479558 <6>[ 0.825549] kvm [1]: disabling GICv2 emulation
10508 11:47:57.486395 <6>[ 0.830237] kvm [1]: GIC system register CPU interface enabled
10509 11:47:57.489451 <6>[ 0.836402] kvm [1]: vgic interrupt IRQ18
10510 11:47:57.495831 <6>[ 0.840760] kvm [1]: VHE mode initialized successfully
10511 11:47:57.502711 <5>[ 0.847199] Initialise system trusted keyrings
10512 11:47:57.509183 <6>[ 0.852057] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10513 11:47:57.516891 <6>[ 0.861948] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10514 11:47:57.523062 <5>[ 0.868331] NFS: Registering the id_resolver key type
10515 11:47:57.526455 <5>[ 0.873632] Key type id_resolver registered
10516 11:47:57.533202 <5>[ 0.878046] Key type id_legacy registered
10517 11:47:57.539678 <6>[ 0.882326] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10518 11:47:57.546031 <6>[ 0.889249] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10519 11:47:57.552691 <6>[ 0.896964] 9p: Installing v9fs 9p2000 file system support
10520 11:47:57.589895 <5>[ 0.934935] Key type asymmetric registered
10521 11:47:57.593135 <5>[ 0.939266] Asymmetric key parser 'x509' registered
10522 11:47:57.602787 <6>[ 0.944405] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10523 11:47:57.606312 <6>[ 0.952021] io scheduler mq-deadline registered
10524 11:47:57.609505 <6>[ 0.956800] io scheduler kyber registered
10525 11:47:57.628293 <6>[ 0.973838] EINJ: ACPI disabled.
10526 11:47:57.660938 <4>[ 0.999619] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 11:47:57.670567 <4>[ 1.010245] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 11:47:57.685394 <6>[ 1.031011] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10529 11:47:57.693855 <6>[ 1.038996] printk: console [ttyS0] disabled
10530 11:47:57.721498 <6>[ 1.063639] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10531 11:47:57.728215 <6>[ 1.073117] printk: console [ttyS0] enabled
10532 11:47:57.731536 <6>[ 1.073117] printk: console [ttyS0] enabled
10533 11:47:57.738086 <6>[ 1.082010] printk: bootconsole [mtk8250] disabled
10534 11:47:57.741267 <6>[ 1.082010] printk: bootconsole [mtk8250] disabled
10535 11:47:57.748442 <6>[ 1.093280] SuperH (H)SCI(F) driver initialized
10536 11:47:57.751463 <6>[ 1.098562] msm_serial: driver initialized
10537 11:47:57.765390 <6>[ 1.107566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10538 11:47:57.775723 <6>[ 1.116113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10539 11:47:57.782444 <6>[ 1.124655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10540 11:47:57.792469 <6>[ 1.133284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10541 11:47:57.798946 <6>[ 1.141991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10542 11:47:57.808652 <6>[ 1.150704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10543 11:47:57.818809 <6>[ 1.159245] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10544 11:47:57.825281 <6>[ 1.168046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10545 11:47:57.835339 <6>[ 1.176596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10546 11:47:57.846768 <6>[ 1.192200] loop: module loaded
10547 11:47:57.853271 <6>[ 1.198084] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10548 11:47:57.876132 <4>[ 1.221712] mtk-pmic-keys: Failed to locate of_node [id: -1]
10549 11:47:57.883277 <6>[ 1.228604] megasas: 07.719.03.00-rc1
10550 11:47:57.892733 <6>[ 1.238225] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10551 11:47:57.900359 <6>[ 1.245757] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10552 11:47:57.917434 <6>[ 1.262594] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10553 11:47:57.974247 <6>[ 1.312991] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10554 11:47:59.019446 <6>[ 2.364957] Freeing initrd memory: 38424K
10555 11:47:59.030145 <6>[ 2.375458] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10556 11:47:59.041294 <6>[ 2.386528] tun: Universal TUN/TAP device driver, 1.6
10557 11:47:59.044509 <6>[ 2.392600] thunder_xcv, ver 1.0
10558 11:47:59.047411 <6>[ 2.396105] thunder_bgx, ver 1.0
10559 11:47:59.051431 <6>[ 2.399599] nicpf, ver 1.0
10560 11:47:59.061534 <6>[ 2.403619] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10561 11:47:59.064797 <6>[ 2.411094] hns3: Copyright (c) 2017 Huawei Corporation.
10562 11:47:59.068061 <6>[ 2.416682] hclge is initializing
10563 11:47:59.075199 <6>[ 2.420257] e1000: Intel(R) PRO/1000 Network Driver
10564 11:47:59.081500 <6>[ 2.425387] e1000: Copyright (c) 1999-2006 Intel Corporation.
10565 11:47:59.084870 <6>[ 2.431401] e1000e: Intel(R) PRO/1000 Network Driver
10566 11:47:59.091536 <6>[ 2.436617] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10567 11:47:59.098049 <6>[ 2.442801] igb: Intel(R) Gigabit Ethernet Network Driver
10568 11:47:59.104850 <6>[ 2.448451] igb: Copyright (c) 2007-2014 Intel Corporation.
10569 11:47:59.111310 <6>[ 2.454286] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10570 11:47:59.115318 <6>[ 2.460804] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10571 11:47:59.122021 <6>[ 2.467275] sky2: driver version 1.30
10572 11:47:59.128618 <6>[ 2.472276] VFIO - User Level meta-driver version: 0.3
10573 11:47:59.135636 <6>[ 2.480564] usbcore: registered new interface driver usb-storage
10574 11:47:59.142069 <6>[ 2.487005] usbcore: registered new device driver onboard-usb-hub
10575 11:47:59.150806 <6>[ 2.496191] mt6397-rtc mt6359-rtc: registered as rtc0
10576 11:47:59.160560 <6>[ 2.501655] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:45:47 UTC (1700826347)
10577 11:47:59.164096 <6>[ 2.511228] i2c_dev: i2c /dev entries driver
10578 11:47:59.180750 <6>[ 2.522988] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10579 11:47:59.200806 <6>[ 2.545990] cpu cpu0: EM: created perf domain
10580 11:47:59.204069 <6>[ 2.550934] cpu cpu4: EM: created perf domain
10581 11:47:59.211129 <6>[ 2.556576] sdhci: Secure Digital Host Controller Interface driver
10582 11:47:59.217544 <6>[ 2.563008] sdhci: Copyright(c) Pierre Ossman
10583 11:47:59.224508 <6>[ 2.567968] Synopsys Designware Multimedia Card Interface Driver
10584 11:47:59.230983 <6>[ 2.574604] sdhci-pltfm: SDHCI platform and OF driver helper
10585 11:47:59.234428 <6>[ 2.574620] mmc0: CQHCI version 5.10
10586 11:47:59.240818 <6>[ 2.584483] ledtrig-cpu: registered to indicate activity on CPUs
10587 11:47:59.247431 <6>[ 2.591613] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 11:47:59.254198 <6>[ 2.598666] usbcore: registered new interface driver usbhid
10589 11:47:59.257438 <6>[ 2.604490] usbhid: USB HID core driver
10590 11:47:59.264359 <6>[ 2.608688] spi_master spi0: will run message pump with realtime priority
10591 11:47:59.308133 <6>[ 2.646722] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 11:47:59.323800 <6>[ 2.662617] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 11:47:59.333101 <6>[ 2.678605] cros-ec-spi spi0.0: Chrome EC device registered
10594 11:47:59.339914 <6>[ 2.678678] mmc0: Command Queue Engine enabled
10595 11:47:59.346928 <6>[ 2.689196] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 11:47:59.350334 <6>[ 2.696492] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 11:47:59.359863 <6>[ 2.705416] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10598 11:47:59.366928 <6>[ 2.712291] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10599 11:47:59.373566 <6>[ 2.718484] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10600 11:47:59.379939 <6>[ 2.724744] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10601 11:47:59.389845 <6>[ 2.729383] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10602 11:47:59.396231 <6>[ 2.742042] NET: Registered PF_PACKET protocol family
10603 11:47:59.400141 <6>[ 2.747436] 9pnet: Installing 9P2000 support
10604 11:47:59.406520 <5>[ 2.752000] Key type dns_resolver registered
10605 11:47:59.409940 <6>[ 2.756961] registered taskstats version 1
10606 11:47:59.416248 <5>[ 2.761354] Loading compiled-in X.509 certificates
10607 11:47:59.448686 <4>[ 2.787305] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 11:47:59.458175 <4>[ 2.798041] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 11:47:59.464942 <3>[ 2.808618] debugfs: File 'uA_load' in directory '/' already present!
10610 11:47:59.471544 <3>[ 2.815323] debugfs: File 'min_uV' in directory '/' already present!
10611 11:47:59.477934 <3>[ 2.821931] debugfs: File 'max_uV' in directory '/' already present!
10612 11:47:59.484630 <3>[ 2.828538] debugfs: File 'constraint_flags' in directory '/' already present!
10613 11:47:59.496319 <3>[ 2.838269] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10614 11:47:59.505761 <6>[ 2.851094] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10615 11:47:59.512208 <6>[ 2.857891] xhci-mtk 11200000.usb: xHCI Host Controller
10616 11:47:59.519388 <6>[ 2.863391] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10617 11:47:59.528963 <6>[ 2.871225] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 11:47:59.535735 <6>[ 2.880660] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10619 11:47:59.541982 <6>[ 2.886740] xhci-mtk 11200000.usb: xHCI Host Controller
10620 11:47:59.549002 <6>[ 2.892216] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10621 11:47:59.555510 <6>[ 2.899860] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10622 11:47:59.562515 <6>[ 2.907653] hub 1-0:1.0: USB hub found
10623 11:47:59.565784 <6>[ 2.911672] hub 1-0:1.0: 1 port detected
10624 11:47:59.572159 <6>[ 2.915949] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10625 11:47:59.579055 <6>[ 2.924701] hub 2-0:1.0: USB hub found
10626 11:47:59.582340 <6>[ 2.928722] hub 2-0:1.0: 1 port detected
10627 11:47:59.591303 <6>[ 2.936975] mtk-msdc 11f70000.mmc: Got CD GPIO
10628 11:47:59.601221 <6>[ 2.943420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10629 11:47:59.608692 <6>[ 2.951442] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10630 11:47:59.617943 <4>[ 2.959343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10631 11:47:59.627833 <6>[ 2.968863] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10632 11:47:59.634806 <6>[ 2.976939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10633 11:47:59.641067 <6>[ 2.985041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10634 11:47:59.651534 <6>[ 2.992981] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10635 11:47:59.658029 <6>[ 3.000798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10636 11:47:59.667612 <6>[ 3.008621] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10637 11:47:59.677924 <6>[ 3.019223] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10638 11:47:59.684438 <6>[ 3.027596] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10639 11:47:59.694491 <6>[ 3.035936] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10640 11:47:59.700522 <6>[ 3.044275] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10641 11:47:59.710771 <6>[ 3.052613] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10642 11:47:59.717195 <6>[ 3.060951] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10643 11:47:59.727473 <6>[ 3.069291] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10644 11:47:59.734200 <6>[ 3.077629] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10645 11:47:59.743566 <6>[ 3.085967] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10646 11:47:59.750335 <6>[ 3.094306] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10647 11:47:59.760712 <6>[ 3.102657] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10648 11:47:59.770416 <6>[ 3.110997] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10649 11:47:59.776906 <6>[ 3.119335] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10650 11:47:59.787263 <6>[ 3.127674] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10651 11:47:59.793763 <6>[ 3.136012] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10652 11:47:59.800411 <6>[ 3.144783] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10653 11:47:59.806960 <6>[ 3.151949] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10654 11:47:59.813260 <6>[ 3.158716] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10655 11:47:59.820118 <6>[ 3.165469] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10656 11:47:59.830181 <6>[ 3.172405] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10657 11:47:59.836960 <6>[ 3.179261] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10658 11:47:59.846926 <6>[ 3.188387] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10659 11:47:59.856779 <6>[ 3.197507] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10660 11:47:59.866590 <6>[ 3.206802] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10661 11:47:59.876734 <6>[ 3.216273] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10662 11:47:59.883066 <6>[ 3.225741] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10663 11:47:59.893052 <6>[ 3.234861] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10664 11:47:59.903022 <6>[ 3.244351] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10665 11:47:59.912877 <6>[ 3.253471] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10666 11:47:59.922905 <6>[ 3.262765] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10667 11:47:59.933173 <6>[ 3.272926] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10668 11:47:59.943010 <6>[ 3.284892] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10669 11:47:59.972521 <6>[ 3.314920] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 11:48:00.000593 <6>[ 3.346322] hub 2-1:1.0: USB hub found
10671 11:48:00.004224 <6>[ 3.350826] hub 2-1:1.0: 3 ports detected
10672 11:48:00.012514 <6>[ 3.358144] hub 2-1:1.0: USB hub found
10673 11:48:00.015797 <6>[ 3.362579] hub 2-1:1.0: 3 ports detected
10674 11:48:00.124615 <6>[ 3.466654] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10675 11:48:00.279444 <6>[ 3.624758] hub 1-1:1.0: USB hub found
10676 11:48:00.282460 <6>[ 3.629190] hub 1-1:1.0: 4 ports detected
10677 11:48:00.291917 <6>[ 3.637586] hub 1-1:1.0: USB hub found
10678 11:48:00.295116 <6>[ 3.641897] hub 1-1:1.0: 4 ports detected
10679 11:48:00.356578 <6>[ 3.698781] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10680 11:48:00.616355 <6>[ 3.958751] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10681 11:48:00.749158 <6>[ 4.094668] hub 1-1.4:1.0: USB hub found
10682 11:48:00.752184 <6>[ 4.099350] hub 1-1.4:1.0: 2 ports detected
10683 11:48:00.762332 <6>[ 4.107779] hub 1-1.4:1.0: USB hub found
10684 11:48:00.765360 <6>[ 4.112370] hub 1-1.4:1.0: 2 ports detected
10685 11:48:01.064282 <6>[ 4.406679] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10686 11:48:01.256306 <6>[ 4.598668] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10687 11:48:12.217568 <6>[ 15.567651] ALSA device list:
10688 11:48:12.223977 <6>[ 15.570950] No soundcards found.
10689 11:48:12.232097 <6>[ 15.578943] Freeing unused kernel memory: 8384K
10690 11:48:12.235490 <6>[ 15.583923] Run /init as init process
10691 11:48:12.284490 <6>[ 15.631317] NET: Registered PF_INET6 protocol family
10692 11:48:12.290960 <6>[ 15.637879] Segment Routing with IPv6
10693 11:48:12.294356 <6>[ 15.641830] In-situ OAM (IOAM) with IPv6
10694 11:48:12.329889 <30>[ 15.657105] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10695 11:48:12.333376 <30>[ 15.680991] systemd[1]: Detected architecture arm64.
10696 11:48:12.333461
10697 11:48:12.339897 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10698 11:48:12.339982
10699 11:48:12.359518 <30>[ 15.706725] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10700 11:48:12.491097 <30>[ 15.834852] systemd[1]: Queued start job for default target Graphical Interface.
10701 11:48:12.516648 <30>[ 15.863661] systemd[1]: Created slice system-getty.slice.
10702 11:48:12.523379 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10703 11:48:12.540640 <30>[ 15.887334] systemd[1]: Created slice system-modprobe.slice.
10704 11:48:12.547271 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10705 11:48:12.564532 <30>[ 15.911634] systemd[1]: Created slice system-serial\x2dgetty.slice.
10706 11:48:12.574745 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10707 11:48:12.589191 <30>[ 15.935912] systemd[1]: Created slice User and Session Slice.
10708 11:48:12.595654 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10709 11:48:12.615423 <30>[ 15.959209] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10710 11:48:12.625676 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10711 11:48:12.643812 <30>[ 15.987196] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10712 11:48:12.650348 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10713 11:48:12.674352 <30>[ 16.014776] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10714 11:48:12.681039 <30>[ 16.026948] systemd[1]: Reached target Local Encrypted Volumes.
10715 11:48:12.687868 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10716 11:48:12.704609 <30>[ 16.051141] systemd[1]: Reached target Paths.
10717 11:48:12.707680 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10718 11:48:12.723578 <30>[ 16.070674] systemd[1]: Reached target Remote File Systems.
10719 11:48:12.730702 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10720 11:48:12.748359 <30>[ 16.095026] systemd[1]: Reached target Slices.
10721 11:48:12.754519 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10722 11:48:12.768047 <30>[ 16.114676] systemd[1]: Reached target Swap.
10723 11:48:12.770931 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10724 11:48:12.791292 <30>[ 16.135155] systemd[1]: Listening on initctl Compatibility Named Pipe.
10725 11:48:12.798411 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10726 11:48:12.804997 <30>[ 16.150323] systemd[1]: Listening on Journal Audit Socket.
10727 11:48:12.811322 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10728 11:48:12.824548 <30>[ 16.171138] systemd[1]: Listening on Journal Socket (/dev/log).
10729 11:48:12.830566 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10730 11:48:12.849207 <30>[ 16.195900] systemd[1]: Listening on Journal Socket.
10731 11:48:12.855383 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10732 11:48:12.868343 <30>[ 16.215355] systemd[1]: Listening on Network Service Netlink Socket.
10733 11:48:12.878764 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10734 11:48:12.892139 <30>[ 16.239209] systemd[1]: Listening on udev Control Socket.
10735 11:48:12.898824 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10736 11:48:12.917003 <30>[ 16.263764] systemd[1]: Listening on udev Kernel Socket.
10737 11:48:12.923243 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10738 11:48:12.979975 <30>[ 16.326874] systemd[1]: Mounting Huge Pages File System...
10739 11:48:12.986745 Mounting [0;1;39mHuge Pages File System[0m...
10740 11:48:13.003906 <30>[ 16.350517] systemd[1]: Mounting POSIX Message Queue File System...
10741 11:48:13.010310 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10742 11:48:13.031548 <30>[ 16.378491] systemd[1]: Mounting Kernel Debug File System...
10743 11:48:13.038103 Mounting [0;1;39mKernel Debug File System[0m...
10744 11:48:13.055579 <30>[ 16.399094] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10745 11:48:13.083734 <30>[ 16.426874] systemd[1]: Starting Create list of static device nodes for the current kernel...
10746 11:48:13.090038 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10747 11:48:13.112033 <30>[ 16.459029] systemd[1]: Starting Load Kernel Module configfs...
10748 11:48:13.118868 Starting [0;1;39mLoad Kernel Module configfs[0m...
10749 11:48:13.136151 <30>[ 16.482824] systemd[1]: Starting Load Kernel Module drm...
10750 11:48:13.142443 Starting [0;1;39mLoad Kernel Module drm[0m...
10751 11:48:13.159398 <30>[ 16.502993] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10752 11:48:13.192109 <30>[ 16.539231] systemd[1]: Starting Journal Service...
10753 11:48:13.195349 Starting [0;1;39mJournal Service[0m...
10754 11:48:13.214535 <30>[ 16.561603] systemd[1]: Starting Load Kernel Modules...
10755 11:48:13.220905 Starting [0;1;39mLoad Kernel Modules[0m...
10756 11:48:13.241509 <30>[ 16.584942] systemd[1]: Starting Remount Root and Kernel File Systems...
10757 11:48:13.247988 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10758 11:48:13.263541 <30>[ 16.610220] systemd[1]: Starting Coldplug All udev Devices...
10759 11:48:13.269734 Starting [0;1;39mColdplug All udev Devices[0m...
10760 11:48:13.287908 <30>[ 16.635034] systemd[1]: Started Journal Service.
10761 11:48:13.294402 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10762 11:48:13.309936 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10763 11:48:13.328469 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10764 11:48:13.344136 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10765 11:48:13.364760 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10766 11:48:13.381095 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10767 11:48:13.397500 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10768 11:48:13.412463 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10769 11:48:13.434384 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10770 11:48:13.447596 See 'systemctl status systemd-remount-fs.service' for details.
10771 11:48:13.495551 Mounting [0;1;39mKernel Configuration File System[0m...
10772 11:48:13.516554 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10773 11:48:13.529324 <46>[ 16.873114] systemd-journald[186]: Received client request to flush runtime journal.
10774 11:48:13.540679 Starting [0;1;39mLoad/Save Random Seed[0m...
10775 11:48:13.559117 Starting [0;1;39mApply Kernel Variables[0m...
10776 11:48:13.581351 Starting [0;1;39mCreate System Users[0m...
10777 11:48:13.601082 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10778 11:48:13.616696 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10779 11:48:13.636668 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10780 11:48:13.649170 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10781 11:48:13.665594 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10782 11:48:13.681435 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10783 11:48:13.736312 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10784 11:48:13.755889 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10785 11:48:13.772117 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10786 11:48:13.791761 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10787 11:48:13.856442 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10788 11:48:13.883859 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10789 11:48:13.910659 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10790 11:48:13.930718 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10791 11:48:13.982273 Starting [0;1;39mNetwork Service[0m...
10792 11:48:14.004911 Starting [0;1;39mNetwork Time Synchronization[0m...
10793 11:48:14.025873 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10794 11:48:14.082072 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10795 11:48:14.102265 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10796 11:48:14.108741 <6>[ 17.453902] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10797 11:48:14.118849 <6>[ 17.462260] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10798 11:48:14.125694 <6>[ 17.464109] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10799 11:48:14.135543 <6>[ 17.471013] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10800 11:48:14.141863 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10801 11:48:14.150814 <6>[ 17.497977] remoteproc remoteproc0: scp is available
10802 11:48:14.157751 <6>[ 17.503547] remoteproc remoteproc0: powering up scp
10803 11:48:14.164136 <6>[ 17.508704] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10804 11:48:14.170979 <6>[ 17.517145] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10805 11:48:14.177400 <3>[ 17.519203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 11:48:14.187456 <4>[ 17.523197] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10807 11:48:14.193736 <3>[ 17.530967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 11:48:14.203642 <3>[ 17.530973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 11:48:14.210463 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10810 11:48:14.223445 <3>[ 17.567203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 11:48:14.230258 <4>[ 17.567337] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10812 11:48:14.239919 <3>[ 17.575373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 11:48:14.243635 <6>[ 17.588421] mc: Linux media interface: v0.10
10814 11:48:14.252984 <3>[ 17.590733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 11:48:14.260193 <3>[ 17.590749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 11:48:14.269768 <3>[ 17.590753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 11:48:14.276591 <3>[ 17.601081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 11:48:14.283096 <6>[ 17.606693] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10819 11:48:14.290162 <6>[ 17.609234] usbcore: registered new interface driver r8152
10820 11:48:14.296637 <6>[ 17.612478] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10821 11:48:14.306927 <3>[ 17.612700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 11:48:14.313718 <3>[ 17.612708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 11:48:14.320606 <3>[ 17.612713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 11:48:14.330319 <3>[ 17.612773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 11:48:14.336872 <3>[ 17.612830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 11:48:14.347416 <3>[ 17.612837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 11:48:14.354692 <3>[ 17.612843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 11:48:14.361356 <3>[ 17.612848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 11:48:14.371094 <3>[ 17.612879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 11:48:14.377836 <4>[ 17.636578] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10831 11:48:14.384733 <4>[ 17.636578] Fallback method does not support PEC.
10832 11:48:14.390854 <6>[ 17.636778] pci_bus 0000:00: root bus resource [bus 00-ff]
10833 11:48:14.397779 <6>[ 17.648060] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10834 11:48:14.404429 <6>[ 17.648070] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10835 11:48:14.411076 <6>[ 17.649379] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10836 11:48:14.417793 <6>[ 17.657478] remoteproc remoteproc0: remote processor scp is now up
10837 11:48:14.428380 <6>[ 17.665545] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10838 11:48:14.438284 <3>[ 17.667056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 11:48:14.445895 <6>[ 17.688758] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10840 11:48:14.449072 <6>[ 17.689911] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10841 11:48:14.459153 <3>[ 17.703835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 11:48:14.469393 <6>[ 17.706529] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10843 11:48:14.475954 <6>[ 17.706533] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10844 11:48:14.483173 <6>[ 17.706637] pci 0000:00:00.0: supports D1 D2
10845 11:48:14.489356 <6>[ 17.706640] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10846 11:48:14.499891 <6>[ 17.708301] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10847 11:48:14.506742 <6>[ 17.710344] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10848 11:48:14.513353 <6>[ 17.710629] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10849 11:48:14.520109 <6>[ 17.710656] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10850 11:48:14.527538 <6>[ 17.710673] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10851 11:48:14.534419 <6>[ 17.710688] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10852 11:48:14.541087 <6>[ 17.710795] pci 0000:01:00.0: supports D1 D2
10853 11:48:14.547798 <6>[ 17.710797] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10854 11:48:14.554347 <6>[ 17.726606] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10855 11:48:14.560968 <3>[ 17.736081] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10856 11:48:14.571141 <6>[ 17.736829] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10857 11:48:14.581717 <6>[ 17.741953] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10858 11:48:14.588523 <4>[ 17.743061] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10859 11:48:14.598411 <4>[ 17.743076] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10860 11:48:14.601991 <6>[ 17.743436] videodev: Linux video capture interface: v2.00
10861 11:48:14.608820 <6>[ 17.755134] usbcore: registered new interface driver cdc_ether
10862 11:48:14.618085 <6>[ 17.757448] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10863 11:48:14.625516 <6>[ 17.766129] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10864 11:48:14.632764 <6>[ 17.771015] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10865 11:48:14.642629 <6>[ 17.771029] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10866 11:48:14.646372 <6>[ 17.771708] Bluetooth: Core ver 2.22
10867 11:48:14.649297 <6>[ 17.771712] usbcore: registered new interface driver r8153_ecm
10868 11:48:14.656535 <6>[ 17.771835] NET: Registered PF_BLUETOOTH protocol family
10869 11:48:14.663515 <6>[ 17.771839] Bluetooth: HCI device and connection manager initialized
10870 11:48:14.667431 <6>[ 17.771875] Bluetooth: HCI socket layer initialized
10871 11:48:14.673821 <6>[ 17.771886] Bluetooth: L2CAP socket layer initialized
10872 11:48:14.677243 <6>[ 17.771905] Bluetooth: SCO socket layer initialized
10873 11:48:14.687158 <3>[ 17.787146] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 11:48:14.694521 <6>[ 17.787508] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10875 11:48:14.704225 <3>[ 17.787869] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10876 11:48:14.711291 <6>[ 17.789715] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10877 11:48:14.721003 <3>[ 17.801373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 11:48:14.724641 <6>[ 17.803087] pci 0000:00:00.0: PCI bridge to [bus 01]
10879 11:48:14.734802 <6>[ 17.803094] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10880 11:48:14.737853 <6>[ 17.813054] r8152 2-1.3:1.0 eth0: v1.12.13
10881 11:48:14.744015 <6>[ 17.822143] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10882 11:48:14.750889 <6>[ 17.824219] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10883 11:48:14.764316 <6>[ 17.825348] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10884 11:48:14.770486 <6>[ 17.825481] usbcore: registered new interface driver uvcvideo
10885 11:48:14.774043 <6>[ 17.835339] usbcore: registered new interface driver btusb
10886 11:48:14.787170 <4>[ 17.836010] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10887 11:48:14.790669 <3>[ 17.836037] Bluetooth: hci0: Failed to load firmware file (-2)
10888 11:48:14.797046 <3>[ 17.836042] Bluetooth: hci0: Failed to set up firmware (-2)
10889 11:48:14.807367 <4>[ 17.836053] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10890 11:48:14.816811 <3>[ 17.836934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 11:48:14.823473 <6>[ 17.841943] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10892 11:48:14.830290 <6>[ 17.841989] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10893 11:48:14.837012 <6>[ 17.851085] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10894 11:48:14.840222 <6>[ 17.858717] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10895 11:48:14.850612 <3>[ 17.860714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 11:48:14.860481 <3>[ 17.882284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:48:14.867170 <5>[ 17.908101] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10898 11:48:14.877029 <3>[ 17.936548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 11:48:14.883783 <5>[ 17.952585] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10900 11:48:14.890473 <4>[ 18.235083] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10901 11:48:14.897165 <6>[ 18.235091] cfg80211: failed to load regulatory.db
10902 11:48:14.903854 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10903 11:48:14.924150 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10904 11:48:14.938335 <6>[ 18.282076] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10905 11:48:14.944649 <6>[ 18.289570] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10906 11:48:14.967465 <6>[ 18.314583] mt7921e 0000:01:00.0: ASIC revision: 79610010
10907 11:48:15.003367 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10908 11:48:15.026693 Starting [0;1;39mNetwork Name Resolution[0m...
10909 11:48:15.044963 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10910 11:48:15.074554 <4>[ 18.414966] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10911 11:48:15.084386 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10912 11:48:15.118109 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10913 11:48:15.192863 <4>[ 18.533190] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10914 11:48:15.280627 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10915 11:48:15.296766 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10916 11:48:15.312439 <4>[ 18.653259] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10917 11:48:15.319265 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10918 11:48:15.335869 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10919 11:48:15.352376 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10920 11:48:15.370554 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10921 11:48:15.383737 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10922 11:48:15.403691 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10923 11:48:15.416894 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10924 11:48:15.432140 <4>[ 18.773071] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10925 11:48:15.438696 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10926 11:48:15.455969 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10927 11:48:15.496696 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10928 11:48:15.530020 Starting [0;1;39mUser Login Management[0m...
10929 11:48:15.552773 <4>[ 18.893412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10930 11:48:15.559249 Starting [0;1;39mPermit User Sessions[0m...
10931 11:48:15.580472 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10932 11:48:15.592135 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10933 11:48:15.611652 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10934 11:48:15.632995 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10935 11:48:15.672512 <4>[ 19.013216] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10936 11:48:15.693013 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10937 11:48:15.718418 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10938 11:48:15.736289 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10939 11:48:15.752479 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10940 11:48:15.768715 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10941 11:48:15.792417 <4>[ 19.132960] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 11:48:15.842016 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10943 11:48:15.880517 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10944 11:48:15.913871 <4>[ 19.254785] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 11:48:15.934090
10946 11:48:15.934172
10947 11:48:15.937887 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10948 11:48:15.937969
10949 11:48:15.940778 debian-bullseye-arm64 login: root (automatic login)
10950 11:48:15.940909
10951 11:48:15.940974
10952 11:48:15.971819 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
10953 11:48:15.971906
10954 11:48:15.978359 The programs included with the Debian GNU/Linux system are free software;
10955 11:48:15.985031 the exact distribution terms for each program are described in the
10956 11:48:15.988368 individual files in /usr/share/doc/*/copyright.
10957 11:48:15.988449
10958 11:48:15.995482 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10959 11:48:15.998752 permitted by applicable law.
10960 11:48:15.999141 Matched prompt #10: / #
10962 11:48:15.999344 Setting prompt string to ['/ #']
10963 11:48:15.999436 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10965 11:48:15.999624 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10966 11:48:15.999711 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10967 11:48:15.999777 Setting prompt string to ['/ #']
10968 11:48:15.999836 Forcing a shell prompt, looking for ['/ #']
10970 11:48:16.050040 / #
10971 11:48:16.050144 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10972 11:48:16.050219 Waiting using forced prompt support (timeout 00:02:30)
10973 11:48:16.050311 <4>[ 19.377352] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 11:48:16.054865
10975 11:48:16.055133 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10976 11:48:16.055227 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10977 11:48:16.055319 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10978 11:48:16.055402 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10979 11:48:16.055484 end: 2 depthcharge-action (duration 00:01:28) [common]
10980 11:48:16.055572 start: 3 lava-test-retry (timeout 00:08:11) [common]
10981 11:48:16.055659 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
10982 11:48:16.055731 Using namespace: common
10984 11:48:16.156070 / # #
10985 11:48:16.156204 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10986 11:48:16.156311 <6>[ 19.457430] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10987 11:48:16.156385 #<6>[ 19.465533] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10988 11:48:16.197715 <4>[ 19.500840] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 11:48:16.197801
10990 11:48:16.198051 Using /lava-12074018
10992 11:48:16.298384 / # export SHELL=/bin/sh
10993 11:48:16.298536 export SHELL=/bin/sh<3>[ 19.618784] mt7921e 0000:01:00.0: hardware init failed
10994 11:48:16.303502
10996 11:48:16.403990 / # . /lava-12074018/environment
10997 11:48:16.409188 . /lava-12074018/environment
10999 11:48:16.509701 / # /lava-12074018/bin/lava-test-runner /lava-12074018/0
11000 11:48:16.509827 Test shell timeout: 10s (minimum of the action and connection timeout)
11001 11:48:16.514697 /lava-12074018/bin/lava-test-runner /lava-12074018/0
11002 11:48:16.538845 + export TESTRUN_ID=0_v4l2-compliance-uvc
11003 11:48:16.542430 + cd /lava-12074018/0/tests/0_v4l2-compliance-uvc
11004 11:48:16.542515 + cat uuid
11005 11:48:16.545417 + UUID=12074018_1.5.2.3.1
11006 11:48:16.545500 + set +x
11007 11:48:16.552087 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12074018_1.5.2.3.1>
11008 11:48:16.552348 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12074018_1.5.2.3.1
11009 11:48:16.552421 Starting test lava.0_v4l2-compliance-uvc (12074018_1.5.2.3.1)
11010 11:48:16.552507 Skipping test definition patterns.
11011 11:48:16.555448 + /usr/bin/v4l2-parser.sh -d uvcvideo
11012 11:48:16.562046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11013 11:48:16.562129 device: /dev/video0
11014 11:48:16.562363 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11016 11:48:23.060720 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11017 11:48:23.073066 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11018 11:48:23.082369
11019 11:48:23.101016 Compliance test for uvcvideo device /dev/video0:
11020 11:48:23.108130
11021 11:48:23.119314 Driver Info:
11022 11:48:23.131842 Driver name : uvcvideo
11023 11:48:23.147979 Card type : HD User Facing: HD User Facing
11024 11:48:23.160959 Bus info : usb-11200000.usb-1.4.1
11025 11:48:23.170762 Driver version : 6.1.62
11026 11:48:23.181021 Capabilities : 0x84a00001
11027 11:48:23.196243 Metadata Capture
11028 11:48:23.206038 Streaming
11029 11:48:23.216917 Extended Pix Format
11030 11:48:23.228609 Device Capabilities
11031 11:48:23.240843 Device Caps : 0x04200001
11032 11:48:23.256727 Streaming
11033 11:48:23.267114 Extended Pix Format
11034 11:48:23.281745 Media Driver Info:
11035 11:48:23.294324 Driver name : uvcvideo
11036 11:48:23.312343 Model : HD User Facing: HD User Facing
11037 11:48:23.321888 Serial : 200901010001
11038 11:48:23.337509 Bus info : usb-11200000.usb-1.4.1
11039 11:48:23.345486 Media version : 6.1.62
11040 11:48:23.364603 Hardware revision: 0x00009758 (38744)
11041 11:48:23.371796 Driver version : 6.1.62
11042 11:48:23.386332 Interface Info:
11043 11:48:23.401770 <LAVA_SIGNAL_TESTSET START Interface-Info>
11044 11:48:23.401877 ID : 0x03000002
11045 11:48:23.402122 Received signal: <TESTSET> START Interface-Info
11046 11:48:23.402196 Starting test_set Interface-Info
11047 11:48:23.411242 Type : V4L Video
11048 11:48:23.421641 Entity Info:
11049 11:48:23.428279 <LAVA_SIGNAL_TESTSET STOP>
11050 11:48:23.428546 Received signal: <TESTSET> STOP
11051 11:48:23.428622 Closing test_set Interface-Info
11052 11:48:23.437332 <LAVA_SIGNAL_TESTSET START Entity-Info>
11053 11:48:23.437420 ID : 0x00000001 (1)
11054 11:48:23.437657 Received signal: <TESTSET> START Entity-Info
11055 11:48:23.437724 Starting test_set Entity-Info
11056 11:48:23.452421 Name : HD User Facing: HD User Facing
11057 11:48:23.460066 Function : V4L2 I/O
11058 11:48:23.472197 Flags : default
11059 11:48:23.481868 Pad 0x01000007 : 0: Sink
11060 11:48:23.503468 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11061 11:48:23.503584
11062 11:48:23.520715 Required ioctls:
11063 11:48:23.529442 <LAVA_SIGNAL_TESTSET STOP>
11064 11:48:23.529748 Received signal: <TESTSET> STOP
11065 11:48:23.529821 Closing test_set Entity-Info
11066 11:48:23.542779 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11067 11:48:23.543054 Received signal: <TESTSET> START Required-ioctls
11068 11:48:23.543141 Starting test_set Required-ioctls
11069 11:48:23.545907 test MC information (see 'Media Driver Info' above): OK
11070 11:48:23.572091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11071 11:48:23.572395 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11073 11:48:23.575090 test VIDIOC_QUERYCAP: OK
11074 11:48:23.593330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11075 11:48:23.593633 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11077 11:48:23.596754 test invalid ioctls: OK
11078 11:48:23.623143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11079 11:48:23.623258
11080 11:48:23.623497 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11082 11:48:23.634513 Allow for multiple opens:
11083 11:48:23.644004 <LAVA_SIGNAL_TESTSET STOP>
11084 11:48:23.644274 Received signal: <TESTSET> STOP
11085 11:48:23.644345 Closing test_set Required-ioctls
11086 11:48:23.653915 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11087 11:48:23.654185 Received signal: <TESTSET> START Allow-for-multiple-opens
11088 11:48:23.654259 Starting test_set Allow-for-multiple-opens
11089 11:48:23.657192 test second /dev/video0 open: OK
11090 11:48:23.682927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11091 11:48:23.683218 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11093 11:48:23.686011 test VIDIOC_QUERYCAP: OK
11094 11:48:23.708908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11095 11:48:23.709192 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11097 11:48:23.712393 test VIDIOC_G/S_PRIORITY: OK
11098 11:48:23.736427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11099 11:48:23.736715 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11101 11:48:23.739434 test for unlimited opens: OK
11102 11:48:23.761343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11103 11:48:23.761460
11104 11:48:23.761701 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11106 11:48:23.775399 Debug ioctls:
11107 11:48:23.784619 <LAVA_SIGNAL_TESTSET STOP>
11108 11:48:23.784896 Received signal: <TESTSET> STOP
11109 11:48:23.784969 Closing test_set Allow-for-multiple-opens
11110 11:48:23.795578 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11111 11:48:23.795848 Received signal: <TESTSET> START Debug-ioctls
11112 11:48:23.795923 Starting test_set Debug-ioctls
11113 11:48:23.799277 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11114 11:48:23.820507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11115 11:48:23.820783 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11117 11:48:23.826734 test VIDIOC_LOG_STATUS: OK (Not Supported)
11118 11:48:23.848289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11119 11:48:23.848409
11120 11:48:23.848649 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11122 11:48:23.858104 Input ioctls:
11123 11:48:23.865429 <LAVA_SIGNAL_TESTSET STOP>
11124 11:48:23.865695 Received signal: <TESTSET> STOP
11125 11:48:23.865767 Closing test_set Debug-ioctls
11126 11:48:23.874686 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11127 11:48:23.874941 Received signal: <TESTSET> START Input-ioctls
11128 11:48:23.875011 Starting test_set Input-ioctls
11129 11:48:23.877830 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11130 11:48:23.904099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11131 11:48:23.904371 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11133 11:48:23.907072 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11134 11:48:23.927758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11135 11:48:23.928021 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11137 11:48:23.934293 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11138 11:48:23.952591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11139 11:48:23.952873 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11141 11:48:23.955764 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11142 11:48:23.976266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11143 11:48:23.976536 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11145 11:48:23.979992 test VIDIOC_G/S/ENUMINPUT: OK
11146 11:48:24.001552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11147 11:48:24.001840 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11149 11:48:24.004495 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11150 11:48:24.027341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11151 11:48:24.027613 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11153 11:48:24.030405 Inputs: 1 Audio Inputs: 0 Tuners: 0
11154 11:48:24.040703
11155 11:48:24.056282 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11156 11:48:24.080527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11157 11:48:24.080800 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11159 11:48:24.087017 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11160 11:48:24.107338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11161 11:48:24.107597 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11163 11:48:24.114006 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11164 11:48:24.131149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11165 11:48:24.131411 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11167 11:48:24.137512 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11168 11:48:24.159463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11169 11:48:24.159740 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11171 11:48:24.166141 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11172 11:48:24.184416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11173 11:48:24.184506
11174 11:48:24.184742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11176 11:48:24.206625 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11177 11:48:24.228429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11178 11:48:24.228742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11180 11:48:24.235502 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11181 11:48:24.257971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11182 11:48:24.258243 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11184 11:48:24.261506 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11185 11:48:24.284633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11186 11:48:24.284910 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11188 11:48:24.287800 test VIDIOC_G/S_EDID: OK (Not Supported)
11189 11:48:24.308748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11190 11:48:24.308855
11191 11:48:24.309103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11193 11:48:24.318343 Control ioctls (Input 0):
11194 11:48:24.326558 <LAVA_SIGNAL_TESTSET STOP>
11195 11:48:24.326847 Received signal: <TESTSET> STOP
11196 11:48:24.326920 Closing test_set Input-ioctls
11197 11:48:24.336203 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11198 11:48:24.336476 Received signal: <TESTSET> START Control-ioctls-Input-0
11199 11:48:24.336575 Starting test_set Control-ioctls-Input-0
11200 11:48:24.339259 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11201 11:48:24.364498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11202 11:48:24.364597 test VIDIOC_QUERYCTRL: OK
11203 11:48:24.364832 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11205 11:48:24.389473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11206 11:48:24.389797 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11208 11:48:24.392981 test VIDIOC_G/S_CTRL: OK
11209 11:48:24.416234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11210 11:48:24.416529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11212 11:48:24.419218 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11213 11:48:24.442193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11214 11:48:24.442482 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11216 11:48:24.448990 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11217 11:48:24.470532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11218 11:48:24.470830 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11220 11:48:24.473482 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11221 11:48:24.493241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11222 11:48:24.493525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11224 11:48:24.496691 Standard Controls: 16 Private Controls: 0
11225 11:48:24.505330
11226 11:48:24.520448 Format ioctls (Input 0):
11227 11:48:24.526396 <LAVA_SIGNAL_TESTSET STOP>
11228 11:48:24.526656 Received signal: <TESTSET> STOP
11229 11:48:24.526725 Closing test_set Control-ioctls-Input-0
11230 11:48:24.536766 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11231 11:48:24.537050 Received signal: <TESTSET> START Format-ioctls-Input-0
11232 11:48:24.537124 Starting test_set Format-ioctls-Input-0
11233 11:48:24.539843 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11234 11:48:24.564239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11235 11:48:24.564541 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11237 11:48:24.567294 test VIDIOC_G/S_PARM: OK
11238 11:48:24.585572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11239 11:48:24.585886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11241 11:48:24.588624 test VIDIOC_G_FBUF: OK (Not Supported)
11242 11:48:24.612247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11243 11:48:24.612526 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11245 11:48:24.615630 test VIDIOC_G_FMT: OK
11246 11:48:24.638079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11247 11:48:24.638368 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11249 11:48:24.641034 test VIDIOC_TRY_FMT: OK
11250 11:48:24.661910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11251 11:48:24.662198 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11253 11:48:24.668594 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11254 11:48:24.677119 test VIDIOC_S_FMT: OK
11255 11:48:24.705008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11256 11:48:24.705299 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11258 11:48:24.708513 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11259 11:48:24.730969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11260 11:48:24.731270 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11262 11:48:24.734495 test Cropping: OK (Not Supported)
11263 11:48:24.756498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11264 11:48:24.756789 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11266 11:48:24.760364 test Composing: OK (Not Supported)
11267 11:48:24.783078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11268 11:48:24.783345 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11270 11:48:24.786252 test Scaling: OK (Not Supported)
11271 11:48:24.811631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11272 11:48:24.811742
11273 11:48:24.811982 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11275 11:48:24.822221 Codec ioctls (Input 0):
11276 11:48:24.829917 <LAVA_SIGNAL_TESTSET STOP>
11277 11:48:24.830178 Received signal: <TESTSET> STOP
11278 11:48:24.830248 Closing test_set Format-ioctls-Input-0
11279 11:48:24.838645 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11280 11:48:24.838902 Received signal: <TESTSET> START Codec-ioctls-Input-0
11281 11:48:24.838989 Starting test_set Codec-ioctls-Input-0
11282 11:48:24.842323 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11283 11:48:24.863455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11284 11:48:24.863738 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11286 11:48:24.869697 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11287 11:48:24.888900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11288 11:48:24.889172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11290 11:48:24.895239 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11291 11:48:24.914431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11292 11:48:24.914531
11293 11:48:24.914768 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11295 11:48:24.925448 Buffer ioctls (Input 0):
11296 11:48:24.935369 <LAVA_SIGNAL_TESTSET STOP>
11297 11:48:24.935636 Received signal: <TESTSET> STOP
11298 11:48:24.935707 Closing test_set Codec-ioctls-Input-0
11299 11:48:24.945797 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11300 11:48:24.946075 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11301 11:48:24.946162 Starting test_set Buffer-ioctls-Input-0
11302 11:48:24.949414 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11303 11:48:24.973357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11304 11:48:24.973477 test VIDIOC_EXPBUF: OK
11305 11:48:24.973719 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11307 11:48:25.000920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11308 11:48:25.001202 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11310 11:48:25.004028 test Requests: OK (Not Supported)
11311 11:48:25.027944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11312 11:48:25.028042
11313 11:48:25.028279 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11315 11:48:25.043599 Test input 0:
11316 11:48:25.057004
11317 11:48:25.068030 Streaming ioctls:
11318 11:48:25.075544 <LAVA_SIGNAL_TESTSET STOP>
11319 11:48:25.075802 Received signal: <TESTSET> STOP
11320 11:48:25.075876 Closing test_set Buffer-ioctls-Input-0
11321 11:48:25.085036 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11322 11:48:25.085298 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11323 11:48:25.085368 Starting test_set Streaming-ioctls_Test-input-0
11324 11:48:25.088225 test read/write: OK (Not Supported)
11325 11:48:25.111846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11326 11:48:25.112132 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11328 11:48:25.114689 test blocking wait: OK
11329 11:48:25.135376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11330 11:48:25.135652 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11332 11:48:25.145775 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11333 11:48:25.145867 test MMAP (no poll): FAIL
11334 11:48:25.172267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11335 11:48:25.172555 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11337 11:48:25.182250 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11338 11:48:25.185452 test MMAP (select): FAIL
11339 11:48:25.208854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11340 11:48:25.209138 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11342 11:48:25.219033 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11343 11:48:25.222134 test MMAP (epoll): FAIL
11344 11:48:25.245845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11345 11:48:25.245951
11346 11:48:25.246190 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11348 11:48:25.258245
11349 11:48:25.444195
11350 11:48:25.453476 test USERPTR (no poll): OK
11351 11:48:25.480244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11352 11:48:25.480365
11353 11:48:25.480606 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11355 11:48:25.495889
11356 11:48:25.691959
11357 11:48:25.700811 test USERPTR (select): OK
11358 11:48:25.727325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11359 11:48:25.727608 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11361 11:48:25.734133 test DMABUF: Cannot test, specify --expbuf-device
11362 11:48:25.738620
11363 11:48:25.755326 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11364 11:48:25.761283 <LAVA_TEST_RUNNER EXIT>
11365 11:48:25.761573 ok: lava_test_shell seems to have completed
11366 11:48:25.761687 Marking unfinished test run as failed
11368 11:48:25.762611 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11369 11:48:25.762735 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11370 11:48:25.762823 end: 3 lava-test-retry (duration 00:00:10) [common]
11371 11:48:25.762911 start: 4 finalize (timeout 00:08:01) [common]
11372 11:48:25.763001 start: 4.1 power-off (timeout 00:00:30) [common]
11373 11:48:25.763213 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11374 11:48:25.841597 >> Command sent successfully.
11375 11:48:25.844155 Returned 0 in 0 seconds
11376 11:48:25.944549 end: 4.1 power-off (duration 00:00:00) [common]
11378 11:48:25.944966 start: 4.2 read-feedback (timeout 00:08:01) [common]
11379 11:48:25.945275 Listened to connection for namespace 'common' for up to 1s
11380 11:48:26.945669 Finalising connection for namespace 'common'
11381 11:48:26.945835 Disconnecting from shell: Finalise
11382 11:48:26.945920 / #
11383 11:48:27.046251 end: 4.2 read-feedback (duration 00:00:01) [common]
11384 11:48:27.046437 end: 4 finalize (duration 00:00:01) [common]
11385 11:48:27.046548 Cleaning after the job
11386 11:48:27.046652 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/ramdisk
11387 11:48:27.052553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/kernel
11388 11:48:27.068215 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/dtb
11389 11:48:27.068433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074018/tftp-deploy-i3e52gb4/modules
11390 11:48:27.075969 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074018
11391 11:48:27.144207 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074018
11392 11:48:27.144381 Job finished correctly