Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 28
- Kernel Warnings: 19
- Boot result: PASS
- Errors: 1
1 11:44:10.160106 lava-dispatcher, installed at version: 2023.10
2 11:44:10.160325 start: 0 validate
3 11:44:10.160461 Start time: 2023-11-24 11:44:10.160454+00:00 (UTC)
4 11:44:10.160576 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:44:10.160705 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:44:10.431295 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:44:10.432041 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:25.713197 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:25.713955 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:25.986776 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:25.987633 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:44:30.755100 validate duration: 20.59
14 11:44:30.755374 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:44:30.755474 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:44:30.755557 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:44:30.755678 Not decompressing ramdisk as can be used compressed.
18 11:44:30.755766 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 11:44:30.755828 saving as /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/ramdisk/rootfs.cpio.gz
20 11:44:30.755890 total size: 8181372 (7 MB)
21 11:44:30.756979 progress 0 % (0 MB)
22 11:44:30.759328 progress 5 % (0 MB)
23 11:44:30.761414 progress 10 % (0 MB)
24 11:44:30.763708 progress 15 % (1 MB)
25 11:44:30.765824 progress 20 % (1 MB)
26 11:44:30.768121 progress 25 % (1 MB)
27 11:44:30.770214 progress 30 % (2 MB)
28 11:44:30.772520 progress 35 % (2 MB)
29 11:44:30.774611 progress 40 % (3 MB)
30 11:44:30.776906 progress 45 % (3 MB)
31 11:44:30.779037 progress 50 % (3 MB)
32 11:44:30.781259 progress 55 % (4 MB)
33 11:44:30.783360 progress 60 % (4 MB)
34 11:44:30.785685 progress 65 % (5 MB)
35 11:44:30.787823 progress 70 % (5 MB)
36 11:44:30.790037 progress 75 % (5 MB)
37 11:44:30.792197 progress 80 % (6 MB)
38 11:44:30.794413 progress 85 % (6 MB)
39 11:44:30.796500 progress 90 % (7 MB)
40 11:44:30.798697 progress 95 % (7 MB)
41 11:44:30.800801 progress 100 % (7 MB)
42 11:44:30.800995 7 MB downloaded in 0.05 s (172.98 MB/s)
43 11:44:30.801148 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:44:30.801386 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:44:30.801470 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:44:30.801551 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:44:30.801687 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:44:30.801759 saving as /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/kernel/Image
50 11:44:30.801817 total size: 49107456 (46 MB)
51 11:44:30.801875 No compression specified
52 11:44:30.803031 progress 0 % (0 MB)
53 11:44:30.815781 progress 5 % (2 MB)
54 11:44:30.828574 progress 10 % (4 MB)
55 11:44:30.841480 progress 15 % (7 MB)
56 11:44:30.854319 progress 20 % (9 MB)
57 11:44:30.867232 progress 25 % (11 MB)
58 11:44:30.879855 progress 30 % (14 MB)
59 11:44:30.892685 progress 35 % (16 MB)
60 11:44:30.907246 progress 40 % (18 MB)
61 11:44:30.920068 progress 45 % (21 MB)
62 11:44:30.933048 progress 50 % (23 MB)
63 11:44:30.945891 progress 55 % (25 MB)
64 11:44:30.958857 progress 60 % (28 MB)
65 11:44:30.971759 progress 65 % (30 MB)
66 11:44:30.984555 progress 70 % (32 MB)
67 11:44:30.997066 progress 75 % (35 MB)
68 11:44:31.010128 progress 80 % (37 MB)
69 11:44:31.022991 progress 85 % (39 MB)
70 11:44:31.035990 progress 90 % (42 MB)
71 11:44:31.048535 progress 95 % (44 MB)
72 11:44:31.061564 progress 100 % (46 MB)
73 11:44:31.061809 46 MB downloaded in 0.26 s (180.13 MB/s)
74 11:44:31.061960 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:44:31.062185 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:44:31.062277 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:44:31.062364 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:44:31.062500 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:44:31.062568 saving as /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/dtb/mt8192-asurada-spherion-r0.dtb
81 11:44:31.062628 total size: 47278 (0 MB)
82 11:44:31.062688 No compression specified
83 11:44:31.064003 progress 69 % (0 MB)
84 11:44:31.064282 progress 100 % (0 MB)
85 11:44:31.064437 0 MB downloaded in 0.00 s (24.95 MB/s)
86 11:44:31.064558 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:44:31.064774 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:44:31.064864 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:44:31.064944 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:44:31.065056 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:44:31.065126 saving as /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/modules/modules.tar
93 11:44:31.065185 total size: 8624756 (8 MB)
94 11:44:31.065244 Using unxz to decompress xz
95 11:44:31.069653 progress 0 % (0 MB)
96 11:44:31.090811 progress 5 % (0 MB)
97 11:44:31.114793 progress 10 % (0 MB)
98 11:44:31.138679 progress 15 % (1 MB)
99 11:44:31.163046 progress 20 % (1 MB)
100 11:44:31.188567 progress 25 % (2 MB)
101 11:44:31.215460 progress 30 % (2 MB)
102 11:44:31.242626 progress 35 % (2 MB)
103 11:44:31.266790 progress 40 % (3 MB)
104 11:44:31.291652 progress 45 % (3 MB)
105 11:44:31.317707 progress 50 % (4 MB)
106 11:44:31.342656 progress 55 % (4 MB)
107 11:44:31.368188 progress 60 % (4 MB)
108 11:44:31.396417 progress 65 % (5 MB)
109 11:44:31.422070 progress 70 % (5 MB)
110 11:44:31.446029 progress 75 % (6 MB)
111 11:44:31.475307 progress 80 % (6 MB)
112 11:44:31.503116 progress 85 % (7 MB)
113 11:44:31.530362 progress 90 % (7 MB)
114 11:44:31.563623 progress 95 % (7 MB)
115 11:44:31.593971 progress 100 % (8 MB)
116 11:44:31.599263 8 MB downloaded in 0.53 s (15.40 MB/s)
117 11:44:31.599530 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:44:31.599800 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:44:31.599902 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:44:31.599999 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:44:31.600079 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:44:31.600169 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:44:31.600398 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc
125 11:44:31.600533 makedir: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin
126 11:44:31.600640 makedir: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/tests
127 11:44:31.600740 makedir: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/results
128 11:44:31.600860 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-add-keys
129 11:44:31.601011 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-add-sources
130 11:44:31.601141 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-background-process-start
131 11:44:31.601271 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-background-process-stop
132 11:44:31.601398 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-common-functions
133 11:44:31.601523 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-echo-ipv4
134 11:44:31.601651 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-install-packages
135 11:44:31.601775 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-installed-packages
136 11:44:31.601905 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-os-build
137 11:44:31.602031 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-probe-channel
138 11:44:31.602156 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-probe-ip
139 11:44:31.602281 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-target-ip
140 11:44:31.602405 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-target-mac
141 11:44:31.602526 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-target-storage
142 11:44:31.602654 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-case
143 11:44:31.602778 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-event
144 11:44:31.602907 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-feedback
145 11:44:31.603033 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-raise
146 11:44:31.603160 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-reference
147 11:44:31.603286 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-runner
148 11:44:31.603411 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-set
149 11:44:31.603536 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-test-shell
150 11:44:31.603664 Updating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-install-packages (oe)
151 11:44:31.603826 Updating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/bin/lava-installed-packages (oe)
152 11:44:31.604004 Creating /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/environment
153 11:44:31.604115 LAVA metadata
154 11:44:31.604190 - LAVA_JOB_ID=12074023
155 11:44:31.604255 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:44:31.604358 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:44:31.604424 skipped lava-vland-overlay
158 11:44:31.604498 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:44:31.604583 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:44:31.604647 skipped lava-multinode-overlay
161 11:44:31.604721 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:44:31.604803 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:44:31.604877 Loading test definitions
164 11:44:31.604966 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:44:31.605038 Using /lava-12074023 at stage 0
166 11:44:31.605358 uuid=12074023_1.5.2.3.1 testdef=None
167 11:44:31.605445 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:44:31.605529 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:44:31.606068 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:44:31.606292 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:44:31.606961 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:44:31.607192 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:44:31.607818 runner path: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/0/tests/0_dmesg test_uuid 12074023_1.5.2.3.1
176 11:44:31.607975 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:44:31.608205 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 11:44:31.608275 Using /lava-12074023 at stage 1
180 11:44:31.608580 uuid=12074023_1.5.2.3.5 testdef=None
181 11:44:31.608666 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 11:44:31.608748 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 11:44:31.609223 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 11:44:31.609439 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 11:44:31.610615 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 11:44:31.610845 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 11:44:31.611497 runner path: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/1/tests/1_bootrr test_uuid 12074023_1.5.2.3.5
190 11:44:31.611651 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 11:44:31.611857 Creating lava-test-runner.conf files
193 11:44:31.611921 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/0 for stage 0
194 11:44:31.612012 - 0_dmesg
195 11:44:31.612091 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074023/lava-overlay-_b_2e3vc/lava-12074023/1 for stage 1
196 11:44:31.612181 - 1_bootrr
197 11:44:31.612273 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 11:44:31.612356 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 11:44:31.620457 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 11:44:31.620582 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 11:44:31.620670 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 11:44:31.620756 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 11:44:31.620840 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 11:44:31.875850 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 11:44:31.876252 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 11:44:31.876367 extracting modules file /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074023/extract-overlay-ramdisk-z239kvfg/ramdisk
207 11:44:32.099362 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 11:44:32.099535 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 11:44:32.099636 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074023/compress-overlay-xim19h0e/overlay-1.5.2.4.tar.gz to ramdisk
210 11:44:32.099708 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074023/compress-overlay-xim19h0e/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074023/extract-overlay-ramdisk-z239kvfg/ramdisk
211 11:44:32.108057 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 11:44:32.108195 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 11:44:32.108287 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 11:44:32.108373 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 11:44:32.108456 Building ramdisk /var/lib/lava/dispatcher/tmp/12074023/extract-overlay-ramdisk-z239kvfg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074023/extract-overlay-ramdisk-z239kvfg/ramdisk
216 11:44:32.556258 >> 145311 blocks
217 11:44:34.888087 rename /var/lib/lava/dispatcher/tmp/12074023/extract-overlay-ramdisk-z239kvfg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/ramdisk/ramdisk.cpio.gz
218 11:44:34.888563 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 11:44:34.888721 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 11:44:34.888843 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 11:44:34.888963 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/kernel/Image'
222 11:44:48.231005 Returned 0 in 13 seconds
223 11:44:48.331672 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/kernel/image.itb
224 11:44:48.735264 output: FIT description: Kernel Image image with one or more FDT blobs
225 11:44:48.735638 output: Created: Fri Nov 24 11:44:48 2023
226 11:44:48.735716 output: Image 0 (kernel-1)
227 11:44:48.735781 output: Description:
228 11:44:48.735845 output: Created: Fri Nov 24 11:44:48 2023
229 11:44:48.735905 output: Type: Kernel Image
230 11:44:48.735962 output: Compression: lzma compressed
231 11:44:48.736024 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
232 11:44:48.736118 output: Architecture: AArch64
233 11:44:48.736200 output: OS: Linux
234 11:44:48.736261 output: Load Address: 0x00000000
235 11:44:48.736318 output: Entry Point: 0x00000000
236 11:44:48.736376 output: Hash algo: crc32
237 11:44:48.736433 output: Hash value: 43cfb6ad
238 11:44:48.736490 output: Image 1 (fdt-1)
239 11:44:48.736546 output: Description: mt8192-asurada-spherion-r0
240 11:44:48.736598 output: Created: Fri Nov 24 11:44:48 2023
241 11:44:48.736651 output: Type: Flat Device Tree
242 11:44:48.736703 output: Compression: uncompressed
243 11:44:48.736755 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 11:44:48.736807 output: Architecture: AArch64
245 11:44:48.736859 output: Hash algo: crc32
246 11:44:48.736911 output: Hash value: cc4352de
247 11:44:48.736963 output: Image 2 (ramdisk-1)
248 11:44:48.737014 output: Description: unavailable
249 11:44:48.737066 output: Created: Fri Nov 24 11:44:48 2023
250 11:44:48.737119 output: Type: RAMDisk Image
251 11:44:48.737171 output: Compression: Unknown Compression
252 11:44:48.737222 output: Data Size: 21376211 Bytes = 20875.21 KiB = 20.39 MiB
253 11:44:48.737274 output: Architecture: AArch64
254 11:44:48.737325 output: OS: Linux
255 11:44:48.737377 output: Load Address: unavailable
256 11:44:48.737428 output: Entry Point: unavailable
257 11:44:48.737480 output: Hash algo: crc32
258 11:44:48.737530 output: Hash value: 55921bae
259 11:44:48.737582 output: Default Configuration: 'conf-1'
260 11:44:48.737633 output: Configuration 0 (conf-1)
261 11:44:48.737684 output: Description: mt8192-asurada-spherion-r0
262 11:44:48.737735 output: Kernel: kernel-1
263 11:44:48.737785 output: Init Ramdisk: ramdisk-1
264 11:44:48.737837 output: FDT: fdt-1
265 11:44:48.737888 output: Loadables: kernel-1
266 11:44:48.737940 output:
267 11:44:48.738149 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 11:44:48.738253 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 11:44:48.738355 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 11:44:48.738456 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 11:44:48.738534 No LXC device requested
272 11:44:48.738623 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 11:44:48.738711 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 11:44:48.738799 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 11:44:48.738935 Checking files for TFTP limit of 4294967296 bytes.
276 11:44:48.739452 end: 1 tftp-deploy (duration 00:00:18) [common]
277 11:44:48.739554 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 11:44:48.739651 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 11:44:48.739777 substitutions:
280 11:44:48.739842 - {DTB}: 12074023/tftp-deploy-e2gwny5j/dtb/mt8192-asurada-spherion-r0.dtb
281 11:44:48.739903 - {INITRD}: 12074023/tftp-deploy-e2gwny5j/ramdisk/ramdisk.cpio.gz
282 11:44:48.739961 - {KERNEL}: 12074023/tftp-deploy-e2gwny5j/kernel/Image
283 11:44:48.740017 - {LAVA_MAC}: None
284 11:44:48.740072 - {PRESEED_CONFIG}: None
285 11:44:48.740176 - {PRESEED_LOCAL}: None
286 11:44:48.740232 - {RAMDISK}: 12074023/tftp-deploy-e2gwny5j/ramdisk/ramdisk.cpio.gz
287 11:44:48.740286 - {ROOT_PART}: None
288 11:44:48.740339 - {ROOT}: None
289 11:44:48.740392 - {SERVER_IP}: 192.168.201.1
290 11:44:48.740445 - {TEE}: None
291 11:44:48.740498 Parsed boot commands:
292 11:44:48.740551 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 11:44:48.740732 Parsed boot commands: tftpboot 192.168.201.1 12074023/tftp-deploy-e2gwny5j/kernel/image.itb 12074023/tftp-deploy-e2gwny5j/kernel/cmdline
294 11:44:48.740823 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 11:44:48.740907 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 11:44:48.741000 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 11:44:48.741084 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 11:44:48.741163 Not connected, no need to disconnect.
299 11:44:48.741235 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 11:44:48.741317 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 11:44:48.741385 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
302 11:44:48.745576 Setting prompt string to ['lava-test: # ']
303 11:44:48.745980 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 11:44:48.746132 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 11:44:48.746298 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 11:44:48.746622 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 11:44:48.746821 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
308 11:44:53.883645 >> Command sent successfully.
309 11:44:53.886589 Returned 0 in 5 seconds
310 11:44:53.987024 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 11:44:53.987361 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 11:44:53.987463 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 11:44:53.987555 Setting prompt string to 'Starting depthcharge on Spherion...'
315 11:44:53.987623 Changing prompt to 'Starting depthcharge on Spherion...'
316 11:44:53.987690 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 11:44:53.988048 [Enter `^Ec?' for help]
318 11:44:54.163215
319 11:44:54.163361
320 11:44:54.163430 F0: 102B 0000
321 11:44:54.163496
322 11:44:54.163558 F3: 1001 0000 [0200]
323 11:44:54.163615
324 11:44:54.166282 F3: 1001 0000
325 11:44:54.166386
326 11:44:54.166464 F7: 102D 0000
327 11:44:54.166524
328 11:44:54.166610 F1: 0000 0000
329 11:44:54.169823
330 11:44:54.169905 V0: 0000 0000 [0001]
331 11:44:54.169974
332 11:44:54.170034 00: 0007 8000
333 11:44:54.170096
334 11:44:54.173216 01: 0000 0000
335 11:44:54.173299
336 11:44:54.173363 BP: 0C00 0209 [0000]
337 11:44:54.173424
338 11:44:54.176550 G0: 1182 0000
339 11:44:54.176631
340 11:44:54.176694 EC: 0000 0021 [4000]
341 11:44:54.176754
342 11:44:54.180263 S7: 0000 0000 [0000]
343 11:44:54.180344
344 11:44:54.180408 CC: 0000 0000 [0001]
345 11:44:54.180466
346 11:44:54.183656 T0: 0000 0040 [010F]
347 11:44:54.183738
348 11:44:54.183802 Jump to BL
349 11:44:54.183861
350 11:44:54.210327
351 11:44:54.210456
352 11:44:54.210523
353 11:44:54.217712 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 11:44:54.221107 ARM64: Exception handlers installed.
355 11:44:54.224996 ARM64: Testing exception
356 11:44:54.225084 ARM64: Done test exception
357 11:44:54.235156 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 11:44:54.245374 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 11:44:54.251902 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 11:44:54.261759 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 11:44:54.268396 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 11:44:54.275185 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 11:44:54.286383 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 11:44:54.293288 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 11:44:54.312294 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 11:44:54.315774 WDT: Last reset was cold boot
367 11:44:54.319290 SPI1(PAD0) initialized at 2873684 Hz
368 11:44:54.322357 SPI5(PAD0) initialized at 992727 Hz
369 11:44:54.325934 VBOOT: Loading verstage.
370 11:44:54.332332 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 11:44:54.335872 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 11:44:54.339224 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 11:44:54.342557 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 11:44:54.349920 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 11:44:54.356384 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 11:44:54.367488 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 11:44:54.367580
378 11:44:54.367646
379 11:44:54.377247 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 11:44:54.380730 ARM64: Exception handlers installed.
381 11:44:54.384457 ARM64: Testing exception
382 11:44:54.384539 ARM64: Done test exception
383 11:44:54.390581 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 11:44:54.394195 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 11:44:54.408319 Probing TPM: . done!
386 11:44:54.408429 TPM ready after 0 ms
387 11:44:54.415256 Connected to device vid:did:rid of 1ae0:0028:00
388 11:44:54.422343 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 11:44:54.479232 Initialized TPM device CR50 revision 0
390 11:44:54.492108 tlcl_send_startup: Startup return code is 0
391 11:44:54.492221 TPM: setup succeeded
392 11:44:54.503151 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 11:44:54.512044 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 11:44:54.523076 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 11:44:54.532737 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 11:44:54.536165 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 11:44:54.545404 in-header: 03 07 00 00 08 00 00 00
398 11:44:54.549117 in-data: aa e4 47 04 13 02 00 00
399 11:44:54.552261 Chrome EC: UHEPI supported
400 11:44:54.559423 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 11:44:54.563442 in-header: 03 ad 00 00 08 00 00 00
402 11:44:54.566810 in-data: 00 20 20 08 00 00 00 00
403 11:44:54.566917 Phase 1
404 11:44:54.570644 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 11:44:54.574526 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 11:44:54.582518 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 11:44:54.586134 Recovery requested (1009000e)
408 11:44:54.594021 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 11:44:54.599239 tlcl_extend: response is 0
410 11:44:54.608288 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 11:44:54.613780 tlcl_extend: response is 0
412 11:44:54.620694 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 11:44:54.640909 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 11:44:54.647559 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 11:44:54.647655
416 11:44:54.647720
417 11:44:54.657762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 11:44:54.661464 ARM64: Exception handlers installed.
419 11:44:54.661593 ARM64: Testing exception
420 11:44:54.664753 ARM64: Done test exception
421 11:44:54.685835 pmic_efuse_setting: Set efuses in 11 msecs
422 11:44:54.689994 pmwrap_interface_init: Select PMIF_VLD_RDY
423 11:44:54.696203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 11:44:54.699765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 11:44:54.706602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 11:44:54.710260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 11:44:54.713996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 11:44:54.717889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 11:44:54.726000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 11:44:54.729800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 11:44:54.733463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 11:44:54.740126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 11:44:54.743885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 11:44:54.748091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 11:44:54.751905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 11:44:54.759309 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 11:44:54.762618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 11:44:54.769818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 11:44:54.777434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 11:44:54.781142 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 11:44:54.788865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 11:44:54.792511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 11:44:54.799579 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 11:44:54.803197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 11:44:54.810645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 11:44:54.813830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 11:44:54.821471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 11:44:54.825241 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 11:44:54.829080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 11:44:54.836044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 11:44:54.839897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 11:44:54.843661 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 11:44:54.850816 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 11:44:54.854045 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 11:44:54.861471 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 11:44:54.864939 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 11:44:54.869334 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 11:44:54.876695 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 11:44:54.879742 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 11:44:54.883530 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 11:44:54.891323 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 11:44:54.894709 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 11:44:54.898718 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 11:44:54.902582 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 11:44:54.905584 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 11:44:54.913132 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 11:44:54.917027 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 11:44:54.920889 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 11:44:54.924481 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 11:44:54.928219 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 11:44:54.932204 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 11:44:54.935430 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 11:44:54.942721 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 11:44:54.950493 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 11:44:54.957473 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 11:44:54.960658 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 11:44:54.968405 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 11:44:54.980097 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 11:44:54.983458 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 11:44:54.987377 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 11:44:54.990686 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 11:44:55.000075 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x26
483 11:44:55.003652 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 11:44:55.011449 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 11:44:55.014834 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 11:44:55.023500 [RTC]rtc_get_frequency_meter,154: input=15, output=788
487 11:44:55.033686 [RTC]rtc_get_frequency_meter,154: input=23, output=978
488 11:44:55.043172 [RTC]rtc_get_frequency_meter,154: input=19, output=884
489 11:44:55.052049 [RTC]rtc_get_frequency_meter,154: input=17, output=838
490 11:44:55.061620 [RTC]rtc_get_frequency_meter,154: input=16, output=814
491 11:44:55.071057 [RTC]rtc_get_frequency_meter,154: input=15, output=790
492 11:44:55.081087 [RTC]rtc_get_frequency_meter,154: input=16, output=813
493 11:44:55.084268 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
494 11:44:55.091679 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
495 11:44:55.095603 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 11:44:55.098737 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 11:44:55.102448 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 11:44:55.106382 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 11:44:55.109847 ADC[4]: Raw value=900590 ID=7
500 11:44:55.113514 ADC[3]: Raw value=213336 ID=1
501 11:44:55.113602 RAM Code: 0x71
502 11:44:55.117218 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 11:44:55.124600 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 11:44:55.132538 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 11:44:55.139790 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 11:44:55.143300 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 11:44:55.146393 in-header: 03 07 00 00 08 00 00 00
508 11:44:55.150349 in-data: aa e4 47 04 13 02 00 00
509 11:44:55.150435 Chrome EC: UHEPI supported
510 11:44:55.157868 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 11:44:55.161581 in-header: 03 ed 00 00 08 00 00 00
512 11:44:55.165668 in-data: 80 20 60 08 00 00 00 00
513 11:44:55.168738 MRC: failed to locate region type 0.
514 11:44:55.176443 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 11:44:55.180137 DRAM-K: Running full calibration
516 11:44:55.183901 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 11:44:55.187359 header.status = 0x0
518 11:44:55.191094 header.version = 0x6 (expected: 0x6)
519 11:44:55.195148 header.size = 0xd00 (expected: 0xd00)
520 11:44:55.195234 header.flags = 0x0
521 11:44:55.201754 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 11:44:55.220002 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 11:44:55.226746 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 11:44:55.230591 dram_init: ddr_geometry: 2
525 11:44:55.230680 [EMI] MDL number = 2
526 11:44:55.234054 [EMI] Get MDL freq = 0
527 11:44:55.234138 dram_init: ddr_type: 0
528 11:44:55.237837 is_discrete_lpddr4: 1
529 11:44:55.241374 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 11:44:55.241459
531 11:44:55.241524
532 11:44:55.241583 [Bian_co] ETT version 0.0.0.1
533 11:44:55.248338 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 11:44:55.248428
535 11:44:55.252800 dramc_set_vcore_voltage set vcore to 650000
536 11:44:55.252887 Read voltage for 800, 4
537 11:44:55.255847 Vio18 = 0
538 11:44:55.255978 Vcore = 650000
539 11:44:55.256076 Vdram = 0
540 11:44:55.259834 Vddq = 0
541 11:44:55.259917 Vmddr = 0
542 11:44:55.259982 dram_init: config_dvfs: 1
543 11:44:55.266911 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 11:44:55.270515 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 11:44:55.274648 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
546 11:44:55.277916 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
547 11:44:55.281310 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
548 11:44:55.288142 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
549 11:44:55.288231 MEM_TYPE=3, freq_sel=18
550 11:44:55.291251 sv_algorithm_assistance_LP4_1600
551 11:44:55.294513 ============ PULL DRAM RESETB DOWN ============
552 11:44:55.301487 ========== PULL DRAM RESETB DOWN end =========
553 11:44:55.304437 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 11:44:55.308021 ===================================
555 11:44:55.311679 LPDDR4 DRAM CONFIGURATION
556 11:44:55.314804 ===================================
557 11:44:55.314932 EX_ROW_EN[0] = 0x0
558 11:44:55.318404 EX_ROW_EN[1] = 0x0
559 11:44:55.318511 LP4Y_EN = 0x0
560 11:44:55.321399 WORK_FSP = 0x0
561 11:44:55.321484 WL = 0x2
562 11:44:55.325033 RL = 0x2
563 11:44:55.325117 BL = 0x2
564 11:44:55.328083 RPST = 0x0
565 11:44:55.331469 RD_PRE = 0x0
566 11:44:55.331553 WR_PRE = 0x1
567 11:44:55.335136 WR_PST = 0x0
568 11:44:55.335218 DBI_WR = 0x0
569 11:44:55.338021 DBI_RD = 0x0
570 11:44:55.338102 OTF = 0x1
571 11:44:55.341629 ===================================
572 11:44:55.345323 ===================================
573 11:44:55.345408 ANA top config
574 11:44:55.348388 ===================================
575 11:44:55.351852 DLL_ASYNC_EN = 0
576 11:44:55.355107 ALL_SLAVE_EN = 1
577 11:44:55.358569 NEW_RANK_MODE = 1
578 11:44:55.358658 DLL_IDLE_MODE = 1
579 11:44:55.362009 LP45_APHY_COMB_EN = 1
580 11:44:55.365494 TX_ODT_DIS = 1
581 11:44:55.369007 NEW_8X_MODE = 1
582 11:44:55.372080 ===================================
583 11:44:55.375246 ===================================
584 11:44:55.378822 data_rate = 1600
585 11:44:55.378976 CKR = 1
586 11:44:55.382499 DQ_P2S_RATIO = 8
587 11:44:55.385301 ===================================
588 11:44:55.388914 CA_P2S_RATIO = 8
589 11:44:55.392179 DQ_CA_OPEN = 0
590 11:44:55.395826 DQ_SEMI_OPEN = 0
591 11:44:55.395909 CA_SEMI_OPEN = 0
592 11:44:55.398618 CA_FULL_RATE = 0
593 11:44:55.402508 DQ_CKDIV4_EN = 1
594 11:44:55.405932 CA_CKDIV4_EN = 1
595 11:44:55.408807 CA_PREDIV_EN = 0
596 11:44:55.412103 PH8_DLY = 0
597 11:44:55.412187 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 11:44:55.415876 DQ_AAMCK_DIV = 4
599 11:44:55.419266 CA_AAMCK_DIV = 4
600 11:44:55.422252 CA_ADMCK_DIV = 4
601 11:44:55.425985 DQ_TRACK_CA_EN = 0
602 11:44:55.429095 CA_PICK = 800
603 11:44:55.429180 CA_MCKIO = 800
604 11:44:55.432706 MCKIO_SEMI = 0
605 11:44:55.436027 PLL_FREQ = 3068
606 11:44:55.440563 DQ_UI_PI_RATIO = 32
607 11:44:55.444037 CA_UI_PI_RATIO = 0
608 11:44:55.444121 ===================================
609 11:44:55.447598 ===================================
610 11:44:55.451525 memory_type:LPDDR4
611 11:44:55.455241 GP_NUM : 10
612 11:44:55.455324 SRAM_EN : 1
613 11:44:55.458408 MD32_EN : 0
614 11:44:55.458490 ===================================
615 11:44:55.462812 [ANA_INIT] >>>>>>>>>>>>>>
616 11:44:55.466548 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 11:44:55.469700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 11:44:55.473434 ===================================
619 11:44:55.476806 data_rate = 1600,PCW = 0X7600
620 11:44:55.476892 ===================================
621 11:44:55.483321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 11:44:55.486557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 11:44:55.493770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 11:44:55.496609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 11:44:55.500019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 11:44:55.503753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 11:44:55.507136 [ANA_INIT] flow start
628 11:44:55.507221 [ANA_INIT] PLL >>>>>>>>
629 11:44:55.510443 [ANA_INIT] PLL <<<<<<<<
630 11:44:55.513741 [ANA_INIT] MIDPI >>>>>>>>
631 11:44:55.516953 [ANA_INIT] MIDPI <<<<<<<<
632 11:44:55.517035 [ANA_INIT] DLL >>>>>>>>
633 11:44:55.520285 [ANA_INIT] flow end
634 11:44:55.524114 ============ LP4 DIFF to SE enter ============
635 11:44:55.527314 ============ LP4 DIFF to SE exit ============
636 11:44:55.530867 [ANA_INIT] <<<<<<<<<<<<<
637 11:44:55.533649 [Flow] Enable top DCM control >>>>>
638 11:44:55.537117 [Flow] Enable top DCM control <<<<<
639 11:44:55.540767 Enable DLL master slave shuffle
640 11:44:55.544289 ==============================================================
641 11:44:55.547285 Gating Mode config
642 11:44:55.553940 ==============================================================
643 11:44:55.554025 Config description:
644 11:44:55.564488 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 11:44:55.570822 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 11:44:55.574343 SELPH_MODE 0: By rank 1: By Phase
647 11:44:55.580780 ==============================================================
648 11:44:55.584132 GAT_TRACK_EN = 1
649 11:44:55.587468 RX_GATING_MODE = 2
650 11:44:55.591070 RX_GATING_TRACK_MODE = 2
651 11:44:55.594335 SELPH_MODE = 1
652 11:44:55.597667 PICG_EARLY_EN = 1
653 11:44:55.597752 VALID_LAT_VALUE = 1
654 11:44:55.604142 ==============================================================
655 11:44:55.608144 Enter into Gating configuration >>>>
656 11:44:55.611024 Exit from Gating configuration <<<<
657 11:44:55.614320 Enter into DVFS_PRE_config >>>>>
658 11:44:55.624263 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 11:44:55.627517 Exit from DVFS_PRE_config <<<<<
660 11:44:55.631715 Enter into PICG configuration >>>>
661 11:44:55.634733 Exit from PICG configuration <<<<
662 11:44:55.637920 [RX_INPUT] configuration >>>>>
663 11:44:55.641090 [RX_INPUT] configuration <<<<<
664 11:44:55.644812 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 11:44:55.651387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 11:44:55.658495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 11:44:55.665312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 11:44:55.668289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 11:44:55.675399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 11:44:55.678785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 11:44:55.681857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 11:44:55.688491 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 11:44:55.692290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 11:44:55.695165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 11:44:55.701700 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 11:44:55.705572 ===================================
677 11:44:55.705666 LPDDR4 DRAM CONFIGURATION
678 11:44:55.708575 ===================================
679 11:44:55.711815 EX_ROW_EN[0] = 0x0
680 11:44:55.711900 EX_ROW_EN[1] = 0x0
681 11:44:55.715397 LP4Y_EN = 0x0
682 11:44:55.718722 WORK_FSP = 0x0
683 11:44:55.718807 WL = 0x2
684 11:44:55.722126 RL = 0x2
685 11:44:55.722209 BL = 0x2
686 11:44:55.725615 RPST = 0x0
687 11:44:55.725697 RD_PRE = 0x0
688 11:44:55.728878 WR_PRE = 0x1
689 11:44:55.728960 WR_PST = 0x0
690 11:44:55.732300 DBI_WR = 0x0
691 11:44:55.732382 DBI_RD = 0x0
692 11:44:55.735491 OTF = 0x1
693 11:44:55.738978 ===================================
694 11:44:55.742039 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 11:44:55.745422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 11:44:55.749271 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:44:55.752699 ===================================
698 11:44:55.756030 LPDDR4 DRAM CONFIGURATION
699 11:44:55.759240 ===================================
700 11:44:55.762639 EX_ROW_EN[0] = 0x10
701 11:44:55.762722 EX_ROW_EN[1] = 0x0
702 11:44:55.765830 LP4Y_EN = 0x0
703 11:44:55.765913 WORK_FSP = 0x0
704 11:44:55.769036 WL = 0x2
705 11:44:55.769120 RL = 0x2
706 11:44:55.772740 BL = 0x2
707 11:44:55.772825 RPST = 0x0
708 11:44:55.775679 RD_PRE = 0x0
709 11:44:55.775761 WR_PRE = 0x1
710 11:44:55.779388 WR_PST = 0x0
711 11:44:55.779471 DBI_WR = 0x0
712 11:44:55.782737 DBI_RD = 0x0
713 11:44:55.782819 OTF = 0x1
714 11:44:55.785861 ===================================
715 11:44:55.792580 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 11:44:55.797553 nWR fixed to 40
717 11:44:55.800696 [ModeRegInit_LP4] CH0 RK0
718 11:44:55.800780 [ModeRegInit_LP4] CH0 RK1
719 11:44:55.803973 [ModeRegInit_LP4] CH1 RK0
720 11:44:55.807135 [ModeRegInit_LP4] CH1 RK1
721 11:44:55.807221 match AC timing 13
722 11:44:55.813762 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 11:44:55.817290 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 11:44:55.820679 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 11:44:55.827353 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 11:44:55.830850 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 11:44:55.830949 [EMI DOE] emi_dcm 0
728 11:44:55.837416 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 11:44:55.837503 ==
730 11:44:55.840565 Dram Type= 6, Freq= 0, CH_0, rank 0
731 11:44:55.844036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 11:44:55.844120 ==
733 11:44:55.850801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 11:44:55.854293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 11:44:55.864819 [CA 0] Center 37 (7~68) winsize 62
736 11:44:55.868260 [CA 1] Center 37 (6~68) winsize 63
737 11:44:55.871387 [CA 2] Center 35 (5~66) winsize 62
738 11:44:55.874657 [CA 3] Center 34 (4~65) winsize 62
739 11:44:55.878095 [CA 4] Center 34 (3~65) winsize 63
740 11:44:55.881647 [CA 5] Center 33 (3~64) winsize 62
741 11:44:55.881731
742 11:44:55.884867 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 11:44:55.884950
744 11:44:55.888349 [CATrainingPosCal] consider 1 rank data
745 11:44:55.891735 u2DelayCellTimex100 = 270/100 ps
746 11:44:55.895255 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 11:44:55.897979 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 11:44:55.901645 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
749 11:44:55.908091 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 11:44:55.911439 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
751 11:44:55.915172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 11:44:55.915257
753 11:44:55.918392 CA PerBit enable=1, Macro0, CA PI delay=33
754 11:44:55.918476
755 11:44:55.921759 [CBTSetCACLKResult] CA Dly = 33
756 11:44:55.921842 CS Dly: 5 (0~36)
757 11:44:55.921908 ==
758 11:44:55.925087 Dram Type= 6, Freq= 0, CH_0, rank 1
759 11:44:55.932017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 11:44:55.932104 ==
761 11:44:55.934750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 11:44:55.941489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 11:44:55.951006 [CA 0] Center 37 (6~68) winsize 63
764 11:44:55.954057 [CA 1] Center 37 (7~68) winsize 62
765 11:44:55.957270 [CA 2] Center 35 (4~66) winsize 63
766 11:44:55.960968 [CA 3] Center 34 (4~65) winsize 62
767 11:44:55.964535 [CA 4] Center 34 (3~65) winsize 63
768 11:44:55.967535 [CA 5] Center 33 (3~64) winsize 62
769 11:44:55.967619
770 11:44:55.970979 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 11:44:55.971064
772 11:44:55.974022 [CATrainingPosCal] consider 2 rank data
773 11:44:55.977455 u2DelayCellTimex100 = 270/100 ps
774 11:44:55.981506 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 11:44:55.984113 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 11:44:55.990896 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
777 11:44:55.994165 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 11:44:55.997527 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
779 11:44:56.001450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 11:44:56.001534
781 11:44:56.004791 CA PerBit enable=1, Macro0, CA PI delay=33
782 11:44:56.004878
783 11:44:56.008091 [CBTSetCACLKResult] CA Dly = 33
784 11:44:56.008185 CS Dly: 6 (0~38)
785 11:44:56.008251
786 11:44:56.011196 ----->DramcWriteLeveling(PI) begin...
787 11:44:56.011281 ==
788 11:44:56.014772 Dram Type= 6, Freq= 0, CH_0, rank 0
789 11:44:56.018497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 11:44:56.022035 ==
791 11:44:56.022120 Write leveling (Byte 0): 31 => 31
792 11:44:56.025928 Write leveling (Byte 1): 29 => 29
793 11:44:56.029446 DramcWriteLeveling(PI) end<-----
794 11:44:56.029530
795 11:44:56.029595 ==
796 11:44:56.033583 Dram Type= 6, Freq= 0, CH_0, rank 0
797 11:44:56.036674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 11:44:56.036759 ==
799 11:44:56.040002 [Gating] SW mode calibration
800 11:44:56.047546 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 11:44:56.050754 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 11:44:56.057430 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 11:44:56.061223 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 11:44:56.063870 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
805 11:44:56.070656 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:44:56.074045 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:44:56.077818 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:44:56.084235 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:44:56.087371 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:44:56.090851 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:44:56.098015 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:44:56.100943 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:44:56.104415 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:44:56.111464 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:44:56.114434 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:44:56.118026 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:44:56.121046 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:44:56.128345 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:44:56.131025 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:44:56.134541 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
821 11:44:56.141198 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 11:44:56.144402 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:44:56.148202 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:44:56.155154 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:44:56.158240 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:44:56.161341 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:44:56.168039 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:44:56.171512 0 9 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
829 11:44:56.175064 0 9 12 | B1->B0 | 2828 2f2f | 1 1 | (0 0) (1 1)
830 11:44:56.178309 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 11:44:56.185084 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 11:44:56.188399 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 11:44:56.191640 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 11:44:56.198376 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 11:44:56.201615 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
836 11:44:56.205209 0 10 8 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
837 11:44:56.211778 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
838 11:44:56.215147 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:44:56.218479 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:44:56.225271 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 11:44:56.228512 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:44:56.232146 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:44:56.235048 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:44:56.242207 0 11 8 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
845 11:44:56.245458 0 11 12 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
846 11:44:56.248833 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 11:44:56.255842 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 11:44:56.259061 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 11:44:56.263422 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:44:56.269062 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 11:44:56.272459 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 11:44:56.275850 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 11:44:56.279459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
854 11:44:56.285720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:44:56.289219 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:44:56.292422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:44:56.299435 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 11:44:56.302731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 11:44:56.306126 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 11:44:56.312864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 11:44:56.315966 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 11:44:56.319699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 11:44:56.325954 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 11:44:56.329147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 11:44:56.333012 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 11:44:56.339665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 11:44:56.342846 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 11:44:56.346159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 11:44:56.350036 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:44:56.352862 Total UI for P1: 0, mck2ui 16
871 11:44:56.356039 best dqsien dly found for B0: ( 0, 14, 8)
872 11:44:56.359704 Total UI for P1: 0, mck2ui 16
873 11:44:56.363108 best dqsien dly found for B1: ( 0, 14, 8)
874 11:44:56.366149 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
875 11:44:56.369872 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 11:44:56.369954
877 11:44:56.376257 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
878 11:44:56.379898 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 11:44:56.379981 [Gating] SW calibration Done
880 11:44:56.383253 ==
881 11:44:56.383336 Dram Type= 6, Freq= 0, CH_0, rank 0
882 11:44:56.389828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 11:44:56.389911 ==
884 11:44:56.389976 RX Vref Scan: 0
885 11:44:56.390036
886 11:44:56.394017 RX Vref 0 -> 0, step: 1
887 11:44:56.394101
888 11:44:56.396630 RX Delay -130 -> 252, step: 16
889 11:44:56.399941 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
890 11:44:56.403481 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
891 11:44:56.406854 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
892 11:44:56.412976 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
893 11:44:56.416744 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
894 11:44:56.420233 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
895 11:44:56.423584 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
896 11:44:56.427121 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
897 11:44:56.430358 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
898 11:44:56.437008 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
899 11:44:56.440314 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
900 11:44:56.443309 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
901 11:44:56.446874 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
902 11:44:56.453532 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
903 11:44:56.457243 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
904 11:44:56.460323 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
905 11:44:56.460419 ==
906 11:44:56.463601 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:44:56.467457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:44:56.467625 ==
909 11:44:56.470649 DQS Delay:
910 11:44:56.470869 DQS0 = 0, DQS1 = 0
911 11:44:56.471051 DQM Delay:
912 11:44:56.474034 DQM0 = 84, DQM1 = 80
913 11:44:56.474167 DQ Delay:
914 11:44:56.477621 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 11:44:56.480790 DQ4 =85, DQ5 =77, DQ6 =85, DQ7 =85
916 11:44:56.484080 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
917 11:44:56.487222 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 11:44:56.487441
919 11:44:56.487598
920 11:44:56.487730 ==
921 11:44:56.490901 Dram Type= 6, Freq= 0, CH_0, rank 0
922 11:44:56.494036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 11:44:56.497591 ==
924 11:44:56.497793
925 11:44:56.497950
926 11:44:56.498096 TX Vref Scan disable
927 11:44:56.500991 == TX Byte 0 ==
928 11:44:56.504696 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 11:44:56.507678 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 11:44:56.511286 == TX Byte 1 ==
931 11:44:56.514604 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
932 11:44:56.518015 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
933 11:44:56.518375 ==
934 11:44:56.521307 Dram Type= 6, Freq= 0, CH_0, rank 0
935 11:44:56.528081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 11:44:56.528526 ==
937 11:44:56.540074 TX Vref=22, minBit 5, minWin=27, winSum=440
938 11:44:56.543624 TX Vref=24, minBit 5, minWin=27, winSum=446
939 11:44:56.546432 TX Vref=26, minBit 5, minWin=27, winSum=448
940 11:44:56.550115 TX Vref=28, minBit 12, minWin=27, winSum=453
941 11:44:56.553359 TX Vref=30, minBit 3, minWin=28, winSum=455
942 11:44:56.559986 TX Vref=32, minBit 12, minWin=27, winSum=454
943 11:44:56.563247 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 30
944 11:44:56.563463
945 11:44:56.566387 Final TX Range 1 Vref 30
946 11:44:56.566557
947 11:44:56.566690 ==
948 11:44:56.569780 Dram Type= 6, Freq= 0, CH_0, rank 0
949 11:44:56.573511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 11:44:56.573608 ==
951 11:44:56.573676
952 11:44:56.576461
953 11:44:56.576571 TX Vref Scan disable
954 11:44:56.579950 == TX Byte 0 ==
955 11:44:56.583157 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
956 11:44:56.586617 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
957 11:44:56.589857 == TX Byte 1 ==
958 11:44:56.593339 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 11:44:56.596638 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 11:44:56.600005
961 11:44:56.600103 [DATLAT]
962 11:44:56.600171 Freq=800, CH0 RK0
963 11:44:56.600232
964 11:44:56.603367 DATLAT Default: 0xa
965 11:44:56.603455 0, 0xFFFF, sum = 0
966 11:44:56.606766 1, 0xFFFF, sum = 0
967 11:44:56.606901 2, 0xFFFF, sum = 0
968 11:44:56.610776 3, 0xFFFF, sum = 0
969 11:44:56.610903 4, 0xFFFF, sum = 0
970 11:44:56.613767 5, 0xFFFF, sum = 0
971 11:44:56.613851 6, 0xFFFF, sum = 0
972 11:44:56.617033 7, 0xFFFF, sum = 0
973 11:44:56.617118 8, 0xFFFF, sum = 0
974 11:44:56.620383 9, 0x0, sum = 1
975 11:44:56.620468 10, 0x0, sum = 2
976 11:44:56.623896 11, 0x0, sum = 3
977 11:44:56.623981 12, 0x0, sum = 4
978 11:44:56.627352 best_step = 10
979 11:44:56.627435
980 11:44:56.627500 ==
981 11:44:56.630468 Dram Type= 6, Freq= 0, CH_0, rank 0
982 11:44:56.634121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 11:44:56.634205 ==
984 11:44:56.634270 RX Vref Scan: 1
985 11:44:56.637036
986 11:44:56.637119 Set Vref Range= 32 -> 127
987 11:44:56.637184
988 11:44:56.640635 RX Vref 32 -> 127, step: 1
989 11:44:56.640718
990 11:44:56.643970 RX Delay -95 -> 252, step: 8
991 11:44:56.644052
992 11:44:56.647211 Set Vref, RX VrefLevel [Byte0]: 32
993 11:44:56.651081 [Byte1]: 32
994 11:44:56.651182
995 11:44:56.654063 Set Vref, RX VrefLevel [Byte0]: 33
996 11:44:56.657819 [Byte1]: 33
997 11:44:56.657930
998 11:44:56.661709 Set Vref, RX VrefLevel [Byte0]: 34
999 11:44:56.664987 [Byte1]: 34
1000 11:44:56.665070
1001 11:44:56.668255 Set Vref, RX VrefLevel [Byte0]: 35
1002 11:44:56.671607 [Byte1]: 35
1003 11:44:56.676038
1004 11:44:56.676125 Set Vref, RX VrefLevel [Byte0]: 36
1005 11:44:56.678747 [Byte1]: 36
1006 11:44:56.683078
1007 11:44:56.683161 Set Vref, RX VrefLevel [Byte0]: 37
1008 11:44:56.686752 [Byte1]: 37
1009 11:44:56.690809
1010 11:44:56.690952 Set Vref, RX VrefLevel [Byte0]: 38
1011 11:44:56.694408 [Byte1]: 38
1012 11:44:56.698735
1013 11:44:56.698820 Set Vref, RX VrefLevel [Byte0]: 39
1014 11:44:56.701811 [Byte1]: 39
1015 11:44:56.705891
1016 11:44:56.705976 Set Vref, RX VrefLevel [Byte0]: 40
1017 11:44:56.709436 [Byte1]: 40
1018 11:44:56.713371
1019 11:44:56.713455 Set Vref, RX VrefLevel [Byte0]: 41
1020 11:44:56.716962 [Byte1]: 41
1021 11:44:56.721089
1022 11:44:56.721174 Set Vref, RX VrefLevel [Byte0]: 42
1023 11:44:56.724768 [Byte1]: 42
1024 11:44:56.729023
1025 11:44:56.729111 Set Vref, RX VrefLevel [Byte0]: 43
1026 11:44:56.732225 [Byte1]: 43
1027 11:44:56.735982
1028 11:44:56.736065 Set Vref, RX VrefLevel [Byte0]: 44
1029 11:44:56.739941 [Byte1]: 44
1030 11:44:56.743904
1031 11:44:56.743985 Set Vref, RX VrefLevel [Byte0]: 45
1032 11:44:56.747465 [Byte1]: 45
1033 11:44:56.751549
1034 11:44:56.751735 Set Vref, RX VrefLevel [Byte0]: 46
1035 11:44:56.754450 [Byte1]: 46
1036 11:44:56.759070
1037 11:44:56.759283 Set Vref, RX VrefLevel [Byte0]: 47
1038 11:44:56.762207 [Byte1]: 47
1039 11:44:56.766390
1040 11:44:56.766603 Set Vref, RX VrefLevel [Byte0]: 48
1041 11:44:56.770016 [Byte1]: 48
1042 11:44:56.774102
1043 11:44:56.774299 Set Vref, RX VrefLevel [Byte0]: 49
1044 11:44:56.777591 [Byte1]: 49
1045 11:44:56.782262
1046 11:44:56.782437 Set Vref, RX VrefLevel [Byte0]: 50
1047 11:44:56.784910 [Byte1]: 50
1048 11:44:56.789597
1049 11:44:56.789778 Set Vref, RX VrefLevel [Byte0]: 51
1050 11:44:56.792728 [Byte1]: 51
1051 11:44:56.797133
1052 11:44:56.797313 Set Vref, RX VrefLevel [Byte0]: 52
1053 11:44:56.800087 [Byte1]: 52
1054 11:44:56.804136
1055 11:44:56.804285 Set Vref, RX VrefLevel [Byte0]: 53
1056 11:44:56.807721 [Byte1]: 53
1057 11:44:56.812088
1058 11:44:56.812225 Set Vref, RX VrefLevel [Byte0]: 54
1059 11:44:56.815553 [Byte1]: 54
1060 11:44:56.819644
1061 11:44:56.819863 Set Vref, RX VrefLevel [Byte0]: 55
1062 11:44:56.823196 [Byte1]: 55
1063 11:44:56.828072
1064 11:44:56.828240 Set Vref, RX VrefLevel [Byte0]: 56
1065 11:44:56.830257 [Byte1]: 56
1066 11:44:56.835257
1067 11:44:56.835339 Set Vref, RX VrefLevel [Byte0]: 57
1068 11:44:56.838220 [Byte1]: 57
1069 11:44:56.842337
1070 11:44:56.842443 Set Vref, RX VrefLevel [Byte0]: 58
1071 11:44:56.845852 [Byte1]: 58
1072 11:44:56.850016
1073 11:44:56.850096 Set Vref, RX VrefLevel [Byte0]: 59
1074 11:44:56.853083 [Byte1]: 59
1075 11:44:56.857772
1076 11:44:56.857855 Set Vref, RX VrefLevel [Byte0]: 60
1077 11:44:56.860843 [Byte1]: 60
1078 11:44:56.865322
1079 11:44:56.865455 Set Vref, RX VrefLevel [Byte0]: 61
1080 11:44:56.868750 [Byte1]: 61
1081 11:44:56.872880
1082 11:44:56.872975 Set Vref, RX VrefLevel [Byte0]: 62
1083 11:44:56.876850 [Byte1]: 62
1084 11:44:56.880614
1085 11:44:56.880709 Set Vref, RX VrefLevel [Byte0]: 63
1086 11:44:56.884073 [Byte1]: 63
1087 11:44:56.887889
1088 11:44:56.887986 Set Vref, RX VrefLevel [Byte0]: 64
1089 11:44:56.891286 [Byte1]: 64
1090 11:44:56.895743
1091 11:44:56.895839 Set Vref, RX VrefLevel [Byte0]: 65
1092 11:44:56.899222 [Byte1]: 65
1093 11:44:56.903610
1094 11:44:56.903706 Set Vref, RX VrefLevel [Byte0]: 66
1095 11:44:56.906793 [Byte1]: 66
1096 11:44:56.910770
1097 11:44:56.910851 Set Vref, RX VrefLevel [Byte0]: 67
1098 11:44:56.914423 [Byte1]: 67
1099 11:44:56.918352
1100 11:44:56.918450 Set Vref, RX VrefLevel [Byte0]: 68
1101 11:44:56.921651 [Byte1]: 68
1102 11:44:56.926168
1103 11:44:56.926254 Set Vref, RX VrefLevel [Byte0]: 69
1104 11:44:56.929269 [Byte1]: 69
1105 11:44:56.933673
1106 11:44:56.933790 Set Vref, RX VrefLevel [Byte0]: 70
1107 11:44:56.936684 [Byte1]: 70
1108 11:44:56.940987
1109 11:44:56.941180 Set Vref, RX VrefLevel [Byte0]: 71
1110 11:44:56.944450 [Byte1]: 71
1111 11:44:56.948519
1112 11:44:56.948642 Set Vref, RX VrefLevel [Byte0]: 72
1113 11:44:56.951989 [Byte1]: 72
1114 11:44:56.956835
1115 11:44:56.956930 Set Vref, RX VrefLevel [Byte0]: 73
1116 11:44:56.960093 [Byte1]: 73
1117 11:44:56.963860
1118 11:44:56.963965 Set Vref, RX VrefLevel [Byte0]: 74
1119 11:44:56.967526 [Byte1]: 74
1120 11:44:56.971705
1121 11:44:56.971789 Set Vref, RX VrefLevel [Byte0]: 75
1122 11:44:56.975146 [Byte1]: 75
1123 11:44:56.979502
1124 11:44:56.979583 Set Vref, RX VrefLevel [Byte0]: 76
1125 11:44:56.982733 [Byte1]: 76
1126 11:44:56.986781
1127 11:44:56.986867 Final RX Vref Byte 0 = 62 to rank0
1128 11:44:56.990199 Final RX Vref Byte 1 = 59 to rank0
1129 11:44:56.994017 Final RX Vref Byte 0 = 62 to rank1
1130 11:44:56.996757 Final RX Vref Byte 1 = 59 to rank1==
1131 11:44:57.000269 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 11:44:57.007060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 11:44:57.007150 ==
1134 11:44:57.007215 DQS Delay:
1135 11:44:57.007273 DQS0 = 0, DQS1 = 0
1136 11:44:57.010273 DQM Delay:
1137 11:44:57.010353 DQM0 = 88, DQM1 = 79
1138 11:44:57.013696 DQ Delay:
1139 11:44:57.016920 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1140 11:44:57.017000 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1141 11:44:57.020326 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1142 11:44:57.023546 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1143 11:44:57.026857
1144 11:44:57.026977
1145 11:44:57.033631 [DQSOSCAuto] RK0, (LSB)MR18= 0x250b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 400 ps
1146 11:44:57.037307 CH0 RK0: MR19=606, MR18=250B
1147 11:44:57.043655 CH0_RK0: MR19=0x606, MR18=0x250B, DQSOSC=400, MR23=63, INC=92, DEC=61
1148 11:44:57.043745
1149 11:44:57.047052 ----->DramcWriteLeveling(PI) begin...
1150 11:44:57.047136 ==
1151 11:44:57.050221 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 11:44:57.053675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 11:44:57.053765 ==
1154 11:44:57.057182 Write leveling (Byte 0): 30 => 30
1155 11:44:57.060619 Write leveling (Byte 1): 27 => 27
1156 11:44:57.063818 DramcWriteLeveling(PI) end<-----
1157 11:44:57.063899
1158 11:44:57.063964 ==
1159 11:44:57.067055 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 11:44:57.070468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 11:44:57.070551 ==
1162 11:44:57.073639 [Gating] SW mode calibration
1163 11:44:57.080392 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 11:44:57.087195 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 11:44:57.090635 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 11:44:57.094036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1167 11:44:57.097346 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 11:44:57.141582 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:44:57.141918 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:44:57.142177 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:44:57.142253 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:44:57.142315 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:44:57.142556 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:44:57.142804 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:44:57.143108 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:44:57.143775 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:44:57.143840 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:44:57.185344 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:44:57.185643 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:44:57.185716 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:44:57.185789 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:44:57.185851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1183 11:44:57.186356 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:44:57.186622 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:44:57.186691 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:44:57.186762 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:44:57.186822 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:44:57.196839 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:44:57.197265 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:44:57.200076 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:44:57.203437 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1192 11:44:57.210350 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1193 11:44:57.213613 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 11:44:57.217152 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 11:44:57.220551 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 11:44:57.227066 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 11:44:57.230443 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 11:44:57.233642 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1199 11:44:57.240929 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
1200 11:44:57.244083 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1201 11:44:57.246967 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:44:57.254435 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:44:57.257807 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:44:57.260521 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:44:57.267698 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:44:57.271636 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1207 11:44:57.275075 0 11 8 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (0 0)
1208 11:44:57.278820 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1209 11:44:57.282467 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 11:44:57.289012 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 11:44:57.292934 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 11:44:57.296497 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 11:44:57.300020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 11:44:57.306357 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1215 11:44:57.309843 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1216 11:44:57.313531 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1217 11:44:57.319961 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:44:57.323290 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:44:57.326791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:44:57.330061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:44:57.337135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:44:57.340042 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:44:57.343463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:44:57.350186 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 11:44:57.353545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 11:44:57.356850 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 11:44:57.364127 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 11:44:57.366989 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 11:44:57.370801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 11:44:57.376847 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1231 11:44:57.380584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 11:44:57.383678 Total UI for P1: 0, mck2ui 16
1233 11:44:57.387119 best dqsien dly found for B0: ( 0, 14, 4)
1234 11:44:57.390553 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 11:44:57.393438 Total UI for P1: 0, mck2ui 16
1236 11:44:57.396875 best dqsien dly found for B1: ( 0, 14, 8)
1237 11:44:57.400710 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1238 11:44:57.403927 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1239 11:44:57.404007
1240 11:44:57.407522 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1241 11:44:57.410536 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1242 11:44:57.413962 [Gating] SW calibration Done
1243 11:44:57.414041 ==
1244 11:44:57.417215 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 11:44:57.420625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 11:44:57.424063 ==
1247 11:44:57.424142 RX Vref Scan: 0
1248 11:44:57.424204
1249 11:44:57.427482 RX Vref 0 -> 0, step: 1
1250 11:44:57.427562
1251 11:44:57.431169 RX Delay -130 -> 252, step: 16
1252 11:44:57.434262 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1253 11:44:57.437257 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1254 11:44:57.441204 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1255 11:44:57.444347 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1256 11:44:57.451178 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1257 11:44:57.454633 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1258 11:44:57.457799 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1259 11:44:57.460983 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1260 11:44:57.464143 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1261 11:44:57.471015 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1262 11:44:57.474116 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1263 11:44:57.477648 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1264 11:44:57.480907 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1265 11:44:57.484056 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1266 11:44:57.490769 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1267 11:44:57.494542 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1268 11:44:57.494624 ==
1269 11:44:57.497753 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 11:44:57.501246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 11:44:57.501326 ==
1272 11:44:57.501389 DQS Delay:
1273 11:44:57.504582 DQS0 = 0, DQS1 = 0
1274 11:44:57.504662 DQM Delay:
1275 11:44:57.507932 DQM0 = 87, DQM1 = 79
1276 11:44:57.508013 DQ Delay:
1277 11:44:57.511727 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1278 11:44:57.515004 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1279 11:44:57.517856 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1280 11:44:57.521455 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1281 11:44:57.521534
1282 11:44:57.521597
1283 11:44:57.521655 ==
1284 11:44:57.524598 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 11:44:57.528064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 11:44:57.528145 ==
1287 11:44:57.531561
1288 11:44:57.531640
1289 11:44:57.531702 TX Vref Scan disable
1290 11:44:57.534930 == TX Byte 0 ==
1291 11:44:57.537914 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 11:44:57.541531 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 11:44:57.544606 == TX Byte 1 ==
1294 11:44:57.547997 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1295 11:44:57.551592 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1296 11:44:57.551671 ==
1297 11:44:57.554754 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 11:44:57.561340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 11:44:57.561419 ==
1300 11:44:57.573563 TX Vref=22, minBit 1, minWin=27, winSum=439
1301 11:44:57.576750 TX Vref=24, minBit 2, minWin=27, winSum=443
1302 11:44:57.580163 TX Vref=26, minBit 8, minWin=27, winSum=448
1303 11:44:57.583806 TX Vref=28, minBit 2, minWin=27, winSum=451
1304 11:44:57.587179 TX Vref=30, minBit 9, minWin=27, winSum=451
1305 11:44:57.590671 TX Vref=32, minBit 8, minWin=27, winSum=450
1306 11:44:57.597063 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1307 11:44:57.597144
1308 11:44:57.600382 Final TX Range 1 Vref 28
1309 11:44:57.600463
1310 11:44:57.600524 ==
1311 11:44:57.604382 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 11:44:57.607394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 11:44:57.607476 ==
1314 11:44:57.607538
1315 11:44:57.607595
1316 11:44:57.610436 TX Vref Scan disable
1317 11:44:57.613940 == TX Byte 0 ==
1318 11:44:57.617032 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 11:44:57.620820 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 11:44:57.623769 == TX Byte 1 ==
1321 11:44:57.627151 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1322 11:44:57.630440 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1323 11:44:57.630518
1324 11:44:57.634222 [DATLAT]
1325 11:44:57.634301 Freq=800, CH0 RK1
1326 11:44:57.634364
1327 11:44:57.637351 DATLAT Default: 0xa
1328 11:44:57.637430 0, 0xFFFF, sum = 0
1329 11:44:57.640478 1, 0xFFFF, sum = 0
1330 11:44:57.640559 2, 0xFFFF, sum = 0
1331 11:44:57.643794 3, 0xFFFF, sum = 0
1332 11:44:57.643875 4, 0xFFFF, sum = 0
1333 11:44:57.647057 5, 0xFFFF, sum = 0
1334 11:44:57.647138 6, 0xFFFF, sum = 0
1335 11:44:57.650539 7, 0xFFFF, sum = 0
1336 11:44:57.650619 8, 0xFFFF, sum = 0
1337 11:44:57.654318 9, 0x0, sum = 1
1338 11:44:57.654398 10, 0x0, sum = 2
1339 11:44:57.657317 11, 0x0, sum = 3
1340 11:44:57.657398 12, 0x0, sum = 4
1341 11:44:57.661079 best_step = 10
1342 11:44:57.661158
1343 11:44:57.661219 ==
1344 11:44:57.664306 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:44:57.667533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:44:57.667613 ==
1347 11:44:57.667674 RX Vref Scan: 0
1348 11:44:57.670623
1349 11:44:57.670700 RX Vref 0 -> 0, step: 1
1350 11:44:57.670762
1351 11:44:57.674159 RX Delay -95 -> 252, step: 8
1352 11:44:57.677704 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1353 11:44:57.684287 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1354 11:44:57.687546 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1355 11:44:57.691077 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1356 11:44:57.694344 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1357 11:44:57.697767 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1358 11:44:57.704670 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1359 11:44:57.707568 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1360 11:44:57.710733 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1361 11:44:57.714091 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1362 11:44:57.717563 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1363 11:44:57.724514 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1364 11:44:57.727869 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1365 11:44:57.731183 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1366 11:44:57.734402 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1367 11:44:57.737900 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1368 11:44:57.737978 ==
1369 11:44:57.741524 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 11:44:57.747895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 11:44:57.747974 ==
1372 11:44:57.748035 DQS Delay:
1373 11:44:57.751264 DQS0 = 0, DQS1 = 0
1374 11:44:57.751343 DQM Delay:
1375 11:44:57.751404 DQM0 = 88, DQM1 = 78
1376 11:44:57.754734 DQ Delay:
1377 11:44:57.758068 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1378 11:44:57.761378 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1379 11:44:57.764847 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1380 11:44:57.768087 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1381 11:44:57.768166
1382 11:44:57.768228
1383 11:44:57.774440 [DQSOSCAuto] RK1, (LSB)MR18= 0x311a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1384 11:44:57.777955 CH0 RK1: MR19=606, MR18=311A
1385 11:44:57.784526 CH0_RK1: MR19=0x606, MR18=0x311A, DQSOSC=397, MR23=63, INC=93, DEC=62
1386 11:44:57.787767 [RxdqsGatingPostProcess] freq 800
1387 11:44:57.791278 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 11:44:57.794785 Pre-setting of DQS Precalculation
1389 11:44:57.801069 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 11:44:57.801149 ==
1391 11:44:57.804775 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 11:44:57.808033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 11:44:57.808113 ==
1394 11:44:57.814907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 11:44:57.818146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 11:44:57.828648 [CA 0] Center 36 (6~67) winsize 62
1397 11:44:57.831817 [CA 1] Center 36 (5~67) winsize 63
1398 11:44:57.835663 [CA 2] Center 34 (4~65) winsize 62
1399 11:44:57.838681 [CA 3] Center 33 (3~64) winsize 62
1400 11:44:57.841784 [CA 4] Center 33 (3~64) winsize 62
1401 11:44:57.845252 [CA 5] Center 33 (3~64) winsize 62
1402 11:44:57.845337
1403 11:44:57.848751 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 11:44:57.848829
1405 11:44:57.852546 [CATrainingPosCal] consider 1 rank data
1406 11:44:57.855442 u2DelayCellTimex100 = 270/100 ps
1407 11:44:57.859016 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1408 11:44:57.862374 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1409 11:44:57.865895 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 11:44:57.868726 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 11:44:57.875844 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1412 11:44:57.878841 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 11:44:57.878959
1414 11:44:57.882716 CA PerBit enable=1, Macro0, CA PI delay=33
1415 11:44:57.882796
1416 11:44:57.885975 [CBTSetCACLKResult] CA Dly = 33
1417 11:44:57.886054 CS Dly: 3 (0~34)
1418 11:44:57.886116 ==
1419 11:44:57.888957 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 11:44:57.892521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 11:44:57.895877 ==
1422 11:44:57.899398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 11:44:57.905948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 11:44:57.914816 [CA 0] Center 36 (6~67) winsize 62
1425 11:44:57.918006 [CA 1] Center 36 (5~67) winsize 63
1426 11:44:57.921246 [CA 2] Center 33 (3~64) winsize 62
1427 11:44:57.924845 [CA 3] Center 33 (3~64) winsize 62
1428 11:44:57.928262 [CA 4] Center 34 (3~65) winsize 63
1429 11:44:57.931839 [CA 5] Center 33 (3~63) winsize 61
1430 11:44:57.931918
1431 11:44:57.935151 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1432 11:44:57.935230
1433 11:44:57.939169 [CATrainingPosCal] consider 2 rank data
1434 11:44:57.942579 u2DelayCellTimex100 = 270/100 ps
1435 11:44:57.946692 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1436 11:44:57.950688 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1437 11:44:57.954143 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1438 11:44:57.957491 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1439 11:44:57.961879 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1440 11:44:57.965083 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1441 11:44:57.965163
1442 11:44:57.969295 CA PerBit enable=1, Macro0, CA PI delay=33
1443 11:44:57.969377
1444 11:44:57.972301 [CBTSetCACLKResult] CA Dly = 33
1445 11:44:57.972380 CS Dly: 5 (0~38)
1446 11:44:57.972442
1447 11:44:57.975959 ----->DramcWriteLeveling(PI) begin...
1448 11:44:57.976040 ==
1449 11:44:57.979197 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 11:44:57.982502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 11:44:57.982581 ==
1452 11:44:57.985425 Write leveling (Byte 0): 27 => 27
1453 11:44:57.988797 Write leveling (Byte 1): 30 => 30
1454 11:44:57.992466 DramcWriteLeveling(PI) end<-----
1455 11:44:57.992545
1456 11:44:57.992607 ==
1457 11:44:57.995850 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 11:44:57.999593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 11:44:58.002346 ==
1460 11:44:58.002425 [Gating] SW mode calibration
1461 11:44:58.012673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 11:44:58.016483 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 11:44:58.019411 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1464 11:44:58.026085 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1465 11:44:58.029701 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1466 11:44:58.032722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:44:58.039833 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:44:58.042761 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:44:58.046673 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:44:58.049455 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:44:58.056328 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:44:58.059720 0 7 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1473 11:44:58.063217 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:44:58.069724 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:44:58.073184 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:44:58.076793 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1477 11:44:58.083111 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:44:58.086714 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:44:58.089707 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:44:58.096821 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:44:58.099904 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1482 11:44:58.103325 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:44:58.106413 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:44:58.113200 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:44:58.116729 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:44:58.120230 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:44:58.127132 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:44:58.130093 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:44:58.133814 0 9 8 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
1490 11:44:58.140424 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 11:44:58.143736 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 11:44:58.146992 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 11:44:58.153999 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1494 11:44:58.157047 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1495 11:44:58.160294 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 11:44:58.164178 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1497 11:44:58.170791 0 10 8 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (0 0)
1498 11:44:58.173806 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:44:58.177201 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:44:58.184038 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:44:58.187221 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:44:58.190644 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:44:58.197174 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:44:58.200854 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:44:58.204337 0 11 8 | B1->B0 | 3737 3333 | 0 0 | (0 0) (0 0)
1506 11:44:58.211062 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 11:44:58.214432 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 11:44:58.217324 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 11:44:58.221009 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 11:44:58.227348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 11:44:58.230706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 11:44:58.234414 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1513 11:44:58.240920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 11:44:58.244362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:44:58.247773 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:44:58.254645 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:44:58.258124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:44:58.261343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:44:58.267668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:44:58.271426 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:44:58.274612 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:44:58.277718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 11:44:58.284400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 11:44:58.289576 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 11:44:58.291452 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 11:44:58.298332 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 11:44:58.301688 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 11:44:58.304874 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 11:44:58.311577 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1530 11:44:58.314656 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 11:44:58.318495 Total UI for P1: 0, mck2ui 16
1532 11:44:58.321927 best dqsien dly found for B0: ( 0, 14, 8)
1533 11:44:58.325049 Total UI for P1: 0, mck2ui 16
1534 11:44:58.328561 best dqsien dly found for B1: ( 0, 14, 8)
1535 11:44:58.331763 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1536 11:44:58.335112 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1537 11:44:58.335192
1538 11:44:58.338444 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1539 11:44:58.341889 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1540 11:44:58.345181 [Gating] SW calibration Done
1541 11:44:58.345260 ==
1542 11:44:58.348803 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 11:44:58.351943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 11:44:58.352022 ==
1545 11:44:58.355260 RX Vref Scan: 0
1546 11:44:58.355340
1547 11:44:58.355441 RX Vref 0 -> 0, step: 1
1548 11:44:58.358674
1549 11:44:58.358782 RX Delay -130 -> 252, step: 16
1550 11:44:58.365350 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1551 11:44:58.368353 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1552 11:44:58.371763 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1553 11:44:58.375289 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1554 11:44:58.378672 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1555 11:44:58.382084 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1556 11:44:58.388921 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1557 11:44:58.392010 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1558 11:44:58.395511 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1559 11:44:58.398744 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1560 11:44:58.401863 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1561 11:44:58.408905 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1562 11:44:58.412155 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1563 11:44:58.415406 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1564 11:44:58.418685 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1565 11:44:58.422098 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1566 11:44:58.425579 ==
1567 11:44:58.425679 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 11:44:58.431880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 11:44:58.431957 ==
1570 11:44:58.432018 DQS Delay:
1571 11:44:58.435621 DQS0 = 0, DQS1 = 0
1572 11:44:58.435688 DQM Delay:
1573 11:44:58.438946 DQM0 = 79, DQM1 = 74
1574 11:44:58.439010 DQ Delay:
1575 11:44:58.442382 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1576 11:44:58.445539 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =69
1577 11:44:58.449399 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1578 11:44:58.452514 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
1579 11:44:58.452585
1580 11:44:58.452673
1581 11:44:58.452756 ==
1582 11:44:58.455472 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 11:44:58.459222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 11:44:58.459297 ==
1585 11:44:58.459362
1586 11:44:58.459422
1587 11:44:58.462609 TX Vref Scan disable
1588 11:44:58.462701 == TX Byte 0 ==
1589 11:44:58.469272 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 11:44:58.472698 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 11:44:58.472771 == TX Byte 1 ==
1592 11:44:58.479101 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1593 11:44:58.482399 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1594 11:44:58.482475 ==
1595 11:44:58.485865 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 11:44:58.489394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 11:44:58.489489 ==
1598 11:44:58.503358 TX Vref=22, minBit 8, minWin=26, winSum=434
1599 11:44:58.506765 TX Vref=24, minBit 11, minWin=26, winSum=436
1600 11:44:58.510188 TX Vref=26, minBit 11, minWin=26, winSum=442
1601 11:44:58.513714 TX Vref=28, minBit 10, minWin=27, winSum=448
1602 11:44:58.517017 TX Vref=30, minBit 13, minWin=27, winSum=454
1603 11:44:58.520967 TX Vref=32, minBit 0, minWin=28, winSum=451
1604 11:44:58.527960 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1605 11:44:58.528065
1606 11:44:58.530871 Final TX Range 1 Vref 32
1607 11:44:58.530975
1608 11:44:58.531040 ==
1609 11:44:58.534302 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 11:44:58.537753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 11:44:58.537822 ==
1612 11:44:58.537879
1613 11:44:58.537934
1614 11:44:58.541107 TX Vref Scan disable
1615 11:44:58.544507 == TX Byte 0 ==
1616 11:44:58.547986 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1617 11:44:58.551583 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1618 11:44:58.554675 == TX Byte 1 ==
1619 11:44:58.558005 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1620 11:44:58.561366 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1621 11:44:58.561460
1622 11:44:58.564438 [DATLAT]
1623 11:44:58.564533 Freq=800, CH1 RK0
1624 11:44:58.564618
1625 11:44:58.568147 DATLAT Default: 0xa
1626 11:44:58.568214 0, 0xFFFF, sum = 0
1627 11:44:58.571589 1, 0xFFFF, sum = 0
1628 11:44:58.571662 2, 0xFFFF, sum = 0
1629 11:44:58.575031 3, 0xFFFF, sum = 0
1630 11:44:58.575131 4, 0xFFFF, sum = 0
1631 11:44:58.577858 5, 0xFFFF, sum = 0
1632 11:44:58.577944 6, 0xFFFF, sum = 0
1633 11:44:58.581339 7, 0xFFFF, sum = 0
1634 11:44:58.581422 8, 0xFFFF, sum = 0
1635 11:44:58.584941 9, 0x0, sum = 1
1636 11:44:58.585022 10, 0x0, sum = 2
1637 11:44:58.588441 11, 0x0, sum = 3
1638 11:44:58.588522 12, 0x0, sum = 4
1639 11:44:58.588585 best_step = 10
1640 11:44:58.588643
1641 11:44:58.591407 ==
1642 11:44:58.594668 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 11:44:58.598228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 11:44:58.598327 ==
1645 11:44:58.598404 RX Vref Scan: 1
1646 11:44:58.598462
1647 11:44:58.601607 Set Vref Range= 32 -> 127
1648 11:44:58.601687
1649 11:44:58.605455 RX Vref 32 -> 127, step: 1
1650 11:44:58.605534
1651 11:44:58.608398 RX Delay -111 -> 252, step: 8
1652 11:44:58.608477
1653 11:44:58.611421 Set Vref, RX VrefLevel [Byte0]: 32
1654 11:44:58.614738 [Byte1]: 32
1655 11:44:58.614843
1656 11:44:58.618223 Set Vref, RX VrefLevel [Byte0]: 33
1657 11:44:58.621805 [Byte1]: 33
1658 11:44:58.621885
1659 11:44:58.625239 Set Vref, RX VrefLevel [Byte0]: 34
1660 11:44:58.628344 [Byte1]: 34
1661 11:44:58.631753
1662 11:44:58.631833 Set Vref, RX VrefLevel [Byte0]: 35
1663 11:44:58.634776 [Byte1]: 35
1664 11:44:58.639798
1665 11:44:58.639878 Set Vref, RX VrefLevel [Byte0]: 36
1666 11:44:58.643269 [Byte1]: 36
1667 11:44:58.646824
1668 11:44:58.646952 Set Vref, RX VrefLevel [Byte0]: 37
1669 11:44:58.650300 [Byte1]: 37
1670 11:44:58.655011
1671 11:44:58.655091 Set Vref, RX VrefLevel [Byte0]: 38
1672 11:44:58.658301 [Byte1]: 38
1673 11:44:58.662179
1674 11:44:58.662259 Set Vref, RX VrefLevel [Byte0]: 39
1675 11:44:58.666247 [Byte1]: 39
1676 11:44:58.670007
1677 11:44:58.670087 Set Vref, RX VrefLevel [Byte0]: 40
1678 11:44:58.673483 [Byte1]: 40
1679 11:44:58.677534
1680 11:44:58.677614 Set Vref, RX VrefLevel [Byte0]: 41
1681 11:44:58.680954 [Byte1]: 41
1682 11:44:58.685013
1683 11:44:58.685093 Set Vref, RX VrefLevel [Byte0]: 42
1684 11:44:58.688360 [Byte1]: 42
1685 11:44:58.692865
1686 11:44:58.692945 Set Vref, RX VrefLevel [Byte0]: 43
1687 11:44:58.696325 [Byte1]: 43
1688 11:44:58.701090
1689 11:44:58.701170 Set Vref, RX VrefLevel [Byte0]: 44
1690 11:44:58.703813 [Byte1]: 44
1691 11:44:58.708039
1692 11:44:58.708124 Set Vref, RX VrefLevel [Byte0]: 45
1693 11:44:58.711334 [Byte1]: 45
1694 11:44:58.715823
1695 11:44:58.715907 Set Vref, RX VrefLevel [Byte0]: 46
1696 11:44:58.719084 [Byte1]: 46
1697 11:44:58.723402
1698 11:44:58.723483 Set Vref, RX VrefLevel [Byte0]: 47
1699 11:44:58.726976 [Byte1]: 47
1700 11:44:58.731620
1701 11:44:58.731700 Set Vref, RX VrefLevel [Byte0]: 48
1702 11:44:58.734515 [Byte1]: 48
1703 11:44:58.738738
1704 11:44:58.738818 Set Vref, RX VrefLevel [Byte0]: 49
1705 11:44:58.742156 [Byte1]: 49
1706 11:44:58.746813
1707 11:44:58.746929 Set Vref, RX VrefLevel [Byte0]: 50
1708 11:44:58.749560 [Byte1]: 50
1709 11:44:58.754253
1710 11:44:58.754333 Set Vref, RX VrefLevel [Byte0]: 51
1711 11:44:58.757764 [Byte1]: 51
1712 11:44:58.762108
1713 11:44:58.762188 Set Vref, RX VrefLevel [Byte0]: 52
1714 11:44:58.765401 [Byte1]: 52
1715 11:44:58.769971
1716 11:44:58.770052 Set Vref, RX VrefLevel [Byte0]: 53
1717 11:44:58.772521 [Byte1]: 53
1718 11:44:58.776965
1719 11:44:58.777045 Set Vref, RX VrefLevel [Byte0]: 54
1720 11:44:58.780386 [Byte1]: 54
1721 11:44:58.784964
1722 11:44:58.785044 Set Vref, RX VrefLevel [Byte0]: 55
1723 11:44:58.788317 [Byte1]: 55
1724 11:44:58.792158
1725 11:44:58.792238 Set Vref, RX VrefLevel [Byte0]: 56
1726 11:44:58.795901 [Byte1]: 56
1727 11:44:58.800311
1728 11:44:58.800392 Set Vref, RX VrefLevel [Byte0]: 57
1729 11:44:58.803610 [Byte1]: 57
1730 11:44:58.808448
1731 11:44:58.808562 Set Vref, RX VrefLevel [Byte0]: 58
1732 11:44:58.810777 [Byte1]: 58
1733 11:44:58.815266
1734 11:44:58.815346 Set Vref, RX VrefLevel [Byte0]: 59
1735 11:44:58.818762 [Byte1]: 59
1736 11:44:58.823124
1737 11:44:58.823205 Set Vref, RX VrefLevel [Byte0]: 60
1738 11:44:58.826083 [Byte1]: 60
1739 11:44:58.830705
1740 11:44:58.830786 Set Vref, RX VrefLevel [Byte0]: 61
1741 11:44:58.833937 [Byte1]: 61
1742 11:44:58.838446
1743 11:44:58.838528 Set Vref, RX VrefLevel [Byte0]: 62
1744 11:44:58.841695 [Byte1]: 62
1745 11:44:58.845777
1746 11:44:58.845856 Set Vref, RX VrefLevel [Byte0]: 63
1747 11:44:58.849170 [Byte1]: 63
1748 11:44:58.853688
1749 11:44:58.853771 Set Vref, RX VrefLevel [Byte0]: 64
1750 11:44:58.856574 [Byte1]: 64
1751 11:44:58.861177
1752 11:44:58.861256 Set Vref, RX VrefLevel [Byte0]: 65
1753 11:44:58.864909 [Byte1]: 65
1754 11:44:58.868678
1755 11:44:58.868758 Set Vref, RX VrefLevel [Byte0]: 66
1756 11:44:58.872297 [Byte1]: 66
1757 11:44:58.876335
1758 11:44:58.876415 Set Vref, RX VrefLevel [Byte0]: 67
1759 11:44:58.879747 [Byte1]: 67
1760 11:44:58.884622
1761 11:44:58.884702 Set Vref, RX VrefLevel [Byte0]: 68
1762 11:44:58.887497 [Byte1]: 68
1763 11:44:58.892118
1764 11:44:58.892198 Set Vref, RX VrefLevel [Byte0]: 69
1765 11:44:58.895110 [Byte1]: 69
1766 11:44:58.899334
1767 11:44:58.899416 Set Vref, RX VrefLevel [Byte0]: 70
1768 11:44:58.902760 [Byte1]: 70
1769 11:44:58.907438
1770 11:44:58.907518 Set Vref, RX VrefLevel [Byte0]: 71
1771 11:44:58.910408 [Byte1]: 71
1772 11:44:58.914457
1773 11:44:58.914537 Set Vref, RX VrefLevel [Byte0]: 72
1774 11:44:58.917854 [Byte1]: 72
1775 11:44:58.922278
1776 11:44:58.922359 Set Vref, RX VrefLevel [Byte0]: 73
1777 11:44:58.925731 [Byte1]: 73
1778 11:44:58.930056
1779 11:44:58.930137 Set Vref, RX VrefLevel [Byte0]: 74
1780 11:44:58.933031 [Byte1]: 74
1781 11:44:58.937820
1782 11:44:58.937906 Set Vref, RX VrefLevel [Byte0]: 75
1783 11:44:58.940970 [Byte1]: 75
1784 11:44:58.945291
1785 11:44:58.945373 Set Vref, RX VrefLevel [Byte0]: 76
1786 11:44:58.948640 [Byte1]: 76
1787 11:44:58.952865
1788 11:44:58.952947 Set Vref, RX VrefLevel [Byte0]: 77
1789 11:44:58.955957 [Byte1]: 77
1790 11:44:58.960473
1791 11:44:58.960554 Final RX Vref Byte 0 = 64 to rank0
1792 11:44:58.964062 Final RX Vref Byte 1 = 59 to rank0
1793 11:44:58.967280 Final RX Vref Byte 0 = 64 to rank1
1794 11:44:58.970847 Final RX Vref Byte 1 = 59 to rank1==
1795 11:44:58.973810 Dram Type= 6, Freq= 0, CH_1, rank 0
1796 11:44:58.977268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 11:44:58.980757 ==
1798 11:44:58.980838 DQS Delay:
1799 11:44:58.980902 DQS0 = 0, DQS1 = 0
1800 11:44:58.984056 DQM Delay:
1801 11:44:58.984136 DQM0 = 83, DQM1 = 74
1802 11:44:58.987497 DQ Delay:
1803 11:44:58.987577 DQ0 =92, DQ1 =76, DQ2 =72, DQ3 =84
1804 11:44:58.990756 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1805 11:44:58.994244 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =76
1806 11:44:58.997912 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1807 11:44:58.997993
1808 11:44:59.000663
1809 11:44:59.007909 [DQSOSCAuto] RK0, (LSB)MR18= 0x2aff, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1810 11:44:59.010838 CH1 RK0: MR19=605, MR18=2AFF
1811 11:44:59.014820 CH1_RK0: MR19=0x605, MR18=0x2AFF, DQSOSC=399, MR23=63, INC=92, DEC=61
1812 11:44:59.017865
1813 11:44:59.021132 ----->DramcWriteLeveling(PI) begin...
1814 11:44:59.021217 ==
1815 11:44:59.024298 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 11:44:59.027794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 11:44:59.027876 ==
1818 11:44:59.031442 Write leveling (Byte 0): 26 => 26
1819 11:44:59.034524 Write leveling (Byte 1): 27 => 27
1820 11:44:59.038029 DramcWriteLeveling(PI) end<-----
1821 11:44:59.038109
1822 11:44:59.038173 ==
1823 11:44:59.041789 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 11:44:59.044852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 11:44:59.044933 ==
1826 11:44:59.047655 [Gating] SW mode calibration
1827 11:44:59.054643 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1828 11:44:59.057889 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1829 11:44:59.064824 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1830 11:44:59.067862 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1831 11:44:59.071304 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:44:59.078027 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1833 11:44:59.081465 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:44:59.084858 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:44:59.091845 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:44:59.094853 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:44:59.098141 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:44:59.105257 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:44:59.108305 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:44:59.111665 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:44:59.115262 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:44:59.121697 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:44:59.125045 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1844 11:44:59.128402 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1845 11:44:59.135218 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1846 11:44:59.138677 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1847 11:44:59.142161 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1848 11:44:59.148737 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:44:59.151911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:44:59.155608 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:44:59.161890 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:44:59.165052 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1853 11:44:59.168339 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:44:59.175219 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1855 11:44:59.178293 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1856 11:44:59.181833 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 11:44:59.185503 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 11:44:59.192205 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 11:44:59.195722 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1860 11:44:59.198475 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 11:44:59.205339 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1862 11:44:59.208788 0 10 4 | B1->B0 | 2e2e 2c2c | 1 0 | (1 0) (0 1)
1863 11:44:59.212235 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1864 11:44:59.218708 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:44:59.222085 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:44:59.225718 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:44:59.232567 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:44:59.235446 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:44:59.239148 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1870 11:44:59.245656 0 11 4 | B1->B0 | 3030 3737 | 0 0 | (0 0) (1 1)
1871 11:44:59.248761 0 11 8 | B1->B0 | 4141 4646 | 1 0 | (1 1) (0 0)
1872 11:44:59.252089 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 11:44:59.256004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 11:44:59.262367 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 11:44:59.265629 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 11:44:59.269402 0 11 28 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
1877 11:44:59.275631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 11:44:59.279062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1879 11:44:59.282455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:44:59.288993 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:44:59.292329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:44:59.295795 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 11:44:59.302571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 11:44:59.305870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 11:44:59.309444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 11:44:59.316015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 11:44:59.319168 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 11:44:59.322388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 11:44:59.326173 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 11:44:59.332983 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 11:44:59.336280 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 11:44:59.339265 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 11:44:59.346419 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 11:44:59.349392 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1895 11:44:59.352846 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 11:44:59.356226 Total UI for P1: 0, mck2ui 16
1897 11:44:59.359706 best dqsien dly found for B0: ( 0, 14, 4)
1898 11:44:59.363066 Total UI for P1: 0, mck2ui 16
1899 11:44:59.366419 best dqsien dly found for B1: ( 0, 14, 4)
1900 11:44:59.369421 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1901 11:44:59.373064 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1902 11:44:59.373145
1903 11:44:59.376406 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1904 11:44:59.383003 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1905 11:44:59.383106 [Gating] SW calibration Done
1906 11:44:59.383171 ==
1907 11:44:59.387078 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 11:44:59.393287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 11:44:59.393369 ==
1910 11:44:59.393431 RX Vref Scan: 0
1911 11:44:59.393490
1912 11:44:59.396468 RX Vref 0 -> 0, step: 1
1913 11:44:59.396548
1914 11:44:59.400254 RX Delay -130 -> 252, step: 16
1915 11:44:59.403045 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1916 11:44:59.406230 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1917 11:44:59.409771 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1918 11:44:59.412984 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1919 11:44:59.419853 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1920 11:44:59.423274 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1921 11:44:59.426661 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1922 11:44:59.430484 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1923 11:44:59.433668 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1924 11:44:59.439740 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1925 11:44:59.443546 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1926 11:44:59.446779 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1927 11:44:59.450104 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1928 11:44:59.453464 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1929 11:44:59.460359 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1930 11:44:59.463625 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1931 11:44:59.463723 ==
1932 11:44:59.467059 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 11:44:59.470537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 11:44:59.470644 ==
1935 11:44:59.470734 DQS Delay:
1936 11:44:59.474148 DQS0 = 0, DQS1 = 0
1937 11:44:59.474228 DQM Delay:
1938 11:44:59.476728 DQM0 = 80, DQM1 = 77
1939 11:44:59.476808 DQ Delay:
1940 11:44:59.480616 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1941 11:44:59.483904 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1942 11:44:59.487143 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1943 11:44:59.490452 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1944 11:44:59.490533
1945 11:44:59.490596
1946 11:44:59.490655 ==
1947 11:44:59.493696 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 11:44:59.497187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 11:44:59.497269 ==
1950 11:44:59.500478
1951 11:44:59.500558
1952 11:44:59.500621 TX Vref Scan disable
1953 11:44:59.504098 == TX Byte 0 ==
1954 11:44:59.507418 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1955 11:44:59.510473 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1956 11:44:59.513660 == TX Byte 1 ==
1957 11:44:59.517104 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1958 11:44:59.520367 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1959 11:44:59.520451 ==
1960 11:44:59.523784 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 11:44:59.530990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 11:44:59.531074 ==
1963 11:44:59.542243 TX Vref=22, minBit 0, minWin=27, winSum=440
1964 11:44:59.545833 TX Vref=24, minBit 11, minWin=26, winSum=440
1965 11:44:59.548885 TX Vref=26, minBit 5, minWin=27, winSum=443
1966 11:44:59.552142 TX Vref=28, minBit 10, minWin=27, winSum=449
1967 11:44:59.555392 TX Vref=30, minBit 0, minWin=27, winSum=450
1968 11:44:59.562297 TX Vref=32, minBit 13, minWin=27, winSum=453
1969 11:44:59.565818 [TxChooseVref] Worse bit 13, Min win 27, Win sum 453, Final Vref 32
1970 11:44:59.565903
1971 11:44:59.569271 Final TX Range 1 Vref 32
1972 11:44:59.569355
1973 11:44:59.569440 ==
1974 11:44:59.572604 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 11:44:59.575820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 11:44:59.575904 ==
1977 11:44:59.579058
1978 11:44:59.579142
1979 11:44:59.579241 TX Vref Scan disable
1980 11:44:59.582615 == TX Byte 0 ==
1981 11:44:59.585710 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1982 11:44:59.589208 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1983 11:44:59.592738 == TX Byte 1 ==
1984 11:44:59.596424 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1985 11:44:59.599476 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1986 11:44:59.599557
1987 11:44:59.602747 [DATLAT]
1988 11:44:59.602828 Freq=800, CH1 RK1
1989 11:44:59.602916
1990 11:44:59.606007 DATLAT Default: 0xa
1991 11:44:59.606088 0, 0xFFFF, sum = 0
1992 11:44:59.609398 1, 0xFFFF, sum = 0
1993 11:44:59.609480 2, 0xFFFF, sum = 0
1994 11:44:59.612967 3, 0xFFFF, sum = 0
1995 11:44:59.613049 4, 0xFFFF, sum = 0
1996 11:44:59.616343 5, 0xFFFF, sum = 0
1997 11:44:59.616425 6, 0xFFFF, sum = 0
1998 11:44:59.619581 7, 0xFFFF, sum = 0
1999 11:44:59.619663 8, 0xFFFF, sum = 0
2000 11:44:59.622825 9, 0x0, sum = 1
2001 11:44:59.622948 10, 0x0, sum = 2
2002 11:44:59.626124 11, 0x0, sum = 3
2003 11:44:59.626205 12, 0x0, sum = 4
2004 11:44:59.629747 best_step = 10
2005 11:44:59.629827
2006 11:44:59.629891 ==
2007 11:44:59.633236 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 11:44:59.636432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 11:44:59.636513 ==
2010 11:44:59.639969 RX Vref Scan: 0
2011 11:44:59.640050
2012 11:44:59.640114 RX Vref 0 -> 0, step: 1
2013 11:44:59.640173
2014 11:44:59.643171 RX Delay -95 -> 252, step: 8
2015 11:44:59.649545 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2016 11:44:59.653217 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2017 11:44:59.656315 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2018 11:44:59.659803 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2019 11:44:59.662755 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2020 11:44:59.666147 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2021 11:44:59.672758 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2022 11:44:59.676344 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2023 11:44:59.679640 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2024 11:44:59.683082 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2025 11:44:59.686451 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2026 11:44:59.693032 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2027 11:44:59.696436 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2028 11:44:59.700072 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2029 11:44:59.703201 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2030 11:44:59.706737 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2031 11:44:59.706818 ==
2032 11:44:59.709789 Dram Type= 6, Freq= 0, CH_1, rank 1
2033 11:44:59.716753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2034 11:44:59.716835 ==
2035 11:44:59.716898 DQS Delay:
2036 11:44:59.720258 DQS0 = 0, DQS1 = 0
2037 11:44:59.720343 DQM Delay:
2038 11:44:59.720407 DQM0 = 79, DQM1 = 75
2039 11:44:59.723870 DQ Delay:
2040 11:44:59.726993 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2041 11:44:59.730147 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2042 11:44:59.733717 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2043 11:44:59.737041 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2044 11:44:59.737121
2045 11:44:59.737184
2046 11:44:59.743723 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2047 11:44:59.747047 CH1 RK1: MR19=606, MR18=232E
2048 11:44:59.753635 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2049 11:44:59.756996 [RxdqsGatingPostProcess] freq 800
2050 11:44:59.760766 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2051 11:44:59.763654 Pre-setting of DQS Precalculation
2052 11:44:59.770643 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2053 11:44:59.777098 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2054 11:44:59.783959 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2055 11:44:59.784041
2056 11:44:59.784103
2057 11:44:59.787023 [Calibration Summary] 1600 Mbps
2058 11:44:59.787104 CH 0, Rank 0
2059 11:44:59.790531 SW Impedance : PASS
2060 11:44:59.790612 DUTY Scan : NO K
2061 11:44:59.793945 ZQ Calibration : PASS
2062 11:44:59.797317 Jitter Meter : NO K
2063 11:44:59.797398 CBT Training : PASS
2064 11:44:59.800647 Write leveling : PASS
2065 11:44:59.804438 RX DQS gating : PASS
2066 11:44:59.804519 RX DQ/DQS(RDDQC) : PASS
2067 11:44:59.807566 TX DQ/DQS : PASS
2068 11:44:59.810661 RX DATLAT : PASS
2069 11:44:59.810742 RX DQ/DQS(Engine): PASS
2070 11:44:59.814321 TX OE : NO K
2071 11:44:59.814402 All Pass.
2072 11:44:59.814465
2073 11:44:59.817755 CH 0, Rank 1
2074 11:44:59.817836 SW Impedance : PASS
2075 11:44:59.820869 DUTY Scan : NO K
2076 11:44:59.820950 ZQ Calibration : PASS
2077 11:44:59.824311 Jitter Meter : NO K
2078 11:44:59.827807 CBT Training : PASS
2079 11:44:59.827888 Write leveling : PASS
2080 11:44:59.831074 RX DQS gating : PASS
2081 11:44:59.834604 RX DQ/DQS(RDDQC) : PASS
2082 11:44:59.834689 TX DQ/DQS : PASS
2083 11:44:59.837864 RX DATLAT : PASS
2084 11:44:59.841045 RX DQ/DQS(Engine): PASS
2085 11:44:59.841126 TX OE : NO K
2086 11:44:59.844933 All Pass.
2087 11:44:59.845013
2088 11:44:59.845077 CH 1, Rank 0
2089 11:44:59.847980 SW Impedance : PASS
2090 11:44:59.848060 DUTY Scan : NO K
2091 11:44:59.851235 ZQ Calibration : PASS
2092 11:44:59.851316 Jitter Meter : NO K
2093 11:44:59.854434 CBT Training : PASS
2094 11:44:59.858185 Write leveling : PASS
2095 11:44:59.858265 RX DQS gating : PASS
2096 11:44:59.861534 RX DQ/DQS(RDDQC) : PASS
2097 11:44:59.864974 TX DQ/DQS : PASS
2098 11:44:59.865055 RX DATLAT : PASS
2099 11:44:59.868333 RX DQ/DQS(Engine): PASS
2100 11:44:59.871540 TX OE : NO K
2101 11:44:59.871620 All Pass.
2102 11:44:59.871683
2103 11:44:59.871742 CH 1, Rank 1
2104 11:44:59.874892 SW Impedance : PASS
2105 11:44:59.878551 DUTY Scan : NO K
2106 11:44:59.878632 ZQ Calibration : PASS
2107 11:44:59.881644 Jitter Meter : NO K
2108 11:44:59.884974 CBT Training : PASS
2109 11:44:59.885055 Write leveling : PASS
2110 11:44:59.888431 RX DQS gating : PASS
2111 11:44:59.888512 RX DQ/DQS(RDDQC) : PASS
2112 11:44:59.891948 TX DQ/DQS : PASS
2113 11:44:59.895139 RX DATLAT : PASS
2114 11:44:59.895219 RX DQ/DQS(Engine): PASS
2115 11:44:59.898379 TX OE : NO K
2116 11:44:59.898460 All Pass.
2117 11:44:59.898523
2118 11:44:59.901837 DramC Write-DBI off
2119 11:44:59.905312 PER_BANK_REFRESH: Hybrid Mode
2120 11:44:59.905392 TX_TRACKING: ON
2121 11:44:59.908268 [GetDramInforAfterCalByMRR] Vendor 6.
2122 11:44:59.911647 [GetDramInforAfterCalByMRR] Revision 606.
2123 11:44:59.915182 [GetDramInforAfterCalByMRR] Revision 2 0.
2124 11:44:59.918671 MR0 0x3b3b
2125 11:44:59.918750 MR8 0x5151
2126 11:44:59.921838 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 11:44:59.921919
2128 11:44:59.921983 MR0 0x3b3b
2129 11:44:59.925268 MR8 0x5151
2130 11:44:59.928413 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2131 11:44:59.928494
2132 11:44:59.938244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2133 11:44:59.941847 [FAST_K] Save calibration result to emmc
2134 11:44:59.945843 [FAST_K] Save calibration result to emmc
2135 11:44:59.945924 dram_init: config_dvfs: 1
2136 11:44:59.952112 dramc_set_vcore_voltage set vcore to 662500
2137 11:44:59.952193 Read voltage for 1200, 2
2138 11:44:59.955596 Vio18 = 0
2139 11:44:59.955677 Vcore = 662500
2140 11:44:59.955740 Vdram = 0
2141 11:44:59.955799 Vddq = 0
2142 11:44:59.958626 Vmddr = 0
2143 11:44:59.961900 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2144 11:44:59.968775 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2145 11:44:59.968855 MEM_TYPE=3, freq_sel=15
2146 11:44:59.972443 sv_algorithm_assistance_LP4_1600
2147 11:44:59.978653 ============ PULL DRAM RESETB DOWN ============
2148 11:44:59.982589 ========== PULL DRAM RESETB DOWN end =========
2149 11:44:59.985910 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2150 11:44:59.988673 ===================================
2151 11:44:59.992099 LPDDR4 DRAM CONFIGURATION
2152 11:44:59.995661 ===================================
2153 11:44:59.995743 EX_ROW_EN[0] = 0x0
2154 11:44:59.999047 EX_ROW_EN[1] = 0x0
2155 11:45:00.002182 LP4Y_EN = 0x0
2156 11:45:00.002262 WORK_FSP = 0x0
2157 11:45:00.005904 WL = 0x4
2158 11:45:00.006027 RL = 0x4
2159 11:45:00.009255 BL = 0x2
2160 11:45:00.009339 RPST = 0x0
2161 11:45:00.012666 RD_PRE = 0x0
2162 11:45:00.012745 WR_PRE = 0x1
2163 11:45:00.015521 WR_PST = 0x0
2164 11:45:00.015601 DBI_WR = 0x0
2165 11:45:00.018958 DBI_RD = 0x0
2166 11:45:00.019037 OTF = 0x1
2167 11:45:00.022344 ===================================
2168 11:45:00.026175 ===================================
2169 11:45:00.029361 ANA top config
2170 11:45:00.032946 ===================================
2171 11:45:00.033026 DLL_ASYNC_EN = 0
2172 11:45:00.035818 ALL_SLAVE_EN = 0
2173 11:45:00.039029 NEW_RANK_MODE = 1
2174 11:45:00.042445 DLL_IDLE_MODE = 1
2175 11:45:00.042524 LP45_APHY_COMB_EN = 1
2176 11:45:00.046538 TX_ODT_DIS = 1
2177 11:45:00.048988 NEW_8X_MODE = 1
2178 11:45:00.052774 ===================================
2179 11:45:00.055969 ===================================
2180 11:45:00.059278 data_rate = 2400
2181 11:45:00.062598 CKR = 1
2182 11:45:00.062678 DQ_P2S_RATIO = 8
2183 11:45:00.066305 ===================================
2184 11:45:00.069330 CA_P2S_RATIO = 8
2185 11:45:00.072920 DQ_CA_OPEN = 0
2186 11:45:00.076449 DQ_SEMI_OPEN = 0
2187 11:45:00.079818 CA_SEMI_OPEN = 0
2188 11:45:00.082892 CA_FULL_RATE = 0
2189 11:45:00.082986 DQ_CKDIV4_EN = 0
2190 11:45:00.086551 CA_CKDIV4_EN = 0
2191 11:45:00.089610 CA_PREDIV_EN = 0
2192 11:45:00.092989 PH8_DLY = 17
2193 11:45:00.095993 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2194 11:45:00.096073 DQ_AAMCK_DIV = 4
2195 11:45:00.099846 CA_AAMCK_DIV = 4
2196 11:45:00.103253 CA_ADMCK_DIV = 4
2197 11:45:00.106291 DQ_TRACK_CA_EN = 0
2198 11:45:00.109625 CA_PICK = 1200
2199 11:45:00.113174 CA_MCKIO = 1200
2200 11:45:00.116215 MCKIO_SEMI = 0
2201 11:45:00.116295 PLL_FREQ = 2366
2202 11:45:00.119626 DQ_UI_PI_RATIO = 32
2203 11:45:00.123315 CA_UI_PI_RATIO = 0
2204 11:45:00.126327 ===================================
2205 11:45:00.129803 ===================================
2206 11:45:00.133389 memory_type:LPDDR4
2207 11:45:00.133473 GP_NUM : 10
2208 11:45:00.136807 SRAM_EN : 1
2209 11:45:00.140247 MD32_EN : 0
2210 11:45:00.143518 ===================================
2211 11:45:00.143597 [ANA_INIT] >>>>>>>>>>>>>>
2212 11:45:00.146737 <<<<<< [CONFIGURE PHASE]: ANA_TX
2213 11:45:00.150096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2214 11:45:00.153454 ===================================
2215 11:45:00.157060 data_rate = 2400,PCW = 0X5b00
2216 11:45:00.160403 ===================================
2217 11:45:00.163714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2218 11:45:00.170312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2219 11:45:00.173727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2220 11:45:00.180374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2221 11:45:00.183480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2222 11:45:00.186743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2223 11:45:00.186825 [ANA_INIT] flow start
2224 11:45:00.190602 [ANA_INIT] PLL >>>>>>>>
2225 11:45:00.193973 [ANA_INIT] PLL <<<<<<<<
2226 11:45:00.194054 [ANA_INIT] MIDPI >>>>>>>>
2227 11:45:00.196855 [ANA_INIT] MIDPI <<<<<<<<
2228 11:45:00.200470 [ANA_INIT] DLL >>>>>>>>
2229 11:45:00.200551 [ANA_INIT] DLL <<<<<<<<
2230 11:45:00.203972 [ANA_INIT] flow end
2231 11:45:00.207253 ============ LP4 DIFF to SE enter ============
2232 11:45:00.211075 ============ LP4 DIFF to SE exit ============
2233 11:45:00.213541 [ANA_INIT] <<<<<<<<<<<<<
2234 11:45:00.216881 [Flow] Enable top DCM control >>>>>
2235 11:45:00.220378 [Flow] Enable top DCM control <<<<<
2236 11:45:00.224137 Enable DLL master slave shuffle
2237 11:45:00.230336 ==============================================================
2238 11:45:00.230445 Gating Mode config
2239 11:45:00.237724 ==============================================================
2240 11:45:00.237805 Config description:
2241 11:45:00.247626 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2242 11:45:00.254067 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2243 11:45:00.261046 SELPH_MODE 0: By rank 1: By Phase
2244 11:45:00.264043 ==============================================================
2245 11:45:00.267588 GAT_TRACK_EN = 1
2246 11:45:00.270745 RX_GATING_MODE = 2
2247 11:45:00.274083 RX_GATING_TRACK_MODE = 2
2248 11:45:00.278005 SELPH_MODE = 1
2249 11:45:00.281198 PICG_EARLY_EN = 1
2250 11:45:00.284486 VALID_LAT_VALUE = 1
2251 11:45:00.287627 ==============================================================
2252 11:45:00.290791 Enter into Gating configuration >>>>
2253 11:45:00.294533 Exit from Gating configuration <<<<
2254 11:45:00.297647 Enter into DVFS_PRE_config >>>>>
2255 11:45:00.307661 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2256 11:45:00.311477 Exit from DVFS_PRE_config <<<<<
2257 11:45:00.314577 Enter into PICG configuration >>>>
2258 11:45:00.318185 Exit from PICG configuration <<<<
2259 11:45:00.321660 [RX_INPUT] configuration >>>>>
2260 11:45:00.324897 [RX_INPUT] configuration <<<<<
2261 11:45:00.331460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2262 11:45:00.334605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2263 11:45:00.341350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2264 11:45:00.348289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2265 11:45:00.354746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 11:45:00.358161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 11:45:00.365049 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2268 11:45:00.368433 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2269 11:45:00.371907 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2270 11:45:00.374836 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2271 11:45:00.381614 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2272 11:45:00.384777 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 11:45:00.388219 ===================================
2274 11:45:00.392025 LPDDR4 DRAM CONFIGURATION
2275 11:45:00.395257 ===================================
2276 11:45:00.395336 EX_ROW_EN[0] = 0x0
2277 11:45:00.398330 EX_ROW_EN[1] = 0x0
2278 11:45:00.398411 LP4Y_EN = 0x0
2279 11:45:00.401731 WORK_FSP = 0x0
2280 11:45:00.401811 WL = 0x4
2281 11:45:00.405125 RL = 0x4
2282 11:45:00.405206 BL = 0x2
2283 11:45:00.408815 RPST = 0x0
2284 11:45:00.408896 RD_PRE = 0x0
2285 11:45:00.411842 WR_PRE = 0x1
2286 11:45:00.411922 WR_PST = 0x0
2287 11:45:00.415320 DBI_WR = 0x0
2288 11:45:00.415401 DBI_RD = 0x0
2289 11:45:00.418987 OTF = 0x1
2290 11:45:00.421881 ===================================
2291 11:45:00.425540 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2292 11:45:00.428752 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2293 11:45:00.435292 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2294 11:45:00.439149 ===================================
2295 11:45:00.439231 LPDDR4 DRAM CONFIGURATION
2296 11:45:00.442402 ===================================
2297 11:45:00.445197 EX_ROW_EN[0] = 0x10
2298 11:45:00.445269 EX_ROW_EN[1] = 0x0
2299 11:45:00.448614 LP4Y_EN = 0x0
2300 11:45:00.452119 WORK_FSP = 0x0
2301 11:45:00.452211 WL = 0x4
2302 11:45:00.455527 RL = 0x4
2303 11:45:00.455606 BL = 0x2
2304 11:45:00.459171 RPST = 0x0
2305 11:45:00.459250 RD_PRE = 0x0
2306 11:45:00.462503 WR_PRE = 0x1
2307 11:45:00.462582 WR_PST = 0x0
2308 11:45:00.465361 DBI_WR = 0x0
2309 11:45:00.465440 DBI_RD = 0x0
2310 11:45:00.468824 OTF = 0x1
2311 11:45:00.472198 ===================================
2312 11:45:00.475720 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2313 11:45:00.479689 ==
2314 11:45:00.482844 Dram Type= 6, Freq= 0, CH_0, rank 0
2315 11:45:00.485902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2316 11:45:00.485982 ==
2317 11:45:00.489393 [Duty_Offset_Calibration]
2318 11:45:00.489474 B0:3 B1:-1 CA:1
2319 11:45:00.489537
2320 11:45:00.492552 [DutyScan_Calibration_Flow] k_type=0
2321 11:45:00.501306
2322 11:45:00.501386 ==CLK 0==
2323 11:45:00.504763 Final CLK duty delay cell = -4
2324 11:45:00.507443 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2325 11:45:00.511114 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2326 11:45:00.514090 [-4] AVG Duty = 4953%(X100)
2327 11:45:00.514172
2328 11:45:00.517601 CH0 CLK Duty spec in!! Max-Min= 156%
2329 11:45:00.520980 [DutyScan_Calibration_Flow] ====Done====
2330 11:45:00.521060
2331 11:45:00.524042 [DutyScan_Calibration_Flow] k_type=1
2332 11:45:00.539677
2333 11:45:00.539782 ==DQS 0 ==
2334 11:45:00.543176 Final DQS duty delay cell = 0
2335 11:45:00.546560 [0] MAX Duty = 5125%(X100), DQS PI = 42
2336 11:45:00.550093 [0] MIN Duty = 5000%(X100), DQS PI = 12
2337 11:45:00.550172 [0] AVG Duty = 5062%(X100)
2338 11:45:00.553547
2339 11:45:00.553625 ==DQS 1 ==
2340 11:45:00.557067 Final DQS duty delay cell = -4
2341 11:45:00.560338 [-4] MAX Duty = 5093%(X100), DQS PI = 4
2342 11:45:00.563670 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2343 11:45:00.566701 [-4] AVG Duty = 5046%(X100)
2344 11:45:00.566780
2345 11:45:00.570131 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2346 11:45:00.570237
2347 11:45:00.573631 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2348 11:45:00.577147 [DutyScan_Calibration_Flow] ====Done====
2349 11:45:00.577226
2350 11:45:00.580176 [DutyScan_Calibration_Flow] k_type=3
2351 11:45:00.596472
2352 11:45:00.596551 ==DQM 0 ==
2353 11:45:00.599737 Final DQM duty delay cell = 0
2354 11:45:00.603833 [0] MAX Duty = 5000%(X100), DQS PI = 32
2355 11:45:00.606462 [0] MIN Duty = 4875%(X100), DQS PI = 4
2356 11:45:00.606543 [0] AVG Duty = 4937%(X100)
2357 11:45:00.609843
2358 11:45:00.609922 ==DQM 1 ==
2359 11:45:00.613333 Final DQM duty delay cell = 0
2360 11:45:00.616651 [0] MAX Duty = 5156%(X100), DQS PI = 62
2361 11:45:00.620424 [0] MIN Duty = 5000%(X100), DQS PI = 8
2362 11:45:00.620504 [0] AVG Duty = 5078%(X100)
2363 11:45:00.620567
2364 11:45:00.623560 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2365 11:45:00.627356
2366 11:45:00.630548 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2367 11:45:00.633422 [DutyScan_Calibration_Flow] ====Done====
2368 11:45:00.633510
2369 11:45:00.636800 [DutyScan_Calibration_Flow] k_type=2
2370 11:45:00.652089
2371 11:45:00.652169 ==DQ 0 ==
2372 11:45:00.655683 Final DQ duty delay cell = -4
2373 11:45:00.659080 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2374 11:45:00.662287 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2375 11:45:00.665811 [-4] AVG Duty = 4968%(X100)
2376 11:45:00.665891
2377 11:45:00.665955 ==DQ 1 ==
2378 11:45:00.669103 Final DQ duty delay cell = 0
2379 11:45:00.672349 [0] MAX Duty = 5031%(X100), DQS PI = 18
2380 11:45:00.675648 [0] MIN Duty = 4907%(X100), DQS PI = 46
2381 11:45:00.679062 [0] AVG Duty = 4969%(X100)
2382 11:45:00.679141
2383 11:45:00.682536 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2384 11:45:00.682620
2385 11:45:00.685499 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2386 11:45:00.688648 [DutyScan_Calibration_Flow] ====Done====
2387 11:45:00.688728 ==
2388 11:45:00.692272 Dram Type= 6, Freq= 0, CH_1, rank 0
2389 11:45:00.695794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2390 11:45:00.695874 ==
2391 11:45:00.699089 [Duty_Offset_Calibration]
2392 11:45:00.699169 B0:1 B1:1 CA:2
2393 11:45:00.699232
2394 11:45:00.702571 [DutyScan_Calibration_Flow] k_type=0
2395 11:45:00.712716
2396 11:45:00.712817 ==CLK 0==
2397 11:45:00.716126 Final CLK duty delay cell = 0
2398 11:45:00.719571 [0] MAX Duty = 5156%(X100), DQS PI = 24
2399 11:45:00.722566 [0] MIN Duty = 4969%(X100), DQS PI = 38
2400 11:45:00.722661 [0] AVG Duty = 5062%(X100)
2401 11:45:00.725785
2402 11:45:00.725868 CH1 CLK Duty spec in!! Max-Min= 187%
2403 11:45:00.732870 [DutyScan_Calibration_Flow] ====Done====
2404 11:45:00.732957
2405 11:45:00.736011 [DutyScan_Calibration_Flow] k_type=1
2406 11:45:00.751911
2407 11:45:00.751998 ==DQS 0 ==
2408 11:45:00.755146 Final DQS duty delay cell = 0
2409 11:45:00.758466 [0] MAX Duty = 5031%(X100), DQS PI = 18
2410 11:45:00.762233 [0] MIN Duty = 4844%(X100), DQS PI = 50
2411 11:45:00.762339 [0] AVG Duty = 4937%(X100)
2412 11:45:00.765509
2413 11:45:00.765592 ==DQS 1 ==
2414 11:45:00.768811 Final DQS duty delay cell = 0
2415 11:45:00.772321 [0] MAX Duty = 5062%(X100), DQS PI = 36
2416 11:45:00.775474 [0] MIN Duty = 4907%(X100), DQS PI = 14
2417 11:45:00.775582 [0] AVG Duty = 4984%(X100)
2418 11:45:00.778719
2419 11:45:00.781937 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2420 11:45:00.782021
2421 11:45:00.785676 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2422 11:45:00.788682 [DutyScan_Calibration_Flow] ====Done====
2423 11:45:00.788765
2424 11:45:00.791976 [DutyScan_Calibration_Flow] k_type=3
2425 11:45:00.808829
2426 11:45:00.808913 ==DQM 0 ==
2427 11:45:00.812323 Final DQM duty delay cell = 0
2428 11:45:00.815284 [0] MAX Duty = 5093%(X100), DQS PI = 18
2429 11:45:00.818604 [0] MIN Duty = 4876%(X100), DQS PI = 50
2430 11:45:00.818689 [0] AVG Duty = 4984%(X100)
2431 11:45:00.818789
2432 11:45:00.822156 ==DQM 1 ==
2433 11:45:00.825597 Final DQM duty delay cell = 0
2434 11:45:00.828664 [0] MAX Duty = 5156%(X100), DQS PI = 62
2435 11:45:00.832482 [0] MIN Duty = 4938%(X100), DQS PI = 22
2436 11:45:00.832566 [0] AVG Duty = 5047%(X100)
2437 11:45:00.832651
2438 11:45:00.838823 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2439 11:45:00.838929
2440 11:45:00.842233 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2441 11:45:00.845521 [DutyScan_Calibration_Flow] ====Done====
2442 11:45:00.845605
2443 11:45:00.848718 [DutyScan_Calibration_Flow] k_type=2
2444 11:45:00.865060
2445 11:45:00.865143 ==DQ 0 ==
2446 11:45:00.868439 Final DQ duty delay cell = 0
2447 11:45:00.871780 [0] MAX Duty = 5124%(X100), DQS PI = 18
2448 11:45:00.875022 [0] MIN Duty = 4938%(X100), DQS PI = 60
2449 11:45:00.875106 [0] AVG Duty = 5031%(X100)
2450 11:45:00.875192
2451 11:45:00.878509 ==DQ 1 ==
2452 11:45:00.881641 Final DQ duty delay cell = 0
2453 11:45:00.885138 [0] MAX Duty = 5093%(X100), DQS PI = 10
2454 11:45:00.888688 [0] MIN Duty = 5031%(X100), DQS PI = 2
2455 11:45:00.888828 [0] AVG Duty = 5062%(X100)
2456 11:45:00.888923
2457 11:45:00.891730 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2458 11:45:00.891811
2459 11:45:00.895491 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2460 11:45:00.898965 [DutyScan_Calibration_Flow] ====Done====
2461 11:45:00.903832 nWR fixed to 30
2462 11:45:00.907311 [ModeRegInit_LP4] CH0 RK0
2463 11:45:00.907392 [ModeRegInit_LP4] CH0 RK1
2464 11:45:00.910798 [ModeRegInit_LP4] CH1 RK0
2465 11:45:00.913931 [ModeRegInit_LP4] CH1 RK1
2466 11:45:00.914013 match AC timing 7
2467 11:45:00.920683 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2468 11:45:00.924349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2469 11:45:00.927669 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2470 11:45:00.934385 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2471 11:45:00.937699 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2472 11:45:00.937780 ==
2473 11:45:00.940614 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 11:45:00.944133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2475 11:45:00.944215 ==
2476 11:45:00.950715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2477 11:45:00.957600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2478 11:45:00.964845 [CA 0] Center 40 (10~71) winsize 62
2479 11:45:00.968396 [CA 1] Center 39 (9~70) winsize 62
2480 11:45:00.971958 [CA 2] Center 36 (6~67) winsize 62
2481 11:45:00.974745 [CA 3] Center 36 (5~67) winsize 63
2482 11:45:00.978380 [CA 4] Center 35 (5~65) winsize 61
2483 11:45:00.981912 [CA 5] Center 34 (4~65) winsize 62
2484 11:45:00.981992
2485 11:45:00.985248 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2486 11:45:00.985328
2487 11:45:00.988838 [CATrainingPosCal] consider 1 rank data
2488 11:45:00.991799 u2DelayCellTimex100 = 270/100 ps
2489 11:45:00.995438 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2490 11:45:00.998355 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2491 11:45:01.001985 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2492 11:45:01.008727 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2493 11:45:01.012236 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2494 11:45:01.015515 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2495 11:45:01.015594
2496 11:45:01.018955 CA PerBit enable=1, Macro0, CA PI delay=34
2497 11:45:01.019035
2498 11:45:01.022204 [CBTSetCACLKResult] CA Dly = 34
2499 11:45:01.022283 CS Dly: 7 (0~38)
2500 11:45:01.022346 ==
2501 11:45:01.025295 Dram Type= 6, Freq= 0, CH_0, rank 1
2502 11:45:01.032556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 11:45:01.032640 ==
2504 11:45:01.035908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 11:45:01.042362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2506 11:45:01.051318 [CA 0] Center 39 (9~70) winsize 62
2507 11:45:01.054644 [CA 1] Center 39 (9~70) winsize 62
2508 11:45:01.057781 [CA 2] Center 36 (6~67) winsize 62
2509 11:45:01.061364 [CA 3] Center 36 (5~67) winsize 63
2510 11:45:01.064829 [CA 4] Center 34 (4~65) winsize 62
2511 11:45:01.067640 [CA 5] Center 34 (4~64) winsize 61
2512 11:45:01.067724
2513 11:45:01.071233 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2514 11:45:01.071317
2515 11:45:01.074836 [CATrainingPosCal] consider 2 rank data
2516 11:45:01.077861 u2DelayCellTimex100 = 270/100 ps
2517 11:45:01.081251 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2518 11:45:01.084417 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2519 11:45:01.087931 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2520 11:45:01.094606 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2521 11:45:01.098088 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2522 11:45:01.101081 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2523 11:45:01.101165
2524 11:45:01.104714 CA PerBit enable=1, Macro0, CA PI delay=34
2525 11:45:01.104798
2526 11:45:01.107818 [CBTSetCACLKResult] CA Dly = 34
2527 11:45:01.107902 CS Dly: 8 (0~41)
2528 11:45:01.107988
2529 11:45:01.111136 ----->DramcWriteLeveling(PI) begin...
2530 11:45:01.111221 ==
2531 11:45:01.114532 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 11:45:01.121377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 11:45:01.121462 ==
2534 11:45:01.124570 Write leveling (Byte 0): 29 => 29
2535 11:45:01.124655 Write leveling (Byte 1): 29 => 29
2536 11:45:01.128157 DramcWriteLeveling(PI) end<-----
2537 11:45:01.128241
2538 11:45:01.131803 ==
2539 11:45:01.131890 Dram Type= 6, Freq= 0, CH_0, rank 0
2540 11:45:01.138285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2541 11:45:01.138370 ==
2542 11:45:01.141896 [Gating] SW mode calibration
2543 11:45:01.148447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2544 11:45:01.152183 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2545 11:45:01.155271 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 11:45:01.162243 0 15 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2547 11:45:01.165547 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2548 11:45:01.168834 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 11:45:01.175538 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 11:45:01.178704 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 11:45:01.182079 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 11:45:01.188815 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 11:45:01.192738 1 0 0 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
2554 11:45:01.196221 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2555 11:45:01.202652 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 11:45:01.205878 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 11:45:01.209343 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 11:45:01.212625 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 11:45:01.219018 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 11:45:01.222388 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 11:45:01.225642 1 1 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (1 1)
2562 11:45:01.232656 1 1 4 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
2563 11:45:01.235860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 11:45:01.239439 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 11:45:01.245888 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 11:45:01.249245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 11:45:01.253024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 11:45:01.259237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 11:45:01.263035 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2570 11:45:01.265899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2571 11:45:01.269378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:45:01.276276 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:45:01.279675 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 11:45:01.283026 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 11:45:01.289673 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 11:45:01.292958 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 11:45:01.296201 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 11:45:01.303285 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 11:45:01.306972 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 11:45:01.309937 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 11:45:01.316554 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 11:45:01.320142 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 11:45:01.323672 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 11:45:01.326750 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 11:45:01.333632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2586 11:45:01.337382 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2587 11:45:01.340406 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 11:45:01.343649 Total UI for P1: 0, mck2ui 16
2589 11:45:01.347041 best dqsien dly found for B0: ( 1, 4, 2)
2590 11:45:01.350738 Total UI for P1: 0, mck2ui 16
2591 11:45:01.353999 best dqsien dly found for B1: ( 1, 4, 2)
2592 11:45:01.357208 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2593 11:45:01.360608 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2594 11:45:01.360693
2595 11:45:01.363952 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2596 11:45:01.370190 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2597 11:45:01.370275 [Gating] SW calibration Done
2598 11:45:01.370361 ==
2599 11:45:01.373799 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 11:45:01.380743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 11:45:01.380829 ==
2602 11:45:01.380914 RX Vref Scan: 0
2603 11:45:01.380995
2604 11:45:01.383747 RX Vref 0 -> 0, step: 1
2605 11:45:01.383831
2606 11:45:01.387240 RX Delay -40 -> 252, step: 8
2607 11:45:01.390797 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2608 11:45:01.393766 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2609 11:45:01.397314 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2610 11:45:01.400770 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2611 11:45:01.407500 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2612 11:45:01.410965 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2613 11:45:01.414300 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2614 11:45:01.417453 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2615 11:45:01.420719 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2616 11:45:01.424625 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2617 11:45:01.431254 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2618 11:45:01.434039 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2619 11:45:01.437855 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2620 11:45:01.441326 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2621 11:45:01.444779 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2622 11:45:01.450719 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2623 11:45:01.450825 ==
2624 11:45:01.454102 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 11:45:01.457526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 11:45:01.457653 ==
2627 11:45:01.457763 DQS Delay:
2628 11:45:01.460943 DQS0 = 0, DQS1 = 0
2629 11:45:01.461042 DQM Delay:
2630 11:45:01.464273 DQM0 = 116, DQM1 = 107
2631 11:45:01.464367 DQ Delay:
2632 11:45:01.467768 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2633 11:45:01.471320 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2634 11:45:01.475155 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2635 11:45:01.478075 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2636 11:45:01.478175
2637 11:45:01.478264
2638 11:45:01.478348 ==
2639 11:45:01.481318 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 11:45:01.488012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 11:45:01.488117 ==
2642 11:45:01.488207
2643 11:45:01.488291
2644 11:45:01.488376 TX Vref Scan disable
2645 11:45:01.491579 == TX Byte 0 ==
2646 11:45:01.495056 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2647 11:45:01.498342 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2648 11:45:01.501852 == TX Byte 1 ==
2649 11:45:01.504658 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2650 11:45:01.508341 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2651 11:45:01.511636 ==
2652 11:45:01.514855 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 11:45:01.518391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 11:45:01.518514 ==
2655 11:45:01.529666 TX Vref=22, minBit 1, minWin=25, winSum=417
2656 11:45:01.532840 TX Vref=24, minBit 5, minWin=25, winSum=424
2657 11:45:01.536236 TX Vref=26, minBit 1, minWin=25, winSum=428
2658 11:45:01.539452 TX Vref=28, minBit 5, minWin=25, winSum=427
2659 11:45:01.542864 TX Vref=30, minBit 1, minWin=26, winSum=436
2660 11:45:01.546083 TX Vref=32, minBit 1, minWin=26, winSum=436
2661 11:45:01.553098 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
2662 11:45:01.553232
2663 11:45:01.556196 Final TX Range 1 Vref 30
2664 11:45:01.556306
2665 11:45:01.556411 ==
2666 11:45:01.559819 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 11:45:01.562891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 11:45:01.562992 ==
2669 11:45:01.563078
2670 11:45:01.563158
2671 11:45:01.566773 TX Vref Scan disable
2672 11:45:01.569783 == TX Byte 0 ==
2673 11:45:01.573068 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2674 11:45:01.576302 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2675 11:45:01.579816 == TX Byte 1 ==
2676 11:45:01.583005 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2677 11:45:01.586745 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2678 11:45:01.586832
2679 11:45:01.590124 [DATLAT]
2680 11:45:01.590208 Freq=1200, CH0 RK0
2681 11:45:01.590294
2682 11:45:01.593019 DATLAT Default: 0xd
2683 11:45:01.593104 0, 0xFFFF, sum = 0
2684 11:45:01.596625 1, 0xFFFF, sum = 0
2685 11:45:01.596711 2, 0xFFFF, sum = 0
2686 11:45:01.600246 3, 0xFFFF, sum = 0
2687 11:45:01.600334 4, 0xFFFF, sum = 0
2688 11:45:01.603204 5, 0xFFFF, sum = 0
2689 11:45:01.603330 6, 0xFFFF, sum = 0
2690 11:45:01.606660 7, 0xFFFF, sum = 0
2691 11:45:01.606781 8, 0xFFFF, sum = 0
2692 11:45:01.609908 9, 0xFFFF, sum = 0
2693 11:45:01.609994 10, 0xFFFF, sum = 0
2694 11:45:01.613482 11, 0xFFFF, sum = 0
2695 11:45:01.613568 12, 0x0, sum = 1
2696 11:45:01.616480 13, 0x0, sum = 2
2697 11:45:01.616568 14, 0x0, sum = 3
2698 11:45:01.620205 15, 0x0, sum = 4
2699 11:45:01.620324 best_step = 13
2700 11:45:01.620425
2701 11:45:01.620506 ==
2702 11:45:01.623685 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 11:45:01.626839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 11:45:01.629863 ==
2705 11:45:01.629949 RX Vref Scan: 1
2706 11:45:01.630036
2707 11:45:01.633466 Set Vref Range= 32 -> 127
2708 11:45:01.633551
2709 11:45:01.637039 RX Vref 32 -> 127, step: 1
2710 11:45:01.637123
2711 11:45:01.637208 RX Delay -21 -> 252, step: 4
2712 11:45:01.637289
2713 11:45:01.640325 Set Vref, RX VrefLevel [Byte0]: 32
2714 11:45:01.643727 [Byte1]: 32
2715 11:45:01.647332
2716 11:45:01.647417 Set Vref, RX VrefLevel [Byte0]: 33
2717 11:45:01.650637 [Byte1]: 33
2718 11:45:01.655544
2719 11:45:01.655629 Set Vref, RX VrefLevel [Byte0]: 34
2720 11:45:01.658628 [Byte1]: 34
2721 11:45:01.663598
2722 11:45:01.663686 Set Vref, RX VrefLevel [Byte0]: 35
2723 11:45:01.667015 [Byte1]: 35
2724 11:45:01.671347
2725 11:45:01.671431 Set Vref, RX VrefLevel [Byte0]: 36
2726 11:45:01.674757 [Byte1]: 36
2727 11:45:01.679547
2728 11:45:01.679632 Set Vref, RX VrefLevel [Byte0]: 37
2729 11:45:01.682585 [Byte1]: 37
2730 11:45:01.687237
2731 11:45:01.687321 Set Vref, RX VrefLevel [Byte0]: 38
2732 11:45:01.690292 [Byte1]: 38
2733 11:45:01.695270
2734 11:45:01.695354 Set Vref, RX VrefLevel [Byte0]: 39
2735 11:45:01.698593 [Byte1]: 39
2736 11:45:01.703150
2737 11:45:01.703235 Set Vref, RX VrefLevel [Byte0]: 40
2738 11:45:01.706669 [Byte1]: 40
2739 11:45:01.711333
2740 11:45:01.711418 Set Vref, RX VrefLevel [Byte0]: 41
2741 11:45:01.714507 [Byte1]: 41
2742 11:45:01.718996
2743 11:45:01.719081 Set Vref, RX VrefLevel [Byte0]: 42
2744 11:45:01.722094 [Byte1]: 42
2745 11:45:01.726773
2746 11:45:01.726919 Set Vref, RX VrefLevel [Byte0]: 43
2747 11:45:01.729952 [Byte1]: 43
2748 11:45:01.735115
2749 11:45:01.735196 Set Vref, RX VrefLevel [Byte0]: 44
2750 11:45:01.738370 [Byte1]: 44
2751 11:45:01.743099
2752 11:45:01.743184 Set Vref, RX VrefLevel [Byte0]: 45
2753 11:45:01.746009 [Byte1]: 45
2754 11:45:01.750855
2755 11:45:01.750992 Set Vref, RX VrefLevel [Byte0]: 46
2756 11:45:01.754148 [Byte1]: 46
2757 11:45:01.758467
2758 11:45:01.758572 Set Vref, RX VrefLevel [Byte0]: 47
2759 11:45:01.762197 [Byte1]: 47
2760 11:45:01.766330
2761 11:45:01.769382 Set Vref, RX VrefLevel [Byte0]: 48
2762 11:45:01.769482 [Byte1]: 48
2763 11:45:01.774410
2764 11:45:01.774490 Set Vref, RX VrefLevel [Byte0]: 49
2765 11:45:01.777957 [Byte1]: 49
2766 11:45:01.783121
2767 11:45:01.783201 Set Vref, RX VrefLevel [Byte0]: 50
2768 11:45:01.785863 [Byte1]: 50
2769 11:45:01.790145
2770 11:45:01.790228 Set Vref, RX VrefLevel [Byte0]: 51
2771 11:45:01.793679 [Byte1]: 51
2772 11:45:01.797988
2773 11:45:01.798068 Set Vref, RX VrefLevel [Byte0]: 52
2774 11:45:01.801758 [Byte1]: 52
2775 11:45:01.806552
2776 11:45:01.806632 Set Vref, RX VrefLevel [Byte0]: 53
2777 11:45:01.809237 [Byte1]: 53
2778 11:45:01.813873
2779 11:45:01.813953 Set Vref, RX VrefLevel [Byte0]: 54
2780 11:45:01.817322 [Byte1]: 54
2781 11:45:01.822061
2782 11:45:01.822153 Set Vref, RX VrefLevel [Byte0]: 55
2783 11:45:01.825143 [Byte1]: 55
2784 11:45:01.830070
2785 11:45:01.830181 Set Vref, RX VrefLevel [Byte0]: 56
2786 11:45:01.833437 [Byte1]: 56
2787 11:45:01.838191
2788 11:45:01.838275 Set Vref, RX VrefLevel [Byte0]: 57
2789 11:45:01.841230 [Byte1]: 57
2790 11:45:01.845754
2791 11:45:01.845839 Set Vref, RX VrefLevel [Byte0]: 58
2792 11:45:01.849255 [Byte1]: 58
2793 11:45:01.853444
2794 11:45:01.853529 Set Vref, RX VrefLevel [Byte0]: 59
2795 11:45:01.857246 [Byte1]: 59
2796 11:45:01.861517
2797 11:45:01.861603 Set Vref, RX VrefLevel [Byte0]: 60
2798 11:45:01.864791 [Byte1]: 60
2799 11:45:01.869309
2800 11:45:01.869399 Set Vref, RX VrefLevel [Byte0]: 61
2801 11:45:01.872772 [Byte1]: 61
2802 11:45:01.877398
2803 11:45:01.877481 Set Vref, RX VrefLevel [Byte0]: 62
2804 11:45:01.880752 [Byte1]: 62
2805 11:45:01.885480
2806 11:45:01.885564 Set Vref, RX VrefLevel [Byte0]: 63
2807 11:45:01.888974 [Byte1]: 63
2808 11:45:01.893551
2809 11:45:01.893635 Set Vref, RX VrefLevel [Byte0]: 64
2810 11:45:01.896728 [Byte1]: 64
2811 11:45:01.901114
2812 11:45:01.901198 Set Vref, RX VrefLevel [Byte0]: 65
2813 11:45:01.904425 [Byte1]: 65
2814 11:45:01.909069
2815 11:45:01.909150 Set Vref, RX VrefLevel [Byte0]: 66
2816 11:45:01.912234 [Byte1]: 66
2817 11:45:01.917052
2818 11:45:01.917135 Set Vref, RX VrefLevel [Byte0]: 67
2819 11:45:01.920689 [Byte1]: 67
2820 11:45:01.925037
2821 11:45:01.925121 Final RX Vref Byte 0 = 53 to rank0
2822 11:45:01.928288 Final RX Vref Byte 1 = 51 to rank0
2823 11:45:01.931737 Final RX Vref Byte 0 = 53 to rank1
2824 11:45:01.934761 Final RX Vref Byte 1 = 51 to rank1==
2825 11:45:01.938164 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 11:45:01.941566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 11:45:01.944962 ==
2828 11:45:01.945044 DQS Delay:
2829 11:45:01.945109 DQS0 = 0, DQS1 = 0
2830 11:45:01.948382 DQM Delay:
2831 11:45:01.948463 DQM0 = 114, DQM1 = 105
2832 11:45:01.951733 DQ Delay:
2833 11:45:01.955148 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2834 11:45:01.958301 DQ4 =114, DQ5 =110, DQ6 =120, DQ7 =122
2835 11:45:01.961930 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2836 11:45:01.964936 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
2837 11:45:01.965018
2838 11:45:01.965082
2839 11:45:01.972033 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2840 11:45:01.974875 CH0 RK0: MR19=303, MR18=FDEC
2841 11:45:01.981708 CH0_RK0: MR19=0x303, MR18=0xFDEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2842 11:45:01.981789
2843 11:45:01.985552 ----->DramcWriteLeveling(PI) begin...
2844 11:45:01.985666 ==
2845 11:45:01.988519 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 11:45:01.991943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 11:45:01.992098 ==
2848 11:45:01.995482 Write leveling (Byte 0): 33 => 33
2849 11:45:01.998799 Write leveling (Byte 1): 29 => 29
2850 11:45:02.002032 DramcWriteLeveling(PI) end<-----
2851 11:45:02.002149
2852 11:45:02.002269 ==
2853 11:45:02.005604 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 11:45:02.008918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 11:45:02.011818 ==
2856 11:45:02.011899 [Gating] SW mode calibration
2857 11:45:02.019307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 11:45:02.025266 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 11:45:02.028719 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2860 11:45:02.035911 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2861 11:45:02.039103 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 11:45:02.042352 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 11:45:02.045792 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 11:45:02.052185 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 11:45:02.055688 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2866 11:45:02.059017 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2867 11:45:02.065954 1 0 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 1) (0 0)
2868 11:45:02.069227 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2869 11:45:02.072640 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 11:45:02.079223 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 11:45:02.082374 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 11:45:02.085843 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 11:45:02.092813 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2874 11:45:02.096849 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2875 11:45:02.099253 1 1 0 | B1->B0 | 3131 3e3e | 0 0 | (1 1) (0 0)
2876 11:45:02.106103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 11:45:02.109286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 11:45:02.112745 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 11:45:02.116067 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 11:45:02.122704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 11:45:02.126094 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 11:45:02.129732 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 11:45:02.135887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 11:45:02.139378 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 11:45:02.142801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:45:02.149660 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:45:02.153014 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:45:02.156313 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:45:02.162819 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:45:02.166404 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:45:02.169931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 11:45:02.173497 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 11:45:02.179608 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 11:45:02.183107 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 11:45:02.186454 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 11:45:02.193440 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:45:02.196340 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:45:02.200361 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 11:45:02.206446 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 11:45:02.206530 Total UI for P1: 0, mck2ui 16
2901 11:45:02.213562 best dqsien dly found for B0: ( 1, 3, 28)
2902 11:45:02.216749 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 11:45:02.220125 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 11:45:02.223661 Total UI for P1: 0, mck2ui 16
2905 11:45:02.226926 best dqsien dly found for B1: ( 1, 4, 2)
2906 11:45:02.229917 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2907 11:45:02.233186 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2908 11:45:02.233270
2909 11:45:02.236666 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2910 11:45:02.243510 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2911 11:45:02.243595 [Gating] SW calibration Done
2912 11:45:02.243680 ==
2913 11:45:02.246614 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 11:45:02.253685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 11:45:02.253771 ==
2916 11:45:02.253857 RX Vref Scan: 0
2917 11:45:02.253938
2918 11:45:02.256812 RX Vref 0 -> 0, step: 1
2919 11:45:02.256896
2920 11:45:02.260083 RX Delay -40 -> 252, step: 8
2921 11:45:02.263543 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2922 11:45:02.266662 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2923 11:45:02.269927 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2924 11:45:02.273502 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2925 11:45:02.280967 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 11:45:02.283956 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2927 11:45:02.286872 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2928 11:45:02.290599 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 11:45:02.293440 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2930 11:45:02.296793 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2931 11:45:02.303724 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 11:45:02.306949 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2933 11:45:02.310333 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2934 11:45:02.313675 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2935 11:45:02.320576 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2936 11:45:02.324250 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2937 11:45:02.324328 ==
2938 11:45:02.327069 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 11:45:02.330497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 11:45:02.330590 ==
2941 11:45:02.330672 DQS Delay:
2942 11:45:02.334033 DQS0 = 0, DQS1 = 0
2943 11:45:02.334104 DQM Delay:
2944 11:45:02.336900 DQM0 = 116, DQM1 = 106
2945 11:45:02.336970 DQ Delay:
2946 11:45:02.340426 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2947 11:45:02.343886 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2948 11:45:02.347159 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2949 11:45:02.350700 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2950 11:45:02.350790
2951 11:45:02.350854
2952 11:45:02.353922 ==
2953 11:45:02.353996 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 11:45:02.360657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 11:45:02.360734 ==
2956 11:45:02.360796
2957 11:45:02.360854
2958 11:45:02.364166 TX Vref Scan disable
2959 11:45:02.364244 == TX Byte 0 ==
2960 11:45:02.367344 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2961 11:45:02.373931 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2962 11:45:02.374007 == TX Byte 1 ==
2963 11:45:02.377203 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2964 11:45:02.384447 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2965 11:45:02.384527 ==
2966 11:45:02.387811 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 11:45:02.390774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 11:45:02.390907 ==
2969 11:45:02.402953 TX Vref=22, minBit 0, minWin=25, winSum=421
2970 11:45:02.405996 TX Vref=24, minBit 1, minWin=25, winSum=426
2971 11:45:02.409482 TX Vref=26, minBit 1, minWin=25, winSum=429
2972 11:45:02.412947 TX Vref=28, minBit 3, minWin=26, winSum=433
2973 11:45:02.416215 TX Vref=30, minBit 2, minWin=26, winSum=431
2974 11:45:02.419502 TX Vref=32, minBit 3, minWin=26, winSum=431
2975 11:45:02.425872 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 28
2976 11:45:02.425950
2977 11:45:02.429563 Final TX Range 1 Vref 28
2978 11:45:02.429638
2979 11:45:02.429698 ==
2980 11:45:02.433195 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 11:45:02.436082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 11:45:02.436153 ==
2983 11:45:02.436216
2984 11:45:02.436275
2985 11:45:02.439598 TX Vref Scan disable
2986 11:45:02.443271 == TX Byte 0 ==
2987 11:45:02.446424 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2988 11:45:02.449464 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2989 11:45:02.452883 == TX Byte 1 ==
2990 11:45:02.456198 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2991 11:45:02.460032 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2992 11:45:02.460117
2993 11:45:02.463063 [DATLAT]
2994 11:45:02.463163 Freq=1200, CH0 RK1
2995 11:45:02.463262
2996 11:45:02.466599 DATLAT Default: 0xd
2997 11:45:02.466683 0, 0xFFFF, sum = 0
2998 11:45:02.470070 1, 0xFFFF, sum = 0
2999 11:45:02.470156 2, 0xFFFF, sum = 0
3000 11:45:02.473237 3, 0xFFFF, sum = 0
3001 11:45:02.473322 4, 0xFFFF, sum = 0
3002 11:45:02.476446 5, 0xFFFF, sum = 0
3003 11:45:02.476531 6, 0xFFFF, sum = 0
3004 11:45:02.479613 7, 0xFFFF, sum = 0
3005 11:45:02.479713 8, 0xFFFF, sum = 0
3006 11:45:02.483408 9, 0xFFFF, sum = 0
3007 11:45:02.483493 10, 0xFFFF, sum = 0
3008 11:45:02.486800 11, 0xFFFF, sum = 0
3009 11:45:02.486941 12, 0x0, sum = 1
3010 11:45:02.490264 13, 0x0, sum = 2
3011 11:45:02.490376 14, 0x0, sum = 3
3012 11:45:02.493633 15, 0x0, sum = 4
3013 11:45:02.493719 best_step = 13
3014 11:45:02.493819
3015 11:45:02.493914 ==
3016 11:45:02.496678 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 11:45:02.503565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 11:45:02.503653 ==
3019 11:45:02.503737 RX Vref Scan: 0
3020 11:45:02.503818
3021 11:45:02.506903 RX Vref 0 -> 0, step: 1
3022 11:45:02.506987
3023 11:45:02.509914 RX Delay -21 -> 252, step: 4
3024 11:45:02.513190 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3025 11:45:02.516542 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3026 11:45:02.520327 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3027 11:45:02.527004 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3028 11:45:02.530187 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 11:45:02.533849 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3030 11:45:02.536872 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3031 11:45:02.540148 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3032 11:45:02.543634 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3033 11:45:02.550496 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3034 11:45:02.553539 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3035 11:45:02.556892 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 11:45:02.560300 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 11:45:02.563418 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3038 11:45:02.570365 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3039 11:45:02.573879 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3040 11:45:02.573993 ==
3041 11:45:02.577531 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 11:45:02.580442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 11:45:02.580527 ==
3044 11:45:02.584055 DQS Delay:
3045 11:45:02.584156 DQS0 = 0, DQS1 = 0
3046 11:45:02.584240 DQM Delay:
3047 11:45:02.587717 DQM0 = 113, DQM1 = 104
3048 11:45:02.587802 DQ Delay:
3049 11:45:02.590660 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3050 11:45:02.594002 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3051 11:45:02.597787 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3052 11:45:02.600492 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3053 11:45:02.600577
3054 11:45:02.604447
3055 11:45:02.610985 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3056 11:45:02.614308 CH0 RK1: MR19=403, MR18=1F2
3057 11:45:02.617797 CH0_RK1: MR19=0x403, MR18=0x1F2, DQSOSC=409, MR23=63, INC=39, DEC=26
3058 11:45:02.621182 [RxdqsGatingPostProcess] freq 1200
3059 11:45:02.627509 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 11:45:02.630647 best DQS0 dly(2T, 0.5T) = (0, 12)
3061 11:45:02.634090 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 11:45:02.637191 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3063 11:45:02.641021 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 11:45:02.644283 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 11:45:02.648066 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 11:45:02.650896 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 11:45:02.653974 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 11:45:02.654059 Pre-setting of DQS Precalculation
3069 11:45:02.661346 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 11:45:02.661437 ==
3071 11:45:02.664626 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 11:45:02.668109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 11:45:02.668199 ==
3074 11:45:02.674301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 11:45:02.681273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 11:45:02.688561 [CA 0] Center 38 (8~68) winsize 61
3077 11:45:02.691583 [CA 1] Center 38 (8~68) winsize 61
3078 11:45:02.694700 [CA 2] Center 35 (5~65) winsize 61
3079 11:45:02.698285 [CA 3] Center 34 (4~65) winsize 62
3080 11:45:02.701643 [CA 4] Center 34 (4~65) winsize 62
3081 11:45:02.704890 [CA 5] Center 34 (4~64) winsize 61
3082 11:45:02.705004
3083 11:45:02.708501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 11:45:02.708610
3085 11:45:02.711569 [CATrainingPosCal] consider 1 rank data
3086 11:45:02.715191 u2DelayCellTimex100 = 270/100 ps
3087 11:45:02.718818 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 11:45:02.721930 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3089 11:45:02.725085 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3090 11:45:02.731970 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 11:45:02.734922 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3092 11:45:02.738905 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3093 11:45:02.738986
3094 11:45:02.742084 CA PerBit enable=1, Macro0, CA PI delay=34
3095 11:45:02.742165
3096 11:45:02.745255 [CBTSetCACLKResult] CA Dly = 34
3097 11:45:02.745337 CS Dly: 6 (0~37)
3098 11:45:02.745401 ==
3099 11:45:02.748852 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 11:45:02.755215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 11:45:02.755297 ==
3102 11:45:02.758811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 11:45:02.765293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 11:45:02.773813 [CA 0] Center 38 (8~68) winsize 61
3105 11:45:02.777375 [CA 1] Center 38 (8~68) winsize 61
3106 11:45:02.780465 [CA 2] Center 34 (4~65) winsize 62
3107 11:45:02.783772 [CA 3] Center 34 (4~65) winsize 62
3108 11:45:02.787752 [CA 4] Center 34 (4~65) winsize 62
3109 11:45:02.790280 [CA 5] Center 34 (4~64) winsize 61
3110 11:45:02.790374
3111 11:45:02.793596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 11:45:02.793689
3113 11:45:02.796886 [CATrainingPosCal] consider 2 rank data
3114 11:45:02.800741 u2DelayCellTimex100 = 270/100 ps
3115 11:45:02.803764 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3116 11:45:02.807017 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3117 11:45:02.813986 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3118 11:45:02.817043 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3119 11:45:02.820386 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3120 11:45:02.824040 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3121 11:45:02.824176
3122 11:45:02.827141 CA PerBit enable=1, Macro0, CA PI delay=34
3123 11:45:02.827211
3124 11:45:02.830326 [CBTSetCACLKResult] CA Dly = 34
3125 11:45:02.830401 CS Dly: 7 (0~40)
3126 11:45:02.830462
3127 11:45:02.834187 ----->DramcWriteLeveling(PI) begin...
3128 11:45:02.834253 ==
3129 11:45:02.837736 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:45:02.843893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:45:02.843961 ==
3132 11:45:02.847876 Write leveling (Byte 0): 25 => 25
3133 11:45:02.850926 Write leveling (Byte 1): 29 => 29
3134 11:45:02.850998 DramcWriteLeveling(PI) end<-----
3135 11:45:02.851059
3136 11:45:02.854092 ==
3137 11:45:02.857689 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 11:45:02.861189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 11:45:02.861286 ==
3140 11:45:02.864404 [Gating] SW mode calibration
3141 11:45:02.870640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 11:45:02.874092 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 11:45:02.881152 0 15 0 | B1->B0 | 2727 2323 | 0 1 | (0 0) (1 1)
3144 11:45:02.884324 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3145 11:45:02.887817 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3146 11:45:02.895053 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 11:45:02.898068 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 11:45:02.901088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 11:45:02.904587 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 11:45:02.911061 0 15 28 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
3151 11:45:02.914765 1 0 0 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (1 0)
3152 11:45:02.917878 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 11:45:02.924617 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 11:45:02.928306 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 11:45:02.931285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 11:45:02.937720 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 11:45:02.941672 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 11:45:02.944794 1 0 28 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
3159 11:45:02.951424 1 1 0 | B1->B0 | 4444 3434 | 0 0 | (0 0) (0 0)
3160 11:45:02.954790 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 11:45:02.958284 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 11:45:02.961318 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 11:45:02.968174 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 11:45:02.971515 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 11:45:02.974960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 11:45:02.981932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 11:45:02.984898 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3168 11:45:02.988603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:45:02.995135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:45:02.998398 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:45:03.001820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:45:03.005735 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:45:03.012214 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:45:03.015669 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:45:03.018986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 11:45:03.025538 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 11:45:03.029257 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 11:45:03.032581 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 11:45:03.039150 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 11:45:03.042137 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:45:03.045408 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:45:03.052638 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3183 11:45:03.055766 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 11:45:03.059096 Total UI for P1: 0, mck2ui 16
3185 11:45:03.062609 best dqsien dly found for B0: ( 1, 3, 28)
3186 11:45:03.066025 Total UI for P1: 0, mck2ui 16
3187 11:45:03.069500 best dqsien dly found for B1: ( 1, 3, 30)
3188 11:45:03.072204 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3189 11:45:03.075805 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3190 11:45:03.075885
3191 11:45:03.079051 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3192 11:45:03.082669 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3193 11:45:03.085896 [Gating] SW calibration Done
3194 11:45:03.085985 ==
3195 11:45:03.089317 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 11:45:03.092772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 11:45:03.092842 ==
3198 11:45:03.095861 RX Vref Scan: 0
3199 11:45:03.095942
3200 11:45:03.096004 RX Vref 0 -> 0, step: 1
3201 11:45:03.099281
3202 11:45:03.099387 RX Delay -40 -> 252, step: 8
3203 11:45:03.105712 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 11:45:03.109483 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 11:45:03.112595 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 11:45:03.115901 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3207 11:45:03.119336 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 11:45:03.122840 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 11:45:03.129154 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3210 11:45:03.132953 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3211 11:45:03.136046 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 11:45:03.139272 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 11:45:03.143321 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3214 11:45:03.149571 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 11:45:03.152668 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3216 11:45:03.156244 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3217 11:45:03.159610 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 11:45:03.163415 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 11:45:03.163495 ==
3220 11:45:03.166897 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 11:45:03.172963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 11:45:03.173046 ==
3223 11:45:03.173114 DQS Delay:
3224 11:45:03.176445 DQS0 = 0, DQS1 = 0
3225 11:45:03.176564 DQM Delay:
3226 11:45:03.176670 DQM0 = 115, DQM1 = 108
3227 11:45:03.179981 DQ Delay:
3228 11:45:03.183729 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3229 11:45:03.186787 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3230 11:45:03.190303 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3231 11:45:03.193239 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3232 11:45:03.193321
3233 11:45:03.193387
3234 11:45:03.193477 ==
3235 11:45:03.196477 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 11:45:03.199980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 11:45:03.200063 ==
3238 11:45:03.200127
3239 11:45:03.203323
3240 11:45:03.203404 TX Vref Scan disable
3241 11:45:03.206554 == TX Byte 0 ==
3242 11:45:03.210266 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 11:45:03.213971 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 11:45:03.217235 == TX Byte 1 ==
3245 11:45:03.220282 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3246 11:45:03.223688 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3247 11:45:03.223764 ==
3248 11:45:03.227432 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 11:45:03.230344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 11:45:03.233863 ==
3251 11:45:03.244229 TX Vref=22, minBit 3, minWin=24, winSum=410
3252 11:45:03.247394 TX Vref=24, minBit 1, minWin=25, winSum=419
3253 11:45:03.250659 TX Vref=26, minBit 1, minWin=25, winSum=421
3254 11:45:03.254285 TX Vref=28, minBit 0, minWin=26, winSum=426
3255 11:45:03.257396 TX Vref=30, minBit 3, minWin=26, winSum=432
3256 11:45:03.260908 TX Vref=32, minBit 3, minWin=26, winSum=430
3257 11:45:03.267503 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
3258 11:45:03.267587
3259 11:45:03.271011 Final TX Range 1 Vref 30
3260 11:45:03.271119
3261 11:45:03.271211 ==
3262 11:45:03.274357 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 11:45:03.277600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 11:45:03.277682 ==
3265 11:45:03.277746
3266 11:45:03.277805
3267 11:45:03.281151 TX Vref Scan disable
3268 11:45:03.284638 == TX Byte 0 ==
3269 11:45:03.288072 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3270 11:45:03.291296 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3271 11:45:03.294747 == TX Byte 1 ==
3272 11:45:03.297640 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3273 11:45:03.301487 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3274 11:45:03.301568
3275 11:45:03.304814 [DATLAT]
3276 11:45:03.304895 Freq=1200, CH1 RK0
3277 11:45:03.304959
3278 11:45:03.307666 DATLAT Default: 0xd
3279 11:45:03.307748 0, 0xFFFF, sum = 0
3280 11:45:03.311005 1, 0xFFFF, sum = 0
3281 11:45:03.311088 2, 0xFFFF, sum = 0
3282 11:45:03.314574 3, 0xFFFF, sum = 0
3283 11:45:03.314669 4, 0xFFFF, sum = 0
3284 11:45:03.317887 5, 0xFFFF, sum = 0
3285 11:45:03.317971 6, 0xFFFF, sum = 0
3286 11:45:03.321360 7, 0xFFFF, sum = 0
3287 11:45:03.321444 8, 0xFFFF, sum = 0
3288 11:45:03.324729 9, 0xFFFF, sum = 0
3289 11:45:03.324811 10, 0xFFFF, sum = 0
3290 11:45:03.328683 11, 0xFFFF, sum = 0
3291 11:45:03.328765 12, 0x0, sum = 1
3292 11:45:03.331383 13, 0x0, sum = 2
3293 11:45:03.331466 14, 0x0, sum = 3
3294 11:45:03.334851 15, 0x0, sum = 4
3295 11:45:03.334942 best_step = 13
3296 11:45:03.335007
3297 11:45:03.335066 ==
3298 11:45:03.338331 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 11:45:03.341448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 11:45:03.344623 ==
3301 11:45:03.344705 RX Vref Scan: 1
3302 11:45:03.344768
3303 11:45:03.348130 Set Vref Range= 32 -> 127
3304 11:45:03.348210
3305 11:45:03.351966 RX Vref 32 -> 127, step: 1
3306 11:45:03.352048
3307 11:45:03.352111 RX Delay -21 -> 252, step: 4
3308 11:45:03.352172
3309 11:45:03.354869 Set Vref, RX VrefLevel [Byte0]: 32
3310 11:45:03.358391 [Byte1]: 32
3311 11:45:03.362480
3312 11:45:03.362559 Set Vref, RX VrefLevel [Byte0]: 33
3313 11:45:03.365737 [Byte1]: 33
3314 11:45:03.370800
3315 11:45:03.370912 Set Vref, RX VrefLevel [Byte0]: 34
3316 11:45:03.373382 [Byte1]: 34
3317 11:45:03.377973
3318 11:45:03.378052 Set Vref, RX VrefLevel [Byte0]: 35
3319 11:45:03.381593 [Byte1]: 35
3320 11:45:03.385782
3321 11:45:03.385860 Set Vref, RX VrefLevel [Byte0]: 36
3322 11:45:03.389597 [Byte1]: 36
3323 11:45:03.394126
3324 11:45:03.394204 Set Vref, RX VrefLevel [Byte0]: 37
3325 11:45:03.397188 [Byte1]: 37
3326 11:45:03.402007
3327 11:45:03.402086 Set Vref, RX VrefLevel [Byte0]: 38
3328 11:45:03.404914 [Byte1]: 38
3329 11:45:03.410456
3330 11:45:03.410534 Set Vref, RX VrefLevel [Byte0]: 39
3331 11:45:03.413344 [Byte1]: 39
3332 11:45:03.417707
3333 11:45:03.417786 Set Vref, RX VrefLevel [Byte0]: 40
3334 11:45:03.420969 [Byte1]: 40
3335 11:45:03.425950
3336 11:45:03.426028 Set Vref, RX VrefLevel [Byte0]: 41
3337 11:45:03.428941 [Byte1]: 41
3338 11:45:03.433371
3339 11:45:03.433476 Set Vref, RX VrefLevel [Byte0]: 42
3340 11:45:03.436949 [Byte1]: 42
3341 11:45:03.441517
3342 11:45:03.441595 Set Vref, RX VrefLevel [Byte0]: 43
3343 11:45:03.445119 [Byte1]: 43
3344 11:45:03.449631
3345 11:45:03.449700 Set Vref, RX VrefLevel [Byte0]: 44
3346 11:45:03.453028 [Byte1]: 44
3347 11:45:03.457361
3348 11:45:03.457428 Set Vref, RX VrefLevel [Byte0]: 45
3349 11:45:03.461091 [Byte1]: 45
3350 11:45:03.465157
3351 11:45:03.465234 Set Vref, RX VrefLevel [Byte0]: 46
3352 11:45:03.468349 [Byte1]: 46
3353 11:45:03.473144
3354 11:45:03.473223 Set Vref, RX VrefLevel [Byte0]: 47
3355 11:45:03.476537 [Byte1]: 47
3356 11:45:03.481071
3357 11:45:03.481149 Set Vref, RX VrefLevel [Byte0]: 48
3358 11:45:03.484271 [Byte1]: 48
3359 11:45:03.488992
3360 11:45:03.492052 Set Vref, RX VrefLevel [Byte0]: 49
3361 11:45:03.492131 [Byte1]: 49
3362 11:45:03.497203
3363 11:45:03.497314 Set Vref, RX VrefLevel [Byte0]: 50
3364 11:45:03.500144 [Byte1]: 50
3365 11:45:03.504739
3366 11:45:03.504837 Set Vref, RX VrefLevel [Byte0]: 51
3367 11:45:03.508027 [Byte1]: 51
3368 11:45:03.512648
3369 11:45:03.512725 Set Vref, RX VrefLevel [Byte0]: 52
3370 11:45:03.515899 [Byte1]: 52
3371 11:45:03.520597
3372 11:45:03.520706 Set Vref, RX VrefLevel [Byte0]: 53
3373 11:45:03.523587 [Byte1]: 53
3374 11:45:03.528604
3375 11:45:03.528724 Set Vref, RX VrefLevel [Byte0]: 54
3376 11:45:03.531801 [Byte1]: 54
3377 11:45:03.536125
3378 11:45:03.536226 Set Vref, RX VrefLevel [Byte0]: 55
3379 11:45:03.539523 [Byte1]: 55
3380 11:45:03.544394
3381 11:45:03.544479 Set Vref, RX VrefLevel [Byte0]: 56
3382 11:45:03.547799 [Byte1]: 56
3383 11:45:03.552365
3384 11:45:03.552444 Set Vref, RX VrefLevel [Byte0]: 57
3385 11:45:03.558769 [Byte1]: 57
3386 11:45:03.558912
3387 11:45:03.562249 Set Vref, RX VrefLevel [Byte0]: 58
3388 11:45:03.565914 [Byte1]: 58
3389 11:45:03.566020
3390 11:45:03.568929 Set Vref, RX VrefLevel [Byte0]: 59
3391 11:45:03.572155 [Byte1]: 59
3392 11:45:03.575882
3393 11:45:03.575960 Set Vref, RX VrefLevel [Byte0]: 60
3394 11:45:03.579495 [Byte1]: 60
3395 11:45:03.584262
3396 11:45:03.584342 Set Vref, RX VrefLevel [Byte0]: 61
3397 11:45:03.587339 [Byte1]: 61
3398 11:45:03.592160
3399 11:45:03.592240 Set Vref, RX VrefLevel [Byte0]: 62
3400 11:45:03.595741 [Byte1]: 62
3401 11:45:03.599894
3402 11:45:03.599969 Set Vref, RX VrefLevel [Byte0]: 63
3403 11:45:03.603214 [Byte1]: 63
3404 11:45:03.607824
3405 11:45:03.607896 Set Vref, RX VrefLevel [Byte0]: 64
3406 11:45:03.611451 [Byte1]: 64
3407 11:45:03.615755
3408 11:45:03.615858 Set Vref, RX VrefLevel [Byte0]: 65
3409 11:45:03.619321 [Byte1]: 65
3410 11:45:03.623708
3411 11:45:03.623780 Set Vref, RX VrefLevel [Byte0]: 66
3412 11:45:03.626997 [Byte1]: 66
3413 11:45:03.631699
3414 11:45:03.631770 Set Vref, RX VrefLevel [Byte0]: 67
3415 11:45:03.634676 [Byte1]: 67
3416 11:45:03.639886
3417 11:45:03.639964 Final RX Vref Byte 0 = 56 to rank0
3418 11:45:03.642822 Final RX Vref Byte 1 = 54 to rank0
3419 11:45:03.645975 Final RX Vref Byte 0 = 56 to rank1
3420 11:45:03.649379 Final RX Vref Byte 1 = 54 to rank1==
3421 11:45:03.652952 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 11:45:03.656412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 11:45:03.659820 ==
3424 11:45:03.659912 DQS Delay:
3425 11:45:03.659976 DQS0 = 0, DQS1 = 0
3426 11:45:03.662718 DQM Delay:
3427 11:45:03.662798 DQM0 = 116, DQM1 = 109
3428 11:45:03.666106 DQ Delay:
3429 11:45:03.669309 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3430 11:45:03.673246 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3431 11:45:03.676251 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3432 11:45:03.679365 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =114
3433 11:45:03.679462
3434 11:45:03.679527
3435 11:45:03.686172 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3436 11:45:03.689650 CH1 RK0: MR19=303, MR18=FFE4
3437 11:45:03.696839 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3438 11:45:03.696968
3439 11:45:03.700224 ----->DramcWriteLeveling(PI) begin...
3440 11:45:03.700309 ==
3441 11:45:03.703325 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 11:45:03.707014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 11:45:03.707095 ==
3444 11:45:03.709610 Write leveling (Byte 0): 27 => 27
3445 11:45:03.713059 Write leveling (Byte 1): 28 => 28
3446 11:45:03.716791 DramcWriteLeveling(PI) end<-----
3447 11:45:03.716882
3448 11:45:03.716948 ==
3449 11:45:03.719810 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 11:45:03.723138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 11:45:03.726570 ==
3452 11:45:03.726699 [Gating] SW mode calibration
3453 11:45:03.733497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 11:45:03.739919 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 11:45:03.743451 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3456 11:45:03.750619 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 11:45:03.753439 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3458 11:45:03.757063 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3459 11:45:03.760556 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 11:45:03.767396 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3461 11:45:03.770622 0 15 24 | B1->B0 | 3434 2a2a | 0 1 | (0 0) (1 0)
3462 11:45:03.773998 0 15 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
3463 11:45:03.780721 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 11:45:03.784124 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 11:45:03.787764 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 11:45:03.793875 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3467 11:45:03.797224 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 11:45:03.800579 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3469 11:45:03.804359 1 0 24 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (0 0)
3470 11:45:03.810622 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3471 11:45:03.813951 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 11:45:03.817569 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 11:45:03.824454 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 11:45:03.827517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 11:45:03.831123 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 11:45:03.837745 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3477 11:45:03.840969 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 11:45:03.844096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3479 11:45:03.851431 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:45:03.854224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:45:03.857742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:45:03.861132 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:45:03.868369 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:45:03.871553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 11:45:03.874474 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 11:45:03.881657 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:45:03.884813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:45:03.888390 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:45:03.894479 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:45:03.898099 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:45:03.901188 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:45:03.908033 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3493 11:45:03.911152 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3494 11:45:03.914979 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3495 11:45:03.918187 Total UI for P1: 0, mck2ui 16
3496 11:45:03.921615 best dqsien dly found for B0: ( 1, 3, 22)
3497 11:45:03.928383 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 11:45:03.928465 Total UI for P1: 0, mck2ui 16
3499 11:45:03.931050 best dqsien dly found for B1: ( 1, 3, 28)
3500 11:45:03.937818 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3501 11:45:03.941415 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3502 11:45:03.941496
3503 11:45:03.944647 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3504 11:45:03.948364 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3505 11:45:03.951365 [Gating] SW calibration Done
3506 11:45:03.951446 ==
3507 11:45:03.954629 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 11:45:03.958434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 11:45:03.958515 ==
3510 11:45:03.961661 RX Vref Scan: 0
3511 11:45:03.961742
3512 11:45:03.961805 RX Vref 0 -> 0, step: 1
3513 11:45:03.961865
3514 11:45:03.965112 RX Delay -40 -> 252, step: 8
3515 11:45:03.968050 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3516 11:45:03.971289 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3517 11:45:03.977753 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3518 11:45:03.981675 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3519 11:45:03.984861 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3520 11:45:03.988000 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3521 11:45:03.991531 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3522 11:45:03.997839 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3523 11:45:04.001163 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3524 11:45:04.004981 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3525 11:45:04.008102 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3526 11:45:04.011642 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3527 11:45:04.017760 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3528 11:45:04.021124 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3529 11:45:04.024835 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3530 11:45:04.027824 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3531 11:45:04.027932 ==
3532 11:45:04.031351 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 11:45:04.037957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 11:45:04.038066 ==
3535 11:45:04.038158 DQS Delay:
3536 11:45:04.038245 DQS0 = 0, DQS1 = 0
3537 11:45:04.041754 DQM Delay:
3538 11:45:04.041835 DQM0 = 113, DQM1 = 110
3539 11:45:04.044526 DQ Delay:
3540 11:45:04.048034 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3541 11:45:04.051461 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3542 11:45:04.055009 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3543 11:45:04.058113 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3544 11:45:04.058193
3545 11:45:04.058255
3546 11:45:04.058313 ==
3547 11:45:04.061597 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 11:45:04.065201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 11:45:04.065282 ==
3550 11:45:04.065346
3551 11:45:04.065404
3552 11:45:04.068207 TX Vref Scan disable
3553 11:45:04.071388 == TX Byte 0 ==
3554 11:45:04.074876 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3555 11:45:04.078363 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3556 11:45:04.081518 == TX Byte 1 ==
3557 11:45:04.085111 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3558 11:45:04.088061 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3559 11:45:04.088141 ==
3560 11:45:04.091772 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 11:45:04.098193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 11:45:04.098274 ==
3563 11:45:04.108689 TX Vref=22, minBit 1, minWin=25, winSum=418
3564 11:45:04.111651 TX Vref=24, minBit 0, minWin=26, winSum=426
3565 11:45:04.114836 TX Vref=26, minBit 0, minWin=26, winSum=428
3566 11:45:04.118180 TX Vref=28, minBit 1, minWin=26, winSum=430
3567 11:45:04.121518 TX Vref=30, minBit 4, minWin=26, winSum=436
3568 11:45:04.125042 TX Vref=32, minBit 2, minWin=26, winSum=433
3569 11:45:04.131573 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 30
3570 11:45:04.131658
3571 11:45:04.135062 Final TX Range 1 Vref 30
3572 11:45:04.135175
3573 11:45:04.135267 ==
3574 11:45:04.138608 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 11:45:04.141867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 11:45:04.141976 ==
3577 11:45:04.142069
3578 11:45:04.145316
3579 11:45:04.145398 TX Vref Scan disable
3580 11:45:04.148153 == TX Byte 0 ==
3581 11:45:04.151663 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 11:45:04.155139 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 11:45:04.158445 == TX Byte 1 ==
3584 11:45:04.161863 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 11:45:04.165172 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 11:45:04.165274
3587 11:45:04.168400 [DATLAT]
3588 11:45:04.168498 Freq=1200, CH1 RK1
3589 11:45:04.168588
3590 11:45:04.171224 DATLAT Default: 0xd
3591 11:45:04.171320 0, 0xFFFF, sum = 0
3592 11:45:04.174716 1, 0xFFFF, sum = 0
3593 11:45:04.174827 2, 0xFFFF, sum = 0
3594 11:45:04.178101 3, 0xFFFF, sum = 0
3595 11:45:04.178175 4, 0xFFFF, sum = 0
3596 11:45:04.181271 5, 0xFFFF, sum = 0
3597 11:45:04.181344 6, 0xFFFF, sum = 0
3598 11:45:04.184552 7, 0xFFFF, sum = 0
3599 11:45:04.188440 8, 0xFFFF, sum = 0
3600 11:45:04.188517 9, 0xFFFF, sum = 0
3601 11:45:04.191391 10, 0xFFFF, sum = 0
3602 11:45:04.191500 11, 0xFFFF, sum = 0
3603 11:45:04.194646 12, 0x0, sum = 1
3604 11:45:04.194722 13, 0x0, sum = 2
3605 11:45:04.198625 14, 0x0, sum = 3
3606 11:45:04.198697 15, 0x0, sum = 4
3607 11:45:04.198758 best_step = 13
3608 11:45:04.198815
3609 11:45:04.201484 ==
3610 11:45:04.201566 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 11:45:04.208555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 11:45:04.208638 ==
3613 11:45:04.208703 RX Vref Scan: 0
3614 11:45:04.208763
3615 11:45:04.212126 RX Vref 0 -> 0, step: 1
3616 11:45:04.212209
3617 11:45:04.214870 RX Delay -21 -> 252, step: 4
3618 11:45:04.218047 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3619 11:45:04.224558 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3620 11:45:04.227929 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3621 11:45:04.230977 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3622 11:45:04.234704 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3623 11:45:04.238074 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3624 11:45:04.241597 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3625 11:45:04.247926 iDelay=191, Bit 7, Center 108 (43 ~ 174) 132
3626 11:45:04.251541 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3627 11:45:04.254816 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3628 11:45:04.258184 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3629 11:45:04.261871 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3630 11:45:04.268043 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3631 11:45:04.271552 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3632 11:45:04.274644 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3633 11:45:04.277981 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3634 11:45:04.278057 ==
3635 11:45:04.281514 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 11:45:04.288016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 11:45:04.288102 ==
3638 11:45:04.288166 DQS Delay:
3639 11:45:04.288227 DQS0 = 0, DQS1 = 0
3640 11:45:04.291439 DQM Delay:
3641 11:45:04.291515 DQM0 = 113, DQM1 = 110
3642 11:45:04.295213 DQ Delay:
3643 11:45:04.297978 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3644 11:45:04.301829 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =108
3645 11:45:04.304591 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3646 11:45:04.308473 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =120
3647 11:45:04.308549
3648 11:45:04.308612
3649 11:45:04.318227 [DQSOSCAuto] RK1, (LSB)MR18= 0xf901, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3650 11:45:04.318340 CH1 RK1: MR19=304, MR18=F901
3651 11:45:04.325024 CH1_RK1: MR19=0x304, MR18=0xF901, DQSOSC=409, MR23=63, INC=39, DEC=26
3652 11:45:04.328280 [RxdqsGatingPostProcess] freq 1200
3653 11:45:04.334903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 11:45:04.338033 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 11:45:04.341618 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 11:45:04.345116 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 11:45:04.347992 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 11:45:04.348075 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 11:45:04.351513 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 11:45:04.354823 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 11:45:04.357983 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 11:45:04.361704 Pre-setting of DQS Precalculation
3663 11:45:04.368068 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 11:45:04.375083 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 11:45:04.381345 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 11:45:04.381429
3667 11:45:04.381494
3668 11:45:04.385328 [Calibration Summary] 2400 Mbps
3669 11:45:04.385412 CH 0, Rank 0
3670 11:45:04.388415 SW Impedance : PASS
3671 11:45:04.391279 DUTY Scan : NO K
3672 11:45:04.391362 ZQ Calibration : PASS
3673 11:45:04.394683 Jitter Meter : NO K
3674 11:45:04.397973 CBT Training : PASS
3675 11:45:04.398056 Write leveling : PASS
3676 11:45:04.401934 RX DQS gating : PASS
3677 11:45:04.402018 RX DQ/DQS(RDDQC) : PASS
3678 11:45:04.404756 TX DQ/DQS : PASS
3679 11:45:04.408179 RX DATLAT : PASS
3680 11:45:04.408262 RX DQ/DQS(Engine): PASS
3681 11:45:04.411715 TX OE : NO K
3682 11:45:04.411813 All Pass.
3683 11:45:04.411907
3684 11:45:04.414849 CH 0, Rank 1
3685 11:45:04.414941 SW Impedance : PASS
3686 11:45:04.418035 DUTY Scan : NO K
3687 11:45:04.421790 ZQ Calibration : PASS
3688 11:45:04.421876 Jitter Meter : NO K
3689 11:45:04.424703 CBT Training : PASS
3690 11:45:04.428087 Write leveling : PASS
3691 11:45:04.428173 RX DQS gating : PASS
3692 11:45:04.431322 RX DQ/DQS(RDDQC) : PASS
3693 11:45:04.435251 TX DQ/DQS : PASS
3694 11:45:04.435337 RX DATLAT : PASS
3695 11:45:04.437961 RX DQ/DQS(Engine): PASS
3696 11:45:04.441534 TX OE : NO K
3697 11:45:04.441620 All Pass.
3698 11:45:04.441707
3699 11:45:04.441788 CH 1, Rank 0
3700 11:45:04.444906 SW Impedance : PASS
3701 11:45:04.448307 DUTY Scan : NO K
3702 11:45:04.448386 ZQ Calibration : PASS
3703 11:45:04.451696 Jitter Meter : NO K
3704 11:45:04.451782 CBT Training : PASS
3705 11:45:04.455092 Write leveling : PASS
3706 11:45:04.458147 RX DQS gating : PASS
3707 11:45:04.458233 RX DQ/DQS(RDDQC) : PASS
3708 11:45:04.461449 TX DQ/DQS : PASS
3709 11:45:04.464997 RX DATLAT : PASS
3710 11:45:04.465083 RX DQ/DQS(Engine): PASS
3711 11:45:04.468093 TX OE : NO K
3712 11:45:04.468179 All Pass.
3713 11:45:04.468265
3714 11:45:04.471885 CH 1, Rank 1
3715 11:45:04.471971 SW Impedance : PASS
3716 11:45:04.474769 DUTY Scan : NO K
3717 11:45:04.478099 ZQ Calibration : PASS
3718 11:45:04.478185 Jitter Meter : NO K
3719 11:45:04.481322 CBT Training : PASS
3720 11:45:04.485184 Write leveling : PASS
3721 11:45:04.485270 RX DQS gating : PASS
3722 11:45:04.488473 RX DQ/DQS(RDDQC) : PASS
3723 11:45:04.488559 TX DQ/DQS : PASS
3724 11:45:04.492055 RX DATLAT : PASS
3725 11:45:04.494909 RX DQ/DQS(Engine): PASS
3726 11:45:04.494995 TX OE : NO K
3727 11:45:04.498523 All Pass.
3728 11:45:04.498609
3729 11:45:04.498695 DramC Write-DBI off
3730 11:45:04.501775 PER_BANK_REFRESH: Hybrid Mode
3731 11:45:04.505226 TX_TRACKING: ON
3732 11:45:04.511806 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 11:45:04.515130 [FAST_K] Save calibration result to emmc
3734 11:45:04.519018 dramc_set_vcore_voltage set vcore to 650000
3735 11:45:04.521906 Read voltage for 600, 5
3736 11:45:04.521992 Vio18 = 0
3737 11:45:04.525055 Vcore = 650000
3738 11:45:04.525141 Vdram = 0
3739 11:45:04.525227 Vddq = 0
3740 11:45:04.528508 Vmddr = 0
3741 11:45:04.531561 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 11:45:04.538355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 11:45:04.538442 MEM_TYPE=3, freq_sel=19
3744 11:45:04.541989 sv_algorithm_assistance_LP4_1600
3745 11:45:04.548488 ============ PULL DRAM RESETB DOWN ============
3746 11:45:04.551796 ========== PULL DRAM RESETB DOWN end =========
3747 11:45:04.555129 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 11:45:04.558425 ===================================
3749 11:45:04.562365 LPDDR4 DRAM CONFIGURATION
3750 11:45:04.565313 ===================================
3751 11:45:04.565397 EX_ROW_EN[0] = 0x0
3752 11:45:04.568661 EX_ROW_EN[1] = 0x0
3753 11:45:04.568769 LP4Y_EN = 0x0
3754 11:45:04.571838 WORK_FSP = 0x0
3755 11:45:04.575301 WL = 0x2
3756 11:45:04.575384 RL = 0x2
3757 11:45:04.579156 BL = 0x2
3758 11:45:04.579264 RPST = 0x0
3759 11:45:04.582193 RD_PRE = 0x0
3760 11:45:04.582277 WR_PRE = 0x1
3761 11:45:04.585748 WR_PST = 0x0
3762 11:45:04.585831 DBI_WR = 0x0
3763 11:45:04.588699 DBI_RD = 0x0
3764 11:45:04.588783 OTF = 0x1
3765 11:45:04.591971 ===================================
3766 11:45:04.595010 ===================================
3767 11:45:04.598600 ANA top config
3768 11:45:04.602429 ===================================
3769 11:45:04.602513 DLL_ASYNC_EN = 0
3770 11:45:04.605057 ALL_SLAVE_EN = 1
3771 11:45:04.608306 NEW_RANK_MODE = 1
3772 11:45:04.611788 DLL_IDLE_MODE = 1
3773 11:45:04.611871 LP45_APHY_COMB_EN = 1
3774 11:45:04.615136 TX_ODT_DIS = 1
3775 11:45:04.618676 NEW_8X_MODE = 1
3776 11:45:04.621856 ===================================
3777 11:45:04.625077 ===================================
3778 11:45:04.628646 data_rate = 1200
3779 11:45:04.632129 CKR = 1
3780 11:45:04.635113 DQ_P2S_RATIO = 8
3781 11:45:04.638781 ===================================
3782 11:45:04.638902 CA_P2S_RATIO = 8
3783 11:45:04.641608 DQ_CA_OPEN = 0
3784 11:45:04.645307 DQ_SEMI_OPEN = 0
3785 11:45:04.648763 CA_SEMI_OPEN = 0
3786 11:45:04.651872 CA_FULL_RATE = 0
3787 11:45:04.651956 DQ_CKDIV4_EN = 1
3788 11:45:04.655594 CA_CKDIV4_EN = 1
3789 11:45:04.658638 CA_PREDIV_EN = 0
3790 11:45:04.661505 PH8_DLY = 0
3791 11:45:04.665198 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 11:45:04.668552 DQ_AAMCK_DIV = 4
3793 11:45:04.668633 CA_AAMCK_DIV = 4
3794 11:45:04.671997 CA_ADMCK_DIV = 4
3795 11:45:04.675241 DQ_TRACK_CA_EN = 0
3796 11:45:04.678285 CA_PICK = 600
3797 11:45:04.681577 CA_MCKIO = 600
3798 11:45:04.685113 MCKIO_SEMI = 0
3799 11:45:04.688951 PLL_FREQ = 2288
3800 11:45:04.689032 DQ_UI_PI_RATIO = 32
3801 11:45:04.691863 CA_UI_PI_RATIO = 0
3802 11:45:04.695080 ===================================
3803 11:45:04.698738 ===================================
3804 11:45:04.701763 memory_type:LPDDR4
3805 11:45:04.705129 GP_NUM : 10
3806 11:45:04.705210 SRAM_EN : 1
3807 11:45:04.708333 MD32_EN : 0
3808 11:45:04.711767 ===================================
3809 11:45:04.711848 [ANA_INIT] >>>>>>>>>>>>>>
3810 11:45:04.715278 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 11:45:04.718342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 11:45:04.721984 ===================================
3813 11:45:04.725180 data_rate = 1200,PCW = 0X5800
3814 11:45:04.728636 ===================================
3815 11:45:04.732206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 11:45:04.738233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 11:45:04.741724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 11:45:04.748714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 11:45:04.751793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 11:45:04.755078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 11:45:04.758285 [ANA_INIT] flow start
3822 11:45:04.758384 [ANA_INIT] PLL >>>>>>>>
3823 11:45:04.761629 [ANA_INIT] PLL <<<<<<<<
3824 11:45:04.764916 [ANA_INIT] MIDPI >>>>>>>>
3825 11:45:04.764997 [ANA_INIT] MIDPI <<<<<<<<
3826 11:45:04.768446 [ANA_INIT] DLL >>>>>>>>
3827 11:45:04.771842 [ANA_INIT] flow end
3828 11:45:04.775324 ============ LP4 DIFF to SE enter ============
3829 11:45:04.778987 ============ LP4 DIFF to SE exit ============
3830 11:45:04.782232 [ANA_INIT] <<<<<<<<<<<<<
3831 11:45:04.785332 [Flow] Enable top DCM control >>>>>
3832 11:45:04.788638 [Flow] Enable top DCM control <<<<<
3833 11:45:04.791601 Enable DLL master slave shuffle
3834 11:45:04.795204 ==============================================================
3835 11:45:04.798490 Gating Mode config
3836 11:45:04.801880 ==============================================================
3837 11:45:04.805285 Config description:
3838 11:45:04.815540 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 11:45:04.821665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 11:45:04.825109 SELPH_MODE 0: By rank 1: By Phase
3841 11:45:04.831739 ==============================================================
3842 11:45:04.835120 GAT_TRACK_EN = 1
3843 11:45:04.838562 RX_GATING_MODE = 2
3844 11:45:04.841799 RX_GATING_TRACK_MODE = 2
3845 11:45:04.845101 SELPH_MODE = 1
3846 11:45:04.848682 PICG_EARLY_EN = 1
3847 11:45:04.848784 VALID_LAT_VALUE = 1
3848 11:45:04.855280 ==============================================================
3849 11:45:04.858700 Enter into Gating configuration >>>>
3850 11:45:04.861526 Exit from Gating configuration <<<<
3851 11:45:04.865083 Enter into DVFS_PRE_config >>>>>
3852 11:45:04.875446 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 11:45:04.878578 Exit from DVFS_PRE_config <<<<<
3854 11:45:04.881971 Enter into PICG configuration >>>>
3855 11:45:04.885569 Exit from PICG configuration <<<<
3856 11:45:04.888591 [RX_INPUT] configuration >>>>>
3857 11:45:04.891830 [RX_INPUT] configuration <<<<<
3858 11:45:04.895003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 11:45:04.901709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 11:45:04.908525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 11:45:04.915078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 11:45:04.921716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 11:45:04.925238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 11:45:04.931594 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 11:45:04.935177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 11:45:04.938618 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 11:45:04.941848 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 11:45:04.945099 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 11:45:04.951913 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 11:45:04.955113 ===================================
3871 11:45:04.958634 LPDDR4 DRAM CONFIGURATION
3872 11:45:04.958735 ===================================
3873 11:45:04.962218 EX_ROW_EN[0] = 0x0
3874 11:45:04.965346 EX_ROW_EN[1] = 0x0
3875 11:45:04.965422 LP4Y_EN = 0x0
3876 11:45:04.968843 WORK_FSP = 0x0
3877 11:45:04.968918 WL = 0x2
3878 11:45:04.971961 RL = 0x2
3879 11:45:04.972058 BL = 0x2
3880 11:45:04.975321 RPST = 0x0
3881 11:45:04.975409 RD_PRE = 0x0
3882 11:45:04.978752 WR_PRE = 0x1
3883 11:45:04.978827 WR_PST = 0x0
3884 11:45:04.981977 DBI_WR = 0x0
3885 11:45:04.982058 DBI_RD = 0x0
3886 11:45:04.985420 OTF = 0x1
3887 11:45:04.988581 ===================================
3888 11:45:04.991858 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 11:45:04.995519 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 11:45:05.002287 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 11:45:05.005624 ===================================
3892 11:45:05.005704 LPDDR4 DRAM CONFIGURATION
3893 11:45:05.009146 ===================================
3894 11:45:05.012110 EX_ROW_EN[0] = 0x10
3895 11:45:05.012177 EX_ROW_EN[1] = 0x0
3896 11:45:05.015536 LP4Y_EN = 0x0
3897 11:45:05.018610 WORK_FSP = 0x0
3898 11:45:05.018708 WL = 0x2
3899 11:45:05.022499 RL = 0x2
3900 11:45:05.022612 BL = 0x2
3901 11:45:05.025624 RPST = 0x0
3902 11:45:05.025721 RD_PRE = 0x0
3903 11:45:05.029105 WR_PRE = 0x1
3904 11:45:05.029204 WR_PST = 0x0
3905 11:45:05.032392 DBI_WR = 0x0
3906 11:45:05.032464 DBI_RD = 0x0
3907 11:45:05.035582 OTF = 0x1
3908 11:45:05.039052 ===================================
3909 11:45:05.042381 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 11:45:05.047739 nWR fixed to 30
3911 11:45:05.051386 [ModeRegInit_LP4] CH0 RK0
3912 11:45:05.051464 [ModeRegInit_LP4] CH0 RK1
3913 11:45:05.054780 [ModeRegInit_LP4] CH1 RK0
3914 11:45:05.057510 [ModeRegInit_LP4] CH1 RK1
3915 11:45:05.057597 match AC timing 17
3916 11:45:05.064515 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 11:45:05.068067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 11:45:05.071037 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 11:45:05.077666 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 11:45:05.081436 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 11:45:05.081561 ==
3922 11:45:05.084925 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 11:45:05.087992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 11:45:05.088097 ==
3925 11:45:05.094711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 11:45:05.101645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3927 11:45:05.104621 [CA 0] Center 36 (6~66) winsize 61
3928 11:45:05.108089 [CA 1] Center 36 (6~66) winsize 61
3929 11:45:05.111513 [CA 2] Center 34 (4~65) winsize 62
3930 11:45:05.114541 [CA 3] Center 34 (4~65) winsize 62
3931 11:45:05.118516 [CA 4] Center 33 (3~64) winsize 62
3932 11:45:05.121161 [CA 5] Center 33 (3~64) winsize 62
3933 11:45:05.121244
3934 11:45:05.124614 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3935 11:45:05.124696
3936 11:45:05.128277 [CATrainingPosCal] consider 1 rank data
3937 11:45:05.131290 u2DelayCellTimex100 = 270/100 ps
3938 11:45:05.134982 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3939 11:45:05.138036 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3940 11:45:05.141500 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 11:45:05.144606 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 11:45:05.148175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 11:45:05.151724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 11:45:05.151802
3945 11:45:05.157731 CA PerBit enable=1, Macro0, CA PI delay=33
3946 11:45:05.157823
3947 11:45:05.157886 [CBTSetCACLKResult] CA Dly = 33
3948 11:45:05.161130 CS Dly: 4 (0~35)
3949 11:45:05.161221 ==
3950 11:45:05.164695 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 11:45:05.168500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 11:45:05.168579 ==
3953 11:45:05.174571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 11:45:05.181181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 11:45:05.184568 [CA 0] Center 36 (6~66) winsize 61
3956 11:45:05.188217 [CA 1] Center 36 (6~66) winsize 61
3957 11:45:05.191403 [CA 2] Center 34 (4~65) winsize 62
3958 11:45:05.194706 [CA 3] Center 34 (4~65) winsize 62
3959 11:45:05.198046 [CA 4] Center 33 (3~64) winsize 62
3960 11:45:05.201044 [CA 5] Center 33 (3~64) winsize 62
3961 11:45:05.201118
3962 11:45:05.204484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 11:45:05.204576
3964 11:45:05.207832 [CATrainingPosCal] consider 2 rank data
3965 11:45:05.211312 u2DelayCellTimex100 = 270/100 ps
3966 11:45:05.214732 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 11:45:05.218242 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 11:45:05.221504 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 11:45:05.225189 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 11:45:05.227840 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 11:45:05.231557 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 11:45:05.231633
3973 11:45:05.234997 CA PerBit enable=1, Macro0, CA PI delay=33
3974 11:45:05.237846
3975 11:45:05.237934 [CBTSetCACLKResult] CA Dly = 33
3976 11:45:05.241730 CS Dly: 5 (0~37)
3977 11:45:05.241808
3978 11:45:05.244555 ----->DramcWriteLeveling(PI) begin...
3979 11:45:05.244641 ==
3980 11:45:05.248217 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 11:45:05.251652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 11:45:05.251723 ==
3983 11:45:05.254557 Write leveling (Byte 0): 35 => 35
3984 11:45:05.257875 Write leveling (Byte 1): 29 => 29
3985 11:45:05.261757 DramcWriteLeveling(PI) end<-----
3986 11:45:05.261833
3987 11:45:05.261898 ==
3988 11:45:05.265011 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 11:45:05.267940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 11:45:05.268026 ==
3991 11:45:05.272017 [Gating] SW mode calibration
3992 11:45:05.277942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 11:45:05.284539 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 11:45:05.288046 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 11:45:05.295004 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 11:45:05.298293 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 11:45:05.301424 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 11:45:05.308088 0 9 16 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (0 0)
3999 11:45:05.311363 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4000 11:45:05.315514 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 11:45:05.318560 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 11:45:05.325267 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 11:45:05.328136 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 11:45:05.331601 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 11:45:05.338241 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4006 11:45:05.341930 0 10 16 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
4007 11:45:05.345039 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 11:45:05.351839 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 11:45:05.354986 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 11:45:05.358259 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 11:45:05.365010 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 11:45:05.368302 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 11:45:05.372256 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 11:45:05.378246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4015 11:45:05.381762 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:45:05.385035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:45:05.388589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:45:05.395288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:45:05.398773 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:45:05.401612 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:45:05.408482 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:45:05.411767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:45:05.415123 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:45:05.422245 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:45:05.425230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:45:05.428462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:45:05.435325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:45:05.438776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:45:05.442193 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4030 11:45:05.448468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4031 11:45:05.448585 Total UI for P1: 0, mck2ui 16
4032 11:45:05.455635 best dqsien dly found for B0: ( 0, 13, 14)
4033 11:45:05.459158 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 11:45:05.462156 Total UI for P1: 0, mck2ui 16
4035 11:45:05.465201 best dqsien dly found for B1: ( 0, 13, 14)
4036 11:45:05.469005 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4037 11:45:05.472167 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4038 11:45:05.472254
4039 11:45:05.475375 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4040 11:45:05.478953 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4041 11:45:05.482197 [Gating] SW calibration Done
4042 11:45:05.482286 ==
4043 11:45:05.485242 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 11:45:05.488864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 11:45:05.488940 ==
4046 11:45:05.492094 RX Vref Scan: 0
4047 11:45:05.492170
4048 11:45:05.495246 RX Vref 0 -> 0, step: 1
4049 11:45:05.495320
4050 11:45:05.495385 RX Delay -230 -> 252, step: 16
4051 11:45:05.502462 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4052 11:45:05.505355 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4053 11:45:05.509085 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4054 11:45:05.512353 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4055 11:45:05.515634 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4056 11:45:05.521952 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4057 11:45:05.525833 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 11:45:05.528976 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 11:45:05.532204 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4060 11:45:05.538771 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4061 11:45:05.542075 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 11:45:05.545402 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4063 11:45:05.548975 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4064 11:45:05.555558 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4065 11:45:05.558776 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4066 11:45:05.562221 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4067 11:45:05.562296 ==
4068 11:45:05.565638 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 11:45:05.569365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 11:45:05.569434 ==
4071 11:45:05.572283 DQS Delay:
4072 11:45:05.572354 DQS0 = 0, DQS1 = 0
4073 11:45:05.575286 DQM Delay:
4074 11:45:05.575358 DQM0 = 41, DQM1 = 32
4075 11:45:05.575418 DQ Delay:
4076 11:45:05.578560 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4077 11:45:05.582309 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4078 11:45:05.585206 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4079 11:45:05.588629 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4080 11:45:05.588702
4081 11:45:05.588764
4082 11:45:05.592397 ==
4083 11:45:05.592477 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 11:45:05.598674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 11:45:05.598782 ==
4086 11:45:05.598895
4087 11:45:05.598970
4088 11:45:05.602446 TX Vref Scan disable
4089 11:45:05.602530 == TX Byte 0 ==
4090 11:45:05.605382 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4091 11:45:05.612071 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4092 11:45:05.612151 == TX Byte 1 ==
4093 11:45:05.618957 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4094 11:45:05.621928 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4095 11:45:05.622008 ==
4096 11:45:05.625515 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 11:45:05.628678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 11:45:05.628758 ==
4099 11:45:05.628821
4100 11:45:05.628891
4101 11:45:05.632295 TX Vref Scan disable
4102 11:45:05.635416 == TX Byte 0 ==
4103 11:45:05.638978 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4104 11:45:05.642391 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4105 11:45:05.645755 == TX Byte 1 ==
4106 11:45:05.648697 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4107 11:45:05.652334 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4108 11:45:05.652414
4109 11:45:05.655650 [DATLAT]
4110 11:45:05.655729 Freq=600, CH0 RK0
4111 11:45:05.655792
4112 11:45:05.659178 DATLAT Default: 0x9
4113 11:45:05.659295 0, 0xFFFF, sum = 0
4114 11:45:05.662379 1, 0xFFFF, sum = 0
4115 11:45:05.662459 2, 0xFFFF, sum = 0
4116 11:45:05.665380 3, 0xFFFF, sum = 0
4117 11:45:05.665486 4, 0xFFFF, sum = 0
4118 11:45:05.668836 5, 0xFFFF, sum = 0
4119 11:45:05.668936 6, 0xFFFF, sum = 0
4120 11:45:05.672481 7, 0xFFFF, sum = 0
4121 11:45:05.672552 8, 0x0, sum = 1
4122 11:45:05.675694 9, 0x0, sum = 2
4123 11:45:05.675765 10, 0x0, sum = 3
4124 11:45:05.679300 11, 0x0, sum = 4
4125 11:45:05.679370 best_step = 9
4126 11:45:05.679428
4127 11:45:05.679483 ==
4128 11:45:05.682232 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 11:45:05.685740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 11:45:05.685811 ==
4131 11:45:05.689336 RX Vref Scan: 1
4132 11:45:05.689399
4133 11:45:05.692523 RX Vref 0 -> 0, step: 1
4134 11:45:05.692598
4135 11:45:05.692657 RX Delay -195 -> 252, step: 8
4136 11:45:05.692714
4137 11:45:05.695984 Set Vref, RX VrefLevel [Byte0]: 53
4138 11:45:05.699023 [Byte1]: 51
4139 11:45:05.703396
4140 11:45:05.703461 Final RX Vref Byte 0 = 53 to rank0
4141 11:45:05.706791 Final RX Vref Byte 1 = 51 to rank0
4142 11:45:05.710530 Final RX Vref Byte 0 = 53 to rank1
4143 11:45:05.714089 Final RX Vref Byte 1 = 51 to rank1==
4144 11:45:05.716929 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 11:45:05.720276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 11:45:05.723633 ==
4147 11:45:05.723713 DQS Delay:
4148 11:45:05.723775 DQS0 = 0, DQS1 = 0
4149 11:45:05.727012 DQM Delay:
4150 11:45:05.727078 DQM0 = 42, DQM1 = 33
4151 11:45:05.730342 DQ Delay:
4152 11:45:05.733761 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4153 11:45:05.733827 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4154 11:45:05.736992 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4155 11:45:05.741028 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4156 11:45:05.741098
4157 11:45:05.744213
4158 11:45:05.750396 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4159 11:45:05.753943 CH0 RK0: MR19=808, MR18=4120
4160 11:45:05.760362 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4161 11:45:05.760470
4162 11:45:05.763823 ----->DramcWriteLeveling(PI) begin...
4163 11:45:05.763906 ==
4164 11:45:05.767231 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 11:45:05.770725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 11:45:05.770809 ==
4167 11:45:05.773748 Write leveling (Byte 0): 32 => 32
4168 11:45:05.777335 Write leveling (Byte 1): 32 => 32
4169 11:45:05.780267 DramcWriteLeveling(PI) end<-----
4170 11:45:05.780347
4171 11:45:05.780409 ==
4172 11:45:05.783512 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 11:45:05.786823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 11:45:05.786957 ==
4175 11:45:05.790293 [Gating] SW mode calibration
4176 11:45:05.797138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 11:45:05.803911 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 11:45:05.807169 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 11:45:05.810427 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 11:45:05.817022 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 11:45:05.820606 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4182 11:45:05.824058 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
4183 11:45:05.830727 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 11:45:05.833920 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 11:45:05.837324 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 11:45:05.840857 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 11:45:05.847301 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 11:45:05.850697 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 11:45:05.854003 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4190 11:45:05.861341 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4191 11:45:05.864623 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 11:45:05.867753 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 11:45:05.874446 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 11:45:05.878036 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 11:45:05.881382 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 11:45:05.887373 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 11:45:05.890971 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4198 11:45:05.893988 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4199 11:45:05.901104 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:45:05.904201 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:45:05.907713 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:45:05.910663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:45:05.917593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:45:05.921030 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 11:45:05.924749 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 11:45:05.930842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:45:05.933906 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:45:05.937335 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:45:05.944271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:45:05.947686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:45:05.951037 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:45:05.957651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:45:05.961030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4214 11:45:05.963932 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4215 11:45:05.967533 Total UI for P1: 0, mck2ui 16
4216 11:45:05.970791 best dqsien dly found for B0: ( 0, 13, 12)
4217 11:45:05.977552 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 11:45:05.977640 Total UI for P1: 0, mck2ui 16
4219 11:45:05.984058 best dqsien dly found for B1: ( 0, 13, 16)
4220 11:45:05.987479 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4221 11:45:05.991035 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4222 11:45:05.991117
4223 11:45:05.994330 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4224 11:45:05.997721 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4225 11:45:06.000913 [Gating] SW calibration Done
4226 11:45:06.000993 ==
4227 11:45:06.004216 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 11:45:06.007778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:45:06.007860 ==
4230 11:45:06.010789 RX Vref Scan: 0
4231 11:45:06.010926
4232 11:45:06.010990 RX Vref 0 -> 0, step: 1
4233 11:45:06.011049
4234 11:45:06.014549 RX Delay -230 -> 252, step: 16
4235 11:45:06.017784 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4236 11:45:06.024088 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4237 11:45:06.027476 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4238 11:45:06.031022 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4239 11:45:06.034354 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4240 11:45:06.040762 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4241 11:45:06.044311 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4242 11:45:06.047890 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4243 11:45:06.051259 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4244 11:45:06.054177 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4245 11:45:06.061393 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4246 11:45:06.064259 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4247 11:45:06.067697 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4248 11:45:06.071391 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4249 11:45:06.078151 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4250 11:45:06.081472 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4251 11:45:06.081546 ==
4252 11:45:06.084432 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 11:45:06.087730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 11:45:06.087807 ==
4255 11:45:06.087870 DQS Delay:
4256 11:45:06.091161 DQS0 = 0, DQS1 = 0
4257 11:45:06.091270 DQM Delay:
4258 11:45:06.094650 DQM0 = 40, DQM1 = 31
4259 11:45:06.094757 DQ Delay:
4260 11:45:06.097953 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4261 11:45:06.101351 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4262 11:45:06.104807 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4263 11:45:06.107764 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4264 11:45:06.107836
4265 11:45:06.107897
4266 11:45:06.107953 ==
4267 11:45:06.111220 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:45:06.114492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:45:06.117988 ==
4270 11:45:06.118061
4271 11:45:06.118120
4272 11:45:06.118178 TX Vref Scan disable
4273 11:45:06.121380 == TX Byte 0 ==
4274 11:45:06.124579 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4275 11:45:06.127953 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4276 11:45:06.131402 == TX Byte 1 ==
4277 11:45:06.134752 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4278 11:45:06.138239 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4279 11:45:06.138312 ==
4280 11:45:06.141266 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 11:45:06.148190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 11:45:06.148263 ==
4283 11:45:06.148324
4284 11:45:06.148380
4285 11:45:06.148438 TX Vref Scan disable
4286 11:45:06.152579 == TX Byte 0 ==
4287 11:45:06.156161 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4288 11:45:06.159834 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4289 11:45:06.162552 == TX Byte 1 ==
4290 11:45:06.165808 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4291 11:45:06.172520 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4292 11:45:06.172597
4293 11:45:06.172658 [DATLAT]
4294 11:45:06.172715 Freq=600, CH0 RK1
4295 11:45:06.172774
4296 11:45:06.175719 DATLAT Default: 0x9
4297 11:45:06.175796 0, 0xFFFF, sum = 0
4298 11:45:06.179206 1, 0xFFFF, sum = 0
4299 11:45:06.179278 2, 0xFFFF, sum = 0
4300 11:45:06.182621 3, 0xFFFF, sum = 0
4301 11:45:06.182694 4, 0xFFFF, sum = 0
4302 11:45:06.186051 5, 0xFFFF, sum = 0
4303 11:45:06.189540 6, 0xFFFF, sum = 0
4304 11:45:06.189607 7, 0xFFFF, sum = 0
4305 11:45:06.189667 8, 0x0, sum = 1
4306 11:45:06.192669 9, 0x0, sum = 2
4307 11:45:06.192746 10, 0x0, sum = 3
4308 11:45:06.195951 11, 0x0, sum = 4
4309 11:45:06.196024 best_step = 9
4310 11:45:06.196083
4311 11:45:06.196138 ==
4312 11:45:06.199105 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 11:45:06.205606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 11:45:06.205703 ==
4315 11:45:06.205780 RX Vref Scan: 0
4316 11:45:06.205841
4317 11:45:06.209752 RX Vref 0 -> 0, step: 1
4318 11:45:06.209831
4319 11:45:06.212297 RX Delay -195 -> 252, step: 8
4320 11:45:06.215674 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4321 11:45:06.222440 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4322 11:45:06.226087 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4323 11:45:06.229003 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4324 11:45:06.232510 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4325 11:45:06.235615 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4326 11:45:06.243216 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4327 11:45:06.246279 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4328 11:45:06.249079 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4329 11:45:06.252910 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4330 11:45:06.259444 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4331 11:45:06.262682 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4332 11:45:06.266009 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4333 11:45:06.269146 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4334 11:45:06.272696 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4335 11:45:06.279528 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4336 11:45:06.279609 ==
4337 11:45:06.282527 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 11:45:06.285975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:45:06.286043 ==
4340 11:45:06.286107 DQS Delay:
4341 11:45:06.289202 DQS0 = 0, DQS1 = 0
4342 11:45:06.289268 DQM Delay:
4343 11:45:06.292603 DQM0 = 39, DQM1 = 32
4344 11:45:06.292677 DQ Delay:
4345 11:45:06.296165 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4346 11:45:06.299363 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4347 11:45:06.302944 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4348 11:45:06.306187 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4349 11:45:06.306260
4350 11:45:06.306320
4351 11:45:06.312642 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4352 11:45:06.316314 CH0 RK1: MR19=808, MR18=4E30
4353 11:45:06.322808 CH0_RK1: MR19=0x808, MR18=0x4E30, DQSOSC=395, MR23=63, INC=168, DEC=112
4354 11:45:06.325907 [RxdqsGatingPostProcess] freq 600
4355 11:45:06.332837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4356 11:45:06.336072 Pre-setting of DQS Precalculation
4357 11:45:06.339073 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4358 11:45:06.339154 ==
4359 11:45:06.342450 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 11:45:06.346067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 11:45:06.346148 ==
4362 11:45:06.352849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 11:45:06.359790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4364 11:45:06.362831 [CA 0] Center 35 (5~65) winsize 61
4365 11:45:06.366373 [CA 1] Center 35 (5~66) winsize 62
4366 11:45:06.369735 [CA 2] Center 34 (4~64) winsize 61
4367 11:45:06.372982 [CA 3] Center 33 (3~64) winsize 62
4368 11:45:06.376325 [CA 4] Center 34 (3~65) winsize 63
4369 11:45:06.379451 [CA 5] Center 33 (3~64) winsize 62
4370 11:45:06.379530
4371 11:45:06.382676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4372 11:45:06.382756
4373 11:45:06.386375 [CATrainingPosCal] consider 1 rank data
4374 11:45:06.389410 u2DelayCellTimex100 = 270/100 ps
4375 11:45:06.392765 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4376 11:45:06.396105 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4377 11:45:06.399419 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4378 11:45:06.402589 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 11:45:06.406457 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4380 11:45:06.409910 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4381 11:45:06.409982
4382 11:45:06.416093 CA PerBit enable=1, Macro0, CA PI delay=33
4383 11:45:06.416166
4384 11:45:06.419522 [CBTSetCACLKResult] CA Dly = 33
4385 11:45:06.419595 CS Dly: 3 (0~34)
4386 11:45:06.419656 ==
4387 11:45:06.423384 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 11:45:06.426266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 11:45:06.426337 ==
4390 11:45:06.433561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 11:45:06.439584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4392 11:45:06.443457 [CA 0] Center 35 (5~66) winsize 62
4393 11:45:06.446359 [CA 1] Center 35 (5~66) winsize 62
4394 11:45:06.449987 [CA 2] Center 34 (3~65) winsize 63
4395 11:45:06.452746 [CA 3] Center 34 (3~65) winsize 63
4396 11:45:06.456254 [CA 4] Center 34 (3~65) winsize 63
4397 11:45:06.459896 [CA 5] Center 33 (3~64) winsize 62
4398 11:45:06.459965
4399 11:45:06.463061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4400 11:45:06.463135
4401 11:45:06.466350 [CATrainingPosCal] consider 2 rank data
4402 11:45:06.469451 u2DelayCellTimex100 = 270/100 ps
4403 11:45:06.472979 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4404 11:45:06.476129 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 11:45:06.479704 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4406 11:45:06.483166 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 11:45:06.486579 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4408 11:45:06.489356 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 11:45:06.489428
4410 11:45:06.496097 CA PerBit enable=1, Macro0, CA PI delay=33
4411 11:45:06.496175
4412 11:45:06.496240 [CBTSetCACLKResult] CA Dly = 33
4413 11:45:06.499597 CS Dly: 4 (0~36)
4414 11:45:06.499669
4415 11:45:06.503081 ----->DramcWriteLeveling(PI) begin...
4416 11:45:06.503153 ==
4417 11:45:06.506240 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 11:45:06.509998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 11:45:06.510075 ==
4420 11:45:06.513293 Write leveling (Byte 0): 29 => 29
4421 11:45:06.516484 Write leveling (Byte 1): 31 => 31
4422 11:45:06.520015 DramcWriteLeveling(PI) end<-----
4423 11:45:06.520084
4424 11:45:06.520146 ==
4425 11:45:06.523027 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 11:45:06.526327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 11:45:06.529660 ==
4428 11:45:06.529733 [Gating] SW mode calibration
4429 11:45:06.536731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4430 11:45:06.542989 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4431 11:45:06.546659 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 11:45:06.553807 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 11:45:06.556649 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 11:45:06.559997 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 11:45:06.567062 0 9 16 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (1 1)
4436 11:45:06.569941 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 11:45:06.573429 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4438 11:45:06.579686 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 11:45:06.583076 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 11:45:06.586582 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 11:45:06.590090 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 11:45:06.596357 0 10 12 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4443 11:45:06.599989 0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
4444 11:45:06.603034 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 11:45:06.609693 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 11:45:06.613504 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 11:45:06.616755 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 11:45:06.623118 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 11:45:06.626331 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 11:45:06.629874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4451 11:45:06.636813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4452 11:45:06.639756 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:45:06.643082 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:45:06.649991 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 11:45:06.653390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 11:45:06.656315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:45:06.663260 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 11:45:06.666366 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:45:06.669874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:45:06.676485 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:45:06.679951 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:45:06.683296 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:45:06.686462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:45:06.693257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:45:06.696432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:45:06.700017 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4467 11:45:06.703334 Total UI for P1: 0, mck2ui 16
4468 11:45:06.706829 best dqsien dly found for B1: ( 0, 13, 10)
4469 11:45:06.713154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 11:45:06.713235 Total UI for P1: 0, mck2ui 16
4471 11:45:06.719897 best dqsien dly found for B0: ( 0, 13, 14)
4472 11:45:06.723152 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4473 11:45:06.726426 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4474 11:45:06.726507
4475 11:45:06.730261 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4476 11:45:06.733144 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4477 11:45:06.736388 [Gating] SW calibration Done
4478 11:45:06.736468 ==
4479 11:45:06.739867 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 11:45:06.743105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 11:45:06.743187 ==
4482 11:45:06.746742 RX Vref Scan: 0
4483 11:45:06.746838
4484 11:45:06.746926 RX Vref 0 -> 0, step: 1
4485 11:45:06.746987
4486 11:45:06.750116 RX Delay -230 -> 252, step: 16
4487 11:45:06.756608 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4488 11:45:06.759925 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4489 11:45:06.763307 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4490 11:45:06.766392 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4491 11:45:06.769642 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4492 11:45:06.776679 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4493 11:45:06.780046 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4494 11:45:06.783453 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4495 11:45:06.786743 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4496 11:45:06.789867 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4497 11:45:06.796776 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4498 11:45:06.799994 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4499 11:45:06.803425 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4500 11:45:06.806777 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4501 11:45:06.813387 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4502 11:45:06.816578 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4503 11:45:06.816658 ==
4504 11:45:06.820200 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 11:45:06.823334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 11:45:06.823414 ==
4507 11:45:06.826659 DQS Delay:
4508 11:45:06.826739 DQS0 = 0, DQS1 = 0
4509 11:45:06.826802 DQM Delay:
4510 11:45:06.829884 DQM0 = 42, DQM1 = 34
4511 11:45:06.829966 DQ Delay:
4512 11:45:06.833212 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4513 11:45:06.836612 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4514 11:45:06.840142 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4515 11:45:06.843552 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4516 11:45:06.843633
4517 11:45:06.843695
4518 11:45:06.843754 ==
4519 11:45:06.846533 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:45:06.853156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:45:06.853247 ==
4522 11:45:06.853332
4523 11:45:06.853404
4524 11:45:06.853493 TX Vref Scan disable
4525 11:45:06.856897 == TX Byte 0 ==
4526 11:45:06.860175 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 11:45:06.867014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 11:45:06.867097 == TX Byte 1 ==
4529 11:45:06.870365 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4530 11:45:06.873631 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4531 11:45:06.876947 ==
4532 11:45:06.880478 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 11:45:06.883835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 11:45:06.883917 ==
4535 11:45:06.883980
4536 11:45:06.884097
4537 11:45:06.887292 TX Vref Scan disable
4538 11:45:06.887373 == TX Byte 0 ==
4539 11:45:06.893915 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 11:45:06.897070 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 11:45:06.897151 == TX Byte 1 ==
4542 11:45:06.903615 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4543 11:45:06.907040 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4544 11:45:06.907120
4545 11:45:06.907182 [DATLAT]
4546 11:45:06.910159 Freq=600, CH1 RK0
4547 11:45:06.910239
4548 11:45:06.910302 DATLAT Default: 0x9
4549 11:45:06.913692 0, 0xFFFF, sum = 0
4550 11:45:06.913775 1, 0xFFFF, sum = 0
4551 11:45:06.917130 2, 0xFFFF, sum = 0
4552 11:45:06.917211 3, 0xFFFF, sum = 0
4553 11:45:06.920646 4, 0xFFFF, sum = 0
4554 11:45:06.920727 5, 0xFFFF, sum = 0
4555 11:45:06.924043 6, 0xFFFF, sum = 0
4556 11:45:06.924124 7, 0xFFFF, sum = 0
4557 11:45:06.926985 8, 0x0, sum = 1
4558 11:45:06.927093 9, 0x0, sum = 2
4559 11:45:06.930398 10, 0x0, sum = 3
4560 11:45:06.930479 11, 0x0, sum = 4
4561 11:45:06.933659 best_step = 9
4562 11:45:06.933739
4563 11:45:06.933802 ==
4564 11:45:06.937059 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 11:45:06.940681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 11:45:06.940762 ==
4567 11:45:06.943907 RX Vref Scan: 1
4568 11:45:06.943987
4569 11:45:06.944049 RX Vref 0 -> 0, step: 1
4570 11:45:06.944108
4571 11:45:06.947133 RX Delay -195 -> 252, step: 8
4572 11:45:06.947212
4573 11:45:06.950503 Set Vref, RX VrefLevel [Byte0]: 56
4574 11:45:06.953890 [Byte1]: 54
4575 11:45:06.957202
4576 11:45:06.957281 Final RX Vref Byte 0 = 56 to rank0
4577 11:45:06.960681 Final RX Vref Byte 1 = 54 to rank0
4578 11:45:06.963836 Final RX Vref Byte 0 = 56 to rank1
4579 11:45:06.967607 Final RX Vref Byte 1 = 54 to rank1==
4580 11:45:06.970793 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 11:45:06.978302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 11:45:06.978383 ==
4583 11:45:06.978445 DQS Delay:
4584 11:45:06.978504 DQS0 = 0, DQS1 = 0
4585 11:45:06.980901 DQM Delay:
4586 11:45:06.980981 DQM0 = 41, DQM1 = 34
4587 11:45:06.984118 DQ Delay:
4588 11:45:06.987444 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4589 11:45:06.987525 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4590 11:45:06.990746 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =32
4591 11:45:06.997573 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4592 11:45:06.997653
4593 11:45:06.997715
4594 11:45:07.003907 [DQSOSCAuto] RK0, (LSB)MR18= 0x4209, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4595 11:45:07.007360 CH1 RK0: MR19=808, MR18=4209
4596 11:45:07.014143 CH1_RK0: MR19=0x808, MR18=0x4209, DQSOSC=397, MR23=63, INC=166, DEC=110
4597 11:45:07.014224
4598 11:45:07.017363 ----->DramcWriteLeveling(PI) begin...
4599 11:45:07.017445 ==
4600 11:45:07.020725 Dram Type= 6, Freq= 0, CH_1, rank 1
4601 11:45:07.024106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:45:07.024191 ==
4603 11:45:07.027472 Write leveling (Byte 0): 31 => 31
4604 11:45:07.030558 Write leveling (Byte 1): 30 => 30
4605 11:45:07.034528 DramcWriteLeveling(PI) end<-----
4606 11:45:07.034608
4607 11:45:07.034671 ==
4608 11:45:07.037690 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 11:45:07.041059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 11:45:07.041139 ==
4611 11:45:07.043942 [Gating] SW mode calibration
4612 11:45:07.050633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4613 11:45:07.057435 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4614 11:45:07.061283 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 11:45:07.064033 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 11:45:07.071437 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4617 11:45:07.074239 0 9 12 | B1->B0 | 3131 2a2a | 0 0 | (0 1) (0 0)
4618 11:45:07.077720 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4619 11:45:07.084548 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 11:45:07.087940 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 11:45:07.090846 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 11:45:07.094604 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 11:45:07.101628 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 11:45:07.104450 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4625 11:45:07.107830 0 10 12 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
4626 11:45:07.114443 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 11:45:07.118254 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 11:45:07.121031 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 11:45:07.127883 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 11:45:07.131194 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 11:45:07.134628 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 11:45:07.141088 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4633 11:45:07.144608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:45:07.147970 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4635 11:45:07.154363 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:45:07.157752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:45:07.161027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:45:07.167838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:45:07.171482 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 11:45:07.174884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 11:45:07.178241 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 11:45:07.184876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:45:07.188175 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:45:07.191230 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:45:07.198551 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:45:07.201438 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:45:07.204725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:45:07.211653 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4649 11:45:07.214750 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4650 11:45:07.217974 Total UI for P1: 0, mck2ui 16
4651 11:45:07.221279 best dqsien dly found for B0: ( 0, 13, 8)
4652 11:45:07.224744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 11:45:07.228199 Total UI for P1: 0, mck2ui 16
4654 11:45:07.231879 best dqsien dly found for B1: ( 0, 13, 12)
4655 11:45:07.235205 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4656 11:45:07.238225 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4657 11:45:07.238324
4658 11:45:07.241527 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4659 11:45:07.248185 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4660 11:45:07.248261 [Gating] SW calibration Done
4661 11:45:07.248329 ==
4662 11:45:07.251630 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:45:07.257900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:45:07.257979 ==
4665 11:45:07.258042 RX Vref Scan: 0
4666 11:45:07.258100
4667 11:45:07.261749 RX Vref 0 -> 0, step: 1
4668 11:45:07.261849
4669 11:45:07.264804 RX Delay -230 -> 252, step: 16
4670 11:45:07.268028 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4671 11:45:07.271333 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4672 11:45:07.278285 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4673 11:45:07.281580 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4674 11:45:07.284666 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4675 11:45:07.287925 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4676 11:45:07.291622 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4677 11:45:07.297899 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4678 11:45:07.301476 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4679 11:45:07.304733 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4680 11:45:07.308016 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4681 11:45:07.311702 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4682 11:45:07.318242 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4683 11:45:07.321405 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4684 11:45:07.324687 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4685 11:45:07.328668 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4686 11:45:07.331276 ==
4687 11:45:07.334617 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 11:45:07.338264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 11:45:07.338367 ==
4690 11:45:07.338459 DQS Delay:
4691 11:45:07.341300 DQS0 = 0, DQS1 = 0
4692 11:45:07.341393 DQM Delay:
4693 11:45:07.344926 DQM0 = 41, DQM1 = 37
4694 11:45:07.345001 DQ Delay:
4695 11:45:07.348266 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4696 11:45:07.351687 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4697 11:45:07.354603 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4698 11:45:07.357899 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4699 11:45:07.357974
4700 11:45:07.358035
4701 11:45:07.358101 ==
4702 11:45:07.361282 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 11:45:07.364583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 11:45:07.364707 ==
4705 11:45:07.364769
4706 11:45:07.364827
4707 11:45:07.368134 TX Vref Scan disable
4708 11:45:07.371246 == TX Byte 0 ==
4709 11:45:07.375183 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4710 11:45:07.378030 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4711 11:45:07.381406 == TX Byte 1 ==
4712 11:45:07.384584 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 11:45:07.388036 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 11:45:07.388105 ==
4715 11:45:07.391342 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 11:45:07.394701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 11:45:07.398134 ==
4718 11:45:07.398206
4719 11:45:07.398273
4720 11:45:07.398333 TX Vref Scan disable
4721 11:45:07.402010 == TX Byte 0 ==
4722 11:45:07.405132 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4723 11:45:07.412155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4724 11:45:07.412231 == TX Byte 1 ==
4725 11:45:07.415019 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 11:45:07.418509 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 11:45:07.421639
4728 11:45:07.421714 [DATLAT]
4729 11:45:07.421777 Freq=600, CH1 RK1
4730 11:45:07.421834
4731 11:45:07.425031 DATLAT Default: 0x9
4732 11:45:07.425128 0, 0xFFFF, sum = 0
4733 11:45:07.429361 1, 0xFFFF, sum = 0
4734 11:45:07.429452 2, 0xFFFF, sum = 0
4735 11:45:07.431848 3, 0xFFFF, sum = 0
4736 11:45:07.431924 4, 0xFFFF, sum = 0
4737 11:45:07.435216 5, 0xFFFF, sum = 0
4738 11:45:07.435286 6, 0xFFFF, sum = 0
4739 11:45:07.438749 7, 0xFFFF, sum = 0
4740 11:45:07.438875 8, 0x0, sum = 1
4741 11:45:07.441824 9, 0x0, sum = 2
4742 11:45:07.441894 10, 0x0, sum = 3
4743 11:45:07.445737 11, 0x0, sum = 4
4744 11:45:07.445807 best_step = 9
4745 11:45:07.445883
4746 11:45:07.445965 ==
4747 11:45:07.448823 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 11:45:07.455270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 11:45:07.455349 ==
4750 11:45:07.455416 RX Vref Scan: 0
4751 11:45:07.455483
4752 11:45:07.458936 RX Vref 0 -> 0, step: 1
4753 11:45:07.459015
4754 11:45:07.462009 RX Delay -179 -> 252, step: 8
4755 11:45:07.465636 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4756 11:45:07.468954 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4757 11:45:07.475218 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4758 11:45:07.478781 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4759 11:45:07.482113 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4760 11:45:07.485633 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4761 11:45:07.491955 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4762 11:45:07.495276 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4763 11:45:07.498770 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4764 11:45:07.502065 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4765 11:45:07.505446 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4766 11:45:07.512175 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4767 11:45:07.515278 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4768 11:45:07.518696 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4769 11:45:07.522143 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4770 11:45:07.529113 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4771 11:45:07.529197 ==
4772 11:45:07.532184 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 11:45:07.536442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 11:45:07.536524 ==
4775 11:45:07.536589 DQS Delay:
4776 11:45:07.539656 DQS0 = 0, DQS1 = 0
4777 11:45:07.539738 DQM Delay:
4778 11:45:07.542575 DQM0 = 38, DQM1 = 33
4779 11:45:07.542683 DQ Delay:
4780 11:45:07.545731 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4781 11:45:07.549014 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4782 11:45:07.552964 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4783 11:45:07.556087 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4784 11:45:07.556167
4785 11:45:07.556230
4786 11:45:07.562246 [DQSOSCAuto] RK1, (LSB)MR18= 0x3746, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4787 11:45:07.565760 CH1 RK1: MR19=808, MR18=3746
4788 11:45:07.572268 CH1_RK1: MR19=0x808, MR18=0x3746, DQSOSC=396, MR23=63, INC=167, DEC=111
4789 11:45:07.575784 [RxdqsGatingPostProcess] freq 600
4790 11:45:07.582289 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4791 11:45:07.582375 Pre-setting of DQS Precalculation
4792 11:45:07.589213 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4793 11:45:07.595599 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4794 11:45:07.602446 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4795 11:45:07.602528
4796 11:45:07.602630
4797 11:45:07.605612 [Calibration Summary] 1200 Mbps
4798 11:45:07.609547 CH 0, Rank 0
4799 11:45:07.609628 SW Impedance : PASS
4800 11:45:07.612525 DUTY Scan : NO K
4801 11:45:07.612605 ZQ Calibration : PASS
4802 11:45:07.615941 Jitter Meter : NO K
4803 11:45:07.619333 CBT Training : PASS
4804 11:45:07.619413 Write leveling : PASS
4805 11:45:07.622312 RX DQS gating : PASS
4806 11:45:07.626146 RX DQ/DQS(RDDQC) : PASS
4807 11:45:07.626242 TX DQ/DQS : PASS
4808 11:45:07.629466 RX DATLAT : PASS
4809 11:45:07.632656 RX DQ/DQS(Engine): PASS
4810 11:45:07.632736 TX OE : NO K
4811 11:45:07.635969 All Pass.
4812 11:45:07.636065
4813 11:45:07.636161 CH 0, Rank 1
4814 11:45:07.639125 SW Impedance : PASS
4815 11:45:07.639223 DUTY Scan : NO K
4816 11:45:07.642917 ZQ Calibration : PASS
4817 11:45:07.646210 Jitter Meter : NO K
4818 11:45:07.646307 CBT Training : PASS
4819 11:45:07.649569 Write leveling : PASS
4820 11:45:07.649666 RX DQS gating : PASS
4821 11:45:07.652583 RX DQ/DQS(RDDQC) : PASS
4822 11:45:07.655694 TX DQ/DQS : PASS
4823 11:45:07.655791 RX DATLAT : PASS
4824 11:45:07.659192 RX DQ/DQS(Engine): PASS
4825 11:45:07.662753 TX OE : NO K
4826 11:45:07.662880 All Pass.
4827 11:45:07.662981
4828 11:45:07.663055 CH 1, Rank 0
4829 11:45:07.665999 SW Impedance : PASS
4830 11:45:07.669690 DUTY Scan : NO K
4831 11:45:07.669770 ZQ Calibration : PASS
4832 11:45:07.672496 Jitter Meter : NO K
4833 11:45:07.675942 CBT Training : PASS
4834 11:45:07.676023 Write leveling : PASS
4835 11:45:07.679659 RX DQS gating : PASS
4836 11:45:07.683158 RX DQ/DQS(RDDQC) : PASS
4837 11:45:07.683239 TX DQ/DQS : PASS
4838 11:45:07.685991 RX DATLAT : PASS
4839 11:45:07.686072 RX DQ/DQS(Engine): PASS
4840 11:45:07.689412 TX OE : NO K
4841 11:45:07.689494 All Pass.
4842 11:45:07.689557
4843 11:45:07.692998 CH 1, Rank 1
4844 11:45:07.693078 SW Impedance : PASS
4845 11:45:07.696613 DUTY Scan : NO K
4846 11:45:07.699654 ZQ Calibration : PASS
4847 11:45:07.699734 Jitter Meter : NO K
4848 11:45:07.702715 CBT Training : PASS
4849 11:45:07.705941 Write leveling : PASS
4850 11:45:07.706067 RX DQS gating : PASS
4851 11:45:07.709772 RX DQ/DQS(RDDQC) : PASS
4852 11:45:07.712645 TX DQ/DQS : PASS
4853 11:45:07.712725 RX DATLAT : PASS
4854 11:45:07.716174 RX DQ/DQS(Engine): PASS
4855 11:45:07.716255 TX OE : NO K
4856 11:45:07.719834 All Pass.
4857 11:45:07.719914
4858 11:45:07.719976 DramC Write-DBI off
4859 11:45:07.723033 PER_BANK_REFRESH: Hybrid Mode
4860 11:45:07.726115 TX_TRACKING: ON
4861 11:45:07.733207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4862 11:45:07.736384 [FAST_K] Save calibration result to emmc
4863 11:45:07.743084 dramc_set_vcore_voltage set vcore to 662500
4864 11:45:07.743167 Read voltage for 933, 3
4865 11:45:07.743231 Vio18 = 0
4866 11:45:07.746119 Vcore = 662500
4867 11:45:07.746188 Vdram = 0
4868 11:45:07.746247 Vddq = 0
4869 11:45:07.749315 Vmddr = 0
4870 11:45:07.752664 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4871 11:45:07.759609 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4872 11:45:07.759690 MEM_TYPE=3, freq_sel=17
4873 11:45:07.762910 sv_algorithm_assistance_LP4_1600
4874 11:45:07.769396 ============ PULL DRAM RESETB DOWN ============
4875 11:45:07.773097 ========== PULL DRAM RESETB DOWN end =========
4876 11:45:07.776065 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 11:45:07.779585 ===================================
4878 11:45:07.782789 LPDDR4 DRAM CONFIGURATION
4879 11:45:07.786451 ===================================
4880 11:45:07.789560 EX_ROW_EN[0] = 0x0
4881 11:45:07.789667 EX_ROW_EN[1] = 0x0
4882 11:45:07.793380 LP4Y_EN = 0x0
4883 11:45:07.793475 WORK_FSP = 0x0
4884 11:45:07.796504 WL = 0x3
4885 11:45:07.796585 RL = 0x3
4886 11:45:07.799575 BL = 0x2
4887 11:45:07.799655 RPST = 0x0
4888 11:45:07.803007 RD_PRE = 0x0
4889 11:45:07.803087 WR_PRE = 0x1
4890 11:45:07.806458 WR_PST = 0x0
4891 11:45:07.806538 DBI_WR = 0x0
4892 11:45:07.809463 DBI_RD = 0x0
4893 11:45:07.809543 OTF = 0x1
4894 11:45:07.813134 ===================================
4895 11:45:07.816387 ===================================
4896 11:45:07.819813 ANA top config
4897 11:45:07.822775 ===================================
4898 11:45:07.822848 DLL_ASYNC_EN = 0
4899 11:45:07.826574 ALL_SLAVE_EN = 1
4900 11:45:07.829792 NEW_RANK_MODE = 1
4901 11:45:07.832695 DLL_IDLE_MODE = 1
4902 11:45:07.836341 LP45_APHY_COMB_EN = 1
4903 11:45:07.836414 TX_ODT_DIS = 1
4904 11:45:07.839551 NEW_8X_MODE = 1
4905 11:45:07.842968 ===================================
4906 11:45:07.846433 ===================================
4907 11:45:07.849766 data_rate = 1866
4908 11:45:07.852774 CKR = 1
4909 11:45:07.856557 DQ_P2S_RATIO = 8
4910 11:45:07.860019 ===================================
4911 11:45:07.860094 CA_P2S_RATIO = 8
4912 11:45:07.862756 DQ_CA_OPEN = 0
4913 11:45:07.866266 DQ_SEMI_OPEN = 0
4914 11:45:07.869756 CA_SEMI_OPEN = 0
4915 11:45:07.873249 CA_FULL_RATE = 0
4916 11:45:07.876364 DQ_CKDIV4_EN = 1
4917 11:45:07.876468 CA_CKDIV4_EN = 1
4918 11:45:07.879356 CA_PREDIV_EN = 0
4919 11:45:07.883145 PH8_DLY = 0
4920 11:45:07.886340 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4921 11:45:07.889969 DQ_AAMCK_DIV = 4
4922 11:45:07.892922 CA_AAMCK_DIV = 4
4923 11:45:07.893005 CA_ADMCK_DIV = 4
4924 11:45:07.896098 DQ_TRACK_CA_EN = 0
4925 11:45:07.899457 CA_PICK = 933
4926 11:45:07.902834 CA_MCKIO = 933
4927 11:45:07.906527 MCKIO_SEMI = 0
4928 11:45:07.910016 PLL_FREQ = 3732
4929 11:45:07.910139 DQ_UI_PI_RATIO = 32
4930 11:45:07.912891 CA_UI_PI_RATIO = 0
4931 11:45:07.916361 ===================================
4932 11:45:07.919549 ===================================
4933 11:45:07.923048 memory_type:LPDDR4
4934 11:45:07.926532 GP_NUM : 10
4935 11:45:07.926636 SRAM_EN : 1
4936 11:45:07.929587 MD32_EN : 0
4937 11:45:07.933010 ===================================
4938 11:45:07.936655 [ANA_INIT] >>>>>>>>>>>>>>
4939 11:45:07.936756 <<<<<< [CONFIGURE PHASE]: ANA_TX
4940 11:45:07.940163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4941 11:45:07.943220 ===================================
4942 11:45:07.946696 data_rate = 1866,PCW = 0X8f00
4943 11:45:07.949725 ===================================
4944 11:45:07.952954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4945 11:45:07.959479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 11:45:07.966276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 11:45:07.969671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4948 11:45:07.973059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4949 11:45:07.976811 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4950 11:45:07.979701 [ANA_INIT] flow start
4951 11:45:07.979786 [ANA_INIT] PLL >>>>>>>>
4952 11:45:07.983197 [ANA_INIT] PLL <<<<<<<<
4953 11:45:07.986182 [ANA_INIT] MIDPI >>>>>>>>
4954 11:45:07.986264 [ANA_INIT] MIDPI <<<<<<<<
4955 11:45:07.989429 [ANA_INIT] DLL >>>>>>>>
4956 11:45:07.992889 [ANA_INIT] flow end
4957 11:45:07.996431 ============ LP4 DIFF to SE enter ============
4958 11:45:07.999477 ============ LP4 DIFF to SE exit ============
4959 11:45:08.002844 [ANA_INIT] <<<<<<<<<<<<<
4960 11:45:08.006122 [Flow] Enable top DCM control >>>>>
4961 11:45:08.009754 [Flow] Enable top DCM control <<<<<
4962 11:45:08.013147 Enable DLL master slave shuffle
4963 11:45:08.016523 ==============================================================
4964 11:45:08.019680 Gating Mode config
4965 11:45:08.026237 ==============================================================
4966 11:45:08.026350 Config description:
4967 11:45:08.036402 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4968 11:45:08.043243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4969 11:45:08.046586 SELPH_MODE 0: By rank 1: By Phase
4970 11:45:08.053074 ==============================================================
4971 11:45:08.056585 GAT_TRACK_EN = 1
4972 11:45:08.060200 RX_GATING_MODE = 2
4973 11:45:08.063181 RX_GATING_TRACK_MODE = 2
4974 11:45:08.066644 SELPH_MODE = 1
4975 11:45:08.069982 PICG_EARLY_EN = 1
4976 11:45:08.072818 VALID_LAT_VALUE = 1
4977 11:45:08.076569 ==============================================================
4978 11:45:08.079601 Enter into Gating configuration >>>>
4979 11:45:08.083141 Exit from Gating configuration <<<<
4980 11:45:08.086341 Enter into DVFS_PRE_config >>>>>
4981 11:45:08.096313 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4982 11:45:08.099693 Exit from DVFS_PRE_config <<<<<
4983 11:45:08.103130 Enter into PICG configuration >>>>
4984 11:45:08.106758 Exit from PICG configuration <<<<
4985 11:45:08.109731 [RX_INPUT] configuration >>>>>
4986 11:45:08.112851 [RX_INPUT] configuration <<<<<
4987 11:45:08.116810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4988 11:45:08.123090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4989 11:45:08.130017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 11:45:08.136855 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 11:45:08.143058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 11:45:08.146593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 11:45:08.152886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4994 11:45:08.156634 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4995 11:45:08.159743 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4996 11:45:08.162895 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4997 11:45:08.169679 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4998 11:45:08.173441 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 11:45:08.176684 ===================================
5000 11:45:08.179691 LPDDR4 DRAM CONFIGURATION
5001 11:45:08.183195 ===================================
5002 11:45:08.183293 EX_ROW_EN[0] = 0x0
5003 11:45:08.186701 EX_ROW_EN[1] = 0x0
5004 11:45:08.186824 LP4Y_EN = 0x0
5005 11:45:08.189519 WORK_FSP = 0x0
5006 11:45:08.189617 WL = 0x3
5007 11:45:08.193088 RL = 0x3
5008 11:45:08.193185 BL = 0x2
5009 11:45:08.196572 RPST = 0x0
5010 11:45:08.196670 RD_PRE = 0x0
5011 11:45:08.199829 WR_PRE = 0x1
5012 11:45:08.199927 WR_PST = 0x0
5013 11:45:08.203222 DBI_WR = 0x0
5014 11:45:08.203319 DBI_RD = 0x0
5015 11:45:08.206774 OTF = 0x1
5016 11:45:08.210085 ===================================
5017 11:45:08.213138 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5018 11:45:08.216448 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5019 11:45:08.223546 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 11:45:08.226541 ===================================
5021 11:45:08.226643 LPDDR4 DRAM CONFIGURATION
5022 11:45:08.230001 ===================================
5023 11:45:08.233574 EX_ROW_EN[0] = 0x10
5024 11:45:08.236734 EX_ROW_EN[1] = 0x0
5025 11:45:08.236830 LP4Y_EN = 0x0
5026 11:45:08.240077 WORK_FSP = 0x0
5027 11:45:08.240184 WL = 0x3
5028 11:45:08.243329 RL = 0x3
5029 11:45:08.243404 BL = 0x2
5030 11:45:08.246982 RPST = 0x0
5031 11:45:08.247053 RD_PRE = 0x0
5032 11:45:08.249966 WR_PRE = 0x1
5033 11:45:08.250061 WR_PST = 0x0
5034 11:45:08.253174 DBI_WR = 0x0
5035 11:45:08.253270 DBI_RD = 0x0
5036 11:45:08.256461 OTF = 0x1
5037 11:45:08.259837 ===================================
5038 11:45:08.266843 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5039 11:45:08.270374 nWR fixed to 30
5040 11:45:08.270479 [ModeRegInit_LP4] CH0 RK0
5041 11:45:08.273429 [ModeRegInit_LP4] CH0 RK1
5042 11:45:08.276802 [ModeRegInit_LP4] CH1 RK0
5043 11:45:08.279743 [ModeRegInit_LP4] CH1 RK1
5044 11:45:08.279814 match AC timing 9
5045 11:45:08.283347 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5046 11:45:08.290051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5047 11:45:08.293606 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5048 11:45:08.297289 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5049 11:45:08.303856 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5050 11:45:08.303929 ==
5051 11:45:08.306894 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 11:45:08.310589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 11:45:08.310685 ==
5054 11:45:08.316820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 11:45:08.320073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5056 11:45:08.324455 [CA 0] Center 38 (8~69) winsize 62
5057 11:45:08.327600 [CA 1] Center 38 (7~69) winsize 63
5058 11:45:08.331348 [CA 2] Center 35 (5~66) winsize 62
5059 11:45:08.334178 [CA 3] Center 34 (4~65) winsize 62
5060 11:45:08.337757 [CA 4] Center 34 (4~64) winsize 61
5061 11:45:08.340871 [CA 5] Center 34 (4~64) winsize 61
5062 11:45:08.340970
5063 11:45:08.344409 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5064 11:45:08.344513
5065 11:45:08.348031 [CATrainingPosCal] consider 1 rank data
5066 11:45:08.351557 u2DelayCellTimex100 = 270/100 ps
5067 11:45:08.354520 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5068 11:45:08.357380 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5069 11:45:08.364796 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5070 11:45:08.367764 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5071 11:45:08.370920 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5072 11:45:08.374746 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5073 11:45:08.374842
5074 11:45:08.378067 CA PerBit enable=1, Macro0, CA PI delay=34
5075 11:45:08.378147
5076 11:45:08.381254 [CBTSetCACLKResult] CA Dly = 34
5077 11:45:08.381371 CS Dly: 7 (0~38)
5078 11:45:08.381434 ==
5079 11:45:08.384087 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 11:45:08.390850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 11:45:08.390970 ==
5082 11:45:08.394256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 11:45:08.401149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 11:45:08.404296 [CA 0] Center 38 (7~69) winsize 63
5085 11:45:08.407746 [CA 1] Center 38 (7~69) winsize 63
5086 11:45:08.411131 [CA 2] Center 35 (5~66) winsize 62
5087 11:45:08.414700 [CA 3] Center 34 (4~65) winsize 62
5088 11:45:08.418009 [CA 4] Center 34 (3~65) winsize 63
5089 11:45:08.421321 [CA 5] Center 33 (3~64) winsize 62
5090 11:45:08.421392
5091 11:45:08.424626 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 11:45:08.424721
5093 11:45:08.427939 [CATrainingPosCal] consider 2 rank data
5094 11:45:08.431221 u2DelayCellTimex100 = 270/100 ps
5095 11:45:08.434502 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5096 11:45:08.437888 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5097 11:45:08.444235 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5098 11:45:08.447393 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5099 11:45:08.450994 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 11:45:08.454311 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5101 11:45:08.454384
5102 11:45:08.458461 CA PerBit enable=1, Macro0, CA PI delay=34
5103 11:45:08.458561
5104 11:45:08.460982 [CBTSetCACLKResult] CA Dly = 34
5105 11:45:08.461156 CS Dly: 7 (0~39)
5106 11:45:08.461233
5107 11:45:08.464312 ----->DramcWriteLeveling(PI) begin...
5108 11:45:08.467568 ==
5109 11:45:08.467641 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 11:45:08.474529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 11:45:08.474601 ==
5112 11:45:08.478165 Write leveling (Byte 0): 29 => 29
5113 11:45:08.481408 Write leveling (Byte 1): 28 => 28
5114 11:45:08.481498 DramcWriteLeveling(PI) end<-----
5115 11:45:08.484536
5116 11:45:08.484618 ==
5117 11:45:08.488345 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 11:45:08.491384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 11:45:08.491464 ==
5120 11:45:08.494357 [Gating] SW mode calibration
5121 11:45:08.500887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5122 11:45:08.504864 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5123 11:45:08.511327 0 14 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
5124 11:45:08.514553 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5125 11:45:08.518170 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 11:45:08.524913 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 11:45:08.528220 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 11:45:08.531587 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 11:45:08.538262 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 11:45:08.541613 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5131 11:45:08.545045 0 15 0 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (0 0)
5132 11:45:08.548106 0 15 4 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
5133 11:45:08.554695 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 11:45:08.558082 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 11:45:08.561611 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 11:45:08.568288 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 11:45:08.571593 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 11:45:08.575092 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 11:45:08.581440 1 0 0 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
5140 11:45:08.584979 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 11:45:08.588101 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 11:45:08.594933 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 11:45:08.598315 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 11:45:08.601844 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 11:45:08.608391 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 11:45:08.611514 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 11:45:08.614783 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 11:45:08.621572 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:45:08.625088 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 11:45:08.628561 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 11:45:08.631903 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 11:45:08.638087 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 11:45:08.641431 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 11:45:08.644890 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 11:45:08.651553 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 11:45:08.655065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:45:08.658611 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:45:08.665406 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 11:45:08.668509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:45:08.671718 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:45:08.678242 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:45:08.682019 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:45:08.685169 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:45:08.691693 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5165 11:45:08.695645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 11:45:08.698575 Total UI for P1: 0, mck2ui 16
5167 11:45:08.701692 best dqsien dly found for B0: ( 1, 3, 4)
5168 11:45:08.705123 Total UI for P1: 0, mck2ui 16
5169 11:45:08.708577 best dqsien dly found for B1: ( 1, 3, 4)
5170 11:45:08.711896 best DQS0 dly(MCK, UI, PI) = (1, 3, 4)
5171 11:45:08.715239 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5172 11:45:08.715335
5173 11:45:08.718705 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 4)
5174 11:45:08.721879 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5175 11:45:08.724918 [Gating] SW calibration Done
5176 11:45:08.724992 ==
5177 11:45:08.728703 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 11:45:08.731937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 11:45:08.732039 ==
5180 11:45:08.735243 RX Vref Scan: 0
5181 11:45:08.735315
5182 11:45:08.735375 RX Vref 0 -> 0, step: 1
5183 11:45:08.735469
5184 11:45:08.738368 RX Delay -80 -> 252, step: 8
5185 11:45:08.741838 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5186 11:45:08.748665 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5187 11:45:08.751990 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5188 11:45:08.755600 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5189 11:45:08.758225 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5190 11:45:08.761697 iDelay=200, Bit 5, Center 83 (-16 ~ 183) 200
5191 11:45:08.768635 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5192 11:45:08.771618 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5193 11:45:08.775113 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5194 11:45:08.778767 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5195 11:45:08.781722 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5196 11:45:08.784974 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5197 11:45:08.791542 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5198 11:45:08.795353 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5199 11:45:08.798317 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5200 11:45:08.801800 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5201 11:45:08.801903 ==
5202 11:45:08.805048 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 11:45:08.808306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 11:45:08.811684 ==
5205 11:45:08.811753 DQS Delay:
5206 11:45:08.811829 DQS0 = 0, DQS1 = 0
5207 11:45:08.815342 DQM Delay:
5208 11:45:08.815471 DQM0 = 97, DQM1 = 86
5209 11:45:08.815534 DQ Delay:
5210 11:45:08.818291 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5211 11:45:08.821766 DQ4 =103, DQ5 =83, DQ6 =103, DQ7 =103
5212 11:45:08.825113 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5213 11:45:08.828209 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5214 11:45:08.832000
5215 11:45:08.832081
5216 11:45:08.832144 ==
5217 11:45:08.835205 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 11:45:08.838757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 11:45:08.838840 ==
5220 11:45:08.838931
5221 11:45:08.838991
5222 11:45:08.842046 TX Vref Scan disable
5223 11:45:08.842129 == TX Byte 0 ==
5224 11:45:08.848562 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5225 11:45:08.851737 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5226 11:45:08.851884 == TX Byte 1 ==
5227 11:45:08.858490 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5228 11:45:08.861985 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5229 11:45:08.862088 ==
5230 11:45:08.865439 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 11:45:08.869062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 11:45:08.869159 ==
5233 11:45:08.869224
5234 11:45:08.869284
5235 11:45:08.872426 TX Vref Scan disable
5236 11:45:08.875181 == TX Byte 0 ==
5237 11:45:08.879161 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5238 11:45:08.882644 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5239 11:45:08.886046 == TX Byte 1 ==
5240 11:45:08.889292 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5241 11:45:08.892678 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5242 11:45:08.892761
5243 11:45:08.892825 [DATLAT]
5244 11:45:08.895754 Freq=933, CH0 RK0
5245 11:45:08.895838
5246 11:45:08.895903 DATLAT Default: 0xd
5247 11:45:08.899038 0, 0xFFFF, sum = 0
5248 11:45:08.902639 1, 0xFFFF, sum = 0
5249 11:45:08.902723 2, 0xFFFF, sum = 0
5250 11:45:08.905751 3, 0xFFFF, sum = 0
5251 11:45:08.905835 4, 0xFFFF, sum = 0
5252 11:45:08.908989 5, 0xFFFF, sum = 0
5253 11:45:08.909072 6, 0xFFFF, sum = 0
5254 11:45:08.912235 7, 0xFFFF, sum = 0
5255 11:45:08.912370 8, 0xFFFF, sum = 0
5256 11:45:08.915666 9, 0xFFFF, sum = 0
5257 11:45:08.915780 10, 0x0, sum = 1
5258 11:45:08.919046 11, 0x0, sum = 2
5259 11:45:08.919130 12, 0x0, sum = 3
5260 11:45:08.922224 13, 0x0, sum = 4
5261 11:45:08.922313 best_step = 11
5262 11:45:08.922407
5263 11:45:08.922467 ==
5264 11:45:08.925564 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 11:45:08.929152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 11:45:08.929241 ==
5267 11:45:08.932672 RX Vref Scan: 1
5268 11:45:08.932773
5269 11:45:08.932838 RX Vref 0 -> 0, step: 1
5270 11:45:08.935780
5271 11:45:08.935863 RX Delay -69 -> 252, step: 4
5272 11:45:08.935956
5273 11:45:08.939176 Set Vref, RX VrefLevel [Byte0]: 53
5274 11:45:08.942545 [Byte1]: 51
5275 11:45:08.947000
5276 11:45:08.947089 Final RX Vref Byte 0 = 53 to rank0
5277 11:45:08.950234 Final RX Vref Byte 1 = 51 to rank0
5278 11:45:08.953648 Final RX Vref Byte 0 = 53 to rank1
5279 11:45:08.956721 Final RX Vref Byte 1 = 51 to rank1==
5280 11:45:08.960323 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 11:45:08.967109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 11:45:08.967234 ==
5283 11:45:08.967317 DQS Delay:
5284 11:45:08.967438 DQS0 = 0, DQS1 = 0
5285 11:45:08.970767 DQM Delay:
5286 11:45:08.970970 DQM0 = 97, DQM1 = 89
5287 11:45:08.973614 DQ Delay:
5288 11:45:08.976829 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5289 11:45:08.980361 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =104
5290 11:45:08.983459 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =82
5291 11:45:08.986795 DQ12 =94, DQ13 =90, DQ14 =100, DQ15 =100
5292 11:45:08.986921
5293 11:45:08.986987
5294 11:45:08.993840 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5295 11:45:08.996939 CH0 RK0: MR19=504, MR18=13FE
5296 11:45:09.003234 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5297 11:45:09.003342
5298 11:45:09.006793 ----->DramcWriteLeveling(PI) begin...
5299 11:45:09.006920 ==
5300 11:45:09.010434 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 11:45:09.013456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 11:45:09.013541 ==
5303 11:45:09.016712 Write leveling (Byte 0): 30 => 30
5304 11:45:09.019940 Write leveling (Byte 1): 28 => 28
5305 11:45:09.023161 DramcWriteLeveling(PI) end<-----
5306 11:45:09.023247
5307 11:45:09.023364 ==
5308 11:45:09.026574 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 11:45:09.030009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 11:45:09.030182 ==
5311 11:45:09.033328 [Gating] SW mode calibration
5312 11:45:09.039872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5313 11:45:09.046677 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5314 11:45:09.049861 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5315 11:45:09.056465 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 11:45:09.060348 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 11:45:09.063721 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 11:45:09.066772 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 11:45:09.073585 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 11:45:09.076947 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5321 11:45:09.080479 0 14 28 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5322 11:45:09.086698 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5323 11:45:09.089987 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 11:45:09.093612 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 11:45:09.100001 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 11:45:09.103187 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 11:45:09.106875 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 11:45:09.113326 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 11:45:09.116570 0 15 28 | B1->B0 | 2b2b 3737 | 0 1 | (0 0) (0 0)
5330 11:45:09.119927 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5331 11:45:09.126846 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:45:09.130513 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 11:45:09.133810 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 11:45:09.140118 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 11:45:09.143502 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 11:45:09.146773 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5337 11:45:09.150119 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 11:45:09.156829 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5339 11:45:09.160026 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 11:45:09.163738 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 11:45:09.170359 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 11:45:09.173985 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 11:45:09.177249 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 11:45:09.183508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 11:45:09.187223 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 11:45:09.190214 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:45:09.197291 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:45:09.200371 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:45:09.203728 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 11:45:09.210234 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:45:09.213848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:45:09.217087 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5353 11:45:09.223835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5354 11:45:09.223933 Total UI for P1: 0, mck2ui 16
5355 11:45:09.227127 best dqsien dly found for B0: ( 1, 2, 24)
5356 11:45:09.234121 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 11:45:09.236833 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 11:45:09.240129 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 11:45:09.243482 Total UI for P1: 0, mck2ui 16
5360 11:45:09.246810 best dqsien dly found for B1: ( 1, 3, 0)
5361 11:45:09.250227 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5362 11:45:09.254012 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5363 11:45:09.254112
5364 11:45:09.260525 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5365 11:45:09.264008 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5366 11:45:09.267460 [Gating] SW calibration Done
5367 11:45:09.267552 ==
5368 11:45:09.270534 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:45:09.273836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:45:09.273919 ==
5371 11:45:09.273982 RX Vref Scan: 0
5372 11:45:09.274040
5373 11:45:09.277333 RX Vref 0 -> 0, step: 1
5374 11:45:09.277414
5375 11:45:09.280384 RX Delay -80 -> 252, step: 8
5376 11:45:09.284325 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5377 11:45:09.286920 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5378 11:45:09.290609 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5379 11:45:09.294013 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5380 11:45:09.300870 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5381 11:45:09.304054 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5382 11:45:09.307243 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5383 11:45:09.310768 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5384 11:45:09.313996 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5385 11:45:09.317055 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5386 11:45:09.324314 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5387 11:45:09.327413 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5388 11:45:09.330955 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5389 11:45:09.334285 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5390 11:45:09.337687 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5391 11:45:09.341014 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5392 11:45:09.344399 ==
5393 11:45:09.344491 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 11:45:09.350755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 11:45:09.350886 ==
5396 11:45:09.350969 DQS Delay:
5397 11:45:09.354179 DQS0 = 0, DQS1 = 0
5398 11:45:09.354264 DQM Delay:
5399 11:45:09.357727 DQM0 = 97, DQM1 = 88
5400 11:45:09.357839 DQ Delay:
5401 11:45:09.360743 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5402 11:45:09.364062 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5403 11:45:09.367970 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5404 11:45:09.371210 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5405 11:45:09.371292
5406 11:45:09.371355
5407 11:45:09.371426 ==
5408 11:45:09.374130 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 11:45:09.377772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 11:45:09.377849 ==
5411 11:45:09.377912
5412 11:45:09.377986
5413 11:45:09.381056 TX Vref Scan disable
5414 11:45:09.384408 == TX Byte 0 ==
5415 11:45:09.387706 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5416 11:45:09.390594 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5417 11:45:09.394513 == TX Byte 1 ==
5418 11:45:09.397880 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5419 11:45:09.400928 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5420 11:45:09.401011 ==
5421 11:45:09.404416 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:45:09.407933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:45:09.408023 ==
5424 11:45:09.410828
5425 11:45:09.410922
5426 11:45:09.410987 TX Vref Scan disable
5427 11:45:09.414616 == TX Byte 0 ==
5428 11:45:09.418001 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 11:45:09.424305 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 11:45:09.424416 == TX Byte 1 ==
5431 11:45:09.427846 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5432 11:45:09.430752 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5433 11:45:09.434219
5434 11:45:09.434344 [DATLAT]
5435 11:45:09.434439 Freq=933, CH0 RK1
5436 11:45:09.434536
5437 11:45:09.437383 DATLAT Default: 0xb
5438 11:45:09.437483 0, 0xFFFF, sum = 0
5439 11:45:09.441491 1, 0xFFFF, sum = 0
5440 11:45:09.441601 2, 0xFFFF, sum = 0
5441 11:45:09.444484 3, 0xFFFF, sum = 0
5442 11:45:09.444597 4, 0xFFFF, sum = 0
5443 11:45:09.447863 5, 0xFFFF, sum = 0
5444 11:45:09.447942 6, 0xFFFF, sum = 0
5445 11:45:09.451204 7, 0xFFFF, sum = 0
5446 11:45:09.454907 8, 0xFFFF, sum = 0
5447 11:45:09.455030 9, 0xFFFF, sum = 0
5448 11:45:09.455120 10, 0x0, sum = 1
5449 11:45:09.457550 11, 0x0, sum = 2
5450 11:45:09.457648 12, 0x0, sum = 3
5451 11:45:09.461358 13, 0x0, sum = 4
5452 11:45:09.461434 best_step = 11
5453 11:45:09.461494
5454 11:45:09.461552 ==
5455 11:45:09.464593 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:45:09.471383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:45:09.471490 ==
5458 11:45:09.471572 RX Vref Scan: 0
5459 11:45:09.471633
5460 11:45:09.474627 RX Vref 0 -> 0, step: 1
5461 11:45:09.474726
5462 11:45:09.477451 RX Delay -61 -> 252, step: 4
5463 11:45:09.480927 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5464 11:45:09.484364 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5465 11:45:09.491245 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5466 11:45:09.494322 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5467 11:45:09.498140 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5468 11:45:09.501101 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5469 11:45:09.504606 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5470 11:45:09.508083 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5471 11:45:09.514604 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5472 11:45:09.517672 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5473 11:45:09.520943 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5474 11:45:09.524882 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5475 11:45:09.527749 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5476 11:45:09.531106 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5477 11:45:09.537832 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5478 11:45:09.541430 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5479 11:45:09.541526 ==
5480 11:45:09.544553 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 11:45:09.548303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 11:45:09.548393 ==
5483 11:45:09.548459 DQS Delay:
5484 11:45:09.551066 DQS0 = 0, DQS1 = 0
5485 11:45:09.551162 DQM Delay:
5486 11:45:09.554497 DQM0 = 95, DQM1 = 88
5487 11:45:09.554583 DQ Delay:
5488 11:45:09.558039 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5489 11:45:09.561458 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5490 11:45:09.564925 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =78
5491 11:45:09.568144 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =96
5492 11:45:09.568232
5493 11:45:09.568296
5494 11:45:09.578015 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5495 11:45:09.578132 CH0 RK1: MR19=505, MR18=1E0C
5496 11:45:09.585149 CH0_RK1: MR19=0x505, MR18=0x1E0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5497 11:45:09.588168 [RxdqsGatingPostProcess] freq 933
5498 11:45:09.594520 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 11:45:09.597929 best DQS0 dly(2T, 0.5T) = (0, 11)
5500 11:45:09.601209 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 11:45:09.604671 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5502 11:45:09.604762 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 11:45:09.608031 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 11:45:09.611767 best DQS1 dly(2T, 0.5T) = (0, 11)
5505 11:45:09.614776 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 11:45:09.618355 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5507 11:45:09.621568 Pre-setting of DQS Precalculation
5508 11:45:09.628432 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 11:45:09.628580 ==
5510 11:45:09.631640 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 11:45:09.634836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 11:45:09.634956 ==
5513 11:45:09.641545 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 11:45:09.644666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5515 11:45:09.648892 [CA 0] Center 37 (7~67) winsize 61
5516 11:45:09.652412 [CA 1] Center 36 (6~67) winsize 62
5517 11:45:09.655595 [CA 2] Center 34 (4~65) winsize 62
5518 11:45:09.659058 [CA 3] Center 33 (3~64) winsize 62
5519 11:45:09.662418 [CA 4] Center 34 (4~65) winsize 62
5520 11:45:09.665653 [CA 5] Center 33 (3~64) winsize 62
5521 11:45:09.665743
5522 11:45:09.669150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5523 11:45:09.669293
5524 11:45:09.672271 [CATrainingPosCal] consider 1 rank data
5525 11:45:09.675890 u2DelayCellTimex100 = 270/100 ps
5526 11:45:09.678829 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5527 11:45:09.682555 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5528 11:45:09.688726 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 11:45:09.692296 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5530 11:45:09.695687 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 11:45:09.699235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 11:45:09.699341
5533 11:45:09.702791 CA PerBit enable=1, Macro0, CA PI delay=33
5534 11:45:09.702951
5535 11:45:09.705403 [CBTSetCACLKResult] CA Dly = 33
5536 11:45:09.705501 CS Dly: 4 (0~35)
5537 11:45:09.705598 ==
5538 11:45:09.709048 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 11:45:09.716227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 11:45:09.716347 ==
5541 11:45:09.719264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 11:45:09.725688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5543 11:45:09.729092 [CA 0] Center 37 (7~67) winsize 61
5544 11:45:09.732832 [CA 1] Center 37 (7~67) winsize 61
5545 11:45:09.735644 [CA 2] Center 34 (4~64) winsize 61
5546 11:45:09.739115 [CA 3] Center 33 (3~64) winsize 62
5547 11:45:09.742716 [CA 4] Center 34 (4~65) winsize 62
5548 11:45:09.746113 [CA 5] Center 32 (2~63) winsize 62
5549 11:45:09.746204
5550 11:45:09.749104 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5551 11:45:09.749187
5552 11:45:09.752066 [CATrainingPosCal] consider 2 rank data
5553 11:45:09.755672 u2DelayCellTimex100 = 270/100 ps
5554 11:45:09.758982 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5555 11:45:09.762150 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5556 11:45:09.768887 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5557 11:45:09.772235 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 11:45:09.775379 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5559 11:45:09.778715 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5560 11:45:09.778831
5561 11:45:09.782197 CA PerBit enable=1, Macro0, CA PI delay=33
5562 11:45:09.782283
5563 11:45:09.785145 [CBTSetCACLKResult] CA Dly = 33
5564 11:45:09.785262 CS Dly: 5 (0~38)
5565 11:45:09.785342
5566 11:45:09.788522 ----->DramcWriteLeveling(PI) begin...
5567 11:45:09.791877 ==
5568 11:45:09.795189 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 11:45:09.798475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 11:45:09.798565 ==
5571 11:45:09.801928 Write leveling (Byte 0): 27 => 27
5572 11:45:09.805572 Write leveling (Byte 1): 28 => 28
5573 11:45:09.808828 DramcWriteLeveling(PI) end<-----
5574 11:45:09.808913
5575 11:45:09.809023 ==
5576 11:45:09.812118 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 11:45:09.815587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 11:45:09.815673 ==
5579 11:45:09.818927 [Gating] SW mode calibration
5580 11:45:09.825270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 11:45:09.828844 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 11:45:09.835112 0 14 0 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
5583 11:45:09.838924 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 11:45:09.842070 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 11:45:09.848977 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 11:45:09.852217 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5587 11:45:09.855467 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 11:45:09.862134 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5589 11:45:09.865381 0 14 28 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (0 0)
5590 11:45:09.868868 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5591 11:45:09.875916 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 11:45:09.879185 0 15 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5593 11:45:09.882100 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 11:45:09.888564 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 11:45:09.892369 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5596 11:45:09.895701 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 11:45:09.902045 0 15 28 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
5598 11:45:09.905206 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 11:45:09.908979 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 11:45:09.915491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 11:45:09.918777 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 11:45:09.922061 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 11:45:09.925576 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 11:45:09.931965 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:45:09.935226 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5606 11:45:09.938651 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5607 11:45:09.945587 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 11:45:09.948828 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 11:45:09.952560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 11:45:09.959175 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 11:45:09.962107 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 11:45:09.965444 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:45:09.972625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:45:09.975699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:45:09.978902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:45:09.982427 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:45:09.988860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:45:09.992386 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:45:09.995882 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:45:10.002581 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:45:10.005995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5622 11:45:10.009098 Total UI for P1: 0, mck2ui 16
5623 11:45:10.012394 best dqsien dly found for B0: ( 1, 2, 26)
5624 11:45:10.015661 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 11:45:10.018892 Total UI for P1: 0, mck2ui 16
5626 11:45:10.022452 best dqsien dly found for B1: ( 1, 2, 28)
5627 11:45:10.025720 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5628 11:45:10.029022 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5629 11:45:10.029119
5630 11:45:10.035639 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 11:45:10.039010 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 11:45:10.042150 [Gating] SW calibration Done
5633 11:45:10.042228 ==
5634 11:45:10.045826 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:45:10.049188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:45:10.049270 ==
5637 11:45:10.049340 RX Vref Scan: 0
5638 11:45:10.049401
5639 11:45:10.052384 RX Vref 0 -> 0, step: 1
5640 11:45:10.052460
5641 11:45:10.055308 RX Delay -80 -> 252, step: 8
5642 11:45:10.058701 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5643 11:45:10.062523 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5644 11:45:10.065598 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5645 11:45:10.072309 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5646 11:45:10.075978 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5647 11:45:10.079012 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5648 11:45:10.082667 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5649 11:45:10.086133 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5650 11:45:10.088949 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5651 11:45:10.096084 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5652 11:45:10.098921 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5653 11:45:10.102535 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5654 11:45:10.105633 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5655 11:45:10.109108 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5656 11:45:10.112325 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5657 11:45:10.119004 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5658 11:45:10.119143 ==
5659 11:45:10.122219 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 11:45:10.125625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 11:45:10.125755 ==
5662 11:45:10.125890 DQS Delay:
5663 11:45:10.128930 DQS0 = 0, DQS1 = 0
5664 11:45:10.129074 DQM Delay:
5665 11:45:10.132658 DQM0 = 97, DQM1 = 89
5666 11:45:10.132755 DQ Delay:
5667 11:45:10.135858 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5668 11:45:10.139325 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5669 11:45:10.142262 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5670 11:45:10.146085 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5671 11:45:10.146175
5672 11:45:10.146248
5673 11:45:10.146307 ==
5674 11:45:10.149210 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 11:45:10.152489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 11:45:10.152585 ==
5677 11:45:10.152650
5678 11:45:10.152709
5679 11:45:10.155645 TX Vref Scan disable
5680 11:45:10.159164 == TX Byte 0 ==
5681 11:45:10.162663 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5682 11:45:10.165728 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5683 11:45:10.169805 == TX Byte 1 ==
5684 11:45:10.172510 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5685 11:45:10.176200 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5686 11:45:10.176292 ==
5687 11:45:10.179266 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 11:45:10.185453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 11:45:10.185554 ==
5690 11:45:10.185620
5691 11:45:10.185698
5692 11:45:10.185759 TX Vref Scan disable
5693 11:45:10.189725 == TX Byte 0 ==
5694 11:45:10.193198 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5695 11:45:10.199659 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5696 11:45:10.199777 == TX Byte 1 ==
5697 11:45:10.203125 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5698 11:45:10.206364 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5699 11:45:10.210081
5700 11:45:10.210177 [DATLAT]
5701 11:45:10.210263 Freq=933, CH1 RK0
5702 11:45:10.210344
5703 11:45:10.213281 DATLAT Default: 0xd
5704 11:45:10.213393 0, 0xFFFF, sum = 0
5705 11:45:10.216240 1, 0xFFFF, sum = 0
5706 11:45:10.216328 2, 0xFFFF, sum = 0
5707 11:45:10.220155 3, 0xFFFF, sum = 0
5708 11:45:10.220247 4, 0xFFFF, sum = 0
5709 11:45:10.223499 5, 0xFFFF, sum = 0
5710 11:45:10.223589 6, 0xFFFF, sum = 0
5711 11:45:10.226284 7, 0xFFFF, sum = 0
5712 11:45:10.229683 8, 0xFFFF, sum = 0
5713 11:45:10.229815 9, 0xFFFF, sum = 0
5714 11:45:10.229923 10, 0x0, sum = 1
5715 11:45:10.233003 11, 0x0, sum = 2
5716 11:45:10.233093 12, 0x0, sum = 3
5717 11:45:10.236520 13, 0x0, sum = 4
5718 11:45:10.236607 best_step = 11
5719 11:45:10.236680
5720 11:45:10.236742 ==
5721 11:45:10.239620 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:45:10.246514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:45:10.246617 ==
5724 11:45:10.246686 RX Vref Scan: 1
5725 11:45:10.246746
5726 11:45:10.249849 RX Vref 0 -> 0, step: 1
5727 11:45:10.249959
5728 11:45:10.252908 RX Delay -61 -> 252, step: 4
5729 11:45:10.252989
5730 11:45:10.256554 Set Vref, RX VrefLevel [Byte0]: 56
5731 11:45:10.259627 [Byte1]: 54
5732 11:45:10.259753
5733 11:45:10.263098 Final RX Vref Byte 0 = 56 to rank0
5734 11:45:10.266497 Final RX Vref Byte 1 = 54 to rank0
5735 11:45:10.269765 Final RX Vref Byte 0 = 56 to rank1
5736 11:45:10.273371 Final RX Vref Byte 1 = 54 to rank1==
5737 11:45:10.276197 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 11:45:10.279940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 11:45:10.280033 ==
5740 11:45:10.283431 DQS Delay:
5741 11:45:10.283547 DQS0 = 0, DQS1 = 0
5742 11:45:10.286213 DQM Delay:
5743 11:45:10.286298 DQM0 = 98, DQM1 = 91
5744 11:45:10.286362 DQ Delay:
5745 11:45:10.289583 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5746 11:45:10.292987 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5747 11:45:10.296344 DQ8 =82, DQ9 =82, DQ10 =90, DQ11 =88
5748 11:45:10.299779 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5749 11:45:10.299872
5750 11:45:10.299938
5751 11:45:10.310185 [DQSOSCAuto] RK0, (LSB)MR18= 0x19f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5752 11:45:10.313107 CH1 RK0: MR19=504, MR18=19F6
5753 11:45:10.316243 CH1_RK0: MR19=0x504, MR18=0x19F6, DQSOSC=413, MR23=63, INC=63, DEC=42
5754 11:45:10.319642
5755 11:45:10.323542 ----->DramcWriteLeveling(PI) begin...
5756 11:45:10.323635 ==
5757 11:45:10.326359 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 11:45:10.329706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 11:45:10.329809 ==
5760 11:45:10.332999 Write leveling (Byte 0): 27 => 27
5761 11:45:10.336406 Write leveling (Byte 1): 31 => 31
5762 11:45:10.339770 DramcWriteLeveling(PI) end<-----
5763 11:45:10.339862
5764 11:45:10.339926 ==
5765 11:45:10.343199 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 11:45:10.346271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 11:45:10.346358 ==
5768 11:45:10.349668 [Gating] SW mode calibration
5769 11:45:10.356429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5770 11:45:10.363301 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5771 11:45:10.366152 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 11:45:10.369536 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 11:45:10.373160 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 11:45:10.379465 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5775 11:45:10.382811 0 14 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5776 11:45:10.386363 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5777 11:45:10.393132 0 14 24 | B1->B0 | 3131 2c2c | 0 0 | (1 0) (0 0)
5778 11:45:10.396387 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5779 11:45:10.399586 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 11:45:10.406644 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 11:45:10.409989 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5782 11:45:10.413347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 11:45:10.419685 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 11:45:10.423189 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5785 11:45:10.426613 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (1 1) (0 0)
5786 11:45:10.433276 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5787 11:45:10.436897 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 11:45:10.440153 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 11:45:10.446709 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 11:45:10.449819 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 11:45:10.453289 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 11:45:10.460176 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5793 11:45:10.463417 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5794 11:45:10.466602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5795 11:45:10.469890 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 11:45:10.476675 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 11:45:10.480150 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 11:45:10.483269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 11:45:10.490006 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 11:45:10.493357 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 11:45:10.496504 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 11:45:10.503379 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 11:45:10.506320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 11:45:10.510103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:45:10.516585 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:45:10.520072 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:45:10.523355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:45:10.530152 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:45:10.533721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5810 11:45:10.536639 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 11:45:10.540077 Total UI for P1: 0, mck2ui 16
5812 11:45:10.543477 best dqsien dly found for B0: ( 1, 2, 24)
5813 11:45:10.546818 Total UI for P1: 0, mck2ui 16
5814 11:45:10.550214 best dqsien dly found for B1: ( 1, 2, 26)
5815 11:45:10.553216 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5816 11:45:10.556862 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5817 11:45:10.556948
5818 11:45:10.559710 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5819 11:45:10.566632 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5820 11:45:10.566739 [Gating] SW calibration Done
5821 11:45:10.566806 ==
5822 11:45:10.569786 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:45:10.576798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:45:10.576903 ==
5825 11:45:10.576980 RX Vref Scan: 0
5826 11:45:10.577041
5827 11:45:10.579724 RX Vref 0 -> 0, step: 1
5828 11:45:10.579799
5829 11:45:10.583824 RX Delay -80 -> 252, step: 8
5830 11:45:10.586958 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5831 11:45:10.589885 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5832 11:45:10.593312 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5833 11:45:10.596749 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5834 11:45:10.599941 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5835 11:45:10.606636 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5836 11:45:10.610216 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5837 11:45:10.613424 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5838 11:45:10.616931 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5839 11:45:10.619803 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5840 11:45:10.626740 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5841 11:45:10.629885 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5842 11:45:10.633402 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5843 11:45:10.636709 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5844 11:45:10.639824 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5845 11:45:10.643796 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5846 11:45:10.646641 ==
5847 11:45:10.646766 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 11:45:10.653378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 11:45:10.653481 ==
5850 11:45:10.653555 DQS Delay:
5851 11:45:10.656797 DQS0 = 0, DQS1 = 0
5852 11:45:10.656873 DQM Delay:
5853 11:45:10.660176 DQM0 = 94, DQM1 = 88
5854 11:45:10.660263 DQ Delay:
5855 11:45:10.663506 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5856 11:45:10.666717 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =87
5857 11:45:10.670190 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5858 11:45:10.673677 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5859 11:45:10.673766
5860 11:45:10.673829
5861 11:45:10.673889 ==
5862 11:45:10.677193 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 11:45:10.679923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 11:45:10.679998 ==
5865 11:45:10.680059
5866 11:45:10.680124
5867 11:45:10.683406 TX Vref Scan disable
5868 11:45:10.687039 == TX Byte 0 ==
5869 11:45:10.689978 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 11:45:10.693392 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 11:45:10.696973 == TX Byte 1 ==
5872 11:45:10.700260 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5873 11:45:10.703639 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5874 11:45:10.703724 ==
5875 11:45:10.707057 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 11:45:10.710281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 11:45:10.713146 ==
5878 11:45:10.713228
5879 11:45:10.713299
5880 11:45:10.713358 TX Vref Scan disable
5881 11:45:10.716820 == TX Byte 0 ==
5882 11:45:10.720057 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5883 11:45:10.723972 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5884 11:45:10.726739 == TX Byte 1 ==
5885 11:45:10.730453 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5886 11:45:10.733289 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5887 11:45:10.736851
5888 11:45:10.736940 [DATLAT]
5889 11:45:10.737011 Freq=933, CH1 RK1
5890 11:45:10.737073
5891 11:45:10.740206 DATLAT Default: 0xb
5892 11:45:10.740286 0, 0xFFFF, sum = 0
5893 11:45:10.743449 1, 0xFFFF, sum = 0
5894 11:45:10.743528 2, 0xFFFF, sum = 0
5895 11:45:10.746737 3, 0xFFFF, sum = 0
5896 11:45:10.746844 4, 0xFFFF, sum = 0
5897 11:45:10.750319 5, 0xFFFF, sum = 0
5898 11:45:10.750409 6, 0xFFFF, sum = 0
5899 11:45:10.753382 7, 0xFFFF, sum = 0
5900 11:45:10.756709 8, 0xFFFF, sum = 0
5901 11:45:10.756797 9, 0xFFFF, sum = 0
5902 11:45:10.756870 10, 0x0, sum = 1
5903 11:45:10.760255 11, 0x0, sum = 2
5904 11:45:10.760409 12, 0x0, sum = 3
5905 11:45:10.764153 13, 0x0, sum = 4
5906 11:45:10.764231 best_step = 11
5907 11:45:10.764293
5908 11:45:10.764357 ==
5909 11:45:10.766969 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:45:10.773592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:45:10.773691 ==
5912 11:45:10.773755 RX Vref Scan: 0
5913 11:45:10.773821
5914 11:45:10.777182 RX Vref 0 -> 0, step: 1
5915 11:45:10.777262
5916 11:45:10.780175 RX Delay -61 -> 252, step: 4
5917 11:45:10.784013 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5918 11:45:10.786948 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5919 11:45:10.793791 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5920 11:45:10.797016 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5921 11:45:10.800377 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5922 11:45:10.803754 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5923 11:45:10.807183 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5924 11:45:10.810404 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5925 11:45:10.817102 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5926 11:45:10.820657 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5927 11:45:10.823623 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5928 11:45:10.827148 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5929 11:45:10.830679 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5930 11:45:10.837263 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5931 11:45:10.840314 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5932 11:45:10.843795 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5933 11:45:10.843879 ==
5934 11:45:10.846976 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 11:45:10.850725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 11:45:10.850821 ==
5937 11:45:10.853544 DQS Delay:
5938 11:45:10.853629 DQS0 = 0, DQS1 = 0
5939 11:45:10.857577 DQM Delay:
5940 11:45:10.857668 DQM0 = 95, DQM1 = 91
5941 11:45:10.857733 DQ Delay:
5942 11:45:10.860750 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5943 11:45:10.863822 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5944 11:45:10.867073 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5945 11:45:10.870380 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5946 11:45:10.870512
5947 11:45:10.870670
5948 11:45:10.880201 [DQSOSCAuto] RK1, (LSB)MR18= 0x111b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5949 11:45:10.883944 CH1 RK1: MR19=505, MR18=111B
5950 11:45:10.890621 CH1_RK1: MR19=0x505, MR18=0x111B, DQSOSC=413, MR23=63, INC=63, DEC=42
5951 11:45:10.890756 [RxdqsGatingPostProcess] freq 933
5952 11:45:10.897038 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5953 11:45:10.900626 best DQS0 dly(2T, 0.5T) = (0, 10)
5954 11:45:10.904041 best DQS1 dly(2T, 0.5T) = (0, 10)
5955 11:45:10.907218 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5956 11:45:10.910786 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5957 11:45:10.913850 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 11:45:10.917186 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 11:45:10.920362 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 11:45:10.923809 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 11:45:10.927078 Pre-setting of DQS Precalculation
5962 11:45:10.930694 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5963 11:45:10.936926 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5964 11:45:10.944161 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5965 11:45:10.944301
5966 11:45:10.944396
5967 11:45:10.947306 [Calibration Summary] 1866 Mbps
5968 11:45:10.950215 CH 0, Rank 0
5969 11:45:10.950321 SW Impedance : PASS
5970 11:45:10.954159 DUTY Scan : NO K
5971 11:45:10.957711 ZQ Calibration : PASS
5972 11:45:10.957827 Jitter Meter : NO K
5973 11:45:10.960511 CBT Training : PASS
5974 11:45:10.964053 Write leveling : PASS
5975 11:45:10.964169 RX DQS gating : PASS
5976 11:45:10.967481 RX DQ/DQS(RDDQC) : PASS
5977 11:45:10.967583 TX DQ/DQS : PASS
5978 11:45:10.971141 RX DATLAT : PASS
5979 11:45:10.974615 RX DQ/DQS(Engine): PASS
5980 11:45:10.974724 TX OE : NO K
5981 11:45:10.977912 All Pass.
5982 11:45:10.978007
5983 11:45:10.978068 CH 0, Rank 1
5984 11:45:10.980820 SW Impedance : PASS
5985 11:45:10.980908 DUTY Scan : NO K
5986 11:45:10.984329 ZQ Calibration : PASS
5987 11:45:10.987789 Jitter Meter : NO K
5988 11:45:10.987889 CBT Training : PASS
5989 11:45:10.991054 Write leveling : PASS
5990 11:45:10.994708 RX DQS gating : PASS
5991 11:45:10.994845 RX DQ/DQS(RDDQC) : PASS
5992 11:45:10.997309 TX DQ/DQS : PASS
5993 11:45:10.997384 RX DATLAT : PASS
5994 11:45:11.001122 RX DQ/DQS(Engine): PASS
5995 11:45:11.004142 TX OE : NO K
5996 11:45:11.004254 All Pass.
5997 11:45:11.004344
5998 11:45:11.004430 CH 1, Rank 0
5999 11:45:11.007643 SW Impedance : PASS
6000 11:45:11.010708 DUTY Scan : NO K
6001 11:45:11.010780 ZQ Calibration : PASS
6002 11:45:11.014371 Jitter Meter : NO K
6003 11:45:11.017422 CBT Training : PASS
6004 11:45:11.017523 Write leveling : PASS
6005 11:45:11.021291 RX DQS gating : PASS
6006 11:45:11.024271 RX DQ/DQS(RDDQC) : PASS
6007 11:45:11.024356 TX DQ/DQS : PASS
6008 11:45:11.027296 RX DATLAT : PASS
6009 11:45:11.030432 RX DQ/DQS(Engine): PASS
6010 11:45:11.030531 TX OE : NO K
6011 11:45:11.033745 All Pass.
6012 11:45:11.033843
6013 11:45:11.033944 CH 1, Rank 1
6014 11:45:11.037261 SW Impedance : PASS
6015 11:45:11.037379 DUTY Scan : NO K
6016 11:45:11.040722 ZQ Calibration : PASS
6017 11:45:11.044318 Jitter Meter : NO K
6018 11:45:11.044454 CBT Training : PASS
6019 11:45:11.047179 Write leveling : PASS
6020 11:45:11.051097 RX DQS gating : PASS
6021 11:45:11.051189 RX DQ/DQS(RDDQC) : PASS
6022 11:45:11.053872 TX DQ/DQS : PASS
6023 11:45:11.053971 RX DATLAT : PASS
6024 11:45:11.057146 RX DQ/DQS(Engine): PASS
6025 11:45:11.060628 TX OE : NO K
6026 11:45:11.060710 All Pass.
6027 11:45:11.060774
6028 11:45:11.064096 DramC Write-DBI off
6029 11:45:11.064179 PER_BANK_REFRESH: Hybrid Mode
6030 11:45:11.067287 TX_TRACKING: ON
6031 11:45:11.077769 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6032 11:45:11.080945 [FAST_K] Save calibration result to emmc
6033 11:45:11.084219 dramc_set_vcore_voltage set vcore to 650000
6034 11:45:11.084319 Read voltage for 400, 6
6035 11:45:11.087189 Vio18 = 0
6036 11:45:11.087277 Vcore = 650000
6037 11:45:11.087362 Vdram = 0
6038 11:45:11.090627 Vddq = 0
6039 11:45:11.090737 Vmddr = 0
6040 11:45:11.094137 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6041 11:45:11.100538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6042 11:45:11.104373 MEM_TYPE=3, freq_sel=20
6043 11:45:11.106960 sv_algorithm_assistance_LP4_800
6044 11:45:11.110551 ============ PULL DRAM RESETB DOWN ============
6045 11:45:11.113745 ========== PULL DRAM RESETB DOWN end =========
6046 11:45:11.120957 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6047 11:45:11.123791 ===================================
6048 11:45:11.123888 LPDDR4 DRAM CONFIGURATION
6049 11:45:11.127101 ===================================
6050 11:45:11.130357 EX_ROW_EN[0] = 0x0
6051 11:45:11.130482 EX_ROW_EN[1] = 0x0
6052 11:45:11.133772 LP4Y_EN = 0x0
6053 11:45:11.133870 WORK_FSP = 0x0
6054 11:45:11.136893 WL = 0x2
6055 11:45:11.136985 RL = 0x2
6056 11:45:11.140509 BL = 0x2
6057 11:45:11.143930 RPST = 0x0
6058 11:45:11.144030 RD_PRE = 0x0
6059 11:45:11.147148 WR_PRE = 0x1
6060 11:45:11.147255 WR_PST = 0x0
6061 11:45:11.151015 DBI_WR = 0x0
6062 11:45:11.151114 DBI_RD = 0x0
6063 11:45:11.154110 OTF = 0x1
6064 11:45:11.157018 ===================================
6065 11:45:11.160338 ===================================
6066 11:45:11.160433 ANA top config
6067 11:45:11.163693 ===================================
6068 11:45:11.167055 DLL_ASYNC_EN = 0
6069 11:45:11.170450 ALL_SLAVE_EN = 1
6070 11:45:11.170550 NEW_RANK_MODE = 1
6071 11:45:11.174011 DLL_IDLE_MODE = 1
6072 11:45:11.177445 LP45_APHY_COMB_EN = 1
6073 11:45:11.180649 TX_ODT_DIS = 1
6074 11:45:11.180748 NEW_8X_MODE = 1
6075 11:45:11.184010 ===================================
6076 11:45:11.187160 ===================================
6077 11:45:11.190790 data_rate = 800
6078 11:45:11.193946 CKR = 1
6079 11:45:11.197280 DQ_P2S_RATIO = 4
6080 11:45:11.200664 ===================================
6081 11:45:11.203854 CA_P2S_RATIO = 4
6082 11:45:11.207438 DQ_CA_OPEN = 0
6083 11:45:11.207536 DQ_SEMI_OPEN = 1
6084 11:45:11.210652 CA_SEMI_OPEN = 1
6085 11:45:11.213921 CA_FULL_RATE = 0
6086 11:45:11.217486 DQ_CKDIV4_EN = 0
6087 11:45:11.220484 CA_CKDIV4_EN = 1
6088 11:45:11.220568 CA_PREDIV_EN = 0
6089 11:45:11.224146 PH8_DLY = 0
6090 11:45:11.227588 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6091 11:45:11.230570 DQ_AAMCK_DIV = 0
6092 11:45:11.234106 CA_AAMCK_DIV = 0
6093 11:45:11.237181 CA_ADMCK_DIV = 4
6094 11:45:11.237308 DQ_TRACK_CA_EN = 0
6095 11:45:11.240347 CA_PICK = 800
6096 11:45:11.244750 CA_MCKIO = 400
6097 11:45:11.247584 MCKIO_SEMI = 400
6098 11:45:11.250622 PLL_FREQ = 3016
6099 11:45:11.253924 DQ_UI_PI_RATIO = 32
6100 11:45:11.257789 CA_UI_PI_RATIO = 32
6101 11:45:11.260622 ===================================
6102 11:45:11.263897 ===================================
6103 11:45:11.264023 memory_type:LPDDR4
6104 11:45:11.267057 GP_NUM : 10
6105 11:45:11.270671 SRAM_EN : 1
6106 11:45:11.270754 MD32_EN : 0
6107 11:45:11.273802 ===================================
6108 11:45:11.277150 [ANA_INIT] >>>>>>>>>>>>>>
6109 11:45:11.280746 <<<<<< [CONFIGURE PHASE]: ANA_TX
6110 11:45:11.283963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6111 11:45:11.287417 ===================================
6112 11:45:11.290725 data_rate = 800,PCW = 0X7400
6113 11:45:11.294409 ===================================
6114 11:45:11.297448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6115 11:45:11.300763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 11:45:11.313954 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 11:45:11.317617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6118 11:45:11.320723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6119 11:45:11.324667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6120 11:45:11.327830 [ANA_INIT] flow start
6121 11:45:11.327954 [ANA_INIT] PLL >>>>>>>>
6122 11:45:11.330976 [ANA_INIT] PLL <<<<<<<<
6123 11:45:11.334333 [ANA_INIT] MIDPI >>>>>>>>
6124 11:45:11.334425 [ANA_INIT] MIDPI <<<<<<<<
6125 11:45:11.337652 [ANA_INIT] DLL >>>>>>>>
6126 11:45:11.341259 [ANA_INIT] flow end
6127 11:45:11.344484 ============ LP4 DIFF to SE enter ============
6128 11:45:11.347534 ============ LP4 DIFF to SE exit ============
6129 11:45:11.350715 [ANA_INIT] <<<<<<<<<<<<<
6130 11:45:11.354675 [Flow] Enable top DCM control >>>>>
6131 11:45:11.357897 [Flow] Enable top DCM control <<<<<
6132 11:45:11.361346 Enable DLL master slave shuffle
6133 11:45:11.364195 ==============================================================
6134 11:45:11.368191 Gating Mode config
6135 11:45:11.374215 ==============================================================
6136 11:45:11.374318 Config description:
6137 11:45:11.384548 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6138 11:45:11.391038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6139 11:45:11.394527 SELPH_MODE 0: By rank 1: By Phase
6140 11:45:11.401332 ==============================================================
6141 11:45:11.404220 GAT_TRACK_EN = 0
6142 11:45:11.407610 RX_GATING_MODE = 2
6143 11:45:11.411110 RX_GATING_TRACK_MODE = 2
6144 11:45:11.414383 SELPH_MODE = 1
6145 11:45:11.417584 PICG_EARLY_EN = 1
6146 11:45:11.420844 VALID_LAT_VALUE = 1
6147 11:45:11.424331 ==============================================================
6148 11:45:11.427422 Enter into Gating configuration >>>>
6149 11:45:11.430872 Exit from Gating configuration <<<<
6150 11:45:11.434419 Enter into DVFS_PRE_config >>>>>
6151 11:45:11.444244 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6152 11:45:11.447411 Exit from DVFS_PRE_config <<<<<
6153 11:45:11.451449 Enter into PICG configuration >>>>
6154 11:45:11.454689 Exit from PICG configuration <<<<
6155 11:45:11.457815 [RX_INPUT] configuration >>>>>
6156 11:45:11.461313 [RX_INPUT] configuration <<<<<
6157 11:45:11.464444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6158 11:45:11.470993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6159 11:45:11.477654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6160 11:45:11.485179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6161 11:45:11.491075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 11:45:11.494565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 11:45:11.501225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6164 11:45:11.504375 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6165 11:45:11.507757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6166 11:45:11.511223 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6167 11:45:11.518061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6168 11:45:11.521164 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 11:45:11.524711 ===================================
6170 11:45:11.527911 LPDDR4 DRAM CONFIGURATION
6171 11:45:11.531414 ===================================
6172 11:45:11.531529 EX_ROW_EN[0] = 0x0
6173 11:45:11.534908 EX_ROW_EN[1] = 0x0
6174 11:45:11.535002 LP4Y_EN = 0x0
6175 11:45:11.538112 WORK_FSP = 0x0
6176 11:45:11.538221 WL = 0x2
6177 11:45:11.541190 RL = 0x2
6178 11:45:11.541294 BL = 0x2
6179 11:45:11.544954 RPST = 0x0
6180 11:45:11.545043 RD_PRE = 0x0
6181 11:45:11.547991 WR_PRE = 0x1
6182 11:45:11.548072 WR_PST = 0x0
6183 11:45:11.551629 DBI_WR = 0x0
6184 11:45:11.551705 DBI_RD = 0x0
6185 11:45:11.554703 OTF = 0x1
6186 11:45:11.558160 ===================================
6187 11:45:11.561486 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6188 11:45:11.564729 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6189 11:45:11.571390 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 11:45:11.574702 ===================================
6191 11:45:11.574814 LPDDR4 DRAM CONFIGURATION
6192 11:45:11.578100 ===================================
6193 11:45:11.581451 EX_ROW_EN[0] = 0x10
6194 11:45:11.584788 EX_ROW_EN[1] = 0x0
6195 11:45:11.584907 LP4Y_EN = 0x0
6196 11:45:11.588182 WORK_FSP = 0x0
6197 11:45:11.588262 WL = 0x2
6198 11:45:11.591618 RL = 0x2
6199 11:45:11.591721 BL = 0x2
6200 11:45:11.594813 RPST = 0x0
6201 11:45:11.594923 RD_PRE = 0x0
6202 11:45:11.598682 WR_PRE = 0x1
6203 11:45:11.598782 WR_PST = 0x0
6204 11:45:11.601634 DBI_WR = 0x0
6205 11:45:11.601716 DBI_RD = 0x0
6206 11:45:11.605091 OTF = 0x1
6207 11:45:11.608585 ===================================
6208 11:45:11.615036 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6209 11:45:11.618067 nWR fixed to 30
6210 11:45:11.618182 [ModeRegInit_LP4] CH0 RK0
6211 11:45:11.621649 [ModeRegInit_LP4] CH0 RK1
6212 11:45:11.624972 [ModeRegInit_LP4] CH1 RK0
6213 11:45:11.625056 [ModeRegInit_LP4] CH1 RK1
6214 11:45:11.628394 match AC timing 19
6215 11:45:11.631467 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6216 11:45:11.635235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6217 11:45:11.642334 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6218 11:45:11.644767 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6219 11:45:11.651336 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6220 11:45:11.651449 ==
6221 11:45:11.654838 Dram Type= 6, Freq= 0, CH_0, rank 0
6222 11:45:11.658105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 11:45:11.658194 ==
6224 11:45:11.664687 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 11:45:11.668194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6226 11:45:11.671562 [CA 0] Center 36 (8~64) winsize 57
6227 11:45:11.674996 [CA 1] Center 36 (8~64) winsize 57
6228 11:45:11.678009 [CA 2] Center 36 (8~64) winsize 57
6229 11:45:11.681611 [CA 3] Center 36 (8~64) winsize 57
6230 11:45:11.684791 [CA 4] Center 36 (8~64) winsize 57
6231 11:45:11.688479 [CA 5] Center 36 (8~64) winsize 57
6232 11:45:11.688575
6233 11:45:11.692066 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6234 11:45:11.692149
6235 11:45:11.694825 [CATrainingPosCal] consider 1 rank data
6236 11:45:11.698277 u2DelayCellTimex100 = 270/100 ps
6237 11:45:11.701709 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 11:45:11.705198 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 11:45:11.708577 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 11:45:11.715360 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:45:11.718536 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:45:11.722008 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:45:11.722105
6244 11:45:11.725529 CA PerBit enable=1, Macro0, CA PI delay=36
6245 11:45:11.725642
6246 11:45:11.728670 [CBTSetCACLKResult] CA Dly = 36
6247 11:45:11.728748 CS Dly: 1 (0~32)
6248 11:45:11.728811 ==
6249 11:45:11.731879 Dram Type= 6, Freq= 0, CH_0, rank 1
6250 11:45:11.735223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 11:45:11.738642 ==
6252 11:45:11.741612 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 11:45:11.748601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6254 11:45:11.752326 [CA 0] Center 36 (8~64) winsize 57
6255 11:45:11.755322 [CA 1] Center 36 (8~64) winsize 57
6256 11:45:11.758351 [CA 2] Center 36 (8~64) winsize 57
6257 11:45:11.761724 [CA 3] Center 36 (8~64) winsize 57
6258 11:45:11.765014 [CA 4] Center 36 (8~64) winsize 57
6259 11:45:11.768483 [CA 5] Center 36 (8~64) winsize 57
6260 11:45:11.768577
6261 11:45:11.771879 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6262 11:45:11.771968
6263 11:45:11.775099 [CATrainingPosCal] consider 2 rank data
6264 11:45:11.778388 u2DelayCellTimex100 = 270/100 ps
6265 11:45:11.781931 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 11:45:11.785100 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 11:45:11.788261 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 11:45:11.791689 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 11:45:11.795851 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 11:45:11.798532 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:45:11.798623
6272 11:45:11.802034 CA PerBit enable=1, Macro0, CA PI delay=36
6273 11:45:11.802124
6274 11:45:11.805437 [CBTSetCACLKResult] CA Dly = 36
6275 11:45:11.808228 CS Dly: 1 (0~32)
6276 11:45:11.808347
6277 11:45:11.811851 ----->DramcWriteLeveling(PI) begin...
6278 11:45:11.811930 ==
6279 11:45:11.815373 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 11:45:11.818463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 11:45:11.818545 ==
6282 11:45:11.821889 Write leveling (Byte 0): 40 => 8
6283 11:45:11.825072 Write leveling (Byte 1): 32 => 0
6284 11:45:11.828513 DramcWriteLeveling(PI) end<-----
6285 11:45:11.828611
6286 11:45:11.828687 ==
6287 11:45:11.831958 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 11:45:11.835303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 11:45:11.835397 ==
6290 11:45:11.838613 [Gating] SW mode calibration
6291 11:45:11.845257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6292 11:45:11.852207 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6293 11:45:11.855476 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 11:45:11.858784 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 11:45:11.865467 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 11:45:11.868621 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 11:45:11.872577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 11:45:11.878970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 11:45:11.882217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 11:45:11.885539 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 11:45:11.892197 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 11:45:11.892312 Total UI for P1: 0, mck2ui 16
6303 11:45:11.898707 best dqsien dly found for B0: ( 0, 14, 24)
6304 11:45:11.898836 Total UI for P1: 0, mck2ui 16
6305 11:45:11.905102 best dqsien dly found for B1: ( 0, 14, 24)
6306 11:45:11.908747 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6307 11:45:11.912351 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6308 11:45:11.912451
6309 11:45:11.915233 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 11:45:11.918912 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 11:45:11.921686 [Gating] SW calibration Done
6312 11:45:11.921776 ==
6313 11:45:11.925492 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:45:11.928939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:45:11.929029 ==
6316 11:45:11.931897 RX Vref Scan: 0
6317 11:45:11.931985
6318 11:45:11.932049 RX Vref 0 -> 0, step: 1
6319 11:45:11.932108
6320 11:45:11.935626 RX Delay -410 -> 252, step: 16
6321 11:45:11.942670 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6322 11:45:11.945586 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6323 11:45:11.948582 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6324 11:45:11.952156 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6325 11:45:11.955381 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6326 11:45:11.961844 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6327 11:45:11.965501 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6328 11:45:11.968470 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6329 11:45:11.971893 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6330 11:45:11.978520 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6331 11:45:11.981909 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6332 11:45:11.985277 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6333 11:45:11.988703 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6334 11:45:11.995246 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6335 11:45:11.998981 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6336 11:45:12.002083 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6337 11:45:12.002195 ==
6338 11:45:12.005456 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:45:12.011934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:45:12.012054 ==
6341 11:45:12.012135 DQS Delay:
6342 11:45:12.015383 DQS0 = 35, DQS1 = 51
6343 11:45:12.015499 DQM Delay:
6344 11:45:12.015563 DQM0 = 6, DQM1 = 10
6345 11:45:12.019052 DQ Delay:
6346 11:45:12.021828 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6347 11:45:12.021929 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6348 11:45:12.025323 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6349 11:45:12.028539 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6350 11:45:12.028629
6351 11:45:12.028693
6352 11:45:12.032192 ==
6353 11:45:12.032298 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 11:45:12.039120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 11:45:12.039233 ==
6356 11:45:12.039296
6357 11:45:12.039354
6358 11:45:12.042201 TX Vref Scan disable
6359 11:45:12.042286 == TX Byte 0 ==
6360 11:45:12.045327 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 11:45:12.051981 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 11:45:12.052090 == TX Byte 1 ==
6363 11:45:12.055696 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6364 11:45:12.062605 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6365 11:45:12.062721 ==
6366 11:45:12.065684 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 11:45:12.068892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 11:45:12.068986 ==
6369 11:45:12.069053
6370 11:45:12.069112
6371 11:45:12.072084 TX Vref Scan disable
6372 11:45:12.072170 == TX Byte 0 ==
6373 11:45:12.075455 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 11:45:12.082413 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 11:45:12.082554 == TX Byte 1 ==
6376 11:45:12.086100 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6377 11:45:12.092062 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6378 11:45:12.092166
6379 11:45:12.092234 [DATLAT]
6380 11:45:12.092294 Freq=400, CH0 RK0
6381 11:45:12.092353
6382 11:45:12.095678 DATLAT Default: 0xf
6383 11:45:12.095763 0, 0xFFFF, sum = 0
6384 11:45:12.098688 1, 0xFFFF, sum = 0
6385 11:45:12.102348 2, 0xFFFF, sum = 0
6386 11:45:12.102444 3, 0xFFFF, sum = 0
6387 11:45:12.105424 4, 0xFFFF, sum = 0
6388 11:45:12.105511 5, 0xFFFF, sum = 0
6389 11:45:12.108959 6, 0xFFFF, sum = 0
6390 11:45:12.109047 7, 0xFFFF, sum = 0
6391 11:45:12.112276 8, 0xFFFF, sum = 0
6392 11:45:12.112363 9, 0xFFFF, sum = 0
6393 11:45:12.115639 10, 0xFFFF, sum = 0
6394 11:45:12.115727 11, 0xFFFF, sum = 0
6395 11:45:12.119415 12, 0xFFFF, sum = 0
6396 11:45:12.119504 13, 0x0, sum = 1
6397 11:45:12.122164 14, 0x0, sum = 2
6398 11:45:12.122251 15, 0x0, sum = 3
6399 11:45:12.125870 16, 0x0, sum = 4
6400 11:45:12.125959 best_step = 14
6401 11:45:12.126025
6402 11:45:12.126084 ==
6403 11:45:12.129101 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:45:12.132516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:45:12.132639 ==
6406 11:45:12.135634 RX Vref Scan: 1
6407 11:45:12.135723
6408 11:45:12.139013 RX Vref 0 -> 0, step: 1
6409 11:45:12.139099
6410 11:45:12.139165 RX Delay -343 -> 252, step: 8
6411 11:45:12.139226
6412 11:45:12.142206 Set Vref, RX VrefLevel [Byte0]: 53
6413 11:45:12.145959 [Byte1]: 51
6414 11:45:12.151120
6415 11:45:12.151219 Final RX Vref Byte 0 = 53 to rank0
6416 11:45:12.154507 Final RX Vref Byte 1 = 51 to rank0
6417 11:45:12.157726 Final RX Vref Byte 0 = 53 to rank1
6418 11:45:12.160892 Final RX Vref Byte 1 = 51 to rank1==
6419 11:45:12.164628 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:45:12.171565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:45:12.171680 ==
6422 11:45:12.171750 DQS Delay:
6423 11:45:12.174210 DQS0 = 44, DQS1 = 60
6424 11:45:12.174294 DQM Delay:
6425 11:45:12.174359 DQM0 = 11, DQM1 = 14
6426 11:45:12.177814 DQ Delay:
6427 11:45:12.181241 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6428 11:45:12.181332 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6429 11:45:12.184127 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6430 11:45:12.187737 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6431 11:45:12.190820
6432 11:45:12.190931
6433 11:45:12.197355 [DQSOSCAuto] RK0, (LSB)MR18= 0x804f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6434 11:45:12.200801 CH0 RK0: MR19=C0C, MR18=804F
6435 11:45:12.207715 CH0_RK0: MR19=0xC0C, MR18=0x804F, DQSOSC=393, MR23=63, INC=382, DEC=254
6436 11:45:12.207835 ==
6437 11:45:12.210985 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 11:45:12.214648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 11:45:12.214743 ==
6440 11:45:12.217232 [Gating] SW mode calibration
6441 11:45:12.224218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6442 11:45:12.231372 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6443 11:45:12.233964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 11:45:12.237418 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 11:45:12.243962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 11:45:12.247606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 11:45:12.251042 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 11:45:12.257704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 11:45:12.260420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 11:45:12.264081 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 11:45:12.267459 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 11:45:12.270888 Total UI for P1: 0, mck2ui 16
6453 11:45:12.274244 best dqsien dly found for B0: ( 0, 14, 24)
6454 11:45:12.277194 Total UI for P1: 0, mck2ui 16
6455 11:45:12.280683 best dqsien dly found for B1: ( 0, 14, 24)
6456 11:45:12.283924 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6457 11:45:12.290717 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6458 11:45:12.290870
6459 11:45:12.294159 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 11:45:12.297173 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 11:45:12.300847 [Gating] SW calibration Done
6462 11:45:12.300936 ==
6463 11:45:12.303946 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:45:12.307267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:45:12.307350 ==
6466 11:45:12.307414 RX Vref Scan: 0
6467 11:45:12.307476
6468 11:45:12.310775 RX Vref 0 -> 0, step: 1
6469 11:45:12.310893
6470 11:45:12.313970 RX Delay -410 -> 252, step: 16
6471 11:45:12.317732 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6472 11:45:12.324304 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6473 11:45:12.327636 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6474 11:45:12.330803 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6475 11:45:12.334425 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6476 11:45:12.340629 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6477 11:45:12.344015 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6478 11:45:12.347397 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6479 11:45:12.350973 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6480 11:45:12.354024 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6481 11:45:12.360990 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6482 11:45:12.364152 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6483 11:45:12.367554 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6484 11:45:12.374309 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6485 11:45:12.377553 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6486 11:45:12.381145 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6487 11:45:12.381255 ==
6488 11:45:12.384294 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:45:12.387940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:45:12.388030 ==
6491 11:45:12.391421 DQS Delay:
6492 11:45:12.391501 DQS0 = 43, DQS1 = 51
6493 11:45:12.394277 DQM Delay:
6494 11:45:12.394376 DQM0 = 11, DQM1 = 10
6495 11:45:12.394464 DQ Delay:
6496 11:45:12.397961 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6497 11:45:12.401268 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6498 11:45:12.404060 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6499 11:45:12.407901 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6500 11:45:12.408059
6501 11:45:12.408122
6502 11:45:12.408180 ==
6503 11:45:12.411009 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 11:45:12.417537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 11:45:12.417640 ==
6506 11:45:12.417746
6507 11:45:12.417804
6508 11:45:12.417860 TX Vref Scan disable
6509 11:45:12.421013 == TX Byte 0 ==
6510 11:45:12.424458 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6511 11:45:12.427745 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6512 11:45:12.431161 == TX Byte 1 ==
6513 11:45:12.434536 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6514 11:45:12.437859 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6515 11:45:12.437963 ==
6516 11:45:12.440917 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 11:45:12.444517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 11:45:12.447716 ==
6519 11:45:12.447824
6520 11:45:12.447916
6521 11:45:12.448001 TX Vref Scan disable
6522 11:45:12.450844 == TX Byte 0 ==
6523 11:45:12.454394 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6524 11:45:12.457753 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6525 11:45:12.461063 == TX Byte 1 ==
6526 11:45:12.464255 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6527 11:45:12.467693 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6528 11:45:12.467791
6529 11:45:12.467878 [DATLAT]
6530 11:45:12.470968 Freq=400, CH0 RK1
6531 11:45:12.471055
6532 11:45:12.474383 DATLAT Default: 0xe
6533 11:45:12.474493 0, 0xFFFF, sum = 0
6534 11:45:12.477881 1, 0xFFFF, sum = 0
6535 11:45:12.477974 2, 0xFFFF, sum = 0
6536 11:45:12.481416 3, 0xFFFF, sum = 0
6537 11:45:12.481507 4, 0xFFFF, sum = 0
6538 11:45:12.484292 5, 0xFFFF, sum = 0
6539 11:45:12.484382 6, 0xFFFF, sum = 0
6540 11:45:12.487994 7, 0xFFFF, sum = 0
6541 11:45:12.488086 8, 0xFFFF, sum = 0
6542 11:45:12.491303 9, 0xFFFF, sum = 0
6543 11:45:12.491393 10, 0xFFFF, sum = 0
6544 11:45:12.494471 11, 0xFFFF, sum = 0
6545 11:45:12.494562 12, 0xFFFF, sum = 0
6546 11:45:12.497811 13, 0x0, sum = 1
6547 11:45:12.497901 14, 0x0, sum = 2
6548 11:45:12.501336 15, 0x0, sum = 3
6549 11:45:12.501432 16, 0x0, sum = 4
6550 11:45:12.504402 best_step = 14
6551 11:45:12.504492
6552 11:45:12.504578 ==
6553 11:45:12.508068 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:45:12.511522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:45:12.511612 ==
6556 11:45:12.514690 RX Vref Scan: 0
6557 11:45:12.514773
6558 11:45:12.514838 RX Vref 0 -> 0, step: 1
6559 11:45:12.514906
6560 11:45:12.517914 RX Delay -343 -> 252, step: 8
6561 11:45:12.525629 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6562 11:45:12.529014 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6563 11:45:12.532144 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6564 11:45:12.535690 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6565 11:45:12.541873 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6566 11:45:12.545200 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6567 11:45:12.548911 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6568 11:45:12.552415 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6569 11:45:12.558608 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6570 11:45:12.562545 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6571 11:45:12.565142 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6572 11:45:12.568593 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6573 11:45:12.575532 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6574 11:45:12.578835 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6575 11:45:12.581995 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6576 11:45:12.588683 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6577 11:45:12.588801 ==
6578 11:45:12.591937 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 11:45:12.595674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 11:45:12.595767 ==
6581 11:45:12.595852 DQS Delay:
6582 11:45:12.598834 DQS0 = 48, DQS1 = 60
6583 11:45:12.598943 DQM Delay:
6584 11:45:12.602283 DQM0 = 13, DQM1 = 13
6585 11:45:12.602388 DQ Delay:
6586 11:45:12.605536 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6587 11:45:12.608840 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6588 11:45:12.612105 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6589 11:45:12.615673 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6590 11:45:12.615769
6591 11:45:12.615854
6592 11:45:12.622124 [DQSOSCAuto] RK1, (LSB)MR18= 0x9264, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6593 11:45:12.625379 CH0 RK1: MR19=C0C, MR18=9264
6594 11:45:12.632131 CH0_RK1: MR19=0xC0C, MR18=0x9264, DQSOSC=391, MR23=63, INC=386, DEC=257
6595 11:45:12.635451 [RxdqsGatingPostProcess] freq 400
6596 11:45:12.638780 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6597 11:45:12.642093 best DQS0 dly(2T, 0.5T) = (0, 10)
6598 11:45:12.645572 best DQS1 dly(2T, 0.5T) = (0, 10)
6599 11:45:12.648611 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6600 11:45:12.652273 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6601 11:45:12.655423 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 11:45:12.659129 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 11:45:12.662177 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 11:45:12.665456 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 11:45:12.668819 Pre-setting of DQS Precalculation
6606 11:45:12.672198 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6607 11:45:12.675614 ==
6608 11:45:12.675697 Dram Type= 6, Freq= 0, CH_1, rank 0
6609 11:45:12.682601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 11:45:12.682702 ==
6611 11:45:12.685289 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 11:45:12.692196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6613 11:45:12.695922 [CA 0] Center 36 (8~64) winsize 57
6614 11:45:12.698768 [CA 1] Center 36 (8~64) winsize 57
6615 11:45:12.702345 [CA 2] Center 36 (8~64) winsize 57
6616 11:45:12.705916 [CA 3] Center 36 (8~64) winsize 57
6617 11:45:12.709194 [CA 4] Center 36 (8~64) winsize 57
6618 11:45:12.712498 [CA 5] Center 36 (8~64) winsize 57
6619 11:45:12.712586
6620 11:45:12.715517 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6621 11:45:12.715591
6622 11:45:12.719033 [CATrainingPosCal] consider 1 rank data
6623 11:45:12.722245 u2DelayCellTimex100 = 270/100 ps
6624 11:45:12.725675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 11:45:12.728932 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 11:45:12.732502 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 11:45:12.735869 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:45:12.739345 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:45:12.742221 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:45:12.742302
6631 11:45:12.749043 CA PerBit enable=1, Macro0, CA PI delay=36
6632 11:45:12.749173
6633 11:45:12.752801 [CBTSetCACLKResult] CA Dly = 36
6634 11:45:12.752880 CS Dly: 1 (0~32)
6635 11:45:12.752965 ==
6636 11:45:12.755839 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 11:45:12.759379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 11:45:12.759467 ==
6639 11:45:12.765984 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 11:45:12.772656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6641 11:45:12.775522 [CA 0] Center 36 (8~64) winsize 57
6642 11:45:12.779006 [CA 1] Center 36 (8~64) winsize 57
6643 11:45:12.782152 [CA 2] Center 36 (8~64) winsize 57
6644 11:45:12.785784 [CA 3] Center 36 (8~64) winsize 57
6645 11:45:12.785871 [CA 4] Center 36 (8~64) winsize 57
6646 11:45:12.789541 [CA 5] Center 36 (8~64) winsize 57
6647 11:45:12.789620
6648 11:45:12.795790 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6649 11:45:12.795880
6650 11:45:12.798973 [CATrainingPosCal] consider 2 rank data
6651 11:45:12.799049 u2DelayCellTimex100 = 270/100 ps
6652 11:45:12.805944 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 11:45:12.809324 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 11:45:12.812467 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 11:45:12.815955 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 11:45:12.819229 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 11:45:12.822657 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:45:12.822766
6659 11:45:12.825868 CA PerBit enable=1, Macro0, CA PI delay=36
6660 11:45:12.825946
6661 11:45:12.829691 [CBTSetCACLKResult] CA Dly = 36
6662 11:45:12.829794 CS Dly: 1 (0~32)
6663 11:45:12.832550
6664 11:45:12.835927 ----->DramcWriteLeveling(PI) begin...
6665 11:45:12.836029 ==
6666 11:45:12.839456 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 11:45:12.842999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:45:12.843108 ==
6669 11:45:12.845843 Write leveling (Byte 0): 40 => 8
6670 11:45:12.849604 Write leveling (Byte 1): 40 => 8
6671 11:45:12.853379 DramcWriteLeveling(PI) end<-----
6672 11:45:12.853486
6673 11:45:12.853575 ==
6674 11:45:12.856276 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 11:45:12.859357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 11:45:12.859469 ==
6677 11:45:12.863167 [Gating] SW mode calibration
6678 11:45:12.869762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6679 11:45:12.872812 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6680 11:45:12.879912 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 11:45:12.883006 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 11:45:12.886118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 11:45:12.893163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 11:45:12.896679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 11:45:12.900068 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 11:45:12.906176 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 11:45:12.909657 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 11:45:12.912794 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 11:45:12.916480 Total UI for P1: 0, mck2ui 16
6690 11:45:12.919414 best dqsien dly found for B0: ( 0, 14, 24)
6691 11:45:12.923056 Total UI for P1: 0, mck2ui 16
6692 11:45:12.926235 best dqsien dly found for B1: ( 0, 14, 24)
6693 11:45:12.929892 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6694 11:45:12.933323 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6695 11:45:12.933440
6696 11:45:12.939833 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 11:45:12.942997 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 11:45:12.943085 [Gating] SW calibration Done
6699 11:45:12.946089 ==
6700 11:45:12.949416 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:45:12.952954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:45:12.953041 ==
6703 11:45:12.953112 RX Vref Scan: 0
6704 11:45:12.953171
6705 11:45:12.956366 RX Vref 0 -> 0, step: 1
6706 11:45:12.956443
6707 11:45:12.959784 RX Delay -410 -> 252, step: 16
6708 11:45:12.963388 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6709 11:45:12.966423 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6710 11:45:12.973023 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6711 11:45:12.976514 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6712 11:45:12.979788 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6713 11:45:12.983019 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6714 11:45:12.990172 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6715 11:45:12.993124 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6716 11:45:12.996406 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6717 11:45:13.000020 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6718 11:45:13.006325 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6719 11:45:13.009849 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6720 11:45:13.013124 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6721 11:45:13.016281 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6722 11:45:13.023633 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6723 11:45:13.026243 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6724 11:45:13.026343 ==
6725 11:45:13.030017 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:45:13.033525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:45:13.033659 ==
6728 11:45:13.036778 DQS Delay:
6729 11:45:13.036894 DQS0 = 51, DQS1 = 59
6730 11:45:13.036988 DQM Delay:
6731 11:45:13.040061 DQM0 = 18, DQM1 = 16
6732 11:45:13.040149 DQ Delay:
6733 11:45:13.043412 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6734 11:45:13.046509 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6735 11:45:13.049873 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6736 11:45:13.053096 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6737 11:45:13.053181
6738 11:45:13.053248
6739 11:45:13.053315 ==
6740 11:45:13.056489 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 11:45:13.063142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 11:45:13.063261 ==
6743 11:45:13.063339
6744 11:45:13.063400
6745 11:45:13.063459 TX Vref Scan disable
6746 11:45:13.066627 == TX Byte 0 ==
6747 11:45:13.069948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 11:45:13.073249 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 11:45:13.076407 == TX Byte 1 ==
6750 11:45:13.079797 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 11:45:13.083486 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 11:45:13.083599 ==
6753 11:45:13.086358 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 11:45:13.093426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 11:45:13.093541 ==
6756 11:45:13.093615
6757 11:45:13.093682
6758 11:45:13.093742 TX Vref Scan disable
6759 11:45:13.096296 == TX Byte 0 ==
6760 11:45:13.100054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 11:45:13.103460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 11:45:13.106844 == TX Byte 1 ==
6763 11:45:13.110281 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 11:45:13.113373 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 11:45:13.113467
6766 11:45:13.116647 [DATLAT]
6767 11:45:13.116727 Freq=400, CH1 RK0
6768 11:45:13.116797
6769 11:45:13.119968 DATLAT Default: 0xf
6770 11:45:13.120043 0, 0xFFFF, sum = 0
6771 11:45:13.123216 1, 0xFFFF, sum = 0
6772 11:45:13.123351 2, 0xFFFF, sum = 0
6773 11:45:13.126805 3, 0xFFFF, sum = 0
6774 11:45:13.126983 4, 0xFFFF, sum = 0
6775 11:45:13.130068 5, 0xFFFF, sum = 0
6776 11:45:13.130237 6, 0xFFFF, sum = 0
6777 11:45:13.133253 7, 0xFFFF, sum = 0
6778 11:45:13.133377 8, 0xFFFF, sum = 0
6779 11:45:13.136893 9, 0xFFFF, sum = 0
6780 11:45:13.137017 10, 0xFFFF, sum = 0
6781 11:45:13.140171 11, 0xFFFF, sum = 0
6782 11:45:13.140260 12, 0xFFFF, sum = 0
6783 11:45:13.144001 13, 0x0, sum = 1
6784 11:45:13.144095 14, 0x0, sum = 2
6785 11:45:13.146796 15, 0x0, sum = 3
6786 11:45:13.146905 16, 0x0, sum = 4
6787 11:45:13.150017 best_step = 14
6788 11:45:13.150130
6789 11:45:13.150223 ==
6790 11:45:13.153850 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:45:13.156660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:45:13.156752 ==
6793 11:45:13.160066 RX Vref Scan: 1
6794 11:45:13.160147
6795 11:45:13.160214 RX Vref 0 -> 0, step: 1
6796 11:45:13.160280
6797 11:45:13.163253 RX Delay -359 -> 252, step: 8
6798 11:45:13.163344
6799 11:45:13.166802 Set Vref, RX VrefLevel [Byte0]: 56
6800 11:45:13.169983 [Byte1]: 54
6801 11:45:13.174528
6802 11:45:13.174651 Final RX Vref Byte 0 = 56 to rank0
6803 11:45:13.178385 Final RX Vref Byte 1 = 54 to rank0
6804 11:45:13.181197 Final RX Vref Byte 0 = 56 to rank1
6805 11:45:13.184878 Final RX Vref Byte 1 = 54 to rank1==
6806 11:45:13.187838 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:45:13.194706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:45:13.194932 ==
6809 11:45:13.195064 DQS Delay:
6810 11:45:13.195199 DQS0 = 48, DQS1 = 64
6811 11:45:13.198057 DQM Delay:
6812 11:45:13.198220 DQM0 = 12, DQM1 = 16
6813 11:45:13.201274 DQ Delay:
6814 11:45:13.204858 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6815 11:45:13.204992 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6816 11:45:13.208090 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =16
6817 11:45:13.211561 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6818 11:45:13.211673
6819 11:45:13.211768
6820 11:45:13.221526 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c34, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6821 11:45:13.224720 CH1 RK0: MR19=C0C, MR18=8C34
6822 11:45:13.231257 CH1_RK0: MR19=0xC0C, MR18=0x8C34, DQSOSC=392, MR23=63, INC=384, DEC=256
6823 11:45:13.231476 ==
6824 11:45:13.234819 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 11:45:13.238255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 11:45:13.238408 ==
6827 11:45:13.241580 [Gating] SW mode calibration
6828 11:45:13.248045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6829 11:45:13.251652 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6830 11:45:13.257861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 11:45:13.261391 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 11:45:13.264775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 11:45:13.271364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 11:45:13.274667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 11:45:13.278232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 11:45:13.284474 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 11:45:13.288002 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 11:45:13.291606 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 11:45:13.294519 Total UI for P1: 0, mck2ui 16
6840 11:45:13.297869 best dqsien dly found for B0: ( 0, 14, 24)
6841 11:45:13.301452 Total UI for P1: 0, mck2ui 16
6842 11:45:13.304827 best dqsien dly found for B1: ( 0, 14, 24)
6843 11:45:13.307914 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6844 11:45:13.311626 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6845 11:45:13.311730
6846 11:45:13.314619 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 11:45:13.321670 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 11:45:13.321781 [Gating] SW calibration Done
6849 11:45:13.321848 ==
6850 11:45:13.324976 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:45:13.331865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:45:13.332001 ==
6853 11:45:13.332129 RX Vref Scan: 0
6854 11:45:13.332216
6855 11:45:13.335261 RX Vref 0 -> 0, step: 1
6856 11:45:13.335372
6857 11:45:13.338463 RX Delay -410 -> 252, step: 16
6858 11:45:13.341509 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6859 11:45:13.345151 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6860 11:45:13.351665 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6861 11:45:13.354695 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6862 11:45:13.358481 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6863 11:45:13.361481 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6864 11:45:13.368395 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6865 11:45:13.371587 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6866 11:45:13.374776 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6867 11:45:13.378595 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6868 11:45:13.384668 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6869 11:45:13.388250 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6870 11:45:13.391536 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6871 11:45:13.395182 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6872 11:45:13.401660 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6873 11:45:13.404817 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6874 11:45:13.404905 ==
6875 11:45:13.408027 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:45:13.411486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:45:13.411572 ==
6878 11:45:13.414876 DQS Delay:
6879 11:45:13.414954 DQS0 = 43, DQS1 = 51
6880 11:45:13.415017 DQM Delay:
6881 11:45:13.418239 DQM0 = 9, DQM1 = 13
6882 11:45:13.418338 DQ Delay:
6883 11:45:13.421813 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6884 11:45:13.425397 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6885 11:45:13.428249 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6886 11:45:13.431704 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6887 11:45:13.431835
6888 11:45:13.431931
6889 11:45:13.432031 ==
6890 11:45:13.435035 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 11:45:13.438563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 11:45:13.438668 ==
6893 11:45:13.438735
6894 11:45:13.441716
6895 11:45:13.441794 TX Vref Scan disable
6896 11:45:13.445354 == TX Byte 0 ==
6897 11:45:13.448143 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6898 11:45:13.451591 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6899 11:45:13.451684 == TX Byte 1 ==
6900 11:45:13.458799 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6901 11:45:13.461857 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6902 11:45:13.461945 ==
6903 11:45:13.464910 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 11:45:13.468623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 11:45:13.468708 ==
6906 11:45:13.468772
6907 11:45:13.468833
6908 11:45:13.471492 TX Vref Scan disable
6909 11:45:13.475581 == TX Byte 0 ==
6910 11:45:13.478276 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6911 11:45:13.481768 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6912 11:45:13.481881 == TX Byte 1 ==
6913 11:45:13.488160 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6914 11:45:13.491884 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6915 11:45:13.491975
6916 11:45:13.492041 [DATLAT]
6917 11:45:13.495117 Freq=400, CH1 RK1
6918 11:45:13.495190
6919 11:45:13.495256 DATLAT Default: 0xe
6920 11:45:13.498566 0, 0xFFFF, sum = 0
6921 11:45:13.498683 1, 0xFFFF, sum = 0
6922 11:45:13.501654 2, 0xFFFF, sum = 0
6923 11:45:13.501759 3, 0xFFFF, sum = 0
6924 11:45:13.504999 4, 0xFFFF, sum = 0
6925 11:45:13.505132 5, 0xFFFF, sum = 0
6926 11:45:13.508988 6, 0xFFFF, sum = 0
6927 11:45:13.509109 7, 0xFFFF, sum = 0
6928 11:45:13.512071 8, 0xFFFF, sum = 0
6929 11:45:13.512178 9, 0xFFFF, sum = 0
6930 11:45:13.515005 10, 0xFFFF, sum = 0
6931 11:45:13.518346 11, 0xFFFF, sum = 0
6932 11:45:13.518451 12, 0xFFFF, sum = 0
6933 11:45:13.521879 13, 0x0, sum = 1
6934 11:45:13.521984 14, 0x0, sum = 2
6935 11:45:13.525240 15, 0x0, sum = 3
6936 11:45:13.525356 16, 0x0, sum = 4
6937 11:45:13.525451 best_step = 14
6938 11:45:13.525522
6939 11:45:13.528758 ==
6940 11:45:13.531943 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:45:13.535328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:45:13.535422 ==
6943 11:45:13.535497 RX Vref Scan: 0
6944 11:45:13.535559
6945 11:45:13.538586 RX Vref 0 -> 0, step: 1
6946 11:45:13.538665
6947 11:45:13.541693 RX Delay -343 -> 252, step: 8
6948 11:45:13.548848 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6949 11:45:13.551838 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6950 11:45:13.555027 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6951 11:45:13.558358 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6952 11:45:13.565038 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6953 11:45:13.568430 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6954 11:45:13.571733 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6955 11:45:13.575363 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6956 11:45:13.581819 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6957 11:45:13.585475 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6958 11:45:13.589136 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6959 11:45:13.591855 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6960 11:45:13.598789 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6961 11:45:13.602226 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6962 11:45:13.605621 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6963 11:45:13.608736 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6964 11:45:13.611946 ==
6965 11:45:13.615765 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 11:45:13.618949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 11:45:13.619038 ==
6968 11:45:13.619108 DQS Delay:
6969 11:45:13.622716 DQS0 = 52, DQS1 = 60
6970 11:45:13.622793 DQM Delay:
6971 11:45:13.625724 DQM0 = 13, DQM1 = 12
6972 11:45:13.625799 DQ Delay:
6973 11:45:13.629030 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6974 11:45:13.632742 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6975 11:45:13.635705 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6976 11:45:13.639080 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6977 11:45:13.639169
6978 11:45:13.639235
6979 11:45:13.645817 [DQSOSCAuto] RK1, (LSB)MR18= 0x738a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6980 11:45:13.648713 CH1 RK1: MR19=C0C, MR18=738A
6981 11:45:13.655684 CH1_RK1: MR19=0xC0C, MR18=0x738A, DQSOSC=392, MR23=63, INC=384, DEC=256
6982 11:45:13.658738 [RxdqsGatingPostProcess] freq 400
6983 11:45:13.662237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6984 11:45:13.665561 best DQS0 dly(2T, 0.5T) = (0, 10)
6985 11:45:13.668818 best DQS1 dly(2T, 0.5T) = (0, 10)
6986 11:45:13.672424 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6987 11:45:13.675853 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6988 11:45:13.679166 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 11:45:13.682174 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 11:45:13.685351 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 11:45:13.688999 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 11:45:13.692396 Pre-setting of DQS Precalculation
6993 11:45:13.696448 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6994 11:45:13.702458 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6995 11:45:13.712152 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6996 11:45:13.712321
6997 11:45:13.712429
6998 11:45:13.716042 [Calibration Summary] 800 Mbps
6999 11:45:13.716156 CH 0, Rank 0
7000 11:45:13.718916 SW Impedance : PASS
7001 11:45:13.719036 DUTY Scan : NO K
7002 11:45:13.722417 ZQ Calibration : PASS
7003 11:45:13.722526 Jitter Meter : NO K
7004 11:45:13.725827 CBT Training : PASS
7005 11:45:13.729068 Write leveling : PASS
7006 11:45:13.729149 RX DQS gating : PASS
7007 11:45:13.732448 RX DQ/DQS(RDDQC) : PASS
7008 11:45:13.735804 TX DQ/DQS : PASS
7009 11:45:13.735928 RX DATLAT : PASS
7010 11:45:13.738838 RX DQ/DQS(Engine): PASS
7011 11:45:13.742288 TX OE : NO K
7012 11:45:13.742380 All Pass.
7013 11:45:13.742443
7014 11:45:13.742502 CH 0, Rank 1
7015 11:45:13.745724 SW Impedance : PASS
7016 11:45:13.749305 DUTY Scan : NO K
7017 11:45:13.749405 ZQ Calibration : PASS
7018 11:45:13.752683 Jitter Meter : NO K
7019 11:45:13.755700 CBT Training : PASS
7020 11:45:13.755817 Write leveling : NO K
7021 11:45:13.759235 RX DQS gating : PASS
7022 11:45:13.759314 RX DQ/DQS(RDDQC) : PASS
7023 11:45:13.762420 TX DQ/DQS : PASS
7024 11:45:13.765638 RX DATLAT : PASS
7025 11:45:13.765747 RX DQ/DQS(Engine): PASS
7026 11:45:13.769140 TX OE : NO K
7027 11:45:13.769228 All Pass.
7028 11:45:13.769296
7029 11:45:13.772543 CH 1, Rank 0
7030 11:45:13.772618 SW Impedance : PASS
7031 11:45:13.775713 DUTY Scan : NO K
7032 11:45:13.778908 ZQ Calibration : PASS
7033 11:45:13.778988 Jitter Meter : NO K
7034 11:45:13.782653 CBT Training : PASS
7035 11:45:13.785575 Write leveling : PASS
7036 11:45:13.785680 RX DQS gating : PASS
7037 11:45:13.788969 RX DQ/DQS(RDDQC) : PASS
7038 11:45:13.792699 TX DQ/DQS : PASS
7039 11:45:13.792863 RX DATLAT : PASS
7040 11:45:13.795842 RX DQ/DQS(Engine): PASS
7041 11:45:13.799116 TX OE : NO K
7042 11:45:13.799216 All Pass.
7043 11:45:13.799283
7044 11:45:13.799343 CH 1, Rank 1
7045 11:45:13.802966 SW Impedance : PASS
7046 11:45:13.805493 DUTY Scan : NO K
7047 11:45:13.805617 ZQ Calibration : PASS
7048 11:45:13.808894 Jitter Meter : NO K
7049 11:45:13.809012 CBT Training : PASS
7050 11:45:13.812471 Write leveling : NO K
7051 11:45:13.815688 RX DQS gating : PASS
7052 11:45:13.815798 RX DQ/DQS(RDDQC) : PASS
7053 11:45:13.819060 TX DQ/DQS : PASS
7054 11:45:13.822473 RX DATLAT : PASS
7055 11:45:13.822580 RX DQ/DQS(Engine): PASS
7056 11:45:13.825818 TX OE : NO K
7057 11:45:13.825926 All Pass.
7058 11:45:13.826019
7059 11:45:13.829030 DramC Write-DBI off
7060 11:45:13.832510 PER_BANK_REFRESH: Hybrid Mode
7061 11:45:13.832620 TX_TRACKING: ON
7062 11:45:13.842977 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7063 11:45:13.845716 [FAST_K] Save calibration result to emmc
7064 11:45:13.848798 dramc_set_vcore_voltage set vcore to 725000
7065 11:45:13.852460 Read voltage for 1600, 0
7066 11:45:13.852550 Vio18 = 0
7067 11:45:13.852620 Vcore = 725000
7068 11:45:13.855625 Vdram = 0
7069 11:45:13.855695 Vddq = 0
7070 11:45:13.855759 Vmddr = 0
7071 11:45:13.862521 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7072 11:45:13.865861 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7073 11:45:13.869130 MEM_TYPE=3, freq_sel=13
7074 11:45:13.872373 sv_algorithm_assistance_LP4_3733
7075 11:45:13.875976 ============ PULL DRAM RESETB DOWN ============
7076 11:45:13.879156 ========== PULL DRAM RESETB DOWN end =========
7077 11:45:13.885750 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7078 11:45:13.889072 ===================================
7079 11:45:13.889165 LPDDR4 DRAM CONFIGURATION
7080 11:45:13.892462 ===================================
7081 11:45:13.895862 EX_ROW_EN[0] = 0x0
7082 11:45:13.899187 EX_ROW_EN[1] = 0x0
7083 11:45:13.899334 LP4Y_EN = 0x0
7084 11:45:13.902485 WORK_FSP = 0x1
7085 11:45:13.902603 WL = 0x5
7086 11:45:13.905825 RL = 0x5
7087 11:45:13.905967 BL = 0x2
7088 11:45:13.909361 RPST = 0x0
7089 11:45:13.909498 RD_PRE = 0x0
7090 11:45:13.912479 WR_PRE = 0x1
7091 11:45:13.912591 WR_PST = 0x1
7092 11:45:13.915955 DBI_WR = 0x0
7093 11:45:13.916070 DBI_RD = 0x0
7094 11:45:13.919324 OTF = 0x1
7095 11:45:13.923044 ===================================
7096 11:45:13.925978 ===================================
7097 11:45:13.926088 ANA top config
7098 11:45:13.929350 ===================================
7099 11:45:13.932205 DLL_ASYNC_EN = 0
7100 11:45:13.935511 ALL_SLAVE_EN = 0
7101 11:45:13.939049 NEW_RANK_MODE = 1
7102 11:45:13.939149 DLL_IDLE_MODE = 1
7103 11:45:13.942694 LP45_APHY_COMB_EN = 1
7104 11:45:13.945509 TX_ODT_DIS = 0
7105 11:45:13.948890 NEW_8X_MODE = 1
7106 11:45:13.952253 ===================================
7107 11:45:13.955625 ===================================
7108 11:45:13.959032 data_rate = 3200
7109 11:45:13.959132 CKR = 1
7110 11:45:13.962487 DQ_P2S_RATIO = 8
7111 11:45:13.965748 ===================================
7112 11:45:13.968997 CA_P2S_RATIO = 8
7113 11:45:13.972322 DQ_CA_OPEN = 0
7114 11:45:13.975541 DQ_SEMI_OPEN = 0
7115 11:45:13.975639 CA_SEMI_OPEN = 0
7116 11:45:13.978810 CA_FULL_RATE = 0
7117 11:45:13.982409 DQ_CKDIV4_EN = 0
7118 11:45:13.985839 CA_CKDIV4_EN = 0
7119 11:45:13.989468 CA_PREDIV_EN = 0
7120 11:45:13.992186 PH8_DLY = 12
7121 11:45:13.992293 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7122 11:45:13.995536 DQ_AAMCK_DIV = 4
7123 11:45:13.998893 CA_AAMCK_DIV = 4
7124 11:45:14.002349 CA_ADMCK_DIV = 4
7125 11:45:14.005490 DQ_TRACK_CA_EN = 0
7126 11:45:14.008727 CA_PICK = 1600
7127 11:45:14.012214 CA_MCKIO = 1600
7128 11:45:14.012333 MCKIO_SEMI = 0
7129 11:45:14.015441 PLL_FREQ = 3068
7130 11:45:14.018753 DQ_UI_PI_RATIO = 32
7131 11:45:14.022657 CA_UI_PI_RATIO = 0
7132 11:45:14.025835 ===================================
7133 11:45:14.028736 ===================================
7134 11:45:14.032485 memory_type:LPDDR4
7135 11:45:14.032601 GP_NUM : 10
7136 11:45:14.035467 SRAM_EN : 1
7137 11:45:14.038877 MD32_EN : 0
7138 11:45:14.038988 ===================================
7139 11:45:14.042133 [ANA_INIT] >>>>>>>>>>>>>>
7140 11:45:14.046303 <<<<<< [CONFIGURE PHASE]: ANA_TX
7141 11:45:14.048877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7142 11:45:14.052248 ===================================
7143 11:45:14.055554 data_rate = 3200,PCW = 0X7600
7144 11:45:14.059005 ===================================
7145 11:45:14.062464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7146 11:45:14.069076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 11:45:14.072332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 11:45:14.079310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7149 11:45:14.082344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7150 11:45:14.085392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7151 11:45:14.085487 [ANA_INIT] flow start
7152 11:45:14.089168 [ANA_INIT] PLL >>>>>>>>
7153 11:45:14.092073 [ANA_INIT] PLL <<<<<<<<
7154 11:45:14.092179 [ANA_INIT] MIDPI >>>>>>>>
7155 11:45:14.095825 [ANA_INIT] MIDPI <<<<<<<<
7156 11:45:14.098985 [ANA_INIT] DLL >>>>>>>>
7157 11:45:14.099130 [ANA_INIT] DLL <<<<<<<<
7158 11:45:14.102587 [ANA_INIT] flow end
7159 11:45:14.105773 ============ LP4 DIFF to SE enter ============
7160 11:45:14.109023 ============ LP4 DIFF to SE exit ============
7161 11:45:14.112810 [ANA_INIT] <<<<<<<<<<<<<
7162 11:45:14.115727 [Flow] Enable top DCM control >>>>>
7163 11:45:14.118907 [Flow] Enable top DCM control <<<<<
7164 11:45:14.122441 Enable DLL master slave shuffle
7165 11:45:14.128931 ==============================================================
7166 11:45:14.129062 Gating Mode config
7167 11:45:14.135578 ==============================================================
7168 11:45:14.135716 Config description:
7169 11:45:14.145985 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7170 11:45:14.152588 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7171 11:45:14.159352 SELPH_MODE 0: By rank 1: By Phase
7172 11:45:14.162972 ==============================================================
7173 11:45:14.165674 GAT_TRACK_EN = 1
7174 11:45:14.169287 RX_GATING_MODE = 2
7175 11:45:14.172509 RX_GATING_TRACK_MODE = 2
7176 11:45:14.176185 SELPH_MODE = 1
7177 11:45:14.179099 PICG_EARLY_EN = 1
7178 11:45:14.182459 VALID_LAT_VALUE = 1
7179 11:45:14.185863 ==============================================================
7180 11:45:14.189235 Enter into Gating configuration >>>>
7181 11:45:14.193029 Exit from Gating configuration <<<<
7182 11:45:14.195857 Enter into DVFS_PRE_config >>>>>
7183 11:45:14.209425 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7184 11:45:14.212681 Exit from DVFS_PRE_config <<<<<
7185 11:45:14.212804 Enter into PICG configuration >>>>
7186 11:45:14.216128 Exit from PICG configuration <<<<
7187 11:45:14.219373 [RX_INPUT] configuration >>>>>
7188 11:45:14.222630 [RX_INPUT] configuration <<<<<
7189 11:45:14.229267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7190 11:45:14.232934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7191 11:45:14.239318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7192 11:45:14.246080 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7193 11:45:14.253293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 11:45:14.259634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 11:45:14.263030 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7196 11:45:14.266057 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7197 11:45:14.269582 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7198 11:45:14.276729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7199 11:45:14.279994 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7200 11:45:14.283162 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 11:45:14.286559 ===================================
7202 11:45:14.289919 LPDDR4 DRAM CONFIGURATION
7203 11:45:14.293150 ===================================
7204 11:45:14.293247 EX_ROW_EN[0] = 0x0
7205 11:45:14.296775 EX_ROW_EN[1] = 0x0
7206 11:45:14.296865 LP4Y_EN = 0x0
7207 11:45:14.299851 WORK_FSP = 0x1
7208 11:45:14.302795 WL = 0x5
7209 11:45:14.302902 RL = 0x5
7210 11:45:14.306495 BL = 0x2
7211 11:45:14.306587 RPST = 0x0
7212 11:45:14.309567 RD_PRE = 0x0
7213 11:45:14.309656 WR_PRE = 0x1
7214 11:45:14.313347 WR_PST = 0x1
7215 11:45:14.313436 DBI_WR = 0x0
7216 11:45:14.316553 DBI_RD = 0x0
7217 11:45:14.316645 OTF = 0x1
7218 11:45:14.319808 ===================================
7219 11:45:14.322967 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7220 11:45:14.329705 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7221 11:45:14.332774 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 11:45:14.336285 ===================================
7223 11:45:14.339552 LPDDR4 DRAM CONFIGURATION
7224 11:45:14.343346 ===================================
7225 11:45:14.343457 EX_ROW_EN[0] = 0x10
7226 11:45:14.346347 EX_ROW_EN[1] = 0x0
7227 11:45:14.346442 LP4Y_EN = 0x0
7228 11:45:14.349952 WORK_FSP = 0x1
7229 11:45:14.350048 WL = 0x5
7230 11:45:14.352630 RL = 0x5
7231 11:45:14.352723 BL = 0x2
7232 11:45:14.356154 RPST = 0x0
7233 11:45:14.356250 RD_PRE = 0x0
7234 11:45:14.359509 WR_PRE = 0x1
7235 11:45:14.362706 WR_PST = 0x1
7236 11:45:14.362813 DBI_WR = 0x0
7237 11:45:14.366257 DBI_RD = 0x0
7238 11:45:14.366369 OTF = 0x1
7239 11:45:14.369498 ===================================
7240 11:45:14.376220 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7241 11:45:14.376370 ==
7242 11:45:14.380262 Dram Type= 6, Freq= 0, CH_0, rank 0
7243 11:45:14.383053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7244 11:45:14.383190 ==
7245 11:45:14.385792 [Duty_Offset_Calibration]
7246 11:45:14.389684 B0:2 B1:-1 CA:1
7247 11:45:14.389809
7248 11:45:14.392518 [DutyScan_Calibration_Flow] k_type=0
7249 11:45:14.400441
7250 11:45:14.400566 ==CLK 0==
7251 11:45:14.403245 Final CLK duty delay cell = -4
7252 11:45:14.406565 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7253 11:45:14.410006 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7254 11:45:14.413395 [-4] AVG Duty = 4937%(X100)
7255 11:45:14.413508
7256 11:45:14.416724 CH0 CLK Duty spec in!! Max-Min= 187%
7257 11:45:14.420270 [DutyScan_Calibration_Flow] ====Done====
7258 11:45:14.420370
7259 11:45:14.423662 [DutyScan_Calibration_Flow] k_type=1
7260 11:45:14.439953
7261 11:45:14.440123 ==DQS 0 ==
7262 11:45:14.442646 Final DQS duty delay cell = 0
7263 11:45:14.445984 [0] MAX Duty = 5125%(X100), DQS PI = 20
7264 11:45:14.449673 [0] MIN Duty = 5031%(X100), DQS PI = 14
7265 11:45:14.452852 [0] AVG Duty = 5078%(X100)
7266 11:45:14.452949
7267 11:45:14.453014 ==DQS 1 ==
7268 11:45:14.456228 Final DQS duty delay cell = -4
7269 11:45:14.459407 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7270 11:45:14.463101 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7271 11:45:14.466342 [-4] AVG Duty = 5046%(X100)
7272 11:45:14.466463
7273 11:45:14.469626 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7274 11:45:14.469743
7275 11:45:14.472975 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7276 11:45:14.476222 [DutyScan_Calibration_Flow] ====Done====
7277 11:45:14.476315
7278 11:45:14.479463 [DutyScan_Calibration_Flow] k_type=3
7279 11:45:14.497095
7280 11:45:14.497240 ==DQM 0 ==
7281 11:45:14.500488 Final DQM duty delay cell = 0
7282 11:45:14.503917 [0] MAX Duty = 5000%(X100), DQS PI = 38
7283 11:45:14.506829 [0] MIN Duty = 4844%(X100), DQS PI = 8
7284 11:45:14.506948 [0] AVG Duty = 4922%(X100)
7285 11:45:14.510246
7286 11:45:14.510333 ==DQM 1 ==
7287 11:45:14.513697 Final DQM duty delay cell = 0
7288 11:45:14.517053 [0] MAX Duty = 5218%(X100), DQS PI = 58
7289 11:45:14.520438 [0] MIN Duty = 4969%(X100), DQS PI = 18
7290 11:45:14.520531 [0] AVG Duty = 5093%(X100)
7291 11:45:14.523855
7292 11:45:14.526947 CH0 DQM 0 Duty spec in!! Max-Min= 156%
7293 11:45:14.527048
7294 11:45:14.530418 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7295 11:45:14.534032 [DutyScan_Calibration_Flow] ====Done====
7296 11:45:14.534125
7297 11:45:14.536870 [DutyScan_Calibration_Flow] k_type=2
7298 11:45:14.554217
7299 11:45:14.554373 ==DQ 0 ==
7300 11:45:14.557452 Final DQ duty delay cell = 0
7301 11:45:14.560646 [0] MAX Duty = 5156%(X100), DQS PI = 0
7302 11:45:14.564036 [0] MIN Duty = 5031%(X100), DQS PI = 10
7303 11:45:14.564146 [0] AVG Duty = 5093%(X100)
7304 11:45:14.564211
7305 11:45:14.567300 ==DQ 1 ==
7306 11:45:14.570874 Final DQ duty delay cell = 0
7307 11:45:14.574202 [0] MAX Duty = 5031%(X100), DQS PI = 30
7308 11:45:14.577372 [0] MIN Duty = 4907%(X100), DQS PI = 18
7309 11:45:14.577552 [0] AVG Duty = 4969%(X100)
7310 11:45:14.577646
7311 11:45:14.580772 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7312 11:45:14.580887
7313 11:45:14.584029 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7314 11:45:14.590721 [DutyScan_Calibration_Flow] ====Done====
7315 11:45:14.590898 ==
7316 11:45:14.594101 Dram Type= 6, Freq= 0, CH_1, rank 0
7317 11:45:14.597522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7318 11:45:14.597679 ==
7319 11:45:14.600916 [Duty_Offset_Calibration]
7320 11:45:14.601028 B0:1 B1:1 CA:2
7321 11:45:14.601093
7322 11:45:14.604621 [DutyScan_Calibration_Flow] k_type=0
7323 11:45:14.614226
7324 11:45:14.614366 ==CLK 0==
7325 11:45:14.617647 Final CLK duty delay cell = 0
7326 11:45:14.621039 [0] MAX Duty = 5187%(X100), DQS PI = 26
7327 11:45:14.623967 [0] MIN Duty = 4938%(X100), DQS PI = 50
7328 11:45:14.627457 [0] AVG Duty = 5062%(X100)
7329 11:45:14.627554
7330 11:45:14.630979 CH1 CLK Duty spec in!! Max-Min= 249%
7331 11:45:14.633987 [DutyScan_Calibration_Flow] ====Done====
7332 11:45:14.634084
7333 11:45:14.637265 [DutyScan_Calibration_Flow] k_type=1
7334 11:45:14.654131
7335 11:45:14.654265 ==DQS 0 ==
7336 11:45:14.657455 Final DQS duty delay cell = 0
7337 11:45:14.660813 [0] MAX Duty = 5062%(X100), DQS PI = 20
7338 11:45:14.663959 [0] MIN Duty = 4813%(X100), DQS PI = 50
7339 11:45:14.667279 [0] AVG Duty = 4937%(X100)
7340 11:45:14.667393
7341 11:45:14.667461 ==DQS 1 ==
7342 11:45:14.670809 Final DQS duty delay cell = 0
7343 11:45:14.674110 [0] MAX Duty = 5031%(X100), DQS PI = 34
7344 11:45:14.677519 [0] MIN Duty = 4938%(X100), DQS PI = 12
7345 11:45:14.680642 [0] AVG Duty = 4984%(X100)
7346 11:45:14.680737
7347 11:45:14.683626 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7348 11:45:14.683714
7349 11:45:14.687173 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7350 11:45:14.690738 [DutyScan_Calibration_Flow] ====Done====
7351 11:45:14.690872
7352 11:45:14.693565 [DutyScan_Calibration_Flow] k_type=3
7353 11:45:14.711168
7354 11:45:14.711307 ==DQM 0 ==
7355 11:45:14.714350 Final DQM duty delay cell = 0
7356 11:45:14.717516 [0] MAX Duty = 5124%(X100), DQS PI = 18
7357 11:45:14.721093 [0] MIN Duty = 4813%(X100), DQS PI = 50
7358 11:45:14.721189 [0] AVG Duty = 4968%(X100)
7359 11:45:14.724491
7360 11:45:14.724578 ==DQM 1 ==
7361 11:45:14.727522 Final DQM duty delay cell = 0
7362 11:45:14.731132 [0] MAX Duty = 5156%(X100), DQS PI = 60
7363 11:45:14.734510 [0] MIN Duty = 4875%(X100), DQS PI = 22
7364 11:45:14.734600 [0] AVG Duty = 5015%(X100)
7365 11:45:14.738242
7366 11:45:14.741368 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7367 11:45:14.741462
7368 11:45:14.744659 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7369 11:45:14.747650 [DutyScan_Calibration_Flow] ====Done====
7370 11:45:14.747744
7371 11:45:14.750774 [DutyScan_Calibration_Flow] k_type=2
7372 11:45:14.768041
7373 11:45:14.768189 ==DQ 0 ==
7374 11:45:14.771216 Final DQ duty delay cell = 0
7375 11:45:14.774574 [0] MAX Duty = 5156%(X100), DQS PI = 22
7376 11:45:14.777846 [0] MIN Duty = 4907%(X100), DQS PI = 52
7377 11:45:14.777951 [0] AVG Duty = 5031%(X100)
7378 11:45:14.778015
7379 11:45:14.781243 ==DQ 1 ==
7380 11:45:14.784275 Final DQ duty delay cell = 0
7381 11:45:14.787631 [0] MAX Duty = 5093%(X100), DQS PI = 8
7382 11:45:14.790875 [0] MIN Duty = 5031%(X100), DQS PI = 0
7383 11:45:14.790979 [0] AVG Duty = 5062%(X100)
7384 11:45:14.791042
7385 11:45:14.794596 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7386 11:45:14.794680
7387 11:45:14.798199 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7388 11:45:14.804351 [DutyScan_Calibration_Flow] ====Done====
7389 11:45:14.807606 nWR fixed to 30
7390 11:45:14.807703 [ModeRegInit_LP4] CH0 RK0
7391 11:45:14.811014 [ModeRegInit_LP4] CH0 RK1
7392 11:45:14.814810 [ModeRegInit_LP4] CH1 RK0
7393 11:45:14.814932 [ModeRegInit_LP4] CH1 RK1
7394 11:45:14.818045 match AC timing 5
7395 11:45:14.821333 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7396 11:45:14.824613 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7397 11:45:14.831304 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7398 11:45:14.834475 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7399 11:45:14.841562 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7400 11:45:14.841689 [MiockJmeterHQA]
7401 11:45:14.841758
7402 11:45:14.844441 [DramcMiockJmeter] u1RxGatingPI = 0
7403 11:45:14.844526 0 : 4368, 4140
7404 11:45:14.848517 4 : 4252, 4027
7405 11:45:14.848607 8 : 4363, 4138
7406 11:45:14.851061 12 : 4253, 4027
7407 11:45:14.851148 16 : 4252, 4027
7408 11:45:14.855105 20 : 4252, 4027
7409 11:45:14.855192 24 : 4366, 4139
7410 11:45:14.855257 28 : 4253, 4027
7411 11:45:14.858231 32 : 4255, 4030
7412 11:45:14.858316 36 : 4252, 4027
7413 11:45:14.861557 40 : 4363, 4137
7414 11:45:14.861655 44 : 4252, 4027
7415 11:45:14.864709 48 : 4366, 4139
7416 11:45:14.864801 52 : 4250, 4027
7417 11:45:14.868113 56 : 4250, 4027
7418 11:45:14.868213 60 : 4252, 4029
7419 11:45:14.868311 64 : 4252, 4029
7420 11:45:14.871478 68 : 4250, 4027
7421 11:45:14.871612 72 : 4253, 4029
7422 11:45:14.874929 76 : 4363, 4139
7423 11:45:14.875066 80 : 4252, 4029
7424 11:45:14.878127 84 : 4253, 4029
7425 11:45:14.878253 88 : 4250, 4027
7426 11:45:14.878321 92 : 4361, 4137
7427 11:45:14.881652 96 : 4250, 2751
7428 11:45:14.881777 100 : 4361, 0
7429 11:45:14.885102 104 : 4360, 0
7430 11:45:14.885211 108 : 4250, 0
7431 11:45:14.885308 112 : 4363, 0
7432 11:45:14.888269 116 : 4363, 0
7433 11:45:14.888355 120 : 4250, 0
7434 11:45:14.891636 124 : 4250, 0
7435 11:45:14.891723 128 : 4250, 0
7436 11:45:14.891804 132 : 4252, 0
7437 11:45:14.894776 136 : 4250, 0
7438 11:45:14.894875 140 : 4250, 0
7439 11:45:14.898191 144 : 4252, 0
7440 11:45:14.898312 148 : 4360, 0
7441 11:45:14.898376 152 : 4360, 0
7442 11:45:14.901532 156 : 4363, 0
7443 11:45:14.901637 160 : 4250, 0
7444 11:45:14.901717 164 : 4250, 0
7445 11:45:14.904618 168 : 4250, 0
7446 11:45:14.904719 172 : 4252, 0
7447 11:45:14.908220 176 : 4250, 0
7448 11:45:14.908325 180 : 4250, 0
7449 11:45:14.908406 184 : 4252, 0
7450 11:45:14.911405 188 : 4361, 0
7451 11:45:14.911522 192 : 4250, 0
7452 11:45:14.914502 196 : 4250, 0
7453 11:45:14.914590 200 : 4250, 0
7454 11:45:14.914671 204 : 4360, 0
7455 11:45:14.918099 208 : 4361, 0
7456 11:45:14.918185 212 : 4250, 292
7457 11:45:14.921226 216 : 4250, 3891
7458 11:45:14.921312 220 : 4360, 4137
7459 11:45:14.924826 224 : 4361, 4137
7460 11:45:14.924926 228 : 4247, 4025
7461 11:45:14.928084 232 : 4363, 4140
7462 11:45:14.928184 236 : 4361, 4137
7463 11:45:14.928280 240 : 4250, 4026
7464 11:45:14.931305 244 : 4250, 4027
7465 11:45:14.931405 248 : 4252, 4030
7466 11:45:14.934420 252 : 4250, 4027
7467 11:45:14.934534 256 : 4250, 4027
7468 11:45:14.938266 260 : 4250, 4027
7469 11:45:14.938391 264 : 4253, 4030
7470 11:45:14.941160 268 : 4250, 4027
7471 11:45:14.941260 272 : 4360, 4138
7472 11:45:14.944441 276 : 4361, 4137
7473 11:45:14.944541 280 : 4250, 4027
7474 11:45:14.947880 284 : 4363, 4140
7475 11:45:14.948034 288 : 4361, 4137
7476 11:45:14.951621 292 : 4250, 4026
7477 11:45:14.951707 296 : 4250, 4027
7478 11:45:14.951773 300 : 4253, 4030
7479 11:45:14.955189 304 : 4250, 4027
7480 11:45:14.955277 308 : 4250, 4026
7481 11:45:14.958152 312 : 4250, 4027
7482 11:45:14.958237 316 : 4252, 4029
7483 11:45:14.961333 320 : 4250, 4027
7484 11:45:14.961419 324 : 4361, 4137
7485 11:45:14.964810 328 : 4361, 4136
7486 11:45:14.964896 332 : 4250, 2780
7487 11:45:14.968148 336 : 4363, 6
7488 11:45:14.968234
7489 11:45:14.968298 MIOCK jitter meter ch=0
7490 11:45:14.968359
7491 11:45:14.971634 1T = (336-100) = 236 dly cells
7492 11:45:14.978408 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7493 11:45:14.978509 ==
7494 11:45:14.981896 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 11:45:14.984901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7496 11:45:14.984989 ==
7497 11:45:14.991740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7498 11:45:14.995024 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7499 11:45:14.998551 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7500 11:45:15.004744 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7501 11:45:15.014496 [CA 0] Center 44 (14~75) winsize 62
7502 11:45:15.017432 [CA 1] Center 44 (14~74) winsize 61
7503 11:45:15.021303 [CA 2] Center 39 (10~68) winsize 59
7504 11:45:15.024359 [CA 3] Center 39 (10~68) winsize 59
7505 11:45:15.027676 [CA 4] Center 37 (7~67) winsize 61
7506 11:45:15.030988 [CA 5] Center 37 (7~67) winsize 61
7507 11:45:15.031078
7508 11:45:15.034340 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7509 11:45:15.034425
7510 11:45:15.038029 [CATrainingPosCal] consider 1 rank data
7511 11:45:15.041704 u2DelayCellTimex100 = 275/100 ps
7512 11:45:15.044884 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7513 11:45:15.050841 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7514 11:45:15.054203 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7515 11:45:15.058227 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7516 11:45:15.061187 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 11:45:15.064241 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7518 11:45:15.064329
7519 11:45:15.067547 CA PerBit enable=1, Macro0, CA PI delay=37
7520 11:45:15.067630
7521 11:45:15.070857 [CBTSetCACLKResult] CA Dly = 37
7522 11:45:15.074396 CS Dly: 10 (0~41)
7523 11:45:15.077866 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7524 11:45:15.081251 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7525 11:45:15.081336 ==
7526 11:45:15.084639 Dram Type= 6, Freq= 0, CH_0, rank 1
7527 11:45:15.088421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 11:45:15.088509 ==
7529 11:45:15.094659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 11:45:15.097875 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 11:45:15.104672 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 11:45:15.107880 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 11:45:15.118536 [CA 0] Center 43 (13~74) winsize 62
7534 11:45:15.121233 [CA 1] Center 43 (13~74) winsize 62
7535 11:45:15.125151 [CA 2] Center 39 (10~69) winsize 60
7536 11:45:15.128232 [CA 3] Center 38 (9~68) winsize 60
7537 11:45:15.131242 [CA 4] Center 37 (7~67) winsize 61
7538 11:45:15.134380 [CA 5] Center 37 (7~67) winsize 61
7539 11:45:15.134467
7540 11:45:15.138265 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 11:45:15.138359
7542 11:45:15.141486 [CATrainingPosCal] consider 2 rank data
7543 11:45:15.144453 u2DelayCellTimex100 = 275/100 ps
7544 11:45:15.147804 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7545 11:45:15.155139 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7546 11:45:15.158176 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7547 11:45:15.161028 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7548 11:45:15.165253 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7549 11:45:15.168105 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7550 11:45:15.168196
7551 11:45:15.171183 CA PerBit enable=1, Macro0, CA PI delay=37
7552 11:45:15.171324
7553 11:45:15.174670 [CBTSetCACLKResult] CA Dly = 37
7554 11:45:15.178397 CS Dly: 11 (0~44)
7555 11:45:15.181487 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 11:45:15.184802 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 11:45:15.184924
7558 11:45:15.188094 ----->DramcWriteLeveling(PI) begin...
7559 11:45:15.188188 ==
7560 11:45:15.191455 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 11:45:15.194555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 11:45:15.197865 ==
7563 11:45:15.197983 Write leveling (Byte 0): 32 => 32
7564 11:45:15.201639 Write leveling (Byte 1): 28 => 28
7565 11:45:15.205041 DramcWriteLeveling(PI) end<-----
7566 11:45:15.205135
7567 11:45:15.205215 ==
7568 11:45:15.208034 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 11:45:15.214427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 11:45:15.214535 ==
7571 11:45:15.214605 [Gating] SW mode calibration
7572 11:45:15.224698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7573 11:45:15.228204 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7574 11:45:15.231808 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 11:45:15.237815 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 11:45:15.241444 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 11:45:15.244550 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 11:45:15.251501 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7579 11:45:15.254703 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7580 11:45:15.258357 1 4 24 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
7581 11:45:15.264960 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 11:45:15.268134 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 11:45:15.271839 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 11:45:15.278014 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 11:45:15.281243 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 11:45:15.285097 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
7587 11:45:15.291269 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7588 11:45:15.294564 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7589 11:45:15.297899 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 11:45:15.304570 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 11:45:15.308365 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 11:45:15.312079 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 11:45:15.315247 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 11:45:15.321530 1 6 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7595 11:45:15.324946 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7596 11:45:15.328402 1 6 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7597 11:45:15.334801 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 11:45:15.338222 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 11:45:15.341791 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 11:45:15.348606 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 11:45:15.351493 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 11:45:15.355180 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7603 11:45:15.361676 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 11:45:15.365068 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7605 11:45:15.368115 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 11:45:15.374800 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 11:45:15.378461 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 11:45:15.381303 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 11:45:15.388313 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 11:45:15.391242 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 11:45:15.394734 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 11:45:15.401425 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 11:45:15.404945 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 11:45:15.408391 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 11:45:15.414535 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 11:45:15.418103 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 11:45:15.421366 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 11:45:15.425099 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7619 11:45:15.431773 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7620 11:45:15.435170 Total UI for P1: 0, mck2ui 16
7621 11:45:15.438105 best dqsien dly found for B0: ( 1, 9, 14)
7622 11:45:15.441579 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 11:45:15.444971 Total UI for P1: 0, mck2ui 16
7624 11:45:15.448189 best dqsien dly found for B1: ( 1, 9, 18)
7625 11:45:15.451525 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7626 11:45:15.454722 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7627 11:45:15.454807
7628 11:45:15.458267 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7629 11:45:15.461449 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7630 11:45:15.465064 [Gating] SW calibration Done
7631 11:45:15.465152 ==
7632 11:45:15.468546 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 11:45:15.471453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 11:45:15.475366 ==
7635 11:45:15.475457 RX Vref Scan: 0
7636 11:45:15.475521
7637 11:45:15.477928 RX Vref 0 -> 0, step: 1
7638 11:45:15.478010
7639 11:45:15.481325 RX Delay 0 -> 252, step: 8
7640 11:45:15.484637 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7641 11:45:15.488068 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7642 11:45:15.491634 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7643 11:45:15.495290 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7644 11:45:15.498365 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7645 11:45:15.504719 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7646 11:45:15.508713 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7647 11:45:15.511678 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7648 11:45:15.515225 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7649 11:45:15.518344 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7650 11:45:15.524955 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7651 11:45:15.528405 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7652 11:45:15.531675 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7653 11:45:15.534972 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7654 11:45:15.542154 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7655 11:45:15.545439 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7656 11:45:15.545534 ==
7657 11:45:15.548191 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 11:45:15.551971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 11:45:15.552059 ==
7660 11:45:15.552123 DQS Delay:
7661 11:45:15.554883 DQS0 = 0, DQS1 = 0
7662 11:45:15.554979 DQM Delay:
7663 11:45:15.558259 DQM0 = 132, DQM1 = 125
7664 11:45:15.558341 DQ Delay:
7665 11:45:15.561860 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7666 11:45:15.564767 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7667 11:45:15.568028 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7668 11:45:15.571872 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7669 11:45:15.571960
7670 11:45:15.575155
7671 11:45:15.575240 ==
7672 11:45:15.578624 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 11:45:15.581731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 11:45:15.581817 ==
7675 11:45:15.581880
7676 11:45:15.581939
7677 11:45:15.585073 TX Vref Scan disable
7678 11:45:15.585156 == TX Byte 0 ==
7679 11:45:15.588321 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7680 11:45:15.594987 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7681 11:45:15.595087 == TX Byte 1 ==
7682 11:45:15.598738 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7683 11:45:15.604958 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7684 11:45:15.605061 ==
7685 11:45:15.608709 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 11:45:15.611632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 11:45:15.611722 ==
7688 11:45:15.626312
7689 11:45:15.630065 TX Vref early break, caculate TX vref
7690 11:45:15.633204 TX Vref=16, minBit 1, minWin=21, winSum=363
7691 11:45:15.636583 TX Vref=18, minBit 0, minWin=22, winSum=371
7692 11:45:15.640098 TX Vref=20, minBit 1, minWin=23, winSum=385
7693 11:45:15.643185 TX Vref=22, minBit 1, minWin=23, winSum=391
7694 11:45:15.646359 TX Vref=24, minBit 4, minWin=23, winSum=405
7695 11:45:15.653440 TX Vref=26, minBit 4, minWin=24, winSum=416
7696 11:45:15.656792 TX Vref=28, minBit 2, minWin=25, winSum=420
7697 11:45:15.660018 TX Vref=30, minBit 4, minWin=24, winSum=416
7698 11:45:15.663472 TX Vref=32, minBit 0, minWin=25, winSum=412
7699 11:45:15.666321 TX Vref=34, minBit 0, minWin=24, winSum=401
7700 11:45:15.669760 TX Vref=36, minBit 3, minWin=23, winSum=393
7701 11:45:15.676975 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 28
7702 11:45:15.677084
7703 11:45:15.680242 Final TX Range 0 Vref 28
7704 11:45:15.680330
7705 11:45:15.680394 ==
7706 11:45:15.683634 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 11:45:15.686790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 11:45:15.686903 ==
7709 11:45:15.686970
7710 11:45:15.687028
7711 11:45:15.689888 TX Vref Scan disable
7712 11:45:15.696756 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7713 11:45:15.696859 == TX Byte 0 ==
7714 11:45:15.699831 u2DelayCellOfst[0]=17 cells (5 PI)
7715 11:45:15.703584 u2DelayCellOfst[1]=21 cells (6 PI)
7716 11:45:15.707108 u2DelayCellOfst[2]=14 cells (4 PI)
7717 11:45:15.710107 u2DelayCellOfst[3]=17 cells (5 PI)
7718 11:45:15.713683 u2DelayCellOfst[4]=10 cells (3 PI)
7719 11:45:15.716466 u2DelayCellOfst[5]=0 cells (0 PI)
7720 11:45:15.719831 u2DelayCellOfst[6]=21 cells (6 PI)
7721 11:45:15.723360 u2DelayCellOfst[7]=21 cells (6 PI)
7722 11:45:15.726931 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7723 11:45:15.730004 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7724 11:45:15.733196 == TX Byte 1 ==
7725 11:45:15.733283 u2DelayCellOfst[8]=0 cells (0 PI)
7726 11:45:15.736872 u2DelayCellOfst[9]=0 cells (0 PI)
7727 11:45:15.740058 u2DelayCellOfst[10]=10 cells (3 PI)
7728 11:45:15.743668 u2DelayCellOfst[11]=0 cells (0 PI)
7729 11:45:15.746954 u2DelayCellOfst[12]=14 cells (4 PI)
7730 11:45:15.750000 u2DelayCellOfst[13]=10 cells (3 PI)
7731 11:45:15.753800 u2DelayCellOfst[14]=17 cells (5 PI)
7732 11:45:15.756730 u2DelayCellOfst[15]=14 cells (4 PI)
7733 11:45:15.759985 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7734 11:45:15.766706 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7735 11:45:15.766810 DramC Write-DBI on
7736 11:45:15.766899 ==
7737 11:45:15.770341 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 11:45:15.773840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 11:45:15.773928 ==
7740 11:45:15.773992
7741 11:45:15.777089
7742 11:45:15.777170 TX Vref Scan disable
7743 11:45:15.780170 == TX Byte 0 ==
7744 11:45:15.783359 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7745 11:45:15.786940 == TX Byte 1 ==
7746 11:45:15.790162 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7747 11:45:15.790253 DramC Write-DBI off
7748 11:45:15.790317
7749 11:45:15.793427 [DATLAT]
7750 11:45:15.793511 Freq=1600, CH0 RK0
7751 11:45:15.793575
7752 11:45:15.797209 DATLAT Default: 0xf
7753 11:45:15.797291 0, 0xFFFF, sum = 0
7754 11:45:15.800685 1, 0xFFFF, sum = 0
7755 11:45:15.800770 2, 0xFFFF, sum = 0
7756 11:45:15.803938 3, 0xFFFF, sum = 0
7757 11:45:15.804024 4, 0xFFFF, sum = 0
7758 11:45:15.806881 5, 0xFFFF, sum = 0
7759 11:45:15.806983 6, 0xFFFF, sum = 0
7760 11:45:15.810436 7, 0xFFFF, sum = 0
7761 11:45:15.810533 8, 0xFFFF, sum = 0
7762 11:45:15.813633 9, 0xFFFF, sum = 0
7763 11:45:15.817474 10, 0xFFFF, sum = 0
7764 11:45:15.817565 11, 0xFFFF, sum = 0
7765 11:45:15.820185 12, 0xFFFF, sum = 0
7766 11:45:15.820268 13, 0xFFFF, sum = 0
7767 11:45:15.823701 14, 0x0, sum = 1
7768 11:45:15.823786 15, 0x0, sum = 2
7769 11:45:15.827265 16, 0x0, sum = 3
7770 11:45:15.827350 17, 0x0, sum = 4
7771 11:45:15.827415 best_step = 15
7772 11:45:15.827474
7773 11:45:15.830561 ==
7774 11:45:15.833547 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 11:45:15.837660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 11:45:15.837748 ==
7777 11:45:15.837812 RX Vref Scan: 1
7778 11:45:15.837871
7779 11:45:15.840533 Set Vref Range= 24 -> 127
7780 11:45:15.840620
7781 11:45:15.843870 RX Vref 24 -> 127, step: 1
7782 11:45:15.843953
7783 11:45:15.847118 RX Delay 11 -> 252, step: 4
7784 11:45:15.847201
7785 11:45:15.850393 Set Vref, RX VrefLevel [Byte0]: 24
7786 11:45:15.853635 [Byte1]: 24
7787 11:45:15.853724
7788 11:45:15.856922 Set Vref, RX VrefLevel [Byte0]: 25
7789 11:45:15.860454 [Byte1]: 25
7790 11:45:15.860541
7791 11:45:15.863616 Set Vref, RX VrefLevel [Byte0]: 26
7792 11:45:15.866924 [Byte1]: 26
7793 11:45:15.870335
7794 11:45:15.870423 Set Vref, RX VrefLevel [Byte0]: 27
7795 11:45:15.873639 [Byte1]: 27
7796 11:45:15.878207
7797 11:45:15.878297 Set Vref, RX VrefLevel [Byte0]: 28
7798 11:45:15.881548 [Byte1]: 28
7799 11:45:15.885544
7800 11:45:15.885632 Set Vref, RX VrefLevel [Byte0]: 29
7801 11:45:15.888828 [Byte1]: 29
7802 11:45:15.893396
7803 11:45:15.893491 Set Vref, RX VrefLevel [Byte0]: 30
7804 11:45:15.896556 [Byte1]: 30
7805 11:45:15.900734
7806 11:45:15.900821 Set Vref, RX VrefLevel [Byte0]: 31
7807 11:45:15.904637 [Byte1]: 31
7808 11:45:15.908515
7809 11:45:15.908607 Set Vref, RX VrefLevel [Byte0]: 32
7810 11:45:15.912116 [Byte1]: 32
7811 11:45:15.915959
7812 11:45:15.916047 Set Vref, RX VrefLevel [Byte0]: 33
7813 11:45:15.919168 [Byte1]: 33
7814 11:45:15.923671
7815 11:45:15.923763 Set Vref, RX VrefLevel [Byte0]: 34
7816 11:45:15.926916 [Byte1]: 34
7817 11:45:15.931363
7818 11:45:15.931474 Set Vref, RX VrefLevel [Byte0]: 35
7819 11:45:15.934933 [Byte1]: 35
7820 11:45:15.938609
7821 11:45:15.938711 Set Vref, RX VrefLevel [Byte0]: 36
7822 11:45:15.942228 [Byte1]: 36
7823 11:45:15.946908
7824 11:45:15.947002 Set Vref, RX VrefLevel [Byte0]: 37
7825 11:45:15.949761 [Byte1]: 37
7826 11:45:15.954286
7827 11:45:15.954378 Set Vref, RX VrefLevel [Byte0]: 38
7828 11:45:15.957412 [Byte1]: 38
7829 11:45:15.961619
7830 11:45:15.961709 Set Vref, RX VrefLevel [Byte0]: 39
7831 11:45:15.965264 [Byte1]: 39
7832 11:45:15.969389
7833 11:45:15.969483 Set Vref, RX VrefLevel [Byte0]: 40
7834 11:45:15.972873 [Byte1]: 40
7835 11:45:15.977000
7836 11:45:15.977093 Set Vref, RX VrefLevel [Byte0]: 41
7837 11:45:15.980671 [Byte1]: 41
7838 11:45:15.984600
7839 11:45:15.984692 Set Vref, RX VrefLevel [Byte0]: 42
7840 11:45:15.988120 [Byte1]: 42
7841 11:45:15.992012
7842 11:45:15.992102 Set Vref, RX VrefLevel [Byte0]: 43
7843 11:45:15.995610 [Byte1]: 43
7844 11:45:15.999782
7845 11:45:15.999873 Set Vref, RX VrefLevel [Byte0]: 44
7846 11:45:16.003086 [Byte1]: 44
7847 11:45:16.007627
7848 11:45:16.007718 Set Vref, RX VrefLevel [Byte0]: 45
7849 11:45:16.010585 [Byte1]: 45
7850 11:45:16.015308
7851 11:45:16.015400 Set Vref, RX VrefLevel [Byte0]: 46
7852 11:45:16.018176 [Byte1]: 46
7853 11:45:16.022760
7854 11:45:16.022852 Set Vref, RX VrefLevel [Byte0]: 47
7855 11:45:16.025961 [Byte1]: 47
7856 11:45:16.030182
7857 11:45:16.030264 Set Vref, RX VrefLevel [Byte0]: 48
7858 11:45:16.033700 [Byte1]: 48
7859 11:45:16.038147
7860 11:45:16.038228 Set Vref, RX VrefLevel [Byte0]: 49
7861 11:45:16.040923 [Byte1]: 49
7862 11:45:16.045816
7863 11:45:16.045896 Set Vref, RX VrefLevel [Byte0]: 50
7864 11:45:16.049122 [Byte1]: 50
7865 11:45:16.053113
7866 11:45:16.053196 Set Vref, RX VrefLevel [Byte0]: 51
7867 11:45:16.056353 [Byte1]: 51
7868 11:45:16.060698
7869 11:45:16.060780 Set Vref, RX VrefLevel [Byte0]: 52
7870 11:45:16.064303 [Byte1]: 52
7871 11:45:16.068118
7872 11:45:16.068198 Set Vref, RX VrefLevel [Byte0]: 53
7873 11:45:16.071408 [Byte1]: 53
7874 11:45:16.075895
7875 11:45:16.075976 Set Vref, RX VrefLevel [Byte0]: 54
7876 11:45:16.079346 [Byte1]: 54
7877 11:45:16.083811
7878 11:45:16.083892 Set Vref, RX VrefLevel [Byte0]: 55
7879 11:45:16.086933 [Byte1]: 55
7880 11:45:16.091396
7881 11:45:16.091477 Set Vref, RX VrefLevel [Byte0]: 56
7882 11:45:16.094520 [Byte1]: 56
7883 11:45:16.098581
7884 11:45:16.098661 Set Vref, RX VrefLevel [Byte0]: 57
7885 11:45:16.101883 [Byte1]: 57
7886 11:45:16.106137
7887 11:45:16.106218 Set Vref, RX VrefLevel [Byte0]: 58
7888 11:45:16.109510 [Byte1]: 58
7889 11:45:16.113898
7890 11:45:16.113977 Set Vref, RX VrefLevel [Byte0]: 59
7891 11:45:16.117054 [Byte1]: 59
7892 11:45:16.121497
7893 11:45:16.121576 Set Vref, RX VrefLevel [Byte0]: 60
7894 11:45:16.125088 [Byte1]: 60
7895 11:45:16.129271
7896 11:45:16.129364 Set Vref, RX VrefLevel [Byte0]: 61
7897 11:45:16.132372 [Byte1]: 61
7898 11:45:16.136936
7899 11:45:16.137016 Set Vref, RX VrefLevel [Byte0]: 62
7900 11:45:16.140130 [Byte1]: 62
7901 11:45:16.144740
7902 11:45:16.144824 Set Vref, RX VrefLevel [Byte0]: 63
7903 11:45:16.148090 [Byte1]: 63
7904 11:45:16.152180
7905 11:45:16.152260 Set Vref, RX VrefLevel [Byte0]: 64
7906 11:45:16.155076 [Byte1]: 64
7907 11:45:16.159578
7908 11:45:16.159658 Set Vref, RX VrefLevel [Byte0]: 65
7909 11:45:16.162846 [Byte1]: 65
7910 11:45:16.167195
7911 11:45:16.167275 Set Vref, RX VrefLevel [Byte0]: 66
7912 11:45:16.170596 [Byte1]: 66
7913 11:45:16.175285
7914 11:45:16.175365 Set Vref, RX VrefLevel [Byte0]: 67
7915 11:45:16.178016 [Byte1]: 67
7916 11:45:16.182601
7917 11:45:16.182681 Set Vref, RX VrefLevel [Byte0]: 68
7918 11:45:16.185644 [Byte1]: 68
7919 11:45:16.190059
7920 11:45:16.190139 Set Vref, RX VrefLevel [Byte0]: 69
7921 11:45:16.193438 [Byte1]: 69
7922 11:45:16.197866
7923 11:45:16.197946 Set Vref, RX VrefLevel [Byte0]: 70
7924 11:45:16.200980 [Byte1]: 70
7925 11:45:16.205415
7926 11:45:16.205495 Set Vref, RX VrefLevel [Byte0]: 71
7927 11:45:16.208556 [Byte1]: 71
7928 11:45:16.212655
7929 11:45:16.212735 Set Vref, RX VrefLevel [Byte0]: 72
7930 11:45:16.216536 [Byte1]: 72
7931 11:45:16.220731
7932 11:45:16.220810 Set Vref, RX VrefLevel [Byte0]: 73
7933 11:45:16.223663 [Byte1]: 73
7934 11:45:16.227970
7935 11:45:16.228050 Set Vref, RX VrefLevel [Byte0]: 74
7936 11:45:16.231780 [Byte1]: 74
7937 11:45:16.235737
7938 11:45:16.235817 Set Vref, RX VrefLevel [Byte0]: 75
7939 11:45:16.238838 [Byte1]: 75
7940 11:45:16.243255
7941 11:45:16.243337 Set Vref, RX VrefLevel [Byte0]: 76
7942 11:45:16.246841 [Byte1]: 76
7943 11:45:16.251247
7944 11:45:16.251322 Final RX Vref Byte 0 = 54 to rank0
7945 11:45:16.254418 Final RX Vref Byte 1 = 61 to rank0
7946 11:45:16.258156 Final RX Vref Byte 0 = 54 to rank1
7947 11:45:16.261179 Final RX Vref Byte 1 = 61 to rank1==
7948 11:45:16.264100 Dram Type= 6, Freq= 0, CH_0, rank 0
7949 11:45:16.270736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 11:45:16.270842 ==
7951 11:45:16.270952 DQS Delay:
7952 11:45:16.271013 DQS0 = 0, DQS1 = 0
7953 11:45:16.274012 DQM Delay:
7954 11:45:16.274118 DQM0 = 130, DQM1 = 122
7955 11:45:16.277564 DQ Delay:
7956 11:45:16.280833 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7957 11:45:16.284595 DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =138
7958 11:45:16.287627 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7959 11:45:16.291017 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7960 11:45:16.291093
7961 11:45:16.291154
7962 11:45:16.291211
7963 11:45:16.294264 [DramC_TX_OE_Calibration] TA2
7964 11:45:16.297746 Original DQ_B0 (3 6) =30, OEN = 27
7965 11:45:16.301102 Original DQ_B1 (3 6) =30, OEN = 27
7966 11:45:16.304293 24, 0x0, End_B0=24 End_B1=24
7967 11:45:16.304402 25, 0x0, End_B0=25 End_B1=25
7968 11:45:16.307627 26, 0x0, End_B0=26 End_B1=26
7969 11:45:16.310960 27, 0x0, End_B0=27 End_B1=27
7970 11:45:16.314278 28, 0x0, End_B0=28 End_B1=28
7971 11:45:16.314378 29, 0x0, End_B0=29 End_B1=29
7972 11:45:16.317650 30, 0x0, End_B0=30 End_B1=30
7973 11:45:16.321154 31, 0x5151, End_B0=30 End_B1=30
7974 11:45:16.324585 Byte0 end_step=30 best_step=27
7975 11:45:16.327834 Byte1 end_step=30 best_step=27
7976 11:45:16.330742 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 11:45:16.330847 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 11:45:16.330957
7979 11:45:16.334084
7980 11:45:16.340804 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7981 11:45:16.344207 CH0 RK0: MR19=303, MR18=1509
7982 11:45:16.350990 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7983 11:45:16.351068
7984 11:45:16.354681 ----->DramcWriteLeveling(PI) begin...
7985 11:45:16.354781 ==
7986 11:45:16.357564 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 11:45:16.361498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 11:45:16.361597 ==
7989 11:45:16.364407 Write leveling (Byte 0): 33 => 33
7990 11:45:16.367897 Write leveling (Byte 1): 25 => 25
7991 11:45:16.371033 DramcWriteLeveling(PI) end<-----
7992 11:45:16.371107
7993 11:45:16.371167 ==
7994 11:45:16.374356 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 11:45:16.378035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 11:45:16.378117 ==
7997 11:45:16.381738 [Gating] SW mode calibration
7998 11:45:16.388201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7999 11:45:16.394585 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8000 11:45:16.398025 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 11:45:16.400897 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 11:45:16.407723 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 11:45:16.410817 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8004 11:45:16.414702 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8005 11:45:16.417857 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8006 11:45:16.424611 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 11:45:16.428175 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 11:45:16.431215 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 11:45:16.437951 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 11:45:16.441279 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8011 11:45:16.444504 1 5 12 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8012 11:45:16.451335 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8013 11:45:16.454899 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8014 11:45:16.458270 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8015 11:45:16.464719 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 11:45:16.467959 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 11:45:16.471532 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 11:45:16.477840 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8019 11:45:16.481348 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8020 11:45:16.484198 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8021 11:45:16.491021 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8022 11:45:16.494482 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 11:45:16.497552 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 11:45:16.504479 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 11:45:16.507782 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 11:45:16.511499 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 11:45:16.517553 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 11:45:16.521085 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8029 11:45:16.524403 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8030 11:45:16.527519 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8031 11:45:16.534278 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 11:45:16.537443 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 11:45:16.540607 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 11:45:16.547332 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 11:45:16.550702 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 11:45:16.554261 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 11:45:16.560741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 11:45:16.564247 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 11:45:16.567581 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 11:45:16.574047 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:45:16.577771 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:45:16.580852 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 11:45:16.587762 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8044 11:45:16.590635 Total UI for P1: 0, mck2ui 16
8045 11:45:16.594030 best dqsien dly found for B0: ( 1, 9, 8)
8046 11:45:16.597291 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8047 11:45:16.601082 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8048 11:45:16.607252 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 11:45:16.610762 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 11:45:16.614246 Total UI for P1: 0, mck2ui 16
8051 11:45:16.617714 best dqsien dly found for B1: ( 1, 9, 22)
8052 11:45:16.621039 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8053 11:45:16.624455 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8054 11:45:16.624535
8055 11:45:16.627727 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8056 11:45:16.630752 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8057 11:45:16.634026 [Gating] SW calibration Done
8058 11:45:16.634107 ==
8059 11:45:16.637260 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 11:45:16.640530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 11:45:16.643892 ==
8062 11:45:16.643979 RX Vref Scan: 0
8063 11:45:16.644042
8064 11:45:16.647229 RX Vref 0 -> 0, step: 1
8065 11:45:16.647309
8066 11:45:16.647372 RX Delay 0 -> 252, step: 8
8067 11:45:16.654240 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8068 11:45:16.657106 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8069 11:45:16.660929 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8070 11:45:16.663689 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8071 11:45:16.667093 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8072 11:45:16.673921 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8073 11:45:16.677132 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8074 11:45:16.680482 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8075 11:45:16.683921 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8076 11:45:16.687263 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8077 11:45:16.694199 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8078 11:45:16.697301 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8079 11:45:16.701008 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8080 11:45:16.704039 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8081 11:45:16.707298 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8082 11:45:16.713959 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8083 11:45:16.714050 ==
8084 11:45:16.717388 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 11:45:16.720680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 11:45:16.720787 ==
8087 11:45:16.720877 DQS Delay:
8088 11:45:16.724211 DQS0 = 0, DQS1 = 0
8089 11:45:16.724307 DQM Delay:
8090 11:45:16.727670 DQM0 = 130, DQM1 = 125
8091 11:45:16.727752 DQ Delay:
8092 11:45:16.731028 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8093 11:45:16.733867 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8094 11:45:16.737244 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8095 11:45:16.740603 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8096 11:45:16.740688
8097 11:45:16.740779
8098 11:45:16.744031 ==
8099 11:45:16.747309 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 11:45:16.750645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 11:45:16.750727 ==
8102 11:45:16.750790
8103 11:45:16.750848
8104 11:45:16.754408 TX Vref Scan disable
8105 11:45:16.754490 == TX Byte 0 ==
8106 11:45:16.757626 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8107 11:45:16.764364 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8108 11:45:16.764449 == TX Byte 1 ==
8109 11:45:16.767739 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8110 11:45:16.773852 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8111 11:45:16.773941 ==
8112 11:45:16.777285 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 11:45:16.780599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 11:45:16.780684 ==
8115 11:45:16.795853
8116 11:45:16.799354 TX Vref early break, caculate TX vref
8117 11:45:16.802431 TX Vref=16, minBit 8, minWin=22, winSum=375
8118 11:45:16.806036 TX Vref=18, minBit 9, minWin=22, winSum=381
8119 11:45:16.809706 TX Vref=20, minBit 3, minWin=23, winSum=391
8120 11:45:16.812781 TX Vref=22, minBit 8, minWin=24, winSum=400
8121 11:45:16.815577 TX Vref=24, minBit 9, minWin=24, winSum=404
8122 11:45:16.822397 TX Vref=26, minBit 3, minWin=25, winSum=413
8123 11:45:16.826277 TX Vref=28, minBit 4, minWin=25, winSum=418
8124 11:45:16.829499 TX Vref=30, minBit 0, minWin=26, winSum=420
8125 11:45:16.832823 TX Vref=32, minBit 4, minWin=25, winSum=413
8126 11:45:16.835447 TX Vref=34, minBit 0, minWin=24, winSum=402
8127 11:45:16.839103 TX Vref=36, minBit 8, minWin=23, winSum=394
8128 11:45:16.845725 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 30
8129 11:45:16.845820
8130 11:45:16.849111 Final TX Range 0 Vref 30
8131 11:45:16.849252
8132 11:45:16.849345 ==
8133 11:45:16.852093 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 11:45:16.855620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 11:45:16.855732 ==
8136 11:45:16.855855
8137 11:45:16.855975
8138 11:45:16.859321 TX Vref Scan disable
8139 11:45:16.865715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8140 11:45:16.865799 == TX Byte 0 ==
8141 11:45:16.869139 u2DelayCellOfst[0]=14 cells (4 PI)
8142 11:45:16.872197 u2DelayCellOfst[1]=21 cells (6 PI)
8143 11:45:16.875531 u2DelayCellOfst[2]=10 cells (3 PI)
8144 11:45:16.879058 u2DelayCellOfst[3]=14 cells (4 PI)
8145 11:45:16.882304 u2DelayCellOfst[4]=10 cells (3 PI)
8146 11:45:16.885735 u2DelayCellOfst[5]=0 cells (0 PI)
8147 11:45:16.889036 u2DelayCellOfst[6]=21 cells (6 PI)
8148 11:45:16.892429 u2DelayCellOfst[7]=21 cells (6 PI)
8149 11:45:16.896153 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8150 11:45:16.898769 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8151 11:45:16.902165 == TX Byte 1 ==
8152 11:45:16.905691 u2DelayCellOfst[8]=0 cells (0 PI)
8153 11:45:16.905774 u2DelayCellOfst[9]=0 cells (0 PI)
8154 11:45:16.908857 u2DelayCellOfst[10]=3 cells (1 PI)
8155 11:45:16.912095 u2DelayCellOfst[11]=0 cells (0 PI)
8156 11:45:16.915924 u2DelayCellOfst[12]=10 cells (3 PI)
8157 11:45:16.919403 u2DelayCellOfst[13]=10 cells (3 PI)
8158 11:45:16.922534 u2DelayCellOfst[14]=14 cells (4 PI)
8159 11:45:16.925670 u2DelayCellOfst[15]=7 cells (2 PI)
8160 11:45:16.929404 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8161 11:45:16.935859 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8162 11:45:16.935946 DramC Write-DBI on
8163 11:45:16.936010 ==
8164 11:45:16.939243 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:45:16.942822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:45:16.946156 ==
8167 11:45:16.946262
8168 11:45:16.946324
8169 11:45:16.946382 TX Vref Scan disable
8170 11:45:16.949241 == TX Byte 0 ==
8171 11:45:16.953408 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8172 11:45:16.956446 == TX Byte 1 ==
8173 11:45:16.959445 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8174 11:45:16.959531 DramC Write-DBI off
8175 11:45:16.962674
8176 11:45:16.962761 [DATLAT]
8177 11:45:16.962825 Freq=1600, CH0 RK1
8178 11:45:16.962925
8179 11:45:16.966433 DATLAT Default: 0xf
8180 11:45:16.966519 0, 0xFFFF, sum = 0
8181 11:45:16.969689 1, 0xFFFF, sum = 0
8182 11:45:16.969780 2, 0xFFFF, sum = 0
8183 11:45:16.972923 3, 0xFFFF, sum = 0
8184 11:45:16.973015 4, 0xFFFF, sum = 0
8185 11:45:16.975984 5, 0xFFFF, sum = 0
8186 11:45:16.979406 6, 0xFFFF, sum = 0
8187 11:45:16.979504 7, 0xFFFF, sum = 0
8188 11:45:16.982838 8, 0xFFFF, sum = 0
8189 11:45:16.982965 9, 0xFFFF, sum = 0
8190 11:45:16.986055 10, 0xFFFF, sum = 0
8191 11:45:16.986153 11, 0xFFFF, sum = 0
8192 11:45:16.989345 12, 0xFFFF, sum = 0
8193 11:45:16.989439 13, 0xFFFF, sum = 0
8194 11:45:16.992866 14, 0x0, sum = 1
8195 11:45:16.992960 15, 0x0, sum = 2
8196 11:45:16.995956 16, 0x0, sum = 3
8197 11:45:16.996053 17, 0x0, sum = 4
8198 11:45:16.999503 best_step = 15
8199 11:45:16.999595
8200 11:45:16.999678 ==
8201 11:45:17.003059 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 11:45:17.006509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 11:45:17.006630 ==
8204 11:45:17.006727 RX Vref Scan: 0
8205 11:45:17.006816
8206 11:45:17.009684 RX Vref 0 -> 0, step: 1
8207 11:45:17.009804
8208 11:45:17.012977 RX Delay 11 -> 252, step: 4
8209 11:45:17.016474 iDelay=191, Bit 0, Center 128 (75 ~ 182) 108
8210 11:45:17.019672 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8211 11:45:17.026090 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8212 11:45:17.029566 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8213 11:45:17.033079 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8214 11:45:17.036083 iDelay=191, Bit 5, Center 116 (59 ~ 174) 116
8215 11:45:17.040035 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8216 11:45:17.046373 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8217 11:45:17.049741 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8218 11:45:17.052629 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8219 11:45:17.055966 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8220 11:45:17.059599 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8221 11:45:17.066435 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8222 11:45:17.069838 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8223 11:45:17.073300 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8224 11:45:17.075985 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8225 11:45:17.076066 ==
8226 11:45:17.079739 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 11:45:17.086084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 11:45:17.086169 ==
8229 11:45:17.086233 DQS Delay:
8230 11:45:17.089760 DQS0 = 0, DQS1 = 0
8231 11:45:17.089846 DQM Delay:
8232 11:45:17.089910 DQM0 = 127, DQM1 = 123
8233 11:45:17.092672 DQ Delay:
8234 11:45:17.096267 DQ0 =128, DQ1 =130, DQ2 =122, DQ3 =126
8235 11:45:17.099510 DQ4 =124, DQ5 =116, DQ6 =134, DQ7 =136
8236 11:45:17.102797 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
8237 11:45:17.106415 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8238 11:45:17.106498
8239 11:45:17.106562
8240 11:45:17.106620
8241 11:45:17.109903 [DramC_TX_OE_Calibration] TA2
8242 11:45:17.113274 Original DQ_B0 (3 6) =30, OEN = 27
8243 11:45:17.116497 Original DQ_B1 (3 6) =30, OEN = 27
8244 11:45:17.119544 24, 0x0, End_B0=24 End_B1=24
8245 11:45:17.119657 25, 0x0, End_B0=25 End_B1=25
8246 11:45:17.122952 26, 0x0, End_B0=26 End_B1=26
8247 11:45:17.126716 27, 0x0, End_B0=27 End_B1=27
8248 11:45:17.129626 28, 0x0, End_B0=28 End_B1=28
8249 11:45:17.129710 29, 0x0, End_B0=29 End_B1=29
8250 11:45:17.132986 30, 0x0, End_B0=30 End_B1=30
8251 11:45:17.136153 31, 0x4141, End_B0=30 End_B1=30
8252 11:45:17.139762 Byte0 end_step=30 best_step=27
8253 11:45:17.143019 Byte1 end_step=30 best_step=27
8254 11:45:17.146345 Byte0 TX OE(2T, 0.5T) = (3, 3)
8255 11:45:17.146423 Byte1 TX OE(2T, 0.5T) = (3, 3)
8256 11:45:17.146486
8257 11:45:17.149518
8258 11:45:17.156511 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8259 11:45:17.159754 CH0 RK1: MR19=303, MR18=160B
8260 11:45:17.166367 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8261 11:45:17.166458 [RxdqsGatingPostProcess] freq 1600
8262 11:45:17.173435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8263 11:45:17.177090 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 11:45:17.180014 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 11:45:17.183438 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 11:45:17.186876 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 11:45:17.189655 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 11:45:17.192964 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 11:45:17.196284 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 11:45:17.196366 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 11:45:17.199563 Pre-setting of DQS Precalculation
8272 11:45:17.206256 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8273 11:45:17.206337 ==
8274 11:45:17.209939 Dram Type= 6, Freq= 0, CH_1, rank 0
8275 11:45:17.213217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 11:45:17.213300 ==
8277 11:45:17.220218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 11:45:17.223078 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 11:45:17.226471 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 11:45:17.233100 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 11:45:17.242223 [CA 0] Center 43 (14~72) winsize 59
8282 11:45:17.245586 [CA 1] Center 43 (14~72) winsize 59
8283 11:45:17.249350 [CA 2] Center 38 (10~67) winsize 58
8284 11:45:17.252672 [CA 3] Center 37 (8~66) winsize 59
8285 11:45:17.255690 [CA 4] Center 38 (8~68) winsize 61
8286 11:45:17.259203 [CA 5] Center 37 (8~66) winsize 59
8287 11:45:17.259286
8288 11:45:17.262734 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8289 11:45:17.262841
8290 11:45:17.266070 [CATrainingPosCal] consider 1 rank data
8291 11:45:17.268996 u2DelayCellTimex100 = 275/100 ps
8292 11:45:17.272639 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8293 11:45:17.279435 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8294 11:45:17.282346 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8295 11:45:17.285681 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 11:45:17.289168 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8297 11:45:17.292883 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 11:45:17.292965
8299 11:45:17.296005 CA PerBit enable=1, Macro0, CA PI delay=37
8300 11:45:17.296087
8301 11:45:17.298782 [CBTSetCACLKResult] CA Dly = 37
8302 11:45:17.302338 CS Dly: 8 (0~39)
8303 11:45:17.305899 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 11:45:17.309230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 11:45:17.309312 ==
8306 11:45:17.312205 Dram Type= 6, Freq= 0, CH_1, rank 1
8307 11:45:17.315461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 11:45:17.315543 ==
8309 11:45:17.322554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 11:45:17.325879 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 11:45:17.332101 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 11:45:17.335960 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 11:45:17.345899 [CA 0] Center 42 (13~72) winsize 60
8314 11:45:17.348851 [CA 1] Center 42 (14~71) winsize 58
8315 11:45:17.352153 [CA 2] Center 37 (9~66) winsize 58
8316 11:45:17.355665 [CA 3] Center 36 (7~66) winsize 60
8317 11:45:17.358874 [CA 4] Center 38 (9~67) winsize 59
8318 11:45:17.362028 [CA 5] Center 37 (8~66) winsize 59
8319 11:45:17.362109
8320 11:45:17.365776 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8321 11:45:17.365858
8322 11:45:17.368825 [CATrainingPosCal] consider 2 rank data
8323 11:45:17.372311 u2DelayCellTimex100 = 275/100 ps
8324 11:45:17.375587 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8325 11:45:17.382340 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8326 11:45:17.385574 CA2 delay=38 (10~66),Diff = 1 PI (3 cell)
8327 11:45:17.389188 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8328 11:45:17.392460 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8329 11:45:17.395498 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8330 11:45:17.395579
8331 11:45:17.399368 CA PerBit enable=1, Macro0, CA PI delay=37
8332 11:45:17.399449
8333 11:45:17.402357 [CBTSetCACLKResult] CA Dly = 37
8334 11:45:17.405809 CS Dly: 10 (0~43)
8335 11:45:17.409124 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 11:45:17.412584 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 11:45:17.412666
8338 11:45:17.415551 ----->DramcWriteLeveling(PI) begin...
8339 11:45:17.415632 ==
8340 11:45:17.419215 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 11:45:17.422245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 11:45:17.425852 ==
8343 11:45:17.425960 Write leveling (Byte 0): 25 => 25
8344 11:45:17.429107 Write leveling (Byte 1): 27 => 27
8345 11:45:17.432083 DramcWriteLeveling(PI) end<-----
8346 11:45:17.432162
8347 11:45:17.432224 ==
8348 11:45:17.435872 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 11:45:17.442124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 11:45:17.442221 ==
8351 11:45:17.442284 [Gating] SW mode calibration
8352 11:45:17.452817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8353 11:45:17.455985 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8354 11:45:17.459064 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 11:45:17.465743 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 11:45:17.468752 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:45:17.472068 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:45:17.478951 1 4 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
8359 11:45:17.482344 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 11:45:17.485533 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 11:45:17.492047 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 11:45:17.496123 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 11:45:17.498988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 11:45:17.505747 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 11:45:17.509190 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8366 11:45:17.512548 1 5 16 | B1->B0 | 2929 3232 | 0 0 | (1 0) (0 1)
8367 11:45:17.519270 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8368 11:45:17.522193 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 11:45:17.525828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 11:45:17.532085 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 11:45:17.535952 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 11:45:17.539363 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 11:45:17.542122 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:45:17.549637 1 6 16 | B1->B0 | 3c3c 2d2d | 0 1 | (0 0) (0 0)
8375 11:45:17.552527 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8376 11:45:17.556096 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 11:45:17.562595 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 11:45:17.565715 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 11:45:17.568867 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 11:45:17.576026 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 11:45:17.579184 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 11:45:17.582707 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8383 11:45:17.589281 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:45:17.592167 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 11:45:17.596060 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 11:45:17.602552 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 11:45:17.606031 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 11:45:17.609104 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 11:45:17.616376 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 11:45:17.619607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:45:17.622760 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:45:17.626396 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:45:17.632857 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:45:17.636149 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:45:17.639844 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:45:17.646000 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:45:17.649529 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 11:45:17.652741 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8399 11:45:17.659650 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 11:45:17.659754 Total UI for P1: 0, mck2ui 16
8401 11:45:17.666021 best dqsien dly found for B0: ( 1, 9, 14)
8402 11:45:17.666105 Total UI for P1: 0, mck2ui 16
8403 11:45:17.672862 best dqsien dly found for B1: ( 1, 9, 14)
8404 11:45:17.675862 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8405 11:45:17.679246 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8406 11:45:17.679368
8407 11:45:17.682587 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8408 11:45:17.686384 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8409 11:45:17.689658 [Gating] SW calibration Done
8410 11:45:17.689739 ==
8411 11:45:17.692847 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 11:45:17.696289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 11:45:17.696371 ==
8414 11:45:17.699899 RX Vref Scan: 0
8415 11:45:17.699980
8416 11:45:17.700044 RX Vref 0 -> 0, step: 1
8417 11:45:17.700104
8418 11:45:17.702975 RX Delay 0 -> 252, step: 8
8419 11:45:17.706442 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8420 11:45:17.709572 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8421 11:45:17.716031 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8422 11:45:17.719871 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8423 11:45:17.723328 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8424 11:45:17.725967 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8425 11:45:17.729696 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8426 11:45:17.736422 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8427 11:45:17.739458 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8428 11:45:17.742721 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8429 11:45:17.745876 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8430 11:45:17.749354 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8431 11:45:17.755909 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8432 11:45:17.759305 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8433 11:45:17.762681 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8434 11:45:17.765899 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8435 11:45:17.765982 ==
8436 11:45:17.769503 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 11:45:17.775951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 11:45:17.776040 ==
8439 11:45:17.776104 DQS Delay:
8440 11:45:17.779364 DQS0 = 0, DQS1 = 0
8441 11:45:17.779446 DQM Delay:
8442 11:45:17.779509 DQM0 = 134, DQM1 = 126
8443 11:45:17.782525 DQ Delay:
8444 11:45:17.785897 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8445 11:45:17.789431 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8446 11:45:17.792496 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8447 11:45:17.796168 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8448 11:45:17.796255
8449 11:45:17.796319
8450 11:45:17.796377 ==
8451 11:45:17.799400 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 11:45:17.802740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 11:45:17.805821 ==
8454 11:45:17.805905
8455 11:45:17.805969
8456 11:45:17.806028 TX Vref Scan disable
8457 11:45:17.809761 == TX Byte 0 ==
8458 11:45:17.812444 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8459 11:45:17.816118 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8460 11:45:17.819360 == TX Byte 1 ==
8461 11:45:17.822684 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8462 11:45:17.826206 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8463 11:45:17.829266 ==
8464 11:45:17.829351 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 11:45:17.836356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 11:45:17.836444 ==
8467 11:45:17.847682
8468 11:45:17.851135 TX Vref early break, caculate TX vref
8469 11:45:17.854749 TX Vref=16, minBit 8, minWin=21, winSum=368
8470 11:45:17.858100 TX Vref=18, minBit 8, minWin=21, winSum=374
8471 11:45:17.861211 TX Vref=20, minBit 9, minWin=22, winSum=385
8472 11:45:17.864894 TX Vref=22, minBit 8, minWin=23, winSum=396
8473 11:45:17.868090 TX Vref=24, minBit 5, minWin=24, winSum=402
8474 11:45:17.874675 TX Vref=26, minBit 5, minWin=25, winSum=416
8475 11:45:17.878145 TX Vref=28, minBit 0, minWin=25, winSum=422
8476 11:45:17.881506 TX Vref=30, minBit 11, minWin=24, winSum=421
8477 11:45:17.884216 TX Vref=32, minBit 0, minWin=25, winSum=414
8478 11:45:17.888193 TX Vref=34, minBit 1, minWin=24, winSum=397
8479 11:45:17.894814 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8480 11:45:17.894953
8481 11:45:17.898046 Final TX Range 0 Vref 28
8482 11:45:17.898132
8483 11:45:17.898195 ==
8484 11:45:17.901461 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 11:45:17.904699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 11:45:17.904785 ==
8487 11:45:17.904849
8488 11:45:17.904908
8489 11:45:17.908228 TX Vref Scan disable
8490 11:45:17.911473 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8491 11:45:17.914711 == TX Byte 0 ==
8492 11:45:17.917900 u2DelayCellOfst[0]=17 cells (5 PI)
8493 11:45:17.921708 u2DelayCellOfst[1]=10 cells (3 PI)
8494 11:45:17.925068 u2DelayCellOfst[2]=0 cells (0 PI)
8495 11:45:17.928445 u2DelayCellOfst[3]=7 cells (2 PI)
8496 11:45:17.931667 u2DelayCellOfst[4]=7 cells (2 PI)
8497 11:45:17.931751 u2DelayCellOfst[5]=17 cells (5 PI)
8498 11:45:17.934853 u2DelayCellOfst[6]=17 cells (5 PI)
8499 11:45:17.938218 u2DelayCellOfst[7]=7 cells (2 PI)
8500 11:45:17.944603 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 11:45:17.948400 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8502 11:45:17.948486 == TX Byte 1 ==
8503 11:45:17.951333 u2DelayCellOfst[8]=0 cells (0 PI)
8504 11:45:17.955096 u2DelayCellOfst[9]=3 cells (1 PI)
8505 11:45:17.958225 u2DelayCellOfst[10]=10 cells (3 PI)
8506 11:45:17.961556 u2DelayCellOfst[11]=7 cells (2 PI)
8507 11:45:17.964428 u2DelayCellOfst[12]=14 cells (4 PI)
8508 11:45:17.968126 u2DelayCellOfst[13]=14 cells (4 PI)
8509 11:45:17.971167 u2DelayCellOfst[14]=17 cells (5 PI)
8510 11:45:17.974805 u2DelayCellOfst[15]=17 cells (5 PI)
8511 11:45:17.977981 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8512 11:45:17.981255 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 11:45:17.984702 DramC Write-DBI on
8514 11:45:17.984785 ==
8515 11:45:17.988267 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 11:45:17.991467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 11:45:17.991550 ==
8518 11:45:17.991614
8519 11:45:17.991673
8520 11:45:17.994278 TX Vref Scan disable
8521 11:45:17.997766 == TX Byte 0 ==
8522 11:45:18.001056 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8523 11:45:18.001138 == TX Byte 1 ==
8524 11:45:18.007790 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 11:45:18.007899 DramC Write-DBI off
8526 11:45:18.007991
8527 11:45:18.010841 [DATLAT]
8528 11:45:18.010988 Freq=1600, CH1 RK0
8529 11:45:18.011081
8530 11:45:18.014394 DATLAT Default: 0xf
8531 11:45:18.014476 0, 0xFFFF, sum = 0
8532 11:45:18.018231 1, 0xFFFF, sum = 0
8533 11:45:18.018319 2, 0xFFFF, sum = 0
8534 11:45:18.021560 3, 0xFFFF, sum = 0
8535 11:45:18.021646 4, 0xFFFF, sum = 0
8536 11:45:18.024864 5, 0xFFFF, sum = 0
8537 11:45:18.024952 6, 0xFFFF, sum = 0
8538 11:45:18.028012 7, 0xFFFF, sum = 0
8539 11:45:18.028121 8, 0xFFFF, sum = 0
8540 11:45:18.031144 9, 0xFFFF, sum = 0
8541 11:45:18.031230 10, 0xFFFF, sum = 0
8542 11:45:18.034296 11, 0xFFFF, sum = 0
8543 11:45:18.034381 12, 0xFFFF, sum = 0
8544 11:45:18.037916 13, 0xFFFF, sum = 0
8545 11:45:18.038002 14, 0x0, sum = 1
8546 11:45:18.041251 15, 0x0, sum = 2
8547 11:45:18.041340 16, 0x0, sum = 3
8548 11:45:18.044650 17, 0x0, sum = 4
8549 11:45:18.044741 best_step = 15
8550 11:45:18.044825
8551 11:45:18.044905 ==
8552 11:45:18.047862 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 11:45:18.054178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 11:45:18.054293 ==
8555 11:45:18.054380 RX Vref Scan: 1
8556 11:45:18.054491
8557 11:45:18.057791 Set Vref Range= 24 -> 127
8558 11:45:18.057876
8559 11:45:18.061613 RX Vref 24 -> 127, step: 1
8560 11:45:18.061744
8561 11:45:18.065089 RX Delay 11 -> 252, step: 4
8562 11:45:18.065174
8563 11:45:18.067801 Set Vref, RX VrefLevel [Byte0]: 24
8564 11:45:18.071151 [Byte1]: 24
8565 11:45:18.071275
8566 11:45:18.074201 Set Vref, RX VrefLevel [Byte0]: 25
8567 11:45:18.077683 [Byte1]: 25
8568 11:45:18.077767
8569 11:45:18.081337 Set Vref, RX VrefLevel [Byte0]: 26
8570 11:45:18.084637 [Byte1]: 26
8571 11:45:18.084722
8572 11:45:18.087735 Set Vref, RX VrefLevel [Byte0]: 27
8573 11:45:18.090846 [Byte1]: 27
8574 11:45:18.094856
8575 11:45:18.094964 Set Vref, RX VrefLevel [Byte0]: 28
8576 11:45:18.098394 [Byte1]: 28
8577 11:45:18.102996
8578 11:45:18.103082 Set Vref, RX VrefLevel [Byte0]: 29
8579 11:45:18.105882 [Byte1]: 29
8580 11:45:18.110408
8581 11:45:18.110494 Set Vref, RX VrefLevel [Byte0]: 30
8582 11:45:18.113916 [Byte1]: 30
8583 11:45:18.118105
8584 11:45:18.118190 Set Vref, RX VrefLevel [Byte0]: 31
8585 11:45:18.121295 [Byte1]: 31
8586 11:45:18.125442
8587 11:45:18.125527 Set Vref, RX VrefLevel [Byte0]: 32
8588 11:45:18.128623 [Byte1]: 32
8589 11:45:18.132929
8590 11:45:18.133015 Set Vref, RX VrefLevel [Byte0]: 33
8591 11:45:18.136536 [Byte1]: 33
8592 11:45:18.141058
8593 11:45:18.141143 Set Vref, RX VrefLevel [Byte0]: 34
8594 11:45:18.144130 [Byte1]: 34
8595 11:45:18.148246
8596 11:45:18.148333 Set Vref, RX VrefLevel [Byte0]: 35
8597 11:45:18.151671 [Byte1]: 35
8598 11:45:18.156436
8599 11:45:18.156523 Set Vref, RX VrefLevel [Byte0]: 36
8600 11:45:18.159608 [Byte1]: 36
8601 11:45:18.163929
8602 11:45:18.164015 Set Vref, RX VrefLevel [Byte0]: 37
8603 11:45:18.167167 [Byte1]: 37
8604 11:45:18.171750
8605 11:45:18.171837 Set Vref, RX VrefLevel [Byte0]: 38
8606 11:45:18.174678 [Byte1]: 38
8607 11:45:18.179026
8608 11:45:18.179131 Set Vref, RX VrefLevel [Byte0]: 39
8609 11:45:18.181939 [Byte1]: 39
8610 11:45:18.186564
8611 11:45:18.186682 Set Vref, RX VrefLevel [Byte0]: 40
8612 11:45:18.189930 [Byte1]: 40
8613 11:45:18.194063
8614 11:45:18.194148 Set Vref, RX VrefLevel [Byte0]: 41
8615 11:45:18.197352 [Byte1]: 41
8616 11:45:18.201415
8617 11:45:18.201502 Set Vref, RX VrefLevel [Byte0]: 42
8618 11:45:18.204835 [Byte1]: 42
8619 11:45:18.209228
8620 11:45:18.209312 Set Vref, RX VrefLevel [Byte0]: 43
8621 11:45:18.212822 [Byte1]: 43
8622 11:45:18.217090
8623 11:45:18.217175 Set Vref, RX VrefLevel [Byte0]: 44
8624 11:45:18.220018 [Byte1]: 44
8625 11:45:18.224517
8626 11:45:18.224604 Set Vref, RX VrefLevel [Byte0]: 45
8627 11:45:18.227889 [Byte1]: 45
8628 11:45:18.231843
8629 11:45:18.231928 Set Vref, RX VrefLevel [Byte0]: 46
8630 11:45:18.235528 [Byte1]: 46
8631 11:45:18.239578
8632 11:45:18.239664 Set Vref, RX VrefLevel [Byte0]: 47
8633 11:45:18.243317 [Byte1]: 47
8634 11:45:18.247148
8635 11:45:18.247231 Set Vref, RX VrefLevel [Byte0]: 48
8636 11:45:18.250612 [Byte1]: 48
8637 11:45:18.254790
8638 11:45:18.254885 Set Vref, RX VrefLevel [Byte0]: 49
8639 11:45:18.258463 [Byte1]: 49
8640 11:45:18.262394
8641 11:45:18.262476 Set Vref, RX VrefLevel [Byte0]: 50
8642 11:45:18.266061 [Byte1]: 50
8643 11:45:18.270427
8644 11:45:18.270509 Set Vref, RX VrefLevel [Byte0]: 51
8645 11:45:18.273653 [Byte1]: 51
8646 11:45:18.277620
8647 11:45:18.277702 Set Vref, RX VrefLevel [Byte0]: 52
8648 11:45:18.281410 [Byte1]: 52
8649 11:45:18.285596
8650 11:45:18.285678 Set Vref, RX VrefLevel [Byte0]: 53
8651 11:45:18.288955 [Byte1]: 53
8652 11:45:18.293151
8653 11:45:18.293235 Set Vref, RX VrefLevel [Byte0]: 54
8654 11:45:18.296344 [Byte1]: 54
8655 11:45:18.300828
8656 11:45:18.300912 Set Vref, RX VrefLevel [Byte0]: 55
8657 11:45:18.304152 [Byte1]: 55
8658 11:45:18.308239
8659 11:45:18.308338 Set Vref, RX VrefLevel [Byte0]: 56
8660 11:45:18.311694 [Byte1]: 56
8661 11:45:18.315826
8662 11:45:18.315913 Set Vref, RX VrefLevel [Byte0]: 57
8663 11:45:18.319336 [Byte1]: 57
8664 11:45:18.323438
8665 11:45:18.323520 Set Vref, RX VrefLevel [Byte0]: 58
8666 11:45:18.326621 [Byte1]: 58
8667 11:45:18.331418
8668 11:45:18.331498 Set Vref, RX VrefLevel [Byte0]: 59
8669 11:45:18.334740 [Byte1]: 59
8670 11:45:18.338665
8671 11:45:18.338745 Set Vref, RX VrefLevel [Byte0]: 60
8672 11:45:18.341715 [Byte1]: 60
8673 11:45:18.346367
8674 11:45:18.346452 Set Vref, RX VrefLevel [Byte0]: 61
8675 11:45:18.349417 [Byte1]: 61
8676 11:45:18.354348
8677 11:45:18.354455 Set Vref, RX VrefLevel [Byte0]: 62
8678 11:45:18.357142 [Byte1]: 62
8679 11:45:18.361373
8680 11:45:18.361457 Set Vref, RX VrefLevel [Byte0]: 63
8681 11:45:18.365080 [Byte1]: 63
8682 11:45:18.369061
8683 11:45:18.369142 Set Vref, RX VrefLevel [Byte0]: 64
8684 11:45:18.372536 [Byte1]: 64
8685 11:45:18.376519
8686 11:45:18.376596 Set Vref, RX VrefLevel [Byte0]: 65
8687 11:45:18.379989 [Byte1]: 65
8688 11:45:18.384062
8689 11:45:18.384140 Set Vref, RX VrefLevel [Byte0]: 66
8690 11:45:18.387538 [Byte1]: 66
8691 11:45:18.391953
8692 11:45:18.392050 Set Vref, RX VrefLevel [Byte0]: 67
8693 11:45:18.395141 [Byte1]: 67
8694 11:45:18.399533
8695 11:45:18.399619 Set Vref, RX VrefLevel [Byte0]: 68
8696 11:45:18.402947 [Byte1]: 68
8697 11:45:18.407309
8698 11:45:18.407395 Set Vref, RX VrefLevel [Byte0]: 69
8699 11:45:18.410727 [Byte1]: 69
8700 11:45:18.414733
8701 11:45:18.414834 Set Vref, RX VrefLevel [Byte0]: 70
8702 11:45:18.418177 [Byte1]: 70
8703 11:45:18.422703
8704 11:45:18.422812 Set Vref, RX VrefLevel [Byte0]: 71
8705 11:45:18.425470 [Byte1]: 71
8706 11:45:18.430036
8707 11:45:18.430119 Set Vref, RX VrefLevel [Byte0]: 72
8708 11:45:18.433452 [Byte1]: 72
8709 11:45:18.437407
8710 11:45:18.437489 Final RX Vref Byte 0 = 59 to rank0
8711 11:45:18.440741 Final RX Vref Byte 1 = 56 to rank0
8712 11:45:18.444139 Final RX Vref Byte 0 = 59 to rank1
8713 11:45:18.447604 Final RX Vref Byte 1 = 56 to rank1==
8714 11:45:18.451374 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 11:45:18.457902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 11:45:18.458013 ==
8717 11:45:18.458078 DQS Delay:
8718 11:45:18.458137 DQS0 = 0, DQS1 = 0
8719 11:45:18.461057 DQM Delay:
8720 11:45:18.461154 DQM0 = 131, DQM1 = 124
8721 11:45:18.464394 DQ Delay:
8722 11:45:18.467568 DQ0 =136, DQ1 =124, DQ2 =120, DQ3 =130
8723 11:45:18.470817 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8724 11:45:18.474443 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8725 11:45:18.477923 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8726 11:45:18.477997
8727 11:45:18.478058
8728 11:45:18.478114
8729 11:45:18.481164 [DramC_TX_OE_Calibration] TA2
8730 11:45:18.484124 Original DQ_B0 (3 6) =30, OEN = 27
8731 11:45:18.487495 Original DQ_B1 (3 6) =30, OEN = 27
8732 11:45:18.490742 24, 0x0, End_B0=24 End_B1=24
8733 11:45:18.490838 25, 0x0, End_B0=25 End_B1=25
8734 11:45:18.494492 26, 0x0, End_B0=26 End_B1=26
8735 11:45:18.497297 27, 0x0, End_B0=27 End_B1=27
8736 11:45:18.501316 28, 0x0, End_B0=28 End_B1=28
8737 11:45:18.501402 29, 0x0, End_B0=29 End_B1=29
8738 11:45:18.504384 30, 0x0, End_B0=30 End_B1=30
8739 11:45:18.507600 31, 0x4141, End_B0=30 End_B1=30
8740 11:45:18.511352 Byte0 end_step=30 best_step=27
8741 11:45:18.514407 Byte1 end_step=30 best_step=27
8742 11:45:18.517802 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 11:45:18.517908 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 11:45:18.517989
8745 11:45:18.521032
8746 11:45:18.528141 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8747 11:45:18.530579 CH1 RK0: MR19=303, MR18=1701
8748 11:45:18.537661 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8749 11:45:18.537751
8750 11:45:18.540919 ----->DramcWriteLeveling(PI) begin...
8751 11:45:18.541002 ==
8752 11:45:18.544276 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 11:45:18.547458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 11:45:18.547545 ==
8755 11:45:18.551047 Write leveling (Byte 0): 25 => 25
8756 11:45:18.554040 Write leveling (Byte 1): 28 => 28
8757 11:45:18.557312 DramcWriteLeveling(PI) end<-----
8758 11:45:18.557407
8759 11:45:18.557473 ==
8760 11:45:18.560642 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 11:45:18.563859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 11:45:18.563936 ==
8763 11:45:18.567552 [Gating] SW mode calibration
8764 11:45:18.573775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 11:45:18.580423 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 11:45:18.584043 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:45:18.587513 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:45:18.593658 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
8769 11:45:18.597065 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8770 11:45:18.600607 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 11:45:18.607223 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 11:45:18.610407 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 11:45:18.613708 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 11:45:18.621018 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 11:45:18.623657 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8776 11:45:18.627350 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8777 11:45:18.633576 1 5 12 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8778 11:45:18.636948 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 11:45:18.640192 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 11:45:18.647084 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 11:45:18.650362 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 11:45:18.653874 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 11:45:18.660500 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8784 11:45:18.663974 1 6 8 | B1->B0 | 2424 4242 | 0 1 | (0 0) (0 0)
8785 11:45:18.666803 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8786 11:45:18.670487 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 11:45:18.677678 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 11:45:18.680786 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 11:45:18.684191 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 11:45:18.690399 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 11:45:18.693828 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 11:45:18.697260 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8793 11:45:18.704167 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8794 11:45:18.707180 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8795 11:45:18.710476 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:45:18.717862 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:45:18.720693 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:45:18.723949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:45:18.730711 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 11:45:18.734175 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 11:45:18.737419 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:45:18.741042 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:45:18.747520 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:45:18.750587 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:45:18.754381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:45:18.761210 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:45:18.764321 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8808 11:45:18.767529 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 11:45:18.774273 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8810 11:45:18.774364 Total UI for P1: 0, mck2ui 16
8811 11:45:18.780913 best dqsien dly found for B0: ( 1, 9, 6)
8812 11:45:18.784088 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:45:18.787305 Total UI for P1: 0, mck2ui 16
8814 11:45:18.790888 best dqsien dly found for B1: ( 1, 9, 12)
8815 11:45:18.794197 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8816 11:45:18.797363 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8817 11:45:18.797475
8818 11:45:18.800729 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8819 11:45:18.804141 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8820 11:45:18.807846 [Gating] SW calibration Done
8821 11:45:18.807994 ==
8822 11:45:18.810802 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 11:45:18.814274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 11:45:18.814381 ==
8825 11:45:18.817480 RX Vref Scan: 0
8826 11:45:18.817561
8827 11:45:18.821023 RX Vref 0 -> 0, step: 1
8828 11:45:18.821104
8829 11:45:18.821167 RX Delay 0 -> 252, step: 8
8830 11:45:18.827724 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8831 11:45:18.831060 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8832 11:45:18.833862 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8833 11:45:18.837846 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8834 11:45:18.840720 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8835 11:45:18.848066 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8836 11:45:18.850611 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8837 11:45:18.854050 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8838 11:45:18.857663 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8839 11:45:18.860812 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8840 11:45:18.867925 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8841 11:45:18.870817 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8842 11:45:18.874083 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8843 11:45:18.877687 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8844 11:45:18.880917 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8845 11:45:18.887580 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8846 11:45:18.887670 ==
8847 11:45:18.890998 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 11:45:18.894074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 11:45:18.894157 ==
8850 11:45:18.894219 DQS Delay:
8851 11:45:18.897371 DQS0 = 0, DQS1 = 0
8852 11:45:18.897452 DQM Delay:
8853 11:45:18.901292 DQM0 = 132, DQM1 = 127
8854 11:45:18.901373 DQ Delay:
8855 11:45:18.904474 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8856 11:45:18.907707 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8857 11:45:18.910982 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8858 11:45:18.914215 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8859 11:45:18.914300
8860 11:45:18.914363
8861 11:45:18.917706 ==
8862 11:45:18.920642 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 11:45:18.923950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 11:45:18.924057 ==
8865 11:45:18.924157
8866 11:45:18.924244
8867 11:45:18.927568 TX Vref Scan disable
8868 11:45:18.927668 == TX Byte 0 ==
8869 11:45:18.930525 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8870 11:45:18.937529 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8871 11:45:18.937641 == TX Byte 1 ==
8872 11:45:18.941189 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8873 11:45:18.947074 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8874 11:45:18.947205 ==
8875 11:45:18.950373 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 11:45:18.953688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 11:45:18.953798 ==
8878 11:45:18.968091
8879 11:45:18.971218 TX Vref early break, caculate TX vref
8880 11:45:18.974496 TX Vref=16, minBit 8, minWin=22, winSum=371
8881 11:45:18.977767 TX Vref=18, minBit 9, minWin=22, winSum=388
8882 11:45:18.981774 TX Vref=20, minBit 8, minWin=23, winSum=396
8883 11:45:18.984731 TX Vref=22, minBit 8, minWin=23, winSum=400
8884 11:45:18.987819 TX Vref=24, minBit 0, minWin=25, winSum=411
8885 11:45:18.994374 TX Vref=26, minBit 8, minWin=25, winSum=416
8886 11:45:18.998026 TX Vref=28, minBit 5, minWin=25, winSum=421
8887 11:45:19.001265 TX Vref=30, minBit 9, minWin=25, winSum=421
8888 11:45:19.004389 TX Vref=32, minBit 0, minWin=24, winSum=413
8889 11:45:19.007616 TX Vref=34, minBit 8, minWin=24, winSum=403
8890 11:45:19.011794 TX Vref=36, minBit 0, minWin=24, winSum=396
8891 11:45:19.017655 [TxChooseVref] Worse bit 5, Min win 25, Win sum 421, Final Vref 28
8892 11:45:19.017742
8893 11:45:19.021050 Final TX Range 0 Vref 28
8894 11:45:19.021132
8895 11:45:19.021195 ==
8896 11:45:19.024409 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 11:45:19.027738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 11:45:19.027820 ==
8899 11:45:19.027883
8900 11:45:19.027942
8901 11:45:19.030772 TX Vref Scan disable
8902 11:45:19.037557 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8903 11:45:19.037640 == TX Byte 0 ==
8904 11:45:19.041277 u2DelayCellOfst[0]=17 cells (5 PI)
8905 11:45:19.044635 u2DelayCellOfst[1]=10 cells (3 PI)
8906 11:45:19.048139 u2DelayCellOfst[2]=0 cells (0 PI)
8907 11:45:19.051328 u2DelayCellOfst[3]=7 cells (2 PI)
8908 11:45:19.054732 u2DelayCellOfst[4]=7 cells (2 PI)
8909 11:45:19.057865 u2DelayCellOfst[5]=17 cells (5 PI)
8910 11:45:19.061604 u2DelayCellOfst[6]=17 cells (5 PI)
8911 11:45:19.064337 u2DelayCellOfst[7]=7 cells (2 PI)
8912 11:45:19.067705 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 11:45:19.070898 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 11:45:19.074231 == TX Byte 1 ==
8915 11:45:19.077830 u2DelayCellOfst[8]=0 cells (0 PI)
8916 11:45:19.077904 u2DelayCellOfst[9]=3 cells (1 PI)
8917 11:45:19.081258 u2DelayCellOfst[10]=10 cells (3 PI)
8918 11:45:19.084376 u2DelayCellOfst[11]=7 cells (2 PI)
8919 11:45:19.087828 u2DelayCellOfst[12]=14 cells (4 PI)
8920 11:45:19.091182 u2DelayCellOfst[13]=17 cells (5 PI)
8921 11:45:19.094500 u2DelayCellOfst[14]=17 cells (5 PI)
8922 11:45:19.098037 u2DelayCellOfst[15]=17 cells (5 PI)
8923 11:45:19.101468 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8924 11:45:19.107975 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 11:45:19.108078 DramC Write-DBI on
8926 11:45:19.108175 ==
8927 11:45:19.111109 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:45:19.114493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:45:19.117728 ==
8930 11:45:19.117802
8931 11:45:19.117867
8932 11:45:19.117936 TX Vref Scan disable
8933 11:45:19.121483 == TX Byte 0 ==
8934 11:45:19.124776 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8935 11:45:19.128395 == TX Byte 1 ==
8936 11:45:19.131567 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 11:45:19.131641 DramC Write-DBI off
8938 11:45:19.134717
8939 11:45:19.134785 [DATLAT]
8940 11:45:19.134847 Freq=1600, CH1 RK1
8941 11:45:19.134955
8942 11:45:19.137817 DATLAT Default: 0xf
8943 11:45:19.137909 0, 0xFFFF, sum = 0
8944 11:45:19.141612 1, 0xFFFF, sum = 0
8945 11:45:19.141714 2, 0xFFFF, sum = 0
8946 11:45:19.144772 3, 0xFFFF, sum = 0
8947 11:45:19.144899 4, 0xFFFF, sum = 0
8948 11:45:19.147896 5, 0xFFFF, sum = 0
8949 11:45:19.151409 6, 0xFFFF, sum = 0
8950 11:45:19.151487 7, 0xFFFF, sum = 0
8951 11:45:19.154616 8, 0xFFFF, sum = 0
8952 11:45:19.154724 9, 0xFFFF, sum = 0
8953 11:45:19.158212 10, 0xFFFF, sum = 0
8954 11:45:19.158288 11, 0xFFFF, sum = 0
8955 11:45:19.161146 12, 0xFFFF, sum = 0
8956 11:45:19.161249 13, 0xFFFF, sum = 0
8957 11:45:19.164663 14, 0x0, sum = 1
8958 11:45:19.164745 15, 0x0, sum = 2
8959 11:45:19.167914 16, 0x0, sum = 3
8960 11:45:19.168007 17, 0x0, sum = 4
8961 11:45:19.171455 best_step = 15
8962 11:45:19.171526
8963 11:45:19.171585 ==
8964 11:45:19.174917 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 11:45:19.177809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 11:45:19.177924 ==
8967 11:45:19.178013 RX Vref Scan: 0
8968 11:45:19.178074
8969 11:45:19.181402 RX Vref 0 -> 0, step: 1
8970 11:45:19.181476
8971 11:45:19.184501 RX Delay 11 -> 252, step: 4
8972 11:45:19.187962 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8973 11:45:19.194483 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8974 11:45:19.197935 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8975 11:45:19.201524 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8976 11:45:19.204847 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8977 11:45:19.208148 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8978 11:45:19.211514 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8979 11:45:19.218127 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8980 11:45:19.221528 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8981 11:45:19.224908 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8982 11:45:19.228226 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8983 11:45:19.231609 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8984 11:45:19.237985 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8985 11:45:19.241741 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8986 11:45:19.244959 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8987 11:45:19.248104 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8988 11:45:19.248184 ==
8989 11:45:19.251297 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 11:45:19.257924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 11:45:19.258003 ==
8992 11:45:19.258064 DQS Delay:
8993 11:45:19.261556 DQS0 = 0, DQS1 = 0
8994 11:45:19.261629 DQM Delay:
8995 11:45:19.261688 DQM0 = 129, DQM1 = 126
8996 11:45:19.264842 DQ Delay:
8997 11:45:19.268178 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
8998 11:45:19.271863 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
8999 11:45:19.274593 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9000 11:45:19.278427 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9001 11:45:19.278531
9002 11:45:19.278620
9003 11:45:19.278714
9004 11:45:19.281963 [DramC_TX_OE_Calibration] TA2
9005 11:45:19.284900 Original DQ_B0 (3 6) =30, OEN = 27
9006 11:45:19.288093 Original DQ_B1 (3 6) =30, OEN = 27
9007 11:45:19.291397 24, 0x0, End_B0=24 End_B1=24
9008 11:45:19.291483 25, 0x0, End_B0=25 End_B1=25
9009 11:45:19.294648 26, 0x0, End_B0=26 End_B1=26
9010 11:45:19.298013 27, 0x0, End_B0=27 End_B1=27
9011 11:45:19.302034 28, 0x0, End_B0=28 End_B1=28
9012 11:45:19.302115 29, 0x0, End_B0=29 End_B1=29
9013 11:45:19.304692 30, 0x0, End_B0=30 End_B1=30
9014 11:45:19.308230 31, 0x4141, End_B0=30 End_B1=30
9015 11:45:19.311554 Byte0 end_step=30 best_step=27
9016 11:45:19.314709 Byte1 end_step=30 best_step=27
9017 11:45:19.317952 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 11:45:19.318039 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 11:45:19.321300
9020 11:45:19.321378
9021 11:45:19.328251 [DQSOSCAuto] RK1, (LSB)MR18= 0x1318, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9022 11:45:19.331389 CH1 RK1: MR19=303, MR18=1318
9023 11:45:19.338276 CH1_RK1: MR19=0x303, MR18=0x1318, DQSOSC=397, MR23=63, INC=23, DEC=15
9024 11:45:19.341420 [RxdqsGatingPostProcess] freq 1600
9025 11:45:19.344462 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 11:45:19.348330 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 11:45:19.351087 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 11:45:19.354529 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 11:45:19.358310 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 11:45:19.361481 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 11:45:19.364650 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 11:45:19.368018 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 11:45:19.371512 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 11:45:19.374809 Pre-setting of DQS Precalculation
9035 11:45:19.378159 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 11:45:19.384907 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 11:45:19.391440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 11:45:19.391545
9039 11:45:19.391635
9040 11:45:19.394744 [Calibration Summary] 3200 Mbps
9041 11:45:19.398112 CH 0, Rank 0
9042 11:45:19.398206 SW Impedance : PASS
9043 11:45:19.401360 DUTY Scan : NO K
9044 11:45:19.404716 ZQ Calibration : PASS
9045 11:45:19.404787 Jitter Meter : NO K
9046 11:45:19.408206 CBT Training : PASS
9047 11:45:19.411023 Write leveling : PASS
9048 11:45:19.411093 RX DQS gating : PASS
9049 11:45:19.414386 RX DQ/DQS(RDDQC) : PASS
9050 11:45:19.418408 TX DQ/DQS : PASS
9051 11:45:19.418481 RX DATLAT : PASS
9052 11:45:19.421256 RX DQ/DQS(Engine): PASS
9053 11:45:19.421334 TX OE : PASS
9054 11:45:19.424610 All Pass.
9055 11:45:19.424681
9056 11:45:19.424741 CH 0, Rank 1
9057 11:45:19.428460 SW Impedance : PASS
9058 11:45:19.428564 DUTY Scan : NO K
9059 11:45:19.431466 ZQ Calibration : PASS
9060 11:45:19.434750 Jitter Meter : NO K
9061 11:45:19.434845 CBT Training : PASS
9062 11:45:19.437787 Write leveling : PASS
9063 11:45:19.441222 RX DQS gating : PASS
9064 11:45:19.441321 RX DQ/DQS(RDDQC) : PASS
9065 11:45:19.445117 TX DQ/DQS : PASS
9066 11:45:19.447889 RX DATLAT : PASS
9067 11:45:19.447979 RX DQ/DQS(Engine): PASS
9068 11:45:19.451631 TX OE : PASS
9069 11:45:19.451712 All Pass.
9070 11:45:19.451772
9071 11:45:19.454447 CH 1, Rank 0
9072 11:45:19.454515 SW Impedance : PASS
9073 11:45:19.458093 DUTY Scan : NO K
9074 11:45:19.461519 ZQ Calibration : PASS
9075 11:45:19.461597 Jitter Meter : NO K
9076 11:45:19.464797 CBT Training : PASS
9077 11:45:19.464868 Write leveling : PASS
9078 11:45:19.468296 RX DQS gating : PASS
9079 11:45:19.471737 RX DQ/DQS(RDDQC) : PASS
9080 11:45:19.471833 TX DQ/DQS : PASS
9081 11:45:19.474568 RX DATLAT : PASS
9082 11:45:19.478411 RX DQ/DQS(Engine): PASS
9083 11:45:19.478481 TX OE : PASS
9084 11:45:19.481184 All Pass.
9085 11:45:19.481254
9086 11:45:19.481313 CH 1, Rank 1
9087 11:45:19.484813 SW Impedance : PASS
9088 11:45:19.484908 DUTY Scan : NO K
9089 11:45:19.487966 ZQ Calibration : PASS
9090 11:45:19.491158 Jitter Meter : NO K
9091 11:45:19.491228 CBT Training : PASS
9092 11:45:19.495060 Write leveling : PASS
9093 11:45:19.497707 RX DQS gating : PASS
9094 11:45:19.497777 RX DQ/DQS(RDDQC) : PASS
9095 11:45:19.501205 TX DQ/DQS : PASS
9096 11:45:19.504957 RX DATLAT : PASS
9097 11:45:19.505048 RX DQ/DQS(Engine): PASS
9098 11:45:19.507933 TX OE : PASS
9099 11:45:19.508018 All Pass.
9100 11:45:19.508082
9101 11:45:19.511309 DramC Write-DBI on
9102 11:45:19.511408 PER_BANK_REFRESH: Hybrid Mode
9103 11:45:19.514839 TX_TRACKING: ON
9104 11:45:19.524391 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 11:45:19.531171 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 11:45:19.537951 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 11:45:19.541204 [FAST_K] Save calibration result to emmc
9108 11:45:19.544897 sync common calibartion params.
9109 11:45:19.548033 sync cbt_mode0:1, 1:1
9110 11:45:19.548115 dram_init: ddr_geometry: 2
9111 11:45:19.551033 dram_init: ddr_geometry: 2
9112 11:45:19.554680 dram_init: ddr_geometry: 2
9113 11:45:19.557887 0:dram_rank_size:100000000
9114 11:45:19.557961 1:dram_rank_size:100000000
9115 11:45:19.564564 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 11:45:19.568279 DFS_SHUFFLE_HW_MODE: ON
9117 11:45:19.571430 dramc_set_vcore_voltage set vcore to 725000
9118 11:45:19.571504 Read voltage for 1600, 0
9119 11:45:19.574380 Vio18 = 0
9120 11:45:19.574456 Vcore = 725000
9121 11:45:19.574516 Vdram = 0
9122 11:45:19.577827 Vddq = 0
9123 11:45:19.577902 Vmddr = 0
9124 11:45:19.581416 switch to 3200 Mbps bootup
9125 11:45:19.581495 [DramcRunTimeConfig]
9126 11:45:19.584861 PHYPLL
9127 11:45:19.584932 DPM_CONTROL_AFTERK: ON
9128 11:45:19.588233 PER_BANK_REFRESH: ON
9129 11:45:19.590959 REFRESH_OVERHEAD_REDUCTION: ON
9130 11:45:19.591032 CMD_PICG_NEW_MODE: OFF
9131 11:45:19.594800 XRTWTW_NEW_MODE: ON
9132 11:45:19.594877 XRTRTR_NEW_MODE: ON
9133 11:45:19.597947 TX_TRACKING: ON
9134 11:45:19.598020 RDSEL_TRACKING: OFF
9135 11:45:19.601285 DQS Precalculation for DVFS: ON
9136 11:45:19.604679 RX_TRACKING: OFF
9137 11:45:19.604753 HW_GATING DBG: ON
9138 11:45:19.607830 ZQCS_ENABLE_LP4: ON
9139 11:45:19.607902 RX_PICG_NEW_MODE: ON
9140 11:45:19.611363 TX_PICG_NEW_MODE: ON
9141 11:45:19.611436 ENABLE_RX_DCM_DPHY: ON
9142 11:45:19.614593 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 11:45:19.618373 DUMMY_READ_FOR_TRACKING: OFF
9144 11:45:19.621364 !!! SPM_CONTROL_AFTERK: OFF
9145 11:45:19.624425 !!! SPM could not control APHY
9146 11:45:19.624500 IMPEDANCE_TRACKING: ON
9147 11:45:19.627681 TEMP_SENSOR: ON
9148 11:45:19.627761 HW_SAVE_FOR_SR: OFF
9149 11:45:19.631337 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 11:45:19.634528 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 11:45:19.637943 Read ODT Tracking: ON
9152 11:45:19.641457 Refresh Rate DeBounce: ON
9153 11:45:19.641543 DFS_NO_QUEUE_FLUSH: ON
9154 11:45:19.644584 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 11:45:19.647898 ENABLE_DFS_RUNTIME_MRW: OFF
9156 11:45:19.647990 DDR_RESERVE_NEW_MODE: ON
9157 11:45:19.651234 MR_CBT_SWITCH_FREQ: ON
9158 11:45:19.654308 =========================
9159 11:45:19.673056 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 11:45:19.676315 dram_init: ddr_geometry: 2
9161 11:45:19.694583 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 11:45:19.697880 dram_init: dram init end (result: 0)
9163 11:45:19.704903 DRAM-K: Full calibration passed in 24514 msecs
9164 11:45:19.707820 MRC: failed to locate region type 0.
9165 11:45:19.707899 DRAM rank0 size:0x100000000,
9166 11:45:19.711389 DRAM rank1 size=0x100000000
9167 11:45:19.721025 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 11:45:19.727608 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 11:45:19.734421 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 11:45:19.741017 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 11:45:19.744211 DRAM rank0 size:0x100000000,
9172 11:45:19.747565 DRAM rank1 size=0x100000000
9173 11:45:19.747649 CBMEM:
9174 11:45:19.751421 IMD: root @ 0xfffff000 254 entries.
9175 11:45:19.754586 IMD: root @ 0xffffec00 62 entries.
9176 11:45:19.757882 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 11:45:19.760851 WARNING: RO_VPD is uninitialized or empty.
9178 11:45:19.767734 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 11:45:19.774751 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 11:45:19.787279 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9181 11:45:19.798369 BS: romstage times (exec / console): total (unknown) / 24028 ms
9182 11:45:19.798459
9183 11:45:19.798521
9184 11:45:19.808403 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 11:45:19.812013 ARM64: Exception handlers installed.
9186 11:45:19.815616 ARM64: Testing exception
9187 11:45:19.818555 ARM64: Done test exception
9188 11:45:19.818636 Enumerating buses...
9189 11:45:19.821865 Show all devs... Before device enumeration.
9190 11:45:19.825224 Root Device: enabled 1
9191 11:45:19.828612 CPU_CLUSTER: 0: enabled 1
9192 11:45:19.828681 CPU: 00: enabled 1
9193 11:45:19.832055 Compare with tree...
9194 11:45:19.832123 Root Device: enabled 1
9195 11:45:19.835366 CPU_CLUSTER: 0: enabled 1
9196 11:45:19.839118 CPU: 00: enabled 1
9197 11:45:19.839187 Root Device scanning...
9198 11:45:19.841955 scan_static_bus for Root Device
9199 11:45:19.845410 CPU_CLUSTER: 0 enabled
9200 11:45:19.848704 scan_static_bus for Root Device done
9201 11:45:19.852158 scan_bus: bus Root Device finished in 8 msecs
9202 11:45:19.852231 done
9203 11:45:19.858670 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 11:45:19.861971 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 11:45:19.869166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 11:45:19.872404 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 11:45:19.875480 Allocating resources...
9208 11:45:19.875550 Reading resources...
9209 11:45:19.878785 Root Device read_resources bus 0 link: 0
9210 11:45:19.882164 DRAM rank0 size:0x100000000,
9211 11:45:19.885820 DRAM rank1 size=0x100000000
9212 11:45:19.888727 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 11:45:19.892051 CPU: 00 missing read_resources
9214 11:45:19.895560 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 11:45:19.901971 Root Device read_resources bus 0 link: 0 done
9216 11:45:19.902043 Done reading resources.
9217 11:45:19.908657 Show resources in subtree (Root Device)...After reading.
9218 11:45:19.911982 Root Device child on link 0 CPU_CLUSTER: 0
9219 11:45:19.915226 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 11:45:19.925571 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 11:45:19.925655 CPU: 00
9222 11:45:19.928632 Root Device assign_resources, bus 0 link: 0
9223 11:45:19.932053 CPU_CLUSTER: 0 missing set_resources
9224 11:45:19.935327 Root Device assign_resources, bus 0 link: 0 done
9225 11:45:19.938756 Done setting resources.
9226 11:45:19.945222 Show resources in subtree (Root Device)...After assigning values.
9227 11:45:19.948598 Root Device child on link 0 CPU_CLUSTER: 0
9228 11:45:19.952099 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 11:45:19.962100 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 11:45:19.962183 CPU: 00
9231 11:45:19.965199 Done allocating resources.
9232 11:45:19.968400 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 11:45:19.972020 Enabling resources...
9234 11:45:19.972090 done.
9235 11:45:19.975334 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 11:45:19.979002 Initializing devices...
9237 11:45:19.979072 Root Device init
9238 11:45:19.982066 init hardware done!
9239 11:45:19.985475 0x00000018: ctrlr->caps
9240 11:45:19.985556 52.000 MHz: ctrlr->f_max
9241 11:45:19.988995 0.400 MHz: ctrlr->f_min
9242 11:45:19.992325 0x40ff8080: ctrlr->voltages
9243 11:45:19.992404 sclk: 390625
9244 11:45:19.995597 Bus Width = 1
9245 11:45:19.995668 sclk: 390625
9246 11:45:19.995729 Bus Width = 1
9247 11:45:19.998820 Early init status = 3
9248 11:45:20.002294 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 11:45:20.006064 in-header: 03 fc 00 00 01 00 00 00
9250 11:45:20.010028 in-data: 00
9251 11:45:20.013060 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 11:45:20.017309 in-header: 03 fd 00 00 00 00 00 00
9253 11:45:20.020907 in-data:
9254 11:45:20.024148 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 11:45:20.027585 in-header: 03 fc 00 00 01 00 00 00
9256 11:45:20.030930 in-data: 00
9257 11:45:20.034040 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 11:45:20.038857 in-header: 03 fd 00 00 00 00 00 00
9259 11:45:20.042381 in-data:
9260 11:45:20.045891 [SSUSB] Setting up USB HOST controller...
9261 11:45:20.049060 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 11:45:20.052416 [SSUSB] phy power-on done.
9263 11:45:20.055606 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 11:45:20.062750 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 11:45:20.066158 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 11:45:20.072620 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 11:45:20.079249 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 11:45:20.085793 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 11:45:20.092574 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 11:45:20.098850 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9271 11:45:20.098933 SPM: binary array size = 0x9dc
9272 11:45:20.105956 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 11:45:20.112269 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 11:45:20.118892 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 11:45:20.122366 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 11:45:20.125676 configure_display: Starting display init
9277 11:45:20.162025 anx7625_power_on_init: Init interface.
9278 11:45:20.165781 anx7625_disable_pd_protocol: Disabled PD feature.
9279 11:45:20.168821 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 11:45:20.196754 anx7625_start_dp_work: Secure OCM version=00
9281 11:45:20.200285 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 11:45:20.214695 sp_tx_get_edid_block: EDID Block = 1
9283 11:45:20.317685 Extracted contents:
9284 11:45:20.320519 header: 00 ff ff ff ff ff ff 00
9285 11:45:20.324406 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 11:45:20.327827 version: 01 04
9287 11:45:20.331004 basic params: 95 1f 11 78 0a
9288 11:45:20.333870 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 11:45:20.337378 established: 00 00 00
9290 11:45:20.344106 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 11:45:20.347645 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 11:45:20.354289 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 11:45:20.360998 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 11:45:20.367689 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 11:45:20.370402 extensions: 00
9296 11:45:20.370478 checksum: fb
9297 11:45:20.370539
9298 11:45:20.374489 Manufacturer: IVO Model 57d Serial Number 0
9299 11:45:20.377314 Made week 0 of 2020
9300 11:45:20.377383 EDID version: 1.4
9301 11:45:20.380678 Digital display
9302 11:45:20.384173 6 bits per primary color channel
9303 11:45:20.384251 DisplayPort interface
9304 11:45:20.387345 Maximum image size: 31 cm x 17 cm
9305 11:45:20.387414 Gamma: 220%
9306 11:45:20.390580 Check DPMS levels
9307 11:45:20.394258 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 11:45:20.397471 First detailed timing is preferred timing
9309 11:45:20.400896 Established timings supported:
9310 11:45:20.403941 Standard timings supported:
9311 11:45:20.404021 Detailed timings
9312 11:45:20.410688 Hex of detail: 383680a07038204018303c0035ae10000019
9313 11:45:20.413970 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 11:45:20.417613 0780 0798 07c8 0820 hborder 0
9315 11:45:20.424498 0438 043b 0447 0458 vborder 0
9316 11:45:20.424618 -hsync -vsync
9317 11:45:20.427659 Did detailed timing
9318 11:45:20.430967 Hex of detail: 000000000000000000000000000000000000
9319 11:45:20.434106 Manufacturer-specified data, tag 0
9320 11:45:20.441316 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 11:45:20.441408 ASCII string: InfoVision
9322 11:45:20.447586 Hex of detail: 000000fe00523134304e574635205248200a
9323 11:45:20.447709 ASCII string: R140NWF5 RH
9324 11:45:20.450952 Checksum
9325 11:45:20.451031 Checksum: 0xfb (valid)
9326 11:45:20.457810 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 11:45:20.457897 DSI data_rate: 832800000 bps
9328 11:45:20.465072 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 11:45:20.468656 anx7625_parse_edid: pixelclock(138800).
9330 11:45:20.471542 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 11:45:20.475308 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 11:45:20.478354 anx7625_dsi_config: config dsi.
9333 11:45:20.485212 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 11:45:20.499417 anx7625_dsi_config: success to config DSI
9335 11:45:20.503044 anx7625_dp_start: MIPI phy setup OK.
9336 11:45:20.506165 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 11:45:20.509737 mtk_ddp_mode_set invalid vrefresh 60
9338 11:45:20.513104 main_disp_path_setup
9339 11:45:20.513185 ovl_layer_smi_id_en
9340 11:45:20.515999 ovl_layer_smi_id_en
9341 11:45:20.516079 ccorr_config
9342 11:45:20.516142 aal_config
9343 11:45:20.519551 gamma_config
9344 11:45:20.519631 postmask_config
9345 11:45:20.522564 dither_config
9346 11:45:20.525996 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 11:45:20.533157 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 11:45:20.536556 Root Device init finished in 551 msecs
9349 11:45:20.536637 CPU_CLUSTER: 0 init
9350 11:45:20.546343 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 11:45:20.549421 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 11:45:20.552726 APU_MBOX 0x190000b0 = 0x10001
9353 11:45:20.556032 APU_MBOX 0x190001b0 = 0x10001
9354 11:45:20.559880 APU_MBOX 0x190005b0 = 0x10001
9355 11:45:20.562933 APU_MBOX 0x190006b0 = 0x10001
9356 11:45:20.566108 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 11:45:20.578288 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9358 11:45:20.590881 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 11:45:20.597544 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 11:45:20.609273 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9361 11:45:20.618203 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 11:45:20.621641 CPU_CLUSTER: 0 init finished in 81 msecs
9363 11:45:20.625273 Devices initialized
9364 11:45:20.628270 Show all devs... After init.
9365 11:45:20.628353 Root Device: enabled 1
9366 11:45:20.631438 CPU_CLUSTER: 0: enabled 1
9367 11:45:20.634879 CPU: 00: enabled 1
9368 11:45:20.638404 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9369 11:45:20.641301 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 11:45:20.644905 ELOG: NV offset 0x57f000 size 0x1000
9371 11:45:20.651177 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9372 11:45:20.657931 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 11:45:20.661373 ELOG: Event(17) added with size 13 at 2023-11-24 11:45:21 UTC
9374 11:45:20.664764 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 11:45:20.669129 in-header: 03 15 00 00 2c 00 00 00
9376 11:45:20.682276 in-data: 4a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 11:45:20.688911 ELOG: Event(A1) added with size 10 at 2023-11-24 11:45:21 UTC
9378 11:45:20.695690 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 11:45:20.702236 ELOG: Event(A0) added with size 9 at 2023-11-24 11:45:21 UTC
9380 11:45:20.706164 elog_add_boot_reason: Logged dev mode boot
9381 11:45:20.709004 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 11:45:20.712647 Finalize devices...
9383 11:45:20.712731 Devices finalized
9384 11:45:20.719359 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 11:45:20.722695 Writing coreboot table at 0xffe64000
9386 11:45:20.725629 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 11:45:20.729146 1. 0000000040000000-00000000400fffff: RAM
9388 11:45:20.732722 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 11:45:20.739216 3. 000000004032b000-00000000545fffff: RAM
9390 11:45:20.742546 4. 0000000054600000-000000005465ffff: BL31
9391 11:45:20.746157 5. 0000000054660000-00000000ffe63fff: RAM
9392 11:45:20.748999 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 11:45:20.756017 7. 0000000100000000-000000023fffffff: RAM
9394 11:45:20.756129 Passing 5 GPIOs to payload:
9395 11:45:20.762405 NAME | PORT | POLARITY | VALUE
9396 11:45:20.765805 EC in RW | 0x000000aa | low | undefined
9397 11:45:20.769019 EC interrupt | 0x00000005 | low | undefined
9398 11:45:20.775639 TPM interrupt | 0x000000ab | high | undefined
9399 11:45:20.778842 SD card detect | 0x00000011 | high | undefined
9400 11:45:20.785714 speaker enable | 0x00000093 | high | undefined
9401 11:45:20.789036 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 11:45:20.792406 in-header: 03 f9 00 00 02 00 00 00
9403 11:45:20.792489 in-data: 02 00
9404 11:45:20.795758 ADC[4]: Raw value=900221 ID=7
9405 11:45:20.798843 ADC[3]: Raw value=213336 ID=1
9406 11:45:20.798949 RAM Code: 0x71
9407 11:45:20.802227 ADC[6]: Raw value=74557 ID=0
9408 11:45:20.805649 ADC[5]: Raw value=212229 ID=1
9409 11:45:20.805730 SKU Code: 0x1
9410 11:45:20.812666 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd5
9411 11:45:20.815850 coreboot table: 964 bytes.
9412 11:45:20.819235 IMD ROOT 0. 0xfffff000 0x00001000
9413 11:45:20.822175 IMD SMALL 1. 0xffffe000 0x00001000
9414 11:45:20.825672 RO MCACHE 2. 0xffffc000 0x00001104
9415 11:45:20.829165 CONSOLE 3. 0xfff7c000 0x00080000
9416 11:45:20.832475 FMAP 4. 0xfff7b000 0x00000452
9417 11:45:20.835481 TIME STAMP 5. 0xfff7a000 0x00000910
9418 11:45:20.838793 VBOOT WORK 6. 0xfff66000 0x00014000
9419 11:45:20.841841 RAMOOPS 7. 0xffe66000 0x00100000
9420 11:45:20.845272 COREBOOT 8. 0xffe64000 0x00002000
9421 11:45:20.845371 IMD small region:
9422 11:45:20.848646 IMD ROOT 0. 0xffffec00 0x00000400
9423 11:45:20.852335 VPD 1. 0xffffeb80 0x0000006c
9424 11:45:20.855672 MMC STATUS 2. 0xffffeb60 0x00000004
9425 11:45:20.862396 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 11:45:20.862481 Probing TPM: done!
9427 11:45:20.868752 Connected to device vid:did:rid of 1ae0:0028:00
9428 11:45:20.875277 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 11:45:20.878617 Initialized TPM device CR50 revision 0
9430 11:45:20.882692 Checking cr50 for pending updates
9431 11:45:20.888644 Reading cr50 TPM mode
9432 11:45:20.897033 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 11:45:20.904161 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 11:45:20.944164 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9435 11:45:20.947908 Checking segment from ROM address 0x40100000
9436 11:45:20.951032 Checking segment from ROM address 0x4010001c
9437 11:45:20.957391 Loading segment from ROM address 0x40100000
9438 11:45:20.957480 code (compression=0)
9439 11:45:20.964414 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 11:45:20.974418 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 11:45:20.974505 it's not compressed!
9442 11:45:20.980805 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 11:45:20.984457 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 11:45:21.004265 Loading segment from ROM address 0x4010001c
9445 11:45:21.004364 Entry Point 0x80000000
9446 11:45:21.007391 Loaded segments
9447 11:45:21.010866 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 11:45:21.017484 Jumping to boot code at 0x80000000(0xffe64000)
9449 11:45:21.024571 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 11:45:21.031123 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 11:45:21.038955 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9452 11:45:21.042426 Checking segment from ROM address 0x40100000
9453 11:45:21.045505 Checking segment from ROM address 0x4010001c
9454 11:45:21.048723 Loading segment from ROM address 0x40100000
9455 11:45:21.052578 code (compression=1)
9456 11:45:21.059014 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 11:45:21.069146 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 11:45:21.069238 using LZMA
9459 11:45:21.077121 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 11:45:21.083725 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 11:45:21.087124 Loading segment from ROM address 0x4010001c
9462 11:45:21.087208 Entry Point 0x54601000
9463 11:45:21.090330 Loaded segments
9464 11:45:21.093696 NOTICE: MT8192 bl31_setup
9465 11:45:21.100605 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 11:45:21.104109 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 11:45:21.107302 WARNING: region 0:
9468 11:45:21.111144 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 11:45:21.111226 WARNING: region 1:
9470 11:45:21.117580 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 11:45:21.121159 WARNING: region 2:
9472 11:45:21.124482 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 11:45:21.127559 WARNING: region 3:
9474 11:45:21.131242 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 11:45:21.134538 WARNING: region 4:
9476 11:45:21.137570 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 11:45:21.141189 WARNING: region 5:
9478 11:45:21.144908 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 11:45:21.147537 WARNING: region 6:
9480 11:45:21.151547 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 11:45:21.151632 WARNING: region 7:
9482 11:45:21.157621 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 11:45:21.164865 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 11:45:21.167818 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 11:45:21.171171 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 11:45:21.174541 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 11:45:21.181179 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 11:45:21.184759 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 11:45:21.191649 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 11:45:21.194531 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 11:45:21.198445 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 11:45:21.205004 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 11:45:21.207926 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 11:45:21.212000 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 11:45:21.218084 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 11:45:21.221408 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 11:45:21.225186 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 11:45:21.231690 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 11:45:21.235146 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 11:45:21.241689 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 11:45:21.244744 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 11:45:21.248713 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 11:45:21.255111 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 11:45:21.258389 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 11:45:21.261973 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 11:45:21.268650 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 11:45:21.272021 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 11:45:21.278727 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 11:45:21.282141 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 11:45:21.285229 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 11:45:21.292073 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 11:45:21.295343 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 11:45:21.302252 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 11:45:21.305706 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 11:45:21.309054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 11:45:21.312524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 11:45:21.319064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 11:45:21.322471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 11:45:21.325762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 11:45:21.329666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 11:45:21.332845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 11:45:21.339305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 11:45:21.342625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 11:45:21.345982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 11:45:21.349673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 11:45:21.355731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 11:45:21.359305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 11:45:21.362853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 11:45:21.365936 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 11:45:21.372505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 11:45:21.376111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 11:45:21.382570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 11:45:21.386366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 11:45:21.389988 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 11:45:21.396050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 11:45:21.399368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 11:45:21.406458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 11:45:21.409730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 11:45:21.412656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 11:45:21.419647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 11:45:21.422717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 11:45:21.429605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 11:45:21.433364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 11:45:21.440096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 11:45:21.443512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 11:45:21.446413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 11:45:21.453248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 11:45:21.456562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 11:45:21.463605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 11:45:21.466582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 11:45:21.470074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 11:45:21.476570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 11:45:21.480192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 11:45:21.486958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 11:45:21.489951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 11:45:21.497205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 11:45:21.500311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 11:45:21.503783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 11:45:21.510194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 11:45:21.513646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 11:45:21.520521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 11:45:21.523631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 11:45:21.530846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 11:45:21.533866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 11:45:21.537316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 11:45:21.544189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 11:45:21.547604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 11:45:21.554112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 11:45:21.557339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 11:45:21.560662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 11:45:21.567301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 11:45:21.570848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 11:45:21.577347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 11:45:21.580989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 11:45:21.587439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 11:45:21.591052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 11:45:21.594576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 11:45:21.601279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 11:45:21.604439 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 11:45:21.608372 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 11:45:21.614380 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 11:45:21.617990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 11:45:21.621043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 11:45:21.624511 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 11:45:21.631336 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 11:45:21.634747 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 11:45:21.641059 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 11:45:21.644723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 11:45:21.647879 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 11:45:21.655048 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 11:45:21.657987 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 11:45:21.664844 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 11:45:21.668123 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 11:45:21.671557 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 11:45:21.678232 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 11:45:21.681511 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 11:45:21.688329 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 11:45:21.691537 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 11:45:21.695435 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 11:45:21.698273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 11:45:21.705223 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 11:45:21.708494 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 11:45:21.711951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 11:45:21.715548 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 11:45:21.721709 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 11:45:21.725105 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 11:45:21.728485 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 11:45:21.735655 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 11:45:21.739073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 11:45:21.742323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 11:45:21.748946 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 11:45:21.752593 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 11:45:21.756319 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 11:45:21.762036 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 11:45:21.765886 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 11:45:21.772268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 11:45:21.775773 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 11:45:21.779011 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 11:45:21.785975 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 11:45:21.789513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 11:45:21.795640 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 11:45:21.799273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 11:45:21.802805 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 11:45:21.809430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 11:45:21.812808 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 11:45:21.816188 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 11:45:21.822854 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 11:45:21.826064 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 11:45:21.829406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 11:45:21.836199 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 11:45:21.839532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 11:45:21.846519 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 11:45:21.849641 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 11:45:21.852868 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 11:45:21.860129 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 11:45:21.863455 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 11:45:21.867100 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 11:45:21.872894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 11:45:21.876799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 11:45:21.883144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 11:45:21.886457 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 11:45:21.889760 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 11:45:21.896500 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 11:45:21.899906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 11:45:21.907115 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 11:45:21.910015 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 11:45:21.913289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 11:45:21.920140 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 11:45:21.922988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 11:45:21.926377 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 11:45:21.933031 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 11:45:21.936733 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 11:45:21.943096 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 11:45:21.946813 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 11:45:21.949645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 11:45:21.957062 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 11:45:21.960101 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 11:45:21.966560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 11:45:21.969981 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 11:45:21.973170 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 11:45:21.980115 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 11:45:21.983072 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 11:45:21.986639 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 11:45:21.993264 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 11:45:21.996713 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 11:45:22.003526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 11:45:22.007049 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 11:45:22.009741 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 11:45:22.016434 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 11:45:22.020217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 11:45:22.026498 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 11:45:22.030018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 11:45:22.033336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 11:45:22.039875 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 11:45:22.043663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 11:45:22.050235 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 11:45:22.053631 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 11:45:22.056769 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 11:45:22.063514 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 11:45:22.067093 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 11:45:22.073500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 11:45:22.076830 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 11:45:22.079797 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 11:45:22.087246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 11:45:22.090263 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 11:45:22.096783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 11:45:22.100211 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 11:45:22.106712 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 11:45:22.110002 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 11:45:22.113310 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 11:45:22.120203 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 11:45:22.123233 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 11:45:22.130038 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 11:45:22.133294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 11:45:22.136979 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 11:45:22.143551 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 11:45:22.147006 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 11:45:22.153255 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 11:45:22.156918 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 11:45:22.160234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 11:45:22.166667 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 11:45:22.169947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 11:45:22.176682 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 11:45:22.180152 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 11:45:22.183484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 11:45:22.190339 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 11:45:22.193471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 11:45:22.200520 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 11:45:22.203663 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 11:45:22.210171 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 11:45:22.213680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 11:45:22.216937 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 11:45:22.220178 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 11:45:22.226981 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 11:45:22.230220 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 11:45:22.233575 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 11:45:22.237402 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 11:45:22.243591 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 11:45:22.247073 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 11:45:22.253854 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 11:45:22.257153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 11:45:22.260042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 11:45:22.267082 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 11:45:22.270102 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 11:45:22.273306 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 11:45:22.280221 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 11:45:22.283671 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 11:45:22.286774 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 11:45:22.293421 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 11:45:22.296668 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 11:45:22.300450 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 11:45:22.307096 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 11:45:22.310759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 11:45:22.313875 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 11:45:22.320232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 11:45:22.324346 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 11:45:22.327097 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 11:45:22.333947 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 11:45:22.337754 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 11:45:22.344126 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 11:45:22.347558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 11:45:22.350990 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 11:45:22.357470 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 11:45:22.360943 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 11:45:22.364617 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 11:45:22.371122 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 11:45:22.374171 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 11:45:22.377489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 11:45:22.384378 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 11:45:22.387520 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 11:45:22.391577 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 11:45:22.398330 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 11:45:22.401612 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 11:45:22.404301 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 11:45:22.407534 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 11:45:22.410894 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 11:45:22.418036 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 11:45:22.421344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 11:45:22.424593 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 11:45:22.427442 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 11:45:22.434580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 11:45:22.437977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 11:45:22.441280 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 11:45:22.447755 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 11:45:22.451130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 11:45:22.454623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 11:45:22.461050 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 11:45:22.464634 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 11:45:22.471609 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 11:45:22.474776 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 11:45:22.481249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 11:45:22.484616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 11:45:22.487949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 11:45:22.494801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 11:45:22.497918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 11:45:22.501441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 11:45:22.507870 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 11:45:22.511315 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 11:45:22.518119 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 11:45:22.521345 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 11:45:22.524549 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 11:45:22.531546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 11:45:22.534499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 11:45:22.541477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 11:45:22.544988 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 11:45:22.551056 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 11:45:22.554926 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 11:45:22.557858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 11:45:22.565298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 11:45:22.568792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 11:45:22.571064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 11:45:22.577918 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 11:45:22.581301 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 11:45:22.587691 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 11:45:22.591609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 11:45:22.594697 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 11:45:22.601371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 11:45:22.604777 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 11:45:22.611549 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 11:45:22.614829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 11:45:22.620988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 11:45:22.624874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 11:45:22.628343 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 11:45:22.634908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 11:45:22.638402 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 11:45:22.641867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 11:45:22.648407 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 11:45:22.651727 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 11:45:22.658268 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 11:45:22.661731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 11:45:22.668299 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 11:45:22.671846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 11:45:22.675068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 11:45:22.681566 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 11:45:22.684548 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 11:45:22.691241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 11:45:22.694347 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 11:45:22.697975 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 11:45:22.704599 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 11:45:22.707852 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 11:45:22.711027 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 11:45:22.717900 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 11:45:22.721512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 11:45:22.728462 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 11:45:22.731056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 11:45:22.738187 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 11:45:22.740834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 11:45:22.744575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 11:45:22.750906 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 11:45:22.754311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 11:45:22.761087 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 11:45:22.764838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 11:45:22.767974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 11:45:22.775105 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 11:45:22.777929 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 11:45:22.784833 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 11:45:22.788187 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 11:45:22.791238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 11:45:22.798374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 11:45:22.801926 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 11:45:22.807780 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 11:45:22.811686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 11:45:22.818232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 11:45:22.821477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 11:45:22.824905 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 11:45:22.831080 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 11:45:22.834433 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 11:45:22.841745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 11:45:22.844592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 11:45:22.851564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 11:45:22.854798 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 11:45:22.857828 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 11:45:22.865111 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 11:45:22.867828 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 11:45:22.874746 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 11:45:22.877707 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 11:45:22.884626 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 11:45:22.888079 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 11:45:22.891410 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 11:45:22.898149 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 11:45:22.901368 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 11:45:22.908244 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 11:45:22.911385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 11:45:22.918076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 11:45:22.921540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 11:45:22.924686 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 11:45:22.931358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 11:45:22.934828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 11:45:22.941692 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 11:45:22.944815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 11:45:22.948161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 11:45:22.954489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 11:45:22.958146 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 11:45:22.965420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 11:45:22.968348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 11:45:22.975525 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 11:45:22.978029 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 11:45:22.981374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 11:45:22.988650 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 11:45:22.991381 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 11:45:22.997990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 11:45:23.002316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 11:45:23.008491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 11:45:23.011817 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 11:45:23.014893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 11:45:23.021932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 11:45:23.025230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 11:45:23.031258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 11:45:23.034713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 11:45:23.041950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 11:45:23.045362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 11:45:23.051483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 11:45:23.055125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 11:45:23.057960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 11:45:23.065259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 11:45:23.068199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 11:45:23.075290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 11:45:23.077930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 11:45:23.085021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 11:45:23.088077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 11:45:23.094934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 11:45:23.098379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 11:45:23.105046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 11:45:23.108665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 11:45:23.115407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 11:45:23.118456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 11:45:23.125357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 11:45:23.128414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 11:45:23.135322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 11:45:23.138582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 11:45:23.145139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 11:45:23.148692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 11:45:23.155096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 11:45:23.158612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 11:45:23.165384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 11:45:23.168764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 11:45:23.171980 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 11:45:23.175467 INFO: [APUAPC] vio 0
9919 11:45:23.178678 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 11:45:23.185077 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 11:45:23.188841 INFO: [APUAPC] D0_APC_0: 0x400510
9922 11:45:23.192002 INFO: [APUAPC] D0_APC_1: 0x0
9923 11:45:23.195326 INFO: [APUAPC] D0_APC_2: 0x1540
9924 11:45:23.195829 INFO: [APUAPC] D0_APC_3: 0x0
9925 11:45:23.198459 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 11:45:23.202199 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 11:45:23.205570 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 11:45:23.208843 INFO: [APUAPC] D1_APC_3: 0x0
9929 11:45:23.212460 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 11:45:23.215316 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 11:45:23.218684 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 11:45:23.222268 INFO: [APUAPC] D2_APC_3: 0x0
9933 11:45:23.225952 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 11:45:23.228805 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 11:45:23.232163 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 11:45:23.235424 INFO: [APUAPC] D3_APC_3: 0x0
9937 11:45:23.239170 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 11:45:23.241951 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 11:45:23.245713 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 11:45:23.249118 INFO: [APUAPC] D4_APC_3: 0x0
9941 11:45:23.252639 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 11:45:23.255284 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 11:45:23.258791 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 11:45:23.262016 INFO: [APUAPC] D5_APC_3: 0x0
9945 11:45:23.265492 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 11:45:23.268894 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 11:45:23.272393 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 11:45:23.275616 INFO: [APUAPC] D6_APC_3: 0x0
9949 11:45:23.278888 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 11:45:23.282024 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 11:45:23.285759 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 11:45:23.289154 INFO: [APUAPC] D7_APC_3: 0x0
9953 11:45:23.292323 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 11:45:23.295656 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 11:45:23.299161 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 11:45:23.302206 INFO: [APUAPC] D8_APC_3: 0x0
9957 11:45:23.305758 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 11:45:23.309202 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 11:45:23.311927 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 11:45:23.315707 INFO: [APUAPC] D9_APC_3: 0x0
9961 11:45:23.319100 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 11:45:23.322659 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 11:45:23.325705 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 11:45:23.329269 INFO: [APUAPC] D10_APC_3: 0x0
9965 11:45:23.332535 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 11:45:23.335528 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 11:45:23.339128 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 11:45:23.339646 INFO: [APUAPC] D11_APC_3: 0x0
9969 11:45:23.345927 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 11:45:23.348942 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 11:45:23.352162 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 11:45:23.355634 INFO: [APUAPC] D12_APC_3: 0x0
9973 11:45:23.359174 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 11:45:23.362049 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 11:45:23.365913 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 11:45:23.369288 INFO: [APUAPC] D13_APC_3: 0x0
9977 11:45:23.372545 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 11:45:23.375588 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 11:45:23.379654 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 11:45:23.380173 INFO: [APUAPC] D14_APC_3: 0x0
9981 11:45:23.385726 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 11:45:23.389435 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 11:45:23.392936 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 11:45:23.393444 INFO: [APUAPC] D15_APC_3: 0x0
9985 11:45:23.395961 INFO: [APUAPC] APC_CON: 0x4
9986 11:45:23.399530 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 11:45:23.402745 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 11:45:23.406191 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 11:45:23.409671 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 11:45:23.412772 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 11:45:23.416045 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 11:45:23.419832 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 11:45:23.420341 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 11:45:23.422709 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 11:45:23.425798 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 11:45:23.429689 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 11:45:23.432533 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 11:45:23.435727 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 11:45:23.439329 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 11:45:23.442761 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 11:45:23.446224 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 11:45:23.449326 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 11:45:23.452647 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 11:45:23.453164 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 11:45:23.455993 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 11:45:23.459090 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 11:45:23.462363 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 11:45:23.466338 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 11:45:23.469693 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 11:45:23.472671 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 11:45:23.476289 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 11:45:23.479563 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 11:45:23.482939 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 11:45:23.486361 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 11:45:23.489682 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 11:45:23.490099 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 11:45:23.492406 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 11:45:23.496318 INFO: [NOCDAPC] APC_CON: 0x4
10019 11:45:23.499099 INFO: [APUAPC] set_apusys_apc done
10020 11:45:23.503384 INFO: [DEVAPC] devapc_init done
10021 11:45:23.506259 INFO: GICv3 without legacy support detected.
10022 11:45:23.512912 INFO: ARM GICv3 driver initialized in EL3
10023 11:45:23.516448 INFO: Maximum SPI INTID supported: 639
10024 11:45:23.519488 INFO: BL31: Initializing runtime services
10025 11:45:23.526218 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 11:45:23.529935 INFO: SPM: enable CPC mode
10027 11:45:23.533524 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 11:45:23.536050 INFO: BL31: Preparing for EL3 exit to normal world
10029 11:45:23.543129 INFO: Entry point address = 0x80000000
10030 11:45:23.543643 INFO: SPSR = 0x8
10031 11:45:23.549413
10032 11:45:23.549919
10033 11:45:23.550241
10034 11:45:23.552647 Starting depthcharge on Spherion...
10035 11:45:23.553103
10036 11:45:23.553431 Wipe memory regions:
10037 11:45:23.553733
10038 11:45:23.556276 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 11:45:23.556766 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 11:45:23.557159 Setting prompt string to ['asurada:']
10041 11:45:23.557804 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 11:45:23.558589 [0x00000040000000, 0x00000054600000)
10043 11:45:23.678346
10044 11:45:23.678927 [0x00000054660000, 0x00000080000000)
10045 11:45:23.938310
10046 11:45:23.938822 [0x000000821a7280, 0x000000ffe64000)
10047 11:45:24.683574
10048 11:45:24.684090 [0x00000100000000, 0x00000240000000)
10049 11:45:26.573667
10050 11:45:26.576144 Initializing XHCI USB controller at 0x11200000.
10051 11:45:27.615695
10052 11:45:27.618728 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 11:45:27.619350
10054 11:45:27.619714
10055 11:45:27.620045
10056 11:45:27.620844 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 11:45:27.722167 asurada: tftpboot 192.168.201.1 12074023/tftp-deploy-e2gwny5j/kernel/image.itb 12074023/tftp-deploy-e2gwny5j/kernel/cmdline
10059 11:45:27.722832 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 11:45:27.723389 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 11:45:27.727807 tftpboot 192.168.201.1 12074023/tftp-deploy-e2gwny5j/kernel/image.ittp-deploy-e2gwny5j/kernel/cmdline
10062 11:45:27.728278
10063 11:45:27.728637 Waiting for link
10064 11:45:27.888451
10065 11:45:27.889005 R8152: Initializing
10066 11:45:27.889378
10067 11:45:27.891411 Version 6 (ocp_data = 5c30)
10068 11:45:27.891974
10069 11:45:27.894815 R8152: Done initializing
10070 11:45:27.895321
10071 11:45:27.895779 Adding net device
10072 11:45:30.171450
10073 11:45:30.171968 done.
10074 11:45:30.172335
10075 11:45:30.172877 MAC: 00:24:32:30:78:52
10076 11:45:30.173377
10077 11:45:30.174784 Sending DHCP discover... done.
10078 11:45:30.175291
10079 11:45:30.178834 Waiting for reply... done.
10080 11:45:30.179564
10081 11:45:30.181530 Sending DHCP request... done.
10082 11:45:30.181988
10083 11:45:30.185373 Waiting for reply... done.
10084 11:45:30.185922
10085 11:45:30.186287 My ip is 192.168.201.14
10086 11:45:30.186633
10087 11:45:30.187922 The DHCP server ip is 192.168.201.1
10088 11:45:30.188387
10089 11:45:30.194474 TFTP server IP predefined by user: 192.168.201.1
10090 11:45:30.194988
10091 11:45:30.201350 Bootfile predefined by user: 12074023/tftp-deploy-e2gwny5j/kernel/image.itb
10092 11:45:30.201852
10093 11:45:30.204158 Sending tftp read request... done.
10094 11:45:30.204617
10095 11:45:30.210965 Waiting for the transfer...
10096 11:45:30.211388
10097 11:45:30.901149 00000000 ################################################################
10098 11:45:30.901634
10099 11:45:31.604299 00080000 ################################################################
10100 11:45:31.604829
10101 11:45:32.286198 00100000 ################################################################
10102 11:45:32.286711
10103 11:45:32.989625 00180000 ################################################################
10104 11:45:32.990131
10105 11:45:33.679762 00200000 ################################################################
10106 11:45:33.680257
10107 11:45:34.400960 00280000 ################################################################
10108 11:45:34.401478
10109 11:45:35.108587 00300000 ################################################################
10110 11:45:35.109079
10111 11:45:35.827278 00380000 ################################################################
10112 11:45:35.827802
10113 11:45:36.538816 00400000 ################################################################
10114 11:45:36.538986
10115 11:45:37.239952 00480000 ################################################################
10116 11:45:37.240443
10117 11:45:37.952494 00500000 ################################################################
10118 11:45:37.953054
10119 11:45:38.675582 00580000 ################################################################
10120 11:45:38.676093
10121 11:45:39.397482 00600000 ################################################################
10122 11:45:39.398046
10123 11:45:40.136203 00680000 ################################################################
10124 11:45:40.136714
10125 11:45:40.793032 00700000 ################################################################
10126 11:45:40.793178
10127 11:45:41.393817 00780000 ################################################################
10128 11:45:41.393951
10129 11:45:41.934090 00800000 ################################################################
10130 11:45:41.934224
10131 11:45:42.474987 00880000 ################################################################
10132 11:45:42.475123
10133 11:45:43.024519 00900000 ################################################################
10134 11:45:43.024655
10135 11:45:43.569917 00980000 ################################################################
10136 11:45:43.570055
10137 11:45:44.109608 00a00000 ################################################################
10138 11:45:44.109754
10139 11:45:44.631464 00a80000 ################################################################
10140 11:45:44.631607
10141 11:45:45.154954 00b00000 ################################################################
10142 11:45:45.155097
10143 11:45:45.690839 00b80000 ################################################################
10144 11:45:45.691025
10145 11:45:46.229641 00c00000 ################################################################
10146 11:45:46.229774
10147 11:45:46.773462 00c80000 ################################################################
10148 11:45:46.773593
10149 11:45:47.312070 00d00000 ################################################################
10150 11:45:47.312235
10151 11:45:47.888642 00d80000 ################################################################
10152 11:45:47.888787
10153 11:45:48.579886 00e00000 ################################################################
10154 11:45:48.580033
10155 11:45:49.212198 00e80000 ################################################################
10156 11:45:49.212332
10157 11:45:49.751677 00f00000 ################################################################
10158 11:45:49.751897
10159 11:45:50.277548 00f80000 ################################################################
10160 11:45:50.277703
10161 11:45:50.903447 01000000 ################################################################
10162 11:45:50.903588
10163 11:45:51.563187 01080000 ################################################################
10164 11:45:51.563335
10165 11:45:52.093184 01100000 ################################################################
10166 11:45:52.093356
10167 11:45:52.630842 01180000 ################################################################
10168 11:45:52.631012
10169 11:45:53.164968 01200000 ################################################################
10170 11:45:53.165106
10171 11:45:53.708917 01280000 ################################################################
10172 11:45:53.709050
10173 11:45:54.241335 01300000 ################################################################
10174 11:45:54.241538
10175 11:45:54.783647 01380000 ################################################################
10176 11:45:54.783780
10177 11:45:55.350694 01400000 ################################################################
10178 11:45:55.351376
10179 11:45:56.001555 01480000 ################################################################
10180 11:45:56.002122
10181 11:45:56.671799 01500000 ################################################################
10182 11:45:56.672407
10183 11:45:57.374152 01580000 ################################################################
10184 11:45:57.374709
10185 11:45:58.044546 01600000 ################################################################
10186 11:45:58.044682
10187 11:45:58.677612 01680000 ################################################################
10188 11:45:58.678124
10189 11:45:59.394237 01700000 ################################################################
10190 11:45:59.394962
10191 11:46:00.085728 01780000 ################################################################
10192 11:46:00.086389
10193 11:46:00.792216 01800000 ################################################################
10194 11:46:00.792732
10195 11:46:01.514997 01880000 ################################################################
10196 11:46:01.515790
10197 11:46:02.225782 01900000 ################################################################
10198 11:46:02.226297
10199 11:46:02.941522 01980000 ################################################################
10200 11:46:02.942036
10201 11:46:03.657572 01a00000 ################################################################
10202 11:46:03.658124
10203 11:46:04.378673 01a80000 ################################################################
10204 11:46:04.379275
10205 11:46:05.108834 01b00000 ################################################################
10206 11:46:05.109437
10207 11:46:05.824502 01b80000 ################################################################
10208 11:46:05.825013
10209 11:46:06.530552 01c00000 ################################################################
10210 11:46:06.530797
10211 11:46:07.236255 01c80000 ################################################################
10212 11:46:07.236811
10213 11:46:07.926896 01d00000 ################################################################
10214 11:46:07.927418
10215 11:46:08.613462 01d80000 ################################################################
10216 11:46:08.614002
10217 11:46:09.304527 01e00000 ################################################################
10218 11:46:09.305046
10219 11:46:09.950612 01e80000 ############################################################# done.
10220 11:46:09.951166
10221 11:46:09.953856 The bootfile was 32473770 bytes long.
10222 11:46:09.954277
10223 11:46:09.957275 Sending tftp read request... done.
10224 11:46:09.957693
10225 11:46:09.960800 Waiting for the transfer...
10226 11:46:09.961216
10227 11:46:09.961541 00000000 # done.
10228 11:46:09.961856
10229 11:46:09.970961 Command line loaded dynamically from TFTP file: 12074023/tftp-deploy-e2gwny5j/kernel/cmdline
10230 11:46:09.971385
10231 11:46:09.983797 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10232 11:46:09.984321
10233 11:46:09.984648 Loading FIT.
10234 11:46:09.984953
10235 11:46:09.987560 Image ramdisk-1 has 21376211 bytes.
10236 11:46:09.987976
10237 11:46:09.990677 Image fdt-1 has 47278 bytes.
10238 11:46:09.991122
10239 11:46:09.994099 Image kernel-1 has 11048246 bytes.
10240 11:46:09.994616
10241 11:46:10.003729 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10242 11:46:10.004238
10243 11:46:10.020659 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10244 11:46:10.021197
10245 11:46:10.024593 Choosing best match conf-1 for compat google,spherion-rev2.
10246 11:46:10.029669
10247 11:46:10.034045 Connected to device vid:did:rid of 1ae0:0028:00
10248 11:46:10.042432
10249 11:46:10.046004 tpm_get_response: command 0x17b, return code 0x0
10250 11:46:10.046471
10251 11:46:10.049153 ec_init: CrosEC protocol v3 supported (256, 248)
10252 11:46:10.053295
10253 11:46:10.056686 tpm_cleanup: add release locality here.
10254 11:46:10.057276
10255 11:46:10.057643 Shutting down all USB controllers.
10256 11:46:10.059850
10257 11:46:10.060310 Removing current net device
10258 11:46:10.060676
10259 11:46:10.066723 Exiting depthcharge with code 4 at timestamp: 75853064
10260 11:46:10.067313
10261 11:46:10.069812 LZMA decompressing kernel-1 to 0x821a6718
10262 11:46:10.070280
10263 11:46:10.073099 LZMA decompressing kernel-1 to 0x40000000
10264 11:46:11.461458
10265 11:46:11.462166 jumping to kernel
10266 11:46:11.463951 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10267 11:46:11.464478 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10268 11:46:11.464890 Setting prompt string to ['Linux version [0-9]']
10269 11:46:11.465261 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10270 11:46:11.465650 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10271 11:46:11.543244
10272 11:46:11.546424 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10273 11:46:11.550471 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10274 11:46:11.551119 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10275 11:46:11.551527 Setting prompt string to []
10276 11:46:11.552239 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10277 11:46:11.552697 Using line separator: #'\n'#
10278 11:46:11.553193 No login prompt set.
10279 11:46:11.553554 Parsing kernel messages
10280 11:46:11.553871 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10281 11:46:11.554436 [login-action] Waiting for messages, (timeout 00:03:37)
10282 11:46:11.570293 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10283 11:46:11.572924 [ 0.000000] random: crng init done
10284 11:46:11.576405 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10285 11:46:11.579758 [ 0.000000] efi: UEFI not found.
10286 11:46:11.589812 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10287 11:46:11.596621 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10288 11:46:11.606801 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10289 11:46:11.616554 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10290 11:46:11.622790 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10291 11:46:11.626652 [ 0.000000] printk: bootconsole [mtk8250] enabled
10292 11:46:11.635530 [ 0.000000] NUMA: No NUMA configuration found
10293 11:46:11.641764 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10294 11:46:11.647826 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10295 11:46:11.648288 [ 0.000000] Zone ranges:
10296 11:46:11.655025 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10297 11:46:11.658271 [ 0.000000] DMA32 empty
10298 11:46:11.665397 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10299 11:46:11.668065 [ 0.000000] Movable zone start for each node
10300 11:46:11.671980 [ 0.000000] Early memory node ranges
10301 11:46:11.678055 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10302 11:46:11.685581 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10303 11:46:11.692069 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10304 11:46:11.698960 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10305 11:46:11.702169 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10306 11:46:11.711834 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10307 11:46:11.766452 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10308 11:46:11.773199 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10309 11:46:11.779995 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10310 11:46:11.783610 [ 0.000000] psci: probing for conduit method from DT.
10311 11:46:11.790214 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10312 11:46:11.793626 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10313 11:46:11.800198 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10314 11:46:11.803470 [ 0.000000] psci: SMC Calling Convention v1.2
10315 11:46:11.810180 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10316 11:46:11.813241 [ 0.000000] Detected VIPT I-cache on CPU0
10317 11:46:11.819691 [ 0.000000] CPU features: detected: GIC system register CPU interface
10318 11:46:11.826356 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10319 11:46:11.833199 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10320 11:46:11.840048 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10321 11:46:11.846559 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10322 11:46:11.853013 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10323 11:46:11.859852 [ 0.000000] alternatives: applying boot alternatives
10324 11:46:11.863353 [ 0.000000] Fallback order for Node 0: 0
10325 11:46:11.869817 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10326 11:46:11.873040 [ 0.000000] Policy zone: Normal
10327 11:46:11.890077 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10328 11:46:11.899888 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10329 11:46:11.911181 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10330 11:46:11.920788 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10331 11:46:11.927674 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10332 11:46:11.930998 <6>[ 0.000000] software IO TLB: area num 8.
10333 11:46:11.987294 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10334 11:46:12.136848 <6>[ 0.000000] Memory: 7948748K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 404020K reserved, 32768K cma-reserved)
10335 11:46:12.143518 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10336 11:46:12.150272 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10337 11:46:12.153844 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10338 11:46:12.159996 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10339 11:46:12.166610 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10340 11:46:12.170252 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10341 11:46:12.179823 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10342 11:46:12.186939 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10343 11:46:12.190091 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10344 11:46:12.197595 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10345 11:46:12.200867 <6>[ 0.000000] GICv3: 608 SPIs implemented
10346 11:46:12.207914 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10347 11:46:12.211167 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10348 11:46:12.214457 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10349 11:46:12.221187 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10350 11:46:12.235211 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10351 11:46:12.248130 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10352 11:46:12.255101 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10353 11:46:12.263456 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10354 11:46:12.276965 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10355 11:46:12.283070 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10356 11:46:12.290114 <6>[ 0.009234] Console: colour dummy device 80x25
10357 11:46:12.300514 <6>[ 0.013988] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10358 11:46:12.303854 <6>[ 0.024429] pid_max: default: 32768 minimum: 301
10359 11:46:12.310260 <6>[ 0.029302] LSM: Security Framework initializing
10360 11:46:12.316912 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10361 11:46:12.326990 <6>[ 0.042052] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10362 11:46:12.333473 <6>[ 0.051512] cblist_init_generic: Setting adjustable number of callback queues.
10363 11:46:12.339981 <6>[ 0.058956] cblist_init_generic: Setting shift to 3 and lim to 1.
10364 11:46:12.346659 <6>[ 0.065294] cblist_init_generic: Setting adjustable number of callback queues.
10365 11:46:12.353596 <6>[ 0.072767] cblist_init_generic: Setting shift to 3 and lim to 1.
10366 11:46:12.360253 <6>[ 0.079166] rcu: Hierarchical SRCU implementation.
10367 11:46:12.366694 <6>[ 0.084182] rcu: Max phase no-delay instances is 1000.
10368 11:46:12.369919 <6>[ 0.091240] EFI services will not be available.
10369 11:46:12.376795 <6>[ 0.096194] smp: Bringing up secondary CPUs ...
10370 11:46:12.384217 <6>[ 0.101269] Detected VIPT I-cache on CPU1
10371 11:46:12.390845 <6>[ 0.101339] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10372 11:46:12.397721 <6>[ 0.101371] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10373 11:46:12.401043 <6>[ 0.101705] Detected VIPT I-cache on CPU2
10374 11:46:12.407104 <6>[ 0.101757] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10375 11:46:12.413847 <6>[ 0.101774] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10376 11:46:12.420510 <6>[ 0.102034] Detected VIPT I-cache on CPU3
10377 11:46:12.427126 <6>[ 0.102079] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10378 11:46:12.433916 <6>[ 0.102093] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10379 11:46:12.437673 <6>[ 0.102395] CPU features: detected: Spectre-v4
10380 11:46:12.443914 <6>[ 0.102402] CPU features: detected: Spectre-BHB
10381 11:46:12.447483 <6>[ 0.102406] Detected PIPT I-cache on CPU4
10382 11:46:12.453838 <6>[ 0.102463] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10383 11:46:12.460846 <6>[ 0.102480] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10384 11:46:12.467156 <6>[ 0.102773] Detected PIPT I-cache on CPU5
10385 11:46:12.473790 <6>[ 0.102838] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10386 11:46:12.480641 <6>[ 0.102854] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10387 11:46:12.483619 <6>[ 0.103133] Detected PIPT I-cache on CPU6
10388 11:46:12.490526 <6>[ 0.103198] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10389 11:46:12.497600 <6>[ 0.103214] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10390 11:46:12.503741 <6>[ 0.103506] Detected PIPT I-cache on CPU7
10391 11:46:12.510182 <6>[ 0.103571] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10392 11:46:12.517245 <6>[ 0.103587] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10393 11:46:12.520662 <6>[ 0.103634] smp: Brought up 1 node, 8 CPUs
10394 11:46:12.527029 <6>[ 0.245063] SMP: Total of 8 processors activated.
10395 11:46:12.530207 <6>[ 0.250014] CPU features: detected: 32-bit EL0 Support
10396 11:46:12.540536 <6>[ 0.255410] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10397 11:46:12.547055 <6>[ 0.264211] CPU features: detected: Common not Private translations
10398 11:46:12.550408 <6>[ 0.270726] CPU features: detected: CRC32 instructions
10399 11:46:12.557039 <6>[ 0.276078] CPU features: detected: RCpc load-acquire (LDAPR)
10400 11:46:12.563939 <6>[ 0.282075] CPU features: detected: LSE atomic instructions
10401 11:46:12.570524 <6>[ 0.287856] CPU features: detected: Privileged Access Never
10402 11:46:12.573840 <6>[ 0.293636] CPU features: detected: RAS Extension Support
10403 11:46:12.580212 <6>[ 0.299280] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10404 11:46:12.586963 <6>[ 0.306542] CPU: All CPU(s) started at EL2
10405 11:46:12.593377 <6>[ 0.310859] alternatives: applying system-wide alternatives
10406 11:46:12.602452 <6>[ 0.321564] devtmpfs: initialized
10407 11:46:12.614314 <6>[ 0.330478] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10408 11:46:12.624255 <6>[ 0.340442] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10409 11:46:12.627625 <6>[ 0.348345] pinctrl core: initialized pinctrl subsystem
10410 11:46:12.635276 <6>[ 0.355010] DMI not present or invalid.
10411 11:46:12.642086 <6>[ 0.359425] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10412 11:46:12.648685 <6>[ 0.366312] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10413 11:46:12.658540 <6>[ 0.373894] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10414 11:46:12.665377 <6>[ 0.382106] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10415 11:46:12.672267 <6>[ 0.390351] audit: initializing netlink subsys (disabled)
10416 11:46:12.678865 <5>[ 0.396044] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10417 11:46:12.685269 <6>[ 0.396750] thermal_sys: Registered thermal governor 'step_wise'
10418 11:46:12.691917 <6>[ 0.404010] thermal_sys: Registered thermal governor 'power_allocator'
10419 11:46:12.695719 <6>[ 0.410265] cpuidle: using governor menu
10420 11:46:12.701814 <6>[ 0.421230] NET: Registered PF_QIPCRTR protocol family
10421 11:46:12.708421 <6>[ 0.426716] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10422 11:46:12.715043 <6>[ 0.433823] ASID allocator initialised with 32768 entries
10423 11:46:12.718697 <6>[ 0.440390] Serial: AMBA PL011 UART driver
10424 11:46:12.729810 <4>[ 0.449185] Trying to register duplicate clock ID: 134
10425 11:46:12.784039 <6>[ 0.506836] KASLR enabled
10426 11:46:12.798270 <6>[ 0.514511] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10427 11:46:12.804714 <6>[ 0.521525] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10428 11:46:12.811781 <6>[ 0.528013] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10429 11:46:12.818097 <6>[ 0.535017] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10430 11:46:12.824660 <6>[ 0.541504] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10431 11:46:12.831289 <6>[ 0.548510] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10432 11:46:12.838235 <6>[ 0.554996] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10433 11:46:12.844837 <6>[ 0.562000] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10434 11:46:12.847991 <6>[ 0.569495] ACPI: Interpreter disabled.
10435 11:46:12.856654 <6>[ 0.575893] iommu: Default domain type: Translated
10436 11:46:12.863015 <6>[ 0.581004] iommu: DMA domain TLB invalidation policy: strict mode
10437 11:46:12.866260 <5>[ 0.587658] SCSI subsystem initialized
10438 11:46:12.872938 <6>[ 0.591826] usbcore: registered new interface driver usbfs
10439 11:46:12.880132 <6>[ 0.597558] usbcore: registered new interface driver hub
10440 11:46:12.883111 <6>[ 0.603108] usbcore: registered new device driver usb
10441 11:46:12.889502 <6>[ 0.609201] pps_core: LinuxPPS API ver. 1 registered
10442 11:46:12.899881 <6>[ 0.614395] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10443 11:46:12.903341 <6>[ 0.623743] PTP clock support registered
10444 11:46:12.906051 <6>[ 0.627985] EDAC MC: Ver: 3.0.0
10445 11:46:12.914037 <6>[ 0.633134] FPGA manager framework
10446 11:46:12.916715 <6>[ 0.636813] Advanced Linux Sound Architecture Driver Initialized.
10447 11:46:12.920732 <6>[ 0.643577] vgaarb: loaded
10448 11:46:12.927361 <6>[ 0.646747] clocksource: Switched to clocksource arch_sys_counter
10449 11:46:12.933920 <5>[ 0.653176] VFS: Disk quotas dquot_6.6.0
10450 11:46:12.940665 <6>[ 0.657356] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10451 11:46:12.943857 <6>[ 0.664543] pnp: PnP ACPI: disabled
10452 11:46:12.952126 <6>[ 0.671176] NET: Registered PF_INET protocol family
10453 11:46:12.961638 <6>[ 0.676761] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10454 11:46:12.973203 <6>[ 0.689039] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10455 11:46:12.982963 <6>[ 0.697853] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10456 11:46:12.989694 <6>[ 0.705821] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10457 11:46:12.995878 <6>[ 0.714522] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10458 11:46:13.007960 <6>[ 0.724271] TCP: Hash tables configured (established 65536 bind 65536)
10459 11:46:13.015135 <6>[ 0.731130] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10460 11:46:13.021175 <6>[ 0.738331] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10461 11:46:13.028007 <6>[ 0.746028] NET: Registered PF_UNIX/PF_LOCAL protocol family
10462 11:46:13.034893 <6>[ 0.752199] RPC: Registered named UNIX socket transport module.
10463 11:46:13.037938 <6>[ 0.758352] RPC: Registered udp transport module.
10464 11:46:13.044762 <6>[ 0.763286] RPC: Registered tcp transport module.
10465 11:46:13.051551 <6>[ 0.768217] RPC: Registered tcp NFSv4.1 backchannel transport module.
10466 11:46:13.054979 <6>[ 0.774885] PCI: CLS 0 bytes, default 64
10467 11:46:13.058230 <6>[ 0.779272] Unpacking initramfs...
10468 11:46:13.075150 <6>[ 0.791357] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10469 11:46:13.085283 <6>[ 0.800012] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10470 11:46:13.088543 <6>[ 0.808863] kvm [1]: IPA Size Limit: 40 bits
10471 11:46:13.094884 <6>[ 0.813391] kvm [1]: GICv3: no GICV resource entry
10472 11:46:13.098646 <6>[ 0.818412] kvm [1]: disabling GICv2 emulation
10473 11:46:13.105389 <6>[ 0.823100] kvm [1]: GIC system register CPU interface enabled
10474 11:46:13.108280 <6>[ 0.829277] kvm [1]: vgic interrupt IRQ18
10475 11:46:13.115153 <6>[ 0.833639] kvm [1]: VHE mode initialized successfully
10476 11:46:13.121311 <5>[ 0.840052] Initialise system trusted keyrings
10477 11:46:13.128515 <6>[ 0.844885] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10478 11:46:13.135392 <6>[ 0.854927] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10479 11:46:13.142112 <5>[ 0.861312] NFS: Registering the id_resolver key type
10480 11:46:13.145282 <5>[ 0.866618] Key type id_resolver registered
10481 11:46:13.152553 <5>[ 0.871032] Key type id_legacy registered
10482 11:46:13.158731 <6>[ 0.875313] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10483 11:46:13.165229 <6>[ 0.882233] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10484 11:46:13.171927 <6>[ 0.889961] 9p: Installing v9fs 9p2000 file system support
10485 11:46:13.208367 <5>[ 0.928141] Key type asymmetric registered
10486 11:46:13.211932 <5>[ 0.932475] Asymmetric key parser 'x509' registered
10487 11:46:13.222076 <6>[ 0.937642] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10488 11:46:13.225575 <6>[ 0.945258] io scheduler mq-deadline registered
10489 11:46:13.228785 <6>[ 0.950038] io scheduler kyber registered
10490 11:46:13.247741 <6>[ 0.967303] EINJ: ACPI disabled.
10491 11:46:13.280570 <4>[ 0.993211] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10492 11:46:13.290512 <4>[ 1.003838] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10493 11:46:13.304798 <6>[ 1.024541] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10494 11:46:13.313105 <6>[ 1.032481] printk: console [ttyS0] disabled
10495 11:46:13.341543 <6>[ 1.057154] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10496 11:46:13.347381 <6>[ 1.066635] printk: console [ttyS0] enabled
10497 11:46:13.351214 <6>[ 1.066635] printk: console [ttyS0] enabled
10498 11:46:13.357754 <6>[ 1.075530] printk: bootconsole [mtk8250] disabled
10499 11:46:13.360968 <6>[ 1.075530] printk: bootconsole [mtk8250] disabled
10500 11:46:13.367206 <6>[ 1.086659] SuperH (H)SCI(F) driver initialized
10501 11:46:13.370384 <6>[ 1.091937] msm_serial: driver initialized
10502 11:46:13.385063 <6>[ 1.101014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10503 11:46:13.394672 <6>[ 1.109563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10504 11:46:13.401547 <6>[ 1.118105] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10505 11:46:13.411324 <6>[ 1.126733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10506 11:46:13.418080 <6>[ 1.135446] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10507 11:46:13.427715 <6>[ 1.144160] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10508 11:46:13.438005 <6>[ 1.152706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10509 11:46:13.444526 <6>[ 1.161513] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10510 11:46:13.454180 <6>[ 1.170064] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10511 11:46:13.465902 <6>[ 1.185622] loop: module loaded
10512 11:46:13.472356 <6>[ 1.191635] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10513 11:46:13.495833 <4>[ 1.215071] mtk-pmic-keys: Failed to locate of_node [id: -1]
10514 11:46:13.502269 <6>[ 1.221948] megasas: 07.719.03.00-rc1
10515 11:46:13.512267 <6>[ 1.231690] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10516 11:46:13.522426 <6>[ 1.242124] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10517 11:46:13.539241 <6>[ 1.258898] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10518 11:46:13.596063 <6>[ 1.309080] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10519 11:46:13.962668 <6>[ 1.682336] Freeing initrd memory: 20868K
10520 11:46:13.978670 <6>[ 1.698247] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10521 11:46:13.989658 <6>[ 1.709157] tun: Universal TUN/TAP device driver, 1.6
10522 11:46:13.992856 <6>[ 1.715226] thunder_xcv, ver 1.0
10523 11:46:13.996688 <6>[ 1.718723] thunder_bgx, ver 1.0
10524 11:46:13.999456 <6>[ 1.722221] nicpf, ver 1.0
10525 11:46:14.010088 <6>[ 1.726253] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10526 11:46:14.013417 <6>[ 1.733729] hns3: Copyright (c) 2017 Huawei Corporation.
10527 11:46:14.016621 <6>[ 1.739317] hclge is initializing
10528 11:46:14.023558 <6>[ 1.742891] e1000: Intel(R) PRO/1000 Network Driver
10529 11:46:14.029901 <6>[ 1.748020] e1000: Copyright (c) 1999-2006 Intel Corporation.
10530 11:46:14.033233 <6>[ 1.754033] e1000e: Intel(R) PRO/1000 Network Driver
10531 11:46:14.040281 <6>[ 1.759248] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10532 11:46:14.046622 <6>[ 1.765432] igb: Intel(R) Gigabit Ethernet Network Driver
10533 11:46:14.053622 <6>[ 1.771082] igb: Copyright (c) 2007-2014 Intel Corporation.
10534 11:46:14.060311 <6>[ 1.776917] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10535 11:46:14.063561 <6>[ 1.783436] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10536 11:46:14.070952 <6>[ 1.789899] sky2: driver version 1.30
10537 11:46:14.076438 <6>[ 1.794907] VFIO - User Level meta-driver version: 0.3
10538 11:46:14.083747 <6>[ 1.803154] usbcore: registered new interface driver usb-storage
10539 11:46:14.090332 <6>[ 1.809603] usbcore: registered new device driver onboard-usb-hub
10540 11:46:14.099080 <6>[ 1.818802] mt6397-rtc mt6359-rtc: registered as rtc0
10541 11:46:14.109485 <6>[ 1.824265] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:46:14 UTC (1700826374)
10542 11:46:14.112520 <6>[ 1.833831] i2c_dev: i2c /dev entries driver
10543 11:46:14.129566 <6>[ 1.845647] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10544 11:46:14.149585 <6>[ 1.868633] cpu cpu0: EM: created perf domain
10545 11:46:14.152312 <6>[ 1.873468] cpu cpu4: EM: created perf domain
10546 11:46:14.159603 <6>[ 1.879077] sdhci: Secure Digital Host Controller Interface driver
10547 11:46:14.166315 <6>[ 1.885508] sdhci: Copyright(c) Pierre Ossman
10548 11:46:14.172715 <6>[ 1.890451] Synopsys Designware Multimedia Card Interface Driver
10549 11:46:14.179968 <6>[ 1.897091] sdhci-pltfm: SDHCI platform and OF driver helper
10550 11:46:14.183332 <6>[ 1.897165] mmc0: CQHCI version 5.10
10551 11:46:14.189541 <6>[ 1.907111] ledtrig-cpu: registered to indicate activity on CPUs
10552 11:46:14.196392 <6>[ 1.914098] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10553 11:46:14.203403 <6>[ 1.921152] usbcore: registered new interface driver usbhid
10554 11:46:14.206603 <6>[ 1.926976] usbhid: USB HID core driver
10555 11:46:14.213254 <6>[ 1.931180] spi_master spi0: will run message pump with realtime priority
10556 11:46:14.258699 <6>[ 1.971871] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10557 11:46:14.275144 <6>[ 1.988147] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10558 11:46:14.282719 <6>[ 2.001759] mmc0: Command Queue Engine enabled
10559 11:46:14.289235 <6>[ 2.006532] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10560 11:46:14.295766 <6>[ 2.013665] cros-ec-spi spi0.0: Chrome EC device registered
10561 11:46:14.299197 <6>[ 2.014034] mmcblk0: mmc0:0001 DA4128 116 GiB
10562 11:46:14.310202 <6>[ 2.029731] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10563 11:46:14.317904 <6>[ 2.037527] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10564 11:46:14.324455 <6>[ 2.043472] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10565 11:46:14.331244 <6>[ 2.049522] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10566 11:46:14.345650 <6>[ 2.061710] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10567 11:46:14.353072 <6>[ 2.072445] NET: Registered PF_PACKET protocol family
10568 11:46:14.356291 <6>[ 2.077900] 9pnet: Installing 9P2000 support
10569 11:46:14.362717 <5>[ 2.082474] Key type dns_resolver registered
10570 11:46:14.366100 <6>[ 2.087598] registered taskstats version 1
10571 11:46:14.372529 <5>[ 2.091996] Loading compiled-in X.509 certificates
10572 11:46:14.404600 <4>[ 2.117338] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 11:46:14.414705 <4>[ 2.128145] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 11:46:14.421137 <3>[ 2.138814] debugfs: File 'uA_load' in directory '/' already present!
10575 11:46:14.427567 <3>[ 2.145533] debugfs: File 'min_uV' in directory '/' already present!
10576 11:46:14.434376 <3>[ 2.152184] debugfs: File 'max_uV' in directory '/' already present!
10577 11:46:14.441203 <3>[ 2.158816] debugfs: File 'constraint_flags' in directory '/' already present!
10578 11:46:14.453150 <3>[ 2.169412] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10579 11:46:14.466508 <6>[ 2.185916] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10580 11:46:14.473120 <6>[ 2.192787] xhci-mtk 11200000.usb: xHCI Host Controller
10581 11:46:14.480133 <6>[ 2.198287] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10582 11:46:14.489763 <6>[ 2.206155] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10583 11:46:14.496366 <6>[ 2.215598] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10584 11:46:14.503064 <6>[ 2.221771] xhci-mtk 11200000.usb: xHCI Host Controller
10585 11:46:14.509634 <6>[ 2.227266] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10586 11:46:14.516395 <6>[ 2.234919] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10587 11:46:14.523306 <6>[ 2.242783] hub 1-0:1.0: USB hub found
10588 11:46:14.526241 <6>[ 2.246809] hub 1-0:1.0: 1 port detected
10589 11:46:14.533015 <6>[ 2.251109] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10590 11:46:14.540146 <6>[ 2.259849] hub 2-0:1.0: USB hub found
10591 11:46:14.543367 <6>[ 2.263877] hub 2-0:1.0: 1 port detected
10592 11:46:14.551329 <6>[ 2.271073] mtk-msdc 11f70000.mmc: Got CD GPIO
10593 11:46:14.563421 <6>[ 2.279665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10594 11:46:14.570430 <6>[ 2.287703] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10595 11:46:14.580171 <4>[ 2.295611] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10596 11:46:14.590274 <6>[ 2.305149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10597 11:46:14.597449 <6>[ 2.313226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10598 11:46:14.603507 <6>[ 2.321246] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10599 11:46:14.613274 <6>[ 2.329168] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10600 11:46:14.620472 <6>[ 2.336984] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10601 11:46:14.629935 <6>[ 2.344801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10602 11:46:14.639920 <6>[ 2.355329] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10603 11:46:14.646514 <6>[ 2.363714] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10604 11:46:14.656625 <6>[ 2.372061] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10605 11:46:14.663085 <6>[ 2.380400] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10606 11:46:14.673295 <6>[ 2.388740] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10607 11:46:14.680202 <6>[ 2.397078] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10608 11:46:14.690123 <6>[ 2.405415] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10609 11:46:14.696642 <6>[ 2.413754] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10610 11:46:14.706237 <6>[ 2.422093] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10611 11:46:14.713286 <6>[ 2.430431] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10612 11:46:14.722882 <6>[ 2.438770] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10613 11:46:14.729463 <6>[ 2.447110] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10614 11:46:14.739617 <6>[ 2.455449] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10615 11:46:14.746483 <6>[ 2.463787] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10616 11:46:14.756225 <6>[ 2.472126] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10617 11:46:14.762982 <6>[ 2.480866] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10618 11:46:14.769580 <6>[ 2.488008] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10619 11:46:14.776274 <6>[ 2.494776] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10620 11:46:14.782875 <6>[ 2.501542] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10621 11:46:14.789634 <6>[ 2.508475] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10622 11:46:14.800103 <6>[ 2.515316] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10623 11:46:14.810236 <6>[ 2.524450] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10624 11:46:14.819957 <6>[ 2.533568] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10625 11:46:14.826309 <6>[ 2.542863] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10626 11:46:14.836340 <6>[ 2.552336] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10627 11:46:14.845840 <6>[ 2.561803] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10628 11:46:14.856438 <6>[ 2.570923] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10629 11:46:14.866003 <6>[ 2.580390] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10630 11:46:14.872458 <6>[ 2.589507] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10631 11:46:14.882970 <6>[ 2.598801] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10632 11:46:14.895638 <6>[ 2.608961] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10633 11:46:14.902747 <6>[ 2.620349] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10634 11:46:14.958163 <6>[ 2.675020] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10635 11:46:15.112859 <6>[ 2.832885] hub 1-1:1.0: USB hub found
10636 11:46:15.116138 <6>[ 2.837417] hub 1-1:1.0: 4 ports detected
10637 11:46:15.126696 <6>[ 2.846160] hub 1-1:1.0: USB hub found
10638 11:46:15.129370 <6>[ 2.850549] hub 1-1:1.0: 4 ports detected
10639 11:46:15.238540 <6>[ 2.955358] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10640 11:46:15.264992 <6>[ 2.985055] hub 2-1:1.0: USB hub found
10641 11:46:15.268473 <6>[ 2.989567] hub 2-1:1.0: 3 ports detected
10642 11:46:15.278258 <6>[ 2.997790] hub 2-1:1.0: USB hub found
10643 11:46:15.281070 <6>[ 3.002271] hub 2-1:1.0: 3 ports detected
10644 11:46:15.454817 <6>[ 3.171054] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10645 11:46:15.586839 <6>[ 3.306776] hub 1-1.4:1.0: USB hub found
10646 11:46:15.590051 <6>[ 3.311421] hub 1-1.4:1.0: 2 ports detected
10647 11:46:15.599577 <6>[ 3.319301] hub 1-1.4:1.0: USB hub found
10648 11:46:15.602474 <6>[ 3.323900] hub 1-1.4:1.0: 2 ports detected
10649 11:46:15.666699 <6>[ 3.383194] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10650 11:46:15.898432 <6>[ 3.615073] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10651 11:46:16.090292 <6>[ 3.807043] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10652 11:46:27.203885 <6>[ 14.928097] ALSA device list:
10653 11:46:27.210474 <6>[ 14.931393] No soundcards found.
10654 11:46:27.218225 <6>[ 14.939488] Freeing unused kernel memory: 8384K
10655 11:46:27.221496 <6>[ 14.944486] Run /init as init process
10656 11:46:27.257565 Starting syslogd: OK
10657 11:46:27.263069 Starting klogd: OK
10658 11:46:27.273171 Running sysctl: OK
10659 11:46:27.282616 Populating /dev using udev: <30>[ 15.002390] udevd[194]: starting version 3.2.9
10660 11:46:27.289328 <27>[ 15.010264] udevd[194]: specified user 'tss' unknown
10661 11:46:27.296064 <27>[ 15.015632] udevd[194]: specified group 'tss' unknown
10662 11:46:27.299552 <30>[ 15.021912] udevd[195]: starting eudev-3.2.9
10663 11:46:27.319496 <27>[ 15.040119] udevd[195]: specified user 'tss' unknown
10664 11:46:27.325959 <27>[ 15.045543] udevd[195]: specified group 'tss' unknown
10665 11:46:27.441889 <6>[ 15.159064] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10666 11:46:27.448364 <6>[ 15.167056] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10667 11:46:27.458323 <6>[ 15.175927] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10668 11:46:27.480766 <3>[ 15.198488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 11:46:27.491102 <3>[ 15.207763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 11:46:27.497407 <3>[ 15.216229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 11:46:27.504071 <6>[ 15.219076] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 11:46:27.514160 <3>[ 15.224673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 11:46:27.517749 <6>[ 15.232751] mc: Linux media interface: v0.10
10674 11:46:27.524218 <6>[ 15.238542] remoteproc remoteproc0: scp is available
10675 11:46:27.527601 <6>[ 15.238657] remoteproc remoteproc0: powering up scp
10676 11:46:27.537274 <6>[ 15.238665] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10677 11:46:27.543809 <6>[ 15.238704] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10678 11:46:27.550963 <6>[ 15.238776] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10679 11:46:27.558003 <3>[ 15.239803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 11:46:27.567332 <3>[ 15.239807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 11:46:27.574339 <3>[ 15.239811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 11:46:27.583636 <3>[ 15.239814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 11:46:27.587040 <6>[ 15.240784] usbcore: registered new interface driver r8152
10684 11:46:27.598312 <3>[ 15.242915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 11:46:27.604604 <3>[ 15.242969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 11:46:27.614797 <3>[ 15.242973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 11:46:27.621360 <3>[ 15.242976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 11:46:27.628632 <3>[ 15.243008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 11:46:27.638581 <3>[ 15.243011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 11:46:27.645605 <3>[ 15.243014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:46:27.651844 <3>[ 15.243018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 11:46:27.662417 <3>[ 15.243020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 11:46:27.668577 <3>[ 15.243041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 11:46:27.678715 <4>[ 15.269104] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10695 11:46:27.682082 <4>[ 15.269104] Fallback method does not support PEC.
10696 11:46:27.688496 <6>[ 15.299078] videodev: Linux video capture interface: v2.00
10697 11:46:27.695996 <4>[ 15.302442] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10698 11:46:27.702003 <6>[ 15.308093] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10699 11:46:27.708640 <6>[ 15.308099] pci_bus 0000:00: root bus resource [bus 00-ff]
10700 11:46:27.715129 <6>[ 15.308103] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10701 11:46:27.725006 <6>[ 15.308105] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10702 11:46:27.731734 <6>[ 15.308133] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10703 11:46:27.738509 <6>[ 15.308148] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10704 11:46:27.745289 <6>[ 15.308212] pci 0000:00:00.0: supports D1 D2
10705 11:46:27.751795 <6>[ 15.308214] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10706 11:46:27.758206 <6>[ 15.309157] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10707 11:46:27.764926 <6>[ 15.311389] Bluetooth: Core ver 2.22
10708 11:46:27.768554 <6>[ 15.311522] NET: Registered PF_BLUETOOTH protocol family
10709 11:46:27.775140 <6>[ 15.311525] Bluetooth: HCI device and connection manager initialized
10710 11:46:27.781667 <6>[ 15.311546] Bluetooth: HCI socket layer initialized
10711 11:46:27.784813 <6>[ 15.311550] Bluetooth: L2CAP socket layer initialized
10712 11:46:27.791844 <6>[ 15.311560] Bluetooth: SCO socket layer initialized
10713 11:46:27.798302 <4>[ 15.315289] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10714 11:46:27.804603 <6>[ 15.323174] usbcore: registered new interface driver cdc_ether
10715 11:46:27.814765 <3>[ 15.323352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 11:46:27.821554 <6>[ 15.327679] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10717 11:46:27.827973 <6>[ 15.327706] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10718 11:46:27.834850 <6>[ 15.327725] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10719 11:46:27.841454 <6>[ 15.327740] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10720 11:46:27.848166 <6>[ 15.327852] pci 0000:01:00.0: supports D1 D2
10721 11:46:27.854625 <6>[ 15.327853] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 11:46:27.861139 <6>[ 15.343669] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10723 11:46:27.867946 <3>[ 15.358330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 11:46:27.877977 <6>[ 15.359593] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10725 11:46:27.884519 <6>[ 15.363847] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10726 11:46:27.894163 <6>[ 15.363984] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10727 11:46:27.901307 <6>[ 15.364013] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10728 11:46:27.907949 <6>[ 15.364044] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10729 11:46:27.917630 <6>[ 15.364063] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10730 11:46:27.924320 <6>[ 15.364081] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10731 11:46:27.930902 <6>[ 15.364103] pci 0000:00:00.0: PCI bridge to [bus 01]
10732 11:46:27.937476 <6>[ 15.364115] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10733 11:46:27.944361 <6>[ 15.364563] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10734 11:46:27.950775 <6>[ 15.366641] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10735 11:46:27.957708 <6>[ 15.371685] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10736 11:46:27.964142 <6>[ 15.379558] remoteproc remoteproc0: remote processor scp is now up
10737 11:46:27.970675 <6>[ 15.395179] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10738 11:46:27.977754 <6>[ 15.416226] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10739 11:46:27.987329 <6>[ 15.439058] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10740 11:46:27.997930 <6>[ 15.530773] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10741 11:46:28.007373 <6>[ 15.542436] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10742 11:46:28.014176 <4>[ 15.544403] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10743 11:46:28.024484 <4>[ 15.544421] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10744 11:46:28.033820 <6>[ 15.546485] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10745 11:46:28.037235 <6>[ 15.563035] r8152 2-1.3:1.0 eth0: v1.12.13
10746 11:46:28.043778 <6>[ 15.603042] usbcore: registered new interface driver r8153_ecm
10747 11:46:28.050528 <5>[ 15.613041] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10748 11:46:28.057162 <6>[ 15.660585] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10749 11:46:28.064318 <6>[ 15.662275] usbcore: registered new interface driver btusb
10750 11:46:28.074224 <4>[ 15.676904] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10751 11:46:28.080587 <6>[ 15.683736] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10752 11:46:28.093719 <6>[ 15.684405] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10753 11:46:28.100717 <6>[ 15.684732] usbcore: registered new interface driver uvcvideo
10754 11:46:28.103871 <3>[ 15.689185] Bluetooth: hci0: Failed to load firmware file (-2)
10755 11:46:28.110486 <3>[ 15.689199] Bluetooth: hci0: Failed to set up firmware (-2)
10756 11:46:28.120938 <4>[ 15.689214] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10757 11:46:28.127182 <5>[ 15.690319] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10758 11:46:28.137008 <4>[ 15.854302] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10759 11:46:28.143447 <6>[ 15.863185] cfg80211: failed to load regulatory.db
10760 11:46:28.183213 <6>[ 15.900908] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10761 11:46:28.190055 <6>[ 15.908405] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10762 11:46:28.214498 <6>[ 15.935278] mt7921e 0000:01:00.0: ASIC revision: 79610010
10763 11:46:28.320289 <4>[ 16.034517] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10764 11:46:28.320623 done
10765 11:46:28.341098 Saving random seed: OK
10766 11:46:28.356191 Starting network: OK
10767 11:46:28.387340 Starting dropbear sshd: <6>[ 16.108176] NET: Registered PF_INET6 protocol family
10768 11:46:28.393956 <6>[ 16.114404] Segment Routing with IPv6
10769 11:46:28.396826 <6>[ 16.118374] In-situ OAM (IOAM) with IPv6
10770 11:46:28.397286 OK
10771 11:46:28.410057 /bin/sh: can't access tty; job control turned off
10772 11:46:28.411091 Matched prompt #10: / #
10774 11:46:28.411964 Setting prompt string to ['/ #']
10775 11:46:28.412328 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10777 11:46:28.413606 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10778 11:46:28.414084 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
10779 11:46:28.414375 Setting prompt string to ['/ #']
10780 11:46:28.414758 Forcing a shell prompt, looking for ['/ #']
10782 11:46:28.465615 / #
10783 11:46:28.466041 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10784 11:46:28.466359 Waiting using forced prompt support (timeout 00:02:30)
10785 11:46:28.466791 <4>[ 16.153189] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 11:46:28.471759
10787 11:46:28.472461 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10788 11:46:28.472996 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
10789 11:46:28.473524 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10790 11:46:28.474046 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
10791 11:46:28.474566 end: 2 depthcharge-action (duration 00:01:40) [common]
10792 11:46:28.475085 start: 3 lava-test-retry (timeout 00:01:00) [common]
10793 11:46:28.475460 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10794 11:46:28.475792 Using namespace: common
10796 11:46:28.576526 / # #
10797 11:46:28.576709 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10798 11:46:28.576860 #<4>[ 16.273266] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 11:46:28.582416
10800 11:46:28.582767 Using /lava-12074023
10802 11:46:28.683319 / # export SHELL=/bin/sh
10803 11:46:28.684111 export SHELL=/bin/sh<4>[ 16.393198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 11:46:28.690042
10806 11:46:28.791729 / # . /lava-12074023/environment
10807 11:46:28.839157 . /lava-12074023/environment<4>[ 16.513661] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 11:46:28.839418
10810 11:46:28.940366 / # /lava-12074023/bin/lava-test-runner /lava-12074023/0
10811 11:46:28.941229 Test shell timeout: 10s (minimum of the action and connection timeout)
10812 11:46:28.943204 /lava-12074023/bin/lava-test-runner /lava-12074023/0<4>[ 16.633849] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 11:46:28.947194
10814 11:46:28.991397 + export 'TESTRUN_ID=0_dmesg'
10815 11:46:28.992183 +<8>[ 16.694277] <LAVA_SIGNAL_STARTRUN 0_dmesg 12074023_1.5.2.3.1>
10816 11:46:28.992658 cd /lava-12074023/0/tests/0_dmesg
10817 11:46:28.992986 + cat uuid
10818 11:46:28.993308 + UUID=12074023_1.5.2.3.1
10819 11:46:28.993625 + set +x
10820 11:46:28.993916 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10821 11:46:28.994534 Received signal: <STARTRUN> 0_dmesg 12074023_1.5.2.3.1
10822 11:46:28.995054 Starting test lava.0_dmesg (12074023_1.5.2.3.1)
10823 11:46:28.995463 Skipping test definition patterns.
10824 11:46:29.003940 <8>[ 16.721814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10825 11:46:29.004604 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10827 11:46:29.036442 <8>[ 16.754068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10828 11:46:29.037242 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10830 11:46:29.049775 <4>[ 16.763124] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 11:46:29.063374 <8>[ 16.781116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10832 11:46:29.063934 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10834 11:46:29.069654 + <8>[ 16.790827] <LAVA_SIGNAL_ENDRUN 0_dmesg 12074023_1.5.2.3.1>
10835 11:46:29.069962 set +x
10836 11:46:29.070426 Received signal: <ENDRUN> 0_dmesg 12074023_1.5.2.3.1
10837 11:46:29.070709 Ending use of test pattern.
10838 11:46:29.070962 Ending test lava.0_dmesg (12074023_1.5.2.3.1), duration 0.08
10840 11:46:29.073215 <LAVA_TEST_RUNNER EXIT>
10841 11:46:29.073657 ok: lava_test_shell seems to have completed
10842 11:46:29.074030 alert: pass
crit: pass
emerg: pass
10843 11:46:29.074336 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10844 11:46:29.074569 end: 3 lava-test-retry (duration 00:00:01) [common]
10845 11:46:29.074795 start: 4 lava-test-retry (timeout 00:01:00) [common]
10846 11:46:29.075044 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10847 11:46:29.075228 Using namespace: common
10849 11:46:29.175827 / # #
10850 11:46:29.176171 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10851 11:46:29.176402 Using /lava-12074023
10853 11:46:29.277135 export SHELL=/bin/sh
10854 11:46:29.277965 #<4>[ 16.881664] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 11:46:29.278350
10857 11:46:29.379765 / # export SHELL=/bin/sh<4>[ 17.001638] mt7921e 0000:01:00.0. /lava-12074023/environment
10858 11:46:29.380484 : Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 11:46:29.380842
10861 11:46:29.482109 / # . /lava-12074023/environment/lava-12074023/bin/lava-test-runner /lava-12074023/1
10862 11:46:29.482523 Test shell timeout: 10s (minimum of the action and connection timeout)
10863 11:46:29.482967
10864 11:46:29.483241 / # <4>[ 17.121833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 11:46:29.527071 /lava-12074023/bin/lava-test-runner /lava-12074023/1
10866 11:46:29.527320 <3>[ 17.240699] mt7921e 0000:01:00.0: hardware init failed
10867 11:46:29.527457 + export 'TESTRUN_ID=1_bootrr'
10868 11:46:29.529610 <8>[ 17.248113] <LAVA_SIGNAL_STARTRUN 1_bootrr 12074023_1.5.2.3.5>
10869 11:46:29.529979 Received signal: <STARTRUN> 1_bootrr 12074023_1.5.2.3.5
10870 11:46:29.530123 Starting test lava.1_bootrr (12074023_1.5.2.3.5)
10871 11:46:29.530287 Skipping test definition patterns.
10872 11:46:29.532774 + cd /lava-12074023/1/tests/1_bootrr
10873 11:46:29.532974 + cat uuid
10874 11:46:29.536144 + UUID=12074023_1.5.2.3.5
10875 11:46:29.536427 + set +x
10876 11:46:29.546249 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12074023/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10877 11:46:29.552919 <8>[ 17.271146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10878 11:46:29.553214
10879 11:46:29.553783 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10881 11:46:29.556459 + cd /opt/bootrr/libexec/bootrr
10882 11:46:29.559597 + sh helpers/bootrr-auto
10883 11:46:29.562647 /lava-12074023/1/../bin/lava-test-case
10884 11:46:29.566659 /lava-12074023/1/../bin/lava-test-case
10885 11:46:29.572482 <8>[ 17.291103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10886 11:46:29.573091 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10888 11:46:29.579310 /usr/bin/tpm2_getcap
10889 11:46:29.614051 /lava-12074023/1/../bin/lava-test-case
10890 11:46:29.620336 <8>[ 17.338527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10891 11:46:29.621019 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10893 11:46:29.637250 /lava-12074023/1/../bin/lava-test-case
10894 11:46:29.643720 <8>[ 17.362242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10895 11:46:29.644571 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10897 11:46:29.656465 /lava-12074023/1/../bin/lava-test-case
10898 11:46:29.663658 <8>[ 17.382607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10899 11:46:29.664312 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10901 11:46:29.677330 /lava-12074023/1/../bin/lava-test-case
10902 11:46:29.684335 <8>[ 17.402301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10903 11:46:29.684954 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10905 11:46:29.696173 /lava-12074023/1/../bin/lava-test-case
10906 11:46:29.702381 <8>[ 17.421669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10907 11:46:29.703080 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10909 11:46:29.715072 /lava-12074023/1/../bin/lava-test-case
10910 11:46:29.721829 <8>[ 17.440329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10911 11:46:29.722595 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10913 11:46:29.732853 /lava-12074023/1/../bin/lava-test-case
10914 11:46:29.738816 <8>[ 17.457414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10915 11:46:29.739536 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10917 11:46:29.750975 /lava-12074023/1/../bin/lava-test-case
10918 11:46:29.757002 <8>[ 17.474715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10919 11:46:29.757839 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10921 11:46:29.765100 /lava-12074023/1/../bin/lava-test-case
10922 11:46:29.775100 <8>[ 17.490974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10923 11:46:29.775614 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10925 11:46:29.786351 /lava-12074023/1/../bin/lava-test-case
10926 11:46:29.792505 <8>[ 17.510667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10927 11:46:29.793021 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10929 11:46:29.804394 /lava-12074023/1/../bin/lava-test-case
10930 11:46:29.811076 <8>[ 17.529083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10931 11:46:29.811593 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10933 11:46:29.822621 /lava-12074023/1/../bin/lava-test-case
10934 11:46:29.829100 <8>[ 17.547257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10935 11:46:29.829714 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10937 11:46:29.841500 /lava-12074023/1/../bin/lava-test-case
10938 11:46:29.848397 <8>[ 17.565331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10939 11:46:29.849033 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10941 11:46:29.859330 /lava-12074023/1/../bin/lava-test-case
10942 11:46:29.866124 <8>[ 17.583739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10943 11:46:29.866652 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10945 11:46:29.876847 /lava-12074023/1/../bin/lava-test-case
10946 11:46:29.883254 <8>[ 17.600671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10947 11:46:29.883867 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10949 11:46:29.899940 /lava-12074023/1/../bin/lava-tes<8>[ 17.617045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10950 11:46:29.900330 t-case
10951 11:46:29.900884 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10953 11:46:29.911997 /lava-12074023/1/../bin/lava-test-case
10954 11:46:29.919146 <8>[ 17.636389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10955 11:46:29.919784 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10957 11:46:29.928450 /lava-12074023/1/../bin/lava-test-case
10958 11:46:29.934900 <8>[ 17.653830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10959 11:46:29.935558 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10961 11:46:29.950490 /lava-12074023/1/../bin/lava-tes<8>[ 17.670645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10962 11:46:29.951165 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10964 11:46:29.953387 t-case
10965 11:46:29.963592 /lava-12074023/1/../bin/lava-test-case
10966 11:46:29.970627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10968 11:46:29.973420 <8>[ 17.689679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10969 11:46:29.982102 /lava-12074023/1/../bin/lava-test-case
10970 11:46:29.993818 <8>[ 17.711253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10971 11:46:29.994686 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10973 11:46:30.001786 /lava-12074023/1/../bin/lava-test-case
10974 11:46:30.008422 <8>[ 17.726399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10975 11:46:30.009062 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10977 11:46:30.022516 /lava-12074023/1/../bin/lava-test-case
10978 11:46:30.029273 <8>[ 17.747013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10979 11:46:30.030050 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10981 11:46:30.039462 /lava-12074023/1/../bin/lava-test-case
10982 11:46:30.046080 <8>[ 17.765185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10983 11:46:30.046722 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10985 11:46:30.056130 /lava-12074023/1/../bin/lava-test-case
10986 11:46:30.062541 <8>[ 17.780335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10987 11:46:30.062907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10989 11:46:30.075881 /lava-12074023/1/../bin/lava-test-case
10990 11:46:30.085542 <8>[ 17.803713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10991 11:46:30.085818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10993 11:46:30.093662 /lava-12074023/1/../bin/lava-test-case
10994 11:46:30.100222 <8>[ 17.819436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10995 11:46:30.100501 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10997 11:46:30.112553 /lava-12074023/1/../bin/lava-test-case
10998 11:46:30.119052 <8>[ 17.837313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10999 11:46:30.119325 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11001 11:46:30.132854 /lava-12074023/1/../bin/lava-test-case
11002 11:46:30.139193 <8>[ 17.857965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11003 11:46:30.139465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11005 11:46:30.150684 /lava-12074023/1/../bin/lava-test-case
11006 11:46:30.157651 <8>[ 17.876739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11007 11:46:30.157956 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11009 11:46:30.177514 /lava-12074023/1/../bin/lava-tes<8>[ 17.895512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11010 11:46:30.177646 t-case
11011 11:46:30.177887 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11013 11:46:30.186450 /lava-12074023/1/../bin/lava-test-case
11014 11:46:30.193443 <8>[ 17.912024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11015 11:46:30.193750 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11017 11:46:30.205191 /lava-12074023/1/../bin/lava-test-case
11018 11:46:30.211592 <8>[ 17.930240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11019 11:46:30.211948 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11021 11:46:30.222500 /lava-12074023/1/../bin/lava-test-case
11022 11:46:30.232408 <8>[ 17.950014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11023 11:46:30.232722 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11025 11:46:30.240885 /lava-12074023/1/../bin/lava-test-case
11026 11:46:30.247775 <8>[ 17.966124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11027 11:46:30.248030 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11029 11:46:30.259631 /lava-12074023/1/../bin/lava-test-case
11030 11:46:30.266628 <8>[ 17.984728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11031 11:46:30.266915 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11033 11:46:30.274777 /lava-12074023/1/../bin/lava-test-case
11034 11:46:30.281656 <8>[ 18.000033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11035 11:46:30.281910 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11037 11:46:30.293197 /lava-12074023/1/../bin/lava-test-case
11038 11:46:30.299901 <8>[ 18.018353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11039 11:46:30.300169 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11041 11:46:30.309659 /lava-12074023/1/../bin/lava-test-case
11042 11:46:30.315944 <8>[ 18.034195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11043 11:46:30.316246 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11045 11:46:30.327613 /lava-12074023/1/../bin/lava-test-case
11046 11:46:30.334191 <8>[ 18.051895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11047 11:46:30.334607 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11049 11:46:30.344559 /lava-12074023/1/../bin/lava-test-case
11050 11:46:30.351218 <8>[ 18.069518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11051 11:46:30.351853 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11053 11:46:30.366341 /lava-12074023/1/../bin/lava-test-case
11054 11:46:30.373219 <8>[ 18.090490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11055 11:46:30.373898 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11057 11:46:30.389628 /lava-12074023/1/../bin/lava-tes<8>[ 18.106725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11058 11:46:30.390059 t-case
11059 11:46:30.390754 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11061 11:46:30.402282 /lava-12074023/1/../bin/lava-test-case
11062 11:46:30.412633 <8>[ 18.129840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11063 11:46:30.413310 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11065 11:46:30.419918 /lava-12074023/1/../bin/lava-test-case
11066 11:46:30.426979 <8>[ 18.145401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11067 11:46:30.427659 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11069 11:46:30.438525 /lava-12074023/1/../bin/lava-test-case
11070 11:46:30.445203 <8>[ 18.164117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11071 11:46:30.446065 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11073 11:46:30.453904 /lava-12074023/1/../bin/lava-test-case
11074 11:46:30.460680 <8>[ 18.178582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11075 11:46:30.461699 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11077 11:46:30.471669 /lava-12074023/1/../bin/lava-test-case
11078 11:46:30.478277 <8>[ 18.197494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11079 11:46:30.479021 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11081 11:46:30.489357 /lava-12074023/1/../bin/lava-test-case
11082 11:46:30.496023 <8>[ 18.214710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11083 11:46:30.496732 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11085 11:46:30.505135 /lava-12074023/1/../bin/lava-test-case
11086 11:46:30.515200 <8>[ 18.232009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11087 11:46:30.515889 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11089 11:46:30.525397 /lava-12074023/1/../bin/lava-test-case
11090 11:46:30.531799 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11092 11:46:30.534847 <8>[ 18.252226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11093 11:46:30.542817 /lava-12074023/1/../bin/lava-test-case
11094 11:46:30.549359 <8>[ 18.268395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11095 11:46:30.550177 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11097 11:46:30.561642 /lava-12074023/1/../bin/lava-test-case
11098 11:46:30.568138 <8>[ 18.286277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11099 11:46:30.568846 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11101 11:46:30.579208 /lava-12074023/1/../bin/lava-test-case
11102 11:46:30.585554 <8>[ 18.303021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11103 11:46:30.586258 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11105 11:46:30.597085 /lava-12074023/1/../bin/lava-test-case
11106 11:46:30.603686 <8>[ 18.322256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11107 11:46:30.604414 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11109 11:46:30.618914 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11111 11:46:30.622123 /lava-12074023/1/../bin/lava-tes<8>[ 18.339194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11112 11:46:30.622653 t-case
11113 11:46:30.638381 /lava-12074023/1/../bin/lava-tes<8>[ 18.355803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11114 11:46:30.638854 t-case
11115 11:46:30.639513 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11117 11:46:30.645909 /lava-12074023/1/../bin/lava-test-case
11118 11:46:30.652512 <8>[ 18.371511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11119 11:46:30.653244 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11121 11:46:30.663703 /lava-12074023/1/../bin/lava-test-case
11122 11:46:30.670023 <8>[ 18.388879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11123 11:46:30.670744 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11125 11:46:30.682262 /lava-12074023/1/../bin/lava-test-case
11126 11:46:30.688903 <8>[ 18.406072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11127 11:46:30.689610 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11129 11:46:30.697099 /lava-12074023/1/../bin/lava-test-case
11130 11:46:30.703889 <8>[ 18.421342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11131 11:46:30.704664 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11133 11:46:30.716748 /lava-12074023/1/../bin/lava-test-case
11134 11:46:30.723298 <8>[ 18.442570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11135 11:46:30.724005 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11137 11:46:30.732399 /lava-12074023/1/../bin/lava-test-case
11138 11:46:30.739385 <8>[ 18.457366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11139 11:46:30.740087 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11141 11:46:30.750556 /lava-12074023/1/../bin/lava-test-case
11142 11:46:30.757593 <8>[ 18.475389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11143 11:46:30.758561 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11145 11:46:30.765779 /lava-12074023/1/../bin/lava-test-case
11146 11:46:30.772414 <8>[ 18.491967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11147 11:46:30.773178 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11149 11:46:30.784251 /lava-12074023/1/../bin/lava-test-case
11150 11:46:30.796132 <8>[ 18.513984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11151 11:46:30.797002 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11153 11:46:30.805889 /lava-12074023/1/../bin/lava-test-case
11154 11:46:30.812550 <8>[ 18.530941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11155 11:46:30.813254 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11157 11:46:30.825517 /lava-12074023/1/../bin/lava-test-case
11158 11:46:30.831796 <8>[ 18.549345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11159 11:46:30.832638 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11161 11:46:30.844288 /lava-12074023/1/../bin/lava-test-case
11162 11:46:30.851167 <8>[ 18.570482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11163 11:46:30.852038 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11165 11:46:30.862285 /lava-12074023/1/../bin/lava-test-case
11166 11:46:30.868899 <8>[ 18.588566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11167 11:46:30.869624 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11169 11:46:30.882328 /lava-12074023/1/../bin/lava-test-case
11170 11:46:30.888538 <8>[ 18.606532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11171 11:46:30.889522 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11173 11:46:30.899257 /lava-12074023/1/../bin/lava-test-case
11174 11:46:30.906028 <8>[ 18.623435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11175 11:46:30.906923 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11177 11:46:30.917841 /lava-12074023/1/../bin/lava-test-case
11178 11:46:30.924363 <8>[ 18.642986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11179 11:46:30.925130 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11181 11:46:30.936207 /lava-12074023/1/../bin/lava-test-case
11182 11:46:30.942837 <8>[ 18.660892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11183 11:46:30.943551 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11185 11:46:30.961322 /lava-12074023/1/../bin/lava-tes<8>[ 18.678235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11186 11:46:30.961749 t-case
11187 11:46:30.962362 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11189 11:46:30.971289 /lava-12074023/1/../bin/lava-test-case
11190 11:46:30.977617 <8>[ 18.696071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11191 11:46:30.978380 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11193 11:46:30.988024 /lava-12074023/1/../bin/lava-test-case
11194 11:46:30.994203 <8>[ 18.712459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11195 11:46:30.994996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11197 11:46:31.006354 /lava-12074023/1/../bin/lava-test-case
11198 11:46:31.012936 <8>[ 18.733124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11199 11:46:31.013758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11201 11:46:31.024643 /lava-12074023/1/../bin/lava-test-case
11202 11:46:31.031735 <8>[ 18.750243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11203 11:46:31.032411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11205 11:46:31.042135 /lava-12074023/1/../bin/lava-test-case
11206 11:46:31.048387 <8>[ 18.766897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11207 11:46:31.049181 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11209 11:46:31.058899 /lava-12074023/1/../bin/lava-test-case
11210 11:46:31.065378 <8>[ 18.783953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11211 11:46:31.066356 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11213 11:46:31.076679 /lava-12074023/1/../bin/lava-test-case
11214 11:46:31.082503 <8>[ 18.801660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11215 11:46:31.083376 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11217 11:46:31.091648 /lava-12074023/1/../bin/lava-test-case
11218 11:46:31.097923 <8>[ 18.816777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11219 11:46:31.098637 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11221 11:46:31.108800 /lava-12074023/1/../bin/lava-test-case
11222 11:46:31.115823 <8>[ 18.833810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11223 11:46:31.116762 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11225 11:46:31.123534 /lava-12074023/1/../bin/lava-test-case
11226 11:46:31.130099 <8>[ 18.848966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11227 11:46:31.131094 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11229 11:46:31.142560 /lava-12074023/1/../bin/lava-test-case
11230 11:46:31.149209 <8>[ 18.866515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11231 11:46:31.150034 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11233 11:46:31.166047 /lava-12074023/1/../bin/lava-tes<8>[ 18.883473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11234 11:46:31.166472 t-case
11235 11:46:31.167056 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11237 11:46:31.179278 /lava-12074023/1/../bin/lava-test-case
11238 11:46:31.185923 <8>[ 18.904329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11239 11:46:31.186692 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11241 11:46:31.195772 /lava-12074023/1/../bin/lava-test-case
11242 11:46:31.202521 <8>[ 18.919613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11243 11:46:31.203325 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11245 11:46:31.217766 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11247 11:46:31.220568 /lava-12074023/1/../bin/lava-tes<8>[ 18.938209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11248 11:46:31.221092 t-case
11249 11:46:31.229121 /lava-12074023/1/../bin/lava-test-case
11250 11:46:31.235893 <8>[ 18.953553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11251 11:46:31.236573 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11253 11:46:31.249013 /lava-12074023/1/../bin/lava-test-case
11254 11:46:31.255223 <8>[ 18.972951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11255 11:46:31.256132 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11257 11:46:31.272537 /lava-12074023/1/../bin/lava-tes<8>[ 18.989914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11258 11:46:31.273135 t-case
11259 11:46:31.273990 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11261 11:46:31.282972 /lava-12074023/1/../bin/lava-test-case
11262 11:46:31.289274 <8>[ 19.008562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11263 11:46:31.290004 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11265 11:46:31.302589 /lava-12074023/1/../bin/lava-test-case
11266 11:46:31.308995 <8>[ 19.027307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11267 11:46:31.309796 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11269 11:46:31.316894 /lava-12074023/1/../bin/lava-test-case
11270 11:46:31.323812 <8>[ 19.042175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11271 11:46:31.324485 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11273 11:46:31.334947 /lava-12074023/1/../bin/lava-test-case
11274 11:46:31.341318 <8>[ 19.059820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11275 11:46:31.341756 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11277 11:46:31.349067 /lava-12074023/1/../bin/lava-test-case
11278 11:46:31.356211 <8>[ 19.074493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11279 11:46:31.356882 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11281 11:46:32.369700 /lava-12074023/1/../bin/lava-test-case
11282 11:46:32.376742 <8>[ 20.095705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11283 11:46:32.377035 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11285 11:46:32.385986 /lava-12074023/1/../bin/lava-test-case
11286 11:46:32.392402 <8>[ 20.111615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11287 11:46:32.392715 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11289 11:46:33.406548 /lava-12074023/1/../bin/lava-test-case
11290 11:46:33.413604 <8>[ 21.132099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11291 11:46:33.413886 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11293 11:46:33.425393 /lava-12074023/1/../bin/lava-test-case
11294 11:46:33.431455 <8>[ 21.149898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11295 11:46:33.431720 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11297 11:46:34.447133 /lava-12074023/1/../bin/lava-test-case
11298 11:46:34.453929 <8>[ 22.173384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11299 11:46:34.454209 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11301 11:46:34.470765 /lava-12074023/1/../bin/lava-tes<8>[ 22.188959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11302 11:46:34.470885 t-case
11303 11:46:34.471160 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11305 11:46:35.483317 /lava-12074023/1/../bin/lava-test-case
11306 11:46:35.489533 <8>[ 23.208684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11307 11:46:35.489831 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11309 11:46:35.501289 /lava-12074023/1/../bin/lava-test-case
11310 11:46:35.507755 <8>[ 23.226132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11311 11:46:35.508019 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11313 11:46:36.520110 /lava-12074023/1/../bin/lava-test-case
11314 11:46:36.530416 <8>[ 24.249659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11315 11:46:36.530698 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11317 11:46:36.539884 /lava-12074023/1/../bin/lava-test-case
11318 11:46:36.546257 <8>[ 24.265518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11319 11:46:36.546550 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11321 11:46:37.560291 /lava-12074023/1/../bin/lava-test-case
11322 11:46:37.567354 <8>[ 25.286155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11323 11:46:37.567647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11325 11:46:37.578047 /lava-12074023/1/../bin/lava-test-case
11326 11:46:37.584641 <8>[ 25.304660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11327 11:46:37.584900 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11329 11:46:38.600118 /lava-12074023/1/../bin/lava-test-case
11330 11:46:38.606732 <8>[ 26.326119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11331 11:46:38.607020 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11333 11:46:38.614921 /lava-12074023/1/../bin/lava-test-case
11334 11:46:38.625135 <8>[ 26.343478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11335 11:46:38.625400 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11337 11:46:38.634145 /lava-12074023/1/../bin/lava-test-case
11338 11:46:38.640951 <8>[ 26.360227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11339 11:46:38.641207 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11341 11:46:39.654791 /lava-12074023/1/../bin/lava-test-case
11342 11:46:39.661060 <8>[ 27.381126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11343 11:46:39.661336 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11345 11:46:39.680844 /lava-12074023/1/../bin/lava-tes<8>[ 27.399687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11346 11:46:39.680950 t-case
11347 11:46:39.681212 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11349 11:46:39.691045 /lava-12074023/1/../bin/lava-test-case
11350 11:46:39.697499 <8>[ 27.418619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11351 11:46:39.697762 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11353 11:46:39.709035 /lava-12074023/1/../bin/lava-test-case
11354 11:46:39.715977 <8>[ 27.435390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11355 11:46:39.716271 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11357 11:46:39.723396 /lava-12074023/1/../bin/lava-test-case
11358 11:46:39.736973 <8>[ 27.456509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11359 11:46:39.737272 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11361 11:46:39.747326 /lava-12074023/1/../bin/lava-test-case
11362 11:46:39.757405 <8>[ 27.476948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11363 11:46:39.757672 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11365 11:46:39.769018 /lava-12074023/1/../bin/lava-test-case
11366 11:46:39.775903 <8>[ 27.494958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11367 11:46:39.776168 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11369 11:46:39.784253 /lava-12074023/1/../bin/lava-test-case
11370 11:46:39.791131 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11372 11:46:39.794136 <8>[ 27.511686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11373 11:46:39.811447 /lava-12074023/1/../bin/lava-tes<8>[ 27.530386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11374 11:46:39.811569 t-case
11375 11:46:39.811835 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11377 11:46:39.828653 /lava-12074023/1/../bin/lava-tes<8>[ 27.547638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11378 11:46:39.828761 t-case
11379 11:46:39.829008 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11381 11:46:39.837645 /lava-12074023/1/../bin/lava-test-case
11382 11:46:39.847498 <8>[ 27.566303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11383 11:46:39.847790 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11385 11:46:39.858848 /lava-12074023/1/../bin/lava-test-case
11386 11:46:39.865293 <8>[ 27.585487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11387 11:46:39.865576 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11389 11:46:39.874487 /lava-12074023/1/../bin/lava-test-case
11390 11:46:39.881625 <8>[ 27.600921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11391 11:46:39.881905 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11393 11:46:39.893765 /lava-12074023/1/../bin/lava-test-case
11394 11:46:39.899849 <8>[ 27.620043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11395 11:46:39.900119 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11397 11:46:39.909614 /lava-12074023/1/../bin/lava-test-case
11398 11:46:39.916050 <8>[ 27.636076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11399 11:46:39.916332 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11401 11:46:39.928697 /lava-12074023/1/../bin/lava-test-case
11402 11:46:39.935368 <8>[ 27.654866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11403 11:46:39.935638 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11405 11:46:39.944294 /lava-12074023/1/../bin/lava-test-case
11406 11:46:39.950785 <8>[ 27.669756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11407 11:46:39.951100 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11409 11:46:39.965646 /lava-12074023/1/../bin/lava-test-case
11410 11:46:39.972212 <8>[ 27.691168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11411 11:46:39.972507 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11413 11:46:39.980783 /lava-12074023/1/../bin/lava-test-case
11414 11:46:39.987689 <8>[ 27.708394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11415 11:46:39.987945 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11417 11:46:40.000010 /lava-12074023/1/../bin/lava-test-case
11418 11:46:40.006328 <8>[ 27.726490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11419 11:46:40.006611 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11421 11:46:40.016207 /lava-12074023/1/../bin/lava-test-case
11422 11:46:40.025141 <8>[ 27.743563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11423 11:46:40.025413 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11425 11:46:41.038294 /lava-12074023/1/../bin/lava-test-case
11426 11:46:41.045149 <8>[ 28.764768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11427 11:46:41.045447 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11429 11:46:42.059492 /lava-12074023/1/../bin/lava-test-case
11430 11:46:42.065730 <8>[ 29.786312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11431 11:46:42.066007 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11433 11:46:42.075560 /lava-12074023/1/../bin/lava-test-case
11434 11:46:42.082076 <8>[ 29.801275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11435 11:46:42.082403 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11437 11:46:42.093234 /lava-12074023/1/../bin/lava-test-case
11438 11:46:42.100089 <8>[ 29.819222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11439 11:46:42.100342 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11441 11:46:42.111487 /lava-12074023/1/../bin/lava-test-case
11442 11:46:42.118505 <8>[ 29.837538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11443 11:46:42.118762 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11445 11:46:42.129325 /lava-12074023/1/../bin/lava-test-case
11446 11:46:42.135364 <8>[ 29.856876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11447 11:46:42.135638 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11449 11:46:42.147051 /lava-12074023/1/../bin/lava-test-case
11450 11:46:42.153429 <8>[ 29.872494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11451 11:46:42.153684 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11453 11:46:42.164527 /lava-12074023/1/../bin/lava-test-case
11454 11:46:42.171509 <8>[ 29.891850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11455 11:46:42.171763 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11457 11:46:42.180930 /lava-12074023/1/../bin/lava-test-case
11458 11:46:42.187724 <8>[ 29.907975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11459 11:46:42.188006 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11461 11:46:42.202637 /lava-12074023/1/../bin/lava-test-case
11462 11:46:42.209286 <8>[ 29.929087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11463 11:46:42.209551 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11465 11:46:42.217287 /lava-12074023/1/../bin/lava-test-case
11466 11:46:42.224114 <8>[ 29.943962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11467 11:46:42.224376 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11469 11:46:42.240038 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11471 11:46:42.242846 /lava-12074023/1/../bin/lava-tes<8>[ 29.962264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11472 11:46:42.242952 t-case
11473 11:46:42.250555 /lava-12074023/1/../bin/lava-test-case
11474 11:46:42.257034 <8>[ 29.977838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11475 11:46:42.257287 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11477 11:46:42.269424 /lava-12074023/1/../bin/lava-test-case
11478 11:46:42.275890 <8>[ 29.995813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11479 11:46:42.276147 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11481 11:46:42.284475 /lava-12074023/1/../bin/lava-test-case
11482 11:46:42.290554 <8>[ 30.009918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11483 11:46:42.290810 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11485 11:46:42.308687 /lava-12074023/1/../bin/lava-tes<8>[ 30.030753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11486 11:46:42.308951 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11488 11:46:42.312291 t-case
11489 11:46:42.321340 /lava-12074023/1/../bin/lava-test-case
11490 11:46:42.331481 <8>[ 30.050355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11491 11:46:42.331750 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11493 11:46:42.341944 /lava-12074023/1/../bin/lava-test-case
11494 11:46:42.348563 <8>[ 30.068790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11495 11:46:42.348820 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11497 11:46:42.356607 /lava-12074023/1/../bin/lava-test-case
11498 11:46:42.363664 <8>[ 30.084070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11499 11:46:42.363920 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11501 11:46:42.375953 /lava-12074023/1/../bin/lava-test-case
11502 11:46:42.382517 <8>[ 30.102499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11503 11:46:42.382781 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11505 11:46:42.390392 /lava-12074023/1/../bin/lava-test-case
11506 11:46:42.396993 <8>[ 30.117229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11507 11:46:42.397252 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11509 11:46:42.408345 /lava-12074023/1/../bin/lava-test-case
11510 11:46:42.415007 <8>[ 30.135517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11511 11:46:42.415263 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11513 11:46:43.427258 /lava-12074023/1/../bin/lava-test-case
11514 11:46:43.433810 <8>[ 31.153397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11515 11:46:43.434123 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11517 11:46:44.446331 /lava-12074023/1/../bin/lava-test-case
11518 11:46:44.452824 <8>[ 32.173196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11519 11:46:44.453108 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11520 11:46:44.453200 Bad test result: blocked
11521 11:46:44.471513 /lava-12074023/1/../bin/lava-tes<8>[ 32.191235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11522 11:46:44.471653 t-case
11523 11:46:44.471895 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11525 11:46:45.484252 /lava-12074023/1/../bin/lava-test-case
11526 11:46:45.491216 <8>[ 33.211319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11527 11:46:45.491519 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11529 11:46:45.501435 /lava-12074023/1/../bin/lava-test-case
11530 11:46:45.508217 <8>[ 33.228564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11531 11:46:45.508522 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11533 11:46:45.519877 /lava-12074023/1/../bin/lava-test-case
11534 11:46:45.526611 <8>[ 33.246576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11535 11:46:45.526918 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11537 11:46:45.534142 /lava-12074023/1/../bin/lava-test-case
11538 11:46:45.543870 <8>[ 33.263880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11539 11:46:45.544183 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11541 11:46:45.552911 /lava-12074023/1/../bin/lava-test-case
11542 11:46:45.559592 <8>[ 33.279277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11543 11:46:45.559878 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11545 11:46:45.571789 /lava-12074023/1/../bin/lava-test-case
11546 11:46:45.578360 <8>[ 33.298616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11547 11:46:45.578655 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11549 11:46:45.586819 /lava-12074023/1/../bin/lava-test-case
11550 11:46:45.593325 <8>[ 33.313351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11551 11:46:45.593635 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11553 11:46:46.609341 /lava-12074023/1/../bin/lava-test-case
11554 11:46:46.615543 <8>[ 34.336291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11555 11:46:46.615873 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11557 11:46:46.623739 /lava-12074023/1/../bin/lava-test-case
11558 11:46:46.633722 <8>[ 34.353378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11559 11:46:46.634043 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11561 11:46:47.646370 /lava-12074023/1/../bin/lava-test-case
11562 11:46:47.653183 <8>[ 35.373378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11563 11:46:47.653486 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11565 11:46:47.660623 /lava-12074023/1/../bin/lava-test-case
11566 11:46:47.670601 <8>[ 35.390101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11567 11:46:47.670908 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11569 11:46:48.683831 /lava-12074023/1/../bin/lava-test-case
11570 11:46:48.690751 <8>[ 36.411416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11571 11:46:48.691124 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11573 11:46:48.702361 /lava-12074023/1/../bin/lava-test-case
11574 11:46:48.711867 <8>[ 36.431816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11575 11:46:48.712178 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11577 11:46:49.724681 /lava-12074023/1/../bin/lava-test-case
11578 11:46:49.731464 <8>[ 37.451777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11579 11:46:49.731768 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11581 11:46:49.749461 /lava-12074023/1/../bin/lava-tes<8>[ 37.469544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11582 11:46:49.749628 t-case
11583 11:46:49.749882 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11585 11:46:49.760204 /lava-12074023/1/../bin/lava-test-case
11586 11:46:49.766433 <8>[ 37.486682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11587 11:46:49.766726 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11589 11:46:49.783433 /lava-12074023/1/../bin/lava-tes<8>[ 37.506706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11590 11:46:49.783759 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11592 11:46:49.786543 t-case
11593 11:46:49.793531 /lava-12074023/1/../bin/lava-test-case
11594 11:46:49.800286 <8>[ 37.522486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11595 11:46:49.800585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11597 11:46:49.813540 /lava-12074023/1/../bin/lava-test-case
11598 11:46:49.820514 <8>[ 37.540879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11599 11:46:49.820817 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11601 11:46:49.827861 /lava-12074023/1/../bin/lava-test-case
11602 11:46:49.834252 <8>[ 37.555611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11603 11:46:49.834609 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11605 11:46:49.845840 /lava-12074023/1/../bin/lava-test-case
11606 11:46:49.852382 <8>[ 37.573405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11607 11:46:49.852681 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11609 11:46:49.861057 /lava-12074023/1/../bin/lava-test-case
11610 11:46:49.867535 <8>[ 37.589070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11611 11:46:49.867840 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11613 11:46:49.880488 /lava-12074023/1/../bin/lava-test-case
11614 11:46:49.887125 <8>[ 37.608101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11615 11:46:49.887428 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11617 11:46:49.894627 + <8>[ 37.618281] <LAVA_SIGNAL_ENDRUN 1_bootrr 12074023_1.5.2.3.5>
11618 11:46:49.894893 Received signal: <ENDRUN> 1_bootrr 12074023_1.5.2.3.5
11619 11:46:49.895003 Ending use of test pattern.
11620 11:46:49.895067 Ending test lava.1_bootrr (12074023_1.5.2.3.5), duration 20.36
11622 11:46:49.897619 set +x
11623 11:46:49.897702 <LAVA_TEST_RUNNER EXIT>
11624 11:46:49.897936 ok: lava_test_shell seems to have completed
11625 11:46:49.898950 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11626 11:46:49.899119 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11627 11:46:49.899225 end: 4 lava-test-retry (duration 00:00:21) [common]
11628 11:46:49.899312 start: 5 finalize (timeout 00:07:41) [common]
11629 11:46:49.899400 start: 5.1 power-off (timeout 00:00:30) [common]
11630 11:46:49.899555 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11631 11:46:49.976574 >> Command sent successfully.
11632 11:46:49.979117 Returned 0 in 0 seconds
11633 11:46:50.079555 end: 5.1 power-off (duration 00:00:00) [common]
11635 11:46:50.079905 start: 5.2 read-feedback (timeout 00:07:41) [common]
11636 11:46:50.080183 Listened to connection for namespace 'common' for up to 1s
11637 11:46:51.081141 Finalising connection for namespace 'common'
11638 11:46:51.081320 Disconnecting from shell: Finalise
11639 11:46:51.081402 / #
11640 11:46:51.181746 end: 5.2 read-feedback (duration 00:00:01) [common]
11641 11:46:51.181925 end: 5 finalize (duration 00:00:01) [common]
11642 11:46:51.182042 Cleaning after the job
11643 11:46:51.182141 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/ramdisk
11644 11:46:51.185507 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/kernel
11645 11:46:51.193937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/dtb
11646 11:46:51.194123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074023/tftp-deploy-e2gwny5j/modules
11647 11:46:51.201564 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074023
11648 11:46:51.248709 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074023
11649 11:46:51.248887 Job finished correctly