Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 38
- Kernel Warnings: 27
- Boot result: FAIL
- Errors: 3
1 11:44:06.120783 lava-dispatcher, installed at version: 2023.10
2 11:44:06.120989 start: 0 validate
3 11:44:06.121115 Start time: 2023-11-24 11:44:06.121108+00:00 (UTC)
4 11:44:06.121230 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:44:06.121359 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:44:06.392237 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:44:06.393019 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:48.705203 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:48.706011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:48.974977 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:48.975697 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:44:49.503866 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:44:49.504652 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:45:06.030578 validate duration: 59.91
16 11:45:06.031827 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:45:06.032396 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:45:06.032932 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:45:06.033590 Not decompressing ramdisk as can be used compressed.
20 11:45:06.034073 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 11:45:06.034435 saving as /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/ramdisk/initrd.cpio.gz
22 11:45:06.034798 total size: 4665412 (4 MB)
23 11:45:06.304839 progress 0 % (0 MB)
24 11:45:06.306345 progress 5 % (0 MB)
25 11:45:06.307607 progress 10 % (0 MB)
26 11:45:06.308901 progress 15 % (0 MB)
27 11:45:06.310151 progress 20 % (0 MB)
28 11:45:06.311385 progress 25 % (1 MB)
29 11:45:06.312653 progress 30 % (1 MB)
30 11:45:06.313886 progress 35 % (1 MB)
31 11:45:06.315109 progress 40 % (1 MB)
32 11:45:06.316496 progress 45 % (2 MB)
33 11:45:06.317718 progress 50 % (2 MB)
34 11:45:06.318946 progress 55 % (2 MB)
35 11:45:06.320170 progress 60 % (2 MB)
36 11:45:06.321395 progress 65 % (2 MB)
37 11:45:06.322642 progress 70 % (3 MB)
38 11:45:06.323860 progress 75 % (3 MB)
39 11:45:06.325085 progress 80 % (3 MB)
40 11:45:06.326476 progress 85 % (3 MB)
41 11:45:06.327696 progress 90 % (4 MB)
42 11:45:06.328919 progress 95 % (4 MB)
43 11:45:06.330155 progress 100 % (4 MB)
44 11:45:06.330311 4 MB downloaded in 0.30 s (15.05 MB/s)
45 11:45:06.330464 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:45:06.330710 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:45:06.330819 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:45:06.330906 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:45:06.331048 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:45:06.331117 saving as /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/kernel/Image
52 11:45:06.331178 total size: 49107456 (46 MB)
53 11:45:06.331240 No compression specified
54 11:45:06.332343 progress 0 % (0 MB)
55 11:45:06.345001 progress 5 % (2 MB)
56 11:45:06.357841 progress 10 % (4 MB)
57 11:45:06.370611 progress 15 % (7 MB)
58 11:45:06.383398 progress 20 % (9 MB)
59 11:45:06.396027 progress 25 % (11 MB)
60 11:45:06.409058 progress 30 % (14 MB)
61 11:45:06.421673 progress 35 % (16 MB)
62 11:45:06.434353 progress 40 % (18 MB)
63 11:45:06.447159 progress 45 % (21 MB)
64 11:45:06.460003 progress 50 % (23 MB)
65 11:45:06.473059 progress 55 % (25 MB)
66 11:45:06.485838 progress 60 % (28 MB)
67 11:45:06.498574 progress 65 % (30 MB)
68 11:45:06.511265 progress 70 % (32 MB)
69 11:45:06.523863 progress 75 % (35 MB)
70 11:45:06.536555 progress 80 % (37 MB)
71 11:45:06.549256 progress 85 % (39 MB)
72 11:45:06.561976 progress 90 % (42 MB)
73 11:45:06.574423 progress 95 % (44 MB)
74 11:45:06.586719 progress 100 % (46 MB)
75 11:45:06.586942 46 MB downloaded in 0.26 s (183.11 MB/s)
76 11:45:06.587094 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:45:06.587327 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:45:06.587414 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:45:06.587503 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:45:06.587647 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:45:06.587717 saving as /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/dtb/mt8192-asurada-spherion-r0.dtb
83 11:45:06.587780 total size: 47278 (0 MB)
84 11:45:06.587842 No compression specified
85 11:45:06.853215 progress 69 % (0 MB)
86 11:45:06.853608 progress 100 % (0 MB)
87 11:45:06.853785 0 MB downloaded in 0.27 s (0.17 MB/s)
88 11:45:06.853963 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:45:06.854196 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:45:06.854282 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:45:06.854364 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:45:06.854496 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 11:45:06.854564 saving as /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/nfsrootfs/full.rootfs.tar
95 11:45:06.854625 total size: 125290964 (119 MB)
96 11:45:06.854687 Using unxz to decompress xz
97 11:45:07.123784 progress 0 % (0 MB)
98 11:45:07.450320 progress 5 % (6 MB)
99 11:45:07.784447 progress 10 % (11 MB)
100 11:45:08.112647 progress 15 % (17 MB)
101 11:45:08.298056 progress 20 % (23 MB)
102 11:45:08.471438 progress 25 % (29 MB)
103 11:45:08.820912 progress 30 % (35 MB)
104 11:45:09.173771 progress 35 % (41 MB)
105 11:45:09.557695 progress 40 % (47 MB)
106 11:45:09.933248 progress 45 % (53 MB)
107 11:45:10.316104 progress 50 % (59 MB)
108 11:45:10.667126 progress 55 % (65 MB)
109 11:45:11.039395 progress 60 % (71 MB)
110 11:45:11.384168 progress 65 % (77 MB)
111 11:45:11.757842 progress 70 % (83 MB)
112 11:45:12.139333 progress 75 % (89 MB)
113 11:45:12.561712 progress 80 % (95 MB)
114 11:45:12.982162 progress 85 % (101 MB)
115 11:45:13.225943 progress 90 % (107 MB)
116 11:45:13.567589 progress 95 % (113 MB)
117 11:45:13.943765 progress 100 % (119 MB)
118 11:45:13.949498 119 MB downloaded in 7.09 s (16.84 MB/s)
119 11:45:13.949829 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:45:13.950242 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:45:13.950366 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:45:13.950490 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:45:13.950685 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:45:13.950791 saving as /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/modules/modules.tar
126 11:45:13.950885 total size: 8624756 (8 MB)
127 11:45:13.950981 Using unxz to decompress xz
128 11:45:13.955705 progress 0 % (0 MB)
129 11:45:13.976955 progress 5 % (0 MB)
130 11:45:14.000886 progress 10 % (0 MB)
131 11:45:14.024898 progress 15 % (1 MB)
132 11:45:14.048517 progress 20 % (1 MB)
133 11:45:14.072886 progress 25 % (2 MB)
134 11:45:14.099180 progress 30 % (2 MB)
135 11:45:14.125766 progress 35 % (2 MB)
136 11:45:14.149610 progress 40 % (3 MB)
137 11:45:14.174197 progress 45 % (3 MB)
138 11:45:14.199831 progress 50 % (4 MB)
139 11:45:14.225198 progress 55 % (4 MB)
140 11:45:14.251467 progress 60 % (4 MB)
141 11:45:14.280516 progress 65 % (5 MB)
142 11:45:14.305944 progress 70 % (5 MB)
143 11:45:14.330702 progress 75 % (6 MB)
144 11:45:14.358904 progress 80 % (6 MB)
145 11:45:14.385273 progress 85 % (7 MB)
146 11:45:14.410514 progress 90 % (7 MB)
147 11:45:14.442556 progress 95 % (7 MB)
148 11:45:14.471213 progress 100 % (8 MB)
149 11:45:14.476204 8 MB downloaded in 0.53 s (15.66 MB/s)
150 11:45:14.476501 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:45:14.476815 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:45:14.476910 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:45:14.477006 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:45:16.675035 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a
156 11:45:16.675255 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:45:16.675364 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:45:16.675546 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2
159 11:45:16.675680 makedir: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin
160 11:45:16.675785 makedir: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/tests
161 11:45:16.675886 makedir: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/results
162 11:45:16.675996 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-add-keys
163 11:45:16.676152 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-add-sources
164 11:45:16.676285 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-background-process-start
165 11:45:16.676421 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-background-process-stop
166 11:45:16.676595 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-common-functions
167 11:45:16.676724 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-echo-ipv4
168 11:45:16.676852 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-install-packages
169 11:45:16.676980 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-installed-packages
170 11:45:16.677108 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-os-build
171 11:45:16.677236 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-probe-channel
172 11:45:16.677362 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-probe-ip
173 11:45:16.677488 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-target-ip
174 11:45:16.677614 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-target-mac
175 11:45:16.677740 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-target-storage
176 11:45:16.677869 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-case
177 11:45:16.677998 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-event
178 11:45:16.678123 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-feedback
179 11:45:16.678250 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-raise
180 11:45:16.678376 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-reference
181 11:45:16.678503 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-runner
182 11:45:16.678629 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-set
183 11:45:16.678754 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-test-shell
184 11:45:16.678884 Updating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-install-packages (oe)
185 11:45:16.679042 Updating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/bin/lava-installed-packages (oe)
186 11:45:16.679175 Creating /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/environment
187 11:45:16.679274 LAVA metadata
188 11:45:16.679346 - LAVA_JOB_ID=12074028
189 11:45:16.679411 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:45:16.679528 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 11:45:16.679597 skipped lava-vland-overlay
192 11:45:16.679674 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:45:16.679756 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 11:45:16.679818 skipped lava-multinode-overlay
195 11:45:16.679893 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:45:16.679972 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 11:45:16.680049 Loading test definitions
198 11:45:16.680143 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 11:45:16.680216 Using /lava-12074028 at stage 0
200 11:45:16.680567 uuid=12074028_1.6.2.3.1 testdef=None
201 11:45:16.680674 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:45:16.680760 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 11:45:16.681289 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:45:16.681516 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 11:45:16.682175 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:45:16.682409 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 11:45:16.683036 runner path: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/0/tests/0_dmesg test_uuid 12074028_1.6.2.3.1
210 11:45:16.683195 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:45:16.683423 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 11:45:16.683497 Using /lava-12074028 at stage 1
214 11:45:16.683811 uuid=12074028_1.6.2.3.5 testdef=None
215 11:45:16.683901 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 11:45:16.683988 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 11:45:16.684464 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 11:45:16.684730 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 11:45:16.685383 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 11:45:16.685616 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 11:45:16.686285 runner path: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/1/tests/1_bootrr test_uuid 12074028_1.6.2.3.5
224 11:45:16.686441 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 11:45:16.686650 Creating lava-test-runner.conf files
227 11:45:16.686715 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/0 for stage 0
228 11:45:16.686808 - 0_dmesg
229 11:45:16.686889 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074028/lava-overlay-b020zth2/lava-12074028/1 for stage 1
230 11:45:16.686981 - 1_bootrr
231 11:45:16.687114 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 11:45:16.687206 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 11:45:16.694627 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 11:45:16.694783 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 11:45:16.694874 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 11:45:16.694964 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 11:45:16.695053 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 11:45:16.816613 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 11:45:16.816997 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 11:45:16.817116 extracting modules file /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a
241 11:45:17.045721 extracting modules file /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074028/extract-overlay-ramdisk-bberhhst/ramdisk
242 11:45:17.280088 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 11:45:17.280284 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 11:45:17.280403 [common] Applying overlay to NFS
245 11:45:17.280483 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074028/compress-overlay-usdpc_o9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a
246 11:45:17.288978 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 11:45:17.289149 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 11:45:17.289248 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 11:45:17.289340 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 11:45:17.289425 Building ramdisk /var/lib/lava/dispatcher/tmp/12074028/extract-overlay-ramdisk-bberhhst/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074028/extract-overlay-ramdisk-bberhhst/ramdisk
251 11:45:17.625713 >> 119398 blocks
252 11:45:19.562628 rename /var/lib/lava/dispatcher/tmp/12074028/extract-overlay-ramdisk-bberhhst/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/ramdisk/ramdisk.cpio.gz
253 11:45:19.563092 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 11:45:19.563220 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 11:45:19.563332 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 11:45:19.563444 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/kernel/Image'
257 11:45:32.095756 Returned 0 in 12 seconds
258 11:45:32.196805 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/kernel/image.itb
259 11:45:32.578858 output: FIT description: Kernel Image image with one or more FDT blobs
260 11:45:32.579236 output: Created: Fri Nov 24 11:45:32 2023
261 11:45:32.579314 output: Image 0 (kernel-1)
262 11:45:32.579380 output: Description:
263 11:45:32.579442 output: Created: Fri Nov 24 11:45:32 2023
264 11:45:32.579502 output: Type: Kernel Image
265 11:45:32.579561 output: Compression: lzma compressed
266 11:45:32.579621 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
267 11:45:32.579681 output: Architecture: AArch64
268 11:45:32.579740 output: OS: Linux
269 11:45:32.579799 output: Load Address: 0x00000000
270 11:45:32.579856 output: Entry Point: 0x00000000
271 11:45:32.579916 output: Hash algo: crc32
272 11:45:32.579976 output: Hash value: 43cfb6ad
273 11:45:32.580031 output: Image 1 (fdt-1)
274 11:45:32.580083 output: Description: mt8192-asurada-spherion-r0
275 11:45:32.580137 output: Created: Fri Nov 24 11:45:32 2023
276 11:45:32.580190 output: Type: Flat Device Tree
277 11:45:32.580243 output: Compression: uncompressed
278 11:45:32.580295 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 11:45:32.580348 output: Architecture: AArch64
280 11:45:32.580401 output: Hash algo: crc32
281 11:45:32.580453 output: Hash value: cc4352de
282 11:45:32.580512 output: Image 2 (ramdisk-1)
283 11:45:32.580598 output: Description: unavailable
284 11:45:32.580651 output: Created: Fri Nov 24 11:45:32 2023
285 11:45:32.580703 output: Type: RAMDisk Image
286 11:45:32.580756 output: Compression: Unknown Compression
287 11:45:32.580809 output: Data Size: 17798204 Bytes = 17381.06 KiB = 16.97 MiB
288 11:45:32.580862 output: Architecture: AArch64
289 11:45:32.580914 output: OS: Linux
290 11:45:32.580967 output: Load Address: unavailable
291 11:45:32.581020 output: Entry Point: unavailable
292 11:45:32.581072 output: Hash algo: crc32
293 11:45:32.581125 output: Hash value: c31f62d1
294 11:45:32.581177 output: Default Configuration: 'conf-1'
295 11:45:32.581230 output: Configuration 0 (conf-1)
296 11:45:32.581283 output: Description: mt8192-asurada-spherion-r0
297 11:45:32.581336 output: Kernel: kernel-1
298 11:45:32.581389 output: Init Ramdisk: ramdisk-1
299 11:45:32.581441 output: FDT: fdt-1
300 11:45:32.581494 output: Loadables: kernel-1
301 11:45:32.581546 output:
302 11:45:32.581781 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 11:45:32.581880 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 11:45:32.581986 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 11:45:32.582079 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 11:45:32.582159 No LXC device requested
307 11:45:32.582237 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 11:45:32.582324 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 11:45:32.582401 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 11:45:32.582470 Checking files for TFTP limit of 4294967296 bytes.
311 11:45:32.582974 end: 1 tftp-deploy (duration 00:00:27) [common]
312 11:45:32.583076 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 11:45:32.583168 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 11:45:32.583295 substitutions:
315 11:45:32.583362 - {DTB}: 12074028/tftp-deploy-zv9inh5g/dtb/mt8192-asurada-spherion-r0.dtb
316 11:45:32.583428 - {INITRD}: 12074028/tftp-deploy-zv9inh5g/ramdisk/ramdisk.cpio.gz
317 11:45:32.583488 - {KERNEL}: 12074028/tftp-deploy-zv9inh5g/kernel/Image
318 11:45:32.583546 - {LAVA_MAC}: None
319 11:45:32.583603 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a
320 11:45:32.583659 - {NFS_SERVER_IP}: 192.168.201.1
321 11:45:32.583716 - {PRESEED_CONFIG}: None
322 11:45:32.583773 - {PRESEED_LOCAL}: None
323 11:45:32.583845 - {RAMDISK}: 12074028/tftp-deploy-zv9inh5g/ramdisk/ramdisk.cpio.gz
324 11:45:32.583943 - {ROOT_PART}: None
325 11:45:32.583999 - {ROOT}: None
326 11:45:32.584053 - {SERVER_IP}: 192.168.201.1
327 11:45:32.584108 - {TEE}: None
328 11:45:32.584162 Parsed boot commands:
329 11:45:32.584215 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 11:45:32.584403 Parsed boot commands: tftpboot 192.168.201.1 12074028/tftp-deploy-zv9inh5g/kernel/image.itb 12074028/tftp-deploy-zv9inh5g/kernel/cmdline
331 11:45:32.584523 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 11:45:32.584700 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 11:45:32.584832 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 11:45:32.584919 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 11:45:32.584991 Not connected, no need to disconnect.
336 11:45:32.585067 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 11:45:32.585187 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 11:45:32.585254 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
339 11:45:32.589227 Setting prompt string to ['lava-test: # ']
340 11:45:32.589617 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 11:45:32.589784 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 11:45:32.589941 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 11:45:32.590098 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 11:45:32.590463 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
345 11:45:37.739690 >> Command sent successfully.
346 11:45:37.751268 Returned 0 in 5 seconds
347 11:45:37.852688 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 11:45:37.854249 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 11:45:37.854788 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 11:45:37.855273 Setting prompt string to 'Starting depthcharge on Spherion...'
352 11:45:37.855701 Changing prompt to 'Starting depthcharge on Spherion...'
353 11:45:37.856105 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 11:45:37.857487 [Enter `^Ec?' for help]
355 11:45:38.021373
356 11:45:38.021971
357 11:45:38.022386 F0: 102B 0000
358 11:45:38.022768
359 11:45:38.023112 F3: 1001 0000 [0200]
360 11:45:38.023812
361 11:45:38.024995 F3: 1001 0000
362 11:45:38.025479
363 11:45:38.025862 F7: 102D 0000
364 11:45:38.026220
365 11:45:38.026565 F1: 0000 0000
366 11:45:38.028249
367 11:45:38.028788 V0: 0000 0000 [0001]
368 11:45:38.029180
369 11:45:38.029537 00: 0007 8000
370 11:45:38.031132
371 11:45:38.031615 01: 0000 0000
372 11:45:38.032010
373 11:45:38.032372 BP: 0C00 0209 [0000]
374 11:45:38.032896
375 11:45:38.034771 G0: 1182 0000
376 11:45:38.035291
377 11:45:38.035676 EC: 0000 0021 [4000]
378 11:45:38.036037
379 11:45:38.038335 S7: 0000 0000 [0000]
380 11:45:38.038807
381 11:45:38.039187 CC: 0000 0000 [0001]
382 11:45:38.039539
383 11:45:38.041628 T0: 0000 0040 [010F]
384 11:45:38.042109
385 11:45:38.042489 Jump to BL
386 11:45:38.042839
387 11:45:38.067876
388 11:45:38.068314
389 11:45:38.068694
390 11:45:38.075162 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 11:45:38.078836 ARM64: Exception handlers installed.
392 11:45:38.082297 ARM64: Testing exception
393 11:45:38.085449 ARM64: Done test exception
394 11:45:38.092458 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 11:45:38.102762 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 11:45:38.109383 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 11:45:38.119454 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 11:45:38.126524 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 11:45:38.132766 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 11:45:38.145039 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 11:45:38.151694 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 11:45:38.171186 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 11:45:38.174111 WDT: Last reset was cold boot
404 11:45:38.177483 SPI1(PAD0) initialized at 2873684 Hz
405 11:45:38.180725 SPI5(PAD0) initialized at 992727 Hz
406 11:45:38.184612 VBOOT: Loading verstage.
407 11:45:38.190591 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 11:45:38.194230 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 11:45:38.197764 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 11:45:38.200719 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:45:38.208389 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 11:45:38.214807 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 11:45:38.225660 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 11:45:38.226271
415 11:45:38.226846
416 11:45:38.235901 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 11:45:38.239376 ARM64: Exception handlers installed.
418 11:45:38.242731 ARM64: Testing exception
419 11:45:38.243324 ARM64: Done test exception
420 11:45:38.249308 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 11:45:38.253720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:45:38.266637 Probing TPM: . done!
423 11:45:38.267289 TPM ready after 0 ms
424 11:45:38.273685 Connected to device vid:did:rid of 1ae0:0028:00
425 11:45:38.280824 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
426 11:45:38.326849 Initialized TPM device CR50 revision 0
427 11:45:38.343281 tlcl_send_startup: Startup return code is 0
428 11:45:38.343817 TPM: setup succeeded
429 11:45:38.353842 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 11:45:38.363401 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 11:45:38.372445 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 11:45:38.381440 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 11:45:38.385192 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 11:45:38.388270 in-header: 03 07 00 00 08 00 00 00
435 11:45:38.391562 in-data: aa e4 47 04 13 02 00 00
436 11:45:38.394697 Chrome EC: UHEPI supported
437 11:45:38.401452 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 11:45:38.405044 in-header: 03 95 00 00 08 00 00 00
439 11:45:38.408551 in-data: 18 20 20 08 00 00 00 00
440 11:45:38.409105 Phase 1
441 11:45:38.413011 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 11:45:38.420095 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 11:45:38.423469 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 11:45:38.426966 Recovery requested (1009000e)
445 11:45:38.435931 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 11:45:38.441334 tlcl_extend: response is 0
447 11:45:38.450825 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 11:45:38.456283 tlcl_extend: response is 0
449 11:45:38.463169 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 11:45:38.483301 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 11:45:38.491247 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 11:45:38.491384
453 11:45:38.491455
454 11:45:38.501479 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 11:45:38.505076 ARM64: Exception handlers installed.
456 11:45:38.505166 ARM64: Testing exception
457 11:45:38.508387 ARM64: Done test exception
458 11:45:38.528803 pmic_efuse_setting: Set efuses in 11 msecs
459 11:45:38.531913 pmwrap_interface_init: Select PMIF_VLD_RDY
460 11:45:38.538512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 11:45:38.542409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 11:45:38.548403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 11:45:38.552379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 11:45:38.558900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 11:45:38.562111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 11:45:38.565372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 11:45:38.572366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 11:45:38.575302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 11:45:38.582105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 11:45:38.585356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 11:45:38.588777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 11:45:38.595194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 11:45:38.602255 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 11:45:38.605755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 11:45:38.612942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 11:45:38.616576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 11:45:38.623717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 11:45:38.631146 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 11:45:38.634994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 11:45:38.642417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 11:45:38.645697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 11:45:38.653055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 11:45:38.656801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 11:45:38.663936 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 11:45:38.667903 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 11:45:38.671356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 11:45:38.678651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 11:45:38.682400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 11:45:38.686047 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 11:45:38.693128 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 11:45:38.696864 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 11:45:38.704315 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 11:45:38.708446 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 11:45:38.711791 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 11:45:38.718996 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 11:45:38.722823 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 11:45:38.726395 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 11:45:38.733601 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 11:45:38.737272 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 11:45:38.740663 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 11:45:38.744611 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 11:45:38.751591 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 11:45:38.755833 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 11:45:38.758704 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 11:45:38.762678 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 11:45:38.766411 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 11:45:38.769654 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 11:45:38.777196 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 11:45:38.780879 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 11:45:38.784427 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 11:45:38.792629 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 11:45:38.798666 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 11:45:38.806133 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 11:45:38.813465 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 11:45:38.820577 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 11:45:38.824793 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 11:45:38.831463 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 11:45:38.834580 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 11:45:38.841644 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x19
520 11:45:38.849188 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 11:45:38.852993 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 11:45:38.856373 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 11:45:38.866240 [RTC]rtc_get_frequency_meter,154: input=15, output=764
524 11:45:38.875762 [RTC]rtc_get_frequency_meter,154: input=23, output=949
525 11:45:38.885527 [RTC]rtc_get_frequency_meter,154: input=19, output=856
526 11:45:38.894481 [RTC]rtc_get_frequency_meter,154: input=17, output=810
527 11:45:38.904566 [RTC]rtc_get_frequency_meter,154: input=16, output=786
528 11:45:38.914231 [RTC]rtc_get_frequency_meter,154: input=16, output=788
529 11:45:38.924142 [RTC]rtc_get_frequency_meter,154: input=17, output=810
530 11:45:38.927351 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 11:45:38.931137 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 11:45:38.938182 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 11:45:38.942290 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 11:45:38.946178 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 11:45:38.949311 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 11:45:38.952986 ADC[4]: Raw value=670800 ID=5
537 11:45:38.956627 ADC[3]: Raw value=212917 ID=1
538 11:45:38.956712 RAM Code: 0x51
539 11:45:38.960517 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 11:45:38.967766 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 11:45:38.975319 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
542 11:45:38.979196 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
543 11:45:38.982802 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 11:45:38.986060 in-header: 03 07 00 00 08 00 00 00
545 11:45:38.989903 in-data: aa e4 47 04 13 02 00 00
546 11:45:38.993380 Chrome EC: UHEPI supported
547 11:45:39.000770 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 11:45:39.004769 in-header: 03 95 00 00 08 00 00 00
549 11:45:39.004854 in-data: 18 20 20 08 00 00 00 00
550 11:45:39.008221 MRC: failed to locate region type 0.
551 11:45:39.015627 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 11:45:39.018938 DRAM-K: Running full calibration
553 11:45:39.026553 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
554 11:45:39.026648 header.status = 0x0
555 11:45:39.030398 header.version = 0x6 (expected: 0x6)
556 11:45:39.033647 header.size = 0xd00 (expected: 0xd00)
557 11:45:39.033732 header.flags = 0x0
558 11:45:39.040709 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 11:45:39.059091 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 11:45:39.066137 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 11:45:39.070052 dram_init: ddr_geometry: 0
562 11:45:39.070137 [EMI] MDL number = 0
563 11:45:39.073857 [EMI] Get MDL freq = 0
564 11:45:39.073944 dram_init: ddr_type: 0
565 11:45:39.077401 is_discrete_lpddr4: 1
566 11:45:39.081709 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 11:45:39.081793
568 11:45:39.081902
569 11:45:39.081965 [Bian_co] ETT version 0.0.0.1
570 11:45:39.089021 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
571 11:45:39.089106
572 11:45:39.092251 dramc_set_vcore_voltage set vcore to 650000
573 11:45:39.092335 Read voltage for 800, 4
574 11:45:39.095909 Vio18 = 0
575 11:45:39.095994 Vcore = 650000
576 11:45:39.096061 Vdram = 0
577 11:45:39.096124 Vddq = 0
578 11:45:39.099444 Vmddr = 0
579 11:45:39.099529 dram_init: config_dvfs: 1
580 11:45:39.106993 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 11:45:39.111072 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 11:45:39.114989 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 11:45:39.118064 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 11:45:39.121878 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 11:45:39.125252 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 11:45:39.128960 MEM_TYPE=3, freq_sel=18
587 11:45:39.132674 sv_algorithm_assistance_LP4_1600
588 11:45:39.136277 ============ PULL DRAM RESETB DOWN ============
589 11:45:39.139874 ========== PULL DRAM RESETB DOWN end =========
590 11:45:39.143987 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 11:45:39.147556 ===================================
592 11:45:39.151010 LPDDR4 DRAM CONFIGURATION
593 11:45:39.154726 ===================================
594 11:45:39.154811 EX_ROW_EN[0] = 0x0
595 11:45:39.158661 EX_ROW_EN[1] = 0x0
596 11:45:39.158745 LP4Y_EN = 0x0
597 11:45:39.161918 WORK_FSP = 0x0
598 11:45:39.162003 WL = 0x2
599 11:45:39.165854 RL = 0x2
600 11:45:39.165938 BL = 0x2
601 11:45:39.169852 RPST = 0x0
602 11:45:39.169937 RD_PRE = 0x0
603 11:45:39.170004 WR_PRE = 0x1
604 11:45:39.173767 WR_PST = 0x0
605 11:45:39.173851 DBI_WR = 0x0
606 11:45:39.176986 DBI_RD = 0x0
607 11:45:39.177079 OTF = 0x1
608 11:45:39.180352 ===================================
609 11:45:39.184053 ===================================
610 11:45:39.187940 ANA top config
611 11:45:39.188024 ===================================
612 11:45:39.191774 DLL_ASYNC_EN = 0
613 11:45:39.195521 ALL_SLAVE_EN = 1
614 11:45:39.195606 NEW_RANK_MODE = 1
615 11:45:39.199483 DLL_IDLE_MODE = 1
616 11:45:39.202820 LP45_APHY_COMB_EN = 1
617 11:45:39.206049 TX_ODT_DIS = 1
618 11:45:39.206134 NEW_8X_MODE = 1
619 11:45:39.209563 ===================================
620 11:45:39.212462 ===================================
621 11:45:39.215960 data_rate = 1600
622 11:45:39.219950 CKR = 1
623 11:45:39.222580 DQ_P2S_RATIO = 8
624 11:45:39.226168 ===================================
625 11:45:39.230137 CA_P2S_RATIO = 8
626 11:45:39.230222 DQ_CA_OPEN = 0
627 11:45:39.233666 DQ_SEMI_OPEN = 0
628 11:45:39.236735 CA_SEMI_OPEN = 0
629 11:45:39.240469 CA_FULL_RATE = 0
630 11:45:39.240592 DQ_CKDIV4_EN = 1
631 11:45:39.244418 CA_CKDIV4_EN = 1
632 11:45:39.247646 CA_PREDIV_EN = 0
633 11:45:39.251148 PH8_DLY = 0
634 11:45:39.254478 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 11:45:39.254563 DQ_AAMCK_DIV = 4
636 11:45:39.257806 CA_AAMCK_DIV = 4
637 11:45:39.261119 CA_ADMCK_DIV = 4
638 11:45:39.264370 DQ_TRACK_CA_EN = 0
639 11:45:39.267704 CA_PICK = 800
640 11:45:39.271945 CA_MCKIO = 800
641 11:45:39.272030 MCKIO_SEMI = 0
642 11:45:39.275134 PLL_FREQ = 3068
643 11:45:39.278748 DQ_UI_PI_RATIO = 32
644 11:45:39.281979 CA_UI_PI_RATIO = 0
645 11:45:39.285141 ===================================
646 11:45:39.289366 ===================================
647 11:45:39.289500 memory_type:LPDDR4
648 11:45:39.292643 GP_NUM : 10
649 11:45:39.296259 SRAM_EN : 1
650 11:45:39.296343 MD32_EN : 0
651 11:45:39.299940 ===================================
652 11:45:39.303525 [ANA_INIT] >>>>>>>>>>>>>>
653 11:45:39.303610 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 11:45:39.307463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 11:45:39.310806 ===================================
656 11:45:39.314241 data_rate = 1600,PCW = 0X7600
657 11:45:39.318114 ===================================
658 11:45:39.321827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 11:45:39.325823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 11:45:39.332246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 11:45:39.335447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 11:45:39.341822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 11:45:39.345111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 11:45:39.345196 [ANA_INIT] flow start
665 11:45:39.348426 [ANA_INIT] PLL >>>>>>>>
666 11:45:39.351869 [ANA_INIT] PLL <<<<<<<<
667 11:45:39.351954 [ANA_INIT] MIDPI >>>>>>>>
668 11:45:39.355322 [ANA_INIT] MIDPI <<<<<<<<
669 11:45:39.358545 [ANA_INIT] DLL >>>>>>>>
670 11:45:39.358630 [ANA_INIT] flow end
671 11:45:39.361883 ============ LP4 DIFF to SE enter ============
672 11:45:39.368581 ============ LP4 DIFF to SE exit ============
673 11:45:39.368666 [ANA_INIT] <<<<<<<<<<<<<
674 11:45:39.371984 [Flow] Enable top DCM control >>>>>
675 11:45:39.375295 [Flow] Enable top DCM control <<<<<
676 11:45:39.378563 Enable DLL master slave shuffle
677 11:45:39.385232 ==============================================================
678 11:45:39.385317 Gating Mode config
679 11:45:39.392157 ==============================================================
680 11:45:39.395249 Config description:
681 11:45:39.405160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 11:45:39.411949 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 11:45:39.415162 SELPH_MODE 0: By rank 1: By Phase
684 11:45:39.422098 ==============================================================
685 11:45:39.425239 GAT_TRACK_EN = 1
686 11:45:39.425323 RX_GATING_MODE = 2
687 11:45:39.428630 RX_GATING_TRACK_MODE = 2
688 11:45:39.431740 SELPH_MODE = 1
689 11:45:39.435214 PICG_EARLY_EN = 1
690 11:45:39.438433 VALID_LAT_VALUE = 1
691 11:45:39.445390 ==============================================================
692 11:45:39.448556 Enter into Gating configuration >>>>
693 11:45:39.452417 Exit from Gating configuration <<<<
694 11:45:39.455240 Enter into DVFS_PRE_config >>>>>
695 11:45:39.465479 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 11:45:39.468904 Exit from DVFS_PRE_config <<<<<
697 11:45:39.472292 Enter into PICG configuration >>>>
698 11:45:39.475674 Exit from PICG configuration <<<<
699 11:45:39.478880 [RX_INPUT] configuration >>>>>
700 11:45:39.478965 [RX_INPUT] configuration <<<<<
701 11:45:39.485316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 11:45:39.492279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 11:45:39.495613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 11:45:39.502003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 11:45:39.508901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 11:45:39.515366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 11:45:39.518891 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 11:45:39.522277 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 11:45:39.528485 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 11:45:39.531915 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 11:45:39.535387 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 11:45:39.541987 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 11:45:39.542072 ===================================
714 11:45:39.545620 LPDDR4 DRAM CONFIGURATION
715 11:45:39.548891 ===================================
716 11:45:39.551992 EX_ROW_EN[0] = 0x0
717 11:45:39.552076 EX_ROW_EN[1] = 0x0
718 11:45:39.555614 LP4Y_EN = 0x0
719 11:45:39.555698 WORK_FSP = 0x0
720 11:45:39.559028 WL = 0x2
721 11:45:39.559113 RL = 0x2
722 11:45:39.562147 BL = 0x2
723 11:45:39.562231 RPST = 0x0
724 11:45:39.566014 RD_PRE = 0x0
725 11:45:39.566098 WR_PRE = 0x1
726 11:45:39.569160 WR_PST = 0x0
727 11:45:39.569244 DBI_WR = 0x0
728 11:45:39.572343 DBI_RD = 0x0
729 11:45:39.572426 OTF = 0x1
730 11:45:39.575703 ===================================
731 11:45:39.582273 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 11:45:39.585471 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 11:45:39.588628 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 11:45:39.592120 ===================================
735 11:45:39.595392 LPDDR4 DRAM CONFIGURATION
736 11:45:39.598885 ===================================
737 11:45:39.602164 EX_ROW_EN[0] = 0x10
738 11:45:39.602248 EX_ROW_EN[1] = 0x0
739 11:45:39.605519 LP4Y_EN = 0x0
740 11:45:39.605625 WORK_FSP = 0x0
741 11:45:39.608635 WL = 0x2
742 11:45:39.608746 RL = 0x2
743 11:45:39.612460 BL = 0x2
744 11:45:39.612546 RPST = 0x0
745 11:45:39.615694 RD_PRE = 0x0
746 11:45:39.615766 WR_PRE = 0x1
747 11:45:39.618906 WR_PST = 0x0
748 11:45:39.618990 DBI_WR = 0x0
749 11:45:39.622394 DBI_RD = 0x0
750 11:45:39.622478 OTF = 0x1
751 11:45:39.625592 ===================================
752 11:45:39.631882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 11:45:39.636466 nWR fixed to 40
754 11:45:39.639957 [ModeRegInit_LP4] CH0 RK0
755 11:45:39.640041 [ModeRegInit_LP4] CH0 RK1
756 11:45:39.643216 [ModeRegInit_LP4] CH1 RK0
757 11:45:39.646936 [ModeRegInit_LP4] CH1 RK1
758 11:45:39.647024 match AC timing 12
759 11:45:39.653213 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
760 11:45:39.657104 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 11:45:39.659947 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 11:45:39.666707 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 11:45:39.669935 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 11:45:39.670019 [EMI DOE] emi_dcm 0
765 11:45:39.676418 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 11:45:39.676503 ==
767 11:45:39.679965 Dram Type= 6, Freq= 0, CH_0, rank 0
768 11:45:39.683523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
769 11:45:39.683609 ==
770 11:45:39.689831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 11:45:39.696393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 11:45:39.704094 [CA 0] Center 37 (7~68) winsize 62
773 11:45:39.707508 [CA 1] Center 37 (7~68) winsize 62
774 11:45:39.710666 [CA 2] Center 35 (5~66) winsize 62
775 11:45:39.714336 [CA 3] Center 35 (4~66) winsize 63
776 11:45:39.717497 [CA 4] Center 34 (4~65) winsize 62
777 11:45:39.720909 [CA 5] Center 33 (3~64) winsize 62
778 11:45:39.720989
779 11:45:39.724193 [CmdBusTrainingLP45] Vref(ca) range 1: 30
780 11:45:39.724296
781 11:45:39.727896 [CATrainingPosCal] consider 1 rank data
782 11:45:39.731177 u2DelayCellTimex100 = 270/100 ps
783 11:45:39.734221 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 11:45:39.737589 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 11:45:39.744283 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 11:45:39.747575 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 11:45:39.750813 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
788 11:45:39.754127 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 11:45:39.754214
790 11:45:39.757537 CA PerBit enable=1, Macro0, CA PI delay=33
791 11:45:39.757611
792 11:45:39.760732 [CBTSetCACLKResult] CA Dly = 33
793 11:45:39.760840 CS Dly: 5 (0~36)
794 11:45:39.760933 ==
795 11:45:39.764294 Dram Type= 6, Freq= 0, CH_0, rank 1
796 11:45:39.770840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
797 11:45:39.770926 ==
798 11:45:39.774113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 11:45:39.780726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 11:45:39.790141 [CA 0] Center 37 (6~68) winsize 63
801 11:45:39.793416 [CA 1] Center 37 (6~68) winsize 63
802 11:45:39.796548 [CA 2] Center 35 (4~66) winsize 63
803 11:45:39.800233 [CA 3] Center 34 (4~65) winsize 62
804 11:45:39.803425 [CA 4] Center 33 (3~64) winsize 62
805 11:45:39.806767 [CA 5] Center 33 (3~64) winsize 62
806 11:45:39.806851
807 11:45:39.809843 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 11:45:39.809927
809 11:45:39.813324 [CATrainingPosCal] consider 2 rank data
810 11:45:39.816397 u2DelayCellTimex100 = 270/100 ps
811 11:45:39.819906 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 11:45:39.826395 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 11:45:39.829768 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 11:45:39.833281 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 11:45:39.836582 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
816 11:45:39.839814 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 11:45:39.839898
818 11:45:39.843173 CA PerBit enable=1, Macro0, CA PI delay=33
819 11:45:39.843258
820 11:45:39.846347 [CBTSetCACLKResult] CA Dly = 33
821 11:45:39.846431 CS Dly: 6 (0~38)
822 11:45:39.849588
823 11:45:39.853022 ----->DramcWriteLeveling(PI) begin...
824 11:45:39.853110 ==
825 11:45:39.856481 Dram Type= 6, Freq= 0, CH_0, rank 0
826 11:45:39.859567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
827 11:45:39.859651 ==
828 11:45:39.862821 Write leveling (Byte 0): 29 => 29
829 11:45:39.866309 Write leveling (Byte 1): 29 => 29
830 11:45:39.870310 DramcWriteLeveling(PI) end<-----
831 11:45:39.870394
832 11:45:39.870461 ==
833 11:45:39.873763 Dram Type= 6, Freq= 0, CH_0, rank 0
834 11:45:39.877237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
835 11:45:39.877330 ==
836 11:45:39.880927 [Gating] SW mode calibration
837 11:45:39.887946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 11:45:39.891686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 11:45:39.895210 0 6 0 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
840 11:45:39.901895 0 6 4 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
841 11:45:39.905171 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:45:39.908974 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:45:39.912113 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:45:39.918768 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:45:39.921800 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:45:39.925098 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:45:39.931846 0 7 0 | B1->B0 | 2525 2d2c | 1 1 | (0 0) (1 1)
848 11:45:39.935400 0 7 4 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
849 11:45:39.938607 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:45:39.945095 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 11:45:39.948301 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 11:45:39.951609 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 11:45:39.958550 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 11:45:39.961852 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 11:45:39.965366 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
856 11:45:39.972124 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
857 11:45:39.975694 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 11:45:39.978722 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 11:45:39.985334 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 11:45:39.988709 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 11:45:39.991970 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 11:45:39.998613 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 11:45:40.002392 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 11:45:40.005246 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 11:45:40.008413 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 11:45:40.015379 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 11:45:40.018365 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 11:45:40.021893 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 11:45:40.028272 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 11:45:40.032024 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 11:45:40.035408 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
872 11:45:40.041596 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 11:45:40.045230 Total UI for P1: 0, mck2ui 16
874 11:45:40.048167 best dqsien dly found for B0: ( 0, 10, 0)
875 11:45:40.051629 Total UI for P1: 0, mck2ui 16
876 11:45:40.055158 best dqsien dly found for B1: ( 0, 10, 2)
877 11:45:40.058209 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
878 11:45:40.061604 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
879 11:45:40.061688
880 11:45:40.064969 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
881 11:45:40.068657 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
882 11:45:40.071891 [Gating] SW calibration Done
883 11:45:40.072003 ==
884 11:45:40.075022 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:45:40.078284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:45:40.078369 ==
887 11:45:40.081826 RX Vref Scan: 0
888 11:45:40.081911
889 11:45:40.081979 RX Vref 0 -> 0, step: 1
890 11:45:40.082063
891 11:45:40.085271 RX Delay -130 -> 252, step: 16
892 11:45:40.091791 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
893 11:45:40.095068 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
894 11:45:40.098112 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
895 11:45:40.101681 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
896 11:45:40.105289 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
897 11:45:40.108274 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
898 11:45:40.115204 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
899 11:45:40.118113 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
900 11:45:40.122037 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
901 11:45:40.125038 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
902 11:45:40.128076 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
903 11:45:40.135316 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
904 11:45:40.138546 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
905 11:45:40.141735 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
906 11:45:40.145067 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
907 11:45:40.148543 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
908 11:45:40.151764 ==
909 11:45:40.154918 Dram Type= 6, Freq= 0, CH_0, rank 0
910 11:45:40.158425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
911 11:45:40.158499 ==
912 11:45:40.158568 DQS Delay:
913 11:45:40.161483 DQS0 = 0, DQS1 = 0
914 11:45:40.161557 DQM Delay:
915 11:45:40.165094 DQM0 = 84, DQM1 = 75
916 11:45:40.165172 DQ Delay:
917 11:45:40.168461 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
918 11:45:40.171727 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
919 11:45:40.174936 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
920 11:45:40.178551 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
921 11:45:40.178624
922 11:45:40.178686
923 11:45:40.178745 ==
924 11:45:40.181907 Dram Type= 6, Freq= 0, CH_0, rank 0
925 11:45:40.185090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
926 11:45:40.185165 ==
927 11:45:40.185241
928 11:45:40.185301
929 11:45:40.188403 TX Vref Scan disable
930 11:45:40.191800 == TX Byte 0 ==
931 11:45:40.195172 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
932 11:45:40.198490 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
933 11:45:40.202052 == TX Byte 1 ==
934 11:45:40.205133 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
935 11:45:40.208657 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
936 11:45:40.208730 ==
937 11:45:40.212017 Dram Type= 6, Freq= 0, CH_0, rank 0
938 11:45:40.215074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 11:45:40.215148 ==
940 11:45:40.229188 TX Vref=22, minBit 2, minWin=27, winSum=442
941 11:45:40.232363 TX Vref=24, minBit 2, minWin=27, winSum=447
942 11:45:40.235957 TX Vref=26, minBit 0, minWin=27, winSum=449
943 11:45:40.239083 TX Vref=28, minBit 4, minWin=27, winSum=457
944 11:45:40.242520 TX Vref=30, minBit 0, minWin=28, winSum=456
945 11:45:40.245663 TX Vref=32, minBit 1, minWin=27, winSum=454
946 11:45:40.252840 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
947 11:45:40.252917
948 11:45:40.255872 Final TX Range 1 Vref 30
949 11:45:40.255954
950 11:45:40.256020 ==
951 11:45:40.259538 Dram Type= 6, Freq= 0, CH_0, rank 0
952 11:45:40.262414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 11:45:40.262487 ==
954 11:45:40.262549
955 11:45:40.262609
956 11:45:40.266568 TX Vref Scan disable
957 11:45:40.270322 == TX Byte 0 ==
958 11:45:40.273149 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 11:45:40.276793 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 11:45:40.280303 == TX Byte 1 ==
961 11:45:40.283288 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
962 11:45:40.286761 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
963 11:45:40.286837
964 11:45:40.286900 [DATLAT]
965 11:45:40.290437 Freq=800, CH0 RK0
966 11:45:40.290532
967 11:45:40.293636 DATLAT Default: 0xa
968 11:45:40.293710 0, 0xFFFF, sum = 0
969 11:45:40.296668 1, 0xFFFF, sum = 0
970 11:45:40.296746 2, 0xFFFF, sum = 0
971 11:45:40.300159 3, 0xFFFF, sum = 0
972 11:45:40.300265 4, 0xFFFF, sum = 0
973 11:45:40.303664 5, 0xFFFF, sum = 0
974 11:45:40.303768 6, 0xFFFF, sum = 0
975 11:45:40.306727 7, 0xFFFF, sum = 0
976 11:45:40.306835 8, 0x0, sum = 1
977 11:45:40.310421 9, 0x0, sum = 2
978 11:45:40.310524 10, 0x0, sum = 3
979 11:45:40.310628 11, 0x0, sum = 4
980 11:45:40.313424 best_step = 9
981 11:45:40.313499
982 11:45:40.313562 ==
983 11:45:40.317228 Dram Type= 6, Freq= 0, CH_0, rank 0
984 11:45:40.320172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
985 11:45:40.320246 ==
986 11:45:40.323632 RX Vref Scan: 1
987 11:45:40.323704
988 11:45:40.327073 Set Vref Range= 32 -> 127
989 11:45:40.327158
990 11:45:40.327225 RX Vref 32 -> 127, step: 1
991 11:45:40.327287
992 11:45:40.330014 RX Delay -111 -> 252, step: 8
993 11:45:40.330099
994 11:45:40.333305 Set Vref, RX VrefLevel [Byte0]: 32
995 11:45:40.336916 [Byte1]: 32
996 11:45:40.337000
997 11:45:40.340195 Set Vref, RX VrefLevel [Byte0]: 33
998 11:45:40.343384 [Byte1]: 33
999 11:45:40.347592
1000 11:45:40.347678 Set Vref, RX VrefLevel [Byte0]: 34
1001 11:45:40.351130 [Byte1]: 34
1002 11:45:40.355327
1003 11:45:40.355412 Set Vref, RX VrefLevel [Byte0]: 35
1004 11:45:40.358701 [Byte1]: 35
1005 11:45:40.362995
1006 11:45:40.363114 Set Vref, RX VrefLevel [Byte0]: 36
1007 11:45:40.366118 [Byte1]: 36
1008 11:45:40.370686
1009 11:45:40.370770 Set Vref, RX VrefLevel [Byte0]: 37
1010 11:45:40.374019 [Byte1]: 37
1011 11:45:40.378128
1012 11:45:40.378241 Set Vref, RX VrefLevel [Byte0]: 38
1013 11:45:40.381505 [Byte1]: 38
1014 11:45:40.386259
1015 11:45:40.386347 Set Vref, RX VrefLevel [Byte0]: 39
1016 11:45:40.389302 [Byte1]: 39
1017 11:45:40.393403
1018 11:45:40.393486 Set Vref, RX VrefLevel [Byte0]: 40
1019 11:45:40.397004 [Byte1]: 40
1020 11:45:40.401100
1021 11:45:40.401184 Set Vref, RX VrefLevel [Byte0]: 41
1022 11:45:40.404347 [Byte1]: 41
1023 11:45:40.408751
1024 11:45:40.408835 Set Vref, RX VrefLevel [Byte0]: 42
1025 11:45:40.412044 [Byte1]: 42
1026 11:45:40.416472
1027 11:45:40.416602 Set Vref, RX VrefLevel [Byte0]: 43
1028 11:45:40.419802 [Byte1]: 43
1029 11:45:40.424359
1030 11:45:40.424442 Set Vref, RX VrefLevel [Byte0]: 44
1031 11:45:40.427248 [Byte1]: 44
1032 11:45:40.431734
1033 11:45:40.431816 Set Vref, RX VrefLevel [Byte0]: 45
1034 11:45:40.434835 [Byte1]: 45
1035 11:45:40.439422
1036 11:45:40.439525 Set Vref, RX VrefLevel [Byte0]: 46
1037 11:45:40.442629 [Byte1]: 46
1038 11:45:40.447338
1039 11:45:40.447422 Set Vref, RX VrefLevel [Byte0]: 47
1040 11:45:40.450425 [Byte1]: 47
1041 11:45:40.454663
1042 11:45:40.454757 Set Vref, RX VrefLevel [Byte0]: 48
1043 11:45:40.458330 [Byte1]: 48
1044 11:45:40.462223
1045 11:45:40.462328 Set Vref, RX VrefLevel [Byte0]: 49
1046 11:45:40.465596 [Byte1]: 49
1047 11:45:40.469922
1048 11:45:40.470005 Set Vref, RX VrefLevel [Byte0]: 50
1049 11:45:40.473297 [Byte1]: 50
1050 11:45:40.477779
1051 11:45:40.477861 Set Vref, RX VrefLevel [Byte0]: 51
1052 11:45:40.480772 [Byte1]: 51
1053 11:45:40.485296
1054 11:45:40.485379 Set Vref, RX VrefLevel [Byte0]: 52
1055 11:45:40.488462 [Byte1]: 52
1056 11:45:40.493058
1057 11:45:40.493141 Set Vref, RX VrefLevel [Byte0]: 53
1058 11:45:40.496110 [Byte1]: 53
1059 11:45:40.500746
1060 11:45:40.500828 Set Vref, RX VrefLevel [Byte0]: 54
1061 11:45:40.504226 [Byte1]: 54
1062 11:45:40.507965
1063 11:45:40.508048 Set Vref, RX VrefLevel [Byte0]: 55
1064 11:45:40.511796 [Byte1]: 55
1065 11:45:40.515777
1066 11:45:40.515859 Set Vref, RX VrefLevel [Byte0]: 56
1067 11:45:40.519497 [Byte1]: 56
1068 11:45:40.523364
1069 11:45:40.523447 Set Vref, RX VrefLevel [Byte0]: 57
1070 11:45:40.526600 [Byte1]: 57
1071 11:45:40.531023
1072 11:45:40.531129 Set Vref, RX VrefLevel [Byte0]: 58
1073 11:45:40.534426 [Byte1]: 58
1074 11:45:40.539266
1075 11:45:40.539395 Set Vref, RX VrefLevel [Byte0]: 59
1076 11:45:40.542494 [Byte1]: 59
1077 11:45:40.546890
1078 11:45:40.547010 Set Vref, RX VrefLevel [Byte0]: 60
1079 11:45:40.550380 [Byte1]: 60
1080 11:45:40.554289
1081 11:45:40.554361 Set Vref, RX VrefLevel [Byte0]: 61
1082 11:45:40.557573 [Byte1]: 61
1083 11:45:40.562287
1084 11:45:40.562369 Set Vref, RX VrefLevel [Byte0]: 62
1085 11:45:40.564929 [Byte1]: 62
1086 11:45:40.569773
1087 11:45:40.569845 Set Vref, RX VrefLevel [Byte0]: 63
1088 11:45:40.572933 [Byte1]: 63
1089 11:45:40.577116
1090 11:45:40.577188 Set Vref, RX VrefLevel [Byte0]: 64
1091 11:45:40.580138 [Byte1]: 64
1092 11:45:40.584527
1093 11:45:40.584625 Set Vref, RX VrefLevel [Byte0]: 65
1094 11:45:40.587858 [Byte1]: 65
1095 11:45:40.592214
1096 11:45:40.592297 Set Vref, RX VrefLevel [Byte0]: 66
1097 11:45:40.595630 [Byte1]: 66
1098 11:45:40.600168
1099 11:45:40.600250 Set Vref, RX VrefLevel [Byte0]: 67
1100 11:45:40.603247 [Byte1]: 67
1101 11:45:40.607661
1102 11:45:40.607744 Set Vref, RX VrefLevel [Byte0]: 68
1103 11:45:40.611119 [Byte1]: 68
1104 11:45:40.615535
1105 11:45:40.615618 Set Vref, RX VrefLevel [Byte0]: 69
1106 11:45:40.618559 [Byte1]: 69
1107 11:45:40.622822
1108 11:45:40.622904 Set Vref, RX VrefLevel [Byte0]: 70
1109 11:45:40.626535 [Byte1]: 70
1110 11:45:40.630736
1111 11:45:40.630843 Set Vref, RX VrefLevel [Byte0]: 71
1112 11:45:40.633999 [Byte1]: 71
1113 11:45:40.638111
1114 11:45:40.638194 Set Vref, RX VrefLevel [Byte0]: 72
1115 11:45:40.641522 [Byte1]: 72
1116 11:45:40.645814
1117 11:45:40.645903 Set Vref, RX VrefLevel [Byte0]: 73
1118 11:45:40.649095 [Byte1]: 73
1119 11:45:40.653703
1120 11:45:40.653791 Set Vref, RX VrefLevel [Byte0]: 74
1121 11:45:40.656668 [Byte1]: 74
1122 11:45:40.660920
1123 11:45:40.661006 Set Vref, RX VrefLevel [Byte0]: 75
1124 11:45:40.664429 [Byte1]: 75
1125 11:45:40.668764
1126 11:45:40.668845 Final RX Vref Byte 0 = 52 to rank0
1127 11:45:40.672195 Final RX Vref Byte 1 = 55 to rank0
1128 11:45:40.675352 Final RX Vref Byte 0 = 52 to rank1
1129 11:45:40.678712 Final RX Vref Byte 1 = 55 to rank1==
1130 11:45:40.681929 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 11:45:40.688586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1132 11:45:40.688690 ==
1133 11:45:40.688872 DQS Delay:
1134 11:45:40.688977 DQS0 = 0, DQS1 = 0
1135 11:45:40.692327 DQM Delay:
1136 11:45:40.692398 DQM0 = 83, DQM1 = 73
1137 11:45:40.695445 DQ Delay:
1138 11:45:40.698746 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1139 11:45:40.698853 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1140 11:45:40.702102 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1141 11:45:40.705590 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1142 11:45:40.709073
1143 11:45:40.709146
1144 11:45:40.715308 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1145 11:45:40.718901 CH0 RK0: MR19=606, MR18=3939
1146 11:45:40.725349 CH0_RK0: MR19=0x606, MR18=0x3939, DQSOSC=395, MR23=63, INC=94, DEC=63
1147 11:45:40.725451
1148 11:45:40.728695 ----->DramcWriteLeveling(PI) begin...
1149 11:45:40.728770 ==
1150 11:45:40.731908 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 11:45:40.735520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 11:45:40.735595 ==
1153 11:45:40.738636 Write leveling (Byte 0): 31 => 31
1154 11:45:40.742125 Write leveling (Byte 1): 28 => 28
1155 11:45:40.745341 DramcWriteLeveling(PI) end<-----
1156 11:45:40.745445
1157 11:45:40.745545 ==
1158 11:45:40.748742 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 11:45:40.752096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 11:45:40.752202 ==
1161 11:45:40.755515 [Gating] SW mode calibration
1162 11:45:40.761946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 11:45:40.768711 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 11:45:40.771808 0 6 0 | B1->B0 | 3131 3131 | 0 1 | (0 0) (1 0)
1165 11:45:40.775316 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1166 11:45:40.781689 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:45:40.785292 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:45:40.788728 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:45:40.795304 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:45:40.798409 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:45:40.802098 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:45:40.808706 0 7 0 | B1->B0 | 2929 2e2e | 1 0 | (0 0) (1 1)
1173 11:45:40.812219 0 7 4 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
1174 11:45:40.815302 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1175 11:45:40.821908 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1176 11:45:40.825019 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1177 11:45:40.828418 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1178 11:45:40.835169 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1179 11:45:40.838448 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 11:45:40.841857 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 11:45:40.848733 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1182 11:45:40.851630 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1183 11:45:40.855163 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1184 11:45:40.858279 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1185 11:45:40.865266 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1186 11:45:40.868295 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 11:45:40.871592 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 11:45:40.878477 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 11:45:40.881611 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 11:45:40.885109 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 11:45:40.891961 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 11:45:40.894877 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 11:45:40.898340 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:45:40.904824 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:45:40.908243 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:45:40.911835 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1197 11:45:40.918629 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:45:40.918713 Total UI for P1: 0, mck2ui 16
1199 11:45:40.925312 best dqsien dly found for B0: ( 0, 10, 0)
1200 11:45:40.925421 Total UI for P1: 0, mck2ui 16
1201 11:45:40.931690 best dqsien dly found for B1: ( 0, 10, 0)
1202 11:45:40.935475 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1203 11:45:40.938578 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1204 11:45:40.938683
1205 11:45:40.941622 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1206 11:45:40.945100 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1207 11:45:40.989076 [Gating] SW calibration Done
1208 11:45:40.989161 ==
1209 11:45:40.989229 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 11:45:40.989476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1211 11:45:40.989548 ==
1212 11:45:40.989609 RX Vref Scan: 0
1213 11:45:40.989674
1214 11:45:40.989954 RX Vref 0 -> 0, step: 1
1215 11:45:40.990020
1216 11:45:40.990080 RX Delay -130 -> 252, step: 16
1217 11:45:40.990456 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1218 11:45:40.990714 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1219 11:45:40.990811 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1220 11:45:40.991330 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1221 11:45:40.991618 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1222 11:45:40.991716 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1223 11:45:40.991807 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1224 11:45:40.994784 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1225 11:45:40.997948 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1226 11:45:41.001679 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1227 11:45:41.004696 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1228 11:45:41.011175 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1229 11:45:41.014649 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1230 11:45:41.017865 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1231 11:45:41.021243 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1232 11:45:41.028140 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1233 11:45:41.028245 ==
1234 11:45:41.031299 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 11:45:41.034590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1236 11:45:41.034692 ==
1237 11:45:41.034790 DQS Delay:
1238 11:45:41.038188 DQS0 = 0, DQS1 = 0
1239 11:45:41.038289 DQM Delay:
1240 11:45:41.041662 DQM0 = 88, DQM1 = 75
1241 11:45:41.041739 DQ Delay:
1242 11:45:41.045080 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1243 11:45:41.047932 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
1244 11:45:41.051527 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1245 11:45:41.054666 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1246 11:45:41.054764
1247 11:45:41.054859
1248 11:45:41.054947 ==
1249 11:45:41.058003 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 11:45:41.061448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 11:45:41.061549 ==
1252 11:45:41.061645
1253 11:45:41.061734
1254 11:45:41.065009 TX Vref Scan disable
1255 11:45:41.067898 == TX Byte 0 ==
1256 11:45:41.071159 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1257 11:45:41.074294 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1258 11:45:41.077879 == TX Byte 1 ==
1259 11:45:41.081029 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1260 11:45:41.084619 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1261 11:45:41.084695 ==
1262 11:45:41.087766 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 11:45:41.094515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1264 11:45:41.094626 ==
1265 11:45:41.106212 TX Vref=22, minBit 9, minWin=27, winSum=448
1266 11:45:41.109735 TX Vref=24, minBit 7, minWin=27, winSum=450
1267 11:45:41.113160 TX Vref=26, minBit 1, minWin=28, winSum=454
1268 11:45:41.116759 TX Vref=28, minBit 2, minWin=28, winSum=454
1269 11:45:41.120739 TX Vref=30, minBit 2, minWin=28, winSum=456
1270 11:45:41.124229 TX Vref=32, minBit 0, minWin=28, winSum=454
1271 11:45:41.131428 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1272 11:45:41.131568
1273 11:45:41.131663 Final TX Range 1 Vref 30
1274 11:45:41.134528
1275 11:45:41.134604 ==
1276 11:45:41.138256 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 11:45:41.141277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1278 11:45:41.141355 ==
1279 11:45:41.141420
1280 11:45:41.141496
1281 11:45:41.145323 TX Vref Scan disable
1282 11:45:41.145399 == TX Byte 0 ==
1283 11:45:41.151545 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1284 11:45:41.155223 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1285 11:45:41.155306 == TX Byte 1 ==
1286 11:45:41.161728 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1287 11:45:41.164757 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1288 11:45:41.164840
1289 11:45:41.164906 [DATLAT]
1290 11:45:41.168322 Freq=800, CH0 RK1
1291 11:45:41.168404
1292 11:45:41.168470 DATLAT Default: 0x9
1293 11:45:41.171823 0, 0xFFFF, sum = 0
1294 11:45:41.171907 1, 0xFFFF, sum = 0
1295 11:45:41.174884 2, 0xFFFF, sum = 0
1296 11:45:41.174969 3, 0xFFFF, sum = 0
1297 11:45:41.178089 4, 0xFFFF, sum = 0
1298 11:45:41.178173 5, 0xFFFF, sum = 0
1299 11:45:41.181773 6, 0xFFFF, sum = 0
1300 11:45:41.181857 7, 0xFFFF, sum = 0
1301 11:45:41.185074 8, 0x0, sum = 1
1302 11:45:41.185158 9, 0x0, sum = 2
1303 11:45:41.188271 10, 0x0, sum = 3
1304 11:45:41.188355 11, 0x0, sum = 4
1305 11:45:41.191507 best_step = 9
1306 11:45:41.191589
1307 11:45:41.191655 ==
1308 11:45:41.194843 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 11:45:41.198280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1310 11:45:41.198363 ==
1311 11:45:41.198430 RX Vref Scan: 0
1312 11:45:41.202100
1313 11:45:41.202183 RX Vref 0 -> 0, step: 1
1314 11:45:41.202249
1315 11:45:41.204866 RX Delay -111 -> 252, step: 8
1316 11:45:41.211861 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1317 11:45:41.214923 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1318 11:45:41.218841 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1319 11:45:41.221887 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1320 11:45:41.225012 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1321 11:45:41.228335 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1322 11:45:41.235142 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1323 11:45:41.238367 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1324 11:45:41.241483 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1325 11:45:41.245173 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1326 11:45:41.248027 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1327 11:45:41.254557 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1328 11:45:41.258139 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1329 11:45:41.261302 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1330 11:45:41.264501 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1331 11:45:41.271319 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1332 11:45:41.271402 ==
1333 11:45:41.274879 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 11:45:41.277931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1335 11:45:41.278014 ==
1336 11:45:41.278081 DQS Delay:
1337 11:45:41.281725 DQS0 = 0, DQS1 = 0
1338 11:45:41.281808 DQM Delay:
1339 11:45:41.284766 DQM0 = 86, DQM1 = 74
1340 11:45:41.284849 DQ Delay:
1341 11:45:41.288022 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1342 11:45:41.291261 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1343 11:45:41.294560 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1344 11:45:41.297891 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1345 11:45:41.297974
1346 11:45:41.298040
1347 11:45:41.304801 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1348 11:45:41.307991 CH0 RK1: MR19=606, MR18=4444
1349 11:45:41.314780 CH0_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1350 11:45:41.317869 [RxdqsGatingPostProcess] freq 800
1351 11:45:41.324502 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1352 11:45:41.327783 Pre-setting of DQS Precalculation
1353 11:45:41.331556 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1354 11:45:41.331639 ==
1355 11:45:41.334632 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 11:45:41.338286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 11:45:41.338368 ==
1358 11:45:41.344722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1359 11:45:41.351086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1360 11:45:41.359367 [CA 0] Center 37 (6~68) winsize 63
1361 11:45:41.362434 [CA 1] Center 37 (6~68) winsize 63
1362 11:45:41.365875 [CA 2] Center 34 (4~65) winsize 62
1363 11:45:41.369044 [CA 3] Center 34 (4~65) winsize 62
1364 11:45:41.372287 [CA 4] Center 33 (3~64) winsize 62
1365 11:45:41.375635 [CA 5] Center 33 (3~64) winsize 62
1366 11:45:41.375767
1367 11:45:41.379012 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1368 11:45:41.379090
1369 11:45:41.382308 [CATrainingPosCal] consider 1 rank data
1370 11:45:41.385544 u2DelayCellTimex100 = 270/100 ps
1371 11:45:41.388994 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1372 11:45:41.392405 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1373 11:45:41.399378 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1374 11:45:41.402206 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1375 11:45:41.405893 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1376 11:45:41.408967 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1377 11:45:41.409041
1378 11:45:41.412659 CA PerBit enable=1, Macro0, CA PI delay=33
1379 11:45:41.412759
1380 11:45:41.416137 [CBTSetCACLKResult] CA Dly = 33
1381 11:45:41.416210 CS Dly: 5 (0~36)
1382 11:45:41.416276 ==
1383 11:45:41.419107 Dram Type= 6, Freq= 0, CH_1, rank 1
1384 11:45:41.425577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1385 11:45:41.425652 ==
1386 11:45:41.429116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1387 11:45:41.435959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1388 11:45:41.444987 [CA 0] Center 36 (6~67) winsize 62
1389 11:45:41.447998 [CA 1] Center 37 (6~68) winsize 63
1390 11:45:41.451476 [CA 2] Center 34 (4~65) winsize 62
1391 11:45:41.454758 [CA 3] Center 34 (4~65) winsize 62
1392 11:45:41.458205 [CA 4] Center 33 (3~64) winsize 62
1393 11:45:41.461532 [CA 5] Center 33 (3~64) winsize 62
1394 11:45:41.461642
1395 11:45:41.464717 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1396 11:45:41.464801
1397 11:45:41.468057 [CATrainingPosCal] consider 2 rank data
1398 11:45:41.471472 u2DelayCellTimex100 = 270/100 ps
1399 11:45:41.475095 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1400 11:45:41.478374 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1401 11:45:41.485115 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 11:45:41.488244 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1403 11:45:41.491629 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 11:45:41.494953 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1405 11:45:41.495037
1406 11:45:41.498374 CA PerBit enable=1, Macro0, CA PI delay=33
1407 11:45:41.498457
1408 11:45:41.501970 [CBTSetCACLKResult] CA Dly = 33
1409 11:45:41.502054 CS Dly: 5 (0~36)
1410 11:45:41.502121
1411 11:45:41.504884 ----->DramcWriteLeveling(PI) begin...
1412 11:45:41.504969 ==
1413 11:45:41.508226 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 11:45:41.514953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 11:45:41.515037 ==
1416 11:45:41.518553 Write leveling (Byte 0): 26 => 26
1417 11:45:41.522017 Write leveling (Byte 1): 23 => 23
1418 11:45:41.522101 DramcWriteLeveling(PI) end<-----
1419 11:45:41.522167
1420 11:45:41.525060 ==
1421 11:45:41.528437 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 11:45:41.531711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1423 11:45:41.531795 ==
1424 11:45:41.535079 [Gating] SW mode calibration
1425 11:45:41.541600 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1426 11:45:41.544988 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1427 11:45:41.551870 0 6 0 | B1->B0 | 2f2f 2525 | 1 0 | (0 0) (0 0)
1428 11:45:41.554975 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1429 11:45:41.558305 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1430 11:45:41.565045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1431 11:45:41.568621 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1432 11:45:41.571896 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1433 11:45:41.578691 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1434 11:45:41.581813 0 6 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1435 11:45:41.585177 0 7 0 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
1436 11:45:41.591901 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1437 11:45:41.595107 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1438 11:45:41.598795 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1439 11:45:41.601771 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1440 11:45:41.608753 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1441 11:45:41.611847 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1442 11:45:41.615611 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 11:45:41.621891 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1444 11:45:41.625042 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1445 11:45:41.628609 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1446 11:45:41.634986 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1447 11:45:41.638449 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1448 11:45:41.641566 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1449 11:45:41.648443 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 11:45:41.651928 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 11:45:41.655151 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 11:45:41.661962 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 11:45:41.664933 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 11:45:41.668258 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 11:45:41.674868 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 11:45:41.678172 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 11:45:41.681611 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 11:45:41.688175 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1459 11:45:41.691549 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1460 11:45:41.694867 Total UI for P1: 0, mck2ui 16
1461 11:45:41.698240 best dqsien dly found for B0: ( 0, 9, 28)
1462 11:45:41.702052 Total UI for P1: 0, mck2ui 16
1463 11:45:41.705008 best dqsien dly found for B1: ( 0, 9, 28)
1464 11:45:41.708853 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1465 11:45:41.711686 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1466 11:45:41.711793
1467 11:45:41.715042 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1468 11:45:41.718610 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1469 11:45:41.721552 [Gating] SW calibration Done
1470 11:45:41.721630 ==
1471 11:45:41.724776 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 11:45:41.728605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1473 11:45:41.728711 ==
1474 11:45:41.731435 RX Vref Scan: 0
1475 11:45:41.731546
1476 11:45:41.734890 RX Vref 0 -> 0, step: 1
1477 11:45:41.734992
1478 11:45:41.735087 RX Delay -130 -> 252, step: 16
1479 11:45:41.741460 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1480 11:45:41.745452 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1481 11:45:41.748328 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1482 11:45:41.751420 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1483 11:45:41.754880 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1484 11:45:41.761237 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1485 11:45:41.764612 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1486 11:45:41.768241 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1487 11:45:41.771267 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1488 11:45:41.774909 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1489 11:45:41.781821 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1490 11:45:41.785554 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1491 11:45:41.788857 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1492 11:45:41.792904 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1493 11:45:41.796733 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1494 11:45:41.799975 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1495 11:45:41.800049 ==
1496 11:45:41.803547 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 11:45:41.807439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1498 11:45:41.807515 ==
1499 11:45:41.810938 DQS Delay:
1500 11:45:41.811040 DQS0 = 0, DQS1 = 0
1501 11:45:41.811133 DQM Delay:
1502 11:45:41.814400 DQM0 = 80, DQM1 = 72
1503 11:45:41.814475 DQ Delay:
1504 11:45:41.817589 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1505 11:45:41.821394 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1506 11:45:41.824337 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1507 11:45:41.827775 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1508 11:45:41.827877
1509 11:45:41.827970
1510 11:45:41.828058 ==
1511 11:45:41.831085 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 11:45:41.834535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1513 11:45:41.837993 ==
1514 11:45:41.838070
1515 11:45:41.838134
1516 11:45:41.838193 TX Vref Scan disable
1517 11:45:41.841297 == TX Byte 0 ==
1518 11:45:41.844386 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1519 11:45:41.847767 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1520 11:45:41.851349 == TX Byte 1 ==
1521 11:45:41.854408 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1522 11:45:41.858047 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1523 11:45:41.861351 ==
1524 11:45:41.861422 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 11:45:41.867796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1526 11:45:41.867869 ==
1527 11:45:41.879970 TX Vref=22, minBit 2, minWin=27, winSum=446
1528 11:45:41.883799 TX Vref=24, minBit 3, minWin=27, winSum=448
1529 11:45:41.887003 TX Vref=26, minBit 0, minWin=28, winSum=455
1530 11:45:41.890169 TX Vref=28, minBit 0, minWin=28, winSum=458
1531 11:45:41.893721 TX Vref=30, minBit 0, minWin=28, winSum=456
1532 11:45:41.896999 TX Vref=32, minBit 0, minWin=28, winSum=456
1533 11:45:41.903385 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1534 11:45:41.903469
1535 11:45:41.906782 Final TX Range 1 Vref 28
1536 11:45:41.906866
1537 11:45:41.906932 ==
1538 11:45:41.910226 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 11:45:41.913295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1540 11:45:41.913380 ==
1541 11:45:41.913446
1542 11:45:41.916667
1543 11:45:41.916749 TX Vref Scan disable
1544 11:45:41.920202 == TX Byte 0 ==
1545 11:45:41.923492 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1546 11:45:41.926691 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1547 11:45:41.930062 == TX Byte 1 ==
1548 11:45:41.933522 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1549 11:45:41.936989 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1550 11:45:41.940331
1551 11:45:41.940473 [DATLAT]
1552 11:45:41.940576 Freq=800, CH1 RK0
1553 11:45:41.940639
1554 11:45:41.943490 DATLAT Default: 0xa
1555 11:45:41.943573 0, 0xFFFF, sum = 0
1556 11:45:41.947284 1, 0xFFFF, sum = 0
1557 11:45:41.947368 2, 0xFFFF, sum = 0
1558 11:45:41.950325 3, 0xFFFF, sum = 0
1559 11:45:41.950410 4, 0xFFFF, sum = 0
1560 11:45:41.953448 5, 0xFFFF, sum = 0
1561 11:45:41.956677 6, 0xFFFF, sum = 0
1562 11:45:41.956762 7, 0xFFFF, sum = 0
1563 11:45:41.956830 8, 0x0, sum = 1
1564 11:45:41.960355 9, 0x0, sum = 2
1565 11:45:41.960440 10, 0x0, sum = 3
1566 11:45:41.963391 11, 0x0, sum = 4
1567 11:45:41.963476 best_step = 9
1568 11:45:41.963542
1569 11:45:41.963604 ==
1570 11:45:41.967077 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 11:45:41.973872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1572 11:45:41.973955 ==
1573 11:45:41.974022 RX Vref Scan: 1
1574 11:45:41.974083
1575 11:45:41.977124 Set Vref Range= 32 -> 127
1576 11:45:41.977207
1577 11:45:41.980229 RX Vref 32 -> 127, step: 1
1578 11:45:41.980312
1579 11:45:41.980378 RX Delay -111 -> 252, step: 8
1580 11:45:41.983722
1581 11:45:41.983804 Set Vref, RX VrefLevel [Byte0]: 32
1582 11:45:41.986647 [Byte1]: 32
1583 11:45:41.991121
1584 11:45:41.991204 Set Vref, RX VrefLevel [Byte0]: 33
1585 11:45:41.994745 [Byte1]: 33
1586 11:45:41.998847
1587 11:45:41.998930 Set Vref, RX VrefLevel [Byte0]: 34
1588 11:45:42.001932 [Byte1]: 34
1589 11:45:42.006266
1590 11:45:42.006349 Set Vref, RX VrefLevel [Byte0]: 35
1591 11:45:42.009947 [Byte1]: 35
1592 11:45:42.013864
1593 11:45:42.013947 Set Vref, RX VrefLevel [Byte0]: 36
1594 11:45:42.017401 [Byte1]: 36
1595 11:45:42.021527
1596 11:45:42.021610 Set Vref, RX VrefLevel [Byte0]: 37
1597 11:45:42.024974 [Byte1]: 37
1598 11:45:42.029570
1599 11:45:42.029653 Set Vref, RX VrefLevel [Byte0]: 38
1600 11:45:42.032465 [Byte1]: 38
1601 11:45:42.036740
1602 11:45:42.036823 Set Vref, RX VrefLevel [Byte0]: 39
1603 11:45:42.040359 [Byte1]: 39
1604 11:45:42.044490
1605 11:45:42.044597 Set Vref, RX VrefLevel [Byte0]: 40
1606 11:45:42.047645 [Byte1]: 40
1607 11:45:42.052386
1608 11:45:42.052479 Set Vref, RX VrefLevel [Byte0]: 41
1609 11:45:42.055537 [Byte1]: 41
1610 11:45:42.059924
1611 11:45:42.060006 Set Vref, RX VrefLevel [Byte0]: 42
1612 11:45:42.063649 [Byte1]: 42
1613 11:45:42.067692
1614 11:45:42.067775 Set Vref, RX VrefLevel [Byte0]: 43
1615 11:45:42.070989 [Byte1]: 43
1616 11:45:42.075392
1617 11:45:42.075474 Set Vref, RX VrefLevel [Byte0]: 44
1618 11:45:42.078703 [Byte1]: 44
1619 11:45:42.082905
1620 11:45:42.082988 Set Vref, RX VrefLevel [Byte0]: 45
1621 11:45:42.085895 [Byte1]: 45
1622 11:45:42.090275
1623 11:45:42.090358 Set Vref, RX VrefLevel [Byte0]: 46
1624 11:45:42.094190 [Byte1]: 46
1625 11:45:42.098200
1626 11:45:42.098283 Set Vref, RX VrefLevel [Byte0]: 47
1627 11:45:42.101317 [Byte1]: 47
1628 11:45:42.105646
1629 11:45:42.105729 Set Vref, RX VrefLevel [Byte0]: 48
1630 11:45:42.109215 [Byte1]: 48
1631 11:45:42.113528
1632 11:45:42.113612 Set Vref, RX VrefLevel [Byte0]: 49
1633 11:45:42.116886 [Byte1]: 49
1634 11:45:42.121054
1635 11:45:42.121136 Set Vref, RX VrefLevel [Byte0]: 50
1636 11:45:42.124274 [Byte1]: 50
1637 11:45:42.128512
1638 11:45:42.128610 Set Vref, RX VrefLevel [Byte0]: 51
1639 11:45:42.132057 [Byte1]: 51
1640 11:45:42.136552
1641 11:45:42.136636 Set Vref, RX VrefLevel [Byte0]: 52
1642 11:45:42.139565 [Byte1]: 52
1643 11:45:42.144233
1644 11:45:42.144316 Set Vref, RX VrefLevel [Byte0]: 53
1645 11:45:42.147478 [Byte1]: 53
1646 11:45:42.151849
1647 11:45:42.151932 Set Vref, RX VrefLevel [Byte0]: 54
1648 11:45:42.154694 [Byte1]: 54
1649 11:45:42.159485
1650 11:45:42.159568 Set Vref, RX VrefLevel [Byte0]: 55
1651 11:45:42.162598 [Byte1]: 55
1652 11:45:42.167006
1653 11:45:42.167088 Set Vref, RX VrefLevel [Byte0]: 56
1654 11:45:42.170097 [Byte1]: 56
1655 11:45:42.174458
1656 11:45:42.174541 Set Vref, RX VrefLevel [Byte0]: 57
1657 11:45:42.177754 [Byte1]: 57
1658 11:45:42.182054
1659 11:45:42.182137 Set Vref, RX VrefLevel [Byte0]: 58
1660 11:45:42.185501 [Byte1]: 58
1661 11:45:42.189704
1662 11:45:42.189788 Set Vref, RX VrefLevel [Byte0]: 59
1663 11:45:42.193064 [Byte1]: 59
1664 11:45:42.197514
1665 11:45:42.197597 Set Vref, RX VrefLevel [Byte0]: 60
1666 11:45:42.200740 [Byte1]: 60
1667 11:45:42.205158
1668 11:45:42.205240 Set Vref, RX VrefLevel [Byte0]: 61
1669 11:45:42.208478 [Byte1]: 61
1670 11:45:42.212836
1671 11:45:42.212918 Set Vref, RX VrefLevel [Byte0]: 62
1672 11:45:42.216250 [Byte1]: 62
1673 11:45:42.220305
1674 11:45:42.220388 Set Vref, RX VrefLevel [Byte0]: 63
1675 11:45:42.223893 [Byte1]: 63
1676 11:45:42.228326
1677 11:45:42.228408 Set Vref, RX VrefLevel [Byte0]: 64
1678 11:45:42.231169 [Byte1]: 64
1679 11:45:42.235575
1680 11:45:42.235658 Set Vref, RX VrefLevel [Byte0]: 65
1681 11:45:42.239116 [Byte1]: 65
1682 11:45:42.243383
1683 11:45:42.243466 Set Vref, RX VrefLevel [Byte0]: 66
1684 11:45:42.246649 [Byte1]: 66
1685 11:45:42.251120
1686 11:45:42.251202 Set Vref, RX VrefLevel [Byte0]: 67
1687 11:45:42.254491 [Byte1]: 67
1688 11:45:42.258812
1689 11:45:42.258896 Set Vref, RX VrefLevel [Byte0]: 68
1690 11:45:42.262260 [Byte1]: 68
1691 11:45:42.266338
1692 11:45:42.266422 Set Vref, RX VrefLevel [Byte0]: 69
1693 11:45:42.270074 [Byte1]: 69
1694 11:45:42.273789
1695 11:45:42.273873 Set Vref, RX VrefLevel [Byte0]: 70
1696 11:45:42.277410 [Byte1]: 70
1697 11:45:42.281767
1698 11:45:42.281850 Set Vref, RX VrefLevel [Byte0]: 71
1699 11:45:42.285063 [Byte1]: 71
1700 11:45:42.289323
1701 11:45:42.289406 Set Vref, RX VrefLevel [Byte0]: 72
1702 11:45:42.292586 [Byte1]: 72
1703 11:45:42.296974
1704 11:45:42.297057 Set Vref, RX VrefLevel [Byte0]: 73
1705 11:45:42.300059 [Byte1]: 73
1706 11:45:42.304547
1707 11:45:42.304644 Set Vref, RX VrefLevel [Byte0]: 74
1708 11:45:42.308033 [Byte1]: 74
1709 11:45:42.312269
1710 11:45:42.312352 Set Vref, RX VrefLevel [Byte0]: 75
1711 11:45:42.315579 [Byte1]: 75
1712 11:45:42.319916
1713 11:45:42.319999 Set Vref, RX VrefLevel [Byte0]: 76
1714 11:45:42.323208 [Byte1]: 76
1715 11:45:42.327538
1716 11:45:42.327621 Set Vref, RX VrefLevel [Byte0]: 77
1717 11:45:42.331303 [Byte1]: 77
1718 11:45:42.335231
1719 11:45:42.335314 Final RX Vref Byte 0 = 60 to rank0
1720 11:45:42.338425 Final RX Vref Byte 1 = 60 to rank0
1721 11:45:42.341773 Final RX Vref Byte 0 = 60 to rank1
1722 11:45:42.345154 Final RX Vref Byte 1 = 60 to rank1==
1723 11:45:42.348831 Dram Type= 6, Freq= 0, CH_1, rank 0
1724 11:45:42.355084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1725 11:45:42.355196 ==
1726 11:45:42.355305 DQS Delay:
1727 11:45:42.355399 DQS0 = 0, DQS1 = 0
1728 11:45:42.358787 DQM Delay:
1729 11:45:42.358891 DQM0 = 81, DQM1 = 74
1730 11:45:42.362889 DQ Delay:
1731 11:45:42.362996 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1732 11:45:42.366446 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1733 11:45:42.369172 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1734 11:45:42.372164 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1735 11:45:42.372245
1736 11:45:42.372310
1737 11:45:42.382349 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1738 11:45:42.385594 CH1 RK0: MR19=606, MR18=5252
1739 11:45:42.389037 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1740 11:45:42.392195
1741 11:45:42.395675 ----->DramcWriteLeveling(PI) begin...
1742 11:45:42.395756 ==
1743 11:45:42.398887 Dram Type= 6, Freq= 0, CH_1, rank 1
1744 11:45:42.402699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1745 11:45:42.402775 ==
1746 11:45:42.405835 Write leveling (Byte 0): 25 => 25
1747 11:45:42.409302 Write leveling (Byte 1): 24 => 24
1748 11:45:42.412236 DramcWriteLeveling(PI) end<-----
1749 11:45:42.412316
1750 11:45:42.412380 ==
1751 11:45:42.415824 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 11:45:42.418859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 11:45:42.418937 ==
1754 11:45:42.422338 [Gating] SW mode calibration
1755 11:45:42.429195 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1756 11:45:42.435680 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1757 11:45:42.439144 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
1758 11:45:42.442420 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 11:45:42.445704 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 11:45:42.452307 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 11:45:42.455590 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 11:45:42.459067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 11:45:42.465831 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 11:45:42.469327 0 6 28 | B1->B0 | 2525 3030 | 0 1 | (0 0) (0 0)
1765 11:45:42.472491 0 7 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1766 11:45:42.479106 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 11:45:42.482477 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 11:45:42.485930 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 11:45:42.492385 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 11:45:42.495926 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 11:45:42.498840 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 11:45:42.505781 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1773 11:45:42.508850 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1774 11:45:42.512789 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 11:45:42.518985 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 11:45:42.522508 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 11:45:42.525624 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 11:45:42.532653 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 11:45:42.535675 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 11:45:42.539088 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 11:45:42.545929 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 11:45:42.548942 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 11:45:42.552277 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 11:45:42.555693 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 11:45:42.562247 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 11:45:42.565511 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 11:45:42.569068 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 11:45:42.575650 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1789 11:45:42.579005 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1790 11:45:42.582463 Total UI for P1: 0, mck2ui 16
1791 11:45:42.585532 best dqsien dly found for B0: ( 0, 9, 28)
1792 11:45:42.588810 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1793 11:45:42.592180 Total UI for P1: 0, mck2ui 16
1794 11:45:42.595662 best dqsien dly found for B1: ( 0, 10, 0)
1795 11:45:42.599058 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1796 11:45:42.602335 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1797 11:45:42.602419
1798 11:45:42.608796 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1799 11:45:42.612259 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1800 11:45:42.612344 [Gating] SW calibration Done
1801 11:45:42.615528 ==
1802 11:45:42.619395 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 11:45:42.622497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 11:45:42.622581 ==
1805 11:45:42.622647 RX Vref Scan: 0
1806 11:45:42.622709
1807 11:45:42.625663 RX Vref 0 -> 0, step: 1
1808 11:45:42.625746
1809 11:45:42.629067 RX Delay -130 -> 252, step: 16
1810 11:45:42.632695 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1811 11:45:42.635816 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1812 11:45:42.642473 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1813 11:45:42.645637 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1814 11:45:42.648949 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1815 11:45:42.652450 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1816 11:45:42.655456 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1817 11:45:42.658935 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1818 11:45:42.665670 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1819 11:45:42.668769 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1820 11:45:42.672489 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1821 11:45:42.675513 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1822 11:45:42.682301 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1823 11:45:42.685651 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1824 11:45:42.689202 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1825 11:45:42.692183 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1826 11:45:42.692266 ==
1827 11:45:42.695670 Dram Type= 6, Freq= 0, CH_1, rank 1
1828 11:45:42.699131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1829 11:45:42.702378 ==
1830 11:45:42.702462 DQS Delay:
1831 11:45:42.702528 DQS0 = 0, DQS1 = 0
1832 11:45:42.705627 DQM Delay:
1833 11:45:42.705709 DQM0 = 85, DQM1 = 72
1834 11:45:42.708788 DQ Delay:
1835 11:45:42.712066 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1836 11:45:42.712149 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1837 11:45:42.715389 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1838 11:45:42.718800 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1839 11:45:42.722371
1840 11:45:42.722454
1841 11:45:42.722521 ==
1842 11:45:42.725561 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 11:45:42.728708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1844 11:45:42.728792 ==
1845 11:45:42.728859
1846 11:45:42.728920
1847 11:45:42.731990 TX Vref Scan disable
1848 11:45:42.732074 == TX Byte 0 ==
1849 11:45:42.738863 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1850 11:45:42.741832 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1851 11:45:42.741942 == TX Byte 1 ==
1852 11:45:42.748991 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1853 11:45:42.752112 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1854 11:45:42.752225 ==
1855 11:45:42.755219 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 11:45:42.758554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 11:45:42.758639 ==
1858 11:45:42.772518 TX Vref=22, minBit 0, minWin=27, winSum=447
1859 11:45:42.775505 TX Vref=24, minBit 0, minWin=27, winSum=453
1860 11:45:42.778976 TX Vref=26, minBit 2, minWin=27, winSum=451
1861 11:45:42.782364 TX Vref=28, minBit 0, minWin=28, winSum=456
1862 11:45:42.785643 TX Vref=30, minBit 0, minWin=28, winSum=457
1863 11:45:42.789040 TX Vref=32, minBit 0, minWin=28, winSum=454
1864 11:45:42.795435 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1865 11:45:42.795519
1866 11:45:42.798962 Final TX Range 1 Vref 30
1867 11:45:42.799042
1868 11:45:42.799105 ==
1869 11:45:42.802179 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 11:45:42.805835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1871 11:45:42.805910 ==
1872 11:45:42.805980
1873 11:45:42.808753
1874 11:45:42.808825 TX Vref Scan disable
1875 11:45:42.812005 == TX Byte 0 ==
1876 11:45:42.815492 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1877 11:45:42.819030 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1878 11:45:42.822169 == TX Byte 1 ==
1879 11:45:42.825604 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1880 11:45:42.829143 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1881 11:45:42.832133
1882 11:45:42.832239 [DATLAT]
1883 11:45:42.832342 Freq=800, CH1 RK1
1884 11:45:42.832442
1885 11:45:42.835458 DATLAT Default: 0x9
1886 11:45:42.835539 0, 0xFFFF, sum = 0
1887 11:45:42.838884 1, 0xFFFF, sum = 0
1888 11:45:42.838960 2, 0xFFFF, sum = 0
1889 11:45:42.842044 3, 0xFFFF, sum = 0
1890 11:45:42.842118 4, 0xFFFF, sum = 0
1891 11:45:42.845382 5, 0xFFFF, sum = 0
1892 11:45:42.848775 6, 0xFFFF, sum = 0
1893 11:45:42.848850 7, 0xFFFF, sum = 0
1894 11:45:42.848914 8, 0x0, sum = 1
1895 11:45:42.852296 9, 0x0, sum = 2
1896 11:45:42.852372 10, 0x0, sum = 3
1897 11:45:42.855720 11, 0x0, sum = 4
1898 11:45:42.855795 best_step = 9
1899 11:45:42.855859
1900 11:45:42.855919 ==
1901 11:45:42.858906 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 11:45:42.865893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1903 11:45:42.865976 ==
1904 11:45:42.866041 RX Vref Scan: 0
1905 11:45:42.866101
1906 11:45:42.868660 RX Vref 0 -> 0, step: 1
1907 11:45:42.868736
1908 11:45:42.872300 RX Delay -111 -> 252, step: 8
1909 11:45:42.875415 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1910 11:45:42.878815 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1911 11:45:42.885802 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1912 11:45:42.889449 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1913 11:45:42.892392 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1914 11:45:42.895585 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1915 11:45:42.898986 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1916 11:45:42.902336 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1917 11:45:42.908857 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1918 11:45:42.912455 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1919 11:45:42.915618 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1920 11:45:42.918631 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1921 11:45:42.925336 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1922 11:45:42.929007 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1923 11:45:42.931980 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1924 11:45:42.935308 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1925 11:45:42.935394 ==
1926 11:45:42.939186 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 11:45:42.941997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1928 11:45:42.945323 ==
1929 11:45:42.945398 DQS Delay:
1930 11:45:42.945463 DQS0 = 0, DQS1 = 0
1931 11:45:42.948887 DQM Delay:
1932 11:45:42.948961 DQM0 = 83, DQM1 = 74
1933 11:45:42.952641 DQ Delay:
1934 11:45:42.955254 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =80
1935 11:45:42.955324 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1936 11:45:42.958700 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1937 11:45:42.962221 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1938 11:45:42.962300
1939 11:45:42.965730
1940 11:45:42.971960 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1941 11:45:42.977156 CH1 RK1: MR19=606, MR18=3434
1942 11:45:42.982114 CH1_RK1: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1943 11:45:42.982191 [RxdqsGatingPostProcess] freq 800
1944 11:45:42.988969 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1945 11:45:42.992002 Pre-setting of DQS Precalculation
1946 11:45:42.995236 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1947 11:45:43.005922 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1948 11:45:43.012151 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1949 11:45:43.012230
1950 11:45:43.012295
1951 11:45:43.015498 [Calibration Summary] 1600 Mbps
1952 11:45:43.015604 CH 0, Rank 0
1953 11:45:43.019161 SW Impedance : PASS
1954 11:45:43.019241 DUTY Scan : NO K
1955 11:45:43.022009 ZQ Calibration : PASS
1956 11:45:43.025238 Jitter Meter : NO K
1957 11:45:43.025312 CBT Training : PASS
1958 11:45:43.029236 Write leveling : PASS
1959 11:45:43.031945 RX DQS gating : PASS
1960 11:45:43.032028 RX DQ/DQS(RDDQC) : PASS
1961 11:45:43.035384 TX DQ/DQS : PASS
1962 11:45:43.038978 RX DATLAT : PASS
1963 11:45:43.039051 RX DQ/DQS(Engine): PASS
1964 11:45:43.042341 TX OE : NO K
1965 11:45:43.042415 All Pass.
1966 11:45:43.042484
1967 11:45:43.045612 CH 0, Rank 1
1968 11:45:43.045689 SW Impedance : PASS
1969 11:45:43.048953 DUTY Scan : NO K
1970 11:45:43.049037 ZQ Calibration : PASS
1971 11:45:43.051968 Jitter Meter : NO K
1972 11:45:43.055524 CBT Training : PASS
1973 11:45:43.055599 Write leveling : PASS
1974 11:45:43.058812 RX DQS gating : PASS
1975 11:45:43.061990 RX DQ/DQS(RDDQC) : PASS
1976 11:45:43.062062 TX DQ/DQS : PASS
1977 11:45:43.065226 RX DATLAT : PASS
1978 11:45:43.068745 RX DQ/DQS(Engine): PASS
1979 11:45:43.068819 TX OE : NO K
1980 11:45:43.072118 All Pass.
1981 11:45:43.072212
1982 11:45:43.072276 CH 1, Rank 0
1983 11:45:43.075802 SW Impedance : PASS
1984 11:45:43.075877 DUTY Scan : NO K
1985 11:45:43.078797 ZQ Calibration : PASS
1986 11:45:43.081979 Jitter Meter : NO K
1987 11:45:43.082055 CBT Training : PASS
1988 11:45:43.085767 Write leveling : PASS
1989 11:45:43.088900 RX DQS gating : PASS
1990 11:45:43.088976 RX DQ/DQS(RDDQC) : PASS
1991 11:45:43.092174 TX DQ/DQS : PASS
1992 11:45:43.092253 RX DATLAT : PASS
1993 11:45:43.095203 RX DQ/DQS(Engine): PASS
1994 11:45:43.098644 TX OE : NO K
1995 11:45:43.098719 All Pass.
1996 11:45:43.098782
1997 11:45:43.098850 CH 1, Rank 1
1998 11:45:43.101980 SW Impedance : PASS
1999 11:45:43.105712 DUTY Scan : NO K
2000 11:45:43.105789 ZQ Calibration : PASS
2001 11:45:43.108655 Jitter Meter : NO K
2002 11:45:43.111960 CBT Training : PASS
2003 11:45:43.112045 Write leveling : PASS
2004 11:45:43.115371 RX DQS gating : PASS
2005 11:45:43.119210 RX DQ/DQS(RDDQC) : PASS
2006 11:45:43.119294 TX DQ/DQS : PASS
2007 11:45:43.122271 RX DATLAT : PASS
2008 11:45:43.125345 RX DQ/DQS(Engine): PASS
2009 11:45:43.125424 TX OE : NO K
2010 11:45:43.128728 All Pass.
2011 11:45:43.128803
2012 11:45:43.128866 DramC Write-DBI off
2013 11:45:43.132047 PER_BANK_REFRESH: Hybrid Mode
2014 11:45:43.132124 TX_TRACKING: ON
2015 11:45:43.135235 [GetDramInforAfterCalByMRR] Vendor 6.
2016 11:45:43.141810 [GetDramInforAfterCalByMRR] Revision 606.
2017 11:45:43.145088 [GetDramInforAfterCalByMRR] Revision 2 0.
2018 11:45:43.145170 MR0 0x3939
2019 11:45:43.145235 MR8 0x1111
2020 11:45:43.148271 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2021 11:45:43.148375
2022 11:45:43.152173 MR0 0x3939
2023 11:45:43.152278 MR8 0x1111
2024 11:45:43.155208 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2025 11:45:43.155285
2026 11:45:43.164998 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2027 11:45:43.168369 [FAST_K] Save calibration result to emmc
2028 11:45:43.171892 [FAST_K] Save calibration result to emmc
2029 11:45:43.175241 dram_init: config_dvfs: 1
2030 11:45:43.178529 dramc_set_vcore_voltage set vcore to 662500
2031 11:45:43.181720 Read voltage for 1200, 2
2032 11:45:43.181805 Vio18 = 0
2033 11:45:43.181871 Vcore = 662500
2034 11:45:43.185309 Vdram = 0
2035 11:45:43.185385 Vddq = 0
2036 11:45:43.185457 Vmddr = 0
2037 11:45:43.191723 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2038 11:45:43.195424 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2039 11:45:43.198179 MEM_TYPE=3, freq_sel=15
2040 11:45:43.201736 sv_algorithm_assistance_LP4_1600
2041 11:45:43.205302 ============ PULL DRAM RESETB DOWN ============
2042 11:45:43.208291 ========== PULL DRAM RESETB DOWN end =========
2043 11:45:43.214901 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2044 11:45:43.218391 ===================================
2045 11:45:43.218470 LPDDR4 DRAM CONFIGURATION
2046 11:45:43.221983 ===================================
2047 11:45:43.225091 EX_ROW_EN[0] = 0x0
2048 11:45:43.228442 EX_ROW_EN[1] = 0x0
2049 11:45:43.228588 LP4Y_EN = 0x0
2050 11:45:43.231585 WORK_FSP = 0x0
2051 11:45:43.231694 WL = 0x4
2052 11:45:43.234885 RL = 0x4
2053 11:45:43.234987 BL = 0x2
2054 11:45:43.238363 RPST = 0x0
2055 11:45:43.238446 RD_PRE = 0x0
2056 11:45:43.241406 WR_PRE = 0x1
2057 11:45:43.241482 WR_PST = 0x0
2058 11:45:43.244950 DBI_WR = 0x0
2059 11:45:43.245026 DBI_RD = 0x0
2060 11:45:43.248352 OTF = 0x1
2061 11:45:43.251748 ===================================
2062 11:45:43.255336 ===================================
2063 11:45:43.255421 ANA top config
2064 11:45:43.258616 ===================================
2065 11:45:43.261632 DLL_ASYNC_EN = 0
2066 11:45:43.265022 ALL_SLAVE_EN = 0
2067 11:45:43.265099 NEW_RANK_MODE = 1
2068 11:45:43.268411 DLL_IDLE_MODE = 1
2069 11:45:43.271726 LP45_APHY_COMB_EN = 1
2070 11:45:43.274964 TX_ODT_DIS = 1
2071 11:45:43.278500 NEW_8X_MODE = 1
2072 11:45:43.281525 ===================================
2073 11:45:43.284933 ===================================
2074 11:45:43.285018 data_rate = 2400
2075 11:45:43.288294 CKR = 1
2076 11:45:43.291548 DQ_P2S_RATIO = 8
2077 11:45:43.295366 ===================================
2078 11:45:43.298448 CA_P2S_RATIO = 8
2079 11:45:43.301858 DQ_CA_OPEN = 0
2080 11:45:43.304901 DQ_SEMI_OPEN = 0
2081 11:45:43.304986 CA_SEMI_OPEN = 0
2082 11:45:43.308251 CA_FULL_RATE = 0
2083 11:45:43.311840 DQ_CKDIV4_EN = 0
2084 11:45:43.315371 CA_CKDIV4_EN = 0
2085 11:45:43.318509 CA_PREDIV_EN = 0
2086 11:45:43.321449 PH8_DLY = 17
2087 11:45:43.321527 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2088 11:45:43.324717 DQ_AAMCK_DIV = 4
2089 11:45:43.328211 CA_AAMCK_DIV = 4
2090 11:45:43.331622 CA_ADMCK_DIV = 4
2091 11:45:43.334870 DQ_TRACK_CA_EN = 0
2092 11:45:43.338038 CA_PICK = 1200
2093 11:45:43.341946 CA_MCKIO = 1200
2094 11:45:43.342047 MCKIO_SEMI = 0
2095 11:45:43.344971 PLL_FREQ = 2366
2096 11:45:43.348162 DQ_UI_PI_RATIO = 32
2097 11:45:43.351794 CA_UI_PI_RATIO = 0
2098 11:45:43.354958 ===================================
2099 11:45:43.358301 ===================================
2100 11:45:43.361293 memory_type:LPDDR4
2101 11:45:43.361376 GP_NUM : 10
2102 11:45:43.364856 SRAM_EN : 1
2103 11:45:43.364939 MD32_EN : 0
2104 11:45:43.368403 ===================================
2105 11:45:43.371654 [ANA_INIT] >>>>>>>>>>>>>>
2106 11:45:43.375136 <<<<<< [CONFIGURE PHASE]: ANA_TX
2107 11:45:43.378107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2108 11:45:43.381649 ===================================
2109 11:45:43.384979 data_rate = 2400,PCW = 0X5b00
2110 11:45:43.388311 ===================================
2111 11:45:43.391445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2112 11:45:43.398330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2113 11:45:43.401572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2114 11:45:43.408259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2115 11:45:43.411718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2116 11:45:43.414900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2117 11:45:43.414984 [ANA_INIT] flow start
2118 11:45:43.418292 [ANA_INIT] PLL >>>>>>>>
2119 11:45:43.421546 [ANA_INIT] PLL <<<<<<<<
2120 11:45:43.421630 [ANA_INIT] MIDPI >>>>>>>>
2121 11:45:43.424905 [ANA_INIT] MIDPI <<<<<<<<
2122 11:45:43.428046 [ANA_INIT] DLL >>>>>>>>
2123 11:45:43.428124 [ANA_INIT] DLL <<<<<<<<
2124 11:45:43.431482 [ANA_INIT] flow end
2125 11:45:43.434814 ============ LP4 DIFF to SE enter ============
2126 11:45:43.437932 ============ LP4 DIFF to SE exit ============
2127 11:45:43.441474 [ANA_INIT] <<<<<<<<<<<<<
2128 11:45:43.444565 [Flow] Enable top DCM control >>>>>
2129 11:45:43.447809 [Flow] Enable top DCM control <<<<<
2130 11:45:43.451625 Enable DLL master slave shuffle
2131 11:45:43.457850 ==============================================================
2132 11:45:43.457952 Gating Mode config
2133 11:45:43.464683 ==============================================================
2134 11:45:43.464764 Config description:
2135 11:45:43.474755 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2136 11:45:43.481776 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2137 11:45:43.487820 SELPH_MODE 0: By rank 1: By Phase
2138 11:45:43.491166 ==============================================================
2139 11:45:43.494841 GAT_TRACK_EN = 1
2140 11:45:43.497813 RX_GATING_MODE = 2
2141 11:45:43.501530 RX_GATING_TRACK_MODE = 2
2142 11:45:43.504784 SELPH_MODE = 1
2143 11:45:43.508416 PICG_EARLY_EN = 1
2144 11:45:43.511405 VALID_LAT_VALUE = 1
2145 11:45:43.518300 ==============================================================
2146 11:45:43.521336 Enter into Gating configuration >>>>
2147 11:45:43.521411 Exit from Gating configuration <<<<
2148 11:45:43.524626 Enter into DVFS_PRE_config >>>>>
2149 11:45:43.537952 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2150 11:45:43.541404 Exit from DVFS_PRE_config <<<<<
2151 11:45:43.544601 Enter into PICG configuration >>>>
2152 11:45:43.548023 Exit from PICG configuration <<<<
2153 11:45:43.548107 [RX_INPUT] configuration >>>>>
2154 11:45:43.551534 [RX_INPUT] configuration <<<<<
2155 11:45:43.557877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2156 11:45:43.561352 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2157 11:45:43.568002 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2158 11:45:43.574462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2159 11:45:43.581377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2160 11:45:43.587964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2161 11:45:43.591277 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2162 11:45:43.595190 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2163 11:45:43.598439 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2164 11:45:43.604640 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2165 11:45:43.608236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2166 11:45:43.611230 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 11:45:43.614989 ===================================
2168 11:45:43.618144 LPDDR4 DRAM CONFIGURATION
2169 11:45:43.621211 ===================================
2170 11:45:43.625107 EX_ROW_EN[0] = 0x0
2171 11:45:43.625181 EX_ROW_EN[1] = 0x0
2172 11:45:43.627915 LP4Y_EN = 0x0
2173 11:45:43.627985 WORK_FSP = 0x0
2174 11:45:43.631793 WL = 0x4
2175 11:45:43.631867 RL = 0x4
2176 11:45:43.634669 BL = 0x2
2177 11:45:43.634749 RPST = 0x0
2178 11:45:43.638475 RD_PRE = 0x0
2179 11:45:43.638553 WR_PRE = 0x1
2180 11:45:43.641627 WR_PST = 0x0
2181 11:45:43.641698 DBI_WR = 0x0
2182 11:45:43.645096 DBI_RD = 0x0
2183 11:45:43.645168 OTF = 0x1
2184 11:45:43.648062 ===================================
2185 11:45:43.651404 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2186 11:45:43.657933 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2187 11:45:43.661475 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 11:45:43.665080 ===================================
2189 11:45:43.667898 LPDDR4 DRAM CONFIGURATION
2190 11:45:43.671406 ===================================
2191 11:45:43.671480 EX_ROW_EN[0] = 0x10
2192 11:45:43.675185 EX_ROW_EN[1] = 0x0
2193 11:45:43.677852 LP4Y_EN = 0x0
2194 11:45:43.677924 WORK_FSP = 0x0
2195 11:45:43.681183 WL = 0x4
2196 11:45:43.681254 RL = 0x4
2197 11:45:43.684833 BL = 0x2
2198 11:45:43.684907 RPST = 0x0
2199 11:45:43.688146 RD_PRE = 0x0
2200 11:45:43.688223 WR_PRE = 0x1
2201 11:45:43.691351 WR_PST = 0x0
2202 11:45:43.691426 DBI_WR = 0x0
2203 11:45:43.694684 DBI_RD = 0x0
2204 11:45:43.694756 OTF = 0x1
2205 11:45:43.698001 ===================================
2206 11:45:43.704611 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2207 11:45:43.704692 ==
2208 11:45:43.707852 Dram Type= 6, Freq= 0, CH_0, rank 0
2209 11:45:43.711384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2210 11:45:43.714453 ==
2211 11:45:43.714527 [Duty_Offset_Calibration]
2212 11:45:43.718235 B0:0 B1:2 CA:1
2213 11:45:43.718310
2214 11:45:43.721478 [DutyScan_Calibration_Flow] k_type=0
2215 11:45:43.729462
2216 11:45:43.729537 ==CLK 0==
2217 11:45:43.732947 Final CLK duty delay cell = 0
2218 11:45:43.736212 [0] MAX Duty = 5093%(X100), DQS PI = 12
2219 11:45:43.739789 [0] MIN Duty = 4938%(X100), DQS PI = 52
2220 11:45:43.739871 [0] AVG Duty = 5015%(X100)
2221 11:45:43.742757
2222 11:45:43.746293 CH0 CLK Duty spec in!! Max-Min= 155%
2223 11:45:43.749546 [DutyScan_Calibration_Flow] ====Done====
2224 11:45:43.749626
2225 11:45:43.753226 [DutyScan_Calibration_Flow] k_type=1
2226 11:45:43.768639
2227 11:45:43.768719 ==DQS 0 ==
2228 11:45:43.772366 Final DQS duty delay cell = 0
2229 11:45:43.775593 [0] MAX Duty = 5125%(X100), DQS PI = 30
2230 11:45:43.778673 [0] MIN Duty = 5031%(X100), DQS PI = 4
2231 11:45:43.778758 [0] AVG Duty = 5078%(X100)
2232 11:45:43.781877
2233 11:45:43.781955 ==DQS 1 ==
2234 11:45:43.785421 Final DQS duty delay cell = 0
2235 11:45:43.788708 [0] MAX Duty = 5062%(X100), DQS PI = 58
2236 11:45:43.792436 [0] MIN Duty = 4906%(X100), DQS PI = 16
2237 11:45:43.792545 [0] AVG Duty = 4984%(X100)
2238 11:45:43.795770
2239 11:45:43.798688 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2240 11:45:43.798763
2241 11:45:43.801968 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2242 11:45:43.805823 [DutyScan_Calibration_Flow] ====Done====
2243 11:45:43.805899
2244 11:45:43.808757 [DutyScan_Calibration_Flow] k_type=3
2245 11:45:43.825253
2246 11:45:43.825338 ==DQM 0 ==
2247 11:45:43.828782 Final DQM duty delay cell = 0
2248 11:45:43.832096 [0] MAX Duty = 5124%(X100), DQS PI = 20
2249 11:45:43.835330 [0] MIN Duty = 4969%(X100), DQS PI = 40
2250 11:45:43.835414 [0] AVG Duty = 5046%(X100)
2251 11:45:43.838760
2252 11:45:43.838829 ==DQM 1 ==
2253 11:45:43.841780 Final DQM duty delay cell = 0
2254 11:45:43.845071 [0] MAX Duty = 5000%(X100), DQS PI = 56
2255 11:45:43.848369 [0] MIN Duty = 4844%(X100), DQS PI = 0
2256 11:45:43.848437 [0] AVG Duty = 4922%(X100)
2257 11:45:43.851944
2258 11:45:43.855399 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2259 11:45:43.855471
2260 11:45:43.858449 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2261 11:45:43.862283 [DutyScan_Calibration_Flow] ====Done====
2262 11:45:43.862360
2263 11:45:43.864918 [DutyScan_Calibration_Flow] k_type=2
2264 11:45:43.879874
2265 11:45:43.879979 ==DQ 0 ==
2266 11:45:43.883313 Final DQ duty delay cell = -4
2267 11:45:43.886774 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2268 11:45:43.890146 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2269 11:45:43.893824 [-4] AVG Duty = 4937%(X100)
2270 11:45:43.893898
2271 11:45:43.893969 ==DQ 1 ==
2272 11:45:43.896639 Final DQ duty delay cell = -4
2273 11:45:43.899807 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2274 11:45:43.903429 [-4] MIN Duty = 4876%(X100), DQS PI = 38
2275 11:45:43.906827 [-4] AVG Duty = 4969%(X100)
2276 11:45:43.906902
2277 11:45:43.909863 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2278 11:45:43.909943
2279 11:45:43.913289 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2280 11:45:43.916469 [DutyScan_Calibration_Flow] ====Done====
2281 11:45:43.916616 ==
2282 11:45:43.920175 Dram Type= 6, Freq= 0, CH_1, rank 0
2283 11:45:43.923575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2284 11:45:43.923648 ==
2285 11:45:43.926862 [Duty_Offset_Calibration]
2286 11:45:43.926948 B0:0 B1:4 CA:-5
2287 11:45:43.927014
2288 11:45:43.929973 [DutyScan_Calibration_Flow] k_type=0
2289 11:45:43.940716
2290 11:45:43.940827 ==CLK 0==
2291 11:45:43.943897 Final CLK duty delay cell = 0
2292 11:45:43.947489 [0] MAX Duty = 5094%(X100), DQS PI = 24
2293 11:45:43.950675 [0] MIN Duty = 4907%(X100), DQS PI = 44
2294 11:45:43.950795 [0] AVG Duty = 5000%(X100)
2295 11:45:43.953972
2296 11:45:43.957554 CH1 CLK Duty spec in!! Max-Min= 187%
2297 11:45:43.960673 [DutyScan_Calibration_Flow] ====Done====
2298 11:45:43.960747
2299 11:45:43.963837 [DutyScan_Calibration_Flow] k_type=1
2300 11:45:43.979099
2301 11:45:43.979179 ==DQS 0 ==
2302 11:45:43.982324 Final DQS duty delay cell = 0
2303 11:45:43.986519 [0] MAX Duty = 5125%(X100), DQS PI = 16
2304 11:45:43.989258 [0] MIN Duty = 4875%(X100), DQS PI = 40
2305 11:45:43.992742 [0] AVG Duty = 5000%(X100)
2306 11:45:43.992836
2307 11:45:43.992903 ==DQS 1 ==
2308 11:45:43.995772 Final DQS duty delay cell = -4
2309 11:45:43.999105 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2310 11:45:44.002308 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2311 11:45:44.005777 [-4] AVG Duty = 4953%(X100)
2312 11:45:44.005851
2313 11:45:44.009349 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2314 11:45:44.009427
2315 11:45:44.012194 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2316 11:45:44.016103 [DutyScan_Calibration_Flow] ====Done====
2317 11:45:44.016175
2318 11:45:44.018806 [DutyScan_Calibration_Flow] k_type=3
2319 11:45:44.034336
2320 11:45:44.034424 ==DQM 0 ==
2321 11:45:44.037466 Final DQM duty delay cell = -4
2322 11:45:44.041017 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2323 11:45:44.044186 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2324 11:45:44.047495 [-4] AVG Duty = 4969%(X100)
2325 11:45:44.047565
2326 11:45:44.047626 ==DQM 1 ==
2327 11:45:44.050875 Final DQM duty delay cell = -4
2328 11:45:44.054190 [-4] MAX Duty = 5093%(X100), DQS PI = 20
2329 11:45:44.057470 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2330 11:45:44.061015 [-4] AVG Duty = 5000%(X100)
2331 11:45:44.061088
2332 11:45:44.064227 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2333 11:45:44.064326
2334 11:45:44.067555 CH1 DQM 1 Duty spec in!! Max-Min= 186%
2335 11:45:44.070859 [DutyScan_Calibration_Flow] ====Done====
2336 11:45:44.070941
2337 11:45:44.074100 [DutyScan_Calibration_Flow] k_type=2
2338 11:45:44.091150
2339 11:45:44.091231 ==DQ 0 ==
2340 11:45:44.094758 Final DQ duty delay cell = 0
2341 11:45:44.097847 [0] MAX Duty = 5062%(X100), DQS PI = 0
2342 11:45:44.101185 [0] MIN Duty = 4969%(X100), DQS PI = 42
2343 11:45:44.101267 [0] AVG Duty = 5015%(X100)
2344 11:45:44.101333
2345 11:45:44.104760 ==DQ 1 ==
2346 11:45:44.108284 Final DQ duty delay cell = 0
2347 11:45:44.111250 [0] MAX Duty = 5000%(X100), DQS PI = 6
2348 11:45:44.114742 [0] MIN Duty = 4907%(X100), DQS PI = 0
2349 11:45:44.114822 [0] AVG Duty = 4953%(X100)
2350 11:45:44.114886
2351 11:45:44.117961 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2352 11:45:44.118032
2353 11:45:44.121207 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2354 11:45:44.124785 [DutyScan_Calibration_Flow] ====Done====
2355 11:45:44.130471 nWR fixed to 30
2356 11:45:44.133483 [ModeRegInit_LP4] CH0 RK0
2357 11:45:44.133559 [ModeRegInit_LP4] CH0 RK1
2358 11:45:44.136945 [ModeRegInit_LP4] CH1 RK0
2359 11:45:44.140115 [ModeRegInit_LP4] CH1 RK1
2360 11:45:44.140184 match AC timing 6
2361 11:45:44.146637 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2362 11:45:44.150289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2363 11:45:44.153602 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2364 11:45:44.160189 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2365 11:45:44.163667 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2366 11:45:44.163739 ==
2367 11:45:44.166511 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 11:45:44.170081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2369 11:45:44.170155 ==
2370 11:45:44.176664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2371 11:45:44.183193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2372 11:45:44.190694 [CA 0] Center 39 (9~70) winsize 62
2373 11:45:44.194171 [CA 1] Center 39 (9~70) winsize 62
2374 11:45:44.197576 [CA 2] Center 36 (5~67) winsize 63
2375 11:45:44.200711 [CA 3] Center 35 (5~66) winsize 62
2376 11:45:44.204210 [CA 4] Center 34 (3~65) winsize 63
2377 11:45:44.207343 [CA 5] Center 33 (3~64) winsize 62
2378 11:45:44.207409
2379 11:45:44.210724 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2380 11:45:44.210792
2381 11:45:44.214237 [CATrainingPosCal] consider 1 rank data
2382 11:45:44.217271 u2DelayCellTimex100 = 270/100 ps
2383 11:45:44.220778 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2384 11:45:44.223823 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2385 11:45:44.230579 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2386 11:45:44.234069 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2387 11:45:44.237093 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2388 11:45:44.240498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2389 11:45:44.240615
2390 11:45:44.244323 CA PerBit enable=1, Macro0, CA PI delay=33
2391 11:45:44.244404
2392 11:45:44.247591 [CBTSetCACLKResult] CA Dly = 33
2393 11:45:44.247672 CS Dly: 7 (0~38)
2394 11:45:44.250800 ==
2395 11:45:44.250881 Dram Type= 6, Freq= 0, CH_0, rank 1
2396 11:45:44.257554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2397 11:45:44.257637 ==
2398 11:45:44.260698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2399 11:45:44.267409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2400 11:45:44.276099 [CA 0] Center 39 (8~70) winsize 63
2401 11:45:44.279510 [CA 1] Center 39 (8~70) winsize 63
2402 11:45:44.282814 [CA 2] Center 35 (5~66) winsize 62
2403 11:45:44.286244 [CA 3] Center 35 (4~66) winsize 63
2404 11:45:44.289335 [CA 4] Center 33 (3~64) winsize 62
2405 11:45:44.293331 [CA 5] Center 33 (3~64) winsize 62
2406 11:45:44.293408
2407 11:45:44.295981 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2408 11:45:44.296050
2409 11:45:44.299547 [CATrainingPosCal] consider 2 rank data
2410 11:45:44.302786 u2DelayCellTimex100 = 270/100 ps
2411 11:45:44.305980 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2412 11:45:44.309403 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2413 11:45:44.316104 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2414 11:45:44.319724 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2415 11:45:44.322789 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2416 11:45:44.326220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2417 11:45:44.326290
2418 11:45:44.329411 CA PerBit enable=1, Macro0, CA PI delay=33
2419 11:45:44.329482
2420 11:45:44.332907 [CBTSetCACLKResult] CA Dly = 33
2421 11:45:44.332977 CS Dly: 7 (0~39)
2422 11:45:44.333038
2423 11:45:44.336357 ----->DramcWriteLeveling(PI) begin...
2424 11:45:44.339204 ==
2425 11:45:44.342911 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 11:45:44.346312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 11:45:44.346384 ==
2428 11:45:44.349447 Write leveling (Byte 0): 28 => 28
2429 11:45:44.353245 Write leveling (Byte 1): 25 => 25
2430 11:45:44.355962 DramcWriteLeveling(PI) end<-----
2431 11:45:44.356032
2432 11:45:44.356093 ==
2433 11:45:44.359687 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 11:45:44.362955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 11:45:44.363031 ==
2436 11:45:44.366508 [Gating] SW mode calibration
2437 11:45:44.372697 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2438 11:45:44.376204 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2439 11:45:44.382701 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 11:45:44.386232 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 11:45:44.389343 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 11:45:44.396114 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 11:45:44.399392 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2444 11:45:44.402669 0 11 20 | B1->B0 | 2d2d 2a2a | 0 0 | (1 0) (1 0)
2445 11:45:44.409463 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 11:45:44.412967 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 11:45:44.416114 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 11:45:44.422960 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 11:45:44.426212 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 11:45:44.429369 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 11:45:44.435994 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 11:45:44.439623 0 12 20 | B1->B0 | 3c3c 4141 | 0 1 | (0 0) (0 0)
2453 11:45:44.442787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 11:45:44.449374 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 11:45:44.452743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 11:45:44.456043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 11:45:44.462768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 11:45:44.465763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 11:45:44.469393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2460 11:45:44.475795 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2461 11:45:44.479394 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2462 11:45:44.482801 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 11:45:44.485773 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 11:45:44.492731 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 11:45:44.495863 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 11:45:44.499166 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 11:45:44.506058 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 11:45:44.509306 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 11:45:44.512771 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 11:45:44.519339 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 11:45:44.522760 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 11:45:44.525646 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 11:45:44.532454 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 11:45:44.535898 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 11:45:44.539598 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2476 11:45:44.545648 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2477 11:45:44.548964 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2478 11:45:44.552258 Total UI for P1: 0, mck2ui 16
2479 11:45:44.555857 best dqsien dly found for B0: ( 0, 15, 18)
2480 11:45:44.559010 Total UI for P1: 0, mck2ui 16
2481 11:45:44.562321 best dqsien dly found for B1: ( 0, 15, 18)
2482 11:45:44.565841 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2483 11:45:44.568891 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2484 11:45:44.568959
2485 11:45:44.572457 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2486 11:45:44.575800 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2487 11:45:44.579020 [Gating] SW calibration Done
2488 11:45:44.579087 ==
2489 11:45:44.582567 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 11:45:44.585481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2491 11:45:44.588801 ==
2492 11:45:44.588869 RX Vref Scan: 0
2493 11:45:44.588929
2494 11:45:44.592092 RX Vref 0 -> 0, step: 1
2495 11:45:44.592157
2496 11:45:44.595609 RX Delay -40 -> 252, step: 8
2497 11:45:44.598915 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2498 11:45:44.602266 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2499 11:45:44.605534 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2500 11:45:44.608804 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2501 11:45:44.615726 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2502 11:45:44.618744 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2503 11:45:44.622062 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2504 11:45:44.625550 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2505 11:45:44.628685 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2506 11:45:44.632380 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2507 11:45:44.638782 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2508 11:45:44.642804 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2509 11:45:44.645359 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2510 11:45:44.649116 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2511 11:45:44.655627 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2512 11:45:44.659098 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2513 11:45:44.659178 ==
2514 11:45:44.662186 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 11:45:44.665364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2516 11:45:44.665442 ==
2517 11:45:44.665505 DQS Delay:
2518 11:45:44.668656 DQS0 = 0, DQS1 = 0
2519 11:45:44.668723 DQM Delay:
2520 11:45:44.672142 DQM0 = 115, DQM1 = 105
2521 11:45:44.672210 DQ Delay:
2522 11:45:44.675220 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2523 11:45:44.678594 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2524 11:45:44.682169 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2525 11:45:44.685406 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
2526 11:45:44.688640
2527 11:45:44.688713
2528 11:45:44.688778 ==
2529 11:45:44.691862 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 11:45:44.695211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 11:45:44.695280 ==
2532 11:45:44.695340
2533 11:45:44.695397
2534 11:45:44.698709 TX Vref Scan disable
2535 11:45:44.698773 == TX Byte 0 ==
2536 11:45:44.705406 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2537 11:45:44.708786 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2538 11:45:44.708854 == TX Byte 1 ==
2539 11:45:44.715551 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2540 11:45:44.718736 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2541 11:45:44.718808 ==
2542 11:45:44.721827 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 11:45:44.725265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 11:45:44.725338 ==
2545 11:45:44.738083 TX Vref=22, minBit 8, minWin=25, winSum=414
2546 11:45:44.741019 TX Vref=24, minBit 10, minWin=25, winSum=421
2547 11:45:44.744215 TX Vref=26, minBit 12, minWin=25, winSum=425
2548 11:45:44.747920 TX Vref=28, minBit 8, minWin=26, winSum=434
2549 11:45:44.751276 TX Vref=30, minBit 8, minWin=26, winSum=433
2550 11:45:44.757907 TX Vref=32, minBit 9, minWin=26, winSum=432
2551 11:45:44.761258 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2552 11:45:44.761329
2553 11:45:44.764268 Final TX Range 1 Vref 28
2554 11:45:44.764341
2555 11:45:44.764401 ==
2556 11:45:44.767801 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 11:45:44.770849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2558 11:45:44.774112 ==
2559 11:45:44.774179
2560 11:45:44.774238
2561 11:45:44.774295 TX Vref Scan disable
2562 11:45:44.777876 == TX Byte 0 ==
2563 11:45:44.781150 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2564 11:45:44.784150 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2565 11:45:44.787880 == TX Byte 1 ==
2566 11:45:44.791112 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2567 11:45:44.794317 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2568 11:45:44.797705
2569 11:45:44.797781 [DATLAT]
2570 11:45:44.797844 Freq=1200, CH0 RK0
2571 11:45:44.797903
2572 11:45:44.800973 DATLAT Default: 0xd
2573 11:45:44.801039 0, 0xFFFF, sum = 0
2574 11:45:44.804680 1, 0xFFFF, sum = 0
2575 11:45:44.804747 2, 0xFFFF, sum = 0
2576 11:45:44.808113 3, 0xFFFF, sum = 0
2577 11:45:44.808179 4, 0xFFFF, sum = 0
2578 11:45:44.811231 5, 0xFFFF, sum = 0
2579 11:45:44.811296 6, 0xFFFF, sum = 0
2580 11:45:44.814494 7, 0xFFFF, sum = 0
2581 11:45:44.817505 8, 0xFFFF, sum = 0
2582 11:45:44.817577 9, 0xFFFF, sum = 0
2583 11:45:44.820993 10, 0xFFFF, sum = 0
2584 11:45:44.821062 11, 0x0, sum = 1
2585 11:45:44.824233 12, 0x0, sum = 2
2586 11:45:44.824308 13, 0x0, sum = 3
2587 11:45:44.824371 14, 0x0, sum = 4
2588 11:45:44.828053 best_step = 12
2589 11:45:44.828122
2590 11:45:44.828180 ==
2591 11:45:44.831376 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 11:45:44.834394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2593 11:45:44.834476 ==
2594 11:45:44.837913 RX Vref Scan: 1
2595 11:45:44.837989
2596 11:45:44.840794 Set Vref Range= 32 -> 127
2597 11:45:44.840865
2598 11:45:44.840924 RX Vref 32 -> 127, step: 1
2599 11:45:44.840982
2600 11:45:44.844154 RX Delay -21 -> 252, step: 4
2601 11:45:44.844218
2602 11:45:44.847635 Set Vref, RX VrefLevel [Byte0]: 32
2603 11:45:44.850708 [Byte1]: 32
2604 11:45:44.854353
2605 11:45:44.854425 Set Vref, RX VrefLevel [Byte0]: 33
2606 11:45:44.857659 [Byte1]: 33
2607 11:45:44.862334
2608 11:45:44.862404 Set Vref, RX VrefLevel [Byte0]: 34
2609 11:45:44.865583 [Byte1]: 34
2610 11:45:44.870161
2611 11:45:44.870230 Set Vref, RX VrefLevel [Byte0]: 35
2612 11:45:44.873430 [Byte1]: 35
2613 11:45:44.878058
2614 11:45:44.878126 Set Vref, RX VrefLevel [Byte0]: 36
2615 11:45:44.881397 [Byte1]: 36
2616 11:45:44.885851
2617 11:45:44.885924 Set Vref, RX VrefLevel [Byte0]: 37
2618 11:45:44.889501 [Byte1]: 37
2619 11:45:44.894059
2620 11:45:44.894126 Set Vref, RX VrefLevel [Byte0]: 38
2621 11:45:44.897127 [Byte1]: 38
2622 11:45:44.901923
2623 11:45:44.901992 Set Vref, RX VrefLevel [Byte0]: 39
2624 11:45:44.905171 [Byte1]: 39
2625 11:45:44.910078
2626 11:45:44.910149 Set Vref, RX VrefLevel [Byte0]: 40
2627 11:45:44.912991 [Byte1]: 40
2628 11:45:44.917954
2629 11:45:44.918027 Set Vref, RX VrefLevel [Byte0]: 41
2630 11:45:44.920964 [Byte1]: 41
2631 11:45:44.925451
2632 11:45:44.925518 Set Vref, RX VrefLevel [Byte0]: 42
2633 11:45:44.929137 [Byte1]: 42
2634 11:45:44.933703
2635 11:45:44.933778 Set Vref, RX VrefLevel [Byte0]: 43
2636 11:45:44.936971 [Byte1]: 43
2637 11:45:44.941386
2638 11:45:44.941460 Set Vref, RX VrefLevel [Byte0]: 44
2639 11:45:44.945016 [Byte1]: 44
2640 11:45:44.949394
2641 11:45:44.949462 Set Vref, RX VrefLevel [Byte0]: 45
2642 11:45:44.952823 [Byte1]: 45
2643 11:45:44.957250
2644 11:45:44.957318 Set Vref, RX VrefLevel [Byte0]: 46
2645 11:45:44.960742 [Byte1]: 46
2646 11:45:44.965454
2647 11:45:44.965524 Set Vref, RX VrefLevel [Byte0]: 47
2648 11:45:44.969106 [Byte1]: 47
2649 11:45:44.973285
2650 11:45:44.973351 Set Vref, RX VrefLevel [Byte0]: 48
2651 11:45:44.976343 [Byte1]: 48
2652 11:45:44.981129
2653 11:45:44.981194 Set Vref, RX VrefLevel [Byte0]: 49
2654 11:45:44.984649 [Byte1]: 49
2655 11:45:44.989500
2656 11:45:44.989571 Set Vref, RX VrefLevel [Byte0]: 50
2657 11:45:44.992260 [Byte1]: 50
2658 11:45:44.996997
2659 11:45:44.997066 Set Vref, RX VrefLevel [Byte0]: 51
2660 11:45:45.000221 [Byte1]: 51
2661 11:45:45.004671
2662 11:45:45.004737 Set Vref, RX VrefLevel [Byte0]: 52
2663 11:45:45.008008 [Byte1]: 52
2664 11:45:45.012898
2665 11:45:45.012965 Set Vref, RX VrefLevel [Byte0]: 53
2666 11:45:45.016338 [Byte1]: 53
2667 11:45:45.020697
2668 11:45:45.020770 Set Vref, RX VrefLevel [Byte0]: 54
2669 11:45:45.023961 [Byte1]: 54
2670 11:45:45.028744
2671 11:45:45.028810 Set Vref, RX VrefLevel [Byte0]: 55
2672 11:45:45.032030 [Byte1]: 55
2673 11:45:45.036736
2674 11:45:45.036817 Set Vref, RX VrefLevel [Byte0]: 56
2675 11:45:45.039931 [Byte1]: 56
2676 11:45:45.044642
2677 11:45:45.044711 Set Vref, RX VrefLevel [Byte0]: 57
2678 11:45:45.047917 [Byte1]: 57
2679 11:45:45.052332
2680 11:45:45.052430 Set Vref, RX VrefLevel [Byte0]: 58
2681 11:45:45.055783 [Byte1]: 58
2682 11:45:45.060310
2683 11:45:45.060376 Set Vref, RX VrefLevel [Byte0]: 59
2684 11:45:45.063766 [Byte1]: 59
2685 11:45:45.068138
2686 11:45:45.068208 Set Vref, RX VrefLevel [Byte0]: 60
2687 11:45:45.071764 [Byte1]: 60
2688 11:45:45.076146
2689 11:45:45.076212 Set Vref, RX VrefLevel [Byte0]: 61
2690 11:45:45.079359 [Byte1]: 61
2691 11:45:45.084169
2692 11:45:45.084243 Set Vref, RX VrefLevel [Byte0]: 62
2693 11:45:45.087364 [Byte1]: 62
2694 11:45:45.091947
2695 11:45:45.092014 Set Vref, RX VrefLevel [Byte0]: 63
2696 11:45:45.095327 [Byte1]: 63
2697 11:45:45.099870
2698 11:45:45.099937 Set Vref, RX VrefLevel [Byte0]: 64
2699 11:45:45.103242 [Byte1]: 64
2700 11:45:45.107766
2701 11:45:45.107838 Set Vref, RX VrefLevel [Byte0]: 65
2702 11:45:45.111418 [Byte1]: 65
2703 11:45:45.116273
2704 11:45:45.116339 Final RX Vref Byte 0 = 46 to rank0
2705 11:45:45.119125 Final RX Vref Byte 1 = 45 to rank0
2706 11:45:45.122458 Final RX Vref Byte 0 = 46 to rank1
2707 11:45:45.125716 Final RX Vref Byte 1 = 45 to rank1==
2708 11:45:45.129247 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 11:45:45.135614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2710 11:45:45.135706 ==
2711 11:45:45.135771 DQS Delay:
2712 11:45:45.135832 DQS0 = 0, DQS1 = 0
2713 11:45:45.138963 DQM Delay:
2714 11:45:45.139044 DQM0 = 113, DQM1 = 104
2715 11:45:45.142614 DQ Delay:
2716 11:45:45.145792 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2717 11:45:45.149170 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2718 11:45:45.152537 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2719 11:45:45.155970 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2720 11:45:45.156052
2721 11:45:45.156117
2722 11:45:45.162322 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2723 11:45:45.165757 CH0 RK0: MR19=404, MR18=909
2724 11:45:45.172572 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2725 11:45:45.172654
2726 11:45:45.175793 ----->DramcWriteLeveling(PI) begin...
2727 11:45:45.175875 ==
2728 11:45:45.179335 Dram Type= 6, Freq= 0, CH_0, rank 1
2729 11:45:45.182583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2730 11:45:45.183005 ==
2731 11:45:45.186145 Write leveling (Byte 0): 28 => 28
2732 11:45:45.189520 Write leveling (Byte 1): 24 => 24
2733 11:45:45.192465 DramcWriteLeveling(PI) end<-----
2734 11:45:45.192920
2735 11:45:45.193252 ==
2736 11:45:45.195906 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 11:45:45.202668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 11:45:45.203111 ==
2739 11:45:45.203462 [Gating] SW mode calibration
2740 11:45:45.212483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2741 11:45:45.216168 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2742 11:45:45.219499 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2743 11:45:45.225958 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2744 11:45:45.229098 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2745 11:45:45.232731 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2746 11:45:45.239482 0 11 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2747 11:45:45.242603 0 11 20 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
2748 11:45:45.245797 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2749 11:45:45.252409 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2750 11:45:45.256370 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2751 11:45:45.259429 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2752 11:45:45.266071 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 11:45:45.269626 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 11:45:45.272951 0 12 16 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
2755 11:45:45.279466 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2756 11:45:45.282575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2757 11:45:45.285595 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2758 11:45:45.292444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2759 11:45:45.296256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2760 11:45:45.299182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 11:45:45.302948 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 11:45:45.309158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2763 11:45:45.312733 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2764 11:45:45.316233 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2765 11:45:45.322514 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2766 11:45:45.325639 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 11:45:45.329097 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 11:45:45.335888 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 11:45:45.339024 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 11:45:45.342447 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 11:45:45.349221 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 11:45:45.352383 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 11:45:45.355479 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 11:45:45.362337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 11:45:45.365628 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 11:45:45.369049 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 11:45:45.375813 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 11:45:45.379050 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2779 11:45:45.382563 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2780 11:45:45.385891 Total UI for P1: 0, mck2ui 16
2781 11:45:45.389281 best dqsien dly found for B0: ( 0, 15, 16)
2782 11:45:45.395841 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2783 11:45:45.396368 Total UI for P1: 0, mck2ui 16
2784 11:45:45.399098 best dqsien dly found for B1: ( 0, 15, 20)
2785 11:45:45.405843 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2786 11:45:45.409151 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2787 11:45:45.409793
2788 11:45:45.412301 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2789 11:45:45.415577 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2790 11:45:45.419038 [Gating] SW calibration Done
2791 11:45:45.419619 ==
2792 11:45:45.422404 Dram Type= 6, Freq= 0, CH_0, rank 1
2793 11:45:45.425667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2794 11:45:45.426174 ==
2795 11:45:45.429015 RX Vref Scan: 0
2796 11:45:45.429459
2797 11:45:45.429844 RX Vref 0 -> 0, step: 1
2798 11:45:45.430203
2799 11:45:45.432332 RX Delay -40 -> 252, step: 8
2800 11:45:45.435626 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2801 11:45:45.442653 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2802 11:45:45.445988 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2803 11:45:45.449269 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2804 11:45:45.452473 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2805 11:45:45.455680 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2806 11:45:45.459016 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2807 11:45:45.465783 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2808 11:45:45.469041 iDelay=200, Bit 8, Center 95 (32 ~ 159) 128
2809 11:45:45.472246 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2810 11:45:45.475691 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2811 11:45:45.479162 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2812 11:45:45.485992 iDelay=200, Bit 12, Center 111 (48 ~ 175) 128
2813 11:45:45.489523 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2814 11:45:45.492290 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2815 11:45:45.495665 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2816 11:45:45.496084 ==
2817 11:45:45.499438 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 11:45:45.505732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2819 11:45:45.506285 ==
2820 11:45:45.506742 DQS Delay:
2821 11:45:45.507148 DQS0 = 0, DQS1 = 0
2822 11:45:45.509423 DQM Delay:
2823 11:45:45.510024 DQM0 = 113, DQM1 = 105
2824 11:45:45.512807 DQ Delay:
2825 11:45:45.515697 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =107
2826 11:45:45.519092 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2827 11:45:45.522219 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =99
2828 11:45:45.525575 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =115
2829 11:45:45.525998
2830 11:45:45.526333
2831 11:45:45.526641 ==
2832 11:45:45.528850 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 11:45:45.532435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2834 11:45:45.532897 ==
2835 11:45:45.533233
2836 11:45:45.535683
2837 11:45:45.536101 TX Vref Scan disable
2838 11:45:45.538931 == TX Byte 0 ==
2839 11:45:45.542185 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2840 11:45:45.545910 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2841 11:45:45.549509 == TX Byte 1 ==
2842 11:45:45.552386 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2843 11:45:45.555867 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2844 11:45:45.556342 ==
2845 11:45:45.559050 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 11:45:45.565868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2847 11:45:45.566408 ==
2848 11:45:45.576209 TX Vref=22, minBit 10, minWin=24, winSum=420
2849 11:45:45.579759 TX Vref=24, minBit 8, minWin=25, winSum=425
2850 11:45:45.583218 TX Vref=26, minBit 8, minWin=25, winSum=426
2851 11:45:45.586327 TX Vref=28, minBit 10, minWin=25, winSum=430
2852 11:45:45.589738 TX Vref=30, minBit 8, minWin=26, winSum=435
2853 11:45:45.596544 TX Vref=32, minBit 8, minWin=25, winSum=434
2854 11:45:45.599563 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2855 11:45:45.599984
2856 11:45:45.603171 Final TX Range 1 Vref 30
2857 11:45:45.603596
2858 11:45:45.603930 ==
2859 11:45:45.606682 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 11:45:45.609789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2861 11:45:45.610212 ==
2862 11:45:45.612785
2863 11:45:45.613202
2864 11:45:45.613536 TX Vref Scan disable
2865 11:45:45.616484 == TX Byte 0 ==
2866 11:45:45.619876 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2867 11:45:45.622621 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2868 11:45:45.626261 == TX Byte 1 ==
2869 11:45:45.629612 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2870 11:45:45.632748 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2871 11:45:45.636393
2872 11:45:45.636846 [DATLAT]
2873 11:45:45.637186 Freq=1200, CH0 RK1
2874 11:45:45.637503
2875 11:45:45.639361 DATLAT Default: 0xc
2876 11:45:45.639785 0, 0xFFFF, sum = 0
2877 11:45:45.642835 1, 0xFFFF, sum = 0
2878 11:45:45.643263 2, 0xFFFF, sum = 0
2879 11:45:45.646028 3, 0xFFFF, sum = 0
2880 11:45:45.649849 4, 0xFFFF, sum = 0
2881 11:45:45.650341 5, 0xFFFF, sum = 0
2882 11:45:45.652751 6, 0xFFFF, sum = 0
2883 11:45:45.653244 7, 0xFFFF, sum = 0
2884 11:45:45.656278 8, 0xFFFF, sum = 0
2885 11:45:45.656752 9, 0xFFFF, sum = 0
2886 11:45:45.659366 10, 0xFFFF, sum = 0
2887 11:45:45.659792 11, 0x0, sum = 1
2888 11:45:45.662808 12, 0x0, sum = 2
2889 11:45:45.663236 13, 0x0, sum = 3
2890 11:45:45.666006 14, 0x0, sum = 4
2891 11:45:45.666429 best_step = 12
2892 11:45:45.666765
2893 11:45:45.667078 ==
2894 11:45:45.669515 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:45:45.672781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2896 11:45:45.673227 ==
2897 11:45:45.675914 RX Vref Scan: 0
2898 11:45:45.676403
2899 11:45:45.679300 RX Vref 0 -> 0, step: 1
2900 11:45:45.679721
2901 11:45:45.680050 RX Delay -21 -> 252, step: 4
2902 11:45:45.686868 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
2903 11:45:45.690450 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2904 11:45:45.693279 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2905 11:45:45.697355 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2906 11:45:45.700386 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
2907 11:45:45.706891 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2908 11:45:45.709952 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
2909 11:45:45.713391 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2910 11:45:45.716678 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2911 11:45:45.719897 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2912 11:45:45.726881 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2913 11:45:45.729855 iDelay=195, Bit 11, Center 94 (35 ~ 154) 120
2914 11:45:45.733054 iDelay=195, Bit 12, Center 112 (51 ~ 174) 124
2915 11:45:45.736638 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
2916 11:45:45.740172 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
2917 11:45:45.746434 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2918 11:45:45.746856 ==
2919 11:45:45.750284 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 11:45:45.753452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2921 11:45:45.753875 ==
2922 11:45:45.754213 DQS Delay:
2923 11:45:45.756894 DQS0 = 0, DQS1 = 0
2924 11:45:45.757313 DQM Delay:
2925 11:45:45.759909 DQM0 = 114, DQM1 = 104
2926 11:45:45.760329 DQ Delay:
2927 11:45:45.763308 DQ0 =108, DQ1 =116, DQ2 =112, DQ3 =108
2928 11:45:45.766763 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2929 11:45:45.770200 DQ8 =92, DQ9 =88, DQ10 =108, DQ11 =94
2930 11:45:45.773419 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =114
2931 11:45:45.773837
2932 11:45:45.774169
2933 11:45:45.783452 [DQSOSCAuto] RK1, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2934 11:45:45.786777 CH0 RK1: MR19=404, MR18=1414
2935 11:45:45.790035 CH0_RK1: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
2936 11:45:45.793045 [RxdqsGatingPostProcess] freq 1200
2937 11:45:45.799856 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2938 11:45:45.803023 Pre-setting of DQS Precalculation
2939 11:45:45.806525 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2940 11:45:45.809979 ==
2941 11:45:45.810432 Dram Type= 6, Freq= 0, CH_1, rank 0
2942 11:45:45.816410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2943 11:45:45.816905 ==
2944 11:45:45.819509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2945 11:45:45.826525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2946 11:45:45.835298 [CA 0] Center 37 (7~68) winsize 62
2947 11:45:45.838595 [CA 1] Center 37 (6~68) winsize 63
2948 11:45:45.842141 [CA 2] Center 34 (4~65) winsize 62
2949 11:45:45.845485 [CA 3] Center 33 (3~64) winsize 62
2950 11:45:45.848661 [CA 4] Center 32 (2~63) winsize 62
2951 11:45:45.851923 [CA 5] Center 32 (2~63) winsize 62
2952 11:45:45.852571
2953 11:45:45.855143 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2954 11:45:45.855605
2955 11:45:45.858703 [CATrainingPosCal] consider 1 rank data
2956 11:45:45.861997 u2DelayCellTimex100 = 270/100 ps
2957 11:45:45.865068 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2958 11:45:45.868491 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2959 11:45:45.875121 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2960 11:45:45.878817 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2961 11:45:45.882446 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2962 11:45:45.885344 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2963 11:45:45.885802
2964 11:45:45.888640 CA PerBit enable=1, Macro0, CA PI delay=32
2965 11:45:45.889097
2966 11:45:45.891825 [CBTSetCACLKResult] CA Dly = 32
2967 11:45:45.892287 CS Dly: 6 (0~37)
2968 11:45:45.895198 ==
2969 11:45:45.895823 Dram Type= 6, Freq= 0, CH_1, rank 1
2970 11:45:45.902041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2971 11:45:45.902487 ==
2972 11:45:45.905139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2973 11:45:45.911316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2974 11:45:45.920293 [CA 0] Center 37 (7~68) winsize 62
2975 11:45:45.923385 [CA 1] Center 37 (7~68) winsize 62
2976 11:45:45.927066 [CA 2] Center 33 (3~64) winsize 62
2977 11:45:45.930903 [CA 3] Center 33 (3~64) winsize 62
2978 11:45:45.933715 [CA 4] Center 32 (2~63) winsize 62
2979 11:45:45.936974 [CA 5] Center 32 (1~63) winsize 63
2980 11:45:45.937050
2981 11:45:45.940188 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2982 11:45:45.940265
2983 11:45:45.943432 [CATrainingPosCal] consider 2 rank data
2984 11:45:45.946934 u2DelayCellTimex100 = 270/100 ps
2985 11:45:45.950308 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2986 11:45:45.953556 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2987 11:45:45.960397 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2988 11:45:45.963893 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2989 11:45:45.967666 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2990 11:45:45.970170 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2991 11:45:45.970252
2992 11:45:45.973651 CA PerBit enable=1, Macro0, CA PI delay=32
2993 11:45:45.973739
2994 11:45:45.976713 [CBTSetCACLKResult] CA Dly = 32
2995 11:45:45.976800 CS Dly: 6 (0~38)
2996 11:45:45.976870
2997 11:45:45.979983 ----->DramcWriteLeveling(PI) begin...
2998 11:45:45.983746 ==
2999 11:45:45.986862 Dram Type= 6, Freq= 0, CH_1, rank 0
3000 11:45:45.990300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3001 11:45:45.990411 ==
3002 11:45:45.993597 Write leveling (Byte 0): 20 => 20
3003 11:45:45.997012 Write leveling (Byte 1): 22 => 22
3004 11:45:46.000090 DramcWriteLeveling(PI) end<-----
3005 11:45:46.000226
3006 11:45:46.000332 ==
3007 11:45:46.003519 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 11:45:46.007134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 11:45:46.007292 ==
3010 11:45:46.010344 [Gating] SW mode calibration
3011 11:45:46.016743 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3012 11:45:46.023717 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3013 11:45:46.026940 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3014 11:45:46.030490 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3015 11:45:46.033723 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3016 11:45:46.040580 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3017 11:45:46.043981 0 11 16 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
3018 11:45:46.046847 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3019 11:45:46.053587 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3020 11:45:46.056791 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3021 11:45:46.059928 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3022 11:45:46.066687 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 11:45:46.070281 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 11:45:46.073545 0 12 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3025 11:45:46.080169 0 12 16 | B1->B0 | 3333 4444 | 1 0 | (0 0) (0 0)
3026 11:45:46.083820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3027 11:45:46.086687 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3028 11:45:46.093215 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3029 11:45:46.096555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3030 11:45:46.100407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 11:45:46.106320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 11:45:46.109718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 11:45:46.113283 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3034 11:45:46.119696 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3035 11:45:46.122846 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3036 11:45:46.126098 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3037 11:45:46.133054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 11:45:46.136270 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 11:45:46.139582 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 11:45:46.146345 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 11:45:46.149354 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 11:45:46.153001 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 11:45:46.159333 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 11:45:46.162838 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 11:45:46.165904 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 11:45:46.172677 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 11:45:46.176347 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 11:45:46.179317 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 11:45:46.182777 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3050 11:45:46.189247 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3051 11:45:46.192755 Total UI for P1: 0, mck2ui 16
3052 11:45:46.195851 best dqsien dly found for B0: ( 0, 15, 16)
3053 11:45:46.199478 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3054 11:45:46.202444 Total UI for P1: 0, mck2ui 16
3055 11:45:46.206164 best dqsien dly found for B1: ( 0, 15, 18)
3056 11:45:46.209409 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3057 11:45:46.212436 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3058 11:45:46.212539
3059 11:45:46.215909 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3060 11:45:46.222783 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3061 11:45:46.222864 [Gating] SW calibration Done
3062 11:45:46.222930 ==
3063 11:45:46.225754 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 11:45:46.232528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3065 11:45:46.232626 ==
3066 11:45:46.232692 RX Vref Scan: 0
3067 11:45:46.232752
3068 11:45:46.235662 RX Vref 0 -> 0, step: 1
3069 11:45:46.235743
3070 11:45:46.239113 RX Delay -40 -> 252, step: 8
3071 11:45:46.242392 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3072 11:45:46.245649 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3073 11:45:46.248924 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3074 11:45:46.252713 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3075 11:45:46.259277 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3076 11:45:46.262377 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3077 11:45:46.266102 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3078 11:45:46.269125 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3079 11:45:46.272768 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3080 11:45:46.279540 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3081 11:45:46.282488 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3082 11:45:46.285937 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3083 11:45:46.289205 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3084 11:45:46.292716 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3085 11:45:46.299588 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3086 11:45:46.302590 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3087 11:45:46.302672 ==
3088 11:45:46.305736 Dram Type= 6, Freq= 0, CH_1, rank 0
3089 11:45:46.308997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3090 11:45:46.309079 ==
3091 11:45:46.312332 DQS Delay:
3092 11:45:46.312414 DQS0 = 0, DQS1 = 0
3093 11:45:46.312478 DQM Delay:
3094 11:45:46.315773 DQM0 = 116, DQM1 = 108
3095 11:45:46.315855 DQ Delay:
3096 11:45:46.319410 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3097 11:45:46.322528 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3098 11:45:46.326049 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3099 11:45:46.332805 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3100 11:45:46.332886
3101 11:45:46.332949
3102 11:45:46.333009 ==
3103 11:45:46.335882 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 11:45:46.339216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3105 11:45:46.339299 ==
3106 11:45:46.339364
3107 11:45:46.339423
3108 11:45:46.342477 TX Vref Scan disable
3109 11:45:46.342558 == TX Byte 0 ==
3110 11:45:46.349385 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3111 11:45:46.352411 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3112 11:45:46.352492 == TX Byte 1 ==
3113 11:45:46.359169 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3114 11:45:46.362346 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3115 11:45:46.362429 ==
3116 11:45:46.366175 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 11:45:46.368918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3118 11:45:46.369000 ==
3119 11:45:46.381156 TX Vref=22, minBit 1, minWin=25, winSum=412
3120 11:45:46.384775 TX Vref=24, minBit 8, minWin=25, winSum=417
3121 11:45:46.387905 TX Vref=26, minBit 15, minWin=25, winSum=424
3122 11:45:46.391474 TX Vref=28, minBit 5, minWin=26, winSum=427
3123 11:45:46.394469 TX Vref=30, minBit 1, minWin=26, winSum=430
3124 11:45:46.401407 TX Vref=32, minBit 0, minWin=26, winSum=427
3125 11:45:46.404723 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3126 11:45:46.404805
3127 11:45:46.407890 Final TX Range 1 Vref 30
3128 11:45:46.407972
3129 11:45:46.408037 ==
3130 11:45:46.411214 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 11:45:46.414571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3132 11:45:46.414655 ==
3133 11:45:46.417746
3134 11:45:46.417827
3135 11:45:46.417892 TX Vref Scan disable
3136 11:45:46.421317 == TX Byte 0 ==
3137 11:45:46.425040 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3138 11:45:46.427995 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3139 11:45:46.431358 == TX Byte 1 ==
3140 11:45:46.434599 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3141 11:45:46.438202 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3142 11:45:46.441205
3143 11:45:46.441286 [DATLAT]
3144 11:45:46.441351 Freq=1200, CH1 RK0
3145 11:45:46.441412
3146 11:45:46.444814 DATLAT Default: 0xd
3147 11:45:46.444896 0, 0xFFFF, sum = 0
3148 11:45:46.448280 1, 0xFFFF, sum = 0
3149 11:45:46.448384 2, 0xFFFF, sum = 0
3150 11:45:46.451142 3, 0xFFFF, sum = 0
3151 11:45:46.451225 4, 0xFFFF, sum = 0
3152 11:45:46.454752 5, 0xFFFF, sum = 0
3153 11:45:46.454834 6, 0xFFFF, sum = 0
3154 11:45:46.457813 7, 0xFFFF, sum = 0
3155 11:45:46.461249 8, 0xFFFF, sum = 0
3156 11:45:46.461332 9, 0xFFFF, sum = 0
3157 11:45:46.464484 10, 0xFFFF, sum = 0
3158 11:45:46.464603 11, 0x0, sum = 1
3159 11:45:46.467967 12, 0x0, sum = 2
3160 11:45:46.468050 13, 0x0, sum = 3
3161 11:45:46.468115 14, 0x0, sum = 4
3162 11:45:46.471191 best_step = 12
3163 11:45:46.471272
3164 11:45:46.471337 ==
3165 11:45:46.474618 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 11:45:46.477787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3167 11:45:46.477869 ==
3168 11:45:46.481293 RX Vref Scan: 1
3169 11:45:46.481375
3170 11:45:46.484660 Set Vref Range= 32 -> 127
3171 11:45:46.484742
3172 11:45:46.484807 RX Vref 32 -> 127, step: 1
3173 11:45:46.484867
3174 11:45:46.487957 RX Delay -29 -> 252, step: 4
3175 11:45:46.488038
3176 11:45:46.491038 Set Vref, RX VrefLevel [Byte0]: 32
3177 11:45:46.494657 [Byte1]: 32
3178 11:45:46.498049
3179 11:45:46.498131 Set Vref, RX VrefLevel [Byte0]: 33
3180 11:45:46.501584 [Byte1]: 33
3181 11:45:46.505901
3182 11:45:46.505982 Set Vref, RX VrefLevel [Byte0]: 34
3183 11:45:46.509283 [Byte1]: 34
3184 11:45:46.513987
3185 11:45:46.514095 Set Vref, RX VrefLevel [Byte0]: 35
3186 11:45:46.516958 [Byte1]: 35
3187 11:45:46.521660
3188 11:45:46.521741 Set Vref, RX VrefLevel [Byte0]: 36
3189 11:45:46.525319 [Byte1]: 36
3190 11:45:46.529912
3191 11:45:46.529993 Set Vref, RX VrefLevel [Byte0]: 37
3192 11:45:46.533092 [Byte1]: 37
3193 11:45:46.538270
3194 11:45:46.538355 Set Vref, RX VrefLevel [Byte0]: 38
3195 11:45:46.541108 [Byte1]: 38
3196 11:45:46.545562
3197 11:45:46.545657 Set Vref, RX VrefLevel [Byte0]: 39
3198 11:45:46.548891 [Byte1]: 39
3199 11:45:46.553670
3200 11:45:46.553779 Set Vref, RX VrefLevel [Byte0]: 40
3201 11:45:46.557264 [Byte1]: 40
3202 11:45:46.561398
3203 11:45:46.561478 Set Vref, RX VrefLevel [Byte0]: 41
3204 11:45:46.564797 [Byte1]: 41
3205 11:45:46.569457
3206 11:45:46.569539 Set Vref, RX VrefLevel [Byte0]: 42
3207 11:45:46.573004 [Byte1]: 42
3208 11:45:46.577500
3209 11:45:46.577581 Set Vref, RX VrefLevel [Byte0]: 43
3210 11:45:46.580602 [Byte1]: 43
3211 11:45:46.585302
3212 11:45:46.585384 Set Vref, RX VrefLevel [Byte0]: 44
3213 11:45:46.588669 [Byte1]: 44
3214 11:45:46.593575
3215 11:45:46.593656 Set Vref, RX VrefLevel [Byte0]: 45
3216 11:45:46.596959 [Byte1]: 45
3217 11:45:46.601424
3218 11:45:46.601505 Set Vref, RX VrefLevel [Byte0]: 46
3219 11:45:46.604425 [Byte1]: 46
3220 11:45:46.609312
3221 11:45:46.609393 Set Vref, RX VrefLevel [Byte0]: 47
3222 11:45:46.612641 [Byte1]: 47
3223 11:45:46.617359
3224 11:45:46.617440 Set Vref, RX VrefLevel [Byte0]: 48
3225 11:45:46.620405 [Byte1]: 48
3226 11:45:46.625127
3227 11:45:46.625209 Set Vref, RX VrefLevel [Byte0]: 49
3228 11:45:46.628610 [Byte1]: 49
3229 11:45:46.633177
3230 11:45:46.633287 Set Vref, RX VrefLevel [Byte0]: 50
3231 11:45:46.636438 [Byte1]: 50
3232 11:45:46.641404
3233 11:45:46.641486 Set Vref, RX VrefLevel [Byte0]: 51
3234 11:45:46.644671 [Byte1]: 51
3235 11:45:46.649218
3236 11:45:46.649300 Set Vref, RX VrefLevel [Byte0]: 52
3237 11:45:46.652384 [Byte1]: 52
3238 11:45:46.656947
3239 11:45:46.657028 Set Vref, RX VrefLevel [Byte0]: 53
3240 11:45:46.660646 [Byte1]: 53
3241 11:45:46.664960
3242 11:45:46.665041 Set Vref, RX VrefLevel [Byte0]: 54
3243 11:45:46.668352 [Byte1]: 54
3244 11:45:46.673031
3245 11:45:46.673112 Set Vref, RX VrefLevel [Byte0]: 55
3246 11:45:46.676219 [Byte1]: 55
3247 11:45:46.680854
3248 11:45:46.680935 Set Vref, RX VrefLevel [Byte0]: 56
3249 11:45:46.684367 [Byte1]: 56
3250 11:45:46.688870
3251 11:45:46.688951 Set Vref, RX VrefLevel [Byte0]: 57
3252 11:45:46.692269 [Byte1]: 57
3253 11:45:46.697225
3254 11:45:46.697306 Set Vref, RX VrefLevel [Byte0]: 58
3255 11:45:46.700170 [Byte1]: 58
3256 11:45:46.704686
3257 11:45:46.704767 Set Vref, RX VrefLevel [Byte0]: 59
3258 11:45:46.708478 [Byte1]: 59
3259 11:45:46.712784
3260 11:45:46.712865 Set Vref, RX VrefLevel [Byte0]: 60
3261 11:45:46.716098 [Byte1]: 60
3262 11:45:46.720567
3263 11:45:46.720678 Set Vref, RX VrefLevel [Byte0]: 61
3264 11:45:46.724080 [Byte1]: 61
3265 11:45:46.728593
3266 11:45:46.728666 Set Vref, RX VrefLevel [Byte0]: 62
3267 11:45:46.731942 [Byte1]: 62
3268 11:45:46.736822
3269 11:45:46.736898 Set Vref, RX VrefLevel [Byte0]: 63
3270 11:45:46.739896 [Byte1]: 63
3271 11:45:46.744439
3272 11:45:46.744561 Set Vref, RX VrefLevel [Byte0]: 64
3273 11:45:46.747779 [Byte1]: 64
3274 11:45:46.752331
3275 11:45:46.752433 Set Vref, RX VrefLevel [Byte0]: 65
3276 11:45:46.755758 [Byte1]: 65
3277 11:45:46.760364
3278 11:45:46.760444 Final RX Vref Byte 0 = 53 to rank0
3279 11:45:46.763753 Final RX Vref Byte 1 = 50 to rank0
3280 11:45:46.767454 Final RX Vref Byte 0 = 53 to rank1
3281 11:45:46.770548 Final RX Vref Byte 1 = 50 to rank1==
3282 11:45:46.773912 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 11:45:46.777272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3284 11:45:46.780850 ==
3285 11:45:46.780918 DQS Delay:
3286 11:45:46.780980 DQS0 = 0, DQS1 = 0
3287 11:45:46.783998 DQM Delay:
3288 11:45:46.784094 DQM0 = 115, DQM1 = 105
3289 11:45:46.787579 DQ Delay:
3290 11:45:46.790463 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3291 11:45:46.794100 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3292 11:45:46.797460 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3293 11:45:46.800715 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3294 11:45:46.800786
3295 11:45:46.800852
3296 11:45:46.807069 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3297 11:45:46.810600 CH1 RK0: MR19=404, MR18=1A1A
3298 11:45:46.817020 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3299 11:45:46.817125
3300 11:45:46.820649 ----->DramcWriteLeveling(PI) begin...
3301 11:45:46.820732 ==
3302 11:45:46.823837 Dram Type= 6, Freq= 0, CH_1, rank 1
3303 11:45:46.827078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3304 11:45:46.830471 ==
3305 11:45:46.830544 Write leveling (Byte 0): 22 => 22
3306 11:45:46.833916 Write leveling (Byte 1): 22 => 22
3307 11:45:46.837425 DramcWriteLeveling(PI) end<-----
3308 11:45:46.837526
3309 11:45:46.837618 ==
3310 11:45:46.840327 Dram Type= 6, Freq= 0, CH_1, rank 1
3311 11:45:46.847110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3312 11:45:46.847217 ==
3313 11:45:46.847310 [Gating] SW mode calibration
3314 11:45:46.856983 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3315 11:45:46.860395 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3316 11:45:46.863828 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3317 11:45:46.870876 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3318 11:45:46.873969 0 11 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
3319 11:45:46.876826 0 11 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3320 11:45:46.883600 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3321 11:45:46.887144 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3322 11:45:46.890251 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3323 11:45:46.897180 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3324 11:45:46.900267 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3325 11:45:46.903829 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3326 11:45:46.910155 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3327 11:45:46.913658 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3328 11:45:46.916888 0 12 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3329 11:45:46.923522 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3330 11:45:46.927002 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3331 11:45:46.930347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3332 11:45:46.936879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3333 11:45:46.940074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 11:45:46.943483 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 11:45:46.950299 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3336 11:45:46.953574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3337 11:45:46.956735 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3338 11:45:46.963419 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 11:45:46.966492 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3340 11:45:46.970223 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3341 11:45:46.976469 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 11:45:46.980022 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 11:45:46.983168 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 11:45:46.989775 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 11:45:46.993059 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 11:45:46.996295 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 11:45:47.000030 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 11:45:47.006645 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 11:45:47.010111 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 11:45:47.013601 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 11:45:47.020081 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3352 11:45:47.023186 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3353 11:45:47.026584 Total UI for P1: 0, mck2ui 16
3354 11:45:47.029966 best dqsien dly found for B0: ( 0, 15, 12)
3355 11:45:47.033512 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3356 11:45:47.039904 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3357 11:45:47.039989 Total UI for P1: 0, mck2ui 16
3358 11:45:47.046726 best dqsien dly found for B1: ( 0, 15, 18)
3359 11:45:47.049933 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3360 11:45:47.053378 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3361 11:45:47.053459
3362 11:45:47.056412 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3363 11:45:47.059776 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3364 11:45:47.063483 [Gating] SW calibration Done
3365 11:45:47.063582 ==
3366 11:45:47.066794 Dram Type= 6, Freq= 0, CH_1, rank 1
3367 11:45:47.070184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3368 11:45:47.070282 ==
3369 11:45:47.073333 RX Vref Scan: 0
3370 11:45:47.073406
3371 11:45:47.073468 RX Vref 0 -> 0, step: 1
3372 11:45:47.073527
3373 11:45:47.076383 RX Delay -40 -> 252, step: 8
3374 11:45:47.083312 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3375 11:45:47.086300 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3376 11:45:47.089511 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3377 11:45:47.093084 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3378 11:45:47.096392 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3379 11:45:47.100126 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3380 11:45:47.106187 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3381 11:45:47.109956 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3382 11:45:47.113131 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3383 11:45:47.116417 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3384 11:45:47.119477 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3385 11:45:47.126451 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3386 11:45:47.129668 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3387 11:45:47.132875 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3388 11:45:47.136513 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3389 11:45:47.139704 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3390 11:45:47.143007 ==
3391 11:45:47.143088 Dram Type= 6, Freq= 0, CH_1, rank 1
3392 11:45:47.149480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3393 11:45:47.149562 ==
3394 11:45:47.149627 DQS Delay:
3395 11:45:47.152844 DQS0 = 0, DQS1 = 0
3396 11:45:47.152925 DQM Delay:
3397 11:45:47.156354 DQM0 = 116, DQM1 = 105
3398 11:45:47.156462 DQ Delay:
3399 11:45:47.159729 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3400 11:45:47.163315 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3401 11:45:47.166231 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3402 11:45:47.169891 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3403 11:45:47.169972
3404 11:45:47.170036
3405 11:45:47.170094 ==
3406 11:45:47.173103 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 11:45:47.176396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3408 11:45:47.179495 ==
3409 11:45:47.179576
3410 11:45:47.179639
3411 11:45:47.179699 TX Vref Scan disable
3412 11:45:47.183205 == TX Byte 0 ==
3413 11:45:47.186277 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3414 11:45:47.189449 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3415 11:45:47.192937 == TX Byte 1 ==
3416 11:45:47.196042 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3417 11:45:47.199584 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3418 11:45:47.202752 ==
3419 11:45:47.206207 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 11:45:47.209507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 11:45:47.209589 ==
3422 11:45:47.220461 TX Vref=22, minBit 1, minWin=25, winSum=419
3423 11:45:47.223603 TX Vref=24, minBit 9, minWin=25, winSum=425
3424 11:45:47.227371 TX Vref=26, minBit 0, minWin=26, winSum=428
3425 11:45:47.230192 TX Vref=28, minBit 3, minWin=26, winSum=430
3426 11:45:47.233941 TX Vref=30, minBit 0, minWin=26, winSum=433
3427 11:45:47.236971 TX Vref=32, minBit 0, minWin=26, winSum=427
3428 11:45:47.243647 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
3429 11:45:47.243727
3430 11:45:47.247062 Final TX Range 1 Vref 30
3431 11:45:47.247166
3432 11:45:47.247258 ==
3433 11:45:47.250554 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 11:45:47.253565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3435 11:45:47.253665 ==
3436 11:45:47.253756
3437 11:45:47.257111
3438 11:45:47.257206 TX Vref Scan disable
3439 11:45:47.260649 == TX Byte 0 ==
3440 11:45:47.264028 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3441 11:45:47.266948 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3442 11:45:47.270440 == TX Byte 1 ==
3443 11:45:47.273829 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3444 11:45:47.276964 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3445 11:45:47.277040
3446 11:45:47.280350 [DATLAT]
3447 11:45:47.280431 Freq=1200, CH1 RK1
3448 11:45:47.280545
3449 11:45:47.283547 DATLAT Default: 0xc
3450 11:45:47.283644 0, 0xFFFF, sum = 0
3451 11:45:47.287038 1, 0xFFFF, sum = 0
3452 11:45:47.287138 2, 0xFFFF, sum = 0
3453 11:45:47.290377 3, 0xFFFF, sum = 0
3454 11:45:47.290447 4, 0xFFFF, sum = 0
3455 11:45:47.293798 5, 0xFFFF, sum = 0
3456 11:45:47.293905 6, 0xFFFF, sum = 0
3457 11:45:47.297122 7, 0xFFFF, sum = 0
3458 11:45:47.297194 8, 0xFFFF, sum = 0
3459 11:45:47.300425 9, 0xFFFF, sum = 0
3460 11:45:47.300560 10, 0xFFFF, sum = 0
3461 11:45:47.303874 11, 0x0, sum = 1
3462 11:45:47.303974 12, 0x0, sum = 2
3463 11:45:47.307149 13, 0x0, sum = 3
3464 11:45:47.307220 14, 0x0, sum = 4
3465 11:45:47.310429 best_step = 12
3466 11:45:47.310502
3467 11:45:47.310565 ==
3468 11:45:47.313866 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 11:45:47.317488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3470 11:45:47.317587 ==
3471 11:45:47.320616 RX Vref Scan: 0
3472 11:45:47.320688
3473 11:45:47.320749 RX Vref 0 -> 0, step: 1
3474 11:45:47.320808
3475 11:45:47.323819 RX Delay -29 -> 252, step: 4
3476 11:45:47.330719 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3477 11:45:47.333850 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3478 11:45:47.337448 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3479 11:45:47.340826 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3480 11:45:47.343954 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3481 11:45:47.350714 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3482 11:45:47.353940 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3483 11:45:47.357016 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3484 11:45:47.360393 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3485 11:45:47.364037 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3486 11:45:47.370786 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3487 11:45:47.373956 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3488 11:45:47.377833 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3489 11:45:47.380714 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3490 11:45:47.383934 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3491 11:45:47.390537 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3492 11:45:47.390619 ==
3493 11:45:47.393835 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 11:45:47.397403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3495 11:45:47.397485 ==
3496 11:45:47.397550 DQS Delay:
3497 11:45:47.400685 DQS0 = 0, DQS1 = 0
3498 11:45:47.400767 DQM Delay:
3499 11:45:47.404034 DQM0 = 115, DQM1 = 104
3500 11:45:47.404116 DQ Delay:
3501 11:45:47.407354 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3502 11:45:47.410751 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3503 11:45:47.413824 DQ8 =88, DQ9 =92, DQ10 =110, DQ11 =98
3504 11:45:47.417404 DQ12 =112, DQ13 =114, DQ14 =114, DQ15 =110
3505 11:45:47.417485
3506 11:45:47.417550
3507 11:45:47.427218 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3508 11:45:47.427305 CH1 RK1: MR19=404, MR18=B0B
3509 11:45:47.433847 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3510 11:45:47.437508 [RxdqsGatingPostProcess] freq 1200
3511 11:45:47.443999 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3512 11:45:47.447079 Pre-setting of DQS Precalculation
3513 11:45:47.450645 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3514 11:45:47.457579 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3515 11:45:47.467297 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3516 11:45:47.467400
3517 11:45:47.467497
3518 11:45:47.470519 [Calibration Summary] 2400 Mbps
3519 11:45:47.470618 CH 0, Rank 0
3520 11:45:47.473983 SW Impedance : PASS
3521 11:45:47.474056 DUTY Scan : NO K
3522 11:45:47.477578 ZQ Calibration : PASS
3523 11:45:47.480643 Jitter Meter : NO K
3524 11:45:47.480716 CBT Training : PASS
3525 11:45:47.484310 Write leveling : PASS
3526 11:45:47.484409 RX DQS gating : PASS
3527 11:45:47.487604 RX DQ/DQS(RDDQC) : PASS
3528 11:45:47.490855 TX DQ/DQS : PASS
3529 11:45:47.490927 RX DATLAT : PASS
3530 11:45:47.494377 RX DQ/DQS(Engine): PASS
3531 11:45:47.497390 TX OE : NO K
3532 11:45:47.497466 All Pass.
3533 11:45:47.497535
3534 11:45:47.497595 CH 0, Rank 1
3535 11:45:47.500710 SW Impedance : PASS
3536 11:45:47.503899 DUTY Scan : NO K
3537 11:45:47.503969 ZQ Calibration : PASS
3538 11:45:47.507409 Jitter Meter : NO K
3539 11:45:47.510451 CBT Training : PASS
3540 11:45:47.510549 Write leveling : PASS
3541 11:45:47.514260 RX DQS gating : PASS
3542 11:45:47.517509 RX DQ/DQS(RDDQC) : PASS
3543 11:45:47.517580 TX DQ/DQS : PASS
3544 11:45:47.520661 RX DATLAT : PASS
3545 11:45:47.524078 RX DQ/DQS(Engine): PASS
3546 11:45:47.524151 TX OE : NO K
3547 11:45:47.524212 All Pass.
3548 11:45:47.527476
3549 11:45:47.527545 CH 1, Rank 0
3550 11:45:47.530632 SW Impedance : PASS
3551 11:45:47.530703 DUTY Scan : NO K
3552 11:45:47.533834 ZQ Calibration : PASS
3553 11:45:47.533932 Jitter Meter : NO K
3554 11:45:47.537094 CBT Training : PASS
3555 11:45:47.540541 Write leveling : PASS
3556 11:45:47.540635 RX DQS gating : PASS
3557 11:45:47.544071 RX DQ/DQS(RDDQC) : PASS
3558 11:45:47.547422 TX DQ/DQS : PASS
3559 11:45:47.547527 RX DATLAT : PASS
3560 11:45:47.550836 RX DQ/DQS(Engine): PASS
3561 11:45:47.554079 TX OE : NO K
3562 11:45:47.554156 All Pass.
3563 11:45:47.554219
3564 11:45:47.554280 CH 1, Rank 1
3565 11:45:47.556855 SW Impedance : PASS
3566 11:45:47.560479 DUTY Scan : NO K
3567 11:45:47.560599 ZQ Calibration : PASS
3568 11:45:47.563847 Jitter Meter : NO K
3569 11:45:47.567374 CBT Training : PASS
3570 11:45:47.567449 Write leveling : PASS
3571 11:45:47.570416 RX DQS gating : PASS
3572 11:45:47.573993 RX DQ/DQS(RDDQC) : PASS
3573 11:45:47.574067 TX DQ/DQS : PASS
3574 11:45:47.577133 RX DATLAT : PASS
3575 11:45:47.577234 RX DQ/DQS(Engine): PASS
3576 11:45:47.580313 TX OE : NO K
3577 11:45:47.580422 All Pass.
3578 11:45:47.580543
3579 11:45:47.583661 DramC Write-DBI off
3580 11:45:47.586959 PER_BANK_REFRESH: Hybrid Mode
3581 11:45:47.587061 TX_TRACKING: ON
3582 11:45:47.596931 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3583 11:45:47.600800 [FAST_K] Save calibration result to emmc
3584 11:45:47.603773 dramc_set_vcore_voltage set vcore to 650000
3585 11:45:47.607010 Read voltage for 600, 5
3586 11:45:47.607115 Vio18 = 0
3587 11:45:47.610284 Vcore = 650000
3588 11:45:47.610387 Vdram = 0
3589 11:45:47.610478 Vddq = 0
3590 11:45:47.610567 Vmddr = 0
3591 11:45:47.617049 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3592 11:45:47.620398 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3593 11:45:47.623902 MEM_TYPE=3, freq_sel=19
3594 11:45:47.627232 sv_algorithm_assistance_LP4_1600
3595 11:45:47.630472 ============ PULL DRAM RESETB DOWN ============
3596 11:45:47.637159 ========== PULL DRAM RESETB DOWN end =========
3597 11:45:47.640648 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3598 11:45:47.643641 ===================================
3599 11:45:47.647060 LPDDR4 DRAM CONFIGURATION
3600 11:45:47.650398 ===================================
3601 11:45:47.650476 EX_ROW_EN[0] = 0x0
3602 11:45:47.653762 EX_ROW_EN[1] = 0x0
3603 11:45:47.653865 LP4Y_EN = 0x0
3604 11:45:47.657080 WORK_FSP = 0x0
3605 11:45:47.657180 WL = 0x2
3606 11:45:47.660399 RL = 0x2
3607 11:45:47.660499 BL = 0x2
3608 11:45:47.663632 RPST = 0x0
3609 11:45:47.663707 RD_PRE = 0x0
3610 11:45:47.667104 WR_PRE = 0x1
3611 11:45:47.667180 WR_PST = 0x0
3612 11:45:47.670488 DBI_WR = 0x0
3613 11:45:47.670557 DBI_RD = 0x0
3614 11:45:47.673673 OTF = 0x1
3615 11:45:47.676913 ===================================
3616 11:45:47.680749 ===================================
3617 11:45:47.680820 ANA top config
3618 11:45:47.683860 ===================================
3619 11:45:47.686909 DLL_ASYNC_EN = 0
3620 11:45:47.690509 ALL_SLAVE_EN = 1
3621 11:45:47.693629 NEW_RANK_MODE = 1
3622 11:45:47.693707 DLL_IDLE_MODE = 1
3623 11:45:47.697032 LP45_APHY_COMB_EN = 1
3624 11:45:47.700191 TX_ODT_DIS = 1
3625 11:45:47.703566 NEW_8X_MODE = 1
3626 11:45:47.706756 ===================================
3627 11:45:47.709986 ===================================
3628 11:45:47.713530 data_rate = 1200
3629 11:45:47.716807 CKR = 1
3630 11:45:47.716908 DQ_P2S_RATIO = 8
3631 11:45:47.720366 ===================================
3632 11:45:47.723683 CA_P2S_RATIO = 8
3633 11:45:47.726713 DQ_CA_OPEN = 0
3634 11:45:47.730464 DQ_SEMI_OPEN = 0
3635 11:45:47.733583 CA_SEMI_OPEN = 0
3636 11:45:47.736941 CA_FULL_RATE = 0
3637 11:45:47.737020 DQ_CKDIV4_EN = 1
3638 11:45:47.739842 CA_CKDIV4_EN = 1
3639 11:45:47.743322 CA_PREDIV_EN = 0
3640 11:45:47.746410 PH8_DLY = 0
3641 11:45:47.749979 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3642 11:45:47.753225 DQ_AAMCK_DIV = 4
3643 11:45:47.753329 CA_AAMCK_DIV = 4
3644 11:45:47.756728 CA_ADMCK_DIV = 4
3645 11:45:47.760245 DQ_TRACK_CA_EN = 0
3646 11:45:47.762999 CA_PICK = 600
3647 11:45:47.766246 CA_MCKIO = 600
3648 11:45:47.769953 MCKIO_SEMI = 0
3649 11:45:47.772790 PLL_FREQ = 2288
3650 11:45:47.772872 DQ_UI_PI_RATIO = 32
3651 11:45:47.776318 CA_UI_PI_RATIO = 0
3652 11:45:47.779495 ===================================
3653 11:45:47.782988 ===================================
3654 11:45:47.786491 memory_type:LPDDR4
3655 11:45:47.789638 GP_NUM : 10
3656 11:45:47.789720 SRAM_EN : 1
3657 11:45:47.792903 MD32_EN : 0
3658 11:45:47.795904 ===================================
3659 11:45:47.799450 [ANA_INIT] >>>>>>>>>>>>>>
3660 11:45:47.799532 <<<<<< [CONFIGURE PHASE]: ANA_TX
3661 11:45:47.802736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3662 11:45:47.805851 ===================================
3663 11:45:47.809202 data_rate = 1200,PCW = 0X5800
3664 11:45:47.812471 ===================================
3665 11:45:47.816078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3666 11:45:47.822760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3667 11:45:47.829210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3668 11:45:47.832670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3669 11:45:47.835821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3670 11:45:47.839201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3671 11:45:47.842791 [ANA_INIT] flow start
3672 11:45:47.842903 [ANA_INIT] PLL >>>>>>>>
3673 11:45:47.845791 [ANA_INIT] PLL <<<<<<<<
3674 11:45:47.849407 [ANA_INIT] MIDPI >>>>>>>>
3675 11:45:47.849488 [ANA_INIT] MIDPI <<<<<<<<
3676 11:45:47.852613 [ANA_INIT] DLL >>>>>>>>
3677 11:45:47.855778 [ANA_INIT] flow end
3678 11:45:47.859612 ============ LP4 DIFF to SE enter ============
3679 11:45:47.862449 ============ LP4 DIFF to SE exit ============
3680 11:45:47.865530 [ANA_INIT] <<<<<<<<<<<<<
3681 11:45:47.868875 [Flow] Enable top DCM control >>>>>
3682 11:45:47.872205 [Flow] Enable top DCM control <<<<<
3683 11:45:47.875779 Enable DLL master slave shuffle
3684 11:45:47.882405 ==============================================================
3685 11:45:47.882487 Gating Mode config
3686 11:45:47.888719 ==============================================================
3687 11:45:47.888800 Config description:
3688 11:45:47.898618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3689 11:45:47.905088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3690 11:45:47.912281 SELPH_MODE 0: By rank 1: By Phase
3691 11:45:47.914820 ==============================================================
3692 11:45:47.918329 GAT_TRACK_EN = 1
3693 11:45:47.921845 RX_GATING_MODE = 2
3694 11:45:47.925015 RX_GATING_TRACK_MODE = 2
3695 11:45:47.928117 SELPH_MODE = 1
3696 11:45:47.931437 PICG_EARLY_EN = 1
3697 11:45:47.934833 VALID_LAT_VALUE = 1
3698 11:45:47.941559 ==============================================================
3699 11:45:47.944992 Enter into Gating configuration >>>>
3700 11:45:47.948073 Exit from Gating configuration <<<<
3701 11:45:47.951495 Enter into DVFS_PRE_config >>>>>
3702 11:45:47.961417 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3703 11:45:47.964707 Exit from DVFS_PRE_config <<<<<
3704 11:45:47.968045 Enter into PICG configuration >>>>
3705 11:45:47.971141 Exit from PICG configuration <<<<
3706 11:45:47.974694 [RX_INPUT] configuration >>>>>
3707 11:45:47.974794 [RX_INPUT] configuration <<<<<
3708 11:45:47.981395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3709 11:45:47.987975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3710 11:45:47.991199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3711 11:45:47.997568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3712 11:45:48.004606 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3713 11:45:48.011066 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3714 11:45:48.014128 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3715 11:45:48.017986 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3716 11:45:48.024050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3717 11:45:48.027528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3718 11:45:48.030785 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3719 11:45:48.037552 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3720 11:45:48.040803 ===================================
3721 11:45:48.040886 LPDDR4 DRAM CONFIGURATION
3722 11:45:48.044268 ===================================
3723 11:45:48.047458 EX_ROW_EN[0] = 0x0
3724 11:45:48.047540 EX_ROW_EN[1] = 0x0
3725 11:45:48.050739 LP4Y_EN = 0x0
3726 11:45:48.053809 WORK_FSP = 0x0
3727 11:45:48.053892 WL = 0x2
3728 11:45:48.057447 RL = 0x2
3729 11:45:48.057528 BL = 0x2
3730 11:45:48.060785 RPST = 0x0
3731 11:45:48.060866 RD_PRE = 0x0
3732 11:45:48.063808 WR_PRE = 0x1
3733 11:45:48.063899 WR_PST = 0x0
3734 11:45:48.067200 DBI_WR = 0x0
3735 11:45:48.067282 DBI_RD = 0x0
3736 11:45:48.070288 OTF = 0x1
3737 11:45:48.074254 ===================================
3738 11:45:48.077132 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3739 11:45:48.080398 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3740 11:45:48.087308 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3741 11:45:48.090037 ===================================
3742 11:45:48.090120 LPDDR4 DRAM CONFIGURATION
3743 11:45:48.093304 ===================================
3744 11:45:48.096924 EX_ROW_EN[0] = 0x10
3745 11:45:48.097006 EX_ROW_EN[1] = 0x0
3746 11:45:48.100437 LP4Y_EN = 0x0
3747 11:45:48.103311 WORK_FSP = 0x0
3748 11:45:48.103394 WL = 0x2
3749 11:45:48.106618 RL = 0x2
3750 11:45:48.106701 BL = 0x2
3751 11:45:48.110005 RPST = 0x0
3752 11:45:48.110086 RD_PRE = 0x0
3753 11:45:48.113503 WR_PRE = 0x1
3754 11:45:48.113584 WR_PST = 0x0
3755 11:45:48.116813 DBI_WR = 0x0
3756 11:45:48.116894 DBI_RD = 0x0
3757 11:45:48.120273 OTF = 0x1
3758 11:45:48.123417 ===================================
3759 11:45:48.129653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3760 11:45:48.133361 nWR fixed to 30
3761 11:45:48.133443 [ModeRegInit_LP4] CH0 RK0
3762 11:45:48.136485 [ModeRegInit_LP4] CH0 RK1
3763 11:45:48.139567 [ModeRegInit_LP4] CH1 RK0
3764 11:45:48.139649 [ModeRegInit_LP4] CH1 RK1
3765 11:45:48.143250 match AC timing 16
3766 11:45:48.146725 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3767 11:45:48.153117 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3768 11:45:48.156388 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3769 11:45:48.159777 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3770 11:45:48.166219 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3771 11:45:48.166301 ==
3772 11:45:48.169409 Dram Type= 6, Freq= 0, CH_0, rank 0
3773 11:45:48.172950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3774 11:45:48.173033 ==
3775 11:45:48.179311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3776 11:45:48.185878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3777 11:45:48.189413 [CA 0] Center 36 (6~66) winsize 61
3778 11:45:48.192503 [CA 1] Center 35 (5~66) winsize 62
3779 11:45:48.195916 [CA 2] Center 34 (4~65) winsize 62
3780 11:45:48.199156 [CA 3] Center 34 (4~65) winsize 62
3781 11:45:48.202462 [CA 4] Center 33 (3~64) winsize 62
3782 11:45:48.205770 [CA 5] Center 33 (3~64) winsize 62
3783 11:45:48.205852
3784 11:45:48.209375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3785 11:45:48.209457
3786 11:45:48.212567 [CATrainingPosCal] consider 1 rank data
3787 11:45:48.215669 u2DelayCellTimex100 = 270/100 ps
3788 11:45:48.219103 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3789 11:45:48.222305 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3790 11:45:48.225432 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3791 11:45:48.228733 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3792 11:45:48.232312 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3793 11:45:48.235756 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3794 11:45:48.235838
3795 11:45:48.242052 CA PerBit enable=1, Macro0, CA PI delay=33
3796 11:45:48.242133
3797 11:45:48.245451 [CBTSetCACLKResult] CA Dly = 33
3798 11:45:48.245537 CS Dly: 5 (0~36)
3799 11:45:48.245604 ==
3800 11:45:48.248904 Dram Type= 6, Freq= 0, CH_0, rank 1
3801 11:45:48.252188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3802 11:45:48.252302 ==
3803 11:45:48.258636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3804 11:45:48.265217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3805 11:45:48.268486 [CA 0] Center 35 (5~66) winsize 62
3806 11:45:48.271982 [CA 1] Center 35 (5~66) winsize 62
3807 11:45:48.275135 [CA 2] Center 34 (4~65) winsize 62
3808 11:45:48.278612 [CA 3] Center 34 (3~65) winsize 63
3809 11:45:48.281880 [CA 4] Center 33 (3~64) winsize 62
3810 11:45:48.285237 [CA 5] Center 33 (3~64) winsize 62
3811 11:45:48.285309
3812 11:45:48.288222 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3813 11:45:48.288292
3814 11:45:48.291713 [CATrainingPosCal] consider 2 rank data
3815 11:45:48.294965 u2DelayCellTimex100 = 270/100 ps
3816 11:45:48.298405 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3817 11:45:48.301893 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3818 11:45:48.305140 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3819 11:45:48.308142 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3820 11:45:48.314684 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3821 11:45:48.318017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3822 11:45:48.318089
3823 11:45:48.321581 CA PerBit enable=1, Macro0, CA PI delay=33
3824 11:45:48.321652
3825 11:45:48.324495 [CBTSetCACLKResult] CA Dly = 33
3826 11:45:48.324601 CS Dly: 5 (0~36)
3827 11:45:48.324663
3828 11:45:48.327902 ----->DramcWriteLeveling(PI) begin...
3829 11:45:48.327973 ==
3830 11:45:48.331587 Dram Type= 6, Freq= 0, CH_0, rank 0
3831 11:45:48.337855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3832 11:45:48.337931 ==
3833 11:45:48.341188 Write leveling (Byte 0): 28 => 28
3834 11:45:48.344881 Write leveling (Byte 1): 28 => 28
3835 11:45:48.344962 DramcWriteLeveling(PI) end<-----
3836 11:45:48.345028
3837 11:45:48.348198 ==
3838 11:45:48.351541 Dram Type= 6, Freq= 0, CH_0, rank 0
3839 11:45:48.354427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3840 11:45:48.354528 ==
3841 11:45:48.357979 [Gating] SW mode calibration
3842 11:45:48.364438 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3843 11:45:48.367641 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3844 11:45:48.374391 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3845 11:45:48.377305 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3846 11:45:48.380754 0 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
3847 11:45:48.387507 0 5 12 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
3848 11:45:48.390868 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3849 11:45:48.394138 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3850 11:45:48.400467 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3851 11:45:48.404356 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3852 11:45:48.407557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 11:45:48.414187 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 11:45:48.417422 0 6 8 | B1->B0 | 2727 2e2e | 1 0 | (0 0) (0 0)
3855 11:45:48.420762 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3856 11:45:48.427172 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3857 11:45:48.430393 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3858 11:45:48.433787 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3859 11:45:48.440313 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 11:45:48.443798 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 11:45:48.446949 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 11:45:48.453407 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3863 11:45:48.456769 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3864 11:45:48.460190 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3865 11:45:48.466984 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 11:45:48.470118 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 11:45:48.473876 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 11:45:48.479951 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 11:45:48.483549 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 11:45:48.486655 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 11:45:48.493034 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 11:45:48.496456 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 11:45:48.499855 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 11:45:48.506370 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 11:45:48.509617 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 11:45:48.513183 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 11:45:48.519525 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 11:45:48.523137 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3879 11:45:48.526222 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 11:45:48.529879 Total UI for P1: 0, mck2ui 16
3881 11:45:48.532961 best dqsien dly found for B0: ( 0, 9, 8)
3882 11:45:48.536252 Total UI for P1: 0, mck2ui 16
3883 11:45:48.539373 best dqsien dly found for B1: ( 0, 9, 10)
3884 11:45:48.542540 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3885 11:45:48.546325 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3886 11:45:48.546428
3887 11:45:48.549298 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3888 11:45:48.556009 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3889 11:45:48.556081 [Gating] SW calibration Done
3890 11:45:48.559315 ==
3891 11:45:48.562313 Dram Type= 6, Freq= 0, CH_0, rank 0
3892 11:45:48.565732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3893 11:45:48.565804 ==
3894 11:45:48.565870 RX Vref Scan: 0
3895 11:45:48.565929
3896 11:45:48.568903 RX Vref 0 -> 0, step: 1
3897 11:45:48.568973
3898 11:45:48.572438 RX Delay -230 -> 252, step: 16
3899 11:45:48.575809 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3900 11:45:48.578949 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3901 11:45:48.585565 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3902 11:45:48.588814 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3903 11:45:48.592249 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3904 11:45:48.595519 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3905 11:45:48.601972 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3906 11:45:48.605198 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3907 11:45:48.608683 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3908 11:45:48.612001 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3909 11:45:48.618828 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3910 11:45:48.621857 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3911 11:45:48.625353 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3912 11:45:48.628488 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3913 11:45:48.632212 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3914 11:45:48.638647 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3915 11:45:48.638753 ==
3916 11:45:48.641958 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 11:45:48.645258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3918 11:45:48.645353 ==
3919 11:45:48.645449 DQS Delay:
3920 11:45:48.648379 DQS0 = 0, DQS1 = 0
3921 11:45:48.648478 DQM Delay:
3922 11:45:48.651797 DQM0 = 37, DQM1 = 33
3923 11:45:48.651869 DQ Delay:
3924 11:45:48.655160 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3925 11:45:48.658111 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3926 11:45:48.661434 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3927 11:45:48.665004 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3928 11:45:48.665107
3929 11:45:48.665201
3930 11:45:48.665295 ==
3931 11:45:48.668180 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 11:45:48.674781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3933 11:45:48.674885 ==
3934 11:45:48.674979
3935 11:45:48.675067
3936 11:45:48.675155 TX Vref Scan disable
3937 11:45:48.678320 == TX Byte 0 ==
3938 11:45:48.681611 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3939 11:45:48.688187 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3940 11:45:48.688292 == TX Byte 1 ==
3941 11:45:48.691237 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3942 11:45:48.698302 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3943 11:45:48.698403 ==
3944 11:45:48.701260 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 11:45:48.704416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 11:45:48.704522 ==
3947 11:45:48.704587
3948 11:45:48.704646
3949 11:45:48.708023 TX Vref Scan disable
3950 11:45:48.711366 == TX Byte 0 ==
3951 11:45:48.714466 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3952 11:45:48.717728 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3953 11:45:48.721040 == TX Byte 1 ==
3954 11:45:48.724408 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3955 11:45:48.727771 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3956 11:45:48.727872
3957 11:45:48.727963 [DATLAT]
3958 11:45:48.731204 Freq=600, CH0 RK0
3959 11:45:48.731300
3960 11:45:48.734247 DATLAT Default: 0x9
3961 11:45:48.734315 0, 0xFFFF, sum = 0
3962 11:45:48.737733 1, 0xFFFF, sum = 0
3963 11:45:48.737804 2, 0xFFFF, sum = 0
3964 11:45:48.740915 3, 0xFFFF, sum = 0
3965 11:45:48.740983 4, 0xFFFF, sum = 0
3966 11:45:48.744292 5, 0xFFFF, sum = 0
3967 11:45:48.744400 6, 0xFFFF, sum = 0
3968 11:45:48.747669 7, 0x0, sum = 1
3969 11:45:48.747742 8, 0x0, sum = 2
3970 11:45:48.747805 9, 0x0, sum = 3
3971 11:45:48.750810 10, 0x0, sum = 4
3972 11:45:48.750912 best_step = 8
3973 11:45:48.751001
3974 11:45:48.754221 ==
3975 11:45:48.757404 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 11:45:48.760996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3977 11:45:48.761069 ==
3978 11:45:48.761154 RX Vref Scan: 1
3979 11:45:48.761242
3980 11:45:48.764515 RX Vref 0 -> 0, step: 1
3981 11:45:48.764581
3982 11:45:48.767421 RX Delay -195 -> 252, step: 8
3983 11:45:48.767518
3984 11:45:48.770567 Set Vref, RX VrefLevel [Byte0]: 46
3985 11:45:48.773906 [Byte1]: 45
3986 11:45:48.773974
3987 11:45:48.777200 Final RX Vref Byte 0 = 46 to rank0
3988 11:45:48.780627 Final RX Vref Byte 1 = 45 to rank0
3989 11:45:48.784237 Final RX Vref Byte 0 = 46 to rank1
3990 11:45:48.787458 Final RX Vref Byte 1 = 45 to rank1==
3991 11:45:48.790641 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 11:45:48.793854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3993 11:45:48.797018 ==
3994 11:45:48.797113 DQS Delay:
3995 11:45:48.797227 DQS0 = 0, DQS1 = 0
3996 11:45:48.800669 DQM Delay:
3997 11:45:48.800735 DQM0 = 39, DQM1 = 31
3998 11:45:48.803880 DQ Delay:
3999 11:45:48.803978 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4000 11:45:48.806987 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4001 11:45:48.810841 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4002 11:45:48.813338 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4003 11:45:48.816621
4004 11:45:48.816691
4005 11:45:48.823590 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
4006 11:45:48.826849 CH0 RK0: MR19=808, MR18=4E4E
4007 11:45:48.833226 CH0_RK0: MR19=0x808, MR18=0x4E4E, DQSOSC=395, MR23=63, INC=168, DEC=112
4008 11:45:48.833306
4009 11:45:48.836562 ----->DramcWriteLeveling(PI) begin...
4010 11:45:48.836641 ==
4011 11:45:48.839913 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 11:45:48.843171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4013 11:45:48.843277 ==
4014 11:45:48.846417 Write leveling (Byte 0): 29 => 29
4015 11:45:48.849797 Write leveling (Byte 1): 28 => 28
4016 11:45:48.853432 DramcWriteLeveling(PI) end<-----
4017 11:45:48.853536
4018 11:45:48.853629 ==
4019 11:45:48.856408 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 11:45:48.859947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4021 11:45:48.860048 ==
4022 11:45:48.863548 [Gating] SW mode calibration
4023 11:45:48.869703 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4024 11:45:48.876319 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4025 11:45:48.879574 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 11:45:48.886222 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4027 11:45:48.889617 0 5 8 | B1->B0 | 3131 3232 | 1 1 | (1 1) (1 0)
4028 11:45:48.892871 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4029 11:45:48.899470 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 11:45:48.902633 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 11:45:48.905904 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 11:45:48.912407 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 11:45:48.915938 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 11:45:48.919240 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 11:45:48.926207 0 6 8 | B1->B0 | 2929 3333 | 1 1 | (1 1) (0 0)
4036 11:45:48.929142 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4037 11:45:48.932659 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 11:45:48.939134 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 11:45:48.942350 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 11:45:48.945776 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 11:45:48.948951 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 11:45:48.955880 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4043 11:45:48.959073 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4044 11:45:48.962343 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4045 11:45:48.969039 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 11:45:48.972429 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 11:45:48.975485 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 11:45:48.982407 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 11:45:48.985345 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 11:45:48.988859 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 11:45:48.995500 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 11:45:48.998428 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:45:49.002497 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:45:49.008424 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:45:49.011741 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:45:49.015123 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:45:49.021614 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:45:49.024863 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:45:49.028467 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4060 11:45:49.031746 Total UI for P1: 0, mck2ui 16
4061 11:45:49.035077 best dqsien dly found for B0: ( 0, 9, 6)
4062 11:45:49.041637 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:45:49.044839 Total UI for P1: 0, mck2ui 16
4064 11:45:49.048218 best dqsien dly found for B1: ( 0, 9, 8)
4065 11:45:49.051857 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4066 11:45:49.054594 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4067 11:45:49.054677
4068 11:45:49.057942 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4069 11:45:49.061418 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4070 11:45:49.064680 [Gating] SW calibration Done
4071 11:45:49.064762 ==
4072 11:45:49.068139 Dram Type= 6, Freq= 0, CH_0, rank 1
4073 11:45:49.071020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4074 11:45:49.071103 ==
4075 11:45:49.074728 RX Vref Scan: 0
4076 11:45:49.074810
4077 11:45:49.074876 RX Vref 0 -> 0, step: 1
4078 11:45:49.077876
4079 11:45:49.077990 RX Delay -230 -> 252, step: 16
4080 11:45:49.084745 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4081 11:45:49.087904 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4082 11:45:49.090947 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4083 11:45:49.094488 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4084 11:45:49.101376 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4085 11:45:49.104375 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4086 11:45:49.107663 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4087 11:45:49.110850 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4088 11:45:49.114085 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4089 11:45:49.120723 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4090 11:45:49.123952 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4091 11:45:49.127424 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4092 11:45:49.130960 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4093 11:45:49.137459 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4094 11:45:49.140921 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4095 11:45:49.144205 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4096 11:45:49.144310 ==
4097 11:45:49.147480 Dram Type= 6, Freq= 0, CH_0, rank 1
4098 11:45:49.150879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4099 11:45:49.153975 ==
4100 11:45:49.154088 DQS Delay:
4101 11:45:49.154181 DQS0 = 0, DQS1 = 0
4102 11:45:49.157243 DQM Delay:
4103 11:45:49.157343 DQM0 = 42, DQM1 = 31
4104 11:45:49.161021 DQ Delay:
4105 11:45:49.161095 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4106 11:45:49.163988 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4107 11:45:49.167205 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4108 11:45:49.170606 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4109 11:45:49.170742
4110 11:45:49.173805
4111 11:45:49.173912 ==
4112 11:45:49.177154 Dram Type= 6, Freq= 0, CH_0, rank 1
4113 11:45:49.180378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4114 11:45:49.180514 ==
4115 11:45:49.180626
4116 11:45:49.180719
4117 11:45:49.183736 TX Vref Scan disable
4118 11:45:49.183840 == TX Byte 0 ==
4119 11:45:49.190359 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4120 11:45:49.193873 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4121 11:45:49.193977 == TX Byte 1 ==
4122 11:45:49.200198 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4123 11:45:49.203847 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4124 11:45:49.203992 ==
4125 11:45:49.206732 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 11:45:49.209991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4127 11:45:49.210221 ==
4128 11:45:49.210352
4129 11:45:49.210476
4130 11:45:49.213262 TX Vref Scan disable
4131 11:45:49.216710 == TX Byte 0 ==
4132 11:45:49.219939 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4133 11:45:49.223071 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4134 11:45:49.226601 == TX Byte 1 ==
4135 11:45:49.230230 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4136 11:45:49.233221 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4137 11:45:49.236753
4138 11:45:49.236900 [DATLAT]
4139 11:45:49.237032 Freq=600, CH0 RK1
4140 11:45:49.237161
4141 11:45:49.239852 DATLAT Default: 0x8
4142 11:45:49.239969 0, 0xFFFF, sum = 0
4143 11:45:49.243247 1, 0xFFFF, sum = 0
4144 11:45:49.243384 2, 0xFFFF, sum = 0
4145 11:45:49.246324 3, 0xFFFF, sum = 0
4146 11:45:49.246431 4, 0xFFFF, sum = 0
4147 11:45:49.249611 5, 0xFFFF, sum = 0
4148 11:45:49.252866 6, 0xFFFF, sum = 0
4149 11:45:49.252969 7, 0x0, sum = 1
4150 11:45:49.253065 8, 0x0, sum = 2
4151 11:45:49.256646 9, 0x0, sum = 3
4152 11:45:49.256745 10, 0x0, sum = 4
4153 11:45:49.259465 best_step = 8
4154 11:45:49.259589
4155 11:45:49.259650 ==
4156 11:45:49.263020 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 11:45:49.266343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4158 11:45:49.266442 ==
4159 11:45:49.269774 RX Vref Scan: 0
4160 11:45:49.269877
4161 11:45:49.269975 RX Vref 0 -> 0, step: 1
4162 11:45:49.270075
4163 11:45:49.272682 RX Delay -195 -> 252, step: 8
4164 11:45:49.280319 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4165 11:45:49.283610 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4166 11:45:49.286920 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4167 11:45:49.290202 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4168 11:45:49.296654 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4169 11:45:49.300200 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4170 11:45:49.303296 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4171 11:45:49.306818 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4172 11:45:49.309940 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4173 11:45:49.316678 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4174 11:45:49.320218 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4175 11:45:49.323052 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4176 11:45:49.326332 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4177 11:45:49.332871 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4178 11:45:49.336226 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4179 11:45:49.339464 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4180 11:45:49.339606 ==
4181 11:45:49.343095 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 11:45:49.346461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4183 11:45:49.349949 ==
4184 11:45:49.350088 DQS Delay:
4185 11:45:49.350213 DQS0 = 0, DQS1 = 0
4186 11:45:49.352955 DQM Delay:
4187 11:45:49.353062 DQM0 = 41, DQM1 = 32
4188 11:45:49.356380 DQ Delay:
4189 11:45:49.359694 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4190 11:45:49.359829 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4191 11:45:49.362808 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4192 11:45:49.366355 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4193 11:45:49.369506
4194 11:45:49.369588
4195 11:45:49.375966 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4196 11:45:49.379477 CH0 RK1: MR19=808, MR18=6B6B
4197 11:45:49.386156 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4198 11:45:49.389647 [RxdqsGatingPostProcess] freq 600
4199 11:45:49.392406 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4200 11:45:49.396331 Pre-setting of DQS Precalculation
4201 11:45:49.402618 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4202 11:45:49.402727 ==
4203 11:45:49.405783 Dram Type= 6, Freq= 0, CH_1, rank 0
4204 11:45:49.408949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4205 11:45:49.409056 ==
4206 11:45:49.416000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4207 11:45:49.419410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4208 11:45:49.423285 [CA 0] Center 35 (5~66) winsize 62
4209 11:45:49.426925 [CA 1] Center 35 (4~66) winsize 63
4210 11:45:49.430636 [CA 2] Center 33 (3~64) winsize 62
4211 11:45:49.433402 [CA 3] Center 33 (3~64) winsize 62
4212 11:45:49.436892 [CA 4] Center 33 (2~64) winsize 63
4213 11:45:49.439844 [CA 5] Center 33 (2~64) winsize 63
4214 11:45:49.439952
4215 11:45:49.443482 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4216 11:45:49.443588
4217 11:45:49.446677 [CATrainingPosCal] consider 1 rank data
4218 11:45:49.450273 u2DelayCellTimex100 = 270/100 ps
4219 11:45:49.453360 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4220 11:45:49.460021 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4221 11:45:49.463285 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4222 11:45:49.466481 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4223 11:45:49.470055 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4224 11:45:49.473531 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4225 11:45:49.473649
4226 11:45:49.476658 CA PerBit enable=1, Macro0, CA PI delay=33
4227 11:45:49.476727
4228 11:45:49.480148 [CBTSetCACLKResult] CA Dly = 33
4229 11:45:49.480219 CS Dly: 3 (0~34)
4230 11:45:49.483134 ==
4231 11:45:49.486418 Dram Type= 6, Freq= 0, CH_1, rank 1
4232 11:45:49.489817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4233 11:45:49.489929 ==
4234 11:45:49.492977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4235 11:45:49.499573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4236 11:45:49.504079 [CA 0] Center 35 (5~66) winsize 62
4237 11:45:49.506716 [CA 1] Center 34 (4~65) winsize 62
4238 11:45:49.510534 [CA 2] Center 33 (3~64) winsize 62
4239 11:45:49.513379 [CA 3] Center 33 (3~64) winsize 62
4240 11:45:49.516763 [CA 4] Center 32 (2~63) winsize 62
4241 11:45:49.520601 [CA 5] Center 32 (2~63) winsize 62
4242 11:45:49.520700
4243 11:45:49.523519 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4244 11:45:49.523617
4245 11:45:49.527150 [CATrainingPosCal] consider 2 rank data
4246 11:45:49.529988 u2DelayCellTimex100 = 270/100 ps
4247 11:45:49.533290 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4248 11:45:49.540143 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4249 11:45:49.543478 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4250 11:45:49.546493 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4251 11:45:49.549961 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4252 11:45:49.553069 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4253 11:45:49.553168
4254 11:45:49.556546 CA PerBit enable=1, Macro0, CA PI delay=32
4255 11:45:49.556659
4256 11:45:49.559721 [CBTSetCACLKResult] CA Dly = 32
4257 11:45:49.559846 CS Dly: 4 (0~36)
4258 11:45:49.563183
4259 11:45:49.566543 ----->DramcWriteLeveling(PI) begin...
4260 11:45:49.566655 ==
4261 11:45:49.569780 Dram Type= 6, Freq= 0, CH_1, rank 0
4262 11:45:49.573037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4263 11:45:49.573171 ==
4264 11:45:49.576393 Write leveling (Byte 0): 27 => 27
4265 11:45:49.579921 Write leveling (Byte 1): 28 => 28
4266 11:45:49.583092 DramcWriteLeveling(PI) end<-----
4267 11:45:49.583197
4268 11:45:49.583290 ==
4269 11:45:49.586386 Dram Type= 6, Freq= 0, CH_1, rank 0
4270 11:45:49.590120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4271 11:45:49.590223 ==
4272 11:45:49.593170 [Gating] SW mode calibration
4273 11:45:49.599583 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4274 11:45:49.606289 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4275 11:45:49.609878 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4276 11:45:49.612830 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4277 11:45:49.619863 0 5 8 | B1->B0 | 3030 2a2a | 0 0 | (1 1) (1 1)
4278 11:45:49.623047 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4279 11:45:49.626116 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 11:45:49.632825 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 11:45:49.636032 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 11:45:49.639567 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 11:45:49.646045 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 11:45:49.648972 0 6 4 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
4285 11:45:49.652710 0 6 8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
4286 11:45:49.659270 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 11:45:49.662718 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 11:45:49.666023 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 11:45:49.672354 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 11:45:49.675734 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 11:45:49.678885 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 11:45:49.685548 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 11:45:49.689402 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4294 11:45:49.692415 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4295 11:45:49.695346 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 11:45:49.702258 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 11:45:49.705755 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 11:45:49.709027 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 11:45:49.715204 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 11:45:49.718743 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 11:45:49.722301 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 11:45:49.728565 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 11:45:49.731568 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 11:45:49.735233 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 11:45:49.741636 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 11:45:49.745015 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 11:45:49.748423 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 11:45:49.755085 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 11:45:49.758164 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 11:45:49.761589 Total UI for P1: 0, mck2ui 16
4311 11:45:49.765043 best dqsien dly found for B0: ( 0, 9, 6)
4312 11:45:49.768239 Total UI for P1: 0, mck2ui 16
4313 11:45:49.771458 best dqsien dly found for B1: ( 0, 9, 6)
4314 11:45:49.774860 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4315 11:45:49.778282 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4316 11:45:49.778363
4317 11:45:49.781219 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4318 11:45:49.784616 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4319 11:45:49.787851 [Gating] SW calibration Done
4320 11:45:49.787933 ==
4321 11:45:49.791552 Dram Type= 6, Freq= 0, CH_1, rank 0
4322 11:45:49.798022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4323 11:45:49.798104 ==
4324 11:45:49.798170 RX Vref Scan: 0
4325 11:45:49.798230
4326 11:45:49.801177 RX Vref 0 -> 0, step: 1
4327 11:45:49.801259
4328 11:45:49.804441 RX Delay -230 -> 252, step: 16
4329 11:45:49.807903 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4330 11:45:49.811480 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4331 11:45:49.814750 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4332 11:45:49.821346 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4333 11:45:49.824319 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4334 11:45:49.827598 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4335 11:45:49.831304 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4336 11:45:49.837912 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4337 11:45:49.841047 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4338 11:45:49.844111 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4339 11:45:49.847508 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4340 11:45:49.854003 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4341 11:45:49.857446 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4342 11:45:49.860793 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4343 11:45:49.863942 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4344 11:45:49.870720 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4345 11:45:49.870824 ==
4346 11:45:49.873823 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 11:45:49.877057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4348 11:45:49.877167 ==
4349 11:45:49.877262 DQS Delay:
4350 11:45:49.880486 DQS0 = 0, DQS1 = 0
4351 11:45:49.880610 DQM Delay:
4352 11:45:49.883558 DQM0 = 41, DQM1 = 35
4353 11:45:49.883652 DQ Delay:
4354 11:45:49.887505 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4355 11:45:49.890653 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4356 11:45:49.893607 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4357 11:45:49.896955 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4358 11:45:49.897058
4359 11:45:49.897149
4360 11:45:49.897238 ==
4361 11:45:49.900198 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 11:45:49.903683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4363 11:45:49.903781 ==
4364 11:45:49.903875
4365 11:45:49.907311
4366 11:45:49.907379 TX Vref Scan disable
4367 11:45:49.910339 == TX Byte 0 ==
4368 11:45:49.913315 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4369 11:45:49.916789 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4370 11:45:49.920244 == TX Byte 1 ==
4371 11:45:49.923525 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4372 11:45:49.926628 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4373 11:45:49.926728 ==
4374 11:45:49.930076 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 11:45:49.936860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4376 11:45:49.936938 ==
4377 11:45:49.937004
4378 11:45:49.937064
4379 11:45:49.937122 TX Vref Scan disable
4380 11:45:49.941399 == TX Byte 0 ==
4381 11:45:49.944813 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4382 11:45:49.951370 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4383 11:45:49.951451 == TX Byte 1 ==
4384 11:45:49.954742 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4385 11:45:49.961104 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4386 11:45:49.961185
4387 11:45:49.961250 [DATLAT]
4388 11:45:49.961310 Freq=600, CH1 RK0
4389 11:45:49.961369
4390 11:45:49.964358 DATLAT Default: 0x9
4391 11:45:49.964439 0, 0xFFFF, sum = 0
4392 11:45:49.967663 1, 0xFFFF, sum = 0
4393 11:45:49.967746 2, 0xFFFF, sum = 0
4394 11:45:49.971125 3, 0xFFFF, sum = 0
4395 11:45:49.974502 4, 0xFFFF, sum = 0
4396 11:45:49.974584 5, 0xFFFF, sum = 0
4397 11:45:49.977732 6, 0xFFFF, sum = 0
4398 11:45:49.977814 7, 0x0, sum = 1
4399 11:45:49.977879 8, 0x0, sum = 2
4400 11:45:49.981155 9, 0x0, sum = 3
4401 11:45:49.981237 10, 0x0, sum = 4
4402 11:45:49.984441 best_step = 8
4403 11:45:49.984528
4404 11:45:49.984592 ==
4405 11:45:49.987631 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 11:45:49.990941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4407 11:45:49.991022 ==
4408 11:45:49.994184 RX Vref Scan: 1
4409 11:45:49.994265
4410 11:45:49.994329 RX Vref 0 -> 0, step: 1
4411 11:45:49.994389
4412 11:45:49.997659 RX Delay -195 -> 252, step: 8
4413 11:45:49.997739
4414 11:45:50.001039 Set Vref, RX VrefLevel [Byte0]: 53
4415 11:45:50.004051 [Byte1]: 50
4416 11:45:50.008318
4417 11:45:50.008399 Final RX Vref Byte 0 = 53 to rank0
4418 11:45:50.011859 Final RX Vref Byte 1 = 50 to rank0
4419 11:45:50.015328 Final RX Vref Byte 0 = 53 to rank1
4420 11:45:50.018667 Final RX Vref Byte 1 = 50 to rank1==
4421 11:45:50.021833 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 11:45:50.028233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4423 11:45:50.028314 ==
4424 11:45:50.028378 DQS Delay:
4425 11:45:50.028437 DQS0 = 0, DQS1 = 0
4426 11:45:50.031394 DQM Delay:
4427 11:45:50.031475 DQM0 = 38, DQM1 = 29
4428 11:45:50.034867 DQ Delay:
4429 11:45:50.038104 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4430 11:45:50.041475 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36
4431 11:45:50.041557 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4432 11:45:50.048241 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4433 11:45:50.048324
4434 11:45:50.048389
4435 11:45:50.054793 [DQSOSCAuto] RK0, (LSB)MR18= 0x7b7b, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4436 11:45:50.058232 CH1 RK0: MR19=808, MR18=7B7B
4437 11:45:50.064631 CH1_RK0: MR19=0x808, MR18=0x7B7B, DQSOSC=386, MR23=63, INC=176, DEC=117
4438 11:45:50.064713
4439 11:45:50.067982 ----->DramcWriteLeveling(PI) begin...
4440 11:45:50.068064 ==
4441 11:45:50.071387 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 11:45:50.074572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4443 11:45:50.074653 ==
4444 11:45:50.078162 Write leveling (Byte 0): 27 => 27
4445 11:45:50.081257 Write leveling (Byte 1): 30 => 30
4446 11:45:50.084534 DramcWriteLeveling(PI) end<-----
4447 11:45:50.084615
4448 11:45:50.084679 ==
4449 11:45:50.087996 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 11:45:50.091347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4451 11:45:50.091428 ==
4452 11:45:50.094472 [Gating] SW mode calibration
4453 11:45:50.101548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4454 11:45:50.107708 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4455 11:45:50.111107 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 11:45:50.117614 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
4457 11:45:50.121022 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (1 1)
4458 11:45:50.124248 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 11:45:50.131354 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 11:45:50.134206 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 11:45:50.137447 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 11:45:50.144375 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 11:45:50.147343 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 11:45:50.151047 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4465 11:45:50.157627 0 6 8 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
4466 11:45:50.160894 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 11:45:50.163834 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 11:45:50.167114 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 11:45:50.174312 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 11:45:50.177595 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 11:45:50.180457 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4472 11:45:50.187571 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4473 11:45:50.190890 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4474 11:45:50.193744 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 11:45:50.200441 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 11:45:50.203905 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 11:45:50.207412 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 11:45:50.213958 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 11:45:50.216877 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 11:45:50.220453 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 11:45:50.226828 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 11:45:50.230411 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 11:45:50.233505 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 11:45:50.240109 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 11:45:50.243631 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 11:45:50.246828 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 11:45:50.253317 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:45:50.256974 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4489 11:45:50.259999 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4490 11:45:50.263765 Total UI for P1: 0, mck2ui 16
4491 11:45:50.266627 best dqsien dly found for B0: ( 0, 9, 4)
4492 11:45:50.273207 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 11:45:50.273322 Total UI for P1: 0, mck2ui 16
4494 11:45:50.279859 best dqsien dly found for B1: ( 0, 9, 8)
4495 11:45:50.283479 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4496 11:45:50.286343 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4497 11:45:50.286445
4498 11:45:50.290011 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4499 11:45:50.293028 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4500 11:45:50.296319 [Gating] SW calibration Done
4501 11:45:50.296420 ==
4502 11:45:50.299759 Dram Type= 6, Freq= 0, CH_1, rank 1
4503 11:45:50.303121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4504 11:45:50.303225 ==
4505 11:45:50.306426 RX Vref Scan: 0
4506 11:45:50.306525
4507 11:45:50.306618 RX Vref 0 -> 0, step: 1
4508 11:45:50.306711
4509 11:45:50.309493 RX Delay -230 -> 252, step: 16
4510 11:45:50.316246 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4511 11:45:50.319503 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4512 11:45:50.322976 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4513 11:45:50.326590 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4514 11:45:50.329575 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4515 11:45:50.336480 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4516 11:45:50.339261 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4517 11:45:50.343008 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4518 11:45:50.345892 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4519 11:45:50.352806 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4520 11:45:50.355860 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4521 11:45:50.359190 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4522 11:45:50.362390 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4523 11:45:50.369165 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4524 11:45:50.372318 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4525 11:45:50.375530 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4526 11:45:50.375632 ==
4527 11:45:50.378757 Dram Type= 6, Freq= 0, CH_1, rank 1
4528 11:45:50.382374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4529 11:45:50.382476 ==
4530 11:45:50.385648 DQS Delay:
4531 11:45:50.385720 DQS0 = 0, DQS1 = 0
4532 11:45:50.388862 DQM Delay:
4533 11:45:50.388977 DQM0 = 42, DQM1 = 34
4534 11:45:50.392205 DQ Delay:
4535 11:45:50.392302 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4536 11:45:50.395623 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4537 11:45:50.398664 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4538 11:45:50.402025 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4539 11:45:50.402126
4540 11:45:50.405607
4541 11:45:50.405678 ==
4542 11:45:50.408500 Dram Type= 6, Freq= 0, CH_1, rank 1
4543 11:45:50.412223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4544 11:45:50.412324 ==
4545 11:45:50.412415
4546 11:45:50.412514
4547 11:45:50.415151 TX Vref Scan disable
4548 11:45:50.415248 == TX Byte 0 ==
4549 11:45:50.421839 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4550 11:45:50.425362 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4551 11:45:50.425467 == TX Byte 1 ==
4552 11:45:50.431811 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4553 11:45:50.435515 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4554 11:45:50.435620 ==
4555 11:45:50.438627 Dram Type= 6, Freq= 0, CH_1, rank 1
4556 11:45:50.441702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4557 11:45:50.441804 ==
4558 11:45:50.441896
4559 11:45:50.441984
4560 11:45:50.444977 TX Vref Scan disable
4561 11:45:50.448342 == TX Byte 0 ==
4562 11:45:50.451929 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4563 11:45:50.455456 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4564 11:45:50.458208 == TX Byte 1 ==
4565 11:45:50.461425 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 11:45:50.465000 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 11:45:50.468163
4568 11:45:50.468260 [DATLAT]
4569 11:45:50.468353 Freq=600, CH1 RK1
4570 11:45:50.468446
4571 11:45:50.471475 DATLAT Default: 0x8
4572 11:45:50.471569 0, 0xFFFF, sum = 0
4573 11:45:50.474884 1, 0xFFFF, sum = 0
4574 11:45:50.475030 2, 0xFFFF, sum = 0
4575 11:45:50.478022 3, 0xFFFF, sum = 0
4576 11:45:50.478120 4, 0xFFFF, sum = 0
4577 11:45:50.481357 5, 0xFFFF, sum = 0
4578 11:45:50.484698 6, 0xFFFF, sum = 0
4579 11:45:50.484795 7, 0x0, sum = 1
4580 11:45:50.484889 8, 0x0, sum = 2
4581 11:45:50.488136 9, 0x0, sum = 3
4582 11:45:50.488232 10, 0x0, sum = 4
4583 11:45:50.491480 best_step = 8
4584 11:45:50.491571
4585 11:45:50.491632 ==
4586 11:45:50.494953 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 11:45:50.498126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4588 11:45:50.498222 ==
4589 11:45:50.501100 RX Vref Scan: 0
4590 11:45:50.501200
4591 11:45:50.501259 RX Vref 0 -> 0, step: 1
4592 11:45:50.501316
4593 11:45:50.504390 RX Delay -195 -> 252, step: 8
4594 11:45:50.511692 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4595 11:45:50.515210 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4596 11:45:50.518484 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4597 11:45:50.522250 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4598 11:45:50.528274 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4599 11:45:50.531974 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4600 11:45:50.534711 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4601 11:45:50.538248 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4602 11:45:50.545174 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4603 11:45:50.548282 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4604 11:45:50.551716 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4605 11:45:50.555018 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4606 11:45:50.558197 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4607 11:45:50.564717 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4608 11:45:50.568242 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4609 11:45:50.571799 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4610 11:45:50.571902 ==
4611 11:45:50.574557 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 11:45:50.581413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4613 11:45:50.581516 ==
4614 11:45:50.581620 DQS Delay:
4615 11:45:50.581712 DQS0 = 0, DQS1 = 0
4616 11:45:50.584623 DQM Delay:
4617 11:45:50.584711 DQM0 = 37, DQM1 = 29
4618 11:45:50.587895 DQ Delay:
4619 11:45:50.591511 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4620 11:45:50.591610 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4621 11:45:50.594578 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4622 11:45:50.601121 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4623 11:45:50.601229
4624 11:45:50.601326
4625 11:45:50.607875 [DQSOSCAuto] RK1, (LSB)MR18= 0x5757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4626 11:45:50.611547 CH1 RK1: MR19=808, MR18=5757
4627 11:45:50.617913 CH1_RK1: MR19=0x808, MR18=0x5757, DQSOSC=393, MR23=63, INC=169, DEC=113
4628 11:45:50.620834 [RxdqsGatingPostProcess] freq 600
4629 11:45:50.624270 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4630 11:45:50.627563 Pre-setting of DQS Precalculation
4631 11:45:50.634509 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4632 11:45:50.641089 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4633 11:45:50.647665 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4634 11:45:50.647765
4635 11:45:50.647862
4636 11:45:50.650879 [Calibration Summary] 1200 Mbps
4637 11:45:50.650991 CH 0, Rank 0
4638 11:45:50.654479 SW Impedance : PASS
4639 11:45:50.657478 DUTY Scan : NO K
4640 11:45:50.657583 ZQ Calibration : PASS
4641 11:45:50.661057 Jitter Meter : NO K
4642 11:45:50.664208 CBT Training : PASS
4643 11:45:50.664308 Write leveling : PASS
4644 11:45:50.668065 RX DQS gating : PASS
4645 11:45:50.670740 RX DQ/DQS(RDDQC) : PASS
4646 11:45:50.670840 TX DQ/DQS : PASS
4647 11:45:50.674091 RX DATLAT : PASS
4648 11:45:50.674193 RX DQ/DQS(Engine): PASS
4649 11:45:50.677629 TX OE : NO K
4650 11:45:50.677703 All Pass.
4651 11:45:50.677767
4652 11:45:50.681138 CH 0, Rank 1
4653 11:45:50.681238 SW Impedance : PASS
4654 11:45:50.684128 DUTY Scan : NO K
4655 11:45:50.687370 ZQ Calibration : PASS
4656 11:45:50.687471 Jitter Meter : NO K
4657 11:45:50.690666 CBT Training : PASS
4658 11:45:50.694023 Write leveling : PASS
4659 11:45:50.694122 RX DQS gating : PASS
4660 11:45:50.697678 RX DQ/DQS(RDDQC) : PASS
4661 11:45:50.700636 TX DQ/DQS : PASS
4662 11:45:50.700738 RX DATLAT : PASS
4663 11:45:50.704116 RX DQ/DQS(Engine): PASS
4664 11:45:50.707235 TX OE : NO K
4665 11:45:50.707347 All Pass.
4666 11:45:50.707443
4667 11:45:50.707535 CH 1, Rank 0
4668 11:45:50.710506 SW Impedance : PASS
4669 11:45:50.713859 DUTY Scan : NO K
4670 11:45:50.713942 ZQ Calibration : PASS
4671 11:45:50.717198 Jitter Meter : NO K
4672 11:45:50.720495 CBT Training : PASS
4673 11:45:50.720623 Write leveling : PASS
4674 11:45:50.723776 RX DQS gating : PASS
4675 11:45:50.727293 RX DQ/DQS(RDDQC) : PASS
4676 11:45:50.727376 TX DQ/DQS : PASS
4677 11:45:50.730576 RX DATLAT : PASS
4678 11:45:50.730660 RX DQ/DQS(Engine): PASS
4679 11:45:50.734020 TX OE : NO K
4680 11:45:50.734103 All Pass.
4681 11:45:50.734174
4682 11:45:50.737398 CH 1, Rank 1
4683 11:45:50.737481 SW Impedance : PASS
4684 11:45:50.740706 DUTY Scan : NO K
4685 11:45:50.744086 ZQ Calibration : PASS
4686 11:45:50.744169 Jitter Meter : NO K
4687 11:45:50.747210 CBT Training : PASS
4688 11:45:50.750929 Write leveling : PASS
4689 11:45:50.751037 RX DQS gating : PASS
4690 11:45:50.753955 RX DQ/DQS(RDDQC) : PASS
4691 11:45:50.757345 TX DQ/DQS : PASS
4692 11:45:50.757445 RX DATLAT : PASS
4693 11:45:50.760928 RX DQ/DQS(Engine): PASS
4694 11:45:50.764184 TX OE : NO K
4695 11:45:50.764289 All Pass.
4696 11:45:50.764383
4697 11:45:50.764502 DramC Write-DBI off
4698 11:45:50.767303 PER_BANK_REFRESH: Hybrid Mode
4699 11:45:50.770621 TX_TRACKING: ON
4700 11:45:50.777246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4701 11:45:50.780640 [FAST_K] Save calibration result to emmc
4702 11:45:50.787571 dramc_set_vcore_voltage set vcore to 662500
4703 11:45:50.787693 Read voltage for 933, 3
4704 11:45:50.790635 Vio18 = 0
4705 11:45:50.790737 Vcore = 662500
4706 11:45:50.790828 Vdram = 0
4707 11:45:50.790918 Vddq = 0
4708 11:45:50.793887 Vmddr = 0
4709 11:45:50.797183 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4710 11:45:50.804050 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4711 11:45:50.807348 MEM_TYPE=3, freq_sel=17
4712 11:45:50.807456 sv_algorithm_assistance_LP4_1600
4713 11:45:50.813732 ============ PULL DRAM RESETB DOWN ============
4714 11:45:50.817103 ========== PULL DRAM RESETB DOWN end =========
4715 11:45:50.820410 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4716 11:45:50.823722 ===================================
4717 11:45:50.826794 LPDDR4 DRAM CONFIGURATION
4718 11:45:50.830294 ===================================
4719 11:45:50.833714 EX_ROW_EN[0] = 0x0
4720 11:45:50.833818 EX_ROW_EN[1] = 0x0
4721 11:45:50.836702 LP4Y_EN = 0x0
4722 11:45:50.836805 WORK_FSP = 0x0
4723 11:45:50.840065 WL = 0x3
4724 11:45:50.840172 RL = 0x3
4725 11:45:50.843721 BL = 0x2
4726 11:45:50.843798 RPST = 0x0
4727 11:45:50.846923 RD_PRE = 0x0
4728 11:45:50.847030 WR_PRE = 0x1
4729 11:45:50.850268 WR_PST = 0x0
4730 11:45:50.850375 DBI_WR = 0x0
4731 11:45:50.853586 DBI_RD = 0x0
4732 11:45:50.856521 OTF = 0x1
4733 11:45:50.859926 ===================================
4734 11:45:50.860037 ===================================
4735 11:45:50.863364 ANA top config
4736 11:45:50.866600 ===================================
4737 11:45:50.870075 DLL_ASYNC_EN = 0
4738 11:45:50.870190 ALL_SLAVE_EN = 1
4739 11:45:50.873126 NEW_RANK_MODE = 1
4740 11:45:50.876775 DLL_IDLE_MODE = 1
4741 11:45:50.880075 LP45_APHY_COMB_EN = 1
4742 11:45:50.883237 TX_ODT_DIS = 1
4743 11:45:50.883321 NEW_8X_MODE = 1
4744 11:45:50.886375 ===================================
4745 11:45:50.889752 ===================================
4746 11:45:50.893345 data_rate = 1866
4747 11:45:50.896731 CKR = 1
4748 11:45:50.900031 DQ_P2S_RATIO = 8
4749 11:45:50.903338 ===================================
4750 11:45:50.906333 CA_P2S_RATIO = 8
4751 11:45:50.910070 DQ_CA_OPEN = 0
4752 11:45:50.910183 DQ_SEMI_OPEN = 0
4753 11:45:50.913484 CA_SEMI_OPEN = 0
4754 11:45:50.916329 CA_FULL_RATE = 0
4755 11:45:50.920216 DQ_CKDIV4_EN = 1
4756 11:45:50.923394 CA_CKDIV4_EN = 1
4757 11:45:50.923478 CA_PREDIV_EN = 0
4758 11:45:50.926425 PH8_DLY = 0
4759 11:45:50.930147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4760 11:45:50.933008 DQ_AAMCK_DIV = 4
4761 11:45:50.936804 CA_AAMCK_DIV = 4
4762 11:45:50.939814 CA_ADMCK_DIV = 4
4763 11:45:50.939896 DQ_TRACK_CA_EN = 0
4764 11:45:50.943005 CA_PICK = 933
4765 11:45:50.946585 CA_MCKIO = 933
4766 11:45:50.949795 MCKIO_SEMI = 0
4767 11:45:50.953398 PLL_FREQ = 3732
4768 11:45:50.956313 DQ_UI_PI_RATIO = 32
4769 11:45:50.959662 CA_UI_PI_RATIO = 0
4770 11:45:50.963138 ===================================
4771 11:45:50.966239 ===================================
4772 11:45:50.966324 memory_type:LPDDR4
4773 11:45:50.969444 GP_NUM : 10
4774 11:45:50.972861 SRAM_EN : 1
4775 11:45:50.972944 MD32_EN : 0
4776 11:45:50.976262 ===================================
4777 11:45:50.979372 [ANA_INIT] >>>>>>>>>>>>>>
4778 11:45:50.982875 <<<<<< [CONFIGURE PHASE]: ANA_TX
4779 11:45:50.985995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4780 11:45:50.989444 ===================================
4781 11:45:50.992927 data_rate = 1866,PCW = 0X8f00
4782 11:45:50.996243 ===================================
4783 11:45:50.999369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4784 11:45:51.002887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4785 11:45:51.009857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4786 11:45:51.012840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4787 11:45:51.016194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4788 11:45:51.019364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4789 11:45:51.023260 [ANA_INIT] flow start
4790 11:45:51.026049 [ANA_INIT] PLL >>>>>>>>
4791 11:45:51.026133 [ANA_INIT] PLL <<<<<<<<
4792 11:45:51.029724 [ANA_INIT] MIDPI >>>>>>>>
4793 11:45:51.032868 [ANA_INIT] MIDPI <<<<<<<<
4794 11:45:51.036425 [ANA_INIT] DLL >>>>>>>>
4795 11:45:51.036572 [ANA_INIT] flow end
4796 11:45:51.039219 ============ LP4 DIFF to SE enter ============
4797 11:45:51.045860 ============ LP4 DIFF to SE exit ============
4798 11:45:51.045945 [ANA_INIT] <<<<<<<<<<<<<
4799 11:45:51.049606 [Flow] Enable top DCM control >>>>>
4800 11:45:51.053052 [Flow] Enable top DCM control <<<<<
4801 11:45:51.055966 Enable DLL master slave shuffle
4802 11:45:51.062716 ==============================================================
4803 11:45:51.062824 Gating Mode config
4804 11:45:51.069070 ==============================================================
4805 11:45:51.072180 Config description:
4806 11:45:51.082220 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4807 11:45:51.089114 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4808 11:45:51.092485 SELPH_MODE 0: By rank 1: By Phase
4809 11:45:51.099006 ==============================================================
4810 11:45:51.102116 GAT_TRACK_EN = 1
4811 11:45:51.105424 RX_GATING_MODE = 2
4812 11:45:51.105507 RX_GATING_TRACK_MODE = 2
4813 11:45:51.108897 SELPH_MODE = 1
4814 11:45:51.111950 PICG_EARLY_EN = 1
4815 11:45:51.115497 VALID_LAT_VALUE = 1
4816 11:45:51.122032 ==============================================================
4817 11:45:51.125525 Enter into Gating configuration >>>>
4818 11:45:51.128739 Exit from Gating configuration <<<<
4819 11:45:51.132204 Enter into DVFS_PRE_config >>>>>
4820 11:45:51.141877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4821 11:45:51.145187 Exit from DVFS_PRE_config <<<<<
4822 11:45:51.148781 Enter into PICG configuration >>>>
4823 11:45:51.151714 Exit from PICG configuration <<<<
4824 11:45:51.155184 [RX_INPUT] configuration >>>>>
4825 11:45:51.158247 [RX_INPUT] configuration <<<<<
4826 11:45:51.161880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4827 11:45:51.168109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4828 11:45:51.174968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4829 11:45:51.181309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4830 11:45:51.185057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4831 11:45:51.191346 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4832 11:45:51.198218 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4833 11:45:51.201281 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4834 11:45:51.204530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4835 11:45:51.207873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4836 11:45:51.214616 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4837 11:45:51.217966 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4838 11:45:51.221423 ===================================
4839 11:45:51.224646 LPDDR4 DRAM CONFIGURATION
4840 11:45:51.227768 ===================================
4841 11:45:51.227879 EX_ROW_EN[0] = 0x0
4842 11:45:51.231039 EX_ROW_EN[1] = 0x0
4843 11:45:51.231122 LP4Y_EN = 0x0
4844 11:45:51.234328 WORK_FSP = 0x0
4845 11:45:51.234412 WL = 0x3
4846 11:45:51.237881 RL = 0x3
4847 11:45:51.237965 BL = 0x2
4848 11:45:51.240965 RPST = 0x0
4849 11:45:51.241048 RD_PRE = 0x0
4850 11:45:51.244361 WR_PRE = 0x1
4851 11:45:51.244470 WR_PST = 0x0
4852 11:45:51.247830 DBI_WR = 0x0
4853 11:45:51.251150 DBI_RD = 0x0
4854 11:45:51.251233 OTF = 0x1
4855 11:45:51.254267 ===================================
4856 11:45:51.257398 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4857 11:45:51.261090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4858 11:45:51.267389 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 11:45:51.270885 ===================================
4860 11:45:51.274251 LPDDR4 DRAM CONFIGURATION
4861 11:45:51.277382 ===================================
4862 11:45:51.277466 EX_ROW_EN[0] = 0x10
4863 11:45:51.280645 EX_ROW_EN[1] = 0x0
4864 11:45:51.280728 LP4Y_EN = 0x0
4865 11:45:51.283871 WORK_FSP = 0x0
4866 11:45:51.283958 WL = 0x3
4867 11:45:51.287398 RL = 0x3
4868 11:45:51.287482 BL = 0x2
4869 11:45:51.290761 RPST = 0x0
4870 11:45:51.290844 RD_PRE = 0x0
4871 11:45:51.293917 WR_PRE = 0x1
4872 11:45:51.294000 WR_PST = 0x0
4873 11:45:51.297387 DBI_WR = 0x0
4874 11:45:51.300522 DBI_RD = 0x0
4875 11:45:51.300620 OTF = 0x1
4876 11:45:51.303571 ===================================
4877 11:45:51.310270 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4878 11:45:51.314196 nWR fixed to 30
4879 11:45:51.316948 [ModeRegInit_LP4] CH0 RK0
4880 11:45:51.317031 [ModeRegInit_LP4] CH0 RK1
4881 11:45:51.320451 [ModeRegInit_LP4] CH1 RK0
4882 11:45:51.323814 [ModeRegInit_LP4] CH1 RK1
4883 11:45:51.323897 match AC timing 8
4884 11:45:51.330482 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4885 11:45:51.333573 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4886 11:45:51.337080 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4887 11:45:51.343619 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4888 11:45:51.346989 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4889 11:45:51.347075 ==
4890 11:45:51.350060 Dram Type= 6, Freq= 0, CH_0, rank 0
4891 11:45:51.353753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4892 11:45:51.353838 ==
4893 11:45:51.360130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4894 11:45:51.367132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4895 11:45:51.369951 [CA 0] Center 38 (8~69) winsize 62
4896 11:45:51.373339 [CA 1] Center 38 (8~69) winsize 62
4897 11:45:51.376585 [CA 2] Center 36 (6~67) winsize 62
4898 11:45:51.379965 [CA 3] Center 35 (5~66) winsize 62
4899 11:45:51.383175 [CA 4] Center 34 (4~65) winsize 62
4900 11:45:51.386441 [CA 5] Center 34 (4~64) winsize 61
4901 11:45:51.386553
4902 11:45:51.389627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4903 11:45:51.389748
4904 11:45:51.393609 [CATrainingPosCal] consider 1 rank data
4905 11:45:51.396250 u2DelayCellTimex100 = 270/100 ps
4906 11:45:51.399592 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4907 11:45:51.402973 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4908 11:45:51.406212 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4909 11:45:51.409412 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4910 11:45:51.416228 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4911 11:45:51.419611 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4912 11:45:51.419694
4913 11:45:51.423053 CA PerBit enable=1, Macro0, CA PI delay=34
4914 11:45:51.423167
4915 11:45:51.426175 [CBTSetCACLKResult] CA Dly = 34
4916 11:45:51.426258 CS Dly: 7 (0~38)
4917 11:45:51.426324 ==
4918 11:45:51.429647 Dram Type= 6, Freq= 0, CH_0, rank 1
4919 11:45:51.435956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4920 11:45:51.436041 ==
4921 11:45:51.439232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4922 11:45:51.446049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4923 11:45:51.449080 [CA 0] Center 38 (8~69) winsize 62
4924 11:45:51.452413 [CA 1] Center 38 (8~69) winsize 62
4925 11:45:51.455862 [CA 2] Center 36 (5~67) winsize 63
4926 11:45:51.459598 [CA 3] Center 35 (5~66) winsize 62
4927 11:45:51.462210 [CA 4] Center 34 (4~65) winsize 62
4928 11:45:51.465668 [CA 5] Center 34 (4~65) winsize 62
4929 11:45:51.465778
4930 11:45:51.469020 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4931 11:45:51.469104
4932 11:45:51.472301 [CATrainingPosCal] consider 2 rank data
4933 11:45:51.475665 u2DelayCellTimex100 = 270/100 ps
4934 11:45:51.479215 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4935 11:45:51.482406 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4936 11:45:51.489038 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4937 11:45:51.492358 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4938 11:45:51.495441 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4939 11:45:51.498656 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4940 11:45:51.498742
4941 11:45:51.502192 CA PerBit enable=1, Macro0, CA PI delay=34
4942 11:45:51.502268
4943 11:45:51.505457 [CBTSetCACLKResult] CA Dly = 34
4944 11:45:51.505557 CS Dly: 7 (0~39)
4945 11:45:51.505626
4946 11:45:51.511968 ----->DramcWriteLeveling(PI) begin...
4947 11:45:51.512075 ==
4948 11:45:51.515147 Dram Type= 6, Freq= 0, CH_0, rank 0
4949 11:45:51.518429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4950 11:45:51.518513 ==
4951 11:45:51.521957 Write leveling (Byte 0): 30 => 30
4952 11:45:51.525659 Write leveling (Byte 1): 29 => 29
4953 11:45:51.528633 DramcWriteLeveling(PI) end<-----
4954 11:45:51.528717
4955 11:45:51.528783 ==
4956 11:45:51.531856 Dram Type= 6, Freq= 0, CH_0, rank 0
4957 11:45:51.535129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4958 11:45:51.535230 ==
4959 11:45:51.538537 [Gating] SW mode calibration
4960 11:45:51.544863 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4961 11:45:51.551526 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4962 11:45:51.555054 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4963 11:45:51.558122 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4964 11:45:51.565263 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4965 11:45:51.568372 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 11:45:51.571498 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 11:45:51.578306 0 10 20 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4968 11:45:51.581317 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
4969 11:45:51.584566 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4970 11:45:51.591990 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4971 11:45:51.594388 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4972 11:45:51.598244 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 11:45:51.604483 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 11:45:51.607771 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 11:45:51.611293 0 11 20 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
4976 11:45:51.618005 0 11 24 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
4977 11:45:51.621082 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4978 11:45:51.624368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4979 11:45:51.631069 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4980 11:45:51.634390 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 11:45:51.637943 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 11:45:51.644577 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 11:45:51.647701 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4984 11:45:51.650714 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4985 11:45:51.654328 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4986 11:45:51.660961 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4987 11:45:51.663982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 11:45:51.670969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 11:45:51.674127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 11:45:51.677580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 11:45:51.680440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 11:45:51.687378 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 11:45:51.690693 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 11:45:51.694109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 11:45:51.700526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 11:45:51.703813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 11:45:51.707483 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 11:45:51.713686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 11:45:51.717279 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5000 11:45:51.720183 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 11:45:51.723882 Total UI for P1: 0, mck2ui 16
5002 11:45:51.726870 best dqsien dly found for B0: ( 0, 14, 20)
5003 11:45:51.730253 Total UI for P1: 0, mck2ui 16
5004 11:45:51.733520 best dqsien dly found for B1: ( 0, 14, 20)
5005 11:45:51.737001 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5006 11:45:51.743689 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5007 11:45:51.743772
5008 11:45:51.746865 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5009 11:45:51.749866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5010 11:45:51.753663 [Gating] SW calibration Done
5011 11:45:51.753770 ==
5012 11:45:51.756946 Dram Type= 6, Freq= 0, CH_0, rank 0
5013 11:45:51.760087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5014 11:45:51.760171 ==
5015 11:45:51.763182 RX Vref Scan: 0
5016 11:45:51.763265
5017 11:45:51.763332 RX Vref 0 -> 0, step: 1
5018 11:45:51.763394
5019 11:45:51.766486 RX Delay -80 -> 252, step: 8
5020 11:45:51.769867 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5021 11:45:51.773213 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5022 11:45:51.779893 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5023 11:45:51.783418 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5024 11:45:51.786626 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5025 11:45:51.790308 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5026 11:45:51.793447 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5027 11:45:51.796767 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5028 11:45:51.803775 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5029 11:45:51.806415 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5030 11:45:51.809688 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5031 11:45:51.813118 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5032 11:45:51.816611 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5033 11:45:51.822980 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5034 11:45:51.826427 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5035 11:45:51.829951 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5036 11:45:51.830035 ==
5037 11:45:51.833168 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 11:45:51.836320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5039 11:45:51.836403 ==
5040 11:45:51.839552 DQS Delay:
5041 11:45:51.839635 DQS0 = 0, DQS1 = 0
5042 11:45:51.842881 DQM Delay:
5043 11:45:51.842963 DQM0 = 95, DQM1 = 87
5044 11:45:51.843029 DQ Delay:
5045 11:45:51.846294 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5046 11:45:51.849756 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5047 11:45:51.852668 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5048 11:45:51.856025 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5049 11:45:51.856163
5050 11:45:51.856319
5051 11:45:51.859630 ==
5052 11:45:51.863149 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 11:45:51.865932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5054 11:45:51.866037 ==
5055 11:45:51.866132
5056 11:45:51.866224
5057 11:45:51.869333 TX Vref Scan disable
5058 11:45:51.869419 == TX Byte 0 ==
5059 11:45:51.872566 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5060 11:45:51.879297 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5061 11:45:51.879396 == TX Byte 1 ==
5062 11:45:51.885671 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5063 11:45:51.889216 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5064 11:45:51.889317 ==
5065 11:45:51.892382 Dram Type= 6, Freq= 0, CH_0, rank 0
5066 11:45:51.895591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5067 11:45:51.895690 ==
5068 11:45:51.895757
5069 11:45:51.895819
5070 11:45:51.899049 TX Vref Scan disable
5071 11:45:51.902730 == TX Byte 0 ==
5072 11:45:51.905873 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5073 11:45:51.909243 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5074 11:45:51.912277 == TX Byte 1 ==
5075 11:45:51.916451 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5076 11:45:51.919001 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5077 11:45:51.919086
5078 11:45:51.922324 [DATLAT]
5079 11:45:51.922407 Freq=933, CH0 RK0
5080 11:45:51.922489
5081 11:45:51.926042 DATLAT Default: 0xd
5082 11:45:51.926126 0, 0xFFFF, sum = 0
5083 11:45:51.928955 1, 0xFFFF, sum = 0
5084 11:45:51.929065 2, 0xFFFF, sum = 0
5085 11:45:51.932233 3, 0xFFFF, sum = 0
5086 11:45:51.932344 4, 0xFFFF, sum = 0
5087 11:45:51.935569 5, 0xFFFF, sum = 0
5088 11:45:51.935644 6, 0xFFFF, sum = 0
5089 11:45:51.938994 7, 0xFFFF, sum = 0
5090 11:45:51.939096 8, 0xFFFF, sum = 0
5091 11:45:51.942025 9, 0xFFFF, sum = 0
5092 11:45:51.942129 10, 0x0, sum = 1
5093 11:45:51.945446 11, 0x0, sum = 2
5094 11:45:51.945529 12, 0x0, sum = 3
5095 11:45:51.948969 13, 0x0, sum = 4
5096 11:45:51.949053 best_step = 11
5097 11:45:51.949134
5098 11:45:51.949197 ==
5099 11:45:51.952183 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 11:45:51.955560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5101 11:45:51.959061 ==
5102 11:45:51.959144 RX Vref Scan: 1
5103 11:45:51.959210
5104 11:45:51.962360 RX Vref 0 -> 0, step: 1
5105 11:45:51.962443
5106 11:45:51.965364 RX Delay -61 -> 252, step: 4
5107 11:45:51.965447
5108 11:45:51.968708 Set Vref, RX VrefLevel [Byte0]: 46
5109 11:45:51.968790 [Byte1]: 45
5110 11:45:51.974069
5111 11:45:51.974151 Final RX Vref Byte 0 = 46 to rank0
5112 11:45:51.977522 Final RX Vref Byte 1 = 45 to rank0
5113 11:45:51.980937 Final RX Vref Byte 0 = 46 to rank1
5114 11:45:51.984177 Final RX Vref Byte 1 = 45 to rank1==
5115 11:45:51.987369 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 11:45:51.994003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5117 11:45:51.994086 ==
5118 11:45:51.994152 DQS Delay:
5119 11:45:51.994213 DQS0 = 0, DQS1 = 0
5120 11:45:51.997016 DQM Delay:
5121 11:45:51.997102 DQM0 = 97, DQM1 = 86
5122 11:45:52.000702 DQ Delay:
5123 11:45:52.003570 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =96
5124 11:45:52.007207 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5125 11:45:52.010573 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =80
5126 11:45:52.013904 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5127 11:45:52.013987
5128 11:45:52.014054
5129 11:45:52.020401 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5130 11:45:52.024049 CH0 RK0: MR19=505, MR18=1F1F
5131 11:45:52.030337 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5132 11:45:52.030437
5133 11:45:52.033739 ----->DramcWriteLeveling(PI) begin...
5134 11:45:52.033824 ==
5135 11:45:52.037272 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 11:45:52.040437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5137 11:45:52.040546 ==
5138 11:45:52.043967 Write leveling (Byte 0): 29 => 29
5139 11:45:52.046851 Write leveling (Byte 1): 29 => 29
5140 11:45:52.050227 DramcWriteLeveling(PI) end<-----
5141 11:45:52.050310
5142 11:45:52.050376 ==
5143 11:45:52.053919 Dram Type= 6, Freq= 0, CH_0, rank 1
5144 11:45:52.057253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5145 11:45:52.057337 ==
5146 11:45:52.060498 [Gating] SW mode calibration
5147 11:45:52.066985 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5148 11:45:52.073652 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5149 11:45:52.077009 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 11:45:52.083379 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 11:45:52.086684 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 11:45:52.089966 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 11:45:52.096524 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 11:45:52.099983 0 10 20 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 0)
5155 11:45:52.103301 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5156 11:45:52.109793 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 11:45:52.112973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 11:45:52.116357 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 11:45:52.123101 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 11:45:52.126532 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 11:45:52.129733 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 11:45:52.136261 0 11 20 | B1->B0 | 2b2b 3535 | 0 1 | (1 1) (0 0)
5163 11:45:52.139664 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5164 11:45:52.143130 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 11:45:52.149501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 11:45:52.152903 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 11:45:52.156145 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 11:45:52.163257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 11:45:52.166090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 11:45:52.169222 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 11:45:52.175821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5172 11:45:52.179493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 11:45:52.182381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 11:45:52.189333 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 11:45:52.192490 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 11:45:52.195872 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 11:45:52.202387 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 11:45:52.205617 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 11:45:52.209289 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 11:45:52.212322 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 11:45:52.219007 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 11:45:52.222051 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 11:45:52.228851 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 11:45:52.231951 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:45:52.235269 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:45:52.242156 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5187 11:45:52.245395 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 11:45:52.248790 Total UI for P1: 0, mck2ui 16
5189 11:45:52.251924 best dqsien dly found for B0: ( 0, 14, 20)
5190 11:45:52.255114 Total UI for P1: 0, mck2ui 16
5191 11:45:52.258407 best dqsien dly found for B1: ( 0, 14, 20)
5192 11:45:52.262137 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5193 11:45:52.264987 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5194 11:45:52.265063
5195 11:45:52.268236 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5196 11:45:52.271808 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5197 11:45:52.275402 [Gating] SW calibration Done
5198 11:45:52.275478 ==
5199 11:45:52.278317 Dram Type= 6, Freq= 0, CH_0, rank 1
5200 11:45:52.281839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5201 11:45:52.281909 ==
5202 11:45:52.285042 RX Vref Scan: 0
5203 11:45:52.285113
5204 11:45:52.288148 RX Vref 0 -> 0, step: 1
5205 11:45:52.288238
5206 11:45:52.288299 RX Delay -80 -> 252, step: 8
5207 11:45:52.295056 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5208 11:45:52.298537 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5209 11:45:52.301929 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5210 11:45:52.305244 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5211 11:45:52.308753 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5212 11:45:52.311712 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5213 11:45:52.318189 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5214 11:45:52.321580 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5215 11:45:52.325192 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5216 11:45:52.328170 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5217 11:45:52.331448 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5218 11:45:52.338109 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5219 11:45:52.341610 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5220 11:45:52.344722 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5221 11:45:52.348200 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5222 11:45:52.351624 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5223 11:45:52.351736 ==
5224 11:45:52.354701 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 11:45:52.361163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 11:45:52.361299 ==
5227 11:45:52.361367 DQS Delay:
5228 11:45:52.364443 DQS0 = 0, DQS1 = 0
5229 11:45:52.364525 DQM Delay:
5230 11:45:52.364603 DQM0 = 97, DQM1 = 85
5231 11:45:52.367805 DQ Delay:
5232 11:45:52.371114 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5233 11:45:52.374307 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5234 11:45:52.378077 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5235 11:45:52.381189 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5236 11:45:52.381261
5237 11:45:52.381324
5238 11:45:52.381436 ==
5239 11:45:52.384223 Dram Type= 6, Freq= 0, CH_0, rank 1
5240 11:45:52.388107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5241 11:45:52.388180 ==
5242 11:45:52.388243
5243 11:45:52.388302
5244 11:45:52.391304 TX Vref Scan disable
5245 11:45:52.394412 == TX Byte 0 ==
5246 11:45:52.397867 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5247 11:45:52.400799 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5248 11:45:52.404080 == TX Byte 1 ==
5249 11:45:52.407439 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5250 11:45:52.411191 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5251 11:45:52.411261 ==
5252 11:45:52.414234 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 11:45:52.417643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5254 11:45:52.420729 ==
5255 11:45:52.420797
5256 11:45:52.420864
5257 11:45:52.420924 TX Vref Scan disable
5258 11:45:52.424181 == TX Byte 0 ==
5259 11:45:52.427432 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5260 11:45:52.434186 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5261 11:45:52.434267 == TX Byte 1 ==
5262 11:45:52.437499 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5263 11:45:52.444001 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5264 11:45:52.444076
5265 11:45:52.444138 [DATLAT]
5266 11:45:52.444205 Freq=933, CH0 RK1
5267 11:45:52.444264
5268 11:45:52.447515 DATLAT Default: 0xb
5269 11:45:52.447599 0, 0xFFFF, sum = 0
5270 11:45:52.450682 1, 0xFFFF, sum = 0
5271 11:45:52.454283 2, 0xFFFF, sum = 0
5272 11:45:52.454364 3, 0xFFFF, sum = 0
5273 11:45:52.457111 4, 0xFFFF, sum = 0
5274 11:45:52.457189 5, 0xFFFF, sum = 0
5275 11:45:52.460803 6, 0xFFFF, sum = 0
5276 11:45:52.460887 7, 0xFFFF, sum = 0
5277 11:45:52.463908 8, 0xFFFF, sum = 0
5278 11:45:52.463996 9, 0xFFFF, sum = 0
5279 11:45:52.467202 10, 0x0, sum = 1
5280 11:45:52.467301 11, 0x0, sum = 2
5281 11:45:52.470687 12, 0x0, sum = 3
5282 11:45:52.470786 13, 0x0, sum = 4
5283 11:45:52.470883 best_step = 11
5284 11:45:52.470976
5285 11:45:52.473832 ==
5286 11:45:52.477374 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 11:45:52.480777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5288 11:45:52.480878 ==
5289 11:45:52.480977 RX Vref Scan: 0
5290 11:45:52.481071
5291 11:45:52.484043 RX Vref 0 -> 0, step: 1
5292 11:45:52.484144
5293 11:45:52.487311 RX Delay -69 -> 252, step: 4
5294 11:45:52.490402 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5295 11:45:52.497132 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5296 11:45:52.500104 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5297 11:45:52.503684 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5298 11:45:52.507082 iDelay=199, Bit 4, Center 104 (15 ~ 194) 180
5299 11:45:52.510120 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5300 11:45:52.517162 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5301 11:45:52.520213 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5302 11:45:52.523807 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5303 11:45:52.526800 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5304 11:45:52.530394 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5305 11:45:52.533700 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5306 11:45:52.540237 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5307 11:45:52.543449 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5308 11:45:52.546946 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5309 11:45:52.550148 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5310 11:45:52.550263 ==
5311 11:45:52.553679 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 11:45:52.556803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5313 11:45:52.560271 ==
5314 11:45:52.560369 DQS Delay:
5315 11:45:52.560436 DQS0 = 0, DQS1 = 0
5316 11:45:52.563331 DQM Delay:
5317 11:45:52.563432 DQM0 = 98, DQM1 = 86
5318 11:45:52.566625 DQ Delay:
5319 11:45:52.569989 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5320 11:45:52.573266 DQ4 =104, DQ5 =88, DQ6 =102, DQ7 =108
5321 11:45:52.576704 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5322 11:45:52.579946 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =96
5323 11:45:52.580046
5324 11:45:52.580144
5325 11:45:52.586465 [DQSOSCAuto] RK1, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5326 11:45:52.589816 CH0 RK1: MR19=505, MR18=3131
5327 11:45:52.596696 CH0_RK1: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5328 11:45:52.599743 [RxdqsGatingPostProcess] freq 933
5329 11:45:52.602973 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5330 11:45:52.606245 Pre-setting of DQS Precalculation
5331 11:45:52.613454 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5332 11:45:52.613534 ==
5333 11:45:52.616497 Dram Type= 6, Freq= 0, CH_1, rank 0
5334 11:45:52.619922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5335 11:45:52.619993 ==
5336 11:45:52.626489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5337 11:45:52.632723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5338 11:45:52.635888 [CA 0] Center 37 (6~68) winsize 63
5339 11:45:52.639278 [CA 1] Center 37 (6~68) winsize 63
5340 11:45:52.642751 [CA 2] Center 34 (4~65) winsize 62
5341 11:45:52.645754 [CA 3] Center 34 (4~65) winsize 62
5342 11:45:52.649126 [CA 4] Center 33 (3~63) winsize 61
5343 11:45:52.652785 [CA 5] Center 33 (3~64) winsize 62
5344 11:45:52.652865
5345 11:45:52.655713 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5346 11:45:52.655804
5347 11:45:52.659192 [CATrainingPosCal] consider 1 rank data
5348 11:45:52.663005 u2DelayCellTimex100 = 270/100 ps
5349 11:45:52.666153 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5350 11:45:52.669356 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5351 11:45:52.672517 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5352 11:45:52.676018 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5353 11:45:52.679350 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5354 11:45:52.682856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5355 11:45:52.682929
5356 11:45:52.688982 CA PerBit enable=1, Macro0, CA PI delay=33
5357 11:45:52.689060
5358 11:45:52.689122 [CBTSetCACLKResult] CA Dly = 33
5359 11:45:52.692285 CS Dly: 5 (0~36)
5360 11:45:52.692363 ==
5361 11:45:52.695512 Dram Type= 6, Freq= 0, CH_1, rank 1
5362 11:45:52.698965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5363 11:45:52.699053 ==
5364 11:45:52.705678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5365 11:45:52.712288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5366 11:45:52.715898 [CA 0] Center 37 (6~68) winsize 63
5367 11:45:52.718708 [CA 1] Center 37 (6~68) winsize 63
5368 11:45:52.722756 [CA 2] Center 34 (4~65) winsize 62
5369 11:45:52.725781 [CA 3] Center 34 (4~65) winsize 62
5370 11:45:52.728953 [CA 4] Center 33 (3~63) winsize 61
5371 11:45:52.732218 [CA 5] Center 32 (2~63) winsize 62
5372 11:45:52.732331
5373 11:45:52.735654 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5374 11:45:52.735766
5375 11:45:52.738944 [CATrainingPosCal] consider 2 rank data
5376 11:45:52.742018 u2DelayCellTimex100 = 270/100 ps
5377 11:45:52.745513 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5378 11:45:52.748821 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5379 11:45:52.752086 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5380 11:45:52.755828 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5381 11:45:52.758857 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5382 11:45:52.761932 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5383 11:45:52.762034
5384 11:45:52.768501 CA PerBit enable=1, Macro0, CA PI delay=33
5385 11:45:52.768623
5386 11:45:52.772111 [CBTSetCACLKResult] CA Dly = 33
5387 11:45:52.772189 CS Dly: 5 (0~37)
5388 11:45:52.772252
5389 11:45:52.775521 ----->DramcWriteLeveling(PI) begin...
5390 11:45:52.775593 ==
5391 11:45:52.779000 Dram Type= 6, Freq= 0, CH_1, rank 0
5392 11:45:52.781883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5393 11:45:52.781956 ==
5394 11:45:52.785006 Write leveling (Byte 0): 23 => 23
5395 11:45:52.788481 Write leveling (Byte 1): 24 => 24
5396 11:45:52.791605 DramcWriteLeveling(PI) end<-----
5397 11:45:52.791674
5398 11:45:52.791735 ==
5399 11:45:52.795140 Dram Type= 6, Freq= 0, CH_1, rank 0
5400 11:45:52.801601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5401 11:45:52.801681 ==
5402 11:45:52.801746 [Gating] SW mode calibration
5403 11:45:52.811494 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5404 11:45:52.814908 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5405 11:45:52.821222 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 11:45:52.824744 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 11:45:52.828035 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 11:45:52.831642 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 11:45:52.838435 0 10 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5410 11:45:52.841440 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
5411 11:45:52.844527 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5412 11:45:52.851567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5413 11:45:52.854762 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 11:45:52.858010 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 11:45:52.864885 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 11:45:52.867890 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 11:45:52.871478 0 11 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5418 11:45:52.877871 0 11 20 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
5419 11:45:52.881158 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5420 11:45:52.884339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 11:45:52.891048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 11:45:52.894507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 11:45:52.897915 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 11:45:52.904188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 11:45:52.907869 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5426 11:45:52.910968 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 11:45:52.917973 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 11:45:52.920784 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 11:45:52.924164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 11:45:52.930745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 11:45:52.934172 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 11:45:52.937768 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 11:45:52.944384 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 11:45:52.948014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 11:45:52.950768 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 11:45:52.957467 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 11:45:52.960836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 11:45:52.964395 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 11:45:52.971259 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 11:45:52.974585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 11:45:52.977598 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5442 11:45:52.980742 Total UI for P1: 0, mck2ui 16
5443 11:45:52.984160 best dqsien dly found for B0: ( 0, 14, 14)
5444 11:45:52.987180 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5445 11:45:52.994352 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 11:45:52.997339 Total UI for P1: 0, mck2ui 16
5447 11:45:53.000344 best dqsien dly found for B1: ( 0, 14, 18)
5448 11:45:53.004181 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5449 11:45:53.007104 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5450 11:45:53.007206
5451 11:45:53.010885 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5452 11:45:53.013853 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5453 11:45:53.017098 [Gating] SW calibration Done
5454 11:45:53.017168 ==
5455 11:45:53.020820 Dram Type= 6, Freq= 0, CH_1, rank 0
5456 11:45:53.023851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5457 11:45:53.023947 ==
5458 11:45:53.026907 RX Vref Scan: 0
5459 11:45:53.026976
5460 11:45:53.030530 RX Vref 0 -> 0, step: 1
5461 11:45:53.030649
5462 11:45:53.030759 RX Delay -80 -> 252, step: 8
5463 11:45:53.036999 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5464 11:45:53.040416 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5465 11:45:53.043550 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5466 11:45:53.047210 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5467 11:45:53.050346 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5468 11:45:53.057214 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5469 11:45:53.060221 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5470 11:45:53.063477 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5471 11:45:53.066820 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5472 11:45:53.070120 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5473 11:45:53.076767 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5474 11:45:53.080076 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5475 11:45:53.083260 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5476 11:45:53.086567 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5477 11:45:53.090055 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5478 11:45:53.093195 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5479 11:45:53.096571 ==
5480 11:45:53.099682 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 11:45:53.103131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5482 11:45:53.103238 ==
5483 11:45:53.103332 DQS Delay:
5484 11:45:53.106445 DQS0 = 0, DQS1 = 0
5485 11:45:53.106544 DQM Delay:
5486 11:45:53.109999 DQM0 = 94, DQM1 = 87
5487 11:45:53.110071 DQ Delay:
5488 11:45:53.113362 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5489 11:45:53.116475 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5490 11:45:53.119985 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5491 11:45:53.123092 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5492 11:45:53.123191
5493 11:45:53.123282
5494 11:45:53.123409 ==
5495 11:45:53.126620 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 11:45:53.129836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5497 11:45:53.129913 ==
5498 11:45:53.130000
5499 11:45:53.130093
5500 11:45:53.133128 TX Vref Scan disable
5501 11:45:53.136799 == TX Byte 0 ==
5502 11:45:53.139741 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5503 11:45:53.143186 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5504 11:45:53.146360 == TX Byte 1 ==
5505 11:45:53.149877 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5506 11:45:53.152990 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5507 11:45:53.153077 ==
5508 11:45:53.156294 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 11:45:53.159783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5510 11:45:53.163055 ==
5511 11:45:53.163155
5512 11:45:53.163254
5513 11:45:53.163358 TX Vref Scan disable
5514 11:45:53.166938 == TX Byte 0 ==
5515 11:45:53.170374 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5516 11:45:53.176687 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5517 11:45:53.176785 == TX Byte 1 ==
5518 11:45:53.180354 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5519 11:45:53.183578 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5520 11:45:53.186787
5521 11:45:53.186885 [DATLAT]
5522 11:45:53.186982 Freq=933, CH1 RK0
5523 11:45:53.187075
5524 11:45:53.190192 DATLAT Default: 0xd
5525 11:45:53.190301 0, 0xFFFF, sum = 0
5526 11:45:53.193546 1, 0xFFFF, sum = 0
5527 11:45:53.193647 2, 0xFFFF, sum = 0
5528 11:45:53.196807 3, 0xFFFF, sum = 0
5529 11:45:53.196908 4, 0xFFFF, sum = 0
5530 11:45:53.200218 5, 0xFFFF, sum = 0
5531 11:45:53.203311 6, 0xFFFF, sum = 0
5532 11:45:53.203413 7, 0xFFFF, sum = 0
5533 11:45:53.207099 8, 0xFFFF, sum = 0
5534 11:45:53.207201 9, 0xFFFF, sum = 0
5535 11:45:53.209820 10, 0x0, sum = 1
5536 11:45:53.209905 11, 0x0, sum = 2
5537 11:45:53.210022 12, 0x0, sum = 3
5538 11:45:53.213749 13, 0x0, sum = 4
5539 11:45:53.213851 best_step = 11
5540 11:45:53.213951
5541 11:45:53.216628 ==
5542 11:45:53.220215 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 11:45:53.223147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5544 11:45:53.223264 ==
5545 11:45:53.223363 RX Vref Scan: 1
5546 11:45:53.223458
5547 11:45:53.226672 RX Vref 0 -> 0, step: 1
5548 11:45:53.226774
5549 11:45:53.229736 RX Delay -69 -> 252, step: 4
5550 11:45:53.229836
5551 11:45:53.233234 Set Vref, RX VrefLevel [Byte0]: 53
5552 11:45:53.236849 [Byte1]: 50
5553 11:45:53.236932
5554 11:45:53.239576 Final RX Vref Byte 0 = 53 to rank0
5555 11:45:53.243148 Final RX Vref Byte 1 = 50 to rank0
5556 11:45:53.246501 Final RX Vref Byte 0 = 53 to rank1
5557 11:45:53.249522 Final RX Vref Byte 1 = 50 to rank1==
5558 11:45:53.252821 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 11:45:53.256238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5560 11:45:53.259593 ==
5561 11:45:53.259676 DQS Delay:
5562 11:45:53.259742 DQS0 = 0, DQS1 = 0
5563 11:45:53.262782 DQM Delay:
5564 11:45:53.262866 DQM0 = 94, DQM1 = 88
5565 11:45:53.266318 DQ Delay:
5566 11:45:53.266401 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5567 11:45:53.269313 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5568 11:45:53.272617 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5569 11:45:53.279409 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5570 11:45:53.279492
5571 11:45:53.279557
5572 11:45:53.285822 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5573 11:45:53.289126 CH1 RK0: MR19=505, MR18=2F2F
5574 11:45:53.296033 CH1_RK0: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5575 11:45:53.296116
5576 11:45:53.299058 ----->DramcWriteLeveling(PI) begin...
5577 11:45:53.299142 ==
5578 11:45:53.302762 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 11:45:53.306129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5580 11:45:53.306214 ==
5581 11:45:53.309319 Write leveling (Byte 0): 26 => 26
5582 11:45:53.312416 Write leveling (Byte 1): 26 => 26
5583 11:45:53.315568 DramcWriteLeveling(PI) end<-----
5584 11:45:53.315644
5585 11:45:53.315708 ==
5586 11:45:53.319072 Dram Type= 6, Freq= 0, CH_1, rank 1
5587 11:45:53.322245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5588 11:45:53.322347 ==
5589 11:45:53.326021 [Gating] SW mode calibration
5590 11:45:53.332117 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 11:45:53.338741 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5592 11:45:53.342251 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 11:45:53.348629 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 11:45:53.352128 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 11:45:53.355420 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5596 11:45:53.361726 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
5597 11:45:53.364916 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5598 11:45:53.368314 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 11:45:53.375201 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 11:45:53.378347 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 11:45:53.381630 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 11:45:53.388480 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 11:45:53.391849 0 11 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5604 11:45:53.395098 0 11 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
5605 11:45:53.398450 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5606 11:45:53.405081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:45:53.408383 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 11:45:53.411706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 11:45:53.418237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 11:45:53.421624 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 11:45:53.424798 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5612 11:45:53.431474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5613 11:45:53.434809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:45:53.438042 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5615 11:45:53.445227 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:45:53.448101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:45:53.451604 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:45:53.458535 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:45:53.461652 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:45:53.464904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:45:53.471412 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:45:53.474844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:45:53.477687 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:45:53.484464 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:45:53.487943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:45:53.491011 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 11:45:53.497558 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 11:45:53.500971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5629 11:45:53.504226 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 11:45:53.507773 Total UI for P1: 0, mck2ui 16
5631 11:45:53.511056 best dqsien dly found for B0: ( 0, 14, 16)
5632 11:45:53.514356 Total UI for P1: 0, mck2ui 16
5633 11:45:53.517499 best dqsien dly found for B1: ( 0, 14, 18)
5634 11:45:53.521119 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5635 11:45:53.524314 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5636 11:45:53.527246
5637 11:45:53.530663 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5638 11:45:53.534223 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5639 11:45:53.537508 [Gating] SW calibration Done
5640 11:45:53.537592 ==
5641 11:45:53.540715 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 11:45:53.543892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 11:45:53.543975 ==
5644 11:45:53.544042 RX Vref Scan: 0
5645 11:45:53.544103
5646 11:45:53.547200 RX Vref 0 -> 0, step: 1
5647 11:45:53.547285
5648 11:45:53.550616 RX Delay -80 -> 252, step: 8
5649 11:45:53.554153 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5650 11:45:53.557475 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5651 11:45:53.563841 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5652 11:45:53.567134 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5653 11:45:53.570792 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5654 11:45:53.573928 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5655 11:45:53.577565 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5656 11:45:53.580467 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5657 11:45:53.587456 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5658 11:45:53.590439 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5659 11:45:53.593784 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5660 11:45:53.597033 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5661 11:45:53.600840 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5662 11:45:53.607315 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5663 11:45:53.610418 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5664 11:45:53.614050 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5665 11:45:53.614132 ==
5666 11:45:53.617007 Dram Type= 6, Freq= 0, CH_1, rank 1
5667 11:45:53.620133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5668 11:45:53.620230 ==
5669 11:45:53.623586 DQS Delay:
5670 11:45:53.623668 DQS0 = 0, DQS1 = 0
5671 11:45:53.623770 DQM Delay:
5672 11:45:53.626937 DQM0 = 95, DQM1 = 86
5673 11:45:53.627019 DQ Delay:
5674 11:45:53.630385 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5675 11:45:53.633619 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5676 11:45:53.636926 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5677 11:45:53.640153 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =91
5678 11:45:53.640240
5679 11:45:53.640349
5680 11:45:53.640460 ==
5681 11:45:53.643534 Dram Type= 6, Freq= 0, CH_1, rank 1
5682 11:45:53.650086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5683 11:45:53.650169 ==
5684 11:45:53.650235
5685 11:45:53.650299
5686 11:45:53.653267 TX Vref Scan disable
5687 11:45:53.653350 == TX Byte 0 ==
5688 11:45:53.656599 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 11:45:53.663176 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 11:45:53.663259 == TX Byte 1 ==
5691 11:45:53.666468 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5692 11:45:53.672943 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5693 11:45:53.673075 ==
5694 11:45:53.676409 Dram Type= 6, Freq= 0, CH_1, rank 1
5695 11:45:53.679568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5696 11:45:53.679651 ==
5697 11:45:53.679717
5698 11:45:53.679788
5699 11:45:53.682964 TX Vref Scan disable
5700 11:45:53.686248 == TX Byte 0 ==
5701 11:45:53.689786 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 11:45:53.692982 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 11:45:53.696408 == TX Byte 1 ==
5704 11:45:53.699989 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5705 11:45:53.703184 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5706 11:45:53.703269
5707 11:45:53.706580 [DATLAT]
5708 11:45:53.706662 Freq=933, CH1 RK1
5709 11:45:53.706728
5710 11:45:53.709448 DATLAT Default: 0xb
5711 11:45:53.709531 0, 0xFFFF, sum = 0
5712 11:45:53.713056 1, 0xFFFF, sum = 0
5713 11:45:53.713156 2, 0xFFFF, sum = 0
5714 11:45:53.716328 3, 0xFFFF, sum = 0
5715 11:45:53.716440 4, 0xFFFF, sum = 0
5716 11:45:53.719388 5, 0xFFFF, sum = 0
5717 11:45:53.719506 6, 0xFFFF, sum = 0
5718 11:45:53.723208 7, 0xFFFF, sum = 0
5719 11:45:53.723308 8, 0xFFFF, sum = 0
5720 11:45:53.726297 9, 0xFFFF, sum = 0
5721 11:45:53.726382 10, 0x0, sum = 1
5722 11:45:53.729606 11, 0x0, sum = 2
5723 11:45:53.729691 12, 0x0, sum = 3
5724 11:45:53.733039 13, 0x0, sum = 4
5725 11:45:53.733147 best_step = 11
5726 11:45:53.733240
5727 11:45:53.733331 ==
5728 11:45:53.736212 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 11:45:53.739352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5730 11:45:53.742669 ==
5731 11:45:53.742744 RX Vref Scan: 0
5732 11:45:53.742845
5733 11:45:53.746125 RX Vref 0 -> 0, step: 1
5734 11:45:53.746205
5735 11:45:53.749386 RX Delay -69 -> 252, step: 4
5736 11:45:53.752771 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5737 11:45:53.755968 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5738 11:45:53.762755 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5739 11:45:53.766069 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5740 11:45:53.769219 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5741 11:45:53.772881 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5742 11:45:53.776260 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5743 11:45:53.779511 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5744 11:45:53.785788 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5745 11:45:53.789222 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5746 11:45:53.792653 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5747 11:45:53.795896 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5748 11:45:53.798866 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5749 11:45:53.802273 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5750 11:45:53.808968 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5751 11:45:53.812178 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5752 11:45:53.812262 ==
5753 11:45:53.815567 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 11:45:53.818888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5755 11:45:53.818980 ==
5756 11:45:53.822125 DQS Delay:
5757 11:45:53.822225 DQS0 = 0, DQS1 = 0
5758 11:45:53.822329 DQM Delay:
5759 11:45:53.825449 DQM0 = 96, DQM1 = 87
5760 11:45:53.825522 DQ Delay:
5761 11:45:53.828952 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94
5762 11:45:53.832217 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5763 11:45:53.835383 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5764 11:45:53.838857 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =94
5765 11:45:53.838935
5766 11:45:53.838999
5767 11:45:53.849110 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5768 11:45:53.851949 CH1 RK1: MR19=505, MR18=1E1E
5769 11:45:53.855098 CH1_RK1: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5770 11:45:53.858897 [RxdqsGatingPostProcess] freq 933
5771 11:45:53.865254 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5772 11:45:53.868741 Pre-setting of DQS Precalculation
5773 11:45:53.871832 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5774 11:45:53.882146 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5775 11:45:53.888958 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5776 11:45:53.889036
5777 11:45:53.889101
5778 11:45:53.892061 [Calibration Summary] 1866 Mbps
5779 11:45:53.892135 CH 0, Rank 0
5780 11:45:53.895090 SW Impedance : PASS
5781 11:45:53.895163 DUTY Scan : NO K
5782 11:45:53.898621 ZQ Calibration : PASS
5783 11:45:53.901935 Jitter Meter : NO K
5784 11:45:53.902007 CBT Training : PASS
5785 11:45:53.904998 Write leveling : PASS
5786 11:45:53.908269 RX DQS gating : PASS
5787 11:45:53.908345 RX DQ/DQS(RDDQC) : PASS
5788 11:45:53.911615 TX DQ/DQS : PASS
5789 11:45:53.915227 RX DATLAT : PASS
5790 11:45:53.915315 RX DQ/DQS(Engine): PASS
5791 11:45:53.918446 TX OE : NO K
5792 11:45:53.918519 All Pass.
5793 11:45:53.918582
5794 11:45:53.921593 CH 0, Rank 1
5795 11:45:53.921665 SW Impedance : PASS
5796 11:45:53.925065 DUTY Scan : NO K
5797 11:45:53.928104 ZQ Calibration : PASS
5798 11:45:53.928213 Jitter Meter : NO K
5799 11:45:53.931917 CBT Training : PASS
5800 11:45:53.932020 Write leveling : PASS
5801 11:45:53.934679 RX DQS gating : PASS
5802 11:45:53.938161 RX DQ/DQS(RDDQC) : PASS
5803 11:45:53.938234 TX DQ/DQS : PASS
5804 11:45:53.941572 RX DATLAT : PASS
5805 11:45:53.944634 RX DQ/DQS(Engine): PASS
5806 11:45:53.944747 TX OE : NO K
5807 11:45:53.948019 All Pass.
5808 11:45:53.948118
5809 11:45:53.948221 CH 1, Rank 0
5810 11:45:53.951498 SW Impedance : PASS
5811 11:45:53.951607 DUTY Scan : NO K
5812 11:45:53.954739 ZQ Calibration : PASS
5813 11:45:53.958233 Jitter Meter : NO K
5814 11:45:53.958339 CBT Training : PASS
5815 11:45:53.961179 Write leveling : PASS
5816 11:45:53.964773 RX DQS gating : PASS
5817 11:45:53.964847 RX DQ/DQS(RDDQC) : PASS
5818 11:45:53.967965 TX DQ/DQS : PASS
5819 11:45:53.971602 RX DATLAT : PASS
5820 11:45:53.971705 RX DQ/DQS(Engine): PASS
5821 11:45:53.974890 TX OE : NO K
5822 11:45:53.974989 All Pass.
5823 11:45:53.975080
5824 11:45:53.977966 CH 1, Rank 1
5825 11:45:53.978054 SW Impedance : PASS
5826 11:45:53.981178 DUTY Scan : NO K
5827 11:45:53.984595 ZQ Calibration : PASS
5828 11:45:53.984676 Jitter Meter : NO K
5829 11:45:53.987950 CBT Training : PASS
5830 11:45:53.988019 Write leveling : PASS
5831 11:45:53.991186 RX DQS gating : PASS
5832 11:45:53.994405 RX DQ/DQS(RDDQC) : PASS
5833 11:45:53.994502 TX DQ/DQS : PASS
5834 11:45:53.997791 RX DATLAT : PASS
5835 11:45:54.001207 RX DQ/DQS(Engine): PASS
5836 11:45:54.001277 TX OE : NO K
5837 11:45:54.004541 All Pass.
5838 11:45:54.004620
5839 11:45:54.004684 DramC Write-DBI off
5840 11:45:54.007865 PER_BANK_REFRESH: Hybrid Mode
5841 11:45:54.011044 TX_TRACKING: ON
5842 11:45:54.017788 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5843 11:45:54.020992 [FAST_K] Save calibration result to emmc
5844 11:45:54.024452 dramc_set_vcore_voltage set vcore to 650000
5845 11:45:54.027441 Read voltage for 400, 6
5846 11:45:54.027540 Vio18 = 0
5847 11:45:54.030943 Vcore = 650000
5848 11:45:54.031017 Vdram = 0
5849 11:45:54.031080 Vddq = 0
5850 11:45:54.034215 Vmddr = 0
5851 11:45:54.037418 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5852 11:45:54.044015 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5853 11:45:54.044146 MEM_TYPE=3, freq_sel=20
5854 11:45:54.047136 sv_algorithm_assistance_LP4_800
5855 11:45:54.053814 ============ PULL DRAM RESETB DOWN ============
5856 11:45:54.057441 ========== PULL DRAM RESETB DOWN end =========
5857 11:45:54.060339 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5858 11:45:54.063579 ===================================
5859 11:45:54.067045 LPDDR4 DRAM CONFIGURATION
5860 11:45:54.070500 ===================================
5861 11:45:54.073593 EX_ROW_EN[0] = 0x0
5862 11:45:54.073663 EX_ROW_EN[1] = 0x0
5863 11:45:54.077067 LP4Y_EN = 0x0
5864 11:45:54.077140 WORK_FSP = 0x0
5865 11:45:54.080631 WL = 0x2
5866 11:45:54.080700 RL = 0x2
5867 11:45:54.083691 BL = 0x2
5868 11:45:54.083792 RPST = 0x0
5869 11:45:54.087027 RD_PRE = 0x0
5870 11:45:54.087133 WR_PRE = 0x1
5871 11:45:54.090178 WR_PST = 0x0
5872 11:45:54.090293 DBI_WR = 0x0
5873 11:45:54.093708 DBI_RD = 0x0
5874 11:45:54.093782 OTF = 0x1
5875 11:45:54.096933 ===================================
5876 11:45:54.100572 ===================================
5877 11:45:54.103570 ANA top config
5878 11:45:54.106979 ===================================
5879 11:45:54.110580 DLL_ASYNC_EN = 0
5880 11:45:54.110681 ALL_SLAVE_EN = 1
5881 11:45:54.113585 NEW_RANK_MODE = 1
5882 11:45:54.116804 DLL_IDLE_MODE = 1
5883 11:45:54.120338 LP45_APHY_COMB_EN = 1
5884 11:45:54.120435 TX_ODT_DIS = 1
5885 11:45:54.123672 NEW_8X_MODE = 1
5886 11:45:54.127113 ===================================
5887 11:45:54.130191 ===================================
5888 11:45:54.133478 data_rate = 800
5889 11:45:54.137255 CKR = 1
5890 11:45:54.140202 DQ_P2S_RATIO = 4
5891 11:45:54.143377 ===================================
5892 11:45:54.146727 CA_P2S_RATIO = 4
5893 11:45:54.146797 DQ_CA_OPEN = 0
5894 11:45:54.150352 DQ_SEMI_OPEN = 1
5895 11:45:54.153504 CA_SEMI_OPEN = 1
5896 11:45:54.156501 CA_FULL_RATE = 0
5897 11:45:54.159797 DQ_CKDIV4_EN = 0
5898 11:45:54.163093 CA_CKDIV4_EN = 1
5899 11:45:54.163197 CA_PREDIV_EN = 0
5900 11:45:54.166536 PH8_DLY = 0
5901 11:45:54.170018 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5902 11:45:54.173110 DQ_AAMCK_DIV = 0
5903 11:45:54.176621 CA_AAMCK_DIV = 0
5904 11:45:54.180008 CA_ADMCK_DIV = 4
5905 11:45:54.180076 DQ_TRACK_CA_EN = 0
5906 11:45:54.183226 CA_PICK = 800
5907 11:45:54.186738 CA_MCKIO = 400
5908 11:45:54.190113 MCKIO_SEMI = 400
5909 11:45:54.193085 PLL_FREQ = 3016
5910 11:45:54.196614 DQ_UI_PI_RATIO = 32
5911 11:45:54.199666 CA_UI_PI_RATIO = 32
5912 11:45:54.203141 ===================================
5913 11:45:54.206232 ===================================
5914 11:45:54.206302 memory_type:LPDDR4
5915 11:45:54.209671 GP_NUM : 10
5916 11:45:54.213043 SRAM_EN : 1
5917 11:45:54.213112 MD32_EN : 0
5918 11:45:54.216337 ===================================
5919 11:45:54.219592 [ANA_INIT] >>>>>>>>>>>>>>
5920 11:45:54.223178 <<<<<< [CONFIGURE PHASE]: ANA_TX
5921 11:45:54.226087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5922 11:45:54.229801 ===================================
5923 11:45:54.232928 data_rate = 800,PCW = 0X7400
5924 11:45:54.236299 ===================================
5925 11:45:54.239579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5926 11:45:54.242853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5927 11:45:54.256110 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5928 11:45:54.259571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5929 11:45:54.262878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5930 11:45:54.265960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5931 11:45:54.269460 [ANA_INIT] flow start
5932 11:45:54.272777 [ANA_INIT] PLL >>>>>>>>
5933 11:45:54.272879 [ANA_INIT] PLL <<<<<<<<
5934 11:45:54.276305 [ANA_INIT] MIDPI >>>>>>>>
5935 11:45:54.279267 [ANA_INIT] MIDPI <<<<<<<<
5936 11:45:54.279338 [ANA_INIT] DLL >>>>>>>>
5937 11:45:54.282974 [ANA_INIT] flow end
5938 11:45:54.286020 ============ LP4 DIFF to SE enter ============
5939 11:45:54.289186 ============ LP4 DIFF to SE exit ============
5940 11:45:54.292806 [ANA_INIT] <<<<<<<<<<<<<
5941 11:45:54.296016 [Flow] Enable top DCM control >>>>>
5942 11:45:54.299488 [Flow] Enable top DCM control <<<<<
5943 11:45:54.302464 Enable DLL master slave shuffle
5944 11:45:54.309177 ==============================================================
5945 11:45:54.309252 Gating Mode config
5946 11:45:54.315828 ==============================================================
5947 11:45:54.315933 Config description:
5948 11:45:54.325936 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5949 11:45:54.332300 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5950 11:45:54.339702 SELPH_MODE 0: By rank 1: By Phase
5951 11:45:54.342379 ==============================================================
5952 11:45:54.345936 GAT_TRACK_EN = 0
5953 11:45:54.349080 RX_GATING_MODE = 2
5954 11:45:54.352316 RX_GATING_TRACK_MODE = 2
5955 11:45:54.355792 SELPH_MODE = 1
5956 11:45:54.359215 PICG_EARLY_EN = 1
5957 11:45:54.362330 VALID_LAT_VALUE = 1
5958 11:45:54.369463 ==============================================================
5959 11:45:54.372477 Enter into Gating configuration >>>>
5960 11:45:54.372601 Exit from Gating configuration <<<<
5961 11:45:54.376012 Enter into DVFS_PRE_config >>>>>
5962 11:45:54.389059 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5963 11:45:54.392406 Exit from DVFS_PRE_config <<<<<
5964 11:45:54.395442 Enter into PICG configuration >>>>
5965 11:45:54.398810 Exit from PICG configuration <<<<
5966 11:45:54.398911 [RX_INPUT] configuration >>>>>
5967 11:45:54.402309 [RX_INPUT] configuration <<<<<
5968 11:45:54.409245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5969 11:45:54.412174 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5970 11:45:54.419562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5971 11:45:54.425611 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5972 11:45:54.432325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5973 11:45:54.438964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5974 11:45:54.441910 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5975 11:45:54.445286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5976 11:45:54.451729 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5977 11:45:54.455008 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5978 11:45:54.458326 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5979 11:45:54.465014 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5980 11:45:54.468276 ===================================
5981 11:45:54.468383 LPDDR4 DRAM CONFIGURATION
5982 11:45:54.471634 ===================================
5983 11:45:54.474838 EX_ROW_EN[0] = 0x0
5984 11:45:54.474940 EX_ROW_EN[1] = 0x0
5985 11:45:54.478281 LP4Y_EN = 0x0
5986 11:45:54.478359 WORK_FSP = 0x0
5987 11:45:54.481814 WL = 0x2
5988 11:45:54.481886 RL = 0x2
5989 11:45:54.484965 BL = 0x2
5990 11:45:54.488517 RPST = 0x0
5991 11:45:54.488621 RD_PRE = 0x0
5992 11:45:54.491659 WR_PRE = 0x1
5993 11:45:54.491770 WR_PST = 0x0
5994 11:45:54.494770 DBI_WR = 0x0
5995 11:45:54.494874 DBI_RD = 0x0
5996 11:45:54.498215 OTF = 0x1
5997 11:45:54.501135 ===================================
5998 11:45:54.504734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5999 11:45:54.507978 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6000 11:45:54.514492 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6001 11:45:54.514595 ===================================
6002 11:45:54.517968 LPDDR4 DRAM CONFIGURATION
6003 11:45:54.521084 ===================================
6004 11:45:54.524373 EX_ROW_EN[0] = 0x10
6005 11:45:54.524475 EX_ROW_EN[1] = 0x0
6006 11:45:54.528221 LP4Y_EN = 0x0
6007 11:45:54.528329 WORK_FSP = 0x0
6008 11:45:54.531359 WL = 0x2
6009 11:45:54.531437 RL = 0x2
6010 11:45:54.534144 BL = 0x2
6011 11:45:54.537668 RPST = 0x0
6012 11:45:54.537739 RD_PRE = 0x0
6013 11:45:54.541010 WR_PRE = 0x1
6014 11:45:54.541093 WR_PST = 0x0
6015 11:45:54.544466 DBI_WR = 0x0
6016 11:45:54.544591 DBI_RD = 0x0
6017 11:45:54.547481 OTF = 0x1
6018 11:45:54.551291 ===================================
6019 11:45:54.557274 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6020 11:45:54.560640 nWR fixed to 30
6021 11:45:54.560790 [ModeRegInit_LP4] CH0 RK0
6022 11:45:54.564132 [ModeRegInit_LP4] CH0 RK1
6023 11:45:54.567536 [ModeRegInit_LP4] CH1 RK0
6024 11:45:54.567660 [ModeRegInit_LP4] CH1 RK1
6025 11:45:54.570834 match AC timing 18
6026 11:45:54.573826 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6027 11:45:54.577463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6028 11:45:54.584049 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6029 11:45:54.587195 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6030 11:45:54.594178 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6031 11:45:54.594254 ==
6032 11:45:54.597497 Dram Type= 6, Freq= 0, CH_0, rank 0
6033 11:45:54.600601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6034 11:45:54.600673 ==
6035 11:45:54.607487 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6036 11:45:54.613908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6037 11:45:54.613992 [CA 0] Center 36 (8~64) winsize 57
6038 11:45:54.617180 [CA 1] Center 36 (8~64) winsize 57
6039 11:45:54.620428 [CA 2] Center 36 (8~64) winsize 57
6040 11:45:54.623518 [CA 3] Center 36 (8~64) winsize 57
6041 11:45:54.627286 [CA 4] Center 36 (8~64) winsize 57
6042 11:45:54.630225 [CA 5] Center 36 (8~64) winsize 57
6043 11:45:54.630309
6044 11:45:54.633466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6045 11:45:54.633549
6046 11:45:54.636743 [CATrainingPosCal] consider 1 rank data
6047 11:45:54.640165 u2DelayCellTimex100 = 270/100 ps
6048 11:45:54.643435 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6049 11:45:54.649982 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6050 11:45:54.653287 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6051 11:45:54.656738 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6052 11:45:54.660232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 11:45:54.663447 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 11:45:54.663588
6055 11:45:54.666634 CA PerBit enable=1, Macro0, CA PI delay=36
6056 11:45:54.666718
6057 11:45:54.669791 [CBTSetCACLKResult] CA Dly = 36
6058 11:45:54.669879 CS Dly: 1 (0~32)
6059 11:45:54.673196 ==
6060 11:45:54.676457 Dram Type= 6, Freq= 0, CH_0, rank 1
6061 11:45:54.679669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6062 11:45:54.679775 ==
6063 11:45:54.683275 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6064 11:45:54.689581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6065 11:45:54.692839 [CA 0] Center 36 (8~64) winsize 57
6066 11:45:54.696519 [CA 1] Center 36 (8~64) winsize 57
6067 11:45:54.699704 [CA 2] Center 36 (8~64) winsize 57
6068 11:45:54.703011 [CA 3] Center 36 (8~64) winsize 57
6069 11:45:54.706440 [CA 4] Center 36 (8~64) winsize 57
6070 11:45:54.709423 [CA 5] Center 36 (8~64) winsize 57
6071 11:45:54.709497
6072 11:45:54.712955 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6073 11:45:54.713025
6074 11:45:54.716386 [CATrainingPosCal] consider 2 rank data
6075 11:45:54.719546 u2DelayCellTimex100 = 270/100 ps
6076 11:45:54.723158 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6077 11:45:54.726126 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6078 11:45:54.730037 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6079 11:45:54.733350 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6080 11:45:54.739709 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 11:45:54.743241 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 11:45:54.743314
6083 11:45:54.746191 CA PerBit enable=1, Macro0, CA PI delay=36
6084 11:45:54.746274
6085 11:45:54.749584 [CBTSetCACLKResult] CA Dly = 36
6086 11:45:54.749667 CS Dly: 1 (0~32)
6087 11:45:54.749733
6088 11:45:54.753075 ----->DramcWriteLeveling(PI) begin...
6089 11:45:54.753159 ==
6090 11:45:54.756231 Dram Type= 6, Freq= 0, CH_0, rank 0
6091 11:45:54.762938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6092 11:45:54.763048 ==
6093 11:45:54.766213 Write leveling (Byte 0): 32 => 0
6094 11:45:54.766299 Write leveling (Byte 1): 32 => 0
6095 11:45:54.769819 DramcWriteLeveling(PI) end<-----
6096 11:45:54.769920
6097 11:45:54.770012 ==
6098 11:45:54.772682 Dram Type= 6, Freq= 0, CH_0, rank 0
6099 11:45:54.779292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6100 11:45:54.779401 ==
6101 11:45:54.782617 [Gating] SW mode calibration
6102 11:45:54.789400 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6103 11:45:54.792635 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6104 11:45:54.799546 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6105 11:45:54.802480 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6106 11:45:54.805941 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6107 11:45:54.812612 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6108 11:45:54.815990 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6109 11:45:54.819335 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6110 11:45:54.826035 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6111 11:45:54.828961 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6112 11:45:54.832205 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6113 11:45:54.835655 Total UI for P1: 0, mck2ui 16
6114 11:45:54.838841 best dqsien dly found for B0: ( 0, 10, 16)
6115 11:45:54.842048 Total UI for P1: 0, mck2ui 16
6116 11:45:54.845610 best dqsien dly found for B1: ( 0, 10, 16)
6117 11:45:54.848704 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6118 11:45:54.852629 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6119 11:45:54.852745
6120 11:45:54.858593 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6121 11:45:54.861763 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6122 11:45:54.865409 [Gating] SW calibration Done
6123 11:45:54.865533 ==
6124 11:45:54.868847 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 11:45:54.871659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 11:45:54.871733 ==
6127 11:45:54.871813 RX Vref Scan: 0
6128 11:45:54.871887
6129 11:45:54.875419 RX Vref 0 -> 0, step: 1
6130 11:45:54.875487
6131 11:45:54.878468 RX Delay -410 -> 252, step: 16
6132 11:45:54.882032 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6133 11:45:54.888547 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6134 11:45:54.891813 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6135 11:45:54.894915 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6136 11:45:54.898712 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6137 11:45:54.904799 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6138 11:45:54.908138 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6139 11:45:54.911588 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6140 11:45:54.915045 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6141 11:45:54.921467 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6142 11:45:54.924695 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6143 11:45:54.928046 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6144 11:45:54.931315 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6145 11:45:54.938090 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6146 11:45:54.941397 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6147 11:45:54.944820 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6148 11:45:54.944928 ==
6149 11:45:54.948750 Dram Type= 6, Freq= 0, CH_0, rank 0
6150 11:45:54.954931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6151 11:45:54.955044 ==
6152 11:45:54.955140 DQS Delay:
6153 11:45:54.955231 DQS0 = 43, DQS1 = 59
6154 11:45:54.958088 DQM Delay:
6155 11:45:54.958214 DQM0 = 5, DQM1 = 14
6156 11:45:54.961398 DQ Delay:
6157 11:45:54.961500 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6158 11:45:54.964705 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6159 11:45:54.968028 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6160 11:45:54.971166 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6161 11:45:54.971251
6162 11:45:54.971318
6163 11:45:54.974561 ==
6164 11:45:54.974643 Dram Type= 6, Freq= 0, CH_0, rank 0
6165 11:45:54.981438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6166 11:45:54.981519 ==
6167 11:45:54.981587
6168 11:45:54.981647
6169 11:45:54.984412 TX Vref Scan disable
6170 11:45:54.984518 == TX Byte 0 ==
6171 11:45:54.987747 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6172 11:45:54.994459 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6173 11:45:54.994537 == TX Byte 1 ==
6174 11:45:54.997881 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6175 11:45:55.004314 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6176 11:45:55.004400 ==
6177 11:45:55.007938 Dram Type= 6, Freq= 0, CH_0, rank 0
6178 11:45:55.010822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6179 11:45:55.010900 ==
6180 11:45:55.010965
6181 11:45:55.011031
6182 11:45:55.014890 TX Vref Scan disable
6183 11:45:55.014958 == TX Byte 0 ==
6184 11:45:55.017685 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6185 11:45:55.024150 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6186 11:45:55.024250 == TX Byte 1 ==
6187 11:45:55.027491 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6188 11:45:55.034468 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6189 11:45:55.034543
6190 11:45:55.034610 [DATLAT]
6191 11:45:55.037494 Freq=400, CH0 RK0
6192 11:45:55.037593
6193 11:45:55.037684 DATLAT Default: 0xf
6194 11:45:55.041014 0, 0xFFFF, sum = 0
6195 11:45:55.041088 1, 0xFFFF, sum = 0
6196 11:45:55.043915 2, 0xFFFF, sum = 0
6197 11:45:55.044013 3, 0xFFFF, sum = 0
6198 11:45:55.047549 4, 0xFFFF, sum = 0
6199 11:45:55.047648 5, 0xFFFF, sum = 0
6200 11:45:55.050531 6, 0xFFFF, sum = 0
6201 11:45:55.050636 7, 0xFFFF, sum = 0
6202 11:45:55.053861 8, 0xFFFF, sum = 0
6203 11:45:55.053969 9, 0xFFFF, sum = 0
6204 11:45:55.057211 10, 0xFFFF, sum = 0
6205 11:45:55.057316 11, 0xFFFF, sum = 0
6206 11:45:55.060640 12, 0x0, sum = 1
6207 11:45:55.060744 13, 0x0, sum = 2
6208 11:45:55.063992 14, 0x0, sum = 3
6209 11:45:55.064096 15, 0x0, sum = 4
6210 11:45:55.067185 best_step = 13
6211 11:45:55.067280
6212 11:45:55.067373 ==
6213 11:45:55.070704 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 11:45:55.073823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6215 11:45:55.073955 ==
6216 11:45:55.076955 RX Vref Scan: 1
6217 11:45:55.077026
6218 11:45:55.077087 RX Vref 0 -> 0, step: 1
6219 11:45:55.077197
6220 11:45:55.080459 RX Delay -359 -> 252, step: 8
6221 11:45:55.080590
6222 11:45:55.083720 Set Vref, RX VrefLevel [Byte0]: 46
6223 11:45:55.087414 [Byte1]: 45
6224 11:45:55.092326
6225 11:45:55.092425 Final RX Vref Byte 0 = 46 to rank0
6226 11:45:55.095342 Final RX Vref Byte 1 = 45 to rank0
6227 11:45:55.098584 Final RX Vref Byte 0 = 46 to rank1
6228 11:45:55.102122 Final RX Vref Byte 1 = 45 to rank1==
6229 11:45:55.105165 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 11:45:55.111731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6231 11:45:55.111845 ==
6232 11:45:55.111940 DQS Delay:
6233 11:45:55.115238 DQS0 = 48, DQS1 = 68
6234 11:45:55.115342 DQM Delay:
6235 11:45:55.115446 DQM0 = 5, DQM1 = 17
6236 11:45:55.118788 DQ Delay:
6237 11:45:55.121630 DQ0 =0, DQ1 =4, DQ2 =4, DQ3 =0
6238 11:45:55.121744 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6239 11:45:55.125189 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6240 11:45:55.128263 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6241 11:45:55.128368
6242 11:45:55.128461
6243 11:45:55.138527 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6244 11:45:55.141534 CH0 RK0: MR19=C0C, MR18=A4A4
6245 11:45:55.148732 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6246 11:45:55.148813 ==
6247 11:45:55.151633 Dram Type= 6, Freq= 0, CH_0, rank 1
6248 11:45:55.154979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 11:45:55.155085 ==
6250 11:45:55.158562 [Gating] SW mode calibration
6251 11:45:55.165234 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6252 11:45:55.168285 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6253 11:45:55.174987 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6254 11:45:55.178470 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6255 11:45:55.181855 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6256 11:45:55.188148 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6257 11:45:55.191374 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 11:45:55.195111 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 11:45:55.201469 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 11:45:55.204953 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6261 11:45:55.208221 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 11:45:55.211220 Total UI for P1: 0, mck2ui 16
6263 11:45:55.214589 best dqsien dly found for B0: ( 0, 10, 16)
6264 11:45:55.218127 Total UI for P1: 0, mck2ui 16
6265 11:45:55.221481 best dqsien dly found for B1: ( 0, 10, 24)
6266 11:45:55.224847 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6267 11:45:55.228081 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6268 11:45:55.231141
6269 11:45:55.234571 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6270 11:45:55.237747 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6271 11:45:55.241012 [Gating] SW calibration Done
6272 11:45:55.241114 ==
6273 11:45:55.244375 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 11:45:55.247726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 11:45:55.247835 ==
6276 11:45:55.251222 RX Vref Scan: 0
6277 11:45:55.251320
6278 11:45:55.251412 RX Vref 0 -> 0, step: 1
6279 11:45:55.251512
6280 11:45:55.255479 RX Delay -410 -> 252, step: 16
6281 11:45:55.257797 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6282 11:45:55.264374 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6283 11:45:55.267756 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6284 11:45:55.270915 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6285 11:45:55.274072 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6286 11:45:55.281296 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6287 11:45:55.284321 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6288 11:45:55.287368 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6289 11:45:55.290757 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6290 11:45:55.297406 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6291 11:45:55.300670 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6292 11:45:55.304220 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6293 11:45:55.310634 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6294 11:45:55.314050 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6295 11:45:55.317276 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6296 11:45:55.320750 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6297 11:45:55.320858 ==
6298 11:45:55.324023 Dram Type= 6, Freq= 0, CH_0, rank 1
6299 11:45:55.330662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6300 11:45:55.330767 ==
6301 11:45:55.330864 DQS Delay:
6302 11:45:55.333695 DQS0 = 43, DQS1 = 59
6303 11:45:55.333767 DQM Delay:
6304 11:45:55.336960 DQM0 = 7, DQM1 = 15
6305 11:45:55.337031 DQ Delay:
6306 11:45:55.340249 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6307 11:45:55.343596 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6308 11:45:55.347014 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6309 11:45:55.350366 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6310 11:45:55.350465
6311 11:45:55.350556
6312 11:45:55.350645 ==
6313 11:45:55.353958 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 11:45:55.357081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6315 11:45:55.357155 ==
6316 11:45:55.357220
6317 11:45:55.357283
6318 11:45:55.360770 TX Vref Scan disable
6319 11:45:55.360879 == TX Byte 0 ==
6320 11:45:55.363782 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6321 11:45:55.370494 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6322 11:45:55.370606 == TX Byte 1 ==
6323 11:45:55.374013 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6324 11:45:55.380479 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6325 11:45:55.380605 ==
6326 11:45:55.383257 Dram Type= 6, Freq= 0, CH_0, rank 1
6327 11:45:55.386887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6328 11:45:55.386990 ==
6329 11:45:55.387092
6330 11:45:55.387212
6331 11:45:55.390138 TX Vref Scan disable
6332 11:45:55.390252 == TX Byte 0 ==
6333 11:45:55.396663 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6334 11:45:55.400248 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6335 11:45:55.400335 == TX Byte 1 ==
6336 11:45:55.403174 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6337 11:45:55.410432 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6338 11:45:55.410507
6339 11:45:55.410570 [DATLAT]
6340 11:45:55.413437 Freq=400, CH0 RK1
6341 11:45:55.413520
6342 11:45:55.413585 DATLAT Default: 0xd
6343 11:45:55.416552 0, 0xFFFF, sum = 0
6344 11:45:55.416646 1, 0xFFFF, sum = 0
6345 11:45:55.419991 2, 0xFFFF, sum = 0
6346 11:45:55.420087 3, 0xFFFF, sum = 0
6347 11:45:55.423231 4, 0xFFFF, sum = 0
6348 11:45:55.423314 5, 0xFFFF, sum = 0
6349 11:45:55.426554 6, 0xFFFF, sum = 0
6350 11:45:55.426637 7, 0xFFFF, sum = 0
6351 11:45:55.429776 8, 0xFFFF, sum = 0
6352 11:45:55.429860 9, 0xFFFF, sum = 0
6353 11:45:55.432820 10, 0xFFFF, sum = 0
6354 11:45:55.432903 11, 0xFFFF, sum = 0
6355 11:45:55.436419 12, 0x0, sum = 1
6356 11:45:55.436554 13, 0x0, sum = 2
6357 11:45:55.439728 14, 0x0, sum = 3
6358 11:45:55.439811 15, 0x0, sum = 4
6359 11:45:55.443303 best_step = 13
6360 11:45:55.443384
6361 11:45:55.443449 ==
6362 11:45:55.446152 Dram Type= 6, Freq= 0, CH_0, rank 1
6363 11:45:55.449518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6364 11:45:55.449600 ==
6365 11:45:55.453129 RX Vref Scan: 0
6366 11:45:55.453202
6367 11:45:55.453265 RX Vref 0 -> 0, step: 1
6368 11:45:55.453347
6369 11:45:55.456012 RX Delay -359 -> 252, step: 8
6370 11:45:55.464320 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6371 11:45:55.467757 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6372 11:45:55.471161 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6373 11:45:55.473994 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6374 11:45:55.480844 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6375 11:45:55.484105 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6376 11:45:55.487507 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6377 11:45:55.490846 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6378 11:45:55.497485 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6379 11:45:55.500488 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6380 11:45:55.504000 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6381 11:45:55.510928 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6382 11:45:55.514004 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6383 11:45:55.517094 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6384 11:45:55.520470 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6385 11:45:55.527450 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6386 11:45:55.527560 ==
6387 11:45:55.530492 Dram Type= 6, Freq= 0, CH_0, rank 1
6388 11:45:55.533746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6389 11:45:55.533820 ==
6390 11:45:55.533882 DQS Delay:
6391 11:45:55.537030 DQS0 = 52, DQS1 = 64
6392 11:45:55.537128 DQM Delay:
6393 11:45:55.540551 DQM0 = 9, DQM1 = 13
6394 11:45:55.540635 DQ Delay:
6395 11:45:55.543664 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6396 11:45:55.547051 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6397 11:45:55.550324 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6398 11:45:55.553629 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6399 11:45:55.553729
6400 11:45:55.553823
6401 11:45:55.560411 [DQSOSCAuto] RK1, (LSB)MR18= 0xc6c6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6402 11:45:55.563736 CH0 RK1: MR19=C0C, MR18=C6C6
6403 11:45:55.570238 CH0_RK1: MR19=0xC0C, MR18=0xC6C6, DQSOSC=385, MR23=63, INC=398, DEC=265
6404 11:45:55.573489 [RxdqsGatingPostProcess] freq 400
6405 11:45:55.580244 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6406 11:45:55.583589 Pre-setting of DQS Precalculation
6407 11:45:55.586904 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6408 11:45:55.587008 ==
6409 11:45:55.590063 Dram Type= 6, Freq= 0, CH_1, rank 0
6410 11:45:55.593280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6411 11:45:55.593353 ==
6412 11:45:55.599810 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6413 11:45:55.606600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6414 11:45:55.609930 [CA 0] Center 36 (8~64) winsize 57
6415 11:45:55.613195 [CA 1] Center 36 (8~64) winsize 57
6416 11:45:55.616474 [CA 2] Center 36 (8~64) winsize 57
6417 11:45:55.620103 [CA 3] Center 36 (8~64) winsize 57
6418 11:45:55.623162 [CA 4] Center 36 (8~64) winsize 57
6419 11:45:55.623269 [CA 5] Center 36 (8~64) winsize 57
6420 11:45:55.626343
6421 11:45:55.630224 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6422 11:45:55.630328
6423 11:45:55.633547 [CATrainingPosCal] consider 1 rank data
6424 11:45:55.636252 u2DelayCellTimex100 = 270/100 ps
6425 11:45:55.639888 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6426 11:45:55.643428 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6427 11:45:55.646178 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6428 11:45:55.650166 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6429 11:45:55.652886 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 11:45:55.656562 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 11:45:55.656637
6432 11:45:55.659758 CA PerBit enable=1, Macro0, CA PI delay=36
6433 11:45:55.659861
6434 11:45:55.663131 [CBTSetCACLKResult] CA Dly = 36
6435 11:45:55.666014 CS Dly: 1 (0~32)
6436 11:45:55.666088 ==
6437 11:45:55.669479 Dram Type= 6, Freq= 0, CH_1, rank 1
6438 11:45:55.672777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6439 11:45:55.672879 ==
6440 11:45:55.679616 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6441 11:45:55.686416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6442 11:45:55.689600 [CA 0] Center 36 (8~64) winsize 57
6443 11:45:55.689705 [CA 1] Center 36 (8~64) winsize 57
6444 11:45:55.693070 [CA 2] Center 36 (8~64) winsize 57
6445 11:45:55.695960 [CA 3] Center 36 (8~64) winsize 57
6446 11:45:55.699436 [CA 4] Center 36 (8~64) winsize 57
6447 11:45:55.702578 [CA 5] Center 36 (8~64) winsize 57
6448 11:45:55.702651
6449 11:45:55.706206 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6450 11:45:55.706292
6451 11:45:55.712695 [CATrainingPosCal] consider 2 rank data
6452 11:45:55.712778 u2DelayCellTimex100 = 270/100 ps
6453 11:45:55.719035 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6454 11:45:55.722690 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6455 11:45:55.725832 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6456 11:45:55.728877 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6457 11:45:55.732284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 11:45:55.735542 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 11:45:55.735668
6460 11:45:55.739318 CA PerBit enable=1, Macro0, CA PI delay=36
6461 11:45:55.739400
6462 11:45:55.742512 [CBTSetCACLKResult] CA Dly = 36
6463 11:45:55.745433 CS Dly: 1 (0~32)
6464 11:45:55.745515
6465 11:45:55.748885 ----->DramcWriteLeveling(PI) begin...
6466 11:45:55.748983 ==
6467 11:45:55.752189 Dram Type= 6, Freq= 0, CH_1, rank 0
6468 11:45:55.755478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6469 11:45:55.755562 ==
6470 11:45:55.758658 Write leveling (Byte 0): 32 => 0
6471 11:45:55.762303 Write leveling (Byte 1): 32 => 0
6472 11:45:55.765335 DramcWriteLeveling(PI) end<-----
6473 11:45:55.765417
6474 11:45:55.765483 ==
6475 11:45:55.769035 Dram Type= 6, Freq= 0, CH_1, rank 0
6476 11:45:55.771982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6477 11:45:55.772064 ==
6478 11:45:55.775489 [Gating] SW mode calibration
6479 11:45:55.782097 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6480 11:45:55.788711 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6481 11:45:55.792166 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 11:45:55.795263 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 11:45:55.801861 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 11:45:55.805312 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6485 11:45:55.808664 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 11:45:55.815550 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 11:45:55.818359 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 11:45:55.821752 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6489 11:45:55.828449 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 11:45:55.828603 Total UI for P1: 0, mck2ui 16
6491 11:45:55.835001 best dqsien dly found for B0: ( 0, 10, 16)
6492 11:45:55.835113 Total UI for P1: 0, mck2ui 16
6493 11:45:55.838625 best dqsien dly found for B1: ( 0, 10, 16)
6494 11:45:55.845090 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6495 11:45:55.848220 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6496 11:45:55.848321
6497 11:45:55.851653 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6498 11:45:55.854995 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6499 11:45:55.858267 [Gating] SW calibration Done
6500 11:45:55.858343 ==
6501 11:45:55.861745 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 11:45:55.865525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 11:45:55.865601 ==
6504 11:45:55.868140 RX Vref Scan: 0
6505 11:45:55.868239
6506 11:45:55.868340 RX Vref 0 -> 0, step: 1
6507 11:45:55.868430
6508 11:45:55.871766 RX Delay -410 -> 252, step: 16
6509 11:45:55.878096 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6510 11:45:55.881693 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6511 11:45:55.884871 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6512 11:45:55.888251 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6513 11:45:55.894754 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6514 11:45:55.898393 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6515 11:45:55.901602 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6516 11:45:55.904941 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6517 11:45:55.911432 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6518 11:45:55.914705 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6519 11:45:55.918237 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6520 11:45:55.921581 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6521 11:45:55.927889 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6522 11:45:55.931686 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6523 11:45:55.934651 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6524 11:45:55.938270 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6525 11:45:55.941125 ==
6526 11:45:55.944660 Dram Type= 6, Freq= 0, CH_1, rank 0
6527 11:45:55.947844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6528 11:45:55.947963 ==
6529 11:45:55.948079 DQS Delay:
6530 11:45:55.951640 DQS0 = 43, DQS1 = 59
6531 11:45:55.951740 DQM Delay:
6532 11:45:55.954714 DQM0 = 6, DQM1 = 16
6533 11:45:55.954833 DQ Delay:
6534 11:45:55.958140 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6535 11:45:55.961623 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6536 11:45:55.964489 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6537 11:45:55.967671 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6538 11:45:55.967760
6539 11:45:55.967833
6540 11:45:55.967925 ==
6541 11:45:55.971218 Dram Type= 6, Freq= 0, CH_1, rank 0
6542 11:45:55.974283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6543 11:45:55.974356 ==
6544 11:45:55.974418
6545 11:45:55.974477
6546 11:45:55.977903 TX Vref Scan disable
6547 11:45:55.977983 == TX Byte 0 ==
6548 11:45:55.984951 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6549 11:45:55.988038 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6550 11:45:55.988125 == TX Byte 1 ==
6551 11:45:55.994556 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6552 11:45:55.997878 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6553 11:45:55.997952 ==
6554 11:45:56.000829 Dram Type= 6, Freq= 0, CH_1, rank 0
6555 11:45:56.004352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6556 11:45:56.004452 ==
6557 11:45:56.004586
6558 11:45:56.004653
6559 11:45:56.007594 TX Vref Scan disable
6560 11:45:56.007665 == TX Byte 0 ==
6561 11:45:56.013965 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6562 11:45:56.017424 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6563 11:45:56.020687 == TX Byte 1 ==
6564 11:45:56.023940 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6565 11:45:56.027495 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6566 11:45:56.027587
6567 11:45:56.027653 [DATLAT]
6568 11:45:56.030839 Freq=400, CH1 RK0
6569 11:45:56.030922
6570 11:45:56.031008 DATLAT Default: 0xf
6571 11:45:56.033974 0, 0xFFFF, sum = 0
6572 11:45:56.037030 1, 0xFFFF, sum = 0
6573 11:45:56.037109 2, 0xFFFF, sum = 0
6574 11:45:56.040706 3, 0xFFFF, sum = 0
6575 11:45:56.040781 4, 0xFFFF, sum = 0
6576 11:45:56.044131 5, 0xFFFF, sum = 0
6577 11:45:56.044292 6, 0xFFFF, sum = 0
6578 11:45:56.047114 7, 0xFFFF, sum = 0
6579 11:45:56.047224 8, 0xFFFF, sum = 0
6580 11:45:56.050281 9, 0xFFFF, sum = 0
6581 11:45:56.050384 10, 0xFFFF, sum = 0
6582 11:45:56.053562 11, 0xFFFF, sum = 0
6583 11:45:56.053641 12, 0x0, sum = 1
6584 11:45:56.057176 13, 0x0, sum = 2
6585 11:45:56.057280 14, 0x0, sum = 3
6586 11:45:56.060474 15, 0x0, sum = 4
6587 11:45:56.060579 best_step = 13
6588 11:45:56.060662
6589 11:45:56.060742 ==
6590 11:45:56.063450 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 11:45:56.066834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6592 11:45:56.070258 ==
6593 11:45:56.070333 RX Vref Scan: 1
6594 11:45:56.070396
6595 11:45:56.073898 RX Vref 0 -> 0, step: 1
6596 11:45:56.073996
6597 11:45:56.076855 RX Delay -359 -> 252, step: 8
6598 11:45:56.076966
6599 11:45:56.080418 Set Vref, RX VrefLevel [Byte0]: 53
6600 11:45:56.083706 [Byte1]: 50
6601 11:45:56.083788
6602 11:45:56.087079 Final RX Vref Byte 0 = 53 to rank0
6603 11:45:56.090215 Final RX Vref Byte 1 = 50 to rank0
6604 11:45:56.093975 Final RX Vref Byte 0 = 53 to rank1
6605 11:45:56.097028 Final RX Vref Byte 1 = 50 to rank1==
6606 11:45:56.100306 Dram Type= 6, Freq= 0, CH_1, rank 0
6607 11:45:56.103596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6608 11:45:56.103679 ==
6609 11:45:56.106850 DQS Delay:
6610 11:45:56.106933 DQS0 = 48, DQS1 = 64
6611 11:45:56.110410 DQM Delay:
6612 11:45:56.110492 DQM0 = 8, DQM1 = 15
6613 11:45:56.110558 DQ Delay:
6614 11:45:56.113408 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6615 11:45:56.116810 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6616 11:45:56.119844 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6617 11:45:56.123157 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6618 11:45:56.123239
6619 11:45:56.123349
6620 11:45:56.133315 [DQSOSCAuto] RK0, (LSB)MR18= 0xd3d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6621 11:45:56.133399 CH1 RK0: MR19=C0C, MR18=D3D3
6622 11:45:56.139822 CH1_RK0: MR19=0xC0C, MR18=0xD3D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6623 11:45:56.139905 ==
6624 11:45:56.143643 Dram Type= 6, Freq= 0, CH_1, rank 1
6625 11:45:56.150188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 11:45:56.150271 ==
6627 11:45:56.152951 [Gating] SW mode calibration
6628 11:45:56.159730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6629 11:45:56.163122 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6630 11:45:56.169599 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6631 11:45:56.172831 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6632 11:45:56.176161 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6633 11:45:56.182901 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6634 11:45:56.185912 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6635 11:45:56.189339 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6636 11:45:56.196348 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6637 11:45:56.199613 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6638 11:45:56.203013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6639 11:45:56.206159 Total UI for P1: 0, mck2ui 16
6640 11:45:56.209345 best dqsien dly found for B0: ( 0, 10, 16)
6641 11:45:56.212493 Total UI for P1: 0, mck2ui 16
6642 11:45:56.215977 best dqsien dly found for B1: ( 0, 10, 16)
6643 11:45:56.219135 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6644 11:45:56.222237 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6645 11:45:56.222320
6646 11:45:56.228859 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6647 11:45:56.232154 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6648 11:45:56.235765 [Gating] SW calibration Done
6649 11:45:56.235850 ==
6650 11:45:56.239106 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 11:45:56.242217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 11:45:56.242296 ==
6653 11:45:56.242360 RX Vref Scan: 0
6654 11:45:56.245588
6655 11:45:56.245670 RX Vref 0 -> 0, step: 1
6656 11:45:56.245736
6657 11:45:56.249014 RX Delay -410 -> 252, step: 16
6658 11:45:56.252335 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6659 11:45:56.258767 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6660 11:45:56.261935 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6661 11:45:56.265435 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6662 11:45:56.268773 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6663 11:45:56.275671 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6664 11:45:56.278628 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6665 11:45:56.282121 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6666 11:45:56.285187 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6667 11:45:56.292008 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6668 11:45:56.294996 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6669 11:45:56.298516 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6670 11:45:56.301897 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6671 11:45:56.308946 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6672 11:45:56.311792 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6673 11:45:56.315044 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6674 11:45:56.315128 ==
6675 11:45:56.318277 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 11:45:56.325080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6677 11:45:56.325163 ==
6678 11:45:56.325229 DQS Delay:
6679 11:45:56.328324 DQS0 = 43, DQS1 = 59
6680 11:45:56.328406 DQM Delay:
6681 11:45:56.328472 DQM0 = 10, DQM1 = 18
6682 11:45:56.331901 DQ Delay:
6683 11:45:56.335191 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6684 11:45:56.335288 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6685 11:45:56.338438 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6686 11:45:56.341597 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6687 11:45:56.341681
6688 11:45:56.341746
6689 11:45:56.345091 ==
6690 11:45:56.348433 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 11:45:56.351678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6692 11:45:56.351777 ==
6693 11:45:56.351844
6694 11:45:56.351905
6695 11:45:56.355150 TX Vref Scan disable
6696 11:45:56.355233 == TX Byte 0 ==
6697 11:45:56.358177 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6698 11:45:56.364845 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6699 11:45:56.364954 == TX Byte 1 ==
6700 11:45:56.368201 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6701 11:45:56.371405 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6702 11:45:56.374851 ==
6703 11:45:56.378246 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 11:45:56.381659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6705 11:45:56.381742 ==
6706 11:45:56.381808
6707 11:45:56.381869
6708 11:45:56.384771 TX Vref Scan disable
6709 11:45:56.384854 == TX Byte 0 ==
6710 11:45:56.388119 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6711 11:45:56.394582 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6712 11:45:56.394665 == TX Byte 1 ==
6713 11:45:56.397992 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6714 11:45:56.404569 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6715 11:45:56.404683
6716 11:45:56.404788 [DATLAT]
6717 11:45:56.404855 Freq=400, CH1 RK1
6718 11:45:56.404917
6719 11:45:56.408003 DATLAT Default: 0xd
6720 11:45:56.408081 0, 0xFFFF, sum = 0
6721 11:45:56.411419 1, 0xFFFF, sum = 0
6722 11:45:56.414750 2, 0xFFFF, sum = 0
6723 11:45:56.414826 3, 0xFFFF, sum = 0
6724 11:45:56.418361 4, 0xFFFF, sum = 0
6725 11:45:56.418435 5, 0xFFFF, sum = 0
6726 11:45:56.421419 6, 0xFFFF, sum = 0
6727 11:45:56.421489 7, 0xFFFF, sum = 0
6728 11:45:56.424851 8, 0xFFFF, sum = 0
6729 11:45:56.424927 9, 0xFFFF, sum = 0
6730 11:45:56.428416 10, 0xFFFF, sum = 0
6731 11:45:56.428526 11, 0xFFFF, sum = 0
6732 11:45:56.431180 12, 0x0, sum = 1
6733 11:45:56.431254 13, 0x0, sum = 2
6734 11:45:56.434765 14, 0x0, sum = 3
6735 11:45:56.434885 15, 0x0, sum = 4
6736 11:45:56.434979 best_step = 13
6737 11:45:56.438089
6738 11:45:56.438173 ==
6739 11:45:56.441308 Dram Type= 6, Freq= 0, CH_1, rank 1
6740 11:45:56.444526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6741 11:45:56.444638 ==
6742 11:45:56.444730 RX Vref Scan: 0
6743 11:45:56.444798
6744 11:45:56.448066 RX Vref 0 -> 0, step: 1
6745 11:45:56.448136
6746 11:45:56.451288 RX Delay -359 -> 252, step: 8
6747 11:45:56.458551 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6748 11:45:56.461549 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6749 11:45:56.465243 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6750 11:45:56.468365 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6751 11:45:56.475144 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6752 11:45:56.478597 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6753 11:45:56.481572 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6754 11:45:56.485177 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6755 11:45:56.491648 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6756 11:45:56.494878 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6757 11:45:56.498124 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6758 11:45:56.504868 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6759 11:45:56.508160 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6760 11:45:56.511315 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6761 11:45:56.514732 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6762 11:45:56.521279 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6763 11:45:56.521356 ==
6764 11:45:56.524581 Dram Type= 6, Freq= 0, CH_1, rank 1
6765 11:45:56.528415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6766 11:45:56.528553 ==
6767 11:45:56.528648 DQS Delay:
6768 11:45:56.531285 DQS0 = 48, DQS1 = 64
6769 11:45:56.531381 DQM Delay:
6770 11:45:56.534867 DQM0 = 9, DQM1 = 15
6771 11:45:56.534945 DQ Delay:
6772 11:45:56.538360 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6773 11:45:56.541251 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6774 11:45:56.544778 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6775 11:45:56.548599 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6776 11:45:56.548700
6777 11:45:56.548796
6778 11:45:56.554580 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6779 11:45:56.558393 CH1 RK1: MR19=C0C, MR18=A3A3
6780 11:45:56.564747 CH1_RK1: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6781 11:45:56.567756 [RxdqsGatingPostProcess] freq 400
6782 11:45:56.574380 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6783 11:45:56.574499 Pre-setting of DQS Precalculation
6784 11:45:56.581036 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6785 11:45:56.587648 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6786 11:45:56.594150 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6787 11:45:56.594231
6788 11:45:56.594297
6789 11:45:56.597672 [Calibration Summary] 800 Mbps
6790 11:45:56.600642 CH 0, Rank 0
6791 11:45:56.600725 SW Impedance : PASS
6792 11:45:56.604117 DUTY Scan : NO K
6793 11:45:56.607510 ZQ Calibration : PASS
6794 11:45:56.607620 Jitter Meter : NO K
6795 11:45:56.610884 CBT Training : PASS
6796 11:45:56.614162 Write leveling : PASS
6797 11:45:56.614242 RX DQS gating : PASS
6798 11:45:56.617554 RX DQ/DQS(RDDQC) : PASS
6799 11:45:56.617625 TX DQ/DQS : PASS
6800 11:45:56.620899 RX DATLAT : PASS
6801 11:45:56.624350 RX DQ/DQS(Engine): PASS
6802 11:45:56.624432 TX OE : NO K
6803 11:45:56.627800 All Pass.
6804 11:45:56.627883
6805 11:45:56.627948 CH 0, Rank 1
6806 11:45:56.630624 SW Impedance : PASS
6807 11:45:56.630706 DUTY Scan : NO K
6808 11:45:56.634192 ZQ Calibration : PASS
6809 11:45:56.637442 Jitter Meter : NO K
6810 11:45:56.637525 CBT Training : PASS
6811 11:45:56.640524 Write leveling : NO K
6812 11:45:56.644296 RX DQS gating : PASS
6813 11:45:56.644378 RX DQ/DQS(RDDQC) : PASS
6814 11:45:56.647477 TX DQ/DQS : PASS
6815 11:45:56.650881 RX DATLAT : PASS
6816 11:45:56.650965 RX DQ/DQS(Engine): PASS
6817 11:45:56.654079 TX OE : NO K
6818 11:45:56.654182 All Pass.
6819 11:45:56.654274
6820 11:45:56.657352 CH 1, Rank 0
6821 11:45:56.657457 SW Impedance : PASS
6822 11:45:56.660785 DUTY Scan : NO K
6823 11:45:56.663897 ZQ Calibration : PASS
6824 11:45:56.664004 Jitter Meter : NO K
6825 11:45:56.667531 CBT Training : PASS
6826 11:45:56.670696 Write leveling : PASS
6827 11:45:56.670797 RX DQS gating : PASS
6828 11:45:56.673937 RX DQ/DQS(RDDQC) : PASS
6829 11:45:56.676994 TX DQ/DQS : PASS
6830 11:45:56.677095 RX DATLAT : PASS
6831 11:45:56.680699 RX DQ/DQS(Engine): PASS
6832 11:45:56.680772 TX OE : NO K
6833 11:45:56.683642 All Pass.
6834 11:45:56.683741
6835 11:45:56.683841 CH 1, Rank 1
6836 11:45:56.687063 SW Impedance : PASS
6837 11:45:56.687162 DUTY Scan : NO K
6838 11:45:56.690277 ZQ Calibration : PASS
6839 11:45:56.693820 Jitter Meter : NO K
6840 11:45:56.693921 CBT Training : PASS
6841 11:45:56.697165 Write leveling : NO K
6842 11:45:56.700632 RX DQS gating : PASS
6843 11:45:56.700704 RX DQ/DQS(RDDQC) : PASS
6844 11:45:56.703711 TX DQ/DQS : PASS
6845 11:45:56.707193 RX DATLAT : PASS
6846 11:45:56.707275 RX DQ/DQS(Engine): PASS
6847 11:45:56.710575 TX OE : NO K
6848 11:45:56.710658 All Pass.
6849 11:45:56.710724
6850 11:45:56.713859 DramC Write-DBI off
6851 11:45:56.716979 PER_BANK_REFRESH: Hybrid Mode
6852 11:45:56.717062 TX_TRACKING: ON
6853 11:45:56.727024 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6854 11:45:56.730510 [FAST_K] Save calibration result to emmc
6855 11:45:56.733940 dramc_set_vcore_voltage set vcore to 725000
6856 11:45:56.736914 Read voltage for 1600, 0
6857 11:45:56.736998 Vio18 = 0
6858 11:45:56.737064 Vcore = 725000
6859 11:45:56.740318 Vdram = 0
6860 11:45:56.740405 Vddq = 0
6861 11:45:56.740528 Vmddr = 0
6862 11:45:56.747334 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6863 11:45:56.750133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6864 11:45:56.753788 MEM_TYPE=3, freq_sel=13
6865 11:45:56.757224 sv_algorithm_assistance_LP4_3733
6866 11:45:56.760447 ============ PULL DRAM RESETB DOWN ============
6867 11:45:56.763956 ========== PULL DRAM RESETB DOWN end =========
6868 11:45:56.770167 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6869 11:45:56.773869 ===================================
6870 11:45:56.773985 LPDDR4 DRAM CONFIGURATION
6871 11:45:56.776999 ===================================
6872 11:45:56.780810 EX_ROW_EN[0] = 0x0
6873 11:45:56.783670 EX_ROW_EN[1] = 0x0
6874 11:45:56.783781 LP4Y_EN = 0x0
6875 11:45:56.786909 WORK_FSP = 0x1
6876 11:45:56.787010 WL = 0x5
6877 11:45:56.790236 RL = 0x5
6878 11:45:56.790311 BL = 0x2
6879 11:45:56.793741 RPST = 0x0
6880 11:45:56.793820 RD_PRE = 0x0
6881 11:45:56.796627 WR_PRE = 0x1
6882 11:45:56.796695 WR_PST = 0x1
6883 11:45:56.799857 DBI_WR = 0x0
6884 11:45:56.799932 DBI_RD = 0x0
6885 11:45:56.803327 OTF = 0x1
6886 11:45:56.807068 ===================================
6887 11:45:56.810161 ===================================
6888 11:45:56.810241 ANA top config
6889 11:45:56.813488 ===================================
6890 11:45:56.816785 DLL_ASYNC_EN = 0
6891 11:45:56.819815 ALL_SLAVE_EN = 0
6892 11:45:56.823414 NEW_RANK_MODE = 1
6893 11:45:56.823518 DLL_IDLE_MODE = 1
6894 11:45:56.826383 LP45_APHY_COMB_EN = 1
6895 11:45:56.829909 TX_ODT_DIS = 0
6896 11:45:56.833363 NEW_8X_MODE = 1
6897 11:45:56.836542 ===================================
6898 11:45:56.839918 ===================================
6899 11:45:56.843409 data_rate = 3200
6900 11:45:56.843489 CKR = 1
6901 11:45:56.846537 DQ_P2S_RATIO = 8
6902 11:45:56.849770 ===================================
6903 11:45:56.853236 CA_P2S_RATIO = 8
6904 11:45:56.856489 DQ_CA_OPEN = 0
6905 11:45:56.860415 DQ_SEMI_OPEN = 0
6906 11:45:56.863279 CA_SEMI_OPEN = 0
6907 11:45:56.863381 CA_FULL_RATE = 0
6908 11:45:56.866468 DQ_CKDIV4_EN = 0
6909 11:45:56.869892 CA_CKDIV4_EN = 0
6910 11:45:56.873124 CA_PREDIV_EN = 0
6911 11:45:56.876299 PH8_DLY = 12
6912 11:45:56.879426 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6913 11:45:56.879534 DQ_AAMCK_DIV = 4
6914 11:45:56.882737 CA_AAMCK_DIV = 4
6915 11:45:56.886072 CA_ADMCK_DIV = 4
6916 11:45:56.889535 DQ_TRACK_CA_EN = 0
6917 11:45:56.893081 CA_PICK = 1600
6918 11:45:56.896072 CA_MCKIO = 1600
6919 11:45:56.899646 MCKIO_SEMI = 0
6920 11:45:56.899725 PLL_FREQ = 3068
6921 11:45:56.903070 DQ_UI_PI_RATIO = 32
6922 11:45:56.905974 CA_UI_PI_RATIO = 0
6923 11:45:56.909686 ===================================
6924 11:45:56.912537 ===================================
6925 11:45:56.916141 memory_type:LPDDR4
6926 11:45:56.919425 GP_NUM : 10
6927 11:45:56.919529 SRAM_EN : 1
6928 11:45:56.922936 MD32_EN : 0
6929 11:45:56.925868 ===================================
6930 11:45:56.925947 [ANA_INIT] >>>>>>>>>>>>>>
6931 11:45:56.929474 <<<<<< [CONFIGURE PHASE]: ANA_TX
6932 11:45:56.932468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6933 11:45:56.936045 ===================================
6934 11:45:56.939016 data_rate = 3200,PCW = 0X7600
6935 11:45:56.942511 ===================================
6936 11:45:56.945434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6937 11:45:56.952157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6938 11:45:56.959054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6939 11:45:56.962636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6940 11:45:56.965486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6941 11:45:56.969037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6942 11:45:56.972392 [ANA_INIT] flow start
6943 11:45:56.972526 [ANA_INIT] PLL >>>>>>>>
6944 11:45:56.975498 [ANA_INIT] PLL <<<<<<<<
6945 11:45:56.979356 [ANA_INIT] MIDPI >>>>>>>>
6946 11:45:56.979459 [ANA_INIT] MIDPI <<<<<<<<
6947 11:45:56.982508 [ANA_INIT] DLL >>>>>>>>
6948 11:45:56.985438 [ANA_INIT] DLL <<<<<<<<
6949 11:45:56.985541 [ANA_INIT] flow end
6950 11:45:56.992211 ============ LP4 DIFF to SE enter ============
6951 11:45:56.995415 ============ LP4 DIFF to SE exit ============
6952 11:45:56.999408 [ANA_INIT] <<<<<<<<<<<<<
6953 11:45:57.002473 [Flow] Enable top DCM control >>>>>
6954 11:45:57.005473 [Flow] Enable top DCM control <<<<<
6955 11:45:57.005555 Enable DLL master slave shuffle
6956 11:45:57.012184 ==============================================================
6957 11:45:57.015330 Gating Mode config
6958 11:45:57.018587 ==============================================================
6959 11:45:57.021795 Config description:
6960 11:45:57.031820 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6961 11:45:57.038598 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6962 11:45:57.041733 SELPH_MODE 0: By rank 1: By Phase
6963 11:45:57.048366 ==============================================================
6964 11:45:57.051724 GAT_TRACK_EN = 1
6965 11:45:57.055128 RX_GATING_MODE = 2
6966 11:45:57.058528 RX_GATING_TRACK_MODE = 2
6967 11:45:57.061435 SELPH_MODE = 1
6968 11:45:57.061515 PICG_EARLY_EN = 1
6969 11:45:57.065175 VALID_LAT_VALUE = 1
6970 11:45:57.071456 ==============================================================
6971 11:45:57.074744 Enter into Gating configuration >>>>
6972 11:45:57.078291 Exit from Gating configuration <<<<
6973 11:45:57.081356 Enter into DVFS_PRE_config >>>>>
6974 11:45:57.091155 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6975 11:45:57.094590 Exit from DVFS_PRE_config <<<<<
6976 11:45:57.097832 Enter into PICG configuration >>>>
6977 11:45:57.101431 Exit from PICG configuration <<<<
6978 11:45:57.104551 [RX_INPUT] configuration >>>>>
6979 11:45:57.108069 [RX_INPUT] configuration <<<<<
6980 11:45:57.111214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6981 11:45:57.117977 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6982 11:45:57.124454 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6983 11:45:57.130820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6984 11:45:57.137377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6985 11:45:57.144338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6986 11:45:57.147839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6987 11:45:57.151069 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6988 11:45:57.153964 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6989 11:45:57.160656 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6990 11:45:57.163866 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6991 11:45:57.167142 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6992 11:45:57.170517 ===================================
6993 11:45:57.173594 LPDDR4 DRAM CONFIGURATION
6994 11:45:57.177145 ===================================
6995 11:45:57.177217 EX_ROW_EN[0] = 0x0
6996 11:45:57.180455 EX_ROW_EN[1] = 0x0
6997 11:45:57.183892 LP4Y_EN = 0x0
6998 11:45:57.183967 WORK_FSP = 0x1
6999 11:45:57.186910 WL = 0x5
7000 11:45:57.187008 RL = 0x5
7001 11:45:57.190347 BL = 0x2
7002 11:45:57.190426 RPST = 0x0
7003 11:45:57.193777 RD_PRE = 0x0
7004 11:45:57.193848 WR_PRE = 0x1
7005 11:45:57.196865 WR_PST = 0x1
7006 11:45:57.196938 DBI_WR = 0x0
7007 11:45:57.200245 DBI_RD = 0x0
7008 11:45:57.200348 OTF = 0x1
7009 11:45:57.203586 ===================================
7010 11:45:57.207611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7011 11:45:57.213743 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7012 11:45:57.216695 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7013 11:45:57.220600 ===================================
7014 11:45:57.223812 LPDDR4 DRAM CONFIGURATION
7015 11:45:57.226740 ===================================
7016 11:45:57.226842 EX_ROW_EN[0] = 0x10
7017 11:45:57.230442 EX_ROW_EN[1] = 0x0
7018 11:45:57.233227 LP4Y_EN = 0x0
7019 11:45:57.233326 WORK_FSP = 0x1
7020 11:45:57.236937 WL = 0x5
7021 11:45:57.237010 RL = 0x5
7022 11:45:57.239860 BL = 0x2
7023 11:45:57.239956 RPST = 0x0
7024 11:45:57.243562 RD_PRE = 0x0
7025 11:45:57.243664 WR_PRE = 0x1
7026 11:45:57.246950 WR_PST = 0x1
7027 11:45:57.247038 DBI_WR = 0x0
7028 11:45:57.250039 DBI_RD = 0x0
7029 11:45:57.250110 OTF = 0x1
7030 11:45:57.253482 ===================================
7031 11:45:57.259922 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7032 11:45:57.260067 ==
7033 11:45:57.263255 Dram Type= 6, Freq= 0, CH_0, rank 0
7034 11:45:57.266806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7035 11:45:57.266925 ==
7036 11:45:57.270293 [Duty_Offset_Calibration]
7037 11:45:57.273061 B0:0 B1:2 CA:1
7038 11:45:57.273144
7039 11:45:57.276447 [DutyScan_Calibration_Flow] k_type=0
7040 11:45:57.285346
7041 11:45:57.285460 ==CLK 0==
7042 11:45:57.288503 Final CLK duty delay cell = 0
7043 11:45:57.292054 [0] MAX Duty = 5156%(X100), DQS PI = 22
7044 11:45:57.295272 [0] MIN Duty = 4938%(X100), DQS PI = 50
7045 11:45:57.295385 [0] AVG Duty = 5047%(X100)
7046 11:45:57.298455
7047 11:45:57.301727 CH0 CLK Duty spec in!! Max-Min= 218%
7048 11:45:57.305321 [DutyScan_Calibration_Flow] ====Done====
7049 11:45:57.305397
7050 11:45:57.308136 [DutyScan_Calibration_Flow] k_type=1
7051 11:45:57.324551
7052 11:45:57.324672 ==DQS 0 ==
7053 11:45:57.328064 Final DQS duty delay cell = -4
7054 11:45:57.330973 [-4] MAX Duty = 4969%(X100), DQS PI = 4
7055 11:45:57.334387 [-4] MIN Duty = 4875%(X100), DQS PI = 8
7056 11:45:57.337803 [-4] AVG Duty = 4922%(X100)
7057 11:45:57.337910
7058 11:45:57.337974 ==DQS 1 ==
7059 11:45:57.341284 Final DQS duty delay cell = 0
7060 11:45:57.344283 [0] MAX Duty = 5031%(X100), DQS PI = 2
7061 11:45:57.347840 [0] MIN Duty = 4876%(X100), DQS PI = 16
7062 11:45:57.351415 [0] AVG Duty = 4953%(X100)
7063 11:45:57.351487
7064 11:45:57.354112 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7065 11:45:57.354185
7066 11:45:57.357638 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7067 11:45:57.361232 [DutyScan_Calibration_Flow] ====Done====
7068 11:45:57.361313
7069 11:45:57.364384 [DutyScan_Calibration_Flow] k_type=3
7070 11:45:57.381929
7071 11:45:57.382014 ==DQM 0 ==
7072 11:45:57.385040 Final DQM duty delay cell = 0
7073 11:45:57.388101 [0] MAX Duty = 5187%(X100), DQS PI = 22
7074 11:45:57.391770 [0] MIN Duty = 4907%(X100), DQS PI = 42
7075 11:45:57.395083 [0] AVG Duty = 5047%(X100)
7076 11:45:57.395161
7077 11:45:57.395225 ==DQM 1 ==
7078 11:45:57.398059 Final DQM duty delay cell = 0
7079 11:45:57.401266 [0] MAX Duty = 5031%(X100), DQS PI = 4
7080 11:45:57.404673 [0] MIN Duty = 4782%(X100), DQS PI = 14
7081 11:45:57.407955 [0] AVG Duty = 4906%(X100)
7082 11:45:57.408029
7083 11:45:57.411692 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7084 11:45:57.411775
7085 11:45:57.414718 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7086 11:45:57.418237 [DutyScan_Calibration_Flow] ====Done====
7087 11:45:57.418309
7088 11:45:57.421168 [DutyScan_Calibration_Flow] k_type=2
7089 11:45:57.437831
7090 11:45:57.437916 ==DQ 0 ==
7091 11:45:57.441378 Final DQ duty delay cell = 0
7092 11:45:57.444411 [0] MAX Duty = 5218%(X100), DQS PI = 18
7093 11:45:57.448087 [0] MIN Duty = 4938%(X100), DQS PI = 56
7094 11:45:57.448161 [0] AVG Duty = 5078%(X100)
7095 11:45:57.451083
7096 11:45:57.451153 ==DQ 1 ==
7097 11:45:57.454705 Final DQ duty delay cell = -4
7098 11:45:57.458216 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7099 11:45:57.461121 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7100 11:45:57.464643 [-4] AVG Duty = 4953%(X100)
7101 11:45:57.464721
7102 11:45:57.467910 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7103 11:45:57.467985
7104 11:45:57.471233 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7105 11:45:57.474823 [DutyScan_Calibration_Flow] ====Done====
7106 11:45:57.474905 ==
7107 11:45:57.477868 Dram Type= 6, Freq= 0, CH_1, rank 0
7108 11:45:57.481188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7109 11:45:57.481272 ==
7110 11:45:57.484227 [Duty_Offset_Calibration]
7111 11:45:57.484309 B0:0 B1:4 CA:-5
7112 11:45:57.484375
7113 11:45:57.487406 [DutyScan_Calibration_Flow] k_type=0
7114 11:45:57.498606
7115 11:45:57.498687 ==CLK 0==
7116 11:45:57.502084 Final CLK duty delay cell = 0
7117 11:45:57.505456 [0] MAX Duty = 5156%(X100), DQS PI = 20
7118 11:45:57.508623 [0] MIN Duty = 4906%(X100), DQS PI = 50
7119 11:45:57.508722 [0] AVG Duty = 5031%(X100)
7120 11:45:57.512172
7121 11:45:57.515079 CH1 CLK Duty spec in!! Max-Min= 250%
7122 11:45:57.518543 [DutyScan_Calibration_Flow] ====Done====
7123 11:45:57.518622
7124 11:45:57.521637 [DutyScan_Calibration_Flow] k_type=1
7125 11:45:57.537399
7126 11:45:57.537479 ==DQS 0 ==
7127 11:45:57.540733 Final DQS duty delay cell = 0
7128 11:45:57.544368 [0] MAX Duty = 5156%(X100), DQS PI = 18
7129 11:45:57.547479 [0] MIN Duty = 4844%(X100), DQS PI = 44
7130 11:45:57.550632 [0] AVG Duty = 5000%(X100)
7131 11:45:57.550719
7132 11:45:57.550783 ==DQS 1 ==
7133 11:45:57.554276 Final DQS duty delay cell = -4
7134 11:45:57.558011 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7135 11:45:57.560768 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7136 11:45:57.563962 [-4] AVG Duty = 4937%(X100)
7137 11:45:57.564051
7138 11:45:57.567746 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7139 11:45:57.567820
7140 11:45:57.571072 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7141 11:45:57.573921 [DutyScan_Calibration_Flow] ====Done====
7142 11:45:57.573994
7143 11:45:57.577100 [DutyScan_Calibration_Flow] k_type=3
7144 11:45:57.592966
7145 11:45:57.593075 ==DQM 0 ==
7146 11:45:57.596576 Final DQM duty delay cell = -4
7147 11:45:57.600007 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7148 11:45:57.603181 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7149 11:45:57.606402 [-4] AVG Duty = 4937%(X100)
7150 11:45:57.606473
7151 11:45:57.606534 ==DQM 1 ==
7152 11:45:57.609784 Final DQM duty delay cell = -4
7153 11:45:57.612960 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7154 11:45:57.616419 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7155 11:45:57.619852 [-4] AVG Duty = 5000%(X100)
7156 11:45:57.619925
7157 11:45:57.622732 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7158 11:45:57.622815
7159 11:45:57.626165 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7160 11:45:57.629745 [DutyScan_Calibration_Flow] ====Done====
7161 11:45:57.629821
7162 11:45:57.632823 [DutyScan_Calibration_Flow] k_type=2
7163 11:45:57.650732
7164 11:45:57.650814 ==DQ 0 ==
7165 11:45:57.654125 Final DQ duty delay cell = 0
7166 11:45:57.657457 [0] MAX Duty = 5093%(X100), DQS PI = 18
7167 11:45:57.660819 [0] MIN Duty = 4969%(X100), DQS PI = 46
7168 11:45:57.660898 [0] AVG Duty = 5031%(X100)
7169 11:45:57.663906
7170 11:45:57.664016 ==DQ 1 ==
7171 11:45:57.667711 Final DQ duty delay cell = 0
7172 11:45:57.670561 [0] MAX Duty = 5031%(X100), DQS PI = 4
7173 11:45:57.674236 [0] MIN Duty = 4907%(X100), DQS PI = 14
7174 11:45:57.674344 [0] AVG Duty = 4969%(X100)
7175 11:45:57.674437
7176 11:45:57.677553 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7177 11:45:57.681002
7178 11:45:57.684268 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7179 11:45:57.687260 [DutyScan_Calibration_Flow] ====Done====
7180 11:45:57.690914 nWR fixed to 30
7181 11:45:57.691015 [ModeRegInit_LP4] CH0 RK0
7182 11:45:57.694080 [ModeRegInit_LP4] CH0 RK1
7183 11:45:57.697463 [ModeRegInit_LP4] CH1 RK0
7184 11:45:57.700648 [ModeRegInit_LP4] CH1 RK1
7185 11:45:57.700748 match AC timing 4
7186 11:45:57.706926 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7187 11:45:57.710321 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7188 11:45:57.714030 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7189 11:45:57.720344 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7190 11:45:57.723629 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7191 11:45:57.723740 [MiockJmeterHQA]
7192 11:45:57.723836
7193 11:45:57.726999 [DramcMiockJmeter] u1RxGatingPI = 0
7194 11:45:57.730294 0 : 4252, 4027
7195 11:45:57.730371 4 : 4363, 4137
7196 11:45:57.733434 8 : 4250, 4026
7197 11:45:57.733510 12 : 4363, 4137
7198 11:45:57.733593 16 : 4255, 4029
7199 11:45:57.736679 20 : 4252, 4027
7200 11:45:57.736770 24 : 4253, 4026
7201 11:45:57.739974 28 : 4255, 4029
7202 11:45:57.740078 32 : 4360, 4138
7203 11:45:57.743263 36 : 4252, 4027
7204 11:45:57.743371 40 : 4250, 4027
7205 11:45:57.747091 44 : 4250, 4027
7206 11:45:57.747168 48 : 4252, 4029
7207 11:45:57.747232 52 : 4250, 4027
7208 11:45:57.750069 56 : 4361, 4137
7209 11:45:57.750142 60 : 4360, 4137
7210 11:45:57.753416 64 : 4250, 4027
7211 11:45:57.753524 68 : 4250, 4026
7212 11:45:57.756676 72 : 4250, 4027
7213 11:45:57.756781 76 : 4250, 4027
7214 11:45:57.759890 80 : 4253, 4029
7215 11:45:57.760003 84 : 4361, 4137
7216 11:45:57.760105 88 : 4250, 4027
7217 11:45:57.763387 92 : 4250, 4026
7218 11:45:57.763491 96 : 4253, 4027
7219 11:45:57.766551 100 : 4252, 2264
7220 11:45:57.766657 104 : 4250, 0
7221 11:45:57.769732 108 : 4250, 0
7222 11:45:57.769837 112 : 4250, 0
7223 11:45:57.769933 116 : 4252, 0
7224 11:45:57.772955 120 : 4249, 0
7225 11:45:57.773061 124 : 4250, 0
7226 11:45:57.773155 128 : 4250, 0
7227 11:45:57.776351 132 : 4252, 0
7228 11:45:57.776456 136 : 4361, 0
7229 11:45:57.780038 140 : 4360, 0
7230 11:45:57.780141 144 : 4363, 0
7231 11:45:57.780237 148 : 4250, 0
7232 11:45:57.783128 152 : 4361, 0
7233 11:45:57.783228 156 : 4250, 0
7234 11:45:57.786741 160 : 4250, 0
7235 11:45:57.786843 164 : 4250, 0
7236 11:45:57.786940 168 : 4250, 0
7237 11:45:57.789900 172 : 4253, 0
7238 11:45:57.790004 176 : 4250, 0
7239 11:45:57.792985 180 : 4250, 0
7240 11:45:57.793087 184 : 4252, 0
7241 11:45:57.793183 188 : 4360, 0
7242 11:45:57.796716 192 : 4360, 0
7243 11:45:57.796816 196 : 4363, 0
7244 11:45:57.799623 200 : 4250, 0
7245 11:45:57.799724 204 : 4250, 0
7246 11:45:57.799819 208 : 4250, 0
7247 11:45:57.802945 212 : 4250, 0
7248 11:45:57.803047 216 : 4249, 0
7249 11:45:57.806133 220 : 4250, 523
7250 11:45:57.806244 224 : 4250, 3998
7251 11:45:57.806340 228 : 4250, 4027
7252 11:45:57.809754 232 : 4361, 4138
7253 11:45:57.809855 236 : 4250, 4027
7254 11:45:57.812767 240 : 4249, 4027
7255 11:45:57.812852 244 : 4250, 4026
7256 11:45:57.816026 248 : 4253, 4029
7257 11:45:57.816143 252 : 4250, 4027
7258 11:45:57.819616 256 : 4250, 4027
7259 11:45:57.819720 260 : 4361, 4137
7260 11:45:57.823157 264 : 4250, 4026
7261 11:45:57.823230 268 : 4250, 4027
7262 11:45:57.826123 272 : 4361, 4137
7263 11:45:57.826227 276 : 4250, 4027
7264 11:45:57.829359 280 : 4250, 4027
7265 11:45:57.829467 284 : 4363, 4139
7266 11:45:57.832805 288 : 4250, 4026
7267 11:45:57.832908 292 : 4250, 4027
7268 11:45:57.833014 296 : 4250, 4027
7269 11:45:57.836122 300 : 4252, 4029
7270 11:45:57.836230 304 : 4250, 4027
7271 11:45:57.839467 308 : 4250, 4027
7272 11:45:57.839570 312 : 4361, 4137
7273 11:45:57.842651 316 : 4250, 4026
7274 11:45:57.842757 320 : 4250, 4027
7275 11:45:57.846030 324 : 4363, 4139
7276 11:45:57.846136 328 : 4250, 4027
7277 11:45:57.849300 332 : 4250, 4027
7278 11:45:57.849405 336 : 4363, 3957
7279 11:45:57.852626 340 : 4250, 1919
7280 11:45:57.852730
7281 11:45:57.852823 MIOCK jitter meter ch=0
7282 11:45:57.852912
7283 11:45:57.856181 1T = (340-104) = 236 dly cells
7284 11:45:57.862744 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7285 11:45:57.862829 ==
7286 11:45:57.866008 Dram Type= 6, Freq= 0, CH_0, rank 0
7287 11:45:57.869257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7288 11:45:57.869334 ==
7289 11:45:57.876135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7290 11:45:57.879113 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7291 11:45:57.882704 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7292 11:45:57.889501 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7293 11:45:57.897990 [CA 0] Center 42 (12~73) winsize 62
7294 11:45:57.901440 [CA 1] Center 42 (12~73) winsize 62
7295 11:45:57.904613 [CA 2] Center 39 (9~69) winsize 61
7296 11:45:57.908266 [CA 3] Center 38 (9~68) winsize 60
7297 11:45:57.911473 [CA 4] Center 37 (7~67) winsize 61
7298 11:45:57.914698 [CA 5] Center 36 (6~66) winsize 61
7299 11:45:57.914799
7300 11:45:57.917766 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7301 11:45:57.917866
7302 11:45:57.921183 [CATrainingPosCal] consider 1 rank data
7303 11:45:57.924440 u2DelayCellTimex100 = 275/100 ps
7304 11:45:57.930897 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7305 11:45:57.934377 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7306 11:45:57.937568 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7307 11:45:57.941414 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7308 11:45:57.944350 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7309 11:45:57.947693 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7310 11:45:57.947795
7311 11:45:57.950990 CA PerBit enable=1, Macro0, CA PI delay=36
7312 11:45:57.951092
7313 11:45:57.954230 [CBTSetCACLKResult] CA Dly = 36
7314 11:45:57.957686 CS Dly: 10 (0~41)
7315 11:45:57.961052 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7316 11:45:57.964341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7317 11:45:57.964444 ==
7318 11:45:57.967616 Dram Type= 6, Freq= 0, CH_0, rank 1
7319 11:45:57.971083 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7320 11:45:57.974328 ==
7321 11:45:57.977425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7322 11:45:57.980823 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7323 11:45:57.987389 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7324 11:45:57.994153 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7325 11:45:58.000577 [CA 0] Center 42 (12~73) winsize 62
7326 11:45:58.003985 [CA 1] Center 41 (11~72) winsize 62
7327 11:45:58.007591 [CA 2] Center 38 (8~68) winsize 61
7328 11:45:58.010644 [CA 3] Center 37 (7~67) winsize 61
7329 11:45:58.013730 [CA 4] Center 35 (5~65) winsize 61
7330 11:45:58.017361 [CA 5] Center 35 (5~66) winsize 62
7331 11:45:58.017469
7332 11:45:58.020885 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7333 11:45:58.020989
7334 11:45:58.023719 [CATrainingPosCal] consider 2 rank data
7335 11:45:58.027398 u2DelayCellTimex100 = 275/100 ps
7336 11:45:58.030499 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7337 11:45:58.037154 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7338 11:45:58.040915 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7339 11:45:58.043712 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7340 11:45:58.047473 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7341 11:45:58.050412 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7342 11:45:58.050514
7343 11:45:58.053476 CA PerBit enable=1, Macro0, CA PI delay=36
7344 11:45:58.053582
7345 11:45:58.056989 [CBTSetCACLKResult] CA Dly = 36
7346 11:45:58.060167 CS Dly: 11 (0~43)
7347 11:45:58.063825 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7348 11:45:58.066920 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7349 11:45:58.067023
7350 11:45:58.070170 ----->DramcWriteLeveling(PI) begin...
7351 11:45:58.070271 ==
7352 11:45:58.073608 Dram Type= 6, Freq= 0, CH_0, rank 0
7353 11:45:58.080118 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7354 11:45:58.080220 ==
7355 11:45:58.083606 Write leveling (Byte 0): 29 => 29
7356 11:45:58.083704 Write leveling (Byte 1): 25 => 25
7357 11:45:58.086804 DramcWriteLeveling(PI) end<-----
7358 11:45:58.086891
7359 11:45:58.090312 ==
7360 11:45:58.090424 Dram Type= 6, Freq= 0, CH_0, rank 0
7361 11:45:58.097279 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7362 11:45:58.097381 ==
7363 11:45:58.100294 [Gating] SW mode calibration
7364 11:45:58.106776 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7365 11:45:58.110004 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7366 11:45:58.117000 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7367 11:45:58.120211 0 12 4 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
7368 11:45:58.123372 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7369 11:45:58.129987 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7370 11:45:58.133391 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7371 11:45:58.136976 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7372 11:45:58.143050 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7373 11:45:58.146506 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7374 11:45:58.149875 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7375 11:45:58.156359 0 13 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
7376 11:45:58.159640 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7377 11:45:58.162953 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7378 11:45:58.169861 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7379 11:45:58.173332 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7380 11:45:58.176400 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7381 11:45:58.182959 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 11:45:58.186160 0 14 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7383 11:45:58.189477 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7384 11:45:58.196242 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7385 11:45:58.199334 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7386 11:45:58.202860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7387 11:45:58.209892 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7388 11:45:58.213180 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7389 11:45:58.216515 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 11:45:58.219313 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7391 11:45:58.226063 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7392 11:45:58.229124 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7393 11:45:58.235541 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7394 11:45:58.239324 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7395 11:45:58.242483 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7396 11:45:58.248689 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 11:45:58.252265 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 11:45:58.255656 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 11:45:58.262144 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 11:45:58.265343 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 11:45:58.268898 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 11:45:58.271975 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 11:45:58.278582 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 11:45:58.282315 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 11:45:58.285327 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7406 11:45:58.292163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7407 11:45:58.295425 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7408 11:45:58.298610 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7409 11:45:58.302035 Total UI for P1: 0, mck2ui 16
7410 11:45:58.305524 best dqsien dly found for B0: ( 1, 1, 0)
7411 11:45:58.312361 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7412 11:45:58.315070 Total UI for P1: 0, mck2ui 16
7413 11:45:58.318559 best dqsien dly found for B1: ( 1, 1, 6)
7414 11:45:58.321793 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7415 11:45:58.325042 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7416 11:45:58.325115
7417 11:45:58.328511 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7418 11:45:58.331431 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7419 11:45:58.334993 [Gating] SW calibration Done
7420 11:45:58.335096 ==
7421 11:45:58.337980 Dram Type= 6, Freq= 0, CH_0, rank 0
7422 11:45:58.341376 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7423 11:45:58.341478 ==
7424 11:45:58.344822 RX Vref Scan: 0
7425 11:45:58.344921
7426 11:45:58.345014 RX Vref 0 -> 0, step: 1
7427 11:45:58.345102
7428 11:45:58.348003 RX Delay 0 -> 252, step: 8
7429 11:45:58.351711 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7430 11:45:58.358256 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7431 11:45:58.361568 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7432 11:45:58.365036 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7433 11:45:58.367830 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7434 11:45:58.371052 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7435 11:45:58.378193 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7436 11:45:58.381401 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7437 11:45:58.384528 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7438 11:45:58.387559 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7439 11:45:58.390994 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7440 11:45:58.397821 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7441 11:45:58.400788 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7442 11:45:58.404516 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7443 11:45:58.407366 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7444 11:45:58.414324 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7445 11:45:58.414419 ==
7446 11:45:58.417214 Dram Type= 6, Freq= 0, CH_0, rank 0
7447 11:45:58.420727 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7448 11:45:58.420830 ==
7449 11:45:58.420925 DQS Delay:
7450 11:45:58.424353 DQS0 = 0, DQS1 = 0
7451 11:45:58.424454 DQM Delay:
7452 11:45:58.427893 DQM0 = 130, DQM1 = 124
7453 11:45:58.427992 DQ Delay:
7454 11:45:58.430681 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7455 11:45:58.433798 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7456 11:45:58.437408 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7457 11:45:58.440461 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7458 11:45:58.440572
7459 11:45:58.443915
7460 11:45:58.444034 ==
7461 11:45:58.447202 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 11:45:58.450441 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7463 11:45:58.450542 ==
7464 11:45:58.450634
7465 11:45:58.450723
7466 11:45:58.453692 TX Vref Scan disable
7467 11:45:58.453787 == TX Byte 0 ==
7468 11:45:58.460430 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7469 11:45:58.463682 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7470 11:45:58.463765 == TX Byte 1 ==
7471 11:45:58.470051 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7472 11:45:58.473605 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7473 11:45:58.473709 ==
7474 11:45:58.476758 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 11:45:58.480214 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7476 11:45:58.480314 ==
7477 11:45:58.493956
7478 11:45:58.497116 TX Vref early break, caculate TX vref
7479 11:45:58.500595 TX Vref=16, minBit 10, minWin=21, winSum=365
7480 11:45:58.503736 TX Vref=18, minBit 10, minWin=22, winSum=373
7481 11:45:58.507168 TX Vref=20, minBit 7, minWin=23, winSum=381
7482 11:45:58.510730 TX Vref=22, minBit 10, minWin=23, winSum=390
7483 11:45:58.517137 TX Vref=24, minBit 1, minWin=24, winSum=403
7484 11:45:58.520510 TX Vref=26, minBit 7, minWin=24, winSum=407
7485 11:45:58.523640 TX Vref=28, minBit 1, minWin=25, winSum=412
7486 11:45:58.526742 TX Vref=30, minBit 1, minWin=24, winSum=403
7487 11:45:58.530311 TX Vref=32, minBit 0, minWin=24, winSum=392
7488 11:45:58.533700 TX Vref=34, minBit 1, minWin=23, winSum=385
7489 11:45:58.540324 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 28
7490 11:45:58.540428
7491 11:45:58.543456 Final TX Range 0 Vref 28
7492 11:45:58.543567
7493 11:45:58.543661 ==
7494 11:45:58.546880 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 11:45:58.550183 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7496 11:45:58.550291 ==
7497 11:45:58.550390
7498 11:45:58.550479
7499 11:45:58.553581 TX Vref Scan disable
7500 11:45:58.559975 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7501 11:45:58.560085 == TX Byte 0 ==
7502 11:45:58.563241 u2DelayCellOfst[0]=14 cells (4 PI)
7503 11:45:58.566921 u2DelayCellOfst[1]=14 cells (4 PI)
7504 11:45:58.570111 u2DelayCellOfst[2]=10 cells (3 PI)
7505 11:45:58.573183 u2DelayCellOfst[3]=10 cells (3 PI)
7506 11:45:58.576420 u2DelayCellOfst[4]=7 cells (2 PI)
7507 11:45:58.580026 u2DelayCellOfst[5]=0 cells (0 PI)
7508 11:45:58.582951 u2DelayCellOfst[6]=17 cells (5 PI)
7509 11:45:58.586352 u2DelayCellOfst[7]=17 cells (5 PI)
7510 11:45:58.589729 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7511 11:45:58.593114 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7512 11:45:58.596574 == TX Byte 1 ==
7513 11:45:58.599684 u2DelayCellOfst[8]=3 cells (1 PI)
7514 11:45:58.603028 u2DelayCellOfst[9]=0 cells (0 PI)
7515 11:45:58.603124 u2DelayCellOfst[10]=10 cells (3 PI)
7516 11:45:58.606567 u2DelayCellOfst[11]=7 cells (2 PI)
7517 11:45:58.609851 u2DelayCellOfst[12]=14 cells (4 PI)
7518 11:45:58.612814 u2DelayCellOfst[13]=14 cells (4 PI)
7519 11:45:58.616362 u2DelayCellOfst[14]=17 cells (5 PI)
7520 11:45:58.619402 u2DelayCellOfst[15]=14 cells (4 PI)
7521 11:45:58.626101 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7522 11:45:58.629240 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7523 11:45:58.629341 DramC Write-DBI on
7524 11:45:58.629434 ==
7525 11:45:58.632656 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 11:45:58.639400 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7527 11:45:58.639502 ==
7528 11:45:58.639589
7529 11:45:58.639664
7530 11:45:58.639751 TX Vref Scan disable
7531 11:45:58.643912 == TX Byte 0 ==
7532 11:45:58.646701 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7533 11:45:58.650477 == TX Byte 1 ==
7534 11:45:58.653432 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7535 11:45:58.656731 DramC Write-DBI off
7536 11:45:58.656836
7537 11:45:58.656932 [DATLAT]
7538 11:45:58.657022 Freq=1600, CH0 RK0
7539 11:45:58.657113
7540 11:45:58.659883 DATLAT Default: 0xf
7541 11:45:58.663312 0, 0xFFFF, sum = 0
7542 11:45:58.663418 1, 0xFFFF, sum = 0
7543 11:45:58.666417 2, 0xFFFF, sum = 0
7544 11:45:58.666522 3, 0xFFFF, sum = 0
7545 11:45:58.670257 4, 0xFFFF, sum = 0
7546 11:45:58.670375 5, 0xFFFF, sum = 0
7547 11:45:58.673533 6, 0xFFFF, sum = 0
7548 11:45:58.673635 7, 0xFFFF, sum = 0
7549 11:45:58.676465 8, 0xFFFF, sum = 0
7550 11:45:58.676588 9, 0xFFFF, sum = 0
7551 11:45:58.679788 10, 0xFFFF, sum = 0
7552 11:45:58.679886 11, 0xFFFF, sum = 0
7553 11:45:58.683164 12, 0xFFF, sum = 0
7554 11:45:58.683263 13, 0x0, sum = 1
7555 11:45:58.686463 14, 0x0, sum = 2
7556 11:45:58.686565 15, 0x0, sum = 3
7557 11:45:58.689998 16, 0x0, sum = 4
7558 11:45:58.690101 best_step = 14
7559 11:45:58.690204
7560 11:45:58.690299 ==
7561 11:45:58.693304 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 11:45:58.696361 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7563 11:45:58.699623 ==
7564 11:45:58.699696 RX Vref Scan: 1
7565 11:45:58.699761
7566 11:45:58.702862 Set Vref Range= 24 -> 127
7567 11:45:58.702931
7568 11:45:58.706199 RX Vref 24 -> 127, step: 1
7569 11:45:58.706268
7570 11:45:58.706327 RX Delay 11 -> 252, step: 4
7571 11:45:58.706388
7572 11:45:58.709793 Set Vref, RX VrefLevel [Byte0]: 24
7573 11:45:58.713035 [Byte1]: 24
7574 11:45:58.716799
7575 11:45:58.716907 Set Vref, RX VrefLevel [Byte0]: 25
7576 11:45:58.720040 [Byte1]: 25
7577 11:45:58.724601
7578 11:45:58.724703 Set Vref, RX VrefLevel [Byte0]: 26
7579 11:45:58.727788 [Byte1]: 26
7580 11:45:58.731934
7581 11:45:58.732033 Set Vref, RX VrefLevel [Byte0]: 27
7582 11:45:58.735725 [Byte1]: 27
7583 11:45:58.739600
7584 11:45:58.739701 Set Vref, RX VrefLevel [Byte0]: 28
7585 11:45:58.743096 [Byte1]: 28
7586 11:45:58.747382
7587 11:45:58.747483 Set Vref, RX VrefLevel [Byte0]: 29
7588 11:45:58.750513 [Byte1]: 29
7589 11:45:58.754866
7590 11:45:58.754967 Set Vref, RX VrefLevel [Byte0]: 30
7591 11:45:58.758213 [Byte1]: 30
7592 11:45:58.762913
7593 11:45:58.763017 Set Vref, RX VrefLevel [Byte0]: 31
7594 11:45:58.765765 [Byte1]: 31
7595 11:45:58.770293
7596 11:45:58.770397 Set Vref, RX VrefLevel [Byte0]: 32
7597 11:45:58.773628 [Byte1]: 32
7598 11:45:58.777706
7599 11:45:58.777804 Set Vref, RX VrefLevel [Byte0]: 33
7600 11:45:58.781133 [Byte1]: 33
7601 11:45:58.785198
7602 11:45:58.785290 Set Vref, RX VrefLevel [Byte0]: 34
7603 11:45:58.788845 [Byte1]: 34
7604 11:45:58.793167
7605 11:45:58.793250 Set Vref, RX VrefLevel [Byte0]: 35
7606 11:45:58.796604 [Byte1]: 35
7607 11:45:58.800804
7608 11:45:58.800908 Set Vref, RX VrefLevel [Byte0]: 36
7609 11:45:58.803716 [Byte1]: 36
7610 11:45:58.808153
7611 11:45:58.808260 Set Vref, RX VrefLevel [Byte0]: 37
7612 11:45:58.811645 [Byte1]: 37
7613 11:45:58.815770
7614 11:45:58.815875 Set Vref, RX VrefLevel [Byte0]: 38
7615 11:45:58.819233 [Byte1]: 38
7616 11:45:58.823690
7617 11:45:58.823796 Set Vref, RX VrefLevel [Byte0]: 39
7618 11:45:58.827005 [Byte1]: 39
7619 11:45:58.830933
7620 11:45:58.831036 Set Vref, RX VrefLevel [Byte0]: 40
7621 11:45:58.834548 [Byte1]: 40
7622 11:45:58.838454
7623 11:45:58.838557 Set Vref, RX VrefLevel [Byte0]: 41
7624 11:45:58.841991 [Byte1]: 41
7625 11:45:58.846180
7626 11:45:58.846292 Set Vref, RX VrefLevel [Byte0]: 42
7627 11:45:58.849862 [Byte1]: 42
7628 11:45:58.853790
7629 11:45:58.853895 Set Vref, RX VrefLevel [Byte0]: 43
7630 11:45:58.857628 [Byte1]: 43
7631 11:45:58.861572
7632 11:45:58.861679 Set Vref, RX VrefLevel [Byte0]: 44
7633 11:45:58.865339 [Byte1]: 44
7634 11:45:58.869399
7635 11:45:58.869483 Set Vref, RX VrefLevel [Byte0]: 45
7636 11:45:58.872329 [Byte1]: 45
7637 11:45:58.876591
7638 11:45:58.876692 Set Vref, RX VrefLevel [Byte0]: 46
7639 11:45:58.880019 [Byte1]: 46
7640 11:45:58.884559
7641 11:45:58.884664 Set Vref, RX VrefLevel [Byte0]: 47
7642 11:45:58.887506 [Byte1]: 47
7643 11:45:58.891982
7644 11:45:58.892082 Set Vref, RX VrefLevel [Byte0]: 48
7645 11:45:58.895102 [Byte1]: 48
7646 11:45:58.899546
7647 11:45:58.899645 Set Vref, RX VrefLevel [Byte0]: 49
7648 11:45:58.902798 [Byte1]: 49
7649 11:45:58.907272
7650 11:45:58.907367 Set Vref, RX VrefLevel [Byte0]: 50
7651 11:45:58.910480 [Byte1]: 50
7652 11:45:58.914578
7653 11:45:58.914678 Set Vref, RX VrefLevel [Byte0]: 51
7654 11:45:58.917991 [Byte1]: 51
7655 11:45:58.922639
7656 11:45:58.922738 Set Vref, RX VrefLevel [Byte0]: 52
7657 11:45:58.925760 [Byte1]: 52
7658 11:45:58.929907
7659 11:45:58.930009 Set Vref, RX VrefLevel [Byte0]: 53
7660 11:45:58.933449 [Byte1]: 53
7661 11:45:58.937671
7662 11:45:58.937769 Set Vref, RX VrefLevel [Byte0]: 54
7663 11:45:58.941305 [Byte1]: 54
7664 11:45:58.945566
7665 11:45:58.945663 Set Vref, RX VrefLevel [Byte0]: 55
7666 11:45:58.948489 [Byte1]: 55
7667 11:45:58.953094
7668 11:45:58.953166 Set Vref, RX VrefLevel [Byte0]: 56
7669 11:45:58.956128 [Byte1]: 56
7670 11:45:58.960423
7671 11:45:58.960559 Set Vref, RX VrefLevel [Byte0]: 57
7672 11:45:58.963819 [Byte1]: 57
7673 11:45:58.968285
7674 11:45:58.968387 Set Vref, RX VrefLevel [Byte0]: 58
7675 11:45:58.971367 [Byte1]: 58
7676 11:45:58.975745
7677 11:45:58.975842 Set Vref, RX VrefLevel [Byte0]: 59
7678 11:45:58.978883 [Byte1]: 59
7679 11:45:58.983278
7680 11:45:58.983376 Set Vref, RX VrefLevel [Byte0]: 60
7681 11:45:58.986476 [Byte1]: 60
7682 11:45:58.990882
7683 11:45:58.990984 Set Vref, RX VrefLevel [Byte0]: 61
7684 11:45:58.994123 [Byte1]: 61
7685 11:45:58.998459
7686 11:45:58.998565 Set Vref, RX VrefLevel [Byte0]: 62
7687 11:45:59.001780 [Byte1]: 62
7688 11:45:59.006147
7689 11:45:59.006246 Set Vref, RX VrefLevel [Byte0]: 63
7690 11:45:59.009441 [Byte1]: 63
7691 11:45:59.013948
7692 11:45:59.014055 Set Vref, RX VrefLevel [Byte0]: 64
7693 11:45:59.016935 [Byte1]: 64
7694 11:45:59.021456
7695 11:45:59.021557 Set Vref, RX VrefLevel [Byte0]: 65
7696 11:45:59.025094 [Byte1]: 65
7697 11:45:59.029066
7698 11:45:59.029145 Set Vref, RX VrefLevel [Byte0]: 66
7699 11:45:59.032280 [Byte1]: 66
7700 11:45:59.036530
7701 11:45:59.036654 Set Vref, RX VrefLevel [Byte0]: 67
7702 11:45:59.039761 [Byte1]: 67
7703 11:45:59.044363
7704 11:45:59.044472 Set Vref, RX VrefLevel [Byte0]: 68
7705 11:45:59.047294 [Byte1]: 68
7706 11:45:59.051943
7707 11:45:59.052047 Set Vref, RX VrefLevel [Byte0]: 69
7708 11:45:59.055154 [Byte1]: 69
7709 11:45:59.059343
7710 11:45:59.059448 Set Vref, RX VrefLevel [Byte0]: 70
7711 11:45:59.062616 [Byte1]: 70
7712 11:45:59.067341
7713 11:45:59.067415 Set Vref, RX VrefLevel [Byte0]: 71
7714 11:45:59.070124 [Byte1]: 71
7715 11:45:59.074711
7716 11:45:59.074815 Set Vref, RX VrefLevel [Byte0]: 72
7717 11:45:59.078002 [Byte1]: 72
7718 11:45:59.082239
7719 11:45:59.082341 Set Vref, RX VrefLevel [Byte0]: 73
7720 11:45:59.085507 [Byte1]: 73
7721 11:45:59.089912
7722 11:45:59.090014 Set Vref, RX VrefLevel [Byte0]: 74
7723 11:45:59.093247 [Byte1]: 74
7724 11:45:59.097369
7725 11:45:59.097468 Final RX Vref Byte 0 = 53 to rank0
7726 11:45:59.100948 Final RX Vref Byte 1 = 56 to rank0
7727 11:45:59.104217 Final RX Vref Byte 0 = 53 to rank1
7728 11:45:59.107403 Final RX Vref Byte 1 = 56 to rank1==
7729 11:45:59.110670 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 11:45:59.117278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7731 11:45:59.117385 ==
7732 11:45:59.117481 DQS Delay:
7733 11:45:59.120684 DQS0 = 0, DQS1 = 0
7734 11:45:59.120782 DQM Delay:
7735 11:45:59.120872 DQM0 = 127, DQM1 = 121
7736 11:45:59.123924 DQ Delay:
7737 11:45:59.127344 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7738 11:45:59.130779 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7739 11:45:59.133891 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7740 11:45:59.136978 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7741 11:45:59.137080
7742 11:45:59.137173
7743 11:45:59.137263
7744 11:45:59.140258 [DramC_TX_OE_Calibration] TA2
7745 11:45:59.143666 Original DQ_B0 (3 6) =30, OEN = 27
7746 11:45:59.146844 Original DQ_B1 (3 6) =30, OEN = 27
7747 11:45:59.150386 24, 0x0, End_B0=24 End_B1=24
7748 11:45:59.150490 25, 0x0, End_B0=25 End_B1=25
7749 11:45:59.154017 26, 0x0, End_B0=26 End_B1=26
7750 11:45:59.156980 27, 0x0, End_B0=27 End_B1=27
7751 11:45:59.160131 28, 0x0, End_B0=28 End_B1=28
7752 11:45:59.163655 29, 0x0, End_B0=29 End_B1=29
7753 11:45:59.163740 30, 0x0, End_B0=30 End_B1=30
7754 11:45:59.166528 31, 0x4141, End_B0=30 End_B1=30
7755 11:45:59.170186 Byte0 end_step=30 best_step=27
7756 11:45:59.173263 Byte1 end_step=30 best_step=27
7757 11:45:59.176718 Byte0 TX OE(2T, 0.5T) = (3, 3)
7758 11:45:59.180048 Byte1 TX OE(2T, 0.5T) = (3, 3)
7759 11:45:59.180142
7760 11:45:59.180235
7761 11:45:59.186579 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7762 11:45:59.189826 CH0 RK0: MR19=303, MR18=1818
7763 11:45:59.196376 CH0_RK0: MR19=0x303, MR18=0x1818, DQSOSC=397, MR23=63, INC=23, DEC=15
7764 11:45:59.196479
7765 11:45:59.199812 ----->DramcWriteLeveling(PI) begin...
7766 11:45:59.199916 ==
7767 11:45:59.202914 Dram Type= 6, Freq= 0, CH_0, rank 1
7768 11:45:59.206413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7769 11:45:59.206514 ==
7770 11:45:59.209967 Write leveling (Byte 0): 31 => 31
7771 11:45:59.213119 Write leveling (Byte 1): 26 => 26
7772 11:45:59.216389 DramcWriteLeveling(PI) end<-----
7773 11:45:59.216500
7774 11:45:59.216618 ==
7775 11:45:59.219487 Dram Type= 6, Freq= 0, CH_0, rank 1
7776 11:45:59.223122 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7777 11:45:59.226344 ==
7778 11:45:59.226444 [Gating] SW mode calibration
7779 11:45:59.233010 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7780 11:45:59.239328 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7781 11:45:59.242896 0 12 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7782 11:45:59.249422 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7783 11:45:59.252759 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7784 11:45:59.255892 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7785 11:45:59.262429 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7786 11:45:59.265926 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7787 11:45:59.269335 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7788 11:45:59.276144 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7789 11:45:59.279260 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7790 11:45:59.282650 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7791 11:45:59.289090 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7792 11:45:59.292638 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7793 11:45:59.295900 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 11:45:59.302326 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7795 11:45:59.305658 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7796 11:45:59.309126 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7797 11:45:59.315636 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7798 11:45:59.318992 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7799 11:45:59.322343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7800 11:45:59.329063 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 11:45:59.332338 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 11:45:59.335594 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7803 11:45:59.342027 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7804 11:45:59.345527 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7805 11:45:59.348758 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7806 11:45:59.355148 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7807 11:45:59.359028 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7808 11:45:59.362146 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 11:45:59.368830 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 11:45:59.371784 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 11:45:59.375526 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 11:45:59.381600 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 11:45:59.385153 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 11:45:59.387958 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 11:45:59.394885 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 11:45:59.398025 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 11:45:59.401365 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 11:45:59.407844 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 11:45:59.411148 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 11:45:59.414783 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7821 11:45:59.421169 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7822 11:45:59.424730 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7823 11:45:59.427841 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7824 11:45:59.431206 Total UI for P1: 0, mck2ui 16
7825 11:45:59.434406 best dqsien dly found for B0: ( 1, 1, 0)
7826 11:45:59.437657 Total UI for P1: 0, mck2ui 16
7827 11:45:59.441011 best dqsien dly found for B1: ( 1, 1, 2)
7828 11:45:59.444485 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7829 11:45:59.448169 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7830 11:45:59.448270
7831 11:45:59.451008 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7832 11:45:59.454166 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7833 11:45:59.457719 [Gating] SW calibration Done
7834 11:45:59.457823 ==
7835 11:45:59.461297 Dram Type= 6, Freq= 0, CH_0, rank 1
7836 11:45:59.467520 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7837 11:45:59.467603 ==
7838 11:45:59.467670 RX Vref Scan: 0
7839 11:45:59.467730
7840 11:45:59.470683 RX Vref 0 -> 0, step: 1
7841 11:45:59.470785
7842 11:45:59.474108 RX Delay 0 -> 252, step: 8
7843 11:45:59.477515 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7844 11:45:59.480495 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7845 11:45:59.483969 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7846 11:45:59.487563 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7847 11:45:59.494098 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7848 11:45:59.497239 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7849 11:45:59.500603 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7850 11:45:59.504370 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7851 11:45:59.507177 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7852 11:45:59.513932 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7853 11:45:59.517138 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7854 11:45:59.520509 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7855 11:45:59.523680 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7856 11:45:59.530032 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7857 11:45:59.533521 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7858 11:45:59.536736 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7859 11:45:59.536823 ==
7860 11:45:59.540091 Dram Type= 6, Freq= 0, CH_0, rank 1
7861 11:45:59.543604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7862 11:45:59.543706 ==
7863 11:45:59.546809 DQS Delay:
7864 11:45:59.546908 DQS0 = 0, DQS1 = 0
7865 11:45:59.550142 DQM Delay:
7866 11:45:59.550219 DQM0 = 131, DQM1 = 124
7867 11:45:59.550288 DQ Delay:
7868 11:45:59.556477 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7869 11:45:59.560030 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7870 11:45:59.563297 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7871 11:45:59.566614 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7872 11:45:59.566716
7873 11:45:59.566810
7874 11:45:59.566902 ==
7875 11:45:59.570022 Dram Type= 6, Freq= 0, CH_0, rank 1
7876 11:45:59.573121 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7877 11:45:59.573225 ==
7878 11:45:59.573317
7879 11:45:59.573408
7880 11:45:59.576709 TX Vref Scan disable
7881 11:45:59.579813 == TX Byte 0 ==
7882 11:45:59.583203 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7883 11:45:59.586465 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7884 11:45:59.589951 == TX Byte 1 ==
7885 11:45:59.593439 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7886 11:45:59.596391 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7887 11:45:59.596488 ==
7888 11:45:59.599549 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 11:45:59.606512 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 11:45:59.606617 ==
7891 11:45:59.619258
7892 11:45:59.622875 TX Vref early break, caculate TX vref
7893 11:45:59.625951 TX Vref=16, minBit 7, minWin=21, winSum=364
7894 11:45:59.629306 TX Vref=18, minBit 1, minWin=22, winSum=374
7895 11:45:59.632491 TX Vref=20, minBit 1, minWin=22, winSum=380
7896 11:45:59.635769 TX Vref=22, minBit 1, minWin=23, winSum=390
7897 11:45:59.639306 TX Vref=24, minBit 1, minWin=23, winSum=394
7898 11:45:59.645906 TX Vref=26, minBit 1, minWin=24, winSum=402
7899 11:45:59.649226 TX Vref=28, minBit 2, minWin=24, winSum=406
7900 11:45:59.652240 TX Vref=30, minBit 0, minWin=24, winSum=401
7901 11:45:59.655800 TX Vref=32, minBit 7, minWin=23, winSum=397
7902 11:45:59.659008 TX Vref=34, minBit 1, minWin=23, winSum=388
7903 11:45:59.662282 TX Vref=36, minBit 1, minWin=22, winSum=375
7904 11:45:59.669231 [TxChooseVref] Worse bit 2, Min win 24, Win sum 406, Final Vref 28
7905 11:45:59.669339
7906 11:45:59.672344 Final TX Range 0 Vref 28
7907 11:45:59.672448
7908 11:45:59.672589 ==
7909 11:45:59.675643 Dram Type= 6, Freq= 0, CH_0, rank 1
7910 11:45:59.678739 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7911 11:45:59.678840 ==
7912 11:45:59.678932
7913 11:45:59.682179
7914 11:45:59.682278 TX Vref Scan disable
7915 11:45:59.688783 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7916 11:45:59.688885 == TX Byte 0 ==
7917 11:45:59.692135 u2DelayCellOfst[0]=10 cells (3 PI)
7918 11:45:59.695520 u2DelayCellOfst[1]=17 cells (5 PI)
7919 11:45:59.699105 u2DelayCellOfst[2]=10 cells (3 PI)
7920 11:45:59.702228 u2DelayCellOfst[3]=14 cells (4 PI)
7921 11:45:59.705270 u2DelayCellOfst[4]=7 cells (2 PI)
7922 11:45:59.708514 u2DelayCellOfst[5]=0 cells (0 PI)
7923 11:45:59.711908 u2DelayCellOfst[6]=17 cells (5 PI)
7924 11:45:59.715483 u2DelayCellOfst[7]=17 cells (5 PI)
7925 11:45:59.718332 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7926 11:45:59.721889 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7927 11:45:59.725331 == TX Byte 1 ==
7928 11:45:59.728347 u2DelayCellOfst[8]=3 cells (1 PI)
7929 11:45:59.731856 u2DelayCellOfst[9]=0 cells (0 PI)
7930 11:45:59.735219 u2DelayCellOfst[10]=14 cells (4 PI)
7931 11:45:59.738208 u2DelayCellOfst[11]=7 cells (2 PI)
7932 11:45:59.741853 u2DelayCellOfst[12]=17 cells (5 PI)
7933 11:45:59.741928 u2DelayCellOfst[13]=17 cells (5 PI)
7934 11:45:59.744881 u2DelayCellOfst[14]=21 cells (6 PI)
7935 11:45:59.748363 u2DelayCellOfst[15]=17 cells (5 PI)
7936 11:45:59.755344 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7937 11:45:59.758561 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7938 11:45:59.758666 DramC Write-DBI on
7939 11:45:59.761774 ==
7940 11:45:59.764834 Dram Type= 6, Freq= 0, CH_0, rank 1
7941 11:45:59.768470 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7942 11:45:59.768608 ==
7943 11:45:59.768701
7944 11:45:59.768793
7945 11:45:59.771360 TX Vref Scan disable
7946 11:45:59.771476 == TX Byte 0 ==
7947 11:45:59.777830 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7948 11:45:59.777936 == TX Byte 1 ==
7949 11:45:59.781269 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7950 11:45:59.784542 DramC Write-DBI off
7951 11:45:59.784631
7952 11:45:59.784693 [DATLAT]
7953 11:45:59.787767 Freq=1600, CH0 RK1
7954 11:45:59.787838
7955 11:45:59.787898 DATLAT Default: 0xe
7956 11:45:59.791462 0, 0xFFFF, sum = 0
7957 11:45:59.791563 1, 0xFFFF, sum = 0
7958 11:45:59.794298 2, 0xFFFF, sum = 0
7959 11:45:59.794370 3, 0xFFFF, sum = 0
7960 11:45:59.797519 4, 0xFFFF, sum = 0
7961 11:45:59.801078 5, 0xFFFF, sum = 0
7962 11:45:59.801178 6, 0xFFFF, sum = 0
7963 11:45:59.804287 7, 0xFFFF, sum = 0
7964 11:45:59.804386 8, 0xFFFF, sum = 0
7965 11:45:59.807569 9, 0xFFFF, sum = 0
7966 11:45:59.807661 10, 0xFFFF, sum = 0
7967 11:45:59.810953 11, 0xFFFF, sum = 0
7968 11:45:59.811048 12, 0x8FFF, sum = 0
7969 11:45:59.814290 13, 0x0, sum = 1
7970 11:45:59.814380 14, 0x0, sum = 2
7971 11:45:59.817952 15, 0x0, sum = 3
7972 11:45:59.818034 16, 0x0, sum = 4
7973 11:45:59.820885 best_step = 14
7974 11:45:59.820989
7975 11:45:59.821081 ==
7976 11:45:59.824096 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 11:45:59.827847 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7978 11:45:59.827948 ==
7979 11:45:59.828042 RX Vref Scan: 0
7980 11:45:59.828130
7981 11:45:59.830780 RX Vref 0 -> 0, step: 1
7982 11:45:59.830881
7983 11:45:59.834056 RX Delay 11 -> 252, step: 4
7984 11:45:59.837459 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7985 11:45:59.844289 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7986 11:45:59.847589 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7987 11:45:59.850930 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7988 11:45:59.854026 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7989 11:45:59.857592 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7990 11:45:59.863972 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7991 11:45:59.867501 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7992 11:45:59.870828 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7993 11:45:59.873694 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7994 11:45:59.877273 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7995 11:45:59.883648 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7996 11:45:59.887078 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7997 11:45:59.890131 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7998 11:45:59.893621 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7999 11:45:59.900467 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8000 11:45:59.900577 ==
8001 11:45:59.903557 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 11:45:59.906698 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8003 11:45:59.906798 ==
8004 11:45:59.906900 DQS Delay:
8005 11:45:59.910170 DQS0 = 0, DQS1 = 0
8006 11:45:59.910274 DQM Delay:
8007 11:45:59.913372 DQM0 = 128, DQM1 = 120
8008 11:45:59.913475 DQ Delay:
8009 11:45:59.916774 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8010 11:45:59.920288 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
8011 11:45:59.923484 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8012 11:45:59.926442 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8013 11:45:59.926548
8014 11:45:59.926641
8015 11:45:59.929905
8016 11:45:59.930012 [DramC_TX_OE_Calibration] TA2
8017 11:45:59.933409 Original DQ_B0 (3 6) =30, OEN = 27
8018 11:45:59.936956 Original DQ_B1 (3 6) =30, OEN = 27
8019 11:45:59.939719 24, 0x0, End_B0=24 End_B1=24
8020 11:45:59.943367 25, 0x0, End_B0=25 End_B1=25
8021 11:45:59.946580 26, 0x0, End_B0=26 End_B1=26
8022 11:45:59.946653 27, 0x0, End_B0=27 End_B1=27
8023 11:45:59.950205 28, 0x0, End_B0=28 End_B1=28
8024 11:45:59.953037 29, 0x0, End_B0=29 End_B1=29
8025 11:45:59.956717 30, 0x0, End_B0=30 End_B1=30
8026 11:45:59.959765 31, 0x4141, End_B0=30 End_B1=30
8027 11:45:59.959871 Byte0 end_step=30 best_step=27
8028 11:45:59.963135 Byte1 end_step=30 best_step=27
8029 11:45:59.966747 Byte0 TX OE(2T, 0.5T) = (3, 3)
8030 11:45:59.969693 Byte1 TX OE(2T, 0.5T) = (3, 3)
8031 11:45:59.969797
8032 11:45:59.969890
8033 11:45:59.976577 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8034 11:45:59.979686 CH0 RK1: MR19=303, MR18=2323
8035 11:45:59.986302 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8036 11:45:59.989763 [RxdqsGatingPostProcess] freq 1600
8037 11:45:59.996384 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8038 11:45:59.999669 Pre-setting of DQS Precalculation
8039 11:46:00.003145 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8040 11:46:00.003223 ==
8041 11:46:00.006103 Dram Type= 6, Freq= 0, CH_1, rank 0
8042 11:46:00.009302 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8043 11:46:00.009376 ==
8044 11:46:00.016102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8045 11:46:00.019084 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8046 11:46:00.025941 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8047 11:46:00.029163 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8048 11:46:00.038694 [CA 0] Center 41 (11~71) winsize 61
8049 11:46:00.042053 [CA 1] Center 41 (11~72) winsize 62
8050 11:46:00.045256 [CA 2] Center 37 (7~67) winsize 61
8051 11:46:00.048816 [CA 3] Center 36 (7~66) winsize 60
8052 11:46:00.052065 [CA 4] Center 34 (4~64) winsize 61
8053 11:46:00.055264 [CA 5] Center 34 (5~64) winsize 60
8054 11:46:00.055370
8055 11:46:00.058791 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8056 11:46:00.058895
8057 11:46:00.062281 [CATrainingPosCal] consider 1 rank data
8058 11:46:00.065326 u2DelayCellTimex100 = 275/100 ps
8059 11:46:00.068730 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8060 11:46:00.075493 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8061 11:46:00.079017 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8062 11:46:00.081939 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8063 11:46:00.085118 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8064 11:46:00.088802 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8065 11:46:00.088875
8066 11:46:00.091824 CA PerBit enable=1, Macro0, CA PI delay=34
8067 11:46:00.091917
8068 11:46:00.095282 [CBTSetCACLKResult] CA Dly = 34
8069 11:46:00.098899 CS Dly: 8 (0~39)
8070 11:46:00.101852 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8071 11:46:00.105263 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8072 11:46:00.105364 ==
8073 11:46:00.108879 Dram Type= 6, Freq= 0, CH_1, rank 1
8074 11:46:00.111659 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8075 11:46:00.115087 ==
8076 11:46:00.118317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8077 11:46:00.121689 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8078 11:46:00.128416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8079 11:46:00.134643 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8080 11:46:00.141131 [CA 0] Center 40 (10~70) winsize 61
8081 11:46:00.144657 [CA 1] Center 39 (9~70) winsize 62
8082 11:46:00.148420 [CA 2] Center 35 (6~65) winsize 60
8083 11:46:00.151126 [CA 3] Center 35 (6~65) winsize 60
8084 11:46:00.154460 [CA 4] Center 33 (4~62) winsize 59
8085 11:46:00.157724 [CA 5] Center 32 (3~62) winsize 60
8086 11:46:00.157827
8087 11:46:00.161337 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8088 11:46:00.161419
8089 11:46:00.164750 [CATrainingPosCal] consider 2 rank data
8090 11:46:00.168041 u2DelayCellTimex100 = 275/100 ps
8091 11:46:00.171569 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8092 11:46:00.177999 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8093 11:46:00.181275 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8094 11:46:00.184586 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8095 11:46:00.187837 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8096 11:46:00.191147 CA5 delay=33 (5~62),Diff = 0 PI (0 cell)
8097 11:46:00.191247
8098 11:46:00.194699 CA PerBit enable=1, Macro0, CA PI delay=33
8099 11:46:00.194800
8100 11:46:00.197692 [CBTSetCACLKResult] CA Dly = 33
8101 11:46:00.200896 CS Dly: 9 (0~41)
8102 11:46:00.204195 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8103 11:46:00.207579 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8104 11:46:00.207681
8105 11:46:00.210786 ----->DramcWriteLeveling(PI) begin...
8106 11:46:00.210893 ==
8107 11:46:00.214044 Dram Type= 6, Freq= 0, CH_1, rank 0
8108 11:46:00.220670 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8109 11:46:00.220765 ==
8110 11:46:00.223891 Write leveling (Byte 0): 22 => 22
8111 11:46:00.223990 Write leveling (Byte 1): 22 => 22
8112 11:46:00.227406 DramcWriteLeveling(PI) end<-----
8113 11:46:00.227505
8114 11:46:00.227576 ==
8115 11:46:00.230583 Dram Type= 6, Freq= 0, CH_1, rank 0
8116 11:46:00.237298 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8117 11:46:00.237402 ==
8118 11:46:00.240630 [Gating] SW mode calibration
8119 11:46:00.247151 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8120 11:46:00.250660 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8121 11:46:00.257150 0 12 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8122 11:46:00.260464 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 11:46:00.263726 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 11:46:00.270149 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 11:46:00.273719 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 11:46:00.276815 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 11:46:00.283851 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8128 11:46:00.286836 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8129 11:46:00.290188 0 13 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8130 11:46:00.297053 0 13 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8131 11:46:00.300216 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 11:46:00.303504 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 11:46:00.309832 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 11:46:00.313224 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 11:46:00.317044 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8136 11:46:00.323423 0 13 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
8137 11:46:00.326359 0 14 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8138 11:46:00.329729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 11:46:00.336689 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 11:46:00.339564 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 11:46:00.343255 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 11:46:00.349469 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 11:46:00.353234 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8144 11:46:00.356007 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8145 11:46:00.362758 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8146 11:46:00.365965 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 11:46:00.369482 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 11:46:00.376017 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 11:46:00.379286 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 11:46:00.382427 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 11:46:00.388973 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 11:46:00.392514 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 11:46:00.395627 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 11:46:00.402183 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 11:46:00.405500 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 11:46:00.408966 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 11:46:00.415887 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 11:46:00.418746 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 11:46:00.422110 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8160 11:46:00.428670 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8161 11:46:00.428746 Total UI for P1: 0, mck2ui 16
8162 11:46:00.432114 best dqsien dly found for B0: ( 1, 0, 24)
8163 11:46:00.438696 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8164 11:46:00.442056 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8165 11:46:00.445384 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8166 11:46:00.451947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8167 11:46:00.455188 Total UI for P1: 0, mck2ui 16
8168 11:46:00.458503 best dqsien dly found for B1: ( 1, 1, 2)
8169 11:46:00.461705 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8170 11:46:00.465142 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8171 11:46:00.465219
8172 11:46:00.468258 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8173 11:46:00.471504 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8174 11:46:00.474892 [Gating] SW calibration Done
8175 11:46:00.475001 ==
8176 11:46:00.478309 Dram Type= 6, Freq= 0, CH_1, rank 0
8177 11:46:00.481774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8178 11:46:00.481883 ==
8179 11:46:00.485076 RX Vref Scan: 0
8180 11:46:00.485158
8181 11:46:00.488198 RX Vref 0 -> 0, step: 1
8182 11:46:00.488338
8183 11:46:00.488429 RX Delay 0 -> 252, step: 8
8184 11:46:00.494708 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8185 11:46:00.497852 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8186 11:46:00.501690 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8187 11:46:00.505055 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8188 11:46:00.508268 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8189 11:46:00.514707 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8190 11:46:00.518155 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8191 11:46:00.521032 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8192 11:46:00.524651 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8193 11:46:00.528110 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8194 11:46:00.534202 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8195 11:46:00.537846 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8196 11:46:00.541007 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8197 11:46:00.544445 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8198 11:46:00.550954 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8199 11:46:00.554276 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8200 11:46:00.554353 ==
8201 11:46:00.557416 Dram Type= 6, Freq= 0, CH_1, rank 0
8202 11:46:00.560896 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8203 11:46:00.560975 ==
8204 11:46:00.561040 DQS Delay:
8205 11:46:00.564123 DQS0 = 0, DQS1 = 0
8206 11:46:00.564241 DQM Delay:
8207 11:46:00.567434 DQM0 = 130, DQM1 = 127
8208 11:46:00.567541 DQ Delay:
8209 11:46:00.571558 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8210 11:46:00.574475 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8211 11:46:00.577363 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =115
8212 11:46:00.584223 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8213 11:46:00.584328
8214 11:46:00.584423
8215 11:46:00.584545 ==
8216 11:46:00.587439 Dram Type= 6, Freq= 0, CH_1, rank 0
8217 11:46:00.590945 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8218 11:46:00.591056 ==
8219 11:46:00.591153
8220 11:46:00.591268
8221 11:46:00.593912 TX Vref Scan disable
8222 11:46:00.594018 == TX Byte 0 ==
8223 11:46:00.600647 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8224 11:46:00.603869 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8225 11:46:00.603942 == TX Byte 1 ==
8226 11:46:00.610482 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8227 11:46:00.613763 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8228 11:46:00.613867 ==
8229 11:46:00.617233 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 11:46:00.620319 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8231 11:46:00.620423 ==
8232 11:46:00.633547
8233 11:46:00.637004 TX Vref early break, caculate TX vref
8234 11:46:00.640154 TX Vref=16, minBit 0, minWin=21, winSum=366
8235 11:46:00.643403 TX Vref=18, minBit 0, minWin=21, winSum=373
8236 11:46:00.647032 TX Vref=20, minBit 3, minWin=22, winSum=383
8237 11:46:00.650351 TX Vref=22, minBit 3, minWin=22, winSum=389
8238 11:46:00.653637 TX Vref=24, minBit 3, minWin=23, winSum=398
8239 11:46:00.659999 TX Vref=26, minBit 1, minWin=24, winSum=409
8240 11:46:00.663429 TX Vref=28, minBit 0, minWin=25, winSum=412
8241 11:46:00.666908 TX Vref=30, minBit 1, minWin=24, winSum=405
8242 11:46:00.669939 TX Vref=32, minBit 3, minWin=23, winSum=397
8243 11:46:00.673277 TX Vref=34, minBit 1, minWin=23, winSum=388
8244 11:46:00.680309 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8245 11:46:00.680396
8246 11:46:00.683277 Final TX Range 0 Vref 28
8247 11:46:00.683361
8248 11:46:00.683428 ==
8249 11:46:00.686641 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 11:46:00.690018 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8251 11:46:00.690102 ==
8252 11:46:00.690169
8253 11:46:00.690231
8254 11:46:00.693156 TX Vref Scan disable
8255 11:46:00.700000 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8256 11:46:00.700083 == TX Byte 0 ==
8257 11:46:00.703537 u2DelayCellOfst[0]=14 cells (4 PI)
8258 11:46:00.706380 u2DelayCellOfst[1]=10 cells (3 PI)
8259 11:46:00.709752 u2DelayCellOfst[2]=0 cells (0 PI)
8260 11:46:00.713061 u2DelayCellOfst[3]=3 cells (1 PI)
8261 11:46:00.716401 u2DelayCellOfst[4]=7 cells (2 PI)
8262 11:46:00.719851 u2DelayCellOfst[5]=14 cells (4 PI)
8263 11:46:00.722963 u2DelayCellOfst[6]=14 cells (4 PI)
8264 11:46:00.726315 u2DelayCellOfst[7]=7 cells (2 PI)
8265 11:46:00.729971 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8266 11:46:00.732904 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8267 11:46:00.736515 == TX Byte 1 ==
8268 11:46:00.736613 u2DelayCellOfst[8]=0 cells (0 PI)
8269 11:46:00.739574 u2DelayCellOfst[9]=7 cells (2 PI)
8270 11:46:00.742866 u2DelayCellOfst[10]=10 cells (3 PI)
8271 11:46:00.746184 u2DelayCellOfst[11]=3 cells (1 PI)
8272 11:46:00.749475 u2DelayCellOfst[12]=17 cells (5 PI)
8273 11:46:00.753046 u2DelayCellOfst[13]=17 cells (5 PI)
8274 11:46:00.756474 u2DelayCellOfst[14]=17 cells (5 PI)
8275 11:46:00.760033 u2DelayCellOfst[15]=17 cells (5 PI)
8276 11:46:00.762679 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8277 11:46:00.769601 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8278 11:46:00.769702 DramC Write-DBI on
8279 11:46:00.769769 ==
8280 11:46:00.772801 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 11:46:00.776108 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8282 11:46:00.779224 ==
8283 11:46:00.779308
8284 11:46:00.779374
8285 11:46:00.779467 TX Vref Scan disable
8286 11:46:00.782564 == TX Byte 0 ==
8287 11:46:00.785995 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8288 11:46:00.789160 == TX Byte 1 ==
8289 11:46:00.792750 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8290 11:46:00.795868 DramC Write-DBI off
8291 11:46:00.795950
8292 11:46:00.796016 [DATLAT]
8293 11:46:00.796093 Freq=1600, CH1 RK0
8294 11:46:00.796169
8295 11:46:00.799460 DATLAT Default: 0xf
8296 11:46:00.799542 0, 0xFFFF, sum = 0
8297 11:46:00.802469 1, 0xFFFF, sum = 0
8298 11:46:00.805631 2, 0xFFFF, sum = 0
8299 11:46:00.805715 3, 0xFFFF, sum = 0
8300 11:46:00.808887 4, 0xFFFF, sum = 0
8301 11:46:00.808974 5, 0xFFFF, sum = 0
8302 11:46:00.812271 6, 0xFFFF, sum = 0
8303 11:46:00.812357 7, 0xFFFF, sum = 0
8304 11:46:00.815721 8, 0xFFFF, sum = 0
8305 11:46:00.815808 9, 0xFFFF, sum = 0
8306 11:46:00.819056 10, 0xFFFF, sum = 0
8307 11:46:00.819143 11, 0xFFFF, sum = 0
8308 11:46:00.822849 12, 0xF7F, sum = 0
8309 11:46:00.822934 13, 0x0, sum = 1
8310 11:46:00.825731 14, 0x0, sum = 2
8311 11:46:00.825817 15, 0x0, sum = 3
8312 11:46:00.829315 16, 0x0, sum = 4
8313 11:46:00.829401 best_step = 14
8314 11:46:00.829469
8315 11:46:00.829532 ==
8316 11:46:00.832239 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 11:46:00.838791 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8318 11:46:00.838877 ==
8319 11:46:00.838946 RX Vref Scan: 1
8320 11:46:00.839041
8321 11:46:00.842246 Set Vref Range= 24 -> 127
8322 11:46:00.842331
8323 11:46:00.845577 RX Vref 24 -> 127, step: 1
8324 11:46:00.845662
8325 11:46:00.845729 RX Delay 11 -> 252, step: 4
8326 11:46:00.845793
8327 11:46:00.848839 Set Vref, RX VrefLevel [Byte0]: 24
8328 11:46:00.851957 [Byte1]: 24
8329 11:46:00.856222
8330 11:46:00.856307 Set Vref, RX VrefLevel [Byte0]: 25
8331 11:46:00.859240 [Byte1]: 25
8332 11:46:00.863513
8333 11:46:00.863598 Set Vref, RX VrefLevel [Byte0]: 26
8334 11:46:00.867060 [Byte1]: 26
8335 11:46:00.871165
8336 11:46:00.871252 Set Vref, RX VrefLevel [Byte0]: 27
8337 11:46:00.874439 [Byte1]: 27
8338 11:46:00.879024
8339 11:46:00.879109 Set Vref, RX VrefLevel [Byte0]: 28
8340 11:46:00.882012 [Byte1]: 28
8341 11:46:00.886412
8342 11:46:00.886497 Set Vref, RX VrefLevel [Byte0]: 29
8343 11:46:00.889635 [Byte1]: 29
8344 11:46:00.894150
8345 11:46:00.894234 Set Vref, RX VrefLevel [Byte0]: 30
8346 11:46:00.897531 [Byte1]: 30
8347 11:46:00.901440
8348 11:46:00.901524 Set Vref, RX VrefLevel [Byte0]: 31
8349 11:46:00.905085 [Byte1]: 31
8350 11:46:00.909313
8351 11:46:00.909397 Set Vref, RX VrefLevel [Byte0]: 32
8352 11:46:00.912734 [Byte1]: 32
8353 11:46:00.917085
8354 11:46:00.917173 Set Vref, RX VrefLevel [Byte0]: 33
8355 11:46:00.920269 [Byte1]: 33
8356 11:46:00.924672
8357 11:46:00.924755 Set Vref, RX VrefLevel [Byte0]: 34
8358 11:46:00.927752 [Byte1]: 34
8359 11:46:00.932187
8360 11:46:00.932271 Set Vref, RX VrefLevel [Byte0]: 35
8361 11:46:00.935287 [Byte1]: 35
8362 11:46:00.939672
8363 11:46:00.939756 Set Vref, RX VrefLevel [Byte0]: 36
8364 11:46:00.943119 [Byte1]: 36
8365 11:46:00.947248
8366 11:46:00.947332 Set Vref, RX VrefLevel [Byte0]: 37
8367 11:46:00.950805 [Byte1]: 37
8368 11:46:00.955032
8369 11:46:00.955116 Set Vref, RX VrefLevel [Byte0]: 38
8370 11:46:00.958364 [Byte1]: 38
8371 11:46:00.962467
8372 11:46:00.962551 Set Vref, RX VrefLevel [Byte0]: 39
8373 11:46:00.966060 [Byte1]: 39
8374 11:46:00.970177
8375 11:46:00.970260 Set Vref, RX VrefLevel [Byte0]: 40
8376 11:46:00.973378 [Byte1]: 40
8377 11:46:00.977684
8378 11:46:00.977768 Set Vref, RX VrefLevel [Byte0]: 41
8379 11:46:00.981109 [Byte1]: 41
8380 11:46:00.985276
8381 11:46:00.985360 Set Vref, RX VrefLevel [Byte0]: 42
8382 11:46:00.988740 [Byte1]: 42
8383 11:46:00.993594
8384 11:46:00.993678 Set Vref, RX VrefLevel [Byte0]: 43
8385 11:46:00.996379 [Byte1]: 43
8386 11:46:01.000728
8387 11:46:01.000812 Set Vref, RX VrefLevel [Byte0]: 44
8388 11:46:01.004230 [Byte1]: 44
8389 11:46:01.008200
8390 11:46:01.008284 Set Vref, RX VrefLevel [Byte0]: 45
8391 11:46:01.011427 [Byte1]: 45
8392 11:46:01.015703
8393 11:46:01.015787 Set Vref, RX VrefLevel [Byte0]: 46
8394 11:46:01.019506 [Byte1]: 46
8395 11:46:01.023597
8396 11:46:01.023681 Set Vref, RX VrefLevel [Byte0]: 47
8397 11:46:01.026638 [Byte1]: 47
8398 11:46:01.030932
8399 11:46:01.031016 Set Vref, RX VrefLevel [Byte0]: 48
8400 11:46:01.034229 [Byte1]: 48
8401 11:46:01.038698
8402 11:46:01.038782 Set Vref, RX VrefLevel [Byte0]: 49
8403 11:46:01.042174 [Byte1]: 49
8404 11:46:01.046270
8405 11:46:01.046354 Set Vref, RX VrefLevel [Byte0]: 50
8406 11:46:01.050098 [Byte1]: 50
8407 11:46:01.053850
8408 11:46:01.053934 Set Vref, RX VrefLevel [Byte0]: 51
8409 11:46:01.058195 [Byte1]: 51
8410 11:46:01.061461
8411 11:46:01.061546 Set Vref, RX VrefLevel [Byte0]: 52
8412 11:46:01.064931 [Byte1]: 52
8413 11:46:01.069465
8414 11:46:01.069550 Set Vref, RX VrefLevel [Byte0]: 53
8415 11:46:01.072467 [Byte1]: 53
8416 11:46:01.077234
8417 11:46:01.077321 Set Vref, RX VrefLevel [Byte0]: 54
8418 11:46:01.080217 [Byte1]: 54
8419 11:46:01.084468
8420 11:46:01.084572 Set Vref, RX VrefLevel [Byte0]: 55
8421 11:46:01.087782 [Byte1]: 55
8422 11:46:01.091960
8423 11:46:01.092045 Set Vref, RX VrefLevel [Byte0]: 56
8424 11:46:01.095209 [Byte1]: 56
8425 11:46:01.099629
8426 11:46:01.099707 Set Vref, RX VrefLevel [Byte0]: 57
8427 11:46:01.102733 [Byte1]: 57
8428 11:46:01.107467
8429 11:46:01.107545 Set Vref, RX VrefLevel [Byte0]: 58
8430 11:46:01.110625 [Byte1]: 58
8431 11:46:01.114887
8432 11:46:01.114971 Set Vref, RX VrefLevel [Byte0]: 59
8433 11:46:01.118115 [Byte1]: 59
8434 11:46:01.122694
8435 11:46:01.122779 Set Vref, RX VrefLevel [Byte0]: 60
8436 11:46:01.125729 [Byte1]: 60
8437 11:46:01.129833
8438 11:46:01.129918 Set Vref, RX VrefLevel [Byte0]: 61
8439 11:46:01.133437 [Byte1]: 61
8440 11:46:01.138155
8441 11:46:01.138239 Set Vref, RX VrefLevel [Byte0]: 62
8442 11:46:01.140879 [Byte1]: 62
8443 11:46:01.145180
8444 11:46:01.145255 Set Vref, RX VrefLevel [Byte0]: 63
8445 11:46:01.148441 [Byte1]: 63
8446 11:46:01.153015
8447 11:46:01.153090 Set Vref, RX VrefLevel [Byte0]: 64
8448 11:46:01.156284 [Byte1]: 64
8449 11:46:01.160871
8450 11:46:01.160956 Set Vref, RX VrefLevel [Byte0]: 65
8451 11:46:01.163618 [Byte1]: 65
8452 11:46:01.168171
8453 11:46:01.168247 Set Vref, RX VrefLevel [Byte0]: 66
8454 11:46:01.171464 [Byte1]: 66
8455 11:46:01.175787
8456 11:46:01.175870 Set Vref, RX VrefLevel [Byte0]: 67
8457 11:46:01.178882 [Byte1]: 67
8458 11:46:01.183208
8459 11:46:01.183281 Set Vref, RX VrefLevel [Byte0]: 68
8460 11:46:01.186747 [Byte1]: 68
8461 11:46:01.190740
8462 11:46:01.190815 Set Vref, RX VrefLevel [Byte0]: 69
8463 11:46:01.194166 [Byte1]: 69
8464 11:46:01.198851
8465 11:46:01.198942 Set Vref, RX VrefLevel [Byte0]: 70
8466 11:46:01.202040 [Byte1]: 70
8467 11:46:01.206045
8468 11:46:01.206117 Set Vref, RX VrefLevel [Byte0]: 71
8469 11:46:01.209549 [Byte1]: 71
8470 11:46:01.214170
8471 11:46:01.214246 Set Vref, RX VrefLevel [Byte0]: 72
8472 11:46:01.217476 [Byte1]: 72
8473 11:46:01.221750
8474 11:46:01.221827 Set Vref, RX VrefLevel [Byte0]: 73
8475 11:46:01.224738 [Byte1]: 73
8476 11:46:01.228954
8477 11:46:01.229029 Set Vref, RX VrefLevel [Byte0]: 74
8478 11:46:01.232161 [Byte1]: 74
8479 11:46:01.236765
8480 11:46:01.236842 Set Vref, RX VrefLevel [Byte0]: 75
8481 11:46:01.239957 [Byte1]: 75
8482 11:46:01.244081
8483 11:46:01.244152 Final RX Vref Byte 0 = 63 to rank0
8484 11:46:01.247558 Final RX Vref Byte 1 = 56 to rank0
8485 11:46:01.251101 Final RX Vref Byte 0 = 63 to rank1
8486 11:46:01.254444 Final RX Vref Byte 1 = 56 to rank1==
8487 11:46:01.257405 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 11:46:01.264209 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8489 11:46:01.264294 ==
8490 11:46:01.264364 DQS Delay:
8491 11:46:01.267494 DQS0 = 0, DQS1 = 0
8492 11:46:01.267564 DQM Delay:
8493 11:46:01.267624 DQM0 = 128, DQM1 = 124
8494 11:46:01.270647 DQ Delay:
8495 11:46:01.274123 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8496 11:46:01.277197 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =124
8497 11:46:01.280849 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8498 11:46:01.283844 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8499 11:46:01.283923
8500 11:46:01.283990
8501 11:46:01.284050
8502 11:46:01.287279 [DramC_TX_OE_Calibration] TA2
8503 11:46:01.290517 Original DQ_B0 (3 6) =30, OEN = 27
8504 11:46:01.293643 Original DQ_B1 (3 6) =30, OEN = 27
8505 11:46:01.297297 24, 0x0, End_B0=24 End_B1=24
8506 11:46:01.297366 25, 0x0, End_B0=25 End_B1=25
8507 11:46:01.300608 26, 0x0, End_B0=26 End_B1=26
8508 11:46:01.303772 27, 0x0, End_B0=27 End_B1=27
8509 11:46:01.306937 28, 0x0, End_B0=28 End_B1=28
8510 11:46:01.310352 29, 0x0, End_B0=29 End_B1=29
8511 11:46:01.310421 30, 0x0, End_B0=30 End_B1=30
8512 11:46:01.313607 31, 0x5151, End_B0=30 End_B1=30
8513 11:46:01.317154 Byte0 end_step=30 best_step=27
8514 11:46:01.319964 Byte1 end_step=30 best_step=27
8515 11:46:01.323552 Byte0 TX OE(2T, 0.5T) = (3, 3)
8516 11:46:01.326872 Byte1 TX OE(2T, 0.5T) = (3, 3)
8517 11:46:01.326973
8518 11:46:01.327071
8519 11:46:01.333391 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8520 11:46:01.336541 CH1 RK0: MR19=303, MR18=2424
8521 11:46:01.343210 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8522 11:46:01.343299
8523 11:46:01.346418 ----->DramcWriteLeveling(PI) begin...
8524 11:46:01.346502 ==
8525 11:46:01.349866 Dram Type= 6, Freq= 0, CH_1, rank 1
8526 11:46:01.353165 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8527 11:46:01.353242 ==
8528 11:46:01.356988 Write leveling (Byte 0): 24 => 24
8529 11:46:01.359827 Write leveling (Byte 1): 23 => 23
8530 11:46:01.363323 DramcWriteLeveling(PI) end<-----
8531 11:46:01.363403
8532 11:46:01.363468 ==
8533 11:46:01.366395 Dram Type= 6, Freq= 0, CH_1, rank 1
8534 11:46:01.370244 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8535 11:46:01.370358 ==
8536 11:46:01.373423 [Gating] SW mode calibration
8537 11:46:01.379806 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8538 11:46:01.386462 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8539 11:46:01.389871 0 12 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8540 11:46:01.396718 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8541 11:46:01.399954 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8542 11:46:01.403030 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8543 11:46:01.409864 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8544 11:46:01.412847 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8545 11:46:01.416182 0 12 24 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8546 11:46:01.422911 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8547 11:46:01.426407 0 13 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8548 11:46:01.429770 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8549 11:46:01.436049 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8550 11:46:01.439675 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8551 11:46:01.442753 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8552 11:46:01.449232 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8553 11:46:01.452566 0 13 24 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8554 11:46:01.455815 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8555 11:46:01.462720 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8556 11:46:01.465747 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8557 11:46:01.469216 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 11:46:01.475678 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8559 11:46:01.479031 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8560 11:46:01.482331 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 11:46:01.485765 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8562 11:46:01.492634 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8563 11:46:01.495911 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 11:46:01.499136 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 11:46:01.505928 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 11:46:01.509411 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 11:46:01.512483 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 11:46:01.519551 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 11:46:01.522592 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 11:46:01.525538 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 11:46:01.532268 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 11:46:01.535442 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 11:46:01.538651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 11:46:01.545752 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 11:46:01.548731 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 11:46:01.551952 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 11:46:01.558766 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8578 11:46:01.562247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8579 11:46:01.565368 Total UI for P1: 0, mck2ui 16
8580 11:46:01.568677 best dqsien dly found for B0: ( 1, 0, 24)
8581 11:46:01.571897 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8582 11:46:01.575387 Total UI for P1: 0, mck2ui 16
8583 11:46:01.578570 best dqsien dly found for B1: ( 1, 0, 28)
8584 11:46:01.581947 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8585 11:46:01.585333 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8586 11:46:01.585406
8587 11:46:01.592223 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8588 11:46:01.595161 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8589 11:46:01.598497 [Gating] SW calibration Done
8590 11:46:01.598566 ==
8591 11:46:01.601706 Dram Type= 6, Freq= 0, CH_1, rank 1
8592 11:46:01.605123 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8593 11:46:01.605193 ==
8594 11:46:01.605254 RX Vref Scan: 0
8595 11:46:01.605311
8596 11:46:01.608240 RX Vref 0 -> 0, step: 1
8597 11:46:01.608306
8598 11:46:01.611470 RX Delay 0 -> 252, step: 8
8599 11:46:01.614902 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8600 11:46:01.618137 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8601 11:46:01.624870 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8602 11:46:01.628079 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8603 11:46:01.631768 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8604 11:46:01.634387 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8605 11:46:01.638172 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8606 11:46:01.644920 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8607 11:46:01.647822 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8608 11:46:01.651103 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8609 11:46:01.654622 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8610 11:46:01.657920 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8611 11:46:01.664452 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8612 11:46:01.667532 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8613 11:46:01.670757 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8614 11:46:01.674144 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8615 11:46:01.674221 ==
8616 11:46:01.677480 Dram Type= 6, Freq= 0, CH_1, rank 1
8617 11:46:01.683859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8618 11:46:01.683942 ==
8619 11:46:01.684005 DQS Delay:
8620 11:46:01.687265 DQS0 = 0, DQS1 = 0
8621 11:46:01.687348 DQM Delay:
8622 11:46:01.690637 DQM0 = 132, DQM1 = 125
8623 11:46:01.690739 DQ Delay:
8624 11:46:01.693829 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =131
8625 11:46:01.697521 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8626 11:46:01.700492 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8627 11:46:01.703866 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8628 11:46:01.703937
8629 11:46:01.703998
8630 11:46:01.704059 ==
8631 11:46:01.707237 Dram Type= 6, Freq= 0, CH_1, rank 1
8632 11:46:01.713889 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8633 11:46:01.713964 ==
8634 11:46:01.714026
8635 11:46:01.714088
8636 11:46:01.714163 TX Vref Scan disable
8637 11:46:01.717107 == TX Byte 0 ==
8638 11:46:01.720245 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8639 11:46:01.726971 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8640 11:46:01.727050 == TX Byte 1 ==
8641 11:46:01.730200 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8642 11:46:01.737186 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8643 11:46:01.737268 ==
8644 11:46:01.740015 Dram Type= 6, Freq= 0, CH_1, rank 1
8645 11:46:01.743459 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8646 11:46:01.743534 ==
8647 11:46:01.756859
8648 11:46:01.760092 TX Vref early break, caculate TX vref
8649 11:46:01.763375 TX Vref=16, minBit 0, minWin=22, winSum=374
8650 11:46:01.766640 TX Vref=18, minBit 0, minWin=22, winSum=383
8651 11:46:01.769928 TX Vref=20, minBit 0, minWin=23, winSum=394
8652 11:46:01.772986 TX Vref=22, minBit 0, minWin=24, winSum=401
8653 11:46:01.776444 TX Vref=24, minBit 0, minWin=24, winSum=409
8654 11:46:01.783144 TX Vref=26, minBit 0, minWin=24, winSum=417
8655 11:46:01.786371 TX Vref=28, minBit 5, minWin=24, winSum=415
8656 11:46:01.789676 TX Vref=30, minBit 0, minWin=24, winSum=415
8657 11:46:01.793067 TX Vref=32, minBit 0, minWin=24, winSum=405
8658 11:46:01.796560 TX Vref=34, minBit 0, minWin=22, winSum=397
8659 11:46:01.803047 TX Vref=36, minBit 0, minWin=23, winSum=388
8660 11:46:01.806215 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8661 11:46:01.806291
8662 11:46:01.809376 Final TX Range 0 Vref 26
8663 11:46:01.809446
8664 11:46:01.809510 ==
8665 11:46:01.812902 Dram Type= 6, Freq= 0, CH_1, rank 1
8666 11:46:01.815980 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8667 11:46:01.816054 ==
8668 11:46:01.819379
8669 11:46:01.819455
8670 11:46:01.819515 TX Vref Scan disable
8671 11:46:01.826032 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8672 11:46:01.826105 == TX Byte 0 ==
8673 11:46:01.829782 u2DelayCellOfst[0]=14 cells (4 PI)
8674 11:46:01.832723 u2DelayCellOfst[1]=10 cells (3 PI)
8675 11:46:01.836002 u2DelayCellOfst[2]=0 cells (0 PI)
8676 11:46:01.839909 u2DelayCellOfst[3]=7 cells (2 PI)
8677 11:46:01.842538 u2DelayCellOfst[4]=7 cells (2 PI)
8678 11:46:01.845776 u2DelayCellOfst[5]=17 cells (5 PI)
8679 11:46:01.849439 u2DelayCellOfst[6]=17 cells (5 PI)
8680 11:46:01.852572 u2DelayCellOfst[7]=3 cells (1 PI)
8681 11:46:01.856047 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8682 11:46:01.859478 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8683 11:46:01.862571 == TX Byte 1 ==
8684 11:46:01.865853 u2DelayCellOfst[8]=0 cells (0 PI)
8685 11:46:01.869104 u2DelayCellOfst[9]=3 cells (1 PI)
8686 11:46:01.872128 u2DelayCellOfst[10]=10 cells (3 PI)
8687 11:46:01.875462 u2DelayCellOfst[11]=3 cells (1 PI)
8688 11:46:01.878915 u2DelayCellOfst[12]=14 cells (4 PI)
8689 11:46:01.878990 u2DelayCellOfst[13]=17 cells (5 PI)
8690 11:46:01.881912 u2DelayCellOfst[14]=17 cells (5 PI)
8691 11:46:01.885493 u2DelayCellOfst[15]=17 cells (5 PI)
8692 11:46:01.891839 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8693 11:46:01.895919 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8694 11:46:01.895995 DramC Write-DBI on
8695 11:46:01.898762 ==
8696 11:46:01.902072 Dram Type= 6, Freq= 0, CH_1, rank 1
8697 11:46:01.905303 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8698 11:46:01.905377 ==
8699 11:46:01.905440
8700 11:46:01.905501
8701 11:46:01.908790 TX Vref Scan disable
8702 11:46:01.908860 == TX Byte 0 ==
8703 11:46:01.915063 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8704 11:46:01.915135 == TX Byte 1 ==
8705 11:46:01.918869 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8706 11:46:01.921760 DramC Write-DBI off
8707 11:46:01.921844
8708 11:46:01.921909 [DATLAT]
8709 11:46:01.925247 Freq=1600, CH1 RK1
8710 11:46:01.925330
8711 11:46:01.925389 DATLAT Default: 0xe
8712 11:46:01.928613 0, 0xFFFF, sum = 0
8713 11:46:01.928687 1, 0xFFFF, sum = 0
8714 11:46:01.932067 2, 0xFFFF, sum = 0
8715 11:46:01.932139 3, 0xFFFF, sum = 0
8716 11:46:01.935338 4, 0xFFFF, sum = 0
8717 11:46:01.935411 5, 0xFFFF, sum = 0
8718 11:46:01.938542 6, 0xFFFF, sum = 0
8719 11:46:01.938616 7, 0xFFFF, sum = 0
8720 11:46:01.941711 8, 0xFFFF, sum = 0
8721 11:46:01.945013 9, 0xFFFF, sum = 0
8722 11:46:01.945105 10, 0xFFFF, sum = 0
8723 11:46:01.948130 11, 0xFFFF, sum = 0
8724 11:46:01.948202 12, 0x8FFF, sum = 0
8725 11:46:01.951783 13, 0x0, sum = 1
8726 11:46:01.951855 14, 0x0, sum = 2
8727 11:46:01.954911 15, 0x0, sum = 3
8728 11:46:01.954980 16, 0x0, sum = 4
8729 11:46:01.955041 best_step = 14
8730 11:46:01.958232
8731 11:46:01.958309 ==
8732 11:46:01.961348 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 11:46:01.964968 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8734 11:46:01.965047 ==
8735 11:46:01.965114 RX Vref Scan: 0
8736 11:46:01.965177
8737 11:46:01.968375 RX Vref 0 -> 0, step: 1
8738 11:46:01.968476
8739 11:46:01.971477 RX Delay 3 -> 252, step: 4
8740 11:46:01.974532 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8741 11:46:01.981375 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8742 11:46:01.984558 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8743 11:46:01.987816 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8744 11:46:01.991500 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8745 11:46:01.994440 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8746 11:46:02.001565 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8747 11:46:02.004430 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8748 11:46:02.007762 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8749 11:46:02.010958 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8750 11:46:02.014501 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8751 11:46:02.021724 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8752 11:46:02.024821 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8753 11:46:02.027751 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8754 11:46:02.031337 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8755 11:46:02.034038 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8756 11:46:02.037496 ==
8757 11:46:02.041093 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 11:46:02.044051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8759 11:46:02.044121 ==
8760 11:46:02.044185 DQS Delay:
8761 11:46:02.047463 DQS0 = 0, DQS1 = 0
8762 11:46:02.047534 DQM Delay:
8763 11:46:02.050987 DQM0 = 127, DQM1 = 122
8764 11:46:02.051059 DQ Delay:
8765 11:46:02.053917 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8766 11:46:02.057633 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8767 11:46:02.060588 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8768 11:46:02.063733 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8769 11:46:02.063819
8770 11:46:02.063891
8771 11:46:02.063950
8772 11:46:02.067152 [DramC_TX_OE_Calibration] TA2
8773 11:46:02.070476 Original DQ_B0 (3 6) =30, OEN = 27
8774 11:46:02.074087 Original DQ_B1 (3 6) =30, OEN = 27
8775 11:46:02.077354 24, 0x0, End_B0=24 End_B1=24
8776 11:46:02.080366 25, 0x0, End_B0=25 End_B1=25
8777 11:46:02.083907 26, 0x0, End_B0=26 End_B1=26
8778 11:46:02.083983 27, 0x0, End_B0=27 End_B1=27
8779 11:46:02.087454 28, 0x0, End_B0=28 End_B1=28
8780 11:46:02.090243 29, 0x0, End_B0=29 End_B1=29
8781 11:46:02.093497 30, 0x0, End_B0=30 End_B1=30
8782 11:46:02.093573 31, 0x4141, End_B0=30 End_B1=30
8783 11:46:02.096816 Byte0 end_step=30 best_step=27
8784 11:46:02.100351 Byte1 end_step=30 best_step=27
8785 11:46:02.103446 Byte0 TX OE(2T, 0.5T) = (3, 3)
8786 11:46:02.106690 Byte1 TX OE(2T, 0.5T) = (3, 3)
8787 11:46:02.106764
8788 11:46:02.106824
8789 11:46:02.113506 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8790 11:46:02.116639 CH1 RK1: MR19=303, MR18=2020
8791 11:46:02.123406 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8792 11:46:02.126466 [RxdqsGatingPostProcess] freq 1600
8793 11:46:02.133680 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8794 11:46:02.136653 Pre-setting of DQS Precalculation
8795 11:46:02.140097 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8796 11:46:02.146442 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8797 11:46:02.153268 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8798 11:46:02.156384
8799 11:46:02.156465
8800 11:46:02.156570 [Calibration Summary] 3200 Mbps
8801 11:46:02.159592 CH 0, Rank 0
8802 11:46:02.159676 SW Impedance : PASS
8803 11:46:02.163300 DUTY Scan : NO K
8804 11:46:02.166443 ZQ Calibration : PASS
8805 11:46:02.166523 Jitter Meter : NO K
8806 11:46:02.169840 CBT Training : PASS
8807 11:46:02.172952 Write leveling : PASS
8808 11:46:02.173060 RX DQS gating : PASS
8809 11:46:02.176537 RX DQ/DQS(RDDQC) : PASS
8810 11:46:02.179619 TX DQ/DQS : PASS
8811 11:46:02.179692 RX DATLAT : PASS
8812 11:46:02.182951 RX DQ/DQS(Engine): PASS
8813 11:46:02.186334 TX OE : PASS
8814 11:46:02.186411 All Pass.
8815 11:46:02.186473
8816 11:46:02.186535 CH 0, Rank 1
8817 11:46:02.189663 SW Impedance : PASS
8818 11:46:02.193206 DUTY Scan : NO K
8819 11:46:02.193287 ZQ Calibration : PASS
8820 11:46:02.196207 Jitter Meter : NO K
8821 11:46:02.199396 CBT Training : PASS
8822 11:46:02.199468 Write leveling : PASS
8823 11:46:02.202740 RX DQS gating : PASS
8824 11:46:02.205907 RX DQ/DQS(RDDQC) : PASS
8825 11:46:02.205975 TX DQ/DQS : PASS
8826 11:46:02.209315 RX DATLAT : PASS
8827 11:46:02.212477 RX DQ/DQS(Engine): PASS
8828 11:46:02.212595 TX OE : PASS
8829 11:46:02.212661 All Pass.
8830 11:46:02.212722
8831 11:46:02.215640 CH 1, Rank 0
8832 11:46:02.219160 SW Impedance : PASS
8833 11:46:02.219237 DUTY Scan : NO K
8834 11:46:02.222616 ZQ Calibration : PASS
8835 11:46:02.222691 Jitter Meter : NO K
8836 11:46:02.225987 CBT Training : PASS
8837 11:46:02.229042 Write leveling : PASS
8838 11:46:02.229133 RX DQS gating : PASS
8839 11:46:02.232457 RX DQ/DQS(RDDQC) : PASS
8840 11:46:02.235642 TX DQ/DQS : PASS
8841 11:46:02.235743 RX DATLAT : PASS
8842 11:46:02.238811 RX DQ/DQS(Engine): PASS
8843 11:46:02.242353 TX OE : PASS
8844 11:46:02.242431 All Pass.
8845 11:46:02.242512
8846 11:46:02.242595 CH 1, Rank 1
8847 11:46:02.246051 SW Impedance : PASS
8848 11:46:02.248992 DUTY Scan : NO K
8849 11:46:02.249079 ZQ Calibration : PASS
8850 11:46:02.252212 Jitter Meter : NO K
8851 11:46:02.255587 CBT Training : PASS
8852 11:46:02.255666 Write leveling : PASS
8853 11:46:02.259302 RX DQS gating : PASS
8854 11:46:02.262089 RX DQ/DQS(RDDQC) : PASS
8855 11:46:02.262186 TX DQ/DQS : PASS
8856 11:46:02.265568 RX DATLAT : PASS
8857 11:46:02.268928 RX DQ/DQS(Engine): PASS
8858 11:46:02.269002 TX OE : PASS
8859 11:46:02.269091 All Pass.
8860 11:46:02.272429
8861 11:46:02.272502 DramC Write-DBI on
8862 11:46:02.275255 PER_BANK_REFRESH: Hybrid Mode
8863 11:46:02.275343 TX_TRACKING: ON
8864 11:46:02.285819 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8865 11:46:02.292040 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8866 11:46:02.301843 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8867 11:46:02.305096 [FAST_K] Save calibration result to emmc
8868 11:46:02.308615 sync common calibartion params.
8869 11:46:02.308690 sync cbt_mode0:0, 1:0
8870 11:46:02.311790 dram_init: ddr_geometry: 0
8871 11:46:02.315177 dram_init: ddr_geometry: 0
8872 11:46:02.315254 dram_init: ddr_geometry: 0
8873 11:46:02.318655 0:dram_rank_size:80000000
8874 11:46:02.321808 1:dram_rank_size:80000000
8875 11:46:02.325193 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8876 11:46:02.328486 DFS_SHUFFLE_HW_MODE: ON
8877 11:46:02.331785 dramc_set_vcore_voltage set vcore to 725000
8878 11:46:02.335092 Read voltage for 1600, 0
8879 11:46:02.335166 Vio18 = 0
8880 11:46:02.338344 Vcore = 725000
8881 11:46:02.338417 Vdram = 0
8882 11:46:02.338501 Vddq = 0
8883 11:46:02.338577 Vmddr = 0
8884 11:46:02.342031 switch to 3200 Mbps bootup
8885 11:46:02.345087 [DramcRunTimeConfig]
8886 11:46:02.345162 PHYPLL
8887 11:46:02.348362 DPM_CONTROL_AFTERK: ON
8888 11:46:02.348436 PER_BANK_REFRESH: ON
8889 11:46:02.351406 REFRESH_OVERHEAD_REDUCTION: ON
8890 11:46:02.354732 CMD_PICG_NEW_MODE: OFF
8891 11:46:02.354811 XRTWTW_NEW_MODE: ON
8892 11:46:02.358234 XRTRTR_NEW_MODE: ON
8893 11:46:02.358308 TX_TRACKING: ON
8894 11:46:02.361499 RDSEL_TRACKING: OFF
8895 11:46:02.365171 DQS Precalculation for DVFS: ON
8896 11:46:02.365254 RX_TRACKING: OFF
8897 11:46:02.365336 HW_GATING DBG: ON
8898 11:46:02.368547 ZQCS_ENABLE_LP4: ON
8899 11:46:02.371895 RX_PICG_NEW_MODE: ON
8900 11:46:02.372025 TX_PICG_NEW_MODE: ON
8901 11:46:02.375022 ENABLE_RX_DCM_DPHY: ON
8902 11:46:02.378450 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8903 11:46:02.378529 DUMMY_READ_FOR_TRACKING: OFF
8904 11:46:02.381490 !!! SPM_CONTROL_AFTERK: OFF
8905 11:46:02.384685 !!! SPM could not control APHY
8906 11:46:02.388090 IMPEDANCE_TRACKING: ON
8907 11:46:02.388162 TEMP_SENSOR: ON
8908 11:46:02.391444 HW_SAVE_FOR_SR: OFF
8909 11:46:02.394813 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8910 11:46:02.398322 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8911 11:46:02.398396 Read ODT Tracking: ON
8912 11:46:02.401118 Refresh Rate DeBounce: ON
8913 11:46:02.404844 DFS_NO_QUEUE_FLUSH: ON
8914 11:46:02.408022 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8915 11:46:02.408097 ENABLE_DFS_RUNTIME_MRW: OFF
8916 11:46:02.411236 DDR_RESERVE_NEW_MODE: ON
8917 11:46:02.414625 MR_CBT_SWITCH_FREQ: ON
8918 11:46:02.414705 =========================
8919 11:46:02.434495 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8920 11:46:02.437645 dram_init: ddr_geometry: 0
8921 11:46:02.455682 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8922 11:46:02.459173 dram_init: dram init end (result: 0)
8923 11:46:02.465445 DRAM-K: Full calibration passed in 23435 msecs
8924 11:46:02.469190 MRC: failed to locate region type 0.
8925 11:46:02.469267 DRAM rank0 size:0x80000000,
8926 11:46:02.472259 DRAM rank1 size=0x80000000
8927 11:46:02.482403 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8928 11:46:02.488985 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8929 11:46:02.495353 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8930 11:46:02.502097 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8931 11:46:02.505233 DRAM rank0 size:0x80000000,
8932 11:46:02.508978 DRAM rank1 size=0x80000000
8933 11:46:02.509049 CBMEM:
8934 11:46:02.512219 IMD: root @ 0xfffff000 254 entries.
8935 11:46:02.515802 IMD: root @ 0xffffec00 62 entries.
8936 11:46:02.518502 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8937 11:46:02.521653 WARNING: RO_VPD is uninitialized or empty.
8938 11:46:02.528132 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8939 11:46:02.535574 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8940 11:46:02.547950 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
8941 11:46:02.559203 BS: romstage times (exec / console): total (unknown) / 22973 ms
8942 11:46:02.559284
8943 11:46:02.559359
8944 11:46:02.569145 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8945 11:46:02.572456 ARM64: Exception handlers installed.
8946 11:46:02.575926 ARM64: Testing exception
8947 11:46:02.579156 ARM64: Done test exception
8948 11:46:02.579234 Enumerating buses...
8949 11:46:02.582665 Show all devs... Before device enumeration.
8950 11:46:02.585781 Root Device: enabled 1
8951 11:46:02.588999 CPU_CLUSTER: 0: enabled 1
8952 11:46:02.589084 CPU: 00: enabled 1
8953 11:46:02.592471 Compare with tree...
8954 11:46:02.592590 Root Device: enabled 1
8955 11:46:02.595585 CPU_CLUSTER: 0: enabled 1
8956 11:46:02.599227 CPU: 00: enabled 1
8957 11:46:02.599303 Root Device scanning...
8958 11:46:02.602667 scan_static_bus for Root Device
8959 11:46:02.605801 CPU_CLUSTER: 0 enabled
8960 11:46:02.608979 scan_static_bus for Root Device done
8961 11:46:02.612331 scan_bus: bus Root Device finished in 8 msecs
8962 11:46:02.612403 done
8963 11:46:02.618939 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8964 11:46:02.622143 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8965 11:46:02.628818 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8966 11:46:02.631995 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8967 11:46:02.635579 Allocating resources...
8968 11:46:02.638652 Reading resources...
8969 11:46:02.642412 Root Device read_resources bus 0 link: 0
8970 11:46:02.645488 DRAM rank0 size:0x80000000,
8971 11:46:02.645576 DRAM rank1 size=0x80000000
8972 11:46:02.648791 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8973 11:46:02.651860 CPU: 00 missing read_resources
8974 11:46:02.658586 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8975 11:46:02.661831 Root Device read_resources bus 0 link: 0 done
8976 11:46:02.661911 Done reading resources.
8977 11:46:02.668448 Show resources in subtree (Root Device)...After reading.
8978 11:46:02.671789 Root Device child on link 0 CPU_CLUSTER: 0
8979 11:46:02.675243 CPU_CLUSTER: 0 child on link 0 CPU: 00
8980 11:46:02.685044 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8981 11:46:02.685126 CPU: 00
8982 11:46:02.688325 Root Device assign_resources, bus 0 link: 0
8983 11:46:02.691850 CPU_CLUSTER: 0 missing set_resources
8984 11:46:02.698385 Root Device assign_resources, bus 0 link: 0 done
8985 11:46:02.698466 Done setting resources.
8986 11:46:02.704815 Show resources in subtree (Root Device)...After assigning values.
8987 11:46:02.708335 Root Device child on link 0 CPU_CLUSTER: 0
8988 11:46:02.711929 CPU_CLUSTER: 0 child on link 0 CPU: 00
8989 11:46:02.721529 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8990 11:46:02.721613 CPU: 00
8991 11:46:02.724917 Done allocating resources.
8992 11:46:02.731678 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8993 11:46:02.731759 Enabling resources...
8994 11:46:02.731839 done.
8995 11:46:02.738122 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8996 11:46:02.738199 Initializing devices...
8997 11:46:02.741373 Root Device init
8998 11:46:02.741470 init hardware done!
8999 11:46:02.745126 0x00000018: ctrlr->caps
9000 11:46:02.747995 52.000 MHz: ctrlr->f_max
9001 11:46:02.748078 0.400 MHz: ctrlr->f_min
9002 11:46:02.751405 0x40ff8080: ctrlr->voltages
9003 11:46:02.754791 sclk: 390625
9004 11:46:02.754905 Bus Width = 1
9005 11:46:02.754986 sclk: 390625
9006 11:46:02.758523 Bus Width = 1
9007 11:46:02.758599 Early init status = 3
9008 11:46:02.764739 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9009 11:46:02.767868 in-header: 03 fb 00 00 01 00 00 00
9010 11:46:02.771019 in-data: 01
9011 11:46:02.774369 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9012 11:46:02.777951 in-header: 03 fb 00 00 01 00 00 00
9013 11:46:02.781366 in-data: 01
9014 11:46:02.784733 [SSUSB] Setting up USB HOST controller...
9015 11:46:02.787898 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9016 11:46:02.791207 [SSUSB] phy power-on done.
9017 11:46:02.794371 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9018 11:46:02.801393 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9019 11:46:02.804501 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9020 11:46:02.811254 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9021 11:46:02.818053 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9022 11:46:02.824340 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9023 11:46:02.831058 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9024 11:46:02.837927 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9025 11:46:02.840928 SPM: binary array size = 0x9dc
9026 11:46:02.844482 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9027 11:46:02.850909 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9028 11:46:02.857436 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9029 11:46:02.864305 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9030 11:46:02.867218 configure_display: Starting display init
9031 11:46:02.901715 anx7625_power_on_init: Init interface.
9032 11:46:02.905267 anx7625_disable_pd_protocol: Disabled PD feature.
9033 11:46:02.907996 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9034 11:46:02.935828 anx7625_start_dp_work: Secure OCM version=00
9035 11:46:02.939289 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9036 11:46:02.954218 sp_tx_get_edid_block: EDID Block = 1
9037 11:46:03.056655 Extracted contents:
9038 11:46:03.060283 header: 00 ff ff ff ff ff ff 00
9039 11:46:03.063392 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9040 11:46:03.066602 version: 01 04
9041 11:46:03.069719 basic params: 95 1f 11 78 0a
9042 11:46:03.073016 chroma info: 76 90 94 55 54 90 27 21 50 54
9043 11:46:03.076392 established: 00 00 00
9044 11:46:03.083033 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9045 11:46:03.086152 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9046 11:46:03.092862 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9047 11:46:03.099524 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9048 11:46:03.106156 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9049 11:46:03.109452 extensions: 00
9050 11:46:03.109530 checksum: fb
9051 11:46:03.109604
9052 11:46:03.112583 Manufacturer: IVO Model 57d Serial Number 0
9053 11:46:03.116399 Made week 0 of 2020
9054 11:46:03.119546 EDID version: 1.4
9055 11:46:03.119648 Digital display
9056 11:46:03.122684 6 bits per primary color channel
9057 11:46:03.122785 DisplayPort interface
9058 11:46:03.126385 Maximum image size: 31 cm x 17 cm
9059 11:46:03.129428 Gamma: 220%
9060 11:46:03.129502 Check DPMS levels
9061 11:46:03.132940 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9062 11:46:03.139497 First detailed timing is preferred timing
9063 11:46:03.139612 Established timings supported:
9064 11:46:03.142577 Standard timings supported:
9065 11:46:03.146076 Detailed timings
9066 11:46:03.149141 Hex of detail: 383680a07038204018303c0035ae10000019
9067 11:46:03.155674 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9068 11:46:03.159255 0780 0798 07c8 0820 hborder 0
9069 11:46:03.162417 0438 043b 0447 0458 vborder 0
9070 11:46:03.165595 -hsync -vsync
9071 11:46:03.165688 Did detailed timing
9072 11:46:03.172512 Hex of detail: 000000000000000000000000000000000000
9073 11:46:03.175782 Manufacturer-specified data, tag 0
9074 11:46:03.178905 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9075 11:46:03.182448 ASCII string: InfoVision
9076 11:46:03.185756 Hex of detail: 000000fe00523134304e574635205248200a
9077 11:46:03.188767 ASCII string: R140NWF5 RH
9078 11:46:03.188850 Checksum
9079 11:46:03.192201 Checksum: 0xfb (valid)
9080 11:46:03.195730 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9081 11:46:03.198602 DSI data_rate: 832800000 bps
9082 11:46:03.205541 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9083 11:46:03.208580 anx7625_parse_edid: pixelclock(138800).
9084 11:46:03.211740 hactive(1920), hsync(48), hfp(24), hbp(88)
9085 11:46:03.215030 vactive(1080), vsync(12), vfp(3), vbp(17)
9086 11:46:03.218582 anx7625_dsi_config: config dsi.
9087 11:46:03.225054 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9088 11:46:03.238619 anx7625_dsi_config: success to config DSI
9089 11:46:03.241803 anx7625_dp_start: MIPI phy setup OK.
9090 11:46:03.245149 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9091 11:46:03.248757 mtk_ddp_mode_set invalid vrefresh 60
9092 11:46:03.251886 main_disp_path_setup
9093 11:46:03.251963 ovl_layer_smi_id_en
9094 11:46:03.254992 ovl_layer_smi_id_en
9095 11:46:03.255072 ccorr_config
9096 11:46:03.255190 aal_config
9097 11:46:03.258327 gamma_config
9098 11:46:03.258411 postmask_config
9099 11:46:03.261694 dither_config
9100 11:46:03.265264 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9101 11:46:03.271724 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9102 11:46:03.275169 Root Device init finished in 530 msecs
9103 11:46:03.278222 CPU_CLUSTER: 0 init
9104 11:46:03.285122 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9105 11:46:03.288022 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9106 11:46:03.291689 APU_MBOX 0x190000b0 = 0x10001
9107 11:46:03.294781 APU_MBOX 0x190001b0 = 0x10001
9108 11:46:03.298335 APU_MBOX 0x190005b0 = 0x10001
9109 11:46:03.301671 APU_MBOX 0x190006b0 = 0x10001
9110 11:46:03.304905 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9111 11:46:03.317793 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9112 11:46:03.329808 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9113 11:46:03.336616 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9114 11:46:03.348477 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9115 11:46:03.357214 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9116 11:46:03.360875 CPU_CLUSTER: 0 init finished in 81 msecs
9117 11:46:03.363947 Devices initialized
9118 11:46:03.367083 Show all devs... After init.
9119 11:46:03.367209 Root Device: enabled 1
9120 11:46:03.370635 CPU_CLUSTER: 0: enabled 1
9121 11:46:03.374229 CPU: 00: enabled 1
9122 11:46:03.377440 BS: BS_DEV_INIT run times (exec / console): 207 / 428 ms
9123 11:46:03.380863 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9124 11:46:03.383705 ELOG: NV offset 0x57f000 size 0x1000
9125 11:46:03.390613 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9126 11:46:03.397091 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9127 11:46:03.400384 ELOG: Event(17) added with size 13 at 2023-11-24 11:46:04 UTC
9128 11:46:03.407303 out: cmd=0x121: 03 db 21 01 00 00 00 00
9129 11:46:03.410302 in-header: 03 fe 00 00 2c 00 00 00
9130 11:46:03.420233 in-data: 65 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9131 11:46:03.427066 ELOG: Event(A1) added with size 10 at 2023-11-24 11:46:04 UTC
9132 11:46:03.433595 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9133 11:46:03.440091 ELOG: Event(A0) added with size 9 at 2023-11-24 11:46:04 UTC
9134 11:46:03.443511 elog_add_boot_reason: Logged dev mode boot
9135 11:46:03.449914 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9136 11:46:03.449998 Finalize devices...
9137 11:46:03.453513 Devices finalized
9138 11:46:03.456954 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9139 11:46:03.459970 Writing coreboot table at 0xffe64000
9140 11:46:03.463280 0. 000000000010a000-0000000000113fff: RAMSTAGE
9141 11:46:03.466881 1. 0000000040000000-00000000400fffff: RAM
9142 11:46:03.473248 2. 0000000040100000-000000004032afff: RAMSTAGE
9143 11:46:03.476743 3. 000000004032b000-00000000545fffff: RAM
9144 11:46:03.479908 4. 0000000054600000-000000005465ffff: BL31
9145 11:46:03.482950 5. 0000000054660000-00000000ffe63fff: RAM
9146 11:46:03.489994 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9147 11:46:03.493137 7. 0000000100000000-000000013fffffff: RAM
9148 11:46:03.496594 Passing 5 GPIOs to payload:
9149 11:46:03.499659 NAME | PORT | POLARITY | VALUE
9150 11:46:03.506405 EC in RW | 0x000000aa | low | undefined
9151 11:46:03.509756 EC interrupt | 0x00000005 | low | undefined
9152 11:46:03.512813 TPM interrupt | 0x000000ab | high | undefined
9153 11:46:03.519743 SD card detect | 0x00000011 | high | undefined
9154 11:46:03.522893 speaker enable | 0x00000093 | high | undefined
9155 11:46:03.526205 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9156 11:46:03.529303 in-header: 03 f4 00 00 02 00 00 00
9157 11:46:03.532747 in-data: 07 00
9158 11:46:03.536036 ADC[4]: Raw value=669327 ID=5
9159 11:46:03.536109 ADC[3]: Raw value=212917 ID=1
9160 11:46:03.539475 RAM Code: 0x51
9161 11:46:03.543371 ADC[6]: Raw value=74778 ID=0
9162 11:46:03.543449 ADC[5]: Raw value=211075 ID=1
9163 11:46:03.546243 SKU Code: 0x1
9164 11:46:03.549309 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7e6
9165 11:46:03.552916 coreboot table: 964 bytes.
9166 11:46:03.556244 IMD ROOT 0. 0xfffff000 0x00001000
9167 11:46:03.559310 IMD SMALL 1. 0xffffe000 0x00001000
9168 11:46:03.563044 RO MCACHE 2. 0xffffc000 0x00001104
9169 11:46:03.566154 CONSOLE 3. 0xfff7c000 0x00080000
9170 11:46:03.569304 FMAP 4. 0xfff7b000 0x00000452
9171 11:46:03.572744 TIME STAMP 5. 0xfff7a000 0x00000910
9172 11:46:03.575792 VBOOT WORK 6. 0xfff66000 0x00014000
9173 11:46:03.579311 RAMOOPS 7. 0xffe66000 0x00100000
9174 11:46:03.582539 COREBOOT 8. 0xffe64000 0x00002000
9175 11:46:03.586034 IMD small region:
9176 11:46:03.589215 IMD ROOT 0. 0xffffec00 0x00000400
9177 11:46:03.592319 VPD 1. 0xffffeb80 0x0000006c
9178 11:46:03.595678 MMC STATUS 2. 0xffffeb60 0x00000004
9179 11:46:03.598981 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9180 11:46:03.602362 Probing TPM: done!
9181 11:46:03.606112 Connected to device vid:did:rid of 1ae0:0028:00
9182 11:46:03.616334 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9183 11:46:03.619500 Initialized TPM device CR50 revision 0
9184 11:46:03.623279 Checking cr50 for pending updates
9185 11:46:03.626997 Reading cr50 TPM mode
9186 11:46:03.635611 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9187 11:46:03.642319 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9188 11:46:03.682423 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9189 11:46:03.686024 Checking segment from ROM address 0x40100000
9190 11:46:03.689536 Checking segment from ROM address 0x4010001c
9191 11:46:03.695459 Loading segment from ROM address 0x40100000
9192 11:46:03.695548 code (compression=0)
9193 11:46:03.705533 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9194 11:46:03.712410 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9195 11:46:03.712571 it's not compressed!
9196 11:46:03.719272 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9197 11:46:03.722432 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9198 11:46:03.742872 Loading segment from ROM address 0x4010001c
9199 11:46:03.742983 Entry Point 0x80000000
9200 11:46:03.745822 Loaded segments
9201 11:46:03.749134 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9202 11:46:03.756028 Jumping to boot code at 0x80000000(0xffe64000)
9203 11:46:03.762946 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9204 11:46:03.769193 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9205 11:46:03.776912 read SPI 0x8eb68 0x74a8: 3222 us, 9268 KB/s, 74.144 Mbps
9206 11:46:03.780710 Checking segment from ROM address 0x40100000
9207 11:46:03.783829 Checking segment from ROM address 0x4010001c
9208 11:46:03.790584 Loading segment from ROM address 0x40100000
9209 11:46:03.790688 code (compression=1)
9210 11:46:03.797337 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9211 11:46:03.807331 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9212 11:46:03.807415 using LZMA
9213 11:46:03.815436 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9214 11:46:03.822088 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9215 11:46:03.825560 Loading segment from ROM address 0x4010001c
9216 11:46:03.825635 Entry Point 0x54601000
9217 11:46:03.828846 Loaded segments
9218 11:46:03.832091 NOTICE: MT8192 bl31_setup
9219 11:46:03.839594 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9220 11:46:03.842399 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9221 11:46:03.845655 WARNING: region 0:
9222 11:46:03.849238 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9223 11:46:03.849314 WARNING: region 1:
9224 11:46:03.855867 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9225 11:46:03.859152 WARNING: region 2:
9226 11:46:03.862376 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9227 11:46:03.865638 WARNING: region 3:
9228 11:46:03.868758 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9229 11:46:03.872202 WARNING: region 4:
9230 11:46:03.878710 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9231 11:46:03.878789 WARNING: region 5:
9232 11:46:03.882492 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9233 11:46:03.885347 WARNING: region 6:
9234 11:46:03.889151 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9235 11:46:03.892614 WARNING: region 7:
9236 11:46:03.895331 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9237 11:46:03.902022 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9238 11:46:03.905539 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9239 11:46:03.909035 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9240 11:46:03.915359 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9241 11:46:03.918959 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9242 11:46:03.921965 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9243 11:46:03.928490 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9244 11:46:03.932147 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9245 11:46:03.938545 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9246 11:46:03.941952 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9247 11:46:03.945541 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9248 11:46:03.952192 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9249 11:46:03.955614 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9250 11:46:03.959127 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9251 11:46:03.965445 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9252 11:46:03.968487 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9253 11:46:03.975392 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9254 11:46:03.978967 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9255 11:46:03.981944 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9256 11:46:03.988515 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9257 11:46:03.991886 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9258 11:46:03.995352 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9259 11:46:04.002269 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9260 11:46:04.005488 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9261 11:46:04.012077 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9262 11:46:04.015293 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9263 11:46:04.021837 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9264 11:46:04.025049 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9265 11:46:04.028495 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9266 11:46:04.035248 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9267 11:46:04.038743 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9268 11:46:04.041870 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9269 11:46:04.048425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9270 11:46:04.052241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9271 11:46:04.055462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9272 11:46:04.058874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9273 11:46:04.065365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9274 11:46:04.068502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9275 11:46:04.072214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9276 11:46:04.075599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9277 11:46:04.082479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9278 11:46:04.085310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9279 11:46:04.088896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9280 11:46:04.092149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9281 11:46:04.098479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9282 11:46:04.101997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9283 11:46:04.105352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9284 11:46:04.108646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9285 11:46:04.115688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9286 11:46:04.118502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9287 11:46:04.125453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9288 11:46:04.129115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9289 11:46:04.132282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9290 11:46:04.138736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9291 11:46:04.141935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9292 11:46:04.148665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9293 11:46:04.152673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9294 11:46:04.158614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9295 11:46:04.161999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9296 11:46:04.168635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9297 11:46:04.172091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9298 11:46:04.175692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9299 11:46:04.181945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9300 11:46:04.185464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9301 11:46:04.191976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9302 11:46:04.195508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9303 11:46:04.201972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9304 11:46:04.205396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9305 11:46:04.208676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9306 11:46:04.215560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9307 11:46:04.218700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9308 11:46:04.225152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9309 11:46:04.228961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9310 11:46:04.235294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9311 11:46:04.238617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9312 11:46:04.242359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9313 11:46:04.248915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9314 11:46:04.252139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9315 11:46:04.258611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9316 11:46:04.262435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9317 11:46:04.268555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9318 11:46:04.271928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9319 11:46:04.278432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9320 11:46:04.282260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9321 11:46:04.285373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9322 11:46:04.292122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9323 11:46:04.295257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9324 11:46:04.302011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9325 11:46:04.305709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9326 11:46:04.308559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9327 11:46:04.315649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9328 11:46:04.318417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9329 11:46:04.325200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9330 11:46:04.328696 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9331 11:46:04.335450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9332 11:46:04.338436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9333 11:46:04.341895 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9334 11:46:04.348342 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9335 11:46:04.351381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9336 11:46:04.355112 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9337 11:46:04.358112 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9338 11:46:04.364936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9339 11:46:04.368101 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9340 11:46:04.374806 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9341 11:46:04.377868 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9342 11:46:04.381293 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9343 11:46:04.387850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9344 11:46:04.391438 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9345 11:46:04.397758 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9346 11:46:04.401133 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9347 11:46:04.408081 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9348 11:46:04.411085 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9349 11:46:04.414542 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9350 11:46:04.421074 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9351 11:46:04.424646 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9352 11:46:04.427627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9353 11:46:04.434544 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9354 11:46:04.437970 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9355 11:46:04.441570 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9356 11:46:04.447691 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9357 11:46:04.451314 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9358 11:46:04.454679 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9359 11:46:04.457738 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9360 11:46:04.464304 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9361 11:46:04.467862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9362 11:46:04.471279 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9363 11:46:04.477570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9364 11:46:04.481246 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9365 11:46:04.488142 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9366 11:46:04.491059 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9367 11:46:04.494658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9368 11:46:04.501082 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9369 11:46:04.504619 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9370 11:46:04.511316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9371 11:46:04.515120 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9372 11:46:04.518021 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9373 11:46:04.524321 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9374 11:46:04.527560 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9375 11:46:04.531143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9376 11:46:04.537863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9377 11:46:04.541209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9378 11:46:04.547734 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9379 11:46:04.551224 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9380 11:46:04.554472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9381 11:46:04.560958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9382 11:46:04.564443 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9383 11:46:04.570770 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9384 11:46:04.574366 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9385 11:46:04.577414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9386 11:46:04.584414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9387 11:46:04.587496 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9388 11:46:04.590871 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9389 11:46:04.597799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9390 11:46:04.600794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9391 11:46:04.607850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9392 11:46:04.610808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9393 11:46:04.614214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9394 11:46:04.620774 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9395 11:46:04.624192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9396 11:46:04.630714 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9397 11:46:04.633943 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9398 11:46:04.637360 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9399 11:46:04.643986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9400 11:46:04.647153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9401 11:46:04.654154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9402 11:46:04.657157 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9403 11:46:04.660797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9404 11:46:04.667159 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9405 11:46:04.670599 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9406 11:46:04.676875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9407 11:46:04.680358 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9408 11:46:04.683931 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9409 11:46:04.690696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9410 11:46:04.693806 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9411 11:46:04.700686 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9412 11:46:04.703556 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9413 11:46:04.706905 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9414 11:46:04.713463 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9415 11:46:04.716710 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9416 11:46:04.720195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9417 11:46:04.726771 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9418 11:46:04.730482 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9419 11:46:04.736593 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9420 11:46:04.740248 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9421 11:46:04.746906 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9422 11:46:04.749895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9423 11:46:04.753588 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9424 11:46:04.760040 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9425 11:46:04.763201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9426 11:46:04.769882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9427 11:46:04.772805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9428 11:46:04.776729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9429 11:46:04.783012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9430 11:46:04.786352 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9431 11:46:04.792749 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9432 11:46:04.796163 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9433 11:46:04.802889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9434 11:46:04.806402 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9435 11:46:04.809337 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9436 11:46:04.816128 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9437 11:46:04.818842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9438 11:46:04.826171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9439 11:46:04.828936 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9440 11:46:04.835537 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9441 11:46:04.839124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9442 11:46:04.842777 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9443 11:46:04.849061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9444 11:46:04.852425 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9445 11:46:04.858931 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9446 11:46:04.862147 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9447 11:46:04.865588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9448 11:46:04.872184 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9449 11:46:04.875128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9450 11:46:04.882020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9451 11:46:04.885389 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9452 11:46:04.891764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9453 11:46:04.895141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9454 11:46:04.898289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9455 11:46:04.904983 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9456 11:46:04.908464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9457 11:46:04.914807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9458 11:46:04.918110 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9459 11:46:04.924781 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9460 11:46:04.928195 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9461 11:46:04.931338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9462 11:46:04.938109 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9463 11:46:04.941575 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9464 11:46:04.947809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9465 11:46:04.951256 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9466 11:46:04.954493 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9467 11:46:04.961301 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9468 11:46:04.964683 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9469 11:46:04.967975 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9470 11:46:04.971172 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9471 11:46:04.977802 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9472 11:46:04.981193 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9473 11:46:04.984373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9474 11:46:04.991283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9475 11:46:04.994209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9476 11:46:04.997865 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9477 11:46:05.004355 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9478 11:46:05.007373 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9479 11:46:05.014012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9480 11:46:05.017228 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9481 11:46:05.020916 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9482 11:46:05.027116 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9483 11:46:05.030729 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9484 11:46:05.034037 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9485 11:46:05.040499 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9486 11:46:05.044335 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9487 11:46:05.050811 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9488 11:46:05.053767 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9489 11:46:05.057354 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9490 11:46:05.063820 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9491 11:46:05.066909 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9492 11:46:05.070369 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9493 11:46:05.076880 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9494 11:46:05.080393 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9495 11:46:05.083863 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9496 11:46:05.090195 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9497 11:46:05.093370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9498 11:46:05.099909 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9499 11:46:05.103292 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9500 11:46:05.106275 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9501 11:46:05.112917 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9502 11:46:05.116338 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9503 11:46:05.123039 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9504 11:46:05.126495 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9505 11:46:05.129732 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9506 11:46:05.133021 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9507 11:46:05.139816 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9508 11:46:05.143107 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9509 11:46:05.146036 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9510 11:46:05.149729 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9511 11:46:05.156382 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9512 11:46:05.159365 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9513 11:46:05.162812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9514 11:46:05.165978 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9515 11:46:05.172754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9516 11:46:05.175817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9517 11:46:05.179473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9518 11:46:05.185794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9519 11:46:05.189362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9520 11:46:05.192432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9521 11:46:05.198957 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9522 11:46:05.202209 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9523 11:46:05.208824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9524 11:46:05.212169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9525 11:46:05.218783 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9526 11:46:05.222084 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9527 11:46:05.225611 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9528 11:46:05.231960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9529 11:46:05.235814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9530 11:46:05.242414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9531 11:46:05.245508 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9532 11:46:05.248727 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9533 11:46:05.255366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9534 11:46:05.258737 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9535 11:46:05.265265 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9536 11:46:05.268262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9537 11:46:05.271813 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9538 11:46:05.278132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9539 11:46:05.281564 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9540 11:46:05.288285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9541 11:46:05.291570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9542 11:46:05.294968 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9543 11:46:05.301511 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9544 11:46:05.304818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9545 11:46:05.311438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9546 11:46:05.315121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9547 11:46:05.321320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9548 11:46:05.324502 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9549 11:46:05.327980 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9550 11:46:05.334889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9551 11:46:05.338179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9552 11:46:05.344540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9553 11:46:05.347921 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9554 11:46:05.351241 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9555 11:46:05.357899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9556 11:46:05.361018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9557 11:46:05.367841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9558 11:46:05.370849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9559 11:46:05.377423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9560 11:46:05.380912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9561 11:46:05.384119 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9562 11:46:05.391190 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9563 11:46:05.394133 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9564 11:46:05.400584 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9565 11:46:05.404384 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9566 11:46:05.407376 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9567 11:46:05.414049 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9568 11:46:05.416912 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9569 11:46:05.423920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9570 11:46:05.427309 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9571 11:46:05.433602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9572 11:46:05.436582 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9573 11:46:05.443388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9574 11:46:05.446636 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9575 11:46:05.450216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9576 11:46:05.456760 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9577 11:46:05.460116 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9578 11:46:05.463717 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9579 11:46:05.469933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9580 11:46:05.473445 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9581 11:46:05.479782 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9582 11:46:05.483190 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9583 11:46:05.489884 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9584 11:46:05.493281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9585 11:46:05.496041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9586 11:46:05.502815 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9587 11:46:05.505878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9588 11:46:05.512830 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9589 11:46:05.516025 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9590 11:46:05.519232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9591 11:46:05.525963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9592 11:46:05.529405 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9593 11:46:05.536170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9594 11:46:05.539694 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9595 11:46:05.545981 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9596 11:46:05.549380 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9597 11:46:05.556028 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9598 11:46:05.559157 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9599 11:46:05.562288 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9600 11:46:05.568849 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9601 11:46:05.572210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9602 11:46:05.579236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9603 11:46:05.582109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9604 11:46:05.588864 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9605 11:46:05.592322 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9606 11:46:05.595365 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9607 11:46:05.601872 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9608 11:46:05.605513 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9609 11:46:05.611844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9610 11:46:05.615192 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9611 11:46:05.621795 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9612 11:46:05.625381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9613 11:46:05.631779 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9614 11:46:05.635090 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9615 11:46:05.638481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9616 11:46:05.644790 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9617 11:46:05.648349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9618 11:46:05.655109 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9619 11:46:05.658073 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9620 11:46:05.664859 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9621 11:46:05.668071 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9622 11:46:05.674841 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9623 11:46:05.677806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9624 11:46:05.681277 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9625 11:46:05.687583 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9626 11:46:05.691259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9627 11:46:05.697645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9628 11:46:05.700934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9629 11:46:05.707931 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9630 11:46:05.710795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9631 11:46:05.717613 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9632 11:46:05.720898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9633 11:46:05.724113 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9634 11:46:05.730799 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9635 11:46:05.734078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9636 11:46:05.740698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9637 11:46:05.743964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9638 11:46:05.750871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9639 11:46:05.754355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9640 11:46:05.757433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9641 11:46:05.764128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9642 11:46:05.767304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9643 11:46:05.774330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9644 11:46:05.777122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9645 11:46:05.783848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9646 11:46:05.787171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9647 11:46:05.793783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9648 11:46:05.797011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9649 11:46:05.803604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9650 11:46:05.806787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9651 11:46:05.813644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9652 11:46:05.816724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9653 11:46:05.823631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9654 11:46:05.826969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9655 11:46:05.833448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9656 11:46:05.837037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9657 11:46:05.843210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9658 11:46:05.846674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9659 11:46:05.853150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9660 11:46:05.856856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9661 11:46:05.863189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9662 11:46:05.866587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9663 11:46:05.873166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9664 11:46:05.876619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9665 11:46:05.883320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9666 11:46:05.886275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9667 11:46:05.892894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9668 11:46:05.896702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9669 11:46:05.902873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9670 11:46:05.906174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9671 11:46:05.909455 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9672 11:46:05.913089 INFO: [APUAPC] vio 0
9673 11:46:05.919372 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9674 11:46:05.922770 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9675 11:46:05.926174 INFO: [APUAPC] D0_APC_0: 0x400510
9676 11:46:05.929397 INFO: [APUAPC] D0_APC_1: 0x0
9677 11:46:05.932684 INFO: [APUAPC] D0_APC_2: 0x1540
9678 11:46:05.935902 INFO: [APUAPC] D0_APC_3: 0x0
9679 11:46:05.939530 INFO: [APUAPC] D1_APC_0: 0xffffffff
9680 11:46:05.942656 INFO: [APUAPC] D1_APC_1: 0xffffffff
9681 11:46:05.945895 INFO: [APUAPC] D1_APC_2: 0x3fffff
9682 11:46:05.949344 INFO: [APUAPC] D1_APC_3: 0x0
9683 11:46:05.952360 INFO: [APUAPC] D2_APC_0: 0xffffffff
9684 11:46:05.955887 INFO: [APUAPC] D2_APC_1: 0xffffffff
9685 11:46:05.959245 INFO: [APUAPC] D2_APC_2: 0x3fffff
9686 11:46:05.959356 INFO: [APUAPC] D2_APC_3: 0x0
9687 11:46:05.965672 INFO: [APUAPC] D3_APC_0: 0xffffffff
9688 11:46:05.969037 INFO: [APUAPC] D3_APC_1: 0xffffffff
9689 11:46:05.972746 INFO: [APUAPC] D3_APC_2: 0x3fffff
9690 11:46:05.972829 INFO: [APUAPC] D3_APC_3: 0x0
9691 11:46:05.975755 INFO: [APUAPC] D4_APC_0: 0xffffffff
9692 11:46:05.979267 INFO: [APUAPC] D4_APC_1: 0xffffffff
9693 11:46:05.982658 INFO: [APUAPC] D4_APC_2: 0x3fffff
9694 11:46:05.986249 INFO: [APUAPC] D4_APC_3: 0x0
9695 11:46:05.989171 INFO: [APUAPC] D5_APC_0: 0xffffffff
9696 11:46:05.992323 INFO: [APUAPC] D5_APC_1: 0xffffffff
9697 11:46:05.995834 INFO: [APUAPC] D5_APC_2: 0x3fffff
9698 11:46:05.999161 INFO: [APUAPC] D5_APC_3: 0x0
9699 11:46:06.002379 INFO: [APUAPC] D6_APC_0: 0xffffffff
9700 11:46:06.005727 INFO: [APUAPC] D6_APC_1: 0xffffffff
9701 11:46:06.009340 INFO: [APUAPC] D6_APC_2: 0x3fffff
9702 11:46:06.012485 INFO: [APUAPC] D6_APC_3: 0x0
9703 11:46:06.015590 INFO: [APUAPC] D7_APC_0: 0xffffffff
9704 11:46:06.018978 INFO: [APUAPC] D7_APC_1: 0xffffffff
9705 11:46:06.021954 INFO: [APUAPC] D7_APC_2: 0x3fffff
9706 11:46:06.025361 INFO: [APUAPC] D7_APC_3: 0x0
9707 11:46:06.028574 INFO: [APUAPC] D8_APC_0: 0xffffffff
9708 11:46:06.032306 INFO: [APUAPC] D8_APC_1: 0xffffffff
9709 11:46:06.035372 INFO: [APUAPC] D8_APC_2: 0x3fffff
9710 11:46:06.038811 INFO: [APUAPC] D8_APC_3: 0x0
9711 11:46:06.041781 INFO: [APUAPC] D9_APC_0: 0xffffffff
9712 11:46:06.045288 INFO: [APUAPC] D9_APC_1: 0xffffffff
9713 11:46:06.048321 INFO: [APUAPC] D9_APC_2: 0x3fffff
9714 11:46:06.051671 INFO: [APUAPC] D9_APC_3: 0x0
9715 11:46:06.055292 INFO: [APUAPC] D10_APC_0: 0xffffffff
9716 11:46:06.058581 INFO: [APUAPC] D10_APC_1: 0xffffffff
9717 11:46:06.061955 INFO: [APUAPC] D10_APC_2: 0x3fffff
9718 11:46:06.064911 INFO: [APUAPC] D10_APC_3: 0x0
9719 11:46:06.068262 INFO: [APUAPC] D11_APC_0: 0xffffffff
9720 11:46:06.071602 INFO: [APUAPC] D11_APC_1: 0xffffffff
9721 11:46:06.075143 INFO: [APUAPC] D11_APC_2: 0x3fffff
9722 11:46:06.078457 INFO: [APUAPC] D11_APC_3: 0x0
9723 11:46:06.081670 INFO: [APUAPC] D12_APC_0: 0xffffffff
9724 11:46:06.084954 INFO: [APUAPC] D12_APC_1: 0xffffffff
9725 11:46:06.088265 INFO: [APUAPC] D12_APC_2: 0x3fffff
9726 11:46:06.091570 INFO: [APUAPC] D12_APC_3: 0x0
9727 11:46:06.094917 INFO: [APUAPC] D13_APC_0: 0xffffffff
9728 11:46:06.098327 INFO: [APUAPC] D13_APC_1: 0xffffffff
9729 11:46:06.101924 INFO: [APUAPC] D13_APC_2: 0x3fffff
9730 11:46:06.104964 INFO: [APUAPC] D13_APC_3: 0x0
9731 11:46:06.108034 INFO: [APUAPC] D14_APC_0: 0xffffffff
9732 11:46:06.111714 INFO: [APUAPC] D14_APC_1: 0xffffffff
9733 11:46:06.114562 INFO: [APUAPC] D14_APC_2: 0x3fffff
9734 11:46:06.118311 INFO: [APUAPC] D14_APC_3: 0x0
9735 11:46:06.121493 INFO: [APUAPC] D15_APC_0: 0xffffffff
9736 11:46:06.124724 INFO: [APUAPC] D15_APC_1: 0xffffffff
9737 11:46:06.128142 INFO: [APUAPC] D15_APC_2: 0x3fffff
9738 11:46:06.131156 INFO: [APUAPC] D15_APC_3: 0x0
9739 11:46:06.134489 INFO: [APUAPC] APC_CON: 0x4
9740 11:46:06.137956 INFO: [NOCDAPC] D0_APC_0: 0x0
9741 11:46:06.141817 INFO: [NOCDAPC] D0_APC_1: 0x0
9742 11:46:06.144863 INFO: [NOCDAPC] D1_APC_0: 0x0
9743 11:46:06.148092 INFO: [NOCDAPC] D1_APC_1: 0xfff
9744 11:46:06.151356 INFO: [NOCDAPC] D2_APC_0: 0x0
9745 11:46:06.151438 INFO: [NOCDAPC] D2_APC_1: 0xfff
9746 11:46:06.154450 INFO: [NOCDAPC] D3_APC_0: 0x0
9747 11:46:06.157647 INFO: [NOCDAPC] D3_APC_1: 0xfff
9748 11:46:06.160906 INFO: [NOCDAPC] D4_APC_0: 0x0
9749 11:46:06.164436 INFO: [NOCDAPC] D4_APC_1: 0xfff
9750 11:46:06.167416 INFO: [NOCDAPC] D5_APC_0: 0x0
9751 11:46:06.171215 INFO: [NOCDAPC] D5_APC_1: 0xfff
9752 11:46:06.174179 INFO: [NOCDAPC] D6_APC_0: 0x0
9753 11:46:06.177597 INFO: [NOCDAPC] D6_APC_1: 0xfff
9754 11:46:06.180967 INFO: [NOCDAPC] D7_APC_0: 0x0
9755 11:46:06.184421 INFO: [NOCDAPC] D7_APC_1: 0xfff
9756 11:46:06.184528 INFO: [NOCDAPC] D8_APC_0: 0x0
9757 11:46:06.187543 INFO: [NOCDAPC] D8_APC_1: 0xfff
9758 11:46:06.190681 INFO: [NOCDAPC] D9_APC_0: 0x0
9759 11:46:06.194249 INFO: [NOCDAPC] D9_APC_1: 0xfff
9760 11:46:06.197323 INFO: [NOCDAPC] D10_APC_0: 0x0
9761 11:46:06.200965 INFO: [NOCDAPC] D10_APC_1: 0xfff
9762 11:46:06.203939 INFO: [NOCDAPC] D11_APC_0: 0x0
9763 11:46:06.207257 INFO: [NOCDAPC] D11_APC_1: 0xfff
9764 11:46:06.210590 INFO: [NOCDAPC] D12_APC_0: 0x0
9765 11:46:06.213823 INFO: [NOCDAPC] D12_APC_1: 0xfff
9766 11:46:06.217229 INFO: [NOCDAPC] D13_APC_0: 0x0
9767 11:46:06.220397 INFO: [NOCDAPC] D13_APC_1: 0xfff
9768 11:46:06.223947 INFO: [NOCDAPC] D14_APC_0: 0x0
9769 11:46:06.227233 INFO: [NOCDAPC] D14_APC_1: 0xfff
9770 11:46:06.230685 INFO: [NOCDAPC] D15_APC_0: 0x0
9771 11:46:06.230767 INFO: [NOCDAPC] D15_APC_1: 0xfff
9772 11:46:06.233863 INFO: [NOCDAPC] APC_CON: 0x4
9773 11:46:06.237237 INFO: [APUAPC] set_apusys_apc done
9774 11:46:06.240454 INFO: [DEVAPC] devapc_init done
9775 11:46:06.247041 INFO: GICv3 without legacy support detected.
9776 11:46:06.250181 INFO: ARM GICv3 driver initialized in EL3
9777 11:46:06.253819 INFO: Maximum SPI INTID supported: 639
9778 11:46:06.257065 INFO: BL31: Initializing runtime services
9779 11:46:06.263576 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9780 11:46:06.266866 INFO: SPM: enable CPC mode
9781 11:46:06.270216 INFO: mcdi ready for mcusys-off-idle and system suspend
9782 11:46:06.276573 INFO: BL31: Preparing for EL3 exit to normal world
9783 11:46:06.279894 INFO: Entry point address = 0x80000000
9784 11:46:06.279977 INFO: SPSR = 0x8
9785 11:46:06.286818
9786 11:46:06.286900
9787 11:46:06.286965
9788 11:46:06.290620 Starting depthcharge on Spherion...
9789 11:46:06.290729
9790 11:46:06.290828 Wipe memory regions:
9791 11:46:06.290893
9792 11:46:06.291539 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9793 11:46:06.291637 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9794 11:46:06.291977 Setting prompt string to ['asurada:']
9795 11:46:06.292062 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9796 11:46:06.293890 [0x00000040000000, 0x00000054600000)
9797 11:46:06.415576
9798 11:46:06.415689 [0x00000054660000, 0x00000080000000)
9799 11:46:06.675970
9800 11:46:06.676097 [0x000000821a7280, 0x000000ffe64000)
9801 11:46:07.420063
9802 11:46:07.420604 [0x00000100000000, 0x00000140000000)
9803 11:46:07.799555
9804 11:46:07.802745 Initializing XHCI USB controller at 0x11200000.
9805 11:46:08.840540
9806 11:46:08.843677 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9807 11:46:08.843772
9808 11:46:08.843838
9809 11:46:08.843900
9810 11:46:08.844182 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9812 11:46:08.944590 asurada: tftpboot 192.168.201.1 12074028/tftp-deploy-zv9inh5g/kernel/image.itb 12074028/tftp-deploy-zv9inh5g/kernel/cmdline
9813 11:46:08.944717 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9814 11:46:08.944836 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9815 11:46:08.948949 tftpboot 192.168.201.1 12074028/tftp-deploy-zv9inh5g/kernel/image.itp-deploy-zv9inh5g/kernel/cmdline
9816 11:46:08.949034
9817 11:46:08.949100 Waiting for link
9818 11:46:09.109699
9819 11:46:09.109827 R8152: Initializing
9820 11:46:09.109896
9821 11:46:09.112727 Version 9 (ocp_data = 6010)
9822 11:46:09.112810
9823 11:46:09.116157 R8152: Done initializing
9824 11:46:09.116240
9825 11:46:09.116305 Adding net device
9826 11:46:11.128768
9827 11:46:11.129336 done.
9828 11:46:11.129714
9829 11:46:11.130102 MAC: 00:e0:4c:68:03:bd
9830 11:46:11.130442
9831 11:46:11.132025 Sending DHCP discover... done.
9832 11:46:11.132489
9833 11:46:16.201859 Waiting for reply... done.
9834 11:46:16.202467
9835 11:46:16.202850 Sending DHCP request... done.
9836 11:46:16.205144
9837 11:46:16.205615 Waiting for reply... done.
9838 11:46:16.208366
9839 11:46:16.208864 My ip is 192.168.201.16
9840 11:46:16.209236
9841 11:46:16.211568 The DHCP server ip is 192.168.201.1
9842 11:46:16.212033
9843 11:46:16.214749 TFTP server IP predefined by user: 192.168.201.1
9844 11:46:16.215510
9845 11:46:16.221975 Bootfile predefined by user: 12074028/tftp-deploy-zv9inh5g/kernel/image.itb
9846 11:46:16.222539
9847 11:46:16.225422 Sending tftp read request... done.
9848 11:46:16.225890
9849 11:46:16.234215 Waiting for the transfer...
9850 11:46:16.234692
9851 11:46:16.633771 00000000 ################################################################
9852 11:46:16.634301
9853 11:46:16.949148 00080000 ################################################################
9854 11:46:16.949293
9855 11:46:17.231006 00100000 ################################################################
9856 11:46:17.231144
9857 11:46:17.491894 00180000 ################################################################
9858 11:46:17.492026
9859 11:46:17.742678 00200000 ################################################################
9860 11:46:17.742816
9861 11:46:17.997507 00280000 ################################################################
9862 11:46:17.997643
9863 11:46:18.248672 00300000 ################################################################
9864 11:46:18.248805
9865 11:46:18.499563 00380000 ################################################################
9866 11:46:18.499693
9867 11:46:18.750325 00400000 ################################################################
9868 11:46:18.750460
9869 11:46:19.001189 00480000 ################################################################
9870 11:46:19.001325
9871 11:46:19.251816 00500000 ################################################################
9872 11:46:19.251952
9873 11:46:19.503059 00580000 ################################################################
9874 11:46:19.503189
9875 11:46:19.753906 00600000 ################################################################
9876 11:46:19.754069
9877 11:46:20.005056 00680000 ################################################################
9878 11:46:20.005188
9879 11:46:20.255524 00700000 ################################################################
9880 11:46:20.255665
9881 11:46:20.505825 00780000 ################################################################
9882 11:46:20.505963
9883 11:46:20.760526 00800000 ################################################################
9884 11:46:20.760659
9885 11:46:21.051069 00880000 ################################################################
9886 11:46:21.051219
9887 11:46:21.352838 00900000 ################################################################
9888 11:46:21.353001
9889 11:46:21.633183 00980000 ################################################################
9890 11:46:21.633326
9891 11:46:21.914046 00a00000 ################################################################
9892 11:46:21.914211
9893 11:46:22.277019 00a80000 ################################################################
9894 11:46:22.277538
9895 11:46:22.568289 00b00000 ################################################################
9896 11:46:22.568428
9897 11:46:22.848753 00b80000 ################################################################
9898 11:46:22.848886
9899 11:46:23.129491 00c00000 ################################################################
9900 11:46:23.129621
9901 11:46:23.417609 00c80000 ################################################################
9902 11:46:23.417746
9903 11:46:23.707862 00d00000 ################################################################
9904 11:46:23.707992
9905 11:46:23.988126 00d80000 ################################################################
9906 11:46:23.988254
9907 11:46:24.267482 00e00000 ################################################################
9908 11:46:24.267613
9909 11:46:24.560444 00e80000 ################################################################
9910 11:46:24.560606
9911 11:46:24.851950 00f00000 ################################################################
9912 11:46:24.852085
9913 11:46:25.153767 00f80000 ################################################################
9914 11:46:25.153904
9915 11:46:25.440880 01000000 ################################################################
9916 11:46:25.441013
9917 11:46:25.724235 01080000 ################################################################
9918 11:46:25.724367
9919 11:46:26.005202 01100000 ################################################################
9920 11:46:26.005339
9921 11:46:26.286330 01180000 ################################################################
9922 11:46:26.286463
9923 11:46:26.564680 01200000 ################################################################
9924 11:46:26.564819
9925 11:46:26.852305 01280000 ################################################################
9926 11:46:26.852451
9927 11:46:27.104286 01300000 ################################################################
9928 11:46:27.104421
9929 11:46:27.356335 01380000 ################################################################
9930 11:46:27.356501
9931 11:46:27.607734 01400000 ################################################################
9932 11:46:27.607884
9933 11:46:27.858678 01480000 ################################################################
9934 11:46:27.858820
9935 11:46:28.109556 01500000 ################################################################
9936 11:46:28.109703
9937 11:46:28.360451 01580000 ################################################################
9938 11:46:28.360629
9939 11:46:28.610982 01600000 ################################################################
9940 11:46:28.611143
9941 11:46:28.861871 01680000 ################################################################
9942 11:46:28.861998
9943 11:46:29.138536 01700000 ################################################################
9944 11:46:29.138696
9945 11:46:29.418968 01780000 ################################################################
9946 11:46:29.419100
9947 11:46:29.697151 01800000 ################################################################
9948 11:46:29.697290
9949 11:46:29.969323 01880000 ################################################################
9950 11:46:29.969460
9951 11:46:30.234572 01900000 ################################################################
9952 11:46:30.234707
9953 11:46:30.485034 01980000 ################################################################
9954 11:46:30.485167
9955 11:46:30.735814 01a00000 ################################################################
9956 11:46:30.735955
9957 11:46:31.006394 01a80000 ################################################################
9958 11:46:31.006535
9959 11:46:31.287399 01b00000 ################################################################
9960 11:46:31.287540
9961 11:46:31.319199 01b80000 ######## done.
9962 11:46:31.319289
9963 11:46:31.322483 The bootfile was 28895762 bytes long.
9964 11:46:31.322573
9965 11:46:31.325987 Sending tftp read request... done.
9966 11:46:31.326157
9967 11:46:31.329126 Waiting for the transfer...
9968 11:46:31.329293
9969 11:46:31.329370 00000000 # done.
9970 11:46:31.329444
9971 11:46:31.339107 Command line loaded dynamically from TFTP file: 12074028/tftp-deploy-zv9inh5g/kernel/cmdline
9972 11:46:31.339301
9973 11:46:31.358962 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9974 11:46:31.359233
9975 11:46:31.362632 Loading FIT.
9976 11:46:31.362931
9977 11:46:31.365549 Image ramdisk-1 has 17798204 bytes.
9978 11:46:31.365844
9979 11:46:31.368890 Image fdt-1 has 47278 bytes.
9980 11:46:31.369229
9981 11:46:31.369444 Image kernel-1 has 11048246 bytes.
9982 11:46:31.372340
9983 11:46:31.378991 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
9984 11:46:31.379493
9985 11:46:31.398598 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9986 11:46:31.399212
9987 11:46:31.402007 Choosing best match conf-1 for compat google,spherion.
9988 11:46:31.405973
9989 11:46:31.410659 Connected to device vid:did:rid of 1ae0:0028:00
9990 11:46:31.417736
9991 11:46:31.421224 tpm_get_response: command 0x17b, return code 0x0
9992 11:46:31.421799
9993 11:46:31.424339 ec_init: CrosEC protocol v3 supported (256, 248)
9994 11:46:31.428362
9995 11:46:31.431738 tpm_cleanup: add release locality here.
9996 11:46:31.432312
9997 11:46:31.432733 Shutting down all USB controllers.
9998 11:46:31.435197
9999 11:46:31.435773 Removing current net device
10000 11:46:31.436151
10001 11:46:31.441607 Exiting depthcharge with code 4 at timestamp: 53370133
10002 11:46:31.442095
10003 11:46:31.444803 LZMA decompressing kernel-1 to 0x821a6718
10004 11:46:31.445276
10005 11:46:31.448250 LZMA decompressing kernel-1 to 0x40000000
10006 11:46:32.836389
10007 11:46:32.837029 jumping to kernel
10008 11:46:32.838749 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10009 11:46:32.839288 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10010 11:46:32.839698 Setting prompt string to ['Linux version [0-9]']
10011 11:46:32.840080 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10012 11:46:32.840473 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10013 11:46:32.886336
10014 11:46:32.889911 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10015 11:46:32.893758 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10016 11:46:32.894363 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10017 11:46:32.894766 Setting prompt string to []
10018 11:46:32.895197 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10019 11:46:32.895737 Using line separator: #'\n'#
10020 11:46:32.896131 No login prompt set.
10021 11:46:32.896486 Parsing kernel messages
10022 11:46:32.896866 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10023 11:46:32.897442 [login-action] Waiting for messages, (timeout 00:04:00)
10024 11:46:32.913105 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10025 11:46:32.915961 [ 0.000000] random: crng init done
10026 11:46:32.922393 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10027 11:46:32.926313 [ 0.000000] efi: UEFI not found.
10028 11:46:32.932981 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10029 11:46:32.942437 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10030 11:46:32.949095 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10031 11:46:32.959341 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10032 11:46:32.965751 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10033 11:46:32.972435 [ 0.000000] printk: bootconsole [mtk8250] enabled
10034 11:46:32.978845 [ 0.000000] NUMA: No NUMA configuration found
10035 11:46:32.985772 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10036 11:46:32.988578 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10037 11:46:32.992346 [ 0.000000] Zone ranges:
10038 11:46:32.998532 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10039 11:46:33.001615 [ 0.000000] DMA32 empty
10040 11:46:33.008400 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10041 11:46:33.011540 [ 0.000000] Movable zone start for each node
10042 11:46:33.014856 [ 0.000000] Early memory node ranges
10043 11:46:33.021634 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10044 11:46:33.028361 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10045 11:46:33.034989 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10046 11:46:33.041610 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10047 11:46:33.048007 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10048 11:46:33.054618 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10049 11:46:33.084642 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10050 11:46:33.091336 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10051 11:46:33.097586 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10052 11:46:33.100985 [ 0.000000] psci: probing for conduit method from DT.
10053 11:46:33.107819 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10054 11:46:33.110983 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10055 11:46:33.117405 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10056 11:46:33.120791 [ 0.000000] psci: SMC Calling Convention v1.2
10057 11:46:33.127366 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10058 11:46:33.130792 [ 0.000000] Detected VIPT I-cache on CPU0
10059 11:46:33.137407 [ 0.000000] CPU features: detected: GIC system register CPU interface
10060 11:46:33.144040 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10061 11:46:33.150539 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10062 11:46:33.157010 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10063 11:46:33.167132 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10064 11:46:33.173383 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10065 11:46:33.176934 [ 0.000000] alternatives: applying boot alternatives
10066 11:46:33.183523 [ 0.000000] Fallback order for Node 0: 0
10067 11:46:33.190402 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10068 11:46:33.193433 [ 0.000000] Policy zone: Normal
10069 11:46:33.216770 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10070 11:46:33.226546 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10071 11:46:33.236495 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10072 11:46:33.242721 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10073 11:46:33.249476 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10074 11:46:33.256039 <6>[ 0.000000] software IO TLB: area num 8.
10075 11:46:33.311073 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10076 11:46:33.391830 <6>[ 0.000000] Memory: 3837828K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 320636K reserved, 32768K cma-reserved)
10077 11:46:33.398577 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10078 11:46:33.404975 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10079 11:46:33.408337 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10080 11:46:33.415189 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10081 11:46:33.421341 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10082 11:46:33.425057 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10083 11:46:33.434853 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10084 11:46:33.441138 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10085 11:46:33.447540 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10086 11:46:33.454315 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10087 11:46:33.457398 <6>[ 0.000000] GICv3: 608 SPIs implemented
10088 11:46:33.460824 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10089 11:46:33.467741 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10090 11:46:33.470887 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10091 11:46:33.477396 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10092 11:46:33.491295 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10093 11:46:33.503994 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10094 11:46:33.510334 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10095 11:46:33.517832 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10096 11:46:33.531292 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10097 11:46:33.537748 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10098 11:46:33.544449 <6>[ 0.009179] Console: colour dummy device 80x25
10099 11:46:33.554614 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10100 11:46:33.560870 <6>[ 0.024374] pid_max: default: 32768 minimum: 301
10101 11:46:33.564088 <6>[ 0.029245] LSM: Security Framework initializing
10102 11:46:33.571009 <6>[ 0.034156] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10103 11:46:33.580801 <6>[ 0.041811] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10104 11:46:33.587422 <6>[ 0.051021] cblist_init_generic: Setting adjustable number of callback queues.
10105 11:46:33.593994 <6>[ 0.058462] cblist_init_generic: Setting shift to 3 and lim to 1.
10106 11:46:33.603864 <6>[ 0.064815] cblist_init_generic: Setting adjustable number of callback queues.
10107 11:46:33.610455 <6>[ 0.072242] cblist_init_generic: Setting shift to 3 and lim to 1.
10108 11:46:33.613751 <6>[ 0.078641] rcu: Hierarchical SRCU implementation.
10109 11:46:33.620246 <6>[ 0.083657] rcu: Max phase no-delay instances is 1000.
10110 11:46:33.627055 <6>[ 0.090670] EFI services will not be available.
10111 11:46:33.630291 <6>[ 0.095619] smp: Bringing up secondary CPUs ...
10112 11:46:33.638630 <6>[ 0.100689] Detected VIPT I-cache on CPU1
10113 11:46:33.645353 <6>[ 0.100757] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10114 11:46:33.651596 <6>[ 0.100788] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10115 11:46:33.655067 <6>[ 0.101124] Detected VIPT I-cache on CPU2
10116 11:46:33.661442 <6>[ 0.101175] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10117 11:46:33.671477 <6>[ 0.101192] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10118 11:46:33.674711 <6>[ 0.101450] Detected VIPT I-cache on CPU3
10119 11:46:33.681428 <6>[ 0.101494] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10120 11:46:33.687994 <6>[ 0.101508] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10121 11:46:33.691111 <6>[ 0.101808] CPU features: detected: Spectre-v4
10122 11:46:33.698080 <6>[ 0.101815] CPU features: detected: Spectre-BHB
10123 11:46:33.701100 <6>[ 0.101820] Detected PIPT I-cache on CPU4
10124 11:46:33.707982 <6>[ 0.101876] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10125 11:46:33.714359 <6>[ 0.101892] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10126 11:46:33.720995 <6>[ 0.102183] Detected PIPT I-cache on CPU5
10127 11:46:33.727755 <6>[ 0.102244] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10128 11:46:33.734507 <6>[ 0.102260] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10129 11:46:33.737534 <6>[ 0.102540] Detected PIPT I-cache on CPU6
10130 11:46:33.744048 <6>[ 0.102601] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10131 11:46:33.750901 <6>[ 0.102617] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10132 11:46:33.757264 <6>[ 0.102915] Detected PIPT I-cache on CPU7
10133 11:46:33.763952 <6>[ 0.102980] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10134 11:46:33.770494 <6>[ 0.102996] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10135 11:46:33.773613 <6>[ 0.103043] smp: Brought up 1 node, 8 CPUs
10136 11:46:33.780568 <6>[ 0.244426] SMP: Total of 8 processors activated.
10137 11:46:33.783680 <6>[ 0.249377] CPU features: detected: 32-bit EL0 Support
10138 11:46:33.793388 <6>[ 0.254740] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10139 11:46:33.800261 <6>[ 0.263540] CPU features: detected: Common not Private translations
10140 11:46:33.807206 <6>[ 0.270015] CPU features: detected: CRC32 instructions
10141 11:46:33.810075 <6>[ 0.275367] CPU features: detected: RCpc load-acquire (LDAPR)
10142 11:46:33.816876 <6>[ 0.281326] CPU features: detected: LSE atomic instructions
10143 11:46:33.823104 <6>[ 0.287108] CPU features: detected: Privileged Access Never
10144 11:46:33.829945 <6>[ 0.292887] CPU features: detected: RAS Extension Support
10145 11:46:33.836580 <6>[ 0.298496] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10146 11:46:33.839993 <6>[ 0.305713] CPU: All CPU(s) started at EL2
10147 11:46:33.846269 <6>[ 0.310030] alternatives: applying system-wide alternatives
10148 11:46:33.855098 <6>[ 0.319871] devtmpfs: initialized
10149 11:46:33.870335 <6>[ 0.328224] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10150 11:46:33.876949 <6>[ 0.338185] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10151 11:46:33.883356 <6>[ 0.346412] pinctrl core: initialized pinctrl subsystem
10152 11:46:33.886678 <6>[ 0.353094] DMI not present or invalid.
10153 11:46:33.893145 <6>[ 0.357497] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10154 11:46:33.903150 <6>[ 0.364375] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10155 11:46:33.909800 <6>[ 0.371824] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10156 11:46:33.919683 <6>[ 0.379914] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10157 11:46:33.923062 <6>[ 0.388071] audit: initializing netlink subsys (disabled)
10158 11:46:33.932680 <5>[ 0.393768] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10159 11:46:33.939135 <6>[ 0.394464] thermal_sys: Registered thermal governor 'step_wise'
10160 11:46:33.945584 <6>[ 0.401733] thermal_sys: Registered thermal governor 'power_allocator'
10161 11:46:33.949153 <6>[ 0.407990] cpuidle: using governor menu
10162 11:46:33.955650 <6>[ 0.418947] NET: Registered PF_QIPCRTR protocol family
10163 11:46:33.962363 <6>[ 0.424444] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10164 11:46:33.968769 <6>[ 0.431544] ASID allocator initialised with 32768 entries
10165 11:46:33.972152 <6>[ 0.438089] Serial: AMBA PL011 UART driver
10166 11:46:33.982188 <4>[ 0.446903] Trying to register duplicate clock ID: 134
10167 11:46:34.038845 <6>[ 0.506530] KASLR enabled
10168 11:46:34.053044 <6>[ 0.514254] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10169 11:46:34.059465 <6>[ 0.521268] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10170 11:46:34.065785 <6>[ 0.527758] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10171 11:46:34.072634 <6>[ 0.534764] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10172 11:46:34.079327 <6>[ 0.541248] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10173 11:46:34.085725 <6>[ 0.548251] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10174 11:46:34.092496 <6>[ 0.554739] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10175 11:46:34.098763 <6>[ 0.561742] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10176 11:46:34.102285 <6>[ 0.569199] ACPI: Interpreter disabled.
10177 11:46:34.111461 <6>[ 0.575620] iommu: Default domain type: Translated
10178 11:46:34.117896 <6>[ 0.580733] iommu: DMA domain TLB invalidation policy: strict mode
10179 11:46:34.120988 <5>[ 0.587392] SCSI subsystem initialized
10180 11:46:34.127531 <6>[ 0.591552] usbcore: registered new interface driver usbfs
10181 11:46:34.134361 <6>[ 0.597284] usbcore: registered new interface driver hub
10182 11:46:34.137425 <6>[ 0.602836] usbcore: registered new device driver usb
10183 11:46:34.144447 <6>[ 0.608941] pps_core: LinuxPPS API ver. 1 registered
10184 11:46:34.154147 <6>[ 0.614136] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10185 11:46:34.157314 <6>[ 0.623482] PTP clock support registered
10186 11:46:34.160777 <6>[ 0.627725] EDAC MC: Ver: 3.0.0
10187 11:46:34.168339 <6>[ 0.632885] FPGA manager framework
10188 11:46:34.174771 <6>[ 0.636565] Advanced Linux Sound Architecture Driver Initialized.
10189 11:46:34.178150 <6>[ 0.643332] vgaarb: loaded
10190 11:46:34.184719 <6>[ 0.646506] clocksource: Switched to clocksource arch_sys_counter
10191 11:46:34.188149 <5>[ 0.652922] VFS: Disk quotas dquot_6.6.0
10192 11:46:34.194726 <6>[ 0.657104] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10193 11:46:34.197609 <6>[ 0.664291] pnp: PnP ACPI: disabled
10194 11:46:34.206343 <6>[ 0.670912] NET: Registered PF_INET protocol family
10195 11:46:34.212808 <6>[ 0.676291] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10196 11:46:34.224821 <6>[ 0.686227] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10197 11:46:34.234975 <6>[ 0.695013] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10198 11:46:34.241466 <6>[ 0.702975] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10199 11:46:34.247947 <6>[ 0.711379] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10200 11:46:34.258736 <6>[ 0.720020] TCP: Hash tables configured (established 32768 bind 32768)
10201 11:46:34.265162 <6>[ 0.726863] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10202 11:46:34.272314 <6>[ 0.733882] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10203 11:46:34.278325 <6>[ 0.741392] NET: Registered PF_UNIX/PF_LOCAL protocol family
10204 11:46:34.285056 <6>[ 0.747543] RPC: Registered named UNIX socket transport module.
10205 11:46:34.288348 <6>[ 0.753698] RPC: Registered udp transport module.
10206 11:46:34.295042 <6>[ 0.758633] RPC: Registered tcp transport module.
10207 11:46:34.301565 <6>[ 0.763567] RPC: Registered tcp NFSv4.1 backchannel transport module.
10208 11:46:34.304926 <6>[ 0.770235] PCI: CLS 0 bytes, default 64
10209 11:46:34.308158 <6>[ 0.774602] Unpacking initramfs...
10210 11:46:34.333262 <6>[ 0.794592] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10211 11:46:34.343106 <6>[ 0.803241] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10212 11:46:34.346435 <6>[ 0.812089] kvm [1]: IPA Size Limit: 40 bits
10213 11:46:34.353240 <6>[ 0.816615] kvm [1]: GICv3: no GICV resource entry
10214 11:46:34.356131 <6>[ 0.821639] kvm [1]: disabling GICv2 emulation
10215 11:46:34.362967 <6>[ 0.826325] kvm [1]: GIC system register CPU interface enabled
10216 11:46:34.366050 <6>[ 0.832491] kvm [1]: vgic interrupt IRQ18
10217 11:46:34.372737 <6>[ 0.836848] kvm [1]: VHE mode initialized successfully
10218 11:46:34.379332 <5>[ 0.843231] Initialise system trusted keyrings
10219 11:46:34.385810 <6>[ 0.848059] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10220 11:46:34.393385 <6>[ 0.858094] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10221 11:46:34.399908 <5>[ 0.864566] NFS: Registering the id_resolver key type
10222 11:46:34.403207 <5>[ 0.869879] Key type id_resolver registered
10223 11:46:34.409891 <5>[ 0.874293] Key type id_legacy registered
10224 11:46:34.416886 <6>[ 0.878570] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10225 11:46:34.422990 <6>[ 0.885493] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10226 11:46:34.429752 <6>[ 0.893258] 9p: Installing v9fs 9p2000 file system support
10227 11:46:34.465988 <5>[ 0.930580] Key type asymmetric registered
10228 11:46:34.469070 <5>[ 0.934914] Asymmetric key parser 'x509' registered
10229 11:46:34.479302 <6>[ 0.940054] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10230 11:46:34.482813 <6>[ 0.947698] io scheduler mq-deadline registered
10231 11:46:34.485667 <6>[ 0.952470] io scheduler kyber registered
10232 11:46:34.504850 <6>[ 0.969644] EINJ: ACPI disabled.
10233 11:46:34.538213 <4>[ 0.996090] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10234 11:46:34.547955 <4>[ 1.006770] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10235 11:46:34.563104 <6>[ 1.027789] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10236 11:46:34.571186 <6>[ 1.035840] printk: console [ttyS0] disabled
10237 11:46:34.599103 <6>[ 1.060486] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10238 11:46:34.605670 <6>[ 1.069962] printk: console [ttyS0] enabled
10239 11:46:34.609381 <6>[ 1.069962] printk: console [ttyS0] enabled
10240 11:46:34.616146 <6>[ 1.078855] printk: bootconsole [mtk8250] disabled
10241 11:46:34.619036 <6>[ 1.078855] printk: bootconsole [mtk8250] disabled
10242 11:46:34.625588 <6>[ 1.090098] SuperH (H)SCI(F) driver initialized
10243 11:46:34.628957 <6>[ 1.095364] msm_serial: driver initialized
10244 11:46:34.643041 <6>[ 1.104356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10245 11:46:34.653239 <6>[ 1.112902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10246 11:46:34.659218 <6>[ 1.121443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10247 11:46:34.669515 <6>[ 1.130071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10248 11:46:34.679506 <6>[ 1.138778] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10249 11:46:34.686024 <6>[ 1.147500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10250 11:46:34.695996 <6>[ 1.156042] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10251 11:46:34.702842 <6>[ 1.164849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10252 11:46:34.712616 <6>[ 1.173394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10253 11:46:34.724243 <6>[ 1.188940] loop: module loaded
10254 11:46:34.730749 <6>[ 1.194965] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10255 11:46:34.753343 <4>[ 1.218378] mtk-pmic-keys: Failed to locate of_node [id: -1]
10256 11:46:34.760473 <6>[ 1.225413] megasas: 07.719.03.00-rc1
10257 11:46:34.770538 <6>[ 1.235032] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10258 11:46:34.777269 <6>[ 1.241917] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10259 11:46:34.793982 <6>[ 1.258595] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10260 11:46:34.850250 <6>[ 1.308389] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10261 11:46:35.052699 <6>[ 1.517420] Freeing initrd memory: 17376K
10262 11:46:35.063185 <6>[ 1.527848] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10263 11:46:35.074374 <6>[ 1.538754] tun: Universal TUN/TAP device driver, 1.6
10264 11:46:35.077330 <6>[ 1.544808] thunder_xcv, ver 1.0
10265 11:46:35.081125 <6>[ 1.548310] thunder_bgx, ver 1.0
10266 11:46:35.083732 <6>[ 1.551802] nicpf, ver 1.0
10267 11:46:35.094682 <6>[ 1.555820] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10268 11:46:35.097734 <6>[ 1.563295] hns3: Copyright (c) 2017 Huawei Corporation.
10269 11:46:35.104565 <6>[ 1.568881] hclge is initializing
10270 11:46:35.107618 <6>[ 1.572460] e1000: Intel(R) PRO/1000 Network Driver
10271 11:46:35.114235 <6>[ 1.577589] e1000: Copyright (c) 1999-2006 Intel Corporation.
10272 11:46:35.117564 <6>[ 1.583602] e1000e: Intel(R) PRO/1000 Network Driver
10273 11:46:35.124124 <6>[ 1.588817] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10274 11:46:35.130983 <6>[ 1.595004] igb: Intel(R) Gigabit Ethernet Network Driver
10275 11:46:35.137319 <6>[ 1.600654] igb: Copyright (c) 2007-2014 Intel Corporation.
10276 11:46:35.143899 <6>[ 1.606493] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10277 11:46:35.150677 <6>[ 1.613017] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10278 11:46:35.153825 <6>[ 1.619483] sky2: driver version 1.30
10279 11:46:35.160251 <6>[ 1.624479] VFIO - User Level meta-driver version: 0.3
10280 11:46:35.168045 <6>[ 1.632778] usbcore: registered new interface driver usb-storage
10281 11:46:35.174717 <6>[ 1.639223] usbcore: registered new device driver onboard-usb-hub
10282 11:46:35.183955 <6>[ 1.648415] mt6397-rtc mt6359-rtc: registered as rtc0
10283 11:46:35.193610 <6>[ 1.653893] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:46:35 UTC (1700826395)
10284 11:46:35.197015 <6>[ 1.663511] i2c_dev: i2c /dev entries driver
10285 11:46:35.213825 <6>[ 1.675304] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10286 11:46:35.234400 <6>[ 1.699281] cpu cpu0: EM: created perf domain
10287 11:46:35.238057 <6>[ 1.704207] cpu cpu4: EM: created perf domain
10288 11:46:35.244985 <6>[ 1.709685] sdhci: Secure Digital Host Controller Interface driver
10289 11:46:35.251902 <6>[ 1.716117] sdhci: Copyright(c) Pierre Ossman
10290 11:46:35.258272 <6>[ 1.721025] Synopsys Designware Multimedia Card Interface Driver
10291 11:46:35.264883 <6>[ 1.727623] sdhci-pltfm: SDHCI platform and OF driver helper
10292 11:46:35.267959 <6>[ 1.727781] mmc0: CQHCI version 5.10
10293 11:46:35.275124 <6>[ 1.737697] ledtrig-cpu: registered to indicate activity on CPUs
10294 11:46:35.281276 <6>[ 1.744673] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10295 11:46:35.288146 <6>[ 1.751718] usbcore: registered new interface driver usbhid
10296 11:46:35.291420 <6>[ 1.757542] usbhid: USB HID core driver
10297 11:46:35.297994 <6>[ 1.761734] spi_master spi0: will run message pump with realtime priority
10298 11:46:35.343542 <6>[ 1.801354] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10299 11:46:35.361804 <6>[ 1.816777] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10300 11:46:35.365219 <6>[ 1.830343] mmc0: Command Queue Engine enabled
10301 11:46:35.372062 <6>[ 1.835120] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10302 11:46:35.378637 <6>[ 1.842417] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10303 11:46:35.382130 <6>[ 1.847468] cros-ec-spi spi0.0: Chrome EC device registered
10304 11:46:35.389046 <6>[ 1.851130] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10305 11:46:35.396236 <6>[ 1.860914] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10306 11:46:35.403179 <6>[ 1.867100] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10307 11:46:35.409775 <6>[ 1.873033] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10308 11:46:35.427442 <6>[ 1.888565] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10309 11:46:35.434500 <6>[ 1.899085] NET: Registered PF_PACKET protocol family
10310 11:46:35.437539 <6>[ 1.904473] 9pnet: Installing 9P2000 support
10311 11:46:35.444340 <5>[ 1.909035] Key type dns_resolver registered
10312 11:46:35.447894 <6>[ 1.913995] registered taskstats version 1
10313 11:46:35.454392 <5>[ 1.918376] Loading compiled-in X.509 certificates
10314 11:46:35.483497 <4>[ 1.941612] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10315 11:46:35.493299 <4>[ 1.952350] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10316 11:46:35.500129 <3>[ 1.962882] debugfs: File 'uA_load' in directory '/' already present!
10317 11:46:35.506504 <3>[ 1.969582] debugfs: File 'min_uV' in directory '/' already present!
10318 11:46:35.513295 <3>[ 1.976189] debugfs: File 'max_uV' in directory '/' already present!
10319 11:46:35.519886 <3>[ 1.982797] debugfs: File 'constraint_flags' in directory '/' already present!
10320 11:46:35.531318 <3>[ 1.992558] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10321 11:46:35.540333 <6>[ 2.004986] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10322 11:46:35.547032 <6>[ 2.011780] xhci-mtk 11200000.usb: xHCI Host Controller
10323 11:46:35.553414 <6>[ 2.017282] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10324 11:46:35.563551 <6>[ 2.025123] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10325 11:46:35.570247 <6>[ 2.034560] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10326 11:46:35.576865 <6>[ 2.040632] xhci-mtk 11200000.usb: xHCI Host Controller
10327 11:46:35.583751 <6>[ 2.046111] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10328 11:46:35.590255 <6>[ 2.053757] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10329 11:46:35.596962 <6>[ 2.061506] hub 1-0:1.0: USB hub found
10330 11:46:35.600276 <6>[ 2.065525] hub 1-0:1.0: 1 port detected
10331 11:46:35.606931 <6>[ 2.069801] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10332 11:46:35.614135 <6>[ 2.078526] hub 2-0:1.0: USB hub found
10333 11:46:35.616990 <6>[ 2.082546] hub 2-0:1.0: 1 port detected
10334 11:46:35.625576 <6>[ 2.090420] mtk-msdc 11f70000.mmc: Got CD GPIO
10335 11:46:35.635815 <6>[ 2.096096] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10336 11:46:35.642373 <6>[ 2.104243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10337 11:46:35.652277 <4>[ 2.112250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10338 11:46:35.658880 <6>[ 2.121770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10339 11:46:35.668677 <6>[ 2.129867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10340 11:46:35.675649 <6>[ 2.137952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10341 11:46:35.685419 <6>[ 2.145880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10342 11:46:35.692185 <6>[ 2.153697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10343 11:46:35.701985 <6>[ 2.161514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10344 11:46:35.711988 <6>[ 2.171947] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10345 11:46:35.718567 <6>[ 2.180325] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10346 11:46:35.728618 <6>[ 2.188664] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10347 11:46:35.735096 <6>[ 2.197002] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10348 11:46:35.745341 <6>[ 2.205340] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10349 11:46:35.752057 <6>[ 2.213680] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10350 11:46:35.761680 <6>[ 2.222018] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10351 11:46:35.768279 <6>[ 2.230356] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10352 11:46:35.777936 <6>[ 2.238695] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10353 11:46:35.784733 <6>[ 2.247043] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10354 11:46:35.794707 <6>[ 2.255387] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10355 11:46:35.801217 <6>[ 2.263725] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10356 11:46:35.811006 <6>[ 2.272063] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10357 11:46:35.818263 <6>[ 2.280403] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10358 11:46:35.827944 <6>[ 2.288740] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10359 11:46:35.834461 <6>[ 2.297590] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10360 11:46:35.841148 <6>[ 2.304787] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10361 11:46:35.847920 <6>[ 2.311543] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10362 11:46:35.854485 <6>[ 2.318281] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10363 11:46:35.860919 <6>[ 2.325188] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10364 11:46:35.870742 <6>[ 2.332022] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10365 11:46:35.880573 <6>[ 2.341148] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10366 11:46:35.890974 <6>[ 2.350266] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10367 11:46:35.900346 <6>[ 2.359563] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10368 11:46:35.906995 <6>[ 2.369036] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10369 11:46:35.916750 <6>[ 2.378503] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10370 11:46:35.926814 <6>[ 2.387623] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10371 11:46:35.937130 <6>[ 2.397088] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10372 11:46:35.946887 <6>[ 2.406206] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10373 11:46:35.956826 <6>[ 2.415499] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10374 11:46:35.966678 <6>[ 2.425659] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10375 11:46:35.976996 <6>[ 2.437207] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10376 11:46:35.983091 <6>[ 2.446321] Trying to probe devices needed for running init ...
10377 11:46:36.029231 <6>[ 2.490771] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10378 11:46:36.184021 <6>[ 2.648759] hub 1-1:1.0: USB hub found
10379 11:46:36.187313 <6>[ 2.653255] hub 1-1:1.0: 4 ports detected
10380 11:46:36.197218 <6>[ 2.661827] hub 1-1:1.0: USB hub found
10381 11:46:36.200442 <6>[ 2.666209] hub 1-1:1.0: 4 ports detected
10382 11:46:36.309301 <6>[ 2.771042] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10383 11:46:36.334374 <6>[ 2.799214] hub 2-1:1.0: USB hub found
10384 11:46:36.337464 <6>[ 2.803638] hub 2-1:1.0: 3 ports detected
10385 11:46:36.345812 <6>[ 2.810766] hub 2-1:1.0: USB hub found
10386 11:46:36.349239 <6>[ 2.815137] hub 2-1:1.0: 3 ports detected
10387 11:46:36.525501 <6>[ 2.986852] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10388 11:46:36.657489 <6>[ 3.121905] hub 1-1.4:1.0: USB hub found
10389 11:46:36.660065 <6>[ 3.126428] hub 1-1.4:1.0: 2 ports detected
10390 11:46:36.668415 <6>[ 3.133177] hub 1-1.4:1.0: USB hub found
10391 11:46:36.671590 <6>[ 3.137762] hub 1-1.4:1.0: 2 ports detected
10392 11:46:36.737200 <6>[ 3.198836] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10393 11:46:36.969242 <6>[ 3.430813] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10394 11:46:37.161022 <6>[ 3.622797] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10395 11:46:48.266327 <6>[ 14.735774] ALSA device list:
10396 11:46:48.272631 <6>[ 14.739065] No soundcards found.
10397 11:46:48.280861 <6>[ 14.746869] Freeing unused kernel memory: 8384K
10398 11:46:48.283811 <6>[ 14.751846] Run /init as init process
10399 11:46:48.295055 Loading, please wait...
10400 11:46:48.315371 Starting version 247.3-7+deb11u2
10401 11:46:48.537548 <6>[ 15.000683] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10402 11:46:48.549852 <6>[ 15.016274] mc: Linux media interface: v0.10
10403 11:46:48.553354 <6>[ 15.016364] remoteproc remoteproc0: scp is available
10404 11:46:48.563577 <6>[ 15.022893] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10405 11:46:48.566864 <6>[ 15.026147] remoteproc remoteproc0: powering up scp
10406 11:46:48.576904 <6>[ 15.033692] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10407 11:46:48.583065 <6>[ 15.038799] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10408 11:46:48.589874 <6>[ 15.038816] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10409 11:46:48.599469 <6>[ 15.047495] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10410 11:46:48.606314 <4>[ 15.049802] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10411 11:46:48.615998 <3>[ 15.057093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10412 11:46:48.622811 <4>[ 15.064278] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10413 11:46:48.629845 <3>[ 15.070475] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10414 11:46:48.639271 <3>[ 15.070484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10415 11:46:48.645931 <6>[ 15.072041] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10416 11:46:48.652785 <3>[ 15.077931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10417 11:46:48.663450 <4>[ 15.101457] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10418 11:46:48.666735 <4>[ 15.101457] Fallback method does not support PEC.
10419 11:46:48.676726 <3>[ 15.109788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 11:46:48.680356 <6>[ 15.113360] usbcore: registered new interface driver r8152
10421 11:46:48.687299 <6>[ 15.118588] videodev: Linux video capture interface: v2.00
10422 11:46:48.694298 <3>[ 15.125386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 11:46:48.704129 <3>[ 15.134105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10424 11:46:48.713753 <3>[ 15.156216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10425 11:46:48.720720 <3>[ 15.158569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 11:46:48.730371 <3>[ 15.158574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 11:46:48.736773 <6>[ 15.167875] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10428 11:46:48.743274 <3>[ 15.175457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 11:46:48.753666 <6>[ 15.175708] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10430 11:46:48.763514 <6>[ 15.176044] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10431 11:46:48.770128 <6>[ 15.184196] pci_bus 0000:00: root bus resource [bus 00-ff]
10432 11:46:48.776591 <6>[ 15.189263] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10433 11:46:48.783188 <6>[ 15.189424] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10434 11:46:48.790081 <6>[ 15.189433] remoteproc remoteproc0: remote processor scp is now up
10435 11:46:48.799859 <6>[ 15.190772] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10436 11:46:48.809836 <3>[ 15.192781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 11:46:48.816190 <6>[ 15.200376] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10438 11:46:48.823161 <3>[ 15.207227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10439 11:46:48.833029 <3>[ 15.207232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10440 11:46:48.839383 <3>[ 15.207300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10441 11:46:48.849319 <6>[ 15.215534] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10442 11:46:48.859562 <6>[ 15.219895] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10443 11:46:48.865975 <6>[ 15.225181] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10444 11:46:48.875961 <3>[ 15.225397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10445 11:46:48.882683 <6>[ 15.234458] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10446 11:46:48.889457 <6>[ 15.235099] usbcore: registered new interface driver cdc_ether
10447 11:46:48.892465 <6>[ 15.235243] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10448 11:46:48.902131 <6>[ 15.235276] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10449 11:46:48.905654 <6>[ 15.235426] pci 0000:00:00.0: supports D1 D2
10450 11:46:48.912160 <6>[ 15.235433] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10451 11:46:48.915202 <6>[ 15.237585] Bluetooth: Core ver 2.22
10452 11:46:48.922215 <6>[ 15.237631] NET: Registered PF_BLUETOOTH protocol family
10453 11:46:48.928549 <6>[ 15.237633] Bluetooth: HCI device and connection manager initialized
10454 11:46:48.935360 <6>[ 15.237646] Bluetooth: HCI socket layer initialized
10455 11:46:48.938690 <6>[ 15.237649] Bluetooth: L2CAP socket layer initialized
10456 11:46:48.945204 <6>[ 15.237655] Bluetooth: SCO socket layer initialized
10457 11:46:48.951676 <6>[ 15.237957] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10458 11:46:48.958500 <6>[ 15.238188] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10459 11:46:48.965145 <6>[ 15.238230] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10460 11:46:48.975421 <6>[ 15.238252] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10461 11:46:48.981664 <6>[ 15.238276] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10462 11:46:48.984866 <6>[ 15.238405] pci 0000:01:00.0: supports D1 D2
10463 11:46:48.991591 <6>[ 15.238410] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10464 11:46:49.001369 <3>[ 15.240175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10465 11:46:49.008292 <6>[ 15.248011] usbcore: registered new interface driver r8153_ecm
10466 11:46:49.014782 <6>[ 15.254634] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10467 11:46:49.021093 <6>[ 15.254658] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10468 11:46:49.031104 <6>[ 15.254660] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10469 11:46:49.037787 <6>[ 15.254668] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10470 11:46:49.044104 <6>[ 15.254680] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10471 11:46:49.054222 <6>[ 15.254693] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10472 11:46:49.057340 <6>[ 15.254705] pci 0000:00:00.0: PCI bridge to [bus 01]
10473 11:46:49.067445 <6>[ 15.254709] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10474 11:46:49.073963 <6>[ 15.254827] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10475 11:46:49.080607 <6>[ 15.255266] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10476 11:46:49.083897 <6>[ 15.255615] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10477 11:46:49.093951 <3>[ 15.255727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10478 11:46:49.100648 <3>[ 15.255736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10479 11:46:49.110382 <3>[ 15.255779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10480 11:46:49.117235 <6>[ 15.257184] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10481 11:46:49.130163 <6>[ 15.258414] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10482 11:46:49.133470 <6>[ 15.258568] usbcore: registered new interface driver uvcvideo
10483 11:46:49.143175 <5>[ 15.274077] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10484 11:46:49.153222 <4>[ 15.274806] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10485 11:46:49.159923 <4>[ 15.274813] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10486 11:46:49.166540 <6>[ 15.295390] usbcore: registered new interface driver btusb
10487 11:46:49.176116 <4>[ 15.295812] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10488 11:46:49.182609 <3>[ 15.295817] Bluetooth: hci0: Failed to load firmware file (-2)
10489 11:46:49.189562 <3>[ 15.295819] Bluetooth: hci0: Failed to set up firmware (-2)
10490 11:46:49.199440 <4>[ 15.295821] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10491 11:46:49.206026 <6>[ 15.303771] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10492 11:46:49.212589 <5>[ 15.315661] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10493 11:46:49.215709 <6>[ 15.362822] r8152 2-1.3:1.0 eth0: v1.12.13
10494 11:46:49.225768 <4>[ 15.365281] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10495 11:46:49.232629 <6>[ 15.379619] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10496 11:46:49.235512 <6>[ 15.383993] cfg80211: failed to load regulatory.db
10497 11:46:49.303205 <6>[ 15.766256] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10498 11:46:49.309787 <6>[ 15.773755] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10499 11:46:49.334329 <6>[ 15.800377] mt7921e 0000:01:00.0: ASIC revision: 79610010
10500 11:46:49.437776 <4>[ 15.897492] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10501 11:46:49.458094 Begin: Loading essential drivers ... done.
10502 11:46:49.461322 Begin: Running /scripts/init-premount ... done.
10503 11:46:49.468547 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10504 11:46:49.478165 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10505 11:46:49.481509 Device /sys/class/net/enx00e04c6803bd found
10506 11:46:49.482075 done.
10507 11:46:49.552759 <4>[ 16.012511] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10508 11:46:49.564365 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10509 11:46:49.671904 <4>[ 16.131754] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10510 11:46:49.787854 <4>[ 16.247440] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10511 11:46:49.903495 <4>[ 16.363366] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10512 11:46:50.019638 <4>[ 16.479277] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10513 11:46:50.135646 <4>[ 16.595308] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10514 11:46:50.250927 <4>[ 16.711235] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10515 11:46:50.367445 <4>[ 16.827199] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10516 11:46:50.483370 <4>[ 16.943116] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10517 11:46:50.528162 <6>[ 16.994785] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10518 11:46:50.590786 <3>[ 17.057146] mt7921e 0000:01:00.0: hardware init failed
10519 11:46:50.687483 IP-Config: no response after 2 secs - giving up
10520 11:46:50.723493 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10521 11:46:50.726866 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10522 11:46:50.733406 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10523 11:46:50.743326 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10524 11:46:50.749903 host : mt8192-asurada-spherion-r0-cbg-4
10525 11:46:50.756620 domain : lava-rack
10526 11:46:50.759733 rootserver: 192.168.201.1 rootpath:
10527 11:46:50.760210 filename :
10528 11:46:50.835659 done.
10529 11:46:50.844095 Begin: Running /scripts/nfs-bottom ... done.
10530 11:46:50.862808 Begin: Running /scripts/init-bottom ... done.
10531 11:46:52.055620 <6>[ 18.522229] NET: Registered PF_INET6 protocol family
10532 11:46:52.062622 <6>[ 18.529436] Segment Routing with IPv6
10533 11:46:52.065816 <6>[ 18.533412] In-situ OAM (IOAM) with IPv6
10534 11:46:52.175463 <30>[ 18.622349] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10535 11:46:52.178731 <30>[ 18.646737] systemd[1]: Detected architecture arm64.
10536 11:46:52.199685
10537 11:46:52.203208 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10538 11:46:52.203685
10539 11:46:52.218273 <30>[ 18.685211] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10540 11:46:53.085731 <30>[ 19.549255] systemd[1]: Queued start job for default target Graphical Interface.
10541 11:46:53.118412 <30>[ 19.585246] systemd[1]: Created slice system-getty.slice.
10542 11:46:53.124814 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10543 11:46:53.141311 <30>[ 19.608258] systemd[1]: Created slice system-modprobe.slice.
10544 11:46:53.148000 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10545 11:46:53.166039 <30>[ 19.632871] systemd[1]: Created slice system-serial\x2dgetty.slice.
10546 11:46:53.176321 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10547 11:46:53.189336 <30>[ 19.655914] systemd[1]: Created slice User and Session Slice.
10548 11:46:53.195611 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10549 11:46:53.216134 <30>[ 19.679640] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10550 11:46:53.225936 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10551 11:46:53.243213 <30>[ 19.707009] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10552 11:46:53.249934 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10553 11:46:53.270780 <30>[ 19.730949] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10554 11:46:53.277085 <30>[ 19.743104] systemd[1]: Reached target Local Encrypted Volumes.
10555 11:46:53.284026 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10556 11:46:53.300437 <30>[ 19.766937] systemd[1]: Reached target Paths.
10557 11:46:53.303609 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10558 11:46:53.319737 <30>[ 19.786780] systemd[1]: Reached target Remote File Systems.
10559 11:46:53.326669 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10560 11:46:53.344182 <30>[ 19.811063] systemd[1]: Reached target Slices.
10561 11:46:53.350861 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10562 11:46:53.363916 <30>[ 19.830803] systemd[1]: Reached target Swap.
10563 11:46:53.366977 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10564 11:46:53.387462 <30>[ 19.851278] systemd[1]: Listening on initctl Compatibility Named Pipe.
10565 11:46:53.394536 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10566 11:46:53.400740 <30>[ 19.867443] systemd[1]: Listening on Journal Audit Socket.
10567 11:46:53.407737 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10568 11:46:53.425305 <30>[ 19.892069] systemd[1]: Listening on Journal Socket (/dev/log).
10569 11:46:53.431748 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10570 11:46:53.448536 <30>[ 19.915341] systemd[1]: Listening on Journal Socket.
10571 11:46:53.455099 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10572 11:46:53.472122 <30>[ 19.935723] systemd[1]: Listening on Network Service Netlink Socket.
10573 11:46:53.478521 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10574 11:46:53.495337 <30>[ 19.961963] systemd[1]: Listening on udev Control Socket.
10575 11:46:53.501395 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10576 11:46:53.516329 <30>[ 19.983229] systemd[1]: Listening on udev Kernel Socket.
10577 11:46:53.522985 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10578 11:46:53.563845 <30>[ 20.030846] systemd[1]: Mounting Huge Pages File System...
10579 11:46:53.570379 Mounting [0;1;39mHuge Pages File System[0m...
10580 11:46:53.588014 <30>[ 20.055015] systemd[1]: Mounting POSIX Message Queue File System...
10581 11:46:53.594922 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10582 11:46:53.616089 <30>[ 20.083073] systemd[1]: Mounting Kernel Debug File System...
10583 11:46:53.622449 Mounting [0;1;39mKernel Debug File System[0m...
10584 11:46:53.639236 <30>[ 20.103217] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10585 11:46:53.683733 <30>[ 20.147290] systemd[1]: Starting Create list of static device nodes for the current kernel...
10586 11:46:53.690268 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10587 11:46:53.712559 <30>[ 20.179443] systemd[1]: Starting Load Kernel Module configfs...
10588 11:46:53.719057 Starting [0;1;39mLoad Kernel Module configfs[0m...
10589 11:46:53.734881 <30>[ 20.201850] systemd[1]: Starting Load Kernel Module drm...
10590 11:46:53.741305 Starting [0;1;39mLoad Kernel Module drm[0m...
10591 11:46:53.760910 <30>[ 20.227701] systemd[1]: Starting Load Kernel Module fuse...
10592 11:46:53.767474 Starting [0;1;39mLoad Kernel Module fuse[0m...
10593 11:46:53.799966 <6>[ 20.266640] fuse: init (API version 7.37)
10594 11:46:53.809683 <30>[ 20.266675] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10595 11:46:53.848740 <30>[ 20.315495] systemd[1]: Starting Journal Service...
10596 11:46:53.855150 Starting [0;1;39mJournal Service[0m...
10597 11:46:53.879389 <30>[ 20.346551] systemd[1]: Starting Load Kernel Modules...
10598 11:46:53.886162 Starting [0;1;39mLoad Kernel Modules[0m...
10599 11:46:53.907297 <30>[ 20.370759] systemd[1]: Starting Remount Root and Kernel File Systems...
10600 11:46:53.913485 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10601 11:46:53.932549 <30>[ 20.400138] systemd[1]: Starting Coldplug All udev Devices...
10602 11:46:53.939322 Starting [0;1;39mColdplug All udev Devices[0m...
10603 11:46:53.960421 <30>[ 20.427675] systemd[1]: Mounted Huge Pages File System.
10604 11:46:53.966753 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10605 11:46:53.984209 <30>[ 20.451460] systemd[1]: Mounted POSIX Message Queue File System.
10606 11:46:53.990857 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10607 11:46:54.008082 <30>[ 20.475326] systemd[1]: Mounted Kernel Debug File System.
10608 11:46:54.015279 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10609 11:46:54.033353 <3>[ 20.497007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10610 11:46:54.044258 <30>[ 20.507853] systemd[1]: Finished Create list of static device nodes for the current kernel.
10611 11:46:54.066410 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 20.528348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10612 11:46:54.066922 for the current kernel[0m.
10613 11:46:54.089538 <30>[ 20.556339] systemd[1]: modprobe@configfs.service: Succeeded.
10614 11:46:54.097115 <30>[ 20.563697] systemd[1]: Finished Load Kernel Module configfs.
10615 11:46:54.103932 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10616 11:46:54.113888 <3>[ 20.576364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 11:46:54.120769 <30>[ 20.587614] systemd[1]: modprobe@drm.service: Succeeded.
10618 11:46:54.127360 <30>[ 20.593766] systemd[1]: Finished Load Kernel Module drm.
10619 11:46:54.134661 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10620 11:46:54.141650 <3>[ 20.605555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 11:46:54.149318 <30>[ 20.616343] systemd[1]: modprobe@fuse.service: Succeeded.
10622 11:46:54.155916 <30>[ 20.622837] systemd[1]: Finished Load Kernel Module fuse.
10623 11:46:54.162843 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10624 11:46:54.174212 <3>[ 20.637882] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10625 11:46:54.181448 <30>[ 20.648386] systemd[1]: Finished Load Kernel Modules.
10626 11:46:54.188116 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10627 11:46:54.204643 <3>[ 20.668186] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 11:46:54.211516 <30>[ 20.669878] systemd[1]: Finished Remount Root and Kernel File Systems.
10629 11:46:54.218036 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10630 11:46:54.236931 <3>[ 20.700407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 11:46:54.269566 <3>[ 20.733140] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 11:46:54.275871 <30>[ 20.734857] systemd[1]: Mounting FUSE Control File System...
10633 11:46:54.282565 Mounting [0;1;39mFUSE Control File System[0m...
10634 11:46:54.302087 <30>[ 20.765442] systemd[1]: Mounting Kernel Configuration File System...
10635 11:46:54.308249 <3>[ 20.765644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 11:46:54.315127 Mounting [0;1;39mKernel Configuration File System[0m...
10637 11:46:54.340340 <3>[ 20.804241] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10638 11:46:54.350537 <30>[ 20.804316] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10639 11:46:54.360382 <30>[ 20.822172] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10640 11:46:54.381337 <30>[ 20.847756] systemd[1]: Starting Load/Save Random Seed...
10641 11:46:54.387510 Starting [0;1;39mLoad/Save Random Seed[0m...
10642 11:46:54.405156 <30>[ 20.871966] systemd[1]: Starting Apply Kernel Variables...
10643 11:46:54.411692 Starting [0;1;39mApply Kernel Variables[0m...
10644 11:46:54.437772 <4>[ 20.895013] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10645 11:46:54.444680 <30>[ 20.895684] systemd[1]: Starting Create System Users...
10646 11:46:54.451224 <3>[ 20.910868] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10647 11:46:54.457526 Starting [0;1;39mCreate System Users[0m...
10648 11:46:54.474178 <30>[ 20.941357] systemd[1]: Started Journal Service.
10649 11:46:54.480830 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10650 11:46:54.504975 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10651 11:46:54.519569 See 'systemctl status systemd-udev-trigger.service' for details.
10652 11:46:54.536571 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10653 11:46:54.552045 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10654 11:46:54.568637 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10655 11:46:54.585635 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10656 11:46:54.601680 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10657 11:46:54.640686 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10658 11:46:54.662475 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10659 11:46:54.690804 <46>[ 21.155098] systemd-journald[300]: Received client request to flush runtime journal.
10660 11:46:54.720444 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10661 11:46:54.731592 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10662 11:46:54.747887 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10663 11:46:54.800048 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10664 11:46:56.101748 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10665 11:46:56.152485 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10666 11:46:56.172219 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10667 11:46:56.197934 Starting [0;1;39mNetwork Service[0m...
10668 11:46:56.549448 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10669 11:46:56.569768 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10670 11:46:56.616323 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10671 11:46:56.774332 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10672 11:46:56.812284 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10673 11:46:56.859956 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10674 11:46:56.917916 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10675 11:46:56.935573 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10676 11:46:56.968327 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10677 11:46:57.007667 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10678 11:46:57.064564 Starting [0;1;39mNetwork Name Resolution[0m...
10679 11:46:57.094301 Starting [0;1;39mNetwork Time Synchronization[0m...
10680 11:46:57.112632 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10681 11:46:57.169825 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10682 11:46:57.301997 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10683 11:46:57.324292 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10684 11:46:57.346912 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10685 11:46:57.371582 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10686 11:46:57.387530 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10687 11:46:57.481956 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10688 11:46:57.525537 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10689 11:46:57.553387 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10690 11:46:57.576957 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10691 11:46:57.591394 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10692 11:46:57.613120 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10693 11:46:57.627299 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10694 11:46:57.643588 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10695 11:46:57.700581 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10696 11:46:57.783249 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10697 11:46:57.905143 Starting [0;1;39mUser Login Management[0m...
10698 11:46:57.923278 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10699 11:46:57.943338 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10700 11:46:57.961368 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10701 11:46:58.014206 Starting [0;1;39mPermit User Sessions[0m...
10702 11:46:58.110865 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10703 11:46:58.135930 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10704 11:46:58.202090 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10705 11:46:58.247174 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10706 11:46:58.263608 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10707 11:46:58.282367 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10708 11:46:58.302016 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10709 11:46:58.317781 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10710 11:46:58.372078 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10711 11:46:58.425860 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10712 11:46:58.498439
10713 11:46:58.498753
10714 11:46:58.501714 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10715 11:46:58.502000
10716 11:46:58.505297 debian-bullseye-arm64 login: root (automatic login)
10717 11:46:58.505590
10718 11:46:58.505812
10719 11:46:58.824117 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
10720 11:46:58.824659
10721 11:46:58.830656 The programs included with the Debian GNU/Linux system are free software;
10722 11:46:58.837583 the exact distribution terms for each program are described in the
10723 11:46:58.840463 individual files in /usr/share/doc/*/copyright.
10724 11:46:58.840926
10725 11:46:58.847019 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10726 11:46:58.850206 permitted by applicable law.
10727 11:46:58.947151 Matched prompt #10: / #
10729 11:46:58.948250 Setting prompt string to ['/ #']
10730 11:46:58.948717 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10732 11:46:58.949705 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10733 11:46:58.950138 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10734 11:46:58.950484 Setting prompt string to ['/ #']
10735 11:46:58.950791 Forcing a shell prompt, looking for ['/ #']
10737 11:46:59.001660 / #
10738 11:46:59.002047 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10739 11:46:59.002372 Waiting using forced prompt support (timeout 00:02:30)
10740 11:46:59.007428
10741 11:46:59.008134 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10742 11:46:59.008482 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10744 11:46:59.109597 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a'
10745 11:46:59.116277 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074028/extract-nfsrootfs-v0izki_a'
10747 11:46:59.218175 / # export NFS_SERVER_IP='192.168.201.1'
10748 11:46:59.224647 export NFS_SERVER_IP='192.168.201.1'
10749 11:46:59.225606 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10750 11:46:59.226129 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
10751 11:46:59.226614 end: 2 depthcharge-action (duration 00:01:27) [common]
10752 11:46:59.227114 start: 3 lava-test-retry (timeout 00:01:00) [common]
10753 11:46:59.227599 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10754 11:46:59.228025 Using namespace: common
10756 11:46:59.329206 / # #
10757 11:46:59.329867 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10758 11:46:59.335591 #
10759 11:46:59.336477 Using /lava-12074028
10761 11:46:59.437753 / # export SHELL=/bin/sh
10762 11:46:59.444190 export SHELL=/bin/sh
10764 11:46:59.545975 / # . /lava-12074028/environment
10765 11:46:59.552270 . /lava-12074028/environment
10767 11:46:59.659946 / # /lava-12074028/bin/lava-test-runner /lava-12074028/0
10768 11:46:59.660631 Test shell timeout: 10s (minimum of the action and connection timeout)
10769 11:46:59.666238 /lava-12074028/bin/lava-test-runner /lava-12074028/0
10770 11:46:59.911445 + export TESTRUN_ID=0_dmesg
10771 11:46:59.914527 + cd /lava-12074028/0/tests/0_dmesg
10772 11:46:59.917813 + cat uuid
10773 11:46:59.932685 + UUID=12074028_<8>[ 26.397654] <LAVA_SIGNAL_STARTRUN 0_dmesg 12074028_1.6.2.3.1>
10774 11:46:59.932867 1.6.2.3.1
10775 11:46:59.932980 + set +x
10776 11:46:59.933280 Received signal: <STARTRUN> 0_dmesg 12074028_1.6.2.3.1
10777 11:46:59.933403 Starting test lava.0_dmesg (12074028_1.6.2.3.1)
10778 11:46:59.933515 Skipping test definition patterns.
10779 11:46:59.939173 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10780 11:47:00.029625 <8>[ 26.494496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10781 11:47:00.029982 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10783 11:47:00.098180 <8>[ 26.562986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10784 11:47:00.098547 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10786 11:47:00.168839 <8>[ 26.633588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10787 11:47:00.169196 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10789 11:47:00.172307 + set +x
10790 11:47:00.175313 <8>[ 26.643212] <LAVA_SIGNAL_ENDRUN 0_dmesg 12074028_1.6.2.3.1>
10791 11:47:00.175666 Received signal: <ENDRUN> 0_dmesg 12074028_1.6.2.3.1
10792 11:47:00.175814 Ending use of test pattern.
10793 11:47:00.175923 Ending test lava.0_dmesg (12074028_1.6.2.3.1), duration 0.24
10795 11:47:00.180974 <LAVA_TEST_RUNNER EXIT>
10796 11:47:00.181368 ok: lava_test_shell seems to have completed
10797 11:47:00.181541 alert: pass
crit: pass
emerg: pass
10798 11:47:00.181678 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10799 11:47:00.181810 end: 3 lava-test-retry (duration 00:00:01) [common]
10800 11:47:00.181932 start: 4 lava-test-retry (timeout 00:01:00) [common]
10801 11:47:00.182050 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10802 11:47:00.182146 Using namespace: common
10804 11:47:00.283041 / # #
10805 11:47:00.283706 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10806 11:47:00.284302 Using /lava-12074028
10808 11:47:00.385596 export SHELL=/bin/sh
10809 11:47:00.386389 #
10811 11:47:00.487923 / # export SHELL=/bin/sh. /lava-12074028/environment
10812 11:47:00.488241
10814 11:47:00.589214 / # . /lava-12074028/environment/lava-12074028/bin/lava-test-runner /lava-12074028/1
10815 11:47:00.589868 Test shell timeout: 10s (minimum of the action and connection timeout)
10816 11:47:00.590521
10817 11:47:00.595203 / # /lava-12074028/bin/lava-test-runner /lava-12074028/1
10818 11:47:00.716890 + export TESTRUN_ID=1_bootrr
10819 11:47:00.719923 + cd /lava-12074028/1/tests/1_bootrr
10820 11:47:00.723551 + cat uuid
10821 11:47:00.731254 + <8>[ 27.199255] <LAVA_SIGNAL_STARTRUN 1_bootrr 12074028_1.6.2.3.5>
10822 11:47:00.732063 Received signal: <STARTRUN> 1_bootrr 12074028_1.6.2.3.5
10823 11:47:00.732434 Starting test lava.1_bootrr (12074028_1.6.2.3.5)
10824 11:47:00.732900 Skipping test definition patterns.
10825 11:47:00.734773 UUID=12074028_1.6.2.3.5
10826 11:47:00.735028 + set +x
10827 11:47:00.747430 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12074028/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
10828 11:47:00.750699 + cd /opt/bootrr/libexec/bootrr
10829 11:47:00.750784 + sh helpers/bootrr-auto
10830 11:47:00.808669 /lava-12074028/1/../bin/lava-test-case
10831 11:47:00.838357 <8>[ 27.302812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10832 11:47:00.838715 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10834 11:47:00.885184 /lava-12074028/1/../bin/lava-test-case
10835 11:47:00.909555 <8>[ 27.374400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10836 11:47:00.909925 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10838 11:47:00.932965 /lava-12074028/1/../bin/lava-test-case
10839 11:47:00.956087 <8>[ 27.421114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
10840 11:47:00.956368 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
10842 11:47:01.009023 /lava-12074028/1/../bin/lava-test-case
10843 11:47:01.034603 <8>[ 27.499262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10844 11:47:01.035301 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10846 11:47:01.075862 /lava-12074028/1/../bin/lava-test-case
10847 11:47:01.099530 <8>[ 27.564551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10848 11:47:01.099900 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10850 11:47:01.131658 /lava-12074028/1/../bin/lava-test-case
10851 11:47:01.154433 <8>[ 27.619393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10852 11:47:01.154797 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10854 11:47:01.185084 /lava-12074028/1/../bin/lava-test-case
10855 11:47:01.210241 <8>[ 27.675103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10856 11:47:01.210603 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10858 11:47:01.242912 /lava-12074028/1/../bin/lava-test-case
10859 11:47:01.267783 <8>[ 27.732610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10860 11:47:01.268157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10862 11:47:01.288634 /lava-12074028/1/../bin/lava-test-case
10863 11:47:01.312155 <8>[ 27.777009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10864 11:47:01.312892 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10866 11:47:01.349497 /lava-12074028/1/../bin/lava-test-case
10867 11:47:01.379929 <8>[ 27.844499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10868 11:47:01.380757 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10870 11:47:01.409790 /lava-12074028/1/../bin/lava-test-case
10871 11:47:01.439922 <8>[ 27.904447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10872 11:47:01.440734 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10874 11:47:01.481733 /lava-12074028/1/../bin/lava-test-case
10875 11:47:01.515294 <8>[ 27.980016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10876 11:47:01.516183 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10878 11:47:01.555054 /lava-12074028/1/../bin/lava-test-case
10879 11:47:01.585547 <8>[ 28.050147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10880 11:47:01.586335 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10882 11:47:01.625943 /lava-12074028/1/../bin/lava-test-case
10883 11:47:01.658778 <8>[ 28.123296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10884 11:47:01.659634 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10886 11:47:01.698447 /lava-12074028/1/../bin/lava-test-case
10887 11:47:01.731144 <8>[ 28.195614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10888 11:47:01.732130 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10890 11:47:01.758646 /lava-12074028/1/../bin/lava-test-case
10891 11:47:01.786075 <8>[ 28.251024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10892 11:47:01.786587 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10894 11:47:01.823041 /lava-12074028/1/../bin/lava-test-case
10895 11:47:01.854195 <8>[ 28.318733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10896 11:47:01.855054 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10898 11:47:01.878005 /lava-12074028/1/../bin/lava-test-case
10899 11:47:01.911949 <8>[ 28.376407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10900 11:47:01.912961 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10902 11:47:01.948664 /lava-12074028/1/../bin/lava-test-case
10903 11:47:01.977426 <8>[ 28.442361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10904 11:47:01.978321 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10906 11:47:02.002422 /lava-12074028/1/../bin/lava-test-case
10907 11:47:02.029844 <8>[ 28.494574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10908 11:47:02.030551 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10910 11:47:02.068796 /lava-12074028/1/../bin/lava-test-case
10911 11:47:02.097112 <8>[ 28.561675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10912 11:47:02.098017 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10914 11:47:02.131670 /lava-12074028/1/../bin/lava-test-case
10915 11:47:02.159676 <8>[ 28.624263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10916 11:47:02.160627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10918 11:47:02.194760 /lava-12074028/1/../bin/lava-test-case
10919 11:47:02.219109 <8>[ 28.683895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10920 11:47:02.219959 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10922 11:47:02.241091 /lava-12074028/1/../bin/lava-test-case
10923 11:47:02.265661 <8>[ 28.730882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10924 11:47:02.266026 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10926 11:47:02.297304 /lava-12074028/1/../bin/lava-test-case
10927 11:47:02.320594 <8>[ 28.785653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10928 11:47:02.320950 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10930 11:47:02.354581 /lava-12074028/1/../bin/lava-test-case
10931 11:47:02.385421 <8>[ 28.850192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10932 11:47:02.386297 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10934 11:47:02.420802 /lava-12074028/1/../bin/lava-test-case
10935 11:47:02.451609 <8>[ 28.916415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10936 11:47:02.452480 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10938 11:47:02.492625 /lava-12074028/1/../bin/lava-test-case
10939 11:47:02.527581 <8>[ 28.992230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10940 11:47:02.528456 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10942 11:47:02.553011 /lava-12074028/1/../bin/lava-test-case
10943 11:47:02.584238 <8>[ 29.049072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10944 11:47:02.585035 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10946 11:47:02.626625 /lava-12074028/1/../bin/lava-test-case
10947 11:47:02.658316 <8>[ 29.123313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10948 11:47:02.659148 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10950 11:47:02.695387 /lava-12074028/1/../bin/lava-test-case
10951 11:47:02.729395 <8>[ 29.194340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10952 11:47:02.730256 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10954 11:47:02.776861 /lava-12074028/1/../bin/lava-test-case
10955 11:47:02.806893 <8>[ 29.271912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10956 11:47:02.807768 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10958 11:47:02.845698 /lava-12074028/1/../bin/lava-test-case
10959 11:47:02.877491 <8>[ 29.342459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10960 11:47:02.878197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10962 11:47:02.904608 /lava-12074028/1/../bin/lava-test-case
10963 11:47:02.936808 <8>[ 29.401597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10964 11:47:02.937693 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10966 11:47:02.976032 /lava-12074028/1/../bin/lava-test-case
10967 11:47:03.008918 <8>[ 29.473746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10968 11:47:03.009698 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10970 11:47:03.048259 /lava-12074028/1/../bin/lava-test-case
10971 11:47:03.079081 <8>[ 29.543704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10972 11:47:03.080062 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10974 11:47:03.111334 /lava-12074028/1/../bin/lava-test-case
10975 11:47:03.140892 <8>[ 29.605673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10976 11:47:03.141747 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10978 11:47:03.183183 /lava-12074028/1/../bin/lava-test-case
10979 11:47:03.215898 <8>[ 29.680608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10980 11:47:03.216752 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10982 11:47:03.241410 /lava-12074028/1/../bin/lava-test-case
10983 11:47:03.272679 <8>[ 29.737543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10984 11:47:03.273530 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10986 11:47:03.308637 /lava-12074028/1/../bin/lava-test-case
10987 11:47:03.338175 <8>[ 29.802562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10988 11:47:03.339006 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10990 11:47:03.362151 /lava-12074028/1/../bin/lava-test-case
10991 11:47:03.393241 <8>[ 29.857902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10992 11:47:03.393995 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10994 11:47:03.429525 /lava-12074028/1/../bin/lava-test-case
10995 11:47:03.460028 <8>[ 29.924932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10996 11:47:03.460912 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10998 11:47:03.492728 /lava-12074028/1/../bin/lava-test-case
10999 11:47:03.525483 <8>[ 29.990337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11000 11:47:03.526335 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11002 11:47:03.566739 /lava-12074028/1/../bin/lava-test-case
11003 11:47:03.600917 <8>[ 30.065671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11004 11:47:03.601801 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11006 11:47:03.625157 /lava-12074028/1/../bin/lava-test-case
11007 11:47:03.657551 <8>[ 30.122479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11008 11:47:03.658448 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11010 11:47:03.696719 /lava-12074028/1/../bin/lava-test-case
11011 11:47:03.729248 <8>[ 30.194019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11012 11:47:03.730102 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11014 11:47:03.753035 /lava-12074028/1/../bin/lava-test-case
11015 11:47:03.782081 <8>[ 30.247004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11016 11:47:03.782967 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11018 11:47:03.816236 /lava-12074028/1/../bin/lava-test-case
11019 11:47:03.844206 <8>[ 30.308997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11020 11:47:03.845372 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11022 11:47:03.874211 /lava-12074028/1/../bin/lava-test-case
11023 11:47:03.909422 <8>[ 30.374359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11024 11:47:03.910295 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11026 11:47:03.950674 /lava-12074028/1/../bin/lava-test-case
11027 11:47:03.985454 <8>[ 30.450308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11028 11:47:03.986296 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11030 11:47:04.023425 /lava-12074028/1/../bin/lava-test-case
11031 11:47:04.056322 <8>[ 30.521074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11032 11:47:04.057288 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11034 11:47:04.081490 /lava-12074028/1/../bin/lava-test-case
11035 11:47:04.114060 <8>[ 30.579153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11036 11:47:04.114855 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11038 11:47:04.152327 /lava-12074028/1/../bin/lava-test-case
11039 11:47:04.182874 <8>[ 30.647994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11040 11:47:04.183793 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11042 11:47:04.212922 /lava-12074028/1/../bin/lava-test-case
11043 11:47:04.246373 <8>[ 30.711455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11044 11:47:04.247265 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11046 11:47:04.284634 /lava-12074028/1/../bin/lava-test-case
11047 11:47:04.318104 <8>[ 30.782927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11048 11:47:04.319021 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11050 11:47:04.357544 /lava-12074028/1/../bin/lava-test-case
11051 11:47:04.390699 <8>[ 30.855702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11052 11:47:04.391404 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11054 11:47:04.431298 /lava-12074028/1/../bin/lava-test-case
11055 11:47:04.462002 <8>[ 30.927007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11056 11:47:04.462854 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11058 11:47:04.500378 /lava-12074028/1/../bin/lava-test-case
11059 11:47:04.532044 <8>[ 30.997126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11060 11:47:04.533038 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11062 11:47:04.576357 /lava-12074028/1/../bin/lava-test-case
11063 11:47:04.610346 <8>[ 31.075361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11064 11:47:04.611302 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11066 11:47:04.636088 /lava-12074028/1/../bin/lava-test-case
11067 11:47:04.670043 <8>[ 31.134856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11068 11:47:04.670948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11070 11:47:04.710089 /lava-12074028/1/../bin/lava-test-case
11071 11:47:04.745025 <8>[ 31.209944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11072 11:47:04.745861 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11074 11:47:04.785729 /lava-12074028/1/../bin/lava-test-case
11075 11:47:04.820878 <8>[ 31.285782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11076 11:47:04.821891 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11078 11:47:04.845597 /lava-12074028/1/../bin/lava-test-case
11079 11:47:04.873890 <8>[ 31.338990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11080 11:47:04.874812 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11082 11:47:04.920033 /lava-12074028/1/../bin/lava-test-case
11083 11:47:04.949958 <8>[ 31.414858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11084 11:47:04.950833 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11086 11:47:04.975779 /lava-12074028/1/../bin/lava-test-case
11087 11:47:05.009663 <8>[ 31.474666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11088 11:47:05.010502 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11090 11:47:05.051995 /lava-12074028/1/../bin/lava-test-case
11091 11:47:05.085450 <8>[ 31.550613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11092 11:47:05.086397 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11094 11:47:05.111160 /lava-12074028/1/../bin/lava-test-case
11095 11:47:05.144554 <8>[ 31.609663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11096 11:47:05.145401 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11098 11:47:05.184267 /lava-12074028/1/../bin/lava-test-case
11099 11:47:05.216470 <8>[ 31.681705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11100 11:47:05.217629 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11102 11:47:05.262659 /lava-12074028/1/../bin/lava-test-case
11103 11:47:05.296692 <8>[ 31.761531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11104 11:47:05.297555 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11106 11:47:05.333055 /lava-12074028/1/../bin/lava-test-case
11107 11:47:05.359186 <8>[ 31.824204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11108 11:47:05.360101 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11110 11:47:05.398382 /lava-12074028/1/../bin/lava-test-case
11111 11:47:05.431618 <8>[ 31.896537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11112 11:47:05.432497 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11114 11:47:05.473708 /lava-12074028/1/../bin/lava-test-case
11115 11:47:05.504261 <8>[ 31.969328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11116 11:47:05.505219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11118 11:47:05.543932 /lava-12074028/1/../bin/lava-test-case
11119 11:47:05.579177 <8>[ 32.044157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11120 11:47:05.580103 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11122 11:47:05.627139 /lava-12074028/1/../bin/lava-test-case
11123 11:47:05.660809 <8>[ 32.125982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11124 11:47:05.661702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11126 11:47:05.702322 /lava-12074028/1/../bin/lava-test-case
11127 11:47:05.737787 <8>[ 32.202884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11128 11:47:05.738557 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11130 11:47:05.776490 /lava-12074028/1/../bin/lava-test-case
11131 11:47:05.805133 <8>[ 32.270196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11132 11:47:05.806051 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11134 11:47:05.847303 /lava-12074028/1/../bin/lava-test-case
11135 11:47:05.881329 <8>[ 32.346357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11136 11:47:05.882226 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11138 11:47:05.926227 /lava-12074028/1/../bin/lava-test-case
11139 11:47:05.959635 <8>[ 32.424775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11140 11:47:05.960385 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11142 11:47:06.005359 /lava-12074028/1/../bin/lava-test-case
11143 11:47:06.040126 <8>[ 32.505354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11144 11:47:06.041033 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11146 11:47:06.078338 /lava-12074028/1/../bin/lava-test-case
11147 11:47:06.108589 <8>[ 32.573944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11148 11:47:06.109370 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11150 11:47:06.150859 /lava-12074028/1/../bin/lava-test-case
11151 11:47:06.184349 <8>[ 32.649449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11152 11:47:06.185362 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11154 11:47:06.225215 /lava-12074028/1/../bin/lava-test-case
11155 11:47:06.257369 <8>[ 32.722685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11156 11:47:06.258212 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11158 11:47:06.283880 /lava-12074028/1/../bin/lava-test-case
11159 11:47:06.314985 <8>[ 32.780360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11160 11:47:06.315856 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11162 11:47:06.362571 /lava-12074028/1/../bin/lava-test-case
11163 11:47:06.390344 <8>[ 32.855488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11164 11:47:06.391133 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11166 11:47:06.413961 /lava-12074028/1/../bin/lava-test-case
11167 11:47:06.445546 <8>[ 32.910699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11168 11:47:06.446425 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11170 11:47:06.484643 /lava-12074028/1/../bin/lava-test-case
11171 11:47:06.515332 <8>[ 32.980455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11172 11:47:06.516197 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11174 11:47:06.537862 /lava-12074028/1/../bin/lava-test-case
11175 11:47:06.568323 <8>[ 33.033526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11176 11:47:06.569179 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11178 11:47:06.605310 /lava-12074028/1/../bin/lava-test-case
11179 11:47:06.636817 <8>[ 33.102005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11180 11:47:06.637647 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11182 11:47:06.661512 /lava-12074028/1/../bin/lava-test-case
11183 11:47:06.695083 <8>[ 33.160397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11184 11:47:06.695915 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11186 11:47:06.738521 /lava-12074028/1/../bin/lava-test-case
11187 11:47:06.773561 <8>[ 33.238854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11188 11:47:06.774552 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11190 11:47:06.797029 /lava-12074028/1/../bin/lava-test-case
11191 11:47:06.828023 <8>[ 33.293102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11192 11:47:06.829045 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11194 11:47:06.866544 /lava-12074028/1/../bin/lava-test-case
11195 11:47:06.899863 <8>[ 33.365220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11196 11:47:06.900636 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11198 11:47:06.923810 /lava-12074028/1/../bin/lava-test-case
11199 11:47:06.955332 <8>[ 33.420587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11200 11:47:06.956224 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11202 11:47:06.998119 /lava-12074028/1/../bin/lava-test-case
11203 11:47:07.028341 <8>[ 33.493737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11204 11:47:07.029258 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11206 11:47:07.071341 /lava-12074028/1/../bin/lava-test-case
11207 11:47:07.104171 <8>[ 33.569491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11208 11:47:07.105021 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11210 11:47:07.129038 /lava-12074028/1/../bin/lava-test-case
11211 11:47:07.162832 <8>[ 33.627931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11212 11:47:07.163691 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11214 11:47:07.203090 /lava-12074028/1/../bin/lava-test-case
11215 11:47:07.232845 <8>[ 33.698290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11216 11:47:07.233727 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11218 11:47:07.255767 /lava-12074028/1/../bin/lava-test-case
11219 11:47:07.286955 <8>[ 33.752301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11220 11:47:07.287884 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11222 11:47:07.323176 /lava-12074028/1/../bin/lava-test-case
11223 11:47:07.350398 <8>[ 33.815603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11224 11:47:07.351300 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11226 11:47:07.372504 /lava-12074028/1/../bin/lava-test-case
11227 11:47:07.401408 <8>[ 33.866643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11228 11:47:07.402306 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11230 11:47:08.470820 /lava-12074028/1/../bin/lava-test-case
11231 11:47:08.499512 <8>[ 34.965339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11232 11:47:08.499905 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11234 11:47:08.519799 /lava-12074028/1/../bin/lava-test-case
11235 11:47:08.549145 <8>[ 35.014365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11236 11:47:08.549941 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11238 11:47:09.605370 /lava-12074028/1/../bin/lava-test-case
11239 11:47:09.635527 <8>[ 36.101019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11240 11:47:09.636438 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11242 11:47:09.658176 /lava-12074028/1/../bin/lava-test-case
11243 11:47:09.688285 <8>[ 36.153872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11244 11:47:09.689224 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11246 11:47:10.745670 /lava-12074028/1/../bin/lava-test-case
11247 11:47:10.775649 <8>[ 37.241462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11248 11:47:10.776555 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11250 11:47:10.798435 /lava-12074028/1/../bin/lava-test-case
11251 11:47:10.826232 <8>[ 37.292104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11252 11:47:10.826989 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11254 11:47:11.881267 /lava-12074028/1/../bin/lava-test-case
11255 11:47:11.914586 <8>[ 38.380455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11256 11:47:11.915385 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11258 11:47:11.937195 /lava-12074028/1/../bin/lava-test-case
11259 11:47:11.966385 <8>[ 38.432374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11260 11:47:11.967238 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11262 11:47:13.019388 /lava-12074028/1/../bin/lava-test-case
11263 11:47:13.056976 <8>[ 39.522907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11264 11:47:13.057824 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11266 11:47:13.079370 /lava-12074028/1/../bin/lava-test-case
11267 11:47:13.109359 <8>[ 39.575245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11268 11:47:13.110472 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11270 11:47:14.160386 /lava-12074028/1/../bin/lava-test-case
11271 11:47:14.189185 <8>[ 40.655453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11272 11:47:14.189962 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11274 11:47:14.213099 /lava-12074028/1/../bin/lava-test-case
11275 11:47:14.242569 <8>[ 40.708712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11276 11:47:14.243424 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11278 11:47:15.296134 /lava-12074028/1/../bin/lava-test-case
11279 11:47:15.328135 <8>[ 41.794401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11280 11:47:15.329032 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11282 11:47:15.350812 /lava-12074028/1/../bin/lava-test-case
11283 11:47:15.377242 <8>[ 41.843689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11284 11:47:15.377599 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11286 11:47:15.396191 /lava-12074028/1/../bin/lava-test-case
11287 11:47:15.421248 <8>[ 41.887887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11288 11:47:15.421644 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11290 11:47:16.467383 /lava-12074028/1/../bin/lava-test-case
11291 11:47:16.500047 <8>[ 42.966473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11292 11:47:16.500993 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11294 11:47:16.522782 /lava-12074028/1/../bin/lava-test-case
11295 11:47:16.548368 <8>[ 43.014936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11296 11:47:16.549268 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11298 11:47:16.584895 /lava-12074028/1/../bin/lava-test-case
11299 11:47:16.613693 <8>[ 43.080282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11300 11:47:16.614630 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11302 11:47:16.636981 /lava-12074028/1/../bin/lava-test-case
11303 11:47:16.667852 <8>[ 43.134274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11304 11:47:16.668733 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11306 11:47:16.704329 /lava-12074028/1/../bin/lava-test-case
11307 11:47:16.734238 <8>[ 43.200731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11308 11:47:16.735126 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11310 11:47:16.769540 /lava-12074028/1/../bin/lava-test-case
11311 11:47:16.797470 <8>[ 43.263959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11312 11:47:16.797865 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11314 11:47:16.834050 /lava-12074028/1/../bin/lava-test-case
11315 11:47:16.856478 <8>[ 43.322769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11316 11:47:16.857505 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11318 11:47:16.876797 /lava-12074028/1/../bin/lava-test-case
11319 11:47:16.899063 <8>[ 43.365980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11320 11:47:16.899431 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11322 11:47:16.931793 /lava-12074028/1/../bin/lava-test-case
11323 11:47:16.961120 <8>[ 43.427689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11324 11:47:16.962024 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11326 11:47:17.001370 /lava-12074028/1/../bin/lava-test-case
11327 11:47:17.033243 <8>[ 43.499755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11328 11:47:17.034136 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11330 11:47:17.058562 /lava-12074028/1/../bin/lava-test-case
11331 11:47:17.088550 <8>[ 43.555118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11332 11:47:17.089328 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11334 11:47:17.123012 /lava-12074028/1/../bin/lava-test-case
11335 11:47:17.150726 <8>[ 43.617143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11336 11:47:17.151723 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11338 11:47:17.179068 /lava-12074028/1/../bin/lava-test-case
11339 11:47:17.208143 <8>[ 43.674373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11340 11:47:17.209011 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11342 11:47:17.242562 /lava-12074028/1/../bin/lava-test-case
11343 11:47:17.273507 <8>[ 43.739706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11344 11:47:17.274340 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11346 11:47:17.296705 /lava-12074028/1/../bin/lava-test-case
11347 11:47:17.327010 <8>[ 43.793288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11348 11:47:17.327877 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11350 11:47:17.364846 /lava-12074028/1/../bin/lava-test-case
11351 11:47:17.395639 <8>[ 43.862163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11352 11:47:17.396466 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11354 11:47:17.417768 /lava-12074028/1/../bin/lava-test-case
11355 11:47:17.444392 <8>[ 43.911094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11356 11:47:17.445164 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11358 11:47:17.482656 /lava-12074028/1/../bin/lava-test-case
11359 11:47:17.512756 <8>[ 43.979167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11360 11:47:17.513597 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11362 11:47:17.542930 /lava-12074028/1/../bin/lava-test-case
11363 11:47:17.570337 <8>[ 44.036779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11364 11:47:17.571217 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11366 11:47:17.607567 /lava-12074028/1/../bin/lava-test-case
11367 11:47:17.638080 <8>[ 44.104745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11368 11:47:17.638828 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11370 11:47:17.660581 /lava-12074028/1/../bin/lava-test-case
11371 11:47:17.684748 <8>[ 44.151588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11372 11:47:17.685117 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11374 11:47:18.728811 /lava-12074028/1/../bin/lava-test-case
11375 11:47:18.760626 <8>[ 45.227250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11376 11:47:18.761524 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11378 11:47:19.806911 /lava-12074028/1/../bin/lava-test-case
11379 11:47:19.836989 <8>[ 46.303604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11380 11:47:19.837739 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11382 11:47:19.858041 /lava-12074028/1/../bin/lava-test-case
11383 11:47:19.887430 <8>[ 46.354194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11384 11:47:19.888199 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11386 11:47:19.921324 /lava-12074028/1/../bin/lava-test-case
11387 11:47:19.950492 <8>[ 46.417294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11388 11:47:19.951366 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11390 11:47:19.972621 /lava-12074028/1/../bin/lava-test-case
11391 11:47:20.004053 <8>[ 46.470667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11392 11:47:20.004991 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11394 11:47:20.007141 <6>[ 46.478247] vpu: disabling
11395 11:47:20.010215 <6>[ 46.482117] vproc2: disabling
11396 11:47:20.013842 <6>[ 46.485398] vproc1: disabling
11397 11:47:20.016997 <6>[ 46.488734] vaud18: disabling
11398 11:47:20.020367 <6>[ 46.492257] vsram_others: disabling
11399 11:47:20.023576 <6>[ 46.496216] va09: disabling
11400 11:47:20.026896 <6>[ 46.499403] vsram_md: disabling
11401 11:47:20.030284 <6>[ 46.502963] Vgpu: disabling
11402 11:47:20.039417 /lava-12074028/1/../bin/lava-test-case
11403 11:47:20.070766 <8>[ 46.537553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11404 11:47:20.071683 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11406 11:47:20.093691 /lava-12074028/1/../bin/lava-test-case
11407 11:47:20.124862 <8>[ 46.591638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11408 11:47:20.125743 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11410 11:47:20.166554 /lava-12074028/1/../bin/lava-test-case
11411 11:47:20.189102 <8>[ 46.656261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11412 11:47:20.189469 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11414 11:47:20.208660 /lava-12074028/1/../bin/lava-test-case
11415 11:47:20.234771 <8>[ 46.701873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11416 11:47:20.235391 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11418 11:47:20.269898 /lava-12074028/1/../bin/lava-test-case
11419 11:47:20.302551 <8>[ 46.769409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11420 11:47:20.303389 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11422 11:47:20.324301 /lava-12074028/1/../bin/lava-test-case
11423 11:47:20.355874 <8>[ 46.822743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11424 11:47:20.356728 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11426 11:47:20.393466 /lava-12074028/1/../bin/lava-test-case
11427 11:47:20.423843 <8>[ 46.890805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11428 11:47:20.424714 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11430 11:47:20.446594 /lava-12074028/1/../bin/lava-test-case
11431 11:47:20.478125 <8>[ 46.945186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11432 11:47:20.478839 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11434 11:47:20.521894 /lava-12074028/1/../bin/lava-test-case
11435 11:47:20.550951 <8>[ 47.017959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11436 11:47:20.551690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11438 11:47:20.572575 /lava-12074028/1/../bin/lava-test-case
11439 11:47:20.601897 <8>[ 47.068778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11440 11:47:20.602634 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11442 11:47:20.636605 /lava-12074028/1/../bin/lava-test-case
11443 11:47:20.665286 <8>[ 47.132348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11444 11:47:20.666046 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11446 11:47:20.687720 /lava-12074028/1/../bin/lava-test-case
11447 11:47:20.719980 <8>[ 47.186760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11448 11:47:20.720890 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11450 11:47:20.756389 /lava-12074028/1/../bin/lava-test-case
11451 11:47:20.789037 <8>[ 47.255843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11452 11:47:20.789889 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11454 11:47:20.811532 /lava-12074028/1/../bin/lava-test-case
11455 11:47:20.842568 <8>[ 47.309356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11456 11:47:20.843445 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11458 11:47:20.882571 /lava-12074028/1/../bin/lava-test-case
11459 11:47:20.910301 <8>[ 47.377417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11460 11:47:20.910957 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11462 11:48:00.182484 Marking unfinished test run as failed
11465 11:48:00.184058 end: 4.1 lava-test-shell (duration 00:01:00) [common]
11467 11:48:00.185092 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11469 11:48:00.185899 end: 4 lava-test-retry (duration 00:01:00) [common]
11471 11:48:00.187119 Cleaning after the job
11472 11:48:00.187593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/ramdisk
11473 11:48:00.190494 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/kernel
11474 11:48:00.202476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/dtb
11475 11:48:00.202627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/nfsrootfs
11476 11:48:00.274600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074028/tftp-deploy-zv9inh5g/modules
11477 11:48:00.281834 start: 5.1 power-off (timeout 00:00:30) [common]
11478 11:48:00.282017 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11479 11:48:00.358966 >> Command sent successfully.
11480 11:48:00.364978 Returned 0 in 0 seconds
11481 11:48:00.465987 end: 5.1 power-off (duration 00:00:00) [common]
11483 11:48:00.467742 start: 5.2 read-feedback (timeout 00:10:00) [common]
11484 11:48:00.469299 Listened to connection for namespace 'common' for up to 1s
11485 11:48:01.469794 Finalising connection for namespace 'common'
11486 11:48:01.470489 Disconnecting from shell: Finalise
11487 11:48:01.571618 end: 5.2 read-feedback (duration 00:00:01) [common]
11488 11:48:01.572286 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074028
11489 11:48:01.983336 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074028
11490 11:48:01.983535 TestError: A test failed to run, look at the error message.