Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 33
- Kernel Warnings: 22
- Boot result: PASS
- Errors: 0
1 11:47:43.047809 lava-dispatcher, installed at version: 2023.10
2 11:47:43.048024 start: 0 validate
3 11:47:43.048154 Start time: 2023-11-24 11:47:43.048146+00:00 (UTC)
4 11:47:43.048269 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:47:43.048401 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:47:43.318362 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:47:43.319118 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:47:43.580319 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:47:43.580504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:47:43.846737 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:47:43.846912 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:47:44.114309 validate duration: 1.07
14 11:47:44.114622 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:47:44.114737 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:47:44.114828 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:47:44.114967 Not decompressing ramdisk as can be used compressed.
18 11:47:44.115057 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 11:47:44.115124 saving as /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/ramdisk/rootfs.cpio.gz
20 11:47:44.115205 total size: 43284872 (41 MB)
21 11:47:44.116545 progress 0 % (0 MB)
22 11:47:44.128925 progress 5 % (2 MB)
23 11:47:44.140993 progress 10 % (4 MB)
24 11:47:44.152988 progress 15 % (6 MB)
25 11:47:44.164914 progress 20 % (8 MB)
26 11:47:44.176380 progress 25 % (10 MB)
27 11:47:44.187631 progress 30 % (12 MB)
28 11:47:44.198850 progress 35 % (14 MB)
29 11:47:44.210036 progress 40 % (16 MB)
30 11:47:44.221754 progress 45 % (18 MB)
31 11:47:44.233591 progress 50 % (20 MB)
32 11:47:44.245419 progress 55 % (22 MB)
33 11:47:44.256614 progress 60 % (24 MB)
34 11:47:44.268507 progress 65 % (26 MB)
35 11:47:44.280419 progress 70 % (28 MB)
36 11:47:44.292041 progress 75 % (30 MB)
37 11:47:44.303321 progress 80 % (33 MB)
38 11:47:44.314611 progress 85 % (35 MB)
39 11:47:44.325808 progress 90 % (37 MB)
40 11:47:44.336798 progress 95 % (39 MB)
41 11:47:44.347852 progress 100 % (41 MB)
42 11:47:44.348103 41 MB downloaded in 0.23 s (177.24 MB/s)
43 11:47:44.348261 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:47:44.348512 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:47:44.348600 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:47:44.348683 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:47:44.348820 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:47:44.348889 saving as /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/kernel/Image
50 11:47:44.348953 total size: 49107456 (46 MB)
51 11:47:44.349015 No compression specified
52 11:47:44.350141 progress 0 % (0 MB)
53 11:47:44.362766 progress 5 % (2 MB)
54 11:47:44.375546 progress 10 % (4 MB)
55 11:47:44.388341 progress 15 % (7 MB)
56 11:47:44.401115 progress 20 % (9 MB)
57 11:47:44.413910 progress 25 % (11 MB)
58 11:47:44.426665 progress 30 % (14 MB)
59 11:47:44.439353 progress 35 % (16 MB)
60 11:47:44.452092 progress 40 % (18 MB)
61 11:47:44.464872 progress 45 % (21 MB)
62 11:47:44.477690 progress 50 % (23 MB)
63 11:47:44.490434 progress 55 % (25 MB)
64 11:47:44.503231 progress 60 % (28 MB)
65 11:47:44.516004 progress 65 % (30 MB)
66 11:47:44.528916 progress 70 % (32 MB)
67 11:47:44.541448 progress 75 % (35 MB)
68 11:47:44.554137 progress 80 % (37 MB)
69 11:47:44.567074 progress 85 % (39 MB)
70 11:47:44.579944 progress 90 % (42 MB)
71 11:47:44.592552 progress 95 % (44 MB)
72 11:47:44.605002 progress 100 % (46 MB)
73 11:47:44.605206 46 MB downloaded in 0.26 s (182.76 MB/s)
74 11:47:44.605353 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:47:44.605583 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:47:44.605669 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:47:44.605762 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:47:44.605900 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:47:44.605971 saving as /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/dtb/mt8192-asurada-spherion-r0.dtb
81 11:47:44.606034 total size: 47278 (0 MB)
82 11:47:44.606096 No compression specified
83 11:47:44.607236 progress 69 % (0 MB)
84 11:47:44.607507 progress 100 % (0 MB)
85 11:47:44.607663 0 MB downloaded in 0.00 s (27.71 MB/s)
86 11:47:44.607786 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:47:44.608007 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:47:44.608092 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:47:44.608174 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:47:44.608291 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:47:44.608359 saving as /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/modules/modules.tar
93 11:47:44.608420 total size: 8624756 (8 MB)
94 11:47:44.608481 Using unxz to decompress xz
95 11:47:44.612616 progress 0 % (0 MB)
96 11:47:44.633760 progress 5 % (0 MB)
97 11:47:44.657180 progress 10 % (0 MB)
98 11:47:44.680589 progress 15 % (1 MB)
99 11:47:44.704121 progress 20 % (1 MB)
100 11:47:44.728072 progress 25 % (2 MB)
101 11:47:44.753471 progress 30 % (2 MB)
102 11:47:44.779392 progress 35 % (2 MB)
103 11:47:44.802746 progress 40 % (3 MB)
104 11:47:44.826839 progress 45 % (3 MB)
105 11:47:44.851983 progress 50 % (4 MB)
106 11:47:44.876061 progress 55 % (4 MB)
107 11:47:44.900977 progress 60 % (4 MB)
108 11:47:44.928628 progress 65 % (5 MB)
109 11:47:44.953392 progress 70 % (5 MB)
110 11:47:44.976747 progress 75 % (6 MB)
111 11:47:45.004197 progress 80 % (6 MB)
112 11:47:45.030021 progress 85 % (7 MB)
113 11:47:45.055002 progress 90 % (7 MB)
114 11:47:45.087015 progress 95 % (7 MB)
115 11:47:45.115115 progress 100 % (8 MB)
116 11:47:45.120082 8 MB downloaded in 0.51 s (16.08 MB/s)
117 11:47:45.120378 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:47:45.120785 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:47:45.120911 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:47:45.121041 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:47:45.121156 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:47:45.121275 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:47:45.121549 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_
125 11:47:45.121722 makedir: /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin
126 11:47:45.121866 makedir: /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/tests
127 11:47:45.121997 makedir: /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/results
128 11:47:45.122168 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-add-keys
129 11:47:45.122399 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-add-sources
130 11:47:45.122578 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-background-process-start
131 11:47:45.122750 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-background-process-stop
132 11:47:45.122918 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-common-functions
133 11:47:45.123085 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-echo-ipv4
134 11:47:45.123246 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-install-packages
135 11:47:45.123414 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-installed-packages
136 11:47:45.123578 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-os-build
137 11:47:45.123739 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-probe-channel
138 11:47:45.123905 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-probe-ip
139 11:47:45.124070 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-target-ip
140 11:47:45.124231 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-target-mac
141 11:47:45.124397 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-target-storage
142 11:47:45.124567 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-case
143 11:47:45.124730 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-event
144 11:47:45.124897 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-feedback
145 11:47:45.125062 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-raise
146 11:47:45.125227 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-reference
147 11:47:45.125393 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-runner
148 11:47:45.125557 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-set
149 11:47:45.125721 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-test-shell
150 11:47:45.125894 Updating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-install-packages (oe)
151 11:47:45.126094 Updating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/bin/lava-installed-packages (oe)
152 11:47:45.126307 Creating /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/environment
153 11:47:45.126446 LAVA metadata
154 11:47:45.126553 - LAVA_JOB_ID=12074051
155 11:47:45.126653 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:47:45.126792 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:47:45.126891 skipped lava-vland-overlay
158 11:47:45.126991 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:47:45.127102 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:47:45.127178 skipped lava-multinode-overlay
161 11:47:45.127259 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:47:45.127370 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:47:45.127461 Loading test definitions
164 11:47:45.127572 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:47:45.127653 Using /lava-12074051 at stage 0
166 11:47:45.128058 uuid=12074051_1.5.2.3.1 testdef=None
167 11:47:45.128181 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:47:45.128308 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:47:45.129079 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:47:45.129448 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:47:45.130381 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:47:45.130625 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:47:45.131419 runner path: /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/0/tests/0_igt-kms-mediatek test_uuid 12074051_1.5.2.3.1
176 11:47:45.131608 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:47:45.131831 Creating lava-test-runner.conf files
179 11:47:45.131903 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074051/lava-overlay-034lk5r_/lava-12074051/0 for stage 0
180 11:47:45.131994 - 0_igt-kms-mediatek
181 11:47:45.132117 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:47:45.132232 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:47:45.140466 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:47:45.140582 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:47:45.140674 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:47:45.140760 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:47:45.140860 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:47:46.545619 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:47:46.546055 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:47:46.546206 extracting modules file /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074051/extract-overlay-ramdisk-a6d28ry3/ramdisk
191 11:47:46.845008 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:47:46.845208 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:47:46.845341 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074051/compress-overlay-g0xx34ub/overlay-1.5.2.4.tar.gz to ramdisk
194 11:47:46.845434 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074051/compress-overlay-g0xx34ub/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074051/extract-overlay-ramdisk-a6d28ry3/ramdisk
195 11:47:46.855356 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:47:46.855507 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:47:46.855631 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:47:46.855756 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:47:46.855865 Building ramdisk /var/lib/lava/dispatcher/tmp/12074051/extract-overlay-ramdisk-a6d28ry3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074051/extract-overlay-ramdisk-a6d28ry3/ramdisk
200 11:47:47.877952 >> 369977 blocks
201 11:47:53.684142 rename /var/lib/lava/dispatcher/tmp/12074051/extract-overlay-ramdisk-a6d28ry3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/ramdisk/ramdisk.cpio.gz
202 11:47:53.684633 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:47:53.684794 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 11:47:53.684928 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 11:47:53.685072 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/kernel/Image'
206 11:48:05.770496 Returned 0 in 12 seconds
207 11:48:05.871118 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/kernel/image.itb
208 11:48:06.726009 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:48:06.726436 output: Created: Fri Nov 24 11:48:06 2023
210 11:48:06.726543 output: Image 0 (kernel-1)
211 11:48:06.726644 output: Description:
212 11:48:06.726731 output: Created: Fri Nov 24 11:48:06 2023
213 11:48:06.726813 output: Type: Kernel Image
214 11:48:06.726914 output: Compression: lzma compressed
215 11:48:06.727015 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
216 11:48:06.727114 output: Architecture: AArch64
217 11:48:06.727215 output: OS: Linux
218 11:48:06.727312 output: Load Address: 0x00000000
219 11:48:06.727407 output: Entry Point: 0x00000000
220 11:48:06.727500 output: Hash algo: crc32
221 11:48:06.727597 output: Hash value: 43cfb6ad
222 11:48:06.727691 output: Image 1 (fdt-1)
223 11:48:06.727786 output: Description: mt8192-asurada-spherion-r0
224 11:48:06.727878 output: Created: Fri Nov 24 11:48:06 2023
225 11:48:06.727970 output: Type: Flat Device Tree
226 11:48:06.728062 output: Compression: uncompressed
227 11:48:06.728153 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:48:06.728245 output: Architecture: AArch64
229 11:48:06.728336 output: Hash algo: crc32
230 11:48:06.728428 output: Hash value: cc4352de
231 11:48:06.728520 output: Image 2 (ramdisk-1)
232 11:48:06.728610 output: Description: unavailable
233 11:48:06.728702 output: Created: Fri Nov 24 11:48:06 2023
234 11:48:06.728793 output: Type: RAMDisk Image
235 11:48:06.728884 output: Compression: Unknown Compression
236 11:48:06.728976 output: Data Size: 56432964 Bytes = 55110.32 KiB = 53.82 MiB
237 11:48:06.729067 output: Architecture: AArch64
238 11:48:06.729158 output: OS: Linux
239 11:48:06.729249 output: Load Address: unavailable
240 11:48:06.729339 output: Entry Point: unavailable
241 11:48:06.729430 output: Hash algo: crc32
242 11:48:06.729520 output: Hash value: b3b92ff3
243 11:48:06.729611 output: Default Configuration: 'conf-1'
244 11:48:06.729701 output: Configuration 0 (conf-1)
245 11:48:06.729792 output: Description: mt8192-asurada-spherion-r0
246 11:48:06.729883 output: Kernel: kernel-1
247 11:48:06.729974 output: Init Ramdisk: ramdisk-1
248 11:48:06.730065 output: FDT: fdt-1
249 11:48:06.730155 output: Loadables: kernel-1
250 11:48:06.730246 output:
251 11:48:06.730536 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:48:06.730679 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:48:06.730830 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 11:48:06.730968 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 11:48:06.731082 No LXC device requested
256 11:48:06.731208 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:48:06.731338 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 11:48:06.731458 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:48:06.731565 Checking files for TFTP limit of 4294967296 bytes.
260 11:48:06.732228 end: 1 tftp-deploy (duration 00:00:23) [common]
261 11:48:06.732365 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:48:06.732496 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:48:06.732672 substitutions:
264 11:48:06.732769 - {DTB}: 12074051/tftp-deploy-i2r_xse5/dtb/mt8192-asurada-spherion-r0.dtb
265 11:48:06.732874 - {INITRD}: 12074051/tftp-deploy-i2r_xse5/ramdisk/ramdisk.cpio.gz
266 11:48:06.732973 - {KERNEL}: 12074051/tftp-deploy-i2r_xse5/kernel/Image
267 11:48:06.733071 - {LAVA_MAC}: None
268 11:48:06.733167 - {PRESEED_CONFIG}: None
269 11:48:06.733263 - {PRESEED_LOCAL}: None
270 11:48:06.733358 - {RAMDISK}: 12074051/tftp-deploy-i2r_xse5/ramdisk/ramdisk.cpio.gz
271 11:48:06.733453 - {ROOT_PART}: None
272 11:48:06.733548 - {ROOT}: None
273 11:48:06.733642 - {SERVER_IP}: 192.168.201.1
274 11:48:06.733736 - {TEE}: None
275 11:48:06.733830 Parsed boot commands:
276 11:48:06.733923 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:48:06.734165 Parsed boot commands: tftpboot 192.168.201.1 12074051/tftp-deploy-i2r_xse5/kernel/image.itb 12074051/tftp-deploy-i2r_xse5/kernel/cmdline
278 11:48:06.734337 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:48:06.734468 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:48:06.734611 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:48:06.734714 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:48:06.734796 Not connected, no need to disconnect.
283 11:48:06.734892 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:48:06.734995 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:48:06.735075 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 11:48:06.739151 Setting prompt string to ['lava-test: # ']
287 11:48:06.739552 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:48:06.739708 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:48:06.739823 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:48:06.739935 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:48:06.740247 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 11:48:11.868679 >> Command sent successfully.
293 11:48:11.871122 Returned 0 in 5 seconds
294 11:48:11.971799 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:48:11.973438 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:48:11.974002 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:48:11.974554 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:48:11.974983 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:48:11.975425 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:48:11.976792 [Enter `^Ec?' for help]
302 11:48:12.144819
303 11:48:12.145370
304 11:48:12.145848 F0: 102B 0000
305 11:48:12.146321
306 11:48:12.146741 F3: 1001 0000 [0200]
307 11:48:12.147155
308 11:48:12.147972 F3: 1001 0000
309 11:48:12.148408
310 11:48:12.148852 F7: 102D 0000
311 11:48:12.149356
312 11:48:12.151431 F1: 0000 0000
313 11:48:12.151868
314 11:48:12.152328 V0: 0000 0000 [0001]
315 11:48:12.152750
316 11:48:12.154360 00: 0007 8000
317 11:48:12.154825
318 11:48:12.155272 01: 0000 0000
319 11:48:12.155703
320 11:48:12.157877 BP: 0C00 0209 [0000]
321 11:48:12.158352
322 11:48:12.158801 G0: 1182 0000
323 11:48:12.159224
324 11:48:12.159642 EC: 0000 0021 [4000]
325 11:48:12.161202
326 11:48:12.161703 S7: 0000 0000 [0000]
327 11:48:12.162237
328 11:48:12.165041 CC: 0000 0000 [0001]
329 11:48:12.165561
330 11:48:12.166080 T0: 0000 0040 [010F]
331 11:48:12.166491
332 11:48:12.166811 Jump to BL
333 11:48:12.167117
334 11:48:12.191830
335 11:48:12.192263
336 11:48:12.192598
337 11:48:12.198974 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:48:12.203382 ARM64: Exception handlers installed.
339 11:48:12.205716 ARM64: Testing exception
340 11:48:12.209420 ARM64: Done test exception
341 11:48:12.216013 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:48:12.225915 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:48:12.232371 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:48:12.242474 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:48:12.249085 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:48:12.255907 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:48:12.268106 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:48:12.274679 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:48:12.294069 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:48:12.297076 WDT: Last reset was cold boot
351 11:48:12.301068 SPI1(PAD0) initialized at 2873684 Hz
352 11:48:12.304023 SPI5(PAD0) initialized at 992727 Hz
353 11:48:12.307075 VBOOT: Loading verstage.
354 11:48:12.313775 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:48:12.317371 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:48:12.320674 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:48:12.324078 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:48:12.331400 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:48:12.338058 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:48:12.348816 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:48:12.348903
362 11:48:12.349005
363 11:48:12.359194 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:48:12.362152 ARM64: Exception handlers installed.
365 11:48:12.365727 ARM64: Testing exception
366 11:48:12.365810 ARM64: Done test exception
367 11:48:12.373323 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:48:12.376573 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:48:12.389679 Probing TPM: . done!
370 11:48:12.389761 TPM ready after 0 ms
371 11:48:12.398421 Connected to device vid:did:rid of 1ae0:0028:00
372 11:48:12.405942 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 11:48:12.461782 Initialized TPM device CR50 revision 0
374 11:48:12.473837 tlcl_send_startup: Startup return code is 0
375 11:48:12.473949 TPM: setup succeeded
376 11:48:12.485264 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:48:12.494184 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:48:12.506115 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:48:12.516198 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:48:12.519622 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:48:12.525355 in-header: 03 07 00 00 08 00 00 00
382 11:48:12.528477 in-data: aa e4 47 04 13 02 00 00
383 11:48:12.532743 Chrome EC: UHEPI supported
384 11:48:12.539755 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:48:12.543280 in-header: 03 95 00 00 08 00 00 00
386 11:48:12.546521 in-data: 18 20 20 08 00 00 00 00
387 11:48:12.546619 Phase 1
388 11:48:12.550444 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:48:12.557927 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:48:12.561136 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:48:12.565124 Recovery requested (1009000e)
392 11:48:12.575102 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:48:12.580228 tlcl_extend: response is 0
394 11:48:12.590093 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:48:12.595625 tlcl_extend: response is 0
396 11:48:12.602348 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:48:12.622285 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:48:12.629074 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:48:12.629588
400 11:48:12.629948
401 11:48:12.638962 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:48:12.642709 ARM64: Exception handlers installed.
403 11:48:12.645285 ARM64: Testing exception
404 11:48:12.645755 ARM64: Done test exception
405 11:48:12.667999 pmic_efuse_setting: Set efuses in 11 msecs
406 11:48:12.671137 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:48:12.677777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:48:12.681185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:48:12.688328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:48:12.691743 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:48:12.695764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:48:12.703354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:48:12.706779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:48:12.710367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:48:12.714489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:48:12.721258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:48:12.724991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:48:12.729128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:48:12.732283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:48:12.740137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:48:12.747753 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:48:12.751104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:48:12.758710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:48:12.762049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:48:12.769303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:48:12.773030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:48:12.780394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:48:12.786991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:48:12.790787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:48:12.797692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:48:12.801611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:48:12.809239 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:48:12.813205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:48:12.816302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:48:12.823569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:48:12.826893 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:48:12.830577 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:48:12.837702 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:48:12.841542 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:48:12.848293 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:48:12.851500 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:48:12.855403 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:48:12.862310 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:48:12.866280 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:48:12.870510 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:48:12.877633 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:48:12.881097 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:48:12.885087 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:48:12.888817 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:48:12.892130 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:48:12.899599 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:48:12.903332 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:48:12.907023 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:48:12.910746 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:48:12.914365 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:48:12.918141 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:48:12.921904 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:48:12.932768 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:48:12.940599 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:48:12.943827 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:48:12.950862 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:48:12.962660 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:48:12.965642 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:48:12.969459 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:48:12.972880 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:48:12.981603 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2
467 11:48:12.984853 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:48:12.993128 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:48:12.996607 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:48:13.005722 [RTC]rtc_get_frequency_meter,154: input=15, output=853
471 11:48:13.015141 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 11:48:13.024468 [RTC]rtc_get_frequency_meter,154: input=11, output=790
473 11:48:13.033912 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 11:48:13.043114 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 11:48:13.053076 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 11:48:13.062793 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 11:48:13.066223 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:48:13.073398 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:48:13.077031 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:48:13.080526 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:48:13.083973 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:48:13.087765 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:48:13.091423 ADC[4]: Raw value=905172 ID=7
484 11:48:13.095844 ADC[3]: Raw value=213546 ID=1
485 11:48:13.096373 RAM Code: 0x71
486 11:48:13.098135 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:48:13.105672 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:48:13.113137 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:48:13.120058 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:48:13.123877 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:48:13.127847 in-header: 03 07 00 00 08 00 00 00
492 11:48:13.131555 in-data: aa e4 47 04 13 02 00 00
493 11:48:13.131983 Chrome EC: UHEPI supported
494 11:48:13.137507 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:48:13.142310 in-header: 03 95 00 00 08 00 00 00
496 11:48:13.145461 in-data: 18 20 20 08 00 00 00 00
497 11:48:13.148774 MRC: failed to locate region type 0.
498 11:48:13.155812 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:48:13.159638 DRAM-K: Running full calibration
500 11:48:13.166927 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:48:13.167358 header.status = 0x0
502 11:48:13.170340 header.version = 0x6 (expected: 0x6)
503 11:48:13.173978 header.size = 0xd00 (expected: 0xd00)
504 11:48:13.174638 header.flags = 0x0
505 11:48:13.181195 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:48:13.199692 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 11:48:13.207441 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:48:13.211079 dram_init: ddr_geometry: 2
509 11:48:13.211516 [EMI] MDL number = 2
510 11:48:13.214769 [EMI] Get MDL freq = 0
511 11:48:13.215302 dram_init: ddr_type: 0
512 11:48:13.218450 is_discrete_lpddr4: 1
513 11:48:13.222222 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:48:13.222854
515 11:48:13.223402
516 11:48:13.225604 [Bian_co] ETT version 0.0.0.1
517 11:48:13.229530 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:48:13.230247
519 11:48:13.233134 dramc_set_vcore_voltage set vcore to 650000
520 11:48:13.233705 Read voltage for 800, 4
521 11:48:13.236700 Vio18 = 0
522 11:48:13.237144 Vcore = 650000
523 11:48:13.237485 Vdram = 0
524 11:48:13.240571 Vddq = 0
525 11:48:13.241029 Vmddr = 0
526 11:48:13.241374 dram_init: config_dvfs: 1
527 11:48:13.247342 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:48:13.250456 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:48:13.257707 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:48:13.260833 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:48:13.264804 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:48:13.268196 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:48:13.268673 MEM_TYPE=3, freq_sel=18
534 11:48:13.271906 sv_algorithm_assistance_LP4_1600
535 11:48:13.275685 ============ PULL DRAM RESETB DOWN ============
536 11:48:13.282437 ========== PULL DRAM RESETB DOWN end =========
537 11:48:13.286524 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:48:13.289531 ===================================
539 11:48:13.289964 LPDDR4 DRAM CONFIGURATION
540 11:48:13.292999 ===================================
541 11:48:13.296341 EX_ROW_EN[0] = 0x0
542 11:48:13.299594 EX_ROW_EN[1] = 0x0
543 11:48:13.300151 LP4Y_EN = 0x0
544 11:48:13.302777 WORK_FSP = 0x0
545 11:48:13.303205 WL = 0x2
546 11:48:13.306194 RL = 0x2
547 11:48:13.306646 BL = 0x2
548 11:48:13.310136 RPST = 0x0
549 11:48:13.310716 RD_PRE = 0x0
550 11:48:13.312628 WR_PRE = 0x1
551 11:48:13.313057 WR_PST = 0x0
552 11:48:13.316580 DBI_WR = 0x0
553 11:48:13.317004 DBI_RD = 0x0
554 11:48:13.319676 OTF = 0x1
555 11:48:13.323392 ===================================
556 11:48:13.326609 ===================================
557 11:48:13.327151 ANA top config
558 11:48:13.330218 ===================================
559 11:48:13.332813 DLL_ASYNC_EN = 0
560 11:48:13.336730 ALL_SLAVE_EN = 1
561 11:48:13.339482 NEW_RANK_MODE = 1
562 11:48:13.340008 DLL_IDLE_MODE = 1
563 11:48:13.343134 LP45_APHY_COMB_EN = 1
564 11:48:13.346693 TX_ODT_DIS = 1
565 11:48:13.349357 NEW_8X_MODE = 1
566 11:48:13.353723 ===================================
567 11:48:13.356196 ===================================
568 11:48:13.359702 data_rate = 1600
569 11:48:13.360221 CKR = 1
570 11:48:13.362813 DQ_P2S_RATIO = 8
571 11:48:13.366215 ===================================
572 11:48:13.369767 CA_P2S_RATIO = 8
573 11:48:13.373518 DQ_CA_OPEN = 0
574 11:48:13.376769 DQ_SEMI_OPEN = 0
575 11:48:13.377295 CA_SEMI_OPEN = 0
576 11:48:13.380350 CA_FULL_RATE = 0
577 11:48:13.382933 DQ_CKDIV4_EN = 1
578 11:48:13.386451 CA_CKDIV4_EN = 1
579 11:48:13.390324 CA_PREDIV_EN = 0
580 11:48:13.390859 PH8_DLY = 0
581 11:48:13.393284 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:48:13.396751 DQ_AAMCK_DIV = 4
583 11:48:13.400330 CA_AAMCK_DIV = 4
584 11:48:13.402872 CA_ADMCK_DIV = 4
585 11:48:13.406350 DQ_TRACK_CA_EN = 0
586 11:48:13.409885 CA_PICK = 800
587 11:48:13.410467 CA_MCKIO = 800
588 11:48:13.413661 MCKIO_SEMI = 0
589 11:48:13.416833 PLL_FREQ = 3068
590 11:48:13.420513 DQ_UI_PI_RATIO = 32
591 11:48:13.424171 CA_UI_PI_RATIO = 0
592 11:48:13.424635 ===================================
593 11:48:13.427925 ===================================
594 11:48:13.431665 memory_type:LPDDR4
595 11:48:13.435245 GP_NUM : 10
596 11:48:13.435676 SRAM_EN : 1
597 11:48:13.438816 MD32_EN : 0
598 11:48:13.442653 ===================================
599 11:48:13.443083 [ANA_INIT] >>>>>>>>>>>>>>
600 11:48:13.446154 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:48:13.449683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:48:13.453367 ===================================
603 11:48:13.457137 data_rate = 1600,PCW = 0X7600
604 11:48:13.460053 ===================================
605 11:48:13.463457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:48:13.466338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:48:13.473543 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:48:13.476768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:48:13.479791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:48:13.483454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:48:13.486447 [ANA_INIT] flow start
612 11:48:13.490240 [ANA_INIT] PLL >>>>>>>>
613 11:48:13.490715 [ANA_INIT] PLL <<<<<<<<
614 11:48:13.493129 [ANA_INIT] MIDPI >>>>>>>>
615 11:48:13.496602 [ANA_INIT] MIDPI <<<<<<<<
616 11:48:13.500107 [ANA_INIT] DLL >>>>>>>>
617 11:48:13.500539 [ANA_INIT] flow end
618 11:48:13.503062 ============ LP4 DIFF to SE enter ============
619 11:48:13.509973 ============ LP4 DIFF to SE exit ============
620 11:48:13.510581 [ANA_INIT] <<<<<<<<<<<<<
621 11:48:13.513058 [Flow] Enable top DCM control >>>>>
622 11:48:13.516354 [Flow] Enable top DCM control <<<<<
623 11:48:13.520798 Enable DLL master slave shuffle
624 11:48:13.526171 ==============================================================
625 11:48:13.526820 Gating Mode config
626 11:48:13.533068 ==============================================================
627 11:48:13.536083 Config description:
628 11:48:13.546315 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:48:13.552870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:48:13.556266 SELPH_MODE 0: By rank 1: By Phase
631 11:48:13.562794 ==============================================================
632 11:48:13.566700 GAT_TRACK_EN = 1
633 11:48:13.567290 RX_GATING_MODE = 2
634 11:48:13.569206 RX_GATING_TRACK_MODE = 2
635 11:48:13.572980 SELPH_MODE = 1
636 11:48:13.576308 PICG_EARLY_EN = 1
637 11:48:13.579173 VALID_LAT_VALUE = 1
638 11:48:13.586549 ==============================================================
639 11:48:13.589415 Enter into Gating configuration >>>>
640 11:48:13.593527 Exit from Gating configuration <<<<
641 11:48:13.596330 Enter into DVFS_PRE_config >>>>>
642 11:48:13.606483 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:48:13.609354 Exit from DVFS_PRE_config <<<<<
644 11:48:13.613139 Enter into PICG configuration >>>>
645 11:48:13.616823 Exit from PICG configuration <<<<
646 11:48:13.619614 [RX_INPUT] configuration >>>>>
647 11:48:13.623254 [RX_INPUT] configuration <<<<<
648 11:48:13.626158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:48:13.632620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:48:13.639425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:48:13.642814 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:48:13.649202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:48:13.656718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:48:13.659644 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:48:13.662985 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:48:13.669238 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:48:13.673026 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:48:13.675797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:48:13.682479 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:48:13.685838 ===================================
661 11:48:13.686601 LPDDR4 DRAM CONFIGURATION
662 11:48:13.688953 ===================================
663 11:48:13.692257 EX_ROW_EN[0] = 0x0
664 11:48:13.696140 EX_ROW_EN[1] = 0x0
665 11:48:13.696716 LP4Y_EN = 0x0
666 11:48:13.699139 WORK_FSP = 0x0
667 11:48:13.699615 WL = 0x2
668 11:48:13.702882 RL = 0x2
669 11:48:13.703461 BL = 0x2
670 11:48:13.706438 RPST = 0x0
671 11:48:13.707019 RD_PRE = 0x0
672 11:48:13.709102 WR_PRE = 0x1
673 11:48:13.709678 WR_PST = 0x0
674 11:48:13.712440 DBI_WR = 0x0
675 11:48:13.713016 DBI_RD = 0x0
676 11:48:13.715725 OTF = 0x1
677 11:48:13.718981 ===================================
678 11:48:13.722553 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:48:13.725537 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:48:13.731869 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:48:13.735528 ===================================
682 11:48:13.736102 LPDDR4 DRAM CONFIGURATION
683 11:48:13.739145 ===================================
684 11:48:13.742023 EX_ROW_EN[0] = 0x10
685 11:48:13.745606 EX_ROW_EN[1] = 0x0
686 11:48:13.746190 LP4Y_EN = 0x0
687 11:48:13.748673 WORK_FSP = 0x0
688 11:48:13.749102 WL = 0x2
689 11:48:13.752274 RL = 0x2
690 11:48:13.752709 BL = 0x2
691 11:48:13.755097 RPST = 0x0
692 11:48:13.755523 RD_PRE = 0x0
693 11:48:13.758764 WR_PRE = 0x1
694 11:48:13.759192 WR_PST = 0x0
695 11:48:13.761996 DBI_WR = 0x0
696 11:48:13.762573 DBI_RD = 0x0
697 11:48:13.765176 OTF = 0x1
698 11:48:13.768554 ===================================
699 11:48:13.775121 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:48:13.778944 nWR fixed to 40
701 11:48:13.779606 [ModeRegInit_LP4] CH0 RK0
702 11:48:13.781969 [ModeRegInit_LP4] CH0 RK1
703 11:48:13.785846 [ModeRegInit_LP4] CH1 RK0
704 11:48:13.786467 [ModeRegInit_LP4] CH1 RK1
705 11:48:13.788994 match AC timing 13
706 11:48:13.791717 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:48:13.795424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:48:13.802168 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:48:13.805197 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:48:13.811915 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:48:13.812501 [EMI DOE] emi_dcm 0
712 11:48:13.818377 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:48:13.818959 ==
714 11:48:13.821414 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:48:13.825105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:48:13.825684 ==
717 11:48:13.831644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:48:13.834825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:48:13.845502 [CA 0] Center 37 (7~68) winsize 62
720 11:48:13.848791 [CA 1] Center 37 (6~68) winsize 63
721 11:48:13.852213 [CA 2] Center 34 (4~65) winsize 62
722 11:48:13.855363 [CA 3] Center 35 (4~66) winsize 63
723 11:48:13.858609 [CA 4] Center 33 (3~64) winsize 62
724 11:48:13.861866 [CA 5] Center 33 (3~64) winsize 62
725 11:48:13.862396
726 11:48:13.865294 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:48:13.865771
728 11:48:13.869068 [CATrainingPosCal] consider 1 rank data
729 11:48:13.871916 u2DelayCellTimex100 = 270/100 ps
730 11:48:13.875493 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:48:13.878865 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:48:13.885638 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:48:13.889032 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 11:48:13.891880 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:48:13.895072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:48:13.895633
737 11:48:13.898417 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:48:13.899002
739 11:48:13.902154 [CBTSetCACLKResult] CA Dly = 33
740 11:48:13.902769 CS Dly: 5 (0~36)
741 11:48:13.904925 ==
742 11:48:13.908464 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:48:13.911658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:48:13.912131 ==
745 11:48:13.915076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:48:13.922060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:48:13.931733 [CA 0] Center 38 (7~69) winsize 63
748 11:48:13.935156 [CA 1] Center 37 (7~68) winsize 62
749 11:48:13.938134 [CA 2] Center 35 (4~66) winsize 63
750 11:48:13.942053 [CA 3] Center 35 (4~66) winsize 63
751 11:48:13.945681 [CA 4] Center 34 (3~65) winsize 63
752 11:48:13.948049 [CA 5] Center 33 (3~64) winsize 62
753 11:48:13.948520
754 11:48:13.951663 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:48:13.952132
756 11:48:13.954741 [CATrainingPosCal] consider 2 rank data
757 11:48:13.958135 u2DelayCellTimex100 = 270/100 ps
758 11:48:13.961469 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:48:13.968139 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:48:13.971556 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 11:48:13.974957 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 11:48:13.978957 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:48:13.982362 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:48:13.982927
765 11:48:13.984641 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:48:13.985107
767 11:48:13.988024 [CBTSetCACLKResult] CA Dly = 33
768 11:48:13.991047 CS Dly: 6 (0~38)
769 11:48:13.991607
770 11:48:13.994730 ----->DramcWriteLeveling(PI) begin...
771 11:48:13.995318 ==
772 11:48:13.998775 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:48:14.001968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:48:14.002603 ==
775 11:48:14.005799 Write leveling (Byte 0): 29 => 29
776 11:48:14.006316 Write leveling (Byte 1): 28 => 28
777 11:48:14.009525 DramcWriteLeveling(PI) end<-----
778 11:48:14.009998
779 11:48:14.010497 ==
780 11:48:14.012665 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:48:14.019733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:48:14.020305 ==
783 11:48:14.020655 [Gating] SW mode calibration
784 11:48:14.026803 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:48:14.033505 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:48:14.036751 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:48:14.043805 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:48:14.047709 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:48:14.050447 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:48:14.053802 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:48:14.059903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:48:14.063097 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:48:14.066677 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:48:14.073620 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:48:14.077047 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:48:14.080140 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:48:14.086923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:48:14.090245 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:48:14.093434 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:48:14.100801 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:48:14.103793 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:48:14.106893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:48:14.113180 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:48:14.116577 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:48:14.120175 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:48:14.127258 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:48:14.130002 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:48:14.133198 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:48:14.139795 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:48:14.143262 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:48:14.146338 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:48:14.152713 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
813 11:48:14.156505 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
814 11:48:14.159652 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:48:14.166610 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:48:14.169985 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:48:14.173272 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:48:14.179657 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:48:14.183262 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
820 11:48:14.186356 0 10 8 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
821 11:48:14.190107 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
822 11:48:14.196528 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:48:14.200187 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:48:14.203127 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:48:14.209803 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:48:14.213137 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:48:14.216179 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
828 11:48:14.222876 0 11 8 | B1->B0 | 2828 3f3f | 0 0 | (0 0) (0 0)
829 11:48:14.225941 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
830 11:48:14.229610 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:48:14.236188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:48:14.239278 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:48:14.242951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:48:14.250374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:48:14.252645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:48:14.256406 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 11:48:14.263193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:48:14.266157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:48:14.269134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:48:14.275742 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:48:14.279417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:48:14.282892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:48:14.289043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:48:14.292239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:48:14.296224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:48:14.302815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:48:14.306033 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:48:14.309083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:48:14.315513 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:48:14.319020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:48:14.322690 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:48:14.328808 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:48:14.329334 Total UI for P1: 0, mck2ui 16
854 11:48:14.332570 best dqsien dly found for B0: ( 0, 14, 4)
855 11:48:14.339072 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:48:14.342437 Total UI for P1: 0, mck2ui 16
857 11:48:14.346147 best dqsien dly found for B1: ( 0, 14, 8)
858 11:48:14.349081 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:48:14.352613 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:48:14.353139
861 11:48:14.355972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:48:14.358748 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:48:14.362204 [Gating] SW calibration Done
864 11:48:14.362661 ==
865 11:48:14.366100 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:48:14.370076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:48:14.370668 ==
868 11:48:14.373272 RX Vref Scan: 0
869 11:48:14.373746
870 11:48:14.374313 RX Vref 0 -> 0, step: 1
871 11:48:14.374662
872 11:48:14.376126 RX Delay -130 -> 252, step: 16
873 11:48:14.379515 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:48:14.385997 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:48:14.389564 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:48:14.392570 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:48:14.396184 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 11:48:14.399499 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:48:14.406476 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:48:14.410121 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:48:14.412708 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:48:14.416213 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 11:48:14.420015 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 11:48:14.426940 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:48:14.429356 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:48:14.433026 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:48:14.436049 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:48:14.439380 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:48:14.442703 ==
890 11:48:14.445898 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:48:14.449418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:48:14.450002 ==
893 11:48:14.450448 DQS Delay:
894 11:48:14.452604 DQS0 = 0, DQS1 = 0
895 11:48:14.453176 DQM Delay:
896 11:48:14.455562 DQM0 = 88, DQM1 = 76
897 11:48:14.456038 DQ Delay:
898 11:48:14.459142 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:48:14.462967 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 11:48:14.465832 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
901 11:48:14.469447 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:48:14.470085
903 11:48:14.470598
904 11:48:14.470958 ==
905 11:48:14.472459 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:48:14.475586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:48:14.476063 ==
908 11:48:14.476445
909 11:48:14.476792
910 11:48:14.479558 TX Vref Scan disable
911 11:48:14.483310 == TX Byte 0 ==
912 11:48:14.486225 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 11:48:14.488956 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 11:48:14.492396 == TX Byte 1 ==
915 11:48:14.495917 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 11:48:14.499163 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 11:48:14.499596 ==
918 11:48:14.502113 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:48:14.508775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:48:14.509256 ==
921 11:48:14.520029 TX Vref=22, minBit 1, minWin=26, winSum=437
922 11:48:14.523739 TX Vref=24, minBit 1, minWin=26, winSum=438
923 11:48:14.526681 TX Vref=26, minBit 1, minWin=27, winSum=447
924 11:48:14.530567 TX Vref=28, minBit 3, minWin=27, winSum=451
925 11:48:14.533873 TX Vref=30, minBit 1, minWin=28, winSum=455
926 11:48:14.540315 TX Vref=32, minBit 2, minWin=27, winSum=448
927 11:48:14.543574 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 30
928 11:48:14.544202
929 11:48:14.546550 Final TX Range 1 Vref 30
930 11:48:14.546980
931 11:48:14.547318 ==
932 11:48:14.550212 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:48:14.553274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:48:14.553707 ==
935 11:48:14.556801
936 11:48:14.557229
937 11:48:14.557574 TX Vref Scan disable
938 11:48:14.560156 == TX Byte 0 ==
939 11:48:14.563118 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 11:48:14.569757 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 11:48:14.570238 == TX Byte 1 ==
942 11:48:14.573276 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 11:48:14.581131 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 11:48:14.581670
945 11:48:14.582015 [DATLAT]
946 11:48:14.582374 Freq=800, CH0 RK0
947 11:48:14.582697
948 11:48:14.583488 DATLAT Default: 0xa
949 11:48:14.583849 0, 0xFFFF, sum = 0
950 11:48:14.587373 1, 0xFFFF, sum = 0
951 11:48:14.587805 2, 0xFFFF, sum = 0
952 11:48:14.589786 3, 0xFFFF, sum = 0
953 11:48:14.593199 4, 0xFFFF, sum = 0
954 11:48:14.593749 5, 0xFFFF, sum = 0
955 11:48:14.596635 6, 0xFFFF, sum = 0
956 11:48:14.597173 7, 0xFFFF, sum = 0
957 11:48:14.600051 8, 0xFFFF, sum = 0
958 11:48:14.600485 9, 0x0, sum = 1
959 11:48:14.603391 10, 0x0, sum = 2
960 11:48:14.603822 11, 0x0, sum = 3
961 11:48:14.604171 12, 0x0, sum = 4
962 11:48:14.606517 best_step = 10
963 11:48:14.606941
964 11:48:14.607278 ==
965 11:48:14.610864 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:48:14.613510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:48:14.614050 ==
968 11:48:14.616529 RX Vref Scan: 1
969 11:48:14.617064
970 11:48:14.617412 Set Vref Range= 32 -> 127
971 11:48:14.619583
972 11:48:14.620009 RX Vref 32 -> 127, step: 1
973 11:48:14.620352
974 11:48:14.623429 RX Delay -111 -> 252, step: 8
975 11:48:14.623964
976 11:48:14.626875 Set Vref, RX VrefLevel [Byte0]: 32
977 11:48:14.629912 [Byte1]: 32
978 11:48:14.630487
979 11:48:14.633166 Set Vref, RX VrefLevel [Byte0]: 33
980 11:48:14.636082 [Byte1]: 33
981 11:48:14.640563
982 11:48:14.640991 Set Vref, RX VrefLevel [Byte0]: 34
983 11:48:14.644466 [Byte1]: 34
984 11:48:14.648633
985 11:48:14.649161 Set Vref, RX VrefLevel [Byte0]: 35
986 11:48:14.651991 [Byte1]: 35
987 11:48:14.656757
988 11:48:14.657310 Set Vref, RX VrefLevel [Byte0]: 36
989 11:48:14.659469 [Byte1]: 36
990 11:48:14.663813
991 11:48:14.664338 Set Vref, RX VrefLevel [Byte0]: 37
992 11:48:14.667177 [Byte1]: 37
993 11:48:14.671633
994 11:48:14.672059 Set Vref, RX VrefLevel [Byte0]: 38
995 11:48:14.674838 [Byte1]: 38
996 11:48:14.679784
997 11:48:14.680329 Set Vref, RX VrefLevel [Byte0]: 39
998 11:48:14.683315 [Byte1]: 39
999 11:48:14.687009
1000 11:48:14.687435 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:48:14.690554 [Byte1]: 40
1002 11:48:14.694592
1003 11:48:14.695027 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:48:14.697737 [Byte1]: 41
1005 11:48:14.701767
1006 11:48:14.702200 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:48:14.705079 [Byte1]: 42
1008 11:48:14.710045
1009 11:48:14.710595 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:48:14.712840 [Byte1]: 43
1011 11:48:14.717111
1012 11:48:14.717647 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:48:14.720489 [Byte1]: 44
1014 11:48:14.725246
1015 11:48:14.725820 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:48:14.728285 [Byte1]: 45
1017 11:48:14.732838
1018 11:48:14.733436 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:48:14.735371 [Byte1]: 46
1020 11:48:14.740130
1021 11:48:14.740699 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:48:14.743254 [Byte1]: 47
1023 11:48:14.747913
1024 11:48:14.748461 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:48:14.750805 [Byte1]: 48
1026 11:48:14.755366
1027 11:48:14.755864 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:48:14.758551 [Byte1]: 49
1029 11:48:14.763148
1030 11:48:14.763570 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:48:14.766234 [Byte1]: 50
1032 11:48:14.770828
1033 11:48:14.771301 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:48:14.773774 [Byte1]: 51
1035 11:48:14.778086
1036 11:48:14.778547 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:48:14.781518 [Byte1]: 52
1038 11:48:14.786068
1039 11:48:14.786658 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:48:14.789242 [Byte1]: 53
1041 11:48:14.793481
1042 11:48:14.793965 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:48:14.796542 [Byte1]: 54
1044 11:48:14.800887
1045 11:48:14.801441 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:48:14.804665 [Byte1]: 55
1047 11:48:14.809142
1048 11:48:14.809656 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:48:14.812135 [Byte1]: 56
1050 11:48:14.816233
1051 11:48:14.816644 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:48:14.819861 [Byte1]: 57
1053 11:48:14.824444
1054 11:48:14.824860 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:48:14.827522 [Byte1]: 58
1056 11:48:14.832640
1057 11:48:14.833127 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:48:14.835353 [Byte1]: 59
1059 11:48:14.839514
1060 11:48:14.840000 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:48:14.843398 [Byte1]: 60
1062 11:48:14.847237
1063 11:48:14.847699 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:48:14.850326 [Byte1]: 61
1065 11:48:14.854721
1066 11:48:14.855230 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:48:14.857922 [Byte1]: 62
1068 11:48:14.862507
1069 11:48:14.862923 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:48:14.865811 [Byte1]: 63
1071 11:48:14.870051
1072 11:48:14.870580 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:48:14.873295 [Byte1]: 64
1074 11:48:14.877853
1075 11:48:14.878414 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:48:14.880880 [Byte1]: 65
1077 11:48:14.885059
1078 11:48:14.885503 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:48:14.888687 [Byte1]: 66
1080 11:48:14.893098
1081 11:48:14.893516 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:48:14.896160 [Byte1]: 67
1083 11:48:14.900304
1084 11:48:14.900721 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:48:14.903603 [Byte1]: 68
1086 11:48:14.908117
1087 11:48:14.908539 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:48:14.911382 [Byte1]: 69
1089 11:48:14.916114
1090 11:48:14.916519 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:48:14.919212 [Byte1]: 70
1092 11:48:14.923540
1093 11:48:14.924046 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:48:14.926449 [Byte1]: 71
1095 11:48:14.931258
1096 11:48:14.931765 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:48:14.934738 [Byte1]: 72
1098 11:48:14.939100
1099 11:48:14.939574 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:48:14.941796 [Byte1]: 73
1101 11:48:14.946733
1102 11:48:14.947210 Final RX Vref Byte 0 = 56 to rank0
1103 11:48:14.950154 Final RX Vref Byte 1 = 59 to rank0
1104 11:48:14.953390 Final RX Vref Byte 0 = 56 to rank1
1105 11:48:14.956771 Final RX Vref Byte 1 = 59 to rank1==
1106 11:48:14.959757 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 11:48:14.966563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 11:48:14.967062 ==
1109 11:48:14.967429 DQS Delay:
1110 11:48:14.967744 DQS0 = 0, DQS1 = 0
1111 11:48:14.969552 DQM Delay:
1112 11:48:14.969962 DQM0 = 88, DQM1 = 77
1113 11:48:14.972803 DQ Delay:
1114 11:48:14.976287 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1115 11:48:14.976792 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1116 11:48:14.979452 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1117 11:48:14.986199 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 11:48:14.986663
1119 11:48:14.987069
1120 11:48:14.992780 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1121 11:48:14.996428 CH0 RK0: MR19=606, MR18=2D27
1122 11:48:15.002918 CH0_RK0: MR19=0x606, MR18=0x2D27, DQSOSC=398, MR23=63, INC=93, DEC=62
1123 11:48:15.003352
1124 11:48:15.006475 ----->DramcWriteLeveling(PI) begin...
1125 11:48:15.006959 ==
1126 11:48:15.009681 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 11:48:15.013426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 11:48:15.013840 ==
1129 11:48:15.016806 Write leveling (Byte 0): 31 => 31
1130 11:48:15.019957 Write leveling (Byte 1): 30 => 30
1131 11:48:15.023082 DramcWriteLeveling(PI) end<-----
1132 11:48:15.023503
1133 11:48:15.023833 ==
1134 11:48:15.025784 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 11:48:15.029762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 11:48:15.030332 ==
1137 11:48:15.032999 [Gating] SW mode calibration
1138 11:48:15.039419 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 11:48:15.046110 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 11:48:15.049285 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 11:48:15.052442 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1142 11:48:15.099895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 11:48:15.100432 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 11:48:15.101167 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 11:48:15.101546 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 11:48:15.101953 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:48:15.102443 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:48:15.102798 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:48:15.103184 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:48:15.103652 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:48:15.104147 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:48:15.133629 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:48:15.134182 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:48:15.134971 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:48:15.135350 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:48:15.135697 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:48:15.136091 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1158 11:48:15.136583 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 11:48:15.136927 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:48:15.139051 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:48:15.141822 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:48:15.147759 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:48:15.151921 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:48:15.154433 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:48:15.161703 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1166 11:48:15.164386 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1167 11:48:15.167923 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1168 11:48:15.171283 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 11:48:15.177896 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 11:48:15.181365 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:48:15.184730 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:48:15.190775 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1173 11:48:15.194329 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1174 11:48:15.198177 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (0 1) (1 0)
1175 11:48:15.204535 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:48:15.207627 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:48:15.211716 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:48:15.217972 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:48:15.221326 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:48:15.224128 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:48:15.231131 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1182 11:48:15.234976 0 11 8 | B1->B0 | 3333 4545 | 0 0 | (1 1) (0 0)
1183 11:48:15.237989 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 11:48:15.244446 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 11:48:15.248463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 11:48:15.252198 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:48:15.255457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:48:15.258804 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:48:15.266624 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1190 11:48:15.269742 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1191 11:48:15.272641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 11:48:15.279060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 11:48:15.282717 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:48:15.286335 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:48:15.292467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:48:15.296088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:48:15.299039 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:48:15.306050 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:48:15.309392 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:48:15.312774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:48:15.319013 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:48:15.322874 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:48:15.326210 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:48:15.332738 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:48:15.335743 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 11:48:15.339268 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1207 11:48:15.345976 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:48:15.346485 Total UI for P1: 0, mck2ui 16
1209 11:48:15.352150 best dqsien dly found for B0: ( 0, 14, 6)
1210 11:48:15.352609 Total UI for P1: 0, mck2ui 16
1211 11:48:15.355942 best dqsien dly found for B1: ( 0, 14, 10)
1212 11:48:15.362791 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1213 11:48:15.365491 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1214 11:48:15.365906
1215 11:48:15.368857 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1216 11:48:15.372155 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1217 11:48:15.375663 [Gating] SW calibration Done
1218 11:48:15.376076 ==
1219 11:48:15.378610 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 11:48:15.382328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 11:48:15.382853 ==
1222 11:48:15.386068 RX Vref Scan: 0
1223 11:48:15.386581
1224 11:48:15.386919 RX Vref 0 -> 0, step: 1
1225 11:48:15.387230
1226 11:48:15.389271 RX Delay -130 -> 252, step: 16
1227 11:48:15.392461 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1228 11:48:15.398959 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1229 11:48:15.402179 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1230 11:48:15.405264 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1231 11:48:15.408821 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1232 11:48:15.412071 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1233 11:48:15.415693 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 11:48:15.422229 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 11:48:15.425810 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 11:48:15.428847 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 11:48:15.432813 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1238 11:48:15.435263 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 11:48:15.442107 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1240 11:48:15.445352 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 11:48:15.448772 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1242 11:48:15.452214 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 11:48:15.452634 ==
1244 11:48:15.455327 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 11:48:15.461967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 11:48:15.462438 ==
1247 11:48:15.462772 DQS Delay:
1248 11:48:15.465444 DQS0 = 0, DQS1 = 0
1249 11:48:15.465853 DQM Delay:
1250 11:48:15.466181 DQM0 = 86, DQM1 = 77
1251 11:48:15.468832 DQ Delay:
1252 11:48:15.472068 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1253 11:48:15.475545 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1254 11:48:15.478976 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1255 11:48:15.482059 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1256 11:48:15.482645
1257 11:48:15.482988
1258 11:48:15.483299 ==
1259 11:48:15.485348 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:48:15.488581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:48:15.489003 ==
1262 11:48:15.489338
1263 11:48:15.489643
1264 11:48:15.492100 TX Vref Scan disable
1265 11:48:15.492514 == TX Byte 0 ==
1266 11:48:15.498926 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1267 11:48:15.502017 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1268 11:48:15.502636 == TX Byte 1 ==
1269 11:48:15.509220 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1270 11:48:15.512450 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1271 11:48:15.512865 ==
1272 11:48:15.515184 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:48:15.518529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:48:15.518984 ==
1275 11:48:15.533046 TX Vref=22, minBit 1, minWin=27, winSum=439
1276 11:48:15.536017 TX Vref=24, minBit 1, minWin=27, winSum=443
1277 11:48:15.539646 TX Vref=26, minBit 3, minWin=27, winSum=446
1278 11:48:15.542799 TX Vref=28, minBit 2, minWin=27, winSum=447
1279 11:48:15.546164 TX Vref=30, minBit 3, minWin=27, winSum=447
1280 11:48:15.552793 TX Vref=32, minBit 1, minWin=27, winSum=446
1281 11:48:15.555498 [TxChooseVref] Worse bit 2, Min win 27, Win sum 447, Final Vref 28
1282 11:48:15.555923
1283 11:48:15.558988 Final TX Range 1 Vref 28
1284 11:48:15.559409
1285 11:48:15.559740 ==
1286 11:48:15.562323 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:48:15.565957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:48:15.566494 ==
1289 11:48:15.569280
1290 11:48:15.569777
1291 11:48:15.570106 TX Vref Scan disable
1292 11:48:15.572150 == TX Byte 0 ==
1293 11:48:15.575810 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1294 11:48:15.582541 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1295 11:48:15.583140 == TX Byte 1 ==
1296 11:48:15.585654 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1297 11:48:15.592190 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1298 11:48:15.592602
1299 11:48:15.592965 [DATLAT]
1300 11:48:15.593314 Freq=800, CH0 RK1
1301 11:48:15.593610
1302 11:48:15.596112 DATLAT Default: 0xa
1303 11:48:15.596521 0, 0xFFFF, sum = 0
1304 11:48:15.598606 1, 0xFFFF, sum = 0
1305 11:48:15.602942 2, 0xFFFF, sum = 0
1306 11:48:15.603355 3, 0xFFFF, sum = 0
1307 11:48:15.605680 4, 0xFFFF, sum = 0
1308 11:48:15.606093 5, 0xFFFF, sum = 0
1309 11:48:15.609019 6, 0xFFFF, sum = 0
1310 11:48:15.609434 7, 0xFFFF, sum = 0
1311 11:48:15.612213 8, 0xFFFF, sum = 0
1312 11:48:15.612680 9, 0x0, sum = 1
1313 11:48:15.615628 10, 0x0, sum = 2
1314 11:48:15.616105 11, 0x0, sum = 3
1315 11:48:15.618777 12, 0x0, sum = 4
1316 11:48:15.619501 best_step = 10
1317 11:48:15.619956
1318 11:48:15.620350 ==
1319 11:48:15.621988 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 11:48:15.625409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 11:48:15.626015 ==
1322 11:48:15.628891 RX Vref Scan: 0
1323 11:48:15.629435
1324 11:48:15.631821 RX Vref 0 -> 0, step: 1
1325 11:48:15.632236
1326 11:48:15.632694 RX Delay -95 -> 252, step: 8
1327 11:48:15.638934 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 11:48:15.642830 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1329 11:48:15.645493 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1330 11:48:15.649388 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 11:48:15.652115 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1332 11:48:15.658649 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1333 11:48:15.662542 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 11:48:15.665849 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 11:48:15.668717 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 11:48:15.675326 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 11:48:15.678890 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 11:48:15.682444 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1339 11:48:15.685302 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1340 11:48:15.688937 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 11:48:15.695390 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 11:48:15.698367 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 11:48:15.698804 ==
1344 11:48:15.702138 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:48:15.704946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:48:15.705594 ==
1347 11:48:15.708299 DQS Delay:
1348 11:48:15.708709 DQS0 = 0, DQS1 = 0
1349 11:48:15.709040 DQM Delay:
1350 11:48:15.711487 DQM0 = 86, DQM1 = 76
1351 11:48:15.712008 DQ Delay:
1352 11:48:15.715277 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1353 11:48:15.718492 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1354 11:48:15.721492 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1355 11:48:15.724966 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1356 11:48:15.725640
1357 11:48:15.726024
1358 11:48:15.734912 [DQSOSCAuto] RK1, (LSB)MR18= 0x2623, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1359 11:48:15.738319 CH0 RK1: MR19=606, MR18=2623
1360 11:48:15.741527 CH0_RK1: MR19=0x606, MR18=0x2623, DQSOSC=400, MR23=63, INC=92, DEC=61
1361 11:48:15.744980 [RxdqsGatingPostProcess] freq 800
1362 11:48:15.751669 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 11:48:15.754668 Pre-setting of DQS Precalculation
1364 11:48:15.759013 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 11:48:15.759437 ==
1366 11:48:15.761398 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 11:48:15.768137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:48:15.768551 ==
1369 11:48:15.770963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 11:48:15.778320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 11:48:15.787494 [CA 0] Center 37 (6~68) winsize 63
1372 11:48:15.790874 [CA 1] Center 37 (6~68) winsize 63
1373 11:48:15.794433 [CA 2] Center 35 (5~66) winsize 62
1374 11:48:15.797501 [CA 3] Center 34 (4~65) winsize 62
1375 11:48:15.801320 [CA 4] Center 35 (5~66) winsize 62
1376 11:48:15.804026 [CA 5] Center 34 (4~65) winsize 62
1377 11:48:15.804435
1378 11:48:15.807322 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 11:48:15.807778
1380 11:48:15.810524 [CATrainingPosCal] consider 1 rank data
1381 11:48:15.814406 u2DelayCellTimex100 = 270/100 ps
1382 11:48:15.817799 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1383 11:48:15.821425 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1384 11:48:15.827261 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1385 11:48:15.830740 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1386 11:48:15.834508 CA4 delay=35 (5~66),Diff = 1 PI (7 cell)
1387 11:48:15.837005 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1388 11:48:15.837417
1389 11:48:15.840529 CA PerBit enable=1, Macro0, CA PI delay=34
1390 11:48:15.841038
1391 11:48:15.843852 [CBTSetCACLKResult] CA Dly = 34
1392 11:48:15.844592 CS Dly: 5 (0~36)
1393 11:48:15.847274 ==
1394 11:48:15.850129 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 11:48:15.853712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 11:48:15.854193 ==
1397 11:48:15.856974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 11:48:15.863872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 11:48:15.873807 [CA 0] Center 36 (6~67) winsize 62
1400 11:48:15.877546 [CA 1] Center 36 (6~67) winsize 62
1401 11:48:15.880044 [CA 2] Center 35 (4~66) winsize 63
1402 11:48:15.883788 [CA 3] Center 34 (4~65) winsize 62
1403 11:48:15.886525 [CA 4] Center 34 (4~65) winsize 62
1404 11:48:15.890048 [CA 5] Center 34 (4~65) winsize 62
1405 11:48:15.890709
1406 11:48:15.893238 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 11:48:15.893651
1408 11:48:15.896936 [CATrainingPosCal] consider 2 rank data
1409 11:48:15.900027 u2DelayCellTimex100 = 270/100 ps
1410 11:48:15.903321 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 11:48:15.907198 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 11:48:15.910677 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1413 11:48:15.914332 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 11:48:15.917747 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1415 11:48:15.921974 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 11:48:15.922427
1417 11:48:15.926219 CA PerBit enable=1, Macro0, CA PI delay=34
1418 11:48:15.926724
1419 11:48:15.929322 [CBTSetCACLKResult] CA Dly = 34
1420 11:48:15.933416 CS Dly: 5 (0~37)
1421 11:48:15.933935
1422 11:48:15.936110 ----->DramcWriteLeveling(PI) begin...
1423 11:48:15.936556 ==
1424 11:48:15.940128 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 11:48:15.944034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:48:15.944456 ==
1427 11:48:15.947474 Write leveling (Byte 0): 26 => 26
1428 11:48:15.950928 Write leveling (Byte 1): 30 => 30
1429 11:48:15.951435 DramcWriteLeveling(PI) end<-----
1430 11:48:15.951769
1431 11:48:15.954367 ==
1432 11:48:15.956927 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 11:48:15.960592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:48:15.961026 ==
1435 11:48:15.964530 [Gating] SW mode calibration
1436 11:48:15.970314 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 11:48:15.974070 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 11:48:15.980240 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1439 11:48:15.984006 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1440 11:48:15.986955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1441 11:48:15.993797 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 11:48:15.996932 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 11:48:16.000501 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:48:16.007051 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:48:16.010281 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:48:16.014101 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:48:16.020396 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:48:16.024024 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:48:16.026834 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:48:16.033607 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:48:16.036993 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:48:16.040501 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:48:16.047020 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:48:16.050224 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:48:16.053151 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1456 11:48:16.060468 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1457 11:48:16.063316 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:48:16.066730 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:48:16.073068 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:48:16.076562 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:48:16.080125 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:48:16.083005 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:48:16.089607 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1464 11:48:16.093329 0 9 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
1465 11:48:16.096925 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 11:48:16.103001 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 11:48:16.106559 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 11:48:16.109774 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:48:16.116068 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:48:16.120366 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:48:16.123247 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1472 11:48:16.129687 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1473 11:48:16.133744 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:48:16.136478 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:48:16.143266 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:48:16.146522 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:48:16.149484 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:48:16.156621 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:48:16.159607 0 11 4 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
1480 11:48:16.162787 0 11 8 | B1->B0 | 3838 4141 | 1 0 | (0 0) (0 0)
1481 11:48:16.169486 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 11:48:16.173309 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 11:48:16.176019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:48:16.182639 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:48:16.186044 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:48:16.189260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1487 11:48:16.196124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 11:48:16.199650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1489 11:48:16.202676 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 11:48:16.208983 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 11:48:16.212665 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:48:16.215655 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:48:16.222470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:48:16.225474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:48:16.229394 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:48:16.235488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:48:16.239263 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:48:16.242621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:48:16.245644 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:48:16.252391 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:48:16.255809 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:48:16.258887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:48:16.265633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1504 11:48:16.269490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:48:16.272678 Total UI for P1: 0, mck2ui 16
1506 11:48:16.275884 best dqsien dly found for B0: ( 0, 14, 4)
1507 11:48:16.279108 Total UI for P1: 0, mck2ui 16
1508 11:48:16.282218 best dqsien dly found for B1: ( 0, 14, 4)
1509 11:48:16.285402 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1510 11:48:16.288716 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1511 11:48:16.289265
1512 11:48:16.292109 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1513 11:48:16.295866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1514 11:48:16.298729 [Gating] SW calibration Done
1515 11:48:16.299242 ==
1516 11:48:16.302186 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 11:48:16.305382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 11:48:16.308869 ==
1519 11:48:16.309287 RX Vref Scan: 0
1520 11:48:16.309623
1521 11:48:16.312499 RX Vref 0 -> 0, step: 1
1522 11:48:16.312979
1523 11:48:16.315613 RX Delay -130 -> 252, step: 16
1524 11:48:16.319078 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1525 11:48:16.322531 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1526 11:48:16.325302 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1527 11:48:16.329017 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1528 11:48:16.335312 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1529 11:48:16.339133 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1530 11:48:16.342390 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1531 11:48:16.345730 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1532 11:48:16.348460 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1533 11:48:16.355517 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1534 11:48:16.359244 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1535 11:48:16.361994 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1536 11:48:16.365655 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1537 11:48:16.372010 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1538 11:48:16.375127 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1539 11:48:16.378348 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1540 11:48:16.378775 ==
1541 11:48:16.381652 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 11:48:16.385152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 11:48:16.385541 ==
1544 11:48:16.389112 DQS Delay:
1545 11:48:16.389633 DQS0 = 0, DQS1 = 0
1546 11:48:16.391581 DQM Delay:
1547 11:48:16.392102 DQM0 = 88, DQM1 = 78
1548 11:48:16.392439 DQ Delay:
1549 11:48:16.394779 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1550 11:48:16.398248 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1551 11:48:16.401653 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1552 11:48:16.405158 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1553 11:48:16.405570
1554 11:48:16.405922
1555 11:48:16.407954 ==
1556 11:48:16.411353 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:48:16.414722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:48:16.415237 ==
1559 11:48:16.415569
1560 11:48:16.415887
1561 11:48:16.418076 TX Vref Scan disable
1562 11:48:16.418609 == TX Byte 0 ==
1563 11:48:16.424883 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1564 11:48:16.427900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1565 11:48:16.428365 == TX Byte 1 ==
1566 11:48:16.434757 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1567 11:48:16.437843 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1568 11:48:16.438373 ==
1569 11:48:16.440845 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:48:16.444787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:48:16.445288 ==
1572 11:48:16.458968 TX Vref=22, minBit 2, minWin=26, winSum=436
1573 11:48:16.462124 TX Vref=24, minBit 0, minWin=27, winSum=444
1574 11:48:16.465517 TX Vref=26, minBit 1, minWin=27, winSum=448
1575 11:48:16.468951 TX Vref=28, minBit 1, minWin=27, winSum=452
1576 11:48:16.471849 TX Vref=30, minBit 6, minWin=27, winSum=455
1577 11:48:16.478328 TX Vref=32, minBit 2, minWin=27, winSum=451
1578 11:48:16.481981 [TxChooseVref] Worse bit 6, Min win 27, Win sum 455, Final Vref 30
1579 11:48:16.482544
1580 11:48:16.485708 Final TX Range 1 Vref 30
1581 11:48:16.486462
1582 11:48:16.486917 ==
1583 11:48:16.488951 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:48:16.492683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:48:16.493241 ==
1586 11:48:16.493610
1587 11:48:16.493997
1588 11:48:16.495959 TX Vref Scan disable
1589 11:48:16.498885 == TX Byte 0 ==
1590 11:48:16.501951 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1591 11:48:16.505737 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1592 11:48:16.508952 == TX Byte 1 ==
1593 11:48:16.511969 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1594 11:48:16.515467 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1595 11:48:16.515889
1596 11:48:16.519829 [DATLAT]
1597 11:48:16.520247 Freq=800, CH1 RK0
1598 11:48:16.520600
1599 11:48:16.522039 DATLAT Default: 0xa
1600 11:48:16.522534 0, 0xFFFF, sum = 0
1601 11:48:16.525175 1, 0xFFFF, sum = 0
1602 11:48:16.525594 2, 0xFFFF, sum = 0
1603 11:48:16.529304 3, 0xFFFF, sum = 0
1604 11:48:16.529732 4, 0xFFFF, sum = 0
1605 11:48:16.531970 5, 0xFFFF, sum = 0
1606 11:48:16.532396 6, 0xFFFF, sum = 0
1607 11:48:16.535698 7, 0xFFFF, sum = 0
1608 11:48:16.536121 8, 0xFFFF, sum = 0
1609 11:48:16.538630 9, 0x0, sum = 1
1610 11:48:16.539057 10, 0x0, sum = 2
1611 11:48:16.542436 11, 0x0, sum = 3
1612 11:48:16.542950 12, 0x0, sum = 4
1613 11:48:16.545442 best_step = 10
1614 11:48:16.545861
1615 11:48:16.546192 ==
1616 11:48:16.549096 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 11:48:16.552015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 11:48:16.552438 ==
1619 11:48:16.555317 RX Vref Scan: 1
1620 11:48:16.555733
1621 11:48:16.556063 Set Vref Range= 32 -> 127
1622 11:48:16.556374
1623 11:48:16.558481 RX Vref 32 -> 127, step: 1
1624 11:48:16.558898
1625 11:48:16.561798 RX Delay -95 -> 252, step: 8
1626 11:48:16.562216
1627 11:48:16.565193 Set Vref, RX VrefLevel [Byte0]: 32
1628 11:48:16.568447 [Byte1]: 32
1629 11:48:16.568868
1630 11:48:16.572223 Set Vref, RX VrefLevel [Byte0]: 33
1631 11:48:16.574939 [Byte1]: 33
1632 11:48:16.578674
1633 11:48:16.579254 Set Vref, RX VrefLevel [Byte0]: 34
1634 11:48:16.582076 [Byte1]: 34
1635 11:48:16.586485
1636 11:48:16.586951 Set Vref, RX VrefLevel [Byte0]: 35
1637 11:48:16.589592 [Byte1]: 35
1638 11:48:16.594835
1639 11:48:16.595344 Set Vref, RX VrefLevel [Byte0]: 36
1640 11:48:16.597275 [Byte1]: 36
1641 11:48:16.601726
1642 11:48:16.602210 Set Vref, RX VrefLevel [Byte0]: 37
1643 11:48:16.604994 [Byte1]: 37
1644 11:48:16.609190
1645 11:48:16.609608 Set Vref, RX VrefLevel [Byte0]: 38
1646 11:48:16.612491 [Byte1]: 38
1647 11:48:16.617026
1648 11:48:16.617444 Set Vref, RX VrefLevel [Byte0]: 39
1649 11:48:16.620335 [Byte1]: 39
1650 11:48:16.624316
1651 11:48:16.624734 Set Vref, RX VrefLevel [Byte0]: 40
1652 11:48:16.627787 [Byte1]: 40
1653 11:48:16.632282
1654 11:48:16.632703 Set Vref, RX VrefLevel [Byte0]: 41
1655 11:48:16.635036 [Byte1]: 41
1656 11:48:16.639599
1657 11:48:16.640011 Set Vref, RX VrefLevel [Byte0]: 42
1658 11:48:16.643169 [Byte1]: 42
1659 11:48:16.647672
1660 11:48:16.648203 Set Vref, RX VrefLevel [Byte0]: 43
1661 11:48:16.650562 [Byte1]: 43
1662 11:48:16.654585
1663 11:48:16.655090 Set Vref, RX VrefLevel [Byte0]: 44
1664 11:48:16.657902 [Byte1]: 44
1665 11:48:16.662154
1666 11:48:16.663004 Set Vref, RX VrefLevel [Byte0]: 45
1667 11:48:16.665459 [Byte1]: 45
1668 11:48:16.669798
1669 11:48:16.670394 Set Vref, RX VrefLevel [Byte0]: 46
1670 11:48:16.673327 [Byte1]: 46
1671 11:48:16.677307
1672 11:48:16.677729 Set Vref, RX VrefLevel [Byte0]: 47
1673 11:48:16.680658 [Byte1]: 47
1674 11:48:16.685258
1675 11:48:16.685856 Set Vref, RX VrefLevel [Byte0]: 48
1676 11:48:16.688852 [Byte1]: 48
1677 11:48:16.692893
1678 11:48:16.693410 Set Vref, RX VrefLevel [Byte0]: 49
1679 11:48:16.696150 [Byte1]: 49
1680 11:48:16.700514
1681 11:48:16.700926 Set Vref, RX VrefLevel [Byte0]: 50
1682 11:48:16.704239 [Byte1]: 50
1683 11:48:16.707956
1684 11:48:16.708364 Set Vref, RX VrefLevel [Byte0]: 51
1685 11:48:16.711619 [Byte1]: 51
1686 11:48:16.715375
1687 11:48:16.715995 Set Vref, RX VrefLevel [Byte0]: 52
1688 11:48:16.718672 [Byte1]: 52
1689 11:48:16.723574
1690 11:48:16.723991 Set Vref, RX VrefLevel [Byte0]: 53
1691 11:48:16.726115 [Byte1]: 53
1692 11:48:16.731133
1693 11:48:16.731552 Set Vref, RX VrefLevel [Byte0]: 54
1694 11:48:16.734201 [Byte1]: 54
1695 11:48:16.738196
1696 11:48:16.738678 Set Vref, RX VrefLevel [Byte0]: 55
1697 11:48:16.741509 [Byte1]: 55
1698 11:48:16.745963
1699 11:48:16.746552 Set Vref, RX VrefLevel [Byte0]: 56
1700 11:48:16.749600 [Byte1]: 56
1701 11:48:16.753570
1702 11:48:16.753978 Set Vref, RX VrefLevel [Byte0]: 57
1703 11:48:16.756772 [Byte1]: 57
1704 11:48:16.761232
1705 11:48:16.761641 Set Vref, RX VrefLevel [Byte0]: 58
1706 11:48:16.764878 [Byte1]: 58
1707 11:48:16.768630
1708 11:48:16.769092 Set Vref, RX VrefLevel [Byte0]: 59
1709 11:48:16.772055 [Byte1]: 59
1710 11:48:16.776898
1711 11:48:16.777307 Set Vref, RX VrefLevel [Byte0]: 60
1712 11:48:16.779811 [Byte1]: 60
1713 11:48:16.784241
1714 11:48:16.784718 Set Vref, RX VrefLevel [Byte0]: 61
1715 11:48:16.787327 [Byte1]: 61
1716 11:48:16.791569
1717 11:48:16.791978 Set Vref, RX VrefLevel [Byte0]: 62
1718 11:48:16.794791 [Byte1]: 62
1719 11:48:16.799145
1720 11:48:16.799649 Set Vref, RX VrefLevel [Byte0]: 63
1721 11:48:16.802350 [Byte1]: 63
1722 11:48:16.806886
1723 11:48:16.807361 Set Vref, RX VrefLevel [Byte0]: 64
1724 11:48:16.809848 [Byte1]: 64
1725 11:48:16.814413
1726 11:48:16.814888 Set Vref, RX VrefLevel [Byte0]: 65
1727 11:48:16.817650 [Byte1]: 65
1728 11:48:16.822162
1729 11:48:16.822757 Set Vref, RX VrefLevel [Byte0]: 66
1730 11:48:16.825276 [Byte1]: 66
1731 11:48:16.829287
1732 11:48:16.829695 Set Vref, RX VrefLevel [Byte0]: 67
1733 11:48:16.833123 [Byte1]: 67
1734 11:48:16.837730
1735 11:48:16.838234 Set Vref, RX VrefLevel [Byte0]: 68
1736 11:48:16.840475 [Byte1]: 68
1737 11:48:16.844451
1738 11:48:16.844917 Set Vref, RX VrefLevel [Byte0]: 69
1739 11:48:16.848315 [Byte1]: 69
1740 11:48:16.852238
1741 11:48:16.852818 Set Vref, RX VrefLevel [Byte0]: 70
1742 11:48:16.855337 [Byte1]: 70
1743 11:48:16.859896
1744 11:48:16.860393 Set Vref, RX VrefLevel [Byte0]: 71
1745 11:48:16.863577 [Byte1]: 71
1746 11:48:16.867987
1747 11:48:16.868399 Set Vref, RX VrefLevel [Byte0]: 72
1748 11:48:16.870875 [Byte1]: 72
1749 11:48:16.875322
1750 11:48:16.875859 Set Vref, RX VrefLevel [Byte0]: 73
1751 11:48:16.878353 [Byte1]: 73
1752 11:48:16.882550
1753 11:48:16.882960 Set Vref, RX VrefLevel [Byte0]: 74
1754 11:48:16.885686 [Byte1]: 74
1755 11:48:16.890242
1756 11:48:16.890761 Set Vref, RX VrefLevel [Byte0]: 75
1757 11:48:16.893463 [Byte1]: 75
1758 11:48:16.898024
1759 11:48:16.898480 Final RX Vref Byte 0 = 59 to rank0
1760 11:48:16.901095 Final RX Vref Byte 1 = 53 to rank0
1761 11:48:16.904699 Final RX Vref Byte 0 = 59 to rank1
1762 11:48:16.908129 Final RX Vref Byte 1 = 53 to rank1==
1763 11:48:16.911275 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 11:48:16.917529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 11:48:16.918004 ==
1766 11:48:16.918445 DQS Delay:
1767 11:48:16.918777 DQS0 = 0, DQS1 = 0
1768 11:48:16.921091 DQM Delay:
1769 11:48:16.921503 DQM0 = 86, DQM1 = 81
1770 11:48:16.924298 DQ Delay:
1771 11:48:16.927830 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1772 11:48:16.931356 DQ4 =80, DQ5 =96, DQ6 =100, DQ7 =84
1773 11:48:16.934138 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
1774 11:48:16.937627 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1775 11:48:16.938040
1776 11:48:16.938414
1777 11:48:16.944668 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1778 11:48:16.947841 CH1 RK0: MR19=606, MR18=1C2F
1779 11:48:16.954158 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1780 11:48:16.954634
1781 11:48:16.957522 ----->DramcWriteLeveling(PI) begin...
1782 11:48:16.957940 ==
1783 11:48:16.961075 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 11:48:16.963822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 11:48:16.964236 ==
1786 11:48:16.967054 Write leveling (Byte 0): 28 => 28
1787 11:48:16.970635 Write leveling (Byte 1): 27 => 27
1788 11:48:16.973979 DramcWriteLeveling(PI) end<-----
1789 11:48:16.974529
1790 11:48:16.975019 ==
1791 11:48:16.977139 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 11:48:16.980596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 11:48:16.981012 ==
1794 11:48:16.983743 [Gating] SW mode calibration
1795 11:48:16.990104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 11:48:16.997055 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 11:48:17.000464 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1798 11:48:17.006749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1799 11:48:17.010138 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 11:48:17.013586 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 11:48:17.020164 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 11:48:17.023406 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 11:48:17.026980 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 11:48:17.033435 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:48:17.037002 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:48:17.040202 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:48:17.046555 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:48:17.050191 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:48:17.053249 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:48:17.059535 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:48:17.062843 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:48:17.066140 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:48:17.072727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1814 11:48:17.076360 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1815 11:48:17.079565 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:48:17.086283 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:48:17.089209 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:48:17.092665 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:48:17.096372 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:48:17.102931 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:48:17.105866 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:48:17.109558 0 9 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1823 11:48:17.117019 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
1824 11:48:17.119544 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 11:48:17.123255 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 11:48:17.130056 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 11:48:17.132615 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 11:48:17.136244 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 11:48:17.143101 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 11:48:17.146153 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
1831 11:48:17.149213 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1832 11:48:17.156192 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:48:17.159252 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:48:17.162978 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:48:17.169074 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:48:17.172658 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:48:17.176325 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1838 11:48:17.183035 0 11 4 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
1839 11:48:17.185609 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1840 11:48:17.189244 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 11:48:17.195787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 11:48:17.199530 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 11:48:17.202486 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 11:48:17.208660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 11:48:17.213184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 11:48:17.215353 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 11:48:17.222049 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 11:48:17.225838 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 11:48:17.229311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 11:48:17.235282 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 11:48:17.238574 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 11:48:17.242373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 11:48:17.248621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:48:17.251988 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:48:17.255841 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:48:17.262063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:48:17.265253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:48:17.268646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:48:17.275436 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:48:17.278211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:48:17.281534 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1862 11:48:17.288642 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:48:17.289152 Total UI for P1: 0, mck2ui 16
1864 11:48:17.291798 best dqsien dly found for B0: ( 0, 14, 0)
1865 11:48:17.295350 Total UI for P1: 0, mck2ui 16
1866 11:48:17.298549 best dqsien dly found for B1: ( 0, 14, 2)
1867 11:48:17.301740 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1868 11:48:17.308260 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1869 11:48:17.308674
1870 11:48:17.312722 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1871 11:48:17.314904 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1872 11:48:17.318514 [Gating] SW calibration Done
1873 11:48:17.319080 ==
1874 11:48:17.322451 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 11:48:17.325125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 11:48:17.325751 ==
1877 11:48:17.326088 RX Vref Scan: 0
1878 11:48:17.326451
1879 11:48:17.329576 RX Vref 0 -> 0, step: 1
1880 11:48:17.330027
1881 11:48:17.332153 RX Delay -130 -> 252, step: 16
1882 11:48:17.335624 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1883 11:48:17.338495 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1884 11:48:17.345089 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1885 11:48:17.348673 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1886 11:48:17.351931 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1887 11:48:17.355041 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1888 11:48:17.358309 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1889 11:48:17.365124 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1890 11:48:17.368771 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1891 11:48:17.371334 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1892 11:48:17.375359 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1893 11:48:17.378511 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1894 11:48:17.384621 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1895 11:48:17.388500 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1896 11:48:17.392146 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1897 11:48:17.394753 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1898 11:48:17.395167 ==
1899 11:48:17.398691 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 11:48:17.404896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 11:48:17.405409 ==
1902 11:48:17.405748 DQS Delay:
1903 11:48:17.408202 DQS0 = 0, DQS1 = 0
1904 11:48:17.408613 DQM Delay:
1905 11:48:17.408938 DQM0 = 84, DQM1 = 83
1906 11:48:17.411435 DQ Delay:
1907 11:48:17.414508 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1908 11:48:17.418209 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1909 11:48:17.422513 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1910 11:48:17.424693 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1911 11:48:17.425104
1912 11:48:17.425427
1913 11:48:17.425732 ==
1914 11:48:17.428077 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 11:48:17.431705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 11:48:17.432250 ==
1917 11:48:17.432636
1918 11:48:17.432948
1919 11:48:17.434575 TX Vref Scan disable
1920 11:48:17.437983 == TX Byte 0 ==
1921 11:48:17.440892 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1922 11:48:17.444620 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1923 11:48:17.448409 == TX Byte 1 ==
1924 11:48:17.451856 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1925 11:48:17.454441 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1926 11:48:17.454947 ==
1927 11:48:17.458356 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 11:48:17.461247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 11:48:17.464614 ==
1930 11:48:17.475695 TX Vref=22, minBit 1, minWin=27, winSum=442
1931 11:48:17.478664 TX Vref=24, minBit 1, minWin=27, winSum=446
1932 11:48:17.481968 TX Vref=26, minBit 1, minWin=27, winSum=448
1933 11:48:17.485588 TX Vref=28, minBit 3, minWin=27, winSum=452
1934 11:48:17.488547 TX Vref=30, minBit 0, minWin=27, winSum=453
1935 11:48:17.495957 TX Vref=32, minBit 1, minWin=27, winSum=452
1936 11:48:17.498448 [TxChooseVref] Worse bit 0, Min win 27, Win sum 453, Final Vref 30
1937 11:48:17.498865
1938 11:48:17.501944 Final TX Range 1 Vref 30
1939 11:48:17.502399
1940 11:48:17.502734 ==
1941 11:48:17.505258 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 11:48:17.508537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 11:48:17.508955 ==
1944 11:48:17.509284
1945 11:48:17.511700
1946 11:48:17.512134 TX Vref Scan disable
1947 11:48:17.514853 == TX Byte 0 ==
1948 11:48:17.518309 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1949 11:48:17.521927 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1950 11:48:17.525039 == TX Byte 1 ==
1951 11:48:17.529013 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1952 11:48:17.531662 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1953 11:48:17.535414
1954 11:48:17.535919 [DATLAT]
1955 11:48:17.536249 Freq=800, CH1 RK1
1956 11:48:17.536556
1957 11:48:17.538418 DATLAT Default: 0xa
1958 11:48:17.538945 0, 0xFFFF, sum = 0
1959 11:48:17.542581 1, 0xFFFF, sum = 0
1960 11:48:17.543157 2, 0xFFFF, sum = 0
1961 11:48:17.545187 3, 0xFFFF, sum = 0
1962 11:48:17.545701 4, 0xFFFF, sum = 0
1963 11:48:17.548651 5, 0xFFFF, sum = 0
1964 11:48:17.552249 6, 0xFFFF, sum = 0
1965 11:48:17.552765 7, 0xFFFF, sum = 0
1966 11:48:17.554755 8, 0xFFFF, sum = 0
1967 11:48:17.555172 9, 0x0, sum = 1
1968 11:48:17.555508 10, 0x0, sum = 2
1969 11:48:17.558016 11, 0x0, sum = 3
1970 11:48:17.558491 12, 0x0, sum = 4
1971 11:48:17.561905 best_step = 10
1972 11:48:17.562704
1973 11:48:17.563064 ==
1974 11:48:17.565300 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 11:48:17.569028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 11:48:17.569538 ==
1977 11:48:17.571843 RX Vref Scan: 0
1978 11:48:17.572252
1979 11:48:17.572577 RX Vref 0 -> 0, step: 1
1980 11:48:17.572883
1981 11:48:17.575560 RX Delay -95 -> 252, step: 8
1982 11:48:17.582402 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1983 11:48:17.585167 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1984 11:48:17.588364 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1985 11:48:17.592776 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1986 11:48:17.595755 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1987 11:48:17.601679 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1988 11:48:17.605405 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1989 11:48:17.608328 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1990 11:48:17.611826 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1991 11:48:17.615100 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1992 11:48:17.621839 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1993 11:48:17.625448 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1994 11:48:17.628065 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1995 11:48:17.631393 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1996 11:48:17.638197 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1997 11:48:17.641420 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1998 11:48:17.641835 ==
1999 11:48:17.645081 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:48:17.647923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:48:17.648436 ==
2002 11:48:17.651519 DQS Delay:
2003 11:48:17.652020 DQS0 = 0, DQS1 = 0
2004 11:48:17.652351 DQM Delay:
2005 11:48:17.655096 DQM0 = 86, DQM1 = 83
2006 11:48:17.655662 DQ Delay:
2007 11:48:17.657810 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2008 11:48:17.661339 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2009 11:48:17.665356 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2010 11:48:17.667846 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =88
2011 11:48:17.668259
2012 11:48:17.668586
2013 11:48:17.677635 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2014 11:48:17.678216 CH1 RK1: MR19=606, MR18=1D39
2015 11:48:17.684549 CH1_RK1: MR19=0x606, MR18=0x1D39, DQSOSC=395, MR23=63, INC=94, DEC=63
2016 11:48:17.687417 [RxdqsGatingPostProcess] freq 800
2017 11:48:17.694417 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 11:48:17.697720 Pre-setting of DQS Precalculation
2019 11:48:17.700837 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 11:48:17.710902 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 11:48:17.717482 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 11:48:17.717995
2023 11:48:17.718379
2024 11:48:17.720335 [Calibration Summary] 1600 Mbps
2025 11:48:17.720798 CH 0, Rank 0
2026 11:48:17.724175 SW Impedance : PASS
2027 11:48:17.724699 DUTY Scan : NO K
2028 11:48:17.727077 ZQ Calibration : PASS
2029 11:48:17.730586 Jitter Meter : NO K
2030 11:48:17.731106 CBT Training : PASS
2031 11:48:17.734183 Write leveling : PASS
2032 11:48:17.737242 RX DQS gating : PASS
2033 11:48:17.737750 RX DQ/DQS(RDDQC) : PASS
2034 11:48:17.740293 TX DQ/DQS : PASS
2035 11:48:17.743841 RX DATLAT : PASS
2036 11:48:17.744364 RX DQ/DQS(Engine): PASS
2037 11:48:17.747268 TX OE : NO K
2038 11:48:17.747752 All Pass.
2039 11:48:17.748087
2040 11:48:17.750169 CH 0, Rank 1
2041 11:48:17.750632 SW Impedance : PASS
2042 11:48:17.753914 DUTY Scan : NO K
2043 11:48:17.756973 ZQ Calibration : PASS
2044 11:48:17.757603 Jitter Meter : NO K
2045 11:48:17.760466 CBT Training : PASS
2046 11:48:17.760898 Write leveling : PASS
2047 11:48:17.763566 RX DQS gating : PASS
2048 11:48:17.766634 RX DQ/DQS(RDDQC) : PASS
2049 11:48:17.767111 TX DQ/DQS : PASS
2050 11:48:17.770005 RX DATLAT : PASS
2051 11:48:17.773536 RX DQ/DQS(Engine): PASS
2052 11:48:17.774111 TX OE : NO K
2053 11:48:17.776713 All Pass.
2054 11:48:17.777170
2055 11:48:17.777503 CH 1, Rank 0
2056 11:48:17.779948 SW Impedance : PASS
2057 11:48:17.780367 DUTY Scan : NO K
2058 11:48:17.783145 ZQ Calibration : PASS
2059 11:48:17.786527 Jitter Meter : NO K
2060 11:48:17.786946 CBT Training : PASS
2061 11:48:17.790248 Write leveling : PASS
2062 11:48:17.793023 RX DQS gating : PASS
2063 11:48:17.793672 RX DQ/DQS(RDDQC) : PASS
2064 11:48:17.796330 TX DQ/DQS : PASS
2065 11:48:17.799865 RX DATLAT : PASS
2066 11:48:17.800261 RX DQ/DQS(Engine): PASS
2067 11:48:17.802999 TX OE : NO K
2068 11:48:17.803430 All Pass.
2069 11:48:17.803870
2070 11:48:17.806493 CH 1, Rank 1
2071 11:48:17.806935 SW Impedance : PASS
2072 11:48:17.809837 DUTY Scan : NO K
2073 11:48:17.813348 ZQ Calibration : PASS
2074 11:48:17.813868 Jitter Meter : NO K
2075 11:48:17.816912 CBT Training : PASS
2076 11:48:17.817438 Write leveling : PASS
2077 11:48:17.819674 RX DQS gating : PASS
2078 11:48:17.823489 RX DQ/DQS(RDDQC) : PASS
2079 11:48:17.823924 TX DQ/DQS : PASS
2080 11:48:17.826675 RX DATLAT : PASS
2081 11:48:17.829915 RX DQ/DQS(Engine): PASS
2082 11:48:17.830502 TX OE : NO K
2083 11:48:17.833165 All Pass.
2084 11:48:17.833686
2085 11:48:17.834134 DramC Write-DBI off
2086 11:48:17.837085 PER_BANK_REFRESH: Hybrid Mode
2087 11:48:17.840013 TX_TRACKING: ON
2088 11:48:17.842946 [GetDramInforAfterCalByMRR] Vendor 6.
2089 11:48:17.846714 [GetDramInforAfterCalByMRR] Revision 606.
2090 11:48:17.849344 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 11:48:17.849854 MR0 0x3b3b
2092 11:48:17.850327 MR8 0x5151
2093 11:48:17.856495 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 11:48:17.856929
2095 11:48:17.857373 MR0 0x3b3b
2096 11:48:17.857805 MR8 0x5151
2097 11:48:17.859357 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 11:48:17.859793
2099 11:48:17.869975 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 11:48:17.872726 [FAST_K] Save calibration result to emmc
2101 11:48:17.876273 [FAST_K] Save calibration result to emmc
2102 11:48:17.879175 dram_init: config_dvfs: 1
2103 11:48:17.882709 dramc_set_vcore_voltage set vcore to 662500
2104 11:48:17.885953 Read voltage for 1200, 2
2105 11:48:17.886139 Vio18 = 0
2106 11:48:17.886360 Vcore = 662500
2107 11:48:17.889116 Vdram = 0
2108 11:48:17.889300 Vddq = 0
2109 11:48:17.889491 Vmddr = 0
2110 11:48:17.896323 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 11:48:17.899470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 11:48:17.902452 MEM_TYPE=3, freq_sel=15
2113 11:48:17.906731 sv_algorithm_assistance_LP4_1600
2114 11:48:17.909608 ============ PULL DRAM RESETB DOWN ============
2115 11:48:17.912581 ========== PULL DRAM RESETB DOWN end =========
2116 11:48:17.919098 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 11:48:17.922858 ===================================
2118 11:48:17.925562 LPDDR4 DRAM CONFIGURATION
2119 11:48:17.929620 ===================================
2120 11:48:17.929891 EX_ROW_EN[0] = 0x0
2121 11:48:17.932318 EX_ROW_EN[1] = 0x0
2122 11:48:17.932589 LP4Y_EN = 0x0
2123 11:48:17.936027 WORK_FSP = 0x0
2124 11:48:17.936219 WL = 0x4
2125 11:48:17.938943 RL = 0x4
2126 11:48:17.939129 BL = 0x2
2127 11:48:17.942664 RPST = 0x0
2128 11:48:17.942843 RD_PRE = 0x0
2129 11:48:17.945490 WR_PRE = 0x1
2130 11:48:17.945667 WR_PST = 0x0
2131 11:48:17.949275 DBI_WR = 0x0
2132 11:48:17.949451 DBI_RD = 0x0
2133 11:48:17.952145 OTF = 0x1
2134 11:48:17.955498 ===================================
2135 11:48:17.959296 ===================================
2136 11:48:17.959475 ANA top config
2137 11:48:17.962115 ===================================
2138 11:48:17.965985 DLL_ASYNC_EN = 0
2139 11:48:17.969161 ALL_SLAVE_EN = 0
2140 11:48:17.972704 NEW_RANK_MODE = 1
2141 11:48:17.972885 DLL_IDLE_MODE = 1
2142 11:48:17.975275 LP45_APHY_COMB_EN = 1
2143 11:48:17.978907 TX_ODT_DIS = 1
2144 11:48:17.981849 NEW_8X_MODE = 1
2145 11:48:17.985741 ===================================
2146 11:48:17.988777 ===================================
2147 11:48:17.992214 data_rate = 2400
2148 11:48:17.992367 CKR = 1
2149 11:48:17.995643 DQ_P2S_RATIO = 8
2150 11:48:17.998901 ===================================
2151 11:48:18.001890 CA_P2S_RATIO = 8
2152 11:48:18.005358 DQ_CA_OPEN = 0
2153 11:48:18.008805 DQ_SEMI_OPEN = 0
2154 11:48:18.012188 CA_SEMI_OPEN = 0
2155 11:48:18.012348 CA_FULL_RATE = 0
2156 11:48:18.016437 DQ_CKDIV4_EN = 0
2157 11:48:18.018595 CA_CKDIV4_EN = 0
2158 11:48:18.022058 CA_PREDIV_EN = 0
2159 11:48:18.025772 PH8_DLY = 17
2160 11:48:18.028723 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 11:48:18.028941 DQ_AAMCK_DIV = 4
2162 11:48:18.032102 CA_AAMCK_DIV = 4
2163 11:48:18.035534 CA_ADMCK_DIV = 4
2164 11:48:18.039208 DQ_TRACK_CA_EN = 0
2165 11:48:18.042052 CA_PICK = 1200
2166 11:48:18.045472 CA_MCKIO = 1200
2167 11:48:18.048783 MCKIO_SEMI = 0
2168 11:48:18.048893 PLL_FREQ = 2366
2169 11:48:18.051894 DQ_UI_PI_RATIO = 32
2170 11:48:18.055659 CA_UI_PI_RATIO = 0
2171 11:48:18.058389 ===================================
2172 11:48:18.061680 ===================================
2173 11:48:18.065051 memory_type:LPDDR4
2174 11:48:18.068787 GP_NUM : 10
2175 11:48:18.068871 SRAM_EN : 1
2176 11:48:18.071599 MD32_EN : 0
2177 11:48:18.075095 ===================================
2178 11:48:18.075217 [ANA_INIT] >>>>>>>>>>>>>>
2179 11:48:18.078136 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 11:48:18.081636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 11:48:18.084756 ===================================
2182 11:48:18.088860 data_rate = 2400,PCW = 0X5b00
2183 11:48:18.091614 ===================================
2184 11:48:18.094998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 11:48:18.101368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 11:48:18.108784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 11:48:18.112289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 11:48:18.115203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 11:48:18.118330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 11:48:18.122428 [ANA_INIT] flow start
2191 11:48:18.122868 [ANA_INIT] PLL >>>>>>>>
2192 11:48:18.125508 [ANA_INIT] PLL <<<<<<<<
2193 11:48:18.128829 [ANA_INIT] MIDPI >>>>>>>>
2194 11:48:18.129291 [ANA_INIT] MIDPI <<<<<<<<
2195 11:48:18.131686 [ANA_INIT] DLL >>>>>>>>
2196 11:48:18.135029 [ANA_INIT] DLL <<<<<<<<
2197 11:48:18.135443 [ANA_INIT] flow end
2198 11:48:18.142627 ============ LP4 DIFF to SE enter ============
2199 11:48:18.145131 ============ LP4 DIFF to SE exit ============
2200 11:48:18.149085 [ANA_INIT] <<<<<<<<<<<<<
2201 11:48:18.151897 [Flow] Enable top DCM control >>>>>
2202 11:48:18.155552 [Flow] Enable top DCM control <<<<<
2203 11:48:18.156057 Enable DLL master slave shuffle
2204 11:48:18.161832 ==============================================================
2205 11:48:18.165046 Gating Mode config
2206 11:48:18.167973 ==============================================================
2207 11:48:18.171320 Config description:
2208 11:48:18.181174 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 11:48:18.187977 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 11:48:18.191561 SELPH_MODE 0: By rank 1: By Phase
2211 11:48:18.198419 ==============================================================
2212 11:48:18.200997 GAT_TRACK_EN = 1
2213 11:48:18.204803 RX_GATING_MODE = 2
2214 11:48:18.207982 RX_GATING_TRACK_MODE = 2
2215 11:48:18.211227 SELPH_MODE = 1
2216 11:48:18.211657 PICG_EARLY_EN = 1
2217 11:48:18.214140 VALID_LAT_VALUE = 1
2218 11:48:18.221026 ==============================================================
2219 11:48:18.224577 Enter into Gating configuration >>>>
2220 11:48:18.227628 Exit from Gating configuration <<<<
2221 11:48:18.231502 Enter into DVFS_PRE_config >>>>>
2222 11:48:18.241083 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 11:48:18.244874 Exit from DVFS_PRE_config <<<<<
2224 11:48:18.247805 Enter into PICG configuration >>>>
2225 11:48:18.251150 Exit from PICG configuration <<<<
2226 11:48:18.254783 [RX_INPUT] configuration >>>>>
2227 11:48:18.257991 [RX_INPUT] configuration <<<<<
2228 11:48:18.261180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 11:48:18.267550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 11:48:18.274163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 11:48:18.280941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 11:48:18.287715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 11:48:18.291447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 11:48:18.297863 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 11:48:18.300781 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 11:48:18.304602 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 11:48:18.307731 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 11:48:18.314928 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 11:48:18.318333 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 11:48:18.320981 ===================================
2241 11:48:18.324261 LPDDR4 DRAM CONFIGURATION
2242 11:48:18.327689 ===================================
2243 11:48:18.328239 EX_ROW_EN[0] = 0x0
2244 11:48:18.330907 EX_ROW_EN[1] = 0x0
2245 11:48:18.331452 LP4Y_EN = 0x0
2246 11:48:18.334590 WORK_FSP = 0x0
2247 11:48:18.335151 WL = 0x4
2248 11:48:18.337352 RL = 0x4
2249 11:48:18.337895 BL = 0x2
2250 11:48:18.340967 RPST = 0x0
2251 11:48:18.341419 RD_PRE = 0x0
2252 11:48:18.344299 WR_PRE = 0x1
2253 11:48:18.344886 WR_PST = 0x0
2254 11:48:18.347897 DBI_WR = 0x0
2255 11:48:18.350932 DBI_RD = 0x0
2256 11:48:18.351475 OTF = 0x1
2257 11:48:18.354503 ===================================
2258 11:48:18.357488 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 11:48:18.360987 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 11:48:18.367137 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 11:48:18.370630 ===================================
2262 11:48:18.373796 LPDDR4 DRAM CONFIGURATION
2263 11:48:18.377543 ===================================
2264 11:48:18.378096 EX_ROW_EN[0] = 0x10
2265 11:48:18.380502 EX_ROW_EN[1] = 0x0
2266 11:48:18.381014 LP4Y_EN = 0x0
2267 11:48:18.384239 WORK_FSP = 0x0
2268 11:48:18.384783 WL = 0x4
2269 11:48:18.387089 RL = 0x4
2270 11:48:18.387543 BL = 0x2
2271 11:48:18.390765 RPST = 0x0
2272 11:48:18.391312 RD_PRE = 0x0
2273 11:48:18.393868 WR_PRE = 0x1
2274 11:48:18.394377 WR_PST = 0x0
2275 11:48:18.397098 DBI_WR = 0x0
2276 11:48:18.397643 DBI_RD = 0x0
2277 11:48:18.401247 OTF = 0x1
2278 11:48:18.403475 ===================================
2279 11:48:18.410645 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 11:48:18.411258 ==
2281 11:48:18.413791 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 11:48:18.417468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 11:48:18.418022 ==
2284 11:48:18.421049 [Duty_Offset_Calibration]
2285 11:48:18.421701 B0:2 B1:0 CA:4
2286 11:48:18.422083
2287 11:48:18.423629 [DutyScan_Calibration_Flow] k_type=0
2288 11:48:18.434679
2289 11:48:18.435191 ==CLK 0==
2290 11:48:18.437803 Final CLK duty delay cell = 0
2291 11:48:18.441233 [0] MAX Duty = 5156%(X100), DQS PI = 14
2292 11:48:18.444646 [0] MIN Duty = 4969%(X100), DQS PI = 8
2293 11:48:18.445058 [0] AVG Duty = 5062%(X100)
2294 11:48:18.447699
2295 11:48:18.450855 CH0 CLK Duty spec in!! Max-Min= 187%
2296 11:48:18.454612 [DutyScan_Calibration_Flow] ====Done====
2297 11:48:18.455020
2298 11:48:18.457478 [DutyScan_Calibration_Flow] k_type=1
2299 11:48:18.473823
2300 11:48:18.474548 ==DQS 0 ==
2301 11:48:18.477386 Final DQS duty delay cell = 0
2302 11:48:18.480218 [0] MAX Duty = 5156%(X100), DQS PI = 20
2303 11:48:18.484201 [0] MIN Duty = 5093%(X100), DQS PI = 0
2304 11:48:18.484713 [0] AVG Duty = 5124%(X100)
2305 11:48:18.486952
2306 11:48:18.487446 ==DQS 1 ==
2307 11:48:18.490389 Final DQS duty delay cell = 0
2308 11:48:18.493573 [0] MAX Duty = 5125%(X100), DQS PI = 50
2309 11:48:18.497255 [0] MIN Duty = 4969%(X100), DQS PI = 62
2310 11:48:18.500640 [0] AVG Duty = 5047%(X100)
2311 11:48:18.501447
2312 11:48:18.503263 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2313 11:48:18.503673
2314 11:48:18.506909 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 11:48:18.510360 [DutyScan_Calibration_Flow] ====Done====
2316 11:48:18.510951
2317 11:48:18.514129 [DutyScan_Calibration_Flow] k_type=3
2318 11:48:18.530380
2319 11:48:18.530886 ==DQM 0 ==
2320 11:48:18.533257 Final DQM duty delay cell = 0
2321 11:48:18.537236 [0] MAX Duty = 5125%(X100), DQS PI = 20
2322 11:48:18.540320 [0] MIN Duty = 4844%(X100), DQS PI = 52
2323 11:48:18.543197 [0] AVG Duty = 4984%(X100)
2324 11:48:18.543703
2325 11:48:18.544078 ==DQM 1 ==
2326 11:48:18.546544 Final DQM duty delay cell = 0
2327 11:48:18.549729 [0] MAX Duty = 4969%(X100), DQS PI = 2
2328 11:48:18.552942 [0] MIN Duty = 4875%(X100), DQS PI = 20
2329 11:48:18.557051 [0] AVG Duty = 4922%(X100)
2330 11:48:18.557547
2331 11:48:18.560011 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2332 11:48:18.560420
2333 11:48:18.562937 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2334 11:48:18.566556 [DutyScan_Calibration_Flow] ====Done====
2335 11:48:18.566970
2336 11:48:18.569510 [DutyScan_Calibration_Flow] k_type=2
2337 11:48:18.586814
2338 11:48:18.587387 ==DQ 0 ==
2339 11:48:18.589866 Final DQ duty delay cell = 0
2340 11:48:18.593161 [0] MAX Duty = 5125%(X100), DQS PI = 18
2341 11:48:18.596203 [0] MIN Duty = 5000%(X100), DQS PI = 4
2342 11:48:18.596611 [0] AVG Duty = 5062%(X100)
2343 11:48:18.599451
2344 11:48:18.599855 ==DQ 1 ==
2345 11:48:18.603396 Final DQ duty delay cell = 0
2346 11:48:18.606649 [0] MAX Duty = 5156%(X100), DQS PI = 4
2347 11:48:18.610614 [0] MIN Duty = 4938%(X100), DQS PI = 14
2348 11:48:18.611180 [0] AVG Duty = 5047%(X100)
2349 11:48:18.611523
2350 11:48:18.612827 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2351 11:48:18.616503
2352 11:48:18.619650 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2353 11:48:18.622471 [DutyScan_Calibration_Flow] ====Done====
2354 11:48:18.622878 ==
2355 11:48:18.626097 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 11:48:18.629155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 11:48:18.629580 ==
2358 11:48:18.632990 [Duty_Offset_Calibration]
2359 11:48:18.633396 B0:0 B1:-1 CA:3
2360 11:48:18.633717
2361 11:48:18.636420 [DutyScan_Calibration_Flow] k_type=0
2362 11:48:18.645436
2363 11:48:18.645928 ==CLK 0==
2364 11:48:18.649125 Final CLK duty delay cell = -4
2365 11:48:18.652275 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2366 11:48:18.655884 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2367 11:48:18.658649 [-4] AVG Duty = 4938%(X100)
2368 11:48:18.659129
2369 11:48:18.662375 CH1 CLK Duty spec in!! Max-Min= 124%
2370 11:48:18.665372 [DutyScan_Calibration_Flow] ====Done====
2371 11:48:18.665779
2372 11:48:18.668765 [DutyScan_Calibration_Flow] k_type=1
2373 11:48:18.685198
2374 11:48:18.685678 ==DQS 0 ==
2375 11:48:18.688299 Final DQS duty delay cell = 0
2376 11:48:18.691703 [0] MAX Duty = 5187%(X100), DQS PI = 18
2377 11:48:18.695160 [0] MIN Duty = 4938%(X100), DQS PI = 38
2378 11:48:18.698206 [0] AVG Duty = 5062%(X100)
2379 11:48:18.698771
2380 11:48:18.699110 ==DQS 1 ==
2381 11:48:18.701443 Final DQS duty delay cell = 0
2382 11:48:18.705182 [0] MAX Duty = 5156%(X100), DQS PI = 8
2383 11:48:18.708808 [0] MIN Duty = 5031%(X100), DQS PI = 18
2384 11:48:18.711311 [0] AVG Duty = 5093%(X100)
2385 11:48:18.711806
2386 11:48:18.715094 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2387 11:48:18.715507
2388 11:48:18.718062 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2389 11:48:18.721787 [DutyScan_Calibration_Flow] ====Done====
2390 11:48:18.722236
2391 11:48:18.725047 [DutyScan_Calibration_Flow] k_type=3
2392 11:48:18.741867
2393 11:48:18.742462 ==DQM 0 ==
2394 11:48:18.745232 Final DQM duty delay cell = 0
2395 11:48:18.748654 [0] MAX Duty = 5031%(X100), DQS PI = 28
2396 11:48:18.751579 [0] MIN Duty = 4813%(X100), DQS PI = 36
2397 11:48:18.755066 [0] AVG Duty = 4922%(X100)
2398 11:48:18.755545
2399 11:48:18.755911 ==DQM 1 ==
2400 11:48:18.758283 Final DQM duty delay cell = 0
2401 11:48:18.761814 [0] MAX Duty = 5000%(X100), DQS PI = 36
2402 11:48:18.764632 [0] MIN Duty = 4844%(X100), DQS PI = 0
2403 11:48:18.768500 [0] AVG Duty = 4922%(X100)
2404 11:48:18.769103
2405 11:48:18.771149 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2406 11:48:18.771610
2407 11:48:18.774707 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 11:48:18.778309 [DutyScan_Calibration_Flow] ====Done====
2409 11:48:18.778825
2410 11:48:18.780939 [DutyScan_Calibration_Flow] k_type=2
2411 11:48:18.797185
2412 11:48:18.797704 ==DQ 0 ==
2413 11:48:18.800712 Final DQ duty delay cell = -4
2414 11:48:18.803761 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2415 11:48:18.806865 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2416 11:48:18.810653 [-4] AVG Duty = 4922%(X100)
2417 11:48:18.811076
2418 11:48:18.811412 ==DQ 1 ==
2419 11:48:18.813961 Final DQ duty delay cell = 0
2420 11:48:18.817076 [0] MAX Duty = 5031%(X100), DQS PI = 34
2421 11:48:18.820483 [0] MIN Duty = 4844%(X100), DQS PI = 62
2422 11:48:18.823610 [0] AVG Duty = 4937%(X100)
2423 11:48:18.824063
2424 11:48:18.827189 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 11:48:18.827603
2426 11:48:18.830479 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2427 11:48:18.834173 [DutyScan_Calibration_Flow] ====Done====
2428 11:48:18.837249 nWR fixed to 30
2429 11:48:18.840312 [ModeRegInit_LP4] CH0 RK0
2430 11:48:18.840722 [ModeRegInit_LP4] CH0 RK1
2431 11:48:18.843809 [ModeRegInit_LP4] CH1 RK0
2432 11:48:18.847115 [ModeRegInit_LP4] CH1 RK1
2433 11:48:18.847526 match AC timing 7
2434 11:48:18.853918 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 11:48:18.857014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 11:48:18.860603 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 11:48:18.867096 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 11:48:18.870357 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 11:48:18.870790 ==
2440 11:48:18.874032 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 11:48:18.876830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 11:48:18.877246 ==
2443 11:48:18.883351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 11:48:18.889841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 11:48:18.897558 [CA 0] Center 39 (9~70) winsize 62
2446 11:48:18.901353 [CA 1] Center 39 (9~69) winsize 61
2447 11:48:18.904801 [CA 2] Center 35 (5~66) winsize 62
2448 11:48:18.907860 [CA 3] Center 35 (5~66) winsize 62
2449 11:48:18.911727 [CA 4] Center 33 (3~64) winsize 62
2450 11:48:18.914803 [CA 5] Center 33 (3~64) winsize 62
2451 11:48:18.915313
2452 11:48:18.917561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2453 11:48:18.917972
2454 11:48:18.920755 [CATrainingPosCal] consider 1 rank data
2455 11:48:18.924608 u2DelayCellTimex100 = 270/100 ps
2456 11:48:18.927095 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2457 11:48:18.933959 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2458 11:48:18.937117 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 11:48:18.940654 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2460 11:48:18.944022 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2461 11:48:18.947392 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2462 11:48:18.947874
2463 11:48:18.950408 CA PerBit enable=1, Macro0, CA PI delay=33
2464 11:48:18.950822
2465 11:48:18.953993 [CBTSetCACLKResult] CA Dly = 33
2466 11:48:18.957215 CS Dly: 7 (0~38)
2467 11:48:18.957801 ==
2468 11:48:18.960442 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 11:48:18.963652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 11:48:18.964107 ==
2471 11:48:18.970440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 11:48:18.973606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 11:48:18.983255 [CA 0] Center 39 (9~70) winsize 62
2474 11:48:18.987030 [CA 1] Center 39 (9~70) winsize 62
2475 11:48:18.990125 [CA 2] Center 35 (5~66) winsize 62
2476 11:48:18.993400 [CA 3] Center 35 (5~66) winsize 62
2477 11:48:18.996807 [CA 4] Center 34 (4~65) winsize 62
2478 11:48:19.000490 [CA 5] Center 33 (3~64) winsize 62
2479 11:48:19.000908
2480 11:48:19.003156 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2481 11:48:19.003565
2482 11:48:19.006946 [CATrainingPosCal] consider 2 rank data
2483 11:48:19.009980 u2DelayCellTimex100 = 270/100 ps
2484 11:48:19.013682 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 11:48:19.019811 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2486 11:48:19.023135 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 11:48:19.026386 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 11:48:19.030219 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2489 11:48:19.033791 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2490 11:48:19.034380
2491 11:48:19.036547 CA PerBit enable=1, Macro0, CA PI delay=33
2492 11:48:19.037143
2493 11:48:19.039943 [CBTSetCACLKResult] CA Dly = 33
2494 11:48:19.040447 CS Dly: 8 (0~41)
2495 11:48:19.043081
2496 11:48:19.046778 ----->DramcWriteLeveling(PI) begin...
2497 11:48:19.047291 ==
2498 11:48:19.050073 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 11:48:19.052680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 11:48:19.053094 ==
2501 11:48:19.056459 Write leveling (Byte 0): 31 => 31
2502 11:48:19.059935 Write leveling (Byte 1): 27 => 27
2503 11:48:19.062829 DramcWriteLeveling(PI) end<-----
2504 11:48:19.063351
2505 11:48:19.063924 ==
2506 11:48:19.066192 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 11:48:19.069850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 11:48:19.070437 ==
2509 11:48:19.072796 [Gating] SW mode calibration
2510 11:48:19.079331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 11:48:19.086331 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 11:48:19.089592 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2513 11:48:19.093577 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2514 11:48:19.099789 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 11:48:19.103065 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 11:48:19.106041 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 11:48:19.113144 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 11:48:19.115731 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2519 11:48:19.119265 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2520 11:48:19.126046 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2521 11:48:19.129687 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2522 11:48:19.132453 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 11:48:19.139229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 11:48:19.142629 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 11:48:19.145826 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 11:48:19.152186 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2527 11:48:19.155498 1 0 28 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
2528 11:48:19.159032 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2529 11:48:19.165558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 11:48:19.168785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 11:48:19.172084 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 11:48:19.175707 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 11:48:19.182343 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 11:48:19.185704 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 11:48:19.189646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 11:48:19.195483 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 11:48:19.199010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 11:48:19.202318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 11:48:19.209445 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 11:48:19.211762 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 11:48:19.214991 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 11:48:19.221650 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 11:48:19.225145 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:48:19.228785 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:48:19.235816 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:48:19.238868 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:48:19.242132 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:48:19.248638 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:48:19.251915 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:48:19.254910 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:48:19.261708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2552 11:48:19.262171 Total UI for P1: 0, mck2ui 16
2553 11:48:19.268031 best dqsien dly found for B0: ( 1, 3, 26)
2554 11:48:19.271640 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 11:48:19.274797 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 11:48:19.278059 Total UI for P1: 0, mck2ui 16
2557 11:48:19.281565 best dqsien dly found for B1: ( 1, 3, 30)
2558 11:48:19.285306 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2559 11:48:19.288584 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2560 11:48:19.289090
2561 11:48:19.294777 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2562 11:48:19.297830 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2563 11:48:19.298245 [Gating] SW calibration Done
2564 11:48:19.301588 ==
2565 11:48:19.305298 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 11:48:19.309215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 11:48:19.309738 ==
2568 11:48:19.310069 RX Vref Scan: 0
2569 11:48:19.310450
2570 11:48:19.311305 RX Vref 0 -> 0, step: 1
2571 11:48:19.311740
2572 11:48:19.314672 RX Delay -40 -> 252, step: 8
2573 11:48:19.318480 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 11:48:19.321703 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2575 11:48:19.327830 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 11:48:19.331393 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2577 11:48:19.334542 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2578 11:48:19.337661 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2579 11:48:19.340771 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 11:48:19.347725 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2581 11:48:19.351444 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2582 11:48:19.354733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2583 11:48:19.358395 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2584 11:48:19.360871 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2585 11:48:19.367692 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2586 11:48:19.371365 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2587 11:48:19.374064 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2588 11:48:19.377274 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2589 11:48:19.377694 ==
2590 11:48:19.380535 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 11:48:19.387489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 11:48:19.387905 ==
2593 11:48:19.388234 DQS Delay:
2594 11:48:19.388538 DQS0 = 0, DQS1 = 0
2595 11:48:19.390636 DQM Delay:
2596 11:48:19.391080 DQM0 = 119, DQM1 = 107
2597 11:48:19.394316 DQ Delay:
2598 11:48:19.397028 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2599 11:48:19.401002 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2600 11:48:19.404147 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2601 11:48:19.407519 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2602 11:48:19.408050
2603 11:48:19.408499
2604 11:48:19.408913 ==
2605 11:48:19.410361 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 11:48:19.414153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 11:48:19.414746 ==
2608 11:48:19.417342
2609 11:48:19.417848
2610 11:48:19.418180 TX Vref Scan disable
2611 11:48:19.420535 == TX Byte 0 ==
2612 11:48:19.423638 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2613 11:48:19.427475 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2614 11:48:19.430798 == TX Byte 1 ==
2615 11:48:19.433711 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2616 11:48:19.437396 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2617 11:48:19.437881 ==
2618 11:48:19.440525 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 11:48:19.447213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 11:48:19.447693 ==
2621 11:48:19.458467 TX Vref=22, minBit 10, minWin=24, winSum=406
2622 11:48:19.461344 TX Vref=24, minBit 10, minWin=24, winSum=413
2623 11:48:19.464639 TX Vref=26, minBit 4, minWin=25, winSum=422
2624 11:48:19.468019 TX Vref=28, minBit 1, minWin=26, winSum=426
2625 11:48:19.470884 TX Vref=30, minBit 0, minWin=26, winSum=428
2626 11:48:19.477836 TX Vref=32, minBit 3, minWin=26, winSum=425
2627 11:48:19.481416 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2628 11:48:19.481985
2629 11:48:19.484892 Final TX Range 1 Vref 30
2630 11:48:19.485463
2631 11:48:19.485953 ==
2632 11:48:19.487979 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 11:48:19.491249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 11:48:19.494439 ==
2635 11:48:19.495005
2636 11:48:19.495487
2637 11:48:19.495945 TX Vref Scan disable
2638 11:48:19.498605 == TX Byte 0 ==
2639 11:48:19.501599 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2640 11:48:19.508197 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2641 11:48:19.508821 == TX Byte 1 ==
2642 11:48:19.511224 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 11:48:19.518793 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 11:48:19.519361
2645 11:48:19.519852 [DATLAT]
2646 11:48:19.520312 Freq=1200, CH0 RK0
2647 11:48:19.520762
2648 11:48:19.521564 DATLAT Default: 0xd
2649 11:48:19.521958 0, 0xFFFF, sum = 0
2650 11:48:19.524586 1, 0xFFFF, sum = 0
2651 11:48:19.528309 2, 0xFFFF, sum = 0
2652 11:48:19.528880 3, 0xFFFF, sum = 0
2653 11:48:19.531353 4, 0xFFFF, sum = 0
2654 11:48:19.531835 5, 0xFFFF, sum = 0
2655 11:48:19.534894 6, 0xFFFF, sum = 0
2656 11:48:19.535375 7, 0xFFFF, sum = 0
2657 11:48:19.537765 8, 0xFFFF, sum = 0
2658 11:48:19.538315 9, 0xFFFF, sum = 0
2659 11:48:19.541372 10, 0xFFFF, sum = 0
2660 11:48:19.541943 11, 0xFFFF, sum = 0
2661 11:48:19.544661 12, 0x0, sum = 1
2662 11:48:19.545234 13, 0x0, sum = 2
2663 11:48:19.548143 14, 0x0, sum = 3
2664 11:48:19.548698 15, 0x0, sum = 4
2665 11:48:19.551113 best_step = 13
2666 11:48:19.551664
2667 11:48:19.552034 ==
2668 11:48:19.554559 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 11:48:19.557849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 11:48:19.558460 ==
2671 11:48:19.558840 RX Vref Scan: 1
2672 11:48:19.561432
2673 11:48:19.561988 Set Vref Range= 32 -> 127
2674 11:48:19.562438
2675 11:48:19.564333 RX Vref 32 -> 127, step: 1
2676 11:48:19.564796
2677 11:48:19.568079 RX Delay -21 -> 252, step: 4
2678 11:48:19.568545
2679 11:48:19.571521 Set Vref, RX VrefLevel [Byte0]: 32
2680 11:48:19.574532 [Byte1]: 32
2681 11:48:19.574997
2682 11:48:19.578596 Set Vref, RX VrefLevel [Byte0]: 33
2683 11:48:19.580818 [Byte1]: 33
2684 11:48:19.584851
2685 11:48:19.585399 Set Vref, RX VrefLevel [Byte0]: 34
2686 11:48:19.587578 [Byte1]: 34
2687 11:48:19.592433
2688 11:48:19.593026 Set Vref, RX VrefLevel [Byte0]: 35
2689 11:48:19.596392 [Byte1]: 35
2690 11:48:19.600496
2691 11:48:19.601042 Set Vref, RX VrefLevel [Byte0]: 36
2692 11:48:19.603565 [Byte1]: 36
2693 11:48:19.608613
2694 11:48:19.609154 Set Vref, RX VrefLevel [Byte0]: 37
2695 11:48:19.611544 [Byte1]: 37
2696 11:48:19.616167
2697 11:48:19.616918 Set Vref, RX VrefLevel [Byte0]: 38
2698 11:48:19.619456 [Byte1]: 38
2699 11:48:19.624325
2700 11:48:19.624872 Set Vref, RX VrefLevel [Byte0]: 39
2701 11:48:19.628173 [Byte1]: 39
2702 11:48:19.632014
2703 11:48:19.632565 Set Vref, RX VrefLevel [Byte0]: 40
2704 11:48:19.635778 [Byte1]: 40
2705 11:48:19.640243
2706 11:48:19.640790 Set Vref, RX VrefLevel [Byte0]: 41
2707 11:48:19.643902 [Byte1]: 41
2708 11:48:19.649172
2709 11:48:19.649718 Set Vref, RX VrefLevel [Byte0]: 42
2710 11:48:19.650900 [Byte1]: 42
2711 11:48:19.655873
2712 11:48:19.656421 Set Vref, RX VrefLevel [Byte0]: 43
2713 11:48:19.659483 [Byte1]: 43
2714 11:48:19.663800
2715 11:48:19.664358 Set Vref, RX VrefLevel [Byte0]: 44
2716 11:48:19.666909 [Byte1]: 44
2717 11:48:19.671883
2718 11:48:19.672350 Set Vref, RX VrefLevel [Byte0]: 45
2719 11:48:19.675139 [Byte1]: 45
2720 11:48:19.679401
2721 11:48:19.679809 Set Vref, RX VrefLevel [Byte0]: 46
2722 11:48:19.682978 [Byte1]: 46
2723 11:48:19.687416
2724 11:48:19.687829 Set Vref, RX VrefLevel [Byte0]: 47
2725 11:48:19.691185 [Byte1]: 47
2726 11:48:19.695679
2727 11:48:19.696187 Set Vref, RX VrefLevel [Byte0]: 48
2728 11:48:19.698577 [Byte1]: 48
2729 11:48:19.703537
2730 11:48:19.706465 Set Vref, RX VrefLevel [Byte0]: 49
2731 11:48:19.706883 [Byte1]: 49
2732 11:48:19.711100
2733 11:48:19.711514 Set Vref, RX VrefLevel [Byte0]: 50
2734 11:48:19.715218 [Byte1]: 50
2735 11:48:19.718942
2736 11:48:19.719419 Set Vref, RX VrefLevel [Byte0]: 51
2737 11:48:19.722635 [Byte1]: 51
2738 11:48:19.726835
2739 11:48:19.727247 Set Vref, RX VrefLevel [Byte0]: 52
2740 11:48:19.730764 [Byte1]: 52
2741 11:48:19.735518
2742 11:48:19.736024 Set Vref, RX VrefLevel [Byte0]: 53
2743 11:48:19.738717 [Byte1]: 53
2744 11:48:19.743057
2745 11:48:19.743571 Set Vref, RX VrefLevel [Byte0]: 54
2746 11:48:19.746436 [Byte1]: 54
2747 11:48:19.751301
2748 11:48:19.751810 Set Vref, RX VrefLevel [Byte0]: 55
2749 11:48:19.754326 [Byte1]: 55
2750 11:48:19.759359
2751 11:48:19.759864 Set Vref, RX VrefLevel [Byte0]: 56
2752 11:48:19.762204 [Byte1]: 56
2753 11:48:19.766823
2754 11:48:19.767331 Set Vref, RX VrefLevel [Byte0]: 57
2755 11:48:19.769828 [Byte1]: 57
2756 11:48:19.774657
2757 11:48:19.775166 Set Vref, RX VrefLevel [Byte0]: 58
2758 11:48:19.778327 [Byte1]: 58
2759 11:48:19.782806
2760 11:48:19.783368 Set Vref, RX VrefLevel [Byte0]: 59
2761 11:48:19.785764 [Byte1]: 59
2762 11:48:19.790723
2763 11:48:19.791227 Set Vref, RX VrefLevel [Byte0]: 60
2764 11:48:19.794084 [Byte1]: 60
2765 11:48:19.798360
2766 11:48:19.798877 Set Vref, RX VrefLevel [Byte0]: 61
2767 11:48:19.804691 [Byte1]: 61
2768 11:48:19.805203
2769 11:48:19.808085 Set Vref, RX VrefLevel [Byte0]: 62
2770 11:48:19.812032 [Byte1]: 62
2771 11:48:19.812442
2772 11:48:19.814748 Set Vref, RX VrefLevel [Byte0]: 63
2773 11:48:19.818587 [Byte1]: 63
2774 11:48:19.822316
2775 11:48:19.822730 Set Vref, RX VrefLevel [Byte0]: 64
2776 11:48:19.825654 [Byte1]: 64
2777 11:48:19.830633
2778 11:48:19.831141 Set Vref, RX VrefLevel [Byte0]: 65
2779 11:48:19.833490 [Byte1]: 65
2780 11:48:19.838150
2781 11:48:19.838706 Set Vref, RX VrefLevel [Byte0]: 66
2782 11:48:19.841271 [Byte1]: 66
2783 11:48:19.846084
2784 11:48:19.846629 Set Vref, RX VrefLevel [Byte0]: 67
2785 11:48:19.849231 [Byte1]: 67
2786 11:48:19.854070
2787 11:48:19.854618 Set Vref, RX VrefLevel [Byte0]: 68
2788 11:48:19.857102 [Byte1]: 68
2789 11:48:19.862420
2790 11:48:19.862930 Final RX Vref Byte 0 = 55 to rank0
2791 11:48:19.866101 Final RX Vref Byte 1 = 50 to rank0
2792 11:48:19.868647 Final RX Vref Byte 0 = 55 to rank1
2793 11:48:19.871514 Final RX Vref Byte 1 = 50 to rank1==
2794 11:48:19.875098 Dram Type= 6, Freq= 0, CH_0, rank 0
2795 11:48:19.881921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2796 11:48:19.882461 ==
2797 11:48:19.882799 DQS Delay:
2798 11:48:19.883143 DQS0 = 0, DQS1 = 0
2799 11:48:19.885607 DQM Delay:
2800 11:48:19.886438 DQM0 = 119, DQM1 = 105
2801 11:48:19.888541 DQ Delay:
2802 11:48:19.891932 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2803 11:48:19.895195 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2804 11:48:19.898345 DQ8 =96, DQ9 =92, DQ10 =104, DQ11 =100
2805 11:48:19.902108 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2806 11:48:19.902567
2807 11:48:19.902948
2808 11:48:19.911543 [DQSOSCAuto] RK0, (LSB)MR18= 0xfef9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2809 11:48:19.911991 CH0 RK0: MR19=303, MR18=FEF9
2810 11:48:19.918608 CH0_RK0: MR19=0x303, MR18=0xFEF9, DQSOSC=410, MR23=63, INC=39, DEC=26
2811 11:48:19.919309
2812 11:48:19.921356 ----->DramcWriteLeveling(PI) begin...
2813 11:48:19.921817 ==
2814 11:48:19.924589 Dram Type= 6, Freq= 0, CH_0, rank 1
2815 11:48:19.931110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 11:48:19.931533 ==
2817 11:48:19.934519 Write leveling (Byte 0): 33 => 33
2818 11:48:19.937642 Write leveling (Byte 1): 26 => 26
2819 11:48:19.938068 DramcWriteLeveling(PI) end<-----
2820 11:48:19.938492
2821 11:48:19.941157 ==
2822 11:48:19.944446 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 11:48:19.947750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 11:48:19.948169 ==
2825 11:48:19.951176 [Gating] SW mode calibration
2826 11:48:19.957779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2827 11:48:19.961313 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2828 11:48:19.967596 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
2829 11:48:19.970862 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 11:48:19.974588 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 11:48:19.981304 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 11:48:19.984080 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 11:48:19.987612 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2834 11:48:19.994885 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2835 11:48:19.998231 0 15 28 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (1 1)
2836 11:48:20.001359 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
2837 11:48:20.007473 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 11:48:20.011334 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 11:48:20.014013 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 11:48:20.021335 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 11:48:20.023855 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 11:48:20.027238 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2843 11:48:20.034833 1 0 28 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2844 11:48:20.037145 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 11:48:20.040691 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 11:48:20.047364 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 11:48:20.050481 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 11:48:20.054363 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 11:48:20.061230 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 11:48:20.064098 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2851 11:48:20.067068 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2852 11:48:20.071157 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 11:48:20.077134 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 11:48:20.080245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 11:48:20.083894 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 11:48:20.090855 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 11:48:20.094013 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 11:48:20.097558 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 11:48:20.104001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 11:48:20.107165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 11:48:20.110694 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 11:48:20.117062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:48:20.120556 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:48:20.123340 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:48:20.130802 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:48:20.133597 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2867 11:48:20.137131 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2868 11:48:20.140536 Total UI for P1: 0, mck2ui 16
2869 11:48:20.143746 best dqsien dly found for B0: ( 1, 3, 24)
2870 11:48:20.150554 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2871 11:48:20.153638 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:48:20.157211 Total UI for P1: 0, mck2ui 16
2873 11:48:20.160445 best dqsien dly found for B1: ( 1, 3, 30)
2874 11:48:20.163795 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2875 11:48:20.167005 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2876 11:48:20.167557
2877 11:48:20.169804 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2878 11:48:20.173847 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2879 11:48:20.176670 [Gating] SW calibration Done
2880 11:48:20.177221 ==
2881 11:48:20.179958 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 11:48:20.183487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 11:48:20.186379 ==
2884 11:48:20.186853 RX Vref Scan: 0
2885 11:48:20.187215
2886 11:48:20.190562 RX Vref 0 -> 0, step: 1
2887 11:48:20.191111
2888 11:48:20.193279 RX Delay -40 -> 252, step: 8
2889 11:48:20.196305 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2890 11:48:20.199790 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2891 11:48:20.203174 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2892 11:48:20.206073 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2893 11:48:20.213513 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2894 11:48:20.216389 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2895 11:48:20.219460 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2896 11:48:20.223419 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2897 11:48:20.226455 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2898 11:48:20.233367 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2899 11:48:20.236889 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2900 11:48:20.239176 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2901 11:48:20.242905 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2902 11:48:20.246459 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2903 11:48:20.252681 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2904 11:48:20.256561 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2905 11:48:20.257116 ==
2906 11:48:20.259108 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 11:48:20.262970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 11:48:20.263524 ==
2909 11:48:20.265702 DQS Delay:
2910 11:48:20.266292 DQS0 = 0, DQS1 = 0
2911 11:48:20.266711 DQM Delay:
2912 11:48:20.269512 DQM0 = 118, DQM1 = 106
2913 11:48:20.269994 DQ Delay:
2914 11:48:20.272604 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2915 11:48:20.276036 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2916 11:48:20.282908 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2917 11:48:20.286045 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2918 11:48:20.286658
2919 11:48:20.287035
2920 11:48:20.287375 ==
2921 11:48:20.289002 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 11:48:20.292597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 11:48:20.293152 ==
2924 11:48:20.293522
2925 11:48:20.293860
2926 11:48:20.295378 TX Vref Scan disable
2927 11:48:20.299163 == TX Byte 0 ==
2928 11:48:20.302634 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2929 11:48:20.305809 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2930 11:48:20.308902 == TX Byte 1 ==
2931 11:48:20.312017 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2932 11:48:20.315470 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2933 11:48:20.315934 ==
2934 11:48:20.318973 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 11:48:20.322026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 11:48:20.326057 ==
2937 11:48:20.335690 TX Vref=22, minBit 13, minWin=25, winSum=417
2938 11:48:20.339980 TX Vref=24, minBit 1, minWin=26, winSum=421
2939 11:48:20.342851 TX Vref=26, minBit 13, minWin=25, winSum=428
2940 11:48:20.346015 TX Vref=28, minBit 14, minWin=25, winSum=428
2941 11:48:20.349416 TX Vref=30, minBit 12, minWin=26, winSum=430
2942 11:48:20.356322 TX Vref=32, minBit 12, minWin=26, winSum=429
2943 11:48:20.359277 [TxChooseVref] Worse bit 12, Min win 26, Win sum 430, Final Vref 30
2944 11:48:20.359830
2945 11:48:20.362553 Final TX Range 1 Vref 30
2946 11:48:20.363110
2947 11:48:20.363477 ==
2948 11:48:20.366121 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 11:48:20.372515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 11:48:20.372986 ==
2951 11:48:20.373625
2952 11:48:20.374007
2953 11:48:20.374386 TX Vref Scan disable
2954 11:48:20.376301 == TX Byte 0 ==
2955 11:48:20.379548 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2956 11:48:20.382751 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2957 11:48:20.386315 == TX Byte 1 ==
2958 11:48:20.389764 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2959 11:48:20.396111 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2960 11:48:20.396698
2961 11:48:20.397072 [DATLAT]
2962 11:48:20.397413 Freq=1200, CH0 RK1
2963 11:48:20.397738
2964 11:48:20.400053 DATLAT Default: 0xd
2965 11:48:20.400599 0, 0xFFFF, sum = 0
2966 11:48:20.402460 1, 0xFFFF, sum = 0
2967 11:48:20.402931 2, 0xFFFF, sum = 0
2968 11:48:20.406117 3, 0xFFFF, sum = 0
2969 11:48:20.409396 4, 0xFFFF, sum = 0
2970 11:48:20.409949 5, 0xFFFF, sum = 0
2971 11:48:20.412607 6, 0xFFFF, sum = 0
2972 11:48:20.413074 7, 0xFFFF, sum = 0
2973 11:48:20.416145 8, 0xFFFF, sum = 0
2974 11:48:20.416698 9, 0xFFFF, sum = 0
2975 11:48:20.420005 10, 0xFFFF, sum = 0
2976 11:48:20.420567 11, 0xFFFF, sum = 0
2977 11:48:20.422823 12, 0x0, sum = 1
2978 11:48:20.423291 13, 0x0, sum = 2
2979 11:48:20.425862 14, 0x0, sum = 3
2980 11:48:20.426423 15, 0x0, sum = 4
2981 11:48:20.426806 best_step = 13
2982 11:48:20.429865
2983 11:48:20.430473 ==
2984 11:48:20.432679 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 11:48:20.436262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 11:48:20.436818 ==
2987 11:48:20.437194 RX Vref Scan: 0
2988 11:48:20.437532
2989 11:48:20.439507 RX Vref 0 -> 0, step: 1
2990 11:48:20.440061
2991 11:48:20.442448 RX Delay -21 -> 252, step: 4
2992 11:48:20.446101 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2993 11:48:20.452836 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
2994 11:48:20.455722 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
2995 11:48:20.459009 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
2996 11:48:20.462483 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
2997 11:48:20.465473 iDelay=195, Bit 5, Center 112 (51 ~ 174) 124
2998 11:48:20.472363 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
2999 11:48:20.475394 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3000 11:48:20.478942 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3001 11:48:20.482401 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3002 11:48:20.485118 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3003 11:48:20.492076 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3004 11:48:20.496210 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3005 11:48:20.498625 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3006 11:48:20.502189 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3007 11:48:20.508518 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3008 11:48:20.508984 ==
3009 11:48:20.512081 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:48:20.515703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:48:20.516138 ==
3012 11:48:20.516581 DQS Delay:
3013 11:48:20.518795 DQS0 = 0, DQS1 = 0
3014 11:48:20.519227 DQM Delay:
3015 11:48:20.521738 DQM0 = 118, DQM1 = 107
3016 11:48:20.522168 DQ Delay:
3017 11:48:20.524918 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3018 11:48:20.528345 DQ4 =122, DQ5 =112, DQ6 =128, DQ7 =124
3019 11:48:20.531640 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3020 11:48:20.535481 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =116
3021 11:48:20.535915
3022 11:48:20.536358
3023 11:48:20.545239 [DQSOSCAuto] RK1, (LSB)MR18= 0xfcfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3024 11:48:20.547994 CH0 RK1: MR19=303, MR18=FCFA
3025 11:48:20.551888 CH0_RK1: MR19=0x303, MR18=0xFCFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3026 11:48:20.555686 [RxdqsGatingPostProcess] freq 1200
3027 11:48:20.561711 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3028 11:48:20.565377 best DQS0 dly(2T, 0.5T) = (0, 11)
3029 11:48:20.568321 best DQS1 dly(2T, 0.5T) = (0, 11)
3030 11:48:20.572037 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3031 11:48:20.575239 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3032 11:48:20.578171 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 11:48:20.581329 best DQS1 dly(2T, 0.5T) = (0, 11)
3034 11:48:20.585279 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 11:48:20.587899 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3036 11:48:20.591070 Pre-setting of DQS Precalculation
3037 11:48:20.594725 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3038 11:48:20.595255 ==
3039 11:48:20.597785 Dram Type= 6, Freq= 0, CH_1, rank 0
3040 11:48:20.601765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 11:48:20.602201 ==
3042 11:48:20.607939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3043 11:48:20.614733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3044 11:48:20.622504 [CA 0] Center 38 (8~68) winsize 61
3045 11:48:20.625909 [CA 1] Center 37 (7~68) winsize 62
3046 11:48:20.629587 [CA 2] Center 35 (5~65) winsize 61
3047 11:48:20.632523 [CA 3] Center 34 (4~64) winsize 61
3048 11:48:20.635890 [CA 4] Center 34 (5~64) winsize 60
3049 11:48:20.638958 [CA 5] Center 33 (3~63) winsize 61
3050 11:48:20.639393
3051 11:48:20.642812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3052 11:48:20.643336
3053 11:48:20.645510 [CATrainingPosCal] consider 1 rank data
3054 11:48:20.649038 u2DelayCellTimex100 = 270/100 ps
3055 11:48:20.652476 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3056 11:48:20.659597 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3057 11:48:20.662628 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3058 11:48:20.665536 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3059 11:48:20.668928 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3060 11:48:20.672086 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3061 11:48:20.672630
3062 11:48:20.675805 CA PerBit enable=1, Macro0, CA PI delay=33
3063 11:48:20.676221
3064 11:48:20.678841 [CBTSetCACLKResult] CA Dly = 33
3065 11:48:20.679253 CS Dly: 5 (0~36)
3066 11:48:20.683055 ==
3067 11:48:20.685261 Dram Type= 6, Freq= 0, CH_1, rank 1
3068 11:48:20.689090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 11:48:20.689610 ==
3070 11:48:20.692582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 11:48:20.698827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3072 11:48:20.708461 [CA 0] Center 37 (7~68) winsize 62
3073 11:48:20.711694 [CA 1] Center 38 (8~68) winsize 61
3074 11:48:20.715131 [CA 2] Center 34 (4~65) winsize 62
3075 11:48:20.718194 [CA 3] Center 33 (3~64) winsize 62
3076 11:48:20.721208 [CA 4] Center 34 (4~64) winsize 61
3077 11:48:20.725369 [CA 5] Center 33 (3~63) winsize 61
3078 11:48:20.725920
3079 11:48:20.728272 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3080 11:48:20.728751
3081 11:48:20.731264 [CATrainingPosCal] consider 2 rank data
3082 11:48:20.735072 u2DelayCellTimex100 = 270/100 ps
3083 11:48:20.738204 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3084 11:48:20.744868 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3085 11:48:20.748052 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3086 11:48:20.751221 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 11:48:20.754748 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3088 11:48:20.758506 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3089 11:48:20.759064
3090 11:48:20.761471 CA PerBit enable=1, Macro0, CA PI delay=33
3091 11:48:20.762023
3092 11:48:20.764844 [CBTSetCACLKResult] CA Dly = 33
3093 11:48:20.765396 CS Dly: 6 (0~39)
3094 11:48:20.768067
3095 11:48:20.771603 ----->DramcWriteLeveling(PI) begin...
3096 11:48:20.772159 ==
3097 11:48:20.774232 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 11:48:20.777830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 11:48:20.778337 ==
3100 11:48:20.781384 Write leveling (Byte 0): 25 => 25
3101 11:48:20.784484 Write leveling (Byte 1): 27 => 27
3102 11:48:20.788126 DramcWriteLeveling(PI) end<-----
3103 11:48:20.788650
3104 11:48:20.788989 ==
3105 11:48:20.790785 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 11:48:20.794389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 11:48:20.794899 ==
3108 11:48:20.797822 [Gating] SW mode calibration
3109 11:48:20.804642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3110 11:48:20.810851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3111 11:48:20.814119 0 15 0 | B1->B0 | 2e2e 3434 | 1 0 | (0 0) (0 0)
3112 11:48:20.817362 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 11:48:20.824631 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 11:48:20.827315 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 11:48:20.830498 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 11:48:20.837586 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 11:48:20.841031 0 15 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
3118 11:48:20.844506 0 15 28 | B1->B0 | 2c2c 2727 | 1 1 | (1 1) (1 0)
3119 11:48:20.851168 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3120 11:48:20.854142 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 11:48:20.857561 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 11:48:20.863777 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 11:48:20.867369 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 11:48:20.870921 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 11:48:20.877114 1 0 24 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
3126 11:48:20.881167 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3127 11:48:20.883832 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 11:48:20.887221 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 11:48:20.893769 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 11:48:20.897341 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 11:48:20.900285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 11:48:20.906866 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 11:48:20.910736 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 11:48:20.913349 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3135 11:48:20.920022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 11:48:20.923294 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 11:48:20.926946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 11:48:20.933827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 11:48:20.936508 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 11:48:20.940313 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 11:48:20.946737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 11:48:20.949803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 11:48:20.953178 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:48:20.959575 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:48:20.962918 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:48:20.966202 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:48:20.973199 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:48:20.976366 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:48:20.979918 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3150 11:48:20.986206 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3151 11:48:20.989197 Total UI for P1: 0, mck2ui 16
3152 11:48:20.993315 best dqsien dly found for B1: ( 1, 3, 26)
3153 11:48:20.996652 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:48:20.999197 Total UI for P1: 0, mck2ui 16
3155 11:48:21.002819 best dqsien dly found for B0: ( 1, 3, 26)
3156 11:48:21.005768 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3157 11:48:21.009318 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3158 11:48:21.009853
3159 11:48:21.012848 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3160 11:48:21.015754 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3161 11:48:21.019270 [Gating] SW calibration Done
3162 11:48:21.019688 ==
3163 11:48:21.022323 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 11:48:21.029162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 11:48:21.029668 ==
3166 11:48:21.030049 RX Vref Scan: 0
3167 11:48:21.030445
3168 11:48:21.032610 RX Vref 0 -> 0, step: 1
3169 11:48:21.033152
3170 11:48:21.035994 RX Delay -40 -> 252, step: 8
3171 11:48:21.039725 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3172 11:48:21.042198 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3173 11:48:21.046293 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3174 11:48:21.049161 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3175 11:48:21.055889 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3176 11:48:21.059221 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3177 11:48:21.062647 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3178 11:48:21.065710 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3179 11:48:21.068963 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3180 11:48:21.075396 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3181 11:48:21.078785 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3182 11:48:21.081799 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3183 11:48:21.084952 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3184 11:48:21.092071 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3185 11:48:21.095552 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3186 11:48:21.098945 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3187 11:48:21.099367 ==
3188 11:48:21.102181 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 11:48:21.105793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 11:48:21.106215 ==
3191 11:48:21.108407 DQS Delay:
3192 11:48:21.108823 DQS0 = 0, DQS1 = 0
3193 11:48:21.112089 DQM Delay:
3194 11:48:21.112606 DQM0 = 115, DQM1 = 113
3195 11:48:21.112945 DQ Delay:
3196 11:48:21.115424 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3197 11:48:21.122079 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3198 11:48:21.124961 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3199 11:48:21.128341 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3200 11:48:21.128761
3201 11:48:21.129091
3202 11:48:21.129395 ==
3203 11:48:21.132448 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 11:48:21.135502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 11:48:21.135926 ==
3206 11:48:21.136259
3207 11:48:21.136659
3208 11:48:21.138143 TX Vref Scan disable
3209 11:48:21.141868 == TX Byte 0 ==
3210 11:48:21.145281 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3211 11:48:21.148357 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3212 11:48:21.152490 == TX Byte 1 ==
3213 11:48:21.154915 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3214 11:48:21.158693 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3215 11:48:21.159238 ==
3216 11:48:21.161528 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 11:48:21.165717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 11:48:21.168249 ==
3219 11:48:21.177842 TX Vref=22, minBit 9, minWin=23, winSum=408
3220 11:48:21.181228 TX Vref=24, minBit 9, minWin=23, winSum=413
3221 11:48:21.184862 TX Vref=26, minBit 9, minWin=24, winSum=418
3222 11:48:21.188286 TX Vref=28, minBit 9, minWin=25, winSum=425
3223 11:48:21.191824 TX Vref=30, minBit 9, minWin=25, winSum=424
3224 11:48:21.195133 TX Vref=32, minBit 9, minWin=25, winSum=425
3225 11:48:21.201195 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3226 11:48:21.201816
3227 11:48:21.204637 Final TX Range 1 Vref 28
3228 11:48:21.205261
3229 11:48:21.205702 ==
3230 11:48:21.207899 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 11:48:21.211218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 11:48:21.211639 ==
3233 11:48:21.211972
3234 11:48:21.215475
3235 11:48:21.215988 TX Vref Scan disable
3236 11:48:21.217991 == TX Byte 0 ==
3237 11:48:21.222355 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3238 11:48:21.224801 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3239 11:48:21.228518 == TX Byte 1 ==
3240 11:48:21.231526 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 11:48:21.235085 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 11:48:21.235604
3243 11:48:21.238101 [DATLAT]
3244 11:48:21.238662 Freq=1200, CH1 RK0
3245 11:48:21.239005
3246 11:48:21.241263 DATLAT Default: 0xd
3247 11:48:21.241780 0, 0xFFFF, sum = 0
3248 11:48:21.244884 1, 0xFFFF, sum = 0
3249 11:48:21.245407 2, 0xFFFF, sum = 0
3250 11:48:21.248256 3, 0xFFFF, sum = 0
3251 11:48:21.248779 4, 0xFFFF, sum = 0
3252 11:48:21.250862 5, 0xFFFF, sum = 0
3253 11:48:21.254865 6, 0xFFFF, sum = 0
3254 11:48:21.255388 7, 0xFFFF, sum = 0
3255 11:48:21.257857 8, 0xFFFF, sum = 0
3256 11:48:21.258421 9, 0xFFFF, sum = 0
3257 11:48:21.261343 10, 0xFFFF, sum = 0
3258 11:48:21.261862 11, 0xFFFF, sum = 0
3259 11:48:21.264612 12, 0x0, sum = 1
3260 11:48:21.265140 13, 0x0, sum = 2
3261 11:48:21.267936 14, 0x0, sum = 3
3262 11:48:21.268463 15, 0x0, sum = 4
3263 11:48:21.268811 best_step = 13
3264 11:48:21.271582
3265 11:48:21.272011 ==
3266 11:48:21.274205 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 11:48:21.278173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 11:48:21.278843 ==
3269 11:48:21.279274 RX Vref Scan: 1
3270 11:48:21.279600
3271 11:48:21.281340 Set Vref Range= 32 -> 127
3272 11:48:21.281757
3273 11:48:21.284596 RX Vref 32 -> 127, step: 1
3274 11:48:21.285014
3275 11:48:21.287678 RX Delay -13 -> 252, step: 4
3276 11:48:21.288095
3277 11:48:21.291421 Set Vref, RX VrefLevel [Byte0]: 32
3278 11:48:21.294641 [Byte1]: 32
3279 11:48:21.295159
3280 11:48:21.297713 Set Vref, RX VrefLevel [Byte0]: 33
3281 11:48:21.301136 [Byte1]: 33
3282 11:48:21.301680
3283 11:48:21.304506 Set Vref, RX VrefLevel [Byte0]: 34
3284 11:48:21.307948 [Byte1]: 34
3285 11:48:21.312113
3286 11:48:21.312531 Set Vref, RX VrefLevel [Byte0]: 35
3287 11:48:21.315679 [Byte1]: 35
3288 11:48:21.320259
3289 11:48:21.320793 Set Vref, RX VrefLevel [Byte0]: 36
3290 11:48:21.323365 [Byte1]: 36
3291 11:48:21.328169
3292 11:48:21.328684 Set Vref, RX VrefLevel [Byte0]: 37
3293 11:48:21.331423 [Byte1]: 37
3294 11:48:21.335976
3295 11:48:21.336388 Set Vref, RX VrefLevel [Byte0]: 38
3296 11:48:21.338726 [Byte1]: 38
3297 11:48:21.343522
3298 11:48:21.343934 Set Vref, RX VrefLevel [Byte0]: 39
3299 11:48:21.347477 [Byte1]: 39
3300 11:48:21.351817
3301 11:48:21.352323 Set Vref, RX VrefLevel [Byte0]: 40
3302 11:48:21.355194 [Byte1]: 40
3303 11:48:21.360174
3304 11:48:21.360688 Set Vref, RX VrefLevel [Byte0]: 41
3305 11:48:21.363027 [Byte1]: 41
3306 11:48:21.367288
3307 11:48:21.367802 Set Vref, RX VrefLevel [Byte0]: 42
3308 11:48:21.370917 [Byte1]: 42
3309 11:48:21.375344
3310 11:48:21.375807 Set Vref, RX VrefLevel [Byte0]: 43
3311 11:48:21.378455 [Byte1]: 43
3312 11:48:21.382973
3313 11:48:21.383488 Set Vref, RX VrefLevel [Byte0]: 44
3314 11:48:21.386594 [Byte1]: 44
3315 11:48:21.390726
3316 11:48:21.391139 Set Vref, RX VrefLevel [Byte0]: 45
3317 11:48:21.394236 [Byte1]: 45
3318 11:48:21.398823
3319 11:48:21.399334 Set Vref, RX VrefLevel [Byte0]: 46
3320 11:48:21.402192 [Byte1]: 46
3321 11:48:21.406608
3322 11:48:21.407020 Set Vref, RX VrefLevel [Byte0]: 47
3323 11:48:21.410461 [Byte1]: 47
3324 11:48:21.414516
3325 11:48:21.415063 Set Vref, RX VrefLevel [Byte0]: 48
3326 11:48:21.417980 [Byte1]: 48
3327 11:48:21.422612
3328 11:48:21.423127 Set Vref, RX VrefLevel [Byte0]: 49
3329 11:48:21.425991 [Byte1]: 49
3330 11:48:21.430605
3331 11:48:21.431291 Set Vref, RX VrefLevel [Byte0]: 50
3332 11:48:21.433562 [Byte1]: 50
3333 11:48:21.438013
3334 11:48:21.438539 Set Vref, RX VrefLevel [Byte0]: 51
3335 11:48:21.441767 [Byte1]: 51
3336 11:48:21.446404
3337 11:48:21.449559 Set Vref, RX VrefLevel [Byte0]: 52
3338 11:48:21.453210 [Byte1]: 52
3339 11:48:21.453723
3340 11:48:21.456413 Set Vref, RX VrefLevel [Byte0]: 53
3341 11:48:21.459654 [Byte1]: 53
3342 11:48:21.460164
3343 11:48:21.462691 Set Vref, RX VrefLevel [Byte0]: 54
3344 11:48:21.465796 [Byte1]: 54
3345 11:48:21.469971
3346 11:48:21.470529 Set Vref, RX VrefLevel [Byte0]: 55
3347 11:48:21.472953 [Byte1]: 55
3348 11:48:21.477645
3349 11:48:21.478149 Set Vref, RX VrefLevel [Byte0]: 56
3350 11:48:21.481099 [Byte1]: 56
3351 11:48:21.485539
3352 11:48:21.486049 Set Vref, RX VrefLevel [Byte0]: 57
3353 11:48:21.489107 [Byte1]: 57
3354 11:48:21.493465
3355 11:48:21.493987 Set Vref, RX VrefLevel [Byte0]: 58
3356 11:48:21.496700 [Byte1]: 58
3357 11:48:21.501278
3358 11:48:21.501789 Set Vref, RX VrefLevel [Byte0]: 59
3359 11:48:21.504834 [Byte1]: 59
3360 11:48:21.509644
3361 11:48:21.510154 Set Vref, RX VrefLevel [Byte0]: 60
3362 11:48:21.512322 [Byte1]: 60
3363 11:48:21.516614
3364 11:48:21.517113 Set Vref, RX VrefLevel [Byte0]: 61
3365 11:48:21.520362 [Byte1]: 61
3366 11:48:21.525056
3367 11:48:21.525558 Set Vref, RX VrefLevel [Byte0]: 62
3368 11:48:21.527961 [Byte1]: 62
3369 11:48:21.533208
3370 11:48:21.533707 Set Vref, RX VrefLevel [Byte0]: 63
3371 11:48:21.536584 [Byte1]: 63
3372 11:48:21.540683
3373 11:48:21.541096 Set Vref, RX VrefLevel [Byte0]: 64
3374 11:48:21.543817 [Byte1]: 64
3375 11:48:21.548704
3376 11:48:21.549353 Final RX Vref Byte 0 = 52 to rank0
3377 11:48:21.552221 Final RX Vref Byte 1 = 52 to rank0
3378 11:48:21.555342 Final RX Vref Byte 0 = 52 to rank1
3379 11:48:21.558352 Final RX Vref Byte 1 = 52 to rank1==
3380 11:48:21.561403 Dram Type= 6, Freq= 0, CH_1, rank 0
3381 11:48:21.568261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3382 11:48:21.568785 ==
3383 11:48:21.569122 DQS Delay:
3384 11:48:21.571839 DQS0 = 0, DQS1 = 0
3385 11:48:21.572357 DQM Delay:
3386 11:48:21.572699 DQM0 = 115, DQM1 = 113
3387 11:48:21.574881 DQ Delay:
3388 11:48:21.578227 DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =114
3389 11:48:21.581707 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3390 11:48:21.585534 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3391 11:48:21.588109 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3392 11:48:21.588529
3393 11:48:21.588866
3394 11:48:21.597922 [DQSOSCAuto] RK0, (LSB)MR18= 0xf300, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3395 11:48:21.598473 CH1 RK0: MR19=304, MR18=F300
3396 11:48:21.605099 CH1_RK0: MR19=0x304, MR18=0xF300, DQSOSC=410, MR23=63, INC=39, DEC=26
3397 11:48:21.605625
3398 11:48:21.608299 ----->DramcWriteLeveling(PI) begin...
3399 11:48:21.608725 ==
3400 11:48:21.611524 Dram Type= 6, Freq= 0, CH_1, rank 1
3401 11:48:21.618157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 11:48:21.618724 ==
3403 11:48:21.621922 Write leveling (Byte 0): 27 => 27
3404 11:48:21.622492 Write leveling (Byte 1): 29 => 29
3405 11:48:21.624957 DramcWriteLeveling(PI) end<-----
3406 11:48:21.625507
3407 11:48:21.625848 ==
3408 11:48:21.627987 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 11:48:21.635204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 11:48:21.635727 ==
3411 11:48:21.638315 [Gating] SW mode calibration
3412 11:48:21.645087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3413 11:48:21.648152 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3414 11:48:21.654783 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3415 11:48:21.658553 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3416 11:48:21.661303 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 11:48:21.667861 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3418 11:48:21.671583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 11:48:21.674662 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3420 11:48:21.681135 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 1)
3421 11:48:21.684993 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
3422 11:48:21.687744 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3423 11:48:21.694961 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3424 11:48:21.698293 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 11:48:21.700885 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3426 11:48:21.708365 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 11:48:21.711371 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3428 11:48:21.714306 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3429 11:48:21.721279 1 0 28 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3430 11:48:21.724585 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3431 11:48:21.727849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3432 11:48:21.734317 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 11:48:21.738329 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 11:48:21.740684 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 11:48:21.744142 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3436 11:48:21.750469 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3437 11:48:21.754209 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3438 11:48:21.760470 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3439 11:48:21.764054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 11:48:21.767389 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 11:48:21.774070 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 11:48:21.777119 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 11:48:21.780900 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 11:48:21.786958 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 11:48:21.790643 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 11:48:21.793645 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 11:48:21.799895 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 11:48:21.803254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 11:48:21.806577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 11:48:21.810583 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 11:48:21.816631 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3452 11:48:21.820328 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3453 11:48:21.823420 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3454 11:48:21.827124 Total UI for P1: 0, mck2ui 16
3455 11:48:21.829833 best dqsien dly found for B0: ( 1, 3, 22)
3456 11:48:21.836481 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:48:21.839371 Total UI for P1: 0, mck2ui 16
3458 11:48:21.843223 best dqsien dly found for B1: ( 1, 3, 26)
3459 11:48:21.846615 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3460 11:48:21.849628 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3461 11:48:21.850046
3462 11:48:21.852870 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3463 11:48:21.856343 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3464 11:48:21.859876 [Gating] SW calibration Done
3465 11:48:21.860395 ==
3466 11:48:21.862734 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 11:48:21.866214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 11:48:21.866761 ==
3469 11:48:21.869760 RX Vref Scan: 0
3470 11:48:21.870309
3471 11:48:21.872592 RX Vref 0 -> 0, step: 1
3472 11:48:21.873105
3473 11:48:21.873441 RX Delay -40 -> 252, step: 8
3474 11:48:21.879149 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3475 11:48:21.882685 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3476 11:48:21.886159 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3477 11:48:21.889114 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3478 11:48:21.895827 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3479 11:48:21.899274 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3480 11:48:21.902332 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3481 11:48:21.906167 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3482 11:48:21.908930 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3483 11:48:21.912650 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3484 11:48:21.918996 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3485 11:48:21.922411 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3486 11:48:21.925396 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3487 11:48:21.928609 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3488 11:48:21.935661 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3489 11:48:21.939186 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3490 11:48:21.939756 ==
3491 11:48:21.942292 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 11:48:21.946068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 11:48:21.946629 ==
3494 11:48:21.946967 DQS Delay:
3495 11:48:21.948593 DQS0 = 0, DQS1 = 0
3496 11:48:21.949010 DQM Delay:
3497 11:48:21.951775 DQM0 = 115, DQM1 = 111
3498 11:48:21.952192 DQ Delay:
3499 11:48:21.955583 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3500 11:48:21.958682 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3501 11:48:21.962002 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3502 11:48:21.968742 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3503 11:48:21.969264
3504 11:48:21.969599
3505 11:48:21.969906 ==
3506 11:48:21.971756 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 11:48:21.974781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 11:48:21.975202 ==
3509 11:48:21.975535
3510 11:48:21.975983
3511 11:48:21.978672 TX Vref Scan disable
3512 11:48:21.979137 == TX Byte 0 ==
3513 11:48:21.984856 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3514 11:48:21.988765 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3515 11:48:21.989284 == TX Byte 1 ==
3516 11:48:21.994851 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3517 11:48:21.997962 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3518 11:48:21.998419 ==
3519 11:48:22.001986 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 11:48:22.004803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 11:48:22.005325 ==
3522 11:48:22.017718 TX Vref=22, minBit 1, minWin=25, winSum=420
3523 11:48:22.020844 TX Vref=24, minBit 3, minWin=25, winSum=424
3524 11:48:22.023968 TX Vref=26, minBit 1, minWin=25, winSum=426
3525 11:48:22.027393 TX Vref=28, minBit 1, minWin=26, winSum=431
3526 11:48:22.030445 TX Vref=30, minBit 1, minWin=26, winSum=432
3527 11:48:22.037486 TX Vref=32, minBit 1, minWin=26, winSum=430
3528 11:48:22.040220 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3529 11:48:22.040646
3530 11:48:22.044359 Final TX Range 1 Vref 30
3531 11:48:22.044868
3532 11:48:22.045201 ==
3533 11:48:22.046848 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 11:48:22.050382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 11:48:22.053772 ==
3536 11:48:22.054524
3537 11:48:22.054891
3538 11:48:22.055280 TX Vref Scan disable
3539 11:48:22.057795 == TX Byte 0 ==
3540 11:48:22.060519 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3541 11:48:22.067025 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3542 11:48:22.067532 == TX Byte 1 ==
3543 11:48:22.071320 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3544 11:48:22.077318 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3545 11:48:22.077839
3546 11:48:22.078176 [DATLAT]
3547 11:48:22.078559 Freq=1200, CH1 RK1
3548 11:48:22.078869
3549 11:48:22.080093 DATLAT Default: 0xd
3550 11:48:22.080513 0, 0xFFFF, sum = 0
3551 11:48:22.083920 1, 0xFFFF, sum = 0
3552 11:48:22.086847 2, 0xFFFF, sum = 0
3553 11:48:22.087272 3, 0xFFFF, sum = 0
3554 11:48:22.090060 4, 0xFFFF, sum = 0
3555 11:48:22.090526 5, 0xFFFF, sum = 0
3556 11:48:22.093548 6, 0xFFFF, sum = 0
3557 11:48:22.093975 7, 0xFFFF, sum = 0
3558 11:48:22.096635 8, 0xFFFF, sum = 0
3559 11:48:22.097060 9, 0xFFFF, sum = 0
3560 11:48:22.100583 10, 0xFFFF, sum = 0
3561 11:48:22.101008 11, 0xFFFF, sum = 0
3562 11:48:22.103608 12, 0x0, sum = 1
3563 11:48:22.104031 13, 0x0, sum = 2
3564 11:48:22.107013 14, 0x0, sum = 3
3565 11:48:22.107539 15, 0x0, sum = 4
3566 11:48:22.110326 best_step = 13
3567 11:48:22.110747
3568 11:48:22.111078 ==
3569 11:48:22.113273 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:48:22.116407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:48:22.116827 ==
3572 11:48:22.119782 RX Vref Scan: 0
3573 11:48:22.120200
3574 11:48:22.120531 RX Vref 0 -> 0, step: 1
3575 11:48:22.120842
3576 11:48:22.123087 RX Delay -13 -> 252, step: 4
3577 11:48:22.130065 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3578 11:48:22.133334 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3579 11:48:22.136979 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3580 11:48:22.139560 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3581 11:48:22.143245 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3582 11:48:22.149652 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3583 11:48:22.152783 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3584 11:48:22.156062 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3585 11:48:22.159623 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3586 11:48:22.162628 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3587 11:48:22.169591 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3588 11:48:22.172746 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3589 11:48:22.175621 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3590 11:48:22.179131 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3591 11:48:22.185700 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3592 11:48:22.189219 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3593 11:48:22.189815 ==
3594 11:48:22.192239 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 11:48:22.195567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 11:48:22.195986 ==
3597 11:48:22.198948 DQS Delay:
3598 11:48:22.199360 DQS0 = 0, DQS1 = 0
3599 11:48:22.199689 DQM Delay:
3600 11:48:22.202838 DQM0 = 115, DQM1 = 112
3601 11:48:22.203251 DQ Delay:
3602 11:48:22.205634 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3603 11:48:22.208593 DQ4 =116, DQ5 =122, DQ6 =120, DQ7 =114
3604 11:48:22.211852 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3605 11:48:22.218742 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3606 11:48:22.219154
3607 11:48:22.219479
3608 11:48:22.225591 [DQSOSCAuto] RK1, (LSB)MR18= 0xf607, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3609 11:48:22.228456 CH1 RK1: MR19=304, MR18=F607
3610 11:48:22.235413 CH1_RK1: MR19=0x304, MR18=0xF607, DQSOSC=407, MR23=63, INC=39, DEC=26
3611 11:48:22.238798 [RxdqsGatingPostProcess] freq 1200
3612 11:48:22.242442 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3613 11:48:22.245595 best DQS0 dly(2T, 0.5T) = (0, 11)
3614 11:48:22.248095 best DQS1 dly(2T, 0.5T) = (0, 11)
3615 11:48:22.252570 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3616 11:48:22.255059 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3617 11:48:22.258630 best DQS0 dly(2T, 0.5T) = (0, 11)
3618 11:48:22.261556 best DQS1 dly(2T, 0.5T) = (0, 11)
3619 11:48:22.264880 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3620 11:48:22.268137 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3621 11:48:22.271758 Pre-setting of DQS Precalculation
3622 11:48:22.278436 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3623 11:48:22.284194 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3624 11:48:22.291042 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3625 11:48:22.291541
3626 11:48:22.291874
3627 11:48:22.294585 [Calibration Summary] 2400 Mbps
3628 11:48:22.295014 CH 0, Rank 0
3629 11:48:22.297585 SW Impedance : PASS
3630 11:48:22.301262 DUTY Scan : NO K
3631 11:48:22.301772 ZQ Calibration : PASS
3632 11:48:22.304356 Jitter Meter : NO K
3633 11:48:22.308041 CBT Training : PASS
3634 11:48:22.308549 Write leveling : PASS
3635 11:48:22.310708 RX DQS gating : PASS
3636 11:48:22.314168 RX DQ/DQS(RDDQC) : PASS
3637 11:48:22.314645 TX DQ/DQS : PASS
3638 11:48:22.317930 RX DATLAT : PASS
3639 11:48:22.318496 RX DQ/DQS(Engine): PASS
3640 11:48:22.320994 TX OE : NO K
3641 11:48:22.321513 All Pass.
3642 11:48:22.321850
3643 11:48:22.324117 CH 0, Rank 1
3644 11:48:22.327581 SW Impedance : PASS
3645 11:48:22.328105 DUTY Scan : NO K
3646 11:48:22.330539 ZQ Calibration : PASS
3647 11:48:22.330954 Jitter Meter : NO K
3648 11:48:22.333802 CBT Training : PASS
3649 11:48:22.337674 Write leveling : PASS
3650 11:48:22.338182 RX DQS gating : PASS
3651 11:48:22.340369 RX DQ/DQS(RDDQC) : PASS
3652 11:48:22.343726 TX DQ/DQS : PASS
3653 11:48:22.344235 RX DATLAT : PASS
3654 11:48:22.348079 RX DQ/DQS(Engine): PASS
3655 11:48:22.350709 TX OE : NO K
3656 11:48:22.351223 All Pass.
3657 11:48:22.351558
3658 11:48:22.351863 CH 1, Rank 0
3659 11:48:22.353412 SW Impedance : PASS
3660 11:48:22.357300 DUTY Scan : NO K
3661 11:48:22.357856 ZQ Calibration : PASS
3662 11:48:22.360353 Jitter Meter : NO K
3663 11:48:22.363460 CBT Training : PASS
3664 11:48:22.363964 Write leveling : PASS
3665 11:48:22.367130 RX DQS gating : PASS
3666 11:48:22.370452 RX DQ/DQS(RDDQC) : PASS
3667 11:48:22.370958 TX DQ/DQS : PASS
3668 11:48:22.373869 RX DATLAT : PASS
3669 11:48:22.377001 RX DQ/DQS(Engine): PASS
3670 11:48:22.377512 TX OE : NO K
3671 11:48:22.380016 All Pass.
3672 11:48:22.380434
3673 11:48:22.380765 CH 1, Rank 1
3674 11:48:22.383622 SW Impedance : PASS
3675 11:48:22.384039 DUTY Scan : NO K
3676 11:48:22.386294 ZQ Calibration : PASS
3677 11:48:22.389834 Jitter Meter : NO K
3678 11:48:22.390414 CBT Training : PASS
3679 11:48:22.393389 Write leveling : PASS
3680 11:48:22.396448 RX DQS gating : PASS
3681 11:48:22.396868 RX DQ/DQS(RDDQC) : PASS
3682 11:48:22.399430 TX DQ/DQS : PASS
3683 11:48:22.403152 RX DATLAT : PASS
3684 11:48:22.403600 RX DQ/DQS(Engine): PASS
3685 11:48:22.406725 TX OE : NO K
3686 11:48:22.407239 All Pass.
3687 11:48:22.407580
3688 11:48:22.409482 DramC Write-DBI off
3689 11:48:22.412769 PER_BANK_REFRESH: Hybrid Mode
3690 11:48:22.413191 TX_TRACKING: ON
3691 11:48:22.423047 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3692 11:48:22.425900 [FAST_K] Save calibration result to emmc
3693 11:48:22.429216 dramc_set_vcore_voltage set vcore to 650000
3694 11:48:22.432436 Read voltage for 600, 5
3695 11:48:22.432855 Vio18 = 0
3696 11:48:22.433191 Vcore = 650000
3697 11:48:22.436511 Vdram = 0
3698 11:48:22.437019 Vddq = 0
3699 11:48:22.437354 Vmddr = 0
3700 11:48:22.442598 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3701 11:48:22.445602 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3702 11:48:22.449072 MEM_TYPE=3, freq_sel=19
3703 11:48:22.452214 sv_algorithm_assistance_LP4_1600
3704 11:48:22.456086 ============ PULL DRAM RESETB DOWN ============
3705 11:48:22.459128 ========== PULL DRAM RESETB DOWN end =========
3706 11:48:22.465834 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3707 11:48:22.469069 ===================================
3708 11:48:22.472500 LPDDR4 DRAM CONFIGURATION
3709 11:48:22.476016 ===================================
3710 11:48:22.476566 EX_ROW_EN[0] = 0x0
3711 11:48:22.479042 EX_ROW_EN[1] = 0x0
3712 11:48:22.479593 LP4Y_EN = 0x0
3713 11:48:22.481850 WORK_FSP = 0x0
3714 11:48:22.482380 WL = 0x2
3715 11:48:22.485667 RL = 0x2
3716 11:48:22.486213 BL = 0x2
3717 11:48:22.489026 RPST = 0x0
3718 11:48:22.489536 RD_PRE = 0x0
3719 11:48:22.491890 WR_PRE = 0x1
3720 11:48:22.492352 WR_PST = 0x0
3721 11:48:22.495366 DBI_WR = 0x0
3722 11:48:22.495798 DBI_RD = 0x0
3723 11:48:22.499190 OTF = 0x1
3724 11:48:22.501572 ===================================
3725 11:48:22.505788 ===================================
3726 11:48:22.506351 ANA top config
3727 11:48:22.508608 ===================================
3728 11:48:22.511531 DLL_ASYNC_EN = 0
3729 11:48:22.515582 ALL_SLAVE_EN = 1
3730 11:48:22.518449 NEW_RANK_MODE = 1
3731 11:48:22.521860 DLL_IDLE_MODE = 1
3732 11:48:22.522412 LP45_APHY_COMB_EN = 1
3733 11:48:22.524577 TX_ODT_DIS = 1
3734 11:48:22.528436 NEW_8X_MODE = 1
3735 11:48:22.531567 ===================================
3736 11:48:22.534736 ===================================
3737 11:48:22.538098 data_rate = 1200
3738 11:48:22.541306 CKR = 1
3739 11:48:22.544814 DQ_P2S_RATIO = 8
3740 11:48:22.547741 ===================================
3741 11:48:22.548171 CA_P2S_RATIO = 8
3742 11:48:22.551230 DQ_CA_OPEN = 0
3743 11:48:22.554242 DQ_SEMI_OPEN = 0
3744 11:48:22.558087 CA_SEMI_OPEN = 0
3745 11:48:22.560962 CA_FULL_RATE = 0
3746 11:48:22.564205 DQ_CKDIV4_EN = 1
3747 11:48:22.564636 CA_CKDIV4_EN = 1
3748 11:48:22.567471 CA_PREDIV_EN = 0
3749 11:48:22.570507 PH8_DLY = 0
3750 11:48:22.574301 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3751 11:48:22.577957 DQ_AAMCK_DIV = 4
3752 11:48:22.580181 CA_AAMCK_DIV = 4
3753 11:48:22.580599 CA_ADMCK_DIV = 4
3754 11:48:22.584140 DQ_TRACK_CA_EN = 0
3755 11:48:22.587107 CA_PICK = 600
3756 11:48:22.590565 CA_MCKIO = 600
3757 11:48:22.593851 MCKIO_SEMI = 0
3758 11:48:22.596941 PLL_FREQ = 2288
3759 11:48:22.600334 DQ_UI_PI_RATIO = 32
3760 11:48:22.603785 CA_UI_PI_RATIO = 0
3761 11:48:22.606910 ===================================
3762 11:48:22.610453 ===================================
3763 11:48:22.610969 memory_type:LPDDR4
3764 11:48:22.613631 GP_NUM : 10
3765 11:48:22.616996 SRAM_EN : 1
3766 11:48:22.617415 MD32_EN : 0
3767 11:48:22.619890 ===================================
3768 11:48:22.623835 [ANA_INIT] >>>>>>>>>>>>>>
3769 11:48:22.626872 <<<<<< [CONFIGURE PHASE]: ANA_TX
3770 11:48:22.630044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3771 11:48:22.633966 ===================================
3772 11:48:22.636445 data_rate = 1200,PCW = 0X5800
3773 11:48:22.640350 ===================================
3774 11:48:22.643660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3775 11:48:22.646798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3776 11:48:22.653115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3777 11:48:22.656764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3778 11:48:22.659867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3779 11:48:22.663695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3780 11:48:22.666317 [ANA_INIT] flow start
3781 11:48:22.669673 [ANA_INIT] PLL >>>>>>>>
3782 11:48:22.670198 [ANA_INIT] PLL <<<<<<<<
3783 11:48:22.673504 [ANA_INIT] MIDPI >>>>>>>>
3784 11:48:22.675990 [ANA_INIT] MIDPI <<<<<<<<
3785 11:48:22.679459 [ANA_INIT] DLL >>>>>>>>
3786 11:48:22.679879 [ANA_INIT] flow end
3787 11:48:22.683034 ============ LP4 DIFF to SE enter ============
3788 11:48:22.689353 ============ LP4 DIFF to SE exit ============
3789 11:48:22.689903 [ANA_INIT] <<<<<<<<<<<<<
3790 11:48:22.692622 [Flow] Enable top DCM control >>>>>
3791 11:48:22.696205 [Flow] Enable top DCM control <<<<<
3792 11:48:22.698987 Enable DLL master slave shuffle
3793 11:48:22.705622 ==============================================================
3794 11:48:22.706112 Gating Mode config
3795 11:48:22.712193 ==============================================================
3796 11:48:22.715440 Config description:
3797 11:48:22.726024 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3798 11:48:22.732342 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3799 11:48:22.735214 SELPH_MODE 0: By rank 1: By Phase
3800 11:48:22.742215 ==============================================================
3801 11:48:22.745250 GAT_TRACK_EN = 1
3802 11:48:22.748414 RX_GATING_MODE = 2
3803 11:48:22.751585 RX_GATING_TRACK_MODE = 2
3804 11:48:22.752048 SELPH_MODE = 1
3805 11:48:22.755602 PICG_EARLY_EN = 1
3806 11:48:22.758703 VALID_LAT_VALUE = 1
3807 11:48:22.764797 ==============================================================
3808 11:48:22.767890 Enter into Gating configuration >>>>
3809 11:48:22.771727 Exit from Gating configuration <<<<
3810 11:48:22.774222 Enter into DVFS_PRE_config >>>>>
3811 11:48:22.786573 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3812 11:48:22.787956 Exit from DVFS_PRE_config <<<<<
3813 11:48:22.790838 Enter into PICG configuration >>>>
3814 11:48:22.794371 Exit from PICG configuration <<<<
3815 11:48:22.797622 [RX_INPUT] configuration >>>>>
3816 11:48:22.800987 [RX_INPUT] configuration <<<<<
3817 11:48:22.807265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3818 11:48:22.810583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3819 11:48:22.817693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3820 11:48:22.824158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3821 11:48:22.830919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3822 11:48:22.837786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3823 11:48:22.840307 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3824 11:48:22.844395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3825 11:48:22.847405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3826 11:48:22.853490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3827 11:48:22.857162 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3828 11:48:22.860535 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3829 11:48:22.864075 ===================================
3830 11:48:22.866746 LPDDR4 DRAM CONFIGURATION
3831 11:48:22.870536 ===================================
3832 11:48:22.873516 EX_ROW_EN[0] = 0x0
3833 11:48:22.874023 EX_ROW_EN[1] = 0x0
3834 11:48:22.876561 LP4Y_EN = 0x0
3835 11:48:22.876978 WORK_FSP = 0x0
3836 11:48:22.880170 WL = 0x2
3837 11:48:22.880589 RL = 0x2
3838 11:48:22.883257 BL = 0x2
3839 11:48:22.883679 RPST = 0x0
3840 11:48:22.886206 RD_PRE = 0x0
3841 11:48:22.886662 WR_PRE = 0x1
3842 11:48:22.890132 WR_PST = 0x0
3843 11:48:22.890727 DBI_WR = 0x0
3844 11:48:22.893720 DBI_RD = 0x0
3845 11:48:22.894231 OTF = 0x1
3846 11:48:22.896403 ===================================
3847 11:48:22.904995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3848 11:48:22.906576 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3849 11:48:22.910344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 11:48:22.912748 ===================================
3851 11:48:22.915894 LPDDR4 DRAM CONFIGURATION
3852 11:48:22.919473 ===================================
3853 11:48:22.922807 EX_ROW_EN[0] = 0x10
3854 11:48:22.923225 EX_ROW_EN[1] = 0x0
3855 11:48:22.925887 LP4Y_EN = 0x0
3856 11:48:22.926342 WORK_FSP = 0x0
3857 11:48:22.929250 WL = 0x2
3858 11:48:22.929758 RL = 0x2
3859 11:48:22.932539 BL = 0x2
3860 11:48:22.933050 RPST = 0x0
3861 11:48:22.935519 RD_PRE = 0x0
3862 11:48:22.935936 WR_PRE = 0x1
3863 11:48:22.939258 WR_PST = 0x0
3864 11:48:22.939674 DBI_WR = 0x0
3865 11:48:22.942245 DBI_RD = 0x0
3866 11:48:22.942700 OTF = 0x1
3867 11:48:22.946320 ===================================
3868 11:48:22.952017 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3869 11:48:22.957655 nWR fixed to 30
3870 11:48:22.960654 [ModeRegInit_LP4] CH0 RK0
3871 11:48:22.961163 [ModeRegInit_LP4] CH0 RK1
3872 11:48:22.964172 [ModeRegInit_LP4] CH1 RK0
3873 11:48:22.967099 [ModeRegInit_LP4] CH1 RK1
3874 11:48:22.967519 match AC timing 17
3875 11:48:22.973903 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3876 11:48:22.977586 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3877 11:48:22.980892 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3878 11:48:22.986743 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3879 11:48:22.990706 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3880 11:48:22.991222 ==
3881 11:48:22.993737 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 11:48:22.996738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3883 11:48:22.997160 ==
3884 11:48:23.003254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3885 11:48:23.010294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3886 11:48:23.013460 [CA 0] Center 36 (6~67) winsize 62
3887 11:48:23.019200 [CA 1] Center 36 (6~66) winsize 61
3888 11:48:23.020822 [CA 2] Center 34 (4~65) winsize 62
3889 11:48:23.023490 [CA 3] Center 34 (4~65) winsize 62
3890 11:48:23.026804 [CA 4] Center 33 (3~64) winsize 62
3891 11:48:23.029640 [CA 5] Center 33 (3~64) winsize 62
3892 11:48:23.030063
3893 11:48:23.032773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3894 11:48:23.033193
3895 11:48:23.036490 [CATrainingPosCal] consider 1 rank data
3896 11:48:23.039385 u2DelayCellTimex100 = 270/100 ps
3897 11:48:23.043517 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3898 11:48:23.046398 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3899 11:48:23.049199 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3900 11:48:23.056480 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3901 11:48:23.059241 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3902 11:48:23.062849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3903 11:48:23.063268
3904 11:48:23.066184 CA PerBit enable=1, Macro0, CA PI delay=33
3905 11:48:23.066741
3906 11:48:23.069861 [CBTSetCACLKResult] CA Dly = 33
3907 11:48:23.070435 CS Dly: 5 (0~36)
3908 11:48:23.070960 ==
3909 11:48:23.072805 Dram Type= 6, Freq= 0, CH_0, rank 1
3910 11:48:23.079339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 11:48:23.079856 ==
3912 11:48:23.083011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 11:48:23.089202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3914 11:48:23.092821 [CA 0] Center 36 (6~67) winsize 62
3915 11:48:23.096200 [CA 1] Center 36 (6~67) winsize 62
3916 11:48:23.099432 [CA 2] Center 34 (4~65) winsize 62
3917 11:48:23.103105 [CA 3] Center 34 (4~65) winsize 62
3918 11:48:23.106363 [CA 4] Center 34 (3~65) winsize 63
3919 11:48:23.109037 [CA 5] Center 33 (3~64) winsize 62
3920 11:48:23.109545
3921 11:48:23.112823 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3922 11:48:23.113345
3923 11:48:23.115470 [CATrainingPosCal] consider 2 rank data
3924 11:48:23.119269 u2DelayCellTimex100 = 270/100 ps
3925 11:48:23.125992 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 11:48:23.129711 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3927 11:48:23.132152 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 11:48:23.135297 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 11:48:23.139423 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 11:48:23.142178 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 11:48:23.142758
3932 11:48:23.145583 CA PerBit enable=1, Macro0, CA PI delay=33
3933 11:48:23.146004
3934 11:48:23.149142 [CBTSetCACLKResult] CA Dly = 33
3935 11:48:23.151596 CS Dly: 5 (0~37)
3936 11:48:23.152014
3937 11:48:23.155305 ----->DramcWriteLeveling(PI) begin...
3938 11:48:23.155847 ==
3939 11:48:23.158516 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 11:48:23.161755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 11:48:23.162302 ==
3942 11:48:23.165003 Write leveling (Byte 0): 31 => 31
3943 11:48:23.168965 Write leveling (Byte 1): 31 => 31
3944 11:48:23.171515 DramcWriteLeveling(PI) end<-----
3945 11:48:23.171931
3946 11:48:23.172265 ==
3947 11:48:23.174884 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 11:48:23.178229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 11:48:23.178691 ==
3950 11:48:23.181331 [Gating] SW mode calibration
3951 11:48:23.188250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3952 11:48:23.194708 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3953 11:48:23.198342 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3954 11:48:23.204717 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3955 11:48:23.207934 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3956 11:48:23.210702 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3957 11:48:23.217574 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
3958 11:48:23.221065 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 11:48:23.223861 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3960 11:48:23.230397 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 11:48:23.233913 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 11:48:23.237471 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 11:48:23.243948 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 11:48:23.247037 0 10 12 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
3965 11:48:23.250292 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3966 11:48:23.256953 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 11:48:23.260554 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3968 11:48:23.263731 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 11:48:23.270695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 11:48:23.273981 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 11:48:23.277308 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 11:48:23.283790 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 11:48:23.286765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3974 11:48:23.290023 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 11:48:23.293483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 11:48:23.299999 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 11:48:23.303146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 11:48:23.306986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 11:48:23.313518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 11:48:23.316524 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 11:48:23.319767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 11:48:23.327092 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 11:48:23.329738 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 11:48:23.336147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 11:48:23.340225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 11:48:23.342730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 11:48:23.349574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:48:23.352993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3989 11:48:23.356008 Total UI for P1: 0, mck2ui 16
3990 11:48:23.359852 best dqsien dly found for B0: ( 0, 13, 10)
3991 11:48:23.362940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:48:23.365748 Total UI for P1: 0, mck2ui 16
3993 11:48:23.369498 best dqsien dly found for B1: ( 0, 13, 14)
3994 11:48:23.372605 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
3995 11:48:23.375839 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
3996 11:48:23.376348
3997 11:48:23.382219 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
3998 11:48:23.385555 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
3999 11:48:23.385975 [Gating] SW calibration Done
4000 11:48:23.389143 ==
4001 11:48:23.391994 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 11:48:23.395759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 11:48:23.396274 ==
4004 11:48:23.396603 RX Vref Scan: 0
4005 11:48:23.396905
4006 11:48:23.398594 RX Vref 0 -> 0, step: 1
4007 11:48:23.399005
4008 11:48:23.402382 RX Delay -230 -> 252, step: 16
4009 11:48:23.405383 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4010 11:48:23.408440 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4011 11:48:23.415179 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4012 11:48:23.418159 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4013 11:48:23.422357 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4014 11:48:23.425156 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4015 11:48:23.431665 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4016 11:48:23.434694 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4017 11:48:23.437950 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4018 11:48:23.441800 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4019 11:48:23.448568 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4020 11:48:23.451135 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4021 11:48:23.454846 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4022 11:48:23.458101 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4023 11:48:23.464631 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4024 11:48:23.467998 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4025 11:48:23.468507 ==
4026 11:48:23.471206 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 11:48:23.475339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 11:48:23.476031 ==
4029 11:48:23.477689 DQS Delay:
4030 11:48:23.478098 DQS0 = 0, DQS1 = 0
4031 11:48:23.478491 DQM Delay:
4032 11:48:23.481196 DQM0 = 46, DQM1 = 37
4033 11:48:23.481623 DQ Delay:
4034 11:48:23.485188 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4035 11:48:23.488116 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4036 11:48:23.491173 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4037 11:48:23.494066 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4038 11:48:23.494536
4039 11:48:23.494865
4040 11:48:23.495167 ==
4041 11:48:23.497680 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 11:48:23.504329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 11:48:23.504842 ==
4044 11:48:23.505175
4045 11:48:23.505477
4046 11:48:23.505768 TX Vref Scan disable
4047 11:48:23.508473 == TX Byte 0 ==
4048 11:48:23.510919 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4049 11:48:23.517636 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4050 11:48:23.518064 == TX Byte 1 ==
4051 11:48:23.521349 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4052 11:48:23.527822 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4053 11:48:23.528344 ==
4054 11:48:23.531058 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 11:48:23.534392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 11:48:23.534822 ==
4057 11:48:23.535250
4058 11:48:23.535731
4059 11:48:23.537151 TX Vref Scan disable
4060 11:48:23.540810 == TX Byte 0 ==
4061 11:48:23.544569 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4062 11:48:23.548006 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4063 11:48:23.551097 == TX Byte 1 ==
4064 11:48:23.554314 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4065 11:48:23.557270 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4066 11:48:23.557794
4067 11:48:23.558233 [DATLAT]
4068 11:48:23.560450 Freq=600, CH0 RK0
4069 11:48:23.560874
4070 11:48:23.564052 DATLAT Default: 0x9
4071 11:48:23.564473 0, 0xFFFF, sum = 0
4072 11:48:23.567917 1, 0xFFFF, sum = 0
4073 11:48:23.568466 2, 0xFFFF, sum = 0
4074 11:48:23.570565 3, 0xFFFF, sum = 0
4075 11:48:23.571098 4, 0xFFFF, sum = 0
4076 11:48:23.573938 5, 0xFFFF, sum = 0
4077 11:48:23.574431 6, 0xFFFF, sum = 0
4078 11:48:23.577161 7, 0xFFFF, sum = 0
4079 11:48:23.577591 8, 0x0, sum = 1
4080 11:48:23.580453 9, 0x0, sum = 2
4081 11:48:23.580965 10, 0x0, sum = 3
4082 11:48:23.583595 11, 0x0, sum = 4
4083 11:48:23.584020 best_step = 9
4084 11:48:23.584352
4085 11:48:23.584661 ==
4086 11:48:23.587034 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 11:48:23.590208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 11:48:23.591003 ==
4089 11:48:23.593663 RX Vref Scan: 1
4090 11:48:23.594173
4091 11:48:23.597128 RX Vref 0 -> 0, step: 1
4092 11:48:23.597637
4093 11:48:23.599877 RX Delay -179 -> 252, step: 8
4094 11:48:23.600294
4095 11:48:23.603401 Set Vref, RX VrefLevel [Byte0]: 55
4096 11:48:23.603913 [Byte1]: 50
4097 11:48:23.608513
4098 11:48:23.609022 Final RX Vref Byte 0 = 55 to rank0
4099 11:48:23.611336 Final RX Vref Byte 1 = 50 to rank0
4100 11:48:23.614778 Final RX Vref Byte 0 = 55 to rank1
4101 11:48:23.618329 Final RX Vref Byte 1 = 50 to rank1==
4102 11:48:23.621808 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 11:48:23.628316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 11:48:23.628828 ==
4105 11:48:23.629161 DQS Delay:
4106 11:48:23.631444 DQS0 = 0, DQS1 = 0
4107 11:48:23.631864 DQM Delay:
4108 11:48:23.632215 DQM0 = 44, DQM1 = 37
4109 11:48:23.634675 DQ Delay:
4110 11:48:23.638399 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4111 11:48:23.641151 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4112 11:48:23.645031 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =32
4113 11:48:23.648349 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4114 11:48:23.648854
4115 11:48:23.649181
4116 11:48:23.654724 [DQSOSCAuto] RK0, (LSB)MR18= 0x463e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4117 11:48:23.657810 CH0 RK0: MR19=808, MR18=463E
4118 11:48:23.664881 CH0_RK0: MR19=0x808, MR18=0x463E, DQSOSC=396, MR23=63, INC=167, DEC=111
4119 11:48:23.665432
4120 11:48:23.668346 ----->DramcWriteLeveling(PI) begin...
4121 11:48:23.668940 ==
4122 11:48:23.670821 Dram Type= 6, Freq= 0, CH_0, rank 1
4123 11:48:23.674213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:48:23.674794 ==
4125 11:48:23.677910 Write leveling (Byte 0): 34 => 34
4126 11:48:23.681142 Write leveling (Byte 1): 31 => 31
4127 11:48:23.684221 DramcWriteLeveling(PI) end<-----
4128 11:48:23.684638
4129 11:48:23.684965 ==
4130 11:48:23.687369 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 11:48:23.691114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 11:48:23.694056 ==
4133 11:48:23.694519 [Gating] SW mode calibration
4134 11:48:23.704325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4135 11:48:23.707693 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4136 11:48:23.710762 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4137 11:48:23.716820 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4138 11:48:23.720192 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4139 11:48:23.723682 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (0 0) (0 0)
4140 11:48:23.731235 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
4141 11:48:23.733357 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4142 11:48:23.736856 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4143 11:48:23.743495 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 11:48:23.747239 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 11:48:23.750232 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 11:48:23.757307 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 11:48:23.759907 0 10 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
4148 11:48:23.763019 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4149 11:48:23.769842 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4150 11:48:23.773235 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4151 11:48:23.776635 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 11:48:23.782893 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 11:48:23.786405 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 11:48:23.789120 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 11:48:23.795803 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4156 11:48:23.799900 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4157 11:48:23.802366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4158 11:48:23.809670 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 11:48:23.812873 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 11:48:23.815888 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 11:48:23.822673 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 11:48:23.825796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 11:48:23.828903 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 11:48:23.835653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 11:48:23.839098 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 11:48:23.842237 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 11:48:23.849091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 11:48:23.852473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 11:48:23.855807 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 11:48:23.862418 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 11:48:23.865717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4172 11:48:23.868549 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4173 11:48:23.872001 Total UI for P1: 0, mck2ui 16
4174 11:48:23.875775 best dqsien dly found for B0: ( 0, 13, 12)
4175 11:48:23.881589 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:48:23.885096 Total UI for P1: 0, mck2ui 16
4177 11:48:23.888285 best dqsien dly found for B1: ( 0, 13, 14)
4178 11:48:23.891870 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4179 11:48:23.895085 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4180 11:48:23.895548
4181 11:48:23.899204 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4182 11:48:23.901337 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4183 11:48:23.904400 [Gating] SW calibration Done
4184 11:48:23.904861 ==
4185 11:48:23.908384 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 11:48:23.910848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 11:48:23.914217 ==
4188 11:48:23.914678 RX Vref Scan: 0
4189 11:48:23.915050
4190 11:48:23.917529 RX Vref 0 -> 0, step: 1
4191 11:48:23.917950
4192 11:48:23.922365 RX Delay -230 -> 252, step: 16
4193 11:48:23.924815 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4194 11:48:23.927566 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4195 11:48:23.930791 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4196 11:48:23.937465 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4197 11:48:23.941036 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4198 11:48:23.943857 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4199 11:48:23.947943 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4200 11:48:23.954867 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4201 11:48:23.957136 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4202 11:48:23.961148 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4203 11:48:23.964300 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4204 11:48:23.970326 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4205 11:48:23.973465 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4206 11:48:23.977003 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4207 11:48:23.980458 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4208 11:48:23.987218 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4209 11:48:23.987785 ==
4210 11:48:23.990404 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 11:48:23.993784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 11:48:23.994293 ==
4213 11:48:23.994777 DQS Delay:
4214 11:48:23.996955 DQS0 = 0, DQS1 = 0
4215 11:48:23.997525 DQM Delay:
4216 11:48:24.000091 DQM0 = 46, DQM1 = 37
4217 11:48:24.000658 DQ Delay:
4218 11:48:24.003353 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4219 11:48:24.006290 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4220 11:48:24.010501 DQ8 =33, DQ9 =17, DQ10 =41, DQ11 =33
4221 11:48:24.012793 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4222 11:48:24.013262
4223 11:48:24.013735
4224 11:48:24.014180 ==
4225 11:48:24.016290 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 11:48:24.019607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 11:48:24.020100 ==
4228 11:48:24.022540
4229 11:48:24.023062
4230 11:48:24.023425 TX Vref Scan disable
4231 11:48:24.026025 == TX Byte 0 ==
4232 11:48:24.029500 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4233 11:48:24.033387 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4234 11:48:24.036291 == TX Byte 1 ==
4235 11:48:24.039149 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4236 11:48:24.043115 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4237 11:48:24.045784 ==
4238 11:48:24.049100 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 11:48:24.052357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 11:48:24.052899 ==
4241 11:48:24.053230
4242 11:48:24.053532
4243 11:48:24.055441 TX Vref Scan disable
4244 11:48:24.058892 == TX Byte 0 ==
4245 11:48:24.062029 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4246 11:48:24.065653 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4247 11:48:24.068505 == TX Byte 1 ==
4248 11:48:24.071972 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4249 11:48:24.075665 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4250 11:48:24.076174
4251 11:48:24.076502 [DATLAT]
4252 11:48:24.078584 Freq=600, CH0 RK1
4253 11:48:24.078995
4254 11:48:24.082029 DATLAT Default: 0x9
4255 11:48:24.082600 0, 0xFFFF, sum = 0
4256 11:48:24.084982 1, 0xFFFF, sum = 0
4257 11:48:24.085397 2, 0xFFFF, sum = 0
4258 11:48:24.088321 3, 0xFFFF, sum = 0
4259 11:48:24.088741 4, 0xFFFF, sum = 0
4260 11:48:24.091996 5, 0xFFFF, sum = 0
4261 11:48:24.092517 6, 0xFFFF, sum = 0
4262 11:48:24.094791 7, 0xFFFF, sum = 0
4263 11:48:24.095206 8, 0x0, sum = 1
4264 11:48:24.099253 9, 0x0, sum = 2
4265 11:48:24.099771 10, 0x0, sum = 3
4266 11:48:24.102168 11, 0x0, sum = 4
4267 11:48:24.102735 best_step = 9
4268 11:48:24.103068
4269 11:48:24.103372 ==
4270 11:48:24.105151 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 11:48:24.108070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 11:48:24.108481 ==
4273 11:48:24.111305 RX Vref Scan: 0
4274 11:48:24.111714
4275 11:48:24.114945 RX Vref 0 -> 0, step: 1
4276 11:48:24.115449
4277 11:48:24.115779 RX Delay -195 -> 252, step: 8
4278 11:48:24.122668 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4279 11:48:24.126891 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4280 11:48:24.129602 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4281 11:48:24.132830 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4282 11:48:24.139799 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4283 11:48:24.142705 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4284 11:48:24.146134 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4285 11:48:24.149906 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4286 11:48:24.152510 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4287 11:48:24.159137 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4288 11:48:24.162241 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4289 11:48:24.165243 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4290 11:48:24.172380 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4291 11:48:24.175575 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4292 11:48:24.178520 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4293 11:48:24.181745 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4294 11:48:24.182200 ==
4295 11:48:24.185107 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 11:48:24.191533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 11:48:24.191952 ==
4298 11:48:24.192280 DQS Delay:
4299 11:48:24.192582 DQS0 = 0, DQS1 = 0
4300 11:48:24.195184 DQM Delay:
4301 11:48:24.195593 DQM0 = 44, DQM1 = 36
4302 11:48:24.198384 DQ Delay:
4303 11:48:24.201655 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4304 11:48:24.205407 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4305 11:48:24.208744 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4306 11:48:24.211899 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4307 11:48:24.212408
4308 11:48:24.212734
4309 11:48:24.218797 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4310 11:48:24.221499 CH0 RK1: MR19=808, MR18=3F3A
4311 11:48:24.228193 CH0_RK1: MR19=0x808, MR18=0x3F3A, DQSOSC=397, MR23=63, INC=166, DEC=110
4312 11:48:24.231653 [RxdqsGatingPostProcess] freq 600
4313 11:48:24.235091 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4314 11:48:24.237928 Pre-setting of DQS Precalculation
4315 11:48:24.244708 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4316 11:48:24.245223 ==
4317 11:48:24.248243 Dram Type= 6, Freq= 0, CH_1, rank 0
4318 11:48:24.250988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:48:24.251401 ==
4320 11:48:24.257910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4321 11:48:24.265442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4322 11:48:24.267886 [CA 0] Center 36 (6~66) winsize 61
4323 11:48:24.270823 [CA 1] Center 35 (5~66) winsize 62
4324 11:48:24.274083 [CA 2] Center 34 (4~65) winsize 62
4325 11:48:24.277658 [CA 3] Center 34 (3~65) winsize 63
4326 11:48:24.280940 [CA 4] Center 34 (4~65) winsize 62
4327 11:48:24.284062 [CA 5] Center 34 (3~65) winsize 63
4328 11:48:24.284521
4329 11:48:24.287711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4330 11:48:24.288170
4331 11:48:24.290963 [CATrainingPosCal] consider 1 rank data
4332 11:48:24.293879 u2DelayCellTimex100 = 270/100 ps
4333 11:48:24.297624 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4334 11:48:24.300468 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4335 11:48:24.304104 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4336 11:48:24.307163 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4337 11:48:24.310573 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4338 11:48:24.313637 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4339 11:48:24.316922
4340 11:48:24.320063 CA PerBit enable=1, Macro0, CA PI delay=34
4341 11:48:24.320520
4342 11:48:24.323629 [CBTSetCACLKResult] CA Dly = 34
4343 11:48:24.324084 CS Dly: 4 (0~35)
4344 11:48:24.324444 ==
4345 11:48:24.326838 Dram Type= 6, Freq= 0, CH_1, rank 1
4346 11:48:24.330214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 11:48:24.333332 ==
4348 11:48:24.336442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 11:48:24.343328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4350 11:48:24.346688 [CA 0] Center 35 (5~66) winsize 62
4351 11:48:24.349809 [CA 1] Center 35 (5~66) winsize 62
4352 11:48:24.353057 [CA 2] Center 34 (4~65) winsize 62
4353 11:48:24.356641 [CA 3] Center 33 (3~64) winsize 62
4354 11:48:24.360112 [CA 4] Center 33 (3~64) winsize 62
4355 11:48:24.362878 [CA 5] Center 34 (3~65) winsize 63
4356 11:48:24.363289
4357 11:48:24.366768 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4358 11:48:24.367299
4359 11:48:24.369842 [CATrainingPosCal] consider 2 rank data
4360 11:48:24.372981 u2DelayCellTimex100 = 270/100 ps
4361 11:48:24.376493 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4362 11:48:24.379269 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 11:48:24.386313 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 11:48:24.389357 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4365 11:48:24.393735 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4366 11:48:24.395934 CA5 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 11:48:24.396347
4368 11:48:24.399435 CA PerBit enable=1, Macro0, CA PI delay=33
4369 11:48:24.399941
4370 11:48:24.402787 [CBTSetCACLKResult] CA Dly = 33
4371 11:48:24.403201 CS Dly: 5 (0~37)
4372 11:48:24.403529
4373 11:48:24.409188 ----->DramcWriteLeveling(PI) begin...
4374 11:48:24.409701 ==
4375 11:48:24.412215 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 11:48:24.416214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 11:48:24.416795 ==
4378 11:48:24.419114 Write leveling (Byte 0): 29 => 29
4379 11:48:24.422146 Write leveling (Byte 1): 30 => 30
4380 11:48:24.425771 DramcWriteLeveling(PI) end<-----
4381 11:48:24.426324
4382 11:48:24.426667 ==
4383 11:48:24.428864 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 11:48:24.431954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 11:48:24.432368 ==
4386 11:48:24.435670 [Gating] SW mode calibration
4387 11:48:24.442325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4388 11:48:24.449011 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4389 11:48:24.452132 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4390 11:48:24.455154 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4391 11:48:24.462393 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4392 11:48:24.465418 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (1 0) (1 0)
4393 11:48:24.468069 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4394 11:48:24.475345 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 11:48:24.479528 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 11:48:24.481643 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 11:48:24.488072 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 11:48:24.491498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 11:48:24.494559 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4400 11:48:24.501518 0 10 12 | B1->B0 | 3030 3636 | 0 0 | (0 0) (0 0)
4401 11:48:24.504252 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4402 11:48:24.507646 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 11:48:24.514039 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 11:48:24.517884 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 11:48:24.521102 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 11:48:24.527661 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 11:48:24.530680 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 11:48:24.534306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4409 11:48:24.541141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4410 11:48:24.543588 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 11:48:24.547061 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 11:48:24.553927 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:48:24.556832 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:48:24.560619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:48:24.566823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:48:24.570315 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:48:24.574318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:48:24.580372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:48:24.584658 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:48:24.586985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:48:24.593316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:48:24.597222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:48:24.600660 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:48:24.606573 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4425 11:48:24.609867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:48:24.612802 Total UI for P1: 0, mck2ui 16
4427 11:48:24.616595 best dqsien dly found for B0: ( 0, 13, 12)
4428 11:48:24.619320 Total UI for P1: 0, mck2ui 16
4429 11:48:24.622643 best dqsien dly found for B1: ( 0, 13, 12)
4430 11:48:24.626017 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4431 11:48:24.629418 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4432 11:48:24.629925
4433 11:48:24.632825 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4434 11:48:24.639093 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4435 11:48:24.639603 [Gating] SW calibration Done
4436 11:48:24.639939 ==
4437 11:48:24.642739 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 11:48:24.649015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 11:48:24.649515 ==
4440 11:48:24.649849 RX Vref Scan: 0
4441 11:48:24.650158
4442 11:48:24.652529 RX Vref 0 -> 0, step: 1
4443 11:48:24.652941
4444 11:48:24.655847 RX Delay -230 -> 252, step: 16
4445 11:48:24.659012 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4446 11:48:24.662054 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4447 11:48:24.668720 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4448 11:48:24.672428 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4449 11:48:24.675714 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4450 11:48:24.679035 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4451 11:48:24.685052 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4452 11:48:24.689161 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4453 11:48:24.692180 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4454 11:48:24.695255 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4455 11:48:24.699033 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4456 11:48:24.705012 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4457 11:48:24.708704 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4458 11:48:24.712318 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4459 11:48:24.715001 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4460 11:48:24.721637 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4461 11:48:24.722103 ==
4462 11:48:24.725461 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 11:48:24.728627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 11:48:24.729140 ==
4465 11:48:24.729474 DQS Delay:
4466 11:48:24.731580 DQS0 = 0, DQS1 = 0
4467 11:48:24.731996 DQM Delay:
4468 11:48:24.734937 DQM0 = 43, DQM1 = 39
4469 11:48:24.735367 DQ Delay:
4470 11:48:24.738176 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4471 11:48:24.742335 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4472 11:48:24.744810 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4473 11:48:24.748201 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4474 11:48:24.748709
4475 11:48:24.749039
4476 11:48:24.749344 ==
4477 11:48:24.751160 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 11:48:24.758229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 11:48:24.758782 ==
4480 11:48:24.759118
4481 11:48:24.759422
4482 11:48:24.759711 TX Vref Scan disable
4483 11:48:24.761897 == TX Byte 0 ==
4484 11:48:24.764589 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4485 11:48:24.771662 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4486 11:48:24.772173 == TX Byte 1 ==
4487 11:48:24.774086 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4488 11:48:24.781087 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4489 11:48:24.781609 ==
4490 11:48:24.784080 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 11:48:24.787554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 11:48:24.788063 ==
4493 11:48:24.788399
4494 11:48:24.788707
4495 11:48:24.791024 TX Vref Scan disable
4496 11:48:24.794387 == TX Byte 0 ==
4497 11:48:24.797718 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4498 11:48:24.800803 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4499 11:48:24.804256 == TX Byte 1 ==
4500 11:48:24.807520 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4501 11:48:24.810851 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4502 11:48:24.811348
4503 11:48:24.811678 [DATLAT]
4504 11:48:24.814352 Freq=600, CH1 RK0
4505 11:48:24.814767
4506 11:48:24.817331 DATLAT Default: 0x9
4507 11:48:24.817909 0, 0xFFFF, sum = 0
4508 11:48:24.821026 1, 0xFFFF, sum = 0
4509 11:48:24.821446 2, 0xFFFF, sum = 0
4510 11:48:24.824292 3, 0xFFFF, sum = 0
4511 11:48:24.824711 4, 0xFFFF, sum = 0
4512 11:48:24.827090 5, 0xFFFF, sum = 0
4513 11:48:24.827509 6, 0xFFFF, sum = 0
4514 11:48:24.830503 7, 0xFFFF, sum = 0
4515 11:48:24.831015 8, 0x0, sum = 1
4516 11:48:24.833954 9, 0x0, sum = 2
4517 11:48:24.834523 10, 0x0, sum = 3
4518 11:48:24.837466 11, 0x0, sum = 4
4519 11:48:24.837982 best_step = 9
4520 11:48:24.838356
4521 11:48:24.838667 ==
4522 11:48:24.839950 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 11:48:24.844112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 11:48:24.844624 ==
4525 11:48:24.847279 RX Vref Scan: 1
4526 11:48:24.847765
4527 11:48:24.850366 RX Vref 0 -> 0, step: 1
4528 11:48:24.850877
4529 11:48:24.854339 RX Delay -179 -> 252, step: 8
4530 11:48:24.854854
4531 11:48:24.857250 Set Vref, RX VrefLevel [Byte0]: 52
4532 11:48:24.860042 [Byte1]: 52
4533 11:48:24.860457
4534 11:48:24.863872 Final RX Vref Byte 0 = 52 to rank0
4535 11:48:24.866769 Final RX Vref Byte 1 = 52 to rank0
4536 11:48:24.870168 Final RX Vref Byte 0 = 52 to rank1
4537 11:48:24.873377 Final RX Vref Byte 1 = 52 to rank1==
4538 11:48:24.876857 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 11:48:24.879761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 11:48:24.880274 ==
4541 11:48:24.883012 DQS Delay:
4542 11:48:24.883423 DQS0 = 0, DQS1 = 0
4543 11:48:24.883753 DQM Delay:
4544 11:48:24.886340 DQM0 = 41, DQM1 = 33
4545 11:48:24.886848 DQ Delay:
4546 11:48:24.889746 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4547 11:48:24.893320 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4548 11:48:24.896229 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4549 11:48:24.899371 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4550 11:48:24.899883
4551 11:48:24.900212
4552 11:48:24.909402 [DQSOSCAuto] RK0, (LSB)MR18= 0x2741, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4553 11:48:24.912874 CH1 RK0: MR19=808, MR18=2741
4554 11:48:24.916264 CH1_RK0: MR19=0x808, MR18=0x2741, DQSOSC=397, MR23=63, INC=166, DEC=110
4555 11:48:24.916778
4556 11:48:24.919370 ----->DramcWriteLeveling(PI) begin...
4557 11:48:24.922658 ==
4558 11:48:24.926244 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 11:48:24.929179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:48:24.929692 ==
4561 11:48:24.932617 Write leveling (Byte 0): 29 => 29
4562 11:48:24.935715 Write leveling (Byte 1): 30 => 30
4563 11:48:24.938758 DramcWriteLeveling(PI) end<-----
4564 11:48:24.939171
4565 11:48:24.939498 ==
4566 11:48:24.942212 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 11:48:24.945535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:48:24.946044 ==
4569 11:48:24.948749 [Gating] SW mode calibration
4570 11:48:24.955250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4571 11:48:24.961969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4572 11:48:24.965061 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4573 11:48:24.968910 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4574 11:48:24.974818 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4575 11:48:24.978037 0 9 12 | B1->B0 | 3131 2c2c | 0 1 | (0 0) (1 0)
4576 11:48:24.981819 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4577 11:48:24.988397 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4578 11:48:24.991377 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 11:48:24.995148 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 11:48:25.001539 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 11:48:25.004620 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 11:48:25.008675 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 11:48:25.014508 0 10 12 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
4584 11:48:25.018309 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4585 11:48:25.021185 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4586 11:48:25.027746 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 11:48:25.031064 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 11:48:25.034307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 11:48:25.040983 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 11:48:25.044485 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4591 11:48:25.047741 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4592 11:48:25.054188 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 11:48:25.057325 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 11:48:25.060565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 11:48:25.067695 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 11:48:25.070214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 11:48:25.073685 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 11:48:25.080372 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 11:48:25.083446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 11:48:25.086639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 11:48:25.093456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 11:48:25.096924 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 11:48:25.100028 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 11:48:25.107001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 11:48:25.110096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 11:48:25.113321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 11:48:25.119814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4608 11:48:25.123139 Total UI for P1: 0, mck2ui 16
4609 11:48:25.126554 best dqsien dly found for B1: ( 0, 13, 10)
4610 11:48:25.129599 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 11:48:25.133416 Total UI for P1: 0, mck2ui 16
4612 11:48:25.136373 best dqsien dly found for B0: ( 0, 13, 12)
4613 11:48:25.139470 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4614 11:48:25.143275 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4615 11:48:25.143826
4616 11:48:25.145769 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4617 11:48:25.153365 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4618 11:48:25.153914 [Gating] SW calibration Done
4619 11:48:25.154315 ==
4620 11:48:25.155842 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 11:48:25.162653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 11:48:25.163220 ==
4623 11:48:25.163589 RX Vref Scan: 0
4624 11:48:25.163929
4625 11:48:25.166368 RX Vref 0 -> 0, step: 1
4626 11:48:25.167007
4627 11:48:25.169541 RX Delay -230 -> 252, step: 16
4628 11:48:25.172412 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4629 11:48:25.175744 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4630 11:48:25.182311 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4631 11:48:25.185924 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4632 11:48:25.188900 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4633 11:48:25.192466 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4634 11:48:25.199649 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4635 11:48:25.202053 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4636 11:48:25.205626 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4637 11:48:25.208573 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4638 11:48:25.212025 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4639 11:48:25.218947 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4640 11:48:25.221903 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4641 11:48:25.225381 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4642 11:48:25.228871 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4643 11:48:25.235193 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4644 11:48:25.235705 ==
4645 11:48:25.238221 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 11:48:25.241224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 11:48:25.241646 ==
4648 11:48:25.244495 DQS Delay:
4649 11:48:25.244906 DQS0 = 0, DQS1 = 0
4650 11:48:25.245236 DQM Delay:
4651 11:48:25.248566 DQM0 = 45, DQM1 = 42
4652 11:48:25.249072 DQ Delay:
4653 11:48:25.251243 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4654 11:48:25.254948 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4655 11:48:25.257830 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4656 11:48:25.261426 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4657 11:48:25.261843
4658 11:48:25.262171
4659 11:48:25.262511 ==
4660 11:48:25.265068 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 11:48:25.270999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 11:48:25.271536 ==
4663 11:48:25.271882
4664 11:48:25.272184
4665 11:48:25.272475 TX Vref Scan disable
4666 11:48:25.274818 == TX Byte 0 ==
4667 11:48:25.277826 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4668 11:48:25.284514 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4669 11:48:25.285023 == TX Byte 1 ==
4670 11:48:25.288039 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4671 11:48:25.294489 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4672 11:48:25.294996 ==
4673 11:48:25.298207 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 11:48:25.301568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 11:48:25.302079 ==
4676 11:48:25.302481
4677 11:48:25.302795
4678 11:48:25.304118 TX Vref Scan disable
4679 11:48:25.307734 == TX Byte 0 ==
4680 11:48:25.310954 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4681 11:48:25.314165 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4682 11:48:25.318087 == TX Byte 1 ==
4683 11:48:25.320486 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4684 11:48:25.323771 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4685 11:48:25.324186
4686 11:48:25.327811 [DATLAT]
4687 11:48:25.328321 Freq=600, CH1 RK1
4688 11:48:25.328657
4689 11:48:25.330500 DATLAT Default: 0x9
4690 11:48:25.330918 0, 0xFFFF, sum = 0
4691 11:48:25.333768 1, 0xFFFF, sum = 0
4692 11:48:25.334186 2, 0xFFFF, sum = 0
4693 11:48:25.337472 3, 0xFFFF, sum = 0
4694 11:48:25.337894 4, 0xFFFF, sum = 0
4695 11:48:25.340264 5, 0xFFFF, sum = 0
4696 11:48:25.340686 6, 0xFFFF, sum = 0
4697 11:48:25.344026 7, 0xFFFF, sum = 0
4698 11:48:25.344540 8, 0x0, sum = 1
4699 11:48:25.346919 9, 0x0, sum = 2
4700 11:48:25.347344 10, 0x0, sum = 3
4701 11:48:25.350818 11, 0x0, sum = 4
4702 11:48:25.351239 best_step = 9
4703 11:48:25.351564
4704 11:48:25.351868 ==
4705 11:48:25.354015 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 11:48:25.357104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 11:48:25.357523 ==
4708 11:48:25.360149 RX Vref Scan: 0
4709 11:48:25.360565
4710 11:48:25.364180 RX Vref 0 -> 0, step: 1
4711 11:48:25.364689
4712 11:48:25.365020 RX Delay -179 -> 252, step: 8
4713 11:48:25.371519 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4714 11:48:25.374842 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4715 11:48:25.378231 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4716 11:48:25.381557 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4717 11:48:25.387928 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4718 11:48:25.391299 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4719 11:48:25.394754 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4720 11:48:25.397819 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4721 11:48:25.404782 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4722 11:48:25.408258 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4723 11:48:25.410948 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4724 11:48:25.414444 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4725 11:48:25.421209 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4726 11:48:25.424286 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4727 11:48:25.427368 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4728 11:48:25.430934 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4729 11:48:25.431570 ==
4730 11:48:25.434013 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 11:48:25.440730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 11:48:25.441145 ==
4733 11:48:25.441499 DQS Delay:
4734 11:48:25.444000 DQS0 = 0, DQS1 = 0
4735 11:48:25.444454 DQM Delay:
4736 11:48:25.444786 DQM0 = 37, DQM1 = 34
4737 11:48:25.447319 DQ Delay:
4738 11:48:25.450572 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4739 11:48:25.454055 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4740 11:48:25.457326 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4741 11:48:25.460497 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4742 11:48:25.460909
4743 11:48:25.461237
4744 11:48:25.467495 [DQSOSCAuto] RK1, (LSB)MR18= 0x3358, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4745 11:48:25.470989 CH1 RK1: MR19=808, MR18=3358
4746 11:48:25.477134 CH1_RK1: MR19=0x808, MR18=0x3358, DQSOSC=393, MR23=63, INC=169, DEC=113
4747 11:48:25.480583 [RxdqsGatingPostProcess] freq 600
4748 11:48:25.486792 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4749 11:48:25.487210 Pre-setting of DQS Precalculation
4750 11:48:25.493514 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4751 11:48:25.500187 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4752 11:48:25.506609 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4753 11:48:25.507110
4754 11:48:25.507439
4755 11:48:25.510693 [Calibration Summary] 1200 Mbps
4756 11:48:25.513231 CH 0, Rank 0
4757 11:48:25.513645 SW Impedance : PASS
4758 11:48:25.516914 DUTY Scan : NO K
4759 11:48:25.519985 ZQ Calibration : PASS
4760 11:48:25.520400 Jitter Meter : NO K
4761 11:48:25.522905 CBT Training : PASS
4762 11:48:25.523320 Write leveling : PASS
4763 11:48:25.526395 RX DQS gating : PASS
4764 11:48:25.530161 RX DQ/DQS(RDDQC) : PASS
4765 11:48:25.530727 TX DQ/DQS : PASS
4766 11:48:25.533618 RX DATLAT : PASS
4767 11:48:25.537035 RX DQ/DQS(Engine): PASS
4768 11:48:25.537553 TX OE : NO K
4769 11:48:25.539768 All Pass.
4770 11:48:25.540181
4771 11:48:25.540508 CH 0, Rank 1
4772 11:48:25.543170 SW Impedance : PASS
4773 11:48:25.543688 DUTY Scan : NO K
4774 11:48:25.546763 ZQ Calibration : PASS
4775 11:48:25.549747 Jitter Meter : NO K
4776 11:48:25.550365 CBT Training : PASS
4777 11:48:25.553317 Write leveling : PASS
4778 11:48:25.556507 RX DQS gating : PASS
4779 11:48:25.556972 RX DQ/DQS(RDDQC) : PASS
4780 11:48:25.559708 TX DQ/DQS : PASS
4781 11:48:25.562811 RX DATLAT : PASS
4782 11:48:25.563377 RX DQ/DQS(Engine): PASS
4783 11:48:25.566491 TX OE : NO K
4784 11:48:25.567054 All Pass.
4785 11:48:25.567427
4786 11:48:25.569671 CH 1, Rank 0
4787 11:48:25.570231 SW Impedance : PASS
4788 11:48:25.572382 DUTY Scan : NO K
4789 11:48:25.575477 ZQ Calibration : PASS
4790 11:48:25.575937 Jitter Meter : NO K
4791 11:48:25.579403 CBT Training : PASS
4792 11:48:25.582233 Write leveling : PASS
4793 11:48:25.582729 RX DQS gating : PASS
4794 11:48:25.585682 RX DQ/DQS(RDDQC) : PASS
4795 11:48:25.589381 TX DQ/DQS : PASS
4796 11:48:25.589946 RX DATLAT : PASS
4797 11:48:25.592165 RX DQ/DQS(Engine): PASS
4798 11:48:25.596077 TX OE : NO K
4799 11:48:25.596644 All Pass.
4800 11:48:25.597014
4801 11:48:25.597352 CH 1, Rank 1
4802 11:48:25.598450 SW Impedance : PASS
4803 11:48:25.602177 DUTY Scan : NO K
4804 11:48:25.602691 ZQ Calibration : PASS
4805 11:48:25.605454 Jitter Meter : NO K
4806 11:48:25.608544 CBT Training : PASS
4807 11:48:25.609107 Write leveling : PASS
4808 11:48:25.611908 RX DQS gating : PASS
4809 11:48:25.615521 RX DQ/DQS(RDDQC) : PASS
4810 11:48:25.615985 TX DQ/DQS : PASS
4811 11:48:25.618145 RX DATLAT : PASS
4812 11:48:25.622031 RX DQ/DQS(Engine): PASS
4813 11:48:25.622642 TX OE : NO K
4814 11:48:25.623083 All Pass.
4815 11:48:25.624946
4816 11:48:25.625405 DramC Write-DBI off
4817 11:48:25.629197 PER_BANK_REFRESH: Hybrid Mode
4818 11:48:25.629761 TX_TRACKING: ON
4819 11:48:25.638305 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4820 11:48:25.641487 [FAST_K] Save calibration result to emmc
4821 11:48:25.645025 dramc_set_vcore_voltage set vcore to 662500
4822 11:48:25.648296 Read voltage for 933, 3
4823 11:48:25.648859 Vio18 = 0
4824 11:48:25.651760 Vcore = 662500
4825 11:48:25.652237 Vdram = 0
4826 11:48:25.652608 Vddq = 0
4827 11:48:25.652950 Vmddr = 0
4828 11:48:25.658136 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4829 11:48:25.664687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4830 11:48:25.665241 MEM_TYPE=3, freq_sel=17
4831 11:48:25.667966 sv_algorithm_assistance_LP4_1600
4832 11:48:25.671125 ============ PULL DRAM RESETB DOWN ============
4833 11:48:25.677733 ========== PULL DRAM RESETB DOWN end =========
4834 11:48:25.681638 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4835 11:48:25.684027 ===================================
4836 11:48:25.687261 LPDDR4 DRAM CONFIGURATION
4837 11:48:25.690991 ===================================
4838 11:48:25.691541 EX_ROW_EN[0] = 0x0
4839 11:48:25.694454 EX_ROW_EN[1] = 0x0
4840 11:48:25.697521 LP4Y_EN = 0x0
4841 11:48:25.698076 WORK_FSP = 0x0
4842 11:48:25.700412 WL = 0x3
4843 11:48:25.700871 RL = 0x3
4844 11:48:25.704227 BL = 0x2
4845 11:48:25.704777 RPST = 0x0
4846 11:48:25.707356 RD_PRE = 0x0
4847 11:48:25.707908 WR_PRE = 0x1
4848 11:48:25.710725 WR_PST = 0x0
4849 11:48:25.711276 DBI_WR = 0x0
4850 11:48:25.713981 DBI_RD = 0x0
4851 11:48:25.714475 OTF = 0x1
4852 11:48:25.717274 ===================================
4853 11:48:25.720386 ===================================
4854 11:48:25.723832 ANA top config
4855 11:48:25.726824 ===================================
4856 11:48:25.730505 DLL_ASYNC_EN = 0
4857 11:48:25.730969 ALL_SLAVE_EN = 1
4858 11:48:25.733471 NEW_RANK_MODE = 1
4859 11:48:25.737053 DLL_IDLE_MODE = 1
4860 11:48:25.740562 LP45_APHY_COMB_EN = 1
4861 11:48:25.741078 TX_ODT_DIS = 1
4862 11:48:25.743834 NEW_8X_MODE = 1
4863 11:48:25.747051 ===================================
4864 11:48:25.750399 ===================================
4865 11:48:25.753320 data_rate = 1866
4866 11:48:25.756863 CKR = 1
4867 11:48:25.760447 DQ_P2S_RATIO = 8
4868 11:48:25.762993 ===================================
4869 11:48:25.766924 CA_P2S_RATIO = 8
4870 11:48:25.769882 DQ_CA_OPEN = 0
4871 11:48:25.770465 DQ_SEMI_OPEN = 0
4872 11:48:25.773341 CA_SEMI_OPEN = 0
4873 11:48:25.776878 CA_FULL_RATE = 0
4874 11:48:25.780498 DQ_CKDIV4_EN = 1
4875 11:48:25.782787 CA_CKDIV4_EN = 1
4876 11:48:25.786551 CA_PREDIV_EN = 0
4877 11:48:25.787115 PH8_DLY = 0
4878 11:48:25.789715 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4879 11:48:25.792884 DQ_AAMCK_DIV = 4
4880 11:48:25.795948 CA_AAMCK_DIV = 4
4881 11:48:25.799180 CA_ADMCK_DIV = 4
4882 11:48:25.802387 DQ_TRACK_CA_EN = 0
4883 11:48:25.805833 CA_PICK = 933
4884 11:48:25.806437 CA_MCKIO = 933
4885 11:48:25.809254 MCKIO_SEMI = 0
4886 11:48:25.812599 PLL_FREQ = 3732
4887 11:48:25.815434 DQ_UI_PI_RATIO = 32
4888 11:48:25.819013 CA_UI_PI_RATIO = 0
4889 11:48:25.822434 ===================================
4890 11:48:25.825952 ===================================
4891 11:48:25.828664 memory_type:LPDDR4
4892 11:48:25.829121 GP_NUM : 10
4893 11:48:25.832143 SRAM_EN : 1
4894 11:48:25.832698 MD32_EN : 0
4895 11:48:25.835163 ===================================
4896 11:48:25.838601 [ANA_INIT] >>>>>>>>>>>>>>
4897 11:48:25.842423 <<<<<< [CONFIGURE PHASE]: ANA_TX
4898 11:48:25.844940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4899 11:48:25.848635 ===================================
4900 11:48:25.851991 data_rate = 1866,PCW = 0X8f00
4901 11:48:25.854854 ===================================
4902 11:48:25.858341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4903 11:48:25.865089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4904 11:48:25.868304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4905 11:48:25.875277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4906 11:48:25.878334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4907 11:48:25.881864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4908 11:48:25.882444 [ANA_INIT] flow start
4909 11:48:25.884438 [ANA_INIT] PLL >>>>>>>>
4910 11:48:25.888466 [ANA_INIT] PLL <<<<<<<<
4911 11:48:25.891836 [ANA_INIT] MIDPI >>>>>>>>
4912 11:48:25.892341 [ANA_INIT] MIDPI <<<<<<<<
4913 11:48:25.894671 [ANA_INIT] DLL >>>>>>>>
4914 11:48:25.895078 [ANA_INIT] flow end
4915 11:48:25.901030 ============ LP4 DIFF to SE enter ============
4916 11:48:25.905094 ============ LP4 DIFF to SE exit ============
4917 11:48:25.907888 [ANA_INIT] <<<<<<<<<<<<<
4918 11:48:25.910951 [Flow] Enable top DCM control >>>>>
4919 11:48:25.914420 [Flow] Enable top DCM control <<<<<
4920 11:48:25.918061 Enable DLL master slave shuffle
4921 11:48:25.921459 ==============================================================
4922 11:48:25.924933 Gating Mode config
4923 11:48:25.931172 ==============================================================
4924 11:48:25.931713 Config description:
4925 11:48:25.940979 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4926 11:48:25.947401 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4927 11:48:25.951378 SELPH_MODE 0: By rank 1: By Phase
4928 11:48:25.957447 ==============================================================
4929 11:48:25.960374 GAT_TRACK_EN = 1
4930 11:48:25.963826 RX_GATING_MODE = 2
4931 11:48:25.967279 RX_GATING_TRACK_MODE = 2
4932 11:48:25.970644 SELPH_MODE = 1
4933 11:48:25.974318 PICG_EARLY_EN = 1
4934 11:48:25.976857 VALID_LAT_VALUE = 1
4935 11:48:25.980269 ==============================================================
4936 11:48:25.983565 Enter into Gating configuration >>>>
4937 11:48:25.986867 Exit from Gating configuration <<<<
4938 11:48:25.990645 Enter into DVFS_PRE_config >>>>>
4939 11:48:26.003191 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4940 11:48:26.007203 Exit from DVFS_PRE_config <<<<<
4941 11:48:26.009873 Enter into PICG configuration >>>>
4942 11:48:26.013110 Exit from PICG configuration <<<<
4943 11:48:26.013664 [RX_INPUT] configuration >>>>>
4944 11:48:26.016422 [RX_INPUT] configuration <<<<<
4945 11:48:26.022779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4946 11:48:26.026385 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4947 11:48:26.033112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4948 11:48:26.038948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4949 11:48:26.046301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4950 11:48:26.053069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4951 11:48:26.055855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4952 11:48:26.059155 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4953 11:48:26.065917 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4954 11:48:26.069137 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4955 11:48:26.073017 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4956 11:48:26.079143 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4957 11:48:26.082437 ===================================
4958 11:48:26.082988 LPDDR4 DRAM CONFIGURATION
4959 11:48:26.085363 ===================================
4960 11:48:26.088556 EX_ROW_EN[0] = 0x0
4961 11:48:26.089018 EX_ROW_EN[1] = 0x0
4962 11:48:26.091929 LP4Y_EN = 0x0
4963 11:48:26.095380 WORK_FSP = 0x0
4964 11:48:26.095943 WL = 0x3
4965 11:48:26.098549 RL = 0x3
4966 11:48:26.099105 BL = 0x2
4967 11:48:26.102119 RPST = 0x0
4968 11:48:26.102632 RD_PRE = 0x0
4969 11:48:26.105600 WR_PRE = 0x1
4970 11:48:26.106166 WR_PST = 0x0
4971 11:48:26.108317 DBI_WR = 0x0
4972 11:48:26.108778 DBI_RD = 0x0
4973 11:48:26.112051 OTF = 0x1
4974 11:48:26.114904 ===================================
4975 11:48:26.118059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4976 11:48:26.122035 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4977 11:48:26.128316 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 11:48:26.131747 ===================================
4979 11:48:26.132301 LPDDR4 DRAM CONFIGURATION
4980 11:48:26.135459 ===================================
4981 11:48:26.137816 EX_ROW_EN[0] = 0x10
4982 11:48:26.141516 EX_ROW_EN[1] = 0x0
4983 11:48:26.142068 LP4Y_EN = 0x0
4984 11:48:26.145417 WORK_FSP = 0x0
4985 11:48:26.145965 WL = 0x3
4986 11:48:26.148066 RL = 0x3
4987 11:48:26.148527 BL = 0x2
4988 11:48:26.151224 RPST = 0x0
4989 11:48:26.151687 RD_PRE = 0x0
4990 11:48:26.154685 WR_PRE = 0x1
4991 11:48:26.155237 WR_PST = 0x0
4992 11:48:26.157663 DBI_WR = 0x0
4993 11:48:26.158124 DBI_RD = 0x0
4994 11:48:26.161685 OTF = 0x1
4995 11:48:26.164526 ===================================
4996 11:48:26.170907 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4997 11:48:26.174493 nWR fixed to 30
4998 11:48:26.177174 [ModeRegInit_LP4] CH0 RK0
4999 11:48:26.177718 [ModeRegInit_LP4] CH0 RK1
5000 11:48:26.180531 [ModeRegInit_LP4] CH1 RK0
5001 11:48:26.183904 [ModeRegInit_LP4] CH1 RK1
5002 11:48:26.184450 match AC timing 9
5003 11:48:26.190610 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5004 11:48:26.194234 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5005 11:48:26.197627 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5006 11:48:26.203540 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5007 11:48:26.207371 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5008 11:48:26.207834 ==
5009 11:48:26.211125 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 11:48:26.213575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5011 11:48:26.214129 ==
5012 11:48:26.220522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5013 11:48:26.227195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5014 11:48:26.230944 [CA 0] Center 38 (7~69) winsize 63
5015 11:48:26.233423 [CA 1] Center 37 (7~68) winsize 62
5016 11:48:26.237118 [CA 2] Center 34 (4~65) winsize 62
5017 11:48:26.240591 [CA 3] Center 34 (4~65) winsize 62
5018 11:48:26.243171 [CA 4] Center 33 (3~64) winsize 62
5019 11:48:26.246695 [CA 5] Center 33 (3~63) winsize 61
5020 11:48:26.247246
5021 11:48:26.249977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5022 11:48:26.250570
5023 11:48:26.253658 [CATrainingPosCal] consider 1 rank data
5024 11:48:26.256853 u2DelayCellTimex100 = 270/100 ps
5025 11:48:26.260038 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5026 11:48:26.263263 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5027 11:48:26.266709 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5028 11:48:26.270035 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5029 11:48:26.273632 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5030 11:48:26.280047 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5031 11:48:26.280601
5032 11:48:26.282925 CA PerBit enable=1, Macro0, CA PI delay=33
5033 11:48:26.283491
5034 11:48:26.285948 [CBTSetCACLKResult] CA Dly = 33
5035 11:48:26.286538 CS Dly: 5 (0~36)
5036 11:48:26.286915 ==
5037 11:48:26.289536 Dram Type= 6, Freq= 0, CH_0, rank 1
5038 11:48:26.296356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 11:48:26.296910 ==
5040 11:48:26.299285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 11:48:26.305865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5042 11:48:26.309212 [CA 0] Center 38 (7~69) winsize 63
5043 11:48:26.312690 [CA 1] Center 38 (7~69) winsize 63
5044 11:48:26.315798 [CA 2] Center 34 (4~65) winsize 62
5045 11:48:26.318786 [CA 3] Center 34 (4~65) winsize 62
5046 11:48:26.322446 [CA 4] Center 33 (3~64) winsize 62
5047 11:48:26.325925 [CA 5] Center 32 (2~63) winsize 62
5048 11:48:26.326518
5049 11:48:26.328869 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5050 11:48:26.329421
5051 11:48:26.332173 [CATrainingPosCal] consider 2 rank data
5052 11:48:26.336618 u2DelayCellTimex100 = 270/100 ps
5053 11:48:26.338736 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5054 11:48:26.345440 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5055 11:48:26.348552 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 11:48:26.352002 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5057 11:48:26.355291 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5058 11:48:26.358752 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5059 11:48:26.359386
5060 11:48:26.361988 CA PerBit enable=1, Macro0, CA PI delay=33
5061 11:48:26.362581
5062 11:48:26.365900 [CBTSetCACLKResult] CA Dly = 33
5063 11:48:26.366503 CS Dly: 6 (0~39)
5064 11:48:26.369053
5065 11:48:26.371840 ----->DramcWriteLeveling(PI) begin...
5066 11:48:26.372400 ==
5067 11:48:26.375474 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 11:48:26.378565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 11:48:26.379116 ==
5070 11:48:26.381797 Write leveling (Byte 0): 28 => 28
5071 11:48:26.385428 Write leveling (Byte 1): 27 => 27
5072 11:48:26.388626 DramcWriteLeveling(PI) end<-----
5073 11:48:26.389120
5074 11:48:26.389481 ==
5075 11:48:26.391269 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 11:48:26.394619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 11:48:26.395179 ==
5078 11:48:26.398157 [Gating] SW mode calibration
5079 11:48:26.404819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5080 11:48:26.411091 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5081 11:48:26.414479 0 14 0 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
5082 11:48:26.417539 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5083 11:48:26.424255 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5084 11:48:26.427439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 11:48:26.431308 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 11:48:26.437773 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 11:48:26.440957 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5088 11:48:26.444043 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 1)
5089 11:48:26.450900 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5090 11:48:26.453905 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5091 11:48:26.457136 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5092 11:48:26.463811 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 11:48:26.467187 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 11:48:26.470036 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 11:48:26.476868 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5096 11:48:26.480335 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5097 11:48:26.483564 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5098 11:48:26.489985 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5099 11:48:26.493063 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 11:48:26.496759 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 11:48:26.503701 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 11:48:26.506774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 11:48:26.510063 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 11:48:26.516119 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5105 11:48:26.519821 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5106 11:48:26.522882 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 11:48:26.529216 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 11:48:26.532521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 11:48:26.536288 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:48:26.542841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:48:26.545804 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:48:26.549225 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 11:48:26.555509 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:48:26.559637 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:48:26.562324 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:48:26.568997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:48:26.572967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:48:26.578972 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:48:26.582211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:48:26.586037 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5121 11:48:26.589206 Total UI for P1: 0, mck2ui 16
5122 11:48:26.592613 best dqsien dly found for B0: ( 1, 2, 26)
5123 11:48:26.595431 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5124 11:48:26.602048 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:48:26.605398 Total UI for P1: 0, mck2ui 16
5126 11:48:26.608657 best dqsien dly found for B1: ( 1, 3, 0)
5127 11:48:26.611663 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5128 11:48:26.614948 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5129 11:48:26.615504
5130 11:48:26.618620 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5131 11:48:26.621519 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5132 11:48:26.624697 [Gating] SW calibration Done
5133 11:48:26.625160 ==
5134 11:48:26.628032 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 11:48:26.632041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 11:48:26.632597 ==
5137 11:48:26.634959 RX Vref Scan: 0
5138 11:48:26.635417
5139 11:48:26.638111 RX Vref 0 -> 0, step: 1
5140 11:48:26.638568
5141 11:48:26.638902 RX Delay -80 -> 252, step: 8
5142 11:48:26.644865 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5143 11:48:26.647702 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5144 11:48:26.651049 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5145 11:48:26.654982 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5146 11:48:26.658219 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5147 11:48:26.661582 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5148 11:48:26.668071 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5149 11:48:26.671206 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5150 11:48:26.674841 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5151 11:48:26.677637 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5152 11:48:26.684573 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5153 11:48:26.687254 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5154 11:48:26.690933 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5155 11:48:26.693977 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5156 11:48:26.697707 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5157 11:48:26.700764 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5158 11:48:26.704018 ==
5159 11:48:26.706920 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 11:48:26.710668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 11:48:26.711115 ==
5162 11:48:26.711443 DQS Delay:
5163 11:48:26.714277 DQS0 = 0, DQS1 = 0
5164 11:48:26.714794 DQM Delay:
5165 11:48:26.717340 DQM0 = 101, DQM1 = 87
5166 11:48:26.717755 DQ Delay:
5167 11:48:26.720055 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =99
5168 11:48:26.723650 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5169 11:48:26.727039 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5170 11:48:26.730421 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5171 11:48:26.730925
5172 11:48:26.731260
5173 11:48:26.731568 ==
5174 11:48:26.733667 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 11:48:26.736982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 11:48:26.737496 ==
5177 11:48:26.740200
5178 11:48:26.740697
5179 11:48:26.741032 TX Vref Scan disable
5180 11:48:26.743630 == TX Byte 0 ==
5181 11:48:26.746744 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5182 11:48:26.750184 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5183 11:48:26.753544 == TX Byte 1 ==
5184 11:48:26.757489 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5185 11:48:26.760251 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5186 11:48:26.763219 ==
5187 11:48:26.763700 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 11:48:26.770030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 11:48:26.770580 ==
5190 11:48:26.770918
5191 11:48:26.771222
5192 11:48:26.773218 TX Vref Scan disable
5193 11:48:26.773743 == TX Byte 0 ==
5194 11:48:26.779922 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5195 11:48:26.783672 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5196 11:48:26.784130 == TX Byte 1 ==
5197 11:48:26.790129 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5198 11:48:26.793229 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5199 11:48:26.793648
5200 11:48:26.793979 [DATLAT]
5201 11:48:26.796266 Freq=933, CH0 RK0
5202 11:48:26.796680
5203 11:48:26.797007 DATLAT Default: 0xd
5204 11:48:26.800094 0, 0xFFFF, sum = 0
5205 11:48:26.800607 1, 0xFFFF, sum = 0
5206 11:48:26.803108 2, 0xFFFF, sum = 0
5207 11:48:26.803530 3, 0xFFFF, sum = 0
5208 11:48:26.806296 4, 0xFFFF, sum = 0
5209 11:48:26.806735 5, 0xFFFF, sum = 0
5210 11:48:26.810574 6, 0xFFFF, sum = 0
5211 11:48:26.811005 7, 0xFFFF, sum = 0
5212 11:48:26.812779 8, 0xFFFF, sum = 0
5213 11:48:26.816419 9, 0xFFFF, sum = 0
5214 11:48:26.816939 10, 0x0, sum = 1
5215 11:48:26.817283 11, 0x0, sum = 2
5216 11:48:26.819594 12, 0x0, sum = 3
5217 11:48:26.820065 13, 0x0, sum = 4
5218 11:48:26.822631 best_step = 11
5219 11:48:26.823048
5220 11:48:26.823502 ==
5221 11:48:26.826247 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 11:48:26.829498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 11:48:26.830011 ==
5224 11:48:26.832877 RX Vref Scan: 1
5225 11:48:26.833382
5226 11:48:26.833719 RX Vref 0 -> 0, step: 1
5227 11:48:26.836166
5228 11:48:26.836713 RX Delay -69 -> 252, step: 4
5229 11:48:26.837087
5230 11:48:26.839176 Set Vref, RX VrefLevel [Byte0]: 55
5231 11:48:26.842418 [Byte1]: 50
5232 11:48:26.847474
5233 11:48:26.848021 Final RX Vref Byte 0 = 55 to rank0
5234 11:48:26.850380 Final RX Vref Byte 1 = 50 to rank0
5235 11:48:26.853972 Final RX Vref Byte 0 = 55 to rank1
5236 11:48:26.857257 Final RX Vref Byte 1 = 50 to rank1==
5237 11:48:26.860147 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:48:26.866875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:48:26.867429 ==
5240 11:48:26.867803 DQS Delay:
5241 11:48:26.869981 DQS0 = 0, DQS1 = 0
5242 11:48:26.870482 DQM Delay:
5243 11:48:26.870851 DQM0 = 102, DQM1 = 91
5244 11:48:26.873460 DQ Delay:
5245 11:48:26.876517 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5246 11:48:26.879804 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =106
5247 11:48:26.883003 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =86
5248 11:48:26.886247 DQ12 =98, DQ13 =92, DQ14 =100, DQ15 =98
5249 11:48:26.886844
5250 11:48:26.887218
5251 11:48:26.893536 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5252 11:48:26.896084 CH0 RK0: MR19=505, MR18=1A14
5253 11:48:26.902891 CH0_RK0: MR19=0x505, MR18=0x1A14, DQSOSC=413, MR23=63, INC=63, DEC=42
5254 11:48:26.903457
5255 11:48:26.906149 ----->DramcWriteLeveling(PI) begin...
5256 11:48:26.906819 ==
5257 11:48:26.909519 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 11:48:26.916197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:48:26.916753 ==
5260 11:48:26.919253 Write leveling (Byte 0): 33 => 33
5261 11:48:26.919714 Write leveling (Byte 1): 27 => 27
5262 11:48:26.922290 DramcWriteLeveling(PI) end<-----
5263 11:48:26.922750
5264 11:48:26.925839 ==
5265 11:48:26.926346 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 11:48:26.933359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:48:26.933911 ==
5268 11:48:26.935644 [Gating] SW mode calibration
5269 11:48:26.942181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5270 11:48:26.946215 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5271 11:48:26.952721 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5272 11:48:26.955692 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
5273 11:48:26.959243 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5274 11:48:26.966400 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 11:48:26.968769 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 11:48:26.972176 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 11:48:26.978521 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5278 11:48:26.982169 0 14 28 | B1->B0 | 3232 2727 | 0 0 | (0 1) (1 1)
5279 11:48:26.985423 0 15 0 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
5280 11:48:26.991944 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5281 11:48:26.995011 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5282 11:48:26.998869 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 11:48:27.005372 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 11:48:27.008133 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 11:48:27.011493 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5286 11:48:27.018121 0 15 28 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
5287 11:48:27.021270 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5288 11:48:27.024936 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5289 11:48:27.031046 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5290 11:48:27.034644 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 11:48:27.038075 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 11:48:27.043973 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 11:48:27.047840 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5294 11:48:27.050904 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5295 11:48:27.057560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5296 11:48:27.060339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 11:48:27.064052 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 11:48:27.071041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 11:48:27.074459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 11:48:27.077321 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 11:48:27.084078 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 11:48:27.086753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 11:48:27.089973 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 11:48:27.097191 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 11:48:27.100139 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 11:48:27.103688 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 11:48:27.110022 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 11:48:27.113517 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 11:48:27.116593 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5310 11:48:27.122974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5311 11:48:27.126354 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5312 11:48:27.130011 Total UI for P1: 0, mck2ui 16
5313 11:48:27.133402 best dqsien dly found for B0: ( 1, 2, 26)
5314 11:48:27.136160 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 11:48:27.140260 Total UI for P1: 0, mck2ui 16
5316 11:48:27.142960 best dqsien dly found for B1: ( 1, 3, 0)
5317 11:48:27.146415 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5318 11:48:27.152894 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5319 11:48:27.153397
5320 11:48:27.156142 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5321 11:48:27.159389 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5322 11:48:27.162950 [Gating] SW calibration Done
5323 11:48:27.163457 ==
5324 11:48:27.165914 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 11:48:27.169658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:48:27.170168 ==
5327 11:48:27.172658 RX Vref Scan: 0
5328 11:48:27.173163
5329 11:48:27.173501 RX Vref 0 -> 0, step: 1
5330 11:48:27.173815
5331 11:48:27.175782 RX Delay -80 -> 252, step: 8
5332 11:48:27.179361 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5333 11:48:27.182440 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5334 11:48:27.189425 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5335 11:48:27.192242 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5336 11:48:27.195410 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5337 11:48:27.199167 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5338 11:48:27.202322 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5339 11:48:27.208374 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5340 11:48:27.211523 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5341 11:48:27.215318 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5342 11:48:27.218598 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5343 11:48:27.221732 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5344 11:48:27.224994 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5345 11:48:27.231396 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5346 11:48:27.235058 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5347 11:48:27.238537 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5348 11:48:27.238958 ==
5349 11:48:27.241549 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 11:48:27.244744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 11:48:27.245256 ==
5352 11:48:27.248027 DQS Delay:
5353 11:48:27.248446 DQS0 = 0, DQS1 = 0
5354 11:48:27.251309 DQM Delay:
5355 11:48:27.251730 DQM0 = 100, DQM1 = 89
5356 11:48:27.254889 DQ Delay:
5357 11:48:27.255393 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5358 11:48:27.261289 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5359 11:48:27.265151 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5360 11:48:27.267662 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5361 11:48:27.268174
5362 11:48:27.268513
5363 11:48:27.268821 ==
5364 11:48:27.271087 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 11:48:27.274048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 11:48:27.274561 ==
5367 11:48:27.274907
5368 11:48:27.275219
5369 11:48:27.277950 TX Vref Scan disable
5370 11:48:27.278496 == TX Byte 0 ==
5371 11:48:27.284530 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5372 11:48:27.287281 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5373 11:48:27.287706 == TX Byte 1 ==
5374 11:48:27.293973 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5375 11:48:27.297411 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5376 11:48:27.297919 ==
5377 11:48:27.300994 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 11:48:27.304292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 11:48:27.304720 ==
5380 11:48:27.307374
5381 11:48:27.307886
5382 11:48:27.308228 TX Vref Scan disable
5383 11:48:27.310373 == TX Byte 0 ==
5384 11:48:27.314102 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5385 11:48:27.321117 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5386 11:48:27.321624 == TX Byte 1 ==
5387 11:48:27.323469 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5388 11:48:27.330639 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5389 11:48:27.331159
5390 11:48:27.331498 [DATLAT]
5391 11:48:27.331811 Freq=933, CH0 RK1
5392 11:48:27.332113
5393 11:48:27.334052 DATLAT Default: 0xb
5394 11:48:27.337295 0, 0xFFFF, sum = 0
5395 11:48:27.337805 1, 0xFFFF, sum = 0
5396 11:48:27.339999 2, 0xFFFF, sum = 0
5397 11:48:27.340455 3, 0xFFFF, sum = 0
5398 11:48:27.343276 4, 0xFFFF, sum = 0
5399 11:48:27.343706 5, 0xFFFF, sum = 0
5400 11:48:27.347140 6, 0xFFFF, sum = 0
5401 11:48:27.347653 7, 0xFFFF, sum = 0
5402 11:48:27.350193 8, 0xFFFF, sum = 0
5403 11:48:27.350937 9, 0xFFFF, sum = 0
5404 11:48:27.353769 10, 0x0, sum = 1
5405 11:48:27.354327 11, 0x0, sum = 2
5406 11:48:27.357101 12, 0x0, sum = 3
5407 11:48:27.357621 13, 0x0, sum = 4
5408 11:48:27.360288 best_step = 11
5409 11:48:27.360708
5410 11:48:27.361046 ==
5411 11:48:27.363507 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 11:48:27.366992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 11:48:27.367505 ==
5414 11:48:27.367841 RX Vref Scan: 0
5415 11:48:27.368155
5416 11:48:27.370124 RX Vref 0 -> 0, step: 1
5417 11:48:27.370681
5418 11:48:27.373318 RX Delay -61 -> 252, step: 4
5419 11:48:27.380329 iDelay=195, Bit 0, Center 102 (19 ~ 186) 168
5420 11:48:27.383487 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5421 11:48:27.386421 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5422 11:48:27.390100 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5423 11:48:27.393122 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5424 11:48:27.400016 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5425 11:48:27.403089 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5426 11:48:27.405886 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5427 11:48:27.409257 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5428 11:48:27.412769 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5429 11:48:27.419592 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5430 11:48:27.422289 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5431 11:48:27.425886 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5432 11:48:27.429432 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5433 11:48:27.432627 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5434 11:48:27.439211 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5435 11:48:27.439808 ==
5436 11:48:27.442054 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 11:48:27.445935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 11:48:27.446550 ==
5439 11:48:27.446925 DQS Delay:
5440 11:48:27.449156 DQS0 = 0, DQS1 = 0
5441 11:48:27.449618 DQM Delay:
5442 11:48:27.453222 DQM0 = 101, DQM1 = 90
5443 11:48:27.453795 DQ Delay:
5444 11:48:27.455977 DQ0 =102, DQ1 =102, DQ2 =96, DQ3 =98
5445 11:48:27.458812 DQ4 =102, DQ5 =92, DQ6 =110, DQ7 =108
5446 11:48:27.462158 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =82
5447 11:48:27.465397 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5448 11:48:27.465861
5449 11:48:27.466228
5450 11:48:27.475524 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5451 11:48:27.476085 CH0 RK1: MR19=505, MR18=1512
5452 11:48:27.482467 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5453 11:48:27.486403 [RxdqsGatingPostProcess] freq 933
5454 11:48:27.491821 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5455 11:48:27.495242 best DQS0 dly(2T, 0.5T) = (0, 10)
5456 11:48:27.498790 best DQS1 dly(2T, 0.5T) = (0, 11)
5457 11:48:27.502239 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5458 11:48:27.505309 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5459 11:48:27.508827 best DQS0 dly(2T, 0.5T) = (0, 10)
5460 11:48:27.511607 best DQS1 dly(2T, 0.5T) = (0, 11)
5461 11:48:27.515306 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5462 11:48:27.515769 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5463 11:48:27.518559 Pre-setting of DQS Precalculation
5464 11:48:27.524920 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5465 11:48:27.525476 ==
5466 11:48:27.528283 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 11:48:27.531744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 11:48:27.532299 ==
5469 11:48:27.538359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5470 11:48:27.544820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5471 11:48:27.547879 [CA 0] Center 36 (6~67) winsize 62
5472 11:48:27.551149 [CA 1] Center 36 (6~67) winsize 62
5473 11:48:27.554357 [CA 2] Center 35 (5~65) winsize 61
5474 11:48:27.557425 [CA 3] Center 34 (4~65) winsize 62
5475 11:48:27.561461 [CA 4] Center 34 (4~65) winsize 62
5476 11:48:27.564164 [CA 5] Center 33 (3~64) winsize 62
5477 11:48:27.564721
5478 11:48:27.567666 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5479 11:48:27.568136
5480 11:48:27.570363 [CATrainingPosCal] consider 1 rank data
5481 11:48:27.574068 u2DelayCellTimex100 = 270/100 ps
5482 11:48:27.577823 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5483 11:48:27.580746 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5484 11:48:27.583810 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5485 11:48:27.587512 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5486 11:48:27.590577 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5487 11:48:27.597449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5488 11:48:27.597865
5489 11:48:27.600704 CA PerBit enable=1, Macro0, CA PI delay=33
5490 11:48:27.601245
5491 11:48:27.604372 [CBTSetCACLKResult] CA Dly = 33
5492 11:48:27.604927 CS Dly: 5 (0~36)
5493 11:48:27.605483 ==
5494 11:48:27.607306 Dram Type= 6, Freq= 0, CH_1, rank 1
5495 11:48:27.610851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 11:48:27.613866 ==
5497 11:48:27.617191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 11:48:27.623551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5499 11:48:27.627092 [CA 0] Center 36 (6~67) winsize 62
5500 11:48:27.630097 [CA 1] Center 37 (7~67) winsize 61
5501 11:48:27.633722 [CA 2] Center 34 (4~65) winsize 62
5502 11:48:27.637180 [CA 3] Center 33 (3~64) winsize 62
5503 11:48:27.639979 [CA 4] Center 33 (3~64) winsize 62
5504 11:48:27.643899 [CA 5] Center 33 (3~64) winsize 62
5505 11:48:27.644411
5506 11:48:27.646619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5507 11:48:27.647035
5508 11:48:27.650427 [CATrainingPosCal] consider 2 rank data
5509 11:48:27.653436 u2DelayCellTimex100 = 270/100 ps
5510 11:48:27.656890 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 11:48:27.660144 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5512 11:48:27.666337 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5513 11:48:27.670105 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 11:48:27.673078 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5515 11:48:27.676500 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 11:48:27.677211
5517 11:48:27.679997 CA PerBit enable=1, Macro0, CA PI delay=33
5518 11:48:27.680546
5519 11:48:27.682918 [CBTSetCACLKResult] CA Dly = 33
5520 11:48:27.683426 CS Dly: 6 (0~39)
5521 11:48:27.683798
5522 11:48:27.689879 ----->DramcWriteLeveling(PI) begin...
5523 11:48:27.690485 ==
5524 11:48:27.692646 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 11:48:27.696224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 11:48:27.696687 ==
5527 11:48:27.699570 Write leveling (Byte 0): 25 => 25
5528 11:48:27.702708 Write leveling (Byte 1): 26 => 26
5529 11:48:27.706476 DramcWriteLeveling(PI) end<-----
5530 11:48:27.707024
5531 11:48:27.707393 ==
5532 11:48:27.709234 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 11:48:27.712302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 11:48:27.712763 ==
5535 11:48:27.715600 [Gating] SW mode calibration
5536 11:48:27.722474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 11:48:27.729120 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5538 11:48:27.732635 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 11:48:27.735246 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 11:48:27.742361 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 11:48:27.745486 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 11:48:27.749735 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 11:48:27.755649 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 11:48:27.759042 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5545 11:48:27.762476 0 14 28 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
5546 11:48:27.768752 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 11:48:27.772356 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 11:48:27.775198 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 11:48:27.781457 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 11:48:27.784955 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 11:48:27.788287 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 11:48:27.795078 0 15 24 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
5553 11:48:27.798448 0 15 28 | B1->B0 | 3535 4242 | 1 0 | (0 0) (0 0)
5554 11:48:27.801639 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 11:48:27.808093 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 11:48:27.811400 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 11:48:27.814608 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 11:48:27.821158 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 11:48:27.824157 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 11:48:27.827585 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5561 11:48:27.834327 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5562 11:48:27.838099 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:48:27.840660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:48:27.847851 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:48:27.851329 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:48:27.855170 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:48:27.861199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:48:27.864177 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 11:48:27.867438 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 11:48:27.874407 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 11:48:27.877157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 11:48:27.880747 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 11:48:27.887038 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:48:27.890386 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:48:27.893582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 11:48:27.899990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 11:48:27.903531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5578 11:48:27.906687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:48:27.910438 Total UI for P1: 0, mck2ui 16
5580 11:48:27.913114 best dqsien dly found for B0: ( 1, 2, 28)
5581 11:48:27.916847 Total UI for P1: 0, mck2ui 16
5582 11:48:27.920103 best dqsien dly found for B1: ( 1, 2, 28)
5583 11:48:27.922830 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5584 11:48:27.929787 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5585 11:48:27.930388
5586 11:48:27.933354 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5587 11:48:27.936223 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5588 11:48:27.940108 [Gating] SW calibration Done
5589 11:48:27.940691 ==
5590 11:48:27.943184 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 11:48:27.946398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 11:48:27.946874 ==
5593 11:48:27.949998 RX Vref Scan: 0
5594 11:48:27.950601
5595 11:48:27.950970 RX Vref 0 -> 0, step: 1
5596 11:48:27.951315
5597 11:48:27.952718 RX Delay -80 -> 252, step: 8
5598 11:48:27.956456 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5599 11:48:27.960242 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5600 11:48:27.966149 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5601 11:48:27.969391 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5602 11:48:27.973031 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5603 11:48:27.975881 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5604 11:48:27.979909 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5605 11:48:27.986217 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5606 11:48:27.989109 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5607 11:48:27.992556 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5608 11:48:27.995598 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5609 11:48:27.999058 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5610 11:48:28.002855 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5611 11:48:28.008903 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5612 11:48:28.012296 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5613 11:48:28.014986 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5614 11:48:28.015444 ==
5615 11:48:28.018234 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 11:48:28.022450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 11:48:28.023026 ==
5618 11:48:28.025226 DQS Delay:
5619 11:48:28.025685 DQS0 = 0, DQS1 = 0
5620 11:48:28.028662 DQM Delay:
5621 11:48:28.029213 DQM0 = 98, DQM1 = 93
5622 11:48:28.029581 DQ Delay:
5623 11:48:28.031758 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5624 11:48:28.035001 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5625 11:48:28.038555 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5626 11:48:28.041506 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5627 11:48:28.044721
5628 11:48:28.045132
5629 11:48:28.045459 ==
5630 11:48:28.048722 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 11:48:28.051568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 11:48:28.051988 ==
5633 11:48:28.052321
5634 11:48:28.052628
5635 11:48:28.054508 TX Vref Scan disable
5636 11:48:28.054974 == TX Byte 0 ==
5637 11:48:28.061447 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5638 11:48:28.064827 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5639 11:48:28.065340 == TX Byte 1 ==
5640 11:48:28.071553 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5641 11:48:28.074565 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5642 11:48:28.075084 ==
5643 11:48:28.077950 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 11:48:28.081183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 11:48:28.081693 ==
5646 11:48:28.082027
5647 11:48:28.082378
5648 11:48:28.084905 TX Vref Scan disable
5649 11:48:28.087985 == TX Byte 0 ==
5650 11:48:28.090917 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5651 11:48:28.094521 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5652 11:48:28.097329 == TX Byte 1 ==
5653 11:48:28.100834 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5654 11:48:28.103961 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5655 11:48:28.104495
5656 11:48:28.108101 [DATLAT]
5657 11:48:28.108646 Freq=933, CH1 RK0
5658 11:48:28.109016
5659 11:48:28.111020 DATLAT Default: 0xd
5660 11:48:28.111478 0, 0xFFFF, sum = 0
5661 11:48:28.113998 1, 0xFFFF, sum = 0
5662 11:48:28.114510 2, 0xFFFF, sum = 0
5663 11:48:28.117916 3, 0xFFFF, sum = 0
5664 11:48:28.118423 4, 0xFFFF, sum = 0
5665 11:48:28.120607 5, 0xFFFF, sum = 0
5666 11:48:28.124047 6, 0xFFFF, sum = 0
5667 11:48:28.124600 7, 0xFFFF, sum = 0
5668 11:48:28.127021 8, 0xFFFF, sum = 0
5669 11:48:28.127513 9, 0xFFFF, sum = 0
5670 11:48:28.130641 10, 0x0, sum = 1
5671 11:48:28.131119 11, 0x0, sum = 2
5672 11:48:28.133638 12, 0x0, sum = 3
5673 11:48:28.134152 13, 0x0, sum = 4
5674 11:48:28.134536 best_step = 11
5675 11:48:28.137297
5676 11:48:28.137794 ==
5677 11:48:28.140655 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 11:48:28.143745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 11:48:28.144174 ==
5680 11:48:28.144506 RX Vref Scan: 1
5681 11:48:28.144816
5682 11:48:28.146814 RX Vref 0 -> 0, step: 1
5683 11:48:28.147228
5684 11:48:28.150360 RX Delay -61 -> 252, step: 4
5685 11:48:28.150860
5686 11:48:28.153921 Set Vref, RX VrefLevel [Byte0]: 52
5687 11:48:28.156670 [Byte1]: 52
5688 11:48:28.160257
5689 11:48:28.160770 Final RX Vref Byte 0 = 52 to rank0
5690 11:48:28.163564 Final RX Vref Byte 1 = 52 to rank0
5691 11:48:28.166868 Final RX Vref Byte 0 = 52 to rank1
5692 11:48:28.170249 Final RX Vref Byte 1 = 52 to rank1==
5693 11:48:28.173575 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 11:48:28.179617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 11:48:28.180128 ==
5696 11:48:28.180463 DQS Delay:
5697 11:48:28.183126 DQS0 = 0, DQS1 = 0
5698 11:48:28.183630 DQM Delay:
5699 11:48:28.183966 DQM0 = 96, DQM1 = 93
5700 11:48:28.186815 DQ Delay:
5701 11:48:28.189768 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5702 11:48:28.192789 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5703 11:48:28.196145 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =86
5704 11:48:28.199746 DQ12 =102, DQ13 =102, DQ14 =98, DQ15 =102
5705 11:48:28.200259
5706 11:48:28.200594
5707 11:48:28.206076 [DQSOSCAuto] RK0, (LSB)MR18= 0x313, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 421 ps
5708 11:48:28.209387 CH1 RK0: MR19=505, MR18=313
5709 11:48:28.215837 CH1_RK0: MR19=0x505, MR18=0x313, DQSOSC=415, MR23=63, INC=62, DEC=41
5710 11:48:28.216258
5711 11:48:28.219729 ----->DramcWriteLeveling(PI) begin...
5712 11:48:28.220240 ==
5713 11:48:28.222207 Dram Type= 6, Freq= 0, CH_1, rank 1
5714 11:48:28.226423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 11:48:28.226944 ==
5716 11:48:28.228983 Write leveling (Byte 0): 28 => 28
5717 11:48:28.232700 Write leveling (Byte 1): 28 => 28
5718 11:48:28.235827 DramcWriteLeveling(PI) end<-----
5719 11:48:28.236359
5720 11:48:28.236694 ==
5721 11:48:28.238560 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 11:48:28.244984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:48:28.245496 ==
5724 11:48:28.248468 [Gating] SW mode calibration
5725 11:48:28.255010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5726 11:48:28.258684 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5727 11:48:28.265598 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
5728 11:48:28.268978 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5729 11:48:28.272156 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 11:48:28.275341 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 11:48:28.281863 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 11:48:28.285158 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5733 11:48:28.291667 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
5734 11:48:28.295402 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5735 11:48:28.298375 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5736 11:48:28.305005 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 11:48:28.307710 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 11:48:28.311573 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 11:48:28.318351 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 11:48:28.321205 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 11:48:28.324841 0 15 24 | B1->B0 | 2b2b 3737 | 0 1 | (1 1) (0 0)
5742 11:48:28.331066 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5743 11:48:28.334349 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5744 11:48:28.337649 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 11:48:28.343873 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 11:48:28.347445 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 11:48:28.350951 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 11:48:28.357424 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 11:48:28.361486 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5750 11:48:28.363878 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5751 11:48:28.370135 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 11:48:28.374035 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 11:48:28.376950 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 11:48:28.383871 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 11:48:28.386950 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 11:48:28.390113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 11:48:28.396715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 11:48:28.399997 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 11:48:28.403752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 11:48:28.409650 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 11:48:28.413055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 11:48:28.416533 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 11:48:28.423186 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 11:48:28.425987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5765 11:48:28.429507 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5766 11:48:28.436203 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5767 11:48:28.436754 Total UI for P1: 0, mck2ui 16
5768 11:48:28.442936 best dqsien dly found for B0: ( 1, 2, 22)
5769 11:48:28.446118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:48:28.449451 Total UI for P1: 0, mck2ui 16
5771 11:48:28.453071 best dqsien dly found for B1: ( 1, 2, 30)
5772 11:48:28.455700 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5773 11:48:28.459188 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5774 11:48:28.459739
5775 11:48:28.462161 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5776 11:48:28.465687 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5777 11:48:28.469284 [Gating] SW calibration Done
5778 11:48:28.469846 ==
5779 11:48:28.472481 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 11:48:28.479452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:48:28.480007 ==
5782 11:48:28.480375 RX Vref Scan: 0
5783 11:48:28.480713
5784 11:48:28.482172 RX Vref 0 -> 0, step: 1
5785 11:48:28.482667
5786 11:48:28.485073 RX Delay -80 -> 252, step: 8
5787 11:48:28.488498 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5788 11:48:28.491897 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5789 11:48:28.495258 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5790 11:48:28.498686 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5791 11:48:28.504873 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5792 11:48:28.508149 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5793 11:48:28.512019 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5794 11:48:28.515244 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5795 11:48:28.518306 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5796 11:48:28.521807 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5797 11:48:28.528004 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5798 11:48:28.531762 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5799 11:48:28.535283 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5800 11:48:28.538482 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5801 11:48:28.541710 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5802 11:48:28.547798 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5803 11:48:28.548261 ==
5804 11:48:28.551472 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 11:48:28.554732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 11:48:28.555244 ==
5807 11:48:28.555577 DQS Delay:
5808 11:48:28.558076 DQS0 = 0, DQS1 = 0
5809 11:48:28.558532 DQM Delay:
5810 11:48:28.561619 DQM0 = 95, DQM1 = 91
5811 11:48:28.562126 DQ Delay:
5812 11:48:28.564179 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5813 11:48:28.567920 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =95
5814 11:48:28.570999 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5815 11:48:28.574513 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5816 11:48:28.575022
5817 11:48:28.575352
5818 11:48:28.575653 ==
5819 11:48:28.577665 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 11:48:28.581171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 11:48:28.581585 ==
5822 11:48:28.584675
5823 11:48:28.585178
5824 11:48:28.585511 TX Vref Scan disable
5825 11:48:28.587972 == TX Byte 0 ==
5826 11:48:28.591108 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5827 11:48:28.594631 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5828 11:48:28.597377 == TX Byte 1 ==
5829 11:48:28.600902 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5830 11:48:28.604447 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5831 11:48:28.604958 ==
5832 11:48:28.607277 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 11:48:28.613752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 11:48:28.614282 ==
5835 11:48:28.614626
5836 11:48:28.614932
5837 11:48:28.617229 TX Vref Scan disable
5838 11:48:28.617637 == TX Byte 0 ==
5839 11:48:28.623621 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5840 11:48:28.627022 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5841 11:48:28.627538 == TX Byte 1 ==
5842 11:48:28.633387 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5843 11:48:28.637160 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5844 11:48:28.637691
5845 11:48:28.638030 [DATLAT]
5846 11:48:28.640133 Freq=933, CH1 RK1
5847 11:48:28.640642
5848 11:48:28.640971 DATLAT Default: 0xb
5849 11:48:28.643540 0, 0xFFFF, sum = 0
5850 11:48:28.643961 1, 0xFFFF, sum = 0
5851 11:48:28.646734 2, 0xFFFF, sum = 0
5852 11:48:28.647149 3, 0xFFFF, sum = 0
5853 11:48:28.650402 4, 0xFFFF, sum = 0
5854 11:48:28.650912 5, 0xFFFF, sum = 0
5855 11:48:28.653213 6, 0xFFFF, sum = 0
5856 11:48:28.656924 7, 0xFFFF, sum = 0
5857 11:48:28.657447 8, 0xFFFF, sum = 0
5858 11:48:28.659929 9, 0xFFFF, sum = 0
5859 11:48:28.660349 10, 0x0, sum = 1
5860 11:48:28.663291 11, 0x0, sum = 2
5861 11:48:28.663705 12, 0x0, sum = 3
5862 11:48:28.664055 13, 0x0, sum = 4
5863 11:48:28.666743 best_step = 11
5864 11:48:28.667149
5865 11:48:28.667471 ==
5866 11:48:28.669757 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 11:48:28.673537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 11:48:28.674242 ==
5869 11:48:28.676594 RX Vref Scan: 0
5870 11:48:28.677065
5871 11:48:28.677395 RX Vref 0 -> 0, step: 1
5872 11:48:28.680246
5873 11:48:28.680654 RX Delay -61 -> 252, step: 4
5874 11:48:28.686969 iDelay=199, Bit 0, Center 100 (7 ~ 194) 188
5875 11:48:28.690795 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5876 11:48:28.693595 iDelay=199, Bit 2, Center 86 (-9 ~ 182) 192
5877 11:48:28.697189 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5878 11:48:28.700298 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5879 11:48:28.704076 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5880 11:48:28.710137 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5881 11:48:28.713620 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5882 11:48:28.716832 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5883 11:48:28.721207 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5884 11:48:28.723608 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5885 11:48:28.730113 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5886 11:48:28.733467 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5887 11:48:28.736817 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5888 11:48:28.740165 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5889 11:48:28.746760 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5890 11:48:28.747277 ==
5891 11:48:28.750078 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 11:48:28.753032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 11:48:28.753563 ==
5894 11:48:28.754008 DQS Delay:
5895 11:48:28.756595 DQS0 = 0, DQS1 = 0
5896 11:48:28.757122 DQM Delay:
5897 11:48:28.759358 DQM0 = 96, DQM1 = 92
5898 11:48:28.759786 DQ Delay:
5899 11:48:28.763039 DQ0 =100, DQ1 =94, DQ2 =86, DQ3 =94
5900 11:48:28.766512 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
5901 11:48:28.769741 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5902 11:48:28.772974 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5903 11:48:28.773505
5904 11:48:28.773951
5905 11:48:28.783014 [DQSOSCAuto] RK1, (LSB)MR18= 0xd24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5906 11:48:28.783549 CH1 RK1: MR19=505, MR18=D24
5907 11:48:28.790151 CH1_RK1: MR19=0x505, MR18=0xD24, DQSOSC=410, MR23=63, INC=64, DEC=42
5908 11:48:28.792578 [RxdqsGatingPostProcess] freq 933
5909 11:48:28.799046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5910 11:48:28.802380 best DQS0 dly(2T, 0.5T) = (0, 10)
5911 11:48:28.805882 best DQS1 dly(2T, 0.5T) = (0, 10)
5912 11:48:28.809604 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5913 11:48:28.812701 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5914 11:48:28.815461 best DQS0 dly(2T, 0.5T) = (0, 10)
5915 11:48:28.815974 best DQS1 dly(2T, 0.5T) = (0, 10)
5916 11:48:28.819083 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5917 11:48:28.822185 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5918 11:48:28.825933 Pre-setting of DQS Precalculation
5919 11:48:28.832945 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5920 11:48:28.838435 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5921 11:48:28.845573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5922 11:48:28.846112
5923 11:48:28.846533
5924 11:48:28.849067 [Calibration Summary] 1866 Mbps
5925 11:48:28.852227 CH 0, Rank 0
5926 11:48:28.852745 SW Impedance : PASS
5927 11:48:28.855079 DUTY Scan : NO K
5928 11:48:28.858921 ZQ Calibration : PASS
5929 11:48:28.859437 Jitter Meter : NO K
5930 11:48:28.862018 CBT Training : PASS
5931 11:48:28.865720 Write leveling : PASS
5932 11:48:28.866234 RX DQS gating : PASS
5933 11:48:28.869064 RX DQ/DQS(RDDQC) : PASS
5934 11:48:28.869579 TX DQ/DQS : PASS
5935 11:48:28.871936 RX DATLAT : PASS
5936 11:48:28.875169 RX DQ/DQS(Engine): PASS
5937 11:48:28.875678 TX OE : NO K
5938 11:48:28.878686 All Pass.
5939 11:48:28.879206
5940 11:48:28.879538 CH 0, Rank 1
5941 11:48:28.881829 SW Impedance : PASS
5942 11:48:28.882386 DUTY Scan : NO K
5943 11:48:28.885440 ZQ Calibration : PASS
5944 11:48:28.888072 Jitter Meter : NO K
5945 11:48:28.888487 CBT Training : PASS
5946 11:48:28.891761 Write leveling : PASS
5947 11:48:28.894499 RX DQS gating : PASS
5948 11:48:28.895023 RX DQ/DQS(RDDQC) : PASS
5949 11:48:28.898681 TX DQ/DQS : PASS
5950 11:48:28.901067 RX DATLAT : PASS
5951 11:48:28.901509 RX DQ/DQS(Engine): PASS
5952 11:48:28.904768 TX OE : NO K
5953 11:48:28.905201 All Pass.
5954 11:48:28.905636
5955 11:48:28.908037 CH 1, Rank 0
5956 11:48:28.908462 SW Impedance : PASS
5957 11:48:28.911687 DUTY Scan : NO K
5958 11:48:28.914587 ZQ Calibration : PASS
5959 11:48:28.915116 Jitter Meter : NO K
5960 11:48:28.917703 CBT Training : PASS
5961 11:48:28.921060 Write leveling : PASS
5962 11:48:28.921583 RX DQS gating : PASS
5963 11:48:28.925069 RX DQ/DQS(RDDQC) : PASS
5964 11:48:28.927454 TX DQ/DQS : PASS
5965 11:48:28.927887 RX DATLAT : PASS
5966 11:48:28.930775 RX DQ/DQS(Engine): PASS
5967 11:48:28.934184 TX OE : NO K
5968 11:48:28.934753 All Pass.
5969 11:48:28.935195
5970 11:48:28.935606 CH 1, Rank 1
5971 11:48:28.937645 SW Impedance : PASS
5972 11:48:28.941578 DUTY Scan : NO K
5973 11:48:28.942142 ZQ Calibration : PASS
5974 11:48:28.945499 Jitter Meter : NO K
5975 11:48:28.947433 CBT Training : PASS
5976 11:48:28.947863 Write leveling : PASS
5977 11:48:28.950914 RX DQS gating : PASS
5978 11:48:28.951342 RX DQ/DQS(RDDQC) : PASS
5979 11:48:28.954157 TX DQ/DQS : PASS
5980 11:48:28.957617 RX DATLAT : PASS
5981 11:48:28.958147 RX DQ/DQS(Engine): PASS
5982 11:48:28.960925 TX OE : NO K
5983 11:48:28.961473 All Pass.
5984 11:48:28.961924
5985 11:48:28.963779 DramC Write-DBI off
5986 11:48:28.967901 PER_BANK_REFRESH: Hybrid Mode
5987 11:48:28.968433 TX_TRACKING: ON
5988 11:48:28.977273 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5989 11:48:28.981024 [FAST_K] Save calibration result to emmc
5990 11:48:28.983481 dramc_set_vcore_voltage set vcore to 650000
5991 11:48:28.987207 Read voltage for 400, 6
5992 11:48:28.987733 Vio18 = 0
5993 11:48:28.990159 Vcore = 650000
5994 11:48:28.990726 Vdram = 0
5995 11:48:28.991170 Vddq = 0
5996 11:48:28.991586 Vmddr = 0
5997 11:48:28.997205 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5998 11:48:29.003429 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5999 11:48:29.003961 MEM_TYPE=3, freq_sel=20
6000 11:48:29.006929 sv_algorithm_assistance_LP4_800
6001 11:48:29.010305 ============ PULL DRAM RESETB DOWN ============
6002 11:48:29.016681 ========== PULL DRAM RESETB DOWN end =========
6003 11:48:29.020233 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6004 11:48:29.023682 ===================================
6005 11:48:29.026715 LPDDR4 DRAM CONFIGURATION
6006 11:48:29.029665 ===================================
6007 11:48:29.030103 EX_ROW_EN[0] = 0x0
6008 11:48:29.033044 EX_ROW_EN[1] = 0x0
6009 11:48:29.033471 LP4Y_EN = 0x0
6010 11:48:29.037149 WORK_FSP = 0x0
6011 11:48:29.040241 WL = 0x2
6012 11:48:29.040755 RL = 0x2
6013 11:48:29.042775 BL = 0x2
6014 11:48:29.043190 RPST = 0x0
6015 11:48:29.046376 RD_PRE = 0x0
6016 11:48:29.046927 WR_PRE = 0x1
6017 11:48:29.049788 WR_PST = 0x0
6018 11:48:29.050373 DBI_WR = 0x0
6019 11:48:29.053375 DBI_RD = 0x0
6020 11:48:29.053906 OTF = 0x1
6021 11:48:29.056075 ===================================
6022 11:48:29.060036 ===================================
6023 11:48:29.062644 ANA top config
6024 11:48:29.066435 ===================================
6025 11:48:29.066969 DLL_ASYNC_EN = 0
6026 11:48:29.069817 ALL_SLAVE_EN = 1
6027 11:48:29.072906 NEW_RANK_MODE = 1
6028 11:48:29.075955 DLL_IDLE_MODE = 1
6029 11:48:29.079215 LP45_APHY_COMB_EN = 1
6030 11:48:29.079752 TX_ODT_DIS = 1
6031 11:48:29.082418 NEW_8X_MODE = 1
6032 11:48:29.086095 ===================================
6033 11:48:29.088852 ===================================
6034 11:48:29.092532 data_rate = 800
6035 11:48:29.095591 CKR = 1
6036 11:48:29.098623 DQ_P2S_RATIO = 4
6037 11:48:29.102334 ===================================
6038 11:48:29.105480 CA_P2S_RATIO = 4
6039 11:48:29.105992 DQ_CA_OPEN = 0
6040 11:48:29.108373 DQ_SEMI_OPEN = 1
6041 11:48:29.112160 CA_SEMI_OPEN = 1
6042 11:48:29.115085 CA_FULL_RATE = 0
6043 11:48:29.118591 DQ_CKDIV4_EN = 0
6044 11:48:29.121676 CA_CKDIV4_EN = 1
6045 11:48:29.122205 CA_PREDIV_EN = 0
6046 11:48:29.125647 PH8_DLY = 0
6047 11:48:29.128332 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6048 11:48:29.131406 DQ_AAMCK_DIV = 0
6049 11:48:29.135105 CA_AAMCK_DIV = 0
6050 11:48:29.138746 CA_ADMCK_DIV = 4
6051 11:48:29.139422 DQ_TRACK_CA_EN = 0
6052 11:48:29.141606 CA_PICK = 800
6053 11:48:29.145266 CA_MCKIO = 400
6054 11:48:29.148950 MCKIO_SEMI = 400
6055 11:48:29.152110 PLL_FREQ = 3016
6056 11:48:29.155275 DQ_UI_PI_RATIO = 32
6057 11:48:29.158073 CA_UI_PI_RATIO = 32
6058 11:48:29.161423 ===================================
6059 11:48:29.165135 ===================================
6060 11:48:29.168248 memory_type:LPDDR4
6061 11:48:29.168781 GP_NUM : 10
6062 11:48:29.171203 SRAM_EN : 1
6063 11:48:29.171633 MD32_EN : 0
6064 11:48:29.174371 ===================================
6065 11:48:29.178035 [ANA_INIT] >>>>>>>>>>>>>>
6066 11:48:29.181632 <<<<<< [CONFIGURE PHASE]: ANA_TX
6067 11:48:29.184852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6068 11:48:29.188068 ===================================
6069 11:48:29.191156 data_rate = 800,PCW = 0X7400
6070 11:48:29.194296 ===================================
6071 11:48:29.198101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6072 11:48:29.201067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6073 11:48:29.214578 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6074 11:48:29.217373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6075 11:48:29.220695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6076 11:48:29.224497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6077 11:48:29.227324 [ANA_INIT] flow start
6078 11:48:29.230857 [ANA_INIT] PLL >>>>>>>>
6079 11:48:29.231387 [ANA_INIT] PLL <<<<<<<<
6080 11:48:29.233944 [ANA_INIT] MIDPI >>>>>>>>
6081 11:48:29.237382 [ANA_INIT] MIDPI <<<<<<<<
6082 11:48:29.240653 [ANA_INIT] DLL >>>>>>>>
6083 11:48:29.241183 [ANA_INIT] flow end
6084 11:48:29.243960 ============ LP4 DIFF to SE enter ============
6085 11:48:29.250415 ============ LP4 DIFF to SE exit ============
6086 11:48:29.250850 [ANA_INIT] <<<<<<<<<<<<<
6087 11:48:29.254075 [Flow] Enable top DCM control >>>>>
6088 11:48:29.256676 [Flow] Enable top DCM control <<<<<
6089 11:48:29.260100 Enable DLL master slave shuffle
6090 11:48:29.267031 ==============================================================
6091 11:48:29.270614 Gating Mode config
6092 11:48:29.273163 ==============================================================
6093 11:48:29.276853 Config description:
6094 11:48:29.286394 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6095 11:48:29.293285 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6096 11:48:29.296436 SELPH_MODE 0: By rank 1: By Phase
6097 11:48:29.302923 ==============================================================
6098 11:48:29.306149 GAT_TRACK_EN = 0
6099 11:48:29.309701 RX_GATING_MODE = 2
6100 11:48:29.313230 RX_GATING_TRACK_MODE = 2
6101 11:48:29.315894 SELPH_MODE = 1
6102 11:48:29.316306 PICG_EARLY_EN = 1
6103 11:48:29.319186 VALID_LAT_VALUE = 1
6104 11:48:29.326154 ==============================================================
6105 11:48:29.329859 Enter into Gating configuration >>>>
6106 11:48:29.332791 Exit from Gating configuration <<<<
6107 11:48:29.336119 Enter into DVFS_PRE_config >>>>>
6108 11:48:29.345767 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6109 11:48:29.349090 Exit from DVFS_PRE_config <<<<<
6110 11:48:29.352971 Enter into PICG configuration >>>>
6111 11:48:29.356337 Exit from PICG configuration <<<<
6112 11:48:29.358695 [RX_INPUT] configuration >>>>>
6113 11:48:29.362835 [RX_INPUT] configuration <<<<<
6114 11:48:29.365725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6115 11:48:29.372436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6116 11:48:29.378760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6117 11:48:29.385314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6118 11:48:29.392034 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6119 11:48:29.398797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6120 11:48:29.402463 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6121 11:48:29.405576 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6122 11:48:29.408143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6123 11:48:29.415436 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6124 11:48:29.418345 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6125 11:48:29.421495 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6126 11:48:29.424793 ===================================
6127 11:48:29.428294 LPDDR4 DRAM CONFIGURATION
6128 11:48:29.431525 ===================================
6129 11:48:29.431951 EX_ROW_EN[0] = 0x0
6130 11:48:29.435165 EX_ROW_EN[1] = 0x0
6131 11:48:29.438206 LP4Y_EN = 0x0
6132 11:48:29.438651 WORK_FSP = 0x0
6133 11:48:29.441327 WL = 0x2
6134 11:48:29.441832 RL = 0x2
6135 11:48:29.444584 BL = 0x2
6136 11:48:29.445073 RPST = 0x0
6137 11:48:29.447481 RD_PRE = 0x0
6138 11:48:29.447899 WR_PRE = 0x1
6139 11:48:29.451430 WR_PST = 0x0
6140 11:48:29.451947 DBI_WR = 0x0
6141 11:48:29.454842 DBI_RD = 0x0
6142 11:48:29.455384 OTF = 0x1
6143 11:48:29.457549 ===================================
6144 11:48:29.461189 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6145 11:48:29.468109 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6146 11:48:29.471316 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 11:48:29.474467 ===================================
6148 11:48:29.477910 LPDDR4 DRAM CONFIGURATION
6149 11:48:29.481028 ===================================
6150 11:48:29.484457 EX_ROW_EN[0] = 0x10
6151 11:48:29.485036 EX_ROW_EN[1] = 0x0
6152 11:48:29.487815 LP4Y_EN = 0x0
6153 11:48:29.488245 WORK_FSP = 0x0
6154 11:48:29.491929 WL = 0x2
6155 11:48:29.492577 RL = 0x2
6156 11:48:29.494056 BL = 0x2
6157 11:48:29.494527 RPST = 0x0
6158 11:48:29.497696 RD_PRE = 0x0
6159 11:48:29.498204 WR_PRE = 0x1
6160 11:48:29.500456 WR_PST = 0x0
6161 11:48:29.500864 DBI_WR = 0x0
6162 11:48:29.503597 DBI_RD = 0x0
6163 11:48:29.504007 OTF = 0x1
6164 11:48:29.507718 ===================================
6165 11:48:29.514178 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6166 11:48:29.518921 nWR fixed to 30
6167 11:48:29.521627 [ModeRegInit_LP4] CH0 RK0
6168 11:48:29.522083 [ModeRegInit_LP4] CH0 RK1
6169 11:48:29.525117 [ModeRegInit_LP4] CH1 RK0
6170 11:48:29.528600 [ModeRegInit_LP4] CH1 RK1
6171 11:48:29.529149 match AC timing 19
6172 11:48:29.534822 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6173 11:48:29.538708 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6174 11:48:29.542341 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6175 11:48:29.548010 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6176 11:48:29.551579 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6177 11:48:29.551993 ==
6178 11:48:29.554805 Dram Type= 6, Freq= 0, CH_0, rank 0
6179 11:48:29.557887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6180 11:48:29.558332 ==
6181 11:48:29.564867 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6182 11:48:29.571221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6183 11:48:29.575008 [CA 0] Center 36 (8~64) winsize 57
6184 11:48:29.578054 [CA 1] Center 36 (8~64) winsize 57
6185 11:48:29.580898 [CA 2] Center 36 (8~64) winsize 57
6186 11:48:29.584110 [CA 3] Center 36 (8~64) winsize 57
6187 11:48:29.587535 [CA 4] Center 36 (8~64) winsize 57
6188 11:48:29.590864 [CA 5] Center 36 (8~64) winsize 57
6189 11:48:29.591567
6190 11:48:29.594173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6191 11:48:29.594607
6192 11:48:29.597520 [CATrainingPosCal] consider 1 rank data
6193 11:48:29.600547 u2DelayCellTimex100 = 270/100 ps
6194 11:48:29.603831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6195 11:48:29.607258 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 11:48:29.611033 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 11:48:29.614037 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 11:48:29.616774 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 11:48:29.620924 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 11:48:29.621723
6201 11:48:29.627092 CA PerBit enable=1, Macro0, CA PI delay=36
6202 11:48:29.627643
6203 11:48:29.630571 [CBTSetCACLKResult] CA Dly = 36
6204 11:48:29.631125 CS Dly: 1 (0~32)
6205 11:48:29.631492 ==
6206 11:48:29.633075 Dram Type= 6, Freq= 0, CH_0, rank 1
6207 11:48:29.636885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 11:48:29.637393 ==
6209 11:48:29.643628 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 11:48:29.650178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6211 11:48:29.653247 [CA 0] Center 36 (8~64) winsize 57
6212 11:48:29.656295 [CA 1] Center 36 (8~64) winsize 57
6213 11:48:29.659790 [CA 2] Center 36 (8~64) winsize 57
6214 11:48:29.662970 [CA 3] Center 36 (8~64) winsize 57
6215 11:48:29.666432 [CA 4] Center 36 (8~64) winsize 57
6216 11:48:29.669806 [CA 5] Center 36 (8~64) winsize 57
6217 11:48:29.670400
6218 11:48:29.673178 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6219 11:48:29.673688
6220 11:48:29.676135 [CATrainingPosCal] consider 2 rank data
6221 11:48:29.679020 u2DelayCellTimex100 = 270/100 ps
6222 11:48:29.683163 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:48:29.686403 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:48:29.689955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:48:29.692820 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:48:29.695987 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:48:29.698988 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:48:29.699398
6229 11:48:29.705862 CA PerBit enable=1, Macro0, CA PI delay=36
6230 11:48:29.706400
6231 11:48:29.706739 [CBTSetCACLKResult] CA Dly = 36
6232 11:48:29.709120 CS Dly: 1 (0~32)
6233 11:48:29.709632
6234 11:48:29.712405 ----->DramcWriteLeveling(PI) begin...
6235 11:48:29.712936 ==
6236 11:48:29.716124 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 11:48:29.718918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 11:48:29.719330 ==
6239 11:48:29.722016 Write leveling (Byte 0): 40 => 8
6240 11:48:29.725513 Write leveling (Byte 1): 40 => 8
6241 11:48:29.729011 DramcWriteLeveling(PI) end<-----
6242 11:48:29.729692
6243 11:48:29.730026 ==
6244 11:48:29.732557 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 11:48:29.738693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 11:48:29.739105 ==
6247 11:48:29.739436 [Gating] SW mode calibration
6248 11:48:29.748673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6249 11:48:29.752065 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6250 11:48:29.754997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6251 11:48:29.762137 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6252 11:48:29.764984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6253 11:48:29.768285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 11:48:29.774755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6255 11:48:29.778472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 11:48:29.781403 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 11:48:29.789093 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 11:48:29.791565 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6259 11:48:29.794951 Total UI for P1: 0, mck2ui 16
6260 11:48:29.797926 best dqsien dly found for B0: ( 0, 14, 24)
6261 11:48:29.801045 Total UI for P1: 0, mck2ui 16
6262 11:48:29.805245 best dqsien dly found for B1: ( 0, 14, 24)
6263 11:48:29.808065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6264 11:48:29.810886 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6265 11:48:29.811300
6266 11:48:29.817678 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6267 11:48:29.821215 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6268 11:48:29.821584 [Gating] SW calibration Done
6269 11:48:29.824014 ==
6270 11:48:29.827691 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 11:48:29.831131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 11:48:29.831556 ==
6273 11:48:29.831895 RX Vref Scan: 0
6274 11:48:29.832204
6275 11:48:29.833905 RX Vref 0 -> 0, step: 1
6276 11:48:29.834384
6277 11:48:29.837609 RX Delay -410 -> 252, step: 16
6278 11:48:29.840761 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6279 11:48:29.847638 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6280 11:48:29.850489 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6281 11:48:29.854202 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6282 11:48:29.857055 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6283 11:48:29.863652 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6284 11:48:29.867443 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6285 11:48:29.870543 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6286 11:48:29.874815 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6287 11:48:29.880670 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6288 11:48:29.883393 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6289 11:48:29.886807 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6290 11:48:29.889959 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6291 11:48:29.896428 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6292 11:48:29.900371 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6293 11:48:29.902994 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6294 11:48:29.903399 ==
6295 11:48:29.906027 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 11:48:29.912949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 11:48:29.913358 ==
6298 11:48:29.913681 DQS Delay:
6299 11:48:29.916271 DQS0 = 35, DQS1 = 59
6300 11:48:29.916720 DQM Delay:
6301 11:48:29.917062 DQM0 = 5, DQM1 = 17
6302 11:48:29.920454 DQ Delay:
6303 11:48:29.922822 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6304 11:48:29.923351 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6305 11:48:29.926470 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6306 11:48:29.929939 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6307 11:48:29.930523
6308 11:48:29.933383
6309 11:48:29.933887 ==
6310 11:48:29.936469 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 11:48:29.939173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 11:48:29.939580 ==
6313 11:48:29.939903
6314 11:48:29.940199
6315 11:48:29.942836 TX Vref Scan disable
6316 11:48:29.943245 == TX Byte 0 ==
6317 11:48:29.945728 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6318 11:48:29.952803 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6319 11:48:29.953299 == TX Byte 1 ==
6320 11:48:29.955697 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6321 11:48:29.962293 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6322 11:48:29.962802 ==
6323 11:48:29.965634 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 11:48:29.968826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 11:48:29.969237 ==
6326 11:48:29.969561
6327 11:48:29.969861
6328 11:48:29.972229 TX Vref Scan disable
6329 11:48:29.972732 == TX Byte 0 ==
6330 11:48:29.978885 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 11:48:29.981975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 11:48:29.982533 == TX Byte 1 ==
6333 11:48:29.988461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 11:48:29.992439 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 11:48:29.992994
6336 11:48:29.993328 [DATLAT]
6337 11:48:29.995371 Freq=400, CH0 RK0
6338 11:48:29.995778
6339 11:48:29.996103 DATLAT Default: 0xf
6340 11:48:29.998309 0, 0xFFFF, sum = 0
6341 11:48:29.998725 1, 0xFFFF, sum = 0
6342 11:48:30.002119 2, 0xFFFF, sum = 0
6343 11:48:30.002753 3, 0xFFFF, sum = 0
6344 11:48:30.004894 4, 0xFFFF, sum = 0
6345 11:48:30.005308 5, 0xFFFF, sum = 0
6346 11:48:30.008574 6, 0xFFFF, sum = 0
6347 11:48:30.009088 7, 0xFFFF, sum = 0
6348 11:48:30.012044 8, 0xFFFF, sum = 0
6349 11:48:30.012555 9, 0xFFFF, sum = 0
6350 11:48:30.015503 10, 0xFFFF, sum = 0
6351 11:48:30.018956 11, 0xFFFF, sum = 0
6352 11:48:30.019528 12, 0xFFFF, sum = 0
6353 11:48:30.021679 13, 0x0, sum = 1
6354 11:48:30.022194 14, 0x0, sum = 2
6355 11:48:30.024585 15, 0x0, sum = 3
6356 11:48:30.024998 16, 0x0, sum = 4
6357 11:48:30.025384 best_step = 14
6358 11:48:30.025863
6359 11:48:30.028241 ==
6360 11:48:30.031181 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 11:48:30.034573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 11:48:30.035086 ==
6363 11:48:30.035412 RX Vref Scan: 1
6364 11:48:30.035711
6365 11:48:30.038057 RX Vref 0 -> 0, step: 1
6366 11:48:30.038513
6367 11:48:30.041459 RX Delay -359 -> 252, step: 8
6368 11:48:30.041965
6369 11:48:30.044686 Set Vref, RX VrefLevel [Byte0]: 55
6370 11:48:30.047785 [Byte1]: 50
6371 11:48:30.052311
6372 11:48:30.052717 Final RX Vref Byte 0 = 55 to rank0
6373 11:48:30.055013 Final RX Vref Byte 1 = 50 to rank0
6374 11:48:30.058994 Final RX Vref Byte 0 = 55 to rank1
6375 11:48:30.062195 Final RX Vref Byte 1 = 50 to rank1==
6376 11:48:30.065320 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 11:48:30.071637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 11:48:30.072147 ==
6379 11:48:30.072473 DQS Delay:
6380 11:48:30.074956 DQS0 = 44, DQS1 = 60
6381 11:48:30.075465 DQM Delay:
6382 11:48:30.075795 DQM0 = 10, DQM1 = 17
6383 11:48:30.078314 DQ Delay:
6384 11:48:30.081661 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6385 11:48:30.084940 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6386 11:48:30.088368 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6387 11:48:30.091633 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6388 11:48:30.092046
6389 11:48:30.092372
6390 11:48:30.098691 [DQSOSCAuto] RK0, (LSB)MR18= 0x9589, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6391 11:48:30.101287 CH0 RK0: MR19=C0C, MR18=9589
6392 11:48:30.107766 CH0_RK0: MR19=0xC0C, MR18=0x9589, DQSOSC=391, MR23=63, INC=386, DEC=257
6393 11:48:30.108276 ==
6394 11:48:30.111186 Dram Type= 6, Freq= 0, CH_0, rank 1
6395 11:48:30.114549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:48:30.115094 ==
6397 11:48:30.117899 [Gating] SW mode calibration
6398 11:48:30.124229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6399 11:48:30.130824 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6400 11:48:30.134202 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 11:48:30.137544 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 11:48:30.144363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 11:48:30.147275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 11:48:30.150847 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 11:48:30.157633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 11:48:30.160863 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 11:48:30.164458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 11:48:30.170471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6409 11:48:30.173878 Total UI for P1: 0, mck2ui 16
6410 11:48:30.177970 best dqsien dly found for B0: ( 0, 14, 24)
6411 11:48:30.180303 Total UI for P1: 0, mck2ui 16
6412 11:48:30.183707 best dqsien dly found for B1: ( 0, 14, 24)
6413 11:48:30.186947 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6414 11:48:30.190313 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6415 11:48:30.190973
6416 11:48:30.193570 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 11:48:30.196611 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 11:48:30.199778 [Gating] SW calibration Done
6419 11:48:30.200186 ==
6420 11:48:30.203707 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 11:48:30.206587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 11:48:30.210165 ==
6423 11:48:30.210709 RX Vref Scan: 0
6424 11:48:30.211044
6425 11:48:30.213580 RX Vref 0 -> 0, step: 1
6426 11:48:30.214094
6427 11:48:30.216295 RX Delay -410 -> 252, step: 16
6428 11:48:30.219435 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6429 11:48:30.223092 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6430 11:48:30.225993 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6431 11:48:30.232672 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6432 11:48:30.235951 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6433 11:48:30.239644 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6434 11:48:30.242904 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6435 11:48:30.249236 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6436 11:48:30.252435 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6437 11:48:30.255712 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6438 11:48:30.262479 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6439 11:48:30.265565 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6440 11:48:30.269144 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6441 11:48:30.271906 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6442 11:48:30.278816 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6443 11:48:30.282399 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6444 11:48:30.282906 ==
6445 11:48:30.285448 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 11:48:30.288875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 11:48:30.289391 ==
6448 11:48:30.291864 DQS Delay:
6449 11:48:30.292273 DQS0 = 35, DQS1 = 59
6450 11:48:30.295081 DQM Delay:
6451 11:48:30.295627 DQM0 = 7, DQM1 = 17
6452 11:48:30.296138 DQ Delay:
6453 11:48:30.298554 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6454 11:48:30.301288 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6455 11:48:30.305391 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6456 11:48:30.308818 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6457 11:48:30.309331
6458 11:48:30.309661
6459 11:48:30.309977 ==
6460 11:48:30.311868 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 11:48:30.318244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 11:48:30.318952 ==
6463 11:48:30.319305
6464 11:48:30.319613
6465 11:48:30.319908 TX Vref Scan disable
6466 11:48:30.321791 == TX Byte 0 ==
6467 11:48:30.324724 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6468 11:48:30.328184 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6469 11:48:30.330860 == TX Byte 1 ==
6470 11:48:30.334572 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6471 11:48:30.337986 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6472 11:48:30.341258 ==
6473 11:48:30.341773 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 11:48:30.347539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 11:48:30.348043 ==
6476 11:48:30.348374
6477 11:48:30.348678
6478 11:48:30.350738 TX Vref Scan disable
6479 11:48:30.351147 == TX Byte 0 ==
6480 11:48:30.354049 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6481 11:48:30.360994 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6482 11:48:30.361637 == TX Byte 1 ==
6483 11:48:30.364191 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6484 11:48:30.370517 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6485 11:48:30.370931
6486 11:48:30.371257 [DATLAT]
6487 11:48:30.371564 Freq=400, CH0 RK1
6488 11:48:30.371860
6489 11:48:30.374213 DATLAT Default: 0xe
6490 11:48:30.374887 0, 0xFFFF, sum = 0
6491 11:48:30.377002 1, 0xFFFF, sum = 0
6492 11:48:30.380129 2, 0xFFFF, sum = 0
6493 11:48:30.380547 3, 0xFFFF, sum = 0
6494 11:48:30.384377 4, 0xFFFF, sum = 0
6495 11:48:30.384896 5, 0xFFFF, sum = 0
6496 11:48:30.387288 6, 0xFFFF, sum = 0
6497 11:48:30.387705 7, 0xFFFF, sum = 0
6498 11:48:30.390354 8, 0xFFFF, sum = 0
6499 11:48:30.390825 9, 0xFFFF, sum = 0
6500 11:48:30.393836 10, 0xFFFF, sum = 0
6501 11:48:30.394411 11, 0xFFFF, sum = 0
6502 11:48:30.396982 12, 0xFFFF, sum = 0
6503 11:48:30.397397 13, 0x0, sum = 1
6504 11:48:30.400185 14, 0x0, sum = 2
6505 11:48:30.400777 15, 0x0, sum = 3
6506 11:48:30.403842 16, 0x0, sum = 4
6507 11:48:30.404361 best_step = 14
6508 11:48:30.404693
6509 11:48:30.404997 ==
6510 11:48:30.406754 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 11:48:30.414067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 11:48:30.414619 ==
6513 11:48:30.414957 RX Vref Scan: 0
6514 11:48:30.415260
6515 11:48:30.416577 RX Vref 0 -> 0, step: 1
6516 11:48:30.416985
6517 11:48:30.419910 RX Delay -359 -> 252, step: 8
6518 11:48:30.426314 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6519 11:48:30.430320 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6520 11:48:30.433152 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6521 11:48:30.436394 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6522 11:48:30.443709 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6523 11:48:30.446161 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6524 11:48:30.449761 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6525 11:48:30.453308 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6526 11:48:30.459306 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6527 11:48:30.462543 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6528 11:48:30.465890 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6529 11:48:30.472746 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6530 11:48:30.476178 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6531 11:48:30.479511 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6532 11:48:30.482845 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6533 11:48:30.489521 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6534 11:48:30.490023 ==
6535 11:48:30.492523 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 11:48:30.495786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 11:48:30.496298 ==
6538 11:48:30.496634 DQS Delay:
6539 11:48:30.499291 DQS0 = 40, DQS1 = 60
6540 11:48:30.499700 DQM Delay:
6541 11:48:30.502586 DQM0 = 6, DQM1 = 14
6542 11:48:30.503139 DQ Delay:
6543 11:48:30.505515 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6544 11:48:30.509419 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6545 11:48:30.512270 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6546 11:48:30.515630 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6547 11:48:30.516136
6548 11:48:30.516465
6549 11:48:30.522291 [DQSOSCAuto] RK1, (LSB)MR18= 0x857e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6550 11:48:30.525414 CH0 RK1: MR19=C0C, MR18=857E
6551 11:48:30.532142 CH0_RK1: MR19=0xC0C, MR18=0x857E, DQSOSC=393, MR23=63, INC=382, DEC=254
6552 11:48:30.535086 [RxdqsGatingPostProcess] freq 400
6553 11:48:30.541843 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6554 11:48:30.545644 best DQS0 dly(2T, 0.5T) = (0, 10)
6555 11:48:30.548123 best DQS1 dly(2T, 0.5T) = (0, 10)
6556 11:48:30.551733 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6557 11:48:30.554895 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6558 11:48:30.555307 best DQS0 dly(2T, 0.5T) = (0, 10)
6559 11:48:30.558185 best DQS1 dly(2T, 0.5T) = (0, 10)
6560 11:48:30.561545 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6561 11:48:30.564901 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6562 11:48:30.568627 Pre-setting of DQS Precalculation
6563 11:48:30.574447 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6564 11:48:30.574956 ==
6565 11:48:30.578160 Dram Type= 6, Freq= 0, CH_1, rank 0
6566 11:48:30.580783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 11:48:30.581212 ==
6568 11:48:30.587992 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6569 11:48:30.594191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6570 11:48:30.597920 [CA 0] Center 36 (8~64) winsize 57
6571 11:48:30.600536 [CA 1] Center 36 (8~64) winsize 57
6572 11:48:30.604136 [CA 2] Center 36 (8~64) winsize 57
6573 11:48:30.607572 [CA 3] Center 36 (8~64) winsize 57
6574 11:48:30.608078 [CA 4] Center 36 (8~64) winsize 57
6575 11:48:30.610492 [CA 5] Center 36 (8~64) winsize 57
6576 11:48:30.611009
6577 11:48:30.617754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6578 11:48:30.618295
6579 11:48:30.620706 [CATrainingPosCal] consider 1 rank data
6580 11:48:30.624100 u2DelayCellTimex100 = 270/100 ps
6581 11:48:30.627347 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6582 11:48:30.631184 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 11:48:30.633423 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 11:48:30.637063 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 11:48:30.639954 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 11:48:30.643454 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 11:48:30.643966
6588 11:48:30.646390 CA PerBit enable=1, Macro0, CA PI delay=36
6589 11:48:30.646864
6590 11:48:30.650005 [CBTSetCACLKResult] CA Dly = 36
6591 11:48:30.653474 CS Dly: 1 (0~32)
6592 11:48:30.654025 ==
6593 11:48:30.656789 Dram Type= 6, Freq= 0, CH_1, rank 1
6594 11:48:30.659746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 11:48:30.660168 ==
6596 11:48:30.666996 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 11:48:30.673357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6598 11:48:30.676659 [CA 0] Center 36 (8~64) winsize 57
6599 11:48:30.679363 [CA 1] Center 36 (8~64) winsize 57
6600 11:48:30.682991 [CA 2] Center 36 (8~64) winsize 57
6601 11:48:30.683504 [CA 3] Center 36 (8~64) winsize 57
6602 11:48:30.686559 [CA 4] Center 36 (8~64) winsize 57
6603 11:48:30.689652 [CA 5] Center 36 (8~64) winsize 57
6604 11:48:30.690196
6605 11:48:30.696197 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6606 11:48:30.696750
6607 11:48:30.700181 [CATrainingPosCal] consider 2 rank data
6608 11:48:30.702994 u2DelayCellTimex100 = 270/100 ps
6609 11:48:30.706022 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:48:30.709462 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:48:30.712577 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:48:30.716462 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:48:30.718848 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:48:30.722322 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:48:30.722834
6616 11:48:30.725546 CA PerBit enable=1, Macro0, CA PI delay=36
6617 11:48:30.726101
6618 11:48:30.729167 [CBTSetCACLKResult] CA Dly = 36
6619 11:48:30.732295 CS Dly: 1 (0~32)
6620 11:48:30.732721
6621 11:48:30.735429 ----->DramcWriteLeveling(PI) begin...
6622 11:48:30.735853 ==
6623 11:48:30.739089 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 11:48:30.742219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 11:48:30.742684 ==
6626 11:48:30.745215 Write leveling (Byte 0): 40 => 8
6627 11:48:30.748954 Write leveling (Byte 1): 40 => 8
6628 11:48:30.751928 DramcWriteLeveling(PI) end<-----
6629 11:48:30.752348
6630 11:48:30.752680 ==
6631 11:48:30.755412 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 11:48:30.758579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 11:48:30.759007 ==
6634 11:48:30.762123 [Gating] SW mode calibration
6635 11:48:30.768802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6636 11:48:30.774814 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6637 11:48:30.778583 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6638 11:48:30.784841 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 11:48:30.788180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6640 11:48:30.791785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 11:48:30.797803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6642 11:48:30.801201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 11:48:30.804248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 11:48:30.811148 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 11:48:30.814224 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6646 11:48:30.817748 Total UI for P1: 0, mck2ui 16
6647 11:48:30.821049 best dqsien dly found for B0: ( 0, 14, 24)
6648 11:48:30.824463 Total UI for P1: 0, mck2ui 16
6649 11:48:30.827369 best dqsien dly found for B1: ( 0, 14, 24)
6650 11:48:30.830812 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6651 11:48:30.834096 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6652 11:48:30.834571
6653 11:48:30.837756 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6654 11:48:30.841092 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6655 11:48:30.843979 [Gating] SW calibration Done
6656 11:48:30.844403 ==
6657 11:48:30.847093 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 11:48:30.854101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 11:48:30.854607 ==
6660 11:48:30.855043 RX Vref Scan: 0
6661 11:48:30.855449
6662 11:48:30.857081 RX Vref 0 -> 0, step: 1
6663 11:48:30.857581
6664 11:48:30.860163 RX Delay -410 -> 252, step: 16
6665 11:48:30.863407 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6666 11:48:30.866695 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6667 11:48:30.873329 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6668 11:48:30.876867 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6669 11:48:30.880724 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6670 11:48:30.883697 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6671 11:48:30.890245 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6672 11:48:30.893243 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6673 11:48:30.896572 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6674 11:48:30.899531 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6675 11:48:30.906712 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6676 11:48:30.910064 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6677 11:48:30.913062 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6678 11:48:30.919575 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6679 11:48:30.923065 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6680 11:48:30.925890 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6681 11:48:30.926438 ==
6682 11:48:30.929297 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 11:48:30.933001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 11:48:30.936291 ==
6685 11:48:30.936879 DQS Delay:
6686 11:48:30.937225 DQS0 = 35, DQS1 = 51
6687 11:48:30.939436 DQM Delay:
6688 11:48:30.939853 DQM0 = 6, DQM1 = 13
6689 11:48:30.942524 DQ Delay:
6690 11:48:30.942943 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6691 11:48:30.946547 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6692 11:48:30.949697 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6693 11:48:30.952640 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6694 11:48:30.953152
6695 11:48:30.953485
6696 11:48:30.953796 ==
6697 11:48:30.955850 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 11:48:30.962808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 11:48:30.963322 ==
6700 11:48:30.963661
6701 11:48:30.963969
6702 11:48:30.965829 TX Vref Scan disable
6703 11:48:30.966372 == TX Byte 0 ==
6704 11:48:30.969733 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6705 11:48:30.975823 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6706 11:48:30.976354 == TX Byte 1 ==
6707 11:48:30.979249 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6708 11:48:30.985742 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6709 11:48:30.986289 ==
6710 11:48:30.988737 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 11:48:30.992452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 11:48:30.992967 ==
6713 11:48:30.993304
6714 11:48:30.993612
6715 11:48:30.995072 TX Vref Scan disable
6716 11:48:30.995491 == TX Byte 0 ==
6717 11:48:30.998351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 11:48:31.005296 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 11:48:31.005811 == TX Byte 1 ==
6720 11:48:31.008557 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 11:48:31.015104 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 11:48:31.015614
6723 11:48:31.015951 [DATLAT]
6724 11:48:31.018295 Freq=400, CH1 RK0
6725 11:48:31.018840
6726 11:48:31.019193 DATLAT Default: 0xf
6727 11:48:31.021866 0, 0xFFFF, sum = 0
6728 11:48:31.022428 1, 0xFFFF, sum = 0
6729 11:48:31.025047 2, 0xFFFF, sum = 0
6730 11:48:31.025575 3, 0xFFFF, sum = 0
6731 11:48:31.027954 4, 0xFFFF, sum = 0
6732 11:48:31.028376 5, 0xFFFF, sum = 0
6733 11:48:31.031656 6, 0xFFFF, sum = 0
6734 11:48:31.032169 7, 0xFFFF, sum = 0
6735 11:48:31.034205 8, 0xFFFF, sum = 0
6736 11:48:31.034865 9, 0xFFFF, sum = 0
6737 11:48:31.037796 10, 0xFFFF, sum = 0
6738 11:48:31.038214 11, 0xFFFF, sum = 0
6739 11:48:31.041018 12, 0xFFFF, sum = 0
6740 11:48:31.041534 13, 0x0, sum = 1
6741 11:48:31.044975 14, 0x0, sum = 2
6742 11:48:31.045636 15, 0x0, sum = 3
6743 11:48:31.047438 16, 0x0, sum = 4
6744 11:48:31.047852 best_step = 14
6745 11:48:31.048178
6746 11:48:31.048483 ==
6747 11:48:31.051127 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 11:48:31.057374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 11:48:31.057798 ==
6750 11:48:31.058133 RX Vref Scan: 1
6751 11:48:31.058513
6752 11:48:31.060897 RX Vref 0 -> 0, step: 1
6753 11:48:31.061317
6754 11:48:31.064275 RX Delay -343 -> 252, step: 8
6755 11:48:31.064691
6756 11:48:31.067630 Set Vref, RX VrefLevel [Byte0]: 52
6757 11:48:31.070730 [Byte1]: 52
6758 11:48:31.074595
6759 11:48:31.075104 Final RX Vref Byte 0 = 52 to rank0
6760 11:48:31.077636 Final RX Vref Byte 1 = 52 to rank0
6761 11:48:31.081076 Final RX Vref Byte 0 = 52 to rank1
6762 11:48:31.084312 Final RX Vref Byte 1 = 52 to rank1==
6763 11:48:31.087168 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 11:48:31.094196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 11:48:31.094748 ==
6766 11:48:31.095089 DQS Delay:
6767 11:48:31.097149 DQS0 = 44, DQS1 = 52
6768 11:48:31.097568 DQM Delay:
6769 11:48:31.097902 DQM0 = 10, DQM1 = 10
6770 11:48:31.100747 DQ Delay:
6771 11:48:31.103913 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6772 11:48:31.107510 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6773 11:48:31.108028 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6774 11:48:31.110460 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6775 11:48:31.114218
6776 11:48:31.114753
6777 11:48:31.120801 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6778 11:48:31.123853 CH1 RK0: MR19=C0C, MR18=5F87
6779 11:48:31.130308 CH1_RK0: MR19=0xC0C, MR18=0x5F87, DQSOSC=392, MR23=63, INC=384, DEC=256
6780 11:48:31.130815 ==
6781 11:48:31.133902 Dram Type= 6, Freq= 0, CH_1, rank 1
6782 11:48:31.136864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:48:31.137391 ==
6784 11:48:31.139992 [Gating] SW mode calibration
6785 11:48:31.146457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6786 11:48:31.153539 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6787 11:48:31.156697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 11:48:31.159815 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 11:48:31.165973 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 11:48:31.169161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 11:48:31.173192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 11:48:31.179459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 11:48:31.182845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 11:48:31.186422 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 11:48:31.192802 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6796 11:48:31.196078 Total UI for P1: 0, mck2ui 16
6797 11:48:31.198733 best dqsien dly found for B0: ( 0, 14, 24)
6798 11:48:31.202465 Total UI for P1: 0, mck2ui 16
6799 11:48:31.205657 best dqsien dly found for B1: ( 0, 14, 24)
6800 11:48:31.208764 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6801 11:48:31.212384 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6802 11:48:31.212896
6803 11:48:31.215746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 11:48:31.219047 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 11:48:31.222552 [Gating] SW calibration Done
6806 11:48:31.223072 ==
6807 11:48:31.225310 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 11:48:31.228600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 11:48:31.231912 ==
6810 11:48:31.232337 RX Vref Scan: 0
6811 11:48:31.232769
6812 11:48:31.235287 RX Vref 0 -> 0, step: 1
6813 11:48:31.235710
6814 11:48:31.238323 RX Delay -410 -> 252, step: 16
6815 11:48:31.242299 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6816 11:48:31.245564 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6817 11:48:31.248058 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6818 11:48:31.255120 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6819 11:48:31.258387 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6820 11:48:31.261381 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6821 11:48:31.265288 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6822 11:48:31.271507 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6823 11:48:31.275091 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6824 11:48:31.277972 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6825 11:48:31.281799 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6826 11:48:31.287660 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6827 11:48:31.291256 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6828 11:48:31.294632 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6829 11:48:31.301583 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6830 11:48:31.304886 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6831 11:48:31.305406 ==
6832 11:48:31.307335 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 11:48:31.310786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 11:48:31.311202 ==
6835 11:48:31.314903 DQS Delay:
6836 11:48:31.315417 DQS0 = 43, DQS1 = 51
6837 11:48:31.317632 DQM Delay:
6838 11:48:31.318042 DQM0 = 10, DQM1 = 14
6839 11:48:31.318395 DQ Delay:
6840 11:48:31.320953 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6841 11:48:31.324399 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6842 11:48:31.327082 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6843 11:48:31.330438 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6844 11:48:31.331019
6845 11:48:31.331363
6846 11:48:31.331675 ==
6847 11:48:31.333494 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 11:48:31.340383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 11:48:31.340897 ==
6850 11:48:31.341236
6851 11:48:31.341543
6852 11:48:31.341835 TX Vref Scan disable
6853 11:48:31.343628 == TX Byte 0 ==
6854 11:48:31.346775 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6855 11:48:31.350907 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6856 11:48:31.354378 == TX Byte 1 ==
6857 11:48:31.357051 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6858 11:48:31.360269 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6859 11:48:31.360787 ==
6860 11:48:31.363812 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 11:48:31.369813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 11:48:31.370514 ==
6863 11:48:31.370882
6864 11:48:31.371198
6865 11:48:31.373472 TX Vref Scan disable
6866 11:48:31.373985 == TX Byte 0 ==
6867 11:48:31.376766 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6868 11:48:31.379617 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6869 11:48:31.383262 == TX Byte 1 ==
6870 11:48:31.386602 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6871 11:48:31.390533 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6872 11:48:31.392794
6873 11:48:31.393207 [DATLAT]
6874 11:48:31.393537 Freq=400, CH1 RK1
6875 11:48:31.393843
6876 11:48:31.396614 DATLAT Default: 0xe
6877 11:48:31.397028 0, 0xFFFF, sum = 0
6878 11:48:31.399332 1, 0xFFFF, sum = 0
6879 11:48:31.399778 2, 0xFFFF, sum = 0
6880 11:48:31.402828 3, 0xFFFF, sum = 0
6881 11:48:31.406433 4, 0xFFFF, sum = 0
6882 11:48:31.406953 5, 0xFFFF, sum = 0
6883 11:48:31.409877 6, 0xFFFF, sum = 0
6884 11:48:31.410450 7, 0xFFFF, sum = 0
6885 11:48:31.413002 8, 0xFFFF, sum = 0
6886 11:48:31.413528 9, 0xFFFF, sum = 0
6887 11:48:31.416186 10, 0xFFFF, sum = 0
6888 11:48:31.416702 11, 0xFFFF, sum = 0
6889 11:48:31.419849 12, 0xFFFF, sum = 0
6890 11:48:31.420270 13, 0x0, sum = 1
6891 11:48:31.423177 14, 0x0, sum = 2
6892 11:48:31.423699 15, 0x0, sum = 3
6893 11:48:31.425912 16, 0x0, sum = 4
6894 11:48:31.426416 best_step = 14
6895 11:48:31.426755
6896 11:48:31.427065 ==
6897 11:48:31.429034 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 11:48:31.432149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 11:48:31.435869 ==
6900 11:48:31.436286 RX Vref Scan: 0
6901 11:48:31.436619
6902 11:48:31.439097 RX Vref 0 -> 0, step: 1
6903 11:48:31.439511
6904 11:48:31.442825 RX Delay -343 -> 252, step: 8
6905 11:48:31.448986 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6906 11:48:31.452421 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6907 11:48:31.455476 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6908 11:48:31.459210 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6909 11:48:31.465326 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6910 11:48:31.468940 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6911 11:48:31.472501 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6912 11:48:31.475365 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6913 11:48:31.481987 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6914 11:48:31.485019 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6915 11:48:31.488443 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6916 11:48:31.491834 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6917 11:48:31.498274 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6918 11:48:31.501797 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6919 11:48:31.505349 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6920 11:48:31.511551 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6921 11:48:31.512202 ==
6922 11:48:31.514933 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 11:48:31.518172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 11:48:31.518741 ==
6925 11:48:31.519183 DQS Delay:
6926 11:48:31.521802 DQS0 = 48, DQS1 = 52
6927 11:48:31.522372 DQM Delay:
6928 11:48:31.524864 DQM0 = 10, DQM1 = 11
6929 11:48:31.525388 DQ Delay:
6930 11:48:31.528053 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6931 11:48:31.531315 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6932 11:48:31.534644 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6933 11:48:31.538300 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6934 11:48:31.538728
6935 11:48:31.539156
6936 11:48:31.544579 [DQSOSCAuto] RK1, (LSB)MR18= 0x78b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6937 11:48:31.547509 CH1 RK1: MR19=C0C, MR18=78B0
6938 11:48:31.554577 CH1_RK1: MR19=0xC0C, MR18=0x78B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6939 11:48:31.557800 [RxdqsGatingPostProcess] freq 400
6940 11:48:31.564358 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6941 11:48:31.567617 best DQS0 dly(2T, 0.5T) = (0, 10)
6942 11:48:31.570813 best DQS1 dly(2T, 0.5T) = (0, 10)
6943 11:48:31.574174 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6944 11:48:31.577859 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6945 11:48:31.578434 best DQS0 dly(2T, 0.5T) = (0, 10)
6946 11:48:31.580684 best DQS1 dly(2T, 0.5T) = (0, 10)
6947 11:48:31.583861 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6948 11:48:31.587213 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6949 11:48:31.590317 Pre-setting of DQS Precalculation
6950 11:48:31.596779 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6951 11:48:31.604198 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6952 11:48:31.610473 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6953 11:48:31.610998
6954 11:48:31.611335
6955 11:48:31.613424 [Calibration Summary] 800 Mbps
6956 11:48:31.613941 CH 0, Rank 0
6957 11:48:31.616605 SW Impedance : PASS
6958 11:48:31.620145 DUTY Scan : NO K
6959 11:48:31.620701 ZQ Calibration : PASS
6960 11:48:31.623225 Jitter Meter : NO K
6961 11:48:31.626715 CBT Training : PASS
6962 11:48:31.627307 Write leveling : PASS
6963 11:48:31.629943 RX DQS gating : PASS
6964 11:48:31.632901 RX DQ/DQS(RDDQC) : PASS
6965 11:48:31.633318 TX DQ/DQS : PASS
6966 11:48:31.636525 RX DATLAT : PASS
6967 11:48:31.639705 RX DQ/DQS(Engine): PASS
6968 11:48:31.640116 TX OE : NO K
6969 11:48:31.643198 All Pass.
6970 11:48:31.643697
6971 11:48:31.644032 CH 0, Rank 1
6972 11:48:31.646079 SW Impedance : PASS
6973 11:48:31.646656 DUTY Scan : NO K
6974 11:48:31.649188 ZQ Calibration : PASS
6975 11:48:31.653074 Jitter Meter : NO K
6976 11:48:31.653488 CBT Training : PASS
6977 11:48:31.656317 Write leveling : NO K
6978 11:48:31.659260 RX DQS gating : PASS
6979 11:48:31.659696 RX DQ/DQS(RDDQC) : PASS
6980 11:48:31.662945 TX DQ/DQS : PASS
6981 11:48:31.666119 RX DATLAT : PASS
6982 11:48:31.666698 RX DQ/DQS(Engine): PASS
6983 11:48:31.669696 TX OE : NO K
6984 11:48:31.670206 All Pass.
6985 11:48:31.670853
6986 11:48:31.672372 CH 1, Rank 0
6987 11:48:31.672788 SW Impedance : PASS
6988 11:48:31.676604 DUTY Scan : NO K
6989 11:48:31.679213 ZQ Calibration : PASS
6990 11:48:31.679721 Jitter Meter : NO K
6991 11:48:31.682684 CBT Training : PASS
6992 11:48:31.683094 Write leveling : PASS
6993 11:48:31.686058 RX DQS gating : PASS
6994 11:48:31.689166 RX DQ/DQS(RDDQC) : PASS
6995 11:48:31.689672 TX DQ/DQS : PASS
6996 11:48:31.692765 RX DATLAT : PASS
6997 11:48:31.696307 RX DQ/DQS(Engine): PASS
6998 11:48:31.696901 TX OE : NO K
6999 11:48:31.699077 All Pass.
7000 11:48:31.699490
7001 11:48:31.699818 CH 1, Rank 1
7002 11:48:31.702745 SW Impedance : PASS
7003 11:48:31.703294 DUTY Scan : NO K
7004 11:48:31.705743 ZQ Calibration : PASS
7005 11:48:31.708695 Jitter Meter : NO K
7006 11:48:31.709180 CBT Training : PASS
7007 11:48:31.712145 Write leveling : NO K
7008 11:48:31.715788 RX DQS gating : PASS
7009 11:48:31.716217 RX DQ/DQS(RDDQC) : PASS
7010 11:48:31.718612 TX DQ/DQS : PASS
7011 11:48:31.722415 RX DATLAT : PASS
7012 11:48:31.722938 RX DQ/DQS(Engine): PASS
7013 11:48:31.725396 TX OE : NO K
7014 11:48:31.725913 All Pass.
7015 11:48:31.726452
7016 11:48:31.728763 DramC Write-DBI off
7017 11:48:31.732064 PER_BANK_REFRESH: Hybrid Mode
7018 11:48:31.732494 TX_TRACKING: ON
7019 11:48:31.741862 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7020 11:48:31.744970 [FAST_K] Save calibration result to emmc
7021 11:48:31.748101 dramc_set_vcore_voltage set vcore to 725000
7022 11:48:31.751890 Read voltage for 1600, 0
7023 11:48:31.752303 Vio18 = 0
7024 11:48:31.752654 Vcore = 725000
7025 11:48:31.754964 Vdram = 0
7026 11:48:31.755436 Vddq = 0
7027 11:48:31.755772 Vmddr = 0
7028 11:48:31.761699 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7029 11:48:31.764881 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7030 11:48:31.768980 MEM_TYPE=3, freq_sel=13
7031 11:48:31.771716 sv_algorithm_assistance_LP4_3733
7032 11:48:31.774869 ============ PULL DRAM RESETB DOWN ============
7033 11:48:31.781911 ========== PULL DRAM RESETB DOWN end =========
7034 11:48:31.784529 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7035 11:48:31.788160 ===================================
7036 11:48:31.791200 LPDDR4 DRAM CONFIGURATION
7037 11:48:31.794420 ===================================
7038 11:48:31.794930 EX_ROW_EN[0] = 0x0
7039 11:48:31.798161 EX_ROW_EN[1] = 0x0
7040 11:48:31.798896 LP4Y_EN = 0x0
7041 11:48:31.801318 WORK_FSP = 0x1
7042 11:48:31.801836 WL = 0x5
7043 11:48:31.804164 RL = 0x5
7044 11:48:31.807617 BL = 0x2
7045 11:48:31.808137 RPST = 0x0
7046 11:48:31.811173 RD_PRE = 0x0
7047 11:48:31.811588 WR_PRE = 0x1
7048 11:48:31.814075 WR_PST = 0x1
7049 11:48:31.814523 DBI_WR = 0x0
7050 11:48:31.817239 DBI_RD = 0x0
7051 11:48:31.817676 OTF = 0x1
7052 11:48:31.820574 ===================================
7053 11:48:31.824039 ===================================
7054 11:48:31.827508 ANA top config
7055 11:48:31.830801 ===================================
7056 11:48:31.831319 DLL_ASYNC_EN = 0
7057 11:48:31.833737 ALL_SLAVE_EN = 0
7058 11:48:31.837203 NEW_RANK_MODE = 1
7059 11:48:31.840339 DLL_IDLE_MODE = 1
7060 11:48:31.843739 LP45_APHY_COMB_EN = 1
7061 11:48:31.844179 TX_ODT_DIS = 0
7062 11:48:31.846965 NEW_8X_MODE = 1
7063 11:48:31.850043 ===================================
7064 11:48:31.853451 ===================================
7065 11:48:31.856985 data_rate = 3200
7066 11:48:31.860333 CKR = 1
7067 11:48:31.864282 DQ_P2S_RATIO = 8
7068 11:48:31.866717 ===================================
7069 11:48:31.870358 CA_P2S_RATIO = 8
7070 11:48:31.870775 DQ_CA_OPEN = 0
7071 11:48:31.873165 DQ_SEMI_OPEN = 0
7072 11:48:31.876743 CA_SEMI_OPEN = 0
7073 11:48:31.879918 CA_FULL_RATE = 0
7074 11:48:31.883161 DQ_CKDIV4_EN = 0
7075 11:48:31.886481 CA_CKDIV4_EN = 0
7076 11:48:31.886893 CA_PREDIV_EN = 0
7077 11:48:31.890012 PH8_DLY = 12
7078 11:48:31.893345 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7079 11:48:31.896110 DQ_AAMCK_DIV = 4
7080 11:48:31.899593 CA_AAMCK_DIV = 4
7081 11:48:31.902885 CA_ADMCK_DIV = 4
7082 11:48:31.903299 DQ_TRACK_CA_EN = 0
7083 11:48:31.906143 CA_PICK = 1600
7084 11:48:31.909319 CA_MCKIO = 1600
7085 11:48:31.912800 MCKIO_SEMI = 0
7086 11:48:31.915776 PLL_FREQ = 3068
7087 11:48:31.919210 DQ_UI_PI_RATIO = 32
7088 11:48:31.922664 CA_UI_PI_RATIO = 0
7089 11:48:31.925825 ===================================
7090 11:48:31.929015 ===================================
7091 11:48:31.932247 memory_type:LPDDR4
7092 11:48:31.932657 GP_NUM : 10
7093 11:48:31.935446 SRAM_EN : 1
7094 11:48:31.935865 MD32_EN : 0
7095 11:48:31.939668 ===================================
7096 11:48:31.942846 [ANA_INIT] >>>>>>>>>>>>>>
7097 11:48:31.945446 <<<<<< [CONFIGURE PHASE]: ANA_TX
7098 11:48:31.949141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7099 11:48:31.952709 ===================================
7100 11:48:31.955547 data_rate = 3200,PCW = 0X7600
7101 11:48:31.958704 ===================================
7102 11:48:31.962072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7103 11:48:31.968871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7104 11:48:31.971933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7105 11:48:31.978896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7106 11:48:31.982433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7107 11:48:31.985389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7108 11:48:31.985918 [ANA_INIT] flow start
7109 11:48:31.988704 [ANA_INIT] PLL >>>>>>>>
7110 11:48:31.991749 [ANA_INIT] PLL <<<<<<<<
7111 11:48:31.992165 [ANA_INIT] MIDPI >>>>>>>>
7112 11:48:31.995004 [ANA_INIT] MIDPI <<<<<<<<
7113 11:48:31.998363 [ANA_INIT] DLL >>>>>>>>
7114 11:48:31.998796 [ANA_INIT] DLL <<<<<<<<
7115 11:48:32.001821 [ANA_INIT] flow end
7116 11:48:32.005464 ============ LP4 DIFF to SE enter ============
7117 11:48:32.011440 ============ LP4 DIFF to SE exit ============
7118 11:48:32.011956 [ANA_INIT] <<<<<<<<<<<<<
7119 11:48:32.015007 [Flow] Enable top DCM control >>>>>
7120 11:48:32.018364 [Flow] Enable top DCM control <<<<<
7121 11:48:32.021090 Enable DLL master slave shuffle
7122 11:48:32.028250 ==============================================================
7123 11:48:32.028769 Gating Mode config
7124 11:48:32.034353 ==============================================================
7125 11:48:32.037660 Config description:
7126 11:48:32.047846 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7127 11:48:32.054201 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7128 11:48:32.057323 SELPH_MODE 0: By rank 1: By Phase
7129 11:48:32.064313 ==============================================================
7130 11:48:32.067497 GAT_TRACK_EN = 1
7131 11:48:32.070983 RX_GATING_MODE = 2
7132 11:48:32.073750 RX_GATING_TRACK_MODE = 2
7133 11:48:32.074309 SELPH_MODE = 1
7134 11:48:32.077328 PICG_EARLY_EN = 1
7135 11:48:32.080638 VALID_LAT_VALUE = 1
7136 11:48:32.086988 ==============================================================
7137 11:48:32.090521 Enter into Gating configuration >>>>
7138 11:48:32.094015 Exit from Gating configuration <<<<
7139 11:48:32.097084 Enter into DVFS_PRE_config >>>>>
7140 11:48:32.107026 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7141 11:48:32.110033 Exit from DVFS_PRE_config <<<<<
7142 11:48:32.113168 Enter into PICG configuration >>>>
7143 11:48:32.116304 Exit from PICG configuration <<<<
7144 11:48:32.119844 [RX_INPUT] configuration >>>>>
7145 11:48:32.123170 [RX_INPUT] configuration <<<<<
7146 11:48:32.126569 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7147 11:48:32.133795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7148 11:48:32.139983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7149 11:48:32.146023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7150 11:48:32.152628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7151 11:48:32.159897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7152 11:48:32.162767 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7153 11:48:32.166397 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7154 11:48:32.169077 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7155 11:48:32.175903 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7156 11:48:32.179119 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7157 11:48:32.182457 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 11:48:32.186127 ===================================
7159 11:48:32.189220 LPDDR4 DRAM CONFIGURATION
7160 11:48:32.192362 ===================================
7161 11:48:32.195785 EX_ROW_EN[0] = 0x0
7162 11:48:32.196221 EX_ROW_EN[1] = 0x0
7163 11:48:32.198583 LP4Y_EN = 0x0
7164 11:48:32.199016 WORK_FSP = 0x1
7165 11:48:32.202597 WL = 0x5
7166 11:48:32.203313 RL = 0x5
7167 11:48:32.205640 BL = 0x2
7168 11:48:32.206161 RPST = 0x0
7169 11:48:32.208699 RD_PRE = 0x0
7170 11:48:32.209131 WR_PRE = 0x1
7171 11:48:32.212340 WR_PST = 0x1
7172 11:48:32.212871 DBI_WR = 0x0
7173 11:48:32.214982 DBI_RD = 0x0
7174 11:48:32.215415 OTF = 0x1
7175 11:48:32.218703 ===================================
7176 11:48:32.224844 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7177 11:48:32.228383 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7178 11:48:32.231968 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 11:48:32.235193 ===================================
7180 11:48:32.238328 LPDDR4 DRAM CONFIGURATION
7181 11:48:32.241546 ===================================
7182 11:48:32.245127 EX_ROW_EN[0] = 0x10
7183 11:48:32.245652 EX_ROW_EN[1] = 0x0
7184 11:48:32.248244 LP4Y_EN = 0x0
7185 11:48:32.248666 WORK_FSP = 0x1
7186 11:48:32.251877 WL = 0x5
7187 11:48:32.252531 RL = 0x5
7188 11:48:32.254826 BL = 0x2
7189 11:48:32.255244 RPST = 0x0
7190 11:48:32.257813 RD_PRE = 0x0
7191 11:48:32.258226 WR_PRE = 0x1
7192 11:48:32.261900 WR_PST = 0x1
7193 11:48:32.262458 DBI_WR = 0x0
7194 11:48:32.264831 DBI_RD = 0x0
7195 11:48:32.265246 OTF = 0x1
7196 11:48:32.268311 ===================================
7197 11:48:32.275025 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7198 11:48:32.275556 ==
7199 11:48:32.277860 Dram Type= 6, Freq= 0, CH_0, rank 0
7200 11:48:32.284747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7201 11:48:32.285237 ==
7202 11:48:32.285574 [Duty_Offset_Calibration]
7203 11:48:32.287402 B0:2 B1:0 CA:4
7204 11:48:32.287814
7205 11:48:32.290566 [DutyScan_Calibration_Flow] k_type=0
7206 11:48:32.299399
7207 11:48:32.299883 ==CLK 0==
7208 11:48:32.302996 Final CLK duty delay cell = -4
7209 11:48:32.306148 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7210 11:48:32.309688 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7211 11:48:32.312525 [-4] AVG Duty = 4937%(X100)
7212 11:48:32.313038
7213 11:48:32.315980 CH0 CLK Duty spec in!! Max-Min= 187%
7214 11:48:32.319075 [DutyScan_Calibration_Flow] ====Done====
7215 11:48:32.319488
7216 11:48:32.322147 [DutyScan_Calibration_Flow] k_type=1
7217 11:48:32.339654
7218 11:48:32.340141 ==DQS 0 ==
7219 11:48:32.343505 Final DQS duty delay cell = 0
7220 11:48:32.346207 [0] MAX Duty = 5218%(X100), DQS PI = 22
7221 11:48:32.349591 [0] MIN Duty = 5093%(X100), DQS PI = 10
7222 11:48:32.353426 [0] AVG Duty = 5155%(X100)
7223 11:48:32.353877
7224 11:48:32.354222 ==DQS 1 ==
7225 11:48:32.356524 Final DQS duty delay cell = 0
7226 11:48:32.360025 [0] MAX Duty = 5187%(X100), DQS PI = 2
7227 11:48:32.363173 [0] MIN Duty = 4969%(X100), DQS PI = 10
7228 11:48:32.366347 [0] AVG Duty = 5078%(X100)
7229 11:48:32.366766
7230 11:48:32.370298 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7231 11:48:32.370827
7232 11:48:32.373000 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7233 11:48:32.376508 [DutyScan_Calibration_Flow] ====Done====
7234 11:48:32.377129
7235 11:48:32.379722 [DutyScan_Calibration_Flow] k_type=3
7236 11:48:32.396963
7237 11:48:32.397427 ==DQM 0 ==
7238 11:48:32.400330 Final DQM duty delay cell = 0
7239 11:48:32.403474 [0] MAX Duty = 5124%(X100), DQS PI = 22
7240 11:48:32.406777 [0] MIN Duty = 4875%(X100), DQS PI = 54
7241 11:48:32.410325 [0] AVG Duty = 4999%(X100)
7242 11:48:32.410744
7243 11:48:32.411078 ==DQM 1 ==
7244 11:48:32.413831 Final DQM duty delay cell = 0
7245 11:48:32.416609 [0] MAX Duty = 4969%(X100), DQS PI = 0
7246 11:48:32.420140 [0] MIN Duty = 4844%(X100), DQS PI = 16
7247 11:48:32.423589 [0] AVG Duty = 4906%(X100)
7248 11:48:32.424106
7249 11:48:32.427124 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7250 11:48:32.427644
7251 11:48:32.430279 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7252 11:48:32.433224 [DutyScan_Calibration_Flow] ====Done====
7253 11:48:32.433643
7254 11:48:32.436819 [DutyScan_Calibration_Flow] k_type=2
7255 11:48:32.454405
7256 11:48:32.454910 ==DQ 0 ==
7257 11:48:32.457332 Final DQ duty delay cell = 0
7258 11:48:32.461001 [0] MAX Duty = 5124%(X100), DQS PI = 20
7259 11:48:32.464179 [0] MIN Duty = 4938%(X100), DQS PI = 12
7260 11:48:32.466983 [0] AVG Duty = 5031%(X100)
7261 11:48:32.467400
7262 11:48:32.467733 ==DQ 1 ==
7263 11:48:32.470547 Final DQ duty delay cell = 0
7264 11:48:32.473785 [0] MAX Duty = 5187%(X100), DQS PI = 4
7265 11:48:32.477319 [0] MIN Duty = 4907%(X100), DQS PI = 34
7266 11:48:32.480314 [0] AVG Duty = 5047%(X100)
7267 11:48:32.480834
7268 11:48:32.483873 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7269 11:48:32.484401
7270 11:48:32.487587 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7271 11:48:32.490563 [DutyScan_Calibration_Flow] ====Done====
7272 11:48:32.490979 ==
7273 11:48:32.493807 Dram Type= 6, Freq= 0, CH_1, rank 0
7274 11:48:32.496626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 11:48:32.497149 ==
7276 11:48:32.500136 [Duty_Offset_Calibration]
7277 11:48:32.500550 B0:0 B1:-1 CA:3
7278 11:48:32.500880
7279 11:48:32.503485 [DutyScan_Calibration_Flow] k_type=0
7280 11:48:32.513637
7281 11:48:32.514217 ==CLK 0==
7282 11:48:32.516797 Final CLK duty delay cell = -4
7283 11:48:32.520176 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7284 11:48:32.523563 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7285 11:48:32.526898 [-4] AVG Duty = 4922%(X100)
7286 11:48:32.527416
7287 11:48:32.530642 CH1 CLK Duty spec in!! Max-Min= 156%
7288 11:48:32.533491 [DutyScan_Calibration_Flow] ====Done====
7289 11:48:32.534013
7290 11:48:32.537498 [DutyScan_Calibration_Flow] k_type=1
7291 11:48:32.553553
7292 11:48:32.554235 ==DQS 0 ==
7293 11:48:32.556253 Final DQS duty delay cell = 0
7294 11:48:32.559265 [0] MAX Duty = 5250%(X100), DQS PI = 28
7295 11:48:32.562525 [0] MIN Duty = 4907%(X100), DQS PI = 56
7296 11:48:32.565599 [0] AVG Duty = 5078%(X100)
7297 11:48:32.566012
7298 11:48:32.566388 ==DQS 1 ==
7299 11:48:32.569266 Final DQS duty delay cell = -4
7300 11:48:32.572155 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7301 11:48:32.575942 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7302 11:48:32.579074 [-4] AVG Duty = 4937%(X100)
7303 11:48:32.579582
7304 11:48:32.582822 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7305 11:48:32.583335
7306 11:48:32.585839 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7307 11:48:32.589142 [DutyScan_Calibration_Flow] ====Done====
7308 11:48:32.589720
7309 11:48:32.592224 [DutyScan_Calibration_Flow] k_type=3
7310 11:48:32.610339
7311 11:48:32.610840 ==DQM 0 ==
7312 11:48:32.613042 Final DQM duty delay cell = 0
7313 11:48:32.617243 [0] MAX Duty = 5062%(X100), DQS PI = 30
7314 11:48:32.619889 [0] MIN Duty = 4782%(X100), DQS PI = 40
7315 11:48:32.622932 [0] AVG Duty = 4922%(X100)
7316 11:48:32.623345
7317 11:48:32.623667 ==DQM 1 ==
7318 11:48:32.626160 Final DQM duty delay cell = 0
7319 11:48:32.629477 [0] MAX Duty = 5000%(X100), DQS PI = 32
7320 11:48:32.632666 [0] MIN Duty = 4813%(X100), DQS PI = 12
7321 11:48:32.635968 [0] AVG Duty = 4906%(X100)
7322 11:48:32.636470
7323 11:48:32.639729 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7324 11:48:32.640185
7325 11:48:32.643203 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7326 11:48:32.646236 [DutyScan_Calibration_Flow] ====Done====
7327 11:48:32.646816
7328 11:48:32.650040 [DutyScan_Calibration_Flow] k_type=2
7329 11:48:32.666013
7330 11:48:32.666547 ==DQ 0 ==
7331 11:48:32.669253 Final DQ duty delay cell = -4
7332 11:48:32.673216 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7333 11:48:32.676175 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7334 11:48:32.679274 [-4] AVG Duty = 4875%(X100)
7335 11:48:32.679702
7336 11:48:32.680137 ==DQ 1 ==
7337 11:48:32.682627 Final DQ duty delay cell = 0
7338 11:48:32.686411 [0] MAX Duty = 5062%(X100), DQS PI = 32
7339 11:48:32.689394 [0] MIN Duty = 4875%(X100), DQS PI = 58
7340 11:48:32.692871 [0] AVG Duty = 4968%(X100)
7341 11:48:32.693572
7342 11:48:32.695989 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7343 11:48:32.696503
7344 11:48:32.699194 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7345 11:48:32.702468 [DutyScan_Calibration_Flow] ====Done====
7346 11:48:32.705791 nWR fixed to 30
7347 11:48:32.709067 [ModeRegInit_LP4] CH0 RK0
7348 11:48:32.709576 [ModeRegInit_LP4] CH0 RK1
7349 11:48:32.711959 [ModeRegInit_LP4] CH1 RK0
7350 11:48:32.715591 [ModeRegInit_LP4] CH1 RK1
7351 11:48:32.716008 match AC timing 5
7352 11:48:32.721877 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7353 11:48:32.725497 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7354 11:48:32.729278 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7355 11:48:32.735723 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7356 11:48:32.738391 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7357 11:48:32.742688 [MiockJmeterHQA]
7358 11:48:32.743197
7359 11:48:32.745127 [DramcMiockJmeter] u1RxGatingPI = 0
7360 11:48:32.745605 0 : 4252, 4027
7361 11:48:32.745940 4 : 4363, 4137
7362 11:48:32.748672 8 : 4252, 4027
7363 11:48:32.749193 12 : 4366, 4139
7364 11:48:32.751614 16 : 4252, 4027
7365 11:48:32.752034 20 : 4253, 4027
7366 11:48:32.755151 24 : 4252, 4027
7367 11:48:32.755574 28 : 4250, 4027
7368 11:48:32.755912 32 : 4363, 4137
7369 11:48:32.758164 36 : 4252, 4027
7370 11:48:32.758656 40 : 4249, 4027
7371 11:48:32.761634 44 : 4252, 4027
7372 11:48:32.762051 48 : 4252, 4029
7373 11:48:32.765010 52 : 4249, 4027
7374 11:48:32.765530 56 : 4363, 4137
7375 11:48:32.768009 60 : 4360, 4138
7376 11:48:32.768430 64 : 4250, 4026
7377 11:48:32.768767 68 : 4250, 4027
7378 11:48:32.771649 72 : 4250, 4027
7379 11:48:32.772070 76 : 4250, 4027
7380 11:48:32.774812 80 : 4253, 4029
7381 11:48:32.775236 84 : 4361, 4137
7382 11:48:32.778066 88 : 4252, 4027
7383 11:48:32.778519 92 : 4249, 4027
7384 11:48:32.781023 96 : 4250, 3391
7385 11:48:32.781445 100 : 4252, 0
7386 11:48:32.781787 104 : 4250, 0
7387 11:48:32.784574 108 : 4250, 0
7388 11:48:32.785001 112 : 4250, 0
7389 11:48:32.787727 116 : 4361, 0
7390 11:48:32.788153 120 : 4361, 0
7391 11:48:32.788496 124 : 4363, 0
7392 11:48:32.790834 128 : 4250, 0
7393 11:48:32.791286 132 : 4250, 0
7394 11:48:32.794457 136 : 4250, 0
7395 11:48:32.794969 140 : 4250, 0
7396 11:48:32.795317 144 : 4250, 0
7397 11:48:32.797677 148 : 4250, 0
7398 11:48:32.798103 152 : 4252, 0
7399 11:48:32.800985 156 : 4250, 0
7400 11:48:32.801413 160 : 4250, 0
7401 11:48:32.801755 164 : 4252, 0
7402 11:48:32.804357 168 : 4361, 0
7403 11:48:32.804877 172 : 4361, 0
7404 11:48:32.808307 176 : 4363, 0
7405 11:48:32.808826 180 : 4250, 0
7406 11:48:32.809184 184 : 4250, 0
7407 11:48:32.810753 188 : 4250, 0
7408 11:48:32.811180 192 : 4250, 0
7409 11:48:32.811522 196 : 4250, 0
7410 11:48:32.813819 200 : 4250, 0
7411 11:48:32.814243 204 : 4252, 0
7412 11:48:32.817703 208 : 4250, 0
7413 11:48:32.818227 212 : 4249, 0
7414 11:48:32.818614 216 : 4252, 0
7415 11:48:32.820727 220 : 4360, 371
7416 11:48:32.821245 224 : 4360, 4037
7417 11:48:32.823818 228 : 4249, 4027
7418 11:48:32.824336 232 : 4250, 4027
7419 11:48:32.827051 236 : 4250, 4027
7420 11:48:32.827570 240 : 4252, 4029
7421 11:48:32.830387 244 : 4250, 4027
7422 11:48:32.830814 248 : 4250, 4026
7423 11:48:32.834319 252 : 4361, 4137
7424 11:48:32.834839 256 : 4250, 4027
7425 11:48:32.836983 260 : 4250, 4027
7426 11:48:32.837408 264 : 4360, 4137
7427 11:48:32.840274 268 : 4250, 4026
7428 11:48:32.840772 272 : 4250, 4027
7429 11:48:32.843566 276 : 4363, 4140
7430 11:48:32.843995 280 : 4250, 4027
7431 11:48:32.844336 284 : 4250, 4026
7432 11:48:32.846892 288 : 4250, 4027
7433 11:48:32.847316 292 : 4252, 4029
7434 11:48:32.850661 296 : 4250, 4027
7435 11:48:32.851206 300 : 4250, 4026
7436 11:48:32.853767 304 : 4361, 4137
7437 11:48:32.854194 308 : 4250, 4027
7438 11:48:32.856885 312 : 4250, 4027
7439 11:48:32.857419 316 : 4361, 4137
7440 11:48:32.859987 320 : 4250, 4026
7441 11:48:32.860412 324 : 4250, 4027
7442 11:48:32.863023 328 : 4363, 4140
7443 11:48:32.863450 332 : 4250, 3998
7444 11:48:32.866758 336 : 4250, 2023
7445 11:48:32.867299
7446 11:48:32.867640 MIOCK jitter meter ch=0
7447 11:48:32.867952
7448 11:48:32.870340 1T = (336-100) = 236 dly cells
7449 11:48:32.876353 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7450 11:48:32.877024 ==
7451 11:48:32.879281 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 11:48:32.883529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7453 11:48:32.884046 ==
7454 11:48:32.889137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7455 11:48:32.892908 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7456 11:48:32.899766 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7457 11:48:32.902654 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7458 11:48:32.912725 [CA 0] Center 44 (14~74) winsize 61
7459 11:48:32.915760 [CA 1] Center 43 (13~74) winsize 62
7460 11:48:32.919172 [CA 2] Center 39 (10~68) winsize 59
7461 11:48:32.922908 [CA 3] Center 38 (9~68) winsize 60
7462 11:48:32.925640 [CA 4] Center 36 (7~66) winsize 60
7463 11:48:32.929677 [CA 5] Center 36 (6~66) winsize 61
7464 11:48:32.930101
7465 11:48:32.933024 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7466 11:48:32.933537
7467 11:48:32.939039 [CATrainingPosCal] consider 1 rank data
7468 11:48:32.939567 u2DelayCellTimex100 = 275/100 ps
7469 11:48:32.945428 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7470 11:48:32.949112 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7471 11:48:32.951990 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7472 11:48:32.955410 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7473 11:48:32.958475 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7474 11:48:32.961910 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7475 11:48:32.962373
7476 11:48:32.965046 CA PerBit enable=1, Macro0, CA PI delay=36
7477 11:48:32.965465
7478 11:48:32.968193 [CBTSetCACLKResult] CA Dly = 36
7479 11:48:32.971740 CS Dly: 11 (0~42)
7480 11:48:32.974858 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7481 11:48:32.978694 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7482 11:48:32.981751 ==
7483 11:48:32.982166 Dram Type= 6, Freq= 0, CH_0, rank 1
7484 11:48:32.988029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 11:48:32.988445 ==
7486 11:48:32.991445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 11:48:32.998365 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 11:48:33.001267 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 11:48:33.007410 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 11:48:33.016340 [CA 0] Center 44 (14~75) winsize 62
7491 11:48:33.019661 [CA 1] Center 44 (14~74) winsize 61
7492 11:48:33.022891 [CA 2] Center 39 (10~69) winsize 60
7493 11:48:33.026419 [CA 3] Center 39 (10~68) winsize 59
7494 11:48:33.029578 [CA 4] Center 37 (7~67) winsize 61
7495 11:48:33.032915 [CA 5] Center 36 (7~66) winsize 60
7496 11:48:33.033433
7497 11:48:33.036311 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 11:48:33.036836
7499 11:48:33.042884 [CATrainingPosCal] consider 2 rank data
7500 11:48:33.043302 u2DelayCellTimex100 = 275/100 ps
7501 11:48:33.049414 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7502 11:48:33.052666 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7503 11:48:33.056342 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7504 11:48:33.059373 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7505 11:48:33.062675 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7506 11:48:33.066330 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7507 11:48:33.066856
7508 11:48:33.069472 CA PerBit enable=1, Macro0, CA PI delay=36
7509 11:48:33.069987
7510 11:48:33.072424 [CBTSetCACLKResult] CA Dly = 36
7511 11:48:33.076187 CS Dly: 12 (0~44)
7512 11:48:33.079351 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 11:48:33.082660 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 11:48:33.083075
7515 11:48:33.085582 ----->DramcWriteLeveling(PI) begin...
7516 11:48:33.089019 ==
7517 11:48:33.089437 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 11:48:33.095865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 11:48:33.096394 ==
7520 11:48:33.099258 Write leveling (Byte 0): 35 => 35
7521 11:48:33.103024 Write leveling (Byte 1): 27 => 27
7522 11:48:33.106033 DramcWriteLeveling(PI) end<-----
7523 11:48:33.106614
7524 11:48:33.106996 ==
7525 11:48:33.109065 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 11:48:33.112168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 11:48:33.112592 ==
7528 11:48:33.115805 [Gating] SW mode calibration
7529 11:48:33.121942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7530 11:48:33.128572 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7531 11:48:33.132418 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7532 11:48:33.135603 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 11:48:33.142011 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7534 11:48:33.145182 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7535 11:48:33.148637 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7536 11:48:33.155131 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7537 11:48:33.158221 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7538 11:48:33.162063 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 11:48:33.168551 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 11:48:33.171879 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 11:48:33.174889 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7542 11:48:33.181910 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7543 11:48:33.185507 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7544 11:48:33.188172 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7545 11:48:33.194532 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7546 11:48:33.198210 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 11:48:33.201481 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 11:48:33.207897 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 11:48:33.212215 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
7550 11:48:33.214978 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7551 11:48:33.221492 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7552 11:48:33.224360 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7553 11:48:33.227717 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7554 11:48:33.234285 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 11:48:33.237606 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 11:48:33.240936 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 11:48:33.247537 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 11:48:33.250643 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7559 11:48:33.254090 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7560 11:48:33.260815 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7561 11:48:33.264158 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 11:48:33.267062 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 11:48:33.273790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 11:48:33.277189 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 11:48:33.280758 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 11:48:33.287733 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 11:48:33.290134 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 11:48:33.293783 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 11:48:33.300324 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 11:48:33.303758 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 11:48:33.306836 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 11:48:33.313347 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 11:48:33.316812 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7574 11:48:33.319469 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7575 11:48:33.326836 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7576 11:48:33.327360 Total UI for P1: 0, mck2ui 16
7577 11:48:33.333206 best dqsien dly found for B0: ( 1, 9, 10)
7578 11:48:33.336097 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7579 11:48:33.340097 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 11:48:33.345904 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 11:48:33.346358 Total UI for P1: 0, mck2ui 16
7582 11:48:33.353010 best dqsien dly found for B1: ( 1, 9, 22)
7583 11:48:33.355714 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7584 11:48:33.359118 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7585 11:48:33.359539
7586 11:48:33.362957 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7587 11:48:33.365941 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7588 11:48:33.369044 [Gating] SW calibration Done
7589 11:48:33.369464 ==
7590 11:48:33.372395 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 11:48:33.376244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 11:48:33.376774 ==
7593 11:48:33.378887 RX Vref Scan: 0
7594 11:48:33.379306
7595 11:48:33.379638 RX Vref 0 -> 0, step: 1
7596 11:48:33.379950
7597 11:48:33.382411 RX Delay 0 -> 252, step: 8
7598 11:48:33.385962 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7599 11:48:33.391867 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7600 11:48:33.395253 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7601 11:48:33.398972 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7602 11:48:33.402101 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7603 11:48:33.405485 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7604 11:48:33.411979 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7605 11:48:33.415087 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7606 11:48:33.418439 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7607 11:48:33.422407 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7608 11:48:33.425297 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7609 11:48:33.431454 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7610 11:48:33.434811 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7611 11:48:33.438870 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7612 11:48:33.441297 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7613 11:48:33.447929 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7614 11:48:33.448408 ==
7615 11:48:33.451525 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 11:48:33.454687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:48:33.455108 ==
7618 11:48:33.455457 DQS Delay:
7619 11:48:33.457924 DQS0 = 0, DQS1 = 0
7620 11:48:33.458370 DQM Delay:
7621 11:48:33.461148 DQM0 = 131, DQM1 = 126
7622 11:48:33.461562 DQ Delay:
7623 11:48:33.464530 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7624 11:48:33.467653 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7625 11:48:33.471023 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7626 11:48:33.478089 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7627 11:48:33.478751
7628 11:48:33.479302
7629 11:48:33.479744 ==
7630 11:48:33.481161 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 11:48:33.484487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 11:48:33.485006 ==
7633 11:48:33.485343
7634 11:48:33.485677
7635 11:48:33.488038 TX Vref Scan disable
7636 11:48:33.488562 == TX Byte 0 ==
7637 11:48:33.494324 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7638 11:48:33.497574 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7639 11:48:33.498084 == TX Byte 1 ==
7640 11:48:33.504048 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7641 11:48:33.507668 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7642 11:48:33.508089 ==
7643 11:48:33.510721 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 11:48:33.513408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 11:48:33.513937 ==
7646 11:48:33.530125
7647 11:48:33.532891 TX Vref early break, caculate TX vref
7648 11:48:33.536734 TX Vref=16, minBit 8, minWin=22, winSum=371
7649 11:48:33.539735 TX Vref=18, minBit 0, minWin=23, winSum=382
7650 11:48:33.543503 TX Vref=20, minBit 1, minWin=23, winSum=389
7651 11:48:33.546187 TX Vref=22, minBit 8, minWin=23, winSum=402
7652 11:48:33.549907 TX Vref=24, minBit 1, minWin=25, winSum=411
7653 11:48:33.556359 TX Vref=26, minBit 4, minWin=25, winSum=417
7654 11:48:33.559353 TX Vref=28, minBit 1, minWin=25, winSum=419
7655 11:48:33.563169 TX Vref=30, minBit 0, minWin=25, winSum=417
7656 11:48:33.566204 TX Vref=32, minBit 0, minWin=24, winSum=410
7657 11:48:33.569132 TX Vref=34, minBit 7, minWin=23, winSum=398
7658 11:48:33.572437 TX Vref=36, minBit 2, minWin=23, winSum=389
7659 11:48:33.579310 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
7660 11:48:33.579735
7661 11:48:33.582608 Final TX Range 0 Vref 28
7662 11:48:33.583027
7663 11:48:33.583410 ==
7664 11:48:33.586820 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 11:48:33.589413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 11:48:33.589912 ==
7667 11:48:33.590248
7668 11:48:33.592320
7669 11:48:33.592800 TX Vref Scan disable
7670 11:48:33.598956 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7671 11:48:33.599376 == TX Byte 0 ==
7672 11:48:33.602821 u2DelayCellOfst[0]=14 cells (4 PI)
7673 11:48:33.605713 u2DelayCellOfst[1]=17 cells (5 PI)
7674 11:48:33.609110 u2DelayCellOfst[2]=14 cells (4 PI)
7675 11:48:33.612676 u2DelayCellOfst[3]=14 cells (4 PI)
7676 11:48:33.615767 u2DelayCellOfst[4]=10 cells (3 PI)
7677 11:48:33.618789 u2DelayCellOfst[5]=0 cells (0 PI)
7678 11:48:33.622772 u2DelayCellOfst[6]=21 cells (6 PI)
7679 11:48:33.625900 u2DelayCellOfst[7]=17 cells (5 PI)
7680 11:48:33.629188 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7681 11:48:33.632196 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7682 11:48:33.635503 == TX Byte 1 ==
7683 11:48:33.639192 u2DelayCellOfst[8]=0 cells (0 PI)
7684 11:48:33.641739 u2DelayCellOfst[9]=0 cells (0 PI)
7685 11:48:33.645145 u2DelayCellOfst[10]=7 cells (2 PI)
7686 11:48:33.648541 u2DelayCellOfst[11]=0 cells (0 PI)
7687 11:48:33.651743 u2DelayCellOfst[12]=10 cells (3 PI)
7688 11:48:33.655239 u2DelayCellOfst[13]=10 cells (3 PI)
7689 11:48:33.658325 u2DelayCellOfst[14]=14 cells (4 PI)
7690 11:48:33.661458 u2DelayCellOfst[15]=10 cells (3 PI)
7691 11:48:33.665046 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7692 11:48:33.668421 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7693 11:48:33.671857 DramC Write-DBI on
7694 11:48:33.672275 ==
7695 11:48:33.674813 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 11:48:33.678446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 11:48:33.678872 ==
7698 11:48:33.679211
7699 11:48:33.679521
7700 11:48:33.681959 TX Vref Scan disable
7701 11:48:33.685157 == TX Byte 0 ==
7702 11:48:33.687700 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7703 11:48:33.688141 == TX Byte 1 ==
7704 11:48:33.694719 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7705 11:48:33.695138 DramC Write-DBI off
7706 11:48:33.695476
7707 11:48:33.695786 [DATLAT]
7708 11:48:33.697828 Freq=1600, CH0 RK0
7709 11:48:33.698245
7710 11:48:33.701070 DATLAT Default: 0xf
7711 11:48:33.701706 0, 0xFFFF, sum = 0
7712 11:48:33.704226 1, 0xFFFF, sum = 0
7713 11:48:33.704655 2, 0xFFFF, sum = 0
7714 11:48:33.707559 3, 0xFFFF, sum = 0
7715 11:48:33.707986 4, 0xFFFF, sum = 0
7716 11:48:33.711034 5, 0xFFFF, sum = 0
7717 11:48:33.711461 6, 0xFFFF, sum = 0
7718 11:48:33.714238 7, 0xFFFF, sum = 0
7719 11:48:33.714831 8, 0xFFFF, sum = 0
7720 11:48:33.717227 9, 0xFFFF, sum = 0
7721 11:48:33.717650 10, 0xFFFF, sum = 0
7722 11:48:33.720573 11, 0xFFFF, sum = 0
7723 11:48:33.721001 12, 0xFFFF, sum = 0
7724 11:48:33.724120 13, 0xFFFF, sum = 0
7725 11:48:33.724545 14, 0x0, sum = 1
7726 11:48:33.727876 15, 0x0, sum = 2
7727 11:48:33.728305 16, 0x0, sum = 3
7728 11:48:33.730379 17, 0x0, sum = 4
7729 11:48:33.730813 best_step = 15
7730 11:48:33.731148
7731 11:48:33.731461 ==
7732 11:48:33.734005 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 11:48:33.740741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 11:48:33.741235 ==
7735 11:48:33.741574 RX Vref Scan: 1
7736 11:48:33.741950
7737 11:48:33.743718 Set Vref Range= 24 -> 127
7738 11:48:33.744164
7739 11:48:33.746803 RX Vref 24 -> 127, step: 1
7740 11:48:33.747242
7741 11:48:33.750684 RX Delay 11 -> 252, step: 4
7742 11:48:33.751168
7743 11:48:33.753420 Set Vref, RX VrefLevel [Byte0]: 24
7744 11:48:33.757416 [Byte1]: 24
7745 11:48:33.757834
7746 11:48:33.760134 Set Vref, RX VrefLevel [Byte0]: 25
7747 11:48:33.763155 [Byte1]: 25
7748 11:48:33.763578
7749 11:48:33.766697 Set Vref, RX VrefLevel [Byte0]: 26
7750 11:48:33.769923 [Byte1]: 26
7751 11:48:33.773742
7752 11:48:33.774235 Set Vref, RX VrefLevel [Byte0]: 27
7753 11:48:33.780024 [Byte1]: 27
7754 11:48:33.780593
7755 11:48:33.783832 Set Vref, RX VrefLevel [Byte0]: 28
7756 11:48:33.786732 [Byte1]: 28
7757 11:48:33.787148
7758 11:48:33.789931 Set Vref, RX VrefLevel [Byte0]: 29
7759 11:48:33.793242 [Byte1]: 29
7760 11:48:33.796504
7761 11:48:33.797016 Set Vref, RX VrefLevel [Byte0]: 30
7762 11:48:33.800004 [Byte1]: 30
7763 11:48:33.803909
7764 11:48:33.804408 Set Vref, RX VrefLevel [Byte0]: 31
7765 11:48:33.807317 [Byte1]: 31
7766 11:48:33.811651
7767 11:48:33.812136 Set Vref, RX VrefLevel [Byte0]: 32
7768 11:48:33.815052 [Byte1]: 32
7769 11:48:33.819562
7770 11:48:33.819975 Set Vref, RX VrefLevel [Byte0]: 33
7771 11:48:33.822623 [Byte1]: 33
7772 11:48:33.826723
7773 11:48:33.827140 Set Vref, RX VrefLevel [Byte0]: 34
7774 11:48:33.830359 [Byte1]: 34
7775 11:48:33.834625
7776 11:48:33.835150 Set Vref, RX VrefLevel [Byte0]: 35
7777 11:48:33.837669 [Byte1]: 35
7778 11:48:33.842391
7779 11:48:33.842809 Set Vref, RX VrefLevel [Byte0]: 36
7780 11:48:33.845672 [Byte1]: 36
7781 11:48:33.849920
7782 11:48:33.850480 Set Vref, RX VrefLevel [Byte0]: 37
7783 11:48:33.853088 [Byte1]: 37
7784 11:48:33.857172
7785 11:48:33.857597 Set Vref, RX VrefLevel [Byte0]: 38
7786 11:48:33.860525 [Byte1]: 38
7787 11:48:33.865007
7788 11:48:33.865521 Set Vref, RX VrefLevel [Byte0]: 39
7789 11:48:33.868000 [Byte1]: 39
7790 11:48:33.873028
7791 11:48:33.873439 Set Vref, RX VrefLevel [Byte0]: 40
7792 11:48:33.875757 [Byte1]: 40
7793 11:48:33.880683
7794 11:48:33.881198 Set Vref, RX VrefLevel [Byte0]: 41
7795 11:48:33.883251 [Byte1]: 41
7796 11:48:33.888308
7797 11:48:33.888831 Set Vref, RX VrefLevel [Byte0]: 42
7798 11:48:33.891568 [Byte1]: 42
7799 11:48:33.895528
7800 11:48:33.895982 Set Vref, RX VrefLevel [Byte0]: 43
7801 11:48:33.898785 [Byte1]: 43
7802 11:48:33.902996
7803 11:48:33.903411 Set Vref, RX VrefLevel [Byte0]: 44
7804 11:48:33.906434 [Byte1]: 44
7805 11:48:33.910634
7806 11:48:33.911141 Set Vref, RX VrefLevel [Byte0]: 45
7807 11:48:33.914160 [Byte1]: 45
7808 11:48:33.918055
7809 11:48:33.918616 Set Vref, RX VrefLevel [Byte0]: 46
7810 11:48:33.921707 [Byte1]: 46
7811 11:48:33.925805
7812 11:48:33.926215 Set Vref, RX VrefLevel [Byte0]: 47
7813 11:48:33.928866 [Byte1]: 47
7814 11:48:33.933938
7815 11:48:33.934480 Set Vref, RX VrefLevel [Byte0]: 48
7816 11:48:33.936713 [Byte1]: 48
7817 11:48:33.941318
7818 11:48:33.941735 Set Vref, RX VrefLevel [Byte0]: 49
7819 11:48:33.944214 [Byte1]: 49
7820 11:48:33.948517
7821 11:48:33.948975 Set Vref, RX VrefLevel [Byte0]: 50
7822 11:48:33.952295 [Byte1]: 50
7823 11:48:33.956379
7824 11:48:33.956852 Set Vref, RX VrefLevel [Byte0]: 51
7825 11:48:33.959299 [Byte1]: 51
7826 11:48:33.964134
7827 11:48:33.964550 Set Vref, RX VrefLevel [Byte0]: 52
7828 11:48:33.966994 [Byte1]: 52
7829 11:48:33.971264
7830 11:48:33.971688 Set Vref, RX VrefLevel [Byte0]: 53
7831 11:48:33.975127 [Byte1]: 53
7832 11:48:33.979040
7833 11:48:33.979456 Set Vref, RX VrefLevel [Byte0]: 54
7834 11:48:33.983121 [Byte1]: 54
7835 11:48:33.986645
7836 11:48:33.987179 Set Vref, RX VrefLevel [Byte0]: 55
7837 11:48:33.990350 [Byte1]: 55
7838 11:48:33.994441
7839 11:48:33.995058 Set Vref, RX VrefLevel [Byte0]: 56
7840 11:48:33.997946 [Byte1]: 56
7841 11:48:34.002180
7842 11:48:34.002747 Set Vref, RX VrefLevel [Byte0]: 57
7843 11:48:34.005387 [Byte1]: 57
7844 11:48:34.009920
7845 11:48:34.010487 Set Vref, RX VrefLevel [Byte0]: 58
7846 11:48:34.013520 [Byte1]: 58
7847 11:48:34.017485
7848 11:48:34.018006 Set Vref, RX VrefLevel [Byte0]: 59
7849 11:48:34.020541 [Byte1]: 59
7850 11:48:34.024626
7851 11:48:34.025048 Set Vref, RX VrefLevel [Byte0]: 60
7852 11:48:34.028179 [Byte1]: 60
7853 11:48:34.032530
7854 11:48:34.032955 Set Vref, RX VrefLevel [Byte0]: 61
7855 11:48:34.036106 [Byte1]: 61
7856 11:48:34.039778
7857 11:48:34.043261 Set Vref, RX VrefLevel [Byte0]: 62
7858 11:48:34.046793 [Byte1]: 62
7859 11:48:34.047216
7860 11:48:34.050013 Set Vref, RX VrefLevel [Byte0]: 63
7861 11:48:34.052689 [Byte1]: 63
7862 11:48:34.053108
7863 11:48:34.056077 Set Vref, RX VrefLevel [Byte0]: 64
7864 11:48:34.059642 [Byte1]: 64
7865 11:48:34.062570
7866 11:48:34.062987 Set Vref, RX VrefLevel [Byte0]: 65
7867 11:48:34.065923 [Byte1]: 65
7868 11:48:34.070582
7869 11:48:34.071001 Set Vref, RX VrefLevel [Byte0]: 66
7870 11:48:34.073981 [Byte1]: 66
7871 11:48:34.077992
7872 11:48:34.078539 Set Vref, RX VrefLevel [Byte0]: 67
7873 11:48:34.081224 [Byte1]: 67
7874 11:48:34.085806
7875 11:48:34.086450 Set Vref, RX VrefLevel [Byte0]: 68
7876 11:48:34.089078 [Byte1]: 68
7877 11:48:34.093761
7878 11:48:34.094315 Set Vref, RX VrefLevel [Byte0]: 69
7879 11:48:34.096983 [Byte1]: 69
7880 11:48:34.100926
7881 11:48:34.101344 Set Vref, RX VrefLevel [Byte0]: 70
7882 11:48:34.104123 [Byte1]: 70
7883 11:48:34.108506
7884 11:48:34.108924 Set Vref, RX VrefLevel [Byte0]: 71
7885 11:48:34.112014 [Byte1]: 71
7886 11:48:34.116398
7887 11:48:34.116968 Set Vref, RX VrefLevel [Byte0]: 72
7888 11:48:34.119488 [Byte1]: 72
7889 11:48:34.123487
7890 11:48:34.123902 Set Vref, RX VrefLevel [Byte0]: 73
7891 11:48:34.126922 [Byte1]: 73
7892 11:48:34.131863
7893 11:48:34.132276 Final RX Vref Byte 0 = 57 to rank0
7894 11:48:34.134466 Final RX Vref Byte 1 = 63 to rank0
7895 11:48:34.137940 Final RX Vref Byte 0 = 57 to rank1
7896 11:48:34.141392 Final RX Vref Byte 1 = 63 to rank1==
7897 11:48:34.144870 Dram Type= 6, Freq= 0, CH_0, rank 0
7898 11:48:34.151085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7899 11:48:34.151510 ==
7900 11:48:34.151851 DQS Delay:
7901 11:48:34.154741 DQS0 = 0, DQS1 = 0
7902 11:48:34.155160 DQM Delay:
7903 11:48:34.155529 DQM0 = 128, DQM1 = 123
7904 11:48:34.157730 DQ Delay:
7905 11:48:34.161037 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7906 11:48:34.164546 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7907 11:48:34.167529 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7908 11:48:34.171417 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7909 11:48:34.171835
7910 11:48:34.172168
7911 11:48:34.172476
7912 11:48:34.174227 [DramC_TX_OE_Calibration] TA2
7913 11:48:34.177595 Original DQ_B0 (3 6) =30, OEN = 27
7914 11:48:34.180925 Original DQ_B1 (3 6) =30, OEN = 27
7915 11:48:34.184467 24, 0x0, End_B0=24 End_B1=24
7916 11:48:34.184893 25, 0x0, End_B0=25 End_B1=25
7917 11:48:34.187820 26, 0x0, End_B0=26 End_B1=26
7918 11:48:34.191217 27, 0x0, End_B0=27 End_B1=27
7919 11:48:34.194210 28, 0x0, End_B0=28 End_B1=28
7920 11:48:34.197828 29, 0x0, End_B0=29 End_B1=29
7921 11:48:34.198290 30, 0x0, End_B0=30 End_B1=30
7922 11:48:34.201290 31, 0x4141, End_B0=30 End_B1=30
7923 11:48:34.204072 Byte0 end_step=30 best_step=27
7924 11:48:34.207483 Byte1 end_step=30 best_step=27
7925 11:48:34.210600 Byte0 TX OE(2T, 0.5T) = (3, 3)
7926 11:48:34.213739 Byte1 TX OE(2T, 0.5T) = (3, 3)
7927 11:48:34.214158
7928 11:48:34.214553
7929 11:48:34.220375 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7930 11:48:34.224220 CH0 RK0: MR19=303, MR18=1916
7931 11:48:34.230637 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7932 11:48:34.231146
7933 11:48:34.233955 ----->DramcWriteLeveling(PI) begin...
7934 11:48:34.234518 ==
7935 11:48:34.237423 Dram Type= 6, Freq= 0, CH_0, rank 1
7936 11:48:34.239833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 11:48:34.240254 ==
7938 11:48:34.243356 Write leveling (Byte 0): 35 => 35
7939 11:48:34.246963 Write leveling (Byte 1): 26 => 26
7940 11:48:34.250402 DramcWriteLeveling(PI) end<-----
7941 11:48:34.250920
7942 11:48:34.251259 ==
7943 11:48:34.253135 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 11:48:34.260098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 11:48:34.260622 ==
7946 11:48:34.260969 [Gating] SW mode calibration
7947 11:48:34.269482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7948 11:48:34.273099 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7949 11:48:34.276188 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7950 11:48:34.282946 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7951 11:48:34.286491 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7952 11:48:34.289707 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7953 11:48:34.296668 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7954 11:48:34.300028 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7955 11:48:34.302647 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7956 11:48:34.309528 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7957 11:48:34.312530 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 11:48:34.319189 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7959 11:48:34.322187 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7960 11:48:34.325505 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7961 11:48:34.332086 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7962 11:48:34.335789 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7963 11:48:34.338634 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 11:48:34.345790 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 11:48:34.349469 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 11:48:34.352370 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 11:48:34.358445 1 6 8 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7968 11:48:34.362003 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7969 11:48:34.365110 1 6 16 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
7970 11:48:34.372517 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7971 11:48:34.375149 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7972 11:48:34.378808 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 11:48:34.384824 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 11:48:34.387988 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 11:48:34.391702 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7976 11:48:34.398354 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7977 11:48:34.401372 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7978 11:48:34.404778 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7979 11:48:34.411287 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7980 11:48:34.414611 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 11:48:34.418105 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 11:48:34.424479 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 11:48:34.428493 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 11:48:34.430976 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 11:48:34.438993 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 11:48:34.440864 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 11:48:34.444058 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 11:48:34.450308 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 11:48:34.454507 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 11:48:34.457195 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7991 11:48:34.463997 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7992 11:48:34.467412 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7993 11:48:34.469945 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7994 11:48:34.473493 Total UI for P1: 0, mck2ui 16
7995 11:48:34.477087 best dqsien dly found for B0: ( 1, 9, 8)
7996 11:48:34.483583 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7997 11:48:34.486708 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 11:48:34.489700 Total UI for P1: 0, mck2ui 16
7999 11:48:34.493062 best dqsien dly found for B1: ( 1, 9, 18)
8000 11:48:34.496564 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8001 11:48:34.500069 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8002 11:48:34.500590
8003 11:48:34.503339 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8004 11:48:34.506426 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8005 11:48:34.509796 [Gating] SW calibration Done
8006 11:48:34.510356 ==
8007 11:48:34.513604 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 11:48:34.519717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 11:48:34.520224 ==
8010 11:48:34.520556 RX Vref Scan: 0
8011 11:48:34.520868
8012 11:48:34.522820 RX Vref 0 -> 0, step: 1
8013 11:48:34.523266
8014 11:48:34.526879 RX Delay 0 -> 252, step: 8
8015 11:48:34.529619 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8016 11:48:34.533538 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8017 11:48:34.535991 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8018 11:48:34.539536 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8019 11:48:34.546331 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8020 11:48:34.549016 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8021 11:48:34.552652 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8022 11:48:34.555792 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8023 11:48:34.559262 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8024 11:48:34.565582 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8025 11:48:34.569188 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8026 11:48:34.573131 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8027 11:48:34.575503 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8028 11:48:34.582424 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8029 11:48:34.585689 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8030 11:48:34.589123 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8031 11:48:34.589643 ==
8032 11:48:34.592072 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 11:48:34.595222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 11:48:34.595644 ==
8035 11:48:34.598531 DQS Delay:
8036 11:48:34.598949 DQS0 = 0, DQS1 = 0
8037 11:48:34.601823 DQM Delay:
8038 11:48:34.602240 DQM0 = 134, DQM1 = 124
8039 11:48:34.605035 DQ Delay:
8040 11:48:34.608740 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8041 11:48:34.611999 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
8042 11:48:34.615161 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8043 11:48:34.618110 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8044 11:48:34.618561
8045 11:48:34.618900
8046 11:48:34.619214 ==
8047 11:48:34.621849 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 11:48:34.625091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 11:48:34.625632 ==
8050 11:48:34.625983
8051 11:48:34.628274
8052 11:48:34.628795 TX Vref Scan disable
8053 11:48:34.631640 == TX Byte 0 ==
8054 11:48:34.635429 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8055 11:48:34.637895 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8056 11:48:34.641079 == TX Byte 1 ==
8057 11:48:34.644745 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8058 11:48:34.648063 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8059 11:48:34.648716 ==
8060 11:48:34.651209 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 11:48:34.657806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 11:48:34.658345 ==
8063 11:48:34.670842
8064 11:48:34.673842 TX Vref early break, caculate TX vref
8065 11:48:34.677591 TX Vref=16, minBit 0, minWin=23, winSum=381
8066 11:48:34.681282 TX Vref=18, minBit 8, minWin=23, winSum=389
8067 11:48:34.684477 TX Vref=20, minBit 8, minWin=24, winSum=395
8068 11:48:34.686747 TX Vref=22, minBit 8, minWin=24, winSum=404
8069 11:48:34.690331 TX Vref=24, minBit 9, minWin=24, winSum=407
8070 11:48:34.696998 TX Vref=26, minBit 1, minWin=25, winSum=418
8071 11:48:34.700306 TX Vref=28, minBit 10, minWin=25, winSum=418
8072 11:48:34.703517 TX Vref=30, minBit 1, minWin=25, winSum=415
8073 11:48:34.706837 TX Vref=32, minBit 1, minWin=24, winSum=402
8074 11:48:34.710394 TX Vref=34, minBit 0, minWin=24, winSum=396
8075 11:48:34.716726 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 26
8076 11:48:34.717254
8077 11:48:34.719713 Final TX Range 0 Vref 26
8078 11:48:34.720133
8079 11:48:34.720467 ==
8080 11:48:34.723392 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 11:48:34.726180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 11:48:34.726677 ==
8083 11:48:34.727022
8084 11:48:34.729854
8085 11:48:34.730298 TX Vref Scan disable
8086 11:48:34.736716 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8087 11:48:34.737244 == TX Byte 0 ==
8088 11:48:34.739960 u2DelayCellOfst[0]=10 cells (3 PI)
8089 11:48:34.743011 u2DelayCellOfst[1]=14 cells (4 PI)
8090 11:48:34.746358 u2DelayCellOfst[2]=7 cells (2 PI)
8091 11:48:34.750001 u2DelayCellOfst[3]=7 cells (2 PI)
8092 11:48:34.752988 u2DelayCellOfst[4]=7 cells (2 PI)
8093 11:48:34.757079 u2DelayCellOfst[5]=0 cells (0 PI)
8094 11:48:34.759724 u2DelayCellOfst[6]=14 cells (4 PI)
8095 11:48:34.762920 u2DelayCellOfst[7]=14 cells (4 PI)
8096 11:48:34.766073 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8097 11:48:34.769021 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8098 11:48:34.772970 == TX Byte 1 ==
8099 11:48:34.776076 u2DelayCellOfst[8]=0 cells (0 PI)
8100 11:48:34.779178 u2DelayCellOfst[9]=0 cells (0 PI)
8101 11:48:34.782156 u2DelayCellOfst[10]=3 cells (1 PI)
8102 11:48:34.782738 u2DelayCellOfst[11]=3 cells (1 PI)
8103 11:48:34.785984 u2DelayCellOfst[12]=7 cells (2 PI)
8104 11:48:34.789499 u2DelayCellOfst[13]=10 cells (3 PI)
8105 11:48:34.792461 u2DelayCellOfst[14]=14 cells (4 PI)
8106 11:48:34.795995 u2DelayCellOfst[15]=10 cells (3 PI)
8107 11:48:34.802371 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8108 11:48:34.805493 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8109 11:48:34.805914 DramC Write-DBI on
8110 11:48:34.808923 ==
8111 11:48:34.812962 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 11:48:34.815343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 11:48:34.815768 ==
8114 11:48:34.816103
8115 11:48:34.816413
8116 11:48:34.818718 TX Vref Scan disable
8117 11:48:34.819381 == TX Byte 0 ==
8118 11:48:34.825365 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8119 11:48:34.825892 == TX Byte 1 ==
8120 11:48:34.828558 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8121 11:48:34.831943 DramC Write-DBI off
8122 11:48:34.832359
8123 11:48:34.832880 [DATLAT]
8124 11:48:34.835074 Freq=1600, CH0 RK1
8125 11:48:34.835496
8126 11:48:34.835828 DATLAT Default: 0xf
8127 11:48:34.838683 0, 0xFFFF, sum = 0
8128 11:48:34.839218 1, 0xFFFF, sum = 0
8129 11:48:34.841644 2, 0xFFFF, sum = 0
8130 11:48:34.842070 3, 0xFFFF, sum = 0
8131 11:48:34.845228 4, 0xFFFF, sum = 0
8132 11:48:34.848088 5, 0xFFFF, sum = 0
8133 11:48:34.848692 6, 0xFFFF, sum = 0
8134 11:48:34.851185 7, 0xFFFF, sum = 0
8135 11:48:34.851608 8, 0xFFFF, sum = 0
8136 11:48:34.854652 9, 0xFFFF, sum = 0
8137 11:48:34.855132 10, 0xFFFF, sum = 0
8138 11:48:34.858136 11, 0xFFFF, sum = 0
8139 11:48:34.858606 12, 0xFFFF, sum = 0
8140 11:48:34.861252 13, 0xFFFF, sum = 0
8141 11:48:34.861675 14, 0x0, sum = 1
8142 11:48:34.864807 15, 0x0, sum = 2
8143 11:48:34.865233 16, 0x0, sum = 3
8144 11:48:34.867992 17, 0x0, sum = 4
8145 11:48:34.868415 best_step = 15
8146 11:48:34.868747
8147 11:48:34.869056 ==
8148 11:48:34.871946 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 11:48:34.874789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 11:48:34.878369 ==
8151 11:48:34.878790 RX Vref Scan: 0
8152 11:48:34.879203
8153 11:48:34.881498 RX Vref 0 -> 0, step: 1
8154 11:48:34.882018
8155 11:48:34.885032 RX Delay 11 -> 252, step: 4
8156 11:48:34.888095 iDelay=187, Bit 0, Center 128 (79 ~ 178) 100
8157 11:48:34.891922 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8158 11:48:34.894358 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8159 11:48:34.902134 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8160 11:48:34.904371 iDelay=187, Bit 4, Center 130 (83 ~ 178) 96
8161 11:48:34.907290 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8162 11:48:34.911358 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8163 11:48:34.914525 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8164 11:48:34.921180 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8165 11:48:34.924094 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8166 11:48:34.928119 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8167 11:48:34.930702 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8168 11:48:34.937069 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8169 11:48:34.940420 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8170 11:48:34.943711 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8171 11:48:34.947043 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8172 11:48:34.947562 ==
8173 11:48:34.950275 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 11:48:34.953946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 11:48:34.956759 ==
8176 11:48:34.957177 DQS Delay:
8177 11:48:34.957547 DQS0 = 0, DQS1 = 0
8178 11:48:34.960845 DQM Delay:
8179 11:48:34.961262 DQM0 = 128, DQM1 = 123
8180 11:48:34.963368 DQ Delay:
8181 11:48:34.967018 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8182 11:48:34.970193 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
8183 11:48:34.973043 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8184 11:48:34.976369 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8185 11:48:34.976934
8186 11:48:34.977444
8187 11:48:34.977875
8188 11:48:34.979859 [DramC_TX_OE_Calibration] TA2
8189 11:48:34.983099 Original DQ_B0 (3 6) =30, OEN = 27
8190 11:48:34.986540 Original DQ_B1 (3 6) =30, OEN = 27
8191 11:48:34.990056 24, 0x0, End_B0=24 End_B1=24
8192 11:48:34.990531 25, 0x0, End_B0=25 End_B1=25
8193 11:48:34.992962 26, 0x0, End_B0=26 End_B1=26
8194 11:48:34.996355 27, 0x0, End_B0=27 End_B1=27
8195 11:48:35.001495 28, 0x0, End_B0=28 End_B1=28
8196 11:48:35.002859 29, 0x0, End_B0=29 End_B1=29
8197 11:48:35.003285 30, 0x0, End_B0=30 End_B1=30
8198 11:48:35.005866 31, 0x4141, End_B0=30 End_B1=30
8199 11:48:35.010394 Byte0 end_step=30 best_step=27
8200 11:48:35.012888 Byte1 end_step=30 best_step=27
8201 11:48:35.015685 Byte0 TX OE(2T, 0.5T) = (3, 3)
8202 11:48:35.019621 Byte1 TX OE(2T, 0.5T) = (3, 3)
8203 11:48:35.020142
8204 11:48:35.020631
8205 11:48:35.026018 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8206 11:48:35.029146 CH0 RK1: MR19=303, MR18=1312
8207 11:48:35.035669 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8208 11:48:35.038943 [RxdqsGatingPostProcess] freq 1600
8209 11:48:35.045380 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8210 11:48:35.045801 best DQS0 dly(2T, 0.5T) = (1, 1)
8211 11:48:35.048595 best DQS1 dly(2T, 0.5T) = (1, 1)
8212 11:48:35.051889 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8213 11:48:35.055870 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8214 11:48:35.058330 best DQS0 dly(2T, 0.5T) = (1, 1)
8215 11:48:35.062371 best DQS1 dly(2T, 0.5T) = (1, 1)
8216 11:48:35.065622 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8217 11:48:35.068954 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8218 11:48:35.072355 Pre-setting of DQS Precalculation
8219 11:48:35.075370 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8220 11:48:35.078403 ==
8221 11:48:35.082028 Dram Type= 6, Freq= 0, CH_1, rank 0
8222 11:48:35.084816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 11:48:35.085334 ==
8224 11:48:35.088230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8225 11:48:35.095063 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8226 11:48:35.098405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8227 11:48:35.105065 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8228 11:48:35.113174 [CA 0] Center 42 (13~72) winsize 60
8229 11:48:35.116482 [CA 1] Center 42 (12~72) winsize 61
8230 11:48:35.119880 [CA 2] Center 39 (10~68) winsize 59
8231 11:48:35.123367 [CA 3] Center 37 (8~67) winsize 60
8232 11:48:35.126562 [CA 4] Center 38 (8~68) winsize 61
8233 11:48:35.130041 [CA 5] Center 37 (7~67) winsize 61
8234 11:48:35.130598
8235 11:48:35.133085 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8236 11:48:35.133634
8237 11:48:35.139612 [CATrainingPosCal] consider 1 rank data
8238 11:48:35.140165 u2DelayCellTimex100 = 275/100 ps
8239 11:48:35.146321 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8240 11:48:35.149519 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8241 11:48:35.152270 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8242 11:48:35.155596 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8243 11:48:35.158944 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8244 11:48:35.162247 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8245 11:48:35.162707
8246 11:48:35.165827 CA PerBit enable=1, Macro0, CA PI delay=37
8247 11:48:35.166244
8248 11:48:35.169503 [CBTSetCACLKResult] CA Dly = 37
8249 11:48:35.171985 CS Dly: 8 (0~39)
8250 11:48:35.175497 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8251 11:48:35.178559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8252 11:48:35.178984 ==
8253 11:48:35.182346 Dram Type= 6, Freq= 0, CH_1, rank 1
8254 11:48:35.188468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 11:48:35.188890 ==
8256 11:48:35.191904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8257 11:48:35.198524 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8258 11:48:35.201800 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8259 11:48:35.208189 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8260 11:48:35.216290 [CA 0] Center 42 (12~72) winsize 61
8261 11:48:35.219940 [CA 1] Center 42 (13~72) winsize 60
8262 11:48:35.223206 [CA 2] Center 38 (8~68) winsize 61
8263 11:48:35.226080 [CA 3] Center 37 (8~67) winsize 60
8264 11:48:35.229372 [CA 4] Center 37 (8~67) winsize 60
8265 11:48:35.232888 [CA 5] Center 37 (7~67) winsize 61
8266 11:48:35.233303
8267 11:48:35.236052 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8268 11:48:35.236554
8269 11:48:35.239511 [CATrainingPosCal] consider 2 rank data
8270 11:48:35.242329 u2DelayCellTimex100 = 275/100 ps
8271 11:48:35.249360 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8272 11:48:35.252862 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8273 11:48:35.256275 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8274 11:48:35.259344 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8275 11:48:35.262494 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8276 11:48:35.265836 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8277 11:48:35.266287
8278 11:48:35.270047 CA PerBit enable=1, Macro0, CA PI delay=37
8279 11:48:35.270766
8280 11:48:35.272555 [CBTSetCACLKResult] CA Dly = 37
8281 11:48:35.275799 CS Dly: 9 (0~42)
8282 11:48:35.278964 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8283 11:48:35.282126 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8284 11:48:35.282580
8285 11:48:35.285797 ----->DramcWriteLeveling(PI) begin...
8286 11:48:35.286359 ==
8287 11:48:35.289395 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 11:48:35.295447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 11:48:35.295957 ==
8290 11:48:35.299382 Write leveling (Byte 0): 27 => 27
8291 11:48:35.302614 Write leveling (Byte 1): 27 => 27
8292 11:48:35.303128 DramcWriteLeveling(PI) end<-----
8293 11:48:35.303461
8294 11:48:35.305372 ==
8295 11:48:35.308752 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 11:48:35.311956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 11:48:35.312372 ==
8298 11:48:35.315389 [Gating] SW mode calibration
8299 11:48:35.321816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8300 11:48:35.325122 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8301 11:48:35.331754 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8302 11:48:35.334796 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8303 11:48:35.338340 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8304 11:48:35.344944 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8305 11:48:35.348707 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8306 11:48:35.351057 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8307 11:48:35.357551 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 11:48:35.361079 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 11:48:35.368090 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 11:48:35.370988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 11:48:35.374177 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8312 11:48:35.380967 1 5 12 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 1)
8313 11:48:35.384473 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8314 11:48:35.387671 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 11:48:35.394486 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 11:48:35.397411 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 11:48:35.400691 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 11:48:35.407866 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 11:48:35.410560 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 11:48:35.413839 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8321 11:48:35.420597 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8322 11:48:35.423735 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 11:48:35.427246 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 11:48:35.434070 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 11:48:35.437606 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 11:48:35.440710 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 11:48:35.447058 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 11:48:35.450308 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8329 11:48:35.453171 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8330 11:48:35.459769 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8331 11:48:35.463764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 11:48:35.466772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 11:48:35.473304 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 11:48:35.476630 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 11:48:35.481193 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 11:48:35.486000 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 11:48:35.490429 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 11:48:35.492585 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 11:48:35.499331 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 11:48:35.502823 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 11:48:35.505795 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 11:48:35.512486 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 11:48:35.516194 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8344 11:48:35.519259 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8345 11:48:35.526396 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8346 11:48:35.526920 Total UI for P1: 0, mck2ui 16
8347 11:48:35.532801 best dqsien dly found for B0: ( 1, 9, 10)
8348 11:48:35.535951 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 11:48:35.539161 Total UI for P1: 0, mck2ui 16
8350 11:48:35.541984 best dqsien dly found for B1: ( 1, 9, 14)
8351 11:48:35.545619 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8352 11:48:35.548840 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8353 11:48:35.549413
8354 11:48:35.552045 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8355 11:48:35.555657 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8356 11:48:35.558508 [Gating] SW calibration Done
8357 11:48:35.558932 ==
8358 11:48:35.562293 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 11:48:35.569203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 11:48:35.569728 ==
8361 11:48:35.570066 RX Vref Scan: 0
8362 11:48:35.570440
8363 11:48:35.572171 RX Vref 0 -> 0, step: 1
8364 11:48:35.572589
8365 11:48:35.575198 RX Delay 0 -> 252, step: 8
8366 11:48:35.578083 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8367 11:48:35.581593 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8368 11:48:35.585003 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8369 11:48:35.588552 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8370 11:48:35.594856 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8371 11:48:35.597656 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8372 11:48:35.601430 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8373 11:48:35.604479 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8374 11:48:35.610970 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8375 11:48:35.614766 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8376 11:48:35.617774 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8377 11:48:35.620985 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8378 11:48:35.624228 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8379 11:48:35.630969 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8380 11:48:35.634346 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8381 11:48:35.637366 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8382 11:48:35.637872 ==
8383 11:48:35.640890 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 11:48:35.643980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 11:48:35.647559 ==
8386 11:48:35.648066 DQS Delay:
8387 11:48:35.648402 DQS0 = 0, DQS1 = 0
8388 11:48:35.650660 DQM Delay:
8389 11:48:35.651073 DQM0 = 133, DQM1 = 129
8390 11:48:35.654570 DQ Delay:
8391 11:48:35.657165 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8392 11:48:35.660434 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8393 11:48:35.663853 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8394 11:48:35.667302 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8395 11:48:35.667723
8396 11:48:35.668054
8397 11:48:35.668365 ==
8398 11:48:35.670414 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 11:48:35.673847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 11:48:35.674305 ==
8401 11:48:35.674654
8402 11:48:35.677335
8403 11:48:35.677851 TX Vref Scan disable
8404 11:48:35.680655 == TX Byte 0 ==
8405 11:48:35.683840 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8406 11:48:35.687236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8407 11:48:35.690062 == TX Byte 1 ==
8408 11:48:35.693717 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8409 11:48:35.696819 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8410 11:48:35.697246 ==
8411 11:48:35.700119 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 11:48:35.706389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 11:48:35.706919 ==
8414 11:48:35.719325
8415 11:48:35.722242 TX Vref early break, caculate TX vref
8416 11:48:35.725766 TX Vref=16, minBit 8, minWin=21, winSum=367
8417 11:48:35.729355 TX Vref=18, minBit 8, minWin=22, winSum=375
8418 11:48:35.732412 TX Vref=20, minBit 8, minWin=22, winSum=383
8419 11:48:35.735428 TX Vref=22, minBit 8, minWin=22, winSum=391
8420 11:48:35.739221 TX Vref=24, minBit 8, minWin=24, winSum=404
8421 11:48:35.745786 TX Vref=26, minBit 9, minWin=24, winSum=412
8422 11:48:35.749507 TX Vref=28, minBit 3, minWin=25, winSum=416
8423 11:48:35.752584 TX Vref=30, minBit 0, minWin=25, winSum=416
8424 11:48:35.755503 TX Vref=32, minBit 9, minWin=24, winSum=408
8425 11:48:35.759157 TX Vref=34, minBit 9, minWin=23, winSum=398
8426 11:48:35.765542 TX Vref=36, minBit 0, minWin=23, winSum=385
8427 11:48:35.768981 [TxChooseVref] Worse bit 3, Min win 25, Win sum 416, Final Vref 28
8428 11:48:35.769546
8429 11:48:35.771715 Final TX Range 0 Vref 28
8430 11:48:35.772178
8431 11:48:35.772545 ==
8432 11:48:35.775326 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 11:48:35.778900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 11:48:35.781593 ==
8435 11:48:35.782101
8436 11:48:35.782650
8437 11:48:35.782988 TX Vref Scan disable
8438 11:48:35.788580 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8439 11:48:35.789093 == TX Byte 0 ==
8440 11:48:35.791727 u2DelayCellOfst[0]=17 cells (5 PI)
8441 11:48:35.795228 u2DelayCellOfst[1]=10 cells (3 PI)
8442 11:48:35.798179 u2DelayCellOfst[2]=0 cells (0 PI)
8443 11:48:35.801769 u2DelayCellOfst[3]=7 cells (2 PI)
8444 11:48:35.805001 u2DelayCellOfst[4]=10 cells (3 PI)
8445 11:48:35.807997 u2DelayCellOfst[5]=17 cells (5 PI)
8446 11:48:35.811746 u2DelayCellOfst[6]=14 cells (4 PI)
8447 11:48:35.814653 u2DelayCellOfst[7]=7 cells (2 PI)
8448 11:48:35.818398 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8449 11:48:35.821527 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8450 11:48:35.824753 == TX Byte 1 ==
8451 11:48:35.828166 u2DelayCellOfst[8]=0 cells (0 PI)
8452 11:48:35.831472 u2DelayCellOfst[9]=7 cells (2 PI)
8453 11:48:35.835061 u2DelayCellOfst[10]=10 cells (3 PI)
8454 11:48:35.837636 u2DelayCellOfst[11]=3 cells (1 PI)
8455 11:48:35.841170 u2DelayCellOfst[12]=14 cells (4 PI)
8456 11:48:35.844911 u2DelayCellOfst[13]=14 cells (4 PI)
8457 11:48:35.847882 u2DelayCellOfst[14]=17 cells (5 PI)
8458 11:48:35.848404 u2DelayCellOfst[15]=17 cells (5 PI)
8459 11:48:35.854367 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8460 11:48:35.857350 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8461 11:48:35.861235 DramC Write-DBI on
8462 11:48:35.861755 ==
8463 11:48:35.863976 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 11:48:35.867533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 11:48:35.868196 ==
8466 11:48:35.868548
8467 11:48:35.868863
8468 11:48:35.871553 TX Vref Scan disable
8469 11:48:35.872072 == TX Byte 0 ==
8470 11:48:35.877872 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8471 11:48:35.878437 == TX Byte 1 ==
8472 11:48:35.880863 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8473 11:48:35.884209 DramC Write-DBI off
8474 11:48:35.884723
8475 11:48:35.885056 [DATLAT]
8476 11:48:35.887065 Freq=1600, CH1 RK0
8477 11:48:35.887487
8478 11:48:35.887821 DATLAT Default: 0xf
8479 11:48:35.890945 0, 0xFFFF, sum = 0
8480 11:48:35.893996 1, 0xFFFF, sum = 0
8481 11:48:35.894566 2, 0xFFFF, sum = 0
8482 11:48:35.896987 3, 0xFFFF, sum = 0
8483 11:48:35.897412 4, 0xFFFF, sum = 0
8484 11:48:35.900133 5, 0xFFFF, sum = 0
8485 11:48:35.900559 6, 0xFFFF, sum = 0
8486 11:48:35.903872 7, 0xFFFF, sum = 0
8487 11:48:35.904402 8, 0xFFFF, sum = 0
8488 11:48:35.907239 9, 0xFFFF, sum = 0
8489 11:48:35.907772 10, 0xFFFF, sum = 0
8490 11:48:35.910530 11, 0xFFFF, sum = 0
8491 11:48:35.911063 12, 0xFFFF, sum = 0
8492 11:48:35.914402 13, 0xFFFF, sum = 0
8493 11:48:35.914932 14, 0x0, sum = 1
8494 11:48:35.916623 15, 0x0, sum = 2
8495 11:48:35.917048 16, 0x0, sum = 3
8496 11:48:35.920523 17, 0x0, sum = 4
8497 11:48:35.921225 best_step = 15
8498 11:48:35.921739
8499 11:48:35.922070 ==
8500 11:48:35.923545 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 11:48:35.930335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 11:48:35.930986 ==
8503 11:48:35.931502 RX Vref Scan: 1
8504 11:48:35.931986
8505 11:48:35.933215 Set Vref Range= 24 -> 127
8506 11:48:35.933633
8507 11:48:35.936801 RX Vref 24 -> 127, step: 1
8508 11:48:35.937368
8509 11:48:35.940130 RX Delay 11 -> 252, step: 4
8510 11:48:35.940734
8511 11:48:35.943132 Set Vref, RX VrefLevel [Byte0]: 24
8512 11:48:35.946455 [Byte1]: 24
8513 11:48:35.947050
8514 11:48:35.949909 Set Vref, RX VrefLevel [Byte0]: 25
8515 11:48:35.953505 [Byte1]: 25
8516 11:48:35.954079
8517 11:48:35.956672 Set Vref, RX VrefLevel [Byte0]: 26
8518 11:48:35.959734 [Byte1]: 26
8519 11:48:35.960257
8520 11:48:35.963185 Set Vref, RX VrefLevel [Byte0]: 27
8521 11:48:35.966620 [Byte1]: 27
8522 11:48:35.970348
8523 11:48:35.970918 Set Vref, RX VrefLevel [Byte0]: 28
8524 11:48:35.973689 [Byte1]: 28
8525 11:48:35.978163
8526 11:48:35.978773 Set Vref, RX VrefLevel [Byte0]: 29
8527 11:48:35.981514 [Byte1]: 29
8528 11:48:35.985858
8529 11:48:35.986496 Set Vref, RX VrefLevel [Byte0]: 30
8530 11:48:35.988648 [Byte1]: 30
8531 11:48:35.994024
8532 11:48:35.994742 Set Vref, RX VrefLevel [Byte0]: 31
8533 11:48:35.997045 [Byte1]: 31
8534 11:48:36.001027
8535 11:48:36.001707 Set Vref, RX VrefLevel [Byte0]: 32
8536 11:48:36.004519 [Byte1]: 32
8537 11:48:36.008658
8538 11:48:36.009184 Set Vref, RX VrefLevel [Byte0]: 33
8539 11:48:36.012227 [Byte1]: 33
8540 11:48:36.016203
8541 11:48:36.016728 Set Vref, RX VrefLevel [Byte0]: 34
8542 11:48:36.019266 [Byte1]: 34
8543 11:48:36.023839
8544 11:48:36.024531 Set Vref, RX VrefLevel [Byte0]: 35
8545 11:48:36.026796 [Byte1]: 35
8546 11:48:36.031104
8547 11:48:36.031684 Set Vref, RX VrefLevel [Byte0]: 36
8548 11:48:36.034932 [Byte1]: 36
8549 11:48:36.039678
8550 11:48:36.040197 Set Vref, RX VrefLevel [Byte0]: 37
8551 11:48:36.042887 [Byte1]: 37
8552 11:48:36.046526
8553 11:48:36.046944 Set Vref, RX VrefLevel [Byte0]: 38
8554 11:48:36.050383 [Byte1]: 38
8555 11:48:36.054557
8556 11:48:36.054975 Set Vref, RX VrefLevel [Byte0]: 39
8557 11:48:36.057187 [Byte1]: 39
8558 11:48:36.061921
8559 11:48:36.062365 Set Vref, RX VrefLevel [Byte0]: 40
8560 11:48:36.064913 [Byte1]: 40
8561 11:48:36.069127
8562 11:48:36.069544 Set Vref, RX VrefLevel [Byte0]: 41
8563 11:48:36.073282 [Byte1]: 41
8564 11:48:36.076984
8565 11:48:36.077512 Set Vref, RX VrefLevel [Byte0]: 42
8566 11:48:36.080710 [Byte1]: 42
8567 11:48:36.084498
8568 11:48:36.084918 Set Vref, RX VrefLevel [Byte0]: 43
8569 11:48:36.087832 [Byte1]: 43
8570 11:48:36.092240
8571 11:48:36.092657 Set Vref, RX VrefLevel [Byte0]: 44
8572 11:48:36.095352 [Byte1]: 44
8573 11:48:36.099893
8574 11:48:36.100422 Set Vref, RX VrefLevel [Byte0]: 45
8575 11:48:36.103439 [Byte1]: 45
8576 11:48:36.107428
8577 11:48:36.107848 Set Vref, RX VrefLevel [Byte0]: 46
8578 11:48:36.111118 [Byte1]: 46
8579 11:48:36.115093
8580 11:48:36.115511 Set Vref, RX VrefLevel [Byte0]: 47
8581 11:48:36.118076 [Byte1]: 47
8582 11:48:36.122688
8583 11:48:36.123104 Set Vref, RX VrefLevel [Byte0]: 48
8584 11:48:36.126005 [Byte1]: 48
8585 11:48:36.130324
8586 11:48:36.130935 Set Vref, RX VrefLevel [Byte0]: 49
8587 11:48:36.133486 [Byte1]: 49
8588 11:48:36.138173
8589 11:48:36.138730 Set Vref, RX VrefLevel [Byte0]: 50
8590 11:48:36.141086 [Byte1]: 50
8591 11:48:36.145612
8592 11:48:36.146088 Set Vref, RX VrefLevel [Byte0]: 51
8593 11:48:36.149256 [Byte1]: 51
8594 11:48:36.153036
8595 11:48:36.153460 Set Vref, RX VrefLevel [Byte0]: 52
8596 11:48:36.156348 [Byte1]: 52
8597 11:48:36.161415
8598 11:48:36.161830 Set Vref, RX VrefLevel [Byte0]: 53
8599 11:48:36.164231 [Byte1]: 53
8600 11:48:36.168241
8601 11:48:36.168659 Set Vref, RX VrefLevel [Byte0]: 54
8602 11:48:36.171775 [Byte1]: 54
8603 11:48:36.176471
8604 11:48:36.176982 Set Vref, RX VrefLevel [Byte0]: 55
8605 11:48:36.179797 [Byte1]: 55
8606 11:48:36.183833
8607 11:48:36.184326 Set Vref, RX VrefLevel [Byte0]: 56
8608 11:48:36.187613 [Byte1]: 56
8609 11:48:36.191051
8610 11:48:36.191561 Set Vref, RX VrefLevel [Byte0]: 57
8611 11:48:36.194711 [Byte1]: 57
8612 11:48:36.198945
8613 11:48:36.199361 Set Vref, RX VrefLevel [Byte0]: 58
8614 11:48:36.201991 [Byte1]: 58
8615 11:48:36.206614
8616 11:48:36.207160 Set Vref, RX VrefLevel [Byte0]: 59
8617 11:48:36.209799 [Byte1]: 59
8618 11:48:36.214376
8619 11:48:36.214897 Set Vref, RX VrefLevel [Byte0]: 60
8620 11:48:36.217604 [Byte1]: 60
8621 11:48:36.221991
8622 11:48:36.222448 Set Vref, RX VrefLevel [Byte0]: 61
8623 11:48:36.225136 [Byte1]: 61
8624 11:48:36.229058
8625 11:48:36.229478 Set Vref, RX VrefLevel [Byte0]: 62
8626 11:48:36.232554 [Byte1]: 62
8627 11:48:36.236865
8628 11:48:36.237447 Set Vref, RX VrefLevel [Byte0]: 63
8629 11:48:36.239819 [Byte1]: 63
8630 11:48:36.244530
8631 11:48:36.244948 Set Vref, RX VrefLevel [Byte0]: 64
8632 11:48:36.248093 [Byte1]: 64
8633 11:48:36.252015
8634 11:48:36.252436 Set Vref, RX VrefLevel [Byte0]: 65
8635 11:48:36.255511 [Byte1]: 65
8636 11:48:36.259746
8637 11:48:36.260213 Set Vref, RX VrefLevel [Byte0]: 66
8638 11:48:36.262999 [Byte1]: 66
8639 11:48:36.267500
8640 11:48:36.267920 Set Vref, RX VrefLevel [Byte0]: 67
8641 11:48:36.270953 [Byte1]: 67
8642 11:48:36.275020
8643 11:48:36.278337 Set Vref, RX VrefLevel [Byte0]: 68
8644 11:48:36.278760 [Byte1]: 68
8645 11:48:36.282452
8646 11:48:36.283005 Set Vref, RX VrefLevel [Byte0]: 69
8647 11:48:36.285641 [Byte1]: 69
8648 11:48:36.290520
8649 11:48:36.290939 Set Vref, RX VrefLevel [Byte0]: 70
8650 11:48:36.293438 [Byte1]: 70
8651 11:48:36.297713
8652 11:48:36.298137 Final RX Vref Byte 0 = 52 to rank0
8653 11:48:36.300964 Final RX Vref Byte 1 = 61 to rank0
8654 11:48:36.304220 Final RX Vref Byte 0 = 52 to rank1
8655 11:48:36.307684 Final RX Vref Byte 1 = 61 to rank1==
8656 11:48:36.310824 Dram Type= 6, Freq= 0, CH_1, rank 0
8657 11:48:36.317437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8658 11:48:36.317863 ==
8659 11:48:36.318197 DQS Delay:
8660 11:48:36.318568 DQS0 = 0, DQS1 = 0
8661 11:48:36.320977 DQM Delay:
8662 11:48:36.321274 DQM0 = 132, DQM1 = 128
8663 11:48:36.324229 DQ Delay:
8664 11:48:36.327232 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8665 11:48:36.330640 DQ4 =126, DQ5 =142, DQ6 =144, DQ7 =126
8666 11:48:36.333625 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8667 11:48:36.336997 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8668 11:48:36.337150
8669 11:48:36.337270
8670 11:48:36.337382
8671 11:48:36.341001 [DramC_TX_OE_Calibration] TA2
8672 11:48:36.343844 Original DQ_B0 (3 6) =30, OEN = 27
8673 11:48:36.347021 Original DQ_B1 (3 6) =30, OEN = 27
8674 11:48:36.350538 24, 0x0, End_B0=24 End_B1=24
8675 11:48:36.350669 25, 0x0, End_B0=25 End_B1=25
8676 11:48:36.353568 26, 0x0, End_B0=26 End_B1=26
8677 11:48:36.356756 27, 0x0, End_B0=27 End_B1=27
8678 11:48:36.360793 28, 0x0, End_B0=28 End_B1=28
8679 11:48:36.363702 29, 0x0, End_B0=29 End_B1=29
8680 11:48:36.363796 30, 0x0, End_B0=30 End_B1=30
8681 11:48:36.366889 31, 0x4141, End_B0=30 End_B1=30
8682 11:48:36.369862 Byte0 end_step=30 best_step=27
8683 11:48:36.373071 Byte1 end_step=30 best_step=27
8684 11:48:36.376357 Byte0 TX OE(2T, 0.5T) = (3, 3)
8685 11:48:36.379908 Byte1 TX OE(2T, 0.5T) = (3, 3)
8686 11:48:36.379999
8687 11:48:36.380072
8688 11:48:36.386537 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8689 11:48:36.389781 CH1 RK0: MR19=303, MR18=D17
8690 11:48:36.396314 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8691 11:48:36.396514
8692 11:48:36.400314 ----->DramcWriteLeveling(PI) begin...
8693 11:48:36.400512 ==
8694 11:48:36.403872 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 11:48:36.406281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8696 11:48:36.406481 ==
8697 11:48:36.409379 Write leveling (Byte 0): 23 => 23
8698 11:48:36.412852 Write leveling (Byte 1): 26 => 26
8699 11:48:36.416552 DramcWriteLeveling(PI) end<-----
8700 11:48:36.416776
8701 11:48:36.416944 ==
8702 11:48:36.419643 Dram Type= 6, Freq= 0, CH_1, rank 1
8703 11:48:36.423210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8704 11:48:36.426950 ==
8705 11:48:36.427233 [Gating] SW mode calibration
8706 11:48:36.433051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8707 11:48:36.439452 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8708 11:48:36.442481 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8709 11:48:36.449814 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8710 11:48:36.453052 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8711 11:48:36.455888 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8712 11:48:36.462454 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8713 11:48:36.466475 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8714 11:48:36.469154 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8715 11:48:36.476147 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8716 11:48:36.478781 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8717 11:48:36.482824 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8718 11:48:36.488907 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8719 11:48:36.492377 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8720 11:48:36.496127 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8721 11:48:36.502425 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8722 11:48:36.505507 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8723 11:48:36.509133 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8724 11:48:36.514952 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 11:48:36.519010 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8726 11:48:36.521696 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8727 11:48:36.528534 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8728 11:48:36.531591 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8729 11:48:36.535131 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8730 11:48:36.541531 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8731 11:48:36.545045 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 11:48:36.548268 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8733 11:48:36.554795 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 11:48:36.557852 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8735 11:48:36.561248 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8736 11:48:36.567984 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8737 11:48:36.571303 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8738 11:48:36.574129 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8739 11:48:36.581712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8740 11:48:36.584083 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 11:48:36.587612 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 11:48:36.594417 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 11:48:36.597737 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 11:48:36.600801 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 11:48:36.607330 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 11:48:36.610200 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 11:48:36.617079 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 11:48:36.620046 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 11:48:36.624195 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 11:48:36.629899 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8751 11:48:36.633694 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8752 11:48:36.636675 Total UI for P1: 0, mck2ui 16
8753 11:48:36.639953 best dqsien dly found for B0: ( 1, 9, 8)
8754 11:48:36.643244 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8755 11:48:36.649663 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 11:48:36.650083 Total UI for P1: 0, mck2ui 16
8757 11:48:36.653204 best dqsien dly found for B1: ( 1, 9, 14)
8758 11:48:36.659391 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8759 11:48:36.663441 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8760 11:48:36.663862
8761 11:48:36.666212 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8762 11:48:36.669953 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8763 11:48:36.672617 [Gating] SW calibration Done
8764 11:48:36.673088 ==
8765 11:48:36.676434 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 11:48:36.679750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 11:48:36.680276 ==
8768 11:48:36.682898 RX Vref Scan: 0
8769 11:48:36.683417
8770 11:48:36.683753 RX Vref 0 -> 0, step: 1
8771 11:48:36.684068
8772 11:48:36.685812 RX Delay 0 -> 252, step: 8
8773 11:48:36.689027 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8774 11:48:36.695682 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8775 11:48:36.699090 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8776 11:48:36.702358 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8777 11:48:36.705859 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8778 11:48:36.708849 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8779 11:48:36.715987 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8780 11:48:36.719076 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8781 11:48:36.721672 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8782 11:48:36.725245 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8783 11:48:36.732056 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8784 11:48:36.736439 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8785 11:48:36.738548 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8786 11:48:36.742193 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8787 11:48:36.745574 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8788 11:48:36.752488 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8789 11:48:36.753018 ==
8790 11:48:36.754995 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 11:48:36.758463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 11:48:36.758986 ==
8793 11:48:36.759329 DQS Delay:
8794 11:48:36.761256 DQS0 = 0, DQS1 = 0
8795 11:48:36.761672 DQM Delay:
8796 11:48:36.765089 DQM0 = 133, DQM1 = 130
8797 11:48:36.765615 DQ Delay:
8798 11:48:36.768437 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8799 11:48:36.771109 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8800 11:48:36.774649 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8801 11:48:36.781437 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8802 11:48:36.781958
8803 11:48:36.782342
8804 11:48:36.782668 ==
8805 11:48:36.784672 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 11:48:36.788190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 11:48:36.788614 ==
8808 11:48:36.788949
8809 11:48:36.789259
8810 11:48:36.790946 TX Vref Scan disable
8811 11:48:36.791363 == TX Byte 0 ==
8812 11:48:36.797845 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8813 11:48:36.801198 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8814 11:48:36.801720 == TX Byte 1 ==
8815 11:48:36.807769 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8816 11:48:36.810999 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8817 11:48:36.811426 ==
8818 11:48:36.814013 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 11:48:36.817197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 11:48:36.817620 ==
8821 11:48:36.832887
8822 11:48:36.836086 TX Vref early break, caculate TX vref
8823 11:48:36.839505 TX Vref=16, minBit 8, minWin=22, winSum=377
8824 11:48:36.842068 TX Vref=18, minBit 9, minWin=22, winSum=388
8825 11:48:36.845838 TX Vref=20, minBit 9, minWin=22, winSum=390
8826 11:48:36.848696 TX Vref=22, minBit 9, minWin=23, winSum=401
8827 11:48:36.852762 TX Vref=24, minBit 8, minWin=24, winSum=407
8828 11:48:36.858601 TX Vref=26, minBit 9, minWin=24, winSum=421
8829 11:48:36.862910 TX Vref=28, minBit 9, minWin=25, winSum=423
8830 11:48:36.865655 TX Vref=30, minBit 8, minWin=25, winSum=417
8831 11:48:36.868647 TX Vref=32, minBit 9, minWin=24, winSum=411
8832 11:48:36.872008 TX Vref=34, minBit 0, minWin=24, winSum=401
8833 11:48:36.878420 TX Vref=36, minBit 9, minWin=23, winSum=396
8834 11:48:36.881838 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8835 11:48:36.882405
8836 11:48:36.885578 Final TX Range 0 Vref 28
8837 11:48:36.886091
8838 11:48:36.886479 ==
8839 11:48:36.888529 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 11:48:36.891390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 11:48:36.895167 ==
8842 11:48:36.895679
8843 11:48:36.896015
8844 11:48:36.896325 TX Vref Scan disable
8845 11:48:36.901823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8846 11:48:36.902404 == TX Byte 0 ==
8847 11:48:36.904977 u2DelayCellOfst[0]=14 cells (4 PI)
8848 11:48:36.908170 u2DelayCellOfst[1]=10 cells (3 PI)
8849 11:48:36.911757 u2DelayCellOfst[2]=0 cells (0 PI)
8850 11:48:36.914790 u2DelayCellOfst[3]=7 cells (2 PI)
8851 11:48:36.918338 u2DelayCellOfst[4]=7 cells (2 PI)
8852 11:48:36.922124 u2DelayCellOfst[5]=14 cells (4 PI)
8853 11:48:36.924810 u2DelayCellOfst[6]=14 cells (4 PI)
8854 11:48:36.928572 u2DelayCellOfst[7]=7 cells (2 PI)
8855 11:48:36.931178 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8856 11:48:36.934615 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8857 11:48:36.938043 == TX Byte 1 ==
8858 11:48:36.941013 u2DelayCellOfst[8]=0 cells (0 PI)
8859 11:48:36.944139 u2DelayCellOfst[9]=3 cells (1 PI)
8860 11:48:36.947810 u2DelayCellOfst[10]=10 cells (3 PI)
8861 11:48:36.950670 u2DelayCellOfst[11]=7 cells (2 PI)
8862 11:48:36.954361 u2DelayCellOfst[12]=14 cells (4 PI)
8863 11:48:36.957831 u2DelayCellOfst[13]=14 cells (4 PI)
8864 11:48:36.960606 u2DelayCellOfst[14]=17 cells (5 PI)
8865 11:48:36.964480 u2DelayCellOfst[15]=17 cells (5 PI)
8866 11:48:36.967441 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8867 11:48:36.970819 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 11:48:36.973746 DramC Write-DBI on
8869 11:48:36.974163 ==
8870 11:48:36.977553 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 11:48:36.980553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 11:48:36.981077 ==
8873 11:48:36.981417
8874 11:48:36.981726
8875 11:48:36.983698 TX Vref Scan disable
8876 11:48:36.986967 == TX Byte 0 ==
8877 11:48:36.990674 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8878 11:48:36.991196 == TX Byte 1 ==
8879 11:48:36.997219 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8880 11:48:36.997740 DramC Write-DBI off
8881 11:48:36.998077
8882 11:48:36.998420 [DATLAT]
8883 11:48:37.000765 Freq=1600, CH1 RK1
8884 11:48:37.001290
8885 11:48:37.004067 DATLAT Default: 0xf
8886 11:48:37.004589 0, 0xFFFF, sum = 0
8887 11:48:37.006902 1, 0xFFFF, sum = 0
8888 11:48:37.007326 2, 0xFFFF, sum = 0
8889 11:48:37.010526 3, 0xFFFF, sum = 0
8890 11:48:37.011057 4, 0xFFFF, sum = 0
8891 11:48:37.013661 5, 0xFFFF, sum = 0
8892 11:48:37.014087 6, 0xFFFF, sum = 0
8893 11:48:37.017058 7, 0xFFFF, sum = 0
8894 11:48:37.017658 8, 0xFFFF, sum = 0
8895 11:48:37.020316 9, 0xFFFF, sum = 0
8896 11:48:37.020741 10, 0xFFFF, sum = 0
8897 11:48:37.023299 11, 0xFFFF, sum = 0
8898 11:48:37.023728 12, 0xFFFF, sum = 0
8899 11:48:37.026666 13, 0xFFFF, sum = 0
8900 11:48:37.027093 14, 0x0, sum = 1
8901 11:48:37.029781 15, 0x0, sum = 2
8902 11:48:37.030205 16, 0x0, sum = 3
8903 11:48:37.033459 17, 0x0, sum = 4
8904 11:48:37.033885 best_step = 15
8905 11:48:37.034217
8906 11:48:37.034562 ==
8907 11:48:37.036313 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 11:48:37.042989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 11:48:37.043412 ==
8910 11:48:37.043881 RX Vref Scan: 0
8911 11:48:37.044364
8912 11:48:37.046966 RX Vref 0 -> 0, step: 1
8913 11:48:37.047385
8914 11:48:37.050391 RX Delay 11 -> 252, step: 4
8915 11:48:37.052689 iDelay=199, Bit 0, Center 134 (83 ~ 186) 104
8916 11:48:37.056428 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
8917 11:48:37.062695 iDelay=199, Bit 2, Center 120 (67 ~ 174) 108
8918 11:48:37.066539 iDelay=199, Bit 3, Center 128 (75 ~ 182) 108
8919 11:48:37.070600 iDelay=199, Bit 4, Center 130 (75 ~ 186) 112
8920 11:48:37.072995 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
8921 11:48:37.076654 iDelay=199, Bit 6, Center 138 (87 ~ 190) 104
8922 11:48:37.082876 iDelay=199, Bit 7, Center 128 (75 ~ 182) 108
8923 11:48:37.086074 iDelay=199, Bit 8, Center 114 (59 ~ 170) 112
8924 11:48:37.089585 iDelay=199, Bit 9, Center 118 (67 ~ 170) 104
8925 11:48:37.092810 iDelay=199, Bit 10, Center 128 (75 ~ 182) 108
8926 11:48:37.096154 iDelay=199, Bit 11, Center 120 (67 ~ 174) 108
8927 11:48:37.103046 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
8928 11:48:37.106362 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
8929 11:48:37.109206 iDelay=199, Bit 14, Center 134 (83 ~ 186) 104
8930 11:48:37.112635 iDelay=199, Bit 15, Center 138 (87 ~ 190) 104
8931 11:48:37.113163 ==
8932 11:48:37.116194 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 11:48:37.122437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 11:48:37.122957 ==
8935 11:48:37.123296 DQS Delay:
8936 11:48:37.125617 DQS0 = 0, DQS1 = 0
8937 11:48:37.126037 DQM Delay:
8938 11:48:37.129008 DQM0 = 131, DQM1 = 128
8939 11:48:37.129555 DQ Delay:
8940 11:48:37.131793 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8941 11:48:37.135849 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =128
8942 11:48:37.138773 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8943 11:48:37.142554 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8944 11:48:37.143076
8945 11:48:37.143415
8946 11:48:37.143728
8947 11:48:37.145110 [DramC_TX_OE_Calibration] TA2
8948 11:48:37.148241 Original DQ_B0 (3 6) =30, OEN = 27
8949 11:48:37.151524 Original DQ_B1 (3 6) =30, OEN = 27
8950 11:48:37.155305 24, 0x0, End_B0=24 End_B1=24
8951 11:48:37.158074 25, 0x0, End_B0=25 End_B1=25
8952 11:48:37.158640 26, 0x0, End_B0=26 End_B1=26
8953 11:48:37.161779 27, 0x0, End_B0=27 End_B1=27
8954 11:48:37.165182 28, 0x0, End_B0=28 End_B1=28
8955 11:48:37.168741 29, 0x0, End_B0=29 End_B1=29
8956 11:48:37.171997 30, 0x0, End_B0=30 End_B1=30
8957 11:48:37.172425 31, 0x4141, End_B0=30 End_B1=30
8958 11:48:37.175123 Byte0 end_step=30 best_step=27
8959 11:48:37.178357 Byte1 end_step=30 best_step=27
8960 11:48:37.181860 Byte0 TX OE(2T, 0.5T) = (3, 3)
8961 11:48:37.184853 Byte1 TX OE(2T, 0.5T) = (3, 3)
8962 11:48:37.185375
8963 11:48:37.185713
8964 11:48:37.191649 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 403 ps
8965 11:48:37.194622 CH1 RK1: MR19=303, MR18=D1C
8966 11:48:37.201926 CH1_RK1: MR19=0x303, MR18=0xD1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8967 11:48:37.205285 [RxdqsGatingPostProcess] freq 1600
8968 11:48:37.211877 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8969 11:48:37.212389 best DQS0 dly(2T, 0.5T) = (1, 1)
8970 11:48:37.215044 best DQS1 dly(2T, 0.5T) = (1, 1)
8971 11:48:37.218010 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8972 11:48:37.221173 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8973 11:48:37.224495 best DQS0 dly(2T, 0.5T) = (1, 1)
8974 11:48:37.227862 best DQS1 dly(2T, 0.5T) = (1, 1)
8975 11:48:37.231096 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8976 11:48:37.234749 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8977 11:48:37.237705 Pre-setting of DQS Precalculation
8978 11:48:37.241056 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8979 11:48:37.251156 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8980 11:48:37.257761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8981 11:48:37.258358
8982 11:48:37.258752
8983 11:48:37.260429 [Calibration Summary] 3200 Mbps
8984 11:48:37.260850 CH 0, Rank 0
8985 11:48:37.263640 SW Impedance : PASS
8986 11:48:37.267260 DUTY Scan : NO K
8987 11:48:37.267829 ZQ Calibration : PASS
8988 11:48:37.270754 Jitter Meter : NO K
8989 11:48:37.271322 CBT Training : PASS
8990 11:48:37.273805 Write leveling : PASS
8991 11:48:37.276870 RX DQS gating : PASS
8992 11:48:37.277334 RX DQ/DQS(RDDQC) : PASS
8993 11:48:37.280734 TX DQ/DQS : PASS
8994 11:48:37.283472 RX DATLAT : PASS
8995 11:48:37.283936 RX DQ/DQS(Engine): PASS
8996 11:48:37.286356 TX OE : PASS
8997 11:48:37.286784 All Pass.
8998 11:48:37.287120
8999 11:48:37.289892 CH 0, Rank 1
9000 11:48:37.290352 SW Impedance : PASS
9001 11:48:37.293910 DUTY Scan : NO K
9002 11:48:37.296677 ZQ Calibration : PASS
9003 11:48:37.297219 Jitter Meter : NO K
9004 11:48:37.299721 CBT Training : PASS
9005 11:48:37.303053 Write leveling : PASS
9006 11:48:37.303473 RX DQS gating : PASS
9007 11:48:37.306096 RX DQ/DQS(RDDQC) : PASS
9008 11:48:37.309419 TX DQ/DQS : PASS
9009 11:48:37.309834 RX DATLAT : PASS
9010 11:48:37.312770 RX DQ/DQS(Engine): PASS
9011 11:48:37.316154 TX OE : PASS
9012 11:48:37.316866 All Pass.
9013 11:48:37.317346
9014 11:48:37.317696 CH 1, Rank 0
9015 11:48:37.320793 SW Impedance : PASS
9016 11:48:37.322628 DUTY Scan : NO K
9017 11:48:37.323022 ZQ Calibration : PASS
9018 11:48:37.326590 Jitter Meter : NO K
9019 11:48:37.330372 CBT Training : PASS
9020 11:48:37.330790 Write leveling : PASS
9021 11:48:37.332683 RX DQS gating : PASS
9022 11:48:37.336408 RX DQ/DQS(RDDQC) : PASS
9023 11:48:37.336824 TX DQ/DQS : PASS
9024 11:48:37.339410 RX DATLAT : PASS
9025 11:48:37.340076 RX DQ/DQS(Engine): PASS
9026 11:48:37.343106 TX OE : PASS
9027 11:48:37.343524 All Pass.
9028 11:48:37.343867
9029 11:48:37.345991 CH 1, Rank 1
9030 11:48:37.346495 SW Impedance : PASS
9031 11:48:37.349341 DUTY Scan : NO K
9032 11:48:37.352359 ZQ Calibration : PASS
9033 11:48:37.352767 Jitter Meter : NO K
9034 11:48:37.355950 CBT Training : PASS
9035 11:48:37.359108 Write leveling : PASS
9036 11:48:37.359520 RX DQS gating : PASS
9037 11:48:37.362559 RX DQ/DQS(RDDQC) : PASS
9038 11:48:37.366053 TX DQ/DQS : PASS
9039 11:48:37.366506 RX DATLAT : PASS
9040 11:48:37.369478 RX DQ/DQS(Engine): PASS
9041 11:48:37.372448 TX OE : PASS
9042 11:48:37.372958 All Pass.
9043 11:48:37.373292
9044 11:48:37.375749 DramC Write-DBI on
9045 11:48:37.376165 PER_BANK_REFRESH: Hybrid Mode
9046 11:48:37.379003 TX_TRACKING: ON
9047 11:48:37.389011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9048 11:48:37.395574 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9049 11:48:37.402452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 11:48:37.405831 [FAST_K] Save calibration result to emmc
9051 11:48:37.409283 sync common calibartion params.
9052 11:48:37.411994 sync cbt_mode0:1, 1:1
9053 11:48:37.412566 dram_init: ddr_geometry: 2
9054 11:48:37.415357 dram_init: ddr_geometry: 2
9055 11:48:37.418515 dram_init: ddr_geometry: 2
9056 11:48:37.422192 0:dram_rank_size:100000000
9057 11:48:37.422835 1:dram_rank_size:100000000
9058 11:48:37.429037 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9059 11:48:37.431656 DFS_SHUFFLE_HW_MODE: ON
9060 11:48:37.435678 dramc_set_vcore_voltage set vcore to 725000
9061 11:48:37.438638 Read voltage for 1600, 0
9062 11:48:37.439169 Vio18 = 0
9063 11:48:37.439652 Vcore = 725000
9064 11:48:37.441599 Vdram = 0
9065 11:48:37.442172 Vddq = 0
9066 11:48:37.442709 Vmddr = 0
9067 11:48:37.445334 switch to 3200 Mbps bootup
9068 11:48:37.445807 [DramcRunTimeConfig]
9069 11:48:37.448311 PHYPLL
9070 11:48:37.448887 DPM_CONTROL_AFTERK: ON
9071 11:48:37.451465 PER_BANK_REFRESH: ON
9072 11:48:37.455155 REFRESH_OVERHEAD_REDUCTION: ON
9073 11:48:37.455730 CMD_PICG_NEW_MODE: OFF
9074 11:48:37.458467 XRTWTW_NEW_MODE: ON
9075 11:48:37.459044 XRTRTR_NEW_MODE: ON
9076 11:48:37.461665 TX_TRACKING: ON
9077 11:48:37.462141 RDSEL_TRACKING: OFF
9078 11:48:37.464451 DQS Precalculation for DVFS: ON
9079 11:48:37.467734 RX_TRACKING: OFF
9080 11:48:37.468208 HW_GATING DBG: ON
9081 11:48:37.470948 ZQCS_ENABLE_LP4: ON
9082 11:48:37.471374 RX_PICG_NEW_MODE: ON
9083 11:48:37.474308 TX_PICG_NEW_MODE: ON
9084 11:48:37.478055 ENABLE_RX_DCM_DPHY: ON
9085 11:48:37.478639 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9086 11:48:37.481487 DUMMY_READ_FOR_TRACKING: OFF
9087 11:48:37.484168 !!! SPM_CONTROL_AFTERK: OFF
9088 11:48:37.488375 !!! SPM could not control APHY
9089 11:48:37.488967 IMPEDANCE_TRACKING: ON
9090 11:48:37.490895 TEMP_SENSOR: ON
9091 11:48:37.493961 HW_SAVE_FOR_SR: OFF
9092 11:48:37.494406 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9093 11:48:37.500728 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9094 11:48:37.501247 Read ODT Tracking: ON
9095 11:48:37.504383 Refresh Rate DeBounce: ON
9096 11:48:37.507518 DFS_NO_QUEUE_FLUSH: ON
9097 11:48:37.508139 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9098 11:48:37.510802 ENABLE_DFS_RUNTIME_MRW: OFF
9099 11:48:37.514307 DDR_RESERVE_NEW_MODE: ON
9100 11:48:37.517290 MR_CBT_SWITCH_FREQ: ON
9101 11:48:37.517709 =========================
9102 11:48:37.536690 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9103 11:48:37.540132 dram_init: ddr_geometry: 2
9104 11:48:37.558993 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9105 11:48:37.561649 dram_init: dram init end (result: 0)
9106 11:48:37.568412 DRAM-K: Full calibration passed in 24397 msecs
9107 11:48:37.571492 MRC: failed to locate region type 0.
9108 11:48:37.571965 DRAM rank0 size:0x100000000,
9109 11:48:37.574687 DRAM rank1 size=0x100000000
9110 11:48:37.585110 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9111 11:48:37.591950 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9112 11:48:37.598293 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9113 11:48:37.605253 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9114 11:48:37.607855 DRAM rank0 size:0x100000000,
9115 11:48:37.611448 DRAM rank1 size=0x100000000
9116 11:48:37.612035 CBMEM:
9117 11:48:37.615035 IMD: root @ 0xfffff000 254 entries.
9118 11:48:37.618466 IMD: root @ 0xffffec00 62 entries.
9119 11:48:37.621605 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9120 11:48:37.627772 WARNING: RO_VPD is uninitialized or empty.
9121 11:48:37.631272 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9122 11:48:37.638059 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9123 11:48:37.650922 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9124 11:48:37.662326 BS: romstage times (exec / console): total (unknown) / 23929 ms
9125 11:48:37.662480
9126 11:48:37.662600
9127 11:48:37.671993 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9128 11:48:37.675662 ARM64: Exception handlers installed.
9129 11:48:37.678453 ARM64: Testing exception
9130 11:48:37.682529 ARM64: Done test exception
9131 11:48:37.682620 Enumerating buses...
9132 11:48:37.685110 Show all devs... Before device enumeration.
9133 11:48:37.689314 Root Device: enabled 1
9134 11:48:37.692131 CPU_CLUSTER: 0: enabled 1
9135 11:48:37.692212 CPU: 00: enabled 1
9136 11:48:37.695227 Compare with tree...
9137 11:48:37.695307 Root Device: enabled 1
9138 11:48:37.698562 CPU_CLUSTER: 0: enabled 1
9139 11:48:37.702391 CPU: 00: enabled 1
9140 11:48:37.702472 Root Device scanning...
9141 11:48:37.705187 scan_static_bus for Root Device
9142 11:48:37.708117 CPU_CLUSTER: 0 enabled
9143 11:48:37.711726 scan_static_bus for Root Device done
9144 11:48:37.714770 scan_bus: bus Root Device finished in 8 msecs
9145 11:48:37.714852 done
9146 11:48:37.721640 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9147 11:48:37.724755 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9148 11:48:37.731757 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9149 11:48:37.734539 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9150 11:48:37.738610 Allocating resources...
9151 11:48:37.741262 Reading resources...
9152 11:48:37.744263 Root Device read_resources bus 0 link: 0
9153 11:48:37.747732 DRAM rank0 size:0x100000000,
9154 11:48:37.747814 DRAM rank1 size=0x100000000
9155 11:48:37.754548 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9156 11:48:37.754632 CPU: 00 missing read_resources
9157 11:48:37.760660 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9158 11:48:37.764197 Root Device read_resources bus 0 link: 0 done
9159 11:48:37.767549 Done reading resources.
9160 11:48:37.770733 Show resources in subtree (Root Device)...After reading.
9161 11:48:37.774143 Root Device child on link 0 CPU_CLUSTER: 0
9162 11:48:37.777762 CPU_CLUSTER: 0 child on link 0 CPU: 00
9163 11:48:37.787428 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9164 11:48:37.787513 CPU: 00
9165 11:48:37.793631 Root Device assign_resources, bus 0 link: 0
9166 11:48:37.797314 CPU_CLUSTER: 0 missing set_resources
9167 11:48:37.800416 Root Device assign_resources, bus 0 link: 0 done
9168 11:48:37.800533 Done setting resources.
9169 11:48:37.807740 Show resources in subtree (Root Device)...After assigning values.
9170 11:48:37.810406 Root Device child on link 0 CPU_CLUSTER: 0
9171 11:48:37.816884 CPU_CLUSTER: 0 child on link 0 CPU: 00
9172 11:48:37.823380 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9173 11:48:37.826911 CPU: 00
9174 11:48:37.827057 Done allocating resources.
9175 11:48:37.833564 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9176 11:48:37.833720 Enabling resources...
9177 11:48:37.836836 done.
9178 11:48:37.840439 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9179 11:48:37.844328 Initializing devices...
9180 11:48:37.844492 Root Device init
9181 11:48:37.847275 init hardware done!
9182 11:48:37.847446 0x00000018: ctrlr->caps
9183 11:48:37.849839 52.000 MHz: ctrlr->f_max
9184 11:48:37.853412 0.400 MHz: ctrlr->f_min
9185 11:48:37.856681 0x40ff8080: ctrlr->voltages
9186 11:48:37.856877 sclk: 390625
9187 11:48:37.856983 Bus Width = 1
9188 11:48:37.859589 sclk: 390625
9189 11:48:37.859757 Bus Width = 1
9190 11:48:37.863344 Early init status = 3
9191 11:48:37.866384 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9192 11:48:37.870898 in-header: 03 fc 00 00 01 00 00 00
9193 11:48:37.874018 in-data: 00
9194 11:48:37.877291 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9195 11:48:37.883185 in-header: 03 fd 00 00 00 00 00 00
9196 11:48:37.886405 in-data:
9197 11:48:37.889603 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9198 11:48:37.894055 in-header: 03 fc 00 00 01 00 00 00
9199 11:48:37.896890 in-data: 00
9200 11:48:37.900410 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9201 11:48:37.906221 in-header: 03 fd 00 00 00 00 00 00
9202 11:48:37.909479 in-data:
9203 11:48:37.912940 [SSUSB] Setting up USB HOST controller...
9204 11:48:37.916049 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9205 11:48:37.919828 [SSUSB] phy power-on done.
9206 11:48:37.923209 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9207 11:48:37.929530 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9208 11:48:37.932856 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9209 11:48:37.939363 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9210 11:48:37.946241 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9211 11:48:37.952490 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9212 11:48:37.959148 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9213 11:48:37.965615 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9214 11:48:37.968786 SPM: binary array size = 0x9dc
9215 11:48:37.972406 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9216 11:48:37.978752 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9217 11:48:37.985944 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9218 11:48:37.992566 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9219 11:48:37.995305 configure_display: Starting display init
9220 11:48:38.030172 anx7625_power_on_init: Init interface.
9221 11:48:38.033048 anx7625_disable_pd_protocol: Disabled PD feature.
9222 11:48:38.036534 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9223 11:48:38.064085 anx7625_start_dp_work: Secure OCM version=00
9224 11:48:38.067149 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9225 11:48:38.082459 sp_tx_get_edid_block: EDID Block = 1
9226 11:48:38.184948 Extracted contents:
9227 11:48:38.187769 header: 00 ff ff ff ff ff ff 00
9228 11:48:38.191203 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9229 11:48:38.194777 version: 01 04
9230 11:48:38.197774 basic params: 95 1f 11 78 0a
9231 11:48:38.202176 chroma info: 76 90 94 55 54 90 27 21 50 54
9232 11:48:38.204720 established: 00 00 00
9233 11:48:38.211165 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9234 11:48:38.217980 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9235 11:48:38.220704 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9236 11:48:38.227560 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9237 11:48:38.234067 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9238 11:48:38.237368 extensions: 00
9239 11:48:38.237938 checksum: fb
9240 11:48:38.238539
9241 11:48:38.243837 Manufacturer: IVO Model 57d Serial Number 0
9242 11:48:38.244400 Made week 0 of 2020
9243 11:48:38.247535 EDID version: 1.4
9244 11:48:38.247992 Digital display
9245 11:48:38.250292 6 bits per primary color channel
9246 11:48:38.254404 DisplayPort interface
9247 11:48:38.254972 Maximum image size: 31 cm x 17 cm
9248 11:48:38.257105 Gamma: 220%
9249 11:48:38.257672 Check DPMS levels
9250 11:48:38.263923 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9251 11:48:38.267320 First detailed timing is preferred timing
9252 11:48:38.270177 Established timings supported:
9253 11:48:38.270691 Standard timings supported:
9254 11:48:38.273609 Detailed timings
9255 11:48:38.276674 Hex of detail: 383680a07038204018303c0035ae10000019
9256 11:48:38.283564 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9257 11:48:38.287083 0780 0798 07c8 0820 hborder 0
9258 11:48:38.290288 0438 043b 0447 0458 vborder 0
9259 11:48:38.293508 -hsync -vsync
9260 11:48:38.293967 Did detailed timing
9261 11:48:38.300223 Hex of detail: 000000000000000000000000000000000000
9262 11:48:38.303463 Manufacturer-specified data, tag 0
9263 11:48:38.306985 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9264 11:48:38.310339 ASCII string: InfoVision
9265 11:48:38.314094 Hex of detail: 000000fe00523134304e574635205248200a
9266 11:48:38.316536 ASCII string: R140NWF5 RH
9267 11:48:38.316992 Checksum
9268 11:48:38.319844 Checksum: 0xfb (valid)
9269 11:48:38.323286 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9270 11:48:38.326062 DSI data_rate: 832800000 bps
9271 11:48:38.333411 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9272 11:48:38.336323 anx7625_parse_edid: pixelclock(138800).
9273 11:48:38.340126 hactive(1920), hsync(48), hfp(24), hbp(88)
9274 11:48:38.343485 vactive(1080), vsync(12), vfp(3), vbp(17)
9275 11:48:38.345710 anx7625_dsi_config: config dsi.
9276 11:48:38.352855 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9277 11:48:38.366923 anx7625_dsi_config: success to config DSI
9278 11:48:38.370214 anx7625_dp_start: MIPI phy setup OK.
9279 11:48:38.373695 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9280 11:48:38.376555 mtk_ddp_mode_set invalid vrefresh 60
9281 11:48:38.380696 main_disp_path_setup
9282 11:48:38.381106 ovl_layer_smi_id_en
9283 11:48:38.383153 ovl_layer_smi_id_en
9284 11:48:38.383568 ccorr_config
9285 11:48:38.383897 aal_config
9286 11:48:38.386484 gamma_config
9287 11:48:38.386950 postmask_config
9288 11:48:38.389713 dither_config
9289 11:48:38.393012 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9290 11:48:38.399777 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9291 11:48:38.403100 Root Device init finished in 555 msecs
9292 11:48:38.406213 CPU_CLUSTER: 0 init
9293 11:48:38.412811 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9294 11:48:38.419926 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9295 11:48:38.420337 APU_MBOX 0x190000b0 = 0x10001
9296 11:48:38.423105 APU_MBOX 0x190001b0 = 0x10001
9297 11:48:38.426455 APU_MBOX 0x190005b0 = 0x10001
9298 11:48:38.429016 APU_MBOX 0x190006b0 = 0x10001
9299 11:48:38.435694 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9300 11:48:38.445547 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9301 11:48:38.457772 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9302 11:48:38.464727 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9303 11:48:38.476722 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9304 11:48:38.486089 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9305 11:48:38.489158 CPU_CLUSTER: 0 init finished in 81 msecs
9306 11:48:38.495609 Devices initialized
9307 11:48:38.496027 Show all devs... After init.
9308 11:48:38.496361 Root Device: enabled 1
9309 11:48:38.499421 CPU_CLUSTER: 0: enabled 1
9310 11:48:38.502084 CPU: 00: enabled 1
9311 11:48:38.505152 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9312 11:48:38.508896 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9313 11:48:38.512028 ELOG: NV offset 0x57f000 size 0x1000
9314 11:48:38.519053 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9315 11:48:38.525553 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9316 11:48:38.529355 ELOG: Event(17) added with size 13 at 2023-11-24 11:48:38 UTC
9317 11:48:38.535107 out: cmd=0x121: 03 db 21 01 00 00 00 00
9318 11:48:38.538241 in-header: 03 46 00 00 2c 00 00 00
9319 11:48:38.548670 in-data: 19 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9320 11:48:38.555401 ELOG: Event(A1) added with size 10 at 2023-11-24 11:48:38 UTC
9321 11:48:38.562092 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9322 11:48:38.568585 ELOG: Event(A0) added with size 9 at 2023-11-24 11:48:38 UTC
9323 11:48:38.571094 elog_add_boot_reason: Logged dev mode boot
9324 11:48:38.578018 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9325 11:48:38.578625 Finalize devices...
9326 11:48:38.581530 Devices finalized
9327 11:48:38.584193 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9328 11:48:38.587698 Writing coreboot table at 0xffe64000
9329 11:48:38.590934 0. 000000000010a000-0000000000113fff: RAMSTAGE
9330 11:48:38.597819 1. 0000000040000000-00000000400fffff: RAM
9331 11:48:38.600497 2. 0000000040100000-000000004032afff: RAMSTAGE
9332 11:48:38.604240 3. 000000004032b000-00000000545fffff: RAM
9333 11:48:38.607141 4. 0000000054600000-000000005465ffff: BL31
9334 11:48:38.610583 5. 0000000054660000-00000000ffe63fff: RAM
9335 11:48:38.617162 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9336 11:48:38.620394 7. 0000000100000000-000000023fffffff: RAM
9337 11:48:38.624040 Passing 5 GPIOs to payload:
9338 11:48:38.626588 NAME | PORT | POLARITY | VALUE
9339 11:48:38.633525 EC in RW | 0x000000aa | low | undefined
9340 11:48:38.636745 EC interrupt | 0x00000005 | low | undefined
9341 11:48:38.644151 TPM interrupt | 0x000000ab | high | undefined
9342 11:48:38.646899 SD card detect | 0x00000011 | high | undefined
9343 11:48:38.649975 speaker enable | 0x00000093 | high | undefined
9344 11:48:38.653617 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9345 11:48:38.657618 in-header: 03 f9 00 00 02 00 00 00
9346 11:48:38.660755 in-data: 02 00
9347 11:48:38.664306 ADC[4]: Raw value=903325 ID=7
9348 11:48:38.667524 ADC[3]: Raw value=213916 ID=1
9349 11:48:38.667763 RAM Code: 0x71
9350 11:48:38.670868 ADC[6]: Raw value=74630 ID=0
9351 11:48:38.674083 ADC[5]: Raw value=213546 ID=1
9352 11:48:38.674370 SKU Code: 0x1
9353 11:48:38.681012 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd3
9354 11:48:38.681358 coreboot table: 964 bytes.
9355 11:48:38.683878 IMD ROOT 0. 0xfffff000 0x00001000
9356 11:48:38.687606 IMD SMALL 1. 0xffffe000 0x00001000
9357 11:48:38.690762 RO MCACHE 2. 0xffffc000 0x00001104
9358 11:48:38.693903 CONSOLE 3. 0xfff7c000 0x00080000
9359 11:48:38.697630 FMAP 4. 0xfff7b000 0x00000452
9360 11:48:38.701339 TIME STAMP 5. 0xfff7a000 0x00000910
9361 11:48:38.704683 VBOOT WORK 6. 0xfff66000 0x00014000
9362 11:48:38.707117 RAMOOPS 7. 0xffe66000 0x00100000
9363 11:48:38.711056 COREBOOT 8. 0xffe64000 0x00002000
9364 11:48:38.714429 IMD small region:
9365 11:48:38.717716 IMD ROOT 0. 0xffffec00 0x00000400
9366 11:48:38.721217 VPD 1. 0xffffeb80 0x0000006c
9367 11:48:38.724061 MMC STATUS 2. 0xffffeb60 0x00000004
9368 11:48:38.730465 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9369 11:48:38.731053 Probing TPM: done!
9370 11:48:38.736958 Connected to device vid:did:rid of 1ae0:0028:00
9371 11:48:38.744037 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9372 11:48:38.747373 Initialized TPM device CR50 revision 0
9373 11:48:38.750890 Checking cr50 for pending updates
9374 11:48:38.756533 Reading cr50 TPM mode
9375 11:48:38.764702 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9376 11:48:38.771637 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9377 11:48:38.811259 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9378 11:48:38.814900 Checking segment from ROM address 0x40100000
9379 11:48:38.818428 Checking segment from ROM address 0x4010001c
9380 11:48:38.824718 Loading segment from ROM address 0x40100000
9381 11:48:38.825296 code (compression=0)
9382 11:48:38.834842 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9383 11:48:38.841213 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9384 11:48:38.841779 it's not compressed!
9385 11:48:38.847924 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9386 11:48:38.854769 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9387 11:48:38.871689 Loading segment from ROM address 0x4010001c
9388 11:48:38.872258 Entry Point 0x80000000
9389 11:48:38.875031 Loaded segments
9390 11:48:38.878895 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9391 11:48:38.885545 Jumping to boot code at 0x80000000(0xffe64000)
9392 11:48:38.892293 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9393 11:48:38.898182 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9394 11:48:38.906549 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9395 11:48:38.910219 Checking segment from ROM address 0x40100000
9396 11:48:38.913182 Checking segment from ROM address 0x4010001c
9397 11:48:38.919861 Loading segment from ROM address 0x40100000
9398 11:48:38.920414 code (compression=1)
9399 11:48:38.926304 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9400 11:48:38.936780 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9401 11:48:38.937354 using LZMA
9402 11:48:38.944684 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9403 11:48:38.952036 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9404 11:48:38.954509 Loading segment from ROM address 0x4010001c
9405 11:48:38.955076 Entry Point 0x54601000
9406 11:48:38.958072 Loaded segments
9407 11:48:38.961457 NOTICE: MT8192 bl31_setup
9408 11:48:38.970445 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9409 11:48:38.974413 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9410 11:48:38.975576 WARNING: region 0:
9411 11:48:38.978370 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9412 11:48:38.978834 WARNING: region 1:
9413 11:48:38.984684 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9414 11:48:38.988416 WARNING: region 2:
9415 11:48:38.991839 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9416 11:48:38.994726 WARNING: region 3:
9417 11:48:38.997917 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9418 11:48:39.001304 WARNING: region 4:
9419 11:48:39.007907 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9420 11:48:39.008325 WARNING: region 5:
9421 11:48:39.012092 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9422 11:48:39.014494 WARNING: region 6:
9423 11:48:39.017860 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9424 11:48:39.021402 WARNING: region 7:
9425 11:48:39.024275 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9426 11:48:39.031535 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9427 11:48:39.034314 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9428 11:48:39.037972 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9429 11:48:39.045222 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9430 11:48:39.048499 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9431 11:48:39.054432 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9432 11:48:39.057833 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9433 11:48:39.060998 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9434 11:48:39.067617 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9435 11:48:39.071137 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9436 11:48:39.074293 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9437 11:48:39.081751 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9438 11:48:39.084440 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9439 11:48:39.092434 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9440 11:48:39.094219 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9441 11:48:39.097217 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9442 11:48:39.103781 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9443 11:48:39.107038 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9444 11:48:39.114069 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9445 11:48:39.117086 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9446 11:48:39.120376 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9447 11:48:39.127332 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9448 11:48:39.130487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9449 11:48:39.133789 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9450 11:48:39.140817 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9451 11:48:39.144097 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9452 11:48:39.150383 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9453 11:48:39.154042 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9454 11:48:39.157681 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9455 11:48:39.164414 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9456 11:48:39.167761 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9457 11:48:39.173806 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9458 11:48:39.177703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9459 11:48:39.180903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9460 11:48:39.183940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9461 11:48:39.190533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9462 11:48:39.194033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9463 11:48:39.197301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9464 11:48:39.200529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9465 11:48:39.207035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9466 11:48:39.210511 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9467 11:48:39.214181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9468 11:48:39.217132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9469 11:48:39.223193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9470 11:48:39.226897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9471 11:48:39.230112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9472 11:48:39.234078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9473 11:48:39.240121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9474 11:48:39.243925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9475 11:48:39.249831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9476 11:48:39.253780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9477 11:48:39.257681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9478 11:48:39.262997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9479 11:48:39.267079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9480 11:48:39.272749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9481 11:48:39.276966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9482 11:48:39.283875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9483 11:48:39.286391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9484 11:48:39.293355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9485 11:48:39.296637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9486 11:48:39.299942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9487 11:48:39.306927 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9488 11:48:39.309421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9489 11:48:39.317050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9490 11:48:39.320154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9491 11:48:39.326502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9492 11:48:39.330784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9493 11:48:39.335903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9494 11:48:39.339582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9495 11:48:39.343089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9496 11:48:39.349413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9497 11:48:39.352495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9498 11:48:39.359254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9499 11:48:39.362779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9500 11:48:39.369823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9501 11:48:39.372497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9502 11:48:39.376161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9503 11:48:39.382991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9504 11:48:39.385674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9505 11:48:39.392418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9506 11:48:39.396246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9507 11:48:39.402615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9508 11:48:39.406710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9509 11:48:39.412304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9510 11:48:39.415489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9511 11:48:39.419056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9512 11:48:39.426121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9513 11:48:39.429039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9514 11:48:39.435688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9515 11:48:39.438995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9516 11:48:39.445455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9517 11:48:39.448779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9518 11:48:39.451861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9519 11:48:39.459036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9520 11:48:39.462582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9521 11:48:39.468767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9522 11:48:39.471859 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9523 11:48:39.475294 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9524 11:48:39.482668 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9525 11:48:39.485261 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9526 11:48:39.488923 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9527 11:48:39.491628 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9528 11:48:39.498843 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9529 11:48:39.501898 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9530 11:48:39.508400 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9531 11:48:39.511784 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9532 11:48:39.518796 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9533 11:48:39.522018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9534 11:48:39.526000 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9535 11:48:39.532274 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9536 11:48:39.534989 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9537 11:48:39.538845 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9538 11:48:39.545339 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9539 11:48:39.548666 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9540 11:48:39.555390 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9541 11:48:39.558709 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9542 11:48:39.561545 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9543 11:48:39.569130 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9544 11:48:39.572284 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9545 11:48:39.574489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9546 11:48:39.581781 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9547 11:48:39.585177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9548 11:48:39.588575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9549 11:48:39.591995 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9550 11:48:39.598334 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9551 11:48:39.601364 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9552 11:48:39.605539 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9553 11:48:39.611357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9554 11:48:39.615053 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9555 11:48:39.621498 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9556 11:48:39.624394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9557 11:48:39.627453 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9558 11:48:39.635218 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9559 11:48:39.638214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9560 11:48:39.645607 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9561 11:48:39.647958 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9562 11:48:39.651853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9563 11:48:39.657667 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9564 11:48:39.661430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9565 11:48:39.667712 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9566 11:48:39.671074 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9567 11:48:39.674481 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9568 11:48:39.681485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9569 11:48:39.684516 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9570 11:48:39.691119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9571 11:48:39.694418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9572 11:48:39.698166 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9573 11:48:39.704002 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9574 11:48:39.708310 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9575 11:48:39.714563 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9576 11:48:39.717366 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9577 11:48:39.721185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9578 11:48:39.727074 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9579 11:48:39.730430 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9580 11:48:39.737341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9581 11:48:39.740905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9582 11:48:39.744176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9583 11:48:39.750217 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9584 11:48:39.753898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9585 11:48:39.760246 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9586 11:48:39.763840 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9587 11:48:39.767720 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9588 11:48:39.773399 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9589 11:48:39.776410 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9590 11:48:39.783717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9591 11:48:39.786453 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9592 11:48:39.790069 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9593 11:48:39.796383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9594 11:48:39.800107 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9595 11:48:39.806414 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9596 11:48:39.809703 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9597 11:48:39.813001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9598 11:48:39.819407 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9599 11:48:39.822584 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9600 11:48:39.829586 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9601 11:48:39.832583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9602 11:48:39.835630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9603 11:48:39.842894 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9604 11:48:39.845836 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9605 11:48:39.852430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9606 11:48:39.855921 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9607 11:48:39.859398 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9608 11:48:39.865618 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9609 11:48:39.868611 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9610 11:48:39.875627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9611 11:48:39.879240 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9612 11:48:39.882508 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9613 11:48:39.888792 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9614 11:48:39.891853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9615 11:48:39.898364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9616 11:48:39.902105 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9617 11:48:39.908367 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9618 11:48:39.911622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9619 11:48:39.915122 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9620 11:48:39.921701 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9621 11:48:39.925039 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9622 11:48:39.931592 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9623 11:48:39.935060 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9624 11:48:39.938243 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9625 11:48:39.945063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9626 11:48:39.947697 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9627 11:48:39.954311 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9628 11:48:39.958808 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9629 11:48:39.964127 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9630 11:48:39.967878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9631 11:48:39.971033 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9632 11:48:39.978706 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9633 11:48:39.981089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9634 11:48:39.987785 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9635 11:48:39.991284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9636 11:48:39.998040 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9637 11:48:40.001048 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9638 11:48:40.004285 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9639 11:48:40.010769 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9640 11:48:40.013814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9641 11:48:40.020548 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9642 11:48:40.024435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9643 11:48:40.030187 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9644 11:48:40.033747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9645 11:48:40.036851 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9646 11:48:40.043332 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9647 11:48:40.046634 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9648 11:48:40.053531 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9649 11:48:40.056338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9650 11:48:40.062963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9651 11:48:40.066450 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9652 11:48:40.072932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9653 11:48:40.076332 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9654 11:48:40.080522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9655 11:48:40.086357 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9656 11:48:40.089275 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9657 11:48:40.093382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9658 11:48:40.096349 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9659 11:48:40.102801 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9660 11:48:40.105929 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9661 11:48:40.109670 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9662 11:48:40.115928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9663 11:48:40.118665 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9664 11:48:40.122188 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9665 11:48:40.128788 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9666 11:48:40.132562 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9667 11:48:40.139298 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9668 11:48:40.142028 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9669 11:48:40.145445 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9670 11:48:40.152889 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9671 11:48:40.155706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9672 11:48:40.158720 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9673 11:48:40.165076 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9674 11:48:40.168657 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9675 11:48:40.175221 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9676 11:48:40.178517 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9677 11:48:40.181538 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9678 11:48:40.188086 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9679 11:48:40.191886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9680 11:48:40.194747 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9681 11:48:40.201496 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9682 11:48:40.204563 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9683 11:48:40.211075 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9684 11:48:40.214093 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9685 11:48:40.217492 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9686 11:48:40.224405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9687 11:48:40.227619 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9688 11:48:40.234416 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9689 11:48:40.237329 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9690 11:48:40.240751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9691 11:48:40.247227 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9692 11:48:40.250917 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9693 11:48:40.254189 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9694 11:48:40.260843 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9695 11:48:40.263549 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9696 11:48:40.267325 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9697 11:48:40.270507 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9698 11:48:40.277755 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9699 11:48:40.280209 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9700 11:48:40.283410 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9701 11:48:40.286622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9702 11:48:40.293892 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9703 11:48:40.297119 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9704 11:48:40.300245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9705 11:48:40.303967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9706 11:48:40.309909 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9707 11:48:40.313607 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9708 11:48:40.316464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9709 11:48:40.322958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9710 11:48:40.326370 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9711 11:48:40.333026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9712 11:48:40.336660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9713 11:48:40.342949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9714 11:48:40.345928 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9715 11:48:40.350090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9716 11:48:40.356347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9717 11:48:40.360475 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9718 11:48:40.365733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9719 11:48:40.369818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9720 11:48:40.375814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9721 11:48:40.379480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9722 11:48:40.382712 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9723 11:48:40.389411 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9724 11:48:40.392728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9725 11:48:40.399523 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9726 11:48:40.402695 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9727 11:48:40.405550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9728 11:48:40.412312 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9729 11:48:40.415795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9730 11:48:40.422208 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9731 11:48:40.425376 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9732 11:48:40.432261 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9733 11:48:40.435658 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9734 11:48:40.438591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9735 11:48:40.444791 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9736 11:48:40.450054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9737 11:48:40.455079 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9738 11:48:40.458721 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9739 11:48:40.461563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9740 11:48:40.468946 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9741 11:48:40.471686 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9742 11:48:40.478138 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9743 11:48:40.481430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9744 11:48:40.487962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9745 11:48:40.491007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9746 11:48:40.497995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9747 11:48:40.501084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9748 11:48:40.504383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9749 11:48:40.511243 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9750 11:48:40.514295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9751 11:48:40.520702 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9752 11:48:40.524121 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9753 11:48:40.526883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9754 11:48:40.533647 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9755 11:48:40.536797 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9756 11:48:40.543817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9757 11:48:40.546974 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9758 11:48:40.550333 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9759 11:48:40.557057 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9760 11:48:40.560266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9761 11:48:40.566424 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9762 11:48:40.569704 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9763 11:48:40.576446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9764 11:48:40.579739 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9765 11:48:40.583156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9766 11:48:40.590227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9767 11:48:40.593636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9768 11:48:40.599825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9769 11:48:40.602759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9770 11:48:40.609608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9771 11:48:40.613320 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9772 11:48:40.616657 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9773 11:48:40.622864 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9774 11:48:40.626150 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9775 11:48:40.632806 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9776 11:48:40.635593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9777 11:48:40.643798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9778 11:48:40.645910 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9779 11:48:40.649265 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9780 11:48:40.655661 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9781 11:48:40.659220 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9782 11:48:40.666108 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9783 11:48:40.669428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9784 11:48:40.675314 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9785 11:48:40.678985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9786 11:48:40.684955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9787 11:48:40.688869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9788 11:48:40.691935 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9789 11:48:40.699033 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9790 11:48:40.701943 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9791 11:48:40.708367 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9792 11:48:40.711723 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9793 11:48:40.718368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9794 11:48:40.722985 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9795 11:48:40.725611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9796 11:48:40.731555 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9797 11:48:40.734850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9798 11:48:40.741205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9799 11:48:40.744287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9800 11:48:40.751267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9801 11:48:40.754833 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9802 11:48:40.761768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9803 11:48:40.764784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9804 11:48:40.767678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9805 11:48:40.774871 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9806 11:48:40.777752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9807 11:48:40.784799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9808 11:48:40.787389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9809 11:48:40.794349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9810 11:48:40.797373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9811 11:48:40.800786 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9812 11:48:40.807571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9813 11:48:40.810537 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9814 11:48:40.817670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9815 11:48:40.821184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9816 11:48:40.827664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9817 11:48:40.830824 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9818 11:48:40.837194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9819 11:48:40.840527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9820 11:48:40.843734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9821 11:48:40.850141 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9822 11:48:40.853321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9823 11:48:40.860254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9824 11:48:40.863910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9825 11:48:40.870609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9826 11:48:40.873035 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9827 11:48:40.879970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9828 11:48:40.883569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9829 11:48:40.887196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9830 11:48:40.893547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9831 11:48:40.896853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9832 11:48:40.902487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9833 11:48:40.905994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9834 11:48:40.912595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9835 11:48:40.915740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9836 11:48:40.922827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9837 11:48:40.925923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9838 11:48:40.932080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9839 11:48:40.936122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9840 11:48:40.942219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9841 11:48:40.945395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9842 11:48:40.952539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9843 11:48:40.955342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9844 11:48:40.961688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9845 11:48:40.965731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9846 11:48:40.972151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9847 11:48:40.975016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9848 11:48:40.982794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9849 11:48:40.984721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9850 11:48:40.991157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9851 11:48:40.995461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9852 11:48:41.001510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9853 11:48:41.005062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9854 11:48:41.011155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9855 11:48:41.014415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9856 11:48:41.021080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9857 11:48:41.024541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9858 11:48:41.031008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9859 11:48:41.037743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9860 11:48:41.040803 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9861 11:48:41.041316 INFO: [APUAPC] vio 0
9862 11:48:41.048185 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9863 11:48:41.051178 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9864 11:48:41.054681 INFO: [APUAPC] D0_APC_0: 0x400510
9865 11:48:41.057903 INFO: [APUAPC] D0_APC_1: 0x0
9866 11:48:41.061097 INFO: [APUAPC] D0_APC_2: 0x1540
9867 11:48:41.064529 INFO: [APUAPC] D0_APC_3: 0x0
9868 11:48:41.068021 INFO: [APUAPC] D1_APC_0: 0xffffffff
9869 11:48:41.071385 INFO: [APUAPC] D1_APC_1: 0xffffffff
9870 11:48:41.074405 INFO: [APUAPC] D1_APC_2: 0x3fffff
9871 11:48:41.077823 INFO: [APUAPC] D1_APC_3: 0x0
9872 11:48:41.081116 INFO: [APUAPC] D2_APC_0: 0xffffffff
9873 11:48:41.084200 INFO: [APUAPC] D2_APC_1: 0xffffffff
9874 11:48:41.087698 INFO: [APUAPC] D2_APC_2: 0x3fffff
9875 11:48:41.090902 INFO: [APUAPC] D2_APC_3: 0x0
9876 11:48:41.095287 INFO: [APUAPC] D3_APC_0: 0xffffffff
9877 11:48:41.099987 INFO: [APUAPC] D3_APC_1: 0xffffffff
9878 11:48:41.100885 INFO: [APUAPC] D3_APC_2: 0x3fffff
9879 11:48:41.104014 INFO: [APUAPC] D3_APC_3: 0x0
9880 11:48:41.107864 INFO: [APUAPC] D4_APC_0: 0xffffffff
9881 11:48:41.110741 INFO: [APUAPC] D4_APC_1: 0xffffffff
9882 11:48:41.114480 INFO: [APUAPC] D4_APC_2: 0x3fffff
9883 11:48:41.117506 INFO: [APUAPC] D4_APC_3: 0x0
9884 11:48:41.120680 INFO: [APUAPC] D5_APC_0: 0xffffffff
9885 11:48:41.124352 INFO: [APUAPC] D5_APC_1: 0xffffffff
9886 11:48:41.126783 INFO: [APUAPC] D5_APC_2: 0x3fffff
9887 11:48:41.130072 INFO: [APUAPC] D5_APC_3: 0x0
9888 11:48:41.133741 INFO: [APUAPC] D6_APC_0: 0xffffffff
9889 11:48:41.136831 INFO: [APUAPC] D6_APC_1: 0xffffffff
9890 11:48:41.140329 INFO: [APUAPC] D6_APC_2: 0x3fffff
9891 11:48:41.143592 INFO: [APUAPC] D6_APC_3: 0x0
9892 11:48:41.146990 INFO: [APUAPC] D7_APC_0: 0xffffffff
9893 11:48:41.150385 INFO: [APUAPC] D7_APC_1: 0xffffffff
9894 11:48:41.153223 INFO: [APUAPC] D7_APC_2: 0x3fffff
9895 11:48:41.153744 INFO: [APUAPC] D7_APC_3: 0x0
9896 11:48:41.160255 INFO: [APUAPC] D8_APC_0: 0xffffffff
9897 11:48:41.163436 INFO: [APUAPC] D8_APC_1: 0xffffffff
9898 11:48:41.166690 INFO: [APUAPC] D8_APC_2: 0x3fffff
9899 11:48:41.167118 INFO: [APUAPC] D8_APC_3: 0x0
9900 11:48:41.169642 INFO: [APUAPC] D9_APC_0: 0xffffffff
9901 11:48:41.176350 INFO: [APUAPC] D9_APC_1: 0xffffffff
9902 11:48:41.179873 INFO: [APUAPC] D9_APC_2: 0x3fffff
9903 11:48:41.180388 INFO: [APUAPC] D9_APC_3: 0x0
9904 11:48:41.183190 INFO: [APUAPC] D10_APC_0: 0xffffffff
9905 11:48:41.190322 INFO: [APUAPC] D10_APC_1: 0xffffffff
9906 11:48:41.193359 INFO: [APUAPC] D10_APC_2: 0x3fffff
9907 11:48:41.193929 INFO: [APUAPC] D10_APC_3: 0x0
9908 11:48:41.199591 INFO: [APUAPC] D11_APC_0: 0xffffffff
9909 11:48:41.202690 INFO: [APUAPC] D11_APC_1: 0xffffffff
9910 11:48:41.206548 INFO: [APUAPC] D11_APC_2: 0x3fffff
9911 11:48:41.207061 INFO: [APUAPC] D11_APC_3: 0x0
9912 11:48:41.214401 INFO: [APUAPC] D12_APC_0: 0xffffffff
9913 11:48:41.215758 INFO: [APUAPC] D12_APC_1: 0xffffffff
9914 11:48:41.219466 INFO: [APUAPC] D12_APC_2: 0x3fffff
9915 11:48:41.222853 INFO: [APUAPC] D12_APC_3: 0x0
9916 11:48:41.226786 INFO: [APUAPC] D13_APC_0: 0xffffffff
9917 11:48:41.229284 INFO: [APUAPC] D13_APC_1: 0xffffffff
9918 11:48:41.232589 INFO: [APUAPC] D13_APC_2: 0x3fffff
9919 11:48:41.236070 INFO: [APUAPC] D13_APC_3: 0x0
9920 11:48:41.238943 INFO: [APUAPC] D14_APC_0: 0xffffffff
9921 11:48:41.242814 INFO: [APUAPC] D14_APC_1: 0xffffffff
9922 11:48:41.246306 INFO: [APUAPC] D14_APC_2: 0x3fffff
9923 11:48:41.249170 INFO: [APUAPC] D14_APC_3: 0x0
9924 11:48:41.252806 INFO: [APUAPC] D15_APC_0: 0xffffffff
9925 11:48:41.256593 INFO: [APUAPC] D15_APC_1: 0xffffffff
9926 11:48:41.259006 INFO: [APUAPC] D15_APC_2: 0x3fffff
9927 11:48:41.262203 INFO: [APUAPC] D15_APC_3: 0x0
9928 11:48:41.265446 INFO: [APUAPC] APC_CON: 0x4
9929 11:48:41.265857 INFO: [NOCDAPC] D0_APC_0: 0x0
9930 11:48:41.268699 INFO: [NOCDAPC] D0_APC_1: 0x0
9931 11:48:41.271975 INFO: [NOCDAPC] D1_APC_0: 0x0
9932 11:48:41.275495 INFO: [NOCDAPC] D1_APC_1: 0xfff
9933 11:48:41.279215 INFO: [NOCDAPC] D2_APC_0: 0x0
9934 11:48:41.281687 INFO: [NOCDAPC] D2_APC_1: 0xfff
9935 11:48:41.284949 INFO: [NOCDAPC] D3_APC_0: 0x0
9936 11:48:41.288981 INFO: [NOCDAPC] D3_APC_1: 0xfff
9937 11:48:41.291710 INFO: [NOCDAPC] D4_APC_0: 0x0
9938 11:48:41.294917 INFO: [NOCDAPC] D4_APC_1: 0xfff
9939 11:48:41.298657 INFO: [NOCDAPC] D5_APC_0: 0x0
9940 11:48:41.301329 INFO: [NOCDAPC] D5_APC_1: 0xfff
9941 11:48:41.301742 INFO: [NOCDAPC] D6_APC_0: 0x0
9942 11:48:41.305031 INFO: [NOCDAPC] D6_APC_1: 0xfff
9943 11:48:41.307799 INFO: [NOCDAPC] D7_APC_0: 0x0
9944 11:48:41.311201 INFO: [NOCDAPC] D7_APC_1: 0xfff
9945 11:48:41.314440 INFO: [NOCDAPC] D8_APC_0: 0x0
9946 11:48:41.317763 INFO: [NOCDAPC] D8_APC_1: 0xfff
9947 11:48:41.321302 INFO: [NOCDAPC] D9_APC_0: 0x0
9948 11:48:41.324527 INFO: [NOCDAPC] D9_APC_1: 0xfff
9949 11:48:41.328210 INFO: [NOCDAPC] D10_APC_0: 0x0
9950 11:48:41.330760 INFO: [NOCDAPC] D10_APC_1: 0xfff
9951 11:48:41.334723 INFO: [NOCDAPC] D11_APC_0: 0x0
9952 11:48:41.337613 INFO: [NOCDAPC] D11_APC_1: 0xfff
9953 11:48:41.340773 INFO: [NOCDAPC] D12_APC_0: 0x0
9954 11:48:41.344176 INFO: [NOCDAPC] D12_APC_1: 0xfff
9955 11:48:41.344690 INFO: [NOCDAPC] D13_APC_0: 0x0
9956 11:48:41.347085 INFO: [NOCDAPC] D13_APC_1: 0xfff
9957 11:48:41.350599 INFO: [NOCDAPC] D14_APC_0: 0x0
9958 11:48:41.353545 INFO: [NOCDAPC] D14_APC_1: 0xfff
9959 11:48:41.357566 INFO: [NOCDAPC] D15_APC_0: 0x0
9960 11:48:41.360342 INFO: [NOCDAPC] D15_APC_1: 0xfff
9961 11:48:41.364033 INFO: [NOCDAPC] APC_CON: 0x4
9962 11:48:41.366954 INFO: [APUAPC] set_apusys_apc done
9963 11:48:41.370164 INFO: [DEVAPC] devapc_init done
9964 11:48:41.374156 INFO: GICv3 without legacy support detected.
9965 11:48:41.380325 INFO: ARM GICv3 driver initialized in EL3
9966 11:48:41.383245 INFO: Maximum SPI INTID supported: 639
9967 11:48:41.387234 INFO: BL31: Initializing runtime services
9968 11:48:41.393330 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9969 11:48:41.396643 INFO: SPM: enable CPC mode
9970 11:48:41.399820 INFO: mcdi ready for mcusys-off-idle and system suspend
9971 11:48:41.406115 INFO: BL31: Preparing for EL3 exit to normal world
9972 11:48:41.409546 INFO: Entry point address = 0x80000000
9973 11:48:41.410068 INFO: SPSR = 0x8
9974 11:48:41.416094
9975 11:48:41.416612
9976 11:48:41.416946
9977 11:48:41.419409 Starting depthcharge on Spherion...
9978 11:48:41.419826
9979 11:48:41.420162 Wipe memory regions:
9980 11:48:41.420475
9981 11:48:41.423032 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9982 11:48:41.423529 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9983 11:48:41.423935 Setting prompt string to ['asurada:']
9984 11:48:41.424320 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9985 11:48:41.424975 [0x00000040000000, 0x00000054600000)
9986 11:48:41.546425
9987 11:48:41.546989 [0x00000054660000, 0x00000080000000)
9988 11:48:41.805853
9989 11:48:41.806473 [0x000000821a7280, 0x000000ffe64000)
9990 11:48:42.550882
9991 11:48:42.553906 [0x00000100000000, 0x00000240000000)
9992 11:48:44.440927
9993 11:48:44.444201 Initializing XHCI USB controller at 0x11200000.
9994 11:48:45.481714
9995 11:48:45.485050 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9996 11:48:45.485473
9997 11:48:45.485805
9998 11:48:45.486115
9999 11:48:45.486886 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10001 11:48:45.588065 asurada: tftpboot 192.168.201.1 12074051/tftp-deploy-i2r_xse5/kernel/image.itb 12074051/tftp-deploy-i2r_xse5/kernel/cmdline
10002 11:48:45.588667 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10003 11:48:45.589091 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10004 11:48:45.594354 tftpboot 192.168.201.1 12074051/tftp-deploy-i2r_xse5/kernel/image.itp-deploy-i2r_xse5/kernel/cmdline
10005 11:48:45.594786
10006 11:48:45.595133 Waiting for link
10007 11:48:45.754550
10008 11:48:45.755068 R8152: Initializing
10009 11:48:45.755407
10010 11:48:45.757357 Version 6 (ocp_data = 5c30)
10011 11:48:45.757777
10012 11:48:45.760661 R8152: Done initializing
10013 11:48:45.761218
10014 11:48:45.761563 Adding net device
10015 11:48:47.723400
10016 11:48:47.723959 done.
10017 11:48:47.724631
10018 11:48:47.725344 MAC: 00:24:32:30:7c:7b
10019 11:48:47.725997
10020 11:48:47.726874 Sending DHCP discover... done.
10021 11:48:47.727254
10022 11:48:47.729503 Waiting for reply... done.
10023 11:48:47.730059
10024 11:48:47.732834 Sending DHCP request... done.
10025 11:48:47.733471
10026 11:48:47.739066 Waiting for reply... done.
10027 11:48:47.739483
10028 11:48:47.739815 My ip is 192.168.201.14
10029 11:48:47.740126
10030 11:48:47.742152 The DHCP server ip is 192.168.201.1
10031 11:48:47.742609
10032 11:48:47.749488 TFTP server IP predefined by user: 192.168.201.1
10033 11:48:47.749904
10034 11:48:47.755564 Bootfile predefined by user: 12074051/tftp-deploy-i2r_xse5/kernel/image.itb
10035 11:48:47.755984
10036 11:48:47.758730 Sending tftp read request... done.
10037 11:48:47.759144
10038 11:48:47.765188 Waiting for the transfer...
10039 11:48:47.765709
10040 11:48:48.455268 00000000 ################################################################
10041 11:48:48.455791
10042 11:48:49.143408 00080000 ################################################################
10043 11:48:49.143931
10044 11:48:49.836632 00100000 ################################################################
10045 11:48:49.837207
10046 11:48:50.516478 00180000 ################################################################
10047 11:48:50.516986
10048 11:48:51.225219 00200000 ################################################################
10049 11:48:51.225743
10050 11:48:51.932769 00280000 ################################################################
10051 11:48:51.933305
10052 11:48:52.652931 00300000 ################################################################
10053 11:48:52.653517
10054 11:48:53.338877 00380000 ################################################################
10055 11:48:53.339384
10056 11:48:54.020777 00400000 ################################################################
10057 11:48:54.020923
10058 11:48:54.663237 00480000 ################################################################
10059 11:48:54.663782
10060 11:48:55.374327 00500000 ################################################################
10061 11:48:55.374914
10062 11:48:56.101873 00580000 ################################################################
10063 11:48:56.102503
10064 11:48:56.823786 00600000 ################################################################
10065 11:48:56.824355
10066 11:48:57.536836 00680000 ################################################################
10067 11:48:57.537363
10068 11:48:58.252923 00700000 ################################################################
10069 11:48:58.253452
10070 11:48:58.965965 00780000 ################################################################
10071 11:48:58.966520
10072 11:48:59.691088 00800000 ################################################################
10073 11:48:59.691646
10074 11:49:00.412462 00880000 ################################################################
10075 11:49:00.412995
10076 11:49:01.129148 00900000 ################################################################
10077 11:49:01.129774
10078 11:49:01.850456 00980000 ################################################################
10079 11:49:01.851004
10080 11:49:02.593772 00a00000 ################################################################
10081 11:49:02.594389
10082 11:49:03.317512 00a80000 ################################################################
10083 11:49:03.318075
10084 11:49:04.035715 00b00000 ################################################################
10085 11:49:04.036231
10086 11:49:04.736444 00b80000 ################################################################
10087 11:49:04.736975
10088 11:49:05.455079 00c00000 ################################################################
10089 11:49:05.455770
10090 11:49:06.159192 00c80000 ################################################################
10091 11:49:06.159743
10092 11:49:06.863139 00d00000 ################################################################
10093 11:49:06.863651
10094 11:49:07.565436 00d80000 ################################################################
10095 11:49:07.565986
10096 11:49:08.283176 00e00000 ################################################################
10097 11:49:08.283689
10098 11:49:09.001706 00e80000 ################################################################
10099 11:49:09.002233
10100 11:49:09.719983 00f00000 ################################################################
10101 11:49:09.720510
10102 11:49:10.422792 00f80000 ################################################################
10103 11:49:10.423327
10104 11:49:11.159933 01000000 ################################################################
10105 11:49:11.160466
10106 11:49:11.884860 01080000 ################################################################
10107 11:49:11.885371
10108 11:49:12.596706 01100000 ################################################################
10109 11:49:12.597213
10110 11:49:13.286357 01180000 ################################################################
10111 11:49:13.286861
10112 11:49:14.011091 01200000 ################################################################
10113 11:49:14.011621
10114 11:49:14.737335 01280000 ################################################################
10115 11:49:14.737927
10116 11:49:15.446413 01300000 ################################################################
10117 11:49:15.446938
10118 11:49:16.147865 01380000 ################################################################
10119 11:49:16.148483
10120 11:49:16.849317 01400000 ################################################################
10121 11:49:16.849847
10122 11:49:17.541360 01480000 ################################################################
10123 11:49:17.541878
10124 11:49:18.227645 01500000 ################################################################
10125 11:49:18.228185
10126 11:49:18.920857 01580000 ################################################################
10127 11:49:18.921391
10128 11:49:19.646419 01600000 ################################################################
10129 11:49:19.646969
10130 11:49:20.353121 01680000 ################################################################
10131 11:49:20.353637
10132 11:49:21.020610 01700000 ################################################################
10133 11:49:21.021122
10134 11:49:21.715781 01780000 ################################################################
10135 11:49:21.716317
10136 11:49:22.423735 01800000 ################################################################
10137 11:49:22.424370
10138 11:49:23.138141 01880000 ################################################################
10139 11:49:23.138709
10140 11:49:23.856230 01900000 ################################################################
10141 11:49:23.856743
10142 11:49:24.548763 01980000 ################################################################
10143 11:49:24.549290
10144 11:49:25.257839 01a00000 ################################################################
10145 11:49:25.258417
10146 11:49:25.963374 01a80000 ################################################################
10147 11:49:25.963885
10148 11:49:26.685704 01b00000 ################################################################
10149 11:49:26.686228
10150 11:49:27.422903 01b80000 ################################################################
10151 11:49:27.423473
10152 11:49:28.136434 01c00000 ################################################################
10153 11:49:28.136967
10154 11:49:28.838061 01c80000 ################################################################
10155 11:49:28.838628
10156 11:49:29.551303 01d00000 ################################################################
10157 11:49:29.551817
10158 11:49:30.254822 01d80000 ################################################################
10159 11:49:30.255347
10160 11:49:30.953007 01e00000 ################################################################
10161 11:49:30.953530
10162 11:49:31.689927 01e80000 ################################################################
10163 11:49:31.690490
10164 11:49:32.394243 01f00000 ################################################################
10165 11:49:32.394815
10166 11:49:33.099320 01f80000 ################################################################
10167 11:49:33.099873
10168 11:49:33.807073 02000000 ################################################################
10169 11:49:33.807584
10170 11:49:34.514669 02080000 ################################################################
10171 11:49:34.515245
10172 11:49:35.232681 02100000 ################################################################
10173 11:49:35.233226
10174 11:49:35.933417 02180000 ################################################################
10175 11:49:35.933957
10176 11:49:36.632805 02200000 ################################################################
10177 11:49:36.633318
10178 11:49:37.322038 02280000 ################################################################
10179 11:49:37.322586
10180 11:49:38.017523 02300000 ################################################################
10181 11:49:38.018049
10182 11:49:38.713426 02380000 ################################################################
10183 11:49:38.713972
10184 11:49:39.400681 02400000 ################################################################
10185 11:49:39.401220
10186 11:49:40.099547 02480000 ################################################################
10187 11:49:40.100094
10188 11:49:40.792638 02500000 ################################################################
10189 11:49:40.793148
10190 11:49:41.489426 02580000 ################################################################
10191 11:49:41.489954
10192 11:49:42.209806 02600000 ################################################################
10193 11:49:42.210377
10194 11:49:42.921435 02680000 ################################################################
10195 11:49:42.921950
10196 11:49:43.636027 02700000 ################################################################
10197 11:49:43.636545
10198 11:49:44.331185 02780000 ################################################################
10199 11:49:44.331707
10200 11:49:45.020224 02800000 ################################################################
10201 11:49:45.020806
10202 11:49:45.708251 02880000 ################################################################
10203 11:49:45.708758
10204 11:49:46.402817 02900000 ################################################################
10205 11:49:46.403341
10206 11:49:47.124027 02980000 ################################################################
10207 11:49:47.124531
10208 11:49:47.823354 02a00000 ################################################################
10209 11:49:47.823503
10210 11:49:48.509336 02a80000 ################################################################
10211 11:49:48.509864
10212 11:49:49.193734 02b00000 ################################################################
10213 11:49:49.193884
10214 11:49:49.811989 02b80000 ################################################################
10215 11:49:49.812510
10216 11:49:50.506510 02c00000 ################################################################
10217 11:49:50.507049
10218 11:49:51.185777 02c80000 ################################################################
10219 11:49:51.186382
10220 11:49:51.883030 02d00000 ################################################################
10221 11:49:51.883547
10222 11:49:52.598309 02d80000 ################################################################
10223 11:49:52.598813
10224 11:49:53.318111 02e00000 ################################################################
10225 11:49:53.318685
10226 11:49:54.028258 02e80000 ################################################################
10227 11:49:54.028794
10228 11:49:54.716913 02f00000 ################################################################
10229 11:49:54.717428
10230 11:49:55.393632 02f80000 ################################################################
10231 11:49:55.394159
10232 11:49:56.074859 03000000 ################################################################
10233 11:49:56.075513
10234 11:49:56.799365 03080000 ################################################################
10235 11:49:56.799896
10236 11:49:57.493352 03100000 ################################################################
10237 11:49:57.493927
10238 11:49:58.225297 03180000 ################################################################
10239 11:49:58.225823
10240 11:49:58.906298 03200000 ################################################################
10241 11:49:58.906816
10242 11:49:59.583945 03280000 ################################################################
10243 11:49:59.584460
10244 11:50:00.266372 03300000 ################################################################
10245 11:50:00.266904
10246 11:50:00.936368 03380000 ################################################################
10247 11:50:00.936911
10248 11:50:01.565457 03400000 ################################################################
10249 11:50:01.565608
10250 11:50:02.216603 03480000 ################################################################
10251 11:50:02.217130
10252 11:50:02.908069 03500000 ################################################################
10253 11:50:02.908596
10254 11:50:03.617553 03580000 ################################################################
10255 11:50:03.618074
10256 11:50:04.307025 03600000 ################################################################
10257 11:50:04.307550
10258 11:50:05.016972 03680000 ################################################################
10259 11:50:05.017516
10260 11:50:05.734640 03700000 ################################################################
10261 11:50:05.735150
10262 11:50:06.455955 03780000 ################################################################
10263 11:50:06.456495
10264 11:50:07.174419 03800000 ################################################################
10265 11:50:07.174932
10266 11:50:07.874615 03880000 ################################################################
10267 11:50:07.875123
10268 11:50:08.554494 03900000 ################################################################
10269 11:50:08.555005
10270 11:50:09.236034 03980000 ################################################################
10271 11:50:09.236540
10272 11:50:09.955252 03a00000 ################################################################
10273 11:50:09.955839
10274 11:50:10.665698 03a80000 ################################################################
10275 11:50:10.666209
10276 11:50:11.361364 03b00000 ################################################################
10277 11:50:11.361872
10278 11:50:12.073952 03b80000 ################################################################
10279 11:50:12.074516
10280 11:50:12.777511 03c00000 ################################################################
10281 11:50:12.778060
10282 11:50:13.494243 03c80000 ################################################################
10283 11:50:13.494814
10284 11:50:14.181462 03d00000 ################################################################
10285 11:50:14.181973
10286 11:50:14.864455 03d80000 ################################################################
10287 11:50:14.864967
10288 11:50:15.595686 03e00000 ################################################################
10289 11:50:15.596209
10290 11:50:16.312807 03e80000 ################################################################
10291 11:50:16.313329
10292 11:50:17.027029 03f00000 ################################################################
10293 11:50:17.027560
10294 11:50:17.720331 03f80000 ################################################################
10295 11:50:17.721037
10296 11:50:18.272727 04000000 #################################################### done.
10297 11:50:18.273232
10298 11:50:18.275210 The bootfile was 67530522 bytes long.
10299 11:50:18.275624
10300 11:50:18.278826 Sending tftp read request... done.
10301 11:50:18.279237
10302 11:50:18.282929 Waiting for the transfer...
10303 11:50:18.283339
10304 11:50:18.283662 00000000 # done.
10305 11:50:18.283978
10306 11:50:18.288990 Command line loaded dynamically from TFTP file: 12074051/tftp-deploy-i2r_xse5/kernel/cmdline
10307 11:50:18.292597
10308 11:50:18.305917 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 11:50:18.306461
10310 11:50:18.306791 Loading FIT.
10311 11:50:18.307095
10312 11:50:18.309282 Image ramdisk-1 has 56432964 bytes.
10313 11:50:18.309689
10314 11:50:18.312407 Image fdt-1 has 47278 bytes.
10315 11:50:18.312945
10316 11:50:18.315644 Image kernel-1 has 11048246 bytes.
10317 11:50:18.316070
10318 11:50:18.321940 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 11:50:18.322498
10320 11:50:18.342204 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 11:50:18.342776
10322 11:50:18.345615 Choosing best match conf-1 for compat google,spherion-rev2.
10323 11:50:18.350960
10324 11:50:18.354821 Connected to device vid:did:rid of 1ae0:0028:00
10325 11:50:18.361629
10326 11:50:18.365458 tpm_get_response: command 0x17b, return code 0x0
10327 11:50:18.365970
10328 11:50:18.368618 ec_init: CrosEC protocol v3 supported (256, 248)
10329 11:50:18.372374
10330 11:50:18.376110 tpm_cleanup: add release locality here.
10331 11:50:18.376639
10332 11:50:18.376981 Shutting down all USB controllers.
10333 11:50:18.378828
10334 11:50:18.379240 Removing current net device
10335 11:50:18.379574
10336 11:50:18.386194 Exiting depthcharge with code 4 at timestamp: 126190403
10337 11:50:18.386646
10338 11:50:18.389508 LZMA decompressing kernel-1 to 0x821a6718
10339 11:50:18.390025
10340 11:50:18.392032 LZMA decompressing kernel-1 to 0x40000000
10341 11:50:19.781328
10342 11:50:19.781875 jumping to kernel
10343 11:50:19.784335 end: 2.2.4 bootloader-commands (duration 00:01:38) [common]
10344 11:50:19.784880 start: 2.2.5 auto-login-action (timeout 00:02:47) [common]
10345 11:50:19.785294 Setting prompt string to ['Linux version [0-9]']
10346 11:50:19.785684 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 11:50:19.786065 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 11:50:19.862783
10349 11:50:19.866312 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 11:50:19.869719 start: 2.2.5.1 login-action (timeout 00:02:47) [common]
10351 11:50:19.870226 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 11:50:19.870664 Setting prompt string to []
10353 11:50:19.871086 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 11:50:19.871497 Using line separator: #'\n'#
10355 11:50:19.871839 No login prompt set.
10356 11:50:19.872178 Parsing kernel messages
10357 11:50:19.872592 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 11:50:19.873171 [login-action] Waiting for messages, (timeout 00:02:47)
10359 11:50:19.889129 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10360 11:50:19.892198 [ 0.000000] random: crng init done
10361 11:50:19.899017 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10362 11:50:19.902162 [ 0.000000] efi: UEFI not found.
10363 11:50:19.908942 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10364 11:50:19.918609 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10365 11:50:19.925241 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10366 11:50:19.935236 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10367 11:50:19.941970 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10368 11:50:19.948438 [ 0.000000] printk: bootconsole [mtk8250] enabled
10369 11:50:19.955323 [ 0.000000] NUMA: No NUMA configuration found
10370 11:50:19.961976 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10371 11:50:19.965452 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10372 11:50:19.968466 [ 0.000000] Zone ranges:
10373 11:50:19.974817 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10374 11:50:19.978192 [ 0.000000] DMA32 empty
10375 11:50:19.984899 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10376 11:50:19.988275 [ 0.000000] Movable zone start for each node
10377 11:50:19.991637 [ 0.000000] Early memory node ranges
10378 11:50:19.998194 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10379 11:50:20.004929 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10380 11:50:20.011399 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10381 11:50:20.017804 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10382 11:50:20.024335 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10383 11:50:20.031153 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10384 11:50:20.087509 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10385 11:50:20.094358 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10386 11:50:20.100830 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10387 11:50:20.103669 [ 0.000000] psci: probing for conduit method from DT.
10388 11:50:20.110532 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10389 11:50:20.113434 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10390 11:50:20.120822 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10391 11:50:20.124211 [ 0.000000] psci: SMC Calling Convention v1.2
10392 11:50:20.130042 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10393 11:50:20.133321 [ 0.000000] Detected VIPT I-cache on CPU0
10394 11:50:20.139700 [ 0.000000] CPU features: detected: GIC system register CPU interface
10395 11:50:20.146779 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10396 11:50:20.154055 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10397 11:50:20.160171 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10398 11:50:20.169833 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10399 11:50:20.176557 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10400 11:50:20.179440 [ 0.000000] alternatives: applying boot alternatives
10401 11:50:20.186532 [ 0.000000] Fallback order for Node 0: 0
10402 11:50:20.192715 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10403 11:50:20.196151 [ 0.000000] Policy zone: Normal
10404 11:50:20.209809 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10405 11:50:20.219250 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10406 11:50:20.232689 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10407 11:50:20.241854 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10408 11:50:20.248692 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10409 11:50:20.251466 <6>[ 0.000000] software IO TLB: area num 8.
10410 11:50:20.308825 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10411 11:50:20.457820 <6>[ 0.000000] Memory: 7914504K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 438264K reserved, 32768K cma-reserved)
10412 11:50:20.464919 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10413 11:50:20.471256 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10414 11:50:20.474395 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10415 11:50:20.481574 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10416 11:50:20.487802 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10417 11:50:20.491198 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10418 11:50:20.500576 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10419 11:50:20.507317 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10420 11:50:20.513720 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10421 11:50:20.520345 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10422 11:50:20.524757 <6>[ 0.000000] GICv3: 608 SPIs implemented
10423 11:50:20.526591 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10424 11:50:20.534105 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10425 11:50:20.537146 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10426 11:50:20.543089 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10427 11:50:20.556745 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10428 11:50:20.569424 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10429 11:50:20.575977 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10430 11:50:20.584026 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10431 11:50:20.597936 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10432 11:50:20.604447 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10433 11:50:20.611472 <6>[ 0.009208] Console: colour dummy device 80x25
10434 11:50:20.620862 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10435 11:50:20.627952 <6>[ 0.024375] pid_max: default: 32768 minimum: 301
10436 11:50:20.630693 <6>[ 0.029247] LSM: Security Framework initializing
10437 11:50:20.637170 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10438 11:50:20.646842 <6>[ 0.041998] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 11:50:20.657546 <6>[ 0.051456] cblist_init_generic: Setting adjustable number of callback queues.
10440 11:50:20.660493 <6>[ 0.058899] cblist_init_generic: Setting shift to 3 and lim to 1.
10441 11:50:20.670130 <6>[ 0.065238] cblist_init_generic: Setting adjustable number of callback queues.
10442 11:50:20.676694 <6>[ 0.072711] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 11:50:20.679770 <6>[ 0.079108] rcu: Hierarchical SRCU implementation.
10444 11:50:20.686691 <6>[ 0.084123] rcu: Max phase no-delay instances is 1000.
10445 11:50:20.693088 <6>[ 0.091173] EFI services will not be available.
10446 11:50:20.696863 <6>[ 0.096120] smp: Bringing up secondary CPUs ...
10447 11:50:20.704740 <6>[ 0.101166] Detected VIPT I-cache on CPU1
10448 11:50:20.711624 <6>[ 0.101238] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10449 11:50:20.718907 <6>[ 0.101270] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10450 11:50:20.721596 <6>[ 0.101602] Detected VIPT I-cache on CPU2
10451 11:50:20.731352 <6>[ 0.101650] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10452 11:50:20.738579 <6>[ 0.101665] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10453 11:50:20.741324 <6>[ 0.101919] Detected VIPT I-cache on CPU3
10454 11:50:20.747605 <6>[ 0.101964] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10455 11:50:20.754436 <6>[ 0.101978] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10456 11:50:20.760918 <6>[ 0.102282] CPU features: detected: Spectre-v4
10457 11:50:20.764205 <6>[ 0.102288] CPU features: detected: Spectre-BHB
10458 11:50:20.767190 <6>[ 0.102293] Detected PIPT I-cache on CPU4
10459 11:50:20.774044 <6>[ 0.102350] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10460 11:50:20.783714 <6>[ 0.102366] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10461 11:50:20.786971 <6>[ 0.102658] Detected PIPT I-cache on CPU5
10462 11:50:20.793792 <6>[ 0.102721] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10463 11:50:20.801071 <6>[ 0.102737] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10464 11:50:20.803681 <6>[ 0.103019] Detected PIPT I-cache on CPU6
10465 11:50:20.813653 <6>[ 0.103082] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10466 11:50:20.820607 <6>[ 0.103098] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10467 11:50:20.824621 <6>[ 0.103394] Detected PIPT I-cache on CPU7
10468 11:50:20.830348 <6>[ 0.103458] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10469 11:50:20.836791 <6>[ 0.103474] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10470 11:50:20.839759 <6>[ 0.103522] smp: Brought up 1 node, 8 CPUs
10471 11:50:20.847682 <6>[ 0.244761] SMP: Total of 8 processors activated.
10472 11:50:20.853618 <6>[ 0.249682] CPU features: detected: 32-bit EL0 Support
10473 11:50:20.859709 <6>[ 0.255045] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10474 11:50:20.866213 <6>[ 0.263899] CPU features: detected: Common not Private translations
10475 11:50:20.873679 <6>[ 0.270415] CPU features: detected: CRC32 instructions
10476 11:50:20.879799 <6>[ 0.275766] CPU features: detected: RCpc load-acquire (LDAPR)
10477 11:50:20.882948 <6>[ 0.281725] CPU features: detected: LSE atomic instructions
10478 11:50:20.890470 <6>[ 0.287507] CPU features: detected: Privileged Access Never
10479 11:50:20.895960 <6>[ 0.293322] CPU features: detected: RAS Extension Support
10480 11:50:20.902644 <6>[ 0.298931] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10481 11:50:20.905912 <6>[ 0.306149] CPU: All CPU(s) started at EL2
10482 11:50:20.912464 <6>[ 0.310466] alternatives: applying system-wide alternatives
10483 11:50:20.922637 <6>[ 0.321193] devtmpfs: initialized
10484 11:50:20.935186 <6>[ 0.330207] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10485 11:50:20.945248 <6>[ 0.340169] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10486 11:50:20.952139 <6>[ 0.348422] pinctrl core: initialized pinctrl subsystem
10487 11:50:20.955386 <6>[ 0.355095] DMI not present or invalid.
10488 11:50:20.961734 <6>[ 0.359510] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10489 11:50:20.971653 <6>[ 0.366356] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10490 11:50:20.978297 <6>[ 0.373934] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10491 11:50:20.987977 <6>[ 0.382162] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10492 11:50:20.991781 <6>[ 0.390406] audit: initializing netlink subsys (disabled)
10493 11:50:21.001411 <5>[ 0.396099] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10494 11:50:21.007740 <6>[ 0.396797] thermal_sys: Registered thermal governor 'step_wise'
10495 11:50:21.014724 <6>[ 0.404068] thermal_sys: Registered thermal governor 'power_allocator'
10496 11:50:21.017673 <6>[ 0.410325] cpuidle: using governor menu
10497 11:50:21.024453 <6>[ 0.421290] NET: Registered PF_QIPCRTR protocol family
10498 11:50:21.030683 <6>[ 0.426776] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10499 11:50:21.037559 <6>[ 0.433875] ASID allocator initialised with 32768 entries
10500 11:50:21.040886 <6>[ 0.440444] Serial: AMBA PL011 UART driver
10501 11:50:21.050915 <4>[ 0.449253] Trying to register duplicate clock ID: 134
10502 11:50:21.107615 <6>[ 0.509028] KASLR enabled
10503 11:50:21.122151 <6>[ 0.516758] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10504 11:50:21.128130 <6>[ 0.523772] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10505 11:50:21.134674 <6>[ 0.530261] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10506 11:50:21.141350 <6>[ 0.537269] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10507 11:50:21.147956 <6>[ 0.543757] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10508 11:50:21.154745 <6>[ 0.550764] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10509 11:50:21.161230 <6>[ 0.557254] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10510 11:50:21.167941 <6>[ 0.564257] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10511 11:50:21.171605 <6>[ 0.571766] ACPI: Interpreter disabled.
10512 11:50:21.179374 <6>[ 0.578174] iommu: Default domain type: Translated
10513 11:50:21.186055 <6>[ 0.583288] iommu: DMA domain TLB invalidation policy: strict mode
10514 11:50:21.189562 <5>[ 0.589942] SCSI subsystem initialized
10515 11:50:21.196072 <6>[ 0.594111] usbcore: registered new interface driver usbfs
10516 11:50:21.202993 <6>[ 0.599843] usbcore: registered new interface driver hub
10517 11:50:21.205947 <6>[ 0.605395] usbcore: registered new device driver usb
10518 11:50:21.213100 <6>[ 0.611493] pps_core: LinuxPPS API ver. 1 registered
10519 11:50:21.222513 <6>[ 0.616687] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10520 11:50:21.226367 <6>[ 0.626036] PTP clock support registered
10521 11:50:21.229552 <6>[ 0.630279] EDAC MC: Ver: 3.0.0
10522 11:50:21.237513 <6>[ 0.635415] FPGA manager framework
10523 11:50:21.244116 <6>[ 0.639092] Advanced Linux Sound Architecture Driver Initialized.
10524 11:50:21.247042 <6>[ 0.645864] vgaarb: loaded
10525 11:50:21.253163 <6>[ 0.649037] clocksource: Switched to clocksource arch_sys_counter
10526 11:50:21.256580 <5>[ 0.655469] VFS: Disk quotas dquot_6.6.0
10527 11:50:21.263348 <6>[ 0.659655] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10528 11:50:21.266297 <6>[ 0.666843] pnp: PnP ACPI: disabled
10529 11:50:21.275510 <6>[ 0.673500] NET: Registered PF_INET protocol family
10530 11:50:21.284997 <6>[ 0.679087] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10531 11:50:21.296337 <6>[ 0.691372] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10532 11:50:21.305747 <6>[ 0.700185] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10533 11:50:21.312958 <6>[ 0.708157] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10534 11:50:21.322416 <6>[ 0.716855] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10535 11:50:21.328680 <6>[ 0.726603] TCP: Hash tables configured (established 65536 bind 65536)
10536 11:50:21.335273 <6>[ 0.733462] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 11:50:21.345835 <6>[ 0.740664] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 11:50:21.352313 <6>[ 0.748357] NET: Registered PF_UNIX/PF_LOCAL protocol family
10539 11:50:21.358325 <6>[ 0.754526] RPC: Registered named UNIX socket transport module.
10540 11:50:21.362429 <6>[ 0.760681] RPC: Registered udp transport module.
10541 11:50:21.368758 <6>[ 0.765616] RPC: Registered tcp transport module.
10542 11:50:21.375143 <6>[ 0.770546] RPC: Registered tcp NFSv4.1 backchannel transport module.
10543 11:50:21.378210 <6>[ 0.777214] PCI: CLS 0 bytes, default 64
10544 11:50:21.381639 <6>[ 0.781600] Unpacking initramfs...
10545 11:50:21.399019 <6>[ 0.793632] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10546 11:50:21.409304 <6>[ 0.802249] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10547 11:50:21.411911 <6>[ 0.811095] kvm [1]: IPA Size Limit: 40 bits
10548 11:50:21.418315 <6>[ 0.815620] kvm [1]: GICv3: no GICV resource entry
10549 11:50:21.421742 <6>[ 0.820642] kvm [1]: disabling GICv2 emulation
10550 11:50:21.428173 <6>[ 0.825328] kvm [1]: GIC system register CPU interface enabled
10551 11:50:21.435242 <6>[ 0.833051] kvm [1]: vgic interrupt IRQ18
10552 11:50:21.438703 <6>[ 0.837429] kvm [1]: VHE mode initialized successfully
10553 11:50:21.445172 <5>[ 0.843876] Initialise system trusted keyrings
10554 11:50:21.451962 <6>[ 0.848649] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10555 11:50:21.461208 <6>[ 0.858701] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10556 11:50:21.466643 <5>[ 0.865117] NFS: Registering the id_resolver key type
10557 11:50:21.470089 <5>[ 0.870427] Key type id_resolver registered
10558 11:50:21.476577 <5>[ 0.874842] Key type id_legacy registered
10559 11:50:21.483065 <6>[ 0.879122] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10560 11:50:21.489408 <6>[ 0.886045] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10561 11:50:21.496264 <6>[ 0.893795] 9p: Installing v9fs 9p2000 file system support
10562 11:50:21.532670 <5>[ 0.931154] Key type asymmetric registered
10563 11:50:21.535758 <5>[ 0.935489] Asymmetric key parser 'x509' registered
10564 11:50:21.546022 <6>[ 0.940635] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10565 11:50:21.549431 <6>[ 0.948252] io scheduler mq-deadline registered
10566 11:50:21.552653 <6>[ 0.953013] io scheduler kyber registered
10567 11:50:21.571759 <6>[ 0.970174] EINJ: ACPI disabled.
10568 11:50:21.605283 <4>[ 0.996395] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 11:50:21.614046 <4>[ 1.007052] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 11:50:21.629456 <6>[ 1.027882] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10571 11:50:21.637990 <6>[ 1.035990] printk: console [ttyS0] disabled
10572 11:50:21.666010 <6>[ 1.060651] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10573 11:50:21.672199 <6>[ 1.070119] printk: console [ttyS0] enabled
10574 11:50:21.676193 <6>[ 1.070119] printk: console [ttyS0] enabled
10575 11:50:21.682497 <6>[ 1.079015] printk: bootconsole [mtk8250] disabled
10576 11:50:21.685336 <6>[ 1.079015] printk: bootconsole [mtk8250] disabled
10577 11:50:21.692301 <6>[ 1.090059] SuperH (H)SCI(F) driver initialized
10578 11:50:21.695710 <6>[ 1.095334] msm_serial: driver initialized
10579 11:50:21.709352 <6>[ 1.104293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10580 11:50:21.718746 <6>[ 1.112837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10581 11:50:21.725921 <6>[ 1.121383] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10582 11:50:21.736124 <6>[ 1.130012] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10583 11:50:21.742939 <6>[ 1.138720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10584 11:50:21.752442 <6>[ 1.147435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10585 11:50:21.762225 <6>[ 1.155977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10586 11:50:21.768964 <6>[ 1.164773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10587 11:50:21.779053 <6>[ 1.173319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10588 11:50:21.790315 <6>[ 1.188584] loop: module loaded
10589 11:50:21.797042 <6>[ 1.194606] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10590 11:50:21.820307 <4>[ 1.217833] mtk-pmic-keys: Failed to locate of_node [id: -1]
10591 11:50:21.826476 <6>[ 1.224587] megasas: 07.719.03.00-rc1
10592 11:50:21.835611 <6>[ 1.234198] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10593 11:50:21.846429 <6>[ 1.244411] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10594 11:50:21.862685 <6>[ 1.260936] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10595 11:50:21.919010 <6>[ 1.310720] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10596 11:50:23.777617 <6>[ 3.176184] Freeing initrd memory: 55104K
10597 11:50:23.787540 <6>[ 3.186596] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10598 11:50:23.798275 <6>[ 3.197480] tun: Universal TUN/TAP device driver, 1.6
10599 11:50:23.801743 <6>[ 3.203531] thunder_xcv, ver 1.0
10600 11:50:23.805006 <6>[ 3.207034] thunder_bgx, ver 1.0
10601 11:50:23.807925 <6>[ 3.210529] nicpf, ver 1.0
10602 11:50:23.818786 <6>[ 3.214542] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10603 11:50:23.821805 <6>[ 3.222018] hns3: Copyright (c) 2017 Huawei Corporation.
10604 11:50:23.829067 <6>[ 3.227621] hclge is initializing
10605 11:50:23.832186 <6>[ 3.231197] e1000: Intel(R) PRO/1000 Network Driver
10606 11:50:23.839385 <6>[ 3.236327] e1000: Copyright (c) 1999-2006 Intel Corporation.
10607 11:50:23.841851 <6>[ 3.242342] e1000e: Intel(R) PRO/1000 Network Driver
10608 11:50:23.849221 <6>[ 3.247558] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10609 11:50:23.855746 <6>[ 3.253742] igb: Intel(R) Gigabit Ethernet Network Driver
10610 11:50:23.862330 <6>[ 3.259392] igb: Copyright (c) 2007-2014 Intel Corporation.
10611 11:50:23.868865 <6>[ 3.265227] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10612 11:50:23.875755 <6>[ 3.271745] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10613 11:50:23.879904 <6>[ 3.278215] sky2: driver version 1.30
10614 11:50:23.885813 <6>[ 3.283211] VFIO - User Level meta-driver version: 0.3
10615 11:50:23.892475 <6>[ 3.291472] usbcore: registered new interface driver usb-storage
10616 11:50:23.898811 <6>[ 3.297916] usbcore: registered new device driver onboard-usb-hub
10617 11:50:23.908516 <6>[ 3.307085] mt6397-rtc mt6359-rtc: registered as rtc0
10618 11:50:23.918577 <6>[ 3.312559] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:50:23 UTC (1700826623)
10619 11:50:23.921707 <6>[ 3.322163] i2c_dev: i2c /dev entries driver
10620 11:50:23.938294 <6>[ 3.333931] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10621 11:50:23.958318 <6>[ 3.356939] cpu cpu0: EM: created perf domain
10622 11:50:23.961071 <6>[ 3.361866] cpu cpu4: EM: created perf domain
10623 11:50:23.969294 <6>[ 3.367427] sdhci: Secure Digital Host Controller Interface driver
10624 11:50:23.975754 <6>[ 3.373859] sdhci: Copyright(c) Pierre Ossman
10625 11:50:23.982127 <6>[ 3.378814] Synopsys Designware Multimedia Card Interface Driver
10626 11:50:23.988946 <6>[ 3.385456] sdhci-pltfm: SDHCI platform and OF driver helper
10627 11:50:23.991796 <6>[ 3.385570] mmc0: CQHCI version 5.10
10628 11:50:23.998324 <6>[ 3.395721] ledtrig-cpu: registered to indicate activity on CPUs
10629 11:50:24.004781 <6>[ 3.402754] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10630 11:50:24.011374 <6>[ 3.409811] usbcore: registered new interface driver usbhid
10631 11:50:24.014948 <6>[ 3.415636] usbhid: USB HID core driver
10632 11:50:24.021629 <6>[ 3.419824] spi_master spi0: will run message pump with realtime priority
10633 11:50:24.065945 <6>[ 3.458025] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10634 11:50:24.085872 <6>[ 3.474057] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10635 11:50:24.089114 <6>[ 3.488241] mmc0: Command Queue Engine enabled
10636 11:50:24.095552 <6>[ 3.493011] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10637 11:50:24.102317 <6>[ 3.499797] cros-ec-spi spi0.0: Chrome EC device registered
10638 11:50:24.106335 <6>[ 3.500284] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 11:50:24.117211 <6>[ 3.515871] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10640 11:50:24.124641 <6>[ 3.523197] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 11:50:24.130979 <6>[ 3.529135] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10642 11:50:24.138083 <6>[ 3.535076] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10643 11:50:24.148631 <6>[ 3.541288] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10644 11:50:24.154320 <6>[ 3.552238] NET: Registered PF_PACKET protocol family
10645 11:50:24.157565 <6>[ 3.557630] 9pnet: Installing 9P2000 support
10646 11:50:24.163996 <5>[ 3.562196] Key type dns_resolver registered
10647 11:50:24.167464 <6>[ 3.567122] registered taskstats version 1
10648 11:50:24.173944 <5>[ 3.571513] Loading compiled-in X.509 certificates
10649 11:50:24.204233 <4>[ 3.596572] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 11:50:24.215022 <4>[ 3.607498] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 11:50:24.221067 <3>[ 3.618104] debugfs: File 'uA_load' in directory '/' already present!
10652 11:50:24.227468 <3>[ 3.624817] debugfs: File 'min_uV' in directory '/' already present!
10653 11:50:24.234432 <3>[ 3.631431] debugfs: File 'max_uV' in directory '/' already present!
10654 11:50:24.241524 <3>[ 3.638042] debugfs: File 'constraint_flags' in directory '/' already present!
10655 11:50:24.253451 <3>[ 3.648249] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10656 11:50:24.265164 <6>[ 3.663910] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10657 11:50:24.271984 <6>[ 3.670767] xhci-mtk 11200000.usb: xHCI Host Controller
10658 11:50:24.278988 <6>[ 3.676273] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10659 11:50:24.288918 <6>[ 3.684213] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10660 11:50:24.295368 <6>[ 3.693650] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10661 11:50:24.301921 <6>[ 3.699728] xhci-mtk 11200000.usb: xHCI Host Controller
10662 11:50:24.309215 <6>[ 3.705210] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10663 11:50:24.314882 <6>[ 3.712857] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10664 11:50:24.321966 <6>[ 3.720650] hub 1-0:1.0: USB hub found
10665 11:50:24.325274 <6>[ 3.724674] hub 1-0:1.0: 1 port detected
10666 11:50:24.335373 <6>[ 3.728959] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10667 11:50:24.338057 <6>[ 3.737651] hub 2-0:1.0: USB hub found
10668 11:50:24.342140 <6>[ 3.741671] hub 2-0:1.0: 1 port detected
10669 11:50:24.349538 <6>[ 3.748498] mtk-msdc 11f70000.mmc: Got CD GPIO
10670 11:50:24.360284 <6>[ 3.755903] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10671 11:50:24.366953 <6>[ 3.763939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10672 11:50:24.377011 <4>[ 3.771844] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10673 11:50:24.386672 <6>[ 3.781375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10674 11:50:24.394402 <6>[ 3.789452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10675 11:50:24.402946 <6>[ 3.797568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10676 11:50:24.409841 <6>[ 3.805487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10677 11:50:24.416394 <6>[ 3.813363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10678 11:50:24.426517 <6>[ 3.821200] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10679 11:50:24.435924 <6>[ 3.831726] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10680 11:50:24.445957 <6>[ 3.840086] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10681 11:50:24.453240 <6>[ 3.848460] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10682 11:50:24.462332 <6>[ 3.856803] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10683 11:50:24.468946 <6>[ 3.865154] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10684 11:50:24.479548 <6>[ 3.873494] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10685 11:50:24.485388 <6>[ 3.881847] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10686 11:50:24.495489 <6>[ 3.890188] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10687 11:50:24.502173 <6>[ 3.898536] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10688 11:50:24.511802 <6>[ 3.906876] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10689 11:50:24.519048 <6>[ 3.915224] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10690 11:50:24.528285 <6>[ 3.923564] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10691 11:50:24.535784 <6>[ 3.931902] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10692 11:50:24.545710 <6>[ 3.940240] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10693 11:50:24.551703 <6>[ 3.948578] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10694 11:50:24.558284 <6>[ 3.957343] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10695 11:50:24.565780 <6>[ 3.964524] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10696 11:50:24.572122 <6>[ 3.971281] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10697 11:50:24.583034 <6>[ 3.978038] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10698 11:50:24.589098 <6>[ 3.984983] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10699 11:50:24.595498 <6>[ 3.991846] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10700 11:50:24.605670 <6>[ 4.000974] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10701 11:50:24.615446 <6>[ 4.010092] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10702 11:50:24.625078 <6>[ 4.019386] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10703 11:50:24.635234 <6>[ 4.028899] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10704 11:50:24.645149 <6>[ 4.038460] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10705 11:50:24.651481 <6>[ 4.047586] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10706 11:50:24.661681 <6>[ 4.057054] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10707 11:50:24.671271 <6>[ 4.066172] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10708 11:50:24.680936 <6>[ 4.075468] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10709 11:50:24.691136 <6>[ 4.085630] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10710 11:50:24.701320 <6>[ 4.097233] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10711 11:50:24.769021 <6>[ 4.165311] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10712 11:50:24.923960 <6>[ 4.323094] hub 1-1:1.0: USB hub found
10713 11:50:24.927238 <6>[ 4.327631] hub 1-1:1.0: 4 ports detected
10714 11:50:24.937323 <6>[ 4.336276] hub 1-1:1.0: USB hub found
10715 11:50:24.940086 <6>[ 4.340649] hub 1-1:1.0: 4 ports detected
10716 11:50:25.049572 <6>[ 4.445657] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10717 11:50:25.076074 <6>[ 4.475167] hub 2-1:1.0: USB hub found
10718 11:50:25.079364 <6>[ 4.479662] hub 2-1:1.0: 3 ports detected
10719 11:50:25.088530 <6>[ 4.487761] hub 2-1:1.0: USB hub found
10720 11:50:25.091809 <6>[ 4.492205] hub 2-1:1.0: 3 ports detected
10721 11:50:25.265040 <6>[ 4.661378] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10722 11:50:25.397973 <6>[ 4.797227] hub 1-1.4:1.0: USB hub found
10723 11:50:25.401145 <6>[ 4.801890] hub 1-1.4:1.0: 2 ports detected
10724 11:50:25.411033 <6>[ 4.810166] hub 1-1.4:1.0: USB hub found
10725 11:50:25.413897 <6>[ 4.814720] hub 1-1.4:1.0: 2 ports detected
10726 11:50:25.477277 <6>[ 4.873545] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10727 11:50:25.709085 <6>[ 5.105363] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10728 11:50:25.901109 <6>[ 5.297335] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10729 11:50:36.994316 <6>[ 16.398342] ALSA device list:
10730 11:50:37.001197 <6>[ 16.401630] No soundcards found.
10731 11:50:37.008983 <6>[ 16.409607] Freeing unused kernel memory: 8384K
10732 11:50:37.013248 <6>[ 16.414592] Run /init as init process
10733 11:50:37.057815 <6>[ 16.458790] NET: Registered PF_INET6 protocol family
10734 11:50:37.061427 <6>[ 16.464807] Segment Routing with IPv6
10735 11:50:37.068131 <6>[ 16.468761] In-situ OAM (IOAM) with IPv6
10736 11:50:37.102305 <30>[ 16.483188] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10737 11:50:37.106191 <30>[ 16.506937] systemd[1]: Detected architecture arm64.
10738 11:50:37.106472
10739 11:50:37.112417 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10740 11:50:37.112614
10741 11:50:37.124354 <30>[ 16.525253] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10742 11:50:37.281592 <30>[ 16.679288] systemd[1]: Queued start job for default target Graphical Interface.
10743 11:50:37.306015 <30>[ 16.706428] systemd[1]: Created slice system-getty.slice.
10744 11:50:37.312265 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10745 11:50:37.329395 <30>[ 16.729871] systemd[1]: Created slice system-modprobe.slice.
10746 11:50:37.335535 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10747 11:50:37.353262 <30>[ 16.754086] systemd[1]: Created slice system-serial\x2dgetty.slice.
10748 11:50:37.363238 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10749 11:50:37.378757 <30>[ 16.778436] systemd[1]: Created slice User and Session Slice.
10750 11:50:37.384462 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10751 11:50:37.404615 <30>[ 16.801952] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10752 11:50:37.414792 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10753 11:50:37.432638 <30>[ 16.830043] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10754 11:50:37.440280 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10755 11:50:37.464204 <30>[ 16.857836] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10756 11:50:37.470240 <30>[ 16.870086] systemd[1]: Reached target Local Encrypted Volumes.
10757 11:50:37.477492 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10758 11:50:37.493315 <30>[ 16.893817] systemd[1]: Reached target Paths.
10759 11:50:37.499786 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10760 11:50:37.512673 <30>[ 16.913375] systemd[1]: Reached target Remote File Systems.
10761 11:50:37.519138 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10762 11:50:37.532531 <30>[ 16.933299] systemd[1]: Reached target Slices.
10763 11:50:37.535747 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10764 11:50:37.553281 <30>[ 16.953321] systemd[1]: Reached target Swap.
10765 11:50:37.557626 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10766 11:50:37.576388 <30>[ 16.973808] systemd[1]: Listening on initctl Compatibility Named Pipe.
10767 11:50:37.582804 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10768 11:50:37.589585 <30>[ 16.988859] systemd[1]: Listening on Journal Audit Socket.
10769 11:50:37.596235 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10770 11:50:37.609608 <30>[ 17.009765] systemd[1]: Listening on Journal Socket (/dev/log).
10771 11:50:37.615776 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10772 11:50:37.634211 <30>[ 17.034558] systemd[1]: Listening on Journal Socket.
10773 11:50:37.640377 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10774 11:50:37.653340 <30>[ 17.053881] systemd[1]: Listening on udev Control Socket.
10775 11:50:37.659731 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10776 11:50:37.677559 <30>[ 17.078330] systemd[1]: Listening on udev Kernel Socket.
10777 11:50:37.684989 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10778 11:50:37.732945 <30>[ 17.133567] systemd[1]: Mounting Huge Pages File System...
10779 11:50:37.739484 Mounting [0;1;39mHuge Pages File System[0m...
10780 11:50:37.756413 <30>[ 17.156308] systemd[1]: Mounting POSIX Message Queue File System...
10781 11:50:37.762517 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10782 11:50:37.780813 <30>[ 17.181252] systemd[1]: Mounting Kernel Debug File System...
10783 11:50:37.787056 Mounting [0;1;39mKernel Debug File System[0m...
10784 11:50:37.804061 <30>[ 17.201511] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10785 11:50:37.817103 <30>[ 17.214624] systemd[1]: Starting Create list of static device nodes for the current kernel...
10786 11:50:37.824265 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10787 11:50:37.844498 <30>[ 17.245236] systemd[1]: Starting Load Kernel Module configfs...
10788 11:50:37.850978 Starting [0;1;39mLoad Kernel Module configfs[0m...
10789 11:50:37.868742 <30>[ 17.269117] systemd[1]: Starting Load Kernel Module drm...
10790 11:50:37.874937 Starting [0;1;39mLoad Kernel Module drm[0m...
10791 11:50:37.892087 <30>[ 17.289387] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10792 11:50:37.924698 <30>[ 17.325727] systemd[1]: Starting Journal Service...
10793 11:50:37.928868 Starting [0;1;39mJournal Service[0m...
10794 11:50:37.947466 <30>[ 17.348169] systemd[1]: Starting Load Kernel Modules...
10795 11:50:37.954096 Starting [0;1;39mLoad Kernel Modules[0m...
10796 11:50:37.976945 <30>[ 17.373949] systemd[1]: Starting Remount Root and Kernel File Systems...
10797 11:50:37.983179 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10798 11:50:38.000267 <30>[ 17.400414] systemd[1]: Starting Coldplug All udev Devices...
10799 11:50:38.006134 Starting [0;1;39mColdplug All udev Devices[0m...
10800 11:50:38.023761 <30>[ 17.424443] systemd[1]: Started Journal Service.
10801 11:50:38.030183 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10802 11:50:38.047781 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10803 11:50:38.065434 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10804 11:50:38.081838 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10805 11:50:38.101438 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10806 11:50:38.118381 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10807 11:50:38.134159 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10808 11:50:38.150578 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10809 11:50:38.169602 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10810 11:50:38.184484 See 'systemctl status systemd-remount-fs.service' for details.
10811 11:50:38.233836 Mounting [0;1;39mKernel Configuration File System[0m...
10812 11:50:38.255300 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10813 11:50:38.275151 <46>[ 17.672064] systemd-journald[187]: Received client request to flush runtime journal.
10814 11:50:38.314993 Starting [0;1;39mLoad/Save Random Seed[0m...
10815 11:50:38.337098 Starting [0;1;39mApply Kernel Variables[0m...
10816 11:50:38.359545 Starting [0;1;39mCreate System Users[0m...
10817 11:50:38.377992 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10818 11:50:38.396819 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10819 11:50:38.418039 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10820 11:50:38.434407 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10821 11:50:38.455398 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10822 11:50:38.471494 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10823 11:50:38.517027 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10824 11:50:38.538921 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10825 11:50:38.553112 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10826 11:50:38.572750 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10827 11:50:38.604983 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10828 11:50:38.629528 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10829 11:50:38.658010 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10830 11:50:38.679229 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10831 11:50:38.731298 Starting [0;1;39mNetwork Time Synchronization[0m...
10832 11:50:38.756770 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10833 11:50:38.807040 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10834 11:50:38.830942 <3>[ 18.228387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 11:50:38.837580 <3>[ 18.236623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 11:50:38.847523 <6>[ 18.244195] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10837 11:50:38.854089 <3>[ 18.245993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 11:50:38.866049 Startin<6>[ 18.264004] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10839 11:50:38.875345 g [0;1;39mLoad/<6>[ 18.271816] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10840 11:50:38.882186 Save Screen …o<6>[ 18.272486] remoteproc remoteproc0: scp is available
10841 11:50:38.892044 <3>[ 18.276163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 11:50:38.901890 f leds:white:kbd<3>[ 18.276178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 11:50:38.908552 _backlight[0m..<3>[ 18.276182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 11:50:38.918201 <3>[ 18.276187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 11:50:38.918795 .
10846 11:50:38.925006 <3>[ 18.276190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 11:50:38.934918 <6>[ 18.281854] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10848 11:50:38.944994 <3>[ 18.285437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 11:50:38.948062 <6>[ 18.288911] remoteproc remoteproc0: powering up scp
10850 11:50:38.958529 <3>[ 18.312675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 11:50:38.964836 <6>[ 18.315646] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10852 11:50:38.974407 <3>[ 18.323801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 11:50:38.977730 <6>[ 18.332164] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10854 11:50:38.987692 <3>[ 18.340784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 11:50:38.994498 <3>[ 18.359020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 11:50:39.001097 <6>[ 18.381221] mc: Linux media interface: v0.10
10857 11:50:39.008972 <6>[ 18.381679] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10858 11:50:39.014135 <4>[ 18.384493] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10859 11:50:39.024750 <3>[ 18.384529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 11:50:39.031223 <3>[ 18.384536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 11:50:39.037800 <3>[ 18.384544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 11:50:39.047254 <3>[ 18.384549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 11:50:39.053825 <3>[ 18.392811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 11:50:39.063979 <4>[ 18.411318] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10865 11:50:39.066990 <4>[ 18.411318] Fallback method does not support PEC.
10866 11:50:39.077082 <4>[ 18.418756] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10867 11:50:39.084201 <6>[ 18.425209] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10868 11:50:39.090052 <6>[ 18.455440] usbcore: registered new interface driver r8152
10869 11:50:39.093778 <6>[ 18.461104] pci_bus 0000:00: root bus resource [bus 00-ff]
10870 11:50:39.099928 <6>[ 18.475875] videodev: Linux video capture interface: v2.00
10871 11:50:39.106892 <6>[ 18.481857] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10872 11:50:39.113831 <6>[ 18.488013] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10873 11:50:39.123548 <6>[ 18.488157] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10874 11:50:39.129730 <6>[ 18.488163] remoteproc remoteproc0: remote processor scp is now up
10875 11:50:39.139781 <6>[ 18.528651] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10876 11:50:39.151179 <6>[ 18.535050] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10877 11:50:39.156647 <6>[ 18.536367] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10878 11:50:39.166905 <6>[ 18.538639] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10879 11:50:39.176768 <6>[ 18.546061] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10880 11:50:39.183133 <6>[ 18.553423] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10881 11:50:39.193515 <3>[ 18.554661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:50:39.200723 <6>[ 18.555170] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10883 11:50:39.207110 <6>[ 18.557461] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10884 11:50:39.210235 <6>[ 18.599681] Bluetooth: Core ver 2.22
10885 11:50:39.216734 <6>[ 18.599892] usbcore: registered new interface driver cdc_ether
10886 11:50:39.223534 <6>[ 18.605180] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10887 11:50:39.230413 <6>[ 18.605416] usbcore: registered new interface driver r8153_ecm
10888 11:50:39.237548 <6>[ 18.613717] NET: Registered PF_BLUETOOTH protocol family
10889 11:50:39.240999 <6>[ 18.616245] pci 0000:00:00.0: supports D1 D2
10890 11:50:39.248014 <3>[ 18.617755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 11:50:39.258689 <3>[ 18.618510] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10892 11:50:39.264846 <6>[ 18.622327] Bluetooth: HCI device and connection manager initialized
10893 11:50:39.274963 <4>[ 18.622897] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10894 11:50:39.281098 <4>[ 18.622906] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10895 11:50:39.287822 <6>[ 18.623533] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10896 11:50:39.302309 <6>[ 18.624566] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10897 11:50:39.306300 <6>[ 18.624677] usbcore: registered new interface driver uvcvideo
10898 11:50:39.312322 <6>[ 18.629756] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10899 11:50:39.318624 <6>[ 18.635790] Bluetooth: HCI socket layer initialized
10900 11:50:39.326036 <6>[ 18.635798] Bluetooth: L2CAP socket layer initialized
10901 11:50:39.329689 <6>[ 18.635814] Bluetooth: SCO socket layer initialized
10902 11:50:39.339272 <6>[ 18.642541] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10903 11:50:39.345679 <3>[ 18.652708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 11:50:39.356254 <3>[ 18.653533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10905 11:50:39.362357 <6>[ 18.654819] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10906 11:50:39.369646 <6>[ 18.655537] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10907 11:50:39.375994 <3>[ 18.665811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 11:50:39.382960 <6>[ 18.670089] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10909 11:50:39.389849 <6>[ 18.673299] r8152 2-1.3:1.0 eth0: v1.12.13
10910 11:50:39.395987 <6>[ 18.685180] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10911 11:50:39.403118 <6>[ 18.687224] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10912 11:50:39.410383 <3>[ 18.700321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 11:50:39.417423 <6>[ 18.706678] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10914 11:50:39.423692 <6>[ 18.707242] usbcore: registered new interface driver btusb
10915 11:50:39.433653 <4>[ 18.708128] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10916 11:50:39.441047 <3>[ 18.708142] Bluetooth: hci0: Failed to load firmware file (-2)
10917 11:50:39.447873 <3>[ 18.708146] Bluetooth: hci0: Failed to set up firmware (-2)
10918 11:50:39.457417 <4>[ 18.708154] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10919 11:50:39.464644 <3>[ 18.736289] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 11:50:39.471245 <6>[ 18.743440] pci 0000:01:00.0: supports D1 D2
10921 11:50:39.477887 <3>[ 18.772477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:50:39.484788 <6>[ 18.773647] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10923 11:50:39.491785 <6>[ 18.785249] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10924 11:50:39.501590 <3>[ 18.811569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:50:39.508647 <6>[ 18.816698] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10926 11:50:39.518785 <6>[ 18.915378] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10927 11:50:39.525379 <6>[ 18.915417] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10928 11:50:39.535053 [[0;32m OK [<6>[ 18.931708] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10929 11:50:39.542099 <6>[ 18.941090] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10930 11:50:39.548769 <6>[ 18.949130] pci 0000:00:00.0: PCI bridge to [bus 01]
10931 11:50:39.554807 <6>[ 18.954350] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10932 11:50:39.565221 0m] Started [0;<6>[ 18.962542] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10933 11:50:39.572075 1;39mNetwork Tim<6>[ 18.970803] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10934 11:50:39.578049 e Synchronizatio<6>[ 18.978458] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10935 11:50:39.581306 n[0m.
10936 11:50:39.604957 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <5>[ 19.002029] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10937 11:50:39.607785 Screen …s of leds:white:kbd_backlight[0m.
10938 11:50:39.622531 <5>[ 19.019662] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10939 11:50:39.628888 <4>[ 19.026630] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10940 11:50:39.635493 <6>[ 19.035561] cfg80211: failed to load regulatory.db
10941 11:50:39.642647 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10942 11:50:39.682019 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10943 11:50:39.692687 <6>[ 19.090101] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10944 11:50:39.699143 <6>[ 19.097836] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10945 11:50:39.724083 <6>[ 19.124615] mt7921e 0000:01:00.0: ASIC revision: 79610010
10946 11:50:39.830952 <4>[ 19.225099] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10947 11:50:39.838233 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10948 11:50:39.850241 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10949 11:50:39.868161 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10950 11:50:39.885285 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10951 11:50:39.904779 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10952 11:50:39.925041 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10953 11:50:39.937472 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10954 11:50:39.951808 <4>[ 19.345538] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 11:50:39.957955 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10956 11:50:39.974088 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10957 11:50:39.988528 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10958 11:50:40.008700 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10959 11:50:40.080258 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0<4>[ 19.472007] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10960 11:50:40.080994 m.
10961 11:50:40.117521 Starting [0;1;39mUser Login Management[0m...
10962 11:50:40.137279 Starting [0;1;39mPermit User Sessions[0m...
10963 11:50:40.156406 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10964 11:50:40.170147 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10965 11:50:40.191691 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10966 11:50:40.205262 <4>[ 19.598797] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 11:50:40.211456 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10968 11:50:40.229324 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10969 11:50:40.245331 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10970 11:50:40.261569 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10971 11:50:40.278249 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10972 11:50:40.293488 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10973 11:50:40.328942 <4>[ 19.722942] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 11:50:40.362806 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10975 11:50:40.397237 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10976 11:50:40.452671 <4>[ 19.846104] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 11:50:40.453172
10978 11:50:40.453505
10979 11:50:40.458472 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10980 11:50:40.458897
10981 11:50:40.461654 debian-bullseye-arm64 login: root (automatic login)
10982 11:50:40.462069
10983 11:50:40.462440
10984 11:50:40.484444 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
10985 11:50:40.484940
10986 11:50:40.489877 The programs included with the Debian GNU/Linux system are free software;
10987 11:50:40.496477 the exact distribution terms for each program are described in the
10988 11:50:40.500192 individual files in /usr/share/doc/*/copyright.
10989 11:50:40.500609
10990 11:50:40.506441 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10991 11:50:40.509725 permitted by applicable law.
10992 11:50:40.512382 Matched prompt #10: / #
10994 11:50:40.513640 Setting prompt string to ['/ #']
10995 11:50:40.514075 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10997 11:50:40.515240 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10998 11:50:40.515676 start: 2.2.6 expect-shell-connection (timeout 00:02:26) [common]
10999 11:50:40.516048 Setting prompt string to ['/ #']
11000 11:50:40.516361 Forcing a shell prompt, looking for ['/ #']
11002 11:50:40.567095 / #
11003 11:50:40.567807 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11004 11:50:40.568287 Waiting using forced prompt support (timeout 00:02:30)
11005 11:50:40.580202 <4>[ 19.973984] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 11:50:40.580705
11007 11:50:40.583586 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 11:50:40.584139 start: 2.2.7 export-device-env (timeout 00:02:26) [common]
11009 11:50:40.584614 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 11:50:40.585047 end: 2.2 depthcharge-retry (duration 00:02:34) [common]
11011 11:50:40.585474 end: 2 depthcharge-action (duration 00:02:34) [common]
11012 11:50:40.585916 start: 3 lava-test-retry (timeout 00:07:04) [common]
11013 11:50:40.586380 start: 3.1 lava-test-shell (timeout 00:07:04) [common]
11014 11:50:40.586766 Using namespace: common
11016 11:50:40.687749 / # #
11017 11:50:40.688507 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11018 11:50:40.699850 #<4>[ 20.094181] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 11:50:40.700396
11020 11:50:40.704496 Using /lava-12074051
11022 11:50:40.805614 / # export SHELL=/bin/sh
11023 11:50:40.819272 export SHELL=/bin/sh<4>[ 20.213612] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11024 11:50:40.819785
11026 11:50:40.924442 / # . /lava-12074051/environment
11027 11:50:40.939519 . /lava-12074051/environment<4>[ 20.333922] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 11:50:40.940035
11030 11:50:41.045565 / # /lava-12074051/bin/lava-test-runner /lava-12074051/0
11031 11:50:41.046129 Test shell timeout: 10s (minimum of the action and connection timeout)
11032 11:50:41.051255 /lava-12074051/bin/lava-test-runner /lava-12074051/0<3>[ 20.452039] mt7921e 0000:01:00.0: hardware init failed
11033 11:50:41.051675
11034 11:50:41.081080 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.480597] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12074051_1.5.2.3.1>
11035 11:50:41.081882 Received signal: <STARTRUN> 0_igt-kms-mediatek 12074051_1.5.2.3.1
11036 11:50:41.082308 Starting test lava.0_igt-kms-mediatek (12074051_1.5.2.3.1)
11037 11:50:41.082740 Skipping test definition patterns.
11038 11:50:41.084772 diatek
11039 11:50:41.087652 + cd /lava-12074051/0/tests/0_igt-kms-mediatek
11040 11:50:41.088087 + cat uuid
11041 11:50:41.090726 + UUID=12074051_1.5.2.3.1
11042 11:50:41.091247 + set +x
11043 11:50:41.104287 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 20.504778] <LAVA_SIGNAL_TESTSET START core_auth>
11044 11:50:41.105209 Received signal: <TESTSET> START core_auth
11045 11:50:41.105592 Starting test_set core_auth
11046 11:50:41.116940 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11047 11:50:41.125346 <14>[ 20.525919] [IGT] core_auth: executing
11048 11:50:41.131860 IGT-Version: 1.2<14>[ 20.530342] [IGT] core_auth: starting subtest getclient-simple
11049 11:50:41.142648 7.1-g621c2d3 (aa<14>[ 20.537974] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11050 11:50:41.145282 rch64) (Linux: 6<14>[ 20.546267] [IGT] core_auth: exiting, ret=0
11051 11:50:41.148580 .1.62-cip9 aarch64)
11052 11:50:41.151838 Starting subtest: getclient-simple
11053 11:50:41.157987 Opened <8>[ 20.556656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11054 11:50:41.158887 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11056 11:50:41.161557 device: /dev/dri/card0
11057 11:50:41.165070 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11058 11:50:41.176687 <14>[ 20.577004] [IGT] core_auth: executing
11059 11:50:41.182972 IGT-Version: 1.2<14>[ 20.581452] [IGT] core_auth: starting subtest getclient-master-drop
11060 11:50:41.192707 7.1-g621c2d3 (aa<14>[ 20.589494] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11061 11:50:41.199766 rch64) (Linux: 6<14>[ 20.598216] [IGT] core_auth: exiting, ret=0
11062 11:50:41.200263 .1.62-cip9 aarch64)
11063 11:50:41.202675 Starting subtest: getclient-master-drop
11064 11:50:41.212325 Op<8>[ 20.608518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11065 11:50:41.212971 ened device: /dev/dri/card0
11066 11:50:41.213740 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11068 11:50:41.218550 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11069 11:50:41.227313 <14>[ 20.628767] [IGT] core_auth: executing
11070 11:50:41.233958 IGT-Version: 1.2<14>[ 20.633235] [IGT] core_auth: starting subtest basic-auth
11071 11:50:41.240497 7.1-g621c2d3 (aa<14>[ 20.640212] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11072 11:50:41.247083 <14>[ 20.647959] [IGT] core_auth: exiting, ret=0
11073 11:50:41.250491 rch64) (Linux: 6.1.62-cip9 aarch64)
11074 11:50:41.256906 Opened device: /dev/dri/car<8>[ 20.656834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11075 11:50:41.257251 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11077 11:50:41.260362 d0
11078 11:50:41.260476 Starting subtest: basic-auth
11079 11:50:41.266963 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11080 11:50:41.275671 <14>[ 20.676649] [IGT] core_auth: executing
11081 11:50:41.282065 IGT-Version: 1.2<14>[ 20.681068] [IGT] core_auth: starting subtest many-magics
11082 11:50:41.285854 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11083 11:50:41.295038 Opened device: /dev/dri/car<14>[ 20.694547] [IGT] core_auth: finished subtest many-magics, SUCCESS
11084 11:50:41.295190 d0
11085 11:50:41.302280 Starting sub<14>[ 20.701711] [IGT] core_auth: exiting, ret=0
11086 11:50:41.302397 test: many-magics
11087 11:50:41.305177 Reopening device failed after 1020 opens
11088 11:50:41.314988 [1<8>[ 20.712175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11089 11:50:41.315275 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11091 11:50:41.318167 mSubtest many-ma<8>[ 20.721315] <LAVA_SIGNAL_TESTSET STOP>
11092 11:50:41.318479 Received signal: <TESTSET> STOP
11093 11:50:41.318579 Closing test_set core_auth
11094 11:50:41.321228 gics: SUCCESS (0.006s)[0m
11095 11:50:41.352735 <14>[ 20.753961] [IGT] core_getclient: executing
11096 11:50:41.359356 IGT-Version: 1.2<14>[ 20.758768] [IGT] core_getclient: exiting, ret=0
11097 11:50:41.363664 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11098 11:50:41.372562 Opened device: /dev/dri/car<8>[ 20.770642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11099 11:50:41.372698 d0
11100 11:50:41.372990 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11102 11:50:41.376013 SUCCESS (0.006s)
11103 11:50:41.403047 <14>[ 20.803955] [IGT] core_getstats: executing
11104 11:50:41.409616 IGT-Version: 1.2<14>[ 20.808700] [IGT] core_getstats: exiting, ret=0
11105 11:50:41.413019 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11106 11:50:41.422363 Opened device: /dev/dri/car<8>[ 20.820395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11107 11:50:41.422458 d0
11108 11:50:41.422698 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11110 11:50:41.425387 SUCCESS (0.006s)
11111 11:50:41.469197 <14>[ 20.870709] [IGT] core_getversion: executing
11112 11:50:41.475765 IGT-Version: 1.2<14>[ 20.875889] [IGT] core_getversion: exiting, ret=0
11113 11:50:41.479142 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11114 11:50:41.482939 Opened device: /dev/dri/card0
11115 11:50:41.492674 SUCCESS (0.0<8>[ 20.889472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11116 11:50:41.492773 06s)
11117 11:50:41.493019 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11119 11:50:41.536595 <14>[ 20.937665] [IGT] core_setmaster_vs_auth: executing
11120 11:50:41.543208 IGT-Version: 1.2<14>[ 20.943531] [IGT] core_setmaster_vs_auth: exiting, ret=0
11121 11:50:41.549855 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11122 11:50:41.559407 Opened device: /dev/dri/car<8>[ 20.956913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11123 11:50:41.559511 d0
11124 11:50:41.559577 SUCCESS (0.007s)
11125 11:50:41.559813 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11127 11:50:41.582943 <8>[ 20.984566] <LAVA_SIGNAL_TESTSET START drm_read>
11128 11:50:41.583269 Received signal: <TESTSET> START drm_read
11129 11:50:41.583345 Starting test_set drm_read
11130 11:50:41.603360 <14>[ 21.004818] [IGT] drm_read: executing
11131 11:50:41.610428 IGT-Version: 1.2<14>[ 21.009470] [IGT] drm_read: exiting, ret=77
11132 11:50:41.613915 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11133 11:50:41.619951 Opened devi<8>[ 21.020133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11134 11:50:41.620206 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11136 11:50:41.623453 ce: /dev/dri/card0
11137 11:50:41.626543 No KMS driver or no outputs, pipes: 8, outputs: 0
11138 11:50:41.633251 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11139 11:50:41.636888 <14>[ 21.039778] [IGT] drm_read: executing
11140 11:50:41.643043 IGT-Version: 1.2<14>[ 21.044231] [IGT] drm_read: exiting, ret=77
11141 11:50:41.646290 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11142 11:50:41.656866 Opened device: /dev/dri/car<8>[ 21.055961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11143 11:50:41.656948 d0
11144 11:50:41.657185 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11146 11:50:41.663205 No KMS driver or no outputs, pipes: 8, outputs: 0
11147 11:50:41.666662 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11148 11:50:41.674780 <14>[ 21.075848] [IGT] drm_read: executing
11149 11:50:41.680972 IGT-Version: 1.2<14>[ 21.080270] [IGT] drm_read: exiting, ret=77
11150 11:50:41.684315 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11151 11:50:41.691132 Opened devi<8>[ 21.091286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11152 11:50:41.691386 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11154 11:50:41.694807 ce: /dev/dri/card0
11155 11:50:41.697506 No KMS driver or no outputs, pipes: 8, outputs: 0
11156 11:50:41.700878 [1mSubtest empty-block: SKIP (0.000s)[0m
11157 11:50:41.711755 <14>[ 21.113309] [IGT] drm_read: executing
11158 11:50:41.718690 IGT-Version: 1.2<14>[ 21.117905] [IGT] drm_read: exiting, ret=77
11159 11:50:41.722565 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11160 11:50:41.728523 Opened devi<8>[ 21.128983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11161 11:50:41.728775 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11163 11:50:41.731563 ce: /dev/dri/card0
11164 11:50:41.735224 No KMS driver or no outputs, pipes: 8, outputs: 0
11165 11:50:41.741738 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11166 11:50:41.745775 <14>[ 21.148368] [IGT] drm_read: executing
11167 11:50:41.751327 IGT-Version: 1.2<14>[ 21.152799] [IGT] drm_read: exiting, ret=77
11168 11:50:41.758077 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11169 11:50:41.767738 Opened device: /dev/dri/car<8>[ 21.164691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11170 11:50:41.767854 d0
11171 11:50:41.768129 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11173 11:50:41.771195 No KMS driver or no outputs, pipes: 8, outputs: 0
11174 11:50:41.774566 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11175 11:50:41.783942 <14>[ 21.184925] [IGT] drm_read: executing
11176 11:50:41.790425 IGT-Version: 1.2<14>[ 21.189487] [IGT] drm_read: exiting, ret=77
11177 11:50:41.793319 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11178 11:50:41.803520 Opened device: /dev/dri/car<8>[ 21.201204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11179 11:50:41.803637 d0
11180 11:50:41.803911 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11182 11:50:41.806424 No KMS driver or no outputs, pipes: 8, outputs: 0
11183 11:50:41.812886 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11184 11:50:41.822116 <14>[ 21.223567] [IGT] drm_read: executing
11185 11:50:41.828839 IGT-Version: 1.2<14>[ 21.228040] [IGT] drm_read: exiting, ret=77
11186 11:50:41.831940 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11187 11:50:41.841962 Opened device: /dev/dri/car<8>[ 21.239343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11188 11:50:41.842044 d0
11189 11:50:41.842275 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11191 11:50:41.848734 No KMS driver or no outputs,<8>[ 21.249715] <LAVA_SIGNAL_TESTSET STOP>
11192 11:50:41.848985 Received signal: <TESTSET> STOP
11193 11:50:41.849054 Closing test_set drm_read
11194 11:50:41.852196 pipes: 8, outputs: 0
11195 11:50:41.855384 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11196 11:50:41.870196 <8>[ 21.271653] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11197 11:50:41.870488 Received signal: <TESTSET> START kms_addfb_basic
11198 11:50:41.870560 Starting test_set kms_addfb_basic
11199 11:50:41.890940 <14>[ 21.292301] [IGT] kms_addfb_basic: executing
11200 11:50:41.904129 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<14>[ 21.301513] [IGT] kms_addfb_basic: starting subtest unused-handle
11201 11:50:41.904213 64)
11202 11:50:41.911287 Opened devi<14>[ 21.309276] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11203 11:50:41.913923 ce: /dev/dri/card0
11204 11:50:41.917625 Starting subtest: unused-handle
11205 11:50:41.920497 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11206 11:50:41.927094 Test requi<14>[ 21.326265] [IGT] kms_addfb_basic: exiting, ret=0
11207 11:50:41.940420 rement not met in function igt_require_i915, file ../lib/drmtest<8>[ 21.338214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11208 11:50:41.940503 .c:720:
11209 11:50:41.940741 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11211 11:50:41.943588 Test requirement: is_i915_device(fd)
11212 11:50:41.950538 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11213 11:50:41.953678 Test requirement: is_i915_device(fd)
11214 11:50:41.960188 No KMS d<14>[ 21.360342] [IGT] kms_addfb_basic: executing
11215 11:50:41.963443 river or no outputs, pipes: 8, outputs: 0
11216 11:50:41.970156 IGT-Version: 1.27.1-g<14>[ 21.369630] [IGT] kms_addfb_basic: starting subtest unused-pitches
11217 11:50:41.979777 621c2d3 (aarch64<14>[ 21.377591] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11218 11:50:41.983242 ) (Linux: 6.1.62-cip9 aarch64)
11219 11:50:41.986453 Opened device: /dev/dri/card0
11220 11:50:41.986534 Starting subtest: unused-pitches
11221 11:50:41.993895 <14>[ 21.394157] [IGT] kms_addfb_basic: exiting, ret=0
11222 11:50:41.993976
11223 11:50:41.997161 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11224 11:50:42.006446 Test requirem<8>[ 21.404898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11225 11:50:42.006706 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11227 11:50:42.013104 ent not met in function igt_require_i915, file ../lib/drmtest.c:720:
11228 11:50:42.016352 Test requirement: is_i915_device(fd)
11229 11:50:42.023290 Test requirement not met in function<14>[ 21.424427] [IGT] kms_addfb_basic: executing
11230 11:50:42.026075 igt_require_i915, file ../lib/drmtest.c:720:
11231 11:50:42.036423 Test requirement:<14>[ 21.433827] [IGT] kms_addfb_basic: starting subtest unused-offsets
11232 11:50:42.042562 is_i915_device(<14>[ 21.441629] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11233 11:50:42.046381 fd)
11234 11:50:42.048950 No KMS driver or no outputs, pipes: 8, outputs: 0
11235 11:50:42.055790 IGT-Version: 1.27.1-g621c2d3 (aarch64) (<14>[ 21.458322] [IGT] kms_addfb_basic: exiting, ret=0
11236 11:50:42.058916 Linux: 6.1.62-cip9 aarch64)
11237 11:50:42.062617 Opened device: /dev/dri/card0
11238 11:50:42.071960 Starting subtest: un<8>[ 21.469995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11239 11:50:42.072041 used-offsets
11240 11:50:42.072278 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11242 11:50:42.075754 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11243 11:50:42.088897 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 21.490315] [IGT] kms_addfb_basic: executing
11244 11:50:42.088979 :
11245 11:50:42.092062 Test requirement: is_i915_device(fd)
11246 11:50:42.101724 Test requirement not me<14>[ 21.499416] [IGT] kms_addfb_basic: starting subtest unused-modifier
11247 11:50:42.108428 t in function ig<14>[ 21.507307] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11248 11:50:42.115169 t_require_i915, file ../lib/drmtest.c:720:
11249 11:50:42.118134 Test requirement: is_i915_device(fd)
11250 11:50:42.121935 No KMS driver <14>[ 21.524057] [IGT] kms_addfb_basic: exiting, ret=0
11251 11:50:42.125165 or no outputs, pipes: 8, outputs: 0
11252 11:50:42.138275 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<8>[ 21.535493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11253 11:50:42.138368 ux: 6.1.62-cip9 aarch64)
11254 11:50:42.138611 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11256 11:50:42.141769 Opened device: /dev/dri/card0
11257 11:50:42.144585 Starting subtest: unused-modifier
11258 11:50:42.151136 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11259 11:50:42.154899 Test requirement <14>[ 21.556392] [IGT] kms_addfb_basic: executing
11260 11:50:42.167976 not met in function igt_require_i915, file ../lib/drmtest.c:720:<14>[ 21.566632] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11261 11:50:42.168056
11262 11:50:42.178052 Test requireme<14>[ 21.574917] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11263 11:50:42.180677 nt: is_i915_device(fd)
11264 11:50:42.190714 Test requirement not met in function igt_require_i915, file ../lib/drmte<14>[ 21.591704] [IGT] kms_addfb_basic: exiting, ret=77
11265 11:50:42.190793 st.c:720:
11266 11:50:42.194100 Test requirement: is_i915_device(fd)
11267 11:50:42.203599 No KMS driver or no outputs, pi<8>[ 21.603222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11268 11:50:42.203852 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11270 11:50:42.207028 pes: 8, outputs: 0
11271 11:50:42.213931 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11272 11:50:42.217161 Opened device: /dev/dri/card0
11273 11:50:42.220180 Starting subtest: clobberred-modifier
11274 11:50:42.223526 T<14>[ 21.624606] [IGT] kms_addfb_basic: executing
11275 11:50:42.237593 est requirement not met in function igt_require_i915, file ../li<14>[ 21.634697] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11276 11:50:42.247211 b/drmtest.c:720:<14>[ 21.643800] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11277 11:50:42.247291
11278 11:50:42.250158 Test requirement: is_i915_device(fd)
11279 11:50:42.253580 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11280 11:50:42.259944 Test<14>[ 21.661266] [IGT] kms_addfb_basic: exiting, ret=77
11281 11:50:42.266637 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11282 11:50:42.276597 T<8>[ 21.672981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11283 11:50:42.276851 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11285 11:50:42.280273 est requirement: is_i915_device(fd)
11286 11:50:42.286627 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11287 11:50:42.289758 Test requirement: is_i915_device(fd)
11288 11:50:42.293169 No<14>[ 21.694944] [IGT] kms_addfb_basic: executing
11289 11:50:42.299516 KMS driver or no outputs, pipes: 8, outputs: 0
11290 11:50:42.306603 IGT-Version: 1.<14>[ 21.704913] [IGT] kms_addfb_basic: starting subtest legacy-format
11291 11:50:42.309499 27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11292 11:50:42.319249 Opened device: /dev/dri/ca<14>[ 21.719183] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11293 11:50:42.319330 rd0
11294 11:50:42.326335 Starting subtest: invalid-smem-bo-on-discrete
11295 11:50:42.332392 Test requirement not met in function igt_req<14>[ 21.734703] [IGT] kms_addfb_basic: exiting, ret=0
11296 11:50:42.336071 uire_intel, file ../lib/drmtest.c:715:
11297 11:50:42.339524 Test requirement: is_intel_device(fd)
11298 11:50:42.349155 <8>[ 21.746167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11299 11:50:42.349409 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11301 11:50:42.352684 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11302 11:50:42.359392 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11303 11:50:42.365457 Test requirement: <14>[ 21.768086] [IGT] kms_addfb_basic: executing
11304 11:50:42.368789 is_i915_device(fd)
11305 11:50:42.378633 Test requirement not met in function igt_require_i915, file <14>[ 21.779301] [IGT] kms_addfb_basic: starting subtest no-handle
11306 11:50:42.388530 ../lib/drmtest.c<14>[ 21.786080] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11307 11:50:42.388610 :720:
11308 11:50:42.391992 Test requirement: is_i915_device(fd)
11309 11:50:42.398398 No KMS driver or no outputs, pipes:<14>[ 21.800183] [IGT] kms_addfb_basic: exiting, ret=0
11310 11:50:42.401974 8, outputs: 0
11311 11:50:42.411843 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11313 11:50:42.414937 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 21.812186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11314 11:50:42.415016 64)
11315 11:50:42.418155 Opened device: /dev/dri/card0
11316 11:50:42.418256 Starting subtest: legacy-format
11317 11:50:42.424783 Successfully fuzzed 10000 {bpp, depth} variations
11318 11:50:42.431653 [1mSubtest legacy-format: SUCCESS (0.00<14>[ 21.833377] [IGT] kms_addfb_basic: executing
11319 11:50:42.431732 6s)[0m
11320 11:50:42.444486 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 21.844985] [IGT] kms_addfb_basic: starting subtest basic
11321 11:50:42.444566 est.c:720:
11322 11:50:42.451389 Test<14>[ 21.851377] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11323 11:50:42.454686 requirement: is_i915_device(fd)
11324 11:50:42.464690 Test requirement not met in function igt_requi<14>[ 21.865203] [IGT] kms_addfb_basic: exiting, ret=0
11325 11:50:42.468091 re_i915, file ../lib/drmtest.c:720:
11326 11:50:42.477540 Test requirement: is_i915_d<8>[ 21.876538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11327 11:50:42.477620 evice(fd)
11328 11:50:42.477856 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11330 11:50:42.481358 No KMS driver or no outputs, pipes: 8, outputs: 0
11331 11:50:42.487497 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11332 11:50:42.494000 Opened device<14>[ 21.895508] [IGT] kms_addfb_basic: executing
11333 11:50:42.494080 : /dev/dri/card0
11334 11:50:42.497482 Starting subtest: no-handle
11335 11:50:42.507928 [1mSubtest no-handle: SUCCESS (0<14>[ 21.906868] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11336 11:50:42.508008 .000s)[0m
11337 11:50:42.514149 Test<14>[ 21.913812] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11338 11:50:42.523948 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11339 11:50:42.527389 T<14>[ 21.927908] [IGT] kms_addfb_basic: exiting, ret=0
11340 11:50:42.530263 est requirement: is_i915_device(fd)
11341 11:50:42.540610 Test requirement not met in function igt_re<8>[ 21.940236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11342 11:50:42.540866 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11344 11:50:42.544097 quire_i915, file ../lib/drmtest.c:720:
11345 11:50:42.547451 Test requirement: is_i915_device(fd)
11346 11:50:42.554099 No KMS driver or no outputs, pipes: 8, outputs: 0
11347 11:50:42.560925 IGT-Version: 1.27.1-g621c2d3 (a<14>[ 21.960809] [IGT] kms_addfb_basic: executing
11348 11:50:42.563979 arch64) (Linux: 6.1.62-cip9 aarch64)
11349 11:50:42.566619 Opened device: /dev/dri/card0
11350 11:50:42.573852 Starting su<14>[ 21.973007] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11351 11:50:42.573933 btest: basic
11352 11:50:42.583545 [<14>[ 21.980091] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11353 11:50:42.587053 1mSubtest basic: SUCCESS (0.000s)[0m
11354 11:50:42.593441 Test requirement not met in function igt_<14>[ 21.994403] [IGT] kms_addfb_basic: exiting, ret=0
11355 11:50:42.598095 require_i915, file ../lib/drmtest.c:720:
11356 11:50:42.599685 Test requirement: is_i915_device(fd)
11357 11:50:42.606574 <8>[ 22.006842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11358 11:50:42.606837 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11360 11:50:42.616499 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11361 11:50:42.620175 Test requirement: is_i915_device(fd)
11362 11:50:42.626796 No KMS driver or no outputs, pipes: 8, <14>[ 22.027875] [IGT] kms_addfb_basic: executing
11363 11:50:42.626878 outputs: 0
11364 11:50:42.632842 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11365 11:50:42.639650 <14>[ 22.039611] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11366 11:50:42.639731
11367 11:50:42.649508 Opened device: <14>[ 22.046519] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11368 11:50:42.649590 /dev/dri/card0
11369 11:50:42.653065 Starting subtest: bad-pitch-0
11370 11:50:42.659305 [1mSubtest bad-pitch-0: SUCCESS <14>[ 22.060781] [IGT] kms_addfb_basic: exiting, ret=0
11371 11:50:42.662658 (0.000s)[0m
11372 11:50:42.675979 Test requirement not met in function igt_require_i915, file ../lib<8>[ 22.073090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11373 11:50:42.676062 /drmtest.c:720:
11374 11:50:42.676302 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11376 11:50:42.679691 Test requirement: is_i915_device(fd)
11377 11:50:42.685669 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11378 11:50:42.692377 Test requirement: is_i<14>[ 22.094243] [IGT] kms_addfb_basic: executing
11379 11:50:42.695778 915_device(fd)
11380 11:50:42.699120 No KMS driver or no outputs, pipes: 8, outputs: 0
11381 11:50:42.706101 IGT-Version: <14>[ 22.106047] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11382 11:50:42.716126 1.27.1-g621c2d3 <14>[ 22.113090] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11383 11:50:42.719193 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11384 11:50:42.722381 Opened device: /dev/dri/card0
11385 11:50:42.729121 Starting <14>[ 22.127373] [IGT] kms_addfb_basic: exiting, ret=0
11386 11:50:42.729201 subtest: bad-pitch-32
11387 11:50:42.732139 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11388 11:50:42.742409 Test requ<8>[ 22.140017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11389 11:50:42.742663 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11391 11:50:42.748565 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11392 11:50:42.751652 Test requirement: is_i915_device(fd)
11393 11:50:42.758496 Test requirement not met in func<14>[ 22.160163] [IGT] kms_addfb_basic: executing
11394 11:50:42.761449 tion igt_require_i915, file ../lib/drmtest.c:720:
11395 11:50:42.771948 Test requirement: is_i915_dev<14>[ 22.171352] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11396 11:50:42.772028 ice(fd)
11397 11:50:42.782158 No KMS <14>[ 22.178400] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11398 11:50:42.784459 driver or no outputs, pipes: 8, outputs: 0
11399 11:50:42.791982 IGT-Version: 1.27.1-g621c2d3 (aarch6<14>[ 22.192763] [IGT] kms_addfb_basic: exiting, ret=0
11400 11:50:42.794634 4) (Linux: 6.1.62-cip9 aarch64)
11401 11:50:42.798036 Opened device: /dev/dri/card0
11402 11:50:42.807936 Starting subtest<8>[ 22.205120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11403 11:50:42.808016 : bad-pitch-63
11404 11:50:42.808253 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11406 11:50:42.811062 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11407 11:50:42.817991 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11408 11:50:42.824403 Test requirem<14>[ 22.225644] [IGT] kms_addfb_basic: executing
11409 11:50:42.828104 ent: is_i915_device(fd)
11410 11:50:42.838073 Test requirement not met in function igt_require_i915, <14>[ 22.238023] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11411 11:50:42.847397 file ../lib/drmt<14>[ 22.245305] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11412 11:50:42.847515 est.c:720:
11413 11:50:42.850886 Test requirement: is_i915_device(fd)
11414 11:50:42.860338 No KMS driver or no outputs, p<14>[ 22.259667] [IGT] kms_addfb_basic: exiting, ret=0
11415 11:50:42.860420 ipes: 8, outputs: 0
11416 11:50:42.873841 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 <8>[ 22.272023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11417 11:50:42.873923 aarch64)
11418 11:50:42.874160 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11420 11:50:42.877082 Opened device: /dev/dri/card0
11421 11:50:42.881020 Starting subtest: bad-pitch-128
11422 11:50:42.883925 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11423 11:50:42.890408 Test requirement not met in function <14>[ 22.292656] [IGT] kms_addfb_basic: executing
11424 11:50:42.897328 igt_require_i915, file ../lib/drmtest.c:720:
11425 11:50:42.906929 Test requirement: is_i915_device(f<14>[ 22.305169] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11426 11:50:42.907017 d)
11427 11:50:42.913641 Test require<14>[ 22.312188] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11428 11:50:42.920248 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11429 11:50:42.927317 Test requ<14>[ 22.326584] [IGT] kms_addfb_basic: exiting, ret=0
11430 11:50:42.929804 irement: is_i915_device(fd)
11431 11:50:42.933903 No KMS driver or no outputs, pipes: 8, outputs: 0
11432 11:50:42.939799 <8>[ 22.339004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11433 11:50:42.940056 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11435 11:50:42.946979 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11436 11:50:42.950389 Opened device: /dev/dri/card0
11437 11:50:42.953469 Starting subtest: bad-pitch-256
11438 11:50:42.959544 [1mSubtest bad-pitch-256: <14>[ 22.359974] [IGT] kms_addfb_basic: executing
11439 11:50:42.959627 SUCCESS (0.000s)[0m
11440 11:50:42.973204 Test requirement not met in function igt_require_i915, fil<14>[ 22.371860] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11441 11:50:42.979827 e ../lib/drmtest<14>[ 22.379199] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11442 11:50:42.983068 .c:720:
11443 11:50:42.987115 Test requirement: is_i915_device(fd)
11444 11:50:42.993118 Test requirement not met in funct<14>[ 22.393639] [IGT] kms_addfb_basic: exiting, ret=0
11445 11:50:42.996239 ion igt_require_i915, file ../lib/drmtest.c:720:
11446 11:50:43.005931 Test requirement: is_i915_devi<8>[ 22.406232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11447 11:50:43.006190 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11449 11:50:43.009838 ce(fd)
11450 11:50:43.012517 No KMS driver or no outputs, pipes: 8, outputs: 0
11451 11:50:43.019965 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11452 11:50:43.022386 Opened device: /dev/dri/card0
11453 11:50:43.026063 S<14>[ 22.426875] [IGT] kms_addfb_basic: executing
11454 11:50:43.029121 tarting subtest: bad-pitch-1024
11455 11:50:43.032437 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11456 11:50:43.042986 Test requirement not met in f<14>[ 22.441078] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11457 11:50:43.052792 unction igt_requ<14>[ 22.449692] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11458 11:50:43.055650 ire_i915, file ../lib/drmtest.c:720:
11459 11:50:43.062112 Test requi<14>[ 22.462863] [IGT] kms_addfb_basic: exiting, ret=0
11460 11:50:43.065846 rement: is_i915_device(fd)
11461 11:50:43.075684 Test requirement not met in function<8>[ 22.473389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11462 11:50:43.075942 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11464 11:50:43.078814 igt_require_i915, file ../lib/drmtest.c:720:
11465 11:50:43.082050 Test requirement: is_i915_device(fd)
11466 11:50:43.085493 No KMS driver or no outputs, pipes: 8, outputs: 0
11467 11:50:43.092081 IGT-Vers<14>[ 22.493339] [IGT] kms_addfb_basic: executing
11468 11:50:43.098530 ion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11469 11:50:43.098620 Opened device: /dev/dri/card0
11470 11:50:43.108692 Starting subtest: ba<14>[ 22.507020] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11471 11:50:43.108776 d-pitch-999
11472 11:50:43.118484 [1<14>[ 22.515076] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11473 11:50:43.121579 mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11474 11:50:43.125065 Te<14>[ 22.527791] [IGT] kms_addfb_basic: exiting, ret=0
11475 11:50:43.135084 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11476 11:50:43.141494 <8>[ 22.539099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11477 11:50:43.141573
11478 11:50:43.141808 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11480 11:50:43.145143 Test requirement: is_i915_device(fd)
11481 11:50:43.151652 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11482 11:50:43.154632 Test requirement: is_i915_device(fd)
11483 11:50:43.158443 <14>[ 22.559972] [IGT] kms_addfb_basic: executing
11484 11:50:43.165095 No KMS driver or no outputs, pipes: 8, outputs: 0
11485 11:50:43.174988 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aa<14>[ 22.574465] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11486 11:50:43.178200 rch64)
11487 11:50:43.185161 Opened d<14>[ 22.582968] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11488 11:50:43.188733 evice: /dev/dri/card0
11489 11:50:43.194365 Starting subtest: bad-pit<14>[ 22.596124] [IGT] kms_addfb_basic: exiting, ret=0
11490 11:50:43.194444 ch-65536
11491 11:50:43.201449 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11492 11:50:43.208712 Test requirement no<8>[ 22.607308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11493 11:50:43.208965 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11495 11:50:43.214516 t met in function igt_require_i915, file ../lib/drmtest.c:720:
11496 11:50:43.217799 Test requirement: is_i915_device(fd)
11497 11:50:43.227966 Test requirement not met in function igt_require_i915, fil<14>[ 22.629475] [IGT] kms_addfb_basic: executing
11498 11:50:43.230866 e ../lib/drmtest.c:720:
11499 11:50:43.234954 Test requirement: is_i915_device(fd)
11500 11:50:43.244156 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 22.643061] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11501 11:50:43.244237
11502 11:50:43.254475 IGT-Version: 1<14>[ 22.651206] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11503 11:50:43.263636 .27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aar<14>[ 22.664118] [IGT] kms_addfb_basic: exiting, ret=0
11504 11:50:43.263719 ch64)
11505 11:50:43.267345 Opened device: /dev/dri/card0
11506 11:50:43.270756 Starting subtest: invalid-get-prop-any
11507 11:50:43.277169 [<8>[ 22.675301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11508 11:50:43.277423 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11510 11:50:43.280444 1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11511 11:50:43.289885 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11512 11:50:43.297066 Test requirement: is_i9<14>[ 22.696811] [IGT] kms_addfb_basic: executing
11513 11:50:43.297147 15_device(fd)
11514 11:50:43.303832 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11515 11:50:43.313470 Test requirement: is_i915_devi<14>[ 22.712640] [IGT] kms_addfb_basic: starting subtest master-rmfb
11516 11:50:43.313552 ce(fd)
11517 11:50:43.320046 No KMS d<14>[ 22.719962] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11518 11:50:43.330271 river or no outputs, pipes: 8, o<14>[ 22.730494] [IGT] kms_addfb_basic: exiting, ret=0
11519 11:50:43.330366 utputs: 0
11520 11:50:43.336381 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11521 11:50:43.343152 <8>[ 22.742138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11522 11:50:43.343406 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11524 11:50:43.346729 Opened device: /dev/dri/card0
11525 11:50:43.349683 Starting subtest: invalid-get-prop
11526 11:50:43.354059 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11527 11:50:43.362886 Test requirement not met in function igt_<14>[ 22.762965] [IGT] kms_addfb_basic: executing
11528 11:50:43.366368 require_i915, file ../lib/drmtest.c:720:
11529 11:50:43.369544 Test requirement: is_i915_device(fd)
11530 11:50:43.383087 Test requirement not met in function igt_require_i915, file ../l<14>[ 22.780861] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11531 11:50:43.392485 ib/drmtest.c:720<14>[ 22.788640] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11532 11:50:43.392567 :
11533 11:50:43.399783 Test requirem<14>[ 22.798282] [IGT] kms_addfb_basic: exiting, ret=0
11534 11:50:43.399864 ent: is_i915_device(fd)
11535 11:50:43.405715 No KMS driver or no outputs, pipes: 8, outputs: 0
11536 11:50:43.412555 IGT-<8>[ 22.810480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11537 11:50:43.412810 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11539 11:50:43.419041 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11540 11:50:43.422313 Opened device: /dev/dri/card0
11541 11:50:43.426906 Starting subtest: invalid-set-prop-any
11542 11:50:43.432338 [1mSubtest invalid-set-<14>[ 22.832199] [IGT] kms_addfb_basic: executing
11543 11:50:43.435830 prop-any: SUCCESS (0.000s)[0m
11544 11:50:43.442580 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11545 11:50:43.451969 Test requirement: is_i915_dev<14>[ 22.850520] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11546 11:50:43.452050 ice(fd)
11547 11:50:43.465254 Test requirement not met in function igt_require_i915, <14>[ 22.862746] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11548 11:50:43.472209 file ../lib/drmt<14>[ 22.871182] [IGT] kms_addfb_basic: exiting, ret=98
11549 11:50:43.472293 est.c:720:
11550 11:50:43.475216 Test requirement: is_i915_device(fd)
11551 11:50:43.485120 No KMS driver or no outputs, p<8>[ 22.883562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11552 11:50:43.485373 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11554 11:50:43.489192 ipes: 8, outputs: 0
11555 11:50:43.494879 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11556 11:50:43.494958 Opened device: /dev/dri/card0
11557 11:50:43.498240 Starting subtest: invalid-set-prop
11558 11:50:43.504866 [1<14>[ 22.905183] [IGT] kms_addfb_basic: executing
11559 11:50:43.508117 mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11560 11:50:43.514891 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11561 11:50:43.524553 Test requirement: is_i915_de<14>[ 22.923177] [IGT] kms_addfb_basic: exiting, ret=77
11562 11:50:43.524633 vice(fd)
11563 11:50:43.537579 Test requirement not met in function igt_require_i915,<8>[ 22.935224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11564 11:50:43.537833 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11566 11:50:43.541806 file ../lib/drmtest.c:720:
11567 11:50:43.544334 Test requirement: is_i915_device(fd)
11568 11:50:43.547750 No KMS driver or no outputs, pipes: 8, outputs: 0
11569 11:50:43.554430 IGT-Version: 1.27.1-g621c2<14>[ 22.956123] [IGT] kms_addfb_basic: executing
11570 11:50:43.558147 d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11571 11:50:43.560629 Opened device: /dev/dri/card0
11572 11:50:43.563732 Starting subtest: master-rmfb
11573 11:50:43.573505 [1mSubtest master-rmfb: SUCCESS (0.000<14>[ 22.973486] [IGT] kms_addfb_basic: exiting, ret=77
11574 11:50:43.573586 s)[0m
11575 11:50:43.587173 Test requirement not met in function igt_require_i915, file ../lib/drmte<8>[ 22.984307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11576 11:50:43.587256 st.c:720:
11577 11:50:43.587492 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11579 11:50:43.590083 Test requirement: is_i915_device(fd)
11580 11:50:43.600230 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11581 11:50:43.603558 Test require<14>[ 23.005817] [IGT] kms_addfb_basic: executing
11582 11:50:43.606439 ment: is_i915_device(fd)
11583 11:50:43.609734 No KMS driver or no outputs, pipes: 8, outputs: 0
11584 11:50:43.623122 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)<14>[ 23.023183] [IGT] kms_addfb_basic: exiting, ret=77
11585 11:50:43.623203
11586 11:50:43.626154 Opened device: /dev/dri/card0
11587 11:50:43.636074 Starting subtest: addfb25-modif<8>[ 23.033848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11588 11:50:43.636153 ier-no-flag
11589 11:50:43.636388 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11591 11:50:43.642950 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11592 11:50:43.649938 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11593 11:50:43.656083 Test requirement: is<14>[ 23.057527] [IGT] kms_addfb_basic: executing
11594 11:50:43.659253 _i915_device(fd)
11595 11:50:43.666092 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11596 11:50:43.669032 Test requirement: is_i915_device(fd)
11597 11:50:43.672306 No KM<14>[ 23.075262] [IGT] kms_addfb_basic: exiting, ret=77
11598 11:50:43.679228 S driver or no outputs, pipes: 8, outputs: 0
11599 11:50:43.686012 IGT-Version: 1.27.<8>[ 23.085736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11600 11:50:43.686292 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11602 11:50:43.692117 1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11603 11:50:43.695962 Opened device: /dev/dri/card0
11604 11:50:43.700109 Starting subtest: addfb25-bad-modifier
11605 11:50:43.705538 (kms_addfb_basic:441) <14>[ 23.105412] [IGT] kms_addfb_basic: executing
11606 11:50:43.712150 CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11607 11:50:43.732525 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11608 11:50:43.735365 (kms_addfb_basic:441) CRITICAL: error: 0 != -1
11609 11:50:43.735443 Stack trace:
11610 11:50:43.738921 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11611 11:50:43.742153 #1 [<unknown>+0xe55247e0]
11612 11:50:43.745847 #2 [<unknown>+0xe5526278]
11613 11:50:43.749557 #3 [<unknown>+0xe552167c]
11614 11:50:43.751847 #4 [__libc_start_main+0xe8]
11615 11:50:43.751925 #5 [<unknown>+0xe55216b4]
11616 11:50:43.755005 #6 [<unknown>+0xe55216b4]
11617 11:50:43.758562 Subtest addfb25-bad-modifier failed.
11618 11:50:43.761681 **** DEBUG ****
11619 11:50:43.768305 (kms_addfb_basic:441) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11620 11:50:43.778555 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11621 11:50:43.797835 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11622 11:50:43.801478 (kms_addfb_basic:441) CRITICAL: error: 0 != -1
11623 11:50:43.804802 (kms_addfb_basic:441) igt_core-INFO: Stack trace:
11624 11:50:43.811325 (kms_addfb_basic:441) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11625 11:50:43.817976 (kms_addfb_basic:441) igt_core-INFO: #1 [<unknown>+0xe55247e0]
11626 11:50:43.824384 (kms_addfb_basic:441) igt_core-INFO: #2 [<unknown>+0xe5526278]
11627 11:50:43.832121 (kms_addfb_basic:441) igt_core-INFO: #3 [<unknown>+0xe552167c]
11628 11:50:43.834432 (kms_addfb_basic:441) igt_core-INFO: #4 [__libc_start_main+0xe8]
11629 11:50:43.840669 (kms_addfb_basic:441) igt_core-INFO: #5 [<unknown>+0xe55216b4]
11630 11:50:43.847704 (kms_addfb_basic:441) igt_core-INFO: #6 [<unknown>+0xe55216b4]
11631 11:50:43.847783 **** END ****
11632 11:50:43.854031 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11633 11:50:43.860547 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11634 11:50:43.864069 Test requirement: is_i915_device(fd)
11635 11:50:43.870385 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11636 11:50:43.873627 Test requirement: is_i915_device(fd)
11637 11:50:43.877207 No KMS driver or no outputs, pipes: 8, outputs: 0
11638 11:50:43.884108 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11639 11:50:43.887125 Opened device: /dev/dri/card0
11640 11:50:43.893870 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11641 11:50:43.897066 Test requirement: is_i915_device(fd)
11642 11:50:43.904197 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11643 11:50:43.910752 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11644 11:50:43.913763 Test requirement: is_i915_device(fd)
11645 11:50:43.916646 No KMS driver or no outputs, pipes: 8, outputs: 0
11646 11:50:43.923686 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11647 11:50:43.927014 Opened device: /dev/dri/card0
11648 11:50:43.933099 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11649 11:50:43.936353 Test requirement: is_i915_device(fd)
11650 11:50:43.943315 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11651 11:50:43.949973 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11652 11:50:43.952778 Test requirement: is_i915_device(fd)
11653 11:50:43.956234 No KMS driver or no outputs, pipes: 8, outputs: 0
11654 11:50:43.962795 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11655 11:50:43.966488 Opened device: /dev/dri/card0
11656 11:50:43.972660 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11657 11:50:43.976616 Test requirement: is_i915_device(fd)
11658 11:50:43.983063 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11659 11:50:43.989380 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11660 11:50:43.992686 Test requirement: is_i915_device(fd)
11661 11:50:43.996221 No KMS driver or no outputs, pipes: 8, outputs: 0
11662 11:50:44.002520 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11663 11:50:44.005799 Opened device: /dev/dri/card0
11664 11:50:44.012229 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11665 11:50:44.016620 Test requirement: is_i915_device(fd)
11666 11:50:44.022220 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11667 11:50:44.025742 Test requirement: is_i915_device(fd)
11668 11:50:44.032337 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11669 11:50:44.035752 No KMS driver or no outputs, pipes: 8, outputs: 0
11670 11:50:44.041935 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11671 11:50:44.045378 Opened device: /dev/dri/card0
11672 11:50:44.055225 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 23.455637] [IGT] kms_addfb_basic: exiting, ret=77
11673 11:50:44.055308 drmtest.c:720:
11674 11:50:44.058589 Test requirement: is_i915_device(fd)
11675 11:50:44.068554 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11677 11:50:44.072078 Test requirement not met i<8>[ 23.468699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11678 11:50:44.075225 n function igt_require_i915, file ../lib/drmtest.c:720:
11679 11:50:44.078288 Test requirement: is_i915_device(fd)
11680 11:50:44.085352 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11681 11:50:44.091493 No KMS driver or no out<14>[ 23.492068] [IGT] kms_addfb_basic: executing
11682 11:50:44.091576 puts, pipes: 8, outputs: 0
11683 11:50:44.098792 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11684 11:50:44.102165 Opened device: /dev/dri/card0
11685 11:50:44.108046 Test requirement<14>[ 23.509487] [IGT] kms_addfb_basic: exiting, ret=77
11686 11:50:44.122090 not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 23.521149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11687 11:50:44.122174 :
11688 11:50:44.122414 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11690 11:50:44.124614 Test requirement: is_i915_device(fd)
11691 11:50:44.134758 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11692 11:50:44.141669 Test requirement: is<14>[ 23.540686] [IGT] kms_addfb_basic: executing
11693 11:50:44.141751 _i915_device(fd)
11694 11:50:44.144599 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11695 11:50:44.151166 No KMS driver or no outputs, pipes: 8, outputs: 0
11696 11:50:44.157802 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 23.558754] [IGT] kms_addfb_basic: exiting, ret=77
11697 11:50:44.161329 (Linux: 6.1.62-cip9 aarch64)
11698 11:50:44.164085 Opened device: /dev/dri/card0
11699 11:50:44.174093 Test requirement no<8>[ 23.571077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11700 11:50:44.174347 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11702 11:50:44.178131 t met in function igt_require_i915, file ../lib/drmtest.c:720:
11703 11:50:44.180675 Test requirement: is_i915_device(fd)
11704 11:50:44.190826 Test requirement not met in function igt_r<14>[ 23.592187] [IGT] kms_addfb_basic: executing
11705 11:50:44.193660 equire_i915, file ../lib/drmtest.c:720:
11706 11:50:44.197465 Test requirement: is_i915_device(fd)
11707 11:50:44.200608 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11708 11:50:44.210486 No KMS driver or no outputs,<14>[ 23.609771] [IGT] kms_addfb_basic: exiting, ret=77
11709 11:50:44.210567 pipes: 8, outputs: 0
11710 11:50:44.220401 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<8>[ 23.621721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11711 11:50:44.220653 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11713 11:50:44.223557 inux: 6.1.62-cip9 aarch64)
11714 11:50:44.226916 Opened device: /dev/dri/card0
11715 11:50:44.233413 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11716 11:50:44.240316 Te<14>[ 23.640051] [IGT] kms_addfb_basic: executing
11717 11:50:44.244022 st requirement: is_i915_device(fd)
11718 11:50:44.249682 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11719 11:50:44.252898 Test requirement: is_i915_device(fd)
11720 11:50:44.256372 No <14>[ 23.658302] [IGT] kms_addfb_basic: exiting, ret=77
11721 11:50:44.263511 KMS driver or no outputs, pipes: 8, outputs: 0
11722 11:50:44.272940 [1mSubtest size-max: SKIP (0.00<8>[ 23.670286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11723 11:50:44.273020 0s)[0m
11724 11:50:44.273255 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11726 11:50:44.279601 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11727 11:50:44.279680 Opened device: /dev/dri/card0
11728 11:50:44.289700 Test requirement not met in functio<14>[ 23.690227] [IGT] kms_addfb_basic: executing
11729 11:50:44.293195 n igt_require_i915, file ../lib/drmtest.c:720:
11730 11:50:44.295904 Test requirement: is_i915_device(fd)
11731 11:50:44.306117 Test requirement not met in function igt_require_i915, fil<14>[ 23.707836] [IGT] kms_addfb_basic: exiting, ret=77
11732 11:50:44.309057 e ../lib/drmtest.c:720:
11733 11:50:44.312435 Test requirement: is_i915_device(fd)
11734 11:50:44.319132 No KMS driver or <8>[ 23.718716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11735 11:50:44.319385 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11737 11:50:44.322360 no outputs, pipes: 8, outputs: 0
11738 11:50:44.326439 [1mSubtest too-wide: SKIP (0.000s)[0m
11739 11:50:44.332422 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11740 11:50:44.336027 Opened device: /dev/dri/card0
11741 11:50:44.338992 T<14>[ 23.741464] [IGT] kms_addfb_basic: executing
11742 11:50:44.347185 est requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11743 11:50:44.351949 Test requirement: is_i915_device(fd)
11744 11:50:44.359203 Test requirement not met<14>[ 23.759097] [IGT] kms_addfb_basic: exiting, ret=77
11745 11:50:44.362366 in function igt_require_i915, file ../lib/drmtest.c:720:
11746 11:50:44.368701 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11748 11:50:44.371830 Test <8>[ 23.769774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11749 11:50:44.371910 requirement: is_i915_device(fd)
11750 11:50:44.378552 No KMS driver or no outputs, pipes: 8, outputs: 0
11751 11:50:44.381832 [1mSubtest too-high: SKIP (0.000s)[0m
11752 11:50:44.391872 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<14>[ 23.791928] [IGT] kms_addfb_basic: executing
11753 11:50:44.391954 62-cip9 aarch64)
11754 11:50:44.395149 Opened device: /dev/dri/card0
11755 11:50:44.401669 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11756 11:50:44.408203 Test requirement: is_i915_de<14>[ 23.809463] [IGT] kms_addfb_basic: exiting, ret=77
11757 11:50:44.411143 vice(fd)
11758 11:50:44.421162 Test requirement not met in function igt_require_i915,<8>[ 23.821417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11759 11:50:44.421414 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11761 11:50:44.424564 file ../lib/drmtest.c:720:
11762 11:50:44.428395 Test requirement: is_i915_device(fd)
11763 11:50:44.430868 No KMS driver or no outputs, pipes: 8, outputs: 0
11764 11:50:44.438017 [1mSubtest bo-too-small: <14>[ 23.839367] [IGT] kms_addfb_basic: executing
11765 11:50:44.441333 SKIP (0.000s)[0m
11766 11:50:44.447556 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11767 11:50:44.447635 Opened device: /dev/dri/card0
11768 11:50:44.457309 Test requirement not met in function igt_<14>[ 23.857879] [IGT] kms_addfb_basic: exiting, ret=77
11769 11:50:44.461035 require_i915, file ../lib/drmtest.c:720:
11770 11:50:44.470882 Test requirement: is_i<8>[ 23.869858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11771 11:50:44.471134 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11773 11:50:44.473932 915_device(fd)
11774 11:50:44.481068 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11775 11:50:44.483636 Test requirement: is_i915_device(fd)
11776 11:50:44.487317 No KMS <14>[ 23.890503] [IGT] kms_addfb_basic: executing
11777 11:50:44.493775 driver or no outputs, pipes: 8, outputs: 0
11778 11:50:44.497306 [1mSubtest small-bo: SKIP (0.000s)[0m
11779 11:50:44.503887 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11780 11:50:44.506964 Opened<14>[ 23.908019] [IGT] kms_addfb_basic: exiting, ret=77
11781 11:50:44.510127 device: /dev/dri/card0
11782 11:50:44.520219 Test requirement not met in function ig<8>[ 23.919853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11783 11:50:44.520473 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11785 11:50:44.523631 t_require_i915, file ../lib/drmtest.c:720:
11786 11:50:44.526651 Test requirement: is_i915_device(fd)
11787 11:50:44.540062 Test requirement not met in function igt_require_i915, file ..<14>[ 23.939300] [IGT] kms_addfb_basic: executing
11788 11:50:44.540143 /lib/drmtest.c:720:
11789 11:50:44.543225 Test requirement: is_i915_device(fd)
11790 11:50:44.546793 No KMS driver or no outputs, pipes: 8, outputs: 0
11791 11:50:44.556652 [1mSubtest bo-too-small-due-to-ti<14>[ 23.957472] [IGT] kms_addfb_basic: exiting, ret=77
11792 11:50:44.559755 ling: SKIP (0.000s)[0m
11793 11:50:44.569576 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-c<8>[ 23.968278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11794 11:50:44.569829 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11796 11:50:44.572849 ip9 aarch64)
11797 11:50:44.576129 Opened device: /dev/dri/card0
11798 11:50:44.583542 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11799 11:50:44.589804 Test requirement<14>[ 23.989797] [IGT] kms_addfb_basic: executing
11800 11:50:44.589885 : is_i915_device(fd)
11801 11:50:44.596743 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11802 11:50:44.599055 Test requirement: is_i915_device(fd)
11803 11:50:44.606192 N<14>[ 24.007141] [IGT] kms_addfb_basic: exiting, ret=77
11804 11:50:44.609647 o KMS driver or no outputs, pipes: 8, outputs: 0
11805 11:50:44.618921 [1mSubtest ad<8>[ 24.017806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11806 11:50:44.619174 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11808 11:50:44.622132 dfb25-y-tiled-legacy: SKIP (0.000s)[0m
11809 11:50:44.629391 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11810 11:50:44.632540 Opened device: /dev/dri/card0
11811 11:50:44.636173 Tes<14>[ 24.038358] [IGT] kms_addfb_basic: executing
11812 11:50:44.645570 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11813 11:50:44.648917 Test requirement: is_i915_device(fd)
11814 11:50:44.655296 Test requirement not met in function igt_r<14>[ 24.056270] [IGT] kms_addfb_basic: exiting, ret=77
11815 11:50:44.658884 equire_i915, file ../lib/drmtest.c:720:
11816 11:50:44.662139 Test requirement: is_i915_device(fd)
11817 11:50:44.668854 N<8>[ 24.068493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11818 11:50:44.669107 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11820 11:50:44.676072 Received signal: <TESTSET> STOP
11821 11:50:44.676151 Closing test_set kms_addfb_basic
11822 11:50:44.678919 o KMS driver or no outputs, pipe<8>[ 24.078636] <LAVA_SIGNAL_TESTSET STOP>
11823 11:50:44.679000 s: 8, outputs: 0
11824 11:50:44.681739 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11825 11:50:44.688300 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11826 11:50:44.692142 Opened device: /dev/dri/card0
11827 11:50:44.698898 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11828 11:50:44.701999 Test requirement: is_i915_device(fd)
11829 11:50:44.708351 Test requ<8>[ 24.109179] <LAVA_SIGNAL_TESTSET START kms_atomic>
11830 11:50:44.708602 Received signal: <TESTSET> START kms_atomic
11831 11:50:44.708673 Starting test_set kms_atomic
11832 11:50:44.714758 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11833 11:50:44.718399 Test requirement: is_i915_device(fd)
11834 11:50:44.721411 No KMS driver or no outputs, pipes: 8, outputs: 0
11835 11:50:44.728568 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11836 11:50:44.734761 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11837 11:50:44.741579 Opened device: /dev/dri/car<14>[ 24.142745] [IGT] kms_atomic: executing
11838 11:50:44.741659 d0
11839 11:50:44.747819 Test require<14>[ 24.148027] [IGT] kms_atomic: exiting, ret=77
11840 11:50:44.754233 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11841 11:50:44.761398 Test requ<8>[ 24.159367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11842 11:50:44.761649 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11844 11:50:44.764995 irement: is_i915_device(fd)
11845 11:50:44.771337 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11846 11:50:44.774194 Test requirement: is_i915_device(fd)
11847 11:50:44.777802 No KMS driver or no outputs, pipes: 8, outputs: 0
11848 11:50:44.784222 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11849 11:50:44.790570 IGT-Version: 1.27.1-g62<14>[ 24.191056] [IGT] kms_atomic: executing
11850 11:50:44.794280 1c2d3 (aarch64) <14>[ 24.196530] [IGT] kms_atomic: exiting, ret=77
11851 11:50:44.797534 (Linux: 6.1.62-cip9 aarch64)
11852 11:50:44.800885 Opened device: /dev/dri/card0
11853 11:50:44.810538 No KMS driver or no<8>[ 24.207814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11854 11:50:44.810790 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11856 11:50:44.814006 outputs, pipes: 8, outputs: 0
11857 11:50:44.817070 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11858 11:50:44.826908 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 <14>[ 24.228934] [IGT] kms_atomic: executing
11859 11:50:44.826988 aarch64)
11860 11:50:44.834043 Opened<14>[ 24.233788] [IGT] kms_atomic: exiting, ret=77
11861 11:50:44.834123 device: /dev/dri/card0
11862 11:50:44.847528 No KMS driver or no outputs, pipes: 8, <8>[ 24.244842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11863 11:50:44.847610 outputs: 0
11864 11:50:44.847844 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11866 11:50:44.854044 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11867 11:50:44.860274 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11868 11:50:44.866649 Opened device: /dev/dri/ca<14>[ 24.266454] [IGT] kms_atomic: executing
11869 11:50:44.866729 rd0
11870 11:50:44.870199 No KMS driv<14>[ 24.272465] [IGT] kms_atomic: exiting, ret=77
11871 11:50:44.874167 er or no outputs, pipes: 8, outputs: 0
11872 11:50:44.883212 [1mSubtest plane-primar<8>[ 24.283629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11873 11:50:44.883463 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11875 11:50:44.889828 y-overlay-mutable-zpos: SKIP (0.000s)[0m
11876 11:50:44.893054 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11877 11:50:44.896950 Opened device: /dev/dri/card0
11878 11:50:44.899605 N<14>[ 24.303779] [IGT] kms_atomic: executing
11879 11:50:44.906480 o KMS driver or <14>[ 24.308572] [IGT] kms_atomic: exiting, ret=77
11880 11:50:44.910169 no outputs, pipes: 8, outputs: 0
11881 11:50:44.920001 [1mSubtest plane-immutable-zpos: SKIP (0.000s<8>[ 24.320617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11882 11:50:44.920252 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11884 11:50:44.922894 )[0m
11885 11:50:44.926812 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11886 11:50:44.929605 Opened device: /dev/dri/card0
11887 11:50:44.939611 No KMS driver or no outputs, pipes: 8<14>[ 24.340270] [IGT] kms_atomic: executing
11888 11:50:44.939691 , outputs: 0
11889 11:50:44.942710 [<14>[ 24.345096] [IGT] kms_atomic: exiting, ret=77
11890 11:50:44.946494 1mSubtest test-only: SKIP (0.000s)[0m
11891 11:50:44.956133 IGT-Version: 1.27.1-g621<8>[ 24.356070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11892 11:50:44.956383 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11894 11:50:44.962585 c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11895 11:50:44.962665 Opened device: /dev/dri/card0
11896 11:50:44.968876 No KMS driver or no outputs, pipes: 8, outputs: 0
11897 11:50:44.976235 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0<14>[ 24.378260] [IGT] kms_atomic: executing
11898 11:50:44.976314 m
11899 11:50:44.982211 IGT-Version: 1.2<14>[ 24.383853] [IGT] kms_atomic: exiting, ret=77
11900 11:50:44.989662 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11901 11:50:44.999133 Opened device: /dev/dri/car<8>[ 24.395487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11902 11:50:44.999214 d0
11903 11:50:44.999447 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11905 11:50:45.002012 No KMS driver or no outputs, pipes: 8, outputs: 0
11906 11:50:45.005597 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11907 11:50:45.015023 <14>[ 24.416770] [IGT] kms_atomic: executing
11908 11:50:45.021541 IGT-Version: 1.2<14>[ 24.421496] [IGT] kms_atomic: exiting, ret=77
11909 11:50:45.025163 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11910 11:50:45.034934 Opened devi<8>[ 24.432512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11911 11:50:45.035015 ce: /dev/dri/card0
11912 11:50:45.035248 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11914 11:50:45.041193 No KMS driver or no outputs, pipes: 8, outputs: 0
11915 11:50:45.044707 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11916 11:50:45.053578 <14>[ 24.455135] [IGT] kms_atomic: executing
11917 11:50:45.060475 IGT-Version: 1.2<14>[ 24.459847] [IGT] kms_atomic: exiting, ret=77
11918 11:50:45.063719 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11919 11:50:45.073679 Opened devi<8>[ 24.470933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11920 11:50:45.073758 ce: /dev/dri/card0
11921 11:50:45.073992 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11923 11:50:45.079730 No KMS driver or no outputs, pipes: 8, outputs: 0
11924 11:50:45.083958 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11925 11:50:45.089969 <14>[ 24.490945] [IGT] kms_atomic: executing
11926 11:50:45.092877 IGT-Version: 1.2<14>[ 24.495557] [IGT] kms_atomic: exiting, ret=77
11927 11:50:45.099811 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11928 11:50:45.109636 Opened devi<8>[ 24.506915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11929 11:50:45.109718 ce: /dev/dri/card0
11930 11:50:45.109955 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11932 11:50:45.115958 No KMS driver or no outputs, pipes: 8, outputs: 0
11933 11:50:45.119574 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11934 11:50:45.129037 <14>[ 24.530735] [IGT] kms_atomic: executing
11935 11:50:45.135599 IGT-Version: 1.2<14>[ 24.535387] [IGT] kms_atomic: exiting, ret=77
11936 11:50:45.138919 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11937 11:50:45.149164 Opened devi<8>[ 24.546664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11938 11:50:45.149245 ce: /dev/dri/card0
11939 11:50:45.149480 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11941 11:50:45.155229 No KMS driver or no outputs, pipes: 8, outputs: 0
11942 11:50:45.158959 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11943 11:50:45.167702 <14>[ 24.569385] [IGT] kms_atomic: executing
11944 11:50:45.174365 IGT-Version: 1.2<14>[ 24.573971] [IGT] kms_atomic: exiting, ret=77
11945 11:50:45.177574 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11946 11:50:45.187155 Opened devi<8>[ 24.585303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11947 11:50:45.187441 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11949 11:50:45.190756 ce: /dev/dri/car<8>[ 24.594275] <LAVA_SIGNAL_TESTSET STOP>
11950 11:50:45.190836 d0
11951 11:50:45.191069 Received signal: <TESTSET> STOP
11952 11:50:45.191133 Closing test_set kms_atomic
11953 11:50:45.197264 No KMS driver or no outputs, pipes: 8, outputs: 0
11954 11:50:45.200367 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11955 11:50:45.221431 <8>[ 24.623503] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11956 11:50:45.221683 Received signal: <TESTSET> START kms_flip_event_leak
11957 11:50:45.221754 Starting test_set kms_flip_event_leak
11958 11:50:45.248767 <14>[ 24.650503] [IGT] kms_flip_event_leak: executing
11959 11:50:45.255271 IGT-Version: 1.2<14>[ 24.656238] [IGT] kms_flip_event_leak: exiting, ret=77
11960 11:50:45.261977 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11961 11:50:45.268836 Opened device: /dev/dri/car<8>[ 24.668338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11962 11:50:45.268917 d0
11963 11:50:45.269152 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11965 11:50:45.275168 No KMS driver or no outputs,<8>[ 24.677872] <LAVA_SIGNAL_TESTSET STOP>
11966 11:50:45.275419 Received signal: <TESTSET> STOP
11967 11:50:45.275489 Closing test_set kms_flip_event_leak
11968 11:50:45.278896 pipes: 8, outputs: 0
11969 11:50:45.281723 [1mSubtest basic: SKIP (0.000s)[0m
11970 11:50:45.296610 <8>[ 24.698092] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11971 11:50:45.296861 Received signal: <TESTSET> START kms_prop_blob
11972 11:50:45.296929 Starting test_set kms_prop_blob
11973 11:50:45.313582 <14>[ 24.715402] [IGT] kms_prop_blob: executing
11974 11:50:45.320137 IGT-Version: 1.2<14>[ 24.720231] [IGT] kms_prop_blob: starting subtest basic
11975 11:50:45.326762 7.1-g621c2d3 (aa<14>[ 24.727104] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
11976 11:50:45.333705 rch64) (Linux: 6<14>[ 24.735035] [IGT] kms_prop_blob: exiting, ret=0
11977 11:50:45.336535 .1.62-cip9 aarch64)
11978 11:50:45.339995 Opened device: /dev/dri/card0
11979 11:50:45.347212 Starting sub<8>[ 24.745485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11980 11:50:45.347291 test: basic
11981 11:50:45.347525 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11983 11:50:45.349805 [1mSubtest basic: SUCCESS (0.000s)[0m
11984 11:50:45.364332 <14>[ 24.765792] [IGT] kms_prop_blob: executing
11985 11:50:45.370746 IGT-Version: 1.2<14>[ 24.770553] [IGT] kms_prop_blob: starting subtest blob-prop-core
11986 11:50:45.380574 7.1-g621c2d3 (aa<14>[ 24.778128] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
11987 11:50:45.384030 <14>[ 24.786678] [IGT] kms_prop_blob: exiting, ret=0
11988 11:50:45.387483 rch64) (Linux: 6.1.62-cip9 aarch64)
11989 11:50:45.397137 Opened device: /dev/dri/car<8>[ 24.796440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11990 11:50:45.397217 d0
11991 11:50:45.397450 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11993 11:50:45.400635 Starting subtest: blob-prop-core
11994 11:50:45.403663 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11995 11:50:45.415211 <14>[ 24.816758] [IGT] kms_prop_blob: executing
11996 11:50:45.422530 IGT-Version: 1.2<14>[ 24.821520] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11997 11:50:45.431275 7.1-g621c2d3 (aa<14>[ 24.829582] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
11998 11:50:45.437833 <14>[ 24.838423] [IGT] kms_prop_blob: exiting, ret=0
11999 11:50:45.441311 rch64) (Linux: 6.1.62-cip9 aarch64)
12000 11:50:45.441389 Opened device: /dev/dri/card0
12001 11:50:45.451085 Starting sub<8>[ 24.849575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12002 11:50:45.451335 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12004 11:50:45.454532 test: blob-prop-validate
12005 11:50:45.457855 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12006 11:50:45.477530 <14>[ 24.879593] [IGT] kms_prop_blob: executing
12007 11:50:45.484600 IGT-Version: 1.2<14>[ 24.884615] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12008 11:50:45.494000 7.1-g621c2d3 (aa<14>[ 24.892912] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12009 11:50:45.500793 rch64) (Linux: 6<14>[ 24.901483] [IGT] kms_prop_blob: exiting, ret=0
12010 11:50:45.504351 .1.62-cip9 aarch64)
12011 11:50:45.504431 Opened device: /dev/dri/card0
12012 11:50:45.507223 Starting subtest: blob-prop-lifetime
12013 11:50:45.517246 [1mSu<8>[ 24.914745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12014 11:50:45.517498 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12016 11:50:45.520513 btest blob-prop-lifetime: SUCCESS (0.000s)[0m
12017 11:50:45.534450 <14>[ 24.936059] [IGT] kms_prop_blob: executing
12018 11:50:45.540933 IGT-Version: 1.2<14>[ 24.940833] [IGT] kms_prop_blob: starting subtest blob-multiple
12019 11:50:45.550538 7.1-g621c2d3 (aa<14>[ 24.948496] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12020 11:50:45.554225 <14>[ 24.956888] [IGT] kms_prop_blob: exiting, ret=0
12021 11:50:45.557309 rch64) (Linux: 6.1.62-cip9 aarch64)
12022 11:50:45.561102 Opened device: /dev/dri/card0
12023 11:50:45.567265 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12025 11:50:45.570461 Starting sub<8>[ 24.967892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12026 11:50:45.570541 test: blob-multiple
12027 11:50:45.574480 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12028 11:50:45.596133 <14>[ 24.997528] [IGT] kms_prop_blob: executing
12029 11:50:45.602661 IGT-Version: 1.2<14>[ 25.002624] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12030 11:50:45.612256 7.1-g621c2d3 (aa<14>[ 25.010762] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12031 11:50:45.618536 rch64) (Linux: 6<14>[ 25.019773] [IGT] kms_prop_blob: exiting, ret=0
12032 11:50:45.621840 .1.62-cip9 aarch64)
12033 11:50:45.625536 Opened device: /dev/dri/card0
12034 11:50:45.635462 Starting subtest: invalid-ge<8>[ 25.032699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12035 11:50:45.635543 t-prop-any
12036 11:50:45.635777 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12038 11:50:45.638594 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12039 11:50:45.660896 <14>[ 25.062702] [IGT] kms_prop_blob: executing
12040 11:50:45.667503 IGT-Version: 1.2<14>[ 25.067754] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12041 11:50:45.677154 7.1-g621c2d3 (aa<14>[ 25.075521] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12042 11:50:45.684293 rch64) (Linux: 6<14>[ 25.084228] [IGT] kms_prop_blob: exiting, ret=0
12043 11:50:45.684373 .1.62-cip9 aarch64)
12044 11:50:45.687441 Opened device: /dev/dri/card0
12045 11:50:45.697256 Starting subtest: invalid-ge<8>[ 25.097193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12046 11:50:45.697336 t-prop
12047 11:50:45.697571 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12049 11:50:45.703808 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12050 11:50:45.725061 <14>[ 25.126945] [IGT] kms_prop_blob: executing
12051 11:50:45.732352 IGT-Version: 1.2<14>[ 25.131945] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12052 11:50:45.741400 7.1-g621c2d3 (aa<14>[ 25.140079] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12053 11:50:45.749187 rch64) (Linux: 6<14>[ 25.149147] [IGT] kms_prop_blob: exiting, ret=0
12054 11:50:45.751689 .1.62-cip9 aarch64)
12055 11:50:45.751769 Opened device: /dev/dri/card0
12056 11:50:45.761631 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12058 11:50:45.764605 Starting subtest: invalid-se<8>[ 25.161971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12059 11:50:45.764684 t-prop-any
12060 11:50:45.768157 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12061 11:50:45.789569 <14>[ 25.191543] [IGT] kms_prop_blob: executing
12062 11:50:45.796135 IGT-Version: 1.2<14>[ 25.196605] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12063 11:50:45.806126 7.1-g621c2d3 (aa<14>[ 25.204327] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12064 11:50:45.809841 <14>[ 25.213048] [IGT] kms_prop_blob: exiting, ret=0
12065 11:50:45.812975 rch64) (Linux: 6.1.62-cip9 aarch64)
12066 11:50:45.816466 Opened device: /dev/dri/card0
12067 11:50:45.826426 Starting sub<8>[ 25.224761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12068 11:50:45.826505 test: invalid-set-prop
12069 11:50:45.826739 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12071 11:50:45.832777 [1mSubt<8>[ 25.234014] <LAVA_SIGNAL_TESTSET STOP>
12072 11:50:45.833025 Received signal: <TESTSET> STOP
12073 11:50:45.833092 Closing test_set kms_prop_blob
12074 11:50:45.835983 est invalid-set-prop: SUCCESS (0.000s)[0m
12075 11:50:45.863009 <8>[ 25.264335] <LAVA_SIGNAL_TESTSET START kms_setmode>
12076 11:50:45.863258 Received signal: <TESTSET> START kms_setmode
12077 11:50:45.863325 Starting test_set kms_setmode
12078 11:50:45.888151 <14>[ 25.289967] [IGT] kms_setmode: executing
12079 11:50:45.895061 IGT-Version: 1.2<14>[ 25.294873] [IGT] kms_setmode: starting subtest basic
12080 11:50:45.901420 7.1-g621c2d3 (aa<14>[ 25.301476] [IGT] kms_setmode: finished subtest basic, SKIP
12081 11:50:45.907802 <14>[ 25.308778] [IGT] kms_setmode: exiting, ret=77
12082 11:50:45.911246 rch64) (Linux: 6.1.62-cip9 aarch64)
12083 11:50:45.911325 Opened device: /dev/dri/card0
12084 11:50:45.920884 Starting sub<8>[ 25.319844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12085 11:50:45.920964 test: basic
12086 11:50:45.921210 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12088 11:50:45.925911 No dynamic tests executed.
12089 11:50:45.927817 [1mSubtest basic: SKIP (0.000s)[0m
12090 11:50:45.938130 <14>[ 25.339537] [IGT] kms_setmode: executing
12091 11:50:45.944676 IGT-Version: 1.2<14>[ 25.344170] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12092 11:50:45.954143 7.1-g621c2d3 (aa<14>[ 25.352361] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12093 11:50:45.960730 rch64) (Linux: 6<14>[ 25.361280] [IGT] kms_setmode: exiting, ret=77
12094 11:50:45.963846 .1.62-cip9 aarch64)
12095 11:50:45.963925 Opened device: /dev/dri/card0
12096 11:50:45.974380 Starting subtest: basic-clon<8>[ 25.373670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12097 11:50:45.974630 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12099 11:50:45.977382 e-single-crtc
12100 11:50:45.981574 No dynamic tests executed.
12101 11:50:45.983965 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12102 11:50:46.002085 <14>[ 25.404097] [IGT] kms_setmode: executing
12103 11:50:46.008625 IGT-Version: 1.2<14>[ 25.409045] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12104 11:50:46.018859 7.1-g621c2d3 (aa<14>[ 25.417325] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12105 11:50:46.025379 rch64) (Linux: 6<14>[ 25.426376] [IGT] kms_setmode: exiting, ret=77
12106 11:50:46.028863 .1.62-cip9 aarch64)
12107 11:50:46.031949 Opened device: /dev/dri/card0
12108 11:50:46.042203 Starting subtest: invalid-cl<8>[ 25.439412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12109 11:50:46.042336 one-single-crtc
12110 11:50:46.042574 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12112 11:50:46.045248 No dynamic tests executed.
12113 11:50:46.048199 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12114 11:50:46.068393 <14>[ 25.469591] [IGT] kms_setmode: executing
12115 11:50:46.078454 IGT-Version: 1.2<14>[ 25.474497] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12116 11:50:46.084300 7.1-g621c2d3 (aa<14>[ 25.483105] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12117 11:50:46.090778 rch64) (Linux: 6<14>[ 25.492412] [IGT] kms_setmode: exiting, ret=77
12118 11:50:46.094855 .1.62-cip9 aarch64)
12119 11:50:46.097350 Opened device: /dev/dri/card0
12120 11:50:46.107669 Starting subtest: invalid-cl<8>[ 25.505329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12121 11:50:46.107751 one-exclusive-crtc
12122 11:50:46.107988 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12124 11:50:46.110673 No dynamic tests executed.
12125 11:50:46.117137 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12126 11:50:46.124349 <14>[ 25.526314] [IGT] kms_setmode: executing
12127 11:50:46.131066 IGT-Version: 1.2<14>[ 25.531041] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12128 11:50:46.141139 7.1-g621c2d3 (aa<14>[ 25.538967] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12129 11:50:46.148296 rch64) (Linux: 6<14>[ 25.547692] [IGT] kms_setmode: exiting, ret=77
12130 11:50:46.148377 .1.62-cip9 aarch64)
12131 11:50:46.150652 Opened device: /dev/dri/card0
12132 11:50:46.161068 Starting subtest: clone-excl<8>[ 25.559981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12133 11:50:46.161321 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12135 11:50:46.164376 usive-crtc
12136 11:50:46.164470 No dynamic tests executed.
12137 11:50:46.170437 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12138 11:50:46.177824 <14>[ 25.579602] [IGT] kms_setmode: executing
12139 11:50:46.187593 IGT-Version: 1.2<14>[ 25.584216] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12140 11:50:46.197233 7.1-g621c2d3 (aa<14>[ 25.593364] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12141 11:50:46.200683 <14>[ 25.603219] [IGT] kms_setmode: exiting, ret=77
12142 11:50:46.203998 rch64) (Linux: 6.1.62-cip9 aarch64)
12143 11:50:46.207066 Opened device: /dev/dri/card0
12144 11:50:46.217254 Starting sub<8>[ 25.614218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12145 11:50:46.217508 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12147 11:50:46.224202 test: invalid-clone-single-crtc-<8>[ 25.625678] <LAVA_SIGNAL_TESTSET STOP>
12148 11:50:46.224298 stealing
12149 11:50:46.224565 Received signal: <TESTSET> STOP
12150 11:50:46.224646 Closing test_set kms_setmode
12151 11:50:46.227331 No dynamic tests executed.
12152 11:50:46.233546 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12153 11:50:46.254387 <8>[ 25.656248] <LAVA_SIGNAL_TESTSET START kms_vblank>
12154 11:50:46.254642 Received signal: <TESTSET> START kms_vblank
12155 11:50:46.254715 Starting test_set kms_vblank
12156 11:50:46.280774 <14>[ 25.682636] [IGT] kms_vblank: executing
12157 11:50:46.287209 IGT-Version: 1.2<14>[ 25.687849] [IGT] kms_vblank: exiting, ret=77
12158 11:50:46.290785 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12159 11:50:46.294062 Opened device: /dev/dri/card0
12160 11:50:46.300412 No KMS drive<8>[ 25.700393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12161 11:50:46.300665 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12163 11:50:46.303634 r or no outputs, pipes: 8, outputs: 0
12164 11:50:46.307283 [1mSubtest invalid: SKIP (0.000s)[0m
12165 11:50:46.318920 <14>[ 25.720914] [IGT] kms_vblank: executing
12166 11:50:46.326080 IGT-Version: 1.2<14>[ 25.725814] [IGT] kms_vblank: exiting, ret=77
12167 11:50:46.329375 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12168 11:50:46.340001 Opened device: /dev/dri/car<8>[ 25.737955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12169 11:50:46.340084 d0
12170 11:50:46.340320 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12172 11:50:46.342301 No KMS driver or no outputs, pipes: 8, outputs: 0
12173 11:50:46.345187 [1mSubtest crtc-id: SKIP (0.000s)[0m
12174 11:50:46.365216 <14>[ 25.766982] [IGT] kms_vblank: executing
12175 11:50:46.371963 IGT-Version: 1.2<14>[ 25.772133] [IGT] kms_vblank: exiting, ret=77
12176 11:50:46.374684 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12177 11:50:46.384881 Opened device: /dev/dri/car<8>[ 25.783802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12178 11:50:46.384963 d0
12179 11:50:46.385198 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12181 11:50:46.391561 No KMS driver or no outputs, pipes: 8, outputs: 0
12182 11:50:46.395092 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12183 11:50:46.413645 <14>[ 25.814288] [IGT] kms_vblank: executing
12184 11:50:46.418759 IGT-Version: 1.2<14>[ 25.819424] [IGT] kms_vblank: exiting, ret=77
12185 11:50:46.422488 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12186 11:50:46.432004 Opened device: /dev/dri/car<8>[ 25.830955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12187 11:50:46.432086 d0
12188 11:50:46.432321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12190 11:50:46.439026 No KMS driver or no outputs, pipes: 8, outputs: 0
12191 11:50:46.442226 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12192 11:50:46.459326 <14>[ 25.861339] [IGT] kms_vblank: executing
12193 11:50:46.465756 IGT-Version: 1.2<14>[ 25.866476] [IGT] kms_vblank: exiting, ret=77
12194 11:50:46.469054 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12195 11:50:46.479046 Opened devi<8>[ 25.877440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12196 11:50:46.479128 ce: /dev/dri/card0
12197 11:50:46.479364 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12199 11:50:46.486144 No KMS driver or no outputs, pipes: 8, outputs: 0
12200 11:50:46.489075 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12201 11:50:46.505677 <14>[ 25.907661] [IGT] kms_vblank: executing
12202 11:50:46.512262 IGT-Version: 1.2<14>[ 25.912730] [IGT] kms_vblank: exiting, ret=77
12203 11:50:46.515834 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12204 11:50:46.525208 Opened devi<8>[ 25.923553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12205 11:50:46.525290 ce: /dev/dri/card0
12206 11:50:46.525524 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12208 11:50:46.532076 No KMS driver or no outputs, pipes: 8, outputs: 0
12209 11:50:46.535431 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12210 11:50:46.543992 <14>[ 25.945836] [IGT] kms_vblank: executing
12211 11:50:46.550523 IGT-Version: 1.2<14>[ 25.950553] [IGT] kms_vblank: exiting, ret=77
12212 11:50:46.554632 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12213 11:50:46.564084 Opened devi<8>[ 25.961779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12214 11:50:46.564164 ce: /dev/dri/card0
12215 11:50:46.564397 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12217 11:50:46.570072 No KMS driver or no outputs, pipes: 8, outputs: 0
12218 11:50:46.573484 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12219 11:50:46.590177 <14>[ 25.991684] [IGT] kms_vblank: executing
12220 11:50:46.597034 IGT-Version: 1.2<14>[ 25.996765] [IGT] kms_vblank: exiting, ret=77
12221 11:50:46.600562 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12222 11:50:46.609993 Opened device: /dev/dri/car<8>[ 26.007818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12223 11:50:46.610098 d0
12224 11:50:46.610359 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12226 11:50:46.612814 No KMS driver or no outputs, pipes: 8, outputs: 0
12227 11:50:46.619270 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12228 11:50:46.637440 <14>[ 26.039471] [IGT] kms_vblank: executing
12229 11:50:46.643926 IGT-Version: 1.2<14>[ 26.044620] [IGT] kms_vblank: exiting, ret=77
12230 11:50:46.647294 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12231 11:50:46.650839 Opened device: /dev/dri/card0
12232 11:50:46.660649 No KMS driver or no outputs,<8>[ 26.059081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12233 11:50:46.660901 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12235 11:50:46.663852 pipes: 8, outputs: 0
12236 11:50:46.667078 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12237 11:50:46.688687 <14>[ 26.090698] [IGT] kms_vblank: executing
12238 11:50:46.695125 IGT-Version: 1.2<14>[ 26.095801] [IGT] kms_vblank: exiting, ret=77
12239 11:50:46.698732 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12240 11:50:46.708798 Opened device: /dev/dri/car<8>[ 26.107034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12241 11:50:46.708878 d0
12242 11:50:46.709112 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12244 11:50:46.715216 No KMS driver or no outputs, pipes: 8, outputs: 0
12245 11:50:46.718752 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12246 11:50:46.736579 <14>[ 26.137670] [IGT] kms_vblank: executing
12247 11:50:46.742168 IGT-Version: 1.2<14>[ 26.142812] [IGT] kms_vblank: exiting, ret=77
12248 11:50:46.746328 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12249 11:50:46.755517 Opened device: /dev/dri/car<8>[ 26.153883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12250 11:50:46.755770 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12252 11:50:46.758675 d0
12253 11:50:46.761764 No KMS driver or no outputs, pipes: 8, outputs: 0
12254 11:50:46.766054 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12255 11:50:46.783508 <14>[ 26.185379] [IGT] kms_vblank: executing
12256 11:50:46.790145 IGT-Version: 1.2<14>[ 26.190568] [IGT] kms_vblank: exiting, ret=77
12257 11:50:46.793611 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12258 11:50:46.803692 Opened device: /dev/dri/car<8>[ 26.202222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12259 11:50:46.803771 d0
12260 11:50:46.804005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12262 11:50:46.809894 No KMS driver or no outputs, pipes: 8, outputs: 0
12263 11:50:46.813198 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12264 11:50:46.830042 <14>[ 26.232094] [IGT] kms_vblank: executing
12265 11:50:46.836990 IGT-Version: 1.2<14>[ 26.237225] [IGT] kms_vblank: exiting, ret=77
12266 11:50:46.840154 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12267 11:50:46.850223 Opened devi<8>[ 26.248126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12268 11:50:46.850334 ce: /dev/dri/card0
12269 11:50:46.850569 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12271 11:50:46.856669 No KMS driver or no outputs, pipes: 8, outputs: 0
12272 11:50:46.859766 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12273 11:50:46.869121 <14>[ 26.270435] [IGT] kms_vblank: executing
12274 11:50:46.874917 IGT-Version: 1.2<14>[ 26.275149] [IGT] kms_vblank: exiting, ret=77
12275 11:50:46.878953 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12276 11:50:46.881795 Opened device: /dev/dri/card0
12277 11:50:46.888795 No KMS drive<8>[ 26.287853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12278 11:50:46.889048 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12280 11:50:46.892101 r or no outputs, pipes: 8, outputs: 0
12281 11:50:46.898212 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12282 11:50:46.916733 <14>[ 26.318710] [IGT] kms_vblank: executing
12283 11:50:46.923612 IGT-Version: 1.2<14>[ 26.323819] [IGT] kms_vblank: exiting, ret=77
12284 11:50:46.926939 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12285 11:50:46.936612 Opened device: /dev/dri/car<8>[ 26.335215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12286 11:50:46.936693 d0
12287 11:50:46.936927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12289 11:50:46.943063 No KMS driver or no outputs, pipes: 8, outputs: 0
12290 11:50:46.946662 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12291 11:50:46.963869 <14>[ 26.366000] [IGT] kms_vblank: executing
12292 11:50:46.970469 IGT-Version: 1.2<14>[ 26.371135] [IGT] kms_vblank: exiting, ret=77
12293 11:50:46.974006 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12294 11:50:46.984166 Opened devi<8>[ 26.381944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12295 11:50:46.984246 ce: /dev/dri/card0
12296 11:50:46.984479 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12298 11:50:46.987171 No KMS driver or no outputs, pipes: 8, outputs: 0
12299 11:50:46.994056 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12300 11:50:47.009430 <14>[ 26.411443] [IGT] kms_vblank: executing
12301 11:50:47.016616 IGT-Version: 1.2<14>[ 26.416532] [IGT] kms_vblank: exiting, ret=77
12302 11:50:47.019456 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12303 11:50:47.029139 Opened device: /dev/dri/car<8>[ 26.428388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12304 11:50:47.029218 d0
12305 11:50:47.029450 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12307 11:50:47.035980 No KMS driver or no outputs, pipes: 8, outputs: 0
12308 11:50:47.039415 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12309 11:50:47.055983 <14>[ 26.458247] [IGT] kms_vblank: executing
12310 11:50:47.063174 IGT-Version: 1.2<14>[ 26.463390] [IGT] kms_vblank: exiting, ret=77
12311 11:50:47.066367 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12312 11:50:47.076150 Opened device: /dev/dri/car<8>[ 26.474685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12313 11:50:47.076232 d0
12314 11:50:47.076479 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12316 11:50:47.082666 No KMS driver or no outputs, pipes: 8, outputs: 0
12317 11:50:47.086127 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12318 11:50:47.103888 <14>[ 26.505897] [IGT] kms_vblank: executing
12319 11:50:47.110651 IGT-Version: 1.2<14>[ 26.511052] [IGT] kms_vblank: exiting, ret=77
12320 11:50:47.114051 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12321 11:50:47.123943 Opened device: /dev/dri/car<8>[ 26.522407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12322 11:50:47.124067 d0
12323 11:50:47.124312 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12325 11:50:47.130443 No KMS driver or no outputs, pipes: 8, outputs: 0
12326 11:50:47.133389 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12327 11:50:47.152295 <14>[ 26.554007] [IGT] kms_vblank: executing
12328 11:50:47.159298 IGT-Version: 1.2<14>[ 26.559181] [IGT] kms_vblank: exiting, ret=77
12329 11:50:47.162456 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12330 11:50:47.171760 Opened devi<8>[ 26.569954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12331 11:50:47.171841 ce: /dev/dri/card0
12332 11:50:47.172075 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12334 11:50:47.179085 No KMS driver or no outputs, pipes: 8, outputs: 0
12335 11:50:47.182146 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12336 11:50:47.198470 <14>[ 26.600584] [IGT] kms_vblank: executing
12337 11:50:47.205459 IGT-Version: 1.2<14>[ 26.605828] [IGT] kms_vblank: exiting, ret=77
12338 11:50:47.208292 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12339 11:50:47.218832 Opened device: /dev/dri/car<8>[ 26.617155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12340 11:50:47.219086 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12342 11:50:47.221928 d0
12343 11:50:47.225063 No KMS driver or no outputs, pipes: 8, outputs: 0
12344 11:50:47.231462 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12345 11:50:47.247658 <14>[ 26.648741] [IGT] kms_vblank: executing
12346 11:50:47.253955 IGT-Version: 1.2<14>[ 26.653986] [IGT] kms_vblank: exiting, ret=77
12347 11:50:47.256804 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12348 11:50:47.266768 Opened devi<8>[ 26.664837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12349 11:50:47.267020 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12351 11:50:47.269949 ce: /dev/dri/card0
12352 11:50:47.273594 No KMS driver or no outputs, pipes: 8, outputs: 0
12353 11:50:47.279883 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12354 11:50:47.294045 <14>[ 26.696128] [IGT] kms_vblank: executing
12355 11:50:47.300901 IGT-Version: 1.2<14>[ 26.701380] [IGT] kms_vblank: exiting, ret=77
12356 11:50:47.303912 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12357 11:50:47.314101 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12359 11:50:47.317367 Opened device: /dev/dri/car<8>[ 26.712217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12360 11:50:47.317447 d0
12361 11:50:47.320824 No KMS driver or no outputs, pipes: 8, outputs: 0
12362 11:50:47.326737 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12363 11:50:47.342485 <14>[ 26.744165] [IGT] kms_vblank: executing
12364 11:50:47.348971 IGT-Version: 1.2<14>[ 26.749356] [IGT] kms_vblank: exiting, ret=77
12365 11:50:47.352643 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12366 11:50:47.361779 Opened devi<8>[ 26.760102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12367 11:50:47.361862 ce: /dev/dri/card0
12368 11:50:47.362106 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12370 11:50:47.368702 No KMS driver or no outputs, pipes: 8, outputs: 0
12371 11:50:47.372032 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12372 11:50:47.389817 <14>[ 26.791399] [IGT] kms_vblank: executing
12373 11:50:47.396659 IGT-Version: 1.2<14>[ 26.796582] [IGT] kms_vblank: exiting, ret=77
12374 11:50:47.399015 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12375 11:50:47.402566 Opened device: /dev/dri/card0
12376 11:50:47.413081 No KMS driver or no outputs,<8>[ 26.811459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12377 11:50:47.413336 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12379 11:50:47.416114 pipes: 8, outputs: 0
12380 11:50:47.419797 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12381 11:50:47.440889 <14>[ 26.843050] [IGT] kms_vblank: executing
12382 11:50:47.447503 IGT-Version: 1.2<14>[ 26.848105] [IGT] kms_vblank: exiting, ret=77
12383 11:50:47.451113 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12384 11:50:47.454479 Opened device: /dev/dri/card0
12385 11:50:47.463967 No KMS driver or no outputs,<8>[ 26.862895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12386 11:50:47.464260 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12388 11:50:47.467782 pipes: 8, outputs: 0
12389 11:50:47.474231 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12390 11:50:47.492693 <14>[ 26.894670] [IGT] kms_vblank: executing
12391 11:50:47.499121 IGT-Version: 1.2<14>[ 26.900084] [IGT] kms_vblank: exiting, ret=77
12392 11:50:47.502783 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12393 11:50:47.506034 Opened device: /dev/dri/card0
12394 11:50:47.515822 No KMS driver or no outputs,<8>[ 26.914537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12395 11:50:47.516078 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12397 11:50:47.519208 pipes: 8, outputs: 0
12398 11:50:47.525398 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12399 11:50:47.545076 <14>[ 26.946492] [IGT] kms_vblank: executing
12400 11:50:47.551014 IGT-Version: 1.2<14>[ 26.951645] [IGT] kms_vblank: exiting, ret=77
12401 11:50:47.554804 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12402 11:50:47.564423 Opened device: /dev/dri/car<8>[ 26.963003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12403 11:50:47.564507 d0
12404 11:50:47.564754 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12406 11:50:47.570791 No KMS driver or no outputs, pipes: 8, outputs: 0
12407 11:50:47.574024 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12408 11:50:47.591912 <14>[ 26.993786] [IGT] kms_vblank: executing
12409 11:50:47.598434 IGT-Version: 1.2<14>[ 26.998953] [IGT] kms_vblank: exiting, ret=77
12410 11:50:47.602135 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12411 11:50:47.611512 Opened device: /dev/dri/car<8>[ 27.010093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12412 11:50:47.611593 d0
12413 11:50:47.611826 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12415 11:50:47.618215 No KMS driver or no outputs, pipes: 8, outputs: 0
12416 11:50:47.621136 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12417 11:50:47.645225 <14>[ 27.047441] [IGT] kms_vblank: executing
12418 11:50:47.651947 IGT-Version: 1.2<14>[ 27.052600] [IGT] kms_vblank: exiting, ret=77
12419 11:50:47.655104 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12420 11:50:47.658832 Opened device: /dev/dri/card0
12421 11:50:47.669407 No KMS driver or no outputs,<8>[ 27.067667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12422 11:50:47.669661 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12424 11:50:47.672126 pipes: 8, outputs: 0
12425 11:50:47.675181 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12426 11:50:47.696293 <14>[ 27.098020] [IGT] kms_vblank: executing
12427 11:50:47.703071 IGT-Version: 1.2<14>[ 27.103220] [IGT] kms_vblank: exiting, ret=77
12428 11:50:47.706171 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12429 11:50:47.709594 Opened device: /dev/dri/card0
12430 11:50:47.719095 No KMS driver or no outputs,<8>[ 27.118311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12431 11:50:47.719347 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12433 11:50:47.722182 pipes: 8, outputs: 0
12434 11:50:47.725595 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12435 11:50:47.736651 <14>[ 27.138949] [IGT] kms_vblank: executing
12436 11:50:47.743179 IGT-Version: 1.2<14>[ 27.143664] [IGT] kms_vblank: exiting, ret=77
12437 11:50:47.746704 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12438 11:50:47.756504 Opened device: /dev/dri/car<8>[ 27.156062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12439 11:50:47.756584 d0
12440 11:50:47.756817 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12442 11:50:47.763344 No KMS driver or no outputs, pipes: 8, outputs: 0
12443 11:50:47.766669 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12444 11:50:47.784448 <14>[ 27.186724] [IGT] kms_vblank: executing
12445 11:50:47.791121 IGT-Version: 1.2<14>[ 27.191884] [IGT] kms_vblank: exiting, ret=77
12446 11:50:47.795152 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12447 11:50:47.805403 Opened device: /dev/dri/car<8>[ 27.203169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12448 11:50:47.805483 d0
12449 11:50:47.805716 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12451 11:50:47.807785 No KMS driver or no outputs, pipes: 8, outputs: 0
12452 11:50:47.814225 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12453 11:50:47.831431 <14>[ 27.233796] [IGT] kms_vblank: executing
12454 11:50:47.838486 IGT-Version: 1.2<14>[ 27.238945] [IGT] kms_vblank: exiting, ret=77
12455 11:50:47.841580 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12456 11:50:47.851599 Opened device: /dev/dri/car<8>[ 27.250194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12457 11:50:47.851679 d0
12458 11:50:47.851912 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12460 11:50:47.858289 No KMS driver or no outputs, pipes: 8, outputs: 0
12461 11:50:47.861517 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12462 11:50:47.879078 <14>[ 27.281022] [IGT] kms_vblank: executing
12463 11:50:47.885657 IGT-Version: 1.2<14>[ 27.286240] [IGT] kms_vblank: exiting, ret=77
12464 11:50:47.888583 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12465 11:50:47.898647 Opened devi<8>[ 27.297247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12466 11:50:47.898728 ce: /dev/dri/card0
12467 11:50:47.898962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12469 11:50:47.905711 No KMS driver or no outputs, pipes: 8, outputs: 0
12470 11:50:47.909126 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12471 11:50:47.916194 <14>[ 27.318306] [IGT] kms_vblank: executing
12472 11:50:47.922847 IGT-Version: 1.2<14>[ 27.323118] [IGT] kms_vblank: exiting, ret=77
12473 11:50:47.925980 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12474 11:50:47.936491 Opened device: /dev/dri/car<8>[ 27.335294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12475 11:50:47.936571 d0
12476 11:50:47.936804 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12478 11:50:47.942377 No KMS driver or no outputs, pipes: 8, outputs: 0
12479 11:50:47.945795 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12480 11:50:47.964633 <14>[ 27.366088] [IGT] kms_vblank: executing
12481 11:50:47.970788 IGT-Version: 1.2<14>[ 27.371224] [IGT] kms_vblank: exiting, ret=77
12482 11:50:47.973758 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12483 11:50:47.983698 Opened device: /dev/dri/car<8>[ 27.382536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12484 11:50:47.983778 d0
12485 11:50:47.984011 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12487 11:50:47.987379 No KMS driver or no outputs, pipes: 8, outputs: 0
12488 11:50:47.993549 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12489 11:50:48.012985 <14>[ 27.413593] [IGT] kms_vblank: executing
12490 11:50:48.018046 IGT-Version: 1.2<14>[ 27.418904] [IGT] kms_vblank: exiting, ret=77
12491 11:50:48.021568 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12492 11:50:48.025316 Opened device: /dev/dri/card0
12493 11:50:48.034726 No KMS driver or no outputs,<8>[ 27.433916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12494 11:50:48.034979 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12496 11:50:48.037985 pipes: 8, outputs: 0
12497 11:50:48.041072 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12498 11:50:48.062499 <14>[ 27.464444] [IGT] kms_vblank: executing
12499 11:50:48.068854 IGT-Version: 1.2<14>[ 27.469854] [IGT] kms_vblank: exiting, ret=77
12500 11:50:48.071970 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12501 11:50:48.075405 Opened device: /dev/dri/card0
12502 11:50:48.085136 No KMS driver or no outputs,<8>[ 27.484467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12503 11:50:48.085388 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12505 11:50:48.089036 pipes: 8, outputs: 0
12506 11:50:48.091821 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12507 11:50:48.112990 <14>[ 27.515114] [IGT] kms_vblank: executing
12508 11:50:48.119659 IGT-Version: 1.2<14>[ 27.520240] [IGT] kms_vblank: exiting, ret=77
12509 11:50:48.122715 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12510 11:50:48.126208 Opened device: /dev/dri/card0
12511 11:50:48.136281 No KMS driver or no outputs,<8>[ 27.535179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12512 11:50:48.136594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12514 11:50:48.139375 pipes: 8, outputs: 0
12515 11:50:48.142495 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12516 11:50:48.164027 <14>[ 27.565905] [IGT] kms_vblank: executing
12517 11:50:48.170435 IGT-Version: 1.2<14>[ 27.571029] [IGT] kms_vblank: exiting, ret=77
12518 11:50:48.173926 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12519 11:50:48.177197 Opened device: /dev/dri/card0
12520 11:50:48.186728 No KMS driver or no outputs,<8>[ 27.585915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12521 11:50:48.186809 pipes: 8, outputs: 0
12522 11:50:48.187043 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12524 11:50:48.193700 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12525 11:50:48.213823 <14>[ 27.616107] [IGT] kms_vblank: executing
12526 11:50:48.220485 IGT-Version: 1.2<14>[ 27.621267] [IGT] kms_vblank: exiting, ret=77
12527 11:50:48.224411 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12528 11:50:48.233715 Opened devi<8>[ 27.632137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12529 11:50:48.233795 ce: /dev/dri/card0
12530 11:50:48.234028 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12532 11:50:48.240582 No KMS driver or no outputs, pipes: 8, outputs: 0
12533 11:50:48.244590 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12534 11:50:48.261050 <14>[ 27.662855] [IGT] kms_vblank: executing
12535 11:50:48.267193 IGT-Version: 1.2<14>[ 27.668027] [IGT] kms_vblank: exiting, ret=77
12536 11:50:48.270883 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12537 11:50:48.280638 Opened devi<8>[ 27.678869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12538 11:50:48.280719 ce: /dev/dri/card0
12539 11:50:48.280953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12541 11:50:48.287098 No KMS driver or no outputs, pipes: 8, outputs: 0
12542 11:50:48.291185 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12543 11:50:48.307120 <14>[ 27.708835] [IGT] kms_vblank: executing
12544 11:50:48.313335 IGT-Version: 1.2<14>[ 27.714081] [IGT] kms_vblank: exiting, ret=77
12545 11:50:48.316936 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12546 11:50:48.327199 Opened devi<8>[ 27.724989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12547 11:50:48.327280 ce: /dev/dri/card0
12548 11:50:48.327514 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12550 11:50:48.333382 No KMS driver or no outputs, pipes: 8, outputs: 0
12551 11:50:48.336725 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12552 11:50:48.354781 <14>[ 27.755851] [IGT] kms_vblank: executing
12553 11:50:48.360474 IGT-Version: 1.2<14>[ 27.760969] [IGT] kms_vblank: exiting, ret=77
12554 11:50:48.363652 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12555 11:50:48.374144 Opened devi<8>[ 27.771776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12556 11:50:48.374227 ce: /dev/dri/card0
12557 11:50:48.374518 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12559 11:50:48.380605 No KMS driver or no outputs, pipes: 8, outputs: 0
12560 11:50:48.383398 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12561 11:50:48.392482 <14>[ 27.794654] [IGT] kms_vblank: executing
12562 11:50:48.399018 IGT-Version: 1.2<14>[ 27.799457] [IGT] kms_vblank: exiting, ret=77
12563 11:50:48.402866 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12564 11:50:48.412227 Opened device: /dev/dri/car<8>[ 27.811603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12565 11:50:48.412551 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12567 11:50:48.416279 d0
12568 11:50:48.418838 No KMS driver or no outputs, pipes: 8, outputs: 0
12569 11:50:48.425559 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12570 11:50:48.433147 <14>[ 27.835063] [IGT] kms_vblank: executing
12571 11:50:48.439737 IGT-Version: 1.2<14>[ 27.839873] [IGT] kms_vblank: exiting, ret=77
12572 11:50:48.442628 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12573 11:50:48.452610 Opened device: /dev/dri/car<8>[ 27.851953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12574 11:50:48.452864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12576 11:50:48.455912 d0
12577 11:50:48.459272 No KMS driver or no outputs, pipes: 8, outputs: 0
12578 11:50:48.465952 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12579 11:50:48.481504 <14>[ 27.883018] [IGT] kms_vblank: executing
12580 11:50:48.487291 IGT-Version: 1.2<14>[ 27.888179] [IGT] kms_vblank: exiting, ret=77
12581 11:50:48.490503 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12582 11:50:48.501091 Opened devi<8>[ 27.899095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12583 11:50:48.501345 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12585 11:50:48.504847 ce: /dev/dri/card0
12586 11:50:48.507088 No KMS driver or no outputs, pipes: 8, outputs: 0
12587 11:50:48.514040 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12588 11:50:48.517862 <14>[ 27.921443] [IGT] kms_vblank: executing
12589 11:50:48.523697 IGT-Version: 1.2<14>[ 27.926159] [IGT] kms_vblank: exiting, ret=77
12590 11:50:48.530218 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12591 11:50:48.540317 Opened device: /dev/dri/car<8>[ 27.938208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12592 11:50:48.540399 d0
12593 11:50:48.540634 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12595 11:50:48.543491 No KMS driver or no outputs, pipes: 8, outputs: 0
12596 11:50:48.550197 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12597 11:50:48.567177 <14>[ 27.969300] [IGT] kms_vblank: executing
12598 11:50:48.573462 IGT-Version: 1.2<14>[ 27.974480] [IGT] kms_vblank: exiting, ret=77
12599 11:50:48.578109 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12600 11:50:48.586910 Opened device: /dev/dri/car<8>[ 27.985557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12601 11:50:48.586992 d0
12602 11:50:48.587228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12604 11:50:48.593714 No KMS driver or no outputs, pipes: 8, outputs: 0
12605 11:50:48.596989 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12606 11:50:48.607639 <14>[ 28.009944] [IGT] kms_vblank: executing
12607 11:50:48.614647 IGT-Version: 1.2<14>[ 28.014696] [IGT] kms_vblank: exiting, ret=77
12608 11:50:48.617846 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12609 11:50:48.627582 Opened device: /dev/dri/car<8>[ 28.026833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12610 11:50:48.627836 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12612 11:50:48.631223 d0
12613 11:50:48.634457 No KMS driver or no outputs, pipes: 8, outputs: 0
12614 11:50:48.640534 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12615 11:50:48.656501 <14>[ 28.058551] [IGT] kms_vblank: executing
12616 11:50:48.663103 IGT-Version: 1.2<14>[ 28.063719] [IGT] kms_vblank: exiting, ret=77
12617 11:50:48.666383 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12618 11:50:48.676147 Opened device: /dev/dri/car<8>[ 28.075044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12619 11:50:48.676400 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12621 11:50:48.679913 d0
12622 11:50:48.682722 No KMS driver or no outputs, pipes: 8, outputs: 0
12623 11:50:48.689363 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12624 11:50:48.696277 <14>[ 28.097913] [IGT] kms_vblank: executing
12625 11:50:48.702890 IGT-Version: 1.2<14>[ 28.102670] [IGT] kms_vblank: exiting, ret=77
12626 11:50:48.705874 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12627 11:50:48.715881 Opened device: /dev/dri/car<8>[ 28.114816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12628 11:50:48.715963 d0
12629 11:50:48.716199 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12631 11:50:48.719555 No KMS driver or no outputs, pipes: 8, outputs: 0
12632 11:50:48.725807 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12633 11:50:48.742696 <14>[ 28.144826] [IGT] kms_vblank: executing
12634 11:50:48.749655 IGT-Version: 1.2<14>[ 28.150075] [IGT] kms_vblank: exiting, ret=77
12635 11:50:48.752659 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12636 11:50:48.762586 Opened device: /dev/dri/car<8>[ 28.161702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12637 11:50:48.762668 d0
12638 11:50:48.762902 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12640 11:50:48.765862 No KMS driver or no outputs, pipes: 8, outputs: 0
12641 11:50:48.772772 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12642 11:50:48.789799 <14>[ 28.191866] [IGT] kms_vblank: executing
12643 11:50:48.796330 IGT-Version: 1.2<14>[ 28.197053] [IGT] kms_vblank: exiting, ret=77
12644 11:50:48.799714 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12645 11:50:48.809641 Opened device: /dev/dri/car<8>[ 28.207928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12646 11:50:48.809723 d0
12647 11:50:48.809958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12649 11:50:48.816168 No KMS driver or no outputs, pipes: 8, outputs: 0
12650 11:50:48.819063 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12651 11:50:48.837719 <14>[ 28.239579] [IGT] kms_vblank: executing
12652 11:50:48.843987 IGT-Version: 1.2<14>[ 28.244581] [IGT] kms_vblank: exiting, ret=77
12653 11:50:48.847445 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12654 11:50:48.857149 Opened devi<8>[ 28.255613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12655 11:50:48.857245 ce: /dev/dri/card0
12656 11:50:48.857511 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12658 11:50:48.864239 No KMS driver or no outputs, pipes: 8, outputs: 0
12659 11:50:48.867189 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12660 11:50:48.884289 <14>[ 28.286361] [IGT] kms_vblank: executing
12661 11:50:48.890732 IGT-Version: 1.2<14>[ 28.291531] [IGT] kms_vblank: exiting, ret=77
12662 11:50:48.894055 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12663 11:50:48.897107 Opened device: /dev/dri/card0
12664 11:50:48.907813 No KMS driver or no outputs,<8>[ 28.306317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12665 11:50:48.908067 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12667 11:50:48.910718 pipes: 8, outputs: 0
12668 11:50:48.913924 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12669 11:50:48.934623 <14>[ 28.336758] [IGT] kms_vblank: executing
12670 11:50:48.941035 IGT-Version: 1.2<14>[ 28.341951] [IGT] kms_vblank: exiting, ret=77
12671 11:50:48.944402 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12672 11:50:48.954503 Opened device: /dev/dri/car<8>[ 28.353193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12673 11:50:48.954583 d0
12674 11:50:48.954818 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12676 11:50:48.957516 No KMS driver or no outputs, pipes: 8, outputs: 0
12677 11:50:48.964348 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12678 11:50:48.972441 <14>[ 28.374606] [IGT] kms_vblank: executing
12679 11:50:48.979480 IGT-Version: 1.2<14>[ 28.379341] [IGT] kms_vblank: exiting, ret=77
12680 11:50:48.982404 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12681 11:50:48.992360 Opened device: /dev/dri/car<8>[ 28.391381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12682 11:50:48.992441 d0
12683 11:50:48.992676 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12685 11:50:48.999191 No KMS driver or no outputs, pipes: 8, outputs: 0
12686 11:50:49.002355 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12687 11:50:49.019393 <14>[ 28.421591] [IGT] kms_vblank: executing
12688 11:50:49.025921 IGT-Version: 1.2<14>[ 28.426807] [IGT] kms_vblank: exiting, ret=77
12689 11:50:49.029406 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12690 11:50:49.039056 Opened devi<8>[ 28.437777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12691 11:50:49.039138 ce: /dev/dri/card0
12692 11:50:49.039374 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12694 11:50:49.045692 No KMS driver or no outputs, pipes: 8, outputs: 0
12695 11:50:49.049537 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12696 11:50:49.066116 <14>[ 28.468284] [IGT] kms_vblank: executing
12697 11:50:49.072343 IGT-Version: 1.2<14>[ 28.473534] [IGT] kms_vblank: exiting, ret=77
12698 11:50:49.076314 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12699 11:50:49.085855 Opened device: /dev/dri/car<8>[ 28.484360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12700 11:50:49.085941 d0
12701 11:50:49.086178 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12703 11:50:49.092969 No KMS driver or no outputs, pipes: 8, outputs: 0
12704 11:50:49.095631 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12705 11:50:49.106536 <14>[ 28.508155] [IGT] kms_vblank: executing
12706 11:50:49.112931 IGT-Version: 1.2<14>[ 28.512914] [IGT] kms_vblank: exiting, ret=77
12707 11:50:49.115650 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12708 11:50:49.125664 Opened device: /dev/dri/car<8>[ 28.525275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12709 11:50:49.125747 d0
12710 11:50:49.125984 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12712 11:50:49.129100 No KMS driver or no outputs, pipes: 8, outputs: 0
12713 11:50:49.136259 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12714 11:50:49.143873 <14>[ 28.546164] [IGT] kms_vblank: executing
12715 11:50:49.150411 IGT-Version: 1.2<14>[ 28.551079] [IGT] kms_vblank: exiting, ret=77
12716 11:50:49.153846 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12717 11:50:49.163650 Opened device: /dev/dri/car<8>[ 28.563165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12718 11:50:49.163732 d0
12719 11:50:49.163969 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12721 11:50:49.170205 No KMS driver or no outputs, pipes: 8, outputs: 0
12722 11:50:49.173455 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12723 11:50:49.191509 <14>[ 28.593611] [IGT] kms_vblank: executing
12724 11:50:49.197751 IGT-Version: 1.2<14>[ 28.598982] [IGT] kms_vblank: exiting, ret=77
12725 11:50:49.200993 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12726 11:50:49.213177 Opened device: /dev/dri/car<8>[ 28.610097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12727 11:50:49.213260 d0
12728 11:50:49.213497 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12730 11:50:49.217791 No KMS driver or no outputs, pipes: 8, outputs: 0
12731 11:50:49.220843 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12732 11:50:49.239003 <14>[ 28.641022] [IGT] kms_vblank: executing
12733 11:50:49.245661 IGT-Version: 1.2<14>[ 28.646272] [IGT] kms_vblank: exiting, ret=77
12734 11:50:49.248999 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12735 11:50:49.252117 Opened device: /dev/dri/card0
12736 11:50:49.261546 No KMS drive<8>[ 28.659170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12737 11:50:49.261807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12739 11:50:49.265045 r or no outputs, pipes: 8, outputs: 0
12740 11:50:49.268651 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12741 11:50:49.278389 <14>[ 28.680735] [IGT] kms_vblank: executing
12742 11:50:49.285069 IGT-Version: 1.2<14>[ 28.685621] [IGT] kms_vblank: exiting, ret=77
12743 11:50:49.289053 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12744 11:50:49.298000 Opened device: /dev/dri/car<8>[ 28.697680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12745 11:50:49.298084 d0
12746 11:50:49.298307 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12748 11:50:49.301811 No KMS driver or no outputs, pipes: 8, outputs: 0
12749 11:50:49.307895 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12750 11:50:49.325067 <14>[ 28.727302] [IGT] kms_vblank: executing
12751 11:50:49.331509 IGT-Version: 1.2<14>[ 28.732475] [IGT] kms_vblank: exiting, ret=77
12752 11:50:49.335565 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12753 11:50:49.344872 Opened devi<8>[ 28.743433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12754 11:50:49.344964 ce: /dev/dri/card0
12755 11:50:49.345204 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12757 11:50:49.351393 No KMS driver or no outputs, pipes: 8, outputs: 0
12758 11:50:49.354500 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12759 11:50:49.363911 <14>[ 28.766332] [IGT] kms_vblank: executing
12760 11:50:49.371148 IGT-Version: 1.2<14>[ 28.771084] [IGT] kms_vblank: exiting, ret=77
12761 11:50:49.373670 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12762 11:50:49.383600 Opened device: /dev/dri/car<8>[ 28.783438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12763 11:50:49.383686 d0
12764 11:50:49.383925 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12766 11:50:49.390456 No KMS driver or no outputs, pipes: 8, outputs: 0
12767 11:50:49.393587 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12768 11:50:49.411873 <14>[ 28.813536] [IGT] kms_vblank: executing
12769 11:50:49.418072 IGT-Version: 1.2<14>[ 28.818702] [IGT] kms_vblank: exiting, ret=77
12770 11:50:49.421873 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12771 11:50:49.431053 Opened devi<8>[ 28.829678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12772 11:50:49.431136 ce: /dev/dri/card0
12773 11:50:49.431375 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12775 11:50:49.438724 No KMS driver or no outputs, pipes: 8, outputs: 0
12776 11:50:49.441089 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12777 11:50:49.457868 <14>[ 28.860324] [IGT] kms_vblank: executing
12778 11:50:49.464791 IGT-Version: 1.2<14>[ 28.865463] [IGT] kms_vblank: exiting, ret=77
12779 11:50:49.467937 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12780 11:50:49.478037 Opened devi<8>[ 28.876173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12781 11:50:49.478193 ce: /dev/dri/card0
12782 11:50:49.478539 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12784 11:50:49.484785 No KMS driver or no outputs, pipes: 8, outputs: 0
12785 11:50:49.487516 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12786 11:50:49.505300 <14>[ 28.907516] [IGT] kms_vblank: executing
12787 11:50:49.512024 IGT-Version: 1.2<14>[ 28.912627] [IGT] kms_vblank: exiting, ret=77
12788 11:50:49.515070 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12789 11:50:49.518511 Opened device: /dev/dri/card0
12790 11:50:49.528328 No KMS driver or no outputs,<8>[ 28.927585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12791 11:50:49.528624 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12793 11:50:49.531530 pipes: 8, outputs: 0
12794 11:50:49.539232 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12795 11:50:49.557388 <14>[ 28.959407] [IGT] kms_vblank: executing
12796 11:50:49.564270 IGT-Version: 1.2<14>[ 28.964522] [IGT] kms_vblank: exiting, ret=77
12797 11:50:49.567736 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12798 11:50:49.570409 Opened device: /dev/dri/card0
12799 11:50:49.580162 No KMS driver or no outputs,<8>[ 28.979640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12800 11:50:49.580439 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12802 11:50:49.583534 pipes: 8, outputs: 0
12803 11:50:49.589888 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12804 11:50:49.609500 <14>[ 29.011112] [IGT] kms_vblank: executing
12805 11:50:49.615286 IGT-Version: 1.2<14>[ 29.016245] [IGT] kms_vblank: exiting, ret=77
12806 11:50:49.618771 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12807 11:50:49.629060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12809 11:50:49.632092 Opened device: /dev/dri/car<8>[ 29.027303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12810 11:50:49.632174 d0
12811 11:50:49.634971 No KMS driver or no outputs, pipes: 8, outputs: 0
12812 11:50:49.642342 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12813 11:50:49.657367 <14>[ 29.059315] [IGT] kms_vblank: executing
12814 11:50:49.663585 IGT-Version: 1.2<14>[ 29.064401] [IGT] kms_vblank: exiting, ret=77
12815 11:50:49.666965 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12816 11:50:49.670423 Opened device: /dev/dri/card0
12817 11:50:49.680242 No KMS driver or no outputs,<8>[ 29.079512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12818 11:50:49.680501 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12820 11:50:49.683583 pipes: 8, outputs: 0
12821 11:50:49.689805 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12822 11:50:49.698969 <14>[ 29.101222] [IGT] kms_vblank: executing
12823 11:50:49.705563 IGT-Version: 1.2<14>[ 29.106005] [IGT] kms_vblank: exiting, ret=77
12824 11:50:49.708686 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12825 11:50:49.719026 Opened device: /dev/dri/car<8>[ 29.118079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12826 11:50:49.719282 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12828 11:50:49.721599 d0
12829 11:50:49.725453 No KMS driver or no outputs, pipes: 8, outputs: 0
12830 11:50:49.731696 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12831 11:50:49.746789 <14>[ 29.149004] [IGT] kms_vblank: executing
12832 11:50:49.753242 IGT-Version: 1.2<14>[ 29.154208] [IGT] kms_vblank: exiting, ret=77
12833 11:50:49.757131 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12834 11:50:49.769803 Opened device: /dev/dri/car<8>[ 29.165506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12835 11:50:49.769934 d0
12836 11:50:49.770182 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12838 11:50:49.773073 No KMS driver or no outputs, pipes: 8, outputs: 0
12839 11:50:49.780028 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12840 11:50:49.794919 <14>[ 29.197359] [IGT] kms_vblank: executing
12841 11:50:49.801441 IGT-Version: 1.2<14>[ 29.202386] [IGT] kms_vblank: exiting, ret=77
12842 11:50:49.804863 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12843 11:50:49.815498 Opened device: /dev/dri/car<8>[ 29.213456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12844 11:50:49.815781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12846 11:50:49.818096 d0
12847 11:50:49.821365 No KMS driver or no outputs, pipes: 8, outputs: 0
12848 11:50:49.827831 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12849 11:50:49.835841 <14>[ 29.238221] [IGT] kms_vblank: executing
12850 11:50:49.842899 IGT-Version: 1.2<14>[ 29.242974] [IGT] kms_vblank: exiting, ret=77
12851 11:50:49.845700 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12852 11:50:49.855624 Opened device: /dev/dri/car<8>[ 29.254968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12853 11:50:49.855710 d0
12854 11:50:49.855952 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12856 11:50:49.862292 No KMS driver or no outputs, pipes: 8, outputs: 0
12857 11:50:49.865301 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12858 11:50:49.882883 <14>[ 29.285198] [IGT] kms_vblank: executing
12859 11:50:49.889521 IGT-Version: 1.2<14>[ 29.290344] [IGT] kms_vblank: exiting, ret=77
12860 11:50:49.893613 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12861 11:50:49.902671 Opened device: /dev/dri/car<8>[ 29.301416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12862 11:50:49.902753 d0
12863 11:50:49.902991 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12865 11:50:49.905946 No KMS driver or no outputs, pipes: 8, outputs: 0
12866 11:50:49.912799 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12867 11:50:49.923332 <14>[ 29.325353] [IGT] kms_vblank: executing
12868 11:50:49.929886 IGT-Version: 1.2<14>[ 29.330070] [IGT] kms_vblank: exiting, ret=77
12869 11:50:49.933036 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12870 11:50:49.942959 Opened device: /dev/dri/car<8>[ 29.342170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12871 11:50:49.943041 d0
12872 11:50:49.943278 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12874 11:50:49.949540 No KMS driver or no outputs, pipes: 8, outputs: 0
12875 11:50:49.952388 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12876 11:50:49.970213 <14>[ 29.372549] [IGT] kms_vblank: executing
12877 11:50:49.976980 IGT-Version: 1.2<14>[ 29.377938] [IGT] kms_vblank: exiting, ret=77
12878 11:50:49.980655 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12879 11:50:49.990270 Opened devi<8>[ 29.388720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12880 11:50:49.990369 ce: /dev/dri/card0
12881 11:50:49.990606 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12883 11:50:49.996906 No KMS driver or no outputs, pipes: 8, outputs: 0
12884 11:50:50.000301 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12885 11:50:50.016495 <14>[ 29.419018] [IGT] kms_vblank: executing
12886 11:50:50.023327 IGT-Version: 1.2<14>[ 29.424183] [IGT] kms_vblank: exiting, ret=77
12887 11:50:50.026823 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12888 11:50:50.036633 Opened device: /dev/dri/car<8>[ 29.435941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12889 11:50:50.036714 d0
12890 11:50:50.036948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12892 11:50:50.043111 No KMS driver or no outputs, pipes: 8, outputs: 0
12893 11:50:50.046931 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12894 11:50:50.064605 <14>[ 29.466780] [IGT] kms_vblank: executing
12895 11:50:50.072376 IGT-Version: 1.2<14>[ 29.471933] [IGT] kms_vblank: exiting, ret=77
12896 11:50:50.075487 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12897 11:50:50.084270 Opened device: /dev/dri/car<8>[ 29.483208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12898 11:50:50.084352 d0
12899 11:50:50.084588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12901 11:50:50.091251 No KMS driver or no outputs, pipes: 8, outputs: 0
12902 11:50:50.093915 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12903 11:50:50.111710 <14>[ 29.513717] [IGT] kms_vblank: executing
12904 11:50:50.118238 IGT-Version: 1.2<14>[ 29.518855] [IGT] kms_vblank: exiting, ret=77
12905 11:50:50.121212 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12906 11:50:50.131272 Opened device: /dev/dri/car<8>[ 29.529903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12907 11:50:50.131352 d0
12908 11:50:50.131586 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12910 11:50:50.138336 No KMS driver or no outputs, pipes: 8, outputs: 0
12911 11:50:50.141314 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12912 11:50:50.159065 <14>[ 29.561266] [IGT] kms_vblank: executing
12913 11:50:50.165577 IGT-Version: 1.2<14>[ 29.566409] [IGT] kms_vblank: exiting, ret=77
12914 11:50:50.169763 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12915 11:50:50.178985 Opened devi<8>[ 29.577376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12916 11:50:50.179067 ce: /dev/dri/card0
12917 11:50:50.179302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12919 11:50:50.185608 No KMS driver or no outputs, pipes: 8, outputs: 0
12920 11:50:50.189086 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12921 11:50:50.205805 <14>[ 29.607662] [IGT] kms_vblank: executing
12922 11:50:50.211962 IGT-Version: 1.2<14>[ 29.612811] [IGT] kms_vblank: exiting, ret=77
12923 11:50:50.215093 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12924 11:50:50.224986 Opened devi<8>[ 29.623790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12925 11:50:50.225068 ce: /dev/dri/card0
12926 11:50:50.225301 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12928 11:50:50.232209 No KMS driver or no outputs, pipes: 8, outputs: 0
12929 11:50:50.234941 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12930 11:50:50.252135 <14>[ 29.654454] [IGT] kms_vblank: executing
12931 11:50:50.258632 IGT-Version: 1.2<14>[ 29.659614] [IGT] kms_vblank: exiting, ret=77
12932 11:50:50.262063 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12933 11:50:50.272147 Opened device: /dev/dri/car<8>[ 29.670829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12934 11:50:50.272229 d0
12935 11:50:50.272463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12937 11:50:50.275358 No KMS driver or no outputs, pipes: 8, outputs: 0
12938 11:50:50.281811 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12939 11:50:50.299113 <14>[ 29.701406] [IGT] kms_vblank: executing
12940 11:50:50.305729 IGT-Version: 1.2<14>[ 29.706558] [IGT] kms_vblank: exiting, ret=77
12941 11:50:50.308762 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12942 11:50:50.319432 Opened device: /dev/dri/car<8>[ 29.717609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12943 11:50:50.319521 d0
12944 11:50:50.319761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12946 11:50:50.325332 No KMS driver or no outputs, pipes: 8, outputs: 0
12947 11:50:50.329229 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12948 11:50:50.346052 <14>[ 29.748577] [IGT] kms_vblank: executing
12949 11:50:50.352988 IGT-Version: 1.2<14>[ 29.753845] [IGT] kms_vblank: exiting, ret=77
12950 11:50:50.356426 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12951 11:50:50.366255 Opened device: /dev/dri/car<8>[ 29.765573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12952 11:50:50.366349 d0
12953 11:50:50.366589 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12955 11:50:50.372359 No KMS driver or no outputs, pipes: 8, outputs: 0
12956 11:50:50.375870 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12957 11:50:50.385252 <14>[ 29.787551] [IGT] kms_vblank: executing
12958 11:50:50.392465 IGT-Version: 1.2<14>[ 29.792266] [IGT] kms_vblank: exiting, ret=77
12959 11:50:50.394841 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12960 11:50:50.405075 Opened devi<8>[ 29.803224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12961 11:50:50.405164 ce: /dev/dri/card0
12962 11:50:50.405404 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12964 11:50:50.411938 No KMS driver or no outputs, pipes: 8, outputs: 0
12965 11:50:50.414564 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12966 11:50:50.421320 <14>[ 29.823774] [IGT] kms_vblank: executing
12967 11:50:50.428174 IGT-Version: 1.2<14>[ 29.828503] [IGT] kms_vblank: exiting, ret=77
12968 11:50:50.431756 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12969 11:50:50.441810 Opened device: /dev/dri/car<8>[ 29.840729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12970 11:50:50.441892 d0
12971 11:50:50.442130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12973 11:50:50.445714 No KMS driver or no outputs, pipes: 8, outputs: 0
12974 11:50:50.451101 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12975 11:50:50.457866 <14>[ 29.860451] [IGT] kms_vblank: executing
12976 11:50:50.464779 IGT-Version: 1.2<14>[ 29.865256] [IGT] kms_vblank: exiting, ret=77
12977 11:50:50.468261 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12978 11:50:50.477838 Opened device: /dev/dri/car<8>[ 29.877415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12979 11:50:50.477921 d0
12980 11:50:50.478159 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12982 11:50:50.485048 No KMS driver or no outputs, pipes: 8, outputs: 0
12983 11:50:50.488044 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12984 11:50:50.505032 <14>[ 29.907341] [IGT] kms_vblank: executing
12985 11:50:50.511481 IGT-Version: 1.2<14>[ 29.912625] [IGT] kms_vblank: exiting, ret=77
12986 11:50:50.514558 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12987 11:50:50.524623 Opened device: /dev/dri/car<8>[ 29.924256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12988 11:50:50.524709 d0
12989 11:50:50.524950 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12991 11:50:50.531405 No KMS driver or no outputs, pipes: 8, outputs: 0
12992 11:50:50.534257 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12993 11:50:50.552561 <14>[ 29.955062] [IGT] kms_vblank: executing
12994 11:50:50.559518 IGT-Version: 1.2<14>[ 29.960248] [IGT] kms_vblank: exiting, ret=77
12995 11:50:50.563000 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12996 11:50:50.572528 Opened device: /dev/dri/car<8>[ 29.972095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12997 11:50:50.572615 d0
12998 11:50:50.572855 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13000 11:50:50.578910 No KMS driver or no outputs, pipes: 8, outputs: 0
13001 11:50:50.582291 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13002 11:50:50.592106 <14>[ 29.994159] [IGT] kms_vblank: executing
13003 11:50:50.598399 IGT-Version: 1.2<14>[ 29.998914] [IGT] kms_vblank: exiting, ret=77
13004 11:50:50.601657 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13005 11:50:50.605617 Opened device: /dev/dri/card0
13006 11:50:50.614956 No KMS driver or no outputs,<8>[ 30.014044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13007 11:50:50.615228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13009 11:50:50.618682 pipes: 8, outputs: 0
13010 11:50:50.621294 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13011 11:50:50.642336 <14>[ 30.044723] [IGT] kms_vblank: executing
13012 11:50:50.648756 IGT-Version: 1.2<14>[ 30.050025] [IGT] kms_vblank: exiting, ret=77
13013 11:50:50.652182 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13014 11:50:50.661985 Opened device: /dev/dri/car<8>[ 30.061413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13015 11:50:50.662262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13017 11:50:50.665557 d0
13018 11:50:50.668774 No KMS driver or no outputs, pipes: 8, outputs: 0
13019 11:50:50.674954 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13020 11:50:50.690832 <14>[ 30.093372] [IGT] kms_vblank: executing
13021 11:50:50.697628 IGT-Version: 1.2<14>[ 30.098448] [IGT] kms_vblank: exiting, ret=77
13022 11:50:50.700980 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13023 11:50:50.704193 Opened device: /dev/dri/card0
13024 11:50:50.714586 No KMS driver or no outputs,<8>[ 30.112994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13025 11:50:50.714848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13027 11:50:50.717294 pipes: 8, outputs: 0
13028 11:50:50.724043 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13029 11:50:50.743475 <14>[ 30.145854] [IGT] kms_vblank: executing
13030 11:50:50.751240 IGT-Version: 1.2<14>[ 30.150976] [IGT] kms_vblank: exiting, ret=77
13031 11:50:50.754602 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13032 11:50:50.756462 Opened device: /dev/dri/card0
13033 11:50:50.766647 No KMS driver or no outputs,<8>[ 30.165509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13034 11:50:50.766942 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13036 11:50:50.769819 pipes: 8, outputs: 0
13037 11:50:50.776345 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13038 11:50:50.795167 <14>[ 30.197569] [IGT] kms_vblank: executing
13039 11:50:50.801604 IGT-Version: 1.2<14>[ 30.202650] [IGT] kms_vblank: exiting, ret=77
13040 11:50:50.805239 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13041 11:50:50.808311 Opened device: /dev/dri/card0
13042 11:50:50.818403 No KMS driver or no outputs,<8>[ 30.217593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13043 11:50:50.818696 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13045 11:50:50.821410 pipes: 8, outputs: 0
13046 11:50:50.828148 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13047 11:50:50.845923 <14>[ 30.248562] [IGT] kms_vblank: executing
13048 11:50:50.852656 IGT-Version: 1.2<14>[ 30.253798] [IGT] kms_vblank: exiting, ret=77
13049 11:50:50.855986 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13050 11:50:50.865854 Opened devi<8>[ 30.264582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13051 11:50:50.866117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13053 11:50:50.869374 ce: /dev/dri/card0
13054 11:50:50.872436 No KMS driver or no outputs, pipes: 8, outputs: 0
13055 11:50:50.878989 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13056 11:50:50.893316 <14>[ 30.295687] [IGT] kms_vblank: executing
13057 11:50:50.899650 IGT-Version: 1.2<14>[ 30.300812] [IGT] kms_vblank: exiting, ret=77
13058 11:50:50.903625 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13059 11:50:50.913488 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13061 11:50:50.916671 Opened device: /dev/dri/car<8>[ 30.312471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13062 11:50:50.916755 d0
13063 11:50:50.920216 No KMS driver or no outputs, pipes: 8, outputs: 0
13064 11:50:50.926541 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13065 11:50:50.941719 <14>[ 30.344115] [IGT] kms_vblank: executing
13066 11:50:50.948516 IGT-Version: 1.2<14>[ 30.349499] [IGT] kms_vblank: exiting, ret=77
13067 11:50:50.951342 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13068 11:50:50.961369 Opened devi<8>[ 30.360359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13069 11:50:50.961695 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13071 11:50:50.965648 ce: /dev/dri/card0
13072 11:50:50.968348 No KMS driver or no outputs, pipes: 8, outputs: 0
13073 11:50:50.974761 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13074 11:50:50.989071 <14>[ 30.391560] [IGT] kms_vblank: executing
13075 11:50:50.995635 IGT-Version: 1.2<14>[ 30.396633] [IGT] kms_vblank: exiting, ret=77
13076 11:50:50.998776 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13077 11:50:51.008944 Opened device: /dev/dri/car<8>[ 30.407708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13078 11:50:51.009032 d0
13079 11:50:51.009288 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13081 11:50:51.015607 No KMS driver or no outputs, pipes: 8, outputs: 0
13082 11:50:51.018385 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13083 11:50:51.036799 <14>[ 30.439403] [IGT] kms_vblank: executing
13084 11:50:51.043587 IGT-Version: 1.2<14>[ 30.444489] [IGT] kms_vblank: exiting, ret=77
13085 11:50:51.046903 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13086 11:50:51.050044 Opened device: /dev/dri/card0
13087 11:50:51.060640 No KMS driver or no outputs, pipes: 8, outpu<8>[ 30.459697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13088 11:50:51.060903 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13090 11:50:51.063194 ts: 0
13091 11:50:51.066463 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13092 11:50:51.089037 <14>[ 30.490763] [IGT] kms_vblank: executing
13093 11:50:51.094866 IGT-Version: 1.2<14>[ 30.495835] [IGT] kms_vblank: exiting, ret=77
13094 11:50:51.098309 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13095 11:50:51.108162 Opened device: /dev/dri/car<8>[ 30.507257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13096 11:50:51.108364 d0
13097 11:50:51.108721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13099 11:50:51.114622 No KMS driver or no outputs, pipes: 8, outputs: 0
13100 11:50:51.117825 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13101 11:50:51.135665 <14>[ 30.538192] [IGT] kms_vblank: executing
13102 11:50:51.142981 IGT-Version: 1.2<14>[ 30.543410] [IGT] kms_vblank: exiting, ret=77
13103 11:50:51.145855 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13104 11:50:51.155523 Opened device: /dev/dri/car<8>[ 30.555068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13105 11:50:51.155606 d0
13106 11:50:51.155842 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13108 11:50:51.162432 No KMS driver or no outputs, pipes: 8, outputs: 0
13109 11:50:51.166097 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13110 11:50:51.183243 <14>[ 30.585430] [IGT] kms_vblank: executing
13111 11:50:51.189298 IGT-Version: 1.2<14>[ 30.590644] [IGT] kms_vblank: exiting, ret=77
13112 11:50:51.192890 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13113 11:50:51.202746 Opened device: /dev/dri/car<8>[ 30.602210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13114 11:50:51.202855 d0
13115 11:50:51.203121 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13117 11:50:51.209529 No KMS driver or no outputs, pipes: 8, outputs: 0
13118 11:50:51.212512 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13119 11:50:51.221871 <14>[ 30.624164] [IGT] kms_vblank: executing
13120 11:50:51.228337 IGT-Version: 1.2<14>[ 30.628962] [IGT] kms_vblank: exiting, ret=77
13121 11:50:51.231624 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13122 11:50:51.241607 Opened device: /dev/dri/car<8>[ 30.641143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13123 11:50:51.241691 d0
13124 11:50:51.241948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13126 11:50:51.244951 No KMS driver or no outputs, pipes: 8, outputs: 0
13127 11:50:51.252090 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13128 11:50:51.261428 <14>[ 30.663604] [IGT] kms_vblank: executing
13129 11:50:51.267702 IGT-Version: 1.2<14>[ 30.668521] [IGT] kms_vblank: exiting, ret=77
13130 11:50:51.271396 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13131 11:50:51.281273 Opened device: /dev/dri/car<8>[ 30.680642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13132 11:50:51.281357 d0
13133 11:50:51.281632 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13135 11:50:51.288028 No KMS driver or no outputs, pipes: 8, outputs: 0
13136 11:50:51.290986 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13137 11:50:51.307938 <14>[ 30.710591] [IGT] kms_vblank: executing
13138 11:50:51.314820 IGT-Version: 1.2<14>[ 30.715789] [IGT] kms_vblank: exiting, ret=77
13139 11:50:51.317988 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13140 11:50:51.327935 Opened device: /dev/dri/car<8>[ 30.727087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13141 11:50:51.328019 d0
13142 11:50:51.328276 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13144 11:50:51.335083 No KMS driver or no outputs, pipes: 8, outputs: 0
13145 11:50:51.338077 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13146 11:50:51.355958 <14>[ 30.757939] [IGT] kms_vblank: executing
13147 11:50:51.362060 IGT-Version: 1.2<14>[ 30.763129] [IGT] kms_vblank: exiting, ret=77
13148 11:50:51.365529 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13149 11:50:51.375514 Opened device: /dev/dri/car<8>[ 30.774460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13150 11:50:51.375598 d0
13151 11:50:51.375837 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13153 11:50:51.382071 No KMS driver or no outputs, pipes: 8, outputs: 0
13154 11:50:51.385434 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13155 11:50:51.403240 <14>[ 30.805955] [IGT] kms_vblank: executing
13156 11:50:51.410539 IGT-Version: 1.2<14>[ 30.811023] [IGT] kms_vblank: exiting, ret=77
13157 11:50:51.414381 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13158 11:50:51.423701 Opened device: /dev/dri/car<8>[ 30.822932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13159 11:50:51.423785 d0
13160 11:50:51.424022 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13162 11:50:51.426837 No KMS driver or no outputs, pipes: 8, outputs: 0
13163 11:50:51.433447 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13164 11:50:51.450113 <14>[ 30.852639] [IGT] kms_vblank: executing
13165 11:50:51.456607 IGT-Version: 1.2<14>[ 30.857864] [IGT] kms_vblank: exiting, ret=77
13166 11:50:51.459991 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13167 11:50:51.469680 Opened devi<8>[ 30.868723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13168 11:50:51.469763 ce: /dev/dri/card0
13169 11:50:51.470001 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13171 11:50:51.476842 No KMS driver or no outputs, pipes: 8, outputs: 0
13172 11:50:51.479819 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13173 11:50:51.496361 <14>[ 30.898870] [IGT] kms_vblank: executing
13174 11:50:51.502771 IGT-Version: 1.2<14>[ 30.904016] [IGT] kms_vblank: exiting, ret=77
13175 11:50:51.506225 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13176 11:50:51.516168 Opened device: /dev/dri/car<8>[ 30.915601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13177 11:50:51.516251 d0
13178 11:50:51.516488 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13180 11:50:51.522992 No KMS driver or no outputs, pipes: 8, outputs: 0
13181 11:50:51.526003 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13182 11:50:51.543582 <14>[ 30.945905] [IGT] kms_vblank: executing
13183 11:50:51.550639 IGT-Version: 1.2<14>[ 30.951102] [IGT] kms_vblank: exiting, ret=77
13184 11:50:51.553518 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13185 11:50:51.563282 Opened device: /dev/dri/car<8>[ 30.962271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13186 11:50:51.563366 d0
13187 11:50:51.563602 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13189 11:50:51.569868 No KMS driver or no outputs, pipes: 8, outputs: 0
13190 11:50:51.572808 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13191 11:50:51.591460 <14>[ 30.993350] [IGT] kms_vblank: executing
13192 11:50:51.597519 IGT-Version: 1.2<14>[ 30.998466] [IGT] kms_vblank: exiting, ret=77
13193 11:50:51.600870 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13194 11:50:51.610814 Opened device: /dev/dri/car<8>[ 31.009740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13195 11:50:51.610898 d0
13196 11:50:51.611134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13198 11:50:51.614049 No KMS driver or no outputs, pipes: 8, outputs: 0
13199 11:50:51.621036 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13200 11:50:51.638105 <14>[ 31.040336] [IGT] kms_vblank: executing
13201 11:50:51.644314 IGT-Version: 1.2<14>[ 31.045543] [IGT] kms_vblank: exiting, ret=77
13202 11:50:51.648779 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13203 11:50:51.658035 Opened devi<8>[ 31.056429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13204 11:50:51.658117 ce: /dev/dri/card0
13205 11:50:51.658355 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13207 11:50:51.664086 No KMS driver or no outputs, pipes: 8, outputs: 0
13208 11:50:51.667617 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13209 11:50:51.675950 <14>[ 31.078573] [IGT] kms_vblank: executing
13210 11:50:51.682545 IGT-Version: 1.2<14>[ 31.083303] [IGT] kms_vblank: exiting, ret=77
13211 11:50:51.686064 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13212 11:50:51.695806 Opened device: /dev/dri/car<8>[ 31.095536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13213 11:50:51.695911 d0
13214 11:50:51.696150 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13216 11:50:51.702318 No KMS driver or no outputs, pipes: 8, outputs: 0
13217 11:50:51.705624 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13218 11:50:51.722807 <14>[ 31.125608] [IGT] kms_vblank: executing
13219 11:50:51.730129 IGT-Version: 1.2<14>[ 31.130800] [IGT] kms_vblank: exiting, ret=77
13220 11:50:51.732743 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13221 11:50:51.742872 Opened device: /dev/dri/car<8>[ 31.142490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13222 11:50:51.742956 d0
13223 11:50:51.743194 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13225 11:50:51.749663 No KMS driver or no outputs, pipes: 8, outputs: 0
13226 11:50:51.752937 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13227 11:50:51.771201 <14>[ 31.173454] [IGT] kms_vblank: executing
13228 11:50:51.777501 IGT-Version: 1.2<14>[ 31.178599] [IGT] kms_vblank: exiting, ret=77
13229 11:50:51.780720 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13230 11:50:51.791170 Opened device: /dev/dri/car<8>[ 31.189545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13231 11:50:51.791253 d0
13232 11:50:51.791489 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13234 11:50:51.797304 No KMS driver or no outputs, pipes: 8, outputs: 0
13235 11:50:51.801707 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13236 11:50:51.818429 <14>[ 31.220803] [IGT] kms_vblank: executing
13237 11:50:51.824993 IGT-Version: 1.2<14>[ 31.226104] [IGT] kms_vblank: exiting, ret=77
13238 11:50:51.828070 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13239 11:50:51.838279 Opened device: /dev/dri/car<8>[ 31.236812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13240 11:50:51.838362 d0
13241 11:50:51.838599 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13243 11:50:51.844790 No KMS driver or no outputs, pipes: 8, outputs: 0
13244 11:50:51.851273 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13245 11:50:51.866691 <14>[ 31.268781] [IGT] kms_vblank: executing
13246 11:50:51.872839 IGT-Version: 1.2<14>[ 31.274061] [IGT] kms_vblank: exiting, ret=77
13247 11:50:51.876327 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13248 11:50:51.885866 Opened device: /dev/dri/car<8>[ 31.286007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13249 11:50:51.886121 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13251 11:50:51.889363 d0
13252 11:50:51.892443 No KMS driver or no outputs, pipes: 8, outputs: 0
13253 11:50:51.898882 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13254 11:50:51.914913 <14>[ 31.317273] [IGT] kms_vblank: executing
13255 11:50:51.921888 IGT-Version: 1.2<14>[ 31.322438] [IGT] kms_vblank: exiting, ret=77
13256 11:50:51.924783 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13257 11:50:51.927878 Opened device: /dev/dri/card0
13258 11:50:51.938246 No KMS driver or no outputs,<8>[ 31.337243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13259 11:50:51.938510 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13261 11:50:51.941004 pipes: 8, outputs: 0
13262 11:50:51.947752 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13263 11:50:51.966535 <14>[ 31.368828] [IGT] kms_vblank: executing
13264 11:50:51.973200 IGT-Version: 1.2<14>[ 31.374068] [IGT] kms_vblank: exiting, ret=77
13265 11:50:51.976417 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13266 11:50:51.979784 Opened device: /dev/dri/card0
13267 11:50:51.989285 No KMS driver or no outputs,<8>[ 31.388997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13268 11:50:51.989541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13270 11:50:51.992657 pipes: 8, outputs: 0
13271 11:50:51.999421 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13272 11:50:52.018456 <14>[ 31.420180] [IGT] kms_vblank: executing
13273 11:50:52.024123 IGT-Version: 1.2<14>[ 31.425276] [IGT] kms_vblank: exiting, ret=77
13274 11:50:52.027565 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13275 11:50:52.037391 Opened device: /dev/dri/car<8>[ 31.436280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13276 11:50:52.037474 d0
13277 11:50:52.037711 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13279 11:50:52.044244 No KMS driver or no outputs, pipes: 8, outputs: 0
13280 11:50:52.047306 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13281 11:50:52.066534 <14>[ 31.468098] [IGT] kms_vblank: executing
13282 11:50:52.072092 IGT-Version: 1.2<14>[ 31.473259] [IGT] kms_vblank: exiting, ret=77
13283 11:50:52.075657 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13284 11:50:52.085418 Opened devi<8>[ 31.484121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13285 11:50:52.085672 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13287 11:50:52.088689 ce: /dev/dri/card0
13288 11:50:52.091887 No KMS driver or no outputs, pipes: 8, outputs: 0
13289 11:50:52.098525 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13290 11:50:52.101904 <14>[ 31.506122] [IGT] kms_vblank: executing
13291 11:50:52.108571 IGT-Version: 1.2<14>[ 31.510853] [IGT] kms_vblank: exiting, ret=77
13292 11:50:52.114972 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13293 11:50:52.124992 Opened device: /dev/dri/car<8>[ 31.523257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13294 11:50:52.125074 d0
13295 11:50:52.125311 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13297 11:50:52.128588 No KMS driver or no outputs, pipes: 8, outputs: 0
13298 11:50:52.135192 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13299 11:50:52.151812 <14>[ 31.554320] [IGT] kms_vblank: executing
13300 11:50:52.158639 IGT-Version: 1.2<14>[ 31.559517] [IGT] kms_vblank: exiting, ret=77
13301 11:50:52.161557 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13302 11:50:52.171333 Opened device: /dev/dri/car<8>[ 31.571085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13303 11:50:52.171416 d0
13304 11:50:52.171652 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13306 11:50:52.178504 No KMS driver or no outputs, pipes: 8, outputs: 0
13307 11:50:52.182241 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13308 11:50:52.199237 <14>[ 31.601660] [IGT] kms_vblank: executing
13309 11:50:52.205791 IGT-Version: 1.2<14>[ 31.606795] [IGT] kms_vblank: exiting, ret=77
13310 11:50:52.209123 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13311 11:50:52.219251 Opened device: /dev/dri/car<8>[ 31.618289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13312 11:50:52.219334 d0
13313 11:50:52.219570 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13315 11:50:52.225459 No KMS driver or no outputs, pipes: 8, outputs: 0
13316 11:50:52.228979 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13317 11:50:52.246082 <14>[ 31.648526] [IGT] kms_vblank: executing
13318 11:50:52.252343 IGT-Version: 1.2<14>[ 31.653838] [IGT] kms_vblank: exiting, ret=77
13319 11:50:52.255983 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13320 11:50:52.266282 Opened device: /dev/dri/car<8>[ 31.665539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13321 11:50:52.266390 d0
13322 11:50:52.266624 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13324 11:50:52.272943 No KMS driver or no outputs, pipes: 8, outputs: 0
13325 11:50:52.275507 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13326 11:50:52.293111 <14>[ 31.695836] [IGT] kms_vblank: executing
13327 11:50:52.300040 IGT-Version: 1.2<14>[ 31.700959] [IGT] kms_vblank: exiting, ret=77
13328 11:50:52.303365 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13329 11:50:52.312958 Opened device: /dev/dri/car<8>[ 31.712038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13330 11:50:52.313038 d0
13331 11:50:52.313272 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13333 11:50:52.319525 No KMS driver or no outputs, pipes: 8, outputs: 0
13334 11:50:52.322986 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13335 11:50:52.333194 <14>[ 31.735935] [IGT] kms_vblank: executing
13336 11:50:52.339913 IGT-Version: 1.2<14>[ 31.740686] [IGT] kms_vblank: exiting, ret=77
13337 11:50:52.343258 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13338 11:50:52.353410 Opened device: /dev/dri/car<8>[ 31.752628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13339 11:50:52.353507 d0
13340 11:50:52.353743 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13342 11:50:52.360080 No KMS driver or no outputs, pipes: 8, outputs: 0
13343 11:50:52.363065 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13344 11:50:52.380690 <14>[ 31.783163] [IGT] kms_vblank: executing
13345 11:50:52.387330 IGT-Version: 1.2<14>[ 31.788271] [IGT] kms_vblank: exiting, ret=77
13346 11:50:52.390430 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13347 11:50:52.400429 Opened device: /dev/dri/car<8>[ 31.799691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13348 11:50:52.400513 d0
13349 11:50:52.400769 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13351 11:50:52.407473 No KMS driver or no outputs, pipes: 8, outputs: 0
13352 11:50:52.410302 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13353 11:50:52.420178 <14>[ 31.822426] [IGT] kms_vblank: executing
13354 11:50:52.426692 IGT-Version: 1.2<14>[ 31.827174] [IGT] kms_vblank: exiting, ret=77
13355 11:50:52.429955 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13356 11:50:52.439984 Opened device: /dev/dri/car<8>[ 31.839266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13357 11:50:52.440068 d0
13358 11:50:52.440325 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13360 11:50:52.446216 No KMS driver or no outputs, pipes: 8, outputs: 0
13361 11:50:52.449302 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13362 11:50:52.467523 <14>[ 31.869275] [IGT] kms_vblank: executing
13363 11:50:52.473214 IGT-Version: 1.2<14>[ 31.874449] [IGT] kms_vblank: exiting, ret=77
13364 11:50:52.476596 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13365 11:50:52.486875 Opened device: /dev/dri/car<8>[ 31.886200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13366 11:50:52.486956 d0
13367 11:50:52.487192 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13369 11:50:52.493503 No KMS driver or no outputs, pipes: 8, outputs: 0
13370 11:50:52.496563 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13371 11:50:52.504710 <14>[ 31.907397] [IGT] kms_vblank: executing
13372 11:50:52.511622 IGT-Version: 1.2<14>[ 31.912140] [IGT] kms_vblank: exiting, ret=77
13373 11:50:52.514673 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13374 11:50:52.524702 Opened device: /dev/dri/car<8>[ 31.924343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13375 11:50:52.524784 d0
13376 11:50:52.525021 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13378 11:50:52.531379 No KMS driver or no outputs, pipes: 8, outputs: 0
13379 11:50:52.534561 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13380 11:50:52.552453 <14>[ 31.955097] [IGT] kms_vblank: executing
13381 11:50:52.560055 IGT-Version: 1.2<14>[ 31.960319] [IGT] kms_vblank: exiting, ret=77
13382 11:50:52.563453 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13383 11:50:52.572254 Opened device: /dev/dri/car<8>[ 31.971758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13384 11:50:52.572338 d0
13385 11:50:52.572574 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13387 11:50:52.578753 No KMS driver or no outputs, pipes: 8, outputs: 0
13388 11:50:52.582379 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13389 11:50:52.599341 <14>[ 32.002070] [IGT] kms_vblank: executing
13390 11:50:52.606870 IGT-Version: 1.2<14>[ 32.007476] [IGT] kms_vblank: exiting, ret=77
13391 11:50:52.609416 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13392 11:50:52.619158 Opened device: /dev/dri/car<8>[ 32.018997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13393 11:50:52.619244 d0
13394 11:50:52.619502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13396 11:50:52.625750 No KMS driver or no outputs, pipes: 8, outputs: 0
13397 11:50:52.629185 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13398 11:50:52.637890 <14>[ 32.040409] [IGT] kms_vblank: executing
13399 11:50:52.644221 IGT-Version: 1.2<14>[ 32.045202] [IGT] kms_vblank: exiting, ret=77
13400 11:50:52.647894 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13401 11:50:52.657829 Opened device: /dev/dri/car<8>[ 32.057283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13402 11:50:52.657915 d0
13403 11:50:52.658173 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13405 11:50:52.664705 No KMS driver or no outputs, pipes: 8, outputs: 0
13406 11:50:52.667277 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13407 11:50:52.676701 <14>[ 32.079143] [IGT] kms_vblank: executing
13408 11:50:52.683081 IGT-Version: 1.2<14>[ 32.084025] [IGT] kms_vblank: exiting, ret=77
13409 11:50:52.686169 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13410 11:50:52.696247 Opened device: /dev/dri/car<8>[ 32.096195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13411 11:50:52.696333 d0
13412 11:50:52.696571 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13414 11:50:52.703037 No KMS driver or no outputs, pipes: 8, outputs: 0
13415 11:50:52.706810 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13416 11:50:52.723386 <14>[ 32.126243] [IGT] kms_vblank: executing
13417 11:50:52.730540 IGT-Version: 1.2<14>[ 32.131397] [IGT] kms_vblank: exiting, ret=77
13418 11:50:52.733570 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13419 11:50:52.743619 Opened device: /dev/dri/car<8>[ 32.143033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13420 11:50:52.743792 d0
13421 11:50:52.744077 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13423 11:50:52.749806 No KMS driver or no outputs, pipes: 8, outputs: 0
13424 11:50:52.753465 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13425 11:50:52.760740 <14>[ 32.163697] [IGT] kms_vblank: executing
13426 11:50:52.767822 IGT-Version: 1.2<14>[ 32.168428] [IGT] kms_vblank: exiting, ret=77
13427 11:50:52.771239 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13428 11:50:52.780986 Opened device: /dev/dri/car<8>[ 32.180684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13429 11:50:52.781071 d0
13430 11:50:52.781308 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13432 11:50:52.787595 No KMS driver or no outputs, pipes: 8, outputs: 0
13433 11:50:52.790670 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13434 11:50:52.808237 <14>[ 32.210761] [IGT] kms_vblank: executing
13435 11:50:52.814797 IGT-Version: 1.2<14>[ 32.215887] [IGT] kms_vblank: exiting, ret=77
13436 11:50:52.818616 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13437 11:50:52.827707 Opened device: /dev/dri/car<8>[ 32.227493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13438 11:50:52.827790 d0
13439 11:50:52.828027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13441 11:50:52.834299 No KMS driver or no outputs, pipes: 8, outputs: 0
13442 11:50:52.837597 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13443 11:50:52.855632 <14>[ 32.258453] [IGT] kms_vblank: executing
13444 11:50:52.862285 IGT-Version: 1.2<14>[ 32.263602] [IGT] kms_vblank: exiting, ret=77
13445 11:50:52.865514 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13446 11:50:52.875404 Opened device: /dev/dri/car<8>[ 32.274981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13447 11:50:52.875487 d0
13448 11:50:52.875724 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13450 11:50:52.882583 No KMS driver or no outputs, pipes: 8, outputs: 0
13451 11:50:52.885511 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13452 11:50:52.903966 <14>[ 32.306451] [IGT] kms_vblank: executing
13453 11:50:52.910376 IGT-Version: 1.2<14>[ 32.313247] [IGT] kms_vblank: exiting, ret=77
13454 11:50:52.913594 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13455 11:50:52.916998 Opened device: /dev/dri/card0
13456 11:50:52.926911 No KMS driver or no outputs,<8>[ 32.326571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13457 11:50:52.927168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13459 11:50:52.930473 pipes: 8, outputs: 0
13460 11:50:52.936639 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13461 11:50:52.947665 <14>[ 32.350406] [IGT] kms_vblank: executing
13462 11:50:52.954444 IGT-Version: 1.2<14>[ 32.355250] [IGT] kms_vblank: exiting, ret=77
13463 11:50:52.957658 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13464 11:50:52.967482 Opened device: /dev/dri/car<8>[ 32.367712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13465 11:50:52.967750 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13467 11:50:52.970931 d0
13468 11:50:52.974863 No KMS driver or no outputs, pipes: 8, outputs: 0
13469 11:50:52.980851 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13470 11:50:52.983844 <14>[ 32.388765] [IGT] kms_vblank: executing
13471 11:50:52.991210 IGT-Version: 1.2<14>[ 32.393645] [IGT] kms_vblank: exiting, ret=77
13472 11:50:52.998211 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13473 11:50:53.006992 Opened device: /dev/dri/car<8>[ 32.406134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13474 11:50:53.007077 d0
13475 11:50:53.007334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13477 11:50:53.014059 No KMS driver or no outputs, pipes: 8, outputs: 0
13478 11:50:53.017263 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13479 11:50:53.024633 <14>[ 32.426986] [IGT] kms_vblank: executing
13480 11:50:53.030753 IGT-Version: 1.2<14>[ 32.431686] [IGT] kms_vblank: exiting, ret=77
13481 11:50:53.034670 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13482 11:50:53.044644 Opened device: /dev/dri/car<8>[ 32.444035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13483 11:50:53.044904 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13485 11:50:53.047632 d0
13486 11:50:53.050934 No KMS driver or no outputs, pipes: 8, outputs: 0
13487 11:50:53.057552 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13488 11:50:53.063648 <14>[ 32.466349] [IGT] kms_vblank: executing
13489 11:50:53.070377 IGT-Version: 1.2<14>[ 32.471245] [IGT] kms_vblank: exiting, ret=77
13490 11:50:53.073455 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13491 11:50:53.083458 Opened device: /dev/dri/car<8>[ 32.482753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13492 11:50:53.083732 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13494 11:50:53.087041 d0
13495 11:50:53.089989 No KMS driver or no outputs, pipes: 8, outputs: 0
13496 11:50:53.096290 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13497 11:50:53.099946 <14>[ 32.504676] [IGT] kms_vblank: executing
13498 11:50:53.107018 IGT-Version: 1.2<14>[ 32.509683] [IGT] kms_vblank: exiting, ret=77
13499 11:50:53.112969 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13500 11:50:53.122904 Opened device: /dev/dri/car<8>[ 32.521501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13501 11:50:53.123040 d0
13502 11:50:53.123327 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13504 11:50:53.129404 No KMS driver or no outputs, pipes: 8, outputs: 0
13505 11:50:53.133968 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13506 11:50:53.140965 <14>[ 32.543440] [IGT] kms_vblank: executing
13507 11:50:53.147516 IGT-Version: 1.2<14>[ 32.548197] [IGT] kms_vblank: exiting, ret=77
13508 11:50:53.150415 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13509 11:50:53.160547 Opened device: /dev/dri/car<8>[ 32.559430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13510 11:50:53.160865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13512 11:50:53.164169 d0
13513 11:50:53.167585 No KMS driver or no outputs, pipes: 8, outputs: 0
13514 11:50:53.173910 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13515 11:50:53.178219 <14>[ 32.582040] [IGT] kms_vblank: executing
13516 11:50:53.184259 IGT-Version: 1.2<14>[ 32.586858] [IGT] kms_vblank: exiting, ret=77
13517 11:50:53.190629 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13518 11:50:53.200817 Opened device: /dev/dri/car<8>[ 32.599004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13519 11:50:53.200951 d0
13520 11:50:53.201235 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13522 11:50:53.207102 No KMS driver or no outputs, pipes: 8, outputs: 0
13523 11:50:53.210078 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13524 11:50:53.219644 <14>[ 32.622469] [IGT] kms_vblank: executing
13525 11:50:53.226945 IGT-Version: 1.2<14>[ 32.627304] [IGT] kms_vblank: exiting, ret=77
13526 11:50:53.229753 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13527 11:50:53.239947 Opened device: /dev/dri/car<8>[ 32.638683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13528 11:50:53.240062 d0
13529 11:50:53.240330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13531 11:50:53.246039 No KMS driver or no outputs, pipes: 8, outputs: 0
13532 11:50:53.249324 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13533 11:50:53.257270 <14>[ 32.660158] [IGT] kms_vblank: executing
13534 11:50:53.264377 IGT-Version: 1.2<14>[ 32.664956] [IGT] kms_vblank: exiting, ret=77
13535 11:50:53.267825 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13536 11:50:53.277958 Opened device: /dev/dri/car<8>[ 32.676501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13537 11:50:53.278059 d0
13538 11:50:53.278364 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13540 11:50:53.283811 No KMS driver or no outputs, pipes: 8, outputs: 0
13541 11:50:53.287188 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13542 11:50:53.294829 <14>[ 32.696847] [IGT] kms_vblank: executing
13543 11:50:53.301057 IGT-Version: 1.2<14>[ 32.701714] [IGT] kms_vblank: exiting, ret=77
13544 11:50:53.304167 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13545 11:50:53.313667 Opened device: /dev/dri/car<8>[ 32.713636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13546 11:50:53.313800 d0
13547 11:50:53.314082 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13549 11:50:53.320306 No KMS driver or no outputs, pipes: 8, outputs: 0
13550 11:50:53.323557 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13551 11:50:53.331819 <14>[ 32.734463] [IGT] kms_vblank: executing
13552 11:50:53.338683 IGT-Version: 1.2<14>[ 32.739189] [IGT] kms_vblank: exiting, ret=77
13553 11:50:53.342693 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13554 11:50:53.351742 Opened device: /dev/dri/car<8>[ 32.750780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13555 11:50:53.351871 d0
13556 11:50:53.352154 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13558 11:50:53.358241 No KMS driver or no outputs, pipes: 8, outputs: 0
13559 11:50:53.361835 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13560 11:50:53.369411 <14>[ 32.771826] [IGT] kms_vblank: executing
13561 11:50:53.375797 IGT-Version: 1.2<14>[ 32.776628] [IGT] kms_vblank: exiting, ret=77
13562 11:50:53.378993 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13563 11:50:53.388836 Opened device: /dev/dri/car<8>[ 32.788859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13564 11:50:53.388979 d0
13565 11:50:53.389266 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13567 11:50:53.395762 No KMS driver or no outputs, pipes: 8, outputs: 0
13568 11:50:53.398914 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13569 11:50:53.406967 <14>[ 32.809533] [IGT] kms_vblank: executing
13570 11:50:53.413224 IGT-Version: 1.2<14>[ 32.814272] [IGT] kms_vblank: exiting, ret=77
13571 11:50:53.417182 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13572 11:50:53.426712 Opened device: /dev/dri/car<8>[ 32.825717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13573 11:50:53.426853 d0
13574 11:50:53.427139 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13576 11:50:53.430213 No KMS driver or no outputs, pipes: 8, outputs: 0
13577 11:50:53.436340 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13578 11:50:53.443901 <14>[ 32.846763] [IGT] kms_vblank: executing
13579 11:50:53.450844 IGT-Version: 1.2<14>[ 32.851509] [IGT] kms_vblank: exiting, ret=77
13580 11:50:53.454159 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13581 11:50:53.464218 Opened device: /dev/dri/car<8>[ 32.862820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13582 11:50:53.464332 d0
13583 11:50:53.464603 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13585 11:50:53.471020 No KMS driver or no outputs, pipes: 8, outputs: 0
13586 11:50:53.474213 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13587 11:50:53.485100 <14>[ 32.887497] [IGT] kms_vblank: executing
13588 11:50:53.491433 IGT-Version: 1.2<14>[ 32.892212] [IGT] kms_vblank: exiting, ret=77
13589 11:50:53.495426 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13590 11:50:53.504972 Opened device: /dev/dri/car<8>[ 32.903598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13591 11:50:53.505115 d0
13592 11:50:53.505401 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13594 11:50:53.511034 No KMS driver or no outputs, pipes: 8, outputs: 0
13595 11:50:53.514148 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13596 11:50:53.522965 <14>[ 32.925458] [IGT] kms_vblank: executing
13597 11:50:53.529219 IGT-Version: 1.2<14>[ 32.930208] [IGT] kms_vblank: exiting, ret=77
13598 11:50:53.532930 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13599 11:50:53.542512 Opened device: /dev/dri/car<8>[ 32.942397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13600 11:50:53.542653 d0
13601 11:50:53.542937 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13603 11:50:53.549237 No KMS driver or no outputs, pipes: 8, outputs: 0
13604 11:50:53.552387 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13605 11:50:53.561152 <14>[ 32.963715] [IGT] kms_vblank: executing
13606 11:50:53.567984 IGT-Version: 1.2<14>[ 32.968473] [IGT] kms_vblank: exiting, ret=77
13607 11:50:53.570631 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13608 11:50:53.580847 Opened device: /dev/dri/car<8>[ 32.980539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13609 11:50:53.581002 d0
13610 11:50:53.581285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13612 11:50:53.584082 No KMS driver or no outputs, pipes: 8, outputs: 0
13613 11:50:53.590625 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13614 11:50:53.598441 <14>[ 33.000454] [IGT] kms_vblank: executing
13615 11:50:53.604483 IGT-Version: 1.2<14>[ 33.005309] [IGT] kms_vblank: exiting, ret=77
13616 11:50:53.607659 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13617 11:50:53.617649 Opened device: /dev/dri/car<8>[ 33.016558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13618 11:50:53.617797 d0
13619 11:50:53.618080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13621 11:50:53.624825 No KMS driver or no outputs, pipes: 8, outputs: 0
13622 11:50:53.627352 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13623 11:50:53.636144 <14>[ 33.038079] [IGT] kms_vblank: executing
13624 11:50:53.641979 IGT-Version: 1.2<14>[ 33.042783] [IGT] kms_vblank: exiting, ret=77
13625 11:50:53.645506 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13626 11:50:53.654938 Opened device: /dev/dri/car<8>[ 33.054160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13627 11:50:53.655057 d0
13628 11:50:53.655340 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13630 11:50:53.661986 No KMS driver or no outputs, pipes: 8, outputs: 0
13631 11:50:53.664685 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13632 11:50:53.673014 <14>[ 33.075258] [IGT] kms_vblank: executing
13633 11:50:53.679444 IGT-Version: 1.2<14>[ 33.080020] [IGT] kms_vblank: exiting, ret=77
13634 11:50:53.683892 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13635 11:50:53.692350 Opened device: /dev/dri/car<8>[ 33.092302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13636 11:50:53.692470 d0
13637 11:50:53.692739 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13639 11:50:53.698836 No KMS driver or no outputs, pipes: 8, outputs: 0
13640 11:50:53.702545 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13641 11:50:53.720864 <14>[ 33.123519] [IGT] kms_vblank: executing
13642 11:50:53.727584 IGT-Version: 1.2<14>[ 33.128568] [IGT] kms_vblank: exiting, ret=77
13643 11:50:53.731021 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13644 11:50:53.740785 Opened device: /dev/dri/car<8>[ 33.140857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13645 11:50:53.740904 d0
13646 11:50:53.741177 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13648 11:50:53.744023 No KMS driver or no outputs, pipes: 8, outputs: 0
13649 11:50:53.750303 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13650 11:50:53.761798 <14>[ 33.164111] [IGT] kms_vblank: executing
13651 11:50:53.768151 IGT-Version: 1.2<14>[ 33.168903] [IGT] kms_vblank: exiting, ret=77
13652 11:50:53.771490 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13653 11:50:53.781482 Opened devi<8>[ 33.179357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13654 11:50:53.781608 ce: /dev/dri/card0
13655 11:50:53.781881 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13657 11:50:53.788113 No KMS driver or no outputs, pipes: 8, outputs: 0
13658 11:50:53.790879 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13659 11:50:53.808687 <14>[ 33.211031] [IGT] kms_vblank: executing
13660 11:50:53.815008 IGT-Version: 1.2<14>[ 33.216190] [IGT] kms_vblank: exiting, ret=77
13661 11:50:53.818576 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13662 11:50:53.828361 Opened device: /dev/dri/car<8>[ 33.227331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13663 11:50:53.828489 d0
13664 11:50:53.828766 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13666 11:50:53.835504 No KMS driver or no outputs, pipes: 8, outputs: 0
13667 11:50:53.838358 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13668 11:50:53.849676 <14>[ 33.251857] [IGT] kms_vblank: executing
13669 11:50:53.855575 IGT-Version: 1.2<14>[ 33.256553] [IGT] kms_vblank: exiting, ret=77
13670 11:50:53.859116 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13671 11:50:53.869120 Opened devi<8>[ 33.267092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13672 11:50:53.869245 ce: /dev/dri/card0
13673 11:50:53.869518 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13675 11:50:53.875163 No KMS driver or no outputs, pipes: 8, outputs: 0
13676 11:50:53.879427 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13677 11:50:53.896514 <14>[ 33.299487] [IGT] kms_vblank: executing
13678 11:50:53.904490 IGT-Version: 1.2<14>[ 33.304476] [IGT] kms_vblank: exiting, ret=77
13679 11:50:53.907758 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13680 11:50:53.917400 Opened device: /dev/dri/car<8>[ 33.315829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13681 11:50:53.917522 d0
13682 11:50:53.917771 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13684 11:50:53.923326 No KMS driver or no outputs, pipes: 8, outputs: 0
13685 11:50:53.926597 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13686 11:50:53.945898 <14>[ 33.348369] [IGT] kms_vblank: executing
13687 11:50:53.952151 IGT-Version: 1.2<14>[ 33.353502] [IGT] kms_vblank: exiting, ret=77
13688 11:50:53.955503 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13689 11:50:53.958681 Opened device: /dev/dri/card0
13690 11:50:53.968912 No KMS drive<8>[ 33.365879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13691 11:50:53.969216 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13693 11:50:53.972003 r or no outputs, pipes: 8, outputs: 0
13694 11:50:53.979612 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13695 11:50:53.985511 <14>[ 33.388483] [IGT] kms_vblank: executing
13696 11:50:53.992107 IGT-Version: 1.2<14>[ 33.393270] [IGT] kms_vblank: exiting, ret=77
13697 11:50:53.996045 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13698 11:50:54.005223 Opened device: /dev/dri/car<8>[ 33.405211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13699 11:50:54.005527 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13701 11:50:54.008789 d0
13702 11:50:54.012005 No KMS driver or no outputs, pipes: 8, outputs: 0
13703 11:50:54.018862 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13704 11:50:54.026844 <14>[ 33.428279] [IGT] kms_vblank: executing
13705 11:50:54.032052 IGT-Version: 1.2<14>[ 33.433063] [IGT] kms_vblank: exiting, ret=77
13706 11:50:54.035828 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13707 11:50:54.045173 Opened device: /dev/dri/car<8>[ 33.444333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13708 11:50:54.045475 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13710 11:50:54.048746 d0
13711 11:50:54.051720 No KMS driver or no outputs, pipes: 8, outputs: 0
13712 11:50:54.058795 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13713 11:50:54.065423 <14>[ 33.467062] [IGT] kms_vblank: executing
13714 11:50:54.068892 IGT-Version: 1.2<14>[ 33.471788] [IGT] kms_vblank: exiting, ret=77
13715 11:50:54.074961 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13716 11:50:54.085468 Opened device: /dev/dri/car<8>[ 33.483056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13717 11:50:54.085594 d0
13718 11:50:54.085845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13720 11:50:54.091599 No KMS driver or no outputs, pipes: 8, outputs: 0
13721 11:50:54.094860 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13722 11:50:54.105337 <14>[ 33.508073] [IGT] kms_vblank: executing
13723 11:50:54.112484 IGT-Version: 1.2<14>[ 33.512896] [IGT] kms_vblank: exiting, ret=77
13724 11:50:54.115526 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13725 11:50:54.125420 Opened devi<8>[ 33.524065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13726 11:50:54.125545 ce: /dev/dri/card0
13727 11:50:54.125792 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13729 11:50:54.132295 No KMS driver or no outputs, pipes: 8, outputs: 0
13730 11:50:54.135125 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13731 11:50:54.142500 <14>[ 33.544701] [IGT] kms_vblank: executing
13732 11:50:54.148634 IGT-Version: 1.2<14>[ 33.549568] [IGT] kms_vblank: exiting, ret=77
13733 11:50:54.151927 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13734 11:50:54.161708 Opened device: /dev/dri/car<8>[ 33.561561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13735 11:50:54.162004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13737 11:50:54.165067 d0
13738 11:50:54.168736 No KMS driver or no outputs, pipes: 8, outputs: 0
13739 11:50:54.174684 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13740 11:50:54.183946 <14>[ 33.586505] [IGT] kms_vblank: executing
13741 11:50:54.190365 IGT-Version: 1.2<14>[ 33.591317] [IGT] kms_vblank: exiting, ret=77
13742 11:50:54.194532 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13743 11:50:54.203452 Opened device: /dev/dri/car<8>[ 33.602729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13744 11:50:54.203752 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13746 11:50:54.206864 d0
13747 11:50:54.210680 No KMS driver or no outputs, pipes: 8, outputs: 0
13748 11:50:54.216560 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13749 11:50:54.226165 <14>[ 33.628142] [IGT] kms_vblank: executing
13750 11:50:54.232100 IGT-Version: 1.2<14>[ 33.632841] [IGT] kms_vblank: exiting, ret=77
13751 11:50:54.235275 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13752 11:50:54.245104 Opened devi<8>[ 33.644064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13753 11:50:54.245226 ce: /dev/dri/card0
13754 11:50:54.245469 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13756 11:50:54.251967 No KMS driver or no outputs, pipes: 8, outputs: 0
13757 11:50:54.254817 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13758 11:50:54.262717 <14>[ 33.664110] [IGT] kms_vblank: executing
13759 11:50:54.268426 IGT-Version: 1.2<14>[ 33.668831] [IGT] kms_vblank: exiting, ret=77
13760 11:50:54.271986 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13761 11:50:54.281624 Opened device: /dev/dri/car<8>[ 33.680145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13762 11:50:54.281757 d0
13763 11:50:54.282004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13765 11:50:54.284903 No KMS driver or no outputs, pipes: 8, outputs: 0
13766 11:50:54.291448 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13767 11:50:54.301143 <14>[ 33.704063] [IGT] kms_vblank: executing
13768 11:50:54.307695 IGT-Version: 1.2<14>[ 33.708900] [IGT] kms_vblank: exiting, ret=77
13769 11:50:54.311196 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13770 11:50:54.321363 Opened devi<8>[ 33.719999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13771 11:50:54.321488 ce: /dev/dri/card0
13772 11:50:54.321735 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13774 11:50:54.328298 No KMS driver or no outputs, pipes: 8, outputs: 0
13775 11:50:54.330947 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13776 11:50:54.338211 <14>[ 33.740281] [IGT] kms_vblank: executing
13777 11:50:54.344380 IGT-Version: 1.2<14>[ 33.745072] [IGT] kms_vblank: exiting, ret=77
13778 11:50:54.347606 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13779 11:50:54.357092 Opened devi<8>[ 33.756180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13780 11:50:54.357214 ce: /dev/dri/card0
13781 11:50:54.357461 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13783 11:50:54.363654 No KMS driver or no outputs, pipes: 8, outputs: 0
13784 11:50:54.366904 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13785 11:50:54.373638 <14>[ 33.776036] [IGT] kms_vblank: executing
13786 11:50:54.381286 IGT-Version: 1.2<14>[ 33.780851] [IGT] kms_vblank: exiting, ret=77
13787 11:50:54.383791 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13788 11:50:54.393773 Opened device: /dev/dri/car<8>[ 33.792252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13789 11:50:54.393902 d0
13790 11:50:54.394145 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13792 11:50:54.397316 No KMS driver or no outputs, pipes: 8, outputs: 0
13793 11:50:54.403661 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13794 11:50:54.412714 <14>[ 33.815468] [IGT] kms_vblank: executing
13795 11:50:54.419255 IGT-Version: 1.2<14>[ 33.820309] [IGT] kms_vblank: exiting, ret=77
13796 11:50:54.422504 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13797 11:50:54.434451 Opened device: /dev/dri/car<8>[ 33.831567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13798 11:50:54.434583 d0
13799 11:50:54.434830 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13801 11:50:54.436908 No KMS driver or no outputs, pipes: 8, outputs: 0
13802 11:50:54.442904 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13803 11:50:54.449711 <14>[ 33.852539] [IGT] kms_vblank: executing
13804 11:50:54.456543 IGT-Version: 1.2<14>[ 33.857353] [IGT] kms_vblank: exiting, ret=77
13805 11:50:54.459559 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13806 11:50:54.469846 Opened device: /dev/dri/car<8>[ 33.869461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13807 11:50:54.469973 d0
13808 11:50:54.470220 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13810 11:50:54.476366 No KMS driver or no outputs, pipes: 8, outputs: 0
13811 11:50:54.479605 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13812 11:50:54.489823 <14>[ 33.892837] [IGT] kms_vblank: executing
13813 11:50:54.497128 IGT-Version: 1.2<14>[ 33.897662] [IGT] kms_vblank: exiting, ret=77
13814 11:50:54.500239 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13815 11:50:54.510086 Opened devi<8>[ 33.908698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13816 11:50:54.510214 ce: /dev/dri/card0
13817 11:50:54.510470 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13819 11:50:54.516552 No KMS driver or no outputs, pipes: 8, outputs: 0
13820 11:50:54.520077 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13821 11:50:54.526391 <14>[ 33.929171] [IGT] kms_vblank: executing
13822 11:50:54.533906 IGT-Version: 1.2<14>[ 33.933888] [IGT] kms_vblank: exiting, ret=77
13823 11:50:54.536203 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13824 11:50:54.546603 Opened device: /dev/dri/car<8>[ 33.946016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13825 11:50:54.546725 d0
13826 11:50:54.546973 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13828 11:50:54.553054 No KMS driver or no outputs, pipes: 8, outputs: 0
13829 11:50:54.556551 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13830 11:50:54.568543 <14>[ 33.970582] [IGT] kms_vblank: executing
13831 11:50:54.574417 IGT-Version: 1.2<14>[ 33.975391] [IGT] kms_vblank: exiting, ret=77
13832 11:50:54.577708 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13833 11:50:54.587663 Opened device: /dev/dri/car<8>[ 33.986767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13834 11:50:54.587791 d0
13835 11:50:54.588037 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13837 11:50:54.591141 No KMS driver or no outputs, pipes: 8, outputs: 0
13838 11:50:54.597224 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13839 11:50:54.607694 <14>[ 34.010658] [IGT] kms_vblank: executing
13840 11:50:54.614911 IGT-Version: 1.2<14>[ 34.015455] [IGT] kms_vblank: exiting, ret=77
13841 11:50:54.617560 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13842 11:50:54.627392 Opened device: /dev/dri/car<8>[ 34.026831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13843 11:50:54.627513 d0
13844 11:50:54.627760 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13846 11:50:54.634175 No KMS driver or no outputs, pipes: 8, outputs: 0
13847 11:50:54.637351 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13848 11:50:54.648664 <14>[ 34.051594] [IGT] kms_vblank: executing
13849 11:50:54.655550 IGT-Version: 1.2<14>[ 34.056310] [IGT] kms_vblank: exiting, ret=77
13850 11:50:54.658750 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13851 11:50:54.669050 Opened device: /dev/dri/car<8>[ 34.067729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13852 11:50:54.669177 d0
13853 11:50:54.669427 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13855 11:50:54.672632 No KMS driver or no outputs, pipes: 8, outputs: 0
13856 11:50:54.678854 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13857 11:50:54.685482 <14>[ 34.088128] [IGT] kms_vblank: executing
13858 11:50:54.691821 IGT-Version: 1.2<14>[ 34.092916] [IGT] kms_vblank: exiting, ret=77
13859 11:50:54.695134 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13860 11:50:54.704950 Opened device: /dev/dri/car<8>[ 34.104192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13861 11:50:54.705081 d0
13862 11:50:54.705328 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13864 11:50:54.711710 No KMS driver or no outputs, pipes: 8, outputs: 0
13865 11:50:54.714846 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13866 11:50:54.722950 <14>[ 34.125645] [IGT] kms_vblank: executing
13867 11:50:54.729359 IGT-Version: 1.2<14>[ 34.130339] [IGT] kms_vblank: exiting, ret=77
13868 11:50:54.732803 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13869 11:50:54.742854 Opened device: /dev/dri/car<8>[ 34.141713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13870 11:50:54.742993 d0
13871 11:50:54.743240 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13873 11:50:54.746010 No KMS driver or no outputs, pipes: 8, outputs: 0
13874 11:50:54.752531 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13875 11:50:54.759779 <14>[ 34.162401] [IGT] kms_vblank: executing
13876 11:50:54.766558 IGT-Version: 1.2<14>[ 34.167178] [IGT] kms_vblank: exiting, ret=77
13877 11:50:54.769582 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13878 11:50:54.772864 Opened device: /dev/dri/card0
13879 11:50:54.779274 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13881 11:50:54.783101 No KMS drive<8>[ 34.180215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13882 11:50:54.785800 r or no outputs, pipes: 8, outputs: 0
13883 11:50:54.789116 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13884 11:50:54.799291 <14>[ 34.202182] [IGT] kms_vblank: executing
13885 11:50:54.805806 IGT-Version: 1.2<14>[ 34.206963] [IGT] kms_vblank: exiting, ret=77
13886 11:50:54.809222 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13887 11:50:54.812563 Opened device: /dev/dri/card0
13888 11:50:54.822407 No KMS drive<8>[ 34.219649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13889 11:50:54.822727 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13891 11:50:54.825362 r or no outputs, pipes: 8, outputs: 0
13892 11:50:54.828683 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13893 11:50:54.839606 <14>[ 34.242129] [IGT] kms_vblank: executing
13894 11:50:54.846184 IGT-Version: 1.2<14>[ 34.246831] [IGT] kms_vblank: exiting, ret=77
13895 11:50:54.849415 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13896 11:50:54.859015 Opened device: /dev/dri/car<8>[ 34.258253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13897 11:50:54.859138 d0
13898 11:50:54.859383 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13900 11:50:54.866505 No KMS driver or no outputs, pipes: 8, outputs: 0
13901 11:50:54.870147 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13902 11:50:54.877856 <14>[ 34.280202] [IGT] kms_vblank: executing
13903 11:50:54.884095 IGT-Version: 1.2<14>[ 34.284953] [IGT] kms_vblank: exiting, ret=77
13904 11:50:54.887857 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13905 11:50:54.897036 Opened device: /dev/dri/car<8>[ 34.297341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13906 11:50:54.897159 d0
13907 11:50:54.897404 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13909 11:50:54.903775 No KMS driver or no outputs, pipes: 8, outputs: 0
13910 11:50:54.907191 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13911 11:50:54.915676 <14>[ 34.318528] [IGT] kms_vblank: executing
13912 11:50:54.922072 IGT-Version: 1.2<14>[ 34.323290] [IGT] kms_vblank: exiting, ret=77
13913 11:50:54.925790 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13914 11:50:54.936363 Opened device: /dev/dri/car<8>[ 34.335365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13915 11:50:54.936684 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13917 11:50:54.939350 d0
13918 11:50:54.943068 No KMS driver or no outputs, pipes: 8, outputs: 0
13919 11:50:54.948334 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13920 11:50:54.964375 <14>[ 34.366610] [IGT] kms_vblank: executing
13921 11:50:54.970517 IGT-Version: 1.2<14>[ 34.371700] [IGT] kms_vblank: exiting, ret=77
13922 11:50:54.973727 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13923 11:50:54.983766 Opened device: /dev/dri/car<8>[ 34.382927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13924 11:50:54.984079 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13926 11:50:54.986813 d0
13927 11:50:54.989953 No KMS driver or no outputs, pipes: 8, outputs: 0
13928 11:50:54.996945 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13929 11:50:55.005708 <14>[ 34.408353] [IGT] kms_vblank: executing
13930 11:50:55.011827 IGT-Version: 1.2<14>[ 34.413179] [IGT] kms_vblank: exiting, ret=77
13931 11:50:55.015639 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13932 11:50:55.025642 Opened device: /dev/dri/car<8>[ 34.424399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13933 11:50:55.025964 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13935 11:50:55.028514 d0
13936 11:50:55.032473 No KMS driver or no outputs, pipes: 8, outputs: 0
13937 11:50:55.038288 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13938 11:50:55.042218 <14>[ 34.446930] [IGT] kms_vblank: executing
13939 11:50:55.048702 IGT-Version: 1.2<14>[ 34.451696] [IGT] kms_vblank: exiting, ret=77
13940 11:50:55.054816 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13941 11:50:55.064778 Opened device: /dev/dri/car<8>[ 34.463073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13942 11:50:55.064908 d0
13943 11:50:55.065155 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13945 11:50:55.071573 No KMS driver or no outputs, pipes: 8, outputs: 0
13946 11:50:55.074830 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13947 11:50:55.085461 <14>[ 34.488026] [IGT] kms_vblank: executing
13948 11:50:55.091672 IGT-Version: 1.2<14>[ 34.492730] [IGT] kms_vblank: exiting, ret=77
13949 11:50:55.094990 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13950 11:50:55.104804 Opened devi<8>[ 34.503058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13951 11:50:55.104932 ce: /dev/dri/card0
13952 11:50:55.105181 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13954 11:50:55.111627 No KMS driver or no outputs, pipes: 8, outputs: 0
13955 11:50:55.114816 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13956 11:50:55.132576 <14>[ 34.535160] [IGT] kms_vblank: executing
13957 11:50:55.138880 IGT-Version: 1.2<14>[ 34.540249] [IGT] kms_vblank: exiting, ret=77
13958 11:50:55.141981 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13959 11:50:55.145523 Opened device: /dev/dri/card0
13960 11:50:55.155728 No KMS drive<8>[ 34.552966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13961 11:50:55.156035 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13963 11:50:55.158946 r or no outputs, pipes: 8, outputs: 0
13964 11:50:55.164831 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13965 11:50:55.172738 <14>[ 34.575662] [IGT] kms_vblank: executing
13966 11:50:55.179870 IGT-Version: 1.2<14>[ 34.580420] [IGT] kms_vblank: exiting, ret=77
13967 11:50:55.182615 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13968 11:50:55.192546 Opened device: /dev/dri/car<8>[ 34.591681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13969 11:50:55.192948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13971 11:50:55.196478 d0
13972 11:50:55.199435 No KMS drive<8>[ 34.603290] <LAVA_SIGNAL_TESTSET STOP>
13973 11:50:55.199699 Received signal: <TESTSET> STOP
13974 11:50:55.199772 Closing test_set kms_vblank
13975 11:50:55.209832 r or no outputs,<8>[ 34.608161] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12074051_1.5.2.3.1>
13976 11:50:55.209957 pipes: 8, outputs: 0
13977 11:50:55.210199 Received signal: <ENDRUN> 0_igt-kms-mediatek 12074051_1.5.2.3.1
13978 11:50:55.210314 Ending use of test pattern.
13979 11:50:55.210390 Ending test lava.0_igt-kms-mediatek (12074051_1.5.2.3.1), duration 14.13
13981 11:50:55.215773 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13982 11:50:55.215861 + set +x
13983 11:50:55.218572 <LAVA_TEST_RUNNER EXIT>
13984 11:50:55.218833 ok: lava_test_shell seems to have completed
13985 11:50:55.222717 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13986 11:50:55.222961 end: 3.1 lava-test-shell (duration 00:00:15) [common]
13987 11:50:55.223056 end: 3 lava-test-retry (duration 00:00:15) [common]
13988 11:50:55.223148 start: 4 finalize (timeout 00:06:49) [common]
13989 11:50:55.223238 start: 4.1 power-off (timeout 00:00:30) [common]
13990 11:50:55.223393 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
13991 11:50:55.299887 >> Command sent successfully.
13992 11:50:55.302505 Returned 0 in 0 seconds
13993 11:50:55.402922 end: 4.1 power-off (duration 00:00:00) [common]
13995 11:50:55.403271 start: 4.2 read-feedback (timeout 00:06:49) [common]
13996 11:50:55.403542 Listened to connection for namespace 'common' for up to 1s
13997 11:50:56.404507 Finalising connection for namespace 'common'
13998 11:50:56.404691 Disconnecting from shell: Finalise
13999 11:50:56.404769 / #
14000 11:50:56.505115 end: 4.2 read-feedback (duration 00:00:01) [common]
14001 11:50:56.505296 end: 4 finalize (duration 00:00:01) [common]
14002 11:50:56.505446 Cleaning after the job
14003 11:50:56.505547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/ramdisk
14004 11:50:56.513621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/kernel
14005 11:50:56.522481 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/dtb
14006 11:50:56.522713 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074051/tftp-deploy-i2r_xse5/modules
14007 11:50:56.529968 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074051
14008 11:50:56.648131 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074051
14009 11:50:56.648314 Job finished correctly