Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 37
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:43:42.370670 lava-dispatcher, installed at version: 2023.10
2 11:43:42.370901 start: 0 validate
3 11:43:42.371037 Start time: 2023-11-24 11:43:42.371029+00:00 (UTC)
4 11:43:42.371173 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:43:42.371319 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:43:42.638194 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:43:42.638366 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:09.907155 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:09.907336 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:10.175237 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:10.175448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:44:10.707200 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:44:10.707377 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:44:12.706691 validate duration: 30.34
16 11:44:12.706957 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:44:12.707054 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:44:12.707142 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:44:12.707267 Not decompressing ramdisk as can be used compressed.
20 11:44:12.707351 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:44:12.707414 saving as /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/ramdisk/initrd.cpio.gz
22 11:44:12.707478 total size: 4665395 (4 MB)
23 11:44:12.973079 progress 0 % (0 MB)
24 11:44:12.974645 progress 5 % (0 MB)
25 11:44:12.975961 progress 10 % (0 MB)
26 11:44:12.977289 progress 15 % (0 MB)
27 11:44:12.978557 progress 20 % (0 MB)
28 11:44:12.979817 progress 25 % (1 MB)
29 11:44:12.981110 progress 30 % (1 MB)
30 11:44:12.982358 progress 35 % (1 MB)
31 11:44:12.983608 progress 40 % (1 MB)
32 11:44:12.985058 progress 45 % (2 MB)
33 11:44:12.986314 progress 50 % (2 MB)
34 11:44:12.987559 progress 55 % (2 MB)
35 11:44:12.988900 progress 60 % (2 MB)
36 11:44:12.990177 progress 65 % (2 MB)
37 11:44:12.991468 progress 70 % (3 MB)
38 11:44:12.992768 progress 75 % (3 MB)
39 11:44:12.994015 progress 80 % (3 MB)
40 11:44:12.995463 progress 85 % (3 MB)
41 11:44:12.996758 progress 90 % (4 MB)
42 11:44:12.998005 progress 95 % (4 MB)
43 11:44:12.999300 progress 100 % (4 MB)
44 11:44:12.999471 4 MB downloaded in 0.29 s (15.24 MB/s)
45 11:44:12.999640 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:44:12.999909 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:44:13.000036 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:44:13.000163 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:44:13.000387 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:44:13.000490 saving as /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/kernel/Image
52 11:44:13.000590 total size: 49107456 (46 MB)
53 11:44:13.000692 No compression specified
54 11:44:13.002362 progress 0 % (0 MB)
55 11:44:13.015284 progress 5 % (2 MB)
56 11:44:13.028618 progress 10 % (4 MB)
57 11:44:13.041937 progress 15 % (7 MB)
58 11:44:13.054996 progress 20 % (9 MB)
59 11:44:13.067982 progress 25 % (11 MB)
60 11:44:13.080779 progress 30 % (14 MB)
61 11:44:13.093746 progress 35 % (16 MB)
62 11:44:13.106945 progress 40 % (18 MB)
63 11:44:13.120444 progress 45 % (21 MB)
64 11:44:13.133974 progress 50 % (23 MB)
65 11:44:13.147545 progress 55 % (25 MB)
66 11:44:13.161418 progress 60 % (28 MB)
67 11:44:13.174706 progress 65 % (30 MB)
68 11:44:13.187717 progress 70 % (32 MB)
69 11:44:13.201334 progress 75 % (35 MB)
70 11:44:13.215338 progress 80 % (37 MB)
71 11:44:13.229664 progress 85 % (39 MB)
72 11:44:13.243654 progress 90 % (42 MB)
73 11:44:13.256931 progress 95 % (44 MB)
74 11:44:13.269844 progress 100 % (46 MB)
75 11:44:13.270116 46 MB downloaded in 0.27 s (173.76 MB/s)
76 11:44:13.270297 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:44:13.270580 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:44:13.270687 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:44:13.270796 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:44:13.270957 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:44:13.271035 saving as /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/dtb/mt8192-asurada-spherion-r0.dtb
83 11:44:13.271138 total size: 47278 (0 MB)
84 11:44:13.271241 No compression specified
85 11:44:13.272806 progress 69 % (0 MB)
86 11:44:13.273102 progress 100 % (0 MB)
87 11:44:13.273278 0 MB downloaded in 0.00 s (21.09 MB/s)
88 11:44:13.273425 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:44:13.273687 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:44:13.273797 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:44:13.273900 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:44:13.274044 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:44:13.274146 saving as /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/nfsrootfs/full.rootfs.tar
95 11:44:13.274252 total size: 200813988 (191 MB)
96 11:44:13.274356 Using unxz to decompress xz
97 11:44:13.278686 progress 0 % (0 MB)
98 11:44:13.827137 progress 5 % (9 MB)
99 11:44:14.355995 progress 10 % (19 MB)
100 11:44:14.953776 progress 15 % (28 MB)
101 11:44:15.339065 progress 20 % (38 MB)
102 11:44:15.678454 progress 25 % (47 MB)
103 11:44:16.288316 progress 30 % (57 MB)
104 11:44:16.848861 progress 35 % (67 MB)
105 11:44:17.452580 progress 40 % (76 MB)
106 11:44:18.028535 progress 45 % (86 MB)
107 11:44:18.630492 progress 50 % (95 MB)
108 11:44:19.309152 progress 55 % (105 MB)
109 11:44:19.988047 progress 60 % (114 MB)
110 11:44:20.116915 progress 65 % (124 MB)
111 11:44:20.276347 progress 70 % (134 MB)
112 11:44:20.391286 progress 75 % (143 MB)
113 11:44:20.466543 progress 80 % (153 MB)
114 11:44:20.538180 progress 85 % (162 MB)
115 11:44:20.656429 progress 90 % (172 MB)
116 11:44:20.944688 progress 95 % (181 MB)
117 11:44:21.542204 progress 100 % (191 MB)
118 11:44:21.547551 191 MB downloaded in 8.27 s (23.15 MB/s)
119 11:44:21.548056 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:44:21.548757 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:44:21.548942 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:44:21.549126 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:44:21.549421 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:44:21.549582 saving as /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/modules/modules.tar
126 11:44:21.549723 total size: 8624756 (8 MB)
127 11:44:21.549868 Using unxz to decompress xz
128 11:44:21.813485 progress 0 % (0 MB)
129 11:44:21.835125 progress 5 % (0 MB)
130 11:44:21.859505 progress 10 % (0 MB)
131 11:44:21.883924 progress 15 % (1 MB)
132 11:44:21.908342 progress 20 % (1 MB)
133 11:44:21.933371 progress 25 % (2 MB)
134 11:44:21.960927 progress 30 % (2 MB)
135 11:44:21.989179 progress 35 % (2 MB)
136 11:44:22.013860 progress 40 % (3 MB)
137 11:44:22.039260 progress 45 % (3 MB)
138 11:44:22.066326 progress 50 % (4 MB)
139 11:44:22.091901 progress 55 % (4 MB)
140 11:44:22.118363 progress 60 % (4 MB)
141 11:44:22.147392 progress 65 % (5 MB)
142 11:44:22.173597 progress 70 % (5 MB)
143 11:44:22.197980 progress 75 % (6 MB)
144 11:44:22.226858 progress 80 % (6 MB)
145 11:44:22.253942 progress 85 % (7 MB)
146 11:44:22.280250 progress 90 % (7 MB)
147 11:44:22.313918 progress 95 % (7 MB)
148 11:44:22.343640 progress 100 % (8 MB)
149 11:44:22.348675 8 MB downloaded in 0.80 s (10.30 MB/s)
150 11:44:22.349061 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:44:22.349496 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:44:22.349632 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:44:22.349774 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:44:26.063749 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5
156 11:44:26.063958 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:44:26.064065 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:44:26.064803 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46
159 11:44:26.064954 makedir: /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin
160 11:44:26.065064 makedir: /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/tests
161 11:44:26.065167 makedir: /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/results
162 11:44:26.065278 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-add-keys
163 11:44:26.065438 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-add-sources
164 11:44:26.065574 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-background-process-start
165 11:44:26.065735 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-background-process-stop
166 11:44:26.065875 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-common-functions
167 11:44:26.066006 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-echo-ipv4
168 11:44:26.066137 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-install-packages
169 11:44:26.066265 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-installed-packages
170 11:44:26.066394 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-os-build
171 11:44:26.066523 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-probe-channel
172 11:44:26.066652 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-probe-ip
173 11:44:26.066781 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-target-ip
174 11:44:26.066910 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-target-mac
175 11:44:26.067039 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-target-storage
176 11:44:26.067172 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-case
177 11:44:26.067303 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-event
178 11:44:26.067434 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-feedback
179 11:44:26.067564 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-raise
180 11:44:26.067700 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-reference
181 11:44:26.067837 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-runner
182 11:44:26.067969 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-set
183 11:44:26.068102 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-test-shell
184 11:44:26.068247 Updating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-add-keys (debian)
185 11:44:26.068427 Updating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-add-sources (debian)
186 11:44:26.068585 Updating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-install-packages (debian)
187 11:44:26.068735 Updating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-installed-packages (debian)
188 11:44:26.068882 Updating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/bin/lava-os-build (debian)
189 11:44:26.069010 Creating /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/environment
190 11:44:26.069112 LAVA metadata
191 11:44:26.069188 - LAVA_JOB_ID=12073986
192 11:44:26.069253 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:44:26.069371 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:44:26.069442 skipped lava-vland-overlay
195 11:44:26.069521 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:44:26.069606 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:44:26.069684 skipped lava-multinode-overlay
198 11:44:26.069762 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:44:26.069844 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:44:26.069925 Loading test definitions
201 11:44:26.070019 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:44:26.070093 Using /lava-12073986 at stage 0
203 11:44:26.070397 uuid=12073986_1.6.2.3.1 testdef=None
204 11:44:26.070487 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:44:26.070577 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:44:26.071052 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:44:26.071283 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:44:26.071882 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:44:26.072133 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:44:26.072744 runner path: /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/0/tests/0_timesync-off test_uuid 12073986_1.6.2.3.1
213 11:44:26.072911 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:44:26.073142 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:44:26.073217 Using /lava-12073986 at stage 0
217 11:44:26.073321 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:44:26.073404 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/0/tests/1_kselftest-tpm2'
219 11:44:36.165001 Running '/usr/bin/git checkout kernelci.org
220 11:44:36.272651 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:44:36.273684 uuid=12073986_1.6.2.3.5 testdef=None
222 11:44:36.273888 end: 1.6.2.3.5 git-repo-action (duration 00:00:10) [common]
224 11:44:36.274290 start: 1.6.2.3.6 test-overlay (timeout 00:09:36) [common]
225 11:44:36.275592 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:44:36.276001 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:36) [common]
228 11:44:36.277736 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:44:36.278150 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:36) [common]
231 11:44:36.279826 runner path: /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/0/tests/1_kselftest-tpm2 test_uuid 12073986_1.6.2.3.5
232 11:44:36.279989 BOARD='mt8192-asurada-spherion-r0'
233 11:44:36.280117 BRANCH='cip-gitlab'
234 11:44:36.280229 SKIPFILE='/dev/null'
235 11:44:36.280327 SKIP_INSTALL='True'
236 11:44:36.280418 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:44:36.280512 TST_CASENAME=''
238 11:44:36.280627 TST_CMDFILES='tpm2'
239 11:44:36.280860 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:44:36.281288 Creating lava-test-runner.conf files
242 11:44:36.281411 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073986/lava-overlay-n7t2ki46/lava-12073986/0 for stage 0
243 11:44:36.281566 - 0_timesync-off
244 11:44:36.281676 - 1_kselftest-tpm2
245 11:44:36.281817 end: 1.6.2.3 test-definition (duration 00:00:10) [common]
246 11:44:36.281965 start: 1.6.2.4 compress-overlay (timeout 00:09:36) [common]
247 11:44:44.279034 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:44:44.279229 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:28) [common]
249 11:44:44.279321 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:44:44.279423 end: 1.6.2 lava-overlay (duration 00:00:18) [common]
251 11:44:44.279520 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:28) [common]
252 11:44:44.408223 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:44:44.408614 start: 1.6.4 extract-modules (timeout 00:09:28) [common]
254 11:44:44.408735 extracting modules file /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5
255 11:44:44.670534 extracting modules file /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073986/extract-overlay-ramdisk-o8512v8d/ramdisk
256 11:44:44.907789 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:44:44.907979 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
258 11:44:44.908109 [common] Applying overlay to NFS
259 11:44:44.908269 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073986/compress-overlay-dks_elv1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5
260 11:44:45.943786 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:44:45.943984 start: 1.6.6 configure-preseed-file (timeout 00:09:27) [common]
262 11:44:45.944109 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:44:45.944247 start: 1.6.7 compress-ramdisk (timeout 00:09:27) [common]
264 11:44:45.944362 Building ramdisk /var/lib/lava/dispatcher/tmp/12073986/extract-overlay-ramdisk-o8512v8d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073986/extract-overlay-ramdisk-o8512v8d/ramdisk
265 11:44:46.268839 >> 119398 blocks
266 11:44:48.317373 rename /var/lib/lava/dispatcher/tmp/12073986/extract-overlay-ramdisk-o8512v8d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/ramdisk/ramdisk.cpio.gz
267 11:44:48.317819 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:44:48.317947 start: 1.6.8 prepare-kernel (timeout 00:09:24) [common]
269 11:44:48.318052 start: 1.6.8.1 prepare-fit (timeout 00:09:24) [common]
270 11:44:48.318177 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/kernel/Image'
271 11:45:01.813157 Returned 0 in 13 seconds
272 11:45:01.913824 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/kernel/image.itb
273 11:45:02.273207 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:45:02.273659 output: Created: Fri Nov 24 11:45:02 2023
275 11:45:02.273785 output: Image 0 (kernel-1)
276 11:45:02.273885 output: Description:
277 11:45:02.273990 output: Created: Fri Nov 24 11:45:02 2023
278 11:45:02.274094 output: Type: Kernel Image
279 11:45:02.274189 output: Compression: lzma compressed
280 11:45:02.274305 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
281 11:45:02.274401 output: Architecture: AArch64
282 11:45:02.274506 output: OS: Linux
283 11:45:02.274612 output: Load Address: 0x00000000
284 11:45:02.274706 output: Entry Point: 0x00000000
285 11:45:02.274795 output: Hash algo: crc32
286 11:45:02.274891 output: Hash value: 43cfb6ad
287 11:45:02.274984 output: Image 1 (fdt-1)
288 11:45:02.275082 output: Description: mt8192-asurada-spherion-r0
289 11:45:02.275179 output: Created: Fri Nov 24 11:45:02 2023
290 11:45:02.275270 output: Type: Flat Device Tree
291 11:45:02.275355 output: Compression: uncompressed
292 11:45:02.275439 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:45:02.275522 output: Architecture: AArch64
294 11:45:02.275585 output: Hash algo: crc32
295 11:45:02.275654 output: Hash value: cc4352de
296 11:45:02.275711 output: Image 2 (ramdisk-1)
297 11:45:02.275765 output: Description: unavailable
298 11:45:02.275819 output: Created: Fri Nov 24 11:45:02 2023
299 11:45:02.275876 output: Type: RAMDisk Image
300 11:45:02.275930 output: Compression: Unknown Compression
301 11:45:02.275984 output: Data Size: 17793025 Bytes = 17376.00 KiB = 16.97 MiB
302 11:45:02.276049 output: Architecture: AArch64
303 11:45:02.276147 output: OS: Linux
304 11:45:02.276251 output: Load Address: unavailable
305 11:45:02.276335 output: Entry Point: unavailable
306 11:45:02.276422 output: Hash algo: crc32
307 11:45:02.276506 output: Hash value: 763abae5
308 11:45:02.276589 output: Default Configuration: 'conf-1'
309 11:45:02.276679 output: Configuration 0 (conf-1)
310 11:45:02.276745 output: Description: mt8192-asurada-spherion-r0
311 11:45:02.276800 output: Kernel: kernel-1
312 11:45:02.276857 output: Init Ramdisk: ramdisk-1
313 11:45:02.276911 output: FDT: fdt-1
314 11:45:02.276964 output: Loadables: kernel-1
315 11:45:02.277017 output:
316 11:45:02.277228 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:45:02.277363 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:45:02.277503 end: 1.6 prepare-tftp-overlay (duration 00:00:40) [common]
319 11:45:02.277632 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:10) [common]
320 11:45:02.277754 No LXC device requested
321 11:45:02.277877 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:45:02.278001 start: 1.8 deploy-device-env (timeout 00:09:10) [common]
323 11:45:02.278113 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:45:02.278214 Checking files for TFTP limit of 4294967296 bytes.
325 11:45:02.278914 end: 1 tftp-deploy (duration 00:00:50) [common]
326 11:45:02.279053 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:45:02.279185 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:45:02.279349 substitutions:
329 11:45:02.279428 - {DTB}: 12073986/tftp-deploy-j5rb8lmf/dtb/mt8192-asurada-spherion-r0.dtb
330 11:45:02.279494 - {INITRD}: 12073986/tftp-deploy-j5rb8lmf/ramdisk/ramdisk.cpio.gz
331 11:45:02.279554 - {KERNEL}: 12073986/tftp-deploy-j5rb8lmf/kernel/Image
332 11:45:02.279616 - {LAVA_MAC}: None
333 11:45:02.279675 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5
334 11:45:02.279732 - {NFS_SERVER_IP}: 192.168.201.1
335 11:45:02.279788 - {PRESEED_CONFIG}: None
336 11:45:02.279853 - {PRESEED_LOCAL}: None
337 11:45:02.279949 - {RAMDISK}: 12073986/tftp-deploy-j5rb8lmf/ramdisk/ramdisk.cpio.gz
338 11:45:02.280035 - {ROOT_PART}: None
339 11:45:02.280133 - {ROOT}: None
340 11:45:02.280225 - {SERVER_IP}: 192.168.201.1
341 11:45:02.280286 - {TEE}: None
342 11:45:02.280349 Parsed boot commands:
343 11:45:02.280415 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:45:02.280619 Parsed boot commands: tftpboot 192.168.201.1 12073986/tftp-deploy-j5rb8lmf/kernel/image.itb 12073986/tftp-deploy-j5rb8lmf/kernel/cmdline
345 11:45:02.280747 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:45:02.280869 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:45:02.281016 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:45:02.281144 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:45:02.281261 Not connected, no need to disconnect.
350 11:45:02.281370 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:45:02.281484 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:45:02.281586 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 11:45:02.286018 Setting prompt string to ['lava-test: # ']
354 11:45:02.286476 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:45:02.286627 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:45:02.286774 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:45:02.286896 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:45:02.287257 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 11:45:07.424936 >> Command sent successfully.
360 11:45:07.427732 Returned 0 in 5 seconds
361 11:45:07.528136 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:45:07.528586 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:45:07.528720 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:45:07.528852 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:45:07.528953 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:45:07.529053 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:45:07.529443 [Enter `^Ec?' for help]
369 11:45:07.701090
370 11:45:07.701274
371 11:45:07.701383 F0: 102B 0000
372 11:45:07.701488
373 11:45:07.701584 F3: 1001 0000 [0200]
374 11:45:07.704401
375 11:45:07.704482 F3: 1001 0000
376 11:45:07.704547
377 11:45:07.704620 F7: 102D 0000
378 11:45:07.704682
379 11:45:07.707674 F1: 0000 0000
380 11:45:07.707783
381 11:45:07.707876 V0: 0000 0000 [0001]
382 11:45:07.707969
383 11:45:07.711259 00: 0007 8000
384 11:45:07.711335
385 11:45:07.711398 01: 0000 0000
386 11:45:07.711459
387 11:45:07.714572 BP: 0C00 0209 [0000]
388 11:45:07.714650
389 11:45:07.714714 G0: 1182 0000
390 11:45:07.714774
391 11:45:07.718106 EC: 0000 0021 [4000]
392 11:45:07.718191
393 11:45:07.718258 S7: 0000 0000 [0000]
394 11:45:07.718321
395 11:45:07.721566 CC: 0000 0000 [0001]
396 11:45:07.721651
397 11:45:07.721718 T0: 0000 0040 [010F]
398 11:45:07.721782
399 11:45:07.721842 Jump to BL
400 11:45:07.721901
401 11:45:07.748351
402 11:45:07.748447
403 11:45:07.748517
404 11:45:07.755560 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:45:07.758341 ARM64: Exception handlers installed.
406 11:45:07.762521 ARM64: Testing exception
407 11:45:07.765918 ARM64: Done test exception
408 11:45:07.772311 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:45:07.782237 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:45:07.788914 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:45:07.799099 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:45:07.805489 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:45:07.816016 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:45:07.826893 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:45:07.833216 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:45:07.850955 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:45:07.854458 WDT: Last reset was cold boot
418 11:45:07.857456 SPI1(PAD0) initialized at 2873684 Hz
419 11:45:07.861043 SPI5(PAD0) initialized at 992727 Hz
420 11:45:07.864270 VBOOT: Loading verstage.
421 11:45:07.871434 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:45:07.874341 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:45:07.877981 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:45:07.881385 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:45:07.888710 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:45:07.895409 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:45:07.906174 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:45:07.906290
429 11:45:07.906396
430 11:45:07.916178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:45:07.919097 ARM64: Exception handlers installed.
432 11:45:07.922435 ARM64: Testing exception
433 11:45:07.922544 ARM64: Done test exception
434 11:45:07.930000 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:45:07.933444 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:45:07.947187 Probing TPM: . done!
437 11:45:07.947279 TPM ready after 0 ms
438 11:45:07.953696 Connected to device vid:did:rid of 1ae0:0028:00
439 11:45:07.960927 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:45:08.000658 Initialized TPM device CR50 revision 0
441 11:45:08.012522 tlcl_send_startup: Startup return code is 0
442 11:45:08.012618 TPM: setup succeeded
443 11:45:08.023682 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:45:08.032510 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:45:08.044488 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:45:08.054392 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:45:08.057522 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:45:08.061960 in-header: 03 07 00 00 08 00 00 00
449 11:45:08.065431 in-data: aa e4 47 04 13 02 00 00
450 11:45:08.068951 Chrome EC: UHEPI supported
451 11:45:08.076479 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:45:08.079317 in-header: 03 9d 00 00 08 00 00 00
453 11:45:08.082848 in-data: 10 20 20 08 00 00 00 00
454 11:45:08.086310 Phase 1
455 11:45:08.089714 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:45:08.093152 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:45:08.100699 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:45:08.104393 Recovery requested (1009000e)
459 11:45:08.110431 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:45:08.115651 tlcl_extend: response is 0
461 11:45:08.123960 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:45:08.129449 tlcl_extend: response is 0
463 11:45:08.135899 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:45:08.157144 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:45:08.164353 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:45:08.164494
467 11:45:08.164597
468 11:45:08.172107 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:45:08.175681 ARM64: Exception handlers installed.
470 11:45:08.179737 ARM64: Testing exception
471 11:45:08.179846 ARM64: Done test exception
472 11:45:08.202221 pmic_efuse_setting: Set efuses in 11 msecs
473 11:45:08.205605 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:45:08.212669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:45:08.216408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:45:08.220042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:45:08.227456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:45:08.231086 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:45:08.235230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:45:08.238640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:45:08.245509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:45:08.249326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:45:08.255482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:45:08.258839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:45:08.262323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:45:08.269043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:45:08.275458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:45:08.279072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:45:08.285565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:45:08.292014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:45:08.295685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:45:08.303226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:45:08.310485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:45:08.313963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:45:08.317915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:45:08.324270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:45:08.331332 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:45:08.334821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:45:08.341331 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:45:08.344669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:45:08.352327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:45:08.355680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:45:08.359042 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:45:08.365657 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:45:08.369729 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:45:08.377183 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:45:08.381034 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:45:08.384817 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:45:08.392640 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:45:08.395468 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:45:08.402357 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:45:08.405810 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:45:08.409388 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:45:08.412294 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:45:08.419422 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:45:08.422260 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:45:08.425716 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:45:08.432181 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:45:08.435518 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:45:08.439333 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:45:08.445886 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:45:08.449377 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:45:08.452233 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:45:08.455742 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:45:08.466155 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:45:08.472400 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:45:08.479253 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:45:08.486072 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:45:08.496175 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:45:08.499160 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:45:08.502780 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:45:08.509162 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:45:08.516053 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x14
534 11:45:08.518874 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:45:08.526288 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:45:08.529795 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:45:08.539208 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 11:45:08.542481 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 11:45:08.549240 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 11:45:08.552190 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
541 11:45:08.555658 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 11:45:08.558959 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
543 11:45:08.562435 ADC[4]: Raw value=896670 ID=7
544 11:45:08.565899 ADC[3]: Raw value=213070 ID=1
545 11:45:08.565976 RAM Code: 0x71
546 11:45:08.572283 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 11:45:08.575655 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 11:45:08.585840 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 11:45:08.592993 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 11:45:08.596754 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 11:45:08.600047 in-header: 03 07 00 00 08 00 00 00
552 11:45:08.602944 in-data: aa e4 47 04 13 02 00 00
553 11:45:08.603022 Chrome EC: UHEPI supported
554 11:45:08.609953 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 11:45:08.613953 in-header: 03 d5 00 00 08 00 00 00
556 11:45:08.617534 in-data: 98 20 60 08 00 00 00 00
557 11:45:08.621051 MRC: failed to locate region type 0.
558 11:45:08.628738 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 11:45:08.632552 DRAM-K: Running full calibration
560 11:45:08.639041 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 11:45:08.639122 header.status = 0x0
562 11:45:08.642506 header.version = 0x6 (expected: 0x6)
563 11:45:08.645929 header.size = 0xd00 (expected: 0xd00)
564 11:45:08.649893 header.flags = 0x0
565 11:45:08.652717 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 11:45:08.671217 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
567 11:45:08.678300 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 11:45:08.681312 dram_init: ddr_geometry: 2
569 11:45:08.684704 [EMI] MDL number = 2
570 11:45:08.684780 [EMI] Get MDL freq = 0
571 11:45:08.687952 dram_init: ddr_type: 0
572 11:45:08.688055 is_discrete_lpddr4: 1
573 11:45:08.691156 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 11:45:08.691265
575 11:45:08.691382
576 11:45:08.694842 [Bian_co] ETT version 0.0.0.1
577 11:45:08.701934 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 11:45:08.702065
579 11:45:08.704737 dramc_set_vcore_voltage set vcore to 650000
580 11:45:08.704845 Read voltage for 800, 4
581 11:45:08.708027 Vio18 = 0
582 11:45:08.708165 Vcore = 650000
583 11:45:08.708286 Vdram = 0
584 11:45:08.711523 Vddq = 0
585 11:45:08.711672 Vmddr = 0
586 11:45:08.714940 dram_init: config_dvfs: 1
587 11:45:08.718202 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 11:45:08.724627 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 11:45:08.728148 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 11:45:08.731650 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 11:45:08.734950 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 11:45:08.738379 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 11:45:08.741360 MEM_TYPE=3, freq_sel=18
594 11:45:08.744932 sv_algorithm_assistance_LP4_1600
595 11:45:08.748333 ============ PULL DRAM RESETB DOWN ============
596 11:45:08.751326 ========== PULL DRAM RESETB DOWN end =========
597 11:45:08.758125 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 11:45:08.761723 ===================================
599 11:45:08.761805 LPDDR4 DRAM CONFIGURATION
600 11:45:08.764683 ===================================
601 11:45:08.768166 EX_ROW_EN[0] = 0x0
602 11:45:08.771725 EX_ROW_EN[1] = 0x0
603 11:45:08.771829 LP4Y_EN = 0x0
604 11:45:08.775195 WORK_FSP = 0x0
605 11:45:08.775305 WL = 0x2
606 11:45:08.778144 RL = 0x2
607 11:45:08.778219 BL = 0x2
608 11:45:08.781629 RPST = 0x0
609 11:45:08.781705 RD_PRE = 0x0
610 11:45:08.784629 WR_PRE = 0x1
611 11:45:08.784717 WR_PST = 0x0
612 11:45:08.788142 DBI_WR = 0x0
613 11:45:08.788249 DBI_RD = 0x0
614 11:45:08.791637 OTF = 0x1
615 11:45:08.794774 ===================================
616 11:45:08.798544 ===================================
617 11:45:08.798631 ANA top config
618 11:45:08.801342 ===================================
619 11:45:08.805221 DLL_ASYNC_EN = 0
620 11:45:08.808075 ALL_SLAVE_EN = 1
621 11:45:08.808194 NEW_RANK_MODE = 1
622 11:45:08.811340 DLL_IDLE_MODE = 1
623 11:45:08.814665 LP45_APHY_COMB_EN = 1
624 11:45:08.818022 TX_ODT_DIS = 1
625 11:45:08.821434 NEW_8X_MODE = 1
626 11:45:08.825026 ===================================
627 11:45:08.828487 ===================================
628 11:45:08.828568 data_rate = 1600
629 11:45:08.831538 CKR = 1
630 11:45:08.834940 DQ_P2S_RATIO = 8
631 11:45:08.838397 ===================================
632 11:45:08.841826 CA_P2S_RATIO = 8
633 11:45:08.845249 DQ_CA_OPEN = 0
634 11:45:08.848143 DQ_SEMI_OPEN = 0
635 11:45:08.848245 CA_SEMI_OPEN = 0
636 11:45:08.851668 CA_FULL_RATE = 0
637 11:45:08.855315 DQ_CKDIV4_EN = 1
638 11:45:08.858086 CA_CKDIV4_EN = 1
639 11:45:08.861403 CA_PREDIV_EN = 0
640 11:45:08.864985 PH8_DLY = 0
641 11:45:08.865082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 11:45:08.868555 DQ_AAMCK_DIV = 4
643 11:45:08.872064 CA_AAMCK_DIV = 4
644 11:45:08.875770 CA_ADMCK_DIV = 4
645 11:45:08.875895 DQ_TRACK_CA_EN = 0
646 11:45:08.879691 CA_PICK = 800
647 11:45:08.883774 CA_MCKIO = 800
648 11:45:08.887168 MCKIO_SEMI = 0
649 11:45:08.887272 PLL_FREQ = 3068
650 11:45:08.890731 DQ_UI_PI_RATIO = 32
651 11:45:08.894851 CA_UI_PI_RATIO = 0
652 11:45:08.898845 ===================================
653 11:45:08.902371 ===================================
654 11:45:08.902456 memory_type:LPDDR4
655 11:45:08.905894 GP_NUM : 10
656 11:45:08.905979 SRAM_EN : 1
657 11:45:08.909629 MD32_EN : 0
658 11:45:08.913313 ===================================
659 11:45:08.913398 [ANA_INIT] >>>>>>>>>>>>>>
660 11:45:08.917266 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 11:45:08.921207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 11:45:08.924949 ===================================
663 11:45:08.928777 data_rate = 1600,PCW = 0X7600
664 11:45:08.932251 ===================================
665 11:45:08.935881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:45:08.939288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 11:45:08.947339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 11:45:08.950870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 11:45:08.954352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 11:45:08.957938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 11:45:08.958025 [ANA_INIT] flow start
672 11:45:08.961464 [ANA_INIT] PLL >>>>>>>>
673 11:45:08.964925 [ANA_INIT] PLL <<<<<<<<
674 11:45:08.965010 [ANA_INIT] MIDPI >>>>>>>>
675 11:45:08.969120 [ANA_INIT] MIDPI <<<<<<<<
676 11:45:08.969205 [ANA_INIT] DLL >>>>>>>>
677 11:45:08.972644 [ANA_INIT] flow end
678 11:45:08.976257 ============ LP4 DIFF to SE enter ============
679 11:45:08.979738 ============ LP4 DIFF to SE exit ============
680 11:45:08.983754 [ANA_INIT] <<<<<<<<<<<<<
681 11:45:08.987693 [Flow] Enable top DCM control >>>>>
682 11:45:08.991181 [Flow] Enable top DCM control <<<<<
683 11:45:08.991268 Enable DLL master slave shuffle
684 11:45:08.998276 ==============================================================
685 11:45:08.998365 Gating Mode config
686 11:45:09.005294 ==============================================================
687 11:45:09.008707 Config description:
688 11:45:09.015306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 11:45:09.021983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 11:45:09.028696 SELPH_MODE 0: By rank 1: By Phase
691 11:45:09.032607 ==============================================================
692 11:45:09.035762 GAT_TRACK_EN = 1
693 11:45:09.038798 RX_GATING_MODE = 2
694 11:45:09.042135 RX_GATING_TRACK_MODE = 2
695 11:45:09.045580 SELPH_MODE = 1
696 11:45:09.048775 PICG_EARLY_EN = 1
697 11:45:09.052198 VALID_LAT_VALUE = 1
698 11:45:09.055512 ==============================================================
699 11:45:09.062573 Enter into Gating configuration >>>>
700 11:45:09.062659 Exit from Gating configuration <<<<
701 11:45:09.065614 Enter into DVFS_PRE_config >>>>>
702 11:45:09.078884 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 11:45:09.082528 Exit from DVFS_PRE_config <<<<<
704 11:45:09.085392 Enter into PICG configuration >>>>
705 11:45:09.088780 Exit from PICG configuration <<<<
706 11:45:09.088861 [RX_INPUT] configuration >>>>>
707 11:45:09.092141 [RX_INPUT] configuration <<<<<
708 11:45:09.099185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 11:45:09.102142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 11:45:09.108763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 11:45:09.115922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 11:45:09.122303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 11:45:09.128710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 11:45:09.132409 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 11:45:09.135465 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 11:45:09.138958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 11:45:09.145494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 11:45:09.149125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 11:45:09.152180 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 11:45:09.155740 ===================================
721 11:45:09.158738 LPDDR4 DRAM CONFIGURATION
722 11:45:09.162139 ===================================
723 11:45:09.165450 EX_ROW_EN[0] = 0x0
724 11:45:09.165538 EX_ROW_EN[1] = 0x0
725 11:45:09.169071 LP4Y_EN = 0x0
726 11:45:09.169160 WORK_FSP = 0x0
727 11:45:09.172571 WL = 0x2
728 11:45:09.172658 RL = 0x2
729 11:45:09.175505 BL = 0x2
730 11:45:09.175592 RPST = 0x0
731 11:45:09.178887 RD_PRE = 0x0
732 11:45:09.178966 WR_PRE = 0x1
733 11:45:09.182454 WR_PST = 0x0
734 11:45:09.182545 DBI_WR = 0x0
735 11:45:09.185342 DBI_RD = 0x0
736 11:45:09.185419 OTF = 0x1
737 11:45:09.188890 ===================================
738 11:45:09.192431 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 11:45:09.198688 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 11:45:09.202225 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 11:45:09.205816 ===================================
742 11:45:09.208689 LPDDR4 DRAM CONFIGURATION
743 11:45:09.212217 ===================================
744 11:45:09.212298 EX_ROW_EN[0] = 0x10
745 11:45:09.215727 EX_ROW_EN[1] = 0x0
746 11:45:09.218716 LP4Y_EN = 0x0
747 11:45:09.218796 WORK_FSP = 0x0
748 11:45:09.222220 WL = 0x2
749 11:45:09.222306 RL = 0x2
750 11:45:09.225774 BL = 0x2
751 11:45:09.225851 RPST = 0x0
752 11:45:09.228688 RD_PRE = 0x0
753 11:45:09.228764 WR_PRE = 0x1
754 11:45:09.232243 WR_PST = 0x0
755 11:45:09.232318 DBI_WR = 0x0
756 11:45:09.235266 DBI_RD = 0x0
757 11:45:09.235343 OTF = 0x1
758 11:45:09.238797 ===================================
759 11:45:09.245341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 11:45:09.249833 nWR fixed to 40
761 11:45:09.253156 [ModeRegInit_LP4] CH0 RK0
762 11:45:09.253241 [ModeRegInit_LP4] CH0 RK1
763 11:45:09.256418 [ModeRegInit_LP4] CH1 RK0
764 11:45:09.259128 [ModeRegInit_LP4] CH1 RK1
765 11:45:09.259231 match AC timing 13
766 11:45:09.265947 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 11:45:09.269342 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 11:45:09.273032 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 11:45:09.279782 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 11:45:09.282492 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 11:45:09.286017 [EMI DOE] emi_dcm 0
772 11:45:09.289642 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 11:45:09.289726 ==
774 11:45:09.292569 Dram Type= 6, Freq= 0, CH_0, rank 0
775 11:45:09.295976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 11:45:09.296061 ==
777 11:45:09.303006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 11:45:09.309189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 11:45:09.316864 [CA 0] Center 38 (7~69) winsize 63
780 11:45:09.320322 [CA 1] Center 37 (7~68) winsize 62
781 11:45:09.323839 [CA 2] Center 35 (5~66) winsize 62
782 11:45:09.327406 [CA 3] Center 35 (5~66) winsize 62
783 11:45:09.330255 [CA 4] Center 34 (4~65) winsize 62
784 11:45:09.333734 [CA 5] Center 34 (4~65) winsize 62
785 11:45:09.333812
786 11:45:09.337327 [CmdBusTrainingLP45] Vref(ca) range 1: 32
787 11:45:09.337405
788 11:45:09.340308 [CATrainingPosCal] consider 1 rank data
789 11:45:09.343766 u2DelayCellTimex100 = 270/100 ps
790 11:45:09.347219 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 11:45:09.350561 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 11:45:09.357253 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 11:45:09.360238 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 11:45:09.363664 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 11:45:09.367227 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 11:45:09.367310
797 11:45:09.370740 CA PerBit enable=1, Macro0, CA PI delay=34
798 11:45:09.370819
799 11:45:09.373902 [CBTSetCACLKResult] CA Dly = 34
800 11:45:09.373976 CS Dly: 6 (0~37)
801 11:45:09.374038 ==
802 11:45:09.377156 Dram Type= 6, Freq= 0, CH_0, rank 1
803 11:45:09.384679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:45:09.384805 ==
805 11:45:09.388285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 11:45:09.395025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 11:45:09.403921 [CA 0] Center 37 (7~68) winsize 62
808 11:45:09.407456 [CA 1] Center 38 (7~69) winsize 63
809 11:45:09.410903 [CA 2] Center 35 (5~66) winsize 62
810 11:45:09.415065 [CA 3] Center 35 (5~66) winsize 62
811 11:45:09.418674 [CA 4] Center 34 (4~65) winsize 62
812 11:45:09.422119 [CA 5] Center 33 (3~64) winsize 62
813 11:45:09.422203
814 11:45:09.425667 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 11:45:09.425751
816 11:45:09.429241 [CATrainingPosCal] consider 2 rank data
817 11:45:09.429328 u2DelayCellTimex100 = 270/100 ps
818 11:45:09.436408 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
819 11:45:09.439986 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 11:45:09.443661 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 11:45:09.447270 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 11:45:09.451365 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 11:45:09.451451 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
824 11:45:09.454864
825 11:45:09.458255 CA PerBit enable=1, Macro0, CA PI delay=34
826 11:45:09.458354
827 11:45:09.458419 [CBTSetCACLKResult] CA Dly = 34
828 11:45:09.462114 CS Dly: 6 (0~37)
829 11:45:09.462222
830 11:45:09.465746 ----->DramcWriteLeveling(PI) begin...
831 11:45:09.465830 ==
832 11:45:09.469726 Dram Type= 6, Freq= 0, CH_0, rank 0
833 11:45:09.473390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 11:45:09.473474 ==
835 11:45:09.477542 Write leveling (Byte 0): 33 => 33
836 11:45:09.477628 Write leveling (Byte 1): 32 => 32
837 11:45:09.481046 DramcWriteLeveling(PI) end<-----
838 11:45:09.481130
839 11:45:09.481195 ==
840 11:45:09.484573 Dram Type= 6, Freq= 0, CH_0, rank 0
841 11:45:09.488581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 11:45:09.488665 ==
843 11:45:09.491916 [Gating] SW mode calibration
844 11:45:09.499379 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 11:45:09.503948 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 11:45:09.511088 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 11:45:09.514927 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 11:45:09.518915 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 11:45:09.522401 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 11:45:09.525988 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:45:09.532939 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:45:09.537137 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:45:09.540702 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:45:09.544295 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:45:09.547736 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:45:09.555382 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:45:09.559386 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:45:09.562898 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:45:09.566217 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:45:09.569842 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:45:09.573832 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:45:09.580983 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:45:09.585089 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:45:09.588698 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
865 11:45:09.592269 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:45:09.596329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:45:09.603115 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:45:09.606631 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:45:09.610709 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:45:09.614441 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:45:09.618052 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:45:09.621732 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:45:09.629287 0 9 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
874 11:45:09.632964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 11:45:09.636735 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 11:45:09.640758 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 11:45:09.644256 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 11:45:09.652016 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:45:09.655506 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:45:09.659007 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
881 11:45:09.662881 0 10 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
882 11:45:09.666929 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 11:45:09.670334 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 11:45:09.677891 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 11:45:09.681513 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:45:09.685477 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:45:09.689095 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:45:09.692629 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
889 11:45:09.700308 0 11 12 | B1->B0 | 3232 4141 | 1 0 | (0 0) (0 0)
890 11:45:09.703807 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 11:45:09.707295 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 11:45:09.710509 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:45:09.716984 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:45:09.720448 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:45:09.723876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:45:09.730855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:45:09.733962 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
898 11:45:09.737133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:45:09.740830 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:45:09.746990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:45:09.750701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:45:09.753798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:45:09.760291 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:45:09.763777 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:45:09.767115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:45:09.774003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:45:09.777399 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:45:09.780306 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:45:09.787275 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:45:09.790252 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:45:09.793837 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:45:09.800217 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
913 11:45:09.803803 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 11:45:09.806820 Total UI for P1: 0, mck2ui 16
915 11:45:09.810395 best dqsien dly found for B0: ( 0, 14, 8)
916 11:45:09.813872 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 11:45:09.817325 Total UI for P1: 0, mck2ui 16
918 11:45:09.820271 best dqsien dly found for B1: ( 0, 14, 10)
919 11:45:09.823809 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 11:45:09.827239 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
921 11:45:09.827351
922 11:45:09.830237 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 11:45:09.836806 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
924 11:45:09.836897 [Gating] SW calibration Done
925 11:45:09.836964 ==
926 11:45:09.840295 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:45:09.847214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:45:09.847322 ==
929 11:45:09.847427 RX Vref Scan: 0
930 11:45:09.847519
931 11:45:09.850460 RX Vref 0 -> 0, step: 1
932 11:45:09.850536
933 11:45:09.853478 RX Delay -130 -> 252, step: 16
934 11:45:09.856950 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 11:45:09.860325 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 11:45:09.863684 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 11:45:09.870775 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 11:45:09.873677 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 11:45:09.877268 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 11:45:09.880322 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 11:45:09.883714 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 11:45:09.890654 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 11:45:09.893535 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 11:45:09.897068 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
945 11:45:09.900537 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 11:45:09.903562 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 11:45:09.910722 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 11:45:09.914138 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 11:45:09.917583 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 11:45:09.917661 ==
951 11:45:09.920409 Dram Type= 6, Freq= 0, CH_0, rank 0
952 11:45:09.924000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 11:45:09.924080 ==
954 11:45:09.927062 DQS Delay:
955 11:45:09.927137 DQS0 = 0, DQS1 = 0
956 11:45:09.927200 DQM Delay:
957 11:45:09.930708 DQM0 = 80, DQM1 = 68
958 11:45:09.930793 DQ Delay:
959 11:45:09.934228 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 11:45:09.937077 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 11:45:09.940535 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
962 11:45:09.943962 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 11:45:09.944047
964 11:45:09.944113
965 11:45:09.944175 ==
966 11:45:09.947507 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:45:09.951269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:45:09.951398 ==
969 11:45:09.954811
970 11:45:09.954894
971 11:45:09.954959 TX Vref Scan disable
972 11:45:09.958247 == TX Byte 0 ==
973 11:45:09.961295 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
974 11:45:09.964740 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
975 11:45:09.967974 == TX Byte 1 ==
976 11:45:09.971356 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 11:45:09.974929 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 11:45:09.975034 ==
979 11:45:09.978121 Dram Type= 6, Freq= 0, CH_0, rank 0
980 11:45:09.984442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 11:45:09.984540 ==
982 11:45:09.996304 TX Vref=22, minBit 12, minWin=26, winSum=436
983 11:45:10.000114 TX Vref=24, minBit 4, minWin=27, winSum=442
984 11:45:10.003192 TX Vref=26, minBit 0, minWin=27, winSum=440
985 11:45:10.006813 TX Vref=28, minBit 9, minWin=27, winSum=445
986 11:45:10.010254 TX Vref=30, minBit 9, minWin=27, winSum=444
987 11:45:10.016739 TX Vref=32, minBit 13, minWin=26, winSum=438
988 11:45:10.020328 [TxChooseVref] Worse bit 9, Min win 27, Win sum 445, Final Vref 28
989 11:45:10.020441
990 11:45:10.023266 Final TX Range 1 Vref 28
991 11:45:10.023351
992 11:45:10.023418 ==
993 11:45:10.026743 Dram Type= 6, Freq= 0, CH_0, rank 0
994 11:45:10.030144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 11:45:10.030238 ==
996 11:45:10.033406
997 11:45:10.033485
998 11:45:10.033550 TX Vref Scan disable
999 11:45:10.037031 == TX Byte 0 ==
1000 11:45:10.039854 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1001 11:45:10.043376 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1002 11:45:10.046801 == TX Byte 1 ==
1003 11:45:10.049760 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 11:45:10.056487 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 11:45:10.056590
1006 11:45:10.056667 [DATLAT]
1007 11:45:10.056729 Freq=800, CH0 RK0
1008 11:45:10.056789
1009 11:45:10.059954 DATLAT Default: 0xa
1010 11:45:10.060071 0, 0xFFFF, sum = 0
1011 11:45:10.063382 1, 0xFFFF, sum = 0
1012 11:45:10.063458 2, 0xFFFF, sum = 0
1013 11:45:10.066672 3, 0xFFFF, sum = 0
1014 11:45:10.066760 4, 0xFFFF, sum = 0
1015 11:45:10.069755 5, 0xFFFF, sum = 0
1016 11:45:10.073062 6, 0xFFFF, sum = 0
1017 11:45:10.073138 7, 0xFFFF, sum = 0
1018 11:45:10.076474 8, 0xFFFF, sum = 0
1019 11:45:10.076559 9, 0x0, sum = 1
1020 11:45:10.076626 10, 0x0, sum = 2
1021 11:45:10.079954 11, 0x0, sum = 3
1022 11:45:10.080038 12, 0x0, sum = 4
1023 11:45:10.083484 best_step = 10
1024 11:45:10.083567
1025 11:45:10.083674 ==
1026 11:45:10.086999 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 11:45:10.089938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 11:45:10.090021 ==
1029 11:45:10.093214 RX Vref Scan: 1
1030 11:45:10.093299
1031 11:45:10.093439 Set Vref Range= 32 -> 127
1032 11:45:10.093545
1033 11:45:10.096804 RX Vref 32 -> 127, step: 1
1034 11:45:10.096886
1035 11:45:10.100183 RX Delay -111 -> 252, step: 8
1036 11:45:10.100301
1037 11:45:10.103410 Set Vref, RX VrefLevel [Byte0]: 32
1038 11:45:10.107072 [Byte1]: 32
1039 11:45:10.107153
1040 11:45:10.110044 Set Vref, RX VrefLevel [Byte0]: 33
1041 11:45:10.113501 [Byte1]: 33
1042 11:45:10.117098
1043 11:45:10.117179 Set Vref, RX VrefLevel [Byte0]: 34
1044 11:45:10.120315 [Byte1]: 34
1045 11:45:10.124901
1046 11:45:10.124983 Set Vref, RX VrefLevel [Byte0]: 35
1047 11:45:10.127865 [Byte1]: 35
1048 11:45:10.132653
1049 11:45:10.132735 Set Vref, RX VrefLevel [Byte0]: 36
1050 11:45:10.135431 [Byte1]: 36
1051 11:45:10.139851
1052 11:45:10.139933 Set Vref, RX VrefLevel [Byte0]: 37
1053 11:45:10.143372 [Byte1]: 37
1054 11:45:10.147508
1055 11:45:10.147590 Set Vref, RX VrefLevel [Byte0]: 38
1056 11:45:10.151101 [Byte1]: 38
1057 11:45:10.155248
1058 11:45:10.155332 Set Vref, RX VrefLevel [Byte0]: 39
1059 11:45:10.158747 [Byte1]: 39
1060 11:45:10.163117
1061 11:45:10.163225 Set Vref, RX VrefLevel [Byte0]: 40
1062 11:45:10.166070 [Byte1]: 40
1063 11:45:10.170853
1064 11:45:10.170961 Set Vref, RX VrefLevel [Byte0]: 41
1065 11:45:10.174269 [Byte1]: 41
1066 11:45:10.178441
1067 11:45:10.178541 Set Vref, RX VrefLevel [Byte0]: 42
1068 11:45:10.181430 [Byte1]: 42
1069 11:45:10.185657
1070 11:45:10.185732 Set Vref, RX VrefLevel [Byte0]: 43
1071 11:45:10.189237 [Byte1]: 43
1072 11:45:10.193334
1073 11:45:10.193410 Set Vref, RX VrefLevel [Byte0]: 44
1074 11:45:10.196841 [Byte1]: 44
1075 11:45:10.201447
1076 11:45:10.201568 Set Vref, RX VrefLevel [Byte0]: 45
1077 11:45:10.204388 [Byte1]: 45
1078 11:45:10.209188
1079 11:45:10.209267 Set Vref, RX VrefLevel [Byte0]: 46
1080 11:45:10.212744 [Byte1]: 46
1081 11:45:10.216826
1082 11:45:10.216907 Set Vref, RX VrefLevel [Byte0]: 47
1083 11:45:10.220736 [Byte1]: 47
1084 11:45:10.224371
1085 11:45:10.224443 Set Vref, RX VrefLevel [Byte0]: 48
1086 11:45:10.228099 [Byte1]: 48
1087 11:45:10.232347
1088 11:45:10.232425 Set Vref, RX VrefLevel [Byte0]: 49
1089 11:45:10.235642 [Byte1]: 49
1090 11:45:10.239776
1091 11:45:10.239857 Set Vref, RX VrefLevel [Byte0]: 50
1092 11:45:10.243134 [Byte1]: 50
1093 11:45:10.247107
1094 11:45:10.247211 Set Vref, RX VrefLevel [Byte0]: 51
1095 11:45:10.250584 [Byte1]: 51
1096 11:45:10.254712
1097 11:45:10.254785 Set Vref, RX VrefLevel [Byte0]: 52
1098 11:45:10.258302 [Byte1]: 52
1099 11:45:10.262331
1100 11:45:10.262401 Set Vref, RX VrefLevel [Byte0]: 53
1101 11:45:10.265814 [Byte1]: 53
1102 11:45:10.270323
1103 11:45:10.270439 Set Vref, RX VrefLevel [Byte0]: 54
1104 11:45:10.273285 [Byte1]: 54
1105 11:45:10.278004
1106 11:45:10.278075 Set Vref, RX VrefLevel [Byte0]: 55
1107 11:45:10.280893 [Byte1]: 55
1108 11:45:10.285232
1109 11:45:10.285315 Set Vref, RX VrefLevel [Byte0]: 56
1110 11:45:10.288819 [Byte1]: 56
1111 11:45:10.293052
1112 11:45:10.293127 Set Vref, RX VrefLevel [Byte0]: 57
1113 11:45:10.296566 [Byte1]: 57
1114 11:45:10.300574
1115 11:45:10.300687 Set Vref, RX VrefLevel [Byte0]: 58
1116 11:45:10.303989 [Byte1]: 58
1117 11:45:10.308507
1118 11:45:10.308590 Set Vref, RX VrefLevel [Byte0]: 59
1119 11:45:10.311406 [Byte1]: 59
1120 11:45:10.316051
1121 11:45:10.316156 Set Vref, RX VrefLevel [Byte0]: 60
1122 11:45:10.319508 [Byte1]: 60
1123 11:45:10.323538
1124 11:45:10.323611 Set Vref, RX VrefLevel [Byte0]: 61
1125 11:45:10.327107 [Byte1]: 61
1126 11:45:10.331277
1127 11:45:10.331376 Set Vref, RX VrefLevel [Byte0]: 62
1128 11:45:10.334221 [Byte1]: 62
1129 11:45:10.338638
1130 11:45:10.338711 Set Vref, RX VrefLevel [Byte0]: 63
1131 11:45:10.342229 [Byte1]: 63
1132 11:45:10.346394
1133 11:45:10.346476 Set Vref, RX VrefLevel [Byte0]: 64
1134 11:45:10.350002 [Byte1]: 64
1135 11:45:10.353890
1136 11:45:10.353966 Set Vref, RX VrefLevel [Byte0]: 65
1137 11:45:10.357497 [Byte1]: 65
1138 11:45:10.361724
1139 11:45:10.361799 Set Vref, RX VrefLevel [Byte0]: 66
1140 11:45:10.364905 [Byte1]: 66
1141 11:45:10.369589
1142 11:45:10.369677 Set Vref, RX VrefLevel [Byte0]: 67
1143 11:45:10.373340 [Byte1]: 67
1144 11:45:10.377392
1145 11:45:10.377463 Set Vref, RX VrefLevel [Byte0]: 68
1146 11:45:10.380385 [Byte1]: 68
1147 11:45:10.384496
1148 11:45:10.384596 Set Vref, RX VrefLevel [Byte0]: 69
1149 11:45:10.388151 [Byte1]: 69
1150 11:45:10.392279
1151 11:45:10.392349 Set Vref, RX VrefLevel [Byte0]: 70
1152 11:45:10.395660 [Byte1]: 70
1153 11:45:10.399771
1154 11:45:10.399902 Set Vref, RX VrefLevel [Byte0]: 71
1155 11:45:10.403090 [Byte1]: 71
1156 11:45:10.407787
1157 11:45:10.407870 Set Vref, RX VrefLevel [Byte0]: 72
1158 11:45:10.411116 [Byte1]: 72
1159 11:45:10.415109
1160 11:45:10.415277 Set Vref, RX VrefLevel [Byte0]: 73
1161 11:45:10.418695 [Byte1]: 73
1162 11:45:10.422746
1163 11:45:10.422858 Set Vref, RX VrefLevel [Byte0]: 74
1164 11:45:10.426186 [Byte1]: 74
1165 11:45:10.430284
1166 11:45:10.430381 Set Vref, RX VrefLevel [Byte0]: 75
1167 11:45:10.433855 [Byte1]: 75
1168 11:45:10.438048
1169 11:45:10.438146 Set Vref, RX VrefLevel [Byte0]: 76
1170 11:45:10.441600 [Byte1]: 76
1171 11:45:10.446044
1172 11:45:10.446111 Set Vref, RX VrefLevel [Byte0]: 77
1173 11:45:10.449514 [Byte1]: 77
1174 11:45:10.453600
1175 11:45:10.453707 Set Vref, RX VrefLevel [Byte0]: 78
1176 11:45:10.457016 [Byte1]: 78
1177 11:45:10.461266
1178 11:45:10.461351 Final RX Vref Byte 0 = 60 to rank0
1179 11:45:10.464422 Final RX Vref Byte 1 = 61 to rank0
1180 11:45:10.467616 Final RX Vref Byte 0 = 60 to rank1
1181 11:45:10.471264 Final RX Vref Byte 1 = 61 to rank1==
1182 11:45:10.474659 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 11:45:10.481173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 11:45:10.481264 ==
1185 11:45:10.481330 DQS Delay:
1186 11:45:10.481389 DQS0 = 0, DQS1 = 0
1187 11:45:10.484812 DQM Delay:
1188 11:45:10.484922 DQM0 = 82, DQM1 = 68
1189 11:45:10.487843 DQ Delay:
1190 11:45:10.491303 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1191 11:45:10.491412 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1192 11:45:10.494876 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1193 11:45:10.497896 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1194 11:45:10.501385
1195 11:45:10.501517
1196 11:45:10.508160 [DQSOSCAuto] RK0, (LSB)MR18= 0x2827, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1197 11:45:10.511440 CH0 RK0: MR19=606, MR18=2827
1198 11:45:10.517885 CH0_RK0: MR19=0x606, MR18=0x2827, DQSOSC=399, MR23=63, INC=92, DEC=61
1199 11:45:10.518021
1200 11:45:10.521278 ----->DramcWriteLeveling(PI) begin...
1201 11:45:10.521385 ==
1202 11:45:10.524788 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 11:45:10.528274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 11:45:10.528362 ==
1205 11:45:10.531250 Write leveling (Byte 0): 32 => 32
1206 11:45:10.534671 Write leveling (Byte 1): 30 => 30
1207 11:45:10.538296 DramcWriteLeveling(PI) end<-----
1208 11:45:10.538394
1209 11:45:10.538493 ==
1210 11:45:10.541837 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:45:10.544816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 11:45:10.544902 ==
1213 11:45:10.548435 [Gating] SW mode calibration
1214 11:45:10.554693 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 11:45:10.561771 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 11:45:10.565201 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 11:45:10.568708 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 11:45:10.574746 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 11:45:10.578228 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:45:10.581724 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:45:10.584699 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:45:10.591654 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:45:10.594807 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:45:10.598288 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:45:10.605155 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:45:10.608056 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:45:10.611696 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:45:10.618458 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:45:10.621522 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:45:10.625048 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:45:10.668768 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:45:10.669051 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:45:10.669125 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1234 11:45:10.669374 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1235 11:45:10.669494 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:45:10.669571 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:45:10.669632 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:45:10.669893 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:45:10.669986 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:45:10.670074 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:45:10.713134 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:45:10.713642 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1243 11:45:10.713927 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1244 11:45:10.714036 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:45:10.714136 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:45:10.714242 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:45:10.714676 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:45:10.715302 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:45:10.715722 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
1250 11:45:10.715794 0 10 8 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (1 1)
1251 11:45:10.737064 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:45:10.737415 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:45:10.737519 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:45:10.737612 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:45:10.737699 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:45:10.741030 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:45:10.744303 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1258 11:45:10.747352 0 11 8 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (1 1)
1259 11:45:10.754372 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1260 11:45:10.757757 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:45:10.760630 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:45:10.767669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:45:10.770591 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:45:10.774164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:45:10.780620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 11:45:10.784587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 11:45:10.788006 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:45:10.791597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:45:10.798786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:45:10.802169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:45:10.805535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:45:10.809084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:45:10.816714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:45:10.820093 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:45:10.823303 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:45:10.826488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:45:10.833305 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:45:10.836157 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:45:10.839678 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:45:10.846180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:45:10.849757 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:45:10.852961 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1283 11:45:10.859384 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 11:45:10.863278 Total UI for P1: 0, mck2ui 16
1285 11:45:10.866197 best dqsien dly found for B0: ( 0, 14, 8)
1286 11:45:10.866274 Total UI for P1: 0, mck2ui 16
1287 11:45:10.872641 best dqsien dly found for B1: ( 0, 14, 8)
1288 11:45:10.876166 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1289 11:45:10.879756 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 11:45:10.879833
1291 11:45:10.882697 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1292 11:45:10.886225 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 11:45:10.889499 [Gating] SW calibration Done
1294 11:45:10.889615 ==
1295 11:45:10.892895 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:45:10.896492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:45:10.896608 ==
1298 11:45:10.899454 RX Vref Scan: 0
1299 11:45:10.899534
1300 11:45:10.899597 RX Vref 0 -> 0, step: 1
1301 11:45:10.899657
1302 11:45:10.902979 RX Delay -130 -> 252, step: 16
1303 11:45:10.909214 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1304 11:45:10.912757 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1305 11:45:10.916266 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1306 11:45:10.919280 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1307 11:45:10.922815 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1308 11:45:10.926360 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1309 11:45:10.932915 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1310 11:45:10.936388 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1311 11:45:10.939200 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1312 11:45:10.943058 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1313 11:45:10.946327 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1314 11:45:10.952912 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1315 11:45:10.956224 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1316 11:45:10.959264 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1317 11:45:10.962549 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1318 11:45:10.969318 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1319 11:45:10.969398 ==
1320 11:45:10.972905 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 11:45:10.975966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 11:45:10.976068 ==
1323 11:45:10.976158 DQS Delay:
1324 11:45:10.979391 DQS0 = 0, DQS1 = 0
1325 11:45:10.979505 DQM Delay:
1326 11:45:10.982376 DQM0 = 78, DQM1 = 70
1327 11:45:10.982476 DQ Delay:
1328 11:45:10.985941 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1329 11:45:10.989467 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1330 11:45:10.992498 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1331 11:45:10.995739 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1332 11:45:10.995839
1333 11:45:10.995937
1334 11:45:10.996027 ==
1335 11:45:10.999117 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 11:45:11.002720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 11:45:11.002822 ==
1338 11:45:11.002913
1339 11:45:11.003002
1340 11:45:11.006227 TX Vref Scan disable
1341 11:45:11.009039 == TX Byte 0 ==
1342 11:45:11.012853 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1343 11:45:11.015875 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1344 11:45:11.019427 == TX Byte 1 ==
1345 11:45:11.022879 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 11:45:11.025819 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 11:45:11.025920 ==
1348 11:45:11.029296 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 11:45:11.032719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 11:45:11.036188 ==
1351 11:45:11.047747 TX Vref=22, minBit 11, minWin=26, winSum=435
1352 11:45:11.051183 TX Vref=24, minBit 13, minWin=26, winSum=436
1353 11:45:11.054018 TX Vref=26, minBit 1, minWin=27, winSum=441
1354 11:45:11.057744 TX Vref=28, minBit 11, minWin=26, winSum=439
1355 11:45:11.061085 TX Vref=30, minBit 1, minWin=27, winSum=441
1356 11:45:11.067481 TX Vref=32, minBit 14, minWin=26, winSum=442
1357 11:45:11.071142 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 26
1358 11:45:11.071243
1359 11:45:11.074675 Final TX Range 1 Vref 26
1360 11:45:11.074777
1361 11:45:11.074870 ==
1362 11:45:11.077839 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:45:11.081045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:45:11.081149 ==
1365 11:45:11.084514
1366 11:45:11.084606
1367 11:45:11.084703 TX Vref Scan disable
1368 11:45:11.087494 == TX Byte 0 ==
1369 11:45:11.091086 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 11:45:11.097947 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 11:45:11.098056 == TX Byte 1 ==
1372 11:45:11.100700 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1373 11:45:11.104654 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1374 11:45:11.107558
1375 11:45:11.107655 [DATLAT]
1376 11:45:11.107753 Freq=800, CH0 RK1
1377 11:45:11.107845
1378 11:45:11.110994 DATLAT Default: 0xa
1379 11:45:11.111096 0, 0xFFFF, sum = 0
1380 11:45:11.114388 1, 0xFFFF, sum = 0
1381 11:45:11.114489 2, 0xFFFF, sum = 0
1382 11:45:11.117779 3, 0xFFFF, sum = 0
1383 11:45:11.117882 4, 0xFFFF, sum = 0
1384 11:45:11.120765 5, 0xFFFF, sum = 0
1385 11:45:11.124170 6, 0xFFFF, sum = 0
1386 11:45:11.124276 7, 0xFFFF, sum = 0
1387 11:45:11.127743 8, 0xFFFF, sum = 0
1388 11:45:11.127851 9, 0x0, sum = 1
1389 11:45:11.127916 10, 0x0, sum = 2
1390 11:45:11.131283 11, 0x0, sum = 3
1391 11:45:11.131356 12, 0x0, sum = 4
1392 11:45:11.134154 best_step = 10
1393 11:45:11.134224
1394 11:45:11.134287 ==
1395 11:45:11.137672 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 11:45:11.141190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 11:45:11.141295 ==
1398 11:45:11.144431 RX Vref Scan: 0
1399 11:45:11.144502
1400 11:45:11.144581 RX Vref 0 -> 0, step: 1
1401 11:45:11.144639
1402 11:45:11.147936 RX Delay -111 -> 252, step: 8
1403 11:45:11.154335 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1404 11:45:11.157919 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1405 11:45:11.161327 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1406 11:45:11.164278 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1407 11:45:11.167969 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1408 11:45:11.174664 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1409 11:45:11.177944 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1410 11:45:11.181154 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1411 11:45:11.184777 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1412 11:45:11.187712 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1413 11:45:11.194717 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1414 11:45:11.197690 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1415 11:45:11.201154 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1416 11:45:11.204541 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1417 11:45:11.207696 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1418 11:45:11.214688 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1419 11:45:11.214797 ==
1420 11:45:11.217671 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 11:45:11.220905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 11:45:11.221007 ==
1423 11:45:11.221097 DQS Delay:
1424 11:45:11.224532 DQS0 = 0, DQS1 = 0
1425 11:45:11.224605 DQM Delay:
1426 11:45:11.227974 DQM0 = 78, DQM1 = 71
1427 11:45:11.228080 DQ Delay:
1428 11:45:11.231481 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1429 11:45:11.234440 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1430 11:45:11.237957 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1431 11:45:11.241420 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1432 11:45:11.241514
1433 11:45:11.241619
1434 11:45:11.248270 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1435 11:45:11.251504 CH0 RK1: MR19=606, MR18=4C27
1436 11:45:11.257988 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1437 11:45:11.261388 [RxdqsGatingPostProcess] freq 800
1438 11:45:11.267942 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 11:45:11.268019 Pre-setting of DQS Precalculation
1440 11:45:11.274763 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 11:45:11.274840 ==
1442 11:45:11.277942 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:45:11.281202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:45:11.281278 ==
1445 11:45:11.288108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 11:45:11.294613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 11:45:11.302803 [CA 0] Center 36 (6~66) winsize 61
1448 11:45:11.306191 [CA 1] Center 36 (6~67) winsize 62
1449 11:45:11.309750 [CA 2] Center 34 (5~64) winsize 60
1450 11:45:11.313040 [CA 3] Center 33 (3~64) winsize 62
1451 11:45:11.316222 [CA 4] Center 34 (4~64) winsize 61
1452 11:45:11.319195 [CA 5] Center 34 (4~64) winsize 61
1453 11:45:11.319310
1454 11:45:11.322618 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 11:45:11.322697
1456 11:45:11.326022 [CATrainingPosCal] consider 1 rank data
1457 11:45:11.329499 u2DelayCellTimex100 = 270/100 ps
1458 11:45:11.332520 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 11:45:11.335975 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 11:45:11.342950 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1461 11:45:11.345872 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 11:45:11.349417 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 11:45:11.352934 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1464 11:45:11.353042
1465 11:45:11.356352 CA PerBit enable=1, Macro0, CA PI delay=33
1466 11:45:11.356461
1467 11:45:11.359717 [CBTSetCACLKResult] CA Dly = 33
1468 11:45:11.359818 CS Dly: 5 (0~36)
1469 11:45:11.359910 ==
1470 11:45:11.363120 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 11:45:11.369639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 11:45:11.369731 ==
1473 11:45:11.372609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 11:45:11.379595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 11:45:11.388852 [CA 0] Center 36 (6~67) winsize 62
1476 11:45:11.392064 [CA 1] Center 36 (6~67) winsize 62
1477 11:45:11.395294 [CA 2] Center 35 (5~65) winsize 61
1478 11:45:11.398789 [CA 3] Center 33 (3~64) winsize 62
1479 11:45:11.402130 [CA 4] Center 34 (4~65) winsize 62
1480 11:45:11.405404 [CA 5] Center 33 (3~64) winsize 62
1481 11:45:11.405504
1482 11:45:11.408759 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 11:45:11.408861
1484 11:45:11.411997 [CATrainingPosCal] consider 2 rank data
1485 11:45:11.415405 u2DelayCellTimex100 = 270/100 ps
1486 11:45:11.418992 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1487 11:45:11.422248 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1488 11:45:11.429111 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1489 11:45:11.431962 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 11:45:11.435482 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1491 11:45:11.438880 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1492 11:45:11.439013
1493 11:45:11.442299 CA PerBit enable=1, Macro0, CA PI delay=33
1494 11:45:11.442408
1495 11:45:11.445873 [CBTSetCACLKResult] CA Dly = 33
1496 11:45:11.446004 CS Dly: 6 (0~38)
1497 11:45:11.446155
1498 11:45:11.449479 ----->DramcWriteLeveling(PI) begin...
1499 11:45:11.449595 ==
1500 11:45:11.453020 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 11:45:11.457124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 11:45:11.457229 ==
1503 11:45:11.460544 Write leveling (Byte 0): 28 => 28
1504 11:45:11.464498 Write leveling (Byte 1): 28 => 28
1505 11:45:11.468682 DramcWriteLeveling(PI) end<-----
1506 11:45:11.468786
1507 11:45:11.468893 ==
1508 11:45:11.472230 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 11:45:11.475834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 11:45:11.475961 ==
1511 11:45:11.479475 [Gating] SW mode calibration
1512 11:45:11.486005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 11:45:11.489457 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 11:45:11.496326 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 11:45:11.499475 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 11:45:11.502737 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:45:11.509157 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:45:11.512961 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:45:11.516248 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:45:11.522870 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:45:11.526222 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:45:11.529337 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:45:11.532559 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:45:11.539356 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:45:11.542991 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:45:11.545904 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:45:11.552913 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:45:11.556310 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:45:11.559280 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:45:11.566290 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:45:11.569662 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:45:11.572646 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:45:11.579197 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:45:11.582669 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:45:11.586205 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:45:11.592754 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:45:11.596293 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:45:11.599758 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:45:11.603171 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:45:11.609833 0 9 8 | B1->B0 | 2c2c 2929 | 0 1 | (0 0) (0 0)
1541 11:45:11.612665 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:45:11.615886 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:45:11.622680 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:45:11.625864 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:45:11.629224 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:45:11.636205 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:45:11.639340 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1548 11:45:11.642883 0 10 8 | B1->B0 | 2828 2b2b | 0 0 | (1 0) (0 0)
1549 11:45:11.649357 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:45:11.652707 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:45:11.656275 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:45:11.662722 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:45:11.666277 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:45:11.669156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:45:11.676095 0 11 4 | B1->B0 | 2a2a 2626 | 1 1 | (0 0) (0 0)
1556 11:45:11.679546 0 11 8 | B1->B0 | 3c3c 4040 | 1 0 | (0 0) (0 0)
1557 11:45:11.682632 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:45:11.689168 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:45:11.692668 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:45:11.696245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:45:11.702665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:45:11.706225 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:45:11.709051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:45:11.716131 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:45:11.719168 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1566 11:45:11.722315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:45:11.725921 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:45:11.732780 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:45:11.736191 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:45:11.739516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:45:11.745856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:45:11.749542 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:45:11.752653 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:45:11.759436 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:45:11.762987 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:45:11.765977 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:45:11.772997 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:45:11.776260 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:45:11.779232 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1580 11:45:11.786280 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1581 11:45:11.789789 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 11:45:11.792723 Total UI for P1: 0, mck2ui 16
1583 11:45:11.796195 best dqsien dly found for B0: ( 0, 14, 8)
1584 11:45:11.799145 Total UI for P1: 0, mck2ui 16
1585 11:45:11.802826 best dqsien dly found for B1: ( 0, 14, 6)
1586 11:45:11.806370 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1587 11:45:11.809340 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1588 11:45:11.809450
1589 11:45:11.812852 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1590 11:45:11.816179 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1591 11:45:11.819572 [Gating] SW calibration Done
1592 11:45:11.819681 ==
1593 11:45:11.822746 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:45:11.825775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:45:11.825859 ==
1596 11:45:11.829486 RX Vref Scan: 0
1597 11:45:11.829567
1598 11:45:11.829630 RX Vref 0 -> 0, step: 1
1599 11:45:11.832887
1600 11:45:11.832960 RX Delay -130 -> 252, step: 16
1601 11:45:11.839651 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1602 11:45:11.842833 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1603 11:45:11.845891 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1604 11:45:11.849173 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1605 11:45:11.853081 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1606 11:45:11.859353 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1607 11:45:11.862754 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1608 11:45:11.865822 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1609 11:45:11.869344 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1610 11:45:11.872755 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1611 11:45:11.879730 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1612 11:45:11.882558 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1613 11:45:11.886120 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1614 11:45:11.889891 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1615 11:45:11.892985 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1616 11:45:11.899484 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1617 11:45:11.899588 ==
1618 11:45:11.902949 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 11:45:11.905937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 11:45:11.906043 ==
1621 11:45:11.906142 DQS Delay:
1622 11:45:11.909475 DQS0 = 0, DQS1 = 0
1623 11:45:11.909572 DQM Delay:
1624 11:45:11.913038 DQM0 = 81, DQM1 = 72
1625 11:45:11.913137 DQ Delay:
1626 11:45:11.915999 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1627 11:45:11.919572 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1628 11:45:11.923117 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1629 11:45:11.926051 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1630 11:45:11.926162
1631 11:45:11.926256
1632 11:45:11.926342 ==
1633 11:45:11.929453 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 11:45:11.932848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 11:45:11.932923 ==
1636 11:45:11.932984
1637 11:45:11.933042
1638 11:45:11.936041 TX Vref Scan disable
1639 11:45:11.939653 == TX Byte 0 ==
1640 11:45:11.942813 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 11:45:11.946331 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 11:45:11.949166 == TX Byte 1 ==
1643 11:45:11.952792 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 11:45:11.955999 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 11:45:11.956120 ==
1646 11:45:11.959573 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:45:11.962861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 11:45:11.966067 ==
1649 11:45:11.977215 TX Vref=22, minBit 9, minWin=27, winSum=445
1650 11:45:11.980459 TX Vref=24, minBit 11, minWin=27, winSum=450
1651 11:45:11.983797 TX Vref=26, minBit 11, minWin=27, winSum=453
1652 11:45:11.987152 TX Vref=28, minBit 1, minWin=28, winSum=456
1653 11:45:11.990770 TX Vref=30, minBit 1, minWin=28, winSum=459
1654 11:45:11.997309 TX Vref=32, minBit 8, minWin=27, winSum=454
1655 11:45:12.000859 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 30
1656 11:45:12.000962
1657 11:45:12.003888 Final TX Range 1 Vref 30
1658 11:45:12.004000
1659 11:45:12.004092 ==
1660 11:45:12.007426 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 11:45:12.010922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 11:45:12.011023 ==
1663 11:45:12.013901
1664 11:45:12.014005
1665 11:45:12.014094 TX Vref Scan disable
1666 11:45:12.017418 == TX Byte 0 ==
1667 11:45:12.020951 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1668 11:45:12.024431 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1669 11:45:12.028023 == TX Byte 1 ==
1670 11:45:12.031535 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 11:45:12.035044 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 11:45:12.035155
1673 11:45:12.038134 [DATLAT]
1674 11:45:12.038236 Freq=800, CH1 RK0
1675 11:45:12.038336
1676 11:45:12.041547 DATLAT Default: 0xa
1677 11:45:12.041657 0, 0xFFFF, sum = 0
1678 11:45:12.044877 1, 0xFFFF, sum = 0
1679 11:45:12.044994 2, 0xFFFF, sum = 0
1680 11:45:12.048068 3, 0xFFFF, sum = 0
1681 11:45:12.048182 4, 0xFFFF, sum = 0
1682 11:45:12.051787 5, 0xFFFF, sum = 0
1683 11:45:12.051886 6, 0xFFFF, sum = 0
1684 11:45:12.055099 7, 0xFFFF, sum = 0
1685 11:45:12.055209 8, 0xFFFF, sum = 0
1686 11:45:12.058469 9, 0x0, sum = 1
1687 11:45:12.058569 10, 0x0, sum = 2
1688 11:45:12.061709 11, 0x0, sum = 3
1689 11:45:12.061785 12, 0x0, sum = 4
1690 11:45:12.064845 best_step = 10
1691 11:45:12.064923
1692 11:45:12.064986 ==
1693 11:45:12.068040 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 11:45:12.071209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 11:45:12.071329 ==
1696 11:45:12.071435 RX Vref Scan: 1
1697 11:45:12.075083
1698 11:45:12.075213 Set Vref Range= 32 -> 127
1699 11:45:12.075282
1700 11:45:12.078268 RX Vref 32 -> 127, step: 1
1701 11:45:12.078370
1702 11:45:12.081263 RX Delay -111 -> 252, step: 8
1703 11:45:12.081373
1704 11:45:12.084652 Set Vref, RX VrefLevel [Byte0]: 32
1705 11:45:12.088069 [Byte1]: 32
1706 11:45:12.088167
1707 11:45:12.091584 Set Vref, RX VrefLevel [Byte0]: 33
1708 11:45:12.094693 [Byte1]: 33
1709 11:45:12.094802
1710 11:45:12.098374 Set Vref, RX VrefLevel [Byte0]: 34
1711 11:45:12.101314 [Byte1]: 34
1712 11:45:12.105410
1713 11:45:12.105512 Set Vref, RX VrefLevel [Byte0]: 35
1714 11:45:12.108824 [Byte1]: 35
1715 11:45:12.112982
1716 11:45:12.113089 Set Vref, RX VrefLevel [Byte0]: 36
1717 11:45:12.116446 [Byte1]: 36
1718 11:45:12.120672
1719 11:45:12.120773 Set Vref, RX VrefLevel [Byte0]: 37
1720 11:45:12.124301 [Byte1]: 37
1721 11:45:12.128267
1722 11:45:12.128373 Set Vref, RX VrefLevel [Byte0]: 38
1723 11:45:12.131819 [Byte1]: 38
1724 11:45:12.135928
1725 11:45:12.136032 Set Vref, RX VrefLevel [Byte0]: 39
1726 11:45:12.139370 [Byte1]: 39
1727 11:45:12.143499
1728 11:45:12.143573 Set Vref, RX VrefLevel [Byte0]: 40
1729 11:45:12.147133 [Byte1]: 40
1730 11:45:12.151121
1731 11:45:12.151250 Set Vref, RX VrefLevel [Byte0]: 41
1732 11:45:12.154926 [Byte1]: 41
1733 11:45:12.159310
1734 11:45:12.159411 Set Vref, RX VrefLevel [Byte0]: 42
1735 11:45:12.162592 [Byte1]: 42
1736 11:45:12.166735
1737 11:45:12.166838 Set Vref, RX VrefLevel [Byte0]: 43
1738 11:45:12.170184 [Byte1]: 43
1739 11:45:12.174136
1740 11:45:12.174218 Set Vref, RX VrefLevel [Byte0]: 44
1741 11:45:12.177452 [Byte1]: 44
1742 11:45:12.182039
1743 11:45:12.182124 Set Vref, RX VrefLevel [Byte0]: 45
1744 11:45:12.185359 [Byte1]: 45
1745 11:45:12.189854
1746 11:45:12.189964 Set Vref, RX VrefLevel [Byte0]: 46
1747 11:45:12.193269 [Byte1]: 46
1748 11:45:12.197109
1749 11:45:12.197227 Set Vref, RX VrefLevel [Byte0]: 47
1750 11:45:12.200740 [Byte1]: 47
1751 11:45:12.204879
1752 11:45:12.204987 Set Vref, RX VrefLevel [Byte0]: 48
1753 11:45:12.208070 [Byte1]: 48
1754 11:45:12.212703
1755 11:45:12.212801 Set Vref, RX VrefLevel [Byte0]: 49
1756 11:45:12.215713 [Byte1]: 49
1757 11:45:12.220417
1758 11:45:12.220548 Set Vref, RX VrefLevel [Byte0]: 50
1759 11:45:12.223405 [Byte1]: 50
1760 11:45:12.228128
1761 11:45:12.228258 Set Vref, RX VrefLevel [Byte0]: 51
1762 11:45:12.231001 [Byte1]: 51
1763 11:45:12.235747
1764 11:45:12.235849 Set Vref, RX VrefLevel [Byte0]: 52
1765 11:45:12.238753 [Byte1]: 52
1766 11:45:12.243539
1767 11:45:12.243649 Set Vref, RX VrefLevel [Byte0]: 53
1768 11:45:12.246329 [Byte1]: 53
1769 11:45:12.251122
1770 11:45:12.251231 Set Vref, RX VrefLevel [Byte0]: 54
1771 11:45:12.254073 [Byte1]: 54
1772 11:45:12.258287
1773 11:45:12.258387 Set Vref, RX VrefLevel [Byte0]: 55
1774 11:45:12.261722 [Byte1]: 55
1775 11:45:12.266098
1776 11:45:12.266173 Set Vref, RX VrefLevel [Byte0]: 56
1777 11:45:12.269395 [Byte1]: 56
1778 11:45:12.273775
1779 11:45:12.273884 Set Vref, RX VrefLevel [Byte0]: 57
1780 11:45:12.276971 [Byte1]: 57
1781 11:45:12.281697
1782 11:45:12.281783 Set Vref, RX VrefLevel [Byte0]: 58
1783 11:45:12.284615 [Byte1]: 58
1784 11:45:12.289323
1785 11:45:12.289403 Set Vref, RX VrefLevel [Byte0]: 59
1786 11:45:12.292126 [Byte1]: 59
1787 11:45:12.296717
1788 11:45:12.296826 Set Vref, RX VrefLevel [Byte0]: 60
1789 11:45:12.300450 [Byte1]: 60
1790 11:45:12.304494
1791 11:45:12.304574 Set Vref, RX VrefLevel [Byte0]: 61
1792 11:45:12.307503 [Byte1]: 61
1793 11:45:12.312136
1794 11:45:12.312254 Set Vref, RX VrefLevel [Byte0]: 62
1795 11:45:12.315092 [Byte1]: 62
1796 11:45:12.319778
1797 11:45:12.319881 Set Vref, RX VrefLevel [Byte0]: 63
1798 11:45:12.326363 [Byte1]: 63
1799 11:45:12.326440
1800 11:45:12.329380 Set Vref, RX VrefLevel [Byte0]: 64
1801 11:45:12.332862 [Byte1]: 64
1802 11:45:12.332949
1803 11:45:12.336356 Set Vref, RX VrefLevel [Byte0]: 65
1804 11:45:12.339279 [Byte1]: 65
1805 11:45:12.342915
1806 11:45:12.342988 Set Vref, RX VrefLevel [Byte0]: 66
1807 11:45:12.345837 [Byte1]: 66
1808 11:45:12.350483
1809 11:45:12.350557 Set Vref, RX VrefLevel [Byte0]: 67
1810 11:45:12.353521 [Byte1]: 67
1811 11:45:12.358132
1812 11:45:12.358204 Set Vref, RX VrefLevel [Byte0]: 68
1813 11:45:12.361100 [Byte1]: 68
1814 11:45:12.365617
1815 11:45:12.365687 Set Vref, RX VrefLevel [Byte0]: 69
1816 11:45:12.368923 [Byte1]: 69
1817 11:45:12.373402
1818 11:45:12.373473 Set Vref, RX VrefLevel [Byte0]: 70
1819 11:45:12.376429 [Byte1]: 70
1820 11:45:12.380837
1821 11:45:12.380917 Set Vref, RX VrefLevel [Byte0]: 71
1822 11:45:12.383927 [Byte1]: 71
1823 11:45:12.388574
1824 11:45:12.388658 Set Vref, RX VrefLevel [Byte0]: 72
1825 11:45:12.392018 [Byte1]: 72
1826 11:45:12.396208
1827 11:45:12.396306 Set Vref, RX VrefLevel [Byte0]: 73
1828 11:45:12.399714 [Byte1]: 73
1829 11:45:12.403766
1830 11:45:12.403849 Final RX Vref Byte 0 = 52 to rank0
1831 11:45:12.407165 Final RX Vref Byte 1 = 62 to rank0
1832 11:45:12.410562 Final RX Vref Byte 0 = 52 to rank1
1833 11:45:12.413799 Final RX Vref Byte 1 = 62 to rank1==
1834 11:45:12.417013 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 11:45:12.423809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 11:45:12.423891 ==
1837 11:45:12.423955 DQS Delay:
1838 11:45:12.424014 DQS0 = 0, DQS1 = 0
1839 11:45:12.427264 DQM Delay:
1840 11:45:12.427348 DQM0 = 80, DQM1 = 70
1841 11:45:12.430515 DQ Delay:
1842 11:45:12.433921 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1843 11:45:12.434028 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1844 11:45:12.437296 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1845 11:45:12.440762 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1846 11:45:12.443720
1847 11:45:12.443830
1848 11:45:12.450254 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1849 11:45:12.453820 CH1 RK0: MR19=606, MR18=F19
1850 11:45:12.460382 CH1_RK0: MR19=0x606, MR18=0xF19, DQSOSC=403, MR23=63, INC=90, DEC=60
1851 11:45:12.460463
1852 11:45:12.463804 ----->DramcWriteLeveling(PI) begin...
1853 11:45:12.463886 ==
1854 11:45:12.467350 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 11:45:12.470378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 11:45:12.470459 ==
1857 11:45:12.473735 Write leveling (Byte 0): 29 => 29
1858 11:45:12.477075 Write leveling (Byte 1): 29 => 29
1859 11:45:12.480526 DramcWriteLeveling(PI) end<-----
1860 11:45:12.480608
1861 11:45:12.480672 ==
1862 11:45:12.483459 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 11:45:12.486863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 11:45:12.486945 ==
1865 11:45:12.490103 [Gating] SW mode calibration
1866 11:45:12.497287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 11:45:12.503734 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 11:45:12.507100 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 11:45:12.510081 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 11:45:12.517020 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 11:45:12.520384 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:45:12.523669 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:45:12.530667 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:45:12.533955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:45:12.536926 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:45:12.540212 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:45:12.546829 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:45:12.550231 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:45:12.553502 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:45:12.560619 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:45:12.564073 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:45:12.567113 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:45:12.573477 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:45:12.577080 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:45:12.580339 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1886 11:45:12.587263 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:45:12.590719 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:45:12.593510 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:45:12.600319 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:45:12.603715 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:45:12.607077 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:45:12.613526 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:45:12.616970 0 9 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
1894 11:45:12.620498 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1895 11:45:12.626892 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:45:12.630744 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:45:12.633662 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:45:12.637455 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:45:12.643911 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:45:12.646983 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1901 11:45:12.650335 0 10 4 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 1)
1902 11:45:12.657177 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1903 11:45:12.660269 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:45:12.664103 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:45:12.670224 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:45:12.673740 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:45:12.677639 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:45:12.684028 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1909 11:45:12.687223 0 11 4 | B1->B0 | 2f2f 3a39 | 0 1 | (0 0) (0 0)
1910 11:45:12.690595 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 11:45:12.697421 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:45:12.700192 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:45:12.703808 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:45:12.710769 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:45:12.714058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:45:12.717048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 11:45:12.724034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:45:12.726938 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 11:45:12.730434 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:45:12.733836 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:45:12.740708 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:45:12.743641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:45:12.747176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:45:12.753501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:45:12.757018 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:45:12.760488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:45:12.766969 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:45:12.770675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:45:12.773924 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:45:12.780286 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:45:12.783783 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:45:12.786799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:45:12.793643 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1934 11:45:12.793750 Total UI for P1: 0, mck2ui 16
1935 11:45:12.800601 best dqsien dly found for B0: ( 0, 14, 2)
1936 11:45:12.804020 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 11:45:12.806961 Total UI for P1: 0, mck2ui 16
1938 11:45:12.810528 best dqsien dly found for B1: ( 0, 14, 4)
1939 11:45:12.814066 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1940 11:45:12.817537 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1941 11:45:12.817633
1942 11:45:12.820364 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1943 11:45:12.823856 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 11:45:12.827226 [Gating] SW calibration Done
1945 11:45:12.827306 ==
1946 11:45:12.830647 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 11:45:12.833659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 11:45:12.833770 ==
1949 11:45:12.837290 RX Vref Scan: 0
1950 11:45:12.837394
1951 11:45:12.840675 RX Vref 0 -> 0, step: 1
1952 11:45:12.840751
1953 11:45:12.840813 RX Delay -130 -> 252, step: 16
1954 11:45:12.846724 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1955 11:45:12.850316 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1956 11:45:12.853790 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1957 11:45:12.857194 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1958 11:45:12.860130 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1959 11:45:12.867221 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1960 11:45:12.870067 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1961 11:45:12.873887 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1962 11:45:12.877198 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1963 11:45:12.880041 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1964 11:45:12.886916 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1965 11:45:12.890500 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1966 11:45:12.893999 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1967 11:45:12.896875 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1968 11:45:12.900078 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1969 11:45:12.906897 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1970 11:45:12.907000 ==
1971 11:45:12.910198 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 11:45:12.913725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 11:45:12.913825 ==
1974 11:45:12.913915 DQS Delay:
1975 11:45:12.917225 DQS0 = 0, DQS1 = 0
1976 11:45:12.917300 DQM Delay:
1977 11:45:12.920126 DQM0 = 79, DQM1 = 71
1978 11:45:12.920262 DQ Delay:
1979 11:45:12.923598 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1980 11:45:12.926975 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1981 11:45:12.930345 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1982 11:45:12.933672 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1983 11:45:12.933746
1984 11:45:12.933810
1985 11:45:12.933867 ==
1986 11:45:12.937208 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 11:45:12.940147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 11:45:12.940306 ==
1989 11:45:12.940397
1990 11:45:12.943599
1991 11:45:12.943725 TX Vref Scan disable
1992 11:45:12.947124 == TX Byte 0 ==
1993 11:45:12.950379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 11:45:12.953359 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 11:45:12.956608 == TX Byte 1 ==
1996 11:45:12.960184 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 11:45:12.963566 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 11:45:12.963652 ==
1999 11:45:12.967017 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:45:12.973566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:45:12.973666 ==
2002 11:45:12.985352 TX Vref=22, minBit 5, minWin=27, winSum=449
2003 11:45:12.988723 TX Vref=24, minBit 11, minWin=27, winSum=455
2004 11:45:12.992061 TX Vref=26, minBit 9, minWin=28, winSum=460
2005 11:45:12.994972 TX Vref=28, minBit 9, minWin=28, winSum=460
2006 11:45:12.998443 TX Vref=30, minBit 5, minWin=28, winSum=459
2007 11:45:13.005179 TX Vref=32, minBit 2, minWin=28, winSum=456
2008 11:45:13.008658 [TxChooseVref] Worse bit 9, Min win 28, Win sum 460, Final Vref 26
2009 11:45:13.008738
2010 11:45:13.011874 Final TX Range 1 Vref 26
2011 11:45:13.011981
2012 11:45:13.012073 ==
2013 11:45:13.015273 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 11:45:13.018574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 11:45:13.018677 ==
2016 11:45:13.021448
2017 11:45:13.021546
2018 11:45:13.021634 TX Vref Scan disable
2019 11:45:13.024851 == TX Byte 0 ==
2020 11:45:13.028409 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2021 11:45:13.031882 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2022 11:45:13.034851 == TX Byte 1 ==
2023 11:45:13.038204 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 11:45:13.041811 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 11:45:13.044754
2026 11:45:13.044825 [DATLAT]
2027 11:45:13.044885 Freq=800, CH1 RK1
2028 11:45:13.044943
2029 11:45:13.048237 DATLAT Default: 0xa
2030 11:45:13.048304 0, 0xFFFF, sum = 0
2031 11:45:13.051848 1, 0xFFFF, sum = 0
2032 11:45:13.051929 2, 0xFFFF, sum = 0
2033 11:45:13.055373 3, 0xFFFF, sum = 0
2034 11:45:13.055455 4, 0xFFFF, sum = 0
2035 11:45:13.058877 5, 0xFFFF, sum = 0
2036 11:45:13.058959 6, 0xFFFF, sum = 0
2037 11:45:13.061916 7, 0xFFFF, sum = 0
2038 11:45:13.065145 8, 0xFFFF, sum = 0
2039 11:45:13.065228 9, 0x0, sum = 1
2040 11:45:13.065311 10, 0x0, sum = 2
2041 11:45:13.068494 11, 0x0, sum = 3
2042 11:45:13.068569 12, 0x0, sum = 4
2043 11:45:13.071593 best_step = 10
2044 11:45:13.071667
2045 11:45:13.071727 ==
2046 11:45:13.075049 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 11:45:13.078740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 11:45:13.078813 ==
2049 11:45:13.082153 RX Vref Scan: 0
2050 11:45:13.082223
2051 11:45:13.082288 RX Vref 0 -> 0, step: 1
2052 11:45:13.082351
2053 11:45:13.084871 RX Delay -111 -> 252, step: 8
2054 11:45:13.091730 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2055 11:45:13.095458 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2056 11:45:13.098781 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2057 11:45:13.101770 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2058 11:45:13.105165 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2059 11:45:13.111953 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2060 11:45:13.114848 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2061 11:45:13.118271 iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240
2062 11:45:13.121568 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
2063 11:45:13.124984 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2064 11:45:13.131437 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2065 11:45:13.135000 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2066 11:45:13.138672 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
2067 11:45:13.141476 iDelay=209, Bit 13, Center 76 (-47 ~ 200) 248
2068 11:45:13.148141 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2069 11:45:13.151314 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2070 11:45:13.151402 ==
2071 11:45:13.154715 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 11:45:13.158196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 11:45:13.158267 ==
2074 11:45:13.158346 DQS Delay:
2075 11:45:13.161847 DQS0 = 0, DQS1 = 0
2076 11:45:13.161946 DQM Delay:
2077 11:45:13.164671 DQM0 = 76, DQM1 = 71
2078 11:45:13.164768 DQ Delay:
2079 11:45:13.167982 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2080 11:45:13.171613 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =72
2081 11:45:13.174838 DQ8 =56, DQ9 =64, DQ10 =76, DQ11 =68
2082 11:45:13.178259 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
2083 11:45:13.178370
2084 11:45:13.178459
2085 11:45:13.188050 [DQSOSCAuto] RK1, (LSB)MR18= 0x233c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2086 11:45:13.188152 CH1 RK1: MR19=606, MR18=233C
2087 11:45:13.195078 CH1_RK1: MR19=0x606, MR18=0x233C, DQSOSC=394, MR23=63, INC=95, DEC=63
2088 11:45:13.198341 [RxdqsGatingPostProcess] freq 800
2089 11:45:13.204778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 11:45:13.208057 Pre-setting of DQS Precalculation
2091 11:45:13.210974 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 11:45:13.217886 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 11:45:13.228404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 11:45:13.228486
2095 11:45:13.228550
2096 11:45:13.231017 [Calibration Summary] 1600 Mbps
2097 11:45:13.231093 CH 0, Rank 0
2098 11:45:13.234641 SW Impedance : PASS
2099 11:45:13.234712 DUTY Scan : NO K
2100 11:45:13.238214 ZQ Calibration : PASS
2101 11:45:13.238286 Jitter Meter : NO K
2102 11:45:13.241248 CBT Training : PASS
2103 11:45:13.244724 Write leveling : PASS
2104 11:45:13.244804 RX DQS gating : PASS
2105 11:45:13.248152 RX DQ/DQS(RDDQC) : PASS
2106 11:45:13.251172 TX DQ/DQS : PASS
2107 11:45:13.251278 RX DATLAT : PASS
2108 11:45:13.254741 RX DQ/DQS(Engine): PASS
2109 11:45:13.257780 TX OE : NO K
2110 11:45:13.257855 All Pass.
2111 11:45:13.257930
2112 11:45:13.257993 CH 0, Rank 1
2113 11:45:13.261118 SW Impedance : PASS
2114 11:45:13.264427 DUTY Scan : NO K
2115 11:45:13.264532 ZQ Calibration : PASS
2116 11:45:13.267848 Jitter Meter : NO K
2117 11:45:13.271198 CBT Training : PASS
2118 11:45:13.271310 Write leveling : PASS
2119 11:45:13.274702 RX DQS gating : PASS
2120 11:45:13.274800 RX DQ/DQS(RDDQC) : PASS
2121 11:45:13.278116 TX DQ/DQS : PASS
2122 11:45:13.280976 RX DATLAT : PASS
2123 11:45:13.281049 RX DQ/DQS(Engine): PASS
2124 11:45:13.284445 TX OE : NO K
2125 11:45:13.284518 All Pass.
2126 11:45:13.284580
2127 11:45:13.288012 CH 1, Rank 0
2128 11:45:13.288111 SW Impedance : PASS
2129 11:45:13.291370 DUTY Scan : NO K
2130 11:45:13.294761 ZQ Calibration : PASS
2131 11:45:13.294870 Jitter Meter : NO K
2132 11:45:13.297672 CBT Training : PASS
2133 11:45:13.301123 Write leveling : PASS
2134 11:45:13.301241 RX DQS gating : PASS
2135 11:45:13.304688 RX DQ/DQS(RDDQC) : PASS
2136 11:45:13.308115 TX DQ/DQS : PASS
2137 11:45:13.308267 RX DATLAT : PASS
2138 11:45:13.311524 RX DQ/DQS(Engine): PASS
2139 11:45:13.311621 TX OE : NO K
2140 11:45:13.314774 All Pass.
2141 11:45:13.314877
2142 11:45:13.314978 CH 1, Rank 1
2143 11:45:13.317994 SW Impedance : PASS
2144 11:45:13.318117 DUTY Scan : NO K
2145 11:45:13.321477 ZQ Calibration : PASS
2146 11:45:13.324482 Jitter Meter : NO K
2147 11:45:13.324575 CBT Training : PASS
2148 11:45:13.327904 Write leveling : PASS
2149 11:45:13.331395 RX DQS gating : PASS
2150 11:45:13.331472 RX DQ/DQS(RDDQC) : PASS
2151 11:45:13.334750 TX DQ/DQS : PASS
2152 11:45:13.337650 RX DATLAT : PASS
2153 11:45:13.337726 RX DQ/DQS(Engine): PASS
2154 11:45:13.341282 TX OE : NO K
2155 11:45:13.341409 All Pass.
2156 11:45:13.341519
2157 11:45:13.344800 DramC Write-DBI off
2158 11:45:13.347687 PER_BANK_REFRESH: Hybrid Mode
2159 11:45:13.347761 TX_TRACKING: ON
2160 11:45:13.351181 [GetDramInforAfterCalByMRR] Vendor 6.
2161 11:45:13.354760 [GetDramInforAfterCalByMRR] Revision 606.
2162 11:45:13.357704 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 11:45:13.361158 MR0 0x3b3b
2164 11:45:13.361232 MR8 0x5151
2165 11:45:13.364515 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 11:45:13.364591
2167 11:45:13.364653 MR0 0x3b3b
2168 11:45:13.367789 MR8 0x5151
2169 11:45:13.371202 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 11:45:13.371309
2171 11:45:13.381285 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 11:45:13.384149 [FAST_K] Save calibration result to emmc
2173 11:45:13.387901 [FAST_K] Save calibration result to emmc
2174 11:45:13.388001 dram_init: config_dvfs: 1
2175 11:45:13.394666 dramc_set_vcore_voltage set vcore to 662500
2176 11:45:13.394761 Read voltage for 1200, 2
2177 11:45:13.397610 Vio18 = 0
2178 11:45:13.397688 Vcore = 662500
2179 11:45:13.397751 Vdram = 0
2180 11:45:13.400908 Vddq = 0
2181 11:45:13.400983 Vmddr = 0
2182 11:45:13.404373 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 11:45:13.411320 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 11:45:13.414276 MEM_TYPE=3, freq_sel=15
2185 11:45:13.417743 sv_algorithm_assistance_LP4_1600
2186 11:45:13.421121 ============ PULL DRAM RESETB DOWN ============
2187 11:45:13.424343 ========== PULL DRAM RESETB DOWN end =========
2188 11:45:13.427523 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 11:45:13.431003 ===================================
2190 11:45:13.434575 LPDDR4 DRAM CONFIGURATION
2191 11:45:13.437715 ===================================
2192 11:45:13.440967 EX_ROW_EN[0] = 0x0
2193 11:45:13.441051 EX_ROW_EN[1] = 0x0
2194 11:45:13.444456 LP4Y_EN = 0x0
2195 11:45:13.444541 WORK_FSP = 0x0
2196 11:45:13.447468 WL = 0x4
2197 11:45:13.447545 RL = 0x4
2198 11:45:13.450920 BL = 0x2
2199 11:45:13.450996 RPST = 0x0
2200 11:45:13.454419 RD_PRE = 0x0
2201 11:45:13.454491 WR_PRE = 0x1
2202 11:45:13.457418 WR_PST = 0x0
2203 11:45:13.457495 DBI_WR = 0x0
2204 11:45:13.461128 DBI_RD = 0x0
2205 11:45:13.461204 OTF = 0x1
2206 11:45:13.464043 ===================================
2207 11:45:13.467707 ===================================
2208 11:45:13.471240 ANA top config
2209 11:45:13.474061 ===================================
2210 11:45:13.477452 DLL_ASYNC_EN = 0
2211 11:45:13.477530 ALL_SLAVE_EN = 0
2212 11:45:13.480843 NEW_RANK_MODE = 1
2213 11:45:13.484014 DLL_IDLE_MODE = 1
2214 11:45:13.487788 LP45_APHY_COMB_EN = 1
2215 11:45:13.487867 TX_ODT_DIS = 1
2216 11:45:13.490705 NEW_8X_MODE = 1
2217 11:45:13.494189 ===================================
2218 11:45:13.497460 ===================================
2219 11:45:13.500792 data_rate = 2400
2220 11:45:13.504151 CKR = 1
2221 11:45:13.507608 DQ_P2S_RATIO = 8
2222 11:45:13.510984 ===================================
2223 11:45:13.514493 CA_P2S_RATIO = 8
2224 11:45:13.514575 DQ_CA_OPEN = 0
2225 11:45:13.518006 DQ_SEMI_OPEN = 0
2226 11:45:13.520914 CA_SEMI_OPEN = 0
2227 11:45:13.524461 CA_FULL_RATE = 0
2228 11:45:13.528072 DQ_CKDIV4_EN = 0
2229 11:45:13.528153 CA_CKDIV4_EN = 0
2230 11:45:13.531357 CA_PREDIV_EN = 0
2231 11:45:13.534675 PH8_DLY = 17
2232 11:45:13.537817 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 11:45:13.541628 DQ_AAMCK_DIV = 4
2234 11:45:13.544549 CA_AAMCK_DIV = 4
2235 11:45:13.544626 CA_ADMCK_DIV = 4
2236 11:45:13.547921 DQ_TRACK_CA_EN = 0
2237 11:45:13.551516 CA_PICK = 1200
2238 11:45:13.554534 CA_MCKIO = 1200
2239 11:45:13.558140 MCKIO_SEMI = 0
2240 11:45:13.561159 PLL_FREQ = 2366
2241 11:45:13.564789 DQ_UI_PI_RATIO = 32
2242 11:45:13.564866 CA_UI_PI_RATIO = 0
2243 11:45:13.568237 ===================================
2244 11:45:13.571229 ===================================
2245 11:45:13.574798 memory_type:LPDDR4
2246 11:45:13.578335 GP_NUM : 10
2247 11:45:13.578419 SRAM_EN : 1
2248 11:45:13.581251 MD32_EN : 0
2249 11:45:13.584809 ===================================
2250 11:45:13.587725 [ANA_INIT] >>>>>>>>>>>>>>
2251 11:45:13.591537 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 11:45:13.594694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 11:45:13.598000 ===================================
2254 11:45:13.598078 data_rate = 2400,PCW = 0X5b00
2255 11:45:13.601358 ===================================
2256 11:45:13.604737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 11:45:13.611653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 11:45:13.617858 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 11:45:13.621400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 11:45:13.625035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 11:45:13.628056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 11:45:13.631512 [ANA_INIT] flow start
2263 11:45:13.631591 [ANA_INIT] PLL >>>>>>>>
2264 11:45:13.635032 [ANA_INIT] PLL <<<<<<<<
2265 11:45:13.638099 [ANA_INIT] MIDPI >>>>>>>>
2266 11:45:13.641549 [ANA_INIT] MIDPI <<<<<<<<
2267 11:45:13.641626 [ANA_INIT] DLL >>>>>>>>
2268 11:45:13.644724 [ANA_INIT] DLL <<<<<<<<
2269 11:45:13.644801 [ANA_INIT] flow end
2270 11:45:13.651375 ============ LP4 DIFF to SE enter ============
2271 11:45:13.654574 ============ LP4 DIFF to SE exit ============
2272 11:45:13.658203 [ANA_INIT] <<<<<<<<<<<<<
2273 11:45:13.661737 [Flow] Enable top DCM control >>>>>
2274 11:45:13.664776 [Flow] Enable top DCM control <<<<<
2275 11:45:13.668270 Enable DLL master slave shuffle
2276 11:45:13.671235 ==============================================================
2277 11:45:13.674712 Gating Mode config
2278 11:45:13.678236 ==============================================================
2279 11:45:13.681133 Config description:
2280 11:45:13.691503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 11:45:13.697959 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 11:45:13.701357 SELPH_MODE 0: By rank 1: By Phase
2283 11:45:13.707979 ==============================================================
2284 11:45:13.711340 GAT_TRACK_EN = 1
2285 11:45:13.714609 RX_GATING_MODE = 2
2286 11:45:13.718133 RX_GATING_TRACK_MODE = 2
2287 11:45:13.718211 SELPH_MODE = 1
2288 11:45:13.721257 PICG_EARLY_EN = 1
2289 11:45:13.724815 VALID_LAT_VALUE = 1
2290 11:45:13.731219 ==============================================================
2291 11:45:13.734731 Enter into Gating configuration >>>>
2292 11:45:13.738220 Exit from Gating configuration <<<<
2293 11:45:13.741706 Enter into DVFS_PRE_config >>>>>
2294 11:45:13.751408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 11:45:13.754903 Exit from DVFS_PRE_config <<<<<
2296 11:45:13.758221 Enter into PICG configuration >>>>
2297 11:45:13.761497 Exit from PICG configuration <<<<
2298 11:45:13.764730 [RX_INPUT] configuration >>>>>
2299 11:45:13.768115 [RX_INPUT] configuration <<<<<
2300 11:45:13.771722 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 11:45:13.778316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 11:45:13.785248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 11:45:13.791826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 11:45:13.794631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 11:45:13.801754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 11:45:13.804693 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 11:45:13.811525 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 11:45:13.814927 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 11:45:13.818225 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 11:45:13.821628 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 11:45:13.828194 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 11:45:13.831536 ===================================
2313 11:45:13.831616 LPDDR4 DRAM CONFIGURATION
2314 11:45:13.835232 ===================================
2315 11:45:13.838542 EX_ROW_EN[0] = 0x0
2316 11:45:13.841989 EX_ROW_EN[1] = 0x0
2317 11:45:13.842102 LP4Y_EN = 0x0
2318 11:45:13.844904 WORK_FSP = 0x0
2319 11:45:13.844978 WL = 0x4
2320 11:45:13.848451 RL = 0x4
2321 11:45:13.848524 BL = 0x2
2322 11:45:13.851480 RPST = 0x0
2323 11:45:13.851554 RD_PRE = 0x0
2324 11:45:13.854905 WR_PRE = 0x1
2325 11:45:13.854979 WR_PST = 0x0
2326 11:45:13.858232 DBI_WR = 0x0
2327 11:45:13.858315 DBI_RD = 0x0
2328 11:45:13.861710 OTF = 0x1
2329 11:45:13.864711 ===================================
2330 11:45:13.867999 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 11:45:13.871696 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 11:45:13.878380 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 11:45:13.881288 ===================================
2334 11:45:13.881370 LPDDR4 DRAM CONFIGURATION
2335 11:45:13.884804 ===================================
2336 11:45:13.888294 EX_ROW_EN[0] = 0x10
2337 11:45:13.888375 EX_ROW_EN[1] = 0x0
2338 11:45:13.891688 LP4Y_EN = 0x0
2339 11:45:13.894667 WORK_FSP = 0x0
2340 11:45:13.894743 WL = 0x4
2341 11:45:13.898176 RL = 0x4
2342 11:45:13.898251 BL = 0x2
2343 11:45:13.901694 RPST = 0x0
2344 11:45:13.901770 RD_PRE = 0x0
2345 11:45:13.905106 WR_PRE = 0x1
2346 11:45:13.905191 WR_PST = 0x0
2347 11:45:13.908091 DBI_WR = 0x0
2348 11:45:13.908169 DBI_RD = 0x0
2349 11:45:13.911566 OTF = 0x1
2350 11:45:13.915055 ===================================
2351 11:45:13.917959 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 11:45:13.921409 ==
2353 11:45:13.924818 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 11:45:13.928130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 11:45:13.928240 ==
2356 11:45:13.931416 [Duty_Offset_Calibration]
2357 11:45:13.931502 B0:2 B1:0 CA:3
2358 11:45:13.931568
2359 11:45:13.934884 [DutyScan_Calibration_Flow] k_type=0
2360 11:45:13.944711
2361 11:45:13.944806 ==CLK 0==
2362 11:45:13.947982 Final CLK duty delay cell = 0
2363 11:45:13.951498 [0] MAX Duty = 5000%(X100), DQS PI = 12
2364 11:45:13.954455 [0] MIN Duty = 4906%(X100), DQS PI = 54
2365 11:45:13.954540 [0] AVG Duty = 4953%(X100)
2366 11:45:13.954604
2367 11:45:13.957935 CH0 CLK Duty spec in!! Max-Min= 94%
2368 11:45:13.964731 [DutyScan_Calibration_Flow] ====Done====
2369 11:45:13.964810
2370 11:45:13.967746 [DutyScan_Calibration_Flow] k_type=1
2371 11:45:13.983055
2372 11:45:13.983142 ==DQS 0 ==
2373 11:45:13.986415 Final DQS duty delay cell = 0
2374 11:45:13.989961 [0] MAX Duty = 5062%(X100), DQS PI = 12
2375 11:45:13.992818 [0] MIN Duty = 4907%(X100), DQS PI = 4
2376 11:45:13.992904 [0] AVG Duty = 4984%(X100)
2377 11:45:13.996306
2378 11:45:13.996394 ==DQS 1 ==
2379 11:45:13.999817 Final DQS duty delay cell = -4
2380 11:45:14.002873 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2381 11:45:14.006316 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2382 11:45:14.009831 [-4] AVG Duty = 4938%(X100)
2383 11:45:14.009909
2384 11:45:14.012857 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2385 11:45:14.012933
2386 11:45:14.016222 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2387 11:45:14.019638 [DutyScan_Calibration_Flow] ====Done====
2388 11:45:14.019716
2389 11:45:14.022686 [DutyScan_Calibration_Flow] k_type=3
2390 11:45:14.040320
2391 11:45:14.040420 ==DQM 0 ==
2392 11:45:14.043731 Final DQM duty delay cell = 0
2393 11:45:14.047154 [0] MAX Duty = 5124%(X100), DQS PI = 12
2394 11:45:14.050322 [0] MIN Duty = 4907%(X100), DQS PI = 0
2395 11:45:14.050403 [0] AVG Duty = 5015%(X100)
2396 11:45:14.053684
2397 11:45:14.053764 ==DQM 1 ==
2398 11:45:14.057153 Final DQM duty delay cell = 4
2399 11:45:14.060049 [4] MAX Duty = 5124%(X100), DQS PI = 50
2400 11:45:14.063611 [4] MIN Duty = 5000%(X100), DQS PI = 14
2401 11:45:14.063689 [4] AVG Duty = 5062%(X100)
2402 11:45:14.066900
2403 11:45:14.070333 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2404 11:45:14.070409
2405 11:45:14.073319 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2406 11:45:14.076880 [DutyScan_Calibration_Flow] ====Done====
2407 11:45:14.076955
2408 11:45:14.079894 [DutyScan_Calibration_Flow] k_type=2
2409 11:45:14.095159
2410 11:45:14.095247 ==DQ 0 ==
2411 11:45:14.098604 Final DQ duty delay cell = -4
2412 11:45:14.101926 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2413 11:45:14.104893 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2414 11:45:14.108316 [-4] AVG Duty = 4969%(X100)
2415 11:45:14.108392
2416 11:45:14.108454 ==DQ 1 ==
2417 11:45:14.111874 Final DQ duty delay cell = -4
2418 11:45:14.114793 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2419 11:45:14.118161 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2420 11:45:14.121503 [-4] AVG Duty = 4938%(X100)
2421 11:45:14.121576
2422 11:45:14.125044 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2423 11:45:14.125116
2424 11:45:14.128693 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 11:45:14.131604 [DutyScan_Calibration_Flow] ====Done====
2426 11:45:14.131685 ==
2427 11:45:14.135043 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 11:45:14.138427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 11:45:14.138508 ==
2430 11:45:14.141637 [Duty_Offset_Calibration]
2431 11:45:14.141714 B0:1 B1:-2 CA:0
2432 11:45:14.141791
2433 11:45:14.145102 [DutyScan_Calibration_Flow] k_type=0
2434 11:45:14.155305
2435 11:45:14.155385 ==CLK 0==
2436 11:45:14.158640 Final CLK duty delay cell = 0
2437 11:45:14.161949 [0] MAX Duty = 5031%(X100), DQS PI = 18
2438 11:45:14.165678 [0] MIN Duty = 4844%(X100), DQS PI = 58
2439 11:45:14.165761 [0] AVG Duty = 4937%(X100)
2440 11:45:14.169089
2441 11:45:14.172559 CH1 CLK Duty spec in!! Max-Min= 187%
2442 11:45:14.175441 [DutyScan_Calibration_Flow] ====Done====
2443 11:45:14.175513
2444 11:45:14.179030 [DutyScan_Calibration_Flow] k_type=1
2445 11:45:14.194132
2446 11:45:14.194215 ==DQS 0 ==
2447 11:45:14.197350 Final DQS duty delay cell = -4
2448 11:45:14.200671 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2449 11:45:14.204225 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2450 11:45:14.207951 [-4] AVG Duty = 4969%(X100)
2451 11:45:14.208038
2452 11:45:14.208103 ==DQS 1 ==
2453 11:45:14.210686 Final DQS duty delay cell = 0
2454 11:45:14.214395 [0] MAX Duty = 5093%(X100), DQS PI = 0
2455 11:45:14.217890 [0] MIN Duty = 4875%(X100), DQS PI = 26
2456 11:45:14.217966 [0] AVG Duty = 4984%(X100)
2457 11:45:14.220990
2458 11:45:14.224501 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2459 11:45:14.224578
2460 11:45:14.227902 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 11:45:14.230841 [DutyScan_Calibration_Flow] ====Done====
2462 11:45:14.230924
2463 11:45:14.234341 [DutyScan_Calibration_Flow] k_type=3
2464 11:45:14.250678
2465 11:45:14.250757 ==DQM 0 ==
2466 11:45:14.253925 Final DQM duty delay cell = 0
2467 11:45:14.257340 [0] MAX Duty = 5031%(X100), DQS PI = 24
2468 11:45:14.260901 [0] MIN Duty = 4844%(X100), DQS PI = 52
2469 11:45:14.264363 [0] AVG Duty = 4937%(X100)
2470 11:45:14.264447
2471 11:45:14.264511 ==DQM 1 ==
2472 11:45:14.267375 Final DQM duty delay cell = 0
2473 11:45:14.270682 [0] MAX Duty = 5031%(X100), DQS PI = 36
2474 11:45:14.273870 [0] MIN Duty = 4907%(X100), DQS PI = 0
2475 11:45:14.277476 [0] AVG Duty = 4969%(X100)
2476 11:45:14.277560
2477 11:45:14.280382 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2478 11:45:14.280457
2479 11:45:14.284040 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 11:45:14.287570 [DutyScan_Calibration_Flow] ====Done====
2481 11:45:14.287645
2482 11:45:14.290467 [DutyScan_Calibration_Flow] k_type=2
2483 11:45:14.307390
2484 11:45:14.307478 ==DQ 0 ==
2485 11:45:14.310677 Final DQ duty delay cell = 0
2486 11:45:14.314161 [0] MAX Duty = 5093%(X100), DQS PI = 26
2487 11:45:14.317054 [0] MIN Duty = 4907%(X100), DQS PI = 56
2488 11:45:14.317169 [0] AVG Duty = 5000%(X100)
2489 11:45:14.320826
2490 11:45:14.320906 ==DQ 1 ==
2491 11:45:14.323626 Final DQ duty delay cell = 0
2492 11:45:14.327034 [0] MAX Duty = 5125%(X100), DQS PI = 46
2493 11:45:14.330273 [0] MIN Duty = 4969%(X100), DQS PI = 26
2494 11:45:14.330375 [0] AVG Duty = 5047%(X100)
2495 11:45:14.330441
2496 11:45:14.333712 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2497 11:45:14.333788
2498 11:45:14.340833 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 11:45:14.343816 [DutyScan_Calibration_Flow] ====Done====
2500 11:45:14.347280 nWR fixed to 30
2501 11:45:14.347356 [ModeRegInit_LP4] CH0 RK0
2502 11:45:14.350347 [ModeRegInit_LP4] CH0 RK1
2503 11:45:14.353718 [ModeRegInit_LP4] CH1 RK0
2504 11:45:14.353805 [ModeRegInit_LP4] CH1 RK1
2505 11:45:14.357048 match AC timing 7
2506 11:45:14.360720 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 11:45:14.364027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 11:45:14.370544 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 11:45:14.374148 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 11:45:14.380645 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 11:45:14.380733 ==
2512 11:45:14.384045 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:45:14.387145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:45:14.387221 ==
2515 11:45:14.394066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 11:45:14.397104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2517 11:45:14.407114 [CA 0] Center 40 (10~71) winsize 62
2518 11:45:14.410674 [CA 1] Center 39 (9~70) winsize 62
2519 11:45:14.414110 [CA 2] Center 36 (6~66) winsize 61
2520 11:45:14.417114 [CA 3] Center 35 (5~66) winsize 62
2521 11:45:14.420462 [CA 4] Center 34 (4~65) winsize 62
2522 11:45:14.423913 [CA 5] Center 33 (3~64) winsize 62
2523 11:45:14.423993
2524 11:45:14.427222 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 11:45:14.427300
2526 11:45:14.430728 [CATrainingPosCal] consider 1 rank data
2527 11:45:14.433725 u2DelayCellTimex100 = 270/100 ps
2528 11:45:14.437581 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2529 11:45:14.443769 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 11:45:14.447312 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2531 11:45:14.450353 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 11:45:14.453954 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 11:45:14.456937 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2534 11:45:14.457020
2535 11:45:14.460388 CA PerBit enable=1, Macro0, CA PI delay=33
2536 11:45:14.460468
2537 11:45:14.463804 [CBTSetCACLKResult] CA Dly = 33
2538 11:45:14.463881 CS Dly: 7 (0~38)
2539 11:45:14.467049 ==
2540 11:45:14.470373 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 11:45:14.473626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 11:45:14.473705 ==
2543 11:45:14.477206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 11:45:14.483756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 11:45:14.493238 [CA 0] Center 40 (10~70) winsize 61
2546 11:45:14.496475 [CA 1] Center 39 (9~70) winsize 62
2547 11:45:14.499787 [CA 2] Center 35 (5~66) winsize 62
2548 11:45:14.503318 [CA 3] Center 35 (5~66) winsize 62
2549 11:45:14.506365 [CA 4] Center 34 (3~65) winsize 63
2550 11:45:14.509986 [CA 5] Center 33 (3~64) winsize 62
2551 11:45:14.510071
2552 11:45:14.512911 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 11:45:14.512994
2554 11:45:14.516608 [CATrainingPosCal] consider 2 rank data
2555 11:45:14.520061 u2DelayCellTimex100 = 270/100 ps
2556 11:45:14.522981 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2557 11:45:14.529996 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 11:45:14.533006 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2559 11:45:14.536579 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 11:45:14.539826 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2561 11:45:14.543257 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2562 11:45:14.543342
2563 11:45:14.546592 CA PerBit enable=1, Macro0, CA PI delay=33
2564 11:45:14.546675
2565 11:45:14.549649 [CBTSetCACLKResult] CA Dly = 33
2566 11:45:14.549731 CS Dly: 8 (0~40)
2567 11:45:14.553178
2568 11:45:14.556635 ----->DramcWriteLeveling(PI) begin...
2569 11:45:14.556718 ==
2570 11:45:14.559583 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 11:45:14.563092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 11:45:14.563172 ==
2573 11:45:14.566677 Write leveling (Byte 0): 32 => 32
2574 11:45:14.570139 Write leveling (Byte 1): 30 => 30
2575 11:45:14.572915 DramcWriteLeveling(PI) end<-----
2576 11:45:14.572992
2577 11:45:14.573055 ==
2578 11:45:14.576446 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:45:14.579791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:45:14.579875 ==
2581 11:45:14.583053 [Gating] SW mode calibration
2582 11:45:14.589828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 11:45:14.596165 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 11:45:14.599434 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2585 11:45:14.602801 0 15 4 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
2586 11:45:14.609497 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:45:14.613009 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:45:14.616490 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:45:14.620091 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:45:14.626433 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 11:45:14.629931 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2592 11:45:14.633011 1 0 0 | B1->B0 | 3131 2626 | 0 0 | (1 0) (0 0)
2593 11:45:14.640051 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 11:45:14.643469 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:45:14.646346 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:45:14.653333 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:45:14.656333 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:45:14.659964 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 11:45:14.666402 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2600 11:45:14.670114 1 1 0 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
2601 11:45:14.672994 1 1 4 | B1->B0 | 3c3c 4545 | 0 0 | (1 1) (0 0)
2602 11:45:14.679877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:45:14.682912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:45:14.686432 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:45:14.693347 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:45:14.696279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:45:14.699755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 11:45:14.703358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 11:45:14.709660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 11:45:14.713047 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:45:14.716435 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:45:14.723029 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:45:14.726508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:45:14.729918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:45:14.736864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:45:14.739766 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:45:14.743266 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:45:14.750138 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:45:14.753158 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:45:14.756701 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:45:14.763041 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:45:14.766531 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:45:14.770041 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 11:45:14.776960 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 11:45:14.780003 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 11:45:14.783170 Total UI for P1: 0, mck2ui 16
2627 11:45:14.786691 best dqsien dly found for B0: ( 1, 3, 30)
2628 11:45:14.790136 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 11:45:14.793489 Total UI for P1: 0, mck2ui 16
2630 11:45:14.796819 best dqsien dly found for B1: ( 1, 4, 2)
2631 11:45:14.799708 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2632 11:45:14.803182 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2633 11:45:14.803260
2634 11:45:14.806576 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2635 11:45:14.810106 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2636 11:45:14.813333 [Gating] SW calibration Done
2637 11:45:14.813416 ==
2638 11:45:14.816798 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 11:45:14.823069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 11:45:14.823146 ==
2641 11:45:14.823209 RX Vref Scan: 0
2642 11:45:14.823268
2643 11:45:14.826588 RX Vref 0 -> 0, step: 1
2644 11:45:14.826660
2645 11:45:14.830104 RX Delay -40 -> 252, step: 8
2646 11:45:14.833106 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2647 11:45:14.836470 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2648 11:45:14.840006 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2649 11:45:14.842973 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2650 11:45:14.849974 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2651 11:45:14.853365 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2652 11:45:14.856774 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2653 11:45:14.859730 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2654 11:45:14.863141 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2655 11:45:14.866642 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2656 11:45:14.873488 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2657 11:45:14.876383 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2658 11:45:14.879774 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2659 11:45:14.883119 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2660 11:45:14.886679 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2661 11:45:14.893488 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2662 11:45:14.893572 ==
2663 11:45:14.896667 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 11:45:14.900101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 11:45:14.900223 ==
2666 11:45:14.900293 DQS Delay:
2667 11:45:14.903041 DQS0 = 0, DQS1 = 0
2668 11:45:14.903123 DQM Delay:
2669 11:45:14.906526 DQM0 = 112, DQM1 = 102
2670 11:45:14.906637 DQ Delay:
2671 11:45:14.909803 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2672 11:45:14.913170 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2673 11:45:14.916353 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2674 11:45:14.919795 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2675 11:45:14.919883
2676 11:45:14.919949
2677 11:45:14.923285 ==
2678 11:45:14.923371 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 11:45:14.929834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 11:45:14.929918 ==
2681 11:45:14.929984
2682 11:45:14.930045
2683 11:45:14.933382 TX Vref Scan disable
2684 11:45:14.933462 == TX Byte 0 ==
2685 11:45:14.936931 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2686 11:45:14.943253 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2687 11:45:14.943356 == TX Byte 1 ==
2688 11:45:14.946800 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2689 11:45:14.953344 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2690 11:45:14.953430 ==
2691 11:45:14.956789 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 11:45:14.960275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 11:45:14.960354 ==
2694 11:45:14.971906 TX Vref=22, minBit 11, minWin=25, winSum=417
2695 11:45:14.975167 TX Vref=24, minBit 14, minWin=25, winSum=420
2696 11:45:14.978752 TX Vref=26, minBit 10, minWin=26, winSum=433
2697 11:45:14.982264 TX Vref=28, minBit 10, minWin=26, winSum=433
2698 11:45:14.985236 TX Vref=30, minBit 10, minWin=26, winSum=438
2699 11:45:14.992003 TX Vref=32, minBit 10, minWin=26, winSum=434
2700 11:45:14.995443 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
2701 11:45:14.995526
2702 11:45:14.998920 Final TX Range 1 Vref 30
2703 11:45:14.999003
2704 11:45:14.999068 ==
2705 11:45:15.001787 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 11:45:15.005568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 11:45:15.008611 ==
2708 11:45:15.008693
2709 11:45:15.008758
2710 11:45:15.008835 TX Vref Scan disable
2711 11:45:15.012325 == TX Byte 0 ==
2712 11:45:15.015211 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2713 11:45:15.022402 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2714 11:45:15.022513 == TX Byte 1 ==
2715 11:45:15.025635 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2716 11:45:15.028728 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2717 11:45:15.032138
2718 11:45:15.032246 [DATLAT]
2719 11:45:15.032345 Freq=1200, CH0 RK0
2720 11:45:15.032433
2721 11:45:15.035427 DATLAT Default: 0xd
2722 11:45:15.035509 0, 0xFFFF, sum = 0
2723 11:45:15.038657 1, 0xFFFF, sum = 0
2724 11:45:15.038803 2, 0xFFFF, sum = 0
2725 11:45:15.042407 3, 0xFFFF, sum = 0
2726 11:45:15.045311 4, 0xFFFF, sum = 0
2727 11:45:15.045417 5, 0xFFFF, sum = 0
2728 11:45:15.048812 6, 0xFFFF, sum = 0
2729 11:45:15.048910 7, 0xFFFF, sum = 0
2730 11:45:15.052389 8, 0xFFFF, sum = 0
2731 11:45:15.052475 9, 0xFFFF, sum = 0
2732 11:45:15.055256 10, 0xFFFF, sum = 0
2733 11:45:15.055368 11, 0xFFFF, sum = 0
2734 11:45:15.058818 12, 0x0, sum = 1
2735 11:45:15.058903 13, 0x0, sum = 2
2736 11:45:15.062238 14, 0x0, sum = 3
2737 11:45:15.062329 15, 0x0, sum = 4
2738 11:45:15.062397 best_step = 13
2739 11:45:15.065217
2740 11:45:15.065294 ==
2741 11:45:15.068723 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 11:45:15.072305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 11:45:15.072390 ==
2744 11:45:15.072456 RX Vref Scan: 1
2745 11:45:15.072517
2746 11:45:15.075235 Set Vref Range= 32 -> 127
2747 11:45:15.075306
2748 11:45:15.078562 RX Vref 32 -> 127, step: 1
2749 11:45:15.078648
2750 11:45:15.081917 RX Delay -37 -> 252, step: 4
2751 11:45:15.081994
2752 11:45:15.085477 Set Vref, RX VrefLevel [Byte0]: 32
2753 11:45:15.088415 [Byte1]: 32
2754 11:45:15.088491
2755 11:45:15.091908 Set Vref, RX VrefLevel [Byte0]: 33
2756 11:45:15.095359 [Byte1]: 33
2757 11:45:15.098902
2758 11:45:15.098987 Set Vref, RX VrefLevel [Byte0]: 34
2759 11:45:15.102494 [Byte1]: 34
2760 11:45:15.106547
2761 11:45:15.106631 Set Vref, RX VrefLevel [Byte0]: 35
2762 11:45:15.110098 [Byte1]: 35
2763 11:45:15.114969
2764 11:45:15.115047 Set Vref, RX VrefLevel [Byte0]: 36
2765 11:45:15.118132 [Byte1]: 36
2766 11:45:15.123096
2767 11:45:15.123173 Set Vref, RX VrefLevel [Byte0]: 37
2768 11:45:15.125938 [Byte1]: 37
2769 11:45:15.130882
2770 11:45:15.130959 Set Vref, RX VrefLevel [Byte0]: 38
2771 11:45:15.133957 [Byte1]: 38
2772 11:45:15.138628
2773 11:45:15.138711 Set Vref, RX VrefLevel [Byte0]: 39
2774 11:45:15.141939 [Byte1]: 39
2775 11:45:15.146827
2776 11:45:15.146906 Set Vref, RX VrefLevel [Byte0]: 40
2777 11:45:15.150087 [Byte1]: 40
2778 11:45:15.154755
2779 11:45:15.154826 Set Vref, RX VrefLevel [Byte0]: 41
2780 11:45:15.158316 [Byte1]: 41
2781 11:45:15.163092
2782 11:45:15.163165 Set Vref, RX VrefLevel [Byte0]: 42
2783 11:45:15.165832 [Byte1]: 42
2784 11:45:15.171002
2785 11:45:15.171077 Set Vref, RX VrefLevel [Byte0]: 43
2786 11:45:15.173926 [Byte1]: 43
2787 11:45:15.178489
2788 11:45:15.178564 Set Vref, RX VrefLevel [Byte0]: 44
2789 11:45:15.182107 [Byte1]: 44
2790 11:45:15.186692
2791 11:45:15.186768 Set Vref, RX VrefLevel [Byte0]: 45
2792 11:45:15.190133 [Byte1]: 45
2793 11:45:15.194865
2794 11:45:15.198176 Set Vref, RX VrefLevel [Byte0]: 46
2795 11:45:15.201109 [Byte1]: 46
2796 11:45:15.201181
2797 11:45:15.204558 Set Vref, RX VrefLevel [Byte0]: 47
2798 11:45:15.208092 [Byte1]: 47
2799 11:45:15.208177
2800 11:45:15.211072 Set Vref, RX VrefLevel [Byte0]: 48
2801 11:45:15.214678 [Byte1]: 48
2802 11:45:15.218653
2803 11:45:15.218726 Set Vref, RX VrefLevel [Byte0]: 49
2804 11:45:15.222222 [Byte1]: 49
2805 11:45:15.226925
2806 11:45:15.226997 Set Vref, RX VrefLevel [Byte0]: 50
2807 11:45:15.230203 [Byte1]: 50
2808 11:45:15.234992
2809 11:45:15.235073 Set Vref, RX VrefLevel [Byte0]: 51
2810 11:45:15.238325 [Byte1]: 51
2811 11:45:15.242697
2812 11:45:15.242767 Set Vref, RX VrefLevel [Byte0]: 52
2813 11:45:15.245839 [Byte1]: 52
2814 11:45:15.251060
2815 11:45:15.251131 Set Vref, RX VrefLevel [Byte0]: 53
2816 11:45:15.254366 [Byte1]: 53
2817 11:45:15.258694
2818 11:45:15.258769 Set Vref, RX VrefLevel [Byte0]: 54
2819 11:45:15.262105 [Byte1]: 54
2820 11:45:15.266789
2821 11:45:15.266861 Set Vref, RX VrefLevel [Byte0]: 55
2822 11:45:15.270290 [Byte1]: 55
2823 11:45:15.274759
2824 11:45:15.274834 Set Vref, RX VrefLevel [Byte0]: 56
2825 11:45:15.278195 [Byte1]: 56
2826 11:45:15.282773
2827 11:45:15.282846 Set Vref, RX VrefLevel [Byte0]: 57
2828 11:45:15.286407 [Byte1]: 57
2829 11:45:15.290946
2830 11:45:15.291033 Set Vref, RX VrefLevel [Byte0]: 58
2831 11:45:15.294031 [Byte1]: 58
2832 11:45:15.298658
2833 11:45:15.298740 Set Vref, RX VrefLevel [Byte0]: 59
2834 11:45:15.302014 [Byte1]: 59
2835 11:45:15.306598
2836 11:45:15.306672 Set Vref, RX VrefLevel [Byte0]: 60
2837 11:45:15.310208 [Byte1]: 60
2838 11:45:15.314834
2839 11:45:15.314904 Set Vref, RX VrefLevel [Byte0]: 61
2840 11:45:15.318316 [Byte1]: 61
2841 11:45:15.322926
2842 11:45:15.322999 Set Vref, RX VrefLevel [Byte0]: 62
2843 11:45:15.325847 [Byte1]: 62
2844 11:45:15.331022
2845 11:45:15.331095 Set Vref, RX VrefLevel [Byte0]: 63
2846 11:45:15.334266 [Byte1]: 63
2847 11:45:15.339054
2848 11:45:15.339130 Set Vref, RX VrefLevel [Byte0]: 64
2849 11:45:15.341930 [Byte1]: 64
2850 11:45:15.347081
2851 11:45:15.347154 Set Vref, RX VrefLevel [Byte0]: 65
2852 11:45:15.350478 [Byte1]: 65
2853 11:45:15.354695
2854 11:45:15.354767 Set Vref, RX VrefLevel [Byte0]: 66
2855 11:45:15.358096 [Byte1]: 66
2856 11:45:15.362729
2857 11:45:15.362807 Set Vref, RX VrefLevel [Byte0]: 67
2858 11:45:15.366041 [Byte1]: 67
2859 11:45:15.370990
2860 11:45:15.371066 Set Vref, RX VrefLevel [Byte0]: 68
2861 11:45:15.373946 [Byte1]: 68
2862 11:45:15.379133
2863 11:45:15.379223 Set Vref, RX VrefLevel [Byte0]: 69
2864 11:45:15.381946 [Byte1]: 69
2865 11:45:15.386764
2866 11:45:15.386867 Set Vref, RX VrefLevel [Byte0]: 70
2867 11:45:15.390275 [Byte1]: 70
2868 11:45:15.394966
2869 11:45:15.395118 Set Vref, RX VrefLevel [Byte0]: 71
2870 11:45:15.397982 [Byte1]: 71
2871 11:45:15.402691
2872 11:45:15.402770 Set Vref, RX VrefLevel [Byte0]: 72
2873 11:45:15.405984 [Byte1]: 72
2874 11:45:15.410557
2875 11:45:15.410628 Set Vref, RX VrefLevel [Byte0]: 73
2876 11:45:15.414068 [Byte1]: 73
2877 11:45:15.418784
2878 11:45:15.418867 Set Vref, RX VrefLevel [Byte0]: 74
2879 11:45:15.422303 [Byte1]: 74
2880 11:45:15.426755
2881 11:45:15.426895 Final RX Vref Byte 0 = 61 to rank0
2882 11:45:15.430260 Final RX Vref Byte 1 = 53 to rank0
2883 11:45:15.433757 Final RX Vref Byte 0 = 61 to rank1
2884 11:45:15.436673 Final RX Vref Byte 1 = 53 to rank1==
2885 11:45:15.440058 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 11:45:15.447011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 11:45:15.447135 ==
2888 11:45:15.447200 DQS Delay:
2889 11:45:15.447259 DQS0 = 0, DQS1 = 0
2890 11:45:15.450002 DQM Delay:
2891 11:45:15.450074 DQM0 = 112, DQM1 = 101
2892 11:45:15.453476 DQ Delay:
2893 11:45:15.456989 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2894 11:45:15.460190 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2895 11:45:15.463739 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2896 11:45:15.466745 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2897 11:45:15.466819
2898 11:45:15.466889
2899 11:45:15.473707 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2900 11:45:15.476882 CH0 RK0: MR19=303, MR18=FCFC
2901 11:45:15.483493 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2902 11:45:15.483572
2903 11:45:15.486771 ----->DramcWriteLeveling(PI) begin...
2904 11:45:15.486845 ==
2905 11:45:15.490351 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 11:45:15.493790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 11:45:15.493866 ==
2908 11:45:15.496712 Write leveling (Byte 0): 32 => 32
2909 11:45:15.500111 Write leveling (Byte 1): 31 => 31
2910 11:45:15.503558 DramcWriteLeveling(PI) end<-----
2911 11:45:15.503631
2912 11:45:15.503692 ==
2913 11:45:15.507123 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 11:45:15.510382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 11:45:15.513336 ==
2916 11:45:15.513408 [Gating] SW mode calibration
2917 11:45:15.523823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 11:45:15.526830 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 11:45:15.530389 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2920 11:45:15.536849 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 11:45:15.540423 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 11:45:15.543885 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 11:45:15.550112 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 11:45:15.553829 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 11:45:15.556936 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2926 11:45:15.563960 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
2927 11:45:15.567329 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 11:45:15.570317 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 11:45:15.576862 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 11:45:15.580226 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 11:45:15.583687 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 11:45:15.590296 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 11:45:15.594106 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2934 11:45:15.596987 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
2935 11:45:15.600813 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2936 11:45:15.607280 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 11:45:15.610286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 11:45:15.613732 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 11:45:15.620842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 11:45:15.623645 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:45:15.627240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:45:15.634066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 11:45:15.637422 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2944 11:45:15.640365 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 11:45:15.647493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 11:45:15.650428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 11:45:15.654048 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 11:45:15.660776 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 11:45:15.663925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:45:15.667031 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:45:15.670649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:45:15.677207 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:45:15.680763 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:45:15.683685 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:45:15.690675 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:45:15.694061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:45:15.697370 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:45:15.704103 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 11:45:15.707212 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 11:45:15.710386 Total UI for P1: 0, mck2ui 16
2961 11:45:15.714107 best dqsien dly found for B0: ( 1, 3, 28)
2962 11:45:15.717505 Total UI for P1: 0, mck2ui 16
2963 11:45:15.720390 best dqsien dly found for B1: ( 1, 3, 30)
2964 11:45:15.723977 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2965 11:45:15.727393 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2966 11:45:15.727473
2967 11:45:15.730380 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2968 11:45:15.734116 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2969 11:45:15.737247 [Gating] SW calibration Done
2970 11:45:15.737328 ==
2971 11:45:15.740750 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:45:15.744250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:45:15.747138 ==
2974 11:45:15.747240 RX Vref Scan: 0
2975 11:45:15.747313
2976 11:45:15.750685 RX Vref 0 -> 0, step: 1
2977 11:45:15.750761
2978 11:45:15.750824 RX Delay -40 -> 252, step: 8
2979 11:45:15.757605 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2980 11:45:15.760600 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2981 11:45:15.764197 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2982 11:45:15.767601 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2983 11:45:15.770466 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2984 11:45:15.777271 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2985 11:45:15.780855 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2986 11:45:15.783751 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2987 11:45:15.787258 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2988 11:45:15.790786 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2989 11:45:15.797357 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2990 11:45:15.800848 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2991 11:45:15.804261 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2992 11:45:15.807522 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2993 11:45:15.810922 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2994 11:45:15.817234 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2995 11:45:15.817309 ==
2996 11:45:15.820672 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:45:15.823855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:45:15.823951 ==
2999 11:45:15.824041 DQS Delay:
3000 11:45:15.827375 DQS0 = 0, DQS1 = 0
3001 11:45:15.827474 DQM Delay:
3002 11:45:15.830829 DQM0 = 112, DQM1 = 101
3003 11:45:15.830941 DQ Delay:
3004 11:45:15.833699 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3005 11:45:15.837278 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3006 11:45:15.840717 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3007 11:45:15.844127 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3008 11:45:15.844264
3009 11:45:15.844329
3010 11:45:15.844390 ==
3011 11:45:15.847102 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 11:45:15.854211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 11:45:15.854309 ==
3014 11:45:15.854399
3015 11:45:15.854484
3016 11:45:15.854568 TX Vref Scan disable
3017 11:45:15.857716 == TX Byte 0 ==
3018 11:45:15.861158 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3019 11:45:15.864107 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3020 11:45:15.867635 == TX Byte 1 ==
3021 11:45:15.871238 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3022 11:45:15.874667 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3023 11:45:15.877651 ==
3024 11:45:15.881041 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 11:45:15.884129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 11:45:15.884238 ==
3027 11:45:15.895633 TX Vref=22, minBit 0, minWin=26, winSum=424
3028 11:45:15.899113 TX Vref=24, minBit 1, minWin=26, winSum=425
3029 11:45:15.902029 TX Vref=26, minBit 1, minWin=26, winSum=433
3030 11:45:15.905500 TX Vref=28, minBit 1, minWin=27, winSum=444
3031 11:45:15.908799 TX Vref=30, minBit 1, minWin=26, winSum=440
3032 11:45:15.912183 TX Vref=32, minBit 14, minWin=26, winSum=440
3033 11:45:15.918676 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
3034 11:45:15.918782
3035 11:45:15.922520 Final TX Range 1 Vref 28
3036 11:45:15.922625
3037 11:45:15.922723 ==
3038 11:45:15.925398 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 11:45:15.928934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 11:45:15.929012 ==
3041 11:45:15.929074
3042 11:45:15.932178
3043 11:45:15.932312 TX Vref Scan disable
3044 11:45:15.935765 == TX Byte 0 ==
3045 11:45:15.938917 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3046 11:45:15.942323 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3047 11:45:15.945737 == TX Byte 1 ==
3048 11:45:15.948698 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3049 11:45:15.952627 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3050 11:45:15.952730
3051 11:45:15.955632 [DATLAT]
3052 11:45:15.955709 Freq=1200, CH0 RK1
3053 11:45:15.955772
3054 11:45:15.959045 DATLAT Default: 0xd
3055 11:45:15.959150 0, 0xFFFF, sum = 0
3056 11:45:15.961996 1, 0xFFFF, sum = 0
3057 11:45:15.962073 2, 0xFFFF, sum = 0
3058 11:45:15.965479 3, 0xFFFF, sum = 0
3059 11:45:15.965584 4, 0xFFFF, sum = 0
3060 11:45:15.968965 5, 0xFFFF, sum = 0
3061 11:45:15.969067 6, 0xFFFF, sum = 0
3062 11:45:15.972449 7, 0xFFFF, sum = 0
3063 11:45:15.972526 8, 0xFFFF, sum = 0
3064 11:45:15.975420 9, 0xFFFF, sum = 0
3065 11:45:15.978904 10, 0xFFFF, sum = 0
3066 11:45:15.978973 11, 0xFFFF, sum = 0
3067 11:45:15.982476 12, 0x0, sum = 1
3068 11:45:15.982582 13, 0x0, sum = 2
3069 11:45:15.982675 14, 0x0, sum = 3
3070 11:45:15.985357 15, 0x0, sum = 4
3071 11:45:15.985462 best_step = 13
3072 11:45:15.985552
3073 11:45:15.985639 ==
3074 11:45:15.988783 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 11:45:15.995737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 11:45:15.995853 ==
3077 11:45:15.995949 RX Vref Scan: 0
3078 11:45:15.996025
3079 11:45:15.998751 RX Vref 0 -> 0, step: 1
3080 11:45:15.998857
3081 11:45:16.002184 RX Delay -37 -> 252, step: 4
3082 11:45:16.005591 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3083 11:45:16.008856 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3084 11:45:16.015884 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3085 11:45:16.018691 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3086 11:45:16.022131 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3087 11:45:16.025555 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3088 11:45:16.028724 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3089 11:45:16.035712 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3090 11:45:16.038706 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3091 11:45:16.042433 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3092 11:45:16.045806 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3093 11:45:16.048873 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3094 11:45:16.055723 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3095 11:45:16.058767 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3096 11:45:16.062036 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3097 11:45:16.065592 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3098 11:45:16.065669 ==
3099 11:45:16.069047 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 11:45:16.075495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 11:45:16.075571 ==
3102 11:45:16.075637 DQS Delay:
3103 11:45:16.075696 DQS0 = 0, DQS1 = 0
3104 11:45:16.079057 DQM Delay:
3105 11:45:16.079133 DQM0 = 111, DQM1 = 101
3106 11:45:16.082535 DQ Delay:
3107 11:45:16.085517 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3108 11:45:16.089068 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3109 11:45:16.092610 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3110 11:45:16.096031 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3111 11:45:16.096114
3112 11:45:16.096178
3113 11:45:16.102266 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3114 11:45:16.105457 CH0 RK1: MR19=403, MR18=11F9
3115 11:45:16.112032 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3116 11:45:16.115656 [RxdqsGatingPostProcess] freq 1200
3117 11:45:16.122501 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3118 11:45:16.125874 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 11:45:16.125949 best DQS1 dly(2T, 0.5T) = (0, 12)
3120 11:45:16.128887 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 11:45:16.132220 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3122 11:45:16.135635 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 11:45:16.139152 best DQS1 dly(2T, 0.5T) = (0, 11)
3124 11:45:16.142107 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 11:45:16.145521 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3126 11:45:16.148979 Pre-setting of DQS Precalculation
3127 11:45:16.155841 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3128 11:45:16.155924 ==
3129 11:45:16.158716 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:45:16.162112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:45:16.162195 ==
3132 11:45:16.169125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 11:45:16.172193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3134 11:45:16.181442 [CA 0] Center 37 (7~67) winsize 61
3135 11:45:16.185003 [CA 1] Center 37 (7~68) winsize 62
3136 11:45:16.188067 [CA 2] Center 34 (5~64) winsize 60
3137 11:45:16.191484 [CA 3] Center 33 (3~64) winsize 62
3138 11:45:16.195025 [CA 4] Center 34 (4~64) winsize 61
3139 11:45:16.198519 [CA 5] Center 33 (3~63) winsize 61
3140 11:45:16.198601
3141 11:45:16.201381 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3142 11:45:16.201486
3143 11:45:16.204713 [CATrainingPosCal] consider 1 rank data
3144 11:45:16.208315 u2DelayCellTimex100 = 270/100 ps
3145 11:45:16.211504 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3146 11:45:16.214592 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 11:45:16.221737 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3148 11:45:16.224689 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 11:45:16.228213 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 11:45:16.231642 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3151 11:45:16.231741
3152 11:45:16.234662 CA PerBit enable=1, Macro0, CA PI delay=33
3153 11:45:16.234745
3154 11:45:16.237936 [CBTSetCACLKResult] CA Dly = 33
3155 11:45:16.238019 CS Dly: 6 (0~37)
3156 11:45:16.238086 ==
3157 11:45:16.241734 Dram Type= 6, Freq= 0, CH_1, rank 1
3158 11:45:16.248173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 11:45:16.248295 ==
3160 11:45:16.251652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3161 11:45:16.257930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3162 11:45:16.267148 [CA 0] Center 37 (8~67) winsize 60
3163 11:45:16.270495 [CA 1] Center 37 (7~68) winsize 62
3164 11:45:16.273946 [CA 2] Center 34 (4~65) winsize 62
3165 11:45:16.277456 [CA 3] Center 33 (3~64) winsize 62
3166 11:45:16.280859 [CA 4] Center 34 (4~65) winsize 62
3167 11:45:16.283841 [CA 5] Center 33 (3~64) winsize 62
3168 11:45:16.283923
3169 11:45:16.287464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3170 11:45:16.287569
3171 11:45:16.290741 [CATrainingPosCal] consider 2 rank data
3172 11:45:16.293675 u2DelayCellTimex100 = 270/100 ps
3173 11:45:16.297158 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3174 11:45:16.300768 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3175 11:45:16.307517 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3176 11:45:16.310386 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3177 11:45:16.313912 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 11:45:16.317436 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3179 11:45:16.317511
3180 11:45:16.320689 CA PerBit enable=1, Macro0, CA PI delay=33
3181 11:45:16.320772
3182 11:45:16.323974 [CBTSetCACLKResult] CA Dly = 33
3183 11:45:16.324055 CS Dly: 7 (0~40)
3184 11:45:16.324145
3185 11:45:16.327194 ----->DramcWriteLeveling(PI) begin...
3186 11:45:16.330808 ==
3187 11:45:16.330916 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 11:45:16.337069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 11:45:16.337153 ==
3190 11:45:16.340506 Write leveling (Byte 0): 25 => 25
3191 11:45:16.343899 Write leveling (Byte 1): 29 => 29
3192 11:45:16.347041 DramcWriteLeveling(PI) end<-----
3193 11:45:16.347124
3194 11:45:16.347189 ==
3195 11:45:16.350837 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 11:45:16.353775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 11:45:16.353858 ==
3198 11:45:16.357263 [Gating] SW mode calibration
3199 11:45:16.363968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3200 11:45:16.367504 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3201 11:45:16.373878 0 15 0 | B1->B0 | 3030 2e2e | 1 0 | (1 1) (0 0)
3202 11:45:16.377435 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 11:45:16.380397 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 11:45:16.387509 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 11:45:16.390404 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 11:45:16.393894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 11:45:16.400643 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 11:45:16.404153 0 15 28 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
3209 11:45:16.407062 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 11:45:16.413910 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 11:45:16.417426 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 11:45:16.420408 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 11:45:16.427257 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 11:45:16.430668 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 11:45:16.433715 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 11:45:16.440522 1 0 28 | B1->B0 | 3c3c 3737 | 0 1 | (0 0) (0 0)
3217 11:45:16.443901 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3218 11:45:16.447339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 11:45:16.450259 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 11:45:16.457128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 11:45:16.460395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:45:16.463751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 11:45:16.470645 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:45:16.474059 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 11:45:16.476897 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:45:16.483889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:45:16.487376 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 11:45:16.490321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:45:16.496968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 11:45:16.500538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:45:16.504011 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:45:16.510262 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:45:16.513602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:45:16.517183 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:45:16.523645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:45:16.527151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:45:16.530706 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:45:16.536927 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:45:16.540280 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:45:16.543868 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3241 11:45:16.547400 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 11:45:16.550198 Total UI for P1: 0, mck2ui 16
3243 11:45:16.553675 best dqsien dly found for B0: ( 1, 3, 30)
3244 11:45:16.556901 Total UI for P1: 0, mck2ui 16
3245 11:45:16.560331 best dqsien dly found for B1: ( 1, 3, 28)
3246 11:45:16.563837 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3247 11:45:16.567152 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3248 11:45:16.570391
3249 11:45:16.573964 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3250 11:45:16.577489 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3251 11:45:16.581078 [Gating] SW calibration Done
3252 11:45:16.581160 ==
3253 11:45:16.583992 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 11:45:16.587506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 11:45:16.587590 ==
3256 11:45:16.587655 RX Vref Scan: 0
3257 11:45:16.587716
3258 11:45:16.590934 RX Vref 0 -> 0, step: 1
3259 11:45:16.591017
3260 11:45:16.593753 RX Delay -40 -> 252, step: 8
3261 11:45:16.597428 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3262 11:45:16.601021 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3263 11:45:16.604082 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3264 11:45:16.610584 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3265 11:45:16.614212 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3266 11:45:16.617192 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3267 11:45:16.620741 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3268 11:45:16.624081 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3269 11:45:16.630578 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3270 11:45:16.634084 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3271 11:45:16.637155 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3272 11:45:16.640653 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3273 11:45:16.644116 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3274 11:45:16.651011 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3275 11:45:16.653949 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3276 11:45:16.657237 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3277 11:45:16.657320 ==
3278 11:45:16.660709 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 11:45:16.664089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 11:45:16.664188 ==
3281 11:45:16.667265 DQS Delay:
3282 11:45:16.667347 DQS0 = 0, DQS1 = 0
3283 11:45:16.670700 DQM Delay:
3284 11:45:16.670783 DQM0 = 114, DQM1 = 104
3285 11:45:16.670848 DQ Delay:
3286 11:45:16.677530 DQ0 =123, DQ1 =111, DQ2 =99, DQ3 =115
3287 11:45:16.680409 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3288 11:45:16.683852 DQ8 =91, DQ9 =99, DQ10 =103, DQ11 =99
3289 11:45:16.687308 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3290 11:45:16.687414
3291 11:45:16.687488
3292 11:45:16.687555 ==
3293 11:45:16.690214 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 11:45:16.693708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 11:45:16.693784 ==
3296 11:45:16.693856
3297 11:45:16.693923
3298 11:45:16.697193 TX Vref Scan disable
3299 11:45:16.700187 == TX Byte 0 ==
3300 11:45:16.703668 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3301 11:45:16.707127 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3302 11:45:16.710776 == TX Byte 1 ==
3303 11:45:16.713769 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3304 11:45:16.717273 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3305 11:45:16.717380 ==
3306 11:45:16.720819 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 11:45:16.723670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 11:45:16.723834 ==
3309 11:45:16.736974 TX Vref=22, minBit 8, minWin=24, winSum=411
3310 11:45:16.740392 TX Vref=24, minBit 8, minWin=25, winSum=420
3311 11:45:16.743816 TX Vref=26, minBit 8, minWin=25, winSum=418
3312 11:45:16.746992 TX Vref=28, minBit 9, minWin=25, winSum=424
3313 11:45:16.750153 TX Vref=30, minBit 9, minWin=25, winSum=426
3314 11:45:16.753741 TX Vref=32, minBit 9, minWin=25, winSum=425
3315 11:45:16.760335 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 30
3316 11:45:16.760477
3317 11:45:16.763457 Final TX Range 1 Vref 30
3318 11:45:16.763591
3319 11:45:16.763698 ==
3320 11:45:16.767219 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 11:45:16.770501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 11:45:16.770642 ==
3323 11:45:16.770752
3324 11:45:16.773637
3325 11:45:16.773774 TX Vref Scan disable
3326 11:45:16.776897 == TX Byte 0 ==
3327 11:45:16.780632 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3328 11:45:16.783951 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3329 11:45:16.787427 == TX Byte 1 ==
3330 11:45:16.790327 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3331 11:45:16.793803 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3332 11:45:16.793889
3333 11:45:16.796662 [DATLAT]
3334 11:45:16.796745 Freq=1200, CH1 RK0
3335 11:45:16.796814
3336 11:45:16.800238 DATLAT Default: 0xd
3337 11:45:16.800321 0, 0xFFFF, sum = 0
3338 11:45:16.803700 1, 0xFFFF, sum = 0
3339 11:45:16.803784 2, 0xFFFF, sum = 0
3340 11:45:16.807301 3, 0xFFFF, sum = 0
3341 11:45:16.807385 4, 0xFFFF, sum = 0
3342 11:45:16.810237 5, 0xFFFF, sum = 0
3343 11:45:16.810321 6, 0xFFFF, sum = 0
3344 11:45:16.813803 7, 0xFFFF, sum = 0
3345 11:45:16.813886 8, 0xFFFF, sum = 0
3346 11:45:16.816788 9, 0xFFFF, sum = 0
3347 11:45:16.820361 10, 0xFFFF, sum = 0
3348 11:45:16.820448 11, 0xFFFF, sum = 0
3349 11:45:16.823773 12, 0x0, sum = 1
3350 11:45:16.823856 13, 0x0, sum = 2
3351 11:45:16.823959 14, 0x0, sum = 3
3352 11:45:16.827413 15, 0x0, sum = 4
3353 11:45:16.827492 best_step = 13
3354 11:45:16.827573
3355 11:45:16.830398 ==
3356 11:45:16.830479 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 11:45:16.836728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 11:45:16.836808 ==
3359 11:45:16.836890 RX Vref Scan: 1
3360 11:45:16.836985
3361 11:45:16.840364 Set Vref Range= 32 -> 127
3362 11:45:16.840469
3363 11:45:16.843861 RX Vref 32 -> 127, step: 1
3364 11:45:16.843943
3365 11:45:16.846907 RX Delay -21 -> 252, step: 4
3366 11:45:16.847017
3367 11:45:16.850815 Set Vref, RX VrefLevel [Byte0]: 32
3368 11:45:16.853751 [Byte1]: 32
3369 11:45:16.853859
3370 11:45:16.857123 Set Vref, RX VrefLevel [Byte0]: 33
3371 11:45:16.860434 [Byte1]: 33
3372 11:45:16.860535
3373 11:45:16.863586 Set Vref, RX VrefLevel [Byte0]: 34
3374 11:45:16.867206 [Byte1]: 34
3375 11:45:16.871167
3376 11:45:16.871241 Set Vref, RX VrefLevel [Byte0]: 35
3377 11:45:16.874433 [Byte1]: 35
3378 11:45:16.878821
3379 11:45:16.882489 Set Vref, RX VrefLevel [Byte0]: 36
3380 11:45:16.882599 [Byte1]: 36
3381 11:45:16.886820
3382 11:45:16.886893 Set Vref, RX VrefLevel [Byte0]: 37
3383 11:45:16.890437 [Byte1]: 37
3384 11:45:16.894706
3385 11:45:16.894787 Set Vref, RX VrefLevel [Byte0]: 38
3386 11:45:16.898598 [Byte1]: 38
3387 11:45:16.902733
3388 11:45:16.902814 Set Vref, RX VrefLevel [Byte0]: 39
3389 11:45:16.906338 [Byte1]: 39
3390 11:45:16.910979
3391 11:45:16.911079 Set Vref, RX VrefLevel [Byte0]: 40
3392 11:45:16.913943 [Byte1]: 40
3393 11:45:16.918647
3394 11:45:16.918744 Set Vref, RX VrefLevel [Byte0]: 41
3395 11:45:16.922091 [Byte1]: 41
3396 11:45:16.926745
3397 11:45:16.926825 Set Vref, RX VrefLevel [Byte0]: 42
3398 11:45:16.929668 [Byte1]: 42
3399 11:45:16.934349
3400 11:45:16.934428 Set Vref, RX VrefLevel [Byte0]: 43
3401 11:45:16.937988 [Byte1]: 43
3402 11:45:16.942466
3403 11:45:16.942549 Set Vref, RX VrefLevel [Byte0]: 44
3404 11:45:16.945882 [Byte1]: 44
3405 11:45:16.950644
3406 11:45:16.950724 Set Vref, RX VrefLevel [Byte0]: 45
3407 11:45:16.953408 [Byte1]: 45
3408 11:45:16.958120
3409 11:45:16.958199 Set Vref, RX VrefLevel [Byte0]: 46
3410 11:45:16.961636 [Byte1]: 46
3411 11:45:16.966349
3412 11:45:16.966452 Set Vref, RX VrefLevel [Byte0]: 47
3413 11:45:16.969739 [Byte1]: 47
3414 11:45:16.974136
3415 11:45:16.974216 Set Vref, RX VrefLevel [Byte0]: 48
3416 11:45:16.977407 [Byte1]: 48
3417 11:45:16.982089
3418 11:45:16.982168 Set Vref, RX VrefLevel [Byte0]: 49
3419 11:45:16.985433 [Byte1]: 49
3420 11:45:16.989771
3421 11:45:16.989851 Set Vref, RX VrefLevel [Byte0]: 50
3422 11:45:16.993042 [Byte1]: 50
3423 11:45:16.997931
3424 11:45:16.998040 Set Vref, RX VrefLevel [Byte0]: 51
3425 11:45:17.001117 [Byte1]: 51
3426 11:45:17.006133
3427 11:45:17.006253 Set Vref, RX VrefLevel [Byte0]: 52
3428 11:45:17.009230 [Byte1]: 52
3429 11:45:17.013861
3430 11:45:17.013962 Set Vref, RX VrefLevel [Byte0]: 53
3431 11:45:17.017385 [Byte1]: 53
3432 11:45:17.021401
3433 11:45:17.021482 Set Vref, RX VrefLevel [Byte0]: 54
3434 11:45:17.024972 [Byte1]: 54
3435 11:45:17.029739
3436 11:45:17.029821 Set Vref, RX VrefLevel [Byte0]: 55
3437 11:45:17.032702 [Byte1]: 55
3438 11:45:17.037479
3439 11:45:17.037561 Set Vref, RX VrefLevel [Byte0]: 56
3440 11:45:17.040918 [Byte1]: 56
3441 11:45:17.045186
3442 11:45:17.045286 Set Vref, RX VrefLevel [Byte0]: 57
3443 11:45:17.048747 [Byte1]: 57
3444 11:45:17.053531
3445 11:45:17.053630 Set Vref, RX VrefLevel [Byte0]: 58
3446 11:45:17.056952 [Byte1]: 58
3447 11:45:17.061518
3448 11:45:17.061587 Set Vref, RX VrefLevel [Byte0]: 59
3449 11:45:17.064503 [Byte1]: 59
3450 11:45:17.069139
3451 11:45:17.069220 Set Vref, RX VrefLevel [Byte0]: 60
3452 11:45:17.072696 [Byte1]: 60
3453 11:45:17.077257
3454 11:45:17.077341 Set Vref, RX VrefLevel [Byte0]: 61
3455 11:45:17.080166 [Byte1]: 61
3456 11:45:17.085194
3457 11:45:17.085277 Set Vref, RX VrefLevel [Byte0]: 62
3458 11:45:17.088241 [Byte1]: 62
3459 11:45:17.092726
3460 11:45:17.092798 Set Vref, RX VrefLevel [Byte0]: 63
3461 11:45:17.096320 [Byte1]: 63
3462 11:45:17.100758
3463 11:45:17.100854 Set Vref, RX VrefLevel [Byte0]: 64
3464 11:45:17.104057 [Byte1]: 64
3465 11:45:17.108617
3466 11:45:17.108698 Set Vref, RX VrefLevel [Byte0]: 65
3467 11:45:17.111882 [Byte1]: 65
3468 11:45:17.116585
3469 11:45:17.116665 Final RX Vref Byte 0 = 60 to rank0
3470 11:45:17.119963 Final RX Vref Byte 1 = 56 to rank0
3471 11:45:17.123405 Final RX Vref Byte 0 = 60 to rank1
3472 11:45:17.126933 Final RX Vref Byte 1 = 56 to rank1==
3473 11:45:17.129824 Dram Type= 6, Freq= 0, CH_1, rank 0
3474 11:45:17.136738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 11:45:17.136820 ==
3476 11:45:17.136906 DQS Delay:
3477 11:45:17.136967 DQS0 = 0, DQS1 = 0
3478 11:45:17.140288 DQM Delay:
3479 11:45:17.140385 DQM0 = 115, DQM1 = 106
3480 11:45:17.143748 DQ Delay:
3481 11:45:17.146733 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3482 11:45:17.150253 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3483 11:45:17.153756 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3484 11:45:17.156630 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3485 11:45:17.156711
3486 11:45:17.156778
3487 11:45:17.163459 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3488 11:45:17.166883 CH1 RK0: MR19=303, MR18=F0F7
3489 11:45:17.173321 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3490 11:45:17.173399
3491 11:45:17.176746 ----->DramcWriteLeveling(PI) begin...
3492 11:45:17.176818 ==
3493 11:45:17.180145 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 11:45:17.183605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 11:45:17.186984 ==
3496 11:45:17.187064 Write leveling (Byte 0): 26 => 26
3497 11:45:17.189878 Write leveling (Byte 1): 27 => 27
3498 11:45:17.193222 DramcWriteLeveling(PI) end<-----
3499 11:45:17.193303
3500 11:45:17.193367 ==
3501 11:45:17.196579 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 11:45:17.203271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 11:45:17.203360 ==
3504 11:45:17.203458 [Gating] SW mode calibration
3505 11:45:17.213335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3506 11:45:17.216886 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3507 11:45:17.220395 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 11:45:17.226688 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 11:45:17.230045 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 11:45:17.233658 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 11:45:17.240126 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:45:17.243544 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 11:45:17.247059 0 15 24 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
3514 11:45:17.253601 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3515 11:45:17.256539 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 11:45:17.260155 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 11:45:17.266540 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 11:45:17.270044 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:45:17.273754 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:45:17.279926 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3521 11:45:17.283747 1 0 24 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
3522 11:45:17.286437 1 0 28 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3523 11:45:17.293117 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:45:17.296631 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 11:45:17.300253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 11:45:17.306611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:45:17.310297 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:45:17.313214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 11:45:17.316649 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3530 11:45:17.323519 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3531 11:45:17.326962 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:45:17.330312 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:45:17.336503 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:45:17.340220 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:45:17.343397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:45:17.350346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:45:17.353318 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:45:17.356819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:45:17.363343 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:45:17.366796 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:45:17.369832 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:45:17.376887 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:45:17.379944 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:45:17.383364 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:45:17.389853 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3546 11:45:17.393459 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 11:45:17.396473 Total UI for P1: 0, mck2ui 16
3548 11:45:17.399881 best dqsien dly found for B0: ( 1, 3, 24)
3549 11:45:17.403218 Total UI for P1: 0, mck2ui 16
3550 11:45:17.406205 best dqsien dly found for B1: ( 1, 3, 26)
3551 11:45:17.409677 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3552 11:45:17.412943 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3553 11:45:17.413129
3554 11:45:17.416321 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3555 11:45:17.420118 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3556 11:45:17.422959 [Gating] SW calibration Done
3557 11:45:17.423167 ==
3558 11:45:17.426523 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 11:45:17.429881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 11:45:17.430039 ==
3561 11:45:17.433297 RX Vref Scan: 0
3562 11:45:17.433446
3563 11:45:17.436474 RX Vref 0 -> 0, step: 1
3564 11:45:17.436556
3565 11:45:17.436620 RX Delay -40 -> 252, step: 8
3566 11:45:17.442786 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3567 11:45:17.446175 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3568 11:45:17.449496 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3569 11:45:17.453064 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3570 11:45:17.456586 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3571 11:45:17.463232 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3572 11:45:17.466317 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3573 11:45:17.469362 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3574 11:45:17.472783 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3575 11:45:17.476169 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3576 11:45:17.483222 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3577 11:45:17.486587 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3578 11:45:17.489843 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3579 11:45:17.493159 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3580 11:45:17.495955 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3581 11:45:17.503202 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3582 11:45:17.503313 ==
3583 11:45:17.506191 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 11:45:17.509855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 11:45:17.510057 ==
3586 11:45:17.510164 DQS Delay:
3587 11:45:17.513214 DQS0 = 0, DQS1 = 0
3588 11:45:17.513391 DQM Delay:
3589 11:45:17.516139 DQM0 = 110, DQM1 = 109
3590 11:45:17.516357 DQ Delay:
3591 11:45:17.519671 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3592 11:45:17.522877 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3593 11:45:17.526636 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3594 11:45:17.529561 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3595 11:45:17.530024
3596 11:45:17.532884
3597 11:45:17.533347 ==
3598 11:45:17.536183 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 11:45:17.539806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 11:45:17.540341 ==
3601 11:45:17.540717
3602 11:45:17.541058
3603 11:45:17.543222 TX Vref Scan disable
3604 11:45:17.543685 == TX Byte 0 ==
3605 11:45:17.549814 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 11:45:17.552969 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 11:45:17.553438 == TX Byte 1 ==
3608 11:45:17.559185 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3609 11:45:17.562707 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3610 11:45:17.563199 ==
3611 11:45:17.566192 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:45:17.569684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:45:17.570196 ==
3614 11:45:17.581549 TX Vref=22, minBit 9, minWin=25, winSum=418
3615 11:45:17.585126 TX Vref=24, minBit 9, minWin=25, winSum=422
3616 11:45:17.587969 TX Vref=26, minBit 0, minWin=26, winSum=431
3617 11:45:17.591586 TX Vref=28, minBit 3, minWin=26, winSum=433
3618 11:45:17.595012 TX Vref=30, minBit 1, minWin=26, winSum=428
3619 11:45:17.601410 TX Vref=32, minBit 1, minWin=25, winSum=430
3620 11:45:17.604805 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 28
3621 11:45:17.605265
3622 11:45:17.608180 Final TX Range 1 Vref 28
3623 11:45:17.608801
3624 11:45:17.609168 ==
3625 11:45:17.611854 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 11:45:17.615054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 11:45:17.615617 ==
3628 11:45:17.618643
3629 11:45:17.619203
3630 11:45:17.619565 TX Vref Scan disable
3631 11:45:17.621576 == TX Byte 0 ==
3632 11:45:17.625057 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3633 11:45:17.628630 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3634 11:45:17.631804 == TX Byte 1 ==
3635 11:45:17.634689 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3636 11:45:17.637959 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3637 11:45:17.641686
3638 11:45:17.642238 [DATLAT]
3639 11:45:17.642606 Freq=1200, CH1 RK1
3640 11:45:17.642962
3641 11:45:17.644939 DATLAT Default: 0xd
3642 11:45:17.645395 0, 0xFFFF, sum = 0
3643 11:45:17.647730 1, 0xFFFF, sum = 0
3644 11:45:17.648195 2, 0xFFFF, sum = 0
3645 11:45:17.651196 3, 0xFFFF, sum = 0
3646 11:45:17.654738 4, 0xFFFF, sum = 0
3647 11:45:17.655217 5, 0xFFFF, sum = 0
3648 11:45:17.658170 6, 0xFFFF, sum = 0
3649 11:45:17.658637 7, 0xFFFF, sum = 0
3650 11:45:17.661508 8, 0xFFFF, sum = 0
3651 11:45:17.661975 9, 0xFFFF, sum = 0
3652 11:45:17.664647 10, 0xFFFF, sum = 0
3653 11:45:17.665136 11, 0xFFFF, sum = 0
3654 11:45:17.667576 12, 0x0, sum = 1
3655 11:45:17.668042 13, 0x0, sum = 2
3656 11:45:17.670779 14, 0x0, sum = 3
3657 11:45:17.671243 15, 0x0, sum = 4
3658 11:45:17.675165 best_step = 13
3659 11:45:17.675723
3660 11:45:17.676088 ==
3661 11:45:17.678127 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 11:45:17.681744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 11:45:17.682304 ==
3664 11:45:17.682669 RX Vref Scan: 0
3665 11:45:17.683004
3666 11:45:17.684339 RX Vref 0 -> 0, step: 1
3667 11:45:17.684799
3668 11:45:17.687652 RX Delay -21 -> 252, step: 4
3669 11:45:17.691063 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3670 11:45:17.697775 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3671 11:45:17.701301 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3672 11:45:17.704136 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3673 11:45:17.708032 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3674 11:45:17.711200 iDelay=195, Bit 5, Center 120 (51 ~ 190) 140
3675 11:45:17.717759 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3676 11:45:17.720735 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3677 11:45:17.724074 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3678 11:45:17.727761 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3679 11:45:17.730883 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3680 11:45:17.737755 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3681 11:45:17.740822 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3682 11:45:17.743882 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3683 11:45:17.747626 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3684 11:45:17.754570 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3685 11:45:17.755149 ==
3686 11:45:17.757116 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 11:45:17.760559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 11:45:17.761023 ==
3689 11:45:17.761386 DQS Delay:
3690 11:45:17.763911 DQS0 = 0, DQS1 = 0
3691 11:45:17.764507 DQM Delay:
3692 11:45:17.767436 DQM0 = 111, DQM1 = 110
3693 11:45:17.768056 DQ Delay:
3694 11:45:17.770898 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3695 11:45:17.774064 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3696 11:45:17.777602 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3697 11:45:17.780644 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =116
3698 11:45:17.781358
3699 11:45:17.781789
3700 11:45:17.790256 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3701 11:45:17.793699 CH1 RK1: MR19=304, MR18=F808
3702 11:45:17.800573 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3703 11:45:17.801137 [RxdqsGatingPostProcess] freq 1200
3704 11:45:17.806796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 11:45:17.810090 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 11:45:17.813611 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 11:45:17.816587 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 11:45:17.820238 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 11:45:17.823224 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 11:45:17.826662 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 11:45:17.829840 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 11:45:17.833639 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 11:45:17.836658 Pre-setting of DQS Precalculation
3714 11:45:17.840494 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 11:45:17.846665 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 11:45:17.856117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 11:45:17.856721
3718 11:45:17.857088
3719 11:45:17.860000 [Calibration Summary] 2400 Mbps
3720 11:45:17.860608 CH 0, Rank 0
3721 11:45:17.863343 SW Impedance : PASS
3722 11:45:17.863800 DUTY Scan : NO K
3723 11:45:17.866238 ZQ Calibration : PASS
3724 11:45:17.866710 Jitter Meter : NO K
3725 11:45:17.869848 CBT Training : PASS
3726 11:45:17.872793 Write leveling : PASS
3727 11:45:17.873249 RX DQS gating : PASS
3728 11:45:17.876383 RX DQ/DQS(RDDQC) : PASS
3729 11:45:17.879756 TX DQ/DQS : PASS
3730 11:45:17.880374 RX DATLAT : PASS
3731 11:45:17.883509 RX DQ/DQS(Engine): PASS
3732 11:45:17.886122 TX OE : NO K
3733 11:45:17.886584 All Pass.
3734 11:45:17.886943
3735 11:45:17.887277 CH 0, Rank 1
3736 11:45:17.890145 SW Impedance : PASS
3737 11:45:17.893307 DUTY Scan : NO K
3738 11:45:17.893858 ZQ Calibration : PASS
3739 11:45:17.896532 Jitter Meter : NO K
3740 11:45:17.899513 CBT Training : PASS
3741 11:45:17.900113 Write leveling : PASS
3742 11:45:17.902533 RX DQS gating : PASS
3743 11:45:17.906191 RX DQ/DQS(RDDQC) : PASS
3744 11:45:17.906648 TX DQ/DQS : PASS
3745 11:45:17.909728 RX DATLAT : PASS
3746 11:45:17.912603 RX DQ/DQS(Engine): PASS
3747 11:45:17.913070 TX OE : NO K
3748 11:45:17.913440 All Pass.
3749 11:45:17.916430
3750 11:45:17.916983 CH 1, Rank 0
3751 11:45:17.920051 SW Impedance : PASS
3752 11:45:17.920674 DUTY Scan : NO K
3753 11:45:17.923025 ZQ Calibration : PASS
3754 11:45:17.923582 Jitter Meter : NO K
3755 11:45:17.926635 CBT Training : PASS
3756 11:45:17.929289 Write leveling : PASS
3757 11:45:17.929746 RX DQS gating : PASS
3758 11:45:17.932937 RX DQ/DQS(RDDQC) : PASS
3759 11:45:17.935761 TX DQ/DQS : PASS
3760 11:45:17.936391 RX DATLAT : PASS
3761 11:45:17.938977 RX DQ/DQS(Engine): PASS
3762 11:45:17.942321 TX OE : NO K
3763 11:45:17.942782 All Pass.
3764 11:45:17.943142
3765 11:45:17.943472 CH 1, Rank 1
3766 11:45:17.946271 SW Impedance : PASS
3767 11:45:17.948927 DUTY Scan : NO K
3768 11:45:17.949389 ZQ Calibration : PASS
3769 11:45:17.952713 Jitter Meter : NO K
3770 11:45:17.955905 CBT Training : PASS
3771 11:45:17.956519 Write leveling : PASS
3772 11:45:17.959107 RX DQS gating : PASS
3773 11:45:17.961920 RX DQ/DQS(RDDQC) : PASS
3774 11:45:17.962379 TX DQ/DQS : PASS
3775 11:45:17.965512 RX DATLAT : PASS
3776 11:45:17.968657 RX DQ/DQS(Engine): PASS
3777 11:45:17.969117 TX OE : NO K
3778 11:45:17.971928 All Pass.
3779 11:45:17.972414
3780 11:45:17.972775 DramC Write-DBI off
3781 11:45:17.975776 PER_BANK_REFRESH: Hybrid Mode
3782 11:45:17.976375 TX_TRACKING: ON
3783 11:45:17.985407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 11:45:17.989125 [FAST_K] Save calibration result to emmc
3785 11:45:17.992118 dramc_set_vcore_voltage set vcore to 650000
3786 11:45:17.995347 Read voltage for 600, 5
3787 11:45:17.995806 Vio18 = 0
3788 11:45:17.999233 Vcore = 650000
3789 11:45:17.999781 Vdram = 0
3790 11:45:18.000148 Vddq = 0
3791 11:45:18.002237 Vmddr = 0
3792 11:45:18.005362 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 11:45:18.011573 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 11:45:18.012115 MEM_TYPE=3, freq_sel=19
3795 11:45:18.014875 sv_algorithm_assistance_LP4_1600
3796 11:45:18.021539 ============ PULL DRAM RESETB DOWN ============
3797 11:45:18.025197 ========== PULL DRAM RESETB DOWN end =========
3798 11:45:18.028571 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 11:45:18.031322 ===================================
3800 11:45:18.034928 LPDDR4 DRAM CONFIGURATION
3801 11:45:18.038567 ===================================
3802 11:45:18.041468 EX_ROW_EN[0] = 0x0
3803 11:45:18.041932 EX_ROW_EN[1] = 0x0
3804 11:45:18.044813 LP4Y_EN = 0x0
3805 11:45:18.045269 WORK_FSP = 0x0
3806 11:45:18.048140 WL = 0x2
3807 11:45:18.048634 RL = 0x2
3808 11:45:18.051511 BL = 0x2
3809 11:45:18.052072 RPST = 0x0
3810 11:45:18.054979 RD_PRE = 0x0
3811 11:45:18.055536 WR_PRE = 0x1
3812 11:45:18.058550 WR_PST = 0x0
3813 11:45:18.059106 DBI_WR = 0x0
3814 11:45:18.061216 DBI_RD = 0x0
3815 11:45:18.061675 OTF = 0x1
3816 11:45:18.064677 ===================================
3817 11:45:18.068085 ===================================
3818 11:45:18.071376 ANA top config
3819 11:45:18.075227 ===================================
3820 11:45:18.078076 DLL_ASYNC_EN = 0
3821 11:45:18.078633 ALL_SLAVE_EN = 1
3822 11:45:18.081045 NEW_RANK_MODE = 1
3823 11:45:18.084969 DLL_IDLE_MODE = 1
3824 11:45:18.088170 LP45_APHY_COMB_EN = 1
3825 11:45:18.088770 TX_ODT_DIS = 1
3826 11:45:18.091425 NEW_8X_MODE = 1
3827 11:45:18.094959 ===================================
3828 11:45:18.097985 ===================================
3829 11:45:18.101177 data_rate = 1200
3830 11:45:18.103960 CKR = 1
3831 11:45:18.107859 DQ_P2S_RATIO = 8
3832 11:45:18.111024 ===================================
3833 11:45:18.114110 CA_P2S_RATIO = 8
3834 11:45:18.114570 DQ_CA_OPEN = 0
3835 11:45:18.117742 DQ_SEMI_OPEN = 0
3836 11:45:18.120952 CA_SEMI_OPEN = 0
3837 11:45:18.124179 CA_FULL_RATE = 0
3838 11:45:18.127825 DQ_CKDIV4_EN = 1
3839 11:45:18.130816 CA_CKDIV4_EN = 1
3840 11:45:18.131275 CA_PREDIV_EN = 0
3841 11:45:18.133925 PH8_DLY = 0
3842 11:45:18.137031 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 11:45:18.140416 DQ_AAMCK_DIV = 4
3844 11:45:18.144268 CA_AAMCK_DIV = 4
3845 11:45:18.147645 CA_ADMCK_DIV = 4
3846 11:45:18.148274 DQ_TRACK_CA_EN = 0
3847 11:45:18.150728 CA_PICK = 600
3848 11:45:18.153817 CA_MCKIO = 600
3849 11:45:18.157553 MCKIO_SEMI = 0
3850 11:45:18.160675 PLL_FREQ = 2288
3851 11:45:18.164170 DQ_UI_PI_RATIO = 32
3852 11:45:18.167376 CA_UI_PI_RATIO = 0
3853 11:45:18.170667 ===================================
3854 11:45:18.173569 ===================================
3855 11:45:18.174033 memory_type:LPDDR4
3856 11:45:18.177208 GP_NUM : 10
3857 11:45:18.180700 SRAM_EN : 1
3858 11:45:18.181263 MD32_EN : 0
3859 11:45:18.184072 ===================================
3860 11:45:18.187260 [ANA_INIT] >>>>>>>>>>>>>>
3861 11:45:18.190561 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 11:45:18.193998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 11:45:18.197504 ===================================
3864 11:45:18.200183 data_rate = 1200,PCW = 0X5800
3865 11:45:18.203725 ===================================
3866 11:45:18.207363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 11:45:18.210426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 11:45:18.217338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 11:45:18.220872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 11:45:18.223901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 11:45:18.227347 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 11:45:18.229871 [ANA_INIT] flow start
3873 11:45:18.233762 [ANA_INIT] PLL >>>>>>>>
3874 11:45:18.234325 [ANA_INIT] PLL <<<<<<<<
3875 11:45:18.237057 [ANA_INIT] MIDPI >>>>>>>>
3876 11:45:18.240128 [ANA_INIT] MIDPI <<<<<<<<
3877 11:45:18.243174 [ANA_INIT] DLL >>>>>>>>
3878 11:45:18.243572 [ANA_INIT] flow end
3879 11:45:18.247125 ============ LP4 DIFF to SE enter ============
3880 11:45:18.253708 ============ LP4 DIFF to SE exit ============
3881 11:45:18.254258 [ANA_INIT] <<<<<<<<<<<<<
3882 11:45:18.256710 [Flow] Enable top DCM control >>>>>
3883 11:45:18.259847 [Flow] Enable top DCM control <<<<<
3884 11:45:18.263418 Enable DLL master slave shuffle
3885 11:45:18.269927 ==============================================================
3886 11:45:18.270493 Gating Mode config
3887 11:45:18.276580 ==============================================================
3888 11:45:18.280133 Config description:
3889 11:45:18.289772 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 11:45:18.296498 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 11:45:18.299454 SELPH_MODE 0: By rank 1: By Phase
3892 11:45:18.305717 ==============================================================
3893 11:45:18.309355 GAT_TRACK_EN = 1
3894 11:45:18.312555 RX_GATING_MODE = 2
3895 11:45:18.316128 RX_GATING_TRACK_MODE = 2
3896 11:45:18.316730 SELPH_MODE = 1
3897 11:45:18.319745 PICG_EARLY_EN = 1
3898 11:45:18.322804 VALID_LAT_VALUE = 1
3899 11:45:18.329167 ==============================================================
3900 11:45:18.332524 Enter into Gating configuration >>>>
3901 11:45:18.335368 Exit from Gating configuration <<<<
3902 11:45:18.339201 Enter into DVFS_PRE_config >>>>>
3903 11:45:18.349010 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 11:45:18.352620 Exit from DVFS_PRE_config <<<<<
3905 11:45:18.355635 Enter into PICG configuration >>>>
3906 11:45:18.359370 Exit from PICG configuration <<<<
3907 11:45:18.362676 [RX_INPUT] configuration >>>>>
3908 11:45:18.365397 [RX_INPUT] configuration <<<<<
3909 11:45:18.368775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 11:45:18.376001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 11:45:18.382273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 11:45:18.388830 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 11:45:18.395312 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 11:45:18.398567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 11:45:18.405226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 11:45:18.408830 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 11:45:18.411989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 11:45:18.414981 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 11:45:18.421641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 11:45:18.425092 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 11:45:18.428073 ===================================
3922 11:45:18.431760 LPDDR4 DRAM CONFIGURATION
3923 11:45:18.434632 ===================================
3924 11:45:18.435088 EX_ROW_EN[0] = 0x0
3925 11:45:18.437988 EX_ROW_EN[1] = 0x0
3926 11:45:18.438443 LP4Y_EN = 0x0
3927 11:45:18.441420 WORK_FSP = 0x0
3928 11:45:18.441878 WL = 0x2
3929 11:45:18.444952 RL = 0x2
3930 11:45:18.445407 BL = 0x2
3931 11:45:18.447939 RPST = 0x0
3932 11:45:18.451749 RD_PRE = 0x0
3933 11:45:18.452360 WR_PRE = 0x1
3934 11:45:18.454520 WR_PST = 0x0
3935 11:45:18.454978 DBI_WR = 0x0
3936 11:45:18.458333 DBI_RD = 0x0
3937 11:45:18.458891 OTF = 0x1
3938 11:45:18.461668 ===================================
3939 11:45:18.464371 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 11:45:18.471162 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 11:45:18.474762 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 11:45:18.477987 ===================================
3943 11:45:18.481309 LPDDR4 DRAM CONFIGURATION
3944 11:45:18.484332 ===================================
3945 11:45:18.484752 EX_ROW_EN[0] = 0x10
3946 11:45:18.487904 EX_ROW_EN[1] = 0x0
3947 11:45:18.488350 LP4Y_EN = 0x0
3948 11:45:18.490703 WORK_FSP = 0x0
3949 11:45:18.491114 WL = 0x2
3950 11:45:18.494445 RL = 0x2
3951 11:45:18.494952 BL = 0x2
3952 11:45:18.497897 RPST = 0x0
3953 11:45:18.498313 RD_PRE = 0x0
3954 11:45:18.500754 WR_PRE = 0x1
3955 11:45:18.504306 WR_PST = 0x0
3956 11:45:18.504723 DBI_WR = 0x0
3957 11:45:18.507344 DBI_RD = 0x0
3958 11:45:18.507756 OTF = 0x1
3959 11:45:18.510807 ===================================
3960 11:45:18.517229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 11:45:18.521564 nWR fixed to 30
3962 11:45:18.524312 [ModeRegInit_LP4] CH0 RK0
3963 11:45:18.524731 [ModeRegInit_LP4] CH0 RK1
3964 11:45:18.527917 [ModeRegInit_LP4] CH1 RK0
3965 11:45:18.531139 [ModeRegInit_LP4] CH1 RK1
3966 11:45:18.531574 match AC timing 17
3967 11:45:18.538157 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 11:45:18.540932 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 11:45:18.544344 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 11:45:18.551784 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 11:45:18.554786 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 11:45:18.555358 ==
3973 11:45:18.558057 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 11:45:18.561061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 11:45:18.561596 ==
3976 11:45:18.568075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 11:45:18.574471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3978 11:45:18.577885 [CA 0] Center 37 (7~67) winsize 61
3979 11:45:18.580756 [CA 1] Center 36 (6~67) winsize 62
3980 11:45:18.584020 [CA 2] Center 35 (5~65) winsize 61
3981 11:45:18.587522 [CA 3] Center 35 (5~65) winsize 61
3982 11:45:18.590972 [CA 4] Center 34 (4~65) winsize 62
3983 11:45:18.594294 [CA 5] Center 33 (3~64) winsize 62
3984 11:45:18.594842
3985 11:45:18.597578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3986 11:45:18.598008
3987 11:45:18.600540 [CATrainingPosCal] consider 1 rank data
3988 11:45:18.604389 u2DelayCellTimex100 = 270/100 ps
3989 11:45:18.607512 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3990 11:45:18.610540 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3991 11:45:18.614022 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3992 11:45:18.617564 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3993 11:45:18.620948 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 11:45:18.627421 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 11:45:18.628110
3996 11:45:18.630703 CA PerBit enable=1, Macro0, CA PI delay=33
3997 11:45:18.631120
3998 11:45:18.634116 [CBTSetCACLKResult] CA Dly = 33
3999 11:45:18.634544 CS Dly: 6 (0~37)
4000 11:45:18.635013 ==
4001 11:45:18.637448 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 11:45:18.640624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 11:45:18.644130 ==
4004 11:45:18.647461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 11:45:18.654141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 11:45:18.657277 [CA 0] Center 37 (7~67) winsize 61
4007 11:45:18.660753 [CA 1] Center 37 (7~67) winsize 61
4008 11:45:18.663602 [CA 2] Center 35 (5~65) winsize 61
4009 11:45:18.667487 [CA 3] Center 35 (5~65) winsize 61
4010 11:45:18.671018 [CA 4] Center 34 (4~64) winsize 61
4011 11:45:18.673588 [CA 5] Center 33 (3~64) winsize 62
4012 11:45:18.674042
4013 11:45:18.677361 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 11:45:18.677879
4015 11:45:18.681110 [CATrainingPosCal] consider 2 rank data
4016 11:45:18.683945 u2DelayCellTimex100 = 270/100 ps
4017 11:45:18.687314 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4018 11:45:18.690680 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
4019 11:45:18.694301 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4020 11:45:18.700678 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4021 11:45:18.704364 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4022 11:45:18.707256 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 11:45:18.707815
4024 11:45:18.710613 CA PerBit enable=1, Macro0, CA PI delay=33
4025 11:45:18.711236
4026 11:45:18.713752 [CBTSetCACLKResult] CA Dly = 33
4027 11:45:18.714442 CS Dly: 6 (0~38)
4028 11:45:18.714832
4029 11:45:18.717070 ----->DramcWriteLeveling(PI) begin...
4030 11:45:18.717534 ==
4031 11:45:18.720517 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 11:45:18.727280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 11:45:18.727864 ==
4034 11:45:18.730547 Write leveling (Byte 0): 32 => 32
4035 11:45:18.733905 Write leveling (Byte 1): 31 => 31
4036 11:45:18.736949 DramcWriteLeveling(PI) end<-----
4037 11:45:18.737372
4038 11:45:18.737701 ==
4039 11:45:18.740184 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 11:45:18.743754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 11:45:18.744340 ==
4042 11:45:18.746974 [Gating] SW mode calibration
4043 11:45:18.753679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 11:45:18.757204 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 11:45:18.763975 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 11:45:18.766547 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 11:45:18.770083 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 11:45:18.776809 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4049 11:45:18.780371 0 9 16 | B1->B0 | 3030 2b2b | 0 1 | (0 0) (1 0)
4050 11:45:18.783703 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4051 11:45:18.790014 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 11:45:18.793346 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 11:45:18.796658 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:45:18.803349 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:45:18.806878 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:45:18.809994 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4057 11:45:18.816526 0 10 16 | B1->B0 | 3434 3939 | 1 0 | (0 0) (0 0)
4058 11:45:18.819876 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 11:45:18.823030 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:45:18.829694 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 11:45:18.832933 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:45:18.836690 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:45:18.843143 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:45:18.846141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4065 11:45:18.849411 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4066 11:45:18.855959 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:45:18.859535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:45:18.862905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:45:18.869651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:45:18.872686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:45:18.876422 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:45:18.882998 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:45:18.886636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:45:18.889469 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:45:18.895859 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:45:18.899386 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:45:18.902786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:45:18.909652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:45:18.912941 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:45:18.915723 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:45:18.922619 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 11:45:18.923210 Total UI for P1: 0, mck2ui 16
4083 11:45:18.926230 best dqsien dly found for B0: ( 0, 13, 14)
4084 11:45:18.929840 Total UI for P1: 0, mck2ui 16
4085 11:45:18.932517 best dqsien dly found for B1: ( 0, 13, 14)
4086 11:45:18.936062 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4087 11:45:18.942789 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4088 11:45:18.943316
4089 11:45:18.945534 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4090 11:45:18.948854 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4091 11:45:18.952541 [Gating] SW calibration Done
4092 11:45:18.952962 ==
4093 11:45:18.956188 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 11:45:18.958754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 11:45:18.959178 ==
4096 11:45:18.962685 RX Vref Scan: 0
4097 11:45:18.963202
4098 11:45:18.963536 RX Vref 0 -> 0, step: 1
4099 11:45:18.963847
4100 11:45:18.965523 RX Delay -230 -> 252, step: 16
4101 11:45:18.968766 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4102 11:45:18.975352 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4103 11:45:18.979149 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4104 11:45:18.981924 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4105 11:45:18.985680 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4106 11:45:18.992136 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4107 11:45:18.995264 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4108 11:45:18.998690 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4109 11:45:19.001701 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4110 11:45:19.008342 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4111 11:45:19.011475 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4112 11:45:19.015407 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4113 11:45:19.018349 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4114 11:45:19.024766 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4115 11:45:19.028311 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4116 11:45:19.031227 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4117 11:45:19.031644 ==
4118 11:45:19.034879 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 11:45:19.038588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 11:45:19.039136 ==
4121 11:45:19.041270 DQS Delay:
4122 11:45:19.041708 DQS0 = 0, DQS1 = 0
4123 11:45:19.044689 DQM Delay:
4124 11:45:19.045104 DQM0 = 38, DQM1 = 28
4125 11:45:19.045502 DQ Delay:
4126 11:45:19.048190 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4127 11:45:19.051624 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4128 11:45:19.054889 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4129 11:45:19.058048 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4130 11:45:19.058463
4131 11:45:19.058789
4132 11:45:19.061670 ==
4133 11:45:19.062132 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:45:19.068036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:45:19.068503 ==
4136 11:45:19.068835
4137 11:45:19.069137
4138 11:45:19.071126 TX Vref Scan disable
4139 11:45:19.071544 == TX Byte 0 ==
4140 11:45:19.078181 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4141 11:45:19.080994 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4142 11:45:19.081412 == TX Byte 1 ==
4143 11:45:19.087825 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4144 11:45:19.090810 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4145 11:45:19.091251 ==
4146 11:45:19.094467 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 11:45:19.097514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 11:45:19.097941 ==
4149 11:45:19.098282
4150 11:45:19.098591
4151 11:45:19.101108 TX Vref Scan disable
4152 11:45:19.104257 == TX Byte 0 ==
4153 11:45:19.107395 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4154 11:45:19.110993 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4155 11:45:19.113962 == TX Byte 1 ==
4156 11:45:19.117438 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4157 11:45:19.120735 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4158 11:45:19.121152
4159 11:45:19.123912 [DATLAT]
4160 11:45:19.124370 Freq=600, CH0 RK0
4161 11:45:19.124704
4162 11:45:19.127396 DATLAT Default: 0x9
4163 11:45:19.127862 0, 0xFFFF, sum = 0
4164 11:45:19.130747 1, 0xFFFF, sum = 0
4165 11:45:19.131176 2, 0xFFFF, sum = 0
4166 11:45:19.134641 3, 0xFFFF, sum = 0
4167 11:45:19.135185 4, 0xFFFF, sum = 0
4168 11:45:19.137374 5, 0xFFFF, sum = 0
4169 11:45:19.137804 6, 0xFFFF, sum = 0
4170 11:45:19.140949 7, 0xFFFF, sum = 0
4171 11:45:19.141407 8, 0x0, sum = 1
4172 11:45:19.143862 9, 0x0, sum = 2
4173 11:45:19.144330 10, 0x0, sum = 3
4174 11:45:19.147259 11, 0x0, sum = 4
4175 11:45:19.147892 best_step = 9
4176 11:45:19.148437
4177 11:45:19.148765 ==
4178 11:45:19.150762 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 11:45:19.157274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 11:45:19.157801 ==
4181 11:45:19.158133 RX Vref Scan: 1
4182 11:45:19.158438
4183 11:45:19.160427 RX Vref 0 -> 0, step: 1
4184 11:45:19.160951
4185 11:45:19.163776 RX Delay -195 -> 252, step: 8
4186 11:45:19.164373
4187 11:45:19.167075 Set Vref, RX VrefLevel [Byte0]: 61
4188 11:45:19.170383 [Byte1]: 53
4189 11:45:19.170808
4190 11:45:19.173874 Final RX Vref Byte 0 = 61 to rank0
4191 11:45:19.176997 Final RX Vref Byte 1 = 53 to rank0
4192 11:45:19.180740 Final RX Vref Byte 0 = 61 to rank1
4193 11:45:19.183766 Final RX Vref Byte 1 = 53 to rank1==
4194 11:45:19.187256 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 11:45:19.190581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 11:45:19.191121 ==
4197 11:45:19.194019 DQS Delay:
4198 11:45:19.194557 DQS0 = 0, DQS1 = 0
4199 11:45:19.196720 DQM Delay:
4200 11:45:19.197136 DQM0 = 33, DQM1 = 28
4201 11:45:19.197467 DQ Delay:
4202 11:45:19.200285 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4203 11:45:19.203454 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4204 11:45:19.207274 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4205 11:45:19.210195 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4206 11:45:19.210793
4207 11:45:19.211168
4208 11:45:19.220422 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4209 11:45:19.223283 CH0 RK0: MR19=808, MR18=3D3B
4210 11:45:19.226793 CH0_RK0: MR19=0x808, MR18=0x3D3B, DQSOSC=398, MR23=63, INC=165, DEC=110
4211 11:45:19.229811
4212 11:45:19.233349 ----->DramcWriteLeveling(PI) begin...
4213 11:45:19.233850 ==
4214 11:45:19.236689 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 11:45:19.239927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 11:45:19.240581 ==
4217 11:45:19.243228 Write leveling (Byte 0): 31 => 31
4218 11:45:19.246573 Write leveling (Byte 1): 31 => 31
4219 11:45:19.250200 DramcWriteLeveling(PI) end<-----
4220 11:45:19.250706
4221 11:45:19.251217 ==
4222 11:45:19.253470 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 11:45:19.256698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 11:45:19.257135 ==
4225 11:45:19.260158 [Gating] SW mode calibration
4226 11:45:19.266581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 11:45:19.273272 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4228 11:45:19.276447 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 11:45:19.279871 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 11:45:19.286816 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 11:45:19.289667 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4232 11:45:19.293025 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4233 11:45:19.299558 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 11:45:19.302728 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:45:19.306507 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 11:45:19.313141 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 11:45:19.316191 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:45:19.319758 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:45:19.323423 0 10 12 | B1->B0 | 2c2c 3030 | 1 0 | (1 1) (0 0)
4240 11:45:19.329833 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4241 11:45:19.332689 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 11:45:19.336349 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:45:19.342953 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:45:19.346190 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 11:45:19.349247 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:45:19.356401 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:45:19.359193 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4248 11:45:19.362777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4249 11:45:19.369206 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:45:19.372641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:45:19.376350 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:45:19.382383 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:45:19.386276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:45:19.389500 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:45:19.395951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:45:19.399571 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:45:19.402381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:45:19.409408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:45:19.412399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:45:19.415602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:45:19.422166 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:45:19.426164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:45:19.428920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4264 11:45:19.435448 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4265 11:45:19.435893 Total UI for P1: 0, mck2ui 16
4266 11:45:19.442262 best dqsien dly found for B0: ( 0, 13, 12)
4267 11:45:19.445464 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 11:45:19.448711 Total UI for P1: 0, mck2ui 16
4269 11:45:19.452360 best dqsien dly found for B1: ( 0, 13, 16)
4270 11:45:19.455448 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4271 11:45:19.458593 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4272 11:45:19.459030
4273 11:45:19.462083 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4274 11:45:19.465303 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4275 11:45:19.468803 [Gating] SW calibration Done
4276 11:45:19.469239 ==
4277 11:45:19.471857 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 11:45:19.475505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 11:45:19.478493 ==
4280 11:45:19.478987 RX Vref Scan: 0
4281 11:45:19.479493
4282 11:45:19.482122 RX Vref 0 -> 0, step: 1
4283 11:45:19.482555
4284 11:45:19.485479 RX Delay -230 -> 252, step: 16
4285 11:45:19.488481 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4286 11:45:19.491808 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4287 11:45:19.495263 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4288 11:45:19.501827 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4289 11:45:19.505414 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4290 11:45:19.508885 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4291 11:45:19.512091 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4292 11:45:19.515485 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4293 11:45:19.521901 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4294 11:45:19.525237 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4295 11:45:19.528362 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4296 11:45:19.531422 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4297 11:45:19.538328 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4298 11:45:19.541880 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4299 11:45:19.545340 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4300 11:45:19.548345 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4301 11:45:19.548765 ==
4302 11:45:19.551799 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 11:45:19.558927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 11:45:19.559465 ==
4305 11:45:19.559914 DQS Delay:
4306 11:45:19.561454 DQS0 = 0, DQS1 = 0
4307 11:45:19.561886 DQM Delay:
4308 11:45:19.562321 DQM0 = 35, DQM1 = 29
4309 11:45:19.565148 DQ Delay:
4310 11:45:19.568126 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4311 11:45:19.571514 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4312 11:45:19.575340 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4313 11:45:19.578421 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4314 11:45:19.578881
4315 11:45:19.579316
4316 11:45:19.579727 ==
4317 11:45:19.582100 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 11:45:19.585192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:45:19.585651 ==
4320 11:45:19.586092
4321 11:45:19.586505
4322 11:45:19.588697 TX Vref Scan disable
4323 11:45:19.591894 == TX Byte 0 ==
4324 11:45:19.595144 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4325 11:45:19.598314 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4326 11:45:19.601706 == TX Byte 1 ==
4327 11:45:19.604610 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4328 11:45:19.608168 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4329 11:45:19.608650 ==
4330 11:45:19.611926 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 11:45:19.614986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 11:45:19.615527 ==
4333 11:45:19.618320
4334 11:45:19.618843
4335 11:45:19.619280 TX Vref Scan disable
4336 11:45:19.621905 == TX Byte 0 ==
4337 11:45:19.624941 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4338 11:45:19.631797 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4339 11:45:19.632425 == TX Byte 1 ==
4340 11:45:19.635012 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 11:45:19.641679 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 11:45:19.642270
4343 11:45:19.642624 [DATLAT]
4344 11:45:19.642937 Freq=600, CH0 RK1
4345 11:45:19.643238
4346 11:45:19.645115 DATLAT Default: 0x9
4347 11:45:19.645608 0, 0xFFFF, sum = 0
4348 11:45:19.648473 1, 0xFFFF, sum = 0
4349 11:45:19.648906 2, 0xFFFF, sum = 0
4350 11:45:19.651345 3, 0xFFFF, sum = 0
4351 11:45:19.655007 4, 0xFFFF, sum = 0
4352 11:45:19.655433 5, 0xFFFF, sum = 0
4353 11:45:19.657977 6, 0xFFFF, sum = 0
4354 11:45:19.658698 7, 0xFFFF, sum = 0
4355 11:45:19.661545 8, 0x0, sum = 1
4356 11:45:19.662176 9, 0x0, sum = 2
4357 11:45:19.662756 10, 0x0, sum = 3
4358 11:45:19.664775 11, 0x0, sum = 4
4359 11:45:19.665391 best_step = 9
4360 11:45:19.665741
4361 11:45:19.666052 ==
4362 11:45:19.667727 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 11:45:19.674705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:45:19.675130 ==
4365 11:45:19.675461 RX Vref Scan: 0
4366 11:45:19.675767
4367 11:45:19.677590 RX Vref 0 -> 0, step: 1
4368 11:45:19.677984
4369 11:45:19.681268 RX Delay -195 -> 252, step: 8
4370 11:45:19.684612 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4371 11:45:19.691360 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4372 11:45:19.694342 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4373 11:45:19.697668 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4374 11:45:19.701003 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4375 11:45:19.708127 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4376 11:45:19.711358 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4377 11:45:19.714508 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4378 11:45:19.717494 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4379 11:45:19.721001 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4380 11:45:19.727773 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4381 11:45:19.731195 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4382 11:45:19.734135 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4383 11:45:19.737900 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4384 11:45:19.744165 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4385 11:45:19.747692 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4386 11:45:19.748109 ==
4387 11:45:19.751225 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 11:45:19.754366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 11:45:19.754792 ==
4390 11:45:19.757582 DQS Delay:
4391 11:45:19.757997 DQS0 = 0, DQS1 = 0
4392 11:45:19.760695 DQM Delay:
4393 11:45:19.761110 DQM0 = 33, DQM1 = 27
4394 11:45:19.761438 DQ Delay:
4395 11:45:19.763980 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4396 11:45:19.767632 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4397 11:45:19.770664 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4398 11:45:19.774237 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4399 11:45:19.774673
4400 11:45:19.775085
4401 11:45:19.784179 [DQSOSCAuto] RK1, (LSB)MR18= 0x7342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4402 11:45:19.787325 CH0 RK1: MR19=808, MR18=7342
4403 11:45:19.794068 CH0_RK1: MR19=0x808, MR18=0x7342, DQSOSC=388, MR23=63, INC=174, DEC=116
4404 11:45:19.794664 [RxdqsGatingPostProcess] freq 600
4405 11:45:19.800433 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4406 11:45:19.803689 Pre-setting of DQS Precalculation
4407 11:45:19.807119 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4408 11:45:19.810149 ==
4409 11:45:19.810752 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 11:45:19.817159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 11:45:19.817724 ==
4412 11:45:19.820598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 11:45:19.827188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4414 11:45:19.830416 [CA 0] Center 35 (5~66) winsize 62
4415 11:45:19.833696 [CA 1] Center 35 (5~66) winsize 62
4416 11:45:19.837407 [CA 2] Center 34 (4~65) winsize 62
4417 11:45:19.840436 [CA 3] Center 34 (3~65) winsize 63
4418 11:45:19.843665 [CA 4] Center 34 (4~65) winsize 62
4419 11:45:19.847294 [CA 5] Center 33 (3~64) winsize 62
4420 11:45:19.847710
4421 11:45:19.850341 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4422 11:45:19.850756
4423 11:45:19.854031 [CATrainingPosCal] consider 1 rank data
4424 11:45:19.856873 u2DelayCellTimex100 = 270/100 ps
4425 11:45:19.860149 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 11:45:19.866880 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 11:45:19.870431 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 11:45:19.873692 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4429 11:45:19.876669 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 11:45:19.880447 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 11:45:19.880867
4432 11:45:19.883484 CA PerBit enable=1, Macro0, CA PI delay=33
4433 11:45:19.883901
4434 11:45:19.887097 [CBTSetCACLKResult] CA Dly = 33
4435 11:45:19.889942 CS Dly: 5 (0~36)
4436 11:45:19.890358 ==
4437 11:45:19.893525 Dram Type= 6, Freq= 0, CH_1, rank 1
4438 11:45:19.896959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 11:45:19.897382 ==
4440 11:45:19.903470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4441 11:45:19.907148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4442 11:45:19.910871 [CA 0] Center 36 (6~66) winsize 61
4443 11:45:19.913808 [CA 1] Center 36 (6~66) winsize 61
4444 11:45:19.917465 [CA 2] Center 34 (4~65) winsize 62
4445 11:45:19.920569 [CA 3] Center 34 (3~65) winsize 63
4446 11:45:19.923974 [CA 4] Center 34 (4~65) winsize 62
4447 11:45:19.927238 [CA 5] Center 33 (3~64) winsize 62
4448 11:45:19.927657
4449 11:45:19.930678 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4450 11:45:19.931209
4451 11:45:19.933651 [CATrainingPosCal] consider 2 rank data
4452 11:45:19.937063 u2DelayCellTimex100 = 270/100 ps
4453 11:45:19.940299 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4454 11:45:19.947014 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4455 11:45:19.950271 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 11:45:19.953797 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4457 11:45:19.956950 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 11:45:19.960404 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 11:45:19.960638
4460 11:45:19.963445 CA PerBit enable=1, Macro0, CA PI delay=33
4461 11:45:19.963656
4462 11:45:19.967101 [CBTSetCACLKResult] CA Dly = 33
4463 11:45:19.967305 CS Dly: 5 (0~37)
4464 11:45:19.969967
4465 11:45:19.973747 ----->DramcWriteLeveling(PI) begin...
4466 11:45:19.973956 ==
4467 11:45:19.976371 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 11:45:19.979933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 11:45:19.980168 ==
4470 11:45:19.983176 Write leveling (Byte 0): 28 => 28
4471 11:45:19.986742 Write leveling (Byte 1): 33 => 33
4472 11:45:19.989809 DramcWriteLeveling(PI) end<-----
4473 11:45:19.990033
4474 11:45:19.990177 ==
4475 11:45:19.993346 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 11:45:19.996474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 11:45:19.996689 ==
4478 11:45:20.000049 [Gating] SW mode calibration
4479 11:45:20.006706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4480 11:45:20.012942 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4481 11:45:20.016231 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 11:45:20.019373 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 11:45:20.026134 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 11:45:20.029607 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 0)
4485 11:45:20.032834 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 11:45:20.039953 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:45:20.042931 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 11:45:20.045865 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 11:45:20.052730 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 11:45:20.056062 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 11:45:20.059099 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 11:45:20.066107 0 10 12 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
4493 11:45:20.069490 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4494 11:45:20.073076 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 11:45:20.079599 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 11:45:20.083209 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 11:45:20.086180 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 11:45:20.092860 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 11:45:20.095931 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:45:20.099584 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4501 11:45:20.103052 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:45:20.109549 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:45:20.112398 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:45:20.116059 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:45:20.122546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:45:20.126030 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:45:20.129006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:45:20.136128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:45:20.139129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:45:20.142406 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:45:20.149304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:45:20.152706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:45:20.155621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:45:20.162457 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:45:20.165435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:45:20.168696 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4517 11:45:20.175475 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4518 11:45:20.179174 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 11:45:20.182090 Total UI for P1: 0, mck2ui 16
4520 11:45:20.185747 best dqsien dly found for B0: ( 0, 13, 14)
4521 11:45:20.188580 Total UI for P1: 0, mck2ui 16
4522 11:45:20.192255 best dqsien dly found for B1: ( 0, 13, 16)
4523 11:45:20.195339 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4524 11:45:20.198989 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4525 11:45:20.199304
4526 11:45:20.201922 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4527 11:45:20.205391 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4528 11:45:20.208322 [Gating] SW calibration Done
4529 11:45:20.208554 ==
4530 11:45:20.212025 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 11:45:20.218527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 11:45:20.218799 ==
4533 11:45:20.218976 RX Vref Scan: 0
4534 11:45:20.219162
4535 11:45:20.222162 RX Vref 0 -> 0, step: 1
4536 11:45:20.222467
4537 11:45:20.225086 RX Delay -230 -> 252, step: 16
4538 11:45:20.228725 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4539 11:45:20.231798 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4540 11:45:20.234774 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4541 11:45:20.241695 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4542 11:45:20.245427 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4543 11:45:20.248390 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4544 11:45:20.251910 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4545 11:45:20.255218 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4546 11:45:20.261608 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4547 11:45:20.265155 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4548 11:45:20.268073 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4549 11:45:20.271377 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4550 11:45:20.278271 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4551 11:45:20.281413 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4552 11:45:20.284808 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4553 11:45:20.288145 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4554 11:45:20.291151 ==
4555 11:45:20.294840 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:45:20.297800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:45:20.297883 ==
4558 11:45:20.297949 DQS Delay:
4559 11:45:20.301401 DQS0 = 0, DQS1 = 0
4560 11:45:20.301483 DQM Delay:
4561 11:45:20.304318 DQM0 = 37, DQM1 = 29
4562 11:45:20.304407 DQ Delay:
4563 11:45:20.307937 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4564 11:45:20.310860 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4565 11:45:20.314343 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4566 11:45:20.317515 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4567 11:45:20.317684
4568 11:45:20.317780
4569 11:45:20.317863 ==
4570 11:45:20.321264 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 11:45:20.324340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:45:20.324467 ==
4573 11:45:20.324564
4574 11:45:20.324654
4575 11:45:20.328076 TX Vref Scan disable
4576 11:45:20.330808 == TX Byte 0 ==
4577 11:45:20.334456 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 11:45:20.337964 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 11:45:20.341035 == TX Byte 1 ==
4580 11:45:20.344554 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4581 11:45:20.347587 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4582 11:45:20.347798 ==
4583 11:45:20.351110 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 11:45:20.357580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 11:45:20.357931 ==
4586 11:45:20.358256
4587 11:45:20.358554
4588 11:45:20.358842 TX Vref Scan disable
4589 11:45:20.362516 == TX Byte 0 ==
4590 11:45:20.365341 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4591 11:45:20.372375 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4592 11:45:20.372794 == TX Byte 1 ==
4593 11:45:20.375388 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4594 11:45:20.382270 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4595 11:45:20.382686
4596 11:45:20.383012 [DATLAT]
4597 11:45:20.383313 Freq=600, CH1 RK0
4598 11:45:20.383607
4599 11:45:20.385238 DATLAT Default: 0x9
4600 11:45:20.385654 0, 0xFFFF, sum = 0
4601 11:45:20.388834 1, 0xFFFF, sum = 0
4602 11:45:20.389256 2, 0xFFFF, sum = 0
4603 11:45:20.392487 3, 0xFFFF, sum = 0
4604 11:45:20.395496 4, 0xFFFF, sum = 0
4605 11:45:20.395921 5, 0xFFFF, sum = 0
4606 11:45:20.398772 6, 0xFFFF, sum = 0
4607 11:45:20.399302 7, 0xFFFF, sum = 0
4608 11:45:20.402190 8, 0x0, sum = 1
4609 11:45:20.402646 9, 0x0, sum = 2
4610 11:45:20.403118 10, 0x0, sum = 3
4611 11:45:20.405336 11, 0x0, sum = 4
4612 11:45:20.405882 best_step = 9
4613 11:45:20.406218
4614 11:45:20.406702 ==
4615 11:45:20.408840 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 11:45:20.415315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 11:45:20.415737 ==
4618 11:45:20.416328 RX Vref Scan: 1
4619 11:45:20.416780
4620 11:45:20.418501 RX Vref 0 -> 0, step: 1
4621 11:45:20.419139
4622 11:45:20.421620 RX Delay -195 -> 252, step: 8
4623 11:45:20.422048
4624 11:45:20.425396 Set Vref, RX VrefLevel [Byte0]: 60
4625 11:45:20.428708 [Byte1]: 56
4626 11:45:20.429125
4627 11:45:20.431834 Final RX Vref Byte 0 = 60 to rank0
4628 11:45:20.434726 Final RX Vref Byte 1 = 56 to rank0
4629 11:45:20.438040 Final RX Vref Byte 0 = 60 to rank1
4630 11:45:20.441731 Final RX Vref Byte 1 = 56 to rank1==
4631 11:45:20.444807 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 11:45:20.447861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 11:45:20.448314 ==
4634 11:45:20.451431 DQS Delay:
4635 11:45:20.451724 DQS0 = 0, DQS1 = 0
4636 11:45:20.454487 DQM Delay:
4637 11:45:20.454891 DQM0 = 37, DQM1 = 28
4638 11:45:20.455254 DQ Delay:
4639 11:45:20.458166 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4640 11:45:20.461002 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4641 11:45:20.464593 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4642 11:45:20.467675 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4643 11:45:20.467968
4644 11:45:20.468292
4645 11:45:20.477949 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4646 11:45:20.481220 CH1 RK0: MR19=808, MR18=1F2C
4647 11:45:20.487799 CH1_RK0: MR19=0x808, MR18=0x1F2C, DQSOSC=401, MR23=63, INC=163, DEC=108
4648 11:45:20.488186
4649 11:45:20.491288 ----->DramcWriteLeveling(PI) begin...
4650 11:45:20.491588 ==
4651 11:45:20.494523 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 11:45:20.497749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 11:45:20.498119 ==
4654 11:45:20.501062 Write leveling (Byte 0): 31 => 31
4655 11:45:20.504244 Write leveling (Byte 1): 31 => 31
4656 11:45:20.507969 DramcWriteLeveling(PI) end<-----
4657 11:45:20.508308
4658 11:45:20.508613 ==
4659 11:45:20.510793 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 11:45:20.514186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 11:45:20.514591 ==
4662 11:45:20.517777 [Gating] SW mode calibration
4663 11:45:20.523771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4664 11:45:20.530644 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4665 11:45:20.534121 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 11:45:20.537277 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 11:45:20.543646 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4668 11:45:20.546988 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (0 1) (1 1)
4669 11:45:20.550413 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 11:45:20.557087 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 11:45:20.560410 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 11:45:20.563261 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 11:45:20.570433 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 11:45:20.573405 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:45:20.576498 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4676 11:45:20.583417 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (1 1)
4677 11:45:20.586468 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4678 11:45:20.590070 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 11:45:20.596804 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 11:45:20.600197 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:45:20.602903 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 11:45:20.609609 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:45:20.613300 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:45:20.616363 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4685 11:45:20.622774 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:45:20.626590 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:45:20.629508 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:45:20.636190 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:45:20.639753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:45:20.642843 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:45:20.649680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:45:20.652518 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:45:20.656080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:45:20.662857 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:45:20.666118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:45:20.669146 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:45:20.676168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:45:20.679168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:45:20.682743 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:45:20.689221 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4701 11:45:20.689320 Total UI for P1: 0, mck2ui 16
4702 11:45:20.695787 best dqsien dly found for B0: ( 0, 13, 10)
4703 11:45:20.699382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 11:45:20.702298 Total UI for P1: 0, mck2ui 16
4705 11:45:20.705780 best dqsien dly found for B1: ( 0, 13, 12)
4706 11:45:20.709347 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4707 11:45:20.712378 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4708 11:45:20.712456
4709 11:45:20.715382 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4710 11:45:20.719027 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4711 11:45:20.722548 [Gating] SW calibration Done
4712 11:45:20.722649 ==
4713 11:45:20.725510 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 11:45:20.728660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 11:45:20.732371 ==
4716 11:45:20.732477 RX Vref Scan: 0
4717 11:45:20.732574
4718 11:45:20.735757 RX Vref 0 -> 0, step: 1
4719 11:45:20.735874
4720 11:45:20.738633 RX Delay -230 -> 252, step: 16
4721 11:45:20.741710 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4722 11:45:20.745384 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4723 11:45:20.748439 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4724 11:45:20.755707 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4725 11:45:20.758594 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4726 11:45:20.762237 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4727 11:45:20.765279 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4728 11:45:20.768971 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4729 11:45:20.775115 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4730 11:45:20.778480 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4731 11:45:20.782285 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4732 11:45:20.785406 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4733 11:45:20.791825 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4734 11:45:20.794843 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4735 11:45:20.798316 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4736 11:45:20.801873 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4737 11:45:20.801991 ==
4738 11:45:20.805061 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:45:20.811518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:45:20.811616 ==
4741 11:45:20.811683 DQS Delay:
4742 11:45:20.815031 DQS0 = 0, DQS1 = 0
4743 11:45:20.815108 DQM Delay:
4744 11:45:20.817987 DQM0 = 36, DQM1 = 32
4745 11:45:20.818062 DQ Delay:
4746 11:45:20.821503 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4747 11:45:20.824601 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4748 11:45:20.828067 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4749 11:45:20.831264 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4750 11:45:20.831336
4751 11:45:20.831397
4752 11:45:20.831455 ==
4753 11:45:20.834760 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 11:45:20.838367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 11:45:20.838460 ==
4756 11:45:20.838533
4757 11:45:20.838600
4758 11:45:20.840979 TX Vref Scan disable
4759 11:45:20.844345 == TX Byte 0 ==
4760 11:45:20.847708 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 11:45:20.850786 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 11:45:20.854428 == TX Byte 1 ==
4763 11:45:20.858211 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4764 11:45:20.861074 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4765 11:45:20.861265 ==
4766 11:45:20.864702 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 11:45:20.871258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 11:45:20.871497 ==
4769 11:45:20.871692
4770 11:45:20.871858
4771 11:45:20.872044 TX Vref Scan disable
4772 11:45:20.875467 == TX Byte 0 ==
4773 11:45:20.878421 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4774 11:45:20.885169 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4775 11:45:20.885368 == TX Byte 1 ==
4776 11:45:20.888730 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4777 11:45:20.895191 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4778 11:45:20.895370
4779 11:45:20.895507 [DATLAT]
4780 11:45:20.895639 Freq=600, CH1 RK1
4781 11:45:20.895773
4782 11:45:20.898384 DATLAT Default: 0x9
4783 11:45:20.898614 0, 0xFFFF, sum = 0
4784 11:45:20.901755 1, 0xFFFF, sum = 0
4785 11:45:20.901997 2, 0xFFFF, sum = 0
4786 11:45:20.905193 3, 0xFFFF, sum = 0
4787 11:45:20.908278 4, 0xFFFF, sum = 0
4788 11:45:20.908515 5, 0xFFFF, sum = 0
4789 11:45:20.911480 6, 0xFFFF, sum = 0
4790 11:45:20.911719 7, 0xFFFF, sum = 0
4791 11:45:20.915237 8, 0x0, sum = 1
4792 11:45:20.915453 9, 0x0, sum = 2
4793 11:45:20.915704 10, 0x0, sum = 3
4794 11:45:20.918239 11, 0x0, sum = 4
4795 11:45:20.918482 best_step = 9
4796 11:45:20.918696
4797 11:45:20.918896 ==
4798 11:45:20.921816 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 11:45:20.928842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 11:45:20.929020 ==
4801 11:45:20.929159 RX Vref Scan: 0
4802 11:45:20.929305
4803 11:45:20.931641 RX Vref 0 -> 0, step: 1
4804 11:45:20.931818
4805 11:45:20.935262 RX Delay -195 -> 252, step: 8
4806 11:45:20.938160 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4807 11:45:20.944812 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4808 11:45:20.948513 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4809 11:45:20.951628 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4810 11:45:20.955024 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4811 11:45:20.961559 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4812 11:45:20.965419 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4813 11:45:20.968355 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4814 11:45:20.972077 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4815 11:45:20.975005 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4816 11:45:20.982108 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4817 11:45:20.984778 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4818 11:45:20.988315 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4819 11:45:20.991813 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4820 11:45:20.998551 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4821 11:45:21.001443 iDelay=205, Bit 15, Center 40 (-123 ~ 204) 328
4822 11:45:21.001877 ==
4823 11:45:21.004908 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 11:45:21.008658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 11:45:21.009081 ==
4826 11:45:21.011488 DQS Delay:
4827 11:45:21.011906 DQS0 = 0, DQS1 = 0
4828 11:45:21.012286 DQM Delay:
4829 11:45:21.014787 DQM0 = 35, DQM1 = 30
4830 11:45:21.015204 DQ Delay:
4831 11:45:21.018541 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4832 11:45:21.021429 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =36
4833 11:45:21.024870 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4834 11:45:21.028135 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =40
4835 11:45:21.028619
4836 11:45:21.028997
4837 11:45:21.038111 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4838 11:45:21.041397 CH1 RK1: MR19=808, MR18=3A5A
4839 11:45:21.044623 CH1_RK1: MR19=0x808, MR18=0x3A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4840 11:45:21.048259 [RxdqsGatingPostProcess] freq 600
4841 11:45:21.054837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4842 11:45:21.057940 Pre-setting of DQS Precalculation
4843 11:45:21.061467 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4844 11:45:21.071075 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4845 11:45:21.077673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4846 11:45:21.077901
4847 11:45:21.078151
4848 11:45:21.081109 [Calibration Summary] 1200 Mbps
4849 11:45:21.081337 CH 0, Rank 0
4850 11:45:21.084266 SW Impedance : PASS
4851 11:45:21.084494 DUTY Scan : NO K
4852 11:45:21.087907 ZQ Calibration : PASS
4853 11:45:21.090890 Jitter Meter : NO K
4854 11:45:21.091115 CBT Training : PASS
4855 11:45:21.094431 Write leveling : PASS
4856 11:45:21.097429 RX DQS gating : PASS
4857 11:45:21.097654 RX DQ/DQS(RDDQC) : PASS
4858 11:45:21.100919 TX DQ/DQS : PASS
4859 11:45:21.104062 RX DATLAT : PASS
4860 11:45:21.104174 RX DQ/DQS(Engine): PASS
4861 11:45:21.107422 TX OE : NO K
4862 11:45:21.107505 All Pass.
4863 11:45:21.107570
4864 11:45:21.110558 CH 0, Rank 1
4865 11:45:21.110641 SW Impedance : PASS
4866 11:45:21.114051 DUTY Scan : NO K
4867 11:45:21.114133 ZQ Calibration : PASS
4868 11:45:21.117495 Jitter Meter : NO K
4869 11:45:21.120341 CBT Training : PASS
4870 11:45:21.120424 Write leveling : PASS
4871 11:45:21.123757 RX DQS gating : PASS
4872 11:45:21.126884 RX DQ/DQS(RDDQC) : PASS
4873 11:45:21.126967 TX DQ/DQS : PASS
4874 11:45:21.130682 RX DATLAT : PASS
4875 11:45:21.133704 RX DQ/DQS(Engine): PASS
4876 11:45:21.133788 TX OE : NO K
4877 11:45:21.136941 All Pass.
4878 11:45:21.137030
4879 11:45:21.137095 CH 1, Rank 0
4880 11:45:21.140416 SW Impedance : PASS
4881 11:45:21.140505 DUTY Scan : NO K
4882 11:45:21.143705 ZQ Calibration : PASS
4883 11:45:21.147003 Jitter Meter : NO K
4884 11:45:21.147100 CBT Training : PASS
4885 11:45:21.150658 Write leveling : PASS
4886 11:45:21.153392 RX DQS gating : PASS
4887 11:45:21.153531 RX DQ/DQS(RDDQC) : PASS
4888 11:45:21.156839 TX DQ/DQS : PASS
4889 11:45:21.160641 RX DATLAT : PASS
4890 11:45:21.160745 RX DQ/DQS(Engine): PASS
4891 11:45:21.163527 TX OE : NO K
4892 11:45:21.163630 All Pass.
4893 11:45:21.163736
4894 11:45:21.166677 CH 1, Rank 1
4895 11:45:21.166823 SW Impedance : PASS
4896 11:45:21.170255 DUTY Scan : NO K
4897 11:45:21.170366 ZQ Calibration : PASS
4898 11:45:21.173874 Jitter Meter : NO K
4899 11:45:21.176880 CBT Training : PASS
4900 11:45:21.176983 Write leveling : PASS
4901 11:45:21.180307 RX DQS gating : PASS
4902 11:45:21.183353 RX DQ/DQS(RDDQC) : PASS
4903 11:45:21.183460 TX DQ/DQS : PASS
4904 11:45:21.186719 RX DATLAT : PASS
4905 11:45:21.190022 RX DQ/DQS(Engine): PASS
4906 11:45:21.190167 TX OE : NO K
4907 11:45:21.193301 All Pass.
4908 11:45:21.193403
4909 11:45:21.193484 DramC Write-DBI off
4910 11:45:21.196953 PER_BANK_REFRESH: Hybrid Mode
4911 11:45:21.197056 TX_TRACKING: ON
4912 11:45:21.207037 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4913 11:45:21.209969 [FAST_K] Save calibration result to emmc
4914 11:45:21.213653 dramc_set_vcore_voltage set vcore to 662500
4915 11:45:21.216687 Read voltage for 933, 3
4916 11:45:21.216829 Vio18 = 0
4917 11:45:21.220217 Vcore = 662500
4918 11:45:21.220320 Vdram = 0
4919 11:45:21.220402 Vddq = 0
4920 11:45:21.223367 Vmddr = 0
4921 11:45:21.226771 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4922 11:45:21.233217 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4923 11:45:21.233354 MEM_TYPE=3, freq_sel=17
4924 11:45:21.236394 sv_algorithm_assistance_LP4_1600
4925 11:45:21.243365 ============ PULL DRAM RESETB DOWN ============
4926 11:45:21.246381 ========== PULL DRAM RESETB DOWN end =========
4927 11:45:21.249665 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4928 11:45:21.253218 ===================================
4929 11:45:21.256622 LPDDR4 DRAM CONFIGURATION
4930 11:45:21.259942 ===================================
4931 11:45:21.260084 EX_ROW_EN[0] = 0x0
4932 11:45:21.263273 EX_ROW_EN[1] = 0x0
4933 11:45:21.266151 LP4Y_EN = 0x0
4934 11:45:21.266292 WORK_FSP = 0x0
4935 11:45:21.269911 WL = 0x3
4936 11:45:21.270015 RL = 0x3
4937 11:45:21.273524 BL = 0x2
4938 11:45:21.273628 RPST = 0x0
4939 11:45:21.276447 RD_PRE = 0x0
4940 11:45:21.276550 WR_PRE = 0x1
4941 11:45:21.279517 WR_PST = 0x0
4942 11:45:21.279621 DBI_WR = 0x0
4943 11:45:21.283163 DBI_RD = 0x0
4944 11:45:21.283268 OTF = 0x1
4945 11:45:21.286054 ===================================
4946 11:45:21.289706 ===================================
4947 11:45:21.292804 ANA top config
4948 11:45:21.296270 ===================================
4949 11:45:21.296375 DLL_ASYNC_EN = 0
4950 11:45:21.299668 ALL_SLAVE_EN = 1
4951 11:45:21.303053 NEW_RANK_MODE = 1
4952 11:45:21.306300 DLL_IDLE_MODE = 1
4953 11:45:21.309198 LP45_APHY_COMB_EN = 1
4954 11:45:21.309280 TX_ODT_DIS = 1
4955 11:45:21.312949 NEW_8X_MODE = 1
4956 11:45:21.315927 ===================================
4957 11:45:21.319617 ===================================
4958 11:45:21.322748 data_rate = 1866
4959 11:45:21.326234 CKR = 1
4960 11:45:21.329145 DQ_P2S_RATIO = 8
4961 11:45:21.332848 ===================================
4962 11:45:21.332929 CA_P2S_RATIO = 8
4963 11:45:21.336547 DQ_CA_OPEN = 0
4964 11:45:21.339349 DQ_SEMI_OPEN = 0
4965 11:45:21.342908 CA_SEMI_OPEN = 0
4966 11:45:21.346604 CA_FULL_RATE = 0
4967 11:45:21.349583 DQ_CKDIV4_EN = 1
4968 11:45:21.350000 CA_CKDIV4_EN = 1
4969 11:45:21.352932 CA_PREDIV_EN = 0
4970 11:45:21.356498 PH8_DLY = 0
4971 11:45:21.359320 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4972 11:45:21.362612 DQ_AAMCK_DIV = 4
4973 11:45:21.366263 CA_AAMCK_DIV = 4
4974 11:45:21.366711 CA_ADMCK_DIV = 4
4975 11:45:21.369675 DQ_TRACK_CA_EN = 0
4976 11:45:21.373245 CA_PICK = 933
4977 11:45:21.375928 CA_MCKIO = 933
4978 11:45:21.379303 MCKIO_SEMI = 0
4979 11:45:21.383054 PLL_FREQ = 3732
4980 11:45:21.385937 DQ_UI_PI_RATIO = 32
4981 11:45:21.389586 CA_UI_PI_RATIO = 0
4982 11:45:21.390087 ===================================
4983 11:45:21.392469 ===================================
4984 11:45:21.395997 memory_type:LPDDR4
4985 11:45:21.399054 GP_NUM : 10
4986 11:45:21.399347 SRAM_EN : 1
4987 11:45:21.402639 MD32_EN : 0
4988 11:45:21.405573 ===================================
4989 11:45:21.409089 [ANA_INIT] >>>>>>>>>>>>>>
4990 11:45:21.412471 <<<<<< [CONFIGURE PHASE]: ANA_TX
4991 11:45:21.415286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4992 11:45:21.418599 ===================================
4993 11:45:21.422141 data_rate = 1866,PCW = 0X8f00
4994 11:45:21.425204 ===================================
4995 11:45:21.429242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4996 11:45:21.432175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 11:45:21.438638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 11:45:21.442113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4999 11:45:21.445094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5000 11:45:21.448790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5001 11:45:21.452061 [ANA_INIT] flow start
5002 11:45:21.455436 [ANA_INIT] PLL >>>>>>>>
5003 11:45:21.455566 [ANA_INIT] PLL <<<<<<<<
5004 11:45:21.458263 [ANA_INIT] MIDPI >>>>>>>>
5005 11:45:21.461745 [ANA_INIT] MIDPI <<<<<<<<
5006 11:45:21.461875 [ANA_INIT] DLL >>>>>>>>
5007 11:45:21.464902 [ANA_INIT] flow end
5008 11:45:21.468401 ============ LP4 DIFF to SE enter ============
5009 11:45:21.474795 ============ LP4 DIFF to SE exit ============
5010 11:45:21.474978 [ANA_INIT] <<<<<<<<<<<<<
5011 11:45:21.478311 [Flow] Enable top DCM control >>>>>
5012 11:45:21.481669 [Flow] Enable top DCM control <<<<<
5013 11:45:21.485149 Enable DLL master slave shuffle
5014 11:45:21.491760 ==============================================================
5015 11:45:21.491876 Gating Mode config
5016 11:45:21.498395 ==============================================================
5017 11:45:21.501520 Config description:
5018 11:45:21.511261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5019 11:45:21.517719 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5020 11:45:21.521353 SELPH_MODE 0: By rank 1: By Phase
5021 11:45:21.527737 ==============================================================
5022 11:45:21.530881 GAT_TRACK_EN = 1
5023 11:45:21.530982 RX_GATING_MODE = 2
5024 11:45:21.534342 RX_GATING_TRACK_MODE = 2
5025 11:45:21.538000 SELPH_MODE = 1
5026 11:45:21.541008 PICG_EARLY_EN = 1
5027 11:45:21.544159 VALID_LAT_VALUE = 1
5028 11:45:21.551150 ==============================================================
5029 11:45:21.554106 Enter into Gating configuration >>>>
5030 11:45:21.557761 Exit from Gating configuration <<<<
5031 11:45:21.560846 Enter into DVFS_PRE_config >>>>>
5032 11:45:21.571049 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5033 11:45:21.573954 Exit from DVFS_PRE_config <<<<<
5034 11:45:21.577453 Enter into PICG configuration >>>>
5035 11:45:21.580902 Exit from PICG configuration <<<<
5036 11:45:21.583708 [RX_INPUT] configuration >>>>>
5037 11:45:21.587313 [RX_INPUT] configuration <<<<<
5038 11:45:21.590523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5039 11:45:21.596980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5040 11:45:21.603652 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 11:45:21.610263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 11:45:21.613968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 11:45:21.620710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 11:45:21.623653 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5045 11:45:21.630708 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5046 11:45:21.633596 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5047 11:45:21.637151 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5048 11:45:21.640492 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5049 11:45:21.647286 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 11:45:21.650456 ===================================
5051 11:45:21.650567 LPDDR4 DRAM CONFIGURATION
5052 11:45:21.653946 ===================================
5053 11:45:21.657357 EX_ROW_EN[0] = 0x0
5054 11:45:21.660902 EX_ROW_EN[1] = 0x0
5055 11:45:21.661035 LP4Y_EN = 0x0
5056 11:45:21.663940 WORK_FSP = 0x0
5057 11:45:21.664091 WL = 0x3
5058 11:45:21.667266 RL = 0x3
5059 11:45:21.667415 BL = 0x2
5060 11:45:21.670596 RPST = 0x0
5061 11:45:21.670767 RD_PRE = 0x0
5062 11:45:21.673873 WR_PRE = 0x1
5063 11:45:21.674135 WR_PST = 0x0
5064 11:45:21.677305 DBI_WR = 0x0
5065 11:45:21.677545 DBI_RD = 0x0
5066 11:45:21.680301 OTF = 0x1
5067 11:45:21.683917 ===================================
5068 11:45:21.686722 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5069 11:45:21.690432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5070 11:45:21.696755 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 11:45:21.700236 ===================================
5072 11:45:21.700319 LPDDR4 DRAM CONFIGURATION
5073 11:45:21.703359 ===================================
5074 11:45:21.707108 EX_ROW_EN[0] = 0x10
5075 11:45:21.710112 EX_ROW_EN[1] = 0x0
5076 11:45:21.710194 LP4Y_EN = 0x0
5077 11:45:21.713719 WORK_FSP = 0x0
5078 11:45:21.713801 WL = 0x3
5079 11:45:21.716852 RL = 0x3
5080 11:45:21.716933 BL = 0x2
5081 11:45:21.720131 RPST = 0x0
5082 11:45:21.720223 RD_PRE = 0x0
5083 11:45:21.723733 WR_PRE = 0x1
5084 11:45:21.723814 WR_PST = 0x0
5085 11:45:21.726734 DBI_WR = 0x0
5086 11:45:21.726815 DBI_RD = 0x0
5087 11:45:21.730602 OTF = 0x1
5088 11:45:21.733338 ===================================
5089 11:45:21.740028 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5090 11:45:21.743515 nWR fixed to 30
5091 11:45:21.743598 [ModeRegInit_LP4] CH0 RK0
5092 11:45:21.746486 [ModeRegInit_LP4] CH0 RK1
5093 11:45:21.750024 [ModeRegInit_LP4] CH1 RK0
5094 11:45:21.753471 [ModeRegInit_LP4] CH1 RK1
5095 11:45:21.753553 match AC timing 9
5096 11:45:21.756771 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5097 11:45:21.763195 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5098 11:45:21.766462 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5099 11:45:21.773301 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5100 11:45:21.776465 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5101 11:45:21.776549 ==
5102 11:45:21.780005 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 11:45:21.782827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 11:45:21.782910 ==
5105 11:45:21.789635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 11:45:21.796282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5107 11:45:21.799987 [CA 0] Center 38 (8~69) winsize 62
5108 11:45:21.802802 [CA 1] Center 38 (8~69) winsize 62
5109 11:45:21.806453 [CA 2] Center 35 (5~65) winsize 61
5110 11:45:21.809522 [CA 3] Center 35 (5~65) winsize 61
5111 11:45:21.813163 [CA 4] Center 34 (4~65) winsize 62
5112 11:45:21.816340 [CA 5] Center 33 (3~64) winsize 62
5113 11:45:21.816461
5114 11:45:21.819462 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5115 11:45:21.819616
5116 11:45:21.823182 [CATrainingPosCal] consider 1 rank data
5117 11:45:21.826074 u2DelayCellTimex100 = 270/100 ps
5118 11:45:21.829819 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5119 11:45:21.832825 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5120 11:45:21.836359 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5121 11:45:21.839424 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5122 11:45:21.843125 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 11:45:21.846072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5124 11:45:21.846154
5125 11:45:21.852532 CA PerBit enable=1, Macro0, CA PI delay=33
5126 11:45:21.852615
5127 11:45:21.852681 [CBTSetCACLKResult] CA Dly = 33
5128 11:45:21.856570 CS Dly: 7 (0~38)
5129 11:45:21.856987 ==
5130 11:45:21.860049 Dram Type= 6, Freq= 0, CH_0, rank 1
5131 11:45:21.863424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 11:45:21.863992 ==
5133 11:45:21.869652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 11:45:21.876460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5135 11:45:21.880046 [CA 0] Center 38 (8~69) winsize 62
5136 11:45:21.883269 [CA 1] Center 38 (8~69) winsize 62
5137 11:45:21.886109 [CA 2] Center 35 (5~66) winsize 62
5138 11:45:21.889684 [CA 3] Center 35 (5~66) winsize 62
5139 11:45:21.892923 [CA 4] Center 34 (3~65) winsize 63
5140 11:45:21.896004 [CA 5] Center 33 (3~64) winsize 62
5141 11:45:21.896475
5142 11:45:21.899508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5143 11:45:21.899925
5144 11:45:21.902728 [CATrainingPosCal] consider 2 rank data
5145 11:45:21.906408 u2DelayCellTimex100 = 270/100 ps
5146 11:45:21.909273 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5147 11:45:21.912651 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5148 11:45:21.915868 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5149 11:45:21.919652 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5150 11:45:21.922748 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5151 11:45:21.929212 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5152 11:45:21.929628
5153 11:45:21.932800 CA PerBit enable=1, Macro0, CA PI delay=33
5154 11:45:21.933382
5155 11:45:21.935880 [CBTSetCACLKResult] CA Dly = 33
5156 11:45:21.936358 CS Dly: 7 (0~38)
5157 11:45:21.936792
5158 11:45:21.939005 ----->DramcWriteLeveling(PI) begin...
5159 11:45:21.939431 ==
5160 11:45:21.942505 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 11:45:21.949331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 11:45:21.949751 ==
5163 11:45:21.952140 Write leveling (Byte 0): 32 => 32
5164 11:45:21.952478 Write leveling (Byte 1): 32 => 32
5165 11:45:21.955773 DramcWriteLeveling(PI) end<-----
5166 11:45:21.956051
5167 11:45:21.956256 ==
5168 11:45:21.958770 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 11:45:21.965310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 11:45:21.965492 ==
5171 11:45:21.969030 [Gating] SW mode calibration
5172 11:45:21.975587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5173 11:45:21.978710 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5174 11:45:21.984969 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
5175 11:45:21.988315 0 14 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
5176 11:45:21.991573 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:45:21.998241 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 11:45:22.001834 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 11:45:22.005385 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 11:45:22.011814 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:45:22.014923 0 14 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5182 11:45:22.018456 0 15 0 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
5183 11:45:22.025040 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5184 11:45:22.028262 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 11:45:22.031703 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 11:45:22.038313 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 11:45:22.041895 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 11:45:22.045074 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:45:22.051740 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:45:22.054683 1 0 0 | B1->B0 | 2929 3a3a | 1 0 | (0 0) (0 0)
5191 11:45:22.058211 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:45:22.064984 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 11:45:22.068046 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:45:22.071601 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 11:45:22.074523 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 11:45:22.081189 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:45:22.084885 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:45:22.087924 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5199 11:45:22.094556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5200 11:45:22.098262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:45:22.101063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:45:22.107871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:45:22.111167 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:45:22.114569 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:45:22.120952 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:45:22.124609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:45:22.127401 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:45:22.134497 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:45:22.137467 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:45:22.140933 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:45:22.147557 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:45:22.151029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:45:22.154161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5214 11:45:22.160802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5215 11:45:22.163708 Total UI for P1: 0, mck2ui 16
5216 11:45:22.167379 best dqsien dly found for B0: ( 1, 2, 28)
5217 11:45:22.171025 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5218 11:45:22.174017 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 11:45:22.177496 Total UI for P1: 0, mck2ui 16
5220 11:45:22.180530 best dqsien dly found for B1: ( 1, 3, 4)
5221 11:45:22.184163 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5222 11:45:22.187186 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5223 11:45:22.187385
5224 11:45:22.194210 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5225 11:45:22.197509 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5226 11:45:22.197927 [Gating] SW calibration Done
5227 11:45:22.200595 ==
5228 11:45:22.204231 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 11:45:22.207289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 11:45:22.207714 ==
5231 11:45:22.208252 RX Vref Scan: 0
5232 11:45:22.208598
5233 11:45:22.211009 RX Vref 0 -> 0, step: 1
5234 11:45:22.211429
5235 11:45:22.214119 RX Delay -80 -> 252, step: 8
5236 11:45:22.217374 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5237 11:45:22.220991 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5238 11:45:22.224323 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5239 11:45:22.230695 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5240 11:45:22.234176 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5241 11:45:22.237606 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5242 11:45:22.240577 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5243 11:45:22.244030 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5244 11:45:22.247296 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5245 11:45:22.253727 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5246 11:45:22.257106 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5247 11:45:22.260258 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5248 11:45:22.263863 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5249 11:45:22.270302 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5250 11:45:22.273731 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5251 11:45:22.277365 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5252 11:45:22.277616 ==
5253 11:45:22.280362 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 11:45:22.284018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 11:45:22.284363 ==
5256 11:45:22.286955 DQS Delay:
5257 11:45:22.287243 DQS0 = 0, DQS1 = 0
5258 11:45:22.287420 DQM Delay:
5259 11:45:22.290442 DQM0 = 95, DQM1 = 83
5260 11:45:22.290663 DQ Delay:
5261 11:45:22.293344 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5262 11:45:22.297130 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5263 11:45:22.300581 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5264 11:45:22.304067 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5265 11:45:22.304449
5266 11:45:22.304727
5267 11:45:22.304984 ==
5268 11:45:22.307135 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 11:45:22.313739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 11:45:22.314226 ==
5271 11:45:22.314556
5272 11:45:22.314861
5273 11:45:22.315240 TX Vref Scan disable
5274 11:45:22.317457 == TX Byte 0 ==
5275 11:45:22.320543 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5276 11:45:22.327555 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5277 11:45:22.328160 == TX Byte 1 ==
5278 11:45:22.330980 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5279 11:45:22.334183 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5280 11:45:22.337428 ==
5281 11:45:22.340416 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 11:45:22.344177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 11:45:22.344667 ==
5284 11:45:22.344995
5285 11:45:22.345295
5286 11:45:22.347328 TX Vref Scan disable
5287 11:45:22.347746 == TX Byte 0 ==
5288 11:45:22.354194 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5289 11:45:22.357149 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5290 11:45:22.357608 == TX Byte 1 ==
5291 11:45:22.363878 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5292 11:45:22.366959 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5293 11:45:22.367397
5294 11:45:22.367898 [DATLAT]
5295 11:45:22.370490 Freq=933, CH0 RK0
5296 11:45:22.371003
5297 11:45:22.371449 DATLAT Default: 0xd
5298 11:45:22.373830 0, 0xFFFF, sum = 0
5299 11:45:22.374271 1, 0xFFFF, sum = 0
5300 11:45:22.376832 2, 0xFFFF, sum = 0
5301 11:45:22.377303 3, 0xFFFF, sum = 0
5302 11:45:22.380499 4, 0xFFFF, sum = 0
5303 11:45:22.383843 5, 0xFFFF, sum = 0
5304 11:45:22.384440 6, 0xFFFF, sum = 0
5305 11:45:22.387178 7, 0xFFFF, sum = 0
5306 11:45:22.387612 8, 0xFFFF, sum = 0
5307 11:45:22.390219 9, 0xFFFF, sum = 0
5308 11:45:22.390786 10, 0x0, sum = 1
5309 11:45:22.393740 11, 0x0, sum = 2
5310 11:45:22.394281 12, 0x0, sum = 3
5311 11:45:22.394726 13, 0x0, sum = 4
5312 11:45:22.397230 best_step = 11
5313 11:45:22.397659
5314 11:45:22.398090 ==
5315 11:45:22.400187 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 11:45:22.403628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 11:45:22.404141 ==
5318 11:45:22.407132 RX Vref Scan: 1
5319 11:45:22.407559
5320 11:45:22.410104 RX Vref 0 -> 0, step: 1
5321 11:45:22.410533
5322 11:45:22.410963 RX Delay -69 -> 252, step: 4
5323 11:45:22.411371
5324 11:45:22.413616 Set Vref, RX VrefLevel [Byte0]: 61
5325 11:45:22.416695 [Byte1]: 53
5326 11:45:22.421113
5327 11:45:22.421539 Final RX Vref Byte 0 = 61 to rank0
5328 11:45:22.424602 Final RX Vref Byte 1 = 53 to rank0
5329 11:45:22.428313 Final RX Vref Byte 0 = 61 to rank1
5330 11:45:22.431032 Final RX Vref Byte 1 = 53 to rank1==
5331 11:45:22.434635 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 11:45:22.440985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 11:45:22.441416 ==
5334 11:45:22.441849 DQS Delay:
5335 11:45:22.444651 DQS0 = 0, DQS1 = 0
5336 11:45:22.445081 DQM Delay:
5337 11:45:22.445513 DQM0 = 95, DQM1 = 82
5338 11:45:22.447476 DQ Delay:
5339 11:45:22.450971 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5340 11:45:22.454165 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5341 11:45:22.458113 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =76
5342 11:45:22.461184 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =90
5343 11:45:22.461663
5344 11:45:22.462189
5345 11:45:22.467892 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5346 11:45:22.470842 CH0 RK0: MR19=505, MR18=1716
5347 11:45:22.477253 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5348 11:45:22.477765
5349 11:45:22.480575 ----->DramcWriteLeveling(PI) begin...
5350 11:45:22.481063 ==
5351 11:45:22.484188 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 11:45:22.487264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 11:45:22.487683 ==
5354 11:45:22.490559 Write leveling (Byte 0): 31 => 31
5355 11:45:22.494070 Write leveling (Byte 1): 30 => 30
5356 11:45:22.497505 DramcWriteLeveling(PI) end<-----
5357 11:45:22.497920
5358 11:45:22.498253 ==
5359 11:45:22.501011 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 11:45:22.504284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 11:45:22.504613 ==
5362 11:45:22.507315 [Gating] SW mode calibration
5363 11:45:22.513755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5364 11:45:22.520377 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5365 11:45:22.523791 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
5366 11:45:22.530510 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 11:45:22.533414 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 11:45:22.537095 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 11:45:22.543664 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:45:22.546771 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:45:22.550165 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5372 11:45:22.557058 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5373 11:45:22.560049 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5374 11:45:22.563590 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 11:45:22.570307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:45:22.573527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:45:22.576632 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:45:22.583419 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:45:22.586471 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:45:22.589947 0 15 28 | B1->B0 | 2929 3838 | 0 1 | (0 0) (0 0)
5381 11:45:22.596371 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5382 11:45:22.599667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:45:22.603437 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:45:22.606448 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:45:22.613192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:45:22.616225 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:45:22.619784 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:45:22.626301 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5389 11:45:22.629848 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5390 11:45:22.632853 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:45:22.639365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:45:22.643106 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:45:22.646000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:45:22.652966 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:45:22.656169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:45:22.659476 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:45:22.665922 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:45:22.669458 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:45:22.672394 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:45:22.679257 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:45:22.682739 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:45:22.686009 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:45:22.692520 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:45:22.696082 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5405 11:45:22.699047 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 11:45:22.702550 Total UI for P1: 0, mck2ui 16
5407 11:45:22.706007 best dqsien dly found for B0: ( 1, 2, 28)
5408 11:45:22.708857 Total UI for P1: 0, mck2ui 16
5409 11:45:22.712723 best dqsien dly found for B1: ( 1, 2, 30)
5410 11:45:22.715855 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5411 11:45:22.719243 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5412 11:45:22.719324
5413 11:45:22.726018 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5414 11:45:22.728845 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5415 11:45:22.728926 [Gating] SW calibration Done
5416 11:45:22.732295 ==
5417 11:45:22.735730 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 11:45:22.739242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 11:45:22.739352 ==
5420 11:45:22.739419 RX Vref Scan: 0
5421 11:45:22.739479
5422 11:45:22.742132 RX Vref 0 -> 0, step: 1
5423 11:45:22.742203
5424 11:45:22.745668 RX Delay -80 -> 252, step: 8
5425 11:45:22.749135 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5426 11:45:22.752093 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5427 11:45:22.755489 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5428 11:45:22.762574 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5429 11:45:22.765322 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5430 11:45:22.768735 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5431 11:45:22.772220 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5432 11:45:22.775235 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5433 11:45:22.782156 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5434 11:45:22.785660 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5435 11:45:22.788598 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5436 11:45:22.792152 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5437 11:45:22.795492 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5438 11:45:22.801907 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5439 11:45:22.805250 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5440 11:45:22.808872 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5441 11:45:22.808953 ==
5442 11:45:22.811858 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 11:45:22.815407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 11:45:22.815488 ==
5445 11:45:22.818355 DQS Delay:
5446 11:45:22.818435 DQS0 = 0, DQS1 = 0
5447 11:45:22.821775 DQM Delay:
5448 11:45:22.821856 DQM0 = 92, DQM1 = 82
5449 11:45:22.821920 DQ Delay:
5450 11:45:22.825359 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
5451 11:45:22.828877 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5452 11:45:22.831678 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5453 11:45:22.835658 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5454 11:45:22.835738
5455 11:45:22.835800
5456 11:45:22.835858 ==
5457 11:45:22.838956 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 11:45:22.845241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 11:45:22.845322 ==
5460 11:45:22.845385
5461 11:45:22.845443
5462 11:45:22.848129 TX Vref Scan disable
5463 11:45:22.848217 == TX Byte 0 ==
5464 11:45:22.851688 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5465 11:45:22.858310 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5466 11:45:22.858390 == TX Byte 1 ==
5467 11:45:22.861853 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5468 11:45:22.868112 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5469 11:45:22.868217 ==
5470 11:45:22.871359 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 11:45:22.874860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 11:45:22.874941 ==
5473 11:45:22.875004
5474 11:45:22.875063
5475 11:45:22.878299 TX Vref Scan disable
5476 11:45:22.881282 == TX Byte 0 ==
5477 11:45:22.884779 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5478 11:45:22.887694 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5479 11:45:22.891274 == TX Byte 1 ==
5480 11:45:22.894698 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5481 11:45:22.898229 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5482 11:45:22.898309
5483 11:45:22.901061 [DATLAT]
5484 11:45:22.901145 Freq=933, CH0 RK1
5485 11:45:22.901209
5486 11:45:22.904529 DATLAT Default: 0xb
5487 11:45:22.904609 0, 0xFFFF, sum = 0
5488 11:45:22.908035 1, 0xFFFF, sum = 0
5489 11:45:22.908117 2, 0xFFFF, sum = 0
5490 11:45:22.911250 3, 0xFFFF, sum = 0
5491 11:45:22.911332 4, 0xFFFF, sum = 0
5492 11:45:22.914484 5, 0xFFFF, sum = 0
5493 11:45:22.914566 6, 0xFFFF, sum = 0
5494 11:45:22.917551 7, 0xFFFF, sum = 0
5495 11:45:22.917633 8, 0xFFFF, sum = 0
5496 11:45:22.921084 9, 0xFFFF, sum = 0
5497 11:45:22.921166 10, 0x0, sum = 1
5498 11:45:22.924390 11, 0x0, sum = 2
5499 11:45:22.924473 12, 0x0, sum = 3
5500 11:45:22.927795 13, 0x0, sum = 4
5501 11:45:22.927877 best_step = 11
5502 11:45:22.927941
5503 11:45:22.928000 ==
5504 11:45:22.930799 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 11:45:22.937524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 11:45:22.937603 ==
5507 11:45:22.937667 RX Vref Scan: 0
5508 11:45:22.937726
5509 11:45:22.940917 RX Vref 0 -> 0, step: 1
5510 11:45:22.940989
5511 11:45:22.944428 RX Delay -77 -> 252, step: 4
5512 11:45:22.947435 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5513 11:45:22.950822 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5514 11:45:22.957225 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5515 11:45:22.960858 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5516 11:45:22.964342 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5517 11:45:22.967265 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5518 11:45:22.970638 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5519 11:45:22.974055 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5520 11:45:22.980433 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5521 11:45:22.983864 iDelay=199, Bit 9, Center 70 (-21 ~ 162) 184
5522 11:45:22.987342 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5523 11:45:22.990879 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5524 11:45:22.993827 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5525 11:45:23.000957 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5526 11:45:23.003821 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5527 11:45:23.007403 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5528 11:45:23.007489 ==
5529 11:45:23.010341 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 11:45:23.013795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 11:45:23.013900 ==
5532 11:45:23.017423 DQS Delay:
5533 11:45:23.017503 DQS0 = 0, DQS1 = 0
5534 11:45:23.020346 DQM Delay:
5535 11:45:23.020426 DQM0 = 92, DQM1 = 84
5536 11:45:23.020490 DQ Delay:
5537 11:45:23.023735 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5538 11:45:23.026900 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =102
5539 11:45:23.030569 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =76
5540 11:45:23.033540 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =92
5541 11:45:23.033621
5542 11:45:23.037065
5543 11:45:23.043802 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5544 11:45:23.047269 CH0 RK1: MR19=505, MR18=2E10
5545 11:45:23.053671 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5546 11:45:23.057137 [RxdqsGatingPostProcess] freq 933
5547 11:45:23.060051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5548 11:45:23.063499 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 11:45:23.066810 best DQS1 dly(2T, 0.5T) = (0, 11)
5550 11:45:23.070008 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 11:45:23.073342 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5552 11:45:23.076342 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 11:45:23.079705 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 11:45:23.083446 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 11:45:23.086434 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 11:45:23.089942 Pre-setting of DQS Precalculation
5557 11:45:23.092859 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5558 11:45:23.092934 ==
5559 11:45:23.096334 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 11:45:23.102949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 11:45:23.103033 ==
5562 11:45:23.106233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 11:45:23.112838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5564 11:45:23.116392 [CA 0] Center 37 (7~67) winsize 61
5565 11:45:23.119445 [CA 1] Center 37 (7~67) winsize 61
5566 11:45:23.122953 [CA 2] Center 34 (5~64) winsize 60
5567 11:45:23.126463 [CA 3] Center 34 (5~64) winsize 60
5568 11:45:23.129365 [CA 4] Center 34 (5~64) winsize 60
5569 11:45:23.132859 [CA 5] Center 34 (4~64) winsize 61
5570 11:45:23.132953
5571 11:45:23.135853 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5572 11:45:23.135959
5573 11:45:23.139277 [CATrainingPosCal] consider 1 rank data
5574 11:45:23.142635 u2DelayCellTimex100 = 270/100 ps
5575 11:45:23.146185 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5576 11:45:23.149594 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5577 11:45:23.152955 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5578 11:45:23.159430 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5579 11:45:23.163027 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5580 11:45:23.165985 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 11:45:23.166095
5582 11:45:23.169704 CA PerBit enable=1, Macro0, CA PI delay=34
5583 11:45:23.169801
5584 11:45:23.173119 [CBTSetCACLKResult] CA Dly = 34
5585 11:45:23.173215 CS Dly: 6 (0~37)
5586 11:45:23.173315 ==
5587 11:45:23.176129 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 11:45:23.182378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 11:45:23.182485 ==
5590 11:45:23.186143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5591 11:45:23.192724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5592 11:45:23.195750 [CA 0] Center 37 (8~67) winsize 60
5593 11:45:23.199281 [CA 1] Center 37 (7~68) winsize 62
5594 11:45:23.202320 [CA 2] Center 35 (6~65) winsize 60
5595 11:45:23.205923 [CA 3] Center 34 (4~64) winsize 61
5596 11:45:23.209379 [CA 4] Center 35 (5~65) winsize 61
5597 11:45:23.212328 [CA 5] Center 34 (4~64) winsize 61
5598 11:45:23.212404
5599 11:45:23.215469 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5600 11:45:23.215547
5601 11:45:23.219055 [CATrainingPosCal] consider 2 rank data
5602 11:45:23.222081 u2DelayCellTimex100 = 270/100 ps
5603 11:45:23.225848 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5604 11:45:23.232426 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5605 11:45:23.235368 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5606 11:45:23.239142 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5607 11:45:23.242137 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5608 11:45:23.245726 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5609 11:45:23.245808
5610 11:45:23.248807 CA PerBit enable=1, Macro0, CA PI delay=34
5611 11:45:23.248890
5612 11:45:23.251900 [CBTSetCACLKResult] CA Dly = 34
5613 11:45:23.255399 CS Dly: 7 (0~39)
5614 11:45:23.255481
5615 11:45:23.258852 ----->DramcWriteLeveling(PI) begin...
5616 11:45:23.258936 ==
5617 11:45:23.262100 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 11:45:23.265372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:45:23.265455 ==
5620 11:45:23.268702 Write leveling (Byte 0): 27 => 27
5621 11:45:23.272333 Write leveling (Byte 1): 29 => 29
5622 11:45:23.275503 DramcWriteLeveling(PI) end<-----
5623 11:45:23.275585
5624 11:45:23.275649 ==
5625 11:45:23.278454 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 11:45:23.282219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 11:45:23.282302 ==
5628 11:45:23.285331 [Gating] SW mode calibration
5629 11:45:23.292183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5630 11:45:23.298531 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5631 11:45:23.301878 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (0 0)
5632 11:45:23.305122 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:45:23.311983 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 11:45:23.315236 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 11:45:23.318652 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:45:23.325246 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:45:23.328588 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5638 11:45:23.332186 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5639 11:45:23.338358 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 11:45:23.341869 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:45:23.344982 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:45:23.351656 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:45:23.354710 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:45:23.358303 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:45:23.365201 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 11:45:23.368156 0 15 28 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
5647 11:45:23.371871 1 0 0 | B1->B0 | 4545 4545 | 1 0 | (0 0) (0 0)
5648 11:45:23.374705 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:45:23.381470 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:45:23.384910 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:45:23.388155 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:45:23.394826 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:45:23.397923 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5654 11:45:23.401608 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 11:45:23.408372 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5656 11:45:23.411260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:45:23.414673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:45:23.421191 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:45:23.424792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:45:23.428095 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:45:23.434823 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:45:23.437892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:45:23.441282 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:45:23.447617 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:45:23.451150 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:45:23.454761 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:45:23.461293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:45:23.464730 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:45:23.468060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:45:23.474655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 11:45:23.477700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 11:45:23.481228 Total UI for P1: 0, mck2ui 16
5673 11:45:23.484504 best dqsien dly found for B0: ( 1, 2, 28)
5674 11:45:23.488019 Total UI for P1: 0, mck2ui 16
5675 11:45:23.490992 best dqsien dly found for B1: ( 1, 2, 28)
5676 11:45:23.494458 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5677 11:45:23.497868 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5678 11:45:23.497951
5679 11:45:23.501570 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5680 11:45:23.504521 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5681 11:45:23.508164 [Gating] SW calibration Done
5682 11:45:23.508293 ==
5683 11:45:23.511121 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 11:45:23.514538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 11:45:23.514621 ==
5686 11:45:23.517548 RX Vref Scan: 0
5687 11:45:23.517629
5688 11:45:23.521174 RX Vref 0 -> 0, step: 1
5689 11:45:23.521257
5690 11:45:23.521321 RX Delay -80 -> 252, step: 8
5691 11:45:23.527699 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5692 11:45:23.531138 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5693 11:45:23.534059 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5694 11:45:23.537514 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5695 11:45:23.541247 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5696 11:45:23.547365 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5697 11:45:23.551103 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5698 11:45:23.554294 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5699 11:45:23.557296 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5700 11:45:23.560915 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5701 11:45:23.563871 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5702 11:45:23.570371 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5703 11:45:23.573910 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5704 11:45:23.577400 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5705 11:45:23.580414 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5706 11:45:23.583861 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5707 11:45:23.587349 ==
5708 11:45:23.590263 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 11:45:23.593853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 11:45:23.593935 ==
5711 11:45:23.593999 DQS Delay:
5712 11:45:23.597382 DQS0 = 0, DQS1 = 0
5713 11:45:23.597463 DQM Delay:
5714 11:45:23.600284 DQM0 = 95, DQM1 = 85
5715 11:45:23.600368 DQ Delay:
5716 11:45:23.603585 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5717 11:45:23.607046 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5718 11:45:23.610506 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5719 11:45:23.613583 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5720 11:45:23.613663
5721 11:45:23.613733
5722 11:45:23.613808 ==
5723 11:45:23.616871 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 11:45:23.620161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:45:23.620287 ==
5726 11:45:23.620351
5727 11:45:23.620409
5728 11:45:23.623563 TX Vref Scan disable
5729 11:45:23.627008 == TX Byte 0 ==
5730 11:45:23.630054 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5731 11:45:23.633682 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5732 11:45:23.636667 == TX Byte 1 ==
5733 11:45:23.640188 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5734 11:45:23.643638 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5735 11:45:23.643720 ==
5736 11:45:23.647058 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 11:45:23.653572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 11:45:23.653654 ==
5739 11:45:23.653719
5740 11:45:23.653778
5741 11:45:23.653833 TX Vref Scan disable
5742 11:45:23.657443 == TX Byte 0 ==
5743 11:45:23.660551 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5744 11:45:23.664332 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5745 11:45:23.667236 == TX Byte 1 ==
5746 11:45:23.670920 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 11:45:23.677561 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 11:45:23.677648
5749 11:45:23.677715 [DATLAT]
5750 11:45:23.677775 Freq=933, CH1 RK0
5751 11:45:23.677834
5752 11:45:23.680347 DATLAT Default: 0xd
5753 11:45:23.680426 0, 0xFFFF, sum = 0
5754 11:45:23.684061 1, 0xFFFF, sum = 0
5755 11:45:23.686936 2, 0xFFFF, sum = 0
5756 11:45:23.687019 3, 0xFFFF, sum = 0
5757 11:45:23.690465 4, 0xFFFF, sum = 0
5758 11:45:23.690548 5, 0xFFFF, sum = 0
5759 11:45:23.693729 6, 0xFFFF, sum = 0
5760 11:45:23.693813 7, 0xFFFF, sum = 0
5761 11:45:23.697322 8, 0xFFFF, sum = 0
5762 11:45:23.697406 9, 0xFFFF, sum = 0
5763 11:45:23.700376 10, 0x0, sum = 1
5764 11:45:23.700459 11, 0x0, sum = 2
5765 11:45:23.703893 12, 0x0, sum = 3
5766 11:45:23.703977 13, 0x0, sum = 4
5767 11:45:23.704042 best_step = 11
5768 11:45:23.706988
5769 11:45:23.707071 ==
5770 11:45:23.710409 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 11:45:23.713748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:45:23.713831 ==
5773 11:45:23.713897 RX Vref Scan: 1
5774 11:45:23.713979
5775 11:45:23.717191 RX Vref 0 -> 0, step: 1
5776 11:45:23.717274
5777 11:45:23.720106 RX Delay -69 -> 252, step: 4
5778 11:45:23.720190
5779 11:45:23.723428 Set Vref, RX VrefLevel [Byte0]: 60
5780 11:45:23.726873 [Byte1]: 56
5781 11:45:23.730378
5782 11:45:23.730459 Final RX Vref Byte 0 = 60 to rank0
5783 11:45:23.733758 Final RX Vref Byte 1 = 56 to rank0
5784 11:45:23.736752 Final RX Vref Byte 0 = 60 to rank1
5785 11:45:23.740380 Final RX Vref Byte 1 = 56 to rank1==
5786 11:45:23.743294 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 11:45:23.746897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 11:45:23.750397 ==
5789 11:45:23.750484 DQS Delay:
5790 11:45:23.750551 DQS0 = 0, DQS1 = 0
5791 11:45:23.753795 DQM Delay:
5792 11:45:23.753898 DQM0 = 96, DQM1 = 88
5793 11:45:23.756555 DQ Delay:
5794 11:45:23.760149 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =92
5795 11:45:23.763505 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5796 11:45:23.766766 DQ8 =78, DQ9 =82, DQ10 =88, DQ11 =82
5797 11:45:23.770220 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5798 11:45:23.770340
5799 11:45:23.770435
5800 11:45:23.776846 [DQSOSCAuto] RK0, (LSB)MR18= 0x20a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5801 11:45:23.780039 CH1 RK0: MR19=505, MR18=20A
5802 11:45:23.786561 CH1_RK0: MR19=0x505, MR18=0x20A, DQSOSC=418, MR23=63, INC=62, DEC=41
5803 11:45:23.786756
5804 11:45:23.790062 ----->DramcWriteLeveling(PI) begin...
5805 11:45:23.790335 ==
5806 11:45:23.793150 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 11:45:23.796802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 11:45:23.797107 ==
5809 11:45:23.800087 Write leveling (Byte 0): 26 => 26
5810 11:45:23.803128 Write leveling (Byte 1): 26 => 26
5811 11:45:23.806713 DramcWriteLeveling(PI) end<-----
5812 11:45:23.806981
5813 11:45:23.807174 ==
5814 11:45:23.809785 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 11:45:23.813369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 11:45:23.813612 ==
5817 11:45:23.816823 [Gating] SW mode calibration
5818 11:45:23.823233 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 11:45:23.829723 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 11:45:23.833335 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5821 11:45:23.836520 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:45:23.843150 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:45:23.846088 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:45:23.849726 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:45:23.856394 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 11:45:23.859271 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5827 11:45:23.862773 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5828 11:45:23.869398 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5829 11:45:23.872473 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:45:23.875906 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:45:23.882666 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:45:23.885942 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:45:23.889422 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5834 11:45:23.896007 0 15 24 | B1->B0 | 2525 3332 | 0 1 | (0 0) (0 0)
5835 11:45:23.898835 0 15 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5836 11:45:23.902381 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 11:45:23.908980 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:45:23.912340 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:45:23.915990 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:45:23.922340 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:45:23.925913 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:45:23.929095 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5843 11:45:23.935407 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5844 11:45:23.938790 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:45:23.942349 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:45:23.949046 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:45:23.952592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:45:23.955557 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:45:23.962552 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:45:23.965740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:45:23.968643 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:45:23.974873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:45:23.978435 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:45:23.981555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:45:23.988151 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:45:23.991653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:45:23.995279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:45:24.001490 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5859 11:45:24.004718 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5860 11:45:24.008033 Total UI for P1: 0, mck2ui 16
5861 11:45:24.011728 best dqsien dly found for B0: ( 1, 2, 24)
5862 11:45:24.014752 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 11:45:24.018378 Total UI for P1: 0, mck2ui 16
5864 11:45:24.021386 best dqsien dly found for B1: ( 1, 2, 28)
5865 11:45:24.024972 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5866 11:45:24.028477 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5867 11:45:24.028558
5868 11:45:24.031444 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5869 11:45:24.037989 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5870 11:45:24.038074 [Gating] SW calibration Done
5871 11:45:24.041457 ==
5872 11:45:24.041534 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 11:45:24.048047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 11:45:24.048174 ==
5875 11:45:24.048274 RX Vref Scan: 0
5876 11:45:24.048336
5877 11:45:24.051737 RX Vref 0 -> 0, step: 1
5878 11:45:24.051844
5879 11:45:24.054738 RX Delay -80 -> 252, step: 8
5880 11:45:24.057786 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5881 11:45:24.061192 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5882 11:45:24.064807 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5883 11:45:24.071386 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5884 11:45:24.074339 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5885 11:45:24.078057 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5886 11:45:24.081157 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5887 11:45:24.084169 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5888 11:45:24.087663 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5889 11:45:24.094144 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5890 11:45:24.097613 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5891 11:45:24.101128 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5892 11:45:24.104638 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5893 11:45:24.107661 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5894 11:45:24.114294 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5895 11:45:24.117509 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5896 11:45:24.117593 ==
5897 11:45:24.120725 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 11:45:24.124306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 11:45:24.124421 ==
5900 11:45:24.124523 DQS Delay:
5901 11:45:24.127429 DQS0 = 0, DQS1 = 0
5902 11:45:24.127511 DQM Delay:
5903 11:45:24.131116 DQM0 = 93, DQM1 = 90
5904 11:45:24.131204 DQ Delay:
5905 11:45:24.134059 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5906 11:45:24.137694 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5907 11:45:24.140664 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5908 11:45:24.144037 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5909 11:45:24.144120
5910 11:45:24.144185
5911 11:45:24.144257 ==
5912 11:45:24.147784 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 11:45:24.153983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 11:45:24.154107 ==
5915 11:45:24.154173
5916 11:45:24.154232
5917 11:45:24.154288 TX Vref Scan disable
5918 11:45:24.157495 == TX Byte 0 ==
5919 11:45:24.161085 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5920 11:45:24.164058 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5921 11:45:24.167756 == TX Byte 1 ==
5922 11:45:24.170825 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5923 11:45:24.174230 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5924 11:45:24.177291 ==
5925 11:45:24.180814 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 11:45:24.183874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 11:45:24.183956 ==
5928 11:45:24.184021
5929 11:45:24.184081
5930 11:45:24.187479 TX Vref Scan disable
5931 11:45:24.187560 == TX Byte 0 ==
5932 11:45:24.193735 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 11:45:24.197558 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 11:45:24.197640 == TX Byte 1 ==
5935 11:45:24.203715 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5936 11:45:24.207209 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5937 11:45:24.207291
5938 11:45:24.207355 [DATLAT]
5939 11:45:24.210825 Freq=933, CH1 RK1
5940 11:45:24.210907
5941 11:45:24.210971 DATLAT Default: 0xb
5942 11:45:24.213791 0, 0xFFFF, sum = 0
5943 11:45:24.213874 1, 0xFFFF, sum = 0
5944 11:45:24.217073 2, 0xFFFF, sum = 0
5945 11:45:24.217155 3, 0xFFFF, sum = 0
5946 11:45:24.220422 4, 0xFFFF, sum = 0
5947 11:45:24.220506 5, 0xFFFF, sum = 0
5948 11:45:24.223753 6, 0xFFFF, sum = 0
5949 11:45:24.227426 7, 0xFFFF, sum = 0
5950 11:45:24.227507 8, 0xFFFF, sum = 0
5951 11:45:24.230597 9, 0xFFFF, sum = 0
5952 11:45:24.230679 10, 0x0, sum = 1
5953 11:45:24.230744 11, 0x0, sum = 2
5954 11:45:24.234006 12, 0x0, sum = 3
5955 11:45:24.234089 13, 0x0, sum = 4
5956 11:45:24.236985 best_step = 11
5957 11:45:24.237068
5958 11:45:24.237132 ==
5959 11:45:24.240465 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 11:45:24.243963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 11:45:24.244044 ==
5962 11:45:24.246924 RX Vref Scan: 0
5963 11:45:24.247028
5964 11:45:24.247093 RX Vref 0 -> 0, step: 1
5965 11:45:24.250513
5966 11:45:24.250596 RX Delay -69 -> 252, step: 4
5967 11:45:24.257804 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5968 11:45:24.261013 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5969 11:45:24.264371 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5970 11:45:24.267943 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5971 11:45:24.271373 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5972 11:45:24.277634 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5973 11:45:24.281192 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5974 11:45:24.284228 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5975 11:45:24.287319 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5976 11:45:24.290786 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5977 11:45:24.294418 iDelay=203, Bit 10, Center 94 (-1 ~ 190) 192
5978 11:45:24.301377 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5979 11:45:24.304184 iDelay=203, Bit 12, Center 98 (3 ~ 194) 192
5980 11:45:24.307647 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5981 11:45:24.311157 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5982 11:45:24.314842 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5983 11:45:24.315058 ==
5984 11:45:24.317809 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 11:45:24.324506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 11:45:24.324723 ==
5987 11:45:24.324894 DQS Delay:
5988 11:45:24.325050 DQS0 = 0, DQS1 = 0
5989 11:45:24.328005 DQM Delay:
5990 11:45:24.328243 DQM0 = 92, DQM1 = 91
5991 11:45:24.331010 DQ Delay:
5992 11:45:24.334687 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =90
5993 11:45:24.337892 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =90
5994 11:45:24.341260 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =86
5995 11:45:24.344564 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96
5996 11:45:24.344776
5997 11:45:24.344943
5998 11:45:24.350990 [DQSOSCAuto] RK1, (LSB)MR18= 0x1226, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5999 11:45:24.354056 CH1 RK1: MR19=505, MR18=1226
6000 11:45:24.361194 CH1_RK1: MR19=0x505, MR18=0x1226, DQSOSC=409, MR23=63, INC=64, DEC=43
6001 11:45:24.364130 [RxdqsGatingPostProcess] freq 933
6002 11:45:24.367400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 11:45:24.370855 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 11:45:24.374089 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 11:45:24.377572 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 11:45:24.380767 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 11:45:24.383863 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 11:45:24.387385 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 11:45:24.390667 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 11:45:24.393789 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 11:45:24.397409 Pre-setting of DQS Precalculation
6012 11:45:24.400303 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 11:45:24.410469 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 11:45:24.416821 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 11:45:24.417037
6016 11:45:24.417207
6017 11:45:24.420263 [Calibration Summary] 1866 Mbps
6018 11:45:24.420478 CH 0, Rank 0
6019 11:45:24.423611 SW Impedance : PASS
6020 11:45:24.423823 DUTY Scan : NO K
6021 11:45:24.426917 ZQ Calibration : PASS
6022 11:45:24.429947 Jitter Meter : NO K
6023 11:45:24.430029 CBT Training : PASS
6024 11:45:24.433353 Write leveling : PASS
6025 11:45:24.436710 RX DQS gating : PASS
6026 11:45:24.436792 RX DQ/DQS(RDDQC) : PASS
6027 11:45:24.439716 TX DQ/DQS : PASS
6028 11:45:24.443229 RX DATLAT : PASS
6029 11:45:24.443311 RX DQ/DQS(Engine): PASS
6030 11:45:24.446408 TX OE : NO K
6031 11:45:24.446518 All Pass.
6032 11:45:24.446616
6033 11:45:24.450185 CH 0, Rank 1
6034 11:45:24.450266 SW Impedance : PASS
6035 11:45:24.453401 DUTY Scan : NO K
6036 11:45:24.456148 ZQ Calibration : PASS
6037 11:45:24.456299 Jitter Meter : NO K
6038 11:45:24.459867 CBT Training : PASS
6039 11:45:24.463235 Write leveling : PASS
6040 11:45:24.463316 RX DQS gating : PASS
6041 11:45:24.466247 RX DQ/DQS(RDDQC) : PASS
6042 11:45:24.469795 TX DQ/DQS : PASS
6043 11:45:24.469873 RX DATLAT : PASS
6044 11:45:24.473289 RX DQ/DQS(Engine): PASS
6045 11:45:24.473365 TX OE : NO K
6046 11:45:24.476238 All Pass.
6047 11:45:24.476332
6048 11:45:24.476395 CH 1, Rank 0
6049 11:45:24.479756 SW Impedance : PASS
6050 11:45:24.482632 DUTY Scan : NO K
6051 11:45:24.482711 ZQ Calibration : PASS
6052 11:45:24.486007 Jitter Meter : NO K
6053 11:45:24.486082 CBT Training : PASS
6054 11:45:24.489656 Write leveling : PASS
6055 11:45:24.492778 RX DQS gating : PASS
6056 11:45:24.492860 RX DQ/DQS(RDDQC) : PASS
6057 11:45:24.496005 TX DQ/DQS : PASS
6058 11:45:24.499290 RX DATLAT : PASS
6059 11:45:24.499372 RX DQ/DQS(Engine): PASS
6060 11:45:24.502824 TX OE : NO K
6061 11:45:24.502906 All Pass.
6062 11:45:24.502970
6063 11:45:24.506195 CH 1, Rank 1
6064 11:45:24.506290 SW Impedance : PASS
6065 11:45:24.509500 DUTY Scan : NO K
6066 11:45:24.512551 ZQ Calibration : PASS
6067 11:45:24.512660 Jitter Meter : NO K
6068 11:45:24.515791 CBT Training : PASS
6069 11:45:24.519374 Write leveling : PASS
6070 11:45:24.519482 RX DQS gating : PASS
6071 11:45:24.522860 RX DQ/DQS(RDDQC) : PASS
6072 11:45:24.525852 TX DQ/DQS : PASS
6073 11:45:24.525934 RX DATLAT : PASS
6074 11:45:24.529152 RX DQ/DQS(Engine): PASS
6075 11:45:24.532767 TX OE : NO K
6076 11:45:24.532849 All Pass.
6077 11:45:24.532914
6078 11:45:24.532973 DramC Write-DBI off
6079 11:45:24.535685 PER_BANK_REFRESH: Hybrid Mode
6080 11:45:24.539174 TX_TRACKING: ON
6081 11:45:24.545728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 11:45:24.548779 [FAST_K] Save calibration result to emmc
6083 11:45:24.555846 dramc_set_vcore_voltage set vcore to 650000
6084 11:45:24.555953 Read voltage for 400, 6
6085 11:45:24.559048 Vio18 = 0
6086 11:45:24.559131 Vcore = 650000
6087 11:45:24.559205 Vdram = 0
6088 11:45:24.562238 Vddq = 0
6089 11:45:24.562344 Vmddr = 0
6090 11:45:24.565578 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 11:45:24.572104 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 11:45:24.575891 MEM_TYPE=3, freq_sel=20
6093 11:45:24.578789 sv_algorithm_assistance_LP4_800
6094 11:45:24.582286 ============ PULL DRAM RESETB DOWN ============
6095 11:45:24.585220 ========== PULL DRAM RESETB DOWN end =========
6096 11:45:24.588688 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 11:45:24.592135 ===================================
6098 11:45:24.595512 LPDDR4 DRAM CONFIGURATION
6099 11:45:24.598946 ===================================
6100 11:45:24.602437 EX_ROW_EN[0] = 0x0
6101 11:45:24.602519 EX_ROW_EN[1] = 0x0
6102 11:45:24.605468 LP4Y_EN = 0x0
6103 11:45:24.605550 WORK_FSP = 0x0
6104 11:45:24.608795 WL = 0x2
6105 11:45:24.608876 RL = 0x2
6106 11:45:24.611902 BL = 0x2
6107 11:45:24.612056 RPST = 0x0
6108 11:45:24.615185 RD_PRE = 0x0
6109 11:45:24.615267 WR_PRE = 0x1
6110 11:45:24.618653 WR_PST = 0x0
6111 11:45:24.618734 DBI_WR = 0x0
6112 11:45:24.622100 DBI_RD = 0x0
6113 11:45:24.625406 OTF = 0x1
6114 11:45:24.628477 ===================================
6115 11:45:24.631933 ===================================
6116 11:45:24.632015 ANA top config
6117 11:45:24.635361 ===================================
6118 11:45:24.638270 DLL_ASYNC_EN = 0
6119 11:45:24.641806 ALL_SLAVE_EN = 1
6120 11:45:24.641887 NEW_RANK_MODE = 1
6121 11:45:24.645199 DLL_IDLE_MODE = 1
6122 11:45:24.648674 LP45_APHY_COMB_EN = 1
6123 11:45:24.651635 TX_ODT_DIS = 1
6124 11:45:24.651716 NEW_8X_MODE = 1
6125 11:45:24.655159 ===================================
6126 11:45:24.658186 ===================================
6127 11:45:24.661728 data_rate = 800
6128 11:45:24.664703 CKR = 1
6129 11:45:24.668193 DQ_P2S_RATIO = 4
6130 11:45:24.671479 ===================================
6131 11:45:24.674888 CA_P2S_RATIO = 4
6132 11:45:24.678318 DQ_CA_OPEN = 0
6133 11:45:24.678399 DQ_SEMI_OPEN = 1
6134 11:45:24.681427 CA_SEMI_OPEN = 1
6135 11:45:24.684879 CA_FULL_RATE = 0
6136 11:45:24.688130 DQ_CKDIV4_EN = 0
6137 11:45:24.691548 CA_CKDIV4_EN = 1
6138 11:45:24.694498 CA_PREDIV_EN = 0
6139 11:45:24.694579 PH8_DLY = 0
6140 11:45:24.697882 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 11:45:24.701330 DQ_AAMCK_DIV = 0
6142 11:45:24.704274 CA_AAMCK_DIV = 0
6143 11:45:24.707721 CA_ADMCK_DIV = 4
6144 11:45:24.711129 DQ_TRACK_CA_EN = 0
6145 11:45:24.715119 CA_PICK = 800
6146 11:45:24.715200 CA_MCKIO = 400
6147 11:45:24.717932 MCKIO_SEMI = 400
6148 11:45:24.721333 PLL_FREQ = 3016
6149 11:45:24.724138 DQ_UI_PI_RATIO = 32
6150 11:45:24.727709 CA_UI_PI_RATIO = 32
6151 11:45:24.730992 ===================================
6152 11:45:24.734454 ===================================
6153 11:45:24.737906 memory_type:LPDDR4
6154 11:45:24.737987 GP_NUM : 10
6155 11:45:24.740879 SRAM_EN : 1
6156 11:45:24.740960 MD32_EN : 0
6157 11:45:24.744355 ===================================
6158 11:45:24.747936 [ANA_INIT] >>>>>>>>>>>>>>
6159 11:45:24.750973 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 11:45:24.753997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 11:45:24.757549 ===================================
6162 11:45:24.761091 data_rate = 800,PCW = 0X7400
6163 11:45:24.764056 ===================================
6164 11:45:24.767579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 11:45:24.774313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 11:45:24.784194 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 11:45:24.787741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 11:45:24.790676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 11:45:24.794116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 11:45:24.797576 [ANA_INIT] flow start
6171 11:45:24.800392 [ANA_INIT] PLL >>>>>>>>
6172 11:45:24.800473 [ANA_INIT] PLL <<<<<<<<
6173 11:45:24.803910 [ANA_INIT] MIDPI >>>>>>>>
6174 11:45:24.807397 [ANA_INIT] MIDPI <<<<<<<<
6175 11:45:24.810802 [ANA_INIT] DLL >>>>>>>>
6176 11:45:24.810882 [ANA_INIT] flow end
6177 11:45:24.813645 ============ LP4 DIFF to SE enter ============
6178 11:45:24.820519 ============ LP4 DIFF to SE exit ============
6179 11:45:24.820600 [ANA_INIT] <<<<<<<<<<<<<
6180 11:45:24.824037 [Flow] Enable top DCM control >>>>>
6181 11:45:24.826991 [Flow] Enable top DCM control <<<<<
6182 11:45:24.830416 Enable DLL master slave shuffle
6183 11:45:24.837173 ==============================================================
6184 11:45:24.837254 Gating Mode config
6185 11:45:24.843728 ==============================================================
6186 11:45:24.847143 Config description:
6187 11:45:24.857015 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 11:45:24.863504 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 11:45:24.867058 SELPH_MODE 0: By rank 1: By Phase
6190 11:45:24.873581 ==============================================================
6191 11:45:24.876852 GAT_TRACK_EN = 0
6192 11:45:24.880390 RX_GATING_MODE = 2
6193 11:45:24.880465 RX_GATING_TRACK_MODE = 2
6194 11:45:24.883298 SELPH_MODE = 1
6195 11:45:24.886868 PICG_EARLY_EN = 1
6196 11:45:24.890192 VALID_LAT_VALUE = 1
6197 11:45:24.897016 ==============================================================
6198 11:45:24.900419 Enter into Gating configuration >>>>
6199 11:45:24.903432 Exit from Gating configuration <<<<
6200 11:45:24.906814 Enter into DVFS_PRE_config >>>>>
6201 11:45:24.916741 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 11:45:24.920089 Exit from DVFS_PRE_config <<<<<
6203 11:45:24.923556 Enter into PICG configuration >>>>
6204 11:45:24.926685 Exit from PICG configuration <<<<
6205 11:45:24.930116 [RX_INPUT] configuration >>>>>
6206 11:45:24.933659 [RX_INPUT] configuration <<<<<
6207 11:45:24.936490 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 11:45:24.943445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 11:45:24.949613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 11:45:24.953459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 11:45:24.959678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 11:45:24.966471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 11:45:24.969749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 11:45:24.976316 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 11:45:24.979769 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 11:45:24.983071 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 11:45:24.986103 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 11:45:24.993220 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 11:45:24.996224 ===================================
6220 11:45:24.996330 LPDDR4 DRAM CONFIGURATION
6221 11:45:24.999576 ===================================
6222 11:45:25.002797 EX_ROW_EN[0] = 0x0
6223 11:45:25.006162 EX_ROW_EN[1] = 0x0
6224 11:45:25.006278 LP4Y_EN = 0x0
6225 11:45:25.009529 WORK_FSP = 0x0
6226 11:45:25.009629 WL = 0x2
6227 11:45:25.012708 RL = 0x2
6228 11:45:25.012806 BL = 0x2
6229 11:45:25.016264 RPST = 0x0
6230 11:45:25.016374 RD_PRE = 0x0
6231 11:45:25.019163 WR_PRE = 0x1
6232 11:45:25.019259 WR_PST = 0x0
6233 11:45:25.022482 DBI_WR = 0x0
6234 11:45:25.022584 DBI_RD = 0x0
6235 11:45:25.025972 OTF = 0x1
6236 11:45:25.029667 ===================================
6237 11:45:25.033074 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 11:45:25.035979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 11:45:25.042453 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 11:45:25.045945 ===================================
6241 11:45:25.046028 LPDDR4 DRAM CONFIGURATION
6242 11:45:25.049003 ===================================
6243 11:45:25.052502 EX_ROW_EN[0] = 0x10
6244 11:45:25.055894 EX_ROW_EN[1] = 0x0
6245 11:45:25.055976 LP4Y_EN = 0x0
6246 11:45:25.059356 WORK_FSP = 0x0
6247 11:45:25.059438 WL = 0x2
6248 11:45:25.062350 RL = 0x2
6249 11:45:25.062431 BL = 0x2
6250 11:45:25.065880 RPST = 0x0
6251 11:45:25.065962 RD_PRE = 0x0
6252 11:45:25.069133 WR_PRE = 0x1
6253 11:45:25.069215 WR_PST = 0x0
6254 11:45:25.072227 DBI_WR = 0x0
6255 11:45:25.072321 DBI_RD = 0x0
6256 11:45:25.075793 OTF = 0x1
6257 11:45:25.079107 ===================================
6258 11:45:25.085452 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 11:45:25.088966 nWR fixed to 30
6260 11:45:25.092414 [ModeRegInit_LP4] CH0 RK0
6261 11:45:25.092496 [ModeRegInit_LP4] CH0 RK1
6262 11:45:25.095397 [ModeRegInit_LP4] CH1 RK0
6263 11:45:25.098950 [ModeRegInit_LP4] CH1 RK1
6264 11:45:25.099031 match AC timing 19
6265 11:45:25.105496 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 11:45:25.108887 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 11:45:25.112327 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 11:45:25.118758 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 11:45:25.122375 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 11:45:25.122478 ==
6271 11:45:25.125727 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 11:45:25.128936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 11:45:25.129019 ==
6274 11:45:25.135532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 11:45:25.141936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 11:45:25.145441 [CA 0] Center 36 (8~64) winsize 57
6277 11:45:25.148418 [CA 1] Center 36 (8~64) winsize 57
6278 11:45:25.148498 [CA 2] Center 36 (8~64) winsize 57
6279 11:45:25.152075 [CA 3] Center 36 (8~64) winsize 57
6280 11:45:25.155076 [CA 4] Center 36 (8~64) winsize 57
6281 11:45:25.158409 [CA 5] Center 36 (8~64) winsize 57
6282 11:45:25.158489
6283 11:45:25.161681 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 11:45:25.161763
6285 11:45:25.168766 [CATrainingPosCal] consider 1 rank data
6286 11:45:25.168848 u2DelayCellTimex100 = 270/100 ps
6287 11:45:25.175215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 11:45:25.178511 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:45:25.181745 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:45:25.185211 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:45:25.188548 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:45:25.191817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:45:25.191899
6294 11:45:25.194998 CA PerBit enable=1, Macro0, CA PI delay=36
6295 11:45:25.195079
6296 11:45:25.198588 [CBTSetCACLKResult] CA Dly = 36
6297 11:45:25.201517 CS Dly: 1 (0~32)
6298 11:45:25.201597 ==
6299 11:45:25.204941 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 11:45:25.207934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 11:45:25.208015 ==
6302 11:45:25.214917 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 11:45:25.218359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6304 11:45:25.221224 [CA 0] Center 36 (8~64) winsize 57
6305 11:45:25.224805 [CA 1] Center 36 (8~64) winsize 57
6306 11:45:25.228142 [CA 2] Center 36 (8~64) winsize 57
6307 11:45:25.231249 [CA 3] Center 36 (8~64) winsize 57
6308 11:45:25.234646 [CA 4] Center 36 (8~64) winsize 57
6309 11:45:25.238398 [CA 5] Center 36 (8~64) winsize 57
6310 11:45:25.238482
6311 11:45:25.241268 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6312 11:45:25.241350
6313 11:45:25.244622 [CATrainingPosCal] consider 2 rank data
6314 11:45:25.248157 u2DelayCellTimex100 = 270/100 ps
6315 11:45:25.251729 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:45:25.254680 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:45:25.258233 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:45:25.264780 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:45:25.268099 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:45:25.271077 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:45:25.271177
6322 11:45:25.274667 CA PerBit enable=1, Macro0, CA PI delay=36
6323 11:45:25.274748
6324 11:45:25.278140 [CBTSetCACLKResult] CA Dly = 36
6325 11:45:25.278235 CS Dly: 1 (0~32)
6326 11:45:25.278303
6327 11:45:25.281102 ----->DramcWriteLeveling(PI) begin...
6328 11:45:25.281184 ==
6329 11:45:25.284598 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:45:25.291202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:45:25.291304 ==
6332 11:45:25.294205 Write leveling (Byte 0): 40 => 8
6333 11:45:25.298120 Write leveling (Byte 1): 40 => 8
6334 11:45:25.298203 DramcWriteLeveling(PI) end<-----
6335 11:45:25.298266
6336 11:45:25.301348 ==
6337 11:45:25.304780 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 11:45:25.307893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:45:25.307979 ==
6340 11:45:25.310891 [Gating] SW mode calibration
6341 11:45:25.317456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 11:45:25.321002 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 11:45:25.327981 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 11:45:25.330904 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 11:45:25.334494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 11:45:25.341038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 11:45:25.344227 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 11:45:25.347833 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 11:45:25.354272 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 11:45:25.357702 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:45:25.361207 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 11:45:25.364735 Total UI for P1: 0, mck2ui 16
6353 11:45:25.367624 best dqsien dly found for B0: ( 0, 14, 24)
6354 11:45:25.370969 Total UI for P1: 0, mck2ui 16
6355 11:45:25.374402 best dqsien dly found for B1: ( 0, 14, 24)
6356 11:45:25.377920 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 11:45:25.380867 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 11:45:25.380948
6359 11:45:25.387903 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 11:45:25.390779 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 11:45:25.390861 [Gating] SW calibration Done
6362 11:45:25.394357 ==
6363 11:45:25.394438 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 11:45:25.401112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 11:45:25.401194 ==
6366 11:45:25.401258 RX Vref Scan: 0
6367 11:45:25.401318
6368 11:45:25.404154 RX Vref 0 -> 0, step: 1
6369 11:45:25.404274
6370 11:45:25.407743 RX Delay -410 -> 252, step: 16
6371 11:45:25.411030 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6372 11:45:25.414172 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6373 11:45:25.420749 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6374 11:45:25.424308 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6375 11:45:25.427220 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6376 11:45:25.430582 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6377 11:45:25.437528 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6378 11:45:25.440414 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6379 11:45:25.443794 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6380 11:45:25.447218 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6381 11:45:25.454014 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6382 11:45:25.457293 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6383 11:45:25.460487 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6384 11:45:25.467258 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6385 11:45:25.470252 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6386 11:45:25.473804 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6387 11:45:25.473886 ==
6388 11:45:25.477209 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 11:45:25.480280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 11:45:25.483769 ==
6391 11:45:25.483844 DQS Delay:
6392 11:45:25.483935 DQS0 = 59, DQS1 = 59
6393 11:45:25.486871 DQM Delay:
6394 11:45:25.486966 DQM0 = 18, DQM1 = 10
6395 11:45:25.490268 DQ Delay:
6396 11:45:25.493802 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6397 11:45:25.493896 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6398 11:45:25.496667 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6399 11:45:25.499725 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6400 11:45:25.499795
6401 11:45:25.503211
6402 11:45:25.503304 ==
6403 11:45:25.506790 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:45:25.510099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:45:25.510197 ==
6406 11:45:25.510285
6407 11:45:25.510368
6408 11:45:25.513273 TX Vref Scan disable
6409 11:45:25.513342 == TX Byte 0 ==
6410 11:45:25.516903 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 11:45:25.523046 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 11:45:25.523122 == TX Byte 1 ==
6413 11:45:25.526698 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 11:45:25.533230 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 11:45:25.533310 ==
6416 11:45:25.536464 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 11:45:25.539839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 11:45:25.539920 ==
6419 11:45:25.539982
6420 11:45:25.540039
6421 11:45:25.543345 TX Vref Scan disable
6422 11:45:25.543424 == TX Byte 0 ==
6423 11:45:25.546275 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 11:45:25.553170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 11:45:25.553251 == TX Byte 1 ==
6426 11:45:25.556135 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 11:45:25.562654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 11:45:25.562735
6429 11:45:25.562797 [DATLAT]
6430 11:45:25.566060 Freq=400, CH0 RK0
6431 11:45:25.566141
6432 11:45:25.566204 DATLAT Default: 0xf
6433 11:45:25.569335 0, 0xFFFF, sum = 0
6434 11:45:25.569417 1, 0xFFFF, sum = 0
6435 11:45:25.573108 2, 0xFFFF, sum = 0
6436 11:45:25.573215 3, 0xFFFF, sum = 0
6437 11:45:25.576102 4, 0xFFFF, sum = 0
6438 11:45:25.576219 5, 0xFFFF, sum = 0
6439 11:45:25.579495 6, 0xFFFF, sum = 0
6440 11:45:25.579576 7, 0xFFFF, sum = 0
6441 11:45:25.583024 8, 0xFFFF, sum = 0
6442 11:45:25.583108 9, 0xFFFF, sum = 0
6443 11:45:25.585911 10, 0xFFFF, sum = 0
6444 11:45:25.585993 11, 0xFFFF, sum = 0
6445 11:45:25.589470 12, 0xFFFF, sum = 0
6446 11:45:25.589550 13, 0x0, sum = 1
6447 11:45:25.593112 14, 0x0, sum = 2
6448 11:45:25.593193 15, 0x0, sum = 3
6449 11:45:25.596028 16, 0x0, sum = 4
6450 11:45:25.596109 best_step = 14
6451 11:45:25.596171
6452 11:45:25.596259 ==
6453 11:45:25.599603 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 11:45:25.606049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 11:45:25.606134 ==
6456 11:45:25.606204 RX Vref Scan: 1
6457 11:45:25.606263
6458 11:45:25.609040 RX Vref 0 -> 0, step: 1
6459 11:45:25.609147
6460 11:45:25.612462 RX Delay -359 -> 252, step: 8
6461 11:45:25.612569
6462 11:45:25.616029 Set Vref, RX VrefLevel [Byte0]: 61
6463 11:45:25.618901 [Byte1]: 53
6464 11:45:25.622310
6465 11:45:25.622388 Final RX Vref Byte 0 = 61 to rank0
6466 11:45:25.625703 Final RX Vref Byte 1 = 53 to rank0
6467 11:45:25.628845 Final RX Vref Byte 0 = 61 to rank1
6468 11:45:25.632459 Final RX Vref Byte 1 = 53 to rank1==
6469 11:45:25.635769 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 11:45:25.642160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 11:45:25.642240 ==
6472 11:45:25.642302 DQS Delay:
6473 11:45:25.645294 DQS0 = 60, DQS1 = 68
6474 11:45:25.645388 DQM Delay:
6475 11:45:25.645451 DQM0 = 14, DQM1 = 14
6476 11:45:25.648711 DQ Delay:
6477 11:45:25.652044 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6478 11:45:25.655288 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6479 11:45:25.655384 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6480 11:45:25.658814 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6481 11:45:25.662330
6482 11:45:25.662410
6483 11:45:25.668755 [DQSOSCAuto] RK0, (LSB)MR18= 0x817f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6484 11:45:25.672124 CH0 RK0: MR19=C0C, MR18=817F
6485 11:45:25.678813 CH0_RK0: MR19=0xC0C, MR18=0x817F, DQSOSC=393, MR23=63, INC=382, DEC=254
6486 11:45:25.678896 ==
6487 11:45:25.681854 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 11:45:25.685036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 11:45:25.685122 ==
6490 11:45:25.688648 [Gating] SW mode calibration
6491 11:45:25.695260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 11:45:25.701844 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 11:45:25.705019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 11:45:25.708483 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 11:45:25.715012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 11:45:25.718515 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 11:45:25.721546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 11:45:25.728131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 11:45:25.731485 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 11:45:25.734802 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:45:25.741363 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 11:45:25.741459 Total UI for P1: 0, mck2ui 16
6503 11:45:25.748288 best dqsien dly found for B0: ( 0, 14, 24)
6504 11:45:25.748400 Total UI for P1: 0, mck2ui 16
6505 11:45:25.754456 best dqsien dly found for B1: ( 0, 14, 24)
6506 11:45:25.758090 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 11:45:25.761698 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 11:45:25.761795
6509 11:45:25.764828 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 11:45:25.767827 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 11:45:25.771241 [Gating] SW calibration Done
6512 11:45:25.771325 ==
6513 11:45:25.774718 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 11:45:25.778256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 11:45:25.778339 ==
6516 11:45:25.781171 RX Vref Scan: 0
6517 11:45:25.781252
6518 11:45:25.781315 RX Vref 0 -> 0, step: 1
6519 11:45:25.781375
6520 11:45:25.784563 RX Delay -410 -> 252, step: 16
6521 11:45:25.791118 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6522 11:45:25.794219 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 11:45:25.797588 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 11:45:25.801132 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 11:45:25.807652 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 11:45:25.811219 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6527 11:45:25.814048 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6528 11:45:25.817612 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6529 11:45:25.824194 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 11:45:25.827691 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 11:45:25.830642 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 11:45:25.834161 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6533 11:45:25.840986 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6534 11:45:25.844278 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6535 11:45:25.847309 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 11:45:25.854205 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6537 11:45:25.854288 ==
6538 11:45:25.857106 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 11:45:25.860649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 11:45:25.860732 ==
6541 11:45:25.860797 DQS Delay:
6542 11:45:25.863522 DQS0 = 59, DQS1 = 59
6543 11:45:25.863604 DQM Delay:
6544 11:45:25.867064 DQM0 = 16, DQM1 = 10
6545 11:45:25.867146 DQ Delay:
6546 11:45:25.870447 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6547 11:45:25.873747 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6548 11:45:25.877275 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6549 11:45:25.880195 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6550 11:45:25.880342
6551 11:45:25.880439
6552 11:45:25.880532 ==
6553 11:45:25.883626 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:45:25.886959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:45:25.887064 ==
6556 11:45:25.887157
6557 11:45:25.887244
6558 11:45:25.890155 TX Vref Scan disable
6559 11:45:25.893195 == TX Byte 0 ==
6560 11:45:25.896762 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 11:45:25.899981 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 11:45:25.903160 == TX Byte 1 ==
6563 11:45:25.906576 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6564 11:45:25.910142 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6565 11:45:25.910248 ==
6566 11:45:25.913093 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 11:45:25.916533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 11:45:25.916614 ==
6569 11:45:25.916677
6570 11:45:25.920138
6571 11:45:25.920280 TX Vref Scan disable
6572 11:45:25.923136 == TX Byte 0 ==
6573 11:45:25.926641 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6574 11:45:25.929568 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6575 11:45:25.933045 == TX Byte 1 ==
6576 11:45:25.936524 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6577 11:45:25.940066 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6578 11:45:25.940149
6579 11:45:25.940297 [DATLAT]
6580 11:45:25.943532 Freq=400, CH0 RK1
6581 11:45:25.943613
6582 11:45:25.943689 DATLAT Default: 0xe
6583 11:45:25.946336 0, 0xFFFF, sum = 0
6584 11:45:25.949811 1, 0xFFFF, sum = 0
6585 11:45:25.949893 2, 0xFFFF, sum = 0
6586 11:45:25.953058 3, 0xFFFF, sum = 0
6587 11:45:25.953139 4, 0xFFFF, sum = 0
6588 11:45:25.956523 5, 0xFFFF, sum = 0
6589 11:45:25.956608 6, 0xFFFF, sum = 0
6590 11:45:25.959664 7, 0xFFFF, sum = 0
6591 11:45:25.959747 8, 0xFFFF, sum = 0
6592 11:45:25.963209 9, 0xFFFF, sum = 0
6593 11:45:25.963292 10, 0xFFFF, sum = 0
6594 11:45:25.966642 11, 0xFFFF, sum = 0
6595 11:45:25.966724 12, 0xFFFF, sum = 0
6596 11:45:25.969677 13, 0x0, sum = 1
6597 11:45:25.969762 14, 0x0, sum = 2
6598 11:45:25.973096 15, 0x0, sum = 3
6599 11:45:25.973181 16, 0x0, sum = 4
6600 11:45:25.976525 best_step = 14
6601 11:45:25.976605
6602 11:45:25.976669 ==
6603 11:45:25.979443 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 11:45:25.982965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 11:45:25.983048 ==
6606 11:45:25.986282 RX Vref Scan: 0
6607 11:45:25.986387
6608 11:45:25.986478 RX Vref 0 -> 0, step: 1
6609 11:45:25.986565
6610 11:45:25.989296 RX Delay -359 -> 252, step: 8
6611 11:45:25.996933 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6612 11:45:26.000445 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6613 11:45:26.003854 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6614 11:45:26.010600 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6615 11:45:26.013672 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6616 11:45:26.017076 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6617 11:45:26.020482 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6618 11:45:26.023395 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6619 11:45:26.030446 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6620 11:45:26.033430 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6621 11:45:26.037031 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6622 11:45:26.043442 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6623 11:45:26.046892 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6624 11:45:26.050213 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6625 11:45:26.053152 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6626 11:45:26.059973 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6627 11:45:26.060059 ==
6628 11:45:26.063266 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 11:45:26.066897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 11:45:26.066979 ==
6631 11:45:26.067043 DQS Delay:
6632 11:45:26.069866 DQS0 = 60, DQS1 = 72
6633 11:45:26.069946 DQM Delay:
6634 11:45:26.073420 DQM0 = 11, DQM1 = 17
6635 11:45:26.073501 DQ Delay:
6636 11:45:26.076851 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6637 11:45:26.079877 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6638 11:45:26.083416 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6639 11:45:26.086430 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6640 11:45:26.086511
6641 11:45:26.086574
6642 11:45:26.093184 [DQSOSCAuto] RK1, (LSB)MR18= 0xc97d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 384 ps
6643 11:45:26.096721 CH0 RK1: MR19=C0C, MR18=C97D
6644 11:45:26.103178 CH0_RK1: MR19=0xC0C, MR18=0xC97D, DQSOSC=384, MR23=63, INC=400, DEC=267
6645 11:45:26.106769 [RxdqsGatingPostProcess] freq 400
6646 11:45:26.113328 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 11:45:26.116482 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 11:45:26.116556 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 11:45:26.119616 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 11:45:26.123200 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 11:45:26.126118 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 11:45:26.129675 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 11:45:26.132643 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 11:45:26.135956 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 11:45:26.139687 Pre-setting of DQS Precalculation
6656 11:45:26.146445 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 11:45:26.146527 ==
6658 11:45:26.149348 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 11:45:26.152859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 11:45:26.152941 ==
6661 11:45:26.159267 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 11:45:26.162756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 11:45:26.165751 [CA 0] Center 36 (8~64) winsize 57
6664 11:45:26.169071 [CA 1] Center 36 (8~64) winsize 57
6665 11:45:26.172714 [CA 2] Center 36 (8~64) winsize 57
6666 11:45:26.175840 [CA 3] Center 36 (8~64) winsize 57
6667 11:45:26.179436 [CA 4] Center 36 (8~64) winsize 57
6668 11:45:26.182303 [CA 5] Center 36 (8~64) winsize 57
6669 11:45:26.182385
6670 11:45:26.185915 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 11:45:26.186003
6672 11:45:26.188920 [CATrainingPosCal] consider 1 rank data
6673 11:45:26.192478 u2DelayCellTimex100 = 270/100 ps
6674 11:45:26.195886 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 11:45:26.198798 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:45:26.205799 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:45:26.208785 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:45:26.212173 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:45:26.215764 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:45:26.215844
6681 11:45:26.218750 CA PerBit enable=1, Macro0, CA PI delay=36
6682 11:45:26.218831
6683 11:45:26.222336 [CBTSetCACLKResult] CA Dly = 36
6684 11:45:26.222417 CS Dly: 1 (0~32)
6685 11:45:26.225268 ==
6686 11:45:26.228766 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 11:45:26.232350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 11:45:26.232432 ==
6689 11:45:26.235453 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 11:45:26.241849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6691 11:45:26.245092 [CA 0] Center 36 (8~64) winsize 57
6692 11:45:26.248609 [CA 1] Center 36 (8~64) winsize 57
6693 11:45:26.251626 [CA 2] Center 36 (8~64) winsize 57
6694 11:45:26.254971 [CA 3] Center 36 (8~64) winsize 57
6695 11:45:26.258601 [CA 4] Center 36 (8~64) winsize 57
6696 11:45:26.261689 [CA 5] Center 36 (8~64) winsize 57
6697 11:45:26.261770
6698 11:45:26.265297 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6699 11:45:26.265380
6700 11:45:26.268654 [CATrainingPosCal] consider 2 rank data
6701 11:45:26.271605 u2DelayCellTimex100 = 270/100 ps
6702 11:45:26.275227 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:45:26.278613 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:45:26.281877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:45:26.284829 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:45:26.291389 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:45:26.294949 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:45:26.295031
6709 11:45:26.298381 CA PerBit enable=1, Macro0, CA PI delay=36
6710 11:45:26.298463
6711 11:45:26.301834 [CBTSetCACLKResult] CA Dly = 36
6712 11:45:26.301915 CS Dly: 1 (0~32)
6713 11:45:26.301979
6714 11:45:26.304760 ----->DramcWriteLeveling(PI) begin...
6715 11:45:26.304842 ==
6716 11:45:26.308196 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:45:26.314760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:45:26.314842 ==
6719 11:45:26.318288 Write leveling (Byte 0): 40 => 8
6720 11:45:26.321162 Write leveling (Byte 1): 40 => 8
6721 11:45:26.321248 DramcWriteLeveling(PI) end<-----
6722 11:45:26.321329
6723 11:45:26.324727 ==
6724 11:45:26.328251 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 11:45:26.331159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:45:26.331241 ==
6727 11:45:26.334737 [Gating] SW mode calibration
6728 11:45:26.341035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 11:45:26.344398 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 11:45:26.351484 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 11:45:26.354394 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 11:45:26.357805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 11:45:26.364500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 11:45:26.367781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 11:45:26.371262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 11:45:26.377716 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 11:45:26.381329 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:45:26.384531 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 11:45:26.387735 Total UI for P1: 0, mck2ui 16
6740 11:45:26.391033 best dqsien dly found for B0: ( 0, 14, 24)
6741 11:45:26.394585 Total UI for P1: 0, mck2ui 16
6742 11:45:26.397561 best dqsien dly found for B1: ( 0, 14, 24)
6743 11:45:26.401334 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 11:45:26.404767 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 11:45:26.405230
6746 11:45:26.411522 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 11:45:26.414558 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 11:45:26.415041 [Gating] SW calibration Done
6749 11:45:26.417942 ==
6750 11:45:26.421032 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 11:45:26.424476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 11:45:26.424939 ==
6753 11:45:26.425306 RX Vref Scan: 0
6754 11:45:26.425641
6755 11:45:26.427943 RX Vref 0 -> 0, step: 1
6756 11:45:26.428614
6757 11:45:26.431037 RX Delay -410 -> 252, step: 16
6758 11:45:26.434667 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6759 11:45:26.438187 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6760 11:45:26.444894 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6761 11:45:26.447756 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6762 11:45:26.451468 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6763 11:45:26.454842 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6764 11:45:26.461232 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6765 11:45:26.464801 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6766 11:45:26.467654 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6767 11:45:26.470935 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6768 11:45:26.477793 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6769 11:45:26.481353 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6770 11:45:26.484710 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6771 11:45:26.491106 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6772 11:45:26.494309 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6773 11:45:26.497652 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6774 11:45:26.498145 ==
6775 11:45:26.500667 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 11:45:26.504338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 11:45:26.505004 ==
6778 11:45:26.507575 DQS Delay:
6779 11:45:26.507996 DQS0 = 51, DQS1 = 67
6780 11:45:26.511012 DQM Delay:
6781 11:45:26.511491 DQM0 = 13, DQM1 = 20
6782 11:45:26.514366 DQ Delay:
6783 11:45:26.514889 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6784 11:45:26.517746 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6785 11:45:26.520721 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6786 11:45:26.524140 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6787 11:45:26.524605
6788 11:45:26.524938
6789 11:45:26.525249 ==
6790 11:45:26.527662 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:45:26.534155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:45:26.534752 ==
6793 11:45:26.535311
6794 11:45:26.535704
6795 11:45:26.536105 TX Vref Scan disable
6796 11:45:26.537600 == TX Byte 0 ==
6797 11:45:26.540615 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 11:45:26.544119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 11:45:26.547698 == TX Byte 1 ==
6800 11:45:26.550639 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 11:45:26.554036 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 11:45:26.557331 ==
6803 11:45:26.560789 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 11:45:26.564023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 11:45:26.564582 ==
6806 11:45:26.564922
6807 11:45:26.565230
6808 11:45:26.567487 TX Vref Scan disable
6809 11:45:26.567908 == TX Byte 0 ==
6810 11:45:26.570405 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 11:45:26.576863 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 11:45:26.577288 == TX Byte 1 ==
6813 11:45:26.580178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 11:45:26.587151 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 11:45:26.587831
6816 11:45:26.588399 [DATLAT]
6817 11:45:26.588734 Freq=400, CH1 RK0
6818 11:45:26.589046
6819 11:45:26.589991 DATLAT Default: 0xf
6820 11:45:26.590542 0, 0xFFFF, sum = 0
6821 11:45:26.593886 1, 0xFFFF, sum = 0
6822 11:45:26.596744 2, 0xFFFF, sum = 0
6823 11:45:26.597169 3, 0xFFFF, sum = 0
6824 11:45:26.600243 4, 0xFFFF, sum = 0
6825 11:45:26.600671 5, 0xFFFF, sum = 0
6826 11:45:26.603669 6, 0xFFFF, sum = 0
6827 11:45:26.604093 7, 0xFFFF, sum = 0
6828 11:45:26.606540 8, 0xFFFF, sum = 0
6829 11:45:26.606963 9, 0xFFFF, sum = 0
6830 11:45:26.610411 10, 0xFFFF, sum = 0
6831 11:45:26.610834 11, 0xFFFF, sum = 0
6832 11:45:26.613652 12, 0xFFFF, sum = 0
6833 11:45:26.614095 13, 0x0, sum = 1
6834 11:45:26.616668 14, 0x0, sum = 2
6835 11:45:26.617095 15, 0x0, sum = 3
6836 11:45:26.620047 16, 0x0, sum = 4
6837 11:45:26.620555 best_step = 14
6838 11:45:26.620885
6839 11:45:26.621191 ==
6840 11:45:26.623348 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 11:45:26.626558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 11:45:26.629996 ==
6843 11:45:26.630412 RX Vref Scan: 1
6844 11:45:26.630760
6845 11:45:26.633397 RX Vref 0 -> 0, step: 1
6846 11:45:26.633812
6847 11:45:26.636958 RX Delay -375 -> 252, step: 8
6848 11:45:26.637501
6849 11:45:26.639927 Set Vref, RX VrefLevel [Byte0]: 60
6850 11:45:26.643385 [Byte1]: 56
6851 11:45:26.643853
6852 11:45:26.646966 Final RX Vref Byte 0 = 60 to rank0
6853 11:45:26.650011 Final RX Vref Byte 1 = 56 to rank0
6854 11:45:26.653465 Final RX Vref Byte 0 = 60 to rank1
6855 11:45:26.656350 Final RX Vref Byte 1 = 56 to rank1==
6856 11:45:26.659723 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 11:45:26.663235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 11:45:26.663680 ==
6859 11:45:26.666110 DQS Delay:
6860 11:45:26.666618 DQS0 = 56, DQS1 = 64
6861 11:45:26.669563 DQM Delay:
6862 11:45:26.670083 DQM0 = 12, DQM1 = 9
6863 11:45:26.673013 DQ Delay:
6864 11:45:26.673442 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6865 11:45:26.676337 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6866 11:45:26.679304 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6867 11:45:26.682897 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6868 11:45:26.683436
6869 11:45:26.683769
6870 11:45:26.692815 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6871 11:45:26.695943 CH1 RK0: MR19=C0C, MR18=5C6F
6872 11:45:26.699268 CH1_RK0: MR19=0xC0C, MR18=0x5C6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6873 11:45:26.702654 ==
6874 11:45:26.706171 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 11:45:26.709807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 11:45:26.710226 ==
6877 11:45:26.712604 [Gating] SW mode calibration
6878 11:45:26.719139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 11:45:26.722357 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 11:45:26.729436 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 11:45:26.732780 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 11:45:26.736014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 11:45:26.742416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 11:45:26.745704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 11:45:26.749492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 11:45:26.755892 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 11:45:26.758899 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:45:26.762350 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 11:45:26.765689 Total UI for P1: 0, mck2ui 16
6890 11:45:26.769205 best dqsien dly found for B0: ( 0, 14, 24)
6891 11:45:26.772723 Total UI for P1: 0, mck2ui 16
6892 11:45:26.775699 best dqsien dly found for B1: ( 0, 14, 24)
6893 11:45:26.779208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 11:45:26.782592 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 11:45:26.783007
6896 11:45:26.789153 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 11:45:26.792679 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 11:45:26.793096 [Gating] SW calibration Done
6899 11:45:26.796120 ==
6900 11:45:26.799198 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 11:45:26.802414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 11:45:26.802886 ==
6903 11:45:26.803276 RX Vref Scan: 0
6904 11:45:26.803616
6905 11:45:26.805671 RX Vref 0 -> 0, step: 1
6906 11:45:26.806131
6907 11:45:26.809212 RX Delay -410 -> 252, step: 16
6908 11:45:26.812177 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6909 11:45:26.815549 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6910 11:45:26.822072 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6911 11:45:26.825577 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6912 11:45:26.829138 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6913 11:45:26.831649 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6914 11:45:26.838583 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6915 11:45:26.841612 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6916 11:45:26.845164 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6917 11:45:26.848469 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6918 11:45:26.854631 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6919 11:45:26.858214 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6920 11:45:26.861709 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6921 11:45:26.868618 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6922 11:45:26.871502 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6923 11:45:26.875011 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6924 11:45:26.875093 ==
6925 11:45:26.878043 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 11:45:26.881556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 11:45:26.885102 ==
6928 11:45:26.885183 DQS Delay:
6929 11:45:26.885248 DQS0 = 59, DQS1 = 67
6930 11:45:26.888434 DQM Delay:
6931 11:45:26.888515 DQM0 = 19, DQM1 = 21
6932 11:45:26.892021 DQ Delay:
6933 11:45:26.892107 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6934 11:45:26.894832 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6935 11:45:26.897929 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6936 11:45:26.901467 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6937 11:45:26.901568
6938 11:45:26.901647
6939 11:45:26.904891 ==
6940 11:45:26.908294 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:45:26.911398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:45:26.911519 ==
6943 11:45:26.911615
6944 11:45:26.911703
6945 11:45:26.914752 TX Vref Scan disable
6946 11:45:26.914873 == TX Byte 0 ==
6947 11:45:26.918362 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 11:45:26.924668 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 11:45:26.924750 == TX Byte 1 ==
6950 11:45:26.927848 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6951 11:45:26.934643 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6952 11:45:26.934724 ==
6953 11:45:26.938114 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 11:45:26.941143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 11:45:26.941235 ==
6956 11:45:26.941300
6957 11:45:26.941358
6958 11:45:26.944725 TX Vref Scan disable
6959 11:45:26.944807 == TX Byte 0 ==
6960 11:45:26.947614 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6961 11:45:26.954184 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6962 11:45:26.954265 == TX Byte 1 ==
6963 11:45:26.957791 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6964 11:45:26.964179 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6965 11:45:26.964301
6966 11:45:26.964366 [DATLAT]
6967 11:45:26.964427 Freq=400, CH1 RK1
6968 11:45:26.964485
6969 11:45:26.967431 DATLAT Default: 0xe
6970 11:45:26.971146 0, 0xFFFF, sum = 0
6971 11:45:26.971228 1, 0xFFFF, sum = 0
6972 11:45:26.974301 2, 0xFFFF, sum = 0
6973 11:45:26.974383 3, 0xFFFF, sum = 0
6974 11:45:26.977360 4, 0xFFFF, sum = 0
6975 11:45:26.977441 5, 0xFFFF, sum = 0
6976 11:45:26.980678 6, 0xFFFF, sum = 0
6977 11:45:26.980759 7, 0xFFFF, sum = 0
6978 11:45:26.984042 8, 0xFFFF, sum = 0
6979 11:45:26.984124 9, 0xFFFF, sum = 0
6980 11:45:26.987371 10, 0xFFFF, sum = 0
6981 11:45:26.987454 11, 0xFFFF, sum = 0
6982 11:45:26.990922 12, 0xFFFF, sum = 0
6983 11:45:26.991004 13, 0x0, sum = 1
6984 11:45:26.993909 14, 0x0, sum = 2
6985 11:45:26.993991 15, 0x0, sum = 3
6986 11:45:26.997181 16, 0x0, sum = 4
6987 11:45:26.997263 best_step = 14
6988 11:45:26.997326
6989 11:45:26.997385 ==
6990 11:45:27.000695 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 11:45:27.004422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 11:45:27.007348 ==
6993 11:45:27.007428 RX Vref Scan: 0
6994 11:45:27.007491
6995 11:45:27.010684 RX Vref 0 -> 0, step: 1
6996 11:45:27.010764
6997 11:45:27.014270 RX Delay -375 -> 252, step: 8
6998 11:45:27.020655 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6999 11:45:27.023999 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7000 11:45:27.027458 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7001 11:45:27.031000 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7002 11:45:27.037599 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7003 11:45:27.040478 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7004 11:45:27.043961 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7005 11:45:27.047461 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
7006 11:45:27.050959 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7007 11:45:27.057653 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7008 11:45:27.060588 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7009 11:45:27.064095 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7010 11:45:27.070492 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7011 11:45:27.074035 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7012 11:45:27.077656 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7013 11:45:27.080899 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7014 11:45:27.080980 ==
7015 11:45:27.084157 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 11:45:27.090783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 11:45:27.090865 ==
7018 11:45:27.090928 DQS Delay:
7019 11:45:27.094194 DQS0 = 60, DQS1 = 64
7020 11:45:27.094274 DQM Delay:
7021 11:45:27.097368 DQM0 = 13, DQM1 = 10
7022 11:45:27.097449 DQ Delay:
7023 11:45:27.100790 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7024 11:45:27.103649 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7025 11:45:27.106959 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7026 11:45:27.110549 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7027 11:45:27.110631
7028 11:45:27.110700
7029 11:45:27.117255 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7030 11:45:27.120771 CH1 RK1: MR19=C0C, MR18=7DAD
7031 11:45:27.127217 CH1_RK1: MR19=0xC0C, MR18=0x7DAD, DQSOSC=388, MR23=63, INC=392, DEC=261
7032 11:45:27.130390 [RxdqsGatingPostProcess] freq 400
7033 11:45:27.133659 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 11:45:27.137114 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 11:45:27.140130 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 11:45:27.143738 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 11:45:27.146833 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 11:45:27.150170 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 11:45:27.153497 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 11:45:27.156580 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 11:45:27.160169 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 11:45:27.163099 Pre-setting of DQS Precalculation
7043 11:45:27.166694 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 11:45:27.176882 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 11:45:27.183237 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 11:45:27.183330
7047 11:45:27.183404
7048 11:45:27.186556 [Calibration Summary] 800 Mbps
7049 11:45:27.186660 CH 0, Rank 0
7050 11:45:27.189864 SW Impedance : PASS
7051 11:45:27.189965 DUTY Scan : NO K
7052 11:45:27.193194 ZQ Calibration : PASS
7053 11:45:27.196909 Jitter Meter : NO K
7054 11:45:27.197030 CBT Training : PASS
7055 11:45:27.199964 Write leveling : PASS
7056 11:45:27.203341 RX DQS gating : PASS
7057 11:45:27.203475 RX DQ/DQS(RDDQC) : PASS
7058 11:45:27.206760 TX DQ/DQS : PASS
7059 11:45:27.210121 RX DATLAT : PASS
7060 11:45:27.210273 RX DQ/DQS(Engine): PASS
7061 11:45:27.213289 TX OE : NO K
7062 11:45:27.213461 All Pass.
7063 11:45:27.213596
7064 11:45:27.216715 CH 0, Rank 1
7065 11:45:27.216914 SW Impedance : PASS
7066 11:45:27.219764 DUTY Scan : NO K
7067 11:45:27.223236 ZQ Calibration : PASS
7068 11:45:27.223472 Jitter Meter : NO K
7069 11:45:27.226333 CBT Training : PASS
7070 11:45:27.226679 Write leveling : NO K
7071 11:45:27.229724 RX DQS gating : PASS
7072 11:45:27.233556 RX DQ/DQS(RDDQC) : PASS
7073 11:45:27.234118 TX DQ/DQS : PASS
7074 11:45:27.236956 RX DATLAT : PASS
7075 11:45:27.240320 RX DQ/DQS(Engine): PASS
7076 11:45:27.240780 TX OE : NO K
7077 11:45:27.243566 All Pass.
7078 11:45:27.244056
7079 11:45:27.244640 CH 1, Rank 0
7080 11:45:27.246420 SW Impedance : PASS
7081 11:45:27.246942 DUTY Scan : NO K
7082 11:45:27.249976 ZQ Calibration : PASS
7083 11:45:27.253001 Jitter Meter : NO K
7084 11:45:27.253439 CBT Training : PASS
7085 11:45:27.256553 Write leveling : PASS
7086 11:45:27.259673 RX DQS gating : PASS
7087 11:45:27.260088 RX DQ/DQS(RDDQC) : PASS
7088 11:45:27.263241 TX DQ/DQS : PASS
7089 11:45:27.266790 RX DATLAT : PASS
7090 11:45:27.267213 RX DQ/DQS(Engine): PASS
7091 11:45:27.269706 TX OE : NO K
7092 11:45:27.270122 All Pass.
7093 11:45:27.270565
7094 11:45:27.273051 CH 1, Rank 1
7095 11:45:27.273463 SW Impedance : PASS
7096 11:45:27.276390 DUTY Scan : NO K
7097 11:45:27.280052 ZQ Calibration : PASS
7098 11:45:27.280605 Jitter Meter : NO K
7099 11:45:27.283002 CBT Training : PASS
7100 11:45:27.283381 Write leveling : NO K
7101 11:45:27.286619 RX DQS gating : PASS
7102 11:45:27.290054 RX DQ/DQS(RDDQC) : PASS
7103 11:45:27.290465 TX DQ/DQS : PASS
7104 11:45:27.293304 RX DATLAT : PASS
7105 11:45:27.296251 RX DQ/DQS(Engine): PASS
7106 11:45:27.296712 TX OE : NO K
7107 11:45:27.300092 All Pass.
7108 11:45:27.300576
7109 11:45:27.300912 DramC Write-DBI off
7110 11:45:27.302978 PER_BANK_REFRESH: Hybrid Mode
7111 11:45:27.306508 TX_TRACKING: ON
7112 11:45:27.313134 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 11:45:27.316626 [FAST_K] Save calibration result to emmc
7114 11:45:27.319454 dramc_set_vcore_voltage set vcore to 725000
7115 11:45:27.323007 Read voltage for 1600, 0
7116 11:45:27.323425 Vio18 = 0
7117 11:45:27.326156 Vcore = 725000
7118 11:45:27.326572 Vdram = 0
7119 11:45:27.326901 Vddq = 0
7120 11:45:27.329796 Vmddr = 0
7121 11:45:27.332709 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 11:45:27.339766 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 11:45:27.340463 MEM_TYPE=3, freq_sel=13
7124 11:45:27.342661 sv_algorithm_assistance_LP4_3733
7125 11:45:27.349436 ============ PULL DRAM RESETB DOWN ============
7126 11:45:27.352507 ========== PULL DRAM RESETB DOWN end =========
7127 11:45:27.355926 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 11:45:27.359309 ===================================
7129 11:45:27.362352 LPDDR4 DRAM CONFIGURATION
7130 11:45:27.365799 ===================================
7131 11:45:27.369336 EX_ROW_EN[0] = 0x0
7132 11:45:27.369754 EX_ROW_EN[1] = 0x0
7133 11:45:27.372376 LP4Y_EN = 0x0
7134 11:45:27.372794 WORK_FSP = 0x1
7135 11:45:27.375864 WL = 0x5
7136 11:45:27.376354 RL = 0x5
7137 11:45:27.379071 BL = 0x2
7138 11:45:27.379151 RPST = 0x0
7139 11:45:27.381754 RD_PRE = 0x0
7140 11:45:27.381835 WR_PRE = 0x1
7141 11:45:27.385282 WR_PST = 0x1
7142 11:45:27.385362 DBI_WR = 0x0
7143 11:45:27.388924 DBI_RD = 0x0
7144 11:45:27.389005 OTF = 0x1
7145 11:45:27.391955 ===================================
7146 11:45:27.394970 ===================================
7147 11:45:27.398413 ANA top config
7148 11:45:27.401816 ===================================
7149 11:45:27.405191 DLL_ASYNC_EN = 0
7150 11:45:27.405272 ALL_SLAVE_EN = 0
7151 11:45:27.408400 NEW_RANK_MODE = 1
7152 11:45:27.411537 DLL_IDLE_MODE = 1
7153 11:45:27.414927 LP45_APHY_COMB_EN = 1
7154 11:45:27.418553 TX_ODT_DIS = 0
7155 11:45:27.418634 NEW_8X_MODE = 1
7156 11:45:27.421520 ===================================
7157 11:45:27.425021 ===================================
7158 11:45:27.428422 data_rate = 3200
7159 11:45:27.431715 CKR = 1
7160 11:45:27.434849 DQ_P2S_RATIO = 8
7161 11:45:27.438009 ===================================
7162 11:45:27.441798 CA_P2S_RATIO = 8
7163 11:45:27.444700 DQ_CA_OPEN = 0
7164 11:45:27.444781 DQ_SEMI_OPEN = 0
7165 11:45:27.448277 CA_SEMI_OPEN = 0
7166 11:45:27.451251 CA_FULL_RATE = 0
7167 11:45:27.454612 DQ_CKDIV4_EN = 0
7168 11:45:27.458114 CA_CKDIV4_EN = 0
7169 11:45:27.461247 CA_PREDIV_EN = 0
7170 11:45:27.461329 PH8_DLY = 12
7171 11:45:27.464647 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 11:45:27.468123 DQ_AAMCK_DIV = 4
7173 11:45:27.471535 CA_AAMCK_DIV = 4
7174 11:45:27.474413 CA_ADMCK_DIV = 4
7175 11:45:27.478115 DQ_TRACK_CA_EN = 0
7176 11:45:27.480916 CA_PICK = 1600
7177 11:45:27.480998 CA_MCKIO = 1600
7178 11:45:27.484370 MCKIO_SEMI = 0
7179 11:45:27.487815 PLL_FREQ = 3068
7180 11:45:27.490762 DQ_UI_PI_RATIO = 32
7181 11:45:27.494255 CA_UI_PI_RATIO = 0
7182 11:45:27.497795 ===================================
7183 11:45:27.501231 ===================================
7184 11:45:27.504475 memory_type:LPDDR4
7185 11:45:27.504556 GP_NUM : 10
7186 11:45:27.507411 SRAM_EN : 1
7187 11:45:27.507492 MD32_EN : 0
7188 11:45:27.510831 ===================================
7189 11:45:27.514326 [ANA_INIT] >>>>>>>>>>>>>>
7190 11:45:27.517493 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 11:45:27.520770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 11:45:27.524269 ===================================
7193 11:45:27.527293 data_rate = 3200,PCW = 0X7600
7194 11:45:27.530757 ===================================
7195 11:45:27.533805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 11:45:27.540770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 11:45:27.543561 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 11:45:27.550269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 11:45:27.554093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 11:45:27.557554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 11:45:27.557636 [ANA_INIT] flow start
7202 11:45:27.560517 [ANA_INIT] PLL >>>>>>>>
7203 11:45:27.564059 [ANA_INIT] PLL <<<<<<<<
7204 11:45:27.564183 [ANA_INIT] MIDPI >>>>>>>>
7205 11:45:27.566895 [ANA_INIT] MIDPI <<<<<<<<
7206 11:45:27.570670 [ANA_INIT] DLL >>>>>>>>
7207 11:45:27.570751 [ANA_INIT] DLL <<<<<<<<
7208 11:45:27.573558 [ANA_INIT] flow end
7209 11:45:27.576932 ============ LP4 DIFF to SE enter ============
7210 11:45:27.583367 ============ LP4 DIFF to SE exit ============
7211 11:45:27.583451 [ANA_INIT] <<<<<<<<<<<<<
7212 11:45:27.586699 [Flow] Enable top DCM control >>>>>
7213 11:45:27.590185 [Flow] Enable top DCM control <<<<<
7214 11:45:27.593336 Enable DLL master slave shuffle
7215 11:45:27.600404 ==============================================================
7216 11:45:27.600486 Gating Mode config
7217 11:45:27.606753 ==============================================================
7218 11:45:27.610149 Config description:
7219 11:45:27.619791 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 11:45:27.626459 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 11:45:27.629702 SELPH_MODE 0: By rank 1: By Phase
7222 11:45:27.636179 ==============================================================
7223 11:45:27.639845 GAT_TRACK_EN = 1
7224 11:45:27.639927 RX_GATING_MODE = 2
7225 11:45:27.642961 RX_GATING_TRACK_MODE = 2
7226 11:45:27.646459 SELPH_MODE = 1
7227 11:45:27.649367 PICG_EARLY_EN = 1
7228 11:45:27.652807 VALID_LAT_VALUE = 1
7229 11:45:27.659336 ==============================================================
7230 11:45:27.662976 Enter into Gating configuration >>>>
7231 11:45:27.666355 Exit from Gating configuration <<<<
7232 11:45:27.669153 Enter into DVFS_PRE_config >>>>>
7233 11:45:27.679155 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 11:45:27.682600 Exit from DVFS_PRE_config <<<<<
7235 11:45:27.686225 Enter into PICG configuration >>>>
7236 11:45:27.689167 Exit from PICG configuration <<<<
7237 11:45:27.692511 [RX_INPUT] configuration >>>>>
7238 11:45:27.695984 [RX_INPUT] configuration <<<<<
7239 11:45:27.699488 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 11:45:27.706123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 11:45:27.712413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 11:45:27.718748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 11:45:27.722184 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 11:45:27.729103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 11:45:27.732498 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 11:45:27.739107 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 11:45:27.742104 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 11:45:27.745066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 11:45:27.748753 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 11:45:27.755267 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 11:45:27.758930 ===================================
7252 11:45:27.762380 LPDDR4 DRAM CONFIGURATION
7253 11:45:27.765195 ===================================
7254 11:45:27.765276 EX_ROW_EN[0] = 0x0
7255 11:45:27.768467 EX_ROW_EN[1] = 0x0
7256 11:45:27.768551 LP4Y_EN = 0x0
7257 11:45:27.772166 WORK_FSP = 0x1
7258 11:45:27.772273 WL = 0x5
7259 11:45:27.775217 RL = 0x5
7260 11:45:27.775298 BL = 0x2
7261 11:45:27.778354 RPST = 0x0
7262 11:45:27.778435 RD_PRE = 0x0
7263 11:45:27.781930 WR_PRE = 0x1
7264 11:45:27.782011 WR_PST = 0x1
7265 11:45:27.785075 DBI_WR = 0x0
7266 11:45:27.788501 DBI_RD = 0x0
7267 11:45:27.788584 OTF = 0x1
7268 11:45:27.791587 ===================================
7269 11:45:27.794946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 11:45:27.798042 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 11:45:27.805116 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 11:45:27.807944 ===================================
7273 11:45:27.811540 LPDDR4 DRAM CONFIGURATION
7274 11:45:27.815083 ===================================
7275 11:45:27.815164 EX_ROW_EN[0] = 0x10
7276 11:45:27.818353 EX_ROW_EN[1] = 0x0
7277 11:45:27.818434 LP4Y_EN = 0x0
7278 11:45:27.821716 WORK_FSP = 0x1
7279 11:45:27.821798 WL = 0x5
7280 11:45:27.825160 RL = 0x5
7281 11:45:27.825241 BL = 0x2
7282 11:45:27.828174 RPST = 0x0
7283 11:45:27.828279 RD_PRE = 0x0
7284 11:45:27.831676 WR_PRE = 0x1
7285 11:45:27.831784 WR_PST = 0x1
7286 11:45:27.834634 DBI_WR = 0x0
7287 11:45:27.834748 DBI_RD = 0x0
7288 11:45:27.838133 OTF = 0x1
7289 11:45:27.841360 ===================================
7290 11:45:27.848433 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 11:45:27.848519 ==
7292 11:45:27.851400 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 11:45:27.854963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 11:45:27.855087 ==
7295 11:45:27.858095 [Duty_Offset_Calibration]
7296 11:45:27.858179 B0:2 B1:0 CA:3
7297 11:45:27.858277
7298 11:45:27.861543 [DutyScan_Calibration_Flow] k_type=0
7299 11:45:27.872796
7300 11:45:27.872878 ==CLK 0==
7301 11:45:27.875757 Final CLK duty delay cell = 0
7302 11:45:27.879014 [0] MAX Duty = 5031%(X100), DQS PI = 12
7303 11:45:27.882356 [0] MIN Duty = 4907%(X100), DQS PI = 4
7304 11:45:27.882447 [0] AVG Duty = 4969%(X100)
7305 11:45:27.885647
7306 11:45:27.889356 CH0 CLK Duty spec in!! Max-Min= 124%
7307 11:45:27.892100 [DutyScan_Calibration_Flow] ====Done====
7308 11:45:27.892229
7309 11:45:27.895345 [DutyScan_Calibration_Flow] k_type=1
7310 11:45:27.912391
7311 11:45:27.912542 ==DQS 0 ==
7312 11:45:27.915994 Final DQS duty delay cell = 0
7313 11:45:27.918895 [0] MAX Duty = 5125%(X100), DQS PI = 32
7314 11:45:27.922519 [0] MIN Duty = 4875%(X100), DQS PI = 48
7315 11:45:27.925904 [0] AVG Duty = 5000%(X100)
7316 11:45:27.926076
7317 11:45:27.926209 ==DQS 1 ==
7318 11:45:27.929253 Final DQS duty delay cell = 0
7319 11:45:27.932563 [0] MAX Duty = 5156%(X100), DQS PI = 32
7320 11:45:27.935491 [0] MIN Duty = 5062%(X100), DQS PI = 6
7321 11:45:27.939271 [0] AVG Duty = 5109%(X100)
7322 11:45:27.939449
7323 11:45:27.942158 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7324 11:45:27.942334
7325 11:45:27.945829 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7326 11:45:27.949266 [DutyScan_Calibration_Flow] ====Done====
7327 11:45:27.949440
7328 11:45:27.952482 [DutyScan_Calibration_Flow] k_type=3
7329 11:45:27.970323
7330 11:45:27.970505 ==DQM 0 ==
7331 11:45:27.973938 Final DQM duty delay cell = 0
7332 11:45:27.976892 [0] MAX Duty = 5156%(X100), DQS PI = 30
7333 11:45:27.980342 [0] MIN Duty = 4875%(X100), DQS PI = 50
7334 11:45:27.983303 [0] AVG Duty = 5015%(X100)
7335 11:45:27.983637
7336 11:45:27.983932 ==DQM 1 ==
7337 11:45:27.986962 Final DQM duty delay cell = 4
7338 11:45:27.990433 [4] MAX Duty = 5187%(X100), DQS PI = 60
7339 11:45:27.993913 [4] MIN Duty = 5031%(X100), DQS PI = 12
7340 11:45:27.997424 [4] AVG Duty = 5109%(X100)
7341 11:45:27.997885
7342 11:45:28.000352 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7343 11:45:28.000877
7344 11:45:28.003917 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7345 11:45:28.006777 [DutyScan_Calibration_Flow] ====Done====
7346 11:45:28.007194
7347 11:45:28.010238 [DutyScan_Calibration_Flow] k_type=2
7348 11:45:28.027075
7349 11:45:28.027603 ==DQ 0 ==
7350 11:45:28.030241 Final DQ duty delay cell = -4
7351 11:45:28.033521 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7352 11:45:28.036883 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7353 11:45:28.040370 [-4] AVG Duty = 4938%(X100)
7354 11:45:28.040788
7355 11:45:28.041115 ==DQ 1 ==
7356 11:45:28.043899 Final DQ duty delay cell = 0
7357 11:45:28.046899 [0] MAX Duty = 5156%(X100), DQS PI = 58
7358 11:45:28.050420 [0] MIN Duty = 5000%(X100), DQS PI = 16
7359 11:45:28.053432 [0] AVG Duty = 5078%(X100)
7360 11:45:28.053852
7361 11:45:28.056915 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7362 11:45:28.057334
7363 11:45:28.060232 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7364 11:45:28.063573 [DutyScan_Calibration_Flow] ====Done====
7365 11:45:28.063995 ==
7366 11:45:28.066831 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 11:45:28.070364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 11:45:28.070788 ==
7369 11:45:28.073360 [Duty_Offset_Calibration]
7370 11:45:28.073776 B0:1 B1:-2 CA:1
7371 11:45:28.074104
7372 11:45:28.076490 [DutyScan_Calibration_Flow] k_type=0
7373 11:45:28.087472
7374 11:45:28.087888 ==CLK 0==
7375 11:45:28.090752 Final CLK duty delay cell = 0
7376 11:45:28.094248 [0] MAX Duty = 5094%(X100), DQS PI = 22
7377 11:45:28.097674 [0] MIN Duty = 4844%(X100), DQS PI = 2
7378 11:45:28.098150 [0] AVG Duty = 4969%(X100)
7379 11:45:28.101131
7380 11:45:28.104184 CH1 CLK Duty spec in!! Max-Min= 250%
7381 11:45:28.107764 [DutyScan_Calibration_Flow] ====Done====
7382 11:45:28.108183
7383 11:45:28.110529 [DutyScan_Calibration_Flow] k_type=1
7384 11:45:28.127320
7385 11:45:28.127777 ==DQS 0 ==
7386 11:45:28.130726 Final DQS duty delay cell = 0
7387 11:45:28.133977 [0] MAX Duty = 5187%(X100), DQS PI = 24
7388 11:45:28.137187 [0] MIN Duty = 5062%(X100), DQS PI = 0
7389 11:45:28.140723 [0] AVG Duty = 5124%(X100)
7390 11:45:28.141181
7391 11:45:28.141536 ==DQS 1 ==
7392 11:45:28.143581 Final DQS duty delay cell = 0
7393 11:45:28.146977 [0] MAX Duty = 5093%(X100), DQS PI = 62
7394 11:45:28.150602 [0] MIN Duty = 4844%(X100), DQS PI = 26
7395 11:45:28.154063 [0] AVG Duty = 4968%(X100)
7396 11:45:28.154886
7397 11:45:28.157075 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7398 11:45:28.157629
7399 11:45:28.160568 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7400 11:45:28.164179 [DutyScan_Calibration_Flow] ====Done====
7401 11:45:28.164795
7402 11:45:28.166824 [DutyScan_Calibration_Flow] k_type=3
7403 11:45:28.184040
7404 11:45:28.184777 ==DQM 0 ==
7405 11:45:28.187523 Final DQM duty delay cell = 0
7406 11:45:28.190916 [0] MAX Duty = 5031%(X100), DQS PI = 24
7407 11:45:28.193763 [0] MIN Duty = 4813%(X100), DQS PI = 54
7408 11:45:28.197312 [0] AVG Duty = 4922%(X100)
7409 11:45:28.197827
7410 11:45:28.198245 ==DQM 1 ==
7411 11:45:28.200799 Final DQM duty delay cell = 0
7412 11:45:28.204181 [0] MAX Duty = 5062%(X100), DQS PI = 34
7413 11:45:28.207553 [0] MIN Duty = 4875%(X100), DQS PI = 26
7414 11:45:28.210548 [0] AVG Duty = 4968%(X100)
7415 11:45:28.211005
7416 11:45:28.213905 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7417 11:45:28.214363
7418 11:45:28.217351 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7419 11:45:28.220861 [DutyScan_Calibration_Flow] ====Done====
7420 11:45:28.221451
7421 11:45:28.223801 [DutyScan_Calibration_Flow] k_type=2
7422 11:45:28.241273
7423 11:45:28.241816 ==DQ 0 ==
7424 11:45:28.244299 Final DQ duty delay cell = 0
7425 11:45:28.247642 [0] MAX Duty = 5093%(X100), DQS PI = 22
7426 11:45:28.250724 [0] MIN Duty = 4907%(X100), DQS PI = 62
7427 11:45:28.251145 [0] AVG Duty = 5000%(X100)
7428 11:45:28.254376
7429 11:45:28.254795 ==DQ 1 ==
7430 11:45:28.257419 Final DQ duty delay cell = 0
7431 11:45:28.260741 [0] MAX Duty = 5125%(X100), DQS PI = 34
7432 11:45:28.264102 [0] MIN Duty = 4969%(X100), DQS PI = 24
7433 11:45:28.264969 [0] AVG Duty = 5047%(X100)
7434 11:45:28.267261
7435 11:45:28.270682 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7436 11:45:28.271150
7437 11:45:28.274094 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7438 11:45:28.277655 [DutyScan_Calibration_Flow] ====Done====
7439 11:45:28.281050 nWR fixed to 30
7440 11:45:28.281645 [ModeRegInit_LP4] CH0 RK0
7441 11:45:28.284133 [ModeRegInit_LP4] CH0 RK1
7442 11:45:28.287439 [ModeRegInit_LP4] CH1 RK0
7443 11:45:28.290520 [ModeRegInit_LP4] CH1 RK1
7444 11:45:28.291172 match AC timing 5
7445 11:45:28.296938 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 11:45:28.300253 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 11:45:28.303812 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 11:45:28.310600 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 11:45:28.313505 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 11:45:28.313806 [MiockJmeterHQA]
7451 11:45:28.314041
7452 11:45:28.317083 [DramcMiockJmeter] u1RxGatingPI = 0
7453 11:45:28.320374 0 : 4255, 4029
7454 11:45:28.320679 4 : 4252, 4027
7455 11:45:28.323849 8 : 4252, 4027
7456 11:45:28.324368 12 : 4255, 4030
7457 11:45:28.324767 16 : 4363, 4137
7458 11:45:28.326979 20 : 4255, 4030
7459 11:45:28.327370 24 : 4363, 4137
7460 11:45:28.330540 28 : 4253, 4027
7461 11:45:28.331065 32 : 4255, 4029
7462 11:45:28.333946 36 : 4252, 4027
7463 11:45:28.334298 40 : 4363, 4137
7464 11:45:28.337347 44 : 4363, 4137
7465 11:45:28.337716 48 : 4253, 4027
7466 11:45:28.338085 52 : 4252, 4027
7467 11:45:28.340307 56 : 4252, 4027
7468 11:45:28.340738 60 : 4252, 4027
7469 11:45:28.343672 64 : 4253, 4026
7470 11:45:28.343770 68 : 4360, 4138
7471 11:45:28.346745 72 : 4250, 4027
7472 11:45:28.346828 76 : 4250, 4027
7473 11:45:28.346892 80 : 4250, 4027
7474 11:45:28.350240 84 : 4250, 4026
7475 11:45:28.350323 88 : 4250, 4027
7476 11:45:28.353348 92 : 4361, 4137
7477 11:45:28.353431 96 : 4361, 4137
7478 11:45:28.356887 100 : 4250, 4027
7479 11:45:28.356970 104 : 4361, 3722
7480 11:45:28.359813 108 : 4250, 2
7481 11:45:28.359926 112 : 4250, 0
7482 11:45:28.360074 116 : 4250, 0
7483 11:45:28.363336 120 : 4253, 0
7484 11:45:28.363418 124 : 4361, 0
7485 11:45:28.366771 128 : 4363, 0
7486 11:45:28.366853 132 : 4361, 0
7487 11:45:28.366919 136 : 4250, 0
7488 11:45:28.369980 140 : 4250, 0
7489 11:45:28.370063 144 : 4250, 0
7490 11:45:28.370128 148 : 4250, 0
7491 11:45:28.373160 152 : 4250, 0
7492 11:45:28.373243 156 : 4250, 0
7493 11:45:28.376784 160 : 4250, 0
7494 11:45:28.376893 164 : 4250, 0
7495 11:45:28.376959 168 : 4250, 0
7496 11:45:28.380333 172 : 4250, 0
7497 11:45:28.380415 176 : 4361, 0
7498 11:45:28.383141 180 : 4360, 0
7499 11:45:28.383223 184 : 4361, 0
7500 11:45:28.383287 188 : 4249, 0
7501 11:45:28.386742 192 : 4250, 0
7502 11:45:28.386824 196 : 4250, 0
7503 11:45:28.389809 200 : 4250, 0
7504 11:45:28.389891 204 : 4250, 0
7505 11:45:28.389956 208 : 4250, 0
7506 11:45:28.393169 212 : 4250, 0
7507 11:45:28.393252 216 : 4250, 0
7508 11:45:28.393318 220 : 4250, 0
7509 11:45:28.396208 224 : 4253, 0
7510 11:45:28.396306 228 : 4361, 0
7511 11:45:28.399752 232 : 4249, 1
7512 11:45:28.399834 236 : 4250, 1349
7513 11:45:28.403000 240 : 4250, 4027
7514 11:45:28.403082 244 : 4250, 4027
7515 11:45:28.406532 248 : 4250, 4027
7516 11:45:28.406615 252 : 4253, 4029
7517 11:45:28.406680 256 : 4250, 4027
7518 11:45:28.410010 260 : 4250, 4027
7519 11:45:28.410092 264 : 4361, 4137
7520 11:45:28.412955 268 : 4250, 4026
7521 11:45:28.413037 272 : 4250, 4027
7522 11:45:28.416387 276 : 4360, 4138
7523 11:45:28.416470 280 : 4250, 4027
7524 11:45:28.419744 284 : 4250, 4027
7525 11:45:28.419827 288 : 4361, 4137
7526 11:45:28.423098 292 : 4250, 4027
7527 11:45:28.423182 296 : 4253, 4029
7528 11:45:28.426566 300 : 4249, 4027
7529 11:45:28.426651 304 : 4250, 4026
7530 11:45:28.429538 308 : 4250, 4027
7531 11:45:28.429621 312 : 4250, 4027
7532 11:45:28.429687 316 : 4361, 4137
7533 11:45:28.433002 320 : 4250, 4027
7534 11:45:28.433104 324 : 4250, 4027
7535 11:45:28.436501 328 : 4360, 4138
7536 11:45:28.436584 332 : 4250, 4027
7537 11:45:28.439383 336 : 4250, 4027
7538 11:45:28.439466 340 : 4361, 4137
7539 11:45:28.442892 344 : 4250, 4027
7540 11:45:28.442975 348 : 4250, 4027
7541 11:45:28.446378 352 : 4250, 4016
7542 11:45:28.446461 356 : 4252, 2914
7543 11:45:28.449401 360 : 4250, 4
7544 11:45:28.449485
7545 11:45:28.449550 MIOCK jitter meter ch=0
7546 11:45:28.449610
7547 11:45:28.452946 1T = (360-108) = 252 dly cells
7548 11:45:28.459812 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7549 11:45:28.459899 ==
7550 11:45:28.462765 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 11:45:28.466321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 11:45:28.466405 ==
7553 11:45:28.472847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 11:45:28.476416 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 11:45:28.479217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 11:45:28.486041 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 11:45:28.495740 [CA 0] Center 43 (13~74) winsize 62
7558 11:45:28.498813 [CA 1] Center 43 (13~74) winsize 62
7559 11:45:28.502399 [CA 2] Center 39 (10~68) winsize 59
7560 11:45:28.505541 [CA 3] Center 38 (9~68) winsize 60
7561 11:45:28.509088 [CA 4] Center 36 (7~66) winsize 60
7562 11:45:28.512439 [CA 5] Center 36 (7~66) winsize 60
7563 11:45:28.512521
7564 11:45:28.515442 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7565 11:45:28.515528
7566 11:45:28.518912 [CATrainingPosCal] consider 1 rank data
7567 11:45:28.522203 u2DelayCellTimex100 = 258/100 ps
7568 11:45:28.525293 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7569 11:45:28.532164 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7570 11:45:28.535722 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7571 11:45:28.538744 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7572 11:45:28.542353 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7573 11:45:28.545296 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 11:45:28.545379
7575 11:45:28.548799 CA PerBit enable=1, Macro0, CA PI delay=36
7576 11:45:28.548882
7577 11:45:28.552320 [CBTSetCACLKResult] CA Dly = 36
7578 11:45:28.555302 CS Dly: 11 (0~42)
7579 11:45:28.558731 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 11:45:28.562204 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 11:45:28.562286 ==
7582 11:45:28.565742 Dram Type= 6, Freq= 0, CH_0, rank 1
7583 11:45:28.568675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 11:45:28.572165 ==
7585 11:45:28.575680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 11:45:28.578516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 11:45:28.585650 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 11:45:28.591814 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 11:45:28.599087 [CA 0] Center 43 (13~74) winsize 62
7590 11:45:28.602543 [CA 1] Center 43 (13~74) winsize 62
7591 11:45:28.606162 [CA 2] Center 39 (10~68) winsize 59
7592 11:45:28.609623 [CA 3] Center 39 (10~68) winsize 59
7593 11:45:28.612822 [CA 4] Center 36 (7~66) winsize 60
7594 11:45:28.615726 [CA 5] Center 36 (6~66) winsize 61
7595 11:45:28.615808
7596 11:45:28.619042 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7597 11:45:28.619125
7598 11:45:28.625890 [CATrainingPosCal] consider 2 rank data
7599 11:45:28.625973 u2DelayCellTimex100 = 258/100 ps
7600 11:45:28.632244 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7601 11:45:28.635979 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 11:45:28.639271 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7603 11:45:28.642690 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7604 11:45:28.645607 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7605 11:45:28.649189 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7606 11:45:28.649265
7607 11:45:28.652436 CA PerBit enable=1, Macro0, CA PI delay=36
7608 11:45:28.652538
7609 11:45:28.655956 [CBTSetCACLKResult] CA Dly = 36
7610 11:45:28.658939 CS Dly: 11 (0~43)
7611 11:45:28.662465 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 11:45:28.665446 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 11:45:28.665532
7614 11:45:28.668993 ----->DramcWriteLeveling(PI) begin...
7615 11:45:28.672526 ==
7616 11:45:28.672609 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 11:45:28.679007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 11:45:28.679091 ==
7619 11:45:28.681972 Write leveling (Byte 0): 36 => 36
7620 11:45:28.685506 Write leveling (Byte 1): 28 => 28
7621 11:45:28.688900 DramcWriteLeveling(PI) end<-----
7622 11:45:28.688983
7623 11:45:28.689047 ==
7624 11:45:28.692323 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 11:45:28.695283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 11:45:28.695366 ==
7627 11:45:28.698758 [Gating] SW mode calibration
7628 11:45:28.705370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7629 11:45:28.708947 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7630 11:45:28.715351 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:45:28.718609 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 11:45:28.722203 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 11:45:28.728622 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 11:45:28.731928 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7635 11:45:28.735219 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7636 11:45:28.742111 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 11:45:28.745438 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 11:45:28.748600 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 11:45:28.755636 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 11:45:28.758839 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 11:45:28.762389 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7642 11:45:28.768791 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7643 11:45:28.772398 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7644 11:45:28.775267 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7645 11:45:28.782259 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:45:28.785360 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:45:28.788736 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 11:45:28.795641 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 11:45:28.798503 1 6 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7650 11:45:28.801978 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7651 11:45:28.808699 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7652 11:45:28.811677 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7653 11:45:28.815217 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:45:28.818786 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 11:45:28.824980 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 11:45:28.828623 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 11:45:28.831359 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7658 11:45:28.838272 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 11:45:28.841314 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7660 11:45:28.845176 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7661 11:45:28.851447 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:45:28.854970 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:45:28.858262 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:45:28.864506 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:45:28.868344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:45:28.871483 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:45:28.877724 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:45:28.881253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:45:28.884733 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:45:28.891303 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:45:28.894323 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:45:28.897734 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:45:28.904698 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7674 11:45:28.907675 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 11:45:28.911085 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7676 11:45:28.914252 Total UI for P1: 0, mck2ui 16
7677 11:45:28.917761 best dqsien dly found for B0: ( 1, 9, 14)
7678 11:45:28.924359 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7679 11:45:28.927739 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7680 11:45:28.930625 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 11:45:28.934110 Total UI for P1: 0, mck2ui 16
7682 11:45:28.937391 best dqsien dly found for B1: ( 1, 9, 26)
7683 11:45:28.940789 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7684 11:45:28.944217 best DQS1 dly(MCK, UI, PI) = (1, 9, 26)
7685 11:45:28.944340
7686 11:45:28.951029 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7687 11:45:28.954499 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)
7688 11:45:28.957441 [Gating] SW calibration Done
7689 11:45:28.957524 ==
7690 11:45:28.960972 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 11:45:28.964513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 11:45:28.964596 ==
7693 11:45:28.964661 RX Vref Scan: 0
7694 11:45:28.964722
7695 11:45:28.967464 RX Vref 0 -> 0, step: 1
7696 11:45:28.967562
7697 11:45:28.970866 RX Delay 0 -> 252, step: 8
7698 11:45:28.974368 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7699 11:45:28.977942 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7700 11:45:28.980799 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7701 11:45:28.987357 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7702 11:45:28.991364 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7703 11:45:28.994263 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7704 11:45:28.997268 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7705 11:45:29.001160 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7706 11:45:29.007442 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7707 11:45:29.010953 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7708 11:45:29.014425 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7709 11:45:29.017704 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7710 11:45:29.020567 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7711 11:45:29.027606 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7712 11:45:29.030519 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7713 11:45:29.033963 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7714 11:45:29.034090 ==
7715 11:45:29.037201 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 11:45:29.040527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 11:45:29.044008 ==
7718 11:45:29.044106 DQS Delay:
7719 11:45:29.044173 DQS0 = 0, DQS1 = 0
7720 11:45:29.047445 DQM Delay:
7721 11:45:29.047530 DQM0 = 127, DQM1 = 124
7722 11:45:29.050423 DQ Delay:
7723 11:45:29.053719 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7724 11:45:29.057210 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7725 11:45:29.060386 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7726 11:45:29.064026 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7727 11:45:29.064108
7728 11:45:29.064173
7729 11:45:29.064275 ==
7730 11:45:29.067017 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 11:45:29.070402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 11:45:29.070485 ==
7733 11:45:29.073734
7734 11:45:29.073815
7735 11:45:29.073879 TX Vref Scan disable
7736 11:45:29.077079 == TX Byte 0 ==
7737 11:45:29.080566 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7738 11:45:29.083756 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7739 11:45:29.087216 == TX Byte 1 ==
7740 11:45:29.090249 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7741 11:45:29.093656 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7742 11:45:29.093738 ==
7743 11:45:29.097124 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:45:29.103837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:45:29.103944 ==
7746 11:45:29.116189
7747 11:45:29.119558 TX Vref early break, caculate TX vref
7748 11:45:29.122767 TX Vref=16, minBit 9, minWin=21, winSum=362
7749 11:45:29.126382 TX Vref=18, minBit 8, minWin=22, winSum=368
7750 11:45:29.129280 TX Vref=20, minBit 11, minWin=22, winSum=380
7751 11:45:29.132859 TX Vref=22, minBit 8, minWin=23, winSum=387
7752 11:45:29.136404 TX Vref=24, minBit 4, minWin=24, winSum=404
7753 11:45:29.142634 TX Vref=26, minBit 11, minWin=24, winSum=408
7754 11:45:29.146312 TX Vref=28, minBit 8, minWin=23, winSum=406
7755 11:45:29.149652 TX Vref=30, minBit 8, minWin=23, winSum=400
7756 11:45:29.152636 TX Vref=32, minBit 8, minWin=23, winSum=393
7757 11:45:29.156117 TX Vref=34, minBit 8, minWin=22, winSum=385
7758 11:45:29.162933 [TxChooseVref] Worse bit 11, Min win 24, Win sum 408, Final Vref 26
7759 11:45:29.163032
7760 11:45:29.166144 Final TX Range 0 Vref 26
7761 11:45:29.166250
7762 11:45:29.166331 ==
7763 11:45:29.168946 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 11:45:29.172433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 11:45:29.172515 ==
7766 11:45:29.172643
7767 11:45:29.172754
7768 11:45:29.176046 TX Vref Scan disable
7769 11:45:29.182720 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7770 11:45:29.182817 == TX Byte 0 ==
7771 11:45:29.185728 u2DelayCellOfst[0]=11 cells (3 PI)
7772 11:45:29.189194 u2DelayCellOfst[1]=15 cells (4 PI)
7773 11:45:29.192134 u2DelayCellOfst[2]=7 cells (2 PI)
7774 11:45:29.195613 u2DelayCellOfst[3]=7 cells (2 PI)
7775 11:45:29.199073 u2DelayCellOfst[4]=3 cells (1 PI)
7776 11:45:29.202580 u2DelayCellOfst[5]=0 cells (0 PI)
7777 11:45:29.205516 u2DelayCellOfst[6]=15 cells (4 PI)
7778 11:45:29.208924 u2DelayCellOfst[7]=15 cells (4 PI)
7779 11:45:29.212418 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7780 11:45:29.215342 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7781 11:45:29.218690 == TX Byte 1 ==
7782 11:45:29.221981 u2DelayCellOfst[8]=0 cells (0 PI)
7783 11:45:29.222062 u2DelayCellOfst[9]=3 cells (1 PI)
7784 11:45:29.225623 u2DelayCellOfst[10]=7 cells (2 PI)
7785 11:45:29.228659 u2DelayCellOfst[11]=3 cells (1 PI)
7786 11:45:29.232168 u2DelayCellOfst[12]=15 cells (4 PI)
7787 11:45:29.235369 u2DelayCellOfst[13]=7 cells (2 PI)
7788 11:45:29.238959 u2DelayCellOfst[14]=15 cells (4 PI)
7789 11:45:29.241769 u2DelayCellOfst[15]=11 cells (3 PI)
7790 11:45:29.245338 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7791 11:45:29.252053 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7792 11:45:29.252134 DramC Write-DBI on
7793 11:45:29.252198 ==
7794 11:45:29.255214 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 11:45:29.261660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 11:45:29.261741 ==
7797 11:45:29.261805
7798 11:45:29.261864
7799 11:45:29.261921 TX Vref Scan disable
7800 11:45:29.265757 == TX Byte 0 ==
7801 11:45:29.269105 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7802 11:45:29.272249 == TX Byte 1 ==
7803 11:45:29.275722 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7804 11:45:29.279207 DramC Write-DBI off
7805 11:45:29.279289
7806 11:45:29.279352 [DATLAT]
7807 11:45:29.279412 Freq=1600, CH0 RK0
7808 11:45:29.279469
7809 11:45:29.282089 DATLAT Default: 0xf
7810 11:45:29.285465 0, 0xFFFF, sum = 0
7811 11:45:29.285548 1, 0xFFFF, sum = 0
7812 11:45:29.288858 2, 0xFFFF, sum = 0
7813 11:45:29.288940 3, 0xFFFF, sum = 0
7814 11:45:29.292354 4, 0xFFFF, sum = 0
7815 11:45:29.292437 5, 0xFFFF, sum = 0
7816 11:45:29.295249 6, 0xFFFF, sum = 0
7817 11:45:29.295331 7, 0xFFFF, sum = 0
7818 11:45:29.298901 8, 0xFFFF, sum = 0
7819 11:45:29.298983 9, 0xFFFF, sum = 0
7820 11:45:29.302423 10, 0xFFFF, sum = 0
7821 11:45:29.302505 11, 0xFFFF, sum = 0
7822 11:45:29.305318 12, 0xFFFF, sum = 0
7823 11:45:29.305417 13, 0xEFFF, sum = 0
7824 11:45:29.308964 14, 0x0, sum = 1
7825 11:45:29.309047 15, 0x0, sum = 2
7826 11:45:29.311728 16, 0x0, sum = 3
7827 11:45:29.311811 17, 0x0, sum = 4
7828 11:45:29.315361 best_step = 15
7829 11:45:29.315442
7830 11:45:29.315505 ==
7831 11:45:29.318965 Dram Type= 6, Freq= 0, CH_0, rank 0
7832 11:45:29.321763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7833 11:45:29.321845 ==
7834 11:45:29.325245 RX Vref Scan: 1
7835 11:45:29.325327
7836 11:45:29.325390 Set Vref Range= 24 -> 127
7837 11:45:29.325450
7838 11:45:29.328717 RX Vref 24 -> 127, step: 1
7839 11:45:29.328827
7840 11:45:29.331607 RX Delay 11 -> 252, step: 4
7841 11:45:29.331688
7842 11:45:29.335266 Set Vref, RX VrefLevel [Byte0]: 24
7843 11:45:29.338639 [Byte1]: 24
7844 11:45:29.338719
7845 11:45:29.341703 Set Vref, RX VrefLevel [Byte0]: 25
7846 11:45:29.344934 [Byte1]: 25
7847 11:45:29.348404
7848 11:45:29.348487 Set Vref, RX VrefLevel [Byte0]: 26
7849 11:45:29.352014 [Byte1]: 26
7850 11:45:29.355985
7851 11:45:29.356082 Set Vref, RX VrefLevel [Byte0]: 27
7852 11:45:29.359379 [Byte1]: 27
7853 11:45:29.363892
7854 11:45:29.364015 Set Vref, RX VrefLevel [Byte0]: 28
7855 11:45:29.367296 [Byte1]: 28
7856 11:45:29.371450
7857 11:45:29.371551 Set Vref, RX VrefLevel [Byte0]: 29
7858 11:45:29.375022 [Byte1]: 29
7859 11:45:29.378691
7860 11:45:29.378771 Set Vref, RX VrefLevel [Byte0]: 30
7861 11:45:29.382239 [Byte1]: 30
7862 11:45:29.386310
7863 11:45:29.386436 Set Vref, RX VrefLevel [Byte0]: 31
7864 11:45:29.389848 [Byte1]: 31
7865 11:45:29.394234
7866 11:45:29.394315 Set Vref, RX VrefLevel [Byte0]: 32
7867 11:45:29.397192 [Byte1]: 32
7868 11:45:29.401924
7869 11:45:29.402020 Set Vref, RX VrefLevel [Byte0]: 33
7870 11:45:29.404826 [Byte1]: 33
7871 11:45:29.409780
7872 11:45:29.409867 Set Vref, RX VrefLevel [Byte0]: 34
7873 11:45:29.412787 [Byte1]: 34
7874 11:45:29.417387
7875 11:45:29.417488 Set Vref, RX VrefLevel [Byte0]: 35
7876 11:45:29.420249 [Byte1]: 35
7877 11:45:29.424943
7878 11:45:29.425054 Set Vref, RX VrefLevel [Byte0]: 36
7879 11:45:29.427763 [Byte1]: 36
7880 11:45:29.432332
7881 11:45:29.432466 Set Vref, RX VrefLevel [Byte0]: 37
7882 11:45:29.435672 [Byte1]: 37
7883 11:45:29.440184
7884 11:45:29.440351 Set Vref, RX VrefLevel [Byte0]: 38
7885 11:45:29.443117 [Byte1]: 38
7886 11:45:29.447544
7887 11:45:29.447746 Set Vref, RX VrefLevel [Byte0]: 39
7888 11:45:29.450800 [Byte1]: 39
7889 11:45:29.455315
7890 11:45:29.455554 Set Vref, RX VrefLevel [Byte0]: 40
7891 11:45:29.458297 [Byte1]: 40
7892 11:45:29.463007
7893 11:45:29.463443 Set Vref, RX VrefLevel [Byte0]: 41
7894 11:45:29.466407 [Byte1]: 41
7895 11:45:29.470472
7896 11:45:29.470933 Set Vref, RX VrefLevel [Byte0]: 42
7897 11:45:29.473905 [Byte1]: 42
7898 11:45:29.478614
7899 11:45:29.479110 Set Vref, RX VrefLevel [Byte0]: 43
7900 11:45:29.481421 [Byte1]: 43
7901 11:45:29.485876
7902 11:45:29.486356 Set Vref, RX VrefLevel [Byte0]: 44
7903 11:45:29.489274 [Byte1]: 44
7904 11:45:29.493823
7905 11:45:29.494303 Set Vref, RX VrefLevel [Byte0]: 45
7906 11:45:29.497153 [Byte1]: 45
7907 11:45:29.500899
7908 11:45:29.501422 Set Vref, RX VrefLevel [Byte0]: 46
7909 11:45:29.504328 [Byte1]: 46
7910 11:45:29.508471
7911 11:45:29.508977 Set Vref, RX VrefLevel [Byte0]: 47
7912 11:45:29.511978 [Byte1]: 47
7913 11:45:29.516644
7914 11:45:29.517195 Set Vref, RX VrefLevel [Byte0]: 48
7915 11:45:29.519456 [Byte1]: 48
7916 11:45:29.524049
7917 11:45:29.524601 Set Vref, RX VrefLevel [Byte0]: 49
7918 11:45:29.527507 [Byte1]: 49
7919 11:45:29.531592
7920 11:45:29.532144 Set Vref, RX VrefLevel [Byte0]: 50
7921 11:45:29.535077 [Byte1]: 50
7922 11:45:29.539077
7923 11:45:29.539562 Set Vref, RX VrefLevel [Byte0]: 51
7924 11:45:29.542524 [Byte1]: 51
7925 11:45:29.546900
7926 11:45:29.547441 Set Vref, RX VrefLevel [Byte0]: 52
7927 11:45:29.549958 [Byte1]: 52
7928 11:45:29.554134
7929 11:45:29.554659 Set Vref, RX VrefLevel [Byte0]: 53
7930 11:45:29.557491 [Byte1]: 53
7931 11:45:29.562093
7932 11:45:29.562641 Set Vref, RX VrefLevel [Byte0]: 54
7933 11:45:29.565634 [Byte1]: 54
7934 11:45:29.569478
7935 11:45:29.569977 Set Vref, RX VrefLevel [Byte0]: 55
7936 11:45:29.572970 [Byte1]: 55
7937 11:45:29.577479
7938 11:45:29.577965 Set Vref, RX VrefLevel [Byte0]: 56
7939 11:45:29.580242 [Byte1]: 56
7940 11:45:29.585000
7941 11:45:29.585489 Set Vref, RX VrefLevel [Byte0]: 57
7942 11:45:29.588447 [Byte1]: 57
7943 11:45:29.592502
7944 11:45:29.592989 Set Vref, RX VrefLevel [Byte0]: 58
7945 11:45:29.595886 [Byte1]: 58
7946 11:45:29.599905
7947 11:45:29.600437 Set Vref, RX VrefLevel [Byte0]: 59
7948 11:45:29.603516 [Byte1]: 59
7949 11:45:29.607875
7950 11:45:29.608400 Set Vref, RX VrefLevel [Byte0]: 60
7951 11:45:29.611230 [Byte1]: 60
7952 11:45:29.615369
7953 11:45:29.615834 Set Vref, RX VrefLevel [Byte0]: 61
7954 11:45:29.618775 [Byte1]: 61
7955 11:45:29.622826
7956 11:45:29.623045 Set Vref, RX VrefLevel [Byte0]: 62
7957 11:45:29.625875 [Byte1]: 62
7958 11:45:29.629905
7959 11:45:29.629987 Set Vref, RX VrefLevel [Byte0]: 63
7960 11:45:29.633487 [Byte1]: 63
7961 11:45:29.637593
7962 11:45:29.637674 Set Vref, RX VrefLevel [Byte0]: 64
7963 11:45:29.641132 [Byte1]: 64
7964 11:45:29.645239
7965 11:45:29.645320 Set Vref, RX VrefLevel [Byte0]: 65
7966 11:45:29.648600 [Byte1]: 65
7967 11:45:29.652920
7968 11:45:29.653012 Set Vref, RX VrefLevel [Byte0]: 66
7969 11:45:29.656173 [Byte1]: 66
7970 11:45:29.660769
7971 11:45:29.660855 Set Vref, RX VrefLevel [Byte0]: 67
7972 11:45:29.663566 [Byte1]: 67
7973 11:45:29.667958
7974 11:45:29.668040 Set Vref, RX VrefLevel [Byte0]: 68
7975 11:45:29.671368 [Byte1]: 68
7976 11:45:29.675918
7977 11:45:29.676000 Set Vref, RX VrefLevel [Byte0]: 69
7978 11:45:29.678875 [Byte1]: 69
7979 11:45:29.683412
7980 11:45:29.683486 Set Vref, RX VrefLevel [Byte0]: 70
7981 11:45:29.686971 [Byte1]: 70
7982 11:45:29.691022
7983 11:45:29.691099 Set Vref, RX VrefLevel [Byte0]: 71
7984 11:45:29.694587 [Byte1]: 71
7985 11:45:29.698953
7986 11:45:29.699025 Set Vref, RX VrefLevel [Byte0]: 72
7987 11:45:29.702147 [Byte1]: 72
7988 11:45:29.706352
7989 11:45:29.706427 Set Vref, RX VrefLevel [Byte0]: 73
7990 11:45:29.709348 [Byte1]: 73
7991 11:45:29.713992
7992 11:45:29.714066 Set Vref, RX VrefLevel [Byte0]: 74
7993 11:45:29.717463 [Byte1]: 74
7994 11:45:29.721572
7995 11:45:29.721643 Set Vref, RX VrefLevel [Byte0]: 75
7996 11:45:29.724755 [Byte1]: 75
7997 11:45:29.729201
7998 11:45:29.729273 Final RX Vref Byte 0 = 64 to rank0
7999 11:45:29.732632 Final RX Vref Byte 1 = 59 to rank0
8000 11:45:29.735561 Final RX Vref Byte 0 = 64 to rank1
8001 11:45:29.739113 Final RX Vref Byte 1 = 59 to rank1==
8002 11:45:29.742679 Dram Type= 6, Freq= 0, CH_0, rank 0
8003 11:45:29.749198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 11:45:29.749281 ==
8005 11:45:29.749347 DQS Delay:
8006 11:45:29.749407 DQS0 = 0, DQS1 = 0
8007 11:45:29.752711 DQM Delay:
8008 11:45:29.752783 DQM0 = 126, DQM1 = 120
8009 11:45:29.755940 DQ Delay:
8010 11:45:29.759175 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8011 11:45:29.762498 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =138
8012 11:45:29.765686 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8013 11:45:29.769086 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8014 11:45:29.769158
8015 11:45:29.769219
8016 11:45:29.769277
8017 11:45:29.772547 [DramC_TX_OE_Calibration] TA2
8018 11:45:29.775723 Original DQ_B0 (3 6) =30, OEN = 27
8019 11:45:29.779103 Original DQ_B1 (3 6) =30, OEN = 27
8020 11:45:29.782804 24, 0x0, End_B0=24 End_B1=24
8021 11:45:29.782877 25, 0x0, End_B0=25 End_B1=25
8022 11:45:29.785550 26, 0x0, End_B0=26 End_B1=26
8023 11:45:29.788949 27, 0x0, End_B0=27 End_B1=27
8024 11:45:29.792346 28, 0x0, End_B0=28 End_B1=28
8025 11:45:29.792418 29, 0x0, End_B0=29 End_B1=29
8026 11:45:29.795374 30, 0x0, End_B0=30 End_B1=30
8027 11:45:29.798898 31, 0x4141, End_B0=30 End_B1=30
8028 11:45:29.802391 Byte0 end_step=30 best_step=27
8029 11:45:29.805782 Byte1 end_step=30 best_step=27
8030 11:45:29.808696 Byte0 TX OE(2T, 0.5T) = (3, 3)
8031 11:45:29.812484 Byte1 TX OE(2T, 0.5T) = (3, 3)
8032 11:45:29.812607
8033 11:45:29.812710
8034 11:45:29.818535 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8035 11:45:29.821914 CH0 RK0: MR19=303, MR18=1615
8036 11:45:29.828864 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
8037 11:45:29.828942
8038 11:45:29.831726 ----->DramcWriteLeveling(PI) begin...
8039 11:45:29.831800 ==
8040 11:45:29.835172 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 11:45:29.838488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 11:45:29.838562 ==
8043 11:45:29.841923 Write leveling (Byte 0): 33 => 33
8044 11:45:29.845551 Write leveling (Byte 1): 29 => 29
8045 11:45:29.848571 DramcWriteLeveling(PI) end<-----
8046 11:45:29.848642
8047 11:45:29.848708 ==
8048 11:45:29.851993 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 11:45:29.855022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 11:45:29.855104 ==
8051 11:45:29.858384 [Gating] SW mode calibration
8052 11:45:29.864840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8053 11:45:29.871562 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8054 11:45:29.874914 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:45:29.881409 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 11:45:29.884874 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 11:45:29.888322 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8058 11:45:29.894656 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8059 11:45:29.897914 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:45:29.901446 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:45:29.905029 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:45:29.911625 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:45:29.914603 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:45:29.918111 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8065 11:45:29.924782 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
8066 11:45:29.927947 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8067 11:45:29.931258 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8068 11:45:29.938072 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:45:29.941040 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:45:29.944569 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:45:29.950941 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:45:29.954416 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:45:29.957864 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8074 11:45:29.964470 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8075 11:45:29.967304 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:45:29.971087 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:45:29.977810 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:45:29.980859 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:45:29.984192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:45:29.990648 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:45:29.994050 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 11:45:29.997652 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 11:45:30.003818 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:45:30.007324 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:45:30.010750 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:45:30.017262 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:45:30.020723 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:45:30.023691 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:45:30.030096 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:45:30.033508 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:45:30.036884 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:45:30.043537 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:45:30.046639 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:45:30.050340 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:45:30.056864 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8096 11:45:30.059715 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8097 11:45:30.063313 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 11:45:30.070101 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 11:45:30.073106 Total UI for P1: 0, mck2ui 16
8100 11:45:30.076830 best dqsien dly found for B0: ( 1, 9, 8)
8101 11:45:30.079992 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 11:45:30.082995 Total UI for P1: 0, mck2ui 16
8103 11:45:30.086496 best dqsien dly found for B1: ( 1, 9, 16)
8104 11:45:30.089972 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8105 11:45:30.093340 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8106 11:45:30.093497
8107 11:45:30.096689 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8108 11:45:30.099846 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8109 11:45:30.103208 [Gating] SW calibration Done
8110 11:45:30.103391 ==
8111 11:45:30.106658 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 11:45:30.109661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 11:45:30.113179 ==
8114 11:45:30.113428 RX Vref Scan: 0
8115 11:45:30.113590
8116 11:45:30.116487 RX Vref 0 -> 0, step: 1
8117 11:45:30.116713
8118 11:45:30.116897 RX Delay 0 -> 252, step: 8
8119 11:45:30.123401 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8120 11:45:30.127022 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8121 11:45:30.129974 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8122 11:45:30.133600 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8123 11:45:30.136559 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8124 11:45:30.143414 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8125 11:45:30.146933 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8126 11:45:30.150231 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8127 11:45:30.153446 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8128 11:45:30.157082 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8129 11:45:30.163550 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8130 11:45:30.166494 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8131 11:45:30.170084 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8132 11:45:30.173012 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8133 11:45:30.179821 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8134 11:45:30.182866 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8135 11:45:30.182958 ==
8136 11:45:30.186058 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 11:45:30.189609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 11:45:30.189701 ==
8139 11:45:30.189784 DQS Delay:
8140 11:45:30.192689 DQS0 = 0, DQS1 = 0
8141 11:45:30.192773 DQM Delay:
8142 11:45:30.196082 DQM0 = 128, DQM1 = 120
8143 11:45:30.196166 DQ Delay:
8144 11:45:30.199603 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8145 11:45:30.202903 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8146 11:45:30.206167 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8147 11:45:30.212963 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8148 11:45:30.213076
8149 11:45:30.213164
8150 11:45:30.213258 ==
8151 11:45:30.216036 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 11:45:30.219522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 11:45:30.219609 ==
8154 11:45:30.219681
8155 11:45:30.219743
8156 11:45:30.222724 TX Vref Scan disable
8157 11:45:30.222813 == TX Byte 0 ==
8158 11:45:30.229615 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8159 11:45:30.232598 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8160 11:45:30.232683 == TX Byte 1 ==
8161 11:45:30.239038 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8162 11:45:30.242789 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8163 11:45:30.242874 ==
8164 11:45:30.245747 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:45:30.249230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:45:30.249313 ==
8167 11:45:30.263390
8168 11:45:30.266846 TX Vref early break, caculate TX vref
8169 11:45:30.269706 TX Vref=16, minBit 1, minWin=21, winSum=369
8170 11:45:30.273102 TX Vref=18, minBit 0, minWin=22, winSum=372
8171 11:45:30.276682 TX Vref=20, minBit 0, minWin=23, winSum=383
8172 11:45:30.279571 TX Vref=22, minBit 0, minWin=24, winSum=394
8173 11:45:30.283059 TX Vref=24, minBit 1, minWin=24, winSum=402
8174 11:45:30.289902 TX Vref=26, minBit 1, minWin=25, winSum=411
8175 11:45:30.293280 TX Vref=28, minBit 10, minWin=25, winSum=418
8176 11:45:30.296242 TX Vref=30, minBit 8, minWin=24, winSum=406
8177 11:45:30.299892 TX Vref=32, minBit 13, minWin=23, winSum=397
8178 11:45:30.303453 TX Vref=34, minBit 8, minWin=22, winSum=389
8179 11:45:30.309825 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 28
8180 11:45:30.309911
8181 11:45:30.313248 Final TX Range 0 Vref 28
8182 11:45:30.313327
8183 11:45:30.313389 ==
8184 11:45:30.316456 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 11:45:30.319342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 11:45:30.319415 ==
8187 11:45:30.319475
8188 11:45:30.319532
8189 11:45:30.322846 TX Vref Scan disable
8190 11:45:30.329199 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8191 11:45:30.329322 == TX Byte 0 ==
8192 11:45:30.332625 u2DelayCellOfst[0]=15 cells (4 PI)
8193 11:45:30.336118 u2DelayCellOfst[1]=18 cells (5 PI)
8194 11:45:30.339693 u2DelayCellOfst[2]=15 cells (4 PI)
8195 11:45:30.342474 u2DelayCellOfst[3]=15 cells (4 PI)
8196 11:45:30.346166 u2DelayCellOfst[4]=11 cells (3 PI)
8197 11:45:30.349038 u2DelayCellOfst[5]=0 cells (0 PI)
8198 11:45:30.352617 u2DelayCellOfst[6]=22 cells (6 PI)
8199 11:45:30.356080 u2DelayCellOfst[7]=22 cells (6 PI)
8200 11:45:30.359624 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8201 11:45:30.362573 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8202 11:45:30.365925 == TX Byte 1 ==
8203 11:45:30.369345 u2DelayCellOfst[8]=0 cells (0 PI)
8204 11:45:30.372188 u2DelayCellOfst[9]=0 cells (0 PI)
8205 11:45:30.372280 u2DelayCellOfst[10]=3 cells (1 PI)
8206 11:45:30.375724 u2DelayCellOfst[11]=3 cells (1 PI)
8207 11:45:30.379075 u2DelayCellOfst[12]=7 cells (2 PI)
8208 11:45:30.382967 u2DelayCellOfst[13]=11 cells (3 PI)
8209 11:45:30.385922 u2DelayCellOfst[14]=11 cells (3 PI)
8210 11:45:30.388976 u2DelayCellOfst[15]=11 cells (3 PI)
8211 11:45:30.392606 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8212 11:45:30.398930 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8213 11:45:30.399016 DramC Write-DBI on
8214 11:45:30.399082 ==
8215 11:45:30.402195 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 11:45:30.408609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 11:45:30.408694 ==
8218 11:45:30.408760
8219 11:45:30.408822
8220 11:45:30.408881 TX Vref Scan disable
8221 11:45:30.412661 == TX Byte 0 ==
8222 11:45:30.416188 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8223 11:45:30.419533 == TX Byte 1 ==
8224 11:45:30.422893 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8225 11:45:30.426274 DramC Write-DBI off
8226 11:45:30.426353
8227 11:45:30.426418 [DATLAT]
8228 11:45:30.426516 Freq=1600, CH0 RK1
8229 11:45:30.426617
8230 11:45:30.429218 DATLAT Default: 0xf
8231 11:45:30.429333 0, 0xFFFF, sum = 0
8232 11:45:30.432706 1, 0xFFFF, sum = 0
8233 11:45:30.436097 2, 0xFFFF, sum = 0
8234 11:45:30.436209 3, 0xFFFF, sum = 0
8235 11:45:30.439348 4, 0xFFFF, sum = 0
8236 11:45:30.439452 5, 0xFFFF, sum = 0
8237 11:45:30.442915 6, 0xFFFF, sum = 0
8238 11:45:30.442992 7, 0xFFFF, sum = 0
8239 11:45:30.445864 8, 0xFFFF, sum = 0
8240 11:45:30.445939 9, 0xFFFF, sum = 0
8241 11:45:30.449411 10, 0xFFFF, sum = 0
8242 11:45:30.449485 11, 0xFFFF, sum = 0
8243 11:45:30.452339 12, 0xFFFF, sum = 0
8244 11:45:30.452417 13, 0xCFFF, sum = 0
8245 11:45:30.455802 14, 0x0, sum = 1
8246 11:45:30.455873 15, 0x0, sum = 2
8247 11:45:30.459220 16, 0x0, sum = 3
8248 11:45:30.459324 17, 0x0, sum = 4
8249 11:45:30.462292 best_step = 15
8250 11:45:30.462365
8251 11:45:30.462424 ==
8252 11:45:30.465770 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 11:45:30.469171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 11:45:30.469294 ==
8255 11:45:30.472590 RX Vref Scan: 0
8256 11:45:30.472676
8257 11:45:30.472753 RX Vref 0 -> 0, step: 1
8258 11:45:30.472832
8259 11:45:30.475467 RX Delay 3 -> 252, step: 4
8260 11:45:30.482502 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8261 11:45:30.485408 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8262 11:45:30.489022 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8263 11:45:30.492359 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8264 11:45:30.495675 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8265 11:45:30.501989 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8266 11:45:30.505600 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8267 11:45:30.508626 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8268 11:45:30.512164 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8269 11:45:30.515305 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8270 11:45:30.521760 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8271 11:45:30.525205 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8272 11:45:30.528648 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8273 11:45:30.531935 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8274 11:45:30.534949 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8275 11:45:30.541504 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8276 11:45:30.541587 ==
8277 11:45:30.545208 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 11:45:30.548486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 11:45:30.548573 ==
8280 11:45:30.548640 DQS Delay:
8281 11:45:30.551487 DQS0 = 0, DQS1 = 0
8282 11:45:30.551568 DQM Delay:
8283 11:45:30.555016 DQM0 = 124, DQM1 = 118
8284 11:45:30.555097 DQ Delay:
8285 11:45:30.557911 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8286 11:45:30.561509 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8287 11:45:30.564628 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8288 11:45:30.568134 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8289 11:45:30.571615
8290 11:45:30.571696
8291 11:45:30.571760
8292 11:45:30.571820 [DramC_TX_OE_Calibration] TA2
8293 11:45:30.575052 Original DQ_B0 (3 6) =30, OEN = 27
8294 11:45:30.578427 Original DQ_B1 (3 6) =30, OEN = 27
8295 11:45:30.581310 24, 0x0, End_B0=24 End_B1=24
8296 11:45:30.584821 25, 0x0, End_B0=25 End_B1=25
8297 11:45:30.587775 26, 0x0, End_B0=26 End_B1=26
8298 11:45:30.587859 27, 0x0, End_B0=27 End_B1=27
8299 11:45:30.591327 28, 0x0, End_B0=28 End_B1=28
8300 11:45:30.594866 29, 0x0, End_B0=29 End_B1=29
8301 11:45:30.597858 30, 0x0, End_B0=30 End_B1=30
8302 11:45:30.601440 31, 0x4141, End_B0=30 End_B1=30
8303 11:45:30.601547 Byte0 end_step=30 best_step=27
8304 11:45:30.604800 Byte1 end_step=30 best_step=27
8305 11:45:30.608410 Byte0 TX OE(2T, 0.5T) = (3, 3)
8306 11:45:30.611148 Byte1 TX OE(2T, 0.5T) = (3, 3)
8307 11:45:30.611246
8308 11:45:30.611334
8309 11:45:30.621433 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8310 11:45:30.621514 CH0 RK1: MR19=303, MR18=2210
8311 11:45:30.627729 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8312 11:45:30.631027 [RxdqsGatingPostProcess] freq 1600
8313 11:45:30.637717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8314 11:45:30.641391 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 11:45:30.644716 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 11:45:30.647521 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 11:45:30.650945 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 11:45:30.651028 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 11:45:30.654222 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 11:45:30.657620 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 11:45:30.661176 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 11:45:30.664057 Pre-setting of DQS Precalculation
8323 11:45:30.670514 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8324 11:45:30.670596 ==
8325 11:45:30.674073 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 11:45:30.677494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 11:45:30.677577 ==
8328 11:45:30.683825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 11:45:30.687324 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 11:45:30.690747 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 11:45:30.697249 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 11:45:30.706214 [CA 0] Center 42 (13~71) winsize 59
8333 11:45:30.709131 [CA 1] Center 42 (13~72) winsize 60
8334 11:45:30.712499 [CA 2] Center 38 (9~67) winsize 59
8335 11:45:30.716097 [CA 3] Center 37 (8~66) winsize 59
8336 11:45:30.719164 [CA 4] Center 37 (8~67) winsize 60
8337 11:45:30.722728 [CA 5] Center 36 (7~66) winsize 60
8338 11:45:30.722810
8339 11:45:30.725955 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8340 11:45:30.726037
8341 11:45:30.729103 [CATrainingPosCal] consider 1 rank data
8342 11:45:30.732628 u2DelayCellTimex100 = 258/100 ps
8343 11:45:30.736011 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8344 11:45:30.742694 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8345 11:45:30.745835 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8346 11:45:30.749178 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8347 11:45:30.752404 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8348 11:45:30.755708 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8349 11:45:30.755820
8350 11:45:30.759314 CA PerBit enable=1, Macro0, CA PI delay=36
8351 11:45:30.759419
8352 11:45:30.762406 [CBTSetCACLKResult] CA Dly = 36
8353 11:45:30.765468 CS Dly: 10 (0~41)
8354 11:45:30.768785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 11:45:30.772113 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 11:45:30.772198 ==
8357 11:45:30.775511 Dram Type= 6, Freq= 0, CH_1, rank 1
8358 11:45:30.779132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 11:45:30.782593 ==
8360 11:45:30.785927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 11:45:30.789341 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 11:45:30.795802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 11:45:30.798682 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 11:45:30.809158 [CA 0] Center 41 (12~71) winsize 60
8365 11:45:30.812650 [CA 1] Center 42 (12~72) winsize 61
8366 11:45:30.815509 [CA 2] Center 37 (8~67) winsize 60
8367 11:45:30.819073 [CA 3] Center 36 (7~66) winsize 60
8368 11:45:30.822087 [CA 4] Center 37 (8~67) winsize 60
8369 11:45:30.825596 [CA 5] Center 36 (6~66) winsize 61
8370 11:45:30.825678
8371 11:45:30.829115 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8372 11:45:30.829196
8373 11:45:30.832366 [CATrainingPosCal] consider 2 rank data
8374 11:45:30.835603 u2DelayCellTimex100 = 258/100 ps
8375 11:45:30.842279 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8376 11:45:30.845866 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8377 11:45:30.848810 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8378 11:45:30.852257 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8379 11:45:30.855300 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8380 11:45:30.858681 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8381 11:45:30.858763
8382 11:45:30.862117 CA PerBit enable=1, Macro0, CA PI delay=36
8383 11:45:30.862199
8384 11:45:30.865542 [CBTSetCACLKResult] CA Dly = 36
8385 11:45:30.868777 CS Dly: 11 (0~43)
8386 11:45:30.872114 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 11:45:30.875710 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 11:45:30.875823
8389 11:45:30.878650 ----->DramcWriteLeveling(PI) begin...
8390 11:45:30.878733 ==
8391 11:45:30.882280 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 11:45:30.888570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 11:45:30.888652 ==
8394 11:45:30.891796 Write leveling (Byte 0): 24 => 24
8395 11:45:30.891877 Write leveling (Byte 1): 28 => 28
8396 11:45:30.895230 DramcWriteLeveling(PI) end<-----
8397 11:45:30.895305
8398 11:45:30.895367 ==
8399 11:45:30.898824 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 11:45:30.905259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:45:30.905339 ==
8402 11:45:30.908832 [Gating] SW mode calibration
8403 11:45:30.915290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8404 11:45:30.918655 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8405 11:45:30.925091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:45:30.928689 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:45:30.931617 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 11:45:30.938832 1 4 12 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
8409 11:45:30.941593 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8410 11:45:30.945241 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:45:30.951590 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:45:30.955165 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:45:30.958338 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:45:30.965032 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 11:45:30.968451 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 11:45:30.971949 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8417 11:45:30.974863 1 5 16 | B1->B0 | 2525 2727 | 0 0 | (1 0) (1 0)
8418 11:45:30.981593 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:45:30.984821 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:45:30.988131 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:45:30.994955 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:45:30.998119 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:45:31.001511 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:45:31.008181 1 6 12 | B1->B0 | 2525 2726 | 0 1 | (0 0) (0 0)
8425 11:45:31.011723 1 6 16 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
8426 11:45:31.014589 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:45:31.021598 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:45:31.025025 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:45:31.028062 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:45:31.035066 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:45:31.037932 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 11:45:31.041465 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 11:45:31.047965 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8434 11:45:31.051182 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:45:31.054299 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:45:31.061337 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:45:31.064778 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:45:31.068020 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:45:31.074252 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:45:31.077585 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:45:31.081090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:45:31.087489 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:45:31.091284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:45:31.094407 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:45:31.100587 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:45:31.104074 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:45:31.107399 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:45:31.114090 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8449 11:45:31.117037 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8450 11:45:31.120874 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8451 11:45:31.123826 Total UI for P1: 0, mck2ui 16
8452 11:45:31.127155 best dqsien dly found for B1: ( 1, 9, 14)
8453 11:45:31.133585 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 11:45:31.133663 Total UI for P1: 0, mck2ui 16
8455 11:45:31.140593 best dqsien dly found for B0: ( 1, 9, 16)
8456 11:45:31.143643 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8457 11:45:31.147122 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8458 11:45:31.147227
8459 11:45:31.150582 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8460 11:45:31.153498 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8461 11:45:31.156988 [Gating] SW calibration Done
8462 11:45:31.157062 ==
8463 11:45:31.160226 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 11:45:31.163464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 11:45:31.163537 ==
8466 11:45:31.166835 RX Vref Scan: 0
8467 11:45:31.166937
8468 11:45:31.167030 RX Vref 0 -> 0, step: 1
8469 11:45:31.167117
8470 11:45:31.170261 RX Delay 0 -> 252, step: 8
8471 11:45:31.173456 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8472 11:45:31.179882 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8473 11:45:31.183422 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8474 11:45:31.186965 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8475 11:45:31.189987 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8476 11:45:31.193482 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8477 11:45:31.200051 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8478 11:45:31.203424 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8479 11:45:31.206512 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8480 11:45:31.209997 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8481 11:45:31.212923 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8482 11:45:31.220048 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8483 11:45:31.223310 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8484 11:45:31.226416 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8485 11:45:31.229687 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8486 11:45:31.236167 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8487 11:45:31.236313 ==
8488 11:45:31.239426 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 11:45:31.243022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 11:45:31.243098 ==
8491 11:45:31.243162 DQS Delay:
8492 11:45:31.246715 DQS0 = 0, DQS1 = 0
8493 11:45:31.246788 DQM Delay:
8494 11:45:31.249797 DQM0 = 132, DQM1 = 126
8495 11:45:31.249886 DQ Delay:
8496 11:45:31.253265 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8497 11:45:31.256068 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8498 11:45:31.259605 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8499 11:45:31.263092 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8500 11:45:31.263182
8501 11:45:31.263246
8502 11:45:31.266475 ==
8503 11:45:31.269729 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 11:45:31.272606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 11:45:31.272692 ==
8506 11:45:31.272758
8507 11:45:31.272819
8508 11:45:31.276121 TX Vref Scan disable
8509 11:45:31.276245 == TX Byte 0 ==
8510 11:45:31.279649 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8511 11:45:31.286384 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8512 11:45:31.286461 == TX Byte 1 ==
8513 11:45:31.289542 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8514 11:45:31.296133 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8515 11:45:31.296264 ==
8516 11:45:31.299199 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 11:45:31.302861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 11:45:31.302941 ==
8519 11:45:31.316701
8520 11:45:31.320227 TX Vref early break, caculate TX vref
8521 11:45:31.323878 TX Vref=16, minBit 11, minWin=21, winSum=361
8522 11:45:31.326774 TX Vref=18, minBit 9, minWin=22, winSum=374
8523 11:45:31.330167 TX Vref=20, minBit 11, minWin=22, winSum=384
8524 11:45:31.333535 TX Vref=22, minBit 0, minWin=24, winSum=396
8525 11:45:31.337062 TX Vref=24, minBit 10, minWin=24, winSum=404
8526 11:45:31.343213 TX Vref=26, minBit 11, minWin=24, winSum=412
8527 11:45:31.346395 TX Vref=28, minBit 1, minWin=25, winSum=417
8528 11:45:31.349867 TX Vref=30, minBit 1, minWin=25, winSum=418
8529 11:45:31.353367 TX Vref=32, minBit 0, minWin=24, winSum=402
8530 11:45:31.356767 TX Vref=34, minBit 0, minWin=24, winSum=398
8531 11:45:31.363311 TX Vref=36, minBit 0, minWin=23, winSum=386
8532 11:45:31.366905 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 30
8533 11:45:31.366982
8534 11:45:31.369739 Final TX Range 0 Vref 30
8535 11:45:31.369819
8536 11:45:31.369880 ==
8537 11:45:31.373298 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 11:45:31.376503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 11:45:31.379705 ==
8540 11:45:31.379780
8541 11:45:31.379841
8542 11:45:31.379900 TX Vref Scan disable
8543 11:45:31.386252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8544 11:45:31.386333 == TX Byte 0 ==
8545 11:45:31.389703 u2DelayCellOfst[0]=22 cells (6 PI)
8546 11:45:31.393088 u2DelayCellOfst[1]=15 cells (4 PI)
8547 11:45:31.396464 u2DelayCellOfst[2]=0 cells (0 PI)
8548 11:45:31.399761 u2DelayCellOfst[3]=3 cells (1 PI)
8549 11:45:31.403003 u2DelayCellOfst[4]=7 cells (2 PI)
8550 11:45:31.406079 u2DelayCellOfst[5]=22 cells (6 PI)
8551 11:45:31.409639 u2DelayCellOfst[6]=22 cells (6 PI)
8552 11:45:31.412966 u2DelayCellOfst[7]=7 cells (2 PI)
8553 11:45:31.416164 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8554 11:45:31.419932 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8555 11:45:31.422775 == TX Byte 1 ==
8556 11:45:31.426366 u2DelayCellOfst[8]=0 cells (0 PI)
8557 11:45:31.429939 u2DelayCellOfst[9]=7 cells (2 PI)
8558 11:45:31.432748 u2DelayCellOfst[10]=18 cells (5 PI)
8559 11:45:31.436166 u2DelayCellOfst[11]=11 cells (3 PI)
8560 11:45:31.436288 u2DelayCellOfst[12]=22 cells (6 PI)
8561 11:45:31.439822 u2DelayCellOfst[13]=22 cells (6 PI)
8562 11:45:31.442724 u2DelayCellOfst[14]=22 cells (6 PI)
8563 11:45:31.446333 u2DelayCellOfst[15]=26 cells (7 PI)
8564 11:45:31.452741 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8565 11:45:31.456040 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8566 11:45:31.456138 DramC Write-DBI on
8567 11:45:31.459342 ==
8568 11:45:31.459424 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 11:45:31.466264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 11:45:31.466358 ==
8571 11:45:31.466455
8572 11:45:31.466518
8573 11:45:31.469564 TX Vref Scan disable
8574 11:45:31.469646 == TX Byte 0 ==
8575 11:45:31.476063 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8576 11:45:31.476147 == TX Byte 1 ==
8577 11:45:31.479606 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8578 11:45:31.482855 DramC Write-DBI off
8579 11:45:31.482932
8580 11:45:31.483000 [DATLAT]
8581 11:45:31.485958 Freq=1600, CH1 RK0
8582 11:45:31.486035
8583 11:45:31.486104 DATLAT Default: 0xf
8584 11:45:31.489592 0, 0xFFFF, sum = 0
8585 11:45:31.489669 1, 0xFFFF, sum = 0
8586 11:45:31.492713 2, 0xFFFF, sum = 0
8587 11:45:31.492795 3, 0xFFFF, sum = 0
8588 11:45:31.495950 4, 0xFFFF, sum = 0
8589 11:45:31.496032 5, 0xFFFF, sum = 0
8590 11:45:31.499530 6, 0xFFFF, sum = 0
8591 11:45:31.499625 7, 0xFFFF, sum = 0
8592 11:45:31.502359 8, 0xFFFF, sum = 0
8593 11:45:31.502441 9, 0xFFFF, sum = 0
8594 11:45:31.505793 10, 0xFFFF, sum = 0
8595 11:45:31.508957 11, 0xFFFF, sum = 0
8596 11:45:31.509064 12, 0xFFFF, sum = 0
8597 11:45:31.512598 13, 0x8FFF, sum = 0
8598 11:45:31.512680 14, 0x0, sum = 1
8599 11:45:31.515575 15, 0x0, sum = 2
8600 11:45:31.515671 16, 0x0, sum = 3
8601 11:45:31.519142 17, 0x0, sum = 4
8602 11:45:31.519241 best_step = 15
8603 11:45:31.519305
8604 11:45:31.519364 ==
8605 11:45:31.522272 Dram Type= 6, Freq= 0, CH_1, rank 0
8606 11:45:31.525634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8607 11:45:31.525710 ==
8608 11:45:31.528817 RX Vref Scan: 1
8609 11:45:31.528887
8610 11:45:31.532617 Set Vref Range= 24 -> 127
8611 11:45:31.532690
8612 11:45:31.532758 RX Vref 24 -> 127, step: 1
8613 11:45:31.532854
8614 11:45:31.535525 RX Delay 11 -> 252, step: 4
8615 11:45:31.535594
8616 11:45:31.538746 Set Vref, RX VrefLevel [Byte0]: 24
8617 11:45:31.542150 [Byte1]: 24
8618 11:45:31.545830
8619 11:45:31.545903 Set Vref, RX VrefLevel [Byte0]: 25
8620 11:45:31.548731 [Byte1]: 25
8621 11:45:31.553439
8622 11:45:31.553515 Set Vref, RX VrefLevel [Byte0]: 26
8623 11:45:31.556429 [Byte1]: 26
8624 11:45:31.561156
8625 11:45:31.561312 Set Vref, RX VrefLevel [Byte0]: 27
8626 11:45:31.564182 [Byte1]: 27
8627 11:45:31.568630
8628 11:45:31.568706 Set Vref, RX VrefLevel [Byte0]: 28
8629 11:45:31.571990 [Byte1]: 28
8630 11:45:31.576358
8631 11:45:31.576434 Set Vref, RX VrefLevel [Byte0]: 29
8632 11:45:31.579183 [Byte1]: 29
8633 11:45:31.583999
8634 11:45:31.584077 Set Vref, RX VrefLevel [Byte0]: 30
8635 11:45:31.587011 [Byte1]: 30
8636 11:45:31.591075
8637 11:45:31.591149 Set Vref, RX VrefLevel [Byte0]: 31
8638 11:45:31.594880 [Byte1]: 31
8639 11:45:31.598995
8640 11:45:31.599073 Set Vref, RX VrefLevel [Byte0]: 32
8641 11:45:31.602336 [Byte1]: 32
8642 11:45:31.606457
8643 11:45:31.606530 Set Vref, RX VrefLevel [Byte0]: 33
8644 11:45:31.609989 [Byte1]: 33
8645 11:45:31.614446
8646 11:45:31.614519 Set Vref, RX VrefLevel [Byte0]: 34
8647 11:45:31.617640 [Byte1]: 34
8648 11:45:31.621697
8649 11:45:31.621820 Set Vref, RX VrefLevel [Byte0]: 35
8650 11:45:31.625300 [Byte1]: 35
8651 11:45:31.629454
8652 11:45:31.629528 Set Vref, RX VrefLevel [Byte0]: 36
8653 11:45:31.632957 [Byte1]: 36
8654 11:45:31.636796
8655 11:45:31.636877 Set Vref, RX VrefLevel [Byte0]: 37
8656 11:45:31.640500 [Byte1]: 37
8657 11:45:31.644909
8658 11:45:31.644988 Set Vref, RX VrefLevel [Byte0]: 38
8659 11:45:31.647885 [Byte1]: 38
8660 11:45:31.652551
8661 11:45:31.652628 Set Vref, RX VrefLevel [Byte0]: 39
8662 11:45:31.655672 [Byte1]: 39
8663 11:45:31.659785
8664 11:45:31.659857 Set Vref, RX VrefLevel [Byte0]: 40
8665 11:45:31.663359 [Byte1]: 40
8666 11:45:31.667420
8667 11:45:31.667497 Set Vref, RX VrefLevel [Byte0]: 41
8668 11:45:31.670966 [Byte1]: 41
8669 11:45:31.675092
8670 11:45:31.675165 Set Vref, RX VrefLevel [Byte0]: 42
8671 11:45:31.678424 [Byte1]: 42
8672 11:45:31.682477
8673 11:45:31.682557 Set Vref, RX VrefLevel [Byte0]: 43
8674 11:45:31.685877 [Byte1]: 43
8675 11:45:31.690280
8676 11:45:31.690367 Set Vref, RX VrefLevel [Byte0]: 44
8677 11:45:31.693797 [Byte1]: 44
8678 11:45:31.697786
8679 11:45:31.697867 Set Vref, RX VrefLevel [Byte0]: 45
8680 11:45:31.701166 [Byte1]: 45
8681 11:45:31.705429
8682 11:45:31.705509 Set Vref, RX VrefLevel [Byte0]: 46
8683 11:45:31.709016 [Byte1]: 46
8684 11:45:31.713239
8685 11:45:31.713320 Set Vref, RX VrefLevel [Byte0]: 47
8686 11:45:31.716537 [Byte1]: 47
8687 11:45:31.720668
8688 11:45:31.720752 Set Vref, RX VrefLevel [Byte0]: 48
8689 11:45:31.723816 [Byte1]: 48
8690 11:45:31.728209
8691 11:45:31.728318 Set Vref, RX VrefLevel [Byte0]: 49
8692 11:45:31.731752 [Byte1]: 49
8693 11:45:31.735756
8694 11:45:31.735837 Set Vref, RX VrefLevel [Byte0]: 50
8695 11:45:31.739424 [Byte1]: 50
8696 11:45:31.743663
8697 11:45:31.743746 Set Vref, RX VrefLevel [Byte0]: 51
8698 11:45:31.746961 [Byte1]: 51
8699 11:45:31.751041
8700 11:45:31.751124 Set Vref, RX VrefLevel [Byte0]: 52
8701 11:45:31.754479 [Byte1]: 52
8702 11:45:31.759107
8703 11:45:31.759188 Set Vref, RX VrefLevel [Byte0]: 53
8704 11:45:31.762095 [Byte1]: 53
8705 11:45:31.766337
8706 11:45:31.766437 Set Vref, RX VrefLevel [Byte0]: 54
8707 11:45:31.769892 [Byte1]: 54
8708 11:45:31.774067
8709 11:45:31.774148 Set Vref, RX VrefLevel [Byte0]: 55
8710 11:45:31.777070 [Byte1]: 55
8711 11:45:31.781682
8712 11:45:31.781764 Set Vref, RX VrefLevel [Byte0]: 56
8713 11:45:31.785077 [Byte1]: 56
8714 11:45:31.789152
8715 11:45:31.789234 Set Vref, RX VrefLevel [Byte0]: 57
8716 11:45:31.792700 [Byte1]: 57
8717 11:45:31.796910
8718 11:45:31.797021 Set Vref, RX VrefLevel [Byte0]: 58
8719 11:45:31.800362 [Byte1]: 58
8720 11:45:31.804599
8721 11:45:31.804683 Set Vref, RX VrefLevel [Byte0]: 59
8722 11:45:31.807634 [Byte1]: 59
8723 11:45:31.812181
8724 11:45:31.812301 Set Vref, RX VrefLevel [Byte0]: 60
8725 11:45:31.815527 [Byte1]: 60
8726 11:45:31.819618
8727 11:45:31.819701 Set Vref, RX VrefLevel [Byte0]: 61
8728 11:45:31.822966 [Byte1]: 61
8729 11:45:31.827106
8730 11:45:31.827219 Set Vref, RX VrefLevel [Byte0]: 62
8731 11:45:31.830537 [Byte1]: 62
8732 11:45:31.834839
8733 11:45:31.834923 Set Vref, RX VrefLevel [Byte0]: 63
8734 11:45:31.838276 [Byte1]: 63
8735 11:45:31.842390
8736 11:45:31.842474 Set Vref, RX VrefLevel [Byte0]: 64
8737 11:45:31.845974 [Byte1]: 64
8738 11:45:31.850087
8739 11:45:31.850172 Set Vref, RX VrefLevel [Byte0]: 65
8740 11:45:31.853593 [Byte1]: 65
8741 11:45:31.857920
8742 11:45:31.858005 Set Vref, RX VrefLevel [Byte0]: 66
8743 11:45:31.860917 [Byte1]: 66
8744 11:45:31.865446
8745 11:45:31.865528 Set Vref, RX VrefLevel [Byte0]: 67
8746 11:45:31.868921 [Byte1]: 67
8747 11:45:31.873066
8748 11:45:31.873150 Set Vref, RX VrefLevel [Byte0]: 68
8749 11:45:31.876075 [Byte1]: 68
8750 11:45:31.880671
8751 11:45:31.880757 Set Vref, RX VrefLevel [Byte0]: 69
8752 11:45:31.883610 [Byte1]: 69
8753 11:45:31.888082
8754 11:45:31.888184 Set Vref, RX VrefLevel [Byte0]: 70
8755 11:45:31.891687 [Byte1]: 70
8756 11:45:31.895830
8757 11:45:31.895910 Set Vref, RX VrefLevel [Byte0]: 71
8758 11:45:31.899237 [Byte1]: 71
8759 11:45:31.903392
8760 11:45:31.903475 Final RX Vref Byte 0 = 56 to rank0
8761 11:45:31.906966 Final RX Vref Byte 1 = 54 to rank0
8762 11:45:31.909885 Final RX Vref Byte 0 = 56 to rank1
8763 11:45:31.913482 Final RX Vref Byte 1 = 54 to rank1==
8764 11:45:31.916777 Dram Type= 6, Freq= 0, CH_1, rank 0
8765 11:45:31.923269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 11:45:31.923377 ==
8767 11:45:31.923462 DQS Delay:
8768 11:45:31.923548 DQS0 = 0, DQS1 = 0
8769 11:45:31.926720 DQM Delay:
8770 11:45:31.926804 DQM0 = 131, DQM1 = 123
8771 11:45:31.929727 DQ Delay:
8772 11:45:31.933150 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8773 11:45:31.936587 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8774 11:45:31.939985 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8775 11:45:31.943238 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8776 11:45:31.943319
8777 11:45:31.943402
8778 11:45:31.943485
8779 11:45:31.946514 [DramC_TX_OE_Calibration] TA2
8780 11:45:31.949544 Original DQ_B0 (3 6) =30, OEN = 27
8781 11:45:31.953104 Original DQ_B1 (3 6) =30, OEN = 27
8782 11:45:31.956716 24, 0x0, End_B0=24 End_B1=24
8783 11:45:31.956805 25, 0x0, End_B0=25 End_B1=25
8784 11:45:31.959608 26, 0x0, End_B0=26 End_B1=26
8785 11:45:31.962967 27, 0x0, End_B0=27 End_B1=27
8786 11:45:31.966171 28, 0x0, End_B0=28 End_B1=28
8787 11:45:31.969813 29, 0x0, End_B0=29 End_B1=29
8788 11:45:31.969894 30, 0x0, End_B0=30 End_B1=30
8789 11:45:31.972943 31, 0x4545, End_B0=30 End_B1=30
8790 11:45:31.976378 Byte0 end_step=30 best_step=27
8791 11:45:31.979843 Byte1 end_step=30 best_step=27
8792 11:45:31.982677 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 11:45:31.986206 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 11:45:31.986291
8795 11:45:31.986375
8796 11:45:31.992630 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8797 11:45:31.996085 CH1 RK0: MR19=303, MR18=70B
8798 11:45:32.002611 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8799 11:45:32.002697
8800 11:45:32.006078 ----->DramcWriteLeveling(PI) begin...
8801 11:45:32.006163 ==
8802 11:45:32.009181 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 11:45:32.012727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 11:45:32.012814 ==
8805 11:45:32.016197 Write leveling (Byte 0): 24 => 24
8806 11:45:32.019108 Write leveling (Byte 1): 26 => 26
8807 11:45:32.022524 DramcWriteLeveling(PI) end<-----
8808 11:45:32.022610
8809 11:45:32.022695 ==
8810 11:45:32.025843 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 11:45:32.029092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 11:45:32.029175 ==
8813 11:45:32.032387 [Gating] SW mode calibration
8814 11:45:32.039008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8815 11:45:32.045635 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8816 11:45:32.049191 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 11:45:32.055811 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 11:45:32.059165 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8819 11:45:32.062124 1 4 12 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
8820 11:45:32.068661 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 11:45:32.072046 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 11:45:32.075386 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 11:45:32.082018 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 11:45:32.085184 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:45:32.088804 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:45:32.091782 1 5 8 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 1)
8827 11:45:32.098760 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8828 11:45:32.102249 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 11:45:32.105132 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 11:45:32.112307 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 11:45:32.115242 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 11:45:32.118763 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:45:32.125346 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8834 11:45:32.128351 1 6 8 | B1->B0 | 2a2a 4444 | 1 0 | (0 0) (0 0)
8835 11:45:32.131781 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
8836 11:45:32.138440 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 11:45:32.141704 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 11:45:32.144994 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 11:45:32.151604 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 11:45:32.155029 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:45:32.158218 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:45:32.165148 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8843 11:45:32.168271 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8844 11:45:32.171722 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 11:45:32.178355 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 11:45:32.181362 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 11:45:32.184882 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 11:45:32.191517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:45:32.195092 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:45:32.197908 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:45:32.204921 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:45:32.207913 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:45:32.211452 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:45:32.217999 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:45:32.221457 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:45:32.224436 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:45:32.231104 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:45:32.234730 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 11:45:32.237709 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8860 11:45:32.244629 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 11:45:32.244748 Total UI for P1: 0, mck2ui 16
8862 11:45:32.250887 best dqsien dly found for B0: ( 1, 9, 10)
8863 11:45:32.250992 Total UI for P1: 0, mck2ui 16
8864 11:45:32.254169 best dqsien dly found for B1: ( 1, 9, 10)
8865 11:45:32.261214 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8866 11:45:32.264151 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8867 11:45:32.264288
8868 11:45:32.267513 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8869 11:45:32.270808 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8870 11:45:32.274442 [Gating] SW calibration Done
8871 11:45:32.274519 ==
8872 11:45:32.277553 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 11:45:32.281192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 11:45:32.281273 ==
8875 11:45:32.284421 RX Vref Scan: 0
8876 11:45:32.284541
8877 11:45:32.284643 RX Vref 0 -> 0, step: 1
8878 11:45:32.284751
8879 11:45:32.287302 RX Delay 0 -> 252, step: 8
8880 11:45:32.290895 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8881 11:45:32.297742 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8882 11:45:32.300963 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8883 11:45:32.304497 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8884 11:45:32.307297 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8885 11:45:32.310688 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8886 11:45:32.314276 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8887 11:45:32.320776 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8888 11:45:32.324354 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8889 11:45:32.327216 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8890 11:45:32.330865 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8891 11:45:32.337486 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8892 11:45:32.340495 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8893 11:45:32.343889 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8894 11:45:32.347312 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8895 11:45:32.350623 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8896 11:45:32.354064 ==
8897 11:45:32.354146 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 11:45:32.361083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 11:45:32.361173 ==
8900 11:45:32.361243 DQS Delay:
8901 11:45:32.363869 DQS0 = 0, DQS1 = 0
8902 11:45:32.363956 DQM Delay:
8903 11:45:32.367080 DQM0 = 132, DQM1 = 128
8904 11:45:32.367176 DQ Delay:
8905 11:45:32.370322 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8906 11:45:32.373889 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8907 11:45:32.377319 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8908 11:45:32.380680 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8909 11:45:32.380794
8910 11:45:32.380911
8911 11:45:32.381000 ==
8912 11:45:32.383986 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 11:45:32.390447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 11:45:32.390623 ==
8915 11:45:32.390753
8916 11:45:32.390876
8917 11:45:32.391009 TX Vref Scan disable
8918 11:45:32.394100 == TX Byte 0 ==
8919 11:45:32.397350 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8920 11:45:32.404239 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8921 11:45:32.404467 == TX Byte 1 ==
8922 11:45:32.407338 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8923 11:45:32.414210 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8924 11:45:32.414511 ==
8925 11:45:32.417484 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 11:45:32.420420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 11:45:32.420739 ==
8928 11:45:32.433156
8929 11:45:32.436123 TX Vref early break, caculate TX vref
8930 11:45:32.439633 TX Vref=16, minBit 0, minWin=23, winSum=385
8931 11:45:32.443139 TX Vref=18, minBit 0, minWin=23, winSum=392
8932 11:45:32.446114 TX Vref=20, minBit 0, minWin=23, winSum=403
8933 11:45:32.449622 TX Vref=22, minBit 0, minWin=23, winSum=409
8934 11:45:32.452679 TX Vref=24, minBit 0, minWin=25, winSum=421
8935 11:45:32.459739 TX Vref=26, minBit 0, minWin=26, winSum=428
8936 11:45:32.463126 TX Vref=28, minBit 0, minWin=26, winSum=430
8937 11:45:32.466107 TX Vref=30, minBit 1, minWin=25, winSum=421
8938 11:45:32.469515 TX Vref=32, minBit 1, minWin=25, winSum=417
8939 11:45:32.472899 TX Vref=34, minBit 0, minWin=24, winSum=406
8940 11:45:32.479464 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8941 11:45:32.479690
8942 11:45:32.482924 Final TX Range 0 Vref 28
8943 11:45:32.483150
8944 11:45:32.483327 ==
8945 11:45:32.485805 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 11:45:32.489272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 11:45:32.489498 ==
8948 11:45:32.489682
8949 11:45:32.489846
8950 11:45:32.492541 TX Vref Scan disable
8951 11:45:32.499404 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8952 11:45:32.499631 == TX Byte 0 ==
8953 11:45:32.502614 u2DelayCellOfst[0]=18 cells (5 PI)
8954 11:45:32.505842 u2DelayCellOfst[1]=11 cells (3 PI)
8955 11:45:32.509077 u2DelayCellOfst[2]=0 cells (0 PI)
8956 11:45:32.512404 u2DelayCellOfst[3]=7 cells (2 PI)
8957 11:45:32.515820 u2DelayCellOfst[4]=7 cells (2 PI)
8958 11:45:32.519164 u2DelayCellOfst[5]=22 cells (6 PI)
8959 11:45:32.522767 u2DelayCellOfst[6]=18 cells (5 PI)
8960 11:45:32.522991 u2DelayCellOfst[7]=7 cells (2 PI)
8961 11:45:32.529287 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8962 11:45:32.532280 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8963 11:45:32.532507 == TX Byte 1 ==
8964 11:45:32.535806 u2DelayCellOfst[8]=0 cells (0 PI)
8965 11:45:32.538784 u2DelayCellOfst[9]=7 cells (2 PI)
8966 11:45:32.542201 u2DelayCellOfst[10]=15 cells (4 PI)
8967 11:45:32.545629 u2DelayCellOfst[11]=7 cells (2 PI)
8968 11:45:32.549195 u2DelayCellOfst[12]=15 cells (4 PI)
8969 11:45:32.552114 u2DelayCellOfst[13]=18 cells (5 PI)
8970 11:45:32.555678 u2DelayCellOfst[14]=18 cells (5 PI)
8971 11:45:32.558675 u2DelayCellOfst[15]=18 cells (5 PI)
8972 11:45:32.562178 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8973 11:45:32.568379 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8974 11:45:32.568609 DramC Write-DBI on
8975 11:45:32.568786 ==
8976 11:45:32.571949 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 11:45:32.578172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 11:45:32.578400 ==
8979 11:45:32.578578
8980 11:45:32.578742
8981 11:45:32.578900 TX Vref Scan disable
8982 11:45:32.582262 == TX Byte 0 ==
8983 11:45:32.585550 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8984 11:45:32.588448 == TX Byte 1 ==
8985 11:45:32.591943 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8986 11:45:32.595299 DramC Write-DBI off
8987 11:45:32.595594
8988 11:45:32.595841 [DATLAT]
8989 11:45:32.596015 Freq=1600, CH1 RK1
8990 11:45:32.596187
8991 11:45:32.598768 DATLAT Default: 0xf
8992 11:45:32.598995 0, 0xFFFF, sum = 0
8993 11:45:32.601793 1, 0xFFFF, sum = 0
8994 11:45:32.602077 2, 0xFFFF, sum = 0
8995 11:45:32.605445 3, 0xFFFF, sum = 0
8996 11:45:32.608816 4, 0xFFFF, sum = 0
8997 11:45:32.609142 5, 0xFFFF, sum = 0
8998 11:45:32.611843 6, 0xFFFF, sum = 0
8999 11:45:32.612131 7, 0xFFFF, sum = 0
9000 11:45:32.615267 8, 0xFFFF, sum = 0
9001 11:45:32.615582 9, 0xFFFF, sum = 0
9002 11:45:32.618534 10, 0xFFFF, sum = 0
9003 11:45:32.618861 11, 0xFFFF, sum = 0
9004 11:45:32.621925 12, 0xFFFF, sum = 0
9005 11:45:32.622318 13, 0x8FFF, sum = 0
9006 11:45:32.625268 14, 0x0, sum = 1
9007 11:45:32.625611 15, 0x0, sum = 2
9008 11:45:32.628431 16, 0x0, sum = 3
9009 11:45:32.628727 17, 0x0, sum = 4
9010 11:45:32.631886 best_step = 15
9011 11:45:32.632246
9012 11:45:32.632501 ==
9013 11:45:32.635158 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 11:45:32.638334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 11:45:32.638445 ==
9016 11:45:32.641877 RX Vref Scan: 0
9017 11:45:32.641960
9018 11:45:32.642024 RX Vref 0 -> 0, step: 1
9019 11:45:32.642085
9020 11:45:32.645291 RX Delay 11 -> 252, step: 4
9021 11:45:32.648149 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9022 11:45:32.654738 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9023 11:45:32.658303 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9024 11:45:32.661837 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9025 11:45:32.664775 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9026 11:45:32.668302 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9027 11:45:32.675019 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9028 11:45:32.678095 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9029 11:45:32.681435 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9030 11:45:32.684991 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9031 11:45:32.687837 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9032 11:45:32.694664 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9033 11:45:32.697786 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9034 11:45:32.701180 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9035 11:45:32.704801 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9036 11:45:32.711494 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9037 11:45:32.711576 ==
9038 11:45:32.714408 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 11:45:32.718000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 11:45:32.718107 ==
9041 11:45:32.718200 DQS Delay:
9042 11:45:32.721366 DQS0 = 0, DQS1 = 0
9043 11:45:32.721456 DQM Delay:
9044 11:45:32.724684 DQM0 = 130, DQM1 = 125
9045 11:45:32.724772 DQ Delay:
9046 11:45:32.728070 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9047 11:45:32.730863 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
9048 11:45:32.734374 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9049 11:45:32.737822 DQ12 =132, DQ13 =136, DQ14 =130, DQ15 =136
9050 11:45:32.737895
9051 11:45:32.737955
9052 11:45:32.738013
9053 11:45:32.740946 [DramC_TX_OE_Calibration] TA2
9054 11:45:32.744661 Original DQ_B0 (3 6) =30, OEN = 27
9055 11:45:32.747644 Original DQ_B1 (3 6) =30, OEN = 27
9056 11:45:32.751099 24, 0x0, End_B0=24 End_B1=24
9057 11:45:32.754559 25, 0x0, End_B0=25 End_B1=25
9058 11:45:32.757439 26, 0x0, End_B0=26 End_B1=26
9059 11:45:32.757517 27, 0x0, End_B0=27 End_B1=27
9060 11:45:32.760937 28, 0x0, End_B0=28 End_B1=28
9061 11:45:32.764475 29, 0x0, End_B0=29 End_B1=29
9062 11:45:32.767478 30, 0x0, End_B0=30 End_B1=30
9063 11:45:32.767553 31, 0x5151, End_B0=30 End_B1=30
9064 11:45:32.771041 Byte0 end_step=30 best_step=27
9065 11:45:32.773955 Byte1 end_step=30 best_step=27
9066 11:45:32.777367 Byte0 TX OE(2T, 0.5T) = (3, 3)
9067 11:45:32.780798 Byte1 TX OE(2T, 0.5T) = (3, 3)
9068 11:45:32.780873
9069 11:45:32.780937
9070 11:45:32.787455 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9071 11:45:32.790937 CH1 RK1: MR19=303, MR18=E1B
9072 11:45:32.797615 CH1_RK1: MR19=0x303, MR18=0xE1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9073 11:45:32.801151 [RxdqsGatingPostProcess] freq 1600
9074 11:45:32.807467 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9075 11:45:32.807552 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 11:45:32.810989 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 11:45:32.813893 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 11:45:32.817364 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 11:45:32.820303 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 11:45:32.823811 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 11:45:32.827259 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 11:45:32.830690 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 11:45:32.834112 Pre-setting of DQS Precalculation
9084 11:45:32.836946 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9085 11:45:32.847160 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9086 11:45:32.853510 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 11:45:32.853592
9088 11:45:32.853656
9089 11:45:32.857209 [Calibration Summary] 3200 Mbps
9090 11:45:32.857281 CH 0, Rank 0
9091 11:45:32.860151 SW Impedance : PASS
9092 11:45:32.860274 DUTY Scan : NO K
9093 11:45:32.863641 ZQ Calibration : PASS
9094 11:45:32.867196 Jitter Meter : NO K
9095 11:45:32.867293 CBT Training : PASS
9096 11:45:32.870218 Write leveling : PASS
9097 11:45:32.873742 RX DQS gating : PASS
9098 11:45:32.873814 RX DQ/DQS(RDDQC) : PASS
9099 11:45:32.876730 TX DQ/DQS : PASS
9100 11:45:32.880417 RX DATLAT : PASS
9101 11:45:32.880490 RX DQ/DQS(Engine): PASS
9102 11:45:32.883322 TX OE : PASS
9103 11:45:32.883419 All Pass.
9104 11:45:32.883508
9105 11:45:32.886697 CH 0, Rank 1
9106 11:45:32.886771 SW Impedance : PASS
9107 11:45:32.890360 DUTY Scan : NO K
9108 11:45:32.893214 ZQ Calibration : PASS
9109 11:45:32.893287 Jitter Meter : NO K
9110 11:45:32.896889 CBT Training : PASS
9111 11:45:32.896964 Write leveling : PASS
9112 11:45:32.900399 RX DQS gating : PASS
9113 11:45:32.903657 RX DQ/DQS(RDDQC) : PASS
9114 11:45:32.903725 TX DQ/DQS : PASS
9115 11:45:32.906709 RX DATLAT : PASS
9116 11:45:32.910059 RX DQ/DQS(Engine): PASS
9117 11:45:32.910134 TX OE : PASS
9118 11:45:32.913363 All Pass.
9119 11:45:32.913442
9120 11:45:32.913503 CH 1, Rank 0
9121 11:45:32.916350 SW Impedance : PASS
9122 11:45:32.916451 DUTY Scan : NO K
9123 11:45:32.919802 ZQ Calibration : PASS
9124 11:45:32.923371 Jitter Meter : NO K
9125 11:45:32.923453 CBT Training : PASS
9126 11:45:32.926323 Write leveling : PASS
9127 11:45:32.929654 RX DQS gating : PASS
9128 11:45:32.929736 RX DQ/DQS(RDDQC) : PASS
9129 11:45:32.933268 TX DQ/DQS : PASS
9130 11:45:32.936707 RX DATLAT : PASS
9131 11:45:32.936786 RX DQ/DQS(Engine): PASS
9132 11:45:32.939663 TX OE : PASS
9133 11:45:32.939753 All Pass.
9134 11:45:32.939815
9135 11:45:32.943033 CH 1, Rank 1
9136 11:45:32.943103 SW Impedance : PASS
9137 11:45:32.946956 DUTY Scan : NO K
9138 11:45:32.949814 ZQ Calibration : PASS
9139 11:45:32.949914 Jitter Meter : NO K
9140 11:45:32.953253 CBT Training : PASS
9141 11:45:32.953332 Write leveling : PASS
9142 11:45:32.956519 RX DQS gating : PASS
9143 11:45:32.959956 RX DQ/DQS(RDDQC) : PASS
9144 11:45:32.960034 TX DQ/DQS : PASS
9145 11:45:32.963140 RX DATLAT : PASS
9146 11:45:32.966399 RX DQ/DQS(Engine): PASS
9147 11:45:32.966469 TX OE : PASS
9148 11:45:32.969878 All Pass.
9149 11:45:32.969950
9150 11:45:32.970010 DramC Write-DBI on
9151 11:45:32.973337 PER_BANK_REFRESH: Hybrid Mode
9152 11:45:32.976337 TX_TRACKING: ON
9153 11:45:32.982782 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9154 11:45:32.992868 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9155 11:45:32.999334 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9156 11:45:33.002704 [FAST_K] Save calibration result to emmc
9157 11:45:33.006300 sync common calibartion params.
9158 11:45:33.006383 sync cbt_mode0:1, 1:1
9159 11:45:33.009263 dram_init: ddr_geometry: 2
9160 11:45:33.012722 dram_init: ddr_geometry: 2
9161 11:45:33.015881 dram_init: ddr_geometry: 2
9162 11:45:33.015964 0:dram_rank_size:100000000
9163 11:45:33.019437 1:dram_rank_size:100000000
9164 11:45:33.025772 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9165 11:45:33.025897 DFS_SHUFFLE_HW_MODE: ON
9166 11:45:33.032447 dramc_set_vcore_voltage set vcore to 725000
9167 11:45:33.032529 Read voltage for 1600, 0
9168 11:45:33.035897 Vio18 = 0
9169 11:45:33.035979 Vcore = 725000
9170 11:45:33.036043 Vdram = 0
9171 11:45:33.036104 Vddq = 0
9172 11:45:33.039441 Vmddr = 0
9173 11:45:33.039525 switch to 3200 Mbps bootup
9174 11:45:33.042429 [DramcRunTimeConfig]
9175 11:45:33.042554 PHYPLL
9176 11:45:33.045534 DPM_CONTROL_AFTERK: ON
9177 11:45:33.045623 PER_BANK_REFRESH: ON
9178 11:45:33.048994 REFRESH_OVERHEAD_REDUCTION: ON
9179 11:45:33.052436 CMD_PICG_NEW_MODE: OFF
9180 11:45:33.052560 XRTWTW_NEW_MODE: ON
9181 11:45:33.055723 XRTRTR_NEW_MODE: ON
9182 11:45:33.055804 TX_TRACKING: ON
9183 11:45:33.058869 RDSEL_TRACKING: OFF
9184 11:45:33.062193 DQS Precalculation for DVFS: ON
9185 11:45:33.062276 RX_TRACKING: OFF
9186 11:45:33.065672 HW_GATING DBG: ON
9187 11:45:33.065754 ZQCS_ENABLE_LP4: ON
9188 11:45:33.069057 RX_PICG_NEW_MODE: ON
9189 11:45:33.072215 TX_PICG_NEW_MODE: ON
9190 11:45:33.072311 ENABLE_RX_DCM_DPHY: ON
9191 11:45:33.076090 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9192 11:45:33.078947 DUMMY_READ_FOR_TRACKING: OFF
9193 11:45:33.082390 !!! SPM_CONTROL_AFTERK: OFF
9194 11:45:33.082485 !!! SPM could not control APHY
9195 11:45:33.085377 IMPEDANCE_TRACKING: ON
9196 11:45:33.085462 TEMP_SENSOR: ON
9197 11:45:33.089015 HW_SAVE_FOR_SR: OFF
9198 11:45:33.092706 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9199 11:45:33.095677 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9200 11:45:33.099248 Read ODT Tracking: ON
9201 11:45:33.099330 Refresh Rate DeBounce: ON
9202 11:45:33.102086 DFS_NO_QUEUE_FLUSH: ON
9203 11:45:33.105498 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9204 11:45:33.108805 ENABLE_DFS_RUNTIME_MRW: OFF
9205 11:45:33.108888 DDR_RESERVE_NEW_MODE: ON
9206 11:45:33.112179 MR_CBT_SWITCH_FREQ: ON
9207 11:45:33.115667 =========================
9208 11:45:33.133205 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9209 11:45:33.136788 dram_init: ddr_geometry: 2
9210 11:45:33.154746 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9211 11:45:33.158096 dram_init: dram init end (result: 0)
9212 11:45:33.164688 DRAM-K: Full calibration passed in 24521 msecs
9213 11:45:33.168324 MRC: failed to locate region type 0.
9214 11:45:33.168407 DRAM rank0 size:0x100000000,
9215 11:45:33.171677 DRAM rank1 size=0x100000000
9216 11:45:33.181208 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9217 11:45:33.187978 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9218 11:45:33.194442 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9219 11:45:33.201492 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9220 11:45:33.204421 DRAM rank0 size:0x100000000,
9221 11:45:33.207977 DRAM rank1 size=0x100000000
9222 11:45:33.208059 CBMEM:
9223 11:45:33.211311 IMD: root @ 0xfffff000 254 entries.
9224 11:45:33.214647 IMD: root @ 0xffffec00 62 entries.
9225 11:45:33.217878 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9226 11:45:33.220889 WARNING: RO_VPD is uninitialized or empty.
9227 11:45:33.227307 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9228 11:45:33.234978 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9229 11:45:33.247339 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9230 11:45:33.259048 BS: romstage times (exec / console): total (unknown) / 23995 ms
9231 11:45:33.259133
9232 11:45:33.259198
9233 11:45:33.268788 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9234 11:45:33.272257 ARM64: Exception handlers installed.
9235 11:45:33.275503 ARM64: Testing exception
9236 11:45:33.278709 ARM64: Done test exception
9237 11:45:33.278791 Enumerating buses...
9238 11:45:33.282240 Show all devs... Before device enumeration.
9239 11:45:33.285665 Root Device: enabled 1
9240 11:45:33.288610 CPU_CLUSTER: 0: enabled 1
9241 11:45:33.288692 CPU: 00: enabled 1
9242 11:45:33.292087 Compare with tree...
9243 11:45:33.292168 Root Device: enabled 1
9244 11:45:33.295542 CPU_CLUSTER: 0: enabled 1
9245 11:45:33.299110 CPU: 00: enabled 1
9246 11:45:33.299191 Root Device scanning...
9247 11:45:33.302097 scan_static_bus for Root Device
9248 11:45:33.305600 CPU_CLUSTER: 0 enabled
9249 11:45:33.308596 scan_static_bus for Root Device done
9250 11:45:33.312129 scan_bus: bus Root Device finished in 8 msecs
9251 11:45:33.312250 done
9252 11:45:33.318922 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9253 11:45:33.321859 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9254 11:45:33.328670 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9255 11:45:33.332222 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9256 11:45:33.335152 Allocating resources...
9257 11:45:33.338763 Reading resources...
9258 11:45:33.341663 Root Device read_resources bus 0 link: 0
9259 11:45:33.341745 DRAM rank0 size:0x100000000,
9260 11:45:33.345183 DRAM rank1 size=0x100000000
9261 11:45:33.348406 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9262 11:45:33.351927 CPU: 00 missing read_resources
9263 11:45:33.354944 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9264 11:45:33.361848 Root Device read_resources bus 0 link: 0 done
9265 11:45:33.361931 Done reading resources.
9266 11:45:33.368274 Show resources in subtree (Root Device)...After reading.
9267 11:45:33.372107 Root Device child on link 0 CPU_CLUSTER: 0
9268 11:45:33.375214 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 11:45:33.384894 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 11:45:33.385003 CPU: 00
9271 11:45:33.388349 Root Device assign_resources, bus 0 link: 0
9272 11:45:33.391725 CPU_CLUSTER: 0 missing set_resources
9273 11:45:33.398410 Root Device assign_resources, bus 0 link: 0 done
9274 11:45:33.398493 Done setting resources.
9275 11:45:33.404621 Show resources in subtree (Root Device)...After assigning values.
9276 11:45:33.408162 Root Device child on link 0 CPU_CLUSTER: 0
9277 11:45:33.411188 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 11:45:33.421652 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 11:45:33.421736 CPU: 00
9280 11:45:33.424485 Done allocating resources.
9281 11:45:33.427936 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9282 11:45:33.431293 Enabling resources...
9283 11:45:33.431380 done.
9284 11:45:33.437768 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9285 11:45:33.437850 Initializing devices...
9286 11:45:33.441289 Root Device init
9287 11:45:33.441378 init hardware done!
9288 11:45:33.444188 0x00000018: ctrlr->caps
9289 11:45:33.447710 52.000 MHz: ctrlr->f_max
9290 11:45:33.447814 0.400 MHz: ctrlr->f_min
9291 11:45:33.451096 0x40ff8080: ctrlr->voltages
9292 11:45:33.454275 sclk: 390625
9293 11:45:33.454360 Bus Width = 1
9294 11:45:33.454424 sclk: 390625
9295 11:45:33.457558 Bus Width = 1
9296 11:45:33.457640 Early init status = 3
9297 11:45:33.464101 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9298 11:45:33.467713 in-header: 03 fc 00 00 01 00 00 00
9299 11:45:33.470695 in-data: 00
9300 11:45:33.473995 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9301 11:45:33.478702 in-header: 03 fd 00 00 00 00 00 00
9302 11:45:33.482061 in-data:
9303 11:45:33.485251 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9304 11:45:33.489571 in-header: 03 fc 00 00 01 00 00 00
9305 11:45:33.492617 in-data: 00
9306 11:45:33.495765 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9307 11:45:33.501848 in-header: 03 fd 00 00 00 00 00 00
9308 11:45:33.505221 in-data:
9309 11:45:33.508381 [SSUSB] Setting up USB HOST controller...
9310 11:45:33.511730 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 11:45:33.514759 [SSUSB] phy power-on done.
9312 11:45:33.518292 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 11:45:33.524762 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 11:45:33.528113 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 11:45:33.534518 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 11:45:33.541386 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9317 11:45:33.547740 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 11:45:33.554209 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 11:45:33.561406 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9320 11:45:33.564206 SPM: binary array size = 0x9dc
9321 11:45:33.567731 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 11:45:33.574208 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 11:45:33.581182 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 11:45:33.587680 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 11:45:33.590625 configure_display: Starting display init
9326 11:45:33.624852 anx7625_power_on_init: Init interface.
9327 11:45:33.628265 anx7625_disable_pd_protocol: Disabled PD feature.
9328 11:45:33.631694 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 11:45:33.659499 anx7625_start_dp_work: Secure OCM version=00
9330 11:45:33.662261 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 11:45:33.677370 sp_tx_get_edid_block: EDID Block = 1
9332 11:45:33.780106 Extracted contents:
9333 11:45:33.783053 header: 00 ff ff ff ff ff ff 00
9334 11:45:33.786566 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 11:45:33.789609 version: 01 04
9336 11:45:33.793058 basic params: 95 1f 11 78 0a
9337 11:45:33.796449 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 11:45:33.799660 established: 00 00 00
9339 11:45:33.806081 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 11:45:33.809679 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 11:45:33.816162 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 11:45:33.822922 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 11:45:33.829199 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 11:45:33.832672 extensions: 00
9345 11:45:33.832745 checksum: fb
9346 11:45:33.832807
9347 11:45:33.835739 Manufacturer: IVO Model 57d Serial Number 0
9348 11:45:33.839331 Made week 0 of 2020
9349 11:45:33.842737 EDID version: 1.4
9350 11:45:33.842814 Digital display
9351 11:45:33.845939 6 bits per primary color channel
9352 11:45:33.846020 DisplayPort interface
9353 11:45:33.849231 Maximum image size: 31 cm x 17 cm
9354 11:45:33.852779 Gamma: 220%
9355 11:45:33.852852 Check DPMS levels
9356 11:45:33.856157 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 11:45:33.862635 First detailed timing is preferred timing
9358 11:45:33.862715 Established timings supported:
9359 11:45:33.866070 Standard timings supported:
9360 11:45:33.869048 Detailed timings
9361 11:45:33.872602 Hex of detail: 383680a07038204018303c0035ae10000019
9362 11:45:33.879292 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 11:45:33.882469 0780 0798 07c8 0820 hborder 0
9364 11:45:33.885933 0438 043b 0447 0458 vborder 0
9365 11:45:33.888849 -hsync -vsync
9366 11:45:33.888924 Did detailed timing
9367 11:45:33.895854 Hex of detail: 000000000000000000000000000000000000
9368 11:45:33.898778 Manufacturer-specified data, tag 0
9369 11:45:33.902079 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 11:45:33.905676 ASCII string: InfoVision
9371 11:45:33.908944 Hex of detail: 000000fe00523134304e574635205248200a
9372 11:45:33.912381 ASCII string: R140NWF5 RH
9373 11:45:33.912453 Checksum
9374 11:45:33.915296 Checksum: 0xfb (valid)
9375 11:45:33.918803 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 11:45:33.922162 DSI data_rate: 832800000 bps
9377 11:45:33.929036 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 11:45:33.932040 anx7625_parse_edid: pixelclock(138800).
9379 11:45:33.935519 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 11:45:33.939030 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 11:45:33.942249 anx7625_dsi_config: config dsi.
9382 11:45:33.948909 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 11:45:33.962266 anx7625_dsi_config: success to config DSI
9384 11:45:33.965519 anx7625_dp_start: MIPI phy setup OK.
9385 11:45:33.968597 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 11:45:33.971946 mtk_ddp_mode_set invalid vrefresh 60
9387 11:45:33.974940 main_disp_path_setup
9388 11:45:33.975014 ovl_layer_smi_id_en
9389 11:45:33.978361 ovl_layer_smi_id_en
9390 11:45:33.978433 ccorr_config
9391 11:45:33.978493 aal_config
9392 11:45:33.981688 gamma_config
9393 11:45:33.981758 postmask_config
9394 11:45:33.984912 dither_config
9395 11:45:33.988245 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 11:45:33.995214 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 11:45:33.998172 Root Device init finished in 554 msecs
9398 11:45:34.001675 CPU_CLUSTER: 0 init
9399 11:45:34.008156 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 11:45:34.011471 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 11:45:34.014687 APU_MBOX 0x190000b0 = 0x10001
9402 11:45:34.018052 APU_MBOX 0x190001b0 = 0x10001
9403 11:45:34.021567 APU_MBOX 0x190005b0 = 0x10001
9404 11:45:34.025038 APU_MBOX 0x190006b0 = 0x10001
9405 11:45:34.028251 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 11:45:34.040564 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9407 11:45:34.053220 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 11:45:34.059976 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 11:45:34.071837 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9410 11:45:34.081038 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 11:45:34.083979 CPU_CLUSTER: 0 init finished in 81 msecs
9412 11:45:34.087364 Devices initialized
9413 11:45:34.090680 Show all devs... After init.
9414 11:45:34.090762 Root Device: enabled 1
9415 11:45:34.094042 CPU_CLUSTER: 0: enabled 1
9416 11:45:34.096896 CPU: 00: enabled 1
9417 11:45:34.100540 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9418 11:45:34.103480 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 11:45:34.106941 ELOG: NV offset 0x57f000 size 0x1000
9420 11:45:34.114061 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9421 11:45:34.120271 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 11:45:34.123568 ELOG: Event(17) added with size 13 at 2023-11-24 11:45:34 UTC
9423 11:45:34.130226 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 11:45:34.133588 in-header: 03 92 00 00 2c 00 00 00
9425 11:45:34.143443 in-data: cd 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 11:45:34.150079 ELOG: Event(A1) added with size 10 at 2023-11-24 11:45:34 UTC
9427 11:45:34.156686 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 11:45:34.162974 ELOG: Event(A0) added with size 9 at 2023-11-24 11:45:34 UTC
9429 11:45:34.166404 elog_add_boot_reason: Logged dev mode boot
9430 11:45:34.172827 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9431 11:45:34.172910 Finalize devices...
9432 11:45:34.176562 Devices finalized
9433 11:45:34.179893 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 11:45:34.183109 Writing coreboot table at 0xffe64000
9435 11:45:34.186363 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 11:45:34.193136 1. 0000000040000000-00000000400fffff: RAM
9437 11:45:34.196323 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 11:45:34.199531 3. 000000004032b000-00000000545fffff: RAM
9439 11:45:34.202617 4. 0000000054600000-000000005465ffff: BL31
9440 11:45:34.206058 5. 0000000054660000-00000000ffe63fff: RAM
9441 11:45:34.213150 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 11:45:34.216088 7. 0000000100000000-000000023fffffff: RAM
9443 11:45:34.219582 Passing 5 GPIOs to payload:
9444 11:45:34.223089 NAME | PORT | POLARITY | VALUE
9445 11:45:34.229470 EC in RW | 0x000000aa | low | undefined
9446 11:45:34.232709 EC interrupt | 0x00000005 | low | undefined
9447 11:45:34.235853 TPM interrupt | 0x000000ab | high | undefined
9448 11:45:34.242757 SD card detect | 0x00000011 | high | undefined
9449 11:45:34.245725 speaker enable | 0x00000093 | high | undefined
9450 11:45:34.249111 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 11:45:34.252694 in-header: 03 f9 00 00 02 00 00 00
9452 11:45:34.255647 in-data: 02 00
9453 11:45:34.259139 ADC[4]: Raw value=892231 ID=7
9454 11:45:34.259222 ADC[3]: Raw value=212700 ID=1
9455 11:45:34.262325 RAM Code: 0x71
9456 11:45:34.265760 ADC[6]: Raw value=74722 ID=0
9457 11:45:34.265843 ADC[5]: Raw value=211960 ID=1
9458 11:45:34.269183 SKU Code: 0x1
9459 11:45:34.275695 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1593
9460 11:45:34.275777 coreboot table: 964 bytes.
9461 11:45:34.279101 IMD ROOT 0. 0xfffff000 0x00001000
9462 11:45:34.282587 IMD SMALL 1. 0xffffe000 0x00001000
9463 11:45:34.285908 RO MCACHE 2. 0xffffc000 0x00001104
9464 11:45:34.288886 CONSOLE 3. 0xfff7c000 0x00080000
9465 11:45:34.292392 FMAP 4. 0xfff7b000 0x00000452
9466 11:45:34.295957 TIME STAMP 5. 0xfff7a000 0x00000910
9467 11:45:34.299306 VBOOT WORK 6. 0xfff66000 0x00014000
9468 11:45:34.302317 RAMOOPS 7. 0xffe66000 0x00100000
9469 11:45:34.305522 COREBOOT 8. 0xffe64000 0x00002000
9470 11:45:34.308757 IMD small region:
9471 11:45:34.312388 IMD ROOT 0. 0xffffec00 0x00000400
9472 11:45:34.315660 VPD 1. 0xffffeb80 0x0000006c
9473 11:45:34.318733 MMC STATUS 2. 0xffffeb60 0x00000004
9474 11:45:34.321986 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 11:45:34.325413 Probing TPM: done!
9476 11:45:34.329052 Connected to device vid:did:rid of 1ae0:0028:00
9477 11:45:34.339852 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9478 11:45:34.343016 Initialized TPM device CR50 revision 0
9479 11:45:34.346789 Checking cr50 for pending updates
9480 11:45:34.350916 Reading cr50 TPM mode
9481 11:45:34.359146 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 11:45:34.365593 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 11:45:34.406120 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9484 11:45:34.409003 Checking segment from ROM address 0x40100000
9485 11:45:34.412442 Checking segment from ROM address 0x4010001c
9486 11:45:34.418954 Loading segment from ROM address 0x40100000
9487 11:45:34.419039 code (compression=0)
9488 11:45:34.429097 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 11:45:34.435596 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 11:45:34.435681 it's not compressed!
9491 11:45:34.442455 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 11:45:34.448640 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 11:45:34.466264 Loading segment from ROM address 0x4010001c
9494 11:45:34.466351 Entry Point 0x80000000
9495 11:45:34.469784 Loaded segments
9496 11:45:34.473188 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9497 11:45:34.479998 Jumping to boot code at 0x80000000(0xffe64000)
9498 11:45:34.486396 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 11:45:34.492870 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 11:45:34.500986 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9501 11:45:34.503985 Checking segment from ROM address 0x40100000
9502 11:45:34.507523 Checking segment from ROM address 0x4010001c
9503 11:45:34.513904 Loading segment from ROM address 0x40100000
9504 11:45:34.513987 code (compression=1)
9505 11:45:34.520854 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 11:45:34.530703 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 11:45:34.530794 using LZMA
9508 11:45:34.539135 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 11:45:34.545955 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 11:45:34.549196 Loading segment from ROM address 0x4010001c
9511 11:45:34.549279 Entry Point 0x54601000
9512 11:45:34.552521 Loaded segments
9513 11:45:34.555466 NOTICE: MT8192 bl31_setup
9514 11:45:34.562796 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 11:45:34.566309 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 11:45:34.569254 WARNING: region 0:
9517 11:45:34.572779 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 11:45:34.572861 WARNING: region 1:
9519 11:45:34.579273 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 11:45:34.582533 WARNING: region 2:
9521 11:45:34.586057 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 11:45:34.589088 WARNING: region 3:
9523 11:45:34.592595 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 11:45:34.595890 WARNING: region 4:
9525 11:45:34.602756 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 11:45:34.602842 WARNING: region 5:
9527 11:45:34.605713 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 11:45:34.609227 WARNING: region 6:
9529 11:45:34.612798 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 11:45:34.615732 WARNING: region 7:
9531 11:45:34.619180 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 11:45:34.625635 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 11:45:34.629164 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 11:45:34.632659 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 11:45:34.639241 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 11:45:34.642732 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 11:45:34.646352 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 11:45:34.652848 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 11:45:34.656043 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 11:45:34.662481 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 11:45:34.666097 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 11:45:34.669139 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 11:45:34.675804 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 11:45:34.679335 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 11:45:34.682903 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 11:45:34.689377 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 11:45:34.692691 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 11:45:34.696042 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 11:45:34.702742 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 11:45:34.705740 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 11:45:34.712572 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 11:45:34.716116 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 11:45:34.719110 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 11:45:34.726027 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 11:45:34.729048 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 11:45:34.735981 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 11:45:34.739372 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 11:45:34.742925 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 11:45:34.749281 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 11:45:34.752857 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 11:45:34.759230 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 11:45:34.762644 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 11:45:34.766050 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 11:45:34.772784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 11:45:34.775948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 11:45:34.779472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 11:45:34.782454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 11:45:34.789445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 11:45:34.792388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 11:45:34.795824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 11:45:34.799421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 11:45:34.805705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 11:45:34.809255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 11:45:34.812548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 11:45:34.815694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 11:45:34.822460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 11:45:34.825656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 11:45:34.829191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 11:45:34.832649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 11:45:34.838985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 11:45:34.842413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 11:45:34.848967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 11:45:34.852501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 11:45:34.859387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 11:45:34.862290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 11:45:34.865660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 11:45:34.872642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 11:45:34.875597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 11:45:34.882140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 11:45:34.885464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 11:45:34.892558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 11:45:34.895795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 11:45:34.899182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 11:45:34.905776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 11:45:34.909133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 11:45:34.915615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 11:45:34.919142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 11:45:34.925701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 11:45:34.928974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 11:45:34.932575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 11:45:34.939250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 11:45:34.942773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 11:45:34.949404 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 11:45:34.952362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 11:45:34.955969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 11:45:34.962314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 11:45:34.965781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 11:45:34.972644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 11:45:34.976084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 11:45:34.982557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 11:45:34.986112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 11:45:34.992458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 11:45:34.995853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 11:45:34.999097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 11:45:35.005657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 11:45:35.009344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 11:45:35.016165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 11:45:35.019183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 11:45:35.025661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 11:45:35.029238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 11:45:35.032670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 11:45:35.039112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 11:45:35.042738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 11:45:35.048858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 11:45:35.052645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 11:45:35.058790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 11:45:35.062368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 11:45:35.065936 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 11:45:35.072172 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 11:45:35.075596 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 11:45:35.079071 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 11:45:35.082541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 11:45:35.089055 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 11:45:35.092129 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 11:45:35.098831 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 11:45:35.102358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 11:45:35.106029 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 11:45:35.112463 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 11:45:35.115657 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 11:45:35.122140 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 11:45:35.125705 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 11:45:35.129120 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 11:45:35.135901 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 11:45:35.138894 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 11:45:35.145881 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 11:45:35.149408 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 11:45:35.152669 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 11:45:35.155895 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 11:45:35.162608 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 11:45:35.165894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 11:45:35.169372 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 11:45:35.175630 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 11:45:35.179068 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 11:45:35.182532 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 11:45:35.185424 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 11:45:35.192337 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 11:45:35.195941 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 11:45:35.202491 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 11:45:35.205378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 11:45:35.208929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 11:45:35.215384 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 11:45:35.218915 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 11:45:35.222055 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 11:45:35.228790 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 11:45:35.232078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 11:45:35.239228 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 11:45:35.242173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 11:45:35.245612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 11:45:35.252748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 11:45:35.255592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 11:45:35.262630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 11:45:35.265656 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 11:45:35.269098 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 11:45:35.275593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 11:45:35.279243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 11:45:35.282653 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 11:45:35.289201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 11:45:35.292715 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 11:45:35.299373 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 11:45:35.302353 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 11:45:35.305769 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 11:45:35.312736 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 11:45:35.315699 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 11:45:35.322744 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 11:45:35.325634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 11:45:35.328876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 11:45:35.336059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 11:45:35.339312 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 11:45:35.342491 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 11:45:35.348960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 11:45:35.352607 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 11:45:35.359116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 11:45:35.362144 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 11:45:35.365624 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 11:45:35.372115 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 11:45:35.375575 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 11:45:35.382373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 11:45:35.385663 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 11:45:35.388621 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 11:45:35.395279 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 11:45:35.398774 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 11:45:35.405478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 11:45:35.408388 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 11:45:35.411925 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 11:45:35.418425 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 11:45:35.422000 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 11:45:35.428436 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 11:45:35.431956 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 11:45:35.435349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 11:45:35.441697 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 11:45:35.445108 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 11:45:35.448604 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 11:45:35.454756 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 11:45:35.458164 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 11:45:35.465224 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 11:45:35.468208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 11:45:35.471732 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 11:45:35.478600 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 11:45:35.481923 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 11:45:35.488329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 11:45:35.491664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 11:45:35.497971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 11:45:35.501350 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 11:45:35.504572 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 11:45:35.511203 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 11:45:35.514991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 11:45:35.521230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 11:45:35.524752 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 11:45:35.527666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 11:45:35.534752 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 11:45:35.538312 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 11:45:35.544614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 11:45:35.547869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 11:45:35.554838 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 11:45:35.558030 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 11:45:35.561270 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 11:45:35.568088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 11:45:35.571160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 11:45:35.577579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 11:45:35.581166 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 11:45:35.587875 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 11:45:35.591097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 11:45:35.594593 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 11:45:35.601022 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 11:45:35.604333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 11:45:35.611508 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 11:45:35.614263 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 11:45:35.617965 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 11:45:35.624380 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 11:45:35.627750 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 11:45:35.634546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 11:45:35.637630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 11:45:35.641149 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 11:45:35.647741 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 11:45:35.651246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 11:45:35.657542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 11:45:35.660804 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 11:45:35.667286 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 11:45:35.670567 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 11:45:35.674155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 11:45:35.680563 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 11:45:35.684020 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 11:45:35.687606 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 11:45:35.690511 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 11:45:35.697327 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 11:45:35.700711 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 11:45:35.704184 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 11:45:35.710935 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 11:45:35.714530 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 11:45:35.717286 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 11:45:35.724271 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 11:45:35.727456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 11:45:35.734204 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 11:45:35.737620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 11:45:35.740920 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 11:45:35.747226 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 11:45:35.750843 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 11:45:35.753936 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 11:45:35.760332 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 11:45:35.763828 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 11:45:35.766947 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 11:45:35.773456 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 11:45:35.777172 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 11:45:35.783606 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 11:45:35.786685 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 11:45:35.790007 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 11:45:35.796521 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 11:45:35.799999 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 11:45:35.806620 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 11:45:35.809965 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 11:45:35.813225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 11:45:35.820172 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 11:45:35.823114 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 11:45:35.826647 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 11:45:35.833081 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 11:45:35.836525 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 11:45:35.839815 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 11:45:35.845971 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 11:45:35.849679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 11:45:35.852648 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 11:45:35.859704 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 11:45:35.862858 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 11:45:35.866348 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 11:45:35.868993 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 11:45:35.872548 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 11:45:35.879079 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 11:45:35.882658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 11:45:35.886087 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 11:45:35.892687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 11:45:35.895594 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 11:45:35.899241 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 11:45:35.905554 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 11:45:35.909070 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 11:45:35.912325 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 11:45:35.919051 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 11:45:35.922262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 11:45:35.928693 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 11:45:35.932238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 11:45:35.935246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 11:45:35.942265 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 11:45:35.945149 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 11:45:35.952280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 11:45:35.955025 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 11:45:35.958491 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 11:45:35.965381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 11:45:35.968336 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 11:45:35.974846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 11:45:35.978365 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 11:45:35.981960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 11:45:35.988319 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 11:45:35.991864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 11:45:35.998206 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 11:45:36.001517 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 11:45:36.007974 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 11:45:36.011724 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 11:45:36.014799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 11:45:36.021702 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 11:45:36.024863 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 11:45:36.031044 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 11:45:36.034351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 11:45:36.037975 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 11:45:36.044540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 11:45:36.047492 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 11:45:36.054443 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 11:45:36.057590 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 11:45:36.064293 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 11:45:36.067671 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 11:45:36.071130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 11:45:36.077515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 11:45:36.080534 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 11:45:36.087567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 11:45:36.090630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 11:45:36.094102 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 11:45:36.100562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 11:45:36.104117 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 11:45:36.110500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 11:45:36.113675 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 11:45:36.120375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 11:45:36.123725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 11:45:36.127136 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 11:45:36.133617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 11:45:36.136933 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 11:45:36.143766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 11:45:36.147033 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 11:45:36.150104 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 11:45:36.156735 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 11:45:36.160083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 11:45:36.166688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 11:45:36.170188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 11:45:36.173591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 11:45:36.179858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 11:45:36.183231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 11:45:36.189840 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 11:45:36.193400 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 11:45:36.199807 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 11:45:36.203485 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 11:45:36.206560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 11:45:36.213180 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 11:45:36.216733 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 11:45:36.222958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 11:45:36.226114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 11:45:36.232371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 11:45:36.235858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 11:45:36.239194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 11:45:36.245317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 11:45:36.248974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 11:45:36.255912 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 11:45:36.258681 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 11:45:36.262432 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 11:45:36.268614 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 11:45:36.272459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 11:45:36.278397 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 11:45:36.281904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 11:45:36.288315 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 11:45:36.291904 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 11:45:36.298353 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 11:45:36.301968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 11:45:36.305456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 11:45:36.312157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 11:45:36.315461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 11:45:36.322302 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 11:45:36.325225 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 11:45:36.332147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 11:45:36.335520 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 11:45:36.341825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 11:45:36.345193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 11:45:36.348355 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 11:45:36.355448 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 11:45:36.358685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 11:45:36.364931 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 11:45:36.368568 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 11:45:36.375008 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 11:45:36.378249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 11:45:36.381472 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 11:45:36.388245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 11:45:36.391540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 11:45:36.398046 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 11:45:36.401639 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 11:45:36.408026 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 11:45:36.411608 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 11:45:36.417829 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 11:45:36.421293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 11:45:36.424641 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 11:45:36.431084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 11:45:36.434586 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 11:45:36.440965 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 11:45:36.444427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 11:45:36.450868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 11:45:36.454314 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 11:45:36.460729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 11:45:36.464276 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 11:45:36.467458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 11:45:36.474493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 11:45:36.477319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 11:45:36.484466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 11:45:36.487290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 11:45:36.493665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 11:45:36.497294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 11:45:36.500386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 11:45:36.507327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 11:45:36.510329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 11:45:36.517206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 11:45:36.520100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 11:45:36.526960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 11:45:36.529988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 11:45:36.536855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 11:45:36.540129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 11:45:36.546391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 11:45:36.549731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 11:45:36.556648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 11:45:36.559981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 11:45:36.566593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 11:45:36.569550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 11:45:36.576585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 11:45:36.579595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 11:45:36.586201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 11:45:36.589810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 11:45:36.596098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 11:45:36.599410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 11:45:36.606158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 11:45:36.609426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 11:45:36.616453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 11:45:36.619335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 11:45:36.626395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 11:45:36.629805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 11:45:36.632710 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 11:45:36.636088 INFO: [APUAPC] vio 0
9968 11:45:36.642607 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 11:45:36.646090 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 11:45:36.649554 INFO: [APUAPC] D0_APC_0: 0x400510
9971 11:45:36.652350 INFO: [APUAPC] D0_APC_1: 0x0
9972 11:45:36.656246 INFO: [APUAPC] D0_APC_2: 0x1540
9973 11:45:36.659278 INFO: [APUAPC] D0_APC_3: 0x0
9974 11:45:36.662741 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 11:45:36.665875 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 11:45:36.669480 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 11:45:36.672933 INFO: [APUAPC] D1_APC_3: 0x0
9978 11:45:36.675882 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 11:45:36.679523 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 11:45:36.682380 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 11:45:36.685665 INFO: [APUAPC] D2_APC_3: 0x0
9982 11:45:36.689177 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 11:45:36.692774 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 11:45:36.695644 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 11:45:36.699519 INFO: [APUAPC] D3_APC_3: 0x0
9986 11:45:36.703002 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 11:45:36.705872 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 11:45:36.709058 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 11:45:36.709526 INFO: [APUAPC] D4_APC_3: 0x0
9990 11:45:36.715814 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 11:45:36.719387 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 11:45:36.722812 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 11:45:36.723278 INFO: [APUAPC] D5_APC_3: 0x0
9994 11:45:36.725865 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 11:45:36.729234 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 11:45:36.732640 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 11:45:36.736054 INFO: [APUAPC] D6_APC_3: 0x0
9998 11:45:36.739526 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 11:45:36.742428 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 11:45:36.745888 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 11:45:36.749329 INFO: [APUAPC] D7_APC_3: 0x0
10002 11:45:36.752182 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 11:45:36.755811 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 11:45:36.759202 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 11:45:36.762105 INFO: [APUAPC] D8_APC_3: 0x0
10006 11:45:36.765724 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 11:45:36.769277 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 11:45:36.772641 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 11:45:36.775658 INFO: [APUAPC] D9_APC_3: 0x0
10010 11:45:36.778934 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 11:45:36.782431 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 11:45:36.785768 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 11:45:36.788651 INFO: [APUAPC] D10_APC_3: 0x0
10014 11:45:36.791982 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 11:45:36.795297 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 11:45:36.798691 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 11:45:36.802219 INFO: [APUAPC] D11_APC_3: 0x0
10018 11:45:36.805240 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 11:45:36.808739 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 11:45:36.811719 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 11:45:36.815056 INFO: [APUAPC] D12_APC_3: 0x0
10022 11:45:36.818270 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 11:45:36.821738 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 11:45:36.825134 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 11:45:36.828606 INFO: [APUAPC] D13_APC_3: 0x0
10026 11:45:36.831572 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 11:45:36.834950 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 11:45:36.838326 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 11:45:36.841825 INFO: [APUAPC] D14_APC_3: 0x0
10030 11:45:36.845217 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 11:45:36.848107 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 11:45:36.851461 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 11:45:36.854863 INFO: [APUAPC] D15_APC_3: 0x0
10034 11:45:36.858508 INFO: [APUAPC] APC_CON: 0x4
10035 11:45:36.861407 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 11:45:36.864787 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 11:45:36.868129 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 11:45:36.871590 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 11:45:36.874579 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 11:45:36.874660 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 11:45:36.878085 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 11:45:36.881643 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 11:45:36.884896 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 11:45:36.887823 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 11:45:36.891686 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 11:45:36.895035 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 11:45:36.898028 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 11:45:36.901331 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 11:45:36.904593 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 11:45:36.908216 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 11:45:36.908317 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 11:45:36.911271 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 11:45:36.914870 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 11:45:36.918217 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 11:45:36.921389 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 11:45:36.924683 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 11:45:36.928232 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 11:45:36.931220 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 11:45:36.934532 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 11:45:36.938124 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 11:45:36.941499 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 11:45:36.944831 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 11:45:36.948297 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 11:45:36.951933 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 11:45:36.952443 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 11:45:36.955154 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 11:45:36.958321 INFO: [NOCDAPC] APC_CON: 0x4
10068 11:45:36.961331 INFO: [APUAPC] set_apusys_apc done
10069 11:45:36.964885 INFO: [DEVAPC] devapc_init done
10070 11:45:36.968534 INFO: GICv3 without legacy support detected.
10071 11:45:36.974827 INFO: ARM GICv3 driver initialized in EL3
10072 11:45:36.978275 INFO: Maximum SPI INTID supported: 639
10073 11:45:36.981326 INFO: BL31: Initializing runtime services
10074 11:45:36.988361 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 11:45:36.991804 INFO: SPM: enable CPC mode
10076 11:45:36.994662 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 11:45:37.001329 INFO: BL31: Preparing for EL3 exit to normal world
10078 11:45:37.005086 INFO: Entry point address = 0x80000000
10079 11:45:37.005547 INFO: SPSR = 0x8
10080 11:45:37.011267
10081 11:45:37.011728
10082 11:45:37.012089
10083 11:45:37.014679 Starting depthcharge on Spherion...
10084 11:45:37.015196
10085 11:45:37.015647 Wipe memory regions:
10086 11:45:37.015996
10087 11:45:37.018983 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10088 11:45:37.019593 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10089 11:45:37.020055 Setting prompt string to ['asurada:']
10090 11:45:37.020599 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10091 11:45:37.021456 [0x00000040000000, 0x00000054600000)
10092 11:45:37.140016
10093 11:45:37.140643 [0x00000054660000, 0x00000080000000)
10094 11:45:37.400631
10095 11:45:37.401174 [0x000000821a7280, 0x000000ffe64000)
10096 11:45:38.144849
10097 11:45:38.144999 [0x00000100000000, 0x00000240000000)
10098 11:45:40.033900
10099 11:45:40.037576 Initializing XHCI USB controller at 0x11200000.
10100 11:45:41.075310
10101 11:45:41.078535 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 11:45:41.078626
10103 11:45:41.078692
10104 11:45:41.078753
10105 11:45:41.079039 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 11:45:41.179386 asurada: tftpboot 192.168.201.1 12073986/tftp-deploy-j5rb8lmf/kernel/image.itb 12073986/tftp-deploy-j5rb8lmf/kernel/cmdline
10108 11:45:41.179599 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 11:45:41.179684 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10110 11:45:41.184243 tftpboot 192.168.201.1 12073986/tftp-deploy-j5rb8lmf/kernel/image.itbtp-deploy-j5rb8lmf/kernel/cmdline
10111 11:45:41.184330
10112 11:45:41.184395 Waiting for link
10113 11:45:41.345038
10114 11:45:41.345184 R8152: Initializing
10115 11:45:41.345251
10116 11:45:41.347782 Version 6 (ocp_data = 5c30)
10117 11:45:41.347865
10118 11:45:41.351249 R8152: Done initializing
10119 11:45:41.351335
10120 11:45:41.351401 Adding net device
10121 11:45:43.443422
10122 11:45:43.443574 done.
10123 11:45:43.443641
10124 11:45:43.443702 MAC: 00:24:32:30:78:ff
10125 11:45:43.443760
10126 11:45:43.446892 Sending DHCP discover... done.
10127 11:45:43.446977
10128 11:45:43.450271 Waiting for reply... done.
10129 11:45:43.450354
10130 11:45:43.453137 Sending DHCP request... done.
10131 11:45:43.453220
10132 11:45:43.456790 Waiting for reply... done.
10133 11:45:43.456871
10134 11:45:43.456974 My ip is 192.168.201.21
10135 11:45:43.457035
10136 11:45:43.460198 The DHCP server ip is 192.168.201.1
10137 11:45:43.460321
10138 11:45:43.466665 TFTP server IP predefined by user: 192.168.201.1
10139 11:45:43.466749
10140 11:45:43.473606 Bootfile predefined by user: 12073986/tftp-deploy-j5rb8lmf/kernel/image.itb
10141 11:45:43.473690
10142 11:45:43.476513 Sending tftp read request... done.
10143 11:45:43.476596
10144 11:45:43.480253 Waiting for the transfer...
10145 11:45:43.480337
10146 11:45:44.039763 00000000 ################################################################
10147 11:45:44.040029
10148 11:45:44.589661 00080000 ################################################################
10149 11:45:44.589819
10150 11:45:45.143839 00100000 ################################################################
10151 11:45:45.144014
10152 11:45:45.708113 00180000 ################################################################
10153 11:45:45.708320
10154 11:45:46.260532 00200000 ################################################################
10155 11:45:46.260688
10156 11:45:46.825830 00280000 ################################################################
10157 11:45:46.826025
10158 11:45:47.372966 00300000 ################################################################
10159 11:45:47.373101
10160 11:45:47.917059 00380000 ################################################################
10161 11:45:47.917202
10162 11:45:48.466164 00400000 ################################################################
10163 11:45:48.466320
10164 11:45:49.013893 00480000 ################################################################
10165 11:45:49.014027
10166 11:45:49.569946 00500000 ################################################################
10167 11:45:49.570492
10168 11:45:50.170196 00580000 ################################################################
10169 11:45:50.170370
10170 11:45:50.714337 00600000 ################################################################
10171 11:45:50.714471
10172 11:45:51.281518 00680000 ################################################################
10173 11:45:51.281654
10174 11:45:51.847556 00700000 ################################################################
10175 11:45:51.847702
10176 11:45:52.377335 00780000 ################################################################
10177 11:45:52.377472
10178 11:45:52.929086 00800000 ################################################################
10179 11:45:52.929230
10180 11:45:53.503236 00880000 ################################################################
10181 11:45:53.503395
10182 11:45:54.063973 00900000 ################################################################
10183 11:45:54.064160
10184 11:45:54.642675 00980000 ################################################################
10185 11:45:54.642820
10186 11:45:55.190246 00a00000 ################################################################
10187 11:45:55.190388
10188 11:45:55.729228 00a80000 ################################################################
10189 11:45:55.729363
10190 11:45:56.283994 00b00000 ################################################################
10191 11:45:56.284129
10192 11:45:56.839128 00b80000 ################################################################
10193 11:45:56.839266
10194 11:45:57.416137 00c00000 ################################################################
10195 11:45:57.416312
10196 11:45:58.001556 00c80000 ################################################################
10197 11:45:58.001696
10198 11:45:58.558641 00d00000 ################################################################
10199 11:45:58.558787
10200 11:45:59.134627 00d80000 ################################################################
10201 11:45:59.134773
10202 11:45:59.706689 00e00000 ################################################################
10203 11:45:59.706839
10204 11:46:00.302477 00e80000 ################################################################
10205 11:46:00.302625
10206 11:46:00.861925 00f00000 ################################################################
10207 11:46:00.862067
10208 11:46:01.422794 00f80000 ################################################################
10209 11:46:01.422937
10210 11:46:01.981900 01000000 ################################################################
10211 11:46:01.982038
10212 11:46:02.563283 01080000 ################################################################
10213 11:46:02.563432
10214 11:46:03.128739 01100000 ################################################################
10215 11:46:03.128877
10216 11:46:03.715102 01180000 ################################################################
10217 11:46:03.715281
10218 11:46:04.276504 01200000 ################################################################
10219 11:46:04.276670
10220 11:46:04.847553 01280000 ################################################################
10221 11:46:04.847691
10222 11:46:05.414725 01300000 ################################################################
10223 11:46:05.414872
10224 11:46:05.945943 01380000 ################################################################
10225 11:46:05.946081
10226 11:46:06.501153 01400000 ################################################################
10227 11:46:06.501292
10228 11:46:07.042195 01480000 ################################################################
10229 11:46:07.042359
10230 11:46:07.608781 01500000 ################################################################
10231 11:46:07.608916
10232 11:46:08.159814 01580000 ################################################################
10233 11:46:08.159983
10234 11:46:08.732430 01600000 ################################################################
10235 11:46:08.732631
10236 11:46:09.303893 01680000 ################################################################
10237 11:46:09.304029
10238 11:46:09.886673 01700000 ################################################################
10239 11:46:09.886816
10240 11:46:10.444225 01780000 ################################################################
10241 11:46:10.444365
10242 11:46:11.009536 01800000 ################################################################
10243 11:46:11.009705
10244 11:46:11.555984 01880000 ################################################################
10245 11:46:11.556146
10246 11:46:12.098921 01900000 ################################################################
10247 11:46:12.099076
10248 11:46:12.633978 01980000 ################################################################
10249 11:46:12.634173
10250 11:46:13.198596 01a00000 ################################################################
10251 11:46:13.198747
10252 11:46:13.735420 01a80000 ################################################################
10253 11:46:13.735574
10254 11:46:14.281917 01b00000 ################################################################
10255 11:46:14.282070
10256 11:46:14.338637 01b80000 ####### done.
10257 11:46:14.338767
10258 11:46:14.341737 The bootfile was 28890586 bytes long.
10259 11:46:14.341865
10260 11:46:14.345096 Sending tftp read request... done.
10261 11:46:14.345181
10262 11:46:14.345247 Waiting for the transfer...
10263 11:46:14.345309
10264 11:46:14.348437 00000000 # done.
10265 11:46:14.348523
10266 11:46:14.355123 Command line loaded dynamically from TFTP file: 12073986/tftp-deploy-j5rb8lmf/kernel/cmdline
10267 11:46:14.355208
10268 11:46:14.378247 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10269 11:46:14.378355
10270 11:46:14.378422 Loading FIT.
10271 11:46:14.378483
10272 11:46:14.381651 Image ramdisk-1 has 17793025 bytes.
10273 11:46:14.381749
10274 11:46:14.385134 Image fdt-1 has 47278 bytes.
10275 11:46:14.385260
10276 11:46:14.388028 Image kernel-1 has 11048246 bytes.
10277 11:46:14.388112
10278 11:46:14.397850 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10279 11:46:14.397946
10280 11:46:14.414592 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10281 11:46:14.414680
10282 11:46:14.421396 Choosing best match conf-1 for compat google,spherion-rev2.
10283 11:46:14.421474
10284 11:46:14.428836 Connected to device vid:did:rid of 1ae0:0028:00
10285 11:46:14.435767
10286 11:46:14.439010 tpm_get_response: command 0x17b, return code 0x0
10287 11:46:14.439126
10288 11:46:14.442120 ec_init: CrosEC protocol v3 supported (256, 248)
10289 11:46:14.446171
10290 11:46:14.449992 tpm_cleanup: add release locality here.
10291 11:46:14.450079
10292 11:46:14.450144 Shutting down all USB controllers.
10293 11:46:14.450203
10294 11:46:14.452865 Removing current net device
10295 11:46:14.452946
10296 11:46:14.459778 Exiting depthcharge with code 4 at timestamp: 66707707
10297 11:46:14.459909
10298 11:46:14.462793 LZMA decompressing kernel-1 to 0x821a6718
10299 11:46:14.462867
10300 11:46:14.466245 LZMA decompressing kernel-1 to 0x40000000
10301 11:46:15.855022
10302 11:46:15.855172 jumping to kernel
10303 11:46:15.855667 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10304 11:46:15.855773 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10305 11:46:15.855849 Setting prompt string to ['Linux version [0-9]']
10306 11:46:15.855928 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10307 11:46:15.856004 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10308 11:46:15.936949
10309 11:46:15.939907 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10310 11:46:15.943537 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10311 11:46:15.943661 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10312 11:46:15.943760 Setting prompt string to []
10313 11:46:15.943871 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10314 11:46:15.943971 Using line separator: #'\n'#
10315 11:46:15.944064 No login prompt set.
10316 11:46:15.944156 Parsing kernel messages
10317 11:46:15.944285 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10318 11:46:15.944389 [login-action] Waiting for messages, (timeout 00:03:46)
10319 11:46:15.963529 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10320 11:46:15.966519 [ 0.000000] random: crng init done
10321 11:46:15.973121 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10322 11:46:15.976579 [ 0.000000] efi: UEFI not found.
10323 11:46:15.983041 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10324 11:46:15.990025 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10325 11:46:15.999708 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10326 11:46:16.009453 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10327 11:46:16.016023 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10328 11:46:16.022846 [ 0.000000] printk: bootconsole [mtk8250] enabled
10329 11:46:16.029554 [ 0.000000] NUMA: No NUMA configuration found
10330 11:46:16.035817 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10331 11:46:16.039221 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10332 11:46:16.042671 [ 0.000000] Zone ranges:
10333 11:46:16.049327 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10334 11:46:16.052746 [ 0.000000] DMA32 empty
10335 11:46:16.059127 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10336 11:46:16.062635 [ 0.000000] Movable zone start for each node
10337 11:46:16.065956 [ 0.000000] Early memory node ranges
10338 11:46:16.072361 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10339 11:46:16.078878 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10340 11:46:16.085717 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10341 11:46:16.092035 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10342 11:46:16.095582 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10343 11:46:16.105384 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10344 11:46:16.161160 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10345 11:46:16.167745 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10346 11:46:16.174405 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10347 11:46:16.177728 [ 0.000000] psci: probing for conduit method from DT.
10348 11:46:16.184381 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10349 11:46:16.188078 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10350 11:46:16.194394 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10351 11:46:16.197413 [ 0.000000] psci: SMC Calling Convention v1.2
10352 11:46:16.204099 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10353 11:46:16.207529 [ 0.000000] Detected VIPT I-cache on CPU0
10354 11:46:16.214431 [ 0.000000] CPU features: detected: GIC system register CPU interface
10355 11:46:16.220719 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10356 11:46:16.227286 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10357 11:46:16.233981 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10358 11:46:16.240802 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10359 11:46:16.250363 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10360 11:46:16.253813 [ 0.000000] alternatives: applying boot alternatives
10361 11:46:16.260386 [ 0.000000] Fallback order for Node 0: 0
10362 11:46:16.267090 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10363 11:46:16.270545 [ 0.000000] Policy zone: Normal
10364 11:46:16.293371 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10365 11:46:16.303373 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10366 11:46:16.313683 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10367 11:46:16.323938 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10368 11:46:16.330544 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10369 11:46:16.333407 <6>[ 0.000000] software IO TLB: area num 8.
10370 11:46:16.390713 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10371 11:46:16.539948 <6>[ 0.000000] Memory: 7952240K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400528K reserved, 32768K cma-reserved)
10372 11:46:16.546392 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10373 11:46:16.552746 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10374 11:46:16.556411 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10375 11:46:16.562656 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10376 11:46:16.569280 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10377 11:46:16.572754 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10378 11:46:16.582590 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10379 11:46:16.589531 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10380 11:46:16.595973 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10381 11:46:16.602814 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10382 11:46:16.605674 <6>[ 0.000000] GICv3: 608 SPIs implemented
10383 11:46:16.609228 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10384 11:46:16.615763 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10385 11:46:16.619135 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10386 11:46:16.625795 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10387 11:46:16.639080 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10388 11:46:16.648823 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10389 11:46:16.659040 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10390 11:46:16.666676 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10391 11:46:16.679542 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10392 11:46:16.685920 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10393 11:46:16.692923 <6>[ 0.009179] Console: colour dummy device 80x25
10394 11:46:16.702471 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10395 11:46:16.709210 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10396 11:46:16.712584 <6>[ 0.029218] LSM: Security Framework initializing
10397 11:46:16.719492 <6>[ 0.034185] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10398 11:46:16.729056 <6>[ 0.041998] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 11:46:16.735917 <6>[ 0.051399] cblist_init_generic: Setting adjustable number of callback queues.
10400 11:46:16.742695 <6>[ 0.058863] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 11:46:16.752589 <6>[ 0.065201] cblist_init_generic: Setting adjustable number of callback queues.
10402 11:46:16.759109 <6>[ 0.072673] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 11:46:16.762098 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10404 11:46:16.768556 <6>[ 0.084126] rcu: Max phase no-delay instances is 1000.
10405 11:46:16.775606 <6>[ 0.091146] EFI services will not be available.
10406 11:46:16.778707 <6>[ 0.096100] smp: Bringing up secondary CPUs ...
10407 11:46:16.787103 <6>[ 0.101176] Detected VIPT I-cache on CPU1
10408 11:46:16.793554 <6>[ 0.101246] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10409 11:46:16.800253 <6>[ 0.101277] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10410 11:46:16.803552 <6>[ 0.101616] Detected VIPT I-cache on CPU2
10411 11:46:16.810364 <6>[ 0.101667] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10412 11:46:16.820144 <6>[ 0.101685] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10413 11:46:16.823593 <6>[ 0.101942] Detected VIPT I-cache on CPU3
10414 11:46:16.829953 <6>[ 0.101986] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10415 11:46:16.836563 <6>[ 0.102000] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10416 11:46:16.840361 <6>[ 0.102301] CPU features: detected: Spectre-v4
10417 11:46:16.846907 <6>[ 0.102308] CPU features: detected: Spectre-BHB
10418 11:46:16.850082 <6>[ 0.102313] Detected PIPT I-cache on CPU4
10419 11:46:16.856710 <6>[ 0.102369] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10420 11:46:16.862948 <6>[ 0.102386] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10421 11:46:16.869945 <6>[ 0.102673] Detected PIPT I-cache on CPU5
10422 11:46:16.876683 <6>[ 0.102735] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10423 11:46:16.883479 <6>[ 0.102752] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10424 11:46:16.886445 <6>[ 0.103032] Detected PIPT I-cache on CPU6
10425 11:46:16.892881 <6>[ 0.103096] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10426 11:46:16.899769 <6>[ 0.103112] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10427 11:46:16.906125 <6>[ 0.103407] Detected PIPT I-cache on CPU7
10428 11:46:16.912822 <6>[ 0.103471] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10429 11:46:16.919791 <6>[ 0.103487] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10430 11:46:16.922595 <6>[ 0.103534] smp: Brought up 1 node, 8 CPUs
10431 11:46:16.929340 <6>[ 0.244941] SMP: Total of 8 processors activated.
10432 11:46:16.933189 <6>[ 0.249891] CPU features: detected: 32-bit EL0 Support
10433 11:46:16.942784 <6>[ 0.255254] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10434 11:46:16.949435 <6>[ 0.264054] CPU features: detected: Common not Private translations
10435 11:46:16.955654 <6>[ 0.270570] CPU features: detected: CRC32 instructions
10436 11:46:16.959319 <6>[ 0.275921] CPU features: detected: RCpc load-acquire (LDAPR)
10437 11:46:16.965517 <6>[ 0.281918] CPU features: detected: LSE atomic instructions
10438 11:46:16.972416 <6>[ 0.287735] CPU features: detected: Privileged Access Never
10439 11:46:16.978744 <6>[ 0.293550] CPU features: detected: RAS Extension Support
10440 11:46:16.985356 <6>[ 0.299159] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10441 11:46:16.988815 <6>[ 0.306422] CPU: All CPU(s) started at EL2
10442 11:46:16.995227 <6>[ 0.310739] alternatives: applying system-wide alternatives
10443 11:46:17.004914 <6>[ 0.321481] devtmpfs: initialized
10444 11:46:17.020632 <6>[ 0.330323] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10445 11:46:17.026902 <6>[ 0.340282] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10446 11:46:17.033736 <6>[ 0.348526] pinctrl core: initialized pinctrl subsystem
10447 11:46:17.037120 <6>[ 0.355189] DMI not present or invalid.
10448 11:46:17.043499 <6>[ 0.359507] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10449 11:46:17.053442 <6>[ 0.366394] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10450 11:46:17.060045 <6>[ 0.373976] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10451 11:46:17.070084 <6>[ 0.382202] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10452 11:46:17.073430 <6>[ 0.390443] audit: initializing netlink subsys (disabled)
10453 11:46:17.083566 <5>[ 0.396133] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10454 11:46:17.090099 <6>[ 0.396828] thermal_sys: Registered thermal governor 'step_wise'
10455 11:46:17.096491 <6>[ 0.404102] thermal_sys: Registered thermal governor 'power_allocator'
10456 11:46:17.099880 <6>[ 0.410358] cpuidle: using governor menu
10457 11:46:17.106556 <6>[ 0.421318] NET: Registered PF_QIPCRTR protocol family
10458 11:46:17.113102 <6>[ 0.426814] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10459 11:46:17.116531 <6>[ 0.433919] ASID allocator initialised with 32768 entries
10460 11:46:17.123905 <6>[ 0.440477] Serial: AMBA PL011 UART driver
10461 11:46:17.132926 <4>[ 0.449239] Trying to register duplicate clock ID: 134
10462 11:46:17.186887 <6>[ 0.506628] KASLR enabled
10463 11:46:17.200870 <6>[ 0.514288] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10464 11:46:17.207595 <6>[ 0.521303] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10465 11:46:17.214672 <6>[ 0.527795] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10466 11:46:17.220688 <6>[ 0.534803] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10467 11:46:17.227596 <6>[ 0.541291] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10468 11:46:17.234322 <6>[ 0.548293] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10469 11:46:17.240858 <6>[ 0.554780] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10470 11:46:17.247219 <6>[ 0.561785] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10471 11:46:17.250530 <6>[ 0.569285] ACPI: Interpreter disabled.
10472 11:46:17.258994 <6>[ 0.575687] iommu: Default domain type: Translated
10473 11:46:17.265687 <6>[ 0.580801] iommu: DMA domain TLB invalidation policy: strict mode
10474 11:46:17.269118 <5>[ 0.587453] SCSI subsystem initialized
10475 11:46:17.275945 <6>[ 0.591614] usbcore: registered new interface driver usbfs
10476 11:46:17.282369 <6>[ 0.597347] usbcore: registered new interface driver hub
10477 11:46:17.285559 <6>[ 0.602899] usbcore: registered new device driver usb
10478 11:46:17.292622 <6>[ 0.609000] pps_core: LinuxPPS API ver. 1 registered
10479 11:46:17.302715 <6>[ 0.614193] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10480 11:46:17.306024 <6>[ 0.623541] PTP clock support registered
10481 11:46:17.308827 <6>[ 0.627783] EDAC MC: Ver: 3.0.0
10482 11:46:17.316223 <6>[ 0.632932] FPGA manager framework
10483 11:46:17.323244 <6>[ 0.636612] Advanced Linux Sound Architecture Driver Initialized.
10484 11:46:17.326226 <6>[ 0.643381] vgaarb: loaded
10485 11:46:17.332968 <6>[ 0.646554] clocksource: Switched to clocksource arch_sys_counter
10486 11:46:17.336440 <5>[ 0.652984] VFS: Disk quotas dquot_6.6.0
10487 11:46:17.342716 <6>[ 0.657169] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10488 11:46:17.346038 <6>[ 0.664358] pnp: PnP ACPI: disabled
10489 11:46:17.354420 <6>[ 0.670971] NET: Registered PF_INET protocol family
10490 11:46:17.364251 <6>[ 0.676551] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10491 11:46:17.375964 <6>[ 0.688826] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10492 11:46:17.385640 <6>[ 0.697637] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10493 11:46:17.392384 <6>[ 0.705609] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10494 11:46:17.401829 <6>[ 0.714308] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10495 11:46:17.408797 <6>[ 0.724055] TCP: Hash tables configured (established 65536 bind 65536)
10496 11:46:17.415152 <6>[ 0.730917] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10497 11:46:17.424905 <6>[ 0.738115] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 11:46:17.431709 <6>[ 0.745811] NET: Registered PF_UNIX/PF_LOCAL protocol family
10499 11:46:17.435247 <6>[ 0.751980] RPC: Registered named UNIX socket transport module.
10500 11:46:17.441529 <6>[ 0.758133] RPC: Registered udp transport module.
10501 11:46:17.445016 <6>[ 0.763066] RPC: Registered tcp transport module.
10502 11:46:17.455003 <6>[ 0.767999] RPC: Registered tcp NFSv4.1 backchannel transport module.
10503 11:46:17.458444 <6>[ 0.774669] PCI: CLS 0 bytes, default 64
10504 11:46:17.461227 <6>[ 0.779052] Unpacking initramfs...
10505 11:46:17.477881 <6>[ 0.791150] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10506 11:46:17.488126 <6>[ 0.799786] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10507 11:46:17.491461 <6>[ 0.808628] kvm [1]: IPA Size Limit: 40 bits
10508 11:46:17.497656 <6>[ 0.813158] kvm [1]: GICv3: no GICV resource entry
10509 11:46:17.501054 <6>[ 0.818180] kvm [1]: disabling GICv2 emulation
10510 11:46:17.507621 <6>[ 0.822868] kvm [1]: GIC system register CPU interface enabled
10511 11:46:17.511214 <6>[ 0.829030] kvm [1]: vgic interrupt IRQ18
10512 11:46:17.517466 <6>[ 0.833391] kvm [1]: VHE mode initialized successfully
10513 11:46:17.524418 <5>[ 0.839892] Initialise system trusted keyrings
10514 11:46:17.530552 <6>[ 0.844682] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10515 11:46:17.538489 <6>[ 0.854660] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10516 11:46:17.544710 <5>[ 0.861059] NFS: Registering the id_resolver key type
10517 11:46:17.548097 <5>[ 0.866358] Key type id_resolver registered
10518 11:46:17.554873 <5>[ 0.870771] Key type id_legacy registered
10519 11:46:17.561177 <6>[ 0.875060] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10520 11:46:17.567989 <6>[ 0.881985] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10521 11:46:17.574626 <6>[ 0.889708] 9p: Installing v9fs 9p2000 file system support
10522 11:46:17.611362 <5>[ 0.927929] Key type asymmetric registered
10523 11:46:17.614786 <5>[ 0.932260] Asymmetric key parser 'x509' registered
10524 11:46:17.624729 <6>[ 0.937404] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10525 11:46:17.628171 <6>[ 0.945019] io scheduler mq-deadline registered
10526 11:46:17.631234 <6>[ 0.949798] io scheduler kyber registered
10527 11:46:17.650643 <6>[ 0.966945] EINJ: ACPI disabled.
10528 11:46:17.683120 <4>[ 0.992843] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 11:46:17.692397 <4>[ 1.003486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 11:46:17.707814 <6>[ 1.024191] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10531 11:46:17.715944 <6>[ 1.032221] printk: console [ttyS0] disabled
10532 11:46:17.743546 <6>[ 1.056868] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10533 11:46:17.750439 <6>[ 1.066345] printk: console [ttyS0] enabled
10534 11:46:17.753406 <6>[ 1.066345] printk: console [ttyS0] enabled
10535 11:46:17.760501 <6>[ 1.075239] printk: bootconsole [mtk8250] disabled
10536 11:46:17.763899 <6>[ 1.075239] printk: bootconsole [mtk8250] disabled
10537 11:46:17.770214 <6>[ 1.086515] SuperH (H)SCI(F) driver initialized
10538 11:46:17.773603 <6>[ 1.091790] msm_serial: driver initialized
10539 11:46:17.787552 <6>[ 1.100778] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10540 11:46:17.797525 <6>[ 1.109330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10541 11:46:17.804381 <6>[ 1.117871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10542 11:46:17.814157 <6>[ 1.126500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10543 11:46:17.823978 <6>[ 1.135208] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10544 11:46:17.830588 <6>[ 1.143933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10545 11:46:17.840909 <6>[ 1.152475] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10546 11:46:17.847264 <6>[ 1.161304] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10547 11:46:17.856788 <6>[ 1.169846] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10548 11:46:17.868893 <6>[ 1.185423] loop: module loaded
10549 11:46:17.875769 <6>[ 1.191437] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10550 11:46:17.897629 <4>[ 1.214274] mtk-pmic-keys: Failed to locate of_node [id: -1]
10551 11:46:17.904418 <6>[ 1.221216] megasas: 07.719.03.00-rc1
10552 11:46:17.914445 <6>[ 1.231020] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10553 11:46:17.925560 <6>[ 1.241935] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10554 11:46:17.942375 <6>[ 1.258647] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10555 11:46:17.998792 <6>[ 1.308662] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10556 11:46:18.204574 <6>[ 1.521255] Freeing initrd memory: 17372K
10557 11:46:18.215095 <6>[ 1.531632] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10558 11:46:18.226128 <6>[ 1.542437] tun: Universal TUN/TAP device driver, 1.6
10559 11:46:18.229424 <6>[ 1.548492] thunder_xcv, ver 1.0
10560 11:46:18.232810 <6>[ 1.551999] thunder_bgx, ver 1.0
10561 11:46:18.236161 <6>[ 1.555493] nicpf, ver 1.0
10562 11:46:18.246078 <6>[ 1.559502] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10563 11:46:18.249396 <6>[ 1.566978] hns3: Copyright (c) 2017 Huawei Corporation.
10564 11:46:18.256243 <6>[ 1.572567] hclge is initializing
10565 11:46:18.259681 <6>[ 1.576142] e1000: Intel(R) PRO/1000 Network Driver
10566 11:46:18.265890 <6>[ 1.581271] e1000: Copyright (c) 1999-2006 Intel Corporation.
10567 11:46:18.269443 <6>[ 1.587283] e1000e: Intel(R) PRO/1000 Network Driver
10568 11:46:18.276078 <6>[ 1.592498] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10569 11:46:18.282797 <6>[ 1.598682] igb: Intel(R) Gigabit Ethernet Network Driver
10570 11:46:18.289275 <6>[ 1.604331] igb: Copyright (c) 2007-2014 Intel Corporation.
10571 11:46:18.296136 <6>[ 1.610165] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10572 11:46:18.302473 <6>[ 1.616683] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10573 11:46:18.306381 <6>[ 1.623148] sky2: driver version 1.30
10574 11:46:18.312713 <6>[ 1.628139] VFIO - User Level meta-driver version: 0.3
10575 11:46:18.320101 <6>[ 1.636373] usbcore: registered new interface driver usb-storage
10576 11:46:18.326484 <6>[ 1.642820] usbcore: registered new device driver onboard-usb-hub
10577 11:46:18.335536 <6>[ 1.651998] mt6397-rtc mt6359-rtc: registered as rtc0
10578 11:46:18.345822 <6>[ 1.657463] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:46:19 UTC (1700826379)
10579 11:46:18.348393 <6>[ 1.667060] i2c_dev: i2c /dev entries driver
10580 11:46:18.365227 <6>[ 1.678765] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10581 11:46:18.385458 <6>[ 1.701758] cpu cpu0: EM: created perf domain
10582 11:46:18.388231 <6>[ 1.706683] cpu cpu4: EM: created perf domain
10583 11:46:18.395473 <6>[ 1.712257] sdhci: Secure Digital Host Controller Interface driver
10584 11:46:18.402323 <6>[ 1.718688] sdhci: Copyright(c) Pierre Ossman
10585 11:46:18.409022 <6>[ 1.723659] Synopsys Designware Multimedia Card Interface Driver
10586 11:46:18.415733 <6>[ 1.730302] sdhci-pltfm: SDHCI platform and OF driver helper
10587 11:46:18.419128 <6>[ 1.730415] mmc0: CQHCI version 5.10
10588 11:46:18.425940 <6>[ 1.740678] ledtrig-cpu: registered to indicate activity on CPUs
10589 11:46:18.432422 <6>[ 1.747665] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10590 11:46:18.439315 <6>[ 1.754741] usbcore: registered new interface driver usbhid
10591 11:46:18.442204 <6>[ 1.760565] usbhid: USB HID core driver
10592 11:46:18.449095 <6>[ 1.764770] spi_master spi0: will run message pump with realtime priority
10593 11:46:18.493460 <6>[ 1.803188] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10594 11:46:18.512476 <6>[ 1.818942] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10595 11:46:18.515393 <6>[ 1.832525] mmc0: Command Queue Engine enabled
10596 11:46:18.522255 <6>[ 1.837281] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 11:46:18.529042 <6>[ 1.844235] cros-ec-spi spi0.0: Chrome EC device registered
10598 11:46:18.532434 <6>[ 1.844577] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 11:46:18.544501 <6>[ 1.861277] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 11:46:18.551844 <6>[ 1.868646] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 11:46:18.558806 <6>[ 1.874700] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10602 11:46:18.568780 <6>[ 1.880325] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10603 11:46:18.575541 <6>[ 1.880695] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10604 11:46:18.578955 <6>[ 1.890837] NET: Registered PF_PACKET protocol family
10605 11:46:18.585353 <6>[ 1.901596] 9pnet: Installing 9P2000 support
10606 11:46:18.588793 <5>[ 1.906175] Key type dns_resolver registered
10607 11:46:18.595257 <6>[ 1.911136] registered taskstats version 1
10608 11:46:18.598729 <5>[ 1.915530] Loading compiled-in X.509 certificates
10609 11:46:18.628069 <4>[ 1.938273] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 11:46:18.638514 <4>[ 1.949108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 11:46:18.644824 <3>[ 1.959733] debugfs: File 'uA_load' in directory '/' already present!
10612 11:46:18.651837 <3>[ 1.966446] debugfs: File 'min_uV' in directory '/' already present!
10613 11:46:18.658405 <3>[ 1.973058] debugfs: File 'max_uV' in directory '/' already present!
10614 11:46:18.664742 <3>[ 1.979668] debugfs: File 'constraint_flags' in directory '/' already present!
10615 11:46:18.676091 <3>[ 1.989511] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10616 11:46:18.688471 <6>[ 2.005120] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10617 11:46:18.695312 <6>[ 2.011965] xhci-mtk 11200000.usb: xHCI Host Controller
10618 11:46:18.701904 <6>[ 2.017523] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10619 11:46:18.712143 <6>[ 2.025463] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10620 11:46:18.719073 <6>[ 2.034895] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10621 11:46:18.725554 <6>[ 2.040982] xhci-mtk 11200000.usb: xHCI Host Controller
10622 11:46:18.731985 <6>[ 2.046461] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 11:46:18.738471 <6>[ 2.054114] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10624 11:46:18.745576 <6>[ 2.061929] hub 1-0:1.0: USB hub found
10625 11:46:18.748881 <6>[ 2.065956] hub 1-0:1.0: 1 port detected
10626 11:46:18.755202 <6>[ 2.070245] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10627 11:46:18.762155 <6>[ 2.078983] hub 2-0:1.0: USB hub found
10628 11:46:18.765460 <6>[ 2.083010] hub 2-0:1.0: 1 port detected
10629 11:46:18.773431 <6>[ 2.089942] mtk-msdc 11f70000.mmc: Got CD GPIO
10630 11:46:18.784820 <6>[ 2.098192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10631 11:46:18.791446 <6>[ 2.106227] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10632 11:46:18.801544 <4>[ 2.114151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10633 11:46:18.811131 <6>[ 2.123684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10634 11:46:18.818126 <6>[ 2.131761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10635 11:46:18.824688 <6>[ 2.139809] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10636 11:46:18.834431 <6>[ 2.147727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10637 11:46:18.841021 <6>[ 2.155544] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10638 11:46:18.850821 <6>[ 2.163362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10639 11:46:18.861053 <6>[ 2.173737] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10640 11:46:18.867703 <6>[ 2.182132] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 11:46:18.877692 <6>[ 2.190477] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 11:46:18.884014 <6>[ 2.198823] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 11:46:18.894592 <6>[ 2.207164] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 11:46:18.900925 <6>[ 2.215503] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 11:46:18.910937 <6>[ 2.223841] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 11:46:18.917393 <6>[ 2.232180] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 11:46:18.927160 <6>[ 2.240518] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 11:46:18.933790 <6>[ 2.248857] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 11:46:18.943634 <6>[ 2.257203] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 11:46:18.953624 <6>[ 2.265542] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 11:46:18.960363 <6>[ 2.273882] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 11:46:18.970528 <6>[ 2.282220] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 11:46:18.976819 <6>[ 2.290558] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 11:46:18.983391 <6>[ 2.299278] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 11:46:18.990298 <6>[ 2.306421] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 11:46:18.996940 <6>[ 2.313188] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 11:46:19.003059 <6>[ 2.319947] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 11:46:19.013229 <6>[ 2.326881] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 11:46:19.020016 <6>[ 2.333724] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 11:46:19.029626 <6>[ 2.342855] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 11:46:19.039857 <6>[ 2.351974] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 11:46:19.049732 <6>[ 2.361267] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 11:46:19.059697 <6>[ 2.370738] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 11:46:19.066083 <6>[ 2.380207] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 11:46:19.076397 <6>[ 2.389328] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 11:46:19.085893 <6>[ 2.398800] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 11:46:19.095869 <6>[ 2.407919] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 11:46:19.105678 <6>[ 2.417212] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 11:46:19.115634 <6>[ 2.427371] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 11:46:19.122547 <6>[ 2.430887] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 11:46:19.132198 <6>[ 2.438906] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10672 11:46:19.139036 <6>[ 2.453950] Trying to probe devices needed for running init ...
10673 11:46:19.153608 <6>[ 2.470209] hub 2-1:1.0: USB hub found
10674 11:46:19.156852 <6>[ 2.474681] hub 2-1:1.0: 3 ports detected
10675 11:46:19.165573 <6>[ 2.482142] hub 2-1:1.0: USB hub found
10676 11:46:19.168854 <6>[ 2.486495] hub 2-1:1.0: 3 ports detected
10677 11:46:19.277491 <6>[ 2.590846] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10678 11:46:19.432276 <6>[ 2.748845] hub 1-1:1.0: USB hub found
10679 11:46:19.435454 <6>[ 2.753295] hub 1-1:1.0: 4 ports detected
10680 11:46:19.444480 <6>[ 2.761175] hub 1-1:1.0: USB hub found
10681 11:46:19.447844 <6>[ 2.765634] hub 1-1:1.0: 4 ports detected
10682 11:46:19.517571 <6>[ 2.831085] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10683 11:46:19.769330 <6>[ 3.082850] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 11:46:19.902007 <6>[ 3.218597] hub 1-1.4:1.0: USB hub found
10685 11:46:19.905260 <6>[ 3.223233] hub 1-1.4:1.0: 2 ports detected
10686 11:46:19.914455 <6>[ 3.231016] hub 1-1.4:1.0: USB hub found
10687 11:46:19.917676 <6>[ 3.235608] hub 1-1.4:1.0: 2 ports detected
10688 11:46:20.213270 <6>[ 3.526812] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 11:46:20.405259 <6>[ 3.718849] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 11:46:31.414634 <6>[ 14.735828] ALSA device list:
10691 11:46:31.420893 <6>[ 14.739123] No soundcards found.
10692 11:46:31.428791 <6>[ 14.747036] Freeing unused kernel memory: 8384K
10693 11:46:31.432417 <6>[ 14.752060] Run /init as init process
10694 11:46:31.443780 Loading, please wait...
10695 11:46:31.464225 Starting version 247.3-7+deb11u2
10696 11:46:31.669183 <6>[ 14.983831] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10697 11:46:31.681613 <3>[ 14.996216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 11:46:31.688164 <6>[ 14.996837] remoteproc remoteproc0: scp is available
10699 11:46:31.694662 <3>[ 15.007034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 11:46:31.701579 <6>[ 15.010209] remoteproc remoteproc0: powering up scp
10701 11:46:31.707787 <3>[ 15.020387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 11:46:31.714340 <6>[ 15.020465] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10703 11:46:31.724545 <6>[ 15.021784] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10704 11:46:31.731091 <6>[ 15.021818] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10705 11:46:31.740893 <6>[ 15.021824] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10706 11:46:31.748106 <6>[ 15.022992] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10707 11:46:31.754752 <6>[ 15.023056] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10708 11:46:31.761553 <3>[ 15.032636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 11:46:31.771160 <4>[ 15.044520] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10710 11:46:31.778288 <4>[ 15.044520] Fallback method does not support PEC.
10711 11:46:31.785060 <3>[ 15.046515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 11:46:31.788523 <6>[ 15.048926] mc: Linux media interface: v0.10
10713 11:46:31.798296 <3>[ 15.072446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 11:46:31.804949 <4>[ 15.073000] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10715 11:46:31.811740 <4>[ 15.073099] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10716 11:46:31.821393 <3>[ 15.077887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 11:46:31.828104 <3>[ 15.107818] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 11:46:31.838200 <3>[ 15.112222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 11:46:31.844615 <6>[ 15.144037] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10720 11:46:31.851341 <3>[ 15.152427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 11:46:31.861356 <3>[ 15.152452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 11:46:31.867698 <6>[ 15.155009] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10723 11:46:31.874608 <6>[ 15.160509] pci_bus 0000:00: root bus resource [bus 00-ff]
10724 11:46:31.884319 <6>[ 15.163240] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10725 11:46:31.890933 <6>[ 15.163661] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10726 11:46:31.900880 <6>[ 15.164573] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10727 11:46:31.907764 <6>[ 15.164606] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10728 11:46:31.914524 <6>[ 15.164614] remoteproc remoteproc0: remote processor scp is now up
10729 11:46:31.924378 <3>[ 15.167410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 11:46:31.930912 <6>[ 15.175446] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10731 11:46:31.937672 <6>[ 15.177152] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10732 11:46:31.947376 <6>[ 15.178339] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10733 11:46:31.954027 <4>[ 15.181824] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10734 11:46:31.963850 <4>[ 15.181830] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10735 11:46:31.973979 <6>[ 15.182917] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10736 11:46:31.980847 <3>[ 15.183521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 11:46:31.990426 <6>[ 15.190649] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10738 11:46:31.996871 <6>[ 15.190687] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10739 11:46:32.003784 <3>[ 15.196456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 11:46:32.010508 <6>[ 15.196863] videodev: Linux video capture interface: v2.00
10741 11:46:32.017143 <6>[ 15.206474] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10742 11:46:32.027024 <3>[ 15.215633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 11:46:32.029863 <6>[ 15.222903] pci 0000:00:00.0: supports D1 D2
10744 11:46:32.040197 <3>[ 15.231184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 11:46:32.043377 <6>[ 15.231988] Bluetooth: Core ver 2.22
10746 11:46:32.049594 <6>[ 15.232162] NET: Registered PF_BLUETOOTH protocol family
10747 11:46:32.056302 <6>[ 15.232166] Bluetooth: HCI device and connection manager initialized
10748 11:46:32.060008 <6>[ 15.232185] Bluetooth: HCI socket layer initialized
10749 11:46:32.066217 <6>[ 15.232191] Bluetooth: L2CAP socket layer initialized
10750 11:46:32.069658 <6>[ 15.232202] Bluetooth: SCO socket layer initialized
10751 11:46:32.076217 <6>[ 15.237615] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10752 11:46:32.086087 <3>[ 15.245694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 11:46:32.092845 <6>[ 15.247200] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10754 11:46:32.106333 <6>[ 15.248842] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10755 11:46:32.109614 <6>[ 15.249119] usbcore: registered new interface driver uvcvideo
10756 11:46:32.116066 <6>[ 15.252912] r8152 2-1.3:1.0 eth0: v1.12.13
10757 11:46:32.122425 <6>[ 15.253928] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10758 11:46:32.129108 <6>[ 15.254011] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10759 11:46:32.135919 <6>[ 15.254036] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10760 11:46:32.145804 <6>[ 15.254052] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10761 11:46:32.152265 <6>[ 15.254067] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10762 11:46:32.155766 <6>[ 15.254169] pci 0000:01:00.0: supports D1 D2
10763 11:46:32.162419 <6>[ 15.254170] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10764 11:46:32.172354 <3>[ 15.261074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 11:46:32.179133 <6>[ 15.262668] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10766 11:46:32.185514 <6>[ 15.262700] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10767 11:46:32.195675 <6>[ 15.262706] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10768 11:46:32.201935 <6>[ 15.262719] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10769 11:46:32.211911 <6>[ 15.262735] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10770 11:46:32.218772 <6>[ 15.262751] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10771 11:46:32.224818 <6>[ 15.262767] pci 0000:00:00.0: PCI bridge to [bus 01]
10772 11:46:32.231856 <6>[ 15.262775] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10773 11:46:32.238130 <6>[ 15.262912] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10774 11:46:32.245075 <6>[ 15.263849] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10775 11:46:32.251269 <6>[ 15.264143] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10776 11:46:32.254770 <6>[ 15.269473] usbcore: registered new interface driver r8152
10777 11:46:32.264639 <3>[ 15.278359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 11:46:32.271121 <3>[ 15.278400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 11:46:32.281075 <5>[ 15.288992] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10780 11:46:32.284493 <6>[ 15.296989] usbcore: registered new interface driver btusb
10781 11:46:32.290993 <6>[ 15.297278] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10782 11:46:32.304440 <4>[ 15.298064] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10783 11:46:32.307789 <3>[ 15.298078] Bluetooth: hci0: Failed to load firmware file (-2)
10784 11:46:32.314347 <3>[ 15.298082] Bluetooth: hci0: Failed to set up firmware (-2)
10785 11:46:32.323927 <4>[ 15.298087] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10786 11:46:32.330616 <6>[ 15.314165] usbcore: registered new interface driver cdc_ether
10787 11:46:32.337493 <5>[ 15.314578] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10788 11:46:32.346954 <4>[ 15.314672] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 11:46:32.350277 <6>[ 15.314683] cfg80211: failed to load regulatory.db
10790 11:46:32.360341 <6>[ 15.415070] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10791 11:46:32.363854 <6>[ 15.428177] usbcore: registered new interface driver r8153_ecm
10792 11:46:32.370399 <6>[ 15.434048] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10793 11:46:32.377032 <6>[ 15.448131] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10794 11:46:32.383259 <6>[ 15.470785] mt7921e 0000:01:00.0: ASIC revision: 79610010
10795 11:46:32.486281 <4>[ 15.797630] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 11:46:32.489112 Begin: Loading essential drivers ... done.
10797 11:46:32.495883 Begin: Running /scripts/init-premount ... done.
10798 11:46:32.502500 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10799 11:46:32.512472 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10800 11:46:32.515857 Device /sys/class/net/enx0024323078ff found
10801 11:46:32.515945 done.
10802 11:46:32.559926 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10803 11:46:32.605324 <4>[ 15.916839] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 11:46:32.720302 <4>[ 16.032131] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 11:46:32.836542 <4>[ 16.147998] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 11:46:32.952078 <4>[ 16.263880] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 11:46:33.067841 <4>[ 16.379804] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 11:46:33.183631 <4>[ 16.495669] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 11:46:33.300063 <4>[ 16.611684] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 11:46:33.416104 <4>[ 16.727657] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 11:46:33.531587 <4>[ 16.843508] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 11:46:33.547723 <6>[ 16.865832] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10813 11:46:33.639212 <3>[ 16.957493] mt7921e 0000:01:00.0: hardware init failed
10814 11:46:33.838960 IP-Config: no response after 2 secs - giving up
10815 11:46:33.895501 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10816 11:46:33.899064 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10817 11:46:33.908684 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10818 11:46:33.915622 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10819 11:46:33.922375 host : mt8192-asurada-spherion-r0-cbg-8
10820 11:46:33.928964 domain : lava-rack
10821 11:46:33.932532 rootserver: 192.168.201.1 rootpath:
10822 11:46:33.932610 filename :
10823 11:46:34.035342 done.
10824 11:46:34.043207 Begin: Running /scripts/nfs-bottom ... done.
10825 11:46:34.060551 Begin: Running /scripts/init-bottom ... done.
10826 11:46:35.313788 <6>[ 18.632334] NET: Registered PF_INET6 protocol family
10827 11:46:35.321043 <6>[ 18.639581] Segment Routing with IPv6
10828 11:46:35.324267 <6>[ 18.643625] In-situ OAM (IOAM) with IPv6
10829 11:46:35.462339 <30>[ 18.761125] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10830 11:46:35.465967 <30>[ 18.785513] systemd[1]: Detected architecture arm64.
10831 11:46:35.489381
10832 11:46:35.492659 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10833 11:46:35.492753
10834 11:46:35.510806 <30>[ 18.829472] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10835 11:46:36.425301 <30>[ 19.740520] systemd[1]: Queued start job for default target Graphical Interface.
10836 11:46:36.466852 <30>[ 19.785285] systemd[1]: Created slice system-getty.slice.
10837 11:46:36.473381 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10838 11:46:36.489555 <30>[ 19.808248] systemd[1]: Created slice system-modprobe.slice.
10839 11:46:36.496140 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10840 11:46:36.513272 <30>[ 19.832034] systemd[1]: Created slice system-serial\x2dgetty.slice.
10841 11:46:36.523721 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10842 11:46:36.537093 <30>[ 19.855887] systemd[1]: Created slice User and Session Slice.
10843 11:46:36.543922 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10844 11:46:36.564453 <30>[ 19.879693] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10845 11:46:36.574496 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10846 11:46:36.591876 <30>[ 19.907050] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10847 11:46:36.598341 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10848 11:46:36.619056 <30>[ 19.930971] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10849 11:46:36.625747 <30>[ 19.943122] systemd[1]: Reached target Local Encrypted Volumes.
10850 11:46:36.632030 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10851 11:46:36.649116 <30>[ 19.967382] systemd[1]: Reached target Paths.
10852 11:46:36.652016 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10853 11:46:36.667996 <30>[ 19.986820] systemd[1]: Reached target Remote File Systems.
10854 11:46:36.674699 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10855 11:46:36.688153 <30>[ 20.006812] systemd[1]: Reached target Slices.
10856 11:46:36.694678 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10857 11:46:36.708399 <30>[ 20.026854] systemd[1]: Reached target Swap.
10858 11:46:36.711372 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10859 11:46:36.732143 <30>[ 20.047428] systemd[1]: Listening on initctl Compatibility Named Pipe.
10860 11:46:36.738998 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10861 11:46:36.745342 <30>[ 20.063841] systemd[1]: Listening on Journal Audit Socket.
10862 11:46:36.752167 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10863 11:46:36.769752 <30>[ 20.088420] systemd[1]: Listening on Journal Socket (/dev/log).
10864 11:46:36.776217 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10865 11:46:36.792820 <30>[ 20.111390] systemd[1]: Listening on Journal Socket.
10866 11:46:36.799088 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10867 11:46:36.814109 <30>[ 20.132428] systemd[1]: Listening on Network Service Netlink Socket.
10868 11:46:36.824064 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10869 11:46:36.839295 <30>[ 20.157834] systemd[1]: Listening on udev Control Socket.
10870 11:46:36.845799 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10871 11:46:36.860609 <30>[ 20.179257] systemd[1]: Listening on udev Kernel Socket.
10872 11:46:36.866980 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10873 11:46:36.916432 <30>[ 20.235323] systemd[1]: Mounting Huge Pages File System...
10874 11:46:36.922951 Mounting [0;1;39mHuge Pages File System[0m...
10875 11:46:36.938778 <30>[ 20.257112] systemd[1]: Mounting POSIX Message Queue File System...
10876 11:46:36.945474 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10877 11:46:36.963552 <30>[ 20.282030] systemd[1]: Mounting Kernel Debug File System...
10878 11:46:36.969844 Mounting [0;1;39mKernel Debug File System[0m...
10879 11:46:36.988093 <30>[ 20.303266] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10880 11:46:37.004846 <30>[ 20.320118] systemd[1]: Starting Create list of static device nodes for the current kernel...
10881 11:46:37.014762 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10882 11:46:37.035528 <30>[ 20.354137] systemd[1]: Starting Load Kernel Module configfs...
10883 11:46:37.042557 Starting [0;1;39mLoad Kernel Module configfs[0m...
10884 11:46:37.060502 <30>[ 20.379248] systemd[1]: Starting Load Kernel Module drm...
10885 11:46:37.067257 Starting [0;1;39mLoad Kernel Module drm[0m...
10886 11:46:37.085733 <30>[ 20.404070] systemd[1]: Starting Load Kernel Module fuse...
10887 11:46:37.091946 Starting [0;1;39mLoad Kernel Module fuse[0m...
10888 11:46:37.116404 <30>[ 20.431786] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10889 11:46:37.145719 <6>[ 20.464425] fuse: init (API version 7.37)
10890 11:46:37.160941 <30>[ 20.479813] systemd[1]: Starting Journal Service...
10891 11:46:37.167546 Starting [0;1;39mJournal Service[0m...
10892 11:46:37.191418 <30>[ 20.510163] systemd[1]: Starting Load Kernel Modules...
10893 11:46:37.197778 Starting [0;1;39mLoad Kernel Modules[0m...
10894 11:46:37.219610 <30>[ 20.535021] systemd[1]: Starting Remount Root and Kernel File Systems...
10895 11:46:37.226253 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10896 11:46:37.244011 <30>[ 20.562842] systemd[1]: Starting Coldplug All udev Devices...
10897 11:46:37.250853 Starting [0;1;39mColdplug All udev Devices[0m...
10898 11:46:37.268707 <30>[ 20.587599] systemd[1]: Mounted Huge Pages File System.
10899 11:46:37.275553 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10900 11:46:37.293580 <30>[ 20.612293] systemd[1]: Mounted POSIX Message Queue File System.
10901 11:46:37.300218 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10902 11:46:37.317038 <30>[ 20.635375] systemd[1]: Mounted Kernel Debug File System.
10903 11:46:37.326894 [[0;32m OK [<3>[ 20.642038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 11:46:37.333547 0m] Mounted [0;1;39mKernel Debug File System[0m.
10905 11:46:37.353840 <30>[ 20.668848] systemd[1]: Finished Create list of static device nodes for the current kernel.
10906 11:46:37.367184 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 20.682252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 11:46:37.370853 for the current kernel[0m.
10908 11:46:37.385952 <30>[ 20.704414] systemd[1]: modprobe@configfs.service: Succeeded.
10909 11:46:37.392935 <30>[ 20.711534] systemd[1]: Finished Load Kernel Module configfs.
10910 11:46:37.399773 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10911 11:46:37.417303 <30>[ 20.735963] systemd[1]: modprobe@drm.service: Succeeded.
10912 11:46:37.424180 <30>[ 20.743089] systemd[1]: Finished Load Kernel Module drm.
10913 11:46:37.431146 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10914 11:46:37.446110 <30>[ 20.764090] systemd[1]: modprobe@fuse.service: Succeeded.
10915 11:46:37.455857 <3>[ 20.767089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:46:37.459102 <30>[ 20.771234] systemd[1]: Finished Load Kernel Module fuse.
10917 11:46:37.466492 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10918 11:46:37.485891 <3>[ 20.801107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:46:37.493253 <30>[ 20.812184] systemd[1]: Finished Load Kernel Modules.
10920 11:46:37.500116 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10921 11:46:37.517685 <3>[ 20.832924] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:46:37.524174 <30>[ 20.833268] systemd[1]: Finished Remount Root and Kernel File Systems.
10923 11:46:37.530758 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10924 11:46:37.549995 <3>[ 20.865472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:46:37.580195 <3>[ 20.895930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 11:46:37.587227 <30>[ 20.901494] systemd[1]: Mounting FUSE Control File System...
10927 11:46:37.593969 Mounting [0;1;39mFUSE Control File System[0m...
10928 11:46:37.610881 <3>[ 20.926281] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:46:37.620030 <30>[ 20.938883] systemd[1]: Mounting Kernel Configuration File System...
10930 11:46:37.626883 Mounting [0;1;39mKernel Configuration File System[0m...
10931 11:46:37.641291 <3>[ 20.956457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 11:46:37.656365 <30>[ 20.971651] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10933 11:46:37.666835 <30>[ 20.980789] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10934 11:46:37.677011 <3>[ 20.988387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:46:37.680452 <30>[ 20.993523] systemd[1]: Starting Load/Save Random Seed...
10936 11:46:37.687120 Starting [0;1;39mLoad/Save Random Seed[0m...
10937 11:46:37.748553 <4>[ 21.057242] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10938 11:46:37.754703 <30>[ 21.059601] systemd[1]: Starting Apply Kernel Variables...
10939 11:46:37.761800 <3>[ 21.072980] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10940 11:46:37.768155 Starting [0;1;39mApply Kernel Variables[0m...
10941 11:46:37.787448 <30>[ 21.106088] systemd[1]: Starting Create System Users...
10942 11:46:37.793717 Starting [0;1;39mCreate System Users[0m...
10943 11:46:37.811275 <30>[ 21.129770] systemd[1]: Started Journal Service.
10944 11:46:37.817653 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10945 11:46:37.843407 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10946 11:46:37.855890 See 'systemctl status systemd-udev-trigger.service' for details.
10947 11:46:37.872698 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10948 11:46:37.888735 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10949 11:46:37.905775 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10950 11:46:37.921020 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10951 11:46:37.937935 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10952 11:46:37.992901 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10953 11:46:38.015545 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10954 11:46:38.061469 <46>[ 21.377006] systemd-journald[299]: Received client request to flush runtime journal.
10955 11:46:38.835337 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10956 11:46:38.852802 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10957 11:46:38.871979 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10958 11:46:38.924482 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10959 11:46:39.498597 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10960 11:46:39.548940 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10961 11:46:39.638542 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10962 11:46:39.706593 Starting [0;1;39mNetwork Service[0m...
10963 11:46:40.044951 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10964 11:46:40.075166 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10965 11:46:40.120723 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10966 11:46:40.383239 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10967 11:46:40.403528 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10968 11:46:40.436854 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10969 11:46:40.457432 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10970 11:46:40.472706 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10971 11:46:40.515222 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10972 11:46:40.573191 Starting [0;1;39mNetwork Name Resolution[0m...
10973 11:46:40.596825 Starting [0;1;39mNetwork Time Synchronization[0m...
10974 11:46:40.615496 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10975 11:46:40.632896 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10976 11:46:40.686129 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10977 11:46:40.849658 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10978 11:46:40.865275 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10979 11:46:40.883750 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10980 11:46:40.900130 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10981 11:46:40.916649 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10982 11:46:41.054007 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10983 11:46:41.101342 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10984 11:46:41.152139 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10985 11:46:41.374955 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10986 11:46:41.387924 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10987 11:46:41.641660 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10988 11:46:41.659735 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10989 11:46:41.675595 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10990 11:46:41.720758 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10991 11:46:41.984368 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10992 11:46:42.344184 Starting [0;1;39mUser Login Management[0m...
10993 11:46:42.367964 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10994 11:46:42.386737 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10995 11:46:42.403558 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10996 11:46:42.456820 Starting [0;1;39mPermit User Sessions[0m...
10997 11:46:42.587804 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10998 11:46:42.628705 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10999 11:46:42.649955 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11000 11:46:42.668324 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11001 11:46:42.689108 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11002 11:46:42.699746 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11003 11:46:42.721163 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11004 11:46:42.740608 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11005 11:46:42.785663 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11006 11:46:42.839070 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11007 11:46:42.950062
11008 11:46:42.950213
11009 11:46:42.953362 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11010 11:46:42.953448
11011 11:46:42.956497 debian-bullseye-arm64 login: root (automatic login)
11012 11:46:42.956580
11013 11:46:42.956646
11014 11:46:43.373575 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11015 11:46:43.373721
11016 11:46:43.380171 The programs included with the Debian GNU/Linux system are free software;
11017 11:46:43.386746 the exact distribution terms for each program are described in the
11018 11:46:43.390399 individual files in /usr/share/doc/*/copyright.
11019 11:46:43.390502
11020 11:46:43.396793 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11021 11:46:43.400060 permitted by applicable law.
11022 11:46:44.442146 Matched prompt #10: / #
11024 11:46:44.442409 Setting prompt string to ['/ #']
11025 11:46:44.442501 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11027 11:46:44.442695 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11028 11:46:44.442782 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11029 11:46:44.442849 Setting prompt string to ['/ #']
11030 11:46:44.442910 Forcing a shell prompt, looking for ['/ #']
11032 11:46:44.493111 / #
11033 11:46:44.493299 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11034 11:46:44.493409 Waiting using forced prompt support (timeout 00:02:30)
11035 11:46:44.498367
11036 11:46:44.498694 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11037 11:46:44.498815 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11039 11:46:44.599209 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5'
11040 11:46:44.604077 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073986/extract-nfsrootfs-i4xd9vp5'
11042 11:46:44.704654 / # export NFS_SERVER_IP='192.168.201.1'
11043 11:46:44.709427 export NFS_SERVER_IP='192.168.201.1'
11044 11:46:44.709869 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11045 11:46:44.710043 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11046 11:46:44.710180 end: 2 depthcharge-action (duration 00:01:42) [common]
11047 11:46:44.710314 start: 3 lava-test-retry (timeout 00:07:28) [common]
11048 11:46:44.710482 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11049 11:46:44.710560 Using namespace: common
11051 11:46:44.811005 / # #
11052 11:46:44.811172 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11053 11:46:44.815778 #
11054 11:46:44.816089 Using /lava-12073986
11056 11:46:44.916450 / # export SHELL=/bin/bash
11057 11:46:44.921650 export SHELL=/bin/bash
11059 11:46:45.022247 / # . /lava-12073986/environment
11060 11:46:45.027550 . /lava-12073986/environment
11062 11:46:45.134044 / # /lava-12073986/bin/lava-test-runner /lava-12073986/0
11063 11:46:45.134204 Test shell timeout: 10s (minimum of the action and connection timeout)
11064 11:46:45.139360 /lava-12073986/bin/lava-test-runner /lava-12073986/0
11065 11:46:45.630673 + export TESTRUN_ID=0_timesync-off
11066 11:46:45.634021 + TESTRUN_ID=0_timesync-off
11067 11:46:45.636815 + cd /lava-12073986/0/tests/0_timesync-off
11068 11:46:45.640347 ++ cat uuid
11069 11:46:45.651518 + UUID=12073986_1.6.2.3.1
11070 11:46:45.651638 + set +x
11071 11:46:45.657962 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12073986_1.6.2.3.1>
11072 11:46:45.658241 Received signal: <STARTRUN> 0_timesync-off 12073986_1.6.2.3.1
11073 11:46:45.658336 Starting test lava.0_timesync-off (12073986_1.6.2.3.1)
11074 11:46:45.658466 Skipping test definition patterns.
11075 11:46:45.661529 + systemctl stop systemd-timesyncd
11076 11:46:45.738732 + set +x
11077 11:46:45.742000 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12073986_1.6.2.3.1>
11078 11:46:45.742359 Received signal: <ENDRUN> 0_timesync-off 12073986_1.6.2.3.1
11079 11:46:45.742518 Ending use of test pattern.
11080 11:46:45.742644 Ending test lava.0_timesync-off (12073986_1.6.2.3.1), duration 0.08
11082 11:46:45.847949 + export TESTRUN_ID=1_kselftest-tpm2
11083 11:46:45.851389 + TESTRUN_ID=1_kselftest-tpm2
11084 11:46:45.858175 + cd /lava-12073986/0/tests/1_kselftest-tpm2
11085 11:46:45.858278 ++ cat uuid
11086 11:46:45.868297 + UUID=12073986_1.6.2.3.5
11087 11:46:45.868425 + set +x
11088 11:46:45.874605 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12073986_1.6.2.3.5>
11089 11:46:45.874902 Received signal: <STARTRUN> 1_kselftest-tpm2 12073986_1.6.2.3.5
11090 11:46:45.874978 Starting test lava.1_kselftest-tpm2 (12073986_1.6.2.3.5)
11091 11:46:45.875059 Skipping test definition patterns.
11092 11:46:45.877937 + cd ./automated/linux/kselftest/
11093 11:46:45.904621 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11094 11:46:45.960602 INFO: install_deps skipped
11095 11:46:46.092803 --2023-11-24 11:46:46-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11096 11:46:46.116487 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11097 11:46:46.245651 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11098 11:46:46.374602 HTTP request sent, awaiting response... 200 OK
11099 11:46:46.377620 Length: 2961876 (2.8M) [application/octet-stream]
11100 11:46:46.380988 Saving to: 'kselftest.tar.xz'
11101 11:46:46.381072
11102 11:46:46.381136
11103 11:46:46.631619 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11104 11:46:46.888764 kselftest.tar.xz 1%[ ] 44.98K 176KB/s
11105 11:46:47.145513 kselftest.tar.xz 7%[> ] 214.67K 419KB/s
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11109 11:46:47.486415
11110 11:46:47.745124 2023-11-24 11:46:47 (2.56 MB/s) - 'kselftest.tar.xz' saved [2961876/2961876]
11111 11:46:47.745317
11112 11:46:55.461002 skiplist:
11113 11:46:55.464484 ========================================
11114 11:46:55.467360 ========================================
11115 11:46:55.527776 tpm2:test_smoke.sh
11116 11:46:55.531106 tpm2:test_space.sh
11117 11:46:55.551677 ============== Tests to run ===============
11118 11:46:55.554932 tpm2:test_smoke.sh
11119 11:46:55.555045 tpm2:test_space.sh
11120 11:46:55.561261 ===========End Tests to run ===============
11121 11:46:55.564910 shardfile-tpm2 pass
11122 11:46:55.697432 <12>[ 39.018274] kselftest: Running tests in tpm2
11123 11:46:55.710315 TAP version 13
11124 11:46:55.724342 1..2
11125 11:46:55.765504 # selftests: tpm2: test_smoke.sh
11126 11:46:57.302902 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11127 11:46:57.306176 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11128 11:46:57.312729 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11129 11:46:57.315999 # Traceback (most recent call last):
11130 11:46:57.326031 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11131 11:46:57.329507 # if self.tpm:
11132 11:46:57.332327 # AttributeError: 'Client' object has no attribute 'tpm'
11133 11:46:57.339367 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11134 11:46:57.342493 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11135 11:46:57.345638 # Traceback (most recent call last):
11136 11:46:57.355515 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11137 11:46:57.358917 # if self.tpm:
11138 11:46:57.362248 # AttributeError: 'Client' object has no attribute 'tpm'
11139 11:46:57.369152 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11140 11:46:57.375741 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11141 11:46:57.378957 # Traceback (most recent call last):
11142 11:46:57.388893 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11143 11:46:57.388976 # if self.tpm:
11144 11:46:57.395621 # AttributeError: 'Client' object has no attribute 'tpm'
11145 11:46:57.398907 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11146 11:46:57.405833 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11147 11:46:57.409170 # Traceback (most recent call last):
11148 11:46:57.419026 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11149 11:46:57.422575 # if self.tpm:
11150 11:46:57.426094 # AttributeError: 'Client' object has no attribute 'tpm'
11151 11:46:57.428847 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11152 11:46:57.435798 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11153 11:46:57.438737 # Traceback (most recent call last):
11154 11:46:57.448936 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11155 11:46:57.452141 # if self.tpm:
11156 11:46:57.455444 # AttributeError: 'Client' object has no attribute 'tpm'
11157 11:46:57.462010 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11158 11:46:57.468896 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11159 11:46:57.472327 # Traceback (most recent call last):
11160 11:46:57.481874 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11161 11:46:57.481958 # if self.tpm:
11162 11:46:57.488768 # AttributeError: 'Client' object has no attribute 'tpm'
11163 11:46:57.491867 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11164 11:46:57.498495 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11165 11:46:57.501630 # Traceback (most recent call last):
11166 11:46:57.511966 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11167 11:46:57.514918 # if self.tpm:
11168 11:46:57.518256 # AttributeError: 'Client' object has no attribute 'tpm'
11169 11:46:57.524786 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11170 11:46:57.531524 # Exception ignored in: <function Client.__del__ at 0xffff93759d30>
11171 11:46:57.535269 # Traceback (most recent call last):
11172 11:46:57.541599 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11173 11:46:57.545553 # if self.tpm:
11174 11:46:57.551758 # AttributeError: 'Client' object has no attribute 'tpm'
11175 11:46:57.551877 #
11176 11:46:57.558070 # ======================================================================
11177 11:46:57.561321 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11178 11:46:57.567907 # ----------------------------------------------------------------------
11179 11:46:57.571344 # Traceback (most recent call last):
11180 11:46:57.581161 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11181 11:46:57.588178 # self.root_key = self.client.create_root_key()
11182 11:46:57.597793 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11183 11:46:57.601448 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11184 11:46:57.614862 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11185 11:46:57.614972 # raise ProtocolError(cc, rc)
11186 11:46:57.621751 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11187 11:46:57.621841 #
11188 11:46:57.628316 # ======================================================================
11189 11:46:57.635090 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11190 11:46:57.641652 # ----------------------------------------------------------------------
11191 11:46:57.641762 # Traceback (most recent call last):
11192 11:46:57.654454 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11193 11:46:57.654577 # self.client = tpm2.Client()
11194 11:46:57.664635 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11195 11:46:57.671119 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11196 11:46:57.677697 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11197 11:46:57.677790 #
11198 11:46:57.684426 # ======================================================================
11199 11:46:57.687616 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11200 11:46:57.694425 # ----------------------------------------------------------------------
11201 11:46:57.697386 # Traceback (most recent call last):
11202 11:46:57.707081 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11203 11:46:57.710707 # self.client = tpm2.Client()
11204 11:46:57.720418 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11205 11:46:57.724312 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11206 11:46:57.730764 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11207 11:46:57.730877 #
11208 11:46:57.737672 # ======================================================================
11209 11:46:57.740808 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11210 11:46:57.747332 # ----------------------------------------------------------------------
11211 11:46:57.750582 # Traceback (most recent call last):
11212 11:46:57.760840 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11213 11:46:57.764278 # self.client = tpm2.Client()
11214 11:46:57.774018 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11215 11:46:57.780775 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11216 11:46:57.783982 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11217 11:46:57.784069 #
11218 11:46:57.790685 # ======================================================================
11219 11:46:57.797383 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11220 11:46:57.803936 # ----------------------------------------------------------------------
11221 11:46:57.807128 # Traceback (most recent call last):
11222 11:46:57.817056 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11223 11:46:57.820523 # self.client = tpm2.Client()
11224 11:46:57.830360 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11225 11:46:57.833468 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11226 11:46:57.840318 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11227 11:46:57.840415 #
11228 11:46:57.847291 # ======================================================================
11229 11:46:57.850219 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11230 11:46:57.856838 # ----------------------------------------------------------------------
11231 11:46:57.860120 # Traceback (most recent call last):
11232 11:46:57.870002 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11233 11:46:57.873582 # self.client = tpm2.Client()
11234 11:46:57.883632 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11235 11:46:57.886500 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11236 11:46:57.893253 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11237 11:46:57.893356 #
11238 11:46:57.899789 # ======================================================================
11239 11:46:57.903354 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11240 11:46:57.909572 # ----------------------------------------------------------------------
11241 11:46:57.912824 # Traceback (most recent call last):
11242 11:46:57.923121 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11243 11:46:57.926697 # self.client = tpm2.Client()
11244 11:46:57.936065 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11245 11:46:57.943102 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11246 11:46:57.946287 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11247 11:46:57.949416 #
11248 11:46:57.952878 # ======================================================================
11249 11:46:57.959369 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11250 11:46:57.966208 # ----------------------------------------------------------------------
11251 11:46:57.969882 # Traceback (most recent call last):
11252 11:46:57.979182 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11253 11:46:57.982589 # self.client = tpm2.Client()
11254 11:46:57.993033 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11255 11:46:57.998707 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11256 11:46:58.001723 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11257 11:46:58.001811 #
11258 11:46:58.008806 # ======================================================================
11259 11:46:58.018119 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11260 11:46:58.021375 # ----------------------------------------------------------------------
11261 11:46:58.024919 # Traceback (most recent call last):
11262 11:46:58.035202 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11263 11:46:58.041516 # self.client = tpm2.Client()
11264 11:46:58.047925 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11265 11:46:58.051568 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11266 11:46:58.057952 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11267 11:46:58.058114 #
11268 11:46:58.064893 # ----------------------------------------------------------------------
11269 11:46:58.064992 # Ran 9 tests in 0.044s
11270 11:46:58.067935 #
11271 11:46:58.068018 # FAILED (errors=9)
11272 11:46:58.071298 # test_async (tpm2_tests.AsyncTest) ... ok
11273 11:46:58.078164 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11274 11:46:58.078261 #
11275 11:46:58.084556 # ----------------------------------------------------------------------
11276 11:46:58.087775 # Ran 2 tests in 0.041s
11277 11:46:58.087863 #
11278 11:46:58.087928 # OK
11279 11:46:58.091034 ok 1 selftests: tpm2: test_smoke.sh
11280 11:46:58.094469 # selftests: tpm2: test_space.sh
11281 11:46:58.097740 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11282 11:46:58.104236 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11283 11:46:58.107981 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11284 11:46:58.110756 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11285 11:46:58.114468 #
11286 11:46:58.117546 # ======================================================================
11287 11:46:58.124485 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11288 11:46:58.130939 # ----------------------------------------------------------------------
11289 11:46:58.133864 # Traceback (most recent call last):
11290 11:46:58.144057 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11291 11:46:58.147504 # root1 = space1.create_root_key()
11292 11:46:58.157373 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11293 11:46:58.163937 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11294 11:46:58.173926 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11295 11:46:58.177512 # raise ProtocolError(cc, rc)
11296 11:46:58.184120 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11297 11:46:58.184267 #
11298 11:46:58.190703 # ======================================================================
11299 11:46:58.193808 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11300 11:46:58.200475 # ----------------------------------------------------------------------
11301 11:46:58.203590 # Traceback (most recent call last):
11302 11:46:58.213741 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11303 11:46:58.216972 # space1.create_root_key()
11304 11:46:58.226897 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11305 11:46:58.233740 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11306 11:46:58.243419 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11307 11:46:58.247171 # raise ProtocolError(cc, rc)
11308 11:46:58.253643 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11309 11:46:58.253749 #
11310 11:46:58.260229 # ======================================================================
11311 11:46:58.263588 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11312 11:46:58.270237 # ----------------------------------------------------------------------
11313 11:46:58.273373 # Traceback (most recent call last):
11314 11:46:58.283422 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11315 11:46:58.286836 # root1 = space1.create_root_key()
11316 11:46:58.300055 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11317 11:46:58.303912 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11318 11:46:58.313605 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11319 11:46:58.316751 # raise ProtocolError(cc, rc)
11320 11:46:58.323134 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11321 11:46:58.323260 #
11322 11:46:58.330192 # ======================================================================
11323 11:46:58.333484 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11324 11:46:58.339871 # ----------------------------------------------------------------------
11325 11:46:58.343314 # Traceback (most recent call last):
11326 11:46:58.356444 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11327 11:46:58.359765 # root1 = space1.create_root_key()
11328 11:46:58.369804 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11329 11:46:58.376102 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11330 11:46:58.386006 # File "/lava-12073986/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11331 11:46:58.389350 # raise ProtocolError(cc, rc)
11332 11:46:58.392671 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11333 11:46:58.396277 #
11334 11:46:58.399884 # ----------------------------------------------------------------------
11335 11:46:58.402685 # Ran 4 tests in 0.092s
11336 11:46:58.402775 #
11337 11:46:58.406465 # FAILED (errors=4)
11338 11:46:58.409302 not ok 2 selftests: tpm2: test_space.sh # exit=1
11339 11:46:58.412599 tpm2_test_smoke_sh pass
11340 11:46:58.412699 tpm2_test_space_sh fail
11341 11:46:58.419221 + ../../utils/send-to-lava.sh ./output/result.txt
11342 11:46:58.423513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11343 11:46:58.423807 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11345 11:46:58.429840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11346 11:46:58.430110 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11348 11:46:58.467066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11349 11:46:58.467394 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11351 11:46:58.470433 + set +x
11352 11:46:58.473292 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12073986_1.6.2.3.5>
11353 11:46:58.473550 Received signal: <ENDRUN> 1_kselftest-tpm2 12073986_1.6.2.3.5
11354 11:46:58.473626 Ending use of test pattern.
11355 11:46:58.473689 Ending test lava.1_kselftest-tpm2 (12073986_1.6.2.3.5), duration 12.60
11357 11:46:58.476656 <LAVA_TEST_RUNNER EXIT>
11358 11:46:58.476913 ok: lava_test_shell seems to have completed
11359 11:46:58.477025 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11360 11:46:58.477116 end: 3.1 lava-test-shell (duration 00:00:14) [common]
11361 11:46:58.477200 end: 3 lava-test-retry (duration 00:00:14) [common]
11362 11:46:58.477284 start: 4 finalize (timeout 00:07:14) [common]
11363 11:46:58.477372 start: 4.1 power-off (timeout 00:00:30) [common]
11364 11:46:58.477524 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11365 11:46:58.554125 >> Command sent successfully.
11366 11:46:58.556608 Returned 0 in 0 seconds
11367 11:46:58.657063 end: 4.1 power-off (duration 00:00:00) [common]
11369 11:46:58.657404 start: 4.2 read-feedback (timeout 00:07:14) [common]
11370 11:46:58.657668 Listened to connection for namespace 'common' for up to 1s
11371 11:46:59.658657 Finalising connection for namespace 'common'
11372 11:46:59.658852 Disconnecting from shell: Finalise
11373 11:46:59.658936 / #
11374 11:46:59.759319 end: 4.2 read-feedback (duration 00:00:01) [common]
11375 11:46:59.759501 end: 4 finalize (duration 00:00:01) [common]
11376 11:46:59.759623 Cleaning after the job
11377 11:46:59.759726 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/ramdisk
11378 11:46:59.762504 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/kernel
11379 11:46:59.774910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/dtb
11380 11:46:59.775148 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/nfsrootfs
11381 11:46:59.869114 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073986/tftp-deploy-j5rb8lmf/modules
11382 11:46:59.876745 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073986
11383 11:47:00.526705 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073986
11384 11:47:00.526891 Job finished correctly