Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 269
- Kernel Warnings: 105
- Boot result: PASS
- Errors: 0
1 11:44:13.540607 lava-dispatcher, installed at version: 2023.10
2 11:44:13.540828 start: 0 validate
3 11:44:13.540962 Start time: 2023-11-24 11:44:13.540955+00:00 (UTC)
4 11:44:13.541082 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:44:13.541214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:44:13.810696 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:44:13.811457 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:31.352192 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:31.352955 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:31.622302 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:31.623025 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:44:40.920377 validate duration: 27.38
14 11:44:40.920649 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:44:40.920747 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:44:40.920833 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:44:40.920960 Not decompressing ramdisk as can be used compressed.
18 11:44:40.921045 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 11:44:40.921110 saving as /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/ramdisk/rootfs.cpio.gz
20 11:44:40.921174 total size: 84918747 (80 MB)
21 11:44:41.189836 progress 0 % (0 MB)
22 11:44:41.212470 progress 5 % (4 MB)
23 11:44:41.235747 progress 10 % (8 MB)
24 11:44:41.259027 progress 15 % (12 MB)
25 11:44:41.282544 progress 20 % (16 MB)
26 11:44:41.304498 progress 25 % (20 MB)
27 11:44:41.326372 progress 30 % (24 MB)
28 11:44:41.348695 progress 35 % (28 MB)
29 11:44:41.370792 progress 40 % (32 MB)
30 11:44:41.393032 progress 45 % (36 MB)
31 11:44:41.414669 progress 50 % (40 MB)
32 11:44:41.436620 progress 55 % (44 MB)
33 11:44:41.458457 progress 60 % (48 MB)
34 11:44:41.480737 progress 65 % (52 MB)
35 11:44:41.502903 progress 70 % (56 MB)
36 11:44:41.524496 progress 75 % (60 MB)
37 11:44:41.546290 progress 80 % (64 MB)
38 11:44:41.568005 progress 85 % (68 MB)
39 11:44:41.590192 progress 90 % (72 MB)
40 11:44:41.611795 progress 95 % (76 MB)
41 11:44:41.633236 progress 100 % (80 MB)
42 11:44:41.633461 80 MB downloaded in 0.71 s (113.70 MB/s)
43 11:44:41.633625 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:44:41.633866 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:44:41.633952 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:44:41.634034 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:44:41.634171 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:44:41.634248 saving as /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/kernel/Image
50 11:44:41.634314 total size: 49107456 (46 MB)
51 11:44:41.634377 No compression specified
52 11:44:41.635484 progress 0 % (0 MB)
53 11:44:41.648172 progress 5 % (2 MB)
54 11:44:41.660825 progress 10 % (4 MB)
55 11:44:41.673530 progress 15 % (7 MB)
56 11:44:41.686275 progress 20 % (9 MB)
57 11:44:41.699171 progress 25 % (11 MB)
58 11:44:41.711878 progress 30 % (14 MB)
59 11:44:41.724512 progress 35 % (16 MB)
60 11:44:41.737254 progress 40 % (18 MB)
61 11:44:41.749907 progress 45 % (21 MB)
62 11:44:41.762788 progress 50 % (23 MB)
63 11:44:41.775642 progress 55 % (25 MB)
64 11:44:41.788479 progress 60 % (28 MB)
65 11:44:41.801467 progress 65 % (30 MB)
66 11:44:41.814337 progress 70 % (32 MB)
67 11:44:41.827280 progress 75 % (35 MB)
68 11:44:41.840384 progress 80 % (37 MB)
69 11:44:41.853292 progress 85 % (39 MB)
70 11:44:41.866342 progress 90 % (42 MB)
71 11:44:41.879011 progress 95 % (44 MB)
72 11:44:41.891583 progress 100 % (46 MB)
73 11:44:41.891835 46 MB downloaded in 0.26 s (181.86 MB/s)
74 11:44:41.891988 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:44:41.892213 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:44:41.892303 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:44:41.892386 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:44:41.892515 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:44:41.892583 saving as /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/dtb/mt8192-asurada-spherion-r0.dtb
81 11:44:41.892643 total size: 47278 (0 MB)
82 11:44:41.892704 No compression specified
83 11:44:41.893863 progress 69 % (0 MB)
84 11:44:41.894137 progress 100 % (0 MB)
85 11:44:41.894291 0 MB downloaded in 0.00 s (27.41 MB/s)
86 11:44:41.894409 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:44:41.894629 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:44:41.894713 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:44:41.894795 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:44:41.894911 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:44:41.894981 saving as /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/modules/modules.tar
93 11:44:41.895041 total size: 8624756 (8 MB)
94 11:44:41.895118 Using unxz to decompress xz
95 11:44:41.899398 progress 0 % (0 MB)
96 11:44:41.920419 progress 5 % (0 MB)
97 11:44:41.944365 progress 10 % (0 MB)
98 11:44:41.968272 progress 15 % (1 MB)
99 11:44:41.992023 progress 20 % (1 MB)
100 11:44:42.016313 progress 25 % (2 MB)
101 11:44:42.041908 progress 30 % (2 MB)
102 11:44:42.067922 progress 35 % (2 MB)
103 11:44:42.090978 progress 40 % (3 MB)
104 11:44:42.114889 progress 45 % (3 MB)
105 11:44:42.139695 progress 50 % (4 MB)
106 11:44:42.163747 progress 55 % (4 MB)
107 11:44:42.188257 progress 60 % (4 MB)
108 11:44:42.215801 progress 65 % (5 MB)
109 11:44:42.240319 progress 70 % (5 MB)
110 11:44:42.263438 progress 75 % (6 MB)
111 11:44:42.291332 progress 80 % (6 MB)
112 11:44:42.319269 progress 85 % (7 MB)
113 11:44:42.344922 progress 90 % (7 MB)
114 11:44:42.376888 progress 95 % (7 MB)
115 11:44:42.405319 progress 100 % (8 MB)
116 11:44:42.410323 8 MB downloaded in 0.52 s (15.96 MB/s)
117 11:44:42.410571 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:44:42.410835 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:44:42.410928 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:44:42.411022 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:44:42.411104 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:44:42.411195 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:44:42.411425 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b
125 11:44:42.411561 makedir: /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin
126 11:44:42.411709 makedir: /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/tests
127 11:44:42.411843 makedir: /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/results
128 11:44:42.411961 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-add-keys
129 11:44:42.412146 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-add-sources
130 11:44:42.412278 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-background-process-start
131 11:44:42.412409 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-background-process-stop
132 11:44:42.412534 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-common-functions
133 11:44:42.412665 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-echo-ipv4
134 11:44:42.412790 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-install-packages
135 11:44:42.412915 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-installed-packages
136 11:44:42.413039 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-os-build
137 11:44:42.413170 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-probe-channel
138 11:44:42.413294 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-probe-ip
139 11:44:42.413444 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-target-ip
140 11:44:42.413600 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-target-mac
141 11:44:42.413778 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-target-storage
142 11:44:42.413956 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-case
143 11:44:42.414090 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-event
144 11:44:42.414215 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-feedback
145 11:44:42.414341 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-raise
146 11:44:42.414467 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-reference
147 11:44:42.414600 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-runner
148 11:44:42.414724 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-set
149 11:44:42.414851 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-test-shell
150 11:44:42.414983 Updating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-install-packages (oe)
151 11:44:42.415137 Updating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/bin/lava-installed-packages (oe)
152 11:44:42.415259 Creating /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/environment
153 11:44:42.415357 LAVA metadata
154 11:44:42.415446 - LAVA_JOB_ID=12074004
155 11:44:42.415544 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:44:42.415711 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:44:42.415779 skipped lava-vland-overlay
158 11:44:42.415852 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:44:42.415930 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:44:42.416004 skipped lava-multinode-overlay
161 11:44:42.416081 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:44:42.416162 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:44:42.416234 Loading test definitions
164 11:44:42.416322 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 11:44:42.416405 Using /lava-12074004 at stage 0
166 11:44:42.416507 Fetching tests from https://github.com/kernelci/kernelci-core
167 11:44:42.416590 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/0/tests/0_sleep'
168 11:44:43.071847 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/0/tests/0_sleep
169 11:44:43.073704 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 11:44:43.074249 uuid=12074004_1.5.2.3.1 testdef=None
171 11:44:43.074450 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 11:44:43.074819 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 11:44:43.075740 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 11:44:43.076103 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 11:44:43.077233 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 11:44:43.077627 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 11:44:43.078610 runner path: /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/0/tests/0_sleep test_uuid 12074004_1.5.2.3.1
181 11:44:43.078730 sleep_params='mem freeze'
182 11:44:43.078957 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 11:44:43.079291 Creating lava-test-runner.conf files
185 11:44:43.079389 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074004/lava-overlay-ytbopp3b/lava-12074004/0 for stage 0
186 11:44:43.079527 - 0_sleep
187 11:44:43.079674 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 11:44:43.079804 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 11:44:43.222094 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 11:44:43.222257 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 11:44:43.222398 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 11:44:43.222534 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 11:44:43.222637 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 11:44:45.740237 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 11:44:45.740644 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 11:44:45.740765 extracting modules file /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074004/extract-overlay-ramdisk-5oerffa7/ramdisk
197 11:44:45.978117 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 11:44:45.978300 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 11:44:45.978403 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074004/compress-overlay-mwedllhx/overlay-1.5.2.4.tar.gz to ramdisk
200 11:44:45.978479 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074004/compress-overlay-mwedllhx/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074004/extract-overlay-ramdisk-5oerffa7/ramdisk
201 11:44:46.079397 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 11:44:46.079568 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 11:44:46.079669 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 11:44:46.079761 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 11:44:46.079844 Building ramdisk /var/lib/lava/dispatcher/tmp/12074004/extract-overlay-ramdisk-5oerffa7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074004/extract-overlay-ramdisk-5oerffa7/ramdisk
206 11:44:47.605614 >> 563549 blocks
207 11:44:57.529394 rename /var/lib/lava/dispatcher/tmp/12074004/extract-overlay-ramdisk-5oerffa7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/ramdisk/ramdisk.cpio.gz
208 11:44:57.529907 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 11:44:57.530037 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 11:44:57.530139 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 11:44:57.530252 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/kernel/Image'
212 11:45:10.350589 Returned 0 in 12 seconds
213 11:45:10.451240 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/kernel/image.itb
214 11:45:11.771458 output: FIT description: Kernel Image image with one or more FDT blobs
215 11:45:11.771848 output: Created: Fri Nov 24 11:45:11 2023
216 11:45:11.771929 output: Image 0 (kernel-1)
217 11:45:11.772000 output: Description:
218 11:45:11.772066 output: Created: Fri Nov 24 11:45:11 2023
219 11:45:11.772130 output: Type: Kernel Image
220 11:45:11.772191 output: Compression: lzma compressed
221 11:45:11.772249 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
222 11:45:11.772307 output: Architecture: AArch64
223 11:45:11.772362 output: OS: Linux
224 11:45:11.772422 output: Load Address: 0x00000000
225 11:45:11.772477 output: Entry Point: 0x00000000
226 11:45:11.772535 output: Hash algo: crc32
227 11:45:11.772593 output: Hash value: 43cfb6ad
228 11:45:11.772655 output: Image 1 (fdt-1)
229 11:45:11.772714 output: Description: mt8192-asurada-spherion-r0
230 11:45:11.772769 output: Created: Fri Nov 24 11:45:11 2023
231 11:45:11.772824 output: Type: Flat Device Tree
232 11:45:11.772879 output: Compression: uncompressed
233 11:45:11.772933 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 11:45:11.772988 output: Architecture: AArch64
235 11:45:11.773042 output: Hash algo: crc32
236 11:45:11.773096 output: Hash value: cc4352de
237 11:45:11.773150 output: Image 2 (ramdisk-1)
238 11:45:11.773204 output: Description: unavailable
239 11:45:11.773258 output: Created: Fri Nov 24 11:45:11 2023
240 11:45:11.773313 output: Type: RAMDisk Image
241 11:45:11.773367 output: Compression: Unknown Compression
242 11:45:11.773433 output: Data Size: 98331512 Bytes = 96026.87 KiB = 93.78 MiB
243 11:45:11.773525 output: Architecture: AArch64
244 11:45:11.773610 output: OS: Linux
245 11:45:11.773667 output: Load Address: unavailable
246 11:45:11.773723 output: Entry Point: unavailable
247 11:45:11.773778 output: Hash algo: crc32
248 11:45:11.773833 output: Hash value: d9a14582
249 11:45:11.773887 output: Default Configuration: 'conf-1'
250 11:45:11.773941 output: Configuration 0 (conf-1)
251 11:45:11.773996 output: Description: mt8192-asurada-spherion-r0
252 11:45:11.774050 output: Kernel: kernel-1
253 11:45:11.774104 output: Init Ramdisk: ramdisk-1
254 11:45:11.774158 output: FDT: fdt-1
255 11:45:11.774212 output: Loadables: kernel-1
256 11:45:11.774266 output:
257 11:45:11.774476 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 11:45:11.774576 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 11:45:11.774684 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 11:45:11.774777 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 11:45:11.774858 No LXC device requested
262 11:45:11.774939 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 11:45:11.775029 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 11:45:11.775110 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 11:45:11.775185 Checking files for TFTP limit of 4294967296 bytes.
266 11:45:11.775719 end: 1 tftp-deploy (duration 00:00:31) [common]
267 11:45:11.775831 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 11:45:11.775927 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 11:45:11.776059 substitutions:
270 11:45:11.776128 - {DTB}: 12074004/tftp-deploy-_a2jwg94/dtb/mt8192-asurada-spherion-r0.dtb
271 11:45:11.776194 - {INITRD}: 12074004/tftp-deploy-_a2jwg94/ramdisk/ramdisk.cpio.gz
272 11:45:11.776256 - {KERNEL}: 12074004/tftp-deploy-_a2jwg94/kernel/Image
273 11:45:11.776316 - {LAVA_MAC}: None
274 11:45:11.776375 - {PRESEED_CONFIG}: None
275 11:45:11.776433 - {PRESEED_LOCAL}: None
276 11:45:11.776490 - {RAMDISK}: 12074004/tftp-deploy-_a2jwg94/ramdisk/ramdisk.cpio.gz
277 11:45:11.776546 - {ROOT_PART}: None
278 11:45:11.776602 - {ROOT}: None
279 11:45:11.776658 - {SERVER_IP}: 192.168.201.1
280 11:45:11.776714 - {TEE}: None
281 11:45:11.776769 Parsed boot commands:
282 11:45:11.776824 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 11:45:11.777013 Parsed boot commands: tftpboot 192.168.201.1 12074004/tftp-deploy-_a2jwg94/kernel/image.itb 12074004/tftp-deploy-_a2jwg94/kernel/cmdline
284 11:45:11.777105 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 11:45:11.777192 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 11:45:11.777289 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 11:45:11.777376 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 11:45:11.777462 Not connected, no need to disconnect.
289 11:45:11.777540 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 11:45:11.777619 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 11:45:11.777686 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
292 11:45:11.781700 Setting prompt string to ['lava-test: # ']
293 11:45:11.782082 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 11:45:11.782194 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 11:45:11.782299 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 11:45:11.782393 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 11:45:11.782600 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
298 11:45:16.917400 >> Command sent successfully.
299 11:45:16.919878 Returned 0 in 5 seconds
300 11:45:17.020287 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 11:45:17.020631 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 11:45:17.020737 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 11:45:17.020822 Setting prompt string to 'Starting depthcharge on Spherion...'
305 11:45:17.020891 Changing prompt to 'Starting depthcharge on Spherion...'
306 11:45:17.020961 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 11:45:17.021236 [Enter `^Ec?' for help]
308 11:45:17.193258
309 11:45:17.193449
310 11:45:17.193541 F0: 102B 0000
311 11:45:17.193611
312 11:45:17.193673 F3: 1001 0000 [0200]
313 11:45:17.193733
314 11:45:17.197023 F3: 1001 0000
315 11:45:17.197110
316 11:45:17.197176 F7: 102D 0000
317 11:45:17.197238
318 11:45:17.197297 F1: 0000 0000
319 11:45:17.197354
320 11:45:17.200982 V0: 0000 0000 [0001]
321 11:45:17.201071
322 11:45:17.201138 00: 0007 8000
323 11:45:17.201206
324 11:45:17.204076 01: 0000 0000
325 11:45:17.204165
326 11:45:17.204269 BP: 0C00 0209 [0000]
327 11:45:17.204332
328 11:45:17.207932 G0: 1182 0000
329 11:45:17.208020
330 11:45:17.208086 EC: 0000 0021 [4000]
331 11:45:17.208180
332 11:45:17.211078 S7: 0000 0000 [0000]
333 11:45:17.211165
334 11:45:17.211233 CC: 0000 0000 [0001]
335 11:45:17.211296
336 11:45:17.215238 T0: 0000 0040 [010F]
337 11:45:17.215335
338 11:45:17.215402 Jump to BL
339 11:45:17.215464
340 11:45:17.239913
341 11:45:17.240069
342 11:45:17.240141
343 11:45:17.247318 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 11:45:17.250199 ARM64: Exception handlers installed.
345 11:45:17.254205 ARM64: Testing exception
346 11:45:17.257302 ARM64: Done test exception
347 11:45:17.265051 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 11:45:17.276206 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 11:45:17.283554 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 11:45:17.290145 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 11:45:17.296805 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 11:45:17.307378 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 11:45:17.317005 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 11:45:17.323808 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 11:45:17.342703 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 11:45:17.345602 WDT: Last reset was cold boot
357 11:45:17.349330 SPI1(PAD0) initialized at 2873684 Hz
358 11:45:17.352709 SPI5(PAD0) initialized at 992727 Hz
359 11:45:17.355928 VBOOT: Loading verstage.
360 11:45:17.362597 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 11:45:17.365980 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 11:45:17.369205 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 11:45:17.372545 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 11:45:17.380064 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 11:45:17.386419 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 11:45:17.397281 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 11:45:17.397448
368 11:45:17.397533
369 11:45:17.407631 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 11:45:17.411044 ARM64: Exception handlers installed.
371 11:45:17.414028 ARM64: Testing exception
372 11:45:17.414115 ARM64: Done test exception
373 11:45:17.420425 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 11:45:17.423852 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 11:45:17.438333 Probing TPM: . done!
376 11:45:17.438472 TPM ready after 0 ms
377 11:45:17.445150 Connected to device vid:did:rid of 1ae0:0028:00
378 11:45:17.452027 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 11:45:17.494233 Initialized TPM device CR50 revision 0
380 11:45:17.505026 tlcl_send_startup: Startup return code is 0
381 11:45:17.505181 TPM: setup succeeded
382 11:45:17.516833 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 11:45:17.525282 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 11:45:17.531909 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 11:45:17.544472 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 11:45:17.548023 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 11:45:17.550913 in-header: 03 07 00 00 08 00 00 00
388 11:45:17.554444 in-data: aa e4 47 04 13 02 00 00
389 11:45:17.558236 Chrome EC: UHEPI supported
390 11:45:17.564815 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 11:45:17.567643 in-header: 03 ad 00 00 08 00 00 00
392 11:45:17.571010 in-data: 00 20 20 08 00 00 00 00
393 11:45:17.571119 Phase 1
394 11:45:17.574292 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 11:45:17.581205 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 11:45:17.587544 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 11:45:17.590934 Recovery requested (1009000e)
398 11:45:17.598150 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 11:45:17.603704 tlcl_extend: response is 0
400 11:45:17.611805 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 11:45:17.616699 tlcl_extend: response is 0
402 11:45:17.623425 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 11:45:17.644201 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 11:45:17.650257 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 11:45:17.650375
406 11:45:17.650461
407 11:45:17.661096 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 11:45:17.664554 ARM64: Exception handlers installed.
409 11:45:17.664647 ARM64: Testing exception
410 11:45:17.667948 ARM64: Done test exception
411 11:45:17.689581 pmic_efuse_setting: Set efuses in 11 msecs
412 11:45:17.693035 pmwrap_interface_init: Select PMIF_VLD_RDY
413 11:45:17.700673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 11:45:17.703605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 11:45:17.707374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 11:45:17.714102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 11:45:17.717708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 11:45:17.724383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 11:45:17.727562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 11:45:17.730850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 11:45:17.737219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 11:45:17.742092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 11:45:17.747452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 11:45:17.751307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 11:45:17.754596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 11:45:17.760796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 11:45:17.767314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 11:45:17.774251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 11:45:17.777349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 11:45:17.784325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 11:45:17.791345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 11:45:17.794279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 11:45:17.800985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 11:45:17.807989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 11:45:17.811268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 11:45:17.818793 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 11:45:17.822241 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 11:45:17.828581 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 11:45:17.835169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 11:45:17.839257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 11:45:17.842373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 11:45:17.849814 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 11:45:17.852676 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 11:45:17.860395 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 11:45:17.864150 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 11:45:17.867062 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 11:45:17.873766 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 11:45:17.877269 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 11:45:17.884100 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 11:45:17.887210 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 11:45:17.894226 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 11:45:17.898379 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 11:45:17.901916 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 11:45:17.905087 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 11:45:17.912115 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 11:45:17.915072 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 11:45:17.918759 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 11:45:17.924826 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 11:45:17.928491 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 11:45:17.931214 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 11:45:17.934620 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 11:45:17.941268 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 11:45:17.944929 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 11:45:17.951250 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 11:45:17.961626 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 11:45:17.964663 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 11:45:17.974634 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 11:45:17.981770 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 11:45:17.988063 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 11:45:17.991349 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 11:45:17.994617 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 11:45:18.001858 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
473 11:45:18.008404 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 11:45:18.012320 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
475 11:45:18.015492 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 11:45:18.026575 [RTC]rtc_get_frequency_meter,154: input=15, output=836
477 11:45:18.036191 [RTC]rtc_get_frequency_meter,154: input=7, output=709
478 11:45:18.045719 [RTC]rtc_get_frequency_meter,154: input=11, output=773
479 11:45:18.055131 [RTC]rtc_get_frequency_meter,154: input=13, output=804
480 11:45:18.064269 [RTC]rtc_get_frequency_meter,154: input=12, output=787
481 11:45:18.073991 [RTC]rtc_get_frequency_meter,154: input=12, output=788
482 11:45:18.083838 [RTC]rtc_get_frequency_meter,154: input=13, output=803
483 11:45:18.086897 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
484 11:45:18.094003 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
485 11:45:18.097551 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 11:45:18.101066 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 11:45:18.107067 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 11:45:18.110531 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 11:45:18.113965 ADC[4]: Raw value=903031 ID=7
490 11:45:18.114058 ADC[3]: Raw value=213282 ID=1
491 11:45:18.116991 RAM Code: 0x71
492 11:45:18.120460 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 11:45:18.126905 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 11:45:18.134074 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 11:45:18.140703 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 11:45:18.143846 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 11:45:18.147374 in-header: 03 07 00 00 08 00 00 00
498 11:45:18.150493 in-data: aa e4 47 04 13 02 00 00
499 11:45:18.153840 Chrome EC: UHEPI supported
500 11:45:18.160459 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 11:45:18.163704 in-header: 03 dd 00 00 08 00 00 00
502 11:45:18.166608 in-data: 90 20 60 08 00 00 00 00
503 11:45:18.170583 MRC: failed to locate region type 0.
504 11:45:18.176871 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 11:45:18.180185 DRAM-K: Running full calibration
506 11:45:18.186612 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 11:45:18.186724 header.status = 0x0
508 11:45:18.190156 header.version = 0x6 (expected: 0x6)
509 11:45:18.193286 header.size = 0xd00 (expected: 0xd00)
510 11:45:18.196633 header.flags = 0x0
511 11:45:18.203166 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 11:45:18.220982 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 11:45:18.226873 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 11:45:18.230239 dram_init: ddr_geometry: 2
515 11:45:18.233854 [EMI] MDL number = 2
516 11:45:18.233947 [EMI] Get MDL freq = 0
517 11:45:18.237499 dram_init: ddr_type: 0
518 11:45:18.237586 is_discrete_lpddr4: 1
519 11:45:18.241063 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 11:45:18.241175
521 11:45:18.241269
522 11:45:18.243582 [Bian_co] ETT version 0.0.0.1
523 11:45:18.250486 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 11:45:18.250594
525 11:45:18.253673 dramc_set_vcore_voltage set vcore to 650000
526 11:45:18.256654 Read voltage for 800, 4
527 11:45:18.256742 Vio18 = 0
528 11:45:18.256807 Vcore = 650000
529 11:45:18.260328 Vdram = 0
530 11:45:18.260416 Vddq = 0
531 11:45:18.260483 Vmddr = 0
532 11:45:18.263140 dram_init: config_dvfs: 1
533 11:45:18.266613 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 11:45:18.273295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 11:45:18.276629 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
536 11:45:18.280125 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
537 11:45:18.283667 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
538 11:45:18.289973 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
539 11:45:18.290085 MEM_TYPE=3, freq_sel=18
540 11:45:18.293217 sv_algorithm_assistance_LP4_1600
541 11:45:18.296360 ============ PULL DRAM RESETB DOWN ============
542 11:45:18.303192 ========== PULL DRAM RESETB DOWN end =========
543 11:45:18.306292 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 11:45:18.310096 ===================================
545 11:45:18.313379 LPDDR4 DRAM CONFIGURATION
546 11:45:18.316542 ===================================
547 11:45:18.316663 EX_ROW_EN[0] = 0x0
548 11:45:18.319724 EX_ROW_EN[1] = 0x0
549 11:45:18.319813 LP4Y_EN = 0x0
550 11:45:18.323163 WORK_FSP = 0x0
551 11:45:18.323250 WL = 0x2
552 11:45:18.326161 RL = 0x2
553 11:45:18.326241 BL = 0x2
554 11:45:18.329894 RPST = 0x0
555 11:45:18.332857 RD_PRE = 0x0
556 11:45:18.332940 WR_PRE = 0x1
557 11:45:18.336582 WR_PST = 0x0
558 11:45:18.336660 DBI_WR = 0x0
559 11:45:18.339952 DBI_RD = 0x0
560 11:45:18.340031 OTF = 0x1
561 11:45:18.342944 ===================================
562 11:45:18.346280 ===================================
563 11:45:18.349972 ANA top config
564 11:45:18.350059 ===================================
565 11:45:18.352808 DLL_ASYNC_EN = 0
566 11:45:18.355934 ALL_SLAVE_EN = 1
567 11:45:18.360183 NEW_RANK_MODE = 1
568 11:45:18.362876 DLL_IDLE_MODE = 1
569 11:45:18.362958 LP45_APHY_COMB_EN = 1
570 11:45:18.365951 TX_ODT_DIS = 1
571 11:45:18.369575 NEW_8X_MODE = 1
572 11:45:18.372589 ===================================
573 11:45:18.376078 ===================================
574 11:45:18.379421 data_rate = 1600
575 11:45:18.382450 CKR = 1
576 11:45:18.385784 DQ_P2S_RATIO = 8
577 11:45:18.389305 ===================================
578 11:45:18.389417 CA_P2S_RATIO = 8
579 11:45:18.393272 DQ_CA_OPEN = 0
580 11:45:18.396066 DQ_SEMI_OPEN = 0
581 11:45:18.399090 CA_SEMI_OPEN = 0
582 11:45:18.402955 CA_FULL_RATE = 0
583 11:45:18.405623 DQ_CKDIV4_EN = 1
584 11:45:18.405708 CA_CKDIV4_EN = 1
585 11:45:18.409226 CA_PREDIV_EN = 0
586 11:45:18.412876 PH8_DLY = 0
587 11:45:18.416003 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 11:45:18.419768 DQ_AAMCK_DIV = 4
589 11:45:18.419859 CA_AAMCK_DIV = 4
590 11:45:18.422878 CA_ADMCK_DIV = 4
591 11:45:18.425652 DQ_TRACK_CA_EN = 0
592 11:45:18.429042 CA_PICK = 800
593 11:45:18.432302 CA_MCKIO = 800
594 11:45:18.436085 MCKIO_SEMI = 0
595 11:45:18.439137 PLL_FREQ = 3068
596 11:45:18.442411 DQ_UI_PI_RATIO = 32
597 11:45:18.442505 CA_UI_PI_RATIO = 0
598 11:45:18.445747 ===================================
599 11:45:18.448887 ===================================
600 11:45:18.452559 memory_type:LPDDR4
601 11:45:18.455937 GP_NUM : 10
602 11:45:18.456022 SRAM_EN : 1
603 11:45:18.458686 MD32_EN : 0
604 11:45:18.462447 ===================================
605 11:45:18.465876 [ANA_INIT] >>>>>>>>>>>>>>
606 11:45:18.465963 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 11:45:18.472381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 11:45:18.472490 ===================================
609 11:45:18.475496 data_rate = 1600,PCW = 0X7600
610 11:45:18.479044 ===================================
611 11:45:18.482629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 11:45:18.488638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 11:45:18.495242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 11:45:18.498558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 11:45:18.502205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 11:45:18.505327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 11:45:18.508797 [ANA_INIT] flow start
618 11:45:18.508882 [ANA_INIT] PLL >>>>>>>>
619 11:45:18.512004 [ANA_INIT] PLL <<<<<<<<
620 11:45:18.515086 [ANA_INIT] MIDPI >>>>>>>>
621 11:45:18.518599 [ANA_INIT] MIDPI <<<<<<<<
622 11:45:18.518690 [ANA_INIT] DLL >>>>>>>>
623 11:45:18.521622 [ANA_INIT] flow end
624 11:45:18.525346 ============ LP4 DIFF to SE enter ============
625 11:45:18.528897 ============ LP4 DIFF to SE exit ============
626 11:45:18.532033 [ANA_INIT] <<<<<<<<<<<<<
627 11:45:18.534933 [Flow] Enable top DCM control >>>>>
628 11:45:18.538561 [Flow] Enable top DCM control <<<<<
629 11:45:18.541882 Enable DLL master slave shuffle
630 11:45:18.548666 ==============================================================
631 11:45:18.548787 Gating Mode config
632 11:45:18.554949 ==============================================================
633 11:45:18.555058 Config description:
634 11:45:18.565333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 11:45:18.571387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 11:45:18.578547 SELPH_MODE 0: By rank 1: By Phase
637 11:45:18.581613 ==============================================================
638 11:45:18.585174 GAT_TRACK_EN = 1
639 11:45:18.588052 RX_GATING_MODE = 2
640 11:45:18.591240 RX_GATING_TRACK_MODE = 2
641 11:45:18.594864 SELPH_MODE = 1
642 11:45:18.598196 PICG_EARLY_EN = 1
643 11:45:18.601113 VALID_LAT_VALUE = 1
644 11:45:18.607824 ==============================================================
645 11:45:18.611729 Enter into Gating configuration >>>>
646 11:45:18.614839 Exit from Gating configuration <<<<
647 11:45:18.614936 Enter into DVFS_PRE_config >>>>>
648 11:45:18.627724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 11:45:18.631136 Exit from DVFS_PRE_config <<<<<
650 11:45:18.634758 Enter into PICG configuration >>>>
651 11:45:18.638421 Exit from PICG configuration <<<<
652 11:45:18.638517 [RX_INPUT] configuration >>>>>
653 11:45:18.641291 [RX_INPUT] configuration <<<<<
654 11:45:18.648265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 11:45:18.651684 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 11:45:18.659055 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 11:45:18.665343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 11:45:18.672801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 11:45:18.676433 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 11:45:18.679944 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 11:45:18.687062 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 11:45:18.691000 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 11:45:18.694687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 11:45:18.698405 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 11:45:18.702188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 11:45:18.705660 ===================================
667 11:45:18.709513 LPDDR4 DRAM CONFIGURATION
668 11:45:18.713230 ===================================
669 11:45:18.713348 EX_ROW_EN[0] = 0x0
670 11:45:18.716414 EX_ROW_EN[1] = 0x0
671 11:45:18.716501 LP4Y_EN = 0x0
672 11:45:18.720251 WORK_FSP = 0x0
673 11:45:18.720360 WL = 0x2
674 11:45:18.723435 RL = 0x2
675 11:45:18.723522 BL = 0x2
676 11:45:18.727131 RPST = 0x0
677 11:45:18.727220 RD_PRE = 0x0
678 11:45:18.730632 WR_PRE = 0x1
679 11:45:18.730723 WR_PST = 0x0
680 11:45:18.734562 DBI_WR = 0x0
681 11:45:18.734655 DBI_RD = 0x0
682 11:45:18.734721 OTF = 0x1
683 11:45:18.738611 ===================================
684 11:45:18.741802 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 11:45:18.745956 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 11:45:18.752840 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 11:45:18.756765 ===================================
688 11:45:18.756872 LPDDR4 DRAM CONFIGURATION
689 11:45:18.760154 ===================================
690 11:45:18.763425 EX_ROW_EN[0] = 0x10
691 11:45:18.763519 EX_ROW_EN[1] = 0x0
692 11:45:18.767750 LP4Y_EN = 0x0
693 11:45:18.767859 WORK_FSP = 0x0
694 11:45:18.771590 WL = 0x2
695 11:45:18.771724 RL = 0x2
696 11:45:18.774758 BL = 0x2
697 11:45:18.774875 RPST = 0x0
698 11:45:18.778778 RD_PRE = 0x0
699 11:45:18.778874 WR_PRE = 0x1
700 11:45:18.781762 WR_PST = 0x0
701 11:45:18.781849 DBI_WR = 0x0
702 11:45:18.785317 DBI_RD = 0x0
703 11:45:18.785405 OTF = 0x1
704 11:45:18.789127 ===================================
705 11:45:18.796076 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 11:45:18.800599 nWR fixed to 40
707 11:45:18.800732 [ModeRegInit_LP4] CH0 RK0
708 11:45:18.803274 [ModeRegInit_LP4] CH0 RK1
709 11:45:18.807254 [ModeRegInit_LP4] CH1 RK0
710 11:45:18.807368 [ModeRegInit_LP4] CH1 RK1
711 11:45:18.811652 match AC timing 13
712 11:45:18.815178 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 11:45:18.818751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 11:45:18.821586 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 11:45:18.828638 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 11:45:18.832175 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 11:45:18.832264 [EMI DOE] emi_dcm 0
718 11:45:18.839364 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 11:45:18.839453 ==
720 11:45:18.841767 Dram Type= 6, Freq= 0, CH_0, rank 0
721 11:45:18.845233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 11:45:18.845317 ==
723 11:45:18.851724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 11:45:18.858653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 11:45:18.865996 [CA 0] Center 37 (7~68) winsize 62
726 11:45:18.869393 [CA 1] Center 37 (7~68) winsize 62
727 11:45:18.872613 [CA 2] Center 34 (4~65) winsize 62
728 11:45:18.876552 [CA 3] Center 34 (4~65) winsize 62
729 11:45:18.879648 [CA 4] Center 33 (3~64) winsize 62
730 11:45:18.883215 [CA 5] Center 33 (3~64) winsize 62
731 11:45:18.883297
732 11:45:18.886696 [CmdBusTrainingLP45] Vref(ca) range 1: 32
733 11:45:18.886780
734 11:45:18.890016 [CATrainingPosCal] consider 1 rank data
735 11:45:18.892927 u2DelayCellTimex100 = 270/100 ps
736 11:45:18.896560 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 11:45:18.899785 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
738 11:45:18.902986 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 11:45:18.910261 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 11:45:18.913058 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 11:45:18.916143 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 11:45:18.916227
743 11:45:18.920187 CA PerBit enable=1, Macro0, CA PI delay=33
744 11:45:18.920273
745 11:45:18.922821 [CBTSetCACLKResult] CA Dly = 33
746 11:45:18.922903 CS Dly: 6 (0~37)
747 11:45:18.922968 ==
748 11:45:18.926964 Dram Type= 6, Freq= 0, CH_0, rank 1
749 11:45:18.932688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 11:45:18.932771 ==
751 11:45:18.936641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 11:45:18.942816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 11:45:18.952197 [CA 0] Center 37 (6~68) winsize 63
754 11:45:18.955542 [CA 1] Center 37 (7~68) winsize 62
755 11:45:18.959167 [CA 2] Center 34 (4~65) winsize 62
756 11:45:18.962492 [CA 3] Center 34 (4~65) winsize 62
757 11:45:18.965708 [CA 4] Center 33 (3~64) winsize 62
758 11:45:18.968914 [CA 5] Center 33 (3~64) winsize 62
759 11:45:18.968995
760 11:45:18.972126 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 11:45:18.972209
762 11:45:18.975492 [CATrainingPosCal] consider 2 rank data
763 11:45:18.978748 u2DelayCellTimex100 = 270/100 ps
764 11:45:18.982156 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 11:45:18.985611 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 11:45:18.992478 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 11:45:18.996176 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 11:45:18.999611 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 11:45:19.002973 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 11:45:19.003056
771 11:45:19.006888 CA PerBit enable=1, Macro0, CA PI delay=33
772 11:45:19.006996
773 11:45:19.009903 [CBTSetCACLKResult] CA Dly = 33
774 11:45:19.009988 CS Dly: 6 (0~38)
775 11:45:19.010053
776 11:45:19.013735 ----->DramcWriteLeveling(PI) begin...
777 11:45:19.013818 ==
778 11:45:19.017572 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:45:19.020189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:45:19.020273 ==
781 11:45:19.023834 Write leveling (Byte 0): 36 => 36
782 11:45:19.027404 Write leveling (Byte 1): 32 => 32
783 11:45:19.030504 DramcWriteLeveling(PI) end<-----
784 11:45:19.030588
785 11:45:19.030653 ==
786 11:45:19.034362 Dram Type= 6, Freq= 0, CH_0, rank 0
787 11:45:19.037269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 11:45:19.037351 ==
789 11:45:19.041142 [Gating] SW mode calibration
790 11:45:19.047535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 11:45:19.054405 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 11:45:19.057094 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 11:45:19.064015 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 11:45:19.066912 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 11:45:19.070308 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:45:19.076956 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:45:19.080560 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:45:19.083615 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:45:19.090173 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:45:19.094362 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:45:19.096883 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:45:19.103445 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:45:19.107089 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:45:19.110793 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:45:19.116837 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:45:19.120029 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:45:19.123475 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:45:19.130153 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:45:19.133607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 11:45:19.136613 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
811 11:45:19.140090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
812 11:45:19.146944 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:45:19.149766 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:45:19.153194 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:45:19.160080 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:45:19.163707 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:45:19.166654 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:45:19.173287 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
819 11:45:19.176879 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
820 11:45:19.179532 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 11:45:19.186523 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 11:45:19.189791 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 11:45:19.192604 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 11:45:19.199294 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 11:45:19.202745 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
826 11:45:19.206155 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
827 11:45:19.212613 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
828 11:45:19.215920 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:45:19.219231 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:45:19.226105 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:45:19.230156 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:45:19.232470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:45:19.238993 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:45:19.242719 0 11 8 | B1->B0 | 2323 3737 | 1 1 | (0 0) (0 0)
835 11:45:19.245822 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
836 11:45:19.252405 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 11:45:19.255646 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 11:45:19.259153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 11:45:19.266443 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 11:45:19.268873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 11:45:19.272032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 11:45:19.278826 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 11:45:19.282259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:45:19.285645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:45:19.291951 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:45:19.295903 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:45:19.298746 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:45:19.305891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:45:19.309389 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:45:19.311980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:45:19.318911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:45:19.322555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 11:45:19.325526 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:45:19.331681 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:45:19.335103 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:45:19.338351 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:45:19.344963 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 11:45:19.348195 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 11:45:19.351479 Total UI for P1: 0, mck2ui 16
860 11:45:19.354949 best dqsien dly found for B0: ( 0, 14, 4)
861 11:45:19.358743 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 11:45:19.361695 Total UI for P1: 0, mck2ui 16
863 11:45:19.365652 best dqsien dly found for B1: ( 0, 14, 8)
864 11:45:19.368421 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
865 11:45:19.371433 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 11:45:19.371515
867 11:45:19.375449 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
868 11:45:19.382177 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 11:45:19.382261 [Gating] SW calibration Done
870 11:45:19.382327 ==
871 11:45:19.385155 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:45:19.392570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 11:45:19.392661 ==
874 11:45:19.392728 RX Vref Scan: 0
875 11:45:19.392789
876 11:45:19.395626 RX Vref 0 -> 0, step: 1
877 11:45:19.395708
878 11:45:19.398470 RX Delay -130 -> 252, step: 16
879 11:45:19.402075 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 11:45:19.405502 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 11:45:19.409498 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 11:45:19.412640 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 11:45:19.416139 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 11:45:19.419701 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 11:45:19.427509 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
886 11:45:19.431722 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
887 11:45:19.434556 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 11:45:19.438646 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 11:45:19.442601 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
890 11:45:19.446103 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 11:45:19.449633 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
892 11:45:19.453208 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
893 11:45:19.456574 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 11:45:19.460553 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
895 11:45:19.460647 ==
896 11:45:19.464202 Dram Type= 6, Freq= 0, CH_0, rank 0
897 11:45:19.467904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 11:45:19.467988 ==
899 11:45:19.471609 DQS Delay:
900 11:45:19.471692 DQS0 = 0, DQS1 = 0
901 11:45:19.474683 DQM Delay:
902 11:45:19.474765 DQM0 = 85, DQM1 = 73
903 11:45:19.474837 DQ Delay:
904 11:45:19.477861 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 11:45:19.481101 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
906 11:45:19.484312 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
907 11:45:19.488057 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
908 11:45:19.488141
909 11:45:19.488206
910 11:45:19.491657 ==
911 11:45:19.494904 Dram Type= 6, Freq= 0, CH_0, rank 0
912 11:45:19.497602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 11:45:19.497686 ==
914 11:45:19.497751
915 11:45:19.497812
916 11:45:19.500925 TX Vref Scan disable
917 11:45:19.501007 == TX Byte 0 ==
918 11:45:19.504506 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
919 11:45:19.511254 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
920 11:45:19.511349 == TX Byte 1 ==
921 11:45:19.514333 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
922 11:45:19.521724 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
923 11:45:19.521824 ==
924 11:45:19.525260 Dram Type= 6, Freq= 0, CH_0, rank 0
925 11:45:19.528317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 11:45:19.528402 ==
927 11:45:19.542367 TX Vref=22, minBit 2, minWin=27, winSum=438
928 11:45:19.545726 TX Vref=24, minBit 2, minWin=27, winSum=438
929 11:45:19.549024 TX Vref=26, minBit 5, minWin=27, winSum=440
930 11:45:19.552196 TX Vref=28, minBit 0, minWin=27, winSum=442
931 11:45:19.555487 TX Vref=30, minBit 0, minWin=27, winSum=443
932 11:45:19.559040 TX Vref=32, minBit 0, minWin=27, winSum=439
933 11:45:19.565353 [TxChooseVref] Worse bit 0, Min win 27, Win sum 443, Final Vref 30
934 11:45:19.565509
935 11:45:19.568925 Final TX Range 1 Vref 30
936 11:45:19.569011
937 11:45:19.569092 ==
938 11:45:19.571968 Dram Type= 6, Freq= 0, CH_0, rank 0
939 11:45:19.575372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 11:45:19.575456 ==
941 11:45:19.575522
942 11:45:19.575603
943 11:45:19.578848 TX Vref Scan disable
944 11:45:19.582525 == TX Byte 0 ==
945 11:45:19.585358 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
946 11:45:19.588807 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
947 11:45:19.591688 == TX Byte 1 ==
948 11:45:19.595160 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
949 11:45:19.598866 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
950 11:45:19.598950
951 11:45:19.602616 [DATLAT]
952 11:45:19.602698 Freq=800, CH0 RK0
953 11:45:19.602764
954 11:45:19.604996 DATLAT Default: 0xa
955 11:45:19.605078 0, 0xFFFF, sum = 0
956 11:45:19.608584 1, 0xFFFF, sum = 0
957 11:45:19.608668 2, 0xFFFF, sum = 0
958 11:45:19.611857 3, 0xFFFF, sum = 0
959 11:45:19.611942 4, 0xFFFF, sum = 0
960 11:45:19.615015 5, 0xFFFF, sum = 0
961 11:45:19.615098 6, 0xFFFF, sum = 0
962 11:45:19.618935 7, 0xFFFF, sum = 0
963 11:45:19.619020 8, 0xFFFF, sum = 0
964 11:45:19.621680 9, 0x0, sum = 1
965 11:45:19.621768 10, 0x0, sum = 2
966 11:45:19.624883 11, 0x0, sum = 3
967 11:45:19.624966 12, 0x0, sum = 4
968 11:45:19.628495 best_step = 10
969 11:45:19.628577
970 11:45:19.628643 ==
971 11:45:19.631558 Dram Type= 6, Freq= 0, CH_0, rank 0
972 11:45:19.635080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 11:45:19.635167 ==
974 11:45:19.638488 RX Vref Scan: 1
975 11:45:19.638573
976 11:45:19.638674 Set Vref Range= 32 -> 127
977 11:45:19.638776
978 11:45:19.641860 RX Vref 32 -> 127, step: 1
979 11:45:19.641943
980 11:45:19.645174 RX Delay -95 -> 252, step: 8
981 11:45:19.645284
982 11:45:19.648557 Set Vref, RX VrefLevel [Byte0]: 32
983 11:45:19.651770 [Byte1]: 32
984 11:45:19.651854
985 11:45:19.655111 Set Vref, RX VrefLevel [Byte0]: 33
986 11:45:19.658238 [Byte1]: 33
987 11:45:19.658322
988 11:45:19.662001 Set Vref, RX VrefLevel [Byte0]: 34
989 11:45:19.664950 [Byte1]: 34
990 11:45:19.669049
991 11:45:19.669175 Set Vref, RX VrefLevel [Byte0]: 35
992 11:45:19.672849 [Byte1]: 35
993 11:45:19.676640
994 11:45:19.676749 Set Vref, RX VrefLevel [Byte0]: 36
995 11:45:19.680345 [Byte1]: 36
996 11:45:19.684566
997 11:45:19.684673 Set Vref, RX VrefLevel [Byte0]: 37
998 11:45:19.688241 [Byte1]: 37
999 11:45:19.691755
1000 11:45:19.691864 Set Vref, RX VrefLevel [Byte0]: 38
1001 11:45:19.695267 [Byte1]: 38
1002 11:45:19.700151
1003 11:45:19.700271 Set Vref, RX VrefLevel [Byte0]: 39
1004 11:45:19.702675 [Byte1]: 39
1005 11:45:19.707289
1006 11:45:19.707401 Set Vref, RX VrefLevel [Byte0]: 40
1007 11:45:19.710575 [Byte1]: 40
1008 11:45:19.714720
1009 11:45:19.714826 Set Vref, RX VrefLevel [Byte0]: 41
1010 11:45:19.717995 [Byte1]: 41
1011 11:45:19.722263
1012 11:45:19.722371 Set Vref, RX VrefLevel [Byte0]: 42
1013 11:45:19.725664 [Byte1]: 42
1014 11:45:19.729727
1015 11:45:19.729840 Set Vref, RX VrefLevel [Byte0]: 43
1016 11:45:19.733261 [Byte1]: 43
1017 11:45:19.737616
1018 11:45:19.737718 Set Vref, RX VrefLevel [Byte0]: 44
1019 11:45:19.741005 [Byte1]: 44
1020 11:45:19.745200
1021 11:45:19.745310 Set Vref, RX VrefLevel [Byte0]: 45
1022 11:45:19.748521 [Byte1]: 45
1023 11:45:19.752899
1024 11:45:19.753016 Set Vref, RX VrefLevel [Byte0]: 46
1025 11:45:19.755987 [Byte1]: 46
1026 11:45:19.760320
1027 11:45:19.760398 Set Vref, RX VrefLevel [Byte0]: 47
1028 11:45:19.764195 [Byte1]: 47
1029 11:45:19.767608
1030 11:45:19.767716 Set Vref, RX VrefLevel [Byte0]: 48
1031 11:45:19.771872 [Byte1]: 48
1032 11:45:19.775586
1033 11:45:19.775662 Set Vref, RX VrefLevel [Byte0]: 49
1034 11:45:19.778958 [Byte1]: 49
1035 11:45:19.782891
1036 11:45:19.782972 Set Vref, RX VrefLevel [Byte0]: 50
1037 11:45:19.786609 [Byte1]: 50
1038 11:45:19.790801
1039 11:45:19.790884 Set Vref, RX VrefLevel [Byte0]: 51
1040 11:45:19.794374 [Byte1]: 51
1041 11:45:19.798240
1042 11:45:19.798318 Set Vref, RX VrefLevel [Byte0]: 52
1043 11:45:19.801880 [Byte1]: 52
1044 11:45:19.805909
1045 11:45:19.805983 Set Vref, RX VrefLevel [Byte0]: 53
1046 11:45:19.808857 [Byte1]: 53
1047 11:45:19.813270
1048 11:45:19.813349 Set Vref, RX VrefLevel [Byte0]: 54
1049 11:45:19.817252 [Byte1]: 54
1050 11:45:19.820864
1051 11:45:19.820966 Set Vref, RX VrefLevel [Byte0]: 55
1052 11:45:19.824338 [Byte1]: 55
1053 11:45:19.828758
1054 11:45:19.828838 Set Vref, RX VrefLevel [Byte0]: 56
1055 11:45:19.831820 [Byte1]: 56
1056 11:45:19.836968
1057 11:45:19.837049 Set Vref, RX VrefLevel [Byte0]: 57
1058 11:45:19.839856 [Byte1]: 57
1059 11:45:19.844295
1060 11:45:19.844377 Set Vref, RX VrefLevel [Byte0]: 58
1061 11:45:19.847595 [Byte1]: 58
1062 11:45:19.851673
1063 11:45:19.851759 Set Vref, RX VrefLevel [Byte0]: 59
1064 11:45:19.854930 [Byte1]: 59
1065 11:45:19.859049
1066 11:45:19.859132 Set Vref, RX VrefLevel [Byte0]: 60
1067 11:45:19.862950 [Byte1]: 60
1068 11:45:19.866691
1069 11:45:19.866772 Set Vref, RX VrefLevel [Byte0]: 61
1070 11:45:19.869975 [Byte1]: 61
1071 11:45:19.874424
1072 11:45:19.874510 Set Vref, RX VrefLevel [Byte0]: 62
1073 11:45:19.878294 [Byte1]: 62
1074 11:45:19.882514
1075 11:45:19.882599 Set Vref, RX VrefLevel [Byte0]: 63
1076 11:45:19.885682 [Byte1]: 63
1077 11:45:19.889548
1078 11:45:19.889656 Set Vref, RX VrefLevel [Byte0]: 64
1079 11:45:19.894100 [Byte1]: 64
1080 11:45:19.897175
1081 11:45:19.897284 Set Vref, RX VrefLevel [Byte0]: 65
1082 11:45:19.900403 [Byte1]: 65
1083 11:45:19.905543
1084 11:45:19.905628 Set Vref, RX VrefLevel [Byte0]: 66
1085 11:45:19.908648 [Byte1]: 66
1086 11:45:19.912622
1087 11:45:19.912704 Set Vref, RX VrefLevel [Byte0]: 67
1088 11:45:19.915868 [Byte1]: 67
1089 11:45:19.920108
1090 11:45:19.920191 Set Vref, RX VrefLevel [Byte0]: 68
1091 11:45:19.923970 [Byte1]: 68
1092 11:45:19.927646
1093 11:45:19.927744 Set Vref, RX VrefLevel [Byte0]: 69
1094 11:45:19.930990 [Byte1]: 69
1095 11:45:19.934593
1096 11:45:19.938313 Set Vref, RX VrefLevel [Byte0]: 70
1097 11:45:19.938396 [Byte1]: 70
1098 11:45:19.942582
1099 11:45:19.942665 Set Vref, RX VrefLevel [Byte0]: 71
1100 11:45:19.946391 [Byte1]: 71
1101 11:45:19.950372
1102 11:45:19.950454 Set Vref, RX VrefLevel [Byte0]: 72
1103 11:45:19.954344 [Byte1]: 72
1104 11:45:19.957819
1105 11:45:19.957899 Set Vref, RX VrefLevel [Byte0]: 73
1106 11:45:19.961111 [Byte1]: 73
1107 11:45:19.965383
1108 11:45:19.965493 Set Vref, RX VrefLevel [Byte0]: 74
1109 11:45:19.968722 [Byte1]: 74
1110 11:45:19.972785
1111 11:45:19.976408 Set Vref, RX VrefLevel [Byte0]: 75
1112 11:45:19.976490 [Byte1]: 75
1113 11:45:19.980405
1114 11:45:19.980485 Set Vref, RX VrefLevel [Byte0]: 76
1115 11:45:19.983916 [Byte1]: 76
1116 11:45:19.988733
1117 11:45:19.988815 Set Vref, RX VrefLevel [Byte0]: 77
1118 11:45:19.991726 [Byte1]: 77
1119 11:45:19.995861
1120 11:45:19.995942 Set Vref, RX VrefLevel [Byte0]: 78
1121 11:45:19.999269 [Byte1]: 78
1122 11:45:20.003160
1123 11:45:20.003242 Set Vref, RX VrefLevel [Byte0]: 79
1124 11:45:20.006638 [Byte1]: 79
1125 11:45:20.011166
1126 11:45:20.011248 Set Vref, RX VrefLevel [Byte0]: 80
1127 11:45:20.014555 [Byte1]: 80
1128 11:45:20.018269
1129 11:45:20.018350 Set Vref, RX VrefLevel [Byte0]: 81
1130 11:45:20.021853 [Byte1]: 81
1131 11:45:20.026092
1132 11:45:20.026175 Set Vref, RX VrefLevel [Byte0]: 82
1133 11:45:20.029416 [Byte1]: 82
1134 11:45:20.034205
1135 11:45:20.034288 Set Vref, RX VrefLevel [Byte0]: 83
1136 11:45:20.036917 [Byte1]: 83
1137 11:45:20.041887
1138 11:45:20.041970 Final RX Vref Byte 0 = 68 to rank0
1139 11:45:20.044950 Final RX Vref Byte 1 = 55 to rank0
1140 11:45:20.047955 Final RX Vref Byte 0 = 68 to rank1
1141 11:45:20.051880 Final RX Vref Byte 1 = 55 to rank1==
1142 11:45:20.055402 Dram Type= 6, Freq= 0, CH_0, rank 0
1143 11:45:20.058450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 11:45:20.058531 ==
1145 11:45:20.062441 DQS Delay:
1146 11:45:20.062523 DQS0 = 0, DQS1 = 0
1147 11:45:20.062588 DQM Delay:
1148 11:45:20.066111 DQM0 = 88, DQM1 = 75
1149 11:45:20.066192 DQ Delay:
1150 11:45:20.070372 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1151 11:45:20.073509 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1152 11:45:20.077527 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1153 11:45:20.080671 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1154 11:45:20.080752
1155 11:45:20.080815
1156 11:45:20.088049 [DQSOSCAuto] RK0, (LSB)MR18= 0x4123, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1157 11:45:20.091878 CH0 RK0: MR19=606, MR18=4123
1158 11:45:20.095712 CH0_RK0: MR19=0x606, MR18=0x4123, DQSOSC=393, MR23=63, INC=95, DEC=63
1159 11:45:20.095794
1160 11:45:20.099549 ----->DramcWriteLeveling(PI) begin...
1161 11:45:20.099633 ==
1162 11:45:20.103158 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 11:45:20.107129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 11:45:20.110040 ==
1165 11:45:20.110121 Write leveling (Byte 0): 34 => 34
1166 11:45:20.113811 Write leveling (Byte 1): 33 => 33
1167 11:45:20.157631 DramcWriteLeveling(PI) end<-----
1168 11:45:20.157763
1169 11:45:20.157830 ==
1170 11:45:20.158433 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 11:45:20.158519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 11:45:20.158591 ==
1173 11:45:20.158838 [Gating] SW mode calibration
1174 11:45:20.158906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1175 11:45:20.158966 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1176 11:45:20.159305 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1177 11:45:20.159570 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1178 11:45:20.159639 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1179 11:45:20.159701 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:45:20.201944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:45:20.202300 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:45:20.202403 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:45:20.202499 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:45:20.202573 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:45:20.202634 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:45:20.203078 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:45:20.203345 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:45:20.203418 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:45:20.203669 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:45:20.246035 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:45:20.246383 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:45:20.246830 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:45:20.246912 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1194 11:45:20.247488 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1195 11:45:20.247907 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1196 11:45:20.248198 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:45:20.248295 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:45:20.248392 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:45:20.248494 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:45:20.290209 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:45:20.290576 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:45:20.290677 0 9 8 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (1 1)
1203 11:45:20.290770 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1204 11:45:20.291596 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 11:45:20.292372 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 11:45:20.292653 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 11:45:20.292745 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 11:45:20.292833 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 11:45:20.293429 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1210 11:45:20.334677 0 10 8 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (1 1)
1211 11:45:20.335719 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1212 11:45:20.335995 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:45:20.336064 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:45:20.336452 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:45:20.337121 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:45:20.337427 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:45:20.337990 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1218 11:45:20.338097 0 11 8 | B1->B0 | 3333 3c3c | 0 0 | (0 0) (0 0)
1219 11:45:20.338776 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1220 11:45:20.346889 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 11:45:20.347167 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 11:45:20.347237 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:45:20.350554 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 11:45:20.357017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 11:45:20.360347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1226 11:45:20.363565 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1227 11:45:20.370336 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 11:45:20.373721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 11:45:20.376930 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 11:45:20.383289 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 11:45:20.386504 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 11:45:20.390406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 11:45:20.396490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 11:45:20.400046 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 11:45:20.403605 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 11:45:20.409826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 11:45:20.413387 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 11:45:20.416751 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 11:45:20.420100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 11:45:20.426389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 11:45:20.429680 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 11:45:20.433403 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1243 11:45:20.440104 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1244 11:45:20.443425 Total UI for P1: 0, mck2ui 16
1245 11:45:20.446899 best dqsien dly found for B0: ( 0, 14, 8)
1246 11:45:20.449660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 11:45:20.452932 Total UI for P1: 0, mck2ui 16
1248 11:45:20.456340 best dqsien dly found for B1: ( 0, 14, 10)
1249 11:45:20.459399 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1250 11:45:20.463034 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1251 11:45:20.463119
1252 11:45:20.466667 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1253 11:45:20.469927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1254 11:45:20.473014 [Gating] SW calibration Done
1255 11:45:20.473096 ==
1256 11:45:20.476076 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 11:45:20.482773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 11:45:20.482856 ==
1259 11:45:20.482920 RX Vref Scan: 0
1260 11:45:20.482980
1261 11:45:20.486752 RX Vref 0 -> 0, step: 1
1262 11:45:20.486860
1263 11:45:20.489736 RX Delay -130 -> 252, step: 16
1264 11:45:20.493172 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1265 11:45:20.496624 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1266 11:45:20.499404 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1267 11:45:20.506244 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1268 11:45:20.509244 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1269 11:45:20.512707 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1270 11:45:20.515909 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1271 11:45:20.519127 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1272 11:45:20.526184 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1273 11:45:20.529157 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1274 11:45:20.532653 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1275 11:45:20.536445 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1276 11:45:20.539081 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1277 11:45:20.545654 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1278 11:45:20.549350 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1279 11:45:20.552647 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1280 11:45:20.552761 ==
1281 11:45:20.555868 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 11:45:20.559153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 11:45:20.559267 ==
1284 11:45:20.562438 DQS Delay:
1285 11:45:20.562544 DQS0 = 0, DQS1 = 0
1286 11:45:20.565866 DQM Delay:
1287 11:45:20.565974 DQM0 = 84, DQM1 = 76
1288 11:45:20.566067 DQ Delay:
1289 11:45:20.568899 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1290 11:45:20.572120 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1291 11:45:20.576022 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1292 11:45:20.578905 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1293 11:45:20.579016
1294 11:45:20.579110
1295 11:45:20.582801 ==
1296 11:45:20.586265 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 11:45:20.588591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 11:45:20.588696 ==
1299 11:45:20.588790
1300 11:45:20.588880
1301 11:45:20.591929 TX Vref Scan disable
1302 11:45:20.592035 == TX Byte 0 ==
1303 11:45:20.598810 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1304 11:45:20.602296 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1305 11:45:20.602407 == TX Byte 1 ==
1306 11:45:20.605309 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1307 11:45:20.612363 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1308 11:45:20.612476 ==
1309 11:45:20.615449 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 11:45:20.618364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 11:45:20.618470 ==
1312 11:45:20.632575 TX Vref=22, minBit 8, minWin=27, winSum=444
1313 11:45:20.635606 TX Vref=24, minBit 10, minWin=27, winSum=448
1314 11:45:20.638451 TX Vref=26, minBit 0, minWin=28, winSum=449
1315 11:45:20.641867 TX Vref=28, minBit 11, minWin=27, winSum=447
1316 11:45:20.645313 TX Vref=30, minBit 4, minWin=27, winSum=445
1317 11:45:20.651844 TX Vref=32, minBit 9, minWin=27, winSum=445
1318 11:45:20.655141 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 26
1319 11:45:20.655247
1320 11:45:20.658092 Final TX Range 1 Vref 26
1321 11:45:20.658198
1322 11:45:20.658290 ==
1323 11:45:20.661603 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 11:45:20.664978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 11:45:20.668156 ==
1326 11:45:20.668242
1327 11:45:20.668309
1328 11:45:20.668369 TX Vref Scan disable
1329 11:45:20.675596 == TX Byte 0 ==
1330 11:45:20.675682 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1331 11:45:20.682194 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1332 11:45:20.682301 == TX Byte 1 ==
1333 11:45:20.685070 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1334 11:45:20.691871 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1335 11:45:20.691959
1336 11:45:20.692024 [DATLAT]
1337 11:45:20.692084 Freq=800, CH0 RK1
1338 11:45:20.692141
1339 11:45:20.695421 DATLAT Default: 0xa
1340 11:45:20.695502 0, 0xFFFF, sum = 0
1341 11:45:20.698657 1, 0xFFFF, sum = 0
1342 11:45:20.698763 2, 0xFFFF, sum = 0
1343 11:45:20.702548 3, 0xFFFF, sum = 0
1344 11:45:20.705267 4, 0xFFFF, sum = 0
1345 11:45:20.705350 5, 0xFFFF, sum = 0
1346 11:45:20.708473 6, 0xFFFF, sum = 0
1347 11:45:20.708555 7, 0xFFFF, sum = 0
1348 11:45:20.711973 8, 0xFFFF, sum = 0
1349 11:45:20.712055 9, 0x0, sum = 1
1350 11:45:20.712120 10, 0x0, sum = 2
1351 11:45:20.715162 11, 0x0, sum = 3
1352 11:45:20.715244 12, 0x0, sum = 4
1353 11:45:20.718971 best_step = 10
1354 11:45:20.719052
1355 11:45:20.719123 ==
1356 11:45:20.722157 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 11:45:20.725079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 11:45:20.725177 ==
1359 11:45:20.728634 RX Vref Scan: 0
1360 11:45:20.728716
1361 11:45:20.728779 RX Vref 0 -> 0, step: 1
1362 11:45:20.731555
1363 11:45:20.731657 RX Delay -111 -> 252, step: 8
1364 11:45:20.739220 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1365 11:45:20.742172 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1366 11:45:20.745597 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1367 11:45:20.748622 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1368 11:45:20.752474 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1369 11:45:20.758910 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1370 11:45:20.761902 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1371 11:45:20.765599 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1372 11:45:20.768632 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1373 11:45:20.772224 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1374 11:45:20.778572 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1375 11:45:20.782441 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1376 11:45:20.785006 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1377 11:45:20.789623 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1378 11:45:20.795239 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1379 11:45:20.798549 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1380 11:45:20.798634 ==
1381 11:45:20.801978 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 11:45:20.805454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:45:20.805537 ==
1384 11:45:20.808352 DQS Delay:
1385 11:45:20.808433 DQS0 = 0, DQS1 = 0
1386 11:45:20.808498 DQM Delay:
1387 11:45:20.812032 DQM0 = 87, DQM1 = 77
1388 11:45:20.812115 DQ Delay:
1389 11:45:20.814999 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1390 11:45:20.818629 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1391 11:45:20.821887 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1392 11:45:20.825569 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1393 11:45:20.825652
1394 11:45:20.825717
1395 11:45:20.835124 [DQSOSCAuto] RK1, (LSB)MR18= 0x4108, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1396 11:45:20.835250 CH0 RK1: MR19=606, MR18=4108
1397 11:45:20.841882 CH0_RK1: MR19=0x606, MR18=0x4108, DQSOSC=393, MR23=63, INC=95, DEC=63
1398 11:45:20.845161 [RxdqsGatingPostProcess] freq 800
1399 11:45:20.851687 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1400 11:45:20.855093 Pre-setting of DQS Precalculation
1401 11:45:20.858747 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1402 11:45:20.858836 ==
1403 11:45:20.861386 Dram Type= 6, Freq= 0, CH_1, rank 0
1404 11:45:20.868556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 11:45:20.868650 ==
1406 11:45:20.871421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 11:45:20.878183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 11:45:20.887917 [CA 0] Center 36 (6~67) winsize 62
1409 11:45:20.890809 [CA 1] Center 37 (7~67) winsize 61
1410 11:45:20.894287 [CA 2] Center 34 (4~65) winsize 62
1411 11:45:20.897336 [CA 3] Center 34 (3~65) winsize 63
1412 11:45:20.900412 [CA 4] Center 34 (4~65) winsize 62
1413 11:45:20.903921 [CA 5] Center 34 (3~65) winsize 63
1414 11:45:20.904003
1415 11:45:20.907902 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 11:45:20.907985
1417 11:45:20.910446 [CATrainingPosCal] consider 1 rank data
1418 11:45:20.914325 u2DelayCellTimex100 = 270/100 ps
1419 11:45:20.917236 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 11:45:20.920580 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1421 11:45:20.927082 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 11:45:20.930665 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1423 11:45:20.934026 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 11:45:20.937468 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1425 11:45:20.937556
1426 11:45:20.940688 CA PerBit enable=1, Macro0, CA PI delay=34
1427 11:45:20.940771
1428 11:45:20.943622 [CBTSetCACLKResult] CA Dly = 34
1429 11:45:20.943704 CS Dly: 4 (0~35)
1430 11:45:20.947346 ==
1431 11:45:20.950411 Dram Type= 6, Freq= 0, CH_1, rank 1
1432 11:45:20.953764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 11:45:20.953848 ==
1434 11:45:20.956865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 11:45:20.964072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 11:45:20.973430 [CA 0] Center 36 (6~67) winsize 62
1437 11:45:20.977100 [CA 1] Center 36 (6~67) winsize 62
1438 11:45:20.980137 [CA 2] Center 34 (4~65) winsize 62
1439 11:45:20.983617 [CA 3] Center 34 (4~65) winsize 62
1440 11:45:20.987030 [CA 4] Center 34 (4~65) winsize 62
1441 11:45:20.990135 [CA 5] Center 34 (3~65) winsize 63
1442 11:45:20.990216
1443 11:45:20.993614 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1444 11:45:20.993696
1445 11:45:20.996898 [CATrainingPosCal] consider 2 rank data
1446 11:45:21.000340 u2DelayCellTimex100 = 270/100 ps
1447 11:45:21.002993 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1448 11:45:21.010315 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1449 11:45:21.013812 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1450 11:45:21.016874 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1451 11:45:21.019766 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 11:45:21.023244 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1453 11:45:21.023329
1454 11:45:21.027005 CA PerBit enable=1, Macro0, CA PI delay=34
1455 11:45:21.027088
1456 11:45:21.029713 [CBTSetCACLKResult] CA Dly = 34
1457 11:45:21.029810 CS Dly: 5 (0~38)
1458 11:45:21.032997
1459 11:45:21.036661 ----->DramcWriteLeveling(PI) begin...
1460 11:45:21.036749 ==
1461 11:45:21.040127 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 11:45:21.044283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 11:45:21.044368 ==
1464 11:45:21.046418 Write leveling (Byte 0): 26 => 26
1465 11:45:21.049669 Write leveling (Byte 1): 27 => 27
1466 11:45:21.053572 DramcWriteLeveling(PI) end<-----
1467 11:45:21.053660
1468 11:45:21.053724 ==
1469 11:45:21.056722 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 11:45:21.059751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 11:45:21.059834 ==
1472 11:45:21.063011 [Gating] SW mode calibration
1473 11:45:21.069886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1474 11:45:21.076356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1475 11:45:21.079848 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1476 11:45:21.083701 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1477 11:45:21.089691 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1478 11:45:21.092915 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:45:21.096337 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:45:21.099671 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:45:21.106493 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:45:21.109646 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:45:21.112946 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:45:21.119440 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:45:21.123011 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:45:21.126373 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:45:21.133090 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:45:21.136404 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:45:21.139925 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:45:21.146055 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:45:21.149242 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1492 11:45:21.152891 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1493 11:45:21.159648 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1494 11:45:21.162498 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:45:21.165829 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:45:21.172622 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:45:21.176072 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:45:21.179121 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:45:21.186017 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:45:21.189248 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:45:21.192915 0 9 8 | B1->B0 | 2a2a 3232 | 1 1 | (1 1) (1 1)
1502 11:45:21.199009 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 11:45:21.202490 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 11:45:21.206259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 11:45:21.212651 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 11:45:21.215613 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 11:45:21.219255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1508 11:45:21.225724 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1509 11:45:21.228966 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1510 11:45:21.232268 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:45:21.239472 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:45:21.242497 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:45:21.245858 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:45:21.252215 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:45:21.256044 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:45:21.258869 0 11 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1517 11:45:21.262303 0 11 8 | B1->B0 | 3c3c 4040 | 0 0 | (0 0) (0 0)
1518 11:45:21.268919 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 11:45:21.272063 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 11:45:21.275402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 11:45:21.282165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 11:45:21.285396 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 11:45:21.289174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 11:45:21.295640 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1525 11:45:21.298772 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1526 11:45:21.302509 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 11:45:21.308357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 11:45:21.311756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 11:45:21.314953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 11:45:21.321726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 11:45:21.325253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 11:45:21.328108 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 11:45:21.335088 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 11:45:21.338192 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 11:45:21.341344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 11:45:21.348300 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 11:45:21.351915 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 11:45:21.355194 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 11:45:21.361092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 11:45:21.364610 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1541 11:45:21.368193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1542 11:45:21.371189 Total UI for P1: 0, mck2ui 16
1543 11:45:21.375116 best dqsien dly found for B0: ( 0, 14, 4)
1544 11:45:21.381057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 11:45:21.381175 Total UI for P1: 0, mck2ui 16
1546 11:45:21.387801 best dqsien dly found for B1: ( 0, 14, 6)
1547 11:45:21.391789 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1548 11:45:21.394698 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1549 11:45:21.394807
1550 11:45:21.397828 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1551 11:45:21.401041 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1552 11:45:21.404587 [Gating] SW calibration Done
1553 11:45:21.404697 ==
1554 11:45:21.408118 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 11:45:21.410886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 11:45:21.410996 ==
1557 11:45:21.414337 RX Vref Scan: 0
1558 11:45:21.414442
1559 11:45:21.414535 RX Vref 0 -> 0, step: 1
1560 11:45:21.414624
1561 11:45:21.417943 RX Delay -130 -> 252, step: 16
1562 11:45:21.421130 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1563 11:45:21.428175 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1564 11:45:21.431378 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1565 11:45:21.434773 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1566 11:45:21.438263 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1567 11:45:21.441546 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1568 11:45:21.448057 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1569 11:45:21.451127 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1570 11:45:21.454636 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1571 11:45:21.457995 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1572 11:45:21.461082 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1573 11:45:21.467586 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1574 11:45:21.471080 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1575 11:45:21.474418 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1576 11:45:21.477569 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1577 11:45:21.484132 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1578 11:45:21.484221 ==
1579 11:45:21.487676 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 11:45:21.491047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 11:45:21.491131 ==
1582 11:45:21.491197 DQS Delay:
1583 11:45:21.494027 DQS0 = 0, DQS1 = 0
1584 11:45:21.494108 DQM Delay:
1585 11:45:21.497621 DQM0 = 89, DQM1 = 79
1586 11:45:21.497703 DQ Delay:
1587 11:45:21.500831 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1588 11:45:21.503927 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1589 11:45:21.507855 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1590 11:45:21.510931 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1591 11:45:21.511014
1592 11:45:21.511079
1593 11:45:21.511139 ==
1594 11:45:21.513833 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 11:45:21.517443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 11:45:21.517528 ==
1597 11:45:21.520462
1598 11:45:21.520542
1599 11:45:21.520606 TX Vref Scan disable
1600 11:45:21.523806 == TX Byte 0 ==
1601 11:45:21.527536 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 11:45:21.530480 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 11:45:21.534045 == TX Byte 1 ==
1604 11:45:21.537389 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1605 11:45:21.540731 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1606 11:45:21.540817 ==
1607 11:45:21.543779 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 11:45:21.550371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 11:45:21.550501 ==
1610 11:45:21.562249 TX Vref=22, minBit 8, minWin=26, winSum=442
1611 11:45:21.565711 TX Vref=24, minBit 8, minWin=26, winSum=446
1612 11:45:21.568893 TX Vref=26, minBit 10, minWin=27, winSum=446
1613 11:45:21.572185 TX Vref=28, minBit 10, minWin=27, winSum=449
1614 11:45:21.576186 TX Vref=30, minBit 10, minWin=27, winSum=447
1615 11:45:21.582748 TX Vref=32, minBit 8, minWin=27, winSum=445
1616 11:45:21.585788 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 28
1617 11:45:21.585873
1618 11:45:21.589006 Final TX Range 1 Vref 28
1619 11:45:21.589088
1620 11:45:21.589152 ==
1621 11:45:21.592169 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:45:21.595593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:45:21.598707 ==
1624 11:45:21.598789
1625 11:45:21.598853
1626 11:45:21.598913 TX Vref Scan disable
1627 11:45:21.602662 == TX Byte 0 ==
1628 11:45:21.606061 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1629 11:45:21.609367 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1630 11:45:21.612871 == TX Byte 1 ==
1631 11:45:21.616300 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1632 11:45:21.619404 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1633 11:45:21.622840
1634 11:45:21.622924 [DATLAT]
1635 11:45:21.622990 Freq=800, CH1 RK0
1636 11:45:21.623051
1637 11:45:21.626624 DATLAT Default: 0xa
1638 11:45:21.626706 0, 0xFFFF, sum = 0
1639 11:45:21.629401 1, 0xFFFF, sum = 0
1640 11:45:21.629509 2, 0xFFFF, sum = 0
1641 11:45:21.632725 3, 0xFFFF, sum = 0
1642 11:45:21.632808 4, 0xFFFF, sum = 0
1643 11:45:21.636246 5, 0xFFFF, sum = 0
1644 11:45:21.636330 6, 0xFFFF, sum = 0
1645 11:45:21.639314 7, 0xFFFF, sum = 0
1646 11:45:21.642664 8, 0xFFFF, sum = 0
1647 11:45:21.642747 9, 0x0, sum = 1
1648 11:45:21.642813 10, 0x0, sum = 2
1649 11:45:21.645860 11, 0x0, sum = 3
1650 11:45:21.645943 12, 0x0, sum = 4
1651 11:45:21.649404 best_step = 10
1652 11:45:21.649525
1653 11:45:21.649590 ==
1654 11:45:21.652684 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 11:45:21.655787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 11:45:21.655869 ==
1657 11:45:21.659176 RX Vref Scan: 1
1658 11:45:21.659257
1659 11:45:21.659322 Set Vref Range= 32 -> 127
1660 11:45:21.662567
1661 11:45:21.662648 RX Vref 32 -> 127, step: 1
1662 11:45:21.662713
1663 11:45:21.665682 RX Delay -95 -> 252, step: 8
1664 11:45:21.665762
1665 11:45:21.669334 Set Vref, RX VrefLevel [Byte0]: 32
1666 11:45:21.672470 [Byte1]: 32
1667 11:45:21.672550
1668 11:45:21.676317 Set Vref, RX VrefLevel [Byte0]: 33
1669 11:45:21.678935 [Byte1]: 33
1670 11:45:21.683223
1671 11:45:21.683303 Set Vref, RX VrefLevel [Byte0]: 34
1672 11:45:21.686065 [Byte1]: 34
1673 11:45:21.690622
1674 11:45:21.690703 Set Vref, RX VrefLevel [Byte0]: 35
1675 11:45:21.694307 [Byte1]: 35
1676 11:45:21.698078
1677 11:45:21.698158 Set Vref, RX VrefLevel [Byte0]: 36
1678 11:45:21.701735 [Byte1]: 36
1679 11:45:21.706365
1680 11:45:21.706446 Set Vref, RX VrefLevel [Byte0]: 37
1681 11:45:21.708903 [Byte1]: 37
1682 11:45:21.713151
1683 11:45:21.713232 Set Vref, RX VrefLevel [Byte0]: 38
1684 11:45:21.716806 [Byte1]: 38
1685 11:45:21.721452
1686 11:45:21.721534 Set Vref, RX VrefLevel [Byte0]: 39
1687 11:45:21.724305 [Byte1]: 39
1688 11:45:21.728614
1689 11:45:21.728695 Set Vref, RX VrefLevel [Byte0]: 40
1690 11:45:21.732509 [Byte1]: 40
1691 11:45:21.736170
1692 11:45:21.736286 Set Vref, RX VrefLevel [Byte0]: 41
1693 11:45:21.739551 [Byte1]: 41
1694 11:45:21.743807
1695 11:45:21.743888 Set Vref, RX VrefLevel [Byte0]: 42
1696 11:45:21.746843 [Byte1]: 42
1697 11:45:21.752034
1698 11:45:21.752115 Set Vref, RX VrefLevel [Byte0]: 43
1699 11:45:21.755032 [Byte1]: 43
1700 11:45:21.759213
1701 11:45:21.759294 Set Vref, RX VrefLevel [Byte0]: 44
1702 11:45:21.762641 [Byte1]: 44
1703 11:45:21.766461
1704 11:45:21.766542 Set Vref, RX VrefLevel [Byte0]: 45
1705 11:45:21.770122 [Byte1]: 45
1706 11:45:21.774216
1707 11:45:21.774297 Set Vref, RX VrefLevel [Byte0]: 46
1708 11:45:21.777865 [Byte1]: 46
1709 11:45:21.781786
1710 11:45:21.781867 Set Vref, RX VrefLevel [Byte0]: 47
1711 11:45:21.785198 [Byte1]: 47
1712 11:45:21.789778
1713 11:45:21.789858 Set Vref, RX VrefLevel [Byte0]: 48
1714 11:45:21.792580 [Byte1]: 48
1715 11:45:21.797091
1716 11:45:21.797174 Set Vref, RX VrefLevel [Byte0]: 49
1717 11:45:21.800088 [Byte1]: 49
1718 11:45:21.804746
1719 11:45:21.804827 Set Vref, RX VrefLevel [Byte0]: 50
1720 11:45:21.807873 [Byte1]: 50
1721 11:45:21.812432
1722 11:45:21.812514 Set Vref, RX VrefLevel [Byte0]: 51
1723 11:45:21.815590 [Byte1]: 51
1724 11:45:21.819796
1725 11:45:21.819877 Set Vref, RX VrefLevel [Byte0]: 52
1726 11:45:21.822976 [Byte1]: 52
1727 11:45:21.827497
1728 11:45:21.827604 Set Vref, RX VrefLevel [Byte0]: 53
1729 11:45:21.830680 [Byte1]: 53
1730 11:45:21.834812
1731 11:45:21.838212 Set Vref, RX VrefLevel [Byte0]: 54
1732 11:45:21.841665 [Byte1]: 54
1733 11:45:21.841773
1734 11:45:21.844667 Set Vref, RX VrefLevel [Byte0]: 55
1735 11:45:21.848421 [Byte1]: 55
1736 11:45:21.848529
1737 11:45:21.851413 Set Vref, RX VrefLevel [Byte0]: 56
1738 11:45:21.854427 [Byte1]: 56
1739 11:45:21.854535
1740 11:45:21.857941 Set Vref, RX VrefLevel [Byte0]: 57
1741 11:45:21.861251 [Byte1]: 57
1742 11:45:21.865675
1743 11:45:21.865781 Set Vref, RX VrefLevel [Byte0]: 58
1744 11:45:21.868623 [Byte1]: 58
1745 11:45:21.873031
1746 11:45:21.873136 Set Vref, RX VrefLevel [Byte0]: 59
1747 11:45:21.876063 [Byte1]: 59
1748 11:45:21.880373
1749 11:45:21.880477 Set Vref, RX VrefLevel [Byte0]: 60
1750 11:45:21.883529 [Byte1]: 60
1751 11:45:21.887960
1752 11:45:21.888067 Set Vref, RX VrefLevel [Byte0]: 61
1753 11:45:21.891909 [Byte1]: 61
1754 11:45:21.895723
1755 11:45:21.895829 Set Vref, RX VrefLevel [Byte0]: 62
1756 11:45:21.899517 [Byte1]: 62
1757 11:45:21.903149
1758 11:45:21.903255 Set Vref, RX VrefLevel [Byte0]: 63
1759 11:45:21.906544 [Byte1]: 63
1760 11:45:21.911479
1761 11:45:21.911591 Set Vref, RX VrefLevel [Byte0]: 64
1762 11:45:21.914140 [Byte1]: 64
1763 11:45:21.918451
1764 11:45:21.918557 Set Vref, RX VrefLevel [Byte0]: 65
1765 11:45:21.921883 [Byte1]: 65
1766 11:45:21.926172
1767 11:45:21.926280 Set Vref, RX VrefLevel [Byte0]: 66
1768 11:45:21.929596 [Byte1]: 66
1769 11:45:21.933579
1770 11:45:21.933685 Set Vref, RX VrefLevel [Byte0]: 67
1771 11:45:21.936903 [Byte1]: 67
1772 11:45:21.941221
1773 11:45:21.941327 Set Vref, RX VrefLevel [Byte0]: 68
1774 11:45:21.945347 [Byte1]: 68
1775 11:45:21.949108
1776 11:45:21.949218 Set Vref, RX VrefLevel [Byte0]: 69
1777 11:45:21.952272 [Byte1]: 69
1778 11:45:21.956455
1779 11:45:21.956566 Set Vref, RX VrefLevel [Byte0]: 70
1780 11:45:21.960171 [Byte1]: 70
1781 11:45:21.964022
1782 11:45:21.964128 Set Vref, RX VrefLevel [Byte0]: 71
1783 11:45:21.970321 [Byte1]: 71
1784 11:45:21.970432
1785 11:45:21.973609 Set Vref, RX VrefLevel [Byte0]: 72
1786 11:45:21.976959 [Byte1]: 72
1787 11:45:21.977066
1788 11:45:21.980525 Set Vref, RX VrefLevel [Byte0]: 73
1789 11:45:21.984138 [Byte1]: 73
1790 11:45:21.984220
1791 11:45:21.987239 Set Vref, RX VrefLevel [Byte0]: 74
1792 11:45:21.990178 [Byte1]: 74
1793 11:45:21.994673
1794 11:45:21.994755 Set Vref, RX VrefLevel [Byte0]: 75
1795 11:45:21.998058 [Byte1]: 75
1796 11:45:22.001996
1797 11:45:22.002078 Set Vref, RX VrefLevel [Byte0]: 76
1798 11:45:22.005867 [Byte1]: 76
1799 11:45:22.010271
1800 11:45:22.010352 Final RX Vref Byte 0 = 57 to rank0
1801 11:45:22.013108 Final RX Vref Byte 1 = 66 to rank0
1802 11:45:22.016416 Final RX Vref Byte 0 = 57 to rank1
1803 11:45:22.019785 Final RX Vref Byte 1 = 66 to rank1==
1804 11:45:22.023537 Dram Type= 6, Freq= 0, CH_1, rank 0
1805 11:45:22.026887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 11:45:22.030066 ==
1807 11:45:22.030149 DQS Delay:
1808 11:45:22.030214 DQS0 = 0, DQS1 = 0
1809 11:45:22.032770 DQM Delay:
1810 11:45:22.032850 DQM0 = 87, DQM1 = 78
1811 11:45:22.036296 DQ Delay:
1812 11:45:22.039444 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
1813 11:45:22.042806 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1814 11:45:22.046146 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1815 11:45:22.049375 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1816 11:45:22.049481
1817 11:45:22.049547
1818 11:45:22.056752 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1819 11:45:22.059271 CH1 RK0: MR19=606, MR18=311D
1820 11:45:22.066495 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1821 11:45:22.066580
1822 11:45:22.069738 ----->DramcWriteLeveling(PI) begin...
1823 11:45:22.069821 ==
1824 11:45:22.072669 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 11:45:22.076302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 11:45:22.076384 ==
1827 11:45:22.079658 Write leveling (Byte 0): 28 => 28
1828 11:45:22.083158 Write leveling (Byte 1): 29 => 29
1829 11:45:22.086324 DramcWriteLeveling(PI) end<-----
1830 11:45:22.086406
1831 11:45:22.086470 ==
1832 11:45:22.089348 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 11:45:22.092654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:45:22.092735 ==
1835 11:45:22.096368 [Gating] SW mode calibration
1836 11:45:22.102432 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1837 11:45:22.109191 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1838 11:45:22.113097 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1839 11:45:22.115848 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1840 11:45:22.122489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:45:22.126274 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:45:22.132929 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:45:22.136156 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:45:22.139138 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:45:22.142575 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:45:22.149187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:45:22.152670 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:45:22.156390 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:45:22.162154 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:45:22.165573 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:45:22.168830 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:45:22.175467 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:45:22.179290 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:45:22.182285 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1855 11:45:22.189339 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1856 11:45:22.192941 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1857 11:45:22.196129 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:45:22.202541 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:45:22.205281 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:45:22.208926 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:45:22.215451 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:45:22.218823 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:45:22.222104 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1864 11:45:22.228820 0 9 8 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 1)
1865 11:45:22.232200 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 11:45:22.235771 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 11:45:22.242621 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 11:45:22.245564 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 11:45:22.249054 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 11:45:22.255383 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 11:45:22.258647 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
1872 11:45:22.262279 0 10 8 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (0 0)
1873 11:45:22.269020 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:45:22.271693 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:45:22.275438 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:45:22.281773 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:45:22.285078 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:45:22.288814 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:45:22.294998 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1880 11:45:22.298268 0 11 8 | B1->B0 | 4545 3b3b | 0 0 | (0 0) (0 0)
1881 11:45:22.301751 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 11:45:22.304686 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 11:45:22.311406 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 11:45:22.315422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 11:45:22.318625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 11:45:22.325041 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 11:45:22.328554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 11:45:22.331387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 11:45:22.337814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 11:45:22.341210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 11:45:22.345056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 11:45:22.351306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 11:45:22.354857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 11:45:22.358408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 11:45:22.364442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 11:45:22.367845 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 11:45:22.371356 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 11:45:22.377542 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:45:22.380863 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:45:22.384324 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:45:22.390953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:45:22.394458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:45:22.397628 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1904 11:45:22.404260 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1905 11:45:22.404361 Total UI for P1: 0, mck2ui 16
1906 11:45:22.410787 best dqsien dly found for B1: ( 0, 14, 4)
1907 11:45:22.414242 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 11:45:22.417923 Total UI for P1: 0, mck2ui 16
1909 11:45:22.421000 best dqsien dly found for B0: ( 0, 14, 8)
1910 11:45:22.424140 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1911 11:45:22.427514 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1912 11:45:22.427590
1913 11:45:22.430728 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1914 11:45:22.433894 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1915 11:45:22.437057 [Gating] SW calibration Done
1916 11:45:22.437158 ==
1917 11:45:22.440329 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 11:45:22.443938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 11:45:22.447156 ==
1920 11:45:22.447256 RX Vref Scan: 0
1921 11:45:22.447351
1922 11:45:22.450536 RX Vref 0 -> 0, step: 1
1923 11:45:22.450620
1924 11:45:22.454174 RX Delay -130 -> 252, step: 16
1925 11:45:22.457044 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1926 11:45:22.460432 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1927 11:45:22.463894 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1928 11:45:22.467290 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1929 11:45:22.473831 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1930 11:45:22.476949 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1931 11:45:22.480367 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1932 11:45:22.483523 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1933 11:45:22.487277 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1934 11:45:22.494109 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1935 11:45:22.497178 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1936 11:45:22.501063 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1937 11:45:22.504053 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1938 11:45:22.507149 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1939 11:45:22.514343 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1940 11:45:22.517151 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1941 11:45:22.517233 ==
1942 11:45:22.520290 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 11:45:22.523807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 11:45:22.523890 ==
1945 11:45:22.527278 DQS Delay:
1946 11:45:22.527364 DQS0 = 0, DQS1 = 0
1947 11:45:22.527429 DQM Delay:
1948 11:45:22.530032 DQM0 = 87, DQM1 = 79
1949 11:45:22.530113 DQ Delay:
1950 11:45:22.533246 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1951 11:45:22.536502 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1952 11:45:22.540218 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1953 11:45:22.543212 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1954 11:45:22.543288
1955 11:45:22.543352
1956 11:45:22.546492 ==
1957 11:45:22.549824 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 11:45:22.553170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 11:45:22.553252 ==
1960 11:45:22.553316
1961 11:45:22.553376
1962 11:45:22.556753 TX Vref Scan disable
1963 11:45:22.556834 == TX Byte 0 ==
1964 11:45:22.559917 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 11:45:22.566420 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 11:45:22.566503 == TX Byte 1 ==
1967 11:45:22.569679 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 11:45:22.576797 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 11:45:22.576879 ==
1970 11:45:22.579803 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 11:45:22.584171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 11:45:22.584255 ==
1973 11:45:22.596228 TX Vref=22, minBit 1, minWin=27, winSum=444
1974 11:45:22.599617 TX Vref=24, minBit 9, minWin=27, winSum=448
1975 11:45:22.603098 TX Vref=26, minBit 8, minWin=27, winSum=450
1976 11:45:22.606218 TX Vref=28, minBit 15, minWin=27, winSum=452
1977 11:45:22.609664 TX Vref=30, minBit 13, minWin=27, winSum=450
1978 11:45:22.616696 TX Vref=32, minBit 13, minWin=27, winSum=448
1979 11:45:22.620019 [TxChooseVref] Worse bit 15, Min win 27, Win sum 452, Final Vref 28
1980 11:45:22.620101
1981 11:45:22.622861 Final TX Range 1 Vref 28
1982 11:45:22.622942
1983 11:45:22.623007 ==
1984 11:45:22.626235 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:45:22.632942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:45:22.633026 ==
1987 11:45:22.633092
1988 11:45:22.633151
1989 11:45:22.633209 TX Vref Scan disable
1990 11:45:22.636486 == TX Byte 0 ==
1991 11:45:22.640019 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1992 11:45:22.646819 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1993 11:45:22.646903 == TX Byte 1 ==
1994 11:45:22.650403 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1995 11:45:22.656479 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1996 11:45:22.656564
1997 11:45:22.656628 [DATLAT]
1998 11:45:22.656689 Freq=800, CH1 RK1
1999 11:45:22.656749
2000 11:45:22.659713 DATLAT Default: 0xa
2001 11:45:22.662879 0, 0xFFFF, sum = 0
2002 11:45:22.662963 1, 0xFFFF, sum = 0
2003 11:45:22.666596 2, 0xFFFF, sum = 0
2004 11:45:22.666708 3, 0xFFFF, sum = 0
2005 11:45:22.669666 4, 0xFFFF, sum = 0
2006 11:45:22.669748 5, 0xFFFF, sum = 0
2007 11:45:22.672728 6, 0xFFFF, sum = 0
2008 11:45:22.672810 7, 0xFFFF, sum = 0
2009 11:45:22.676410 8, 0xFFFF, sum = 0
2010 11:45:22.676493 9, 0x0, sum = 1
2011 11:45:22.679836 10, 0x0, sum = 2
2012 11:45:22.679921 11, 0x0, sum = 3
2013 11:45:22.682798 12, 0x0, sum = 4
2014 11:45:22.682881 best_step = 10
2015 11:45:22.682945
2016 11:45:22.683005 ==
2017 11:45:22.686209 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:45:22.689562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:45:22.689645 ==
2020 11:45:22.693110 RX Vref Scan: 0
2021 11:45:22.693191
2022 11:45:22.696127 RX Vref 0 -> 0, step: 1
2023 11:45:22.696216
2024 11:45:22.696283 RX Delay -95 -> 252, step: 8
2025 11:45:22.703383 iDelay=217, Bit 0, Center 96 (-15 ~ 208) 224
2026 11:45:22.706491 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2027 11:45:22.710011 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2028 11:45:22.713047 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2029 11:45:22.716554 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2030 11:45:22.723346 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2031 11:45:22.726290 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2032 11:45:22.729674 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2033 11:45:22.732829 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2034 11:45:22.739675 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2035 11:45:22.743360 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2036 11:45:22.746364 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2037 11:45:22.749786 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2038 11:45:22.753142 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2039 11:45:22.759765 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2040 11:45:22.763222 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2041 11:45:22.763305 ==
2042 11:45:22.766071 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 11:45:22.769307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 11:45:22.769390 ==
2045 11:45:22.773192 DQS Delay:
2046 11:45:22.773274 DQS0 = 0, DQS1 = 0
2047 11:45:22.773338 DQM Delay:
2048 11:45:22.776437 DQM0 = 87, DQM1 = 79
2049 11:45:22.776518 DQ Delay:
2050 11:45:22.779894 DQ0 =96, DQ1 =80, DQ2 =76, DQ3 =84
2051 11:45:22.782574 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2052 11:45:22.786307 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =68
2053 11:45:22.789568 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2054 11:45:22.789650
2055 11:45:22.789714
2056 11:45:22.799982 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
2057 11:45:22.802769 CH1 RK1: MR19=606, MR18=1B14
2058 11:45:22.805985 CH1_RK1: MR19=0x606, MR18=0x1B14, DQSOSC=403, MR23=63, INC=90, DEC=60
2059 11:45:22.809259 [RxdqsGatingPostProcess] freq 800
2060 11:45:22.815714 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2061 11:45:22.819123 Pre-setting of DQS Precalculation
2062 11:45:22.822824 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2063 11:45:22.832672 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2064 11:45:22.839296 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2065 11:45:22.839387
2066 11:45:22.839452
2067 11:45:22.842277 [Calibration Summary] 1600 Mbps
2068 11:45:22.842387 CH 0, Rank 0
2069 11:45:22.845959 SW Impedance : PASS
2070 11:45:22.846040 DUTY Scan : NO K
2071 11:45:22.849656 ZQ Calibration : PASS
2072 11:45:22.852168 Jitter Meter : NO K
2073 11:45:22.852253 CBT Training : PASS
2074 11:45:22.855550 Write leveling : PASS
2075 11:45:22.858860 RX DQS gating : PASS
2076 11:45:22.858943 RX DQ/DQS(RDDQC) : PASS
2077 11:45:22.862903 TX DQ/DQS : PASS
2078 11:45:22.865621 RX DATLAT : PASS
2079 11:45:22.865703 RX DQ/DQS(Engine): PASS
2080 11:45:22.869138 TX OE : NO K
2081 11:45:22.869221 All Pass.
2082 11:45:22.869285
2083 11:45:22.871935 CH 0, Rank 1
2084 11:45:22.872016 SW Impedance : PASS
2085 11:45:22.875875 DUTY Scan : NO K
2086 11:45:22.878590 ZQ Calibration : PASS
2087 11:45:22.878674 Jitter Meter : NO K
2088 11:45:22.882498 CBT Training : PASS
2089 11:45:22.882580 Write leveling : PASS
2090 11:45:22.885568 RX DQS gating : PASS
2091 11:45:22.888944 RX DQ/DQS(RDDQC) : PASS
2092 11:45:22.889025 TX DQ/DQS : PASS
2093 11:45:22.892106 RX DATLAT : PASS
2094 11:45:22.895507 RX DQ/DQS(Engine): PASS
2095 11:45:22.895588 TX OE : NO K
2096 11:45:22.898693 All Pass.
2097 11:45:22.898775
2098 11:45:22.898839 CH 1, Rank 0
2099 11:45:22.902154 SW Impedance : PASS
2100 11:45:22.902236 DUTY Scan : NO K
2101 11:45:22.905385 ZQ Calibration : PASS
2102 11:45:22.908828 Jitter Meter : NO K
2103 11:45:22.908954 CBT Training : PASS
2104 11:45:22.912297 Write leveling : PASS
2105 11:45:22.915231 RX DQS gating : PASS
2106 11:45:22.915314 RX DQ/DQS(RDDQC) : PASS
2107 11:45:22.918753 TX DQ/DQS : PASS
2108 11:45:22.921919 RX DATLAT : PASS
2109 11:45:22.922003 RX DQ/DQS(Engine): PASS
2110 11:45:22.925513 TX OE : NO K
2111 11:45:22.925593 All Pass.
2112 11:45:22.925657
2113 11:45:22.928711 CH 1, Rank 1
2114 11:45:22.928786 SW Impedance : PASS
2115 11:45:22.932122 DUTY Scan : NO K
2116 11:45:22.932204 ZQ Calibration : PASS
2117 11:45:22.935681 Jitter Meter : NO K
2118 11:45:22.938631 CBT Training : PASS
2119 11:45:22.938740 Write leveling : PASS
2120 11:45:22.942087 RX DQS gating : PASS
2121 11:45:22.945377 RX DQ/DQS(RDDQC) : PASS
2122 11:45:22.945485 TX DQ/DQS : PASS
2123 11:45:22.948719 RX DATLAT : PASS
2124 11:45:22.951891 RX DQ/DQS(Engine): PASS
2125 11:45:22.951972 TX OE : NO K
2126 11:45:22.955211 All Pass.
2127 11:45:22.955293
2128 11:45:22.955359 DramC Write-DBI off
2129 11:45:22.958673 PER_BANK_REFRESH: Hybrid Mode
2130 11:45:22.958755 TX_TRACKING: ON
2131 11:45:22.965007 [GetDramInforAfterCalByMRR] Vendor 6.
2132 11:45:22.968100 [GetDramInforAfterCalByMRR] Revision 606.
2133 11:45:22.971464 [GetDramInforAfterCalByMRR] Revision 2 0.
2134 11:45:22.971546 MR0 0x3b3b
2135 11:45:22.971612 MR8 0x5151
2136 11:45:22.975287 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 11:45:22.978110
2138 11:45:22.978219 MR0 0x3b3b
2139 11:45:22.978316 MR8 0x5151
2140 11:45:22.981706 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 11:45:22.981788
2142 11:45:22.991484 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2143 11:45:22.994664 [FAST_K] Save calibration result to emmc
2144 11:45:22.997857 [FAST_K] Save calibration result to emmc
2145 11:45:23.001881 dram_init: config_dvfs: 1
2146 11:45:23.004627 dramc_set_vcore_voltage set vcore to 662500
2147 11:45:23.008053 Read voltage for 1200, 2
2148 11:45:23.008135 Vio18 = 0
2149 11:45:23.008198 Vcore = 662500
2150 11:45:23.011108 Vdram = 0
2151 11:45:23.011188 Vddq = 0
2152 11:45:23.011252 Vmddr = 0
2153 11:45:23.018250 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2154 11:45:23.021351 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2155 11:45:23.024586 MEM_TYPE=3, freq_sel=15
2156 11:45:23.028196 sv_algorithm_assistance_LP4_1600
2157 11:45:23.031252 ============ PULL DRAM RESETB DOWN ============
2158 11:45:23.034906 ========== PULL DRAM RESETB DOWN end =========
2159 11:45:23.041651 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2160 11:45:23.044565 ===================================
2161 11:45:23.048392 LPDDR4 DRAM CONFIGURATION
2162 11:45:23.051096 ===================================
2163 11:45:23.051179 EX_ROW_EN[0] = 0x0
2164 11:45:23.054362 EX_ROW_EN[1] = 0x0
2165 11:45:23.054471 LP4Y_EN = 0x0
2166 11:45:23.057714 WORK_FSP = 0x0
2167 11:45:23.057801 WL = 0x4
2168 11:45:23.061193 RL = 0x4
2169 11:45:23.061290 BL = 0x2
2170 11:45:23.064435 RPST = 0x0
2171 11:45:23.064517 RD_PRE = 0x0
2172 11:45:23.067820 WR_PRE = 0x1
2173 11:45:23.067901 WR_PST = 0x0
2174 11:45:23.071244 DBI_WR = 0x0
2175 11:45:23.071325 DBI_RD = 0x0
2176 11:45:23.074439 OTF = 0x1
2177 11:45:23.077750 ===================================
2178 11:45:23.081192 ===================================
2179 11:45:23.081299 ANA top config
2180 11:45:23.084316 ===================================
2181 11:45:23.087644 DLL_ASYNC_EN = 0
2182 11:45:23.090866 ALL_SLAVE_EN = 0
2183 11:45:23.094553 NEW_RANK_MODE = 1
2184 11:45:23.094636 DLL_IDLE_MODE = 1
2185 11:45:23.097455 LP45_APHY_COMB_EN = 1
2186 11:45:23.101228 TX_ODT_DIS = 1
2187 11:45:23.104140 NEW_8X_MODE = 1
2188 11:45:23.107854 ===================================
2189 11:45:23.110796 ===================================
2190 11:45:23.114165 data_rate = 2400
2191 11:45:23.117818 CKR = 1
2192 11:45:23.117901 DQ_P2S_RATIO = 8
2193 11:45:23.121122 ===================================
2194 11:45:23.123943 CA_P2S_RATIO = 8
2195 11:45:23.127589 DQ_CA_OPEN = 0
2196 11:45:23.130585 DQ_SEMI_OPEN = 0
2197 11:45:23.134044 CA_SEMI_OPEN = 0
2198 11:45:23.137552 CA_FULL_RATE = 0
2199 11:45:23.137633 DQ_CKDIV4_EN = 0
2200 11:45:23.140725 CA_CKDIV4_EN = 0
2201 11:45:23.144020 CA_PREDIV_EN = 0
2202 11:45:23.147390 PH8_DLY = 17
2203 11:45:23.150401 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2204 11:45:23.154078 DQ_AAMCK_DIV = 4
2205 11:45:23.154162 CA_AAMCK_DIV = 4
2206 11:45:23.156977 CA_ADMCK_DIV = 4
2207 11:45:23.160717 DQ_TRACK_CA_EN = 0
2208 11:45:23.163857 CA_PICK = 1200
2209 11:45:23.167041 CA_MCKIO = 1200
2210 11:45:23.170787 MCKIO_SEMI = 0
2211 11:45:23.174100 PLL_FREQ = 2366
2212 11:45:23.174182 DQ_UI_PI_RATIO = 32
2213 11:45:23.177155 CA_UI_PI_RATIO = 0
2214 11:45:23.180279 ===================================
2215 11:45:23.183782 ===================================
2216 11:45:23.186799 memory_type:LPDDR4
2217 11:45:23.190315 GP_NUM : 10
2218 11:45:23.190421 SRAM_EN : 1
2219 11:45:23.193683 MD32_EN : 0
2220 11:45:23.196682 ===================================
2221 11:45:23.200429 [ANA_INIT] >>>>>>>>>>>>>>
2222 11:45:23.200509 <<<<<< [CONFIGURE PHASE]: ANA_TX
2223 11:45:23.206670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2224 11:45:23.210348 ===================================
2225 11:45:23.210429 data_rate = 2400,PCW = 0X5b00
2226 11:45:23.213872 ===================================
2227 11:45:23.216769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2228 11:45:23.223148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 11:45:23.230171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 11:45:23.233519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2231 11:45:23.236518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2232 11:45:23.240263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2233 11:45:23.243500 [ANA_INIT] flow start
2234 11:45:23.243581 [ANA_INIT] PLL >>>>>>>>
2235 11:45:23.246979 [ANA_INIT] PLL <<<<<<<<
2236 11:45:23.249708 [ANA_INIT] MIDPI >>>>>>>>
2237 11:45:23.253264 [ANA_INIT] MIDPI <<<<<<<<
2238 11:45:23.253371 [ANA_INIT] DLL >>>>>>>>
2239 11:45:23.256665 [ANA_INIT] DLL <<<<<<<<
2240 11:45:23.256746 [ANA_INIT] flow end
2241 11:45:23.263259 ============ LP4 DIFF to SE enter ============
2242 11:45:23.266879 ============ LP4 DIFF to SE exit ============
2243 11:45:23.269810 [ANA_INIT] <<<<<<<<<<<<<
2244 11:45:23.273745 [Flow] Enable top DCM control >>>>>
2245 11:45:23.276775 [Flow] Enable top DCM control <<<<<
2246 11:45:23.276857 Enable DLL master slave shuffle
2247 11:45:23.283322 ==============================================================
2248 11:45:23.286367 Gating Mode config
2249 11:45:23.289906 ==============================================================
2250 11:45:23.293251 Config description:
2251 11:45:23.303027 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2252 11:45:23.309369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2253 11:45:23.313284 SELPH_MODE 0: By rank 1: By Phase
2254 11:45:23.319322 ==============================================================
2255 11:45:23.322824 GAT_TRACK_EN = 1
2256 11:45:23.325859 RX_GATING_MODE = 2
2257 11:45:23.329643 RX_GATING_TRACK_MODE = 2
2258 11:45:23.332747 SELPH_MODE = 1
2259 11:45:23.336167 PICG_EARLY_EN = 1
2260 11:45:23.336249 VALID_LAT_VALUE = 1
2261 11:45:23.342764 ==============================================================
2262 11:45:23.346292 Enter into Gating configuration >>>>
2263 11:45:23.349120 Exit from Gating configuration <<<<
2264 11:45:23.352765 Enter into DVFS_PRE_config >>>>>
2265 11:45:23.363083 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2266 11:45:23.365696 Exit from DVFS_PRE_config <<<<<
2267 11:45:23.369506 Enter into PICG configuration >>>>
2268 11:45:23.372526 Exit from PICG configuration <<<<
2269 11:45:23.375688 [RX_INPUT] configuration >>>>>
2270 11:45:23.378989 [RX_INPUT] configuration <<<<<
2271 11:45:23.386139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2272 11:45:23.389147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2273 11:45:23.395480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2274 11:45:23.402369 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2275 11:45:23.409078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2276 11:45:23.415741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2277 11:45:23.419082 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2278 11:45:23.422547 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2279 11:45:23.425511 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2280 11:45:23.432166 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2281 11:45:23.435594 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2282 11:45:23.439220 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 11:45:23.442999 ===================================
2284 11:45:23.445698 LPDDR4 DRAM CONFIGURATION
2285 11:45:23.448940 ===================================
2286 11:45:23.449041 EX_ROW_EN[0] = 0x0
2287 11:45:23.452492 EX_ROW_EN[1] = 0x0
2288 11:45:23.452576 LP4Y_EN = 0x0
2289 11:45:23.455689 WORK_FSP = 0x0
2290 11:45:23.455772 WL = 0x4
2291 11:45:23.458656 RL = 0x4
2292 11:45:23.462120 BL = 0x2
2293 11:45:23.462202 RPST = 0x0
2294 11:45:23.465841 RD_PRE = 0x0
2295 11:45:23.465924 WR_PRE = 0x1
2296 11:45:23.468736 WR_PST = 0x0
2297 11:45:23.468819 DBI_WR = 0x0
2298 11:45:23.472135 DBI_RD = 0x0
2299 11:45:23.472218 OTF = 0x1
2300 11:45:23.475780 ===================================
2301 11:45:23.478711 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2302 11:45:23.486001 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2303 11:45:23.488975 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 11:45:23.492159 ===================================
2305 11:45:23.495845 LPDDR4 DRAM CONFIGURATION
2306 11:45:23.498780 ===================================
2307 11:45:23.498862 EX_ROW_EN[0] = 0x10
2308 11:45:23.502332 EX_ROW_EN[1] = 0x0
2309 11:45:23.502413 LP4Y_EN = 0x0
2310 11:45:23.505766 WORK_FSP = 0x0
2311 11:45:23.505847 WL = 0x4
2312 11:45:23.508409 RL = 0x4
2313 11:45:23.508490 BL = 0x2
2314 11:45:23.512068 RPST = 0x0
2315 11:45:23.512150 RD_PRE = 0x0
2316 11:45:23.515323 WR_PRE = 0x1
2317 11:45:23.518504 WR_PST = 0x0
2318 11:45:23.518585 DBI_WR = 0x0
2319 11:45:23.521683 DBI_RD = 0x0
2320 11:45:23.521772 OTF = 0x1
2321 11:45:23.525622 ===================================
2322 11:45:23.531687 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2323 11:45:23.531808 ==
2324 11:45:23.535028 Dram Type= 6, Freq= 0, CH_0, rank 0
2325 11:45:23.538698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2326 11:45:23.538780 ==
2327 11:45:23.541830 [Duty_Offset_Calibration]
2328 11:45:23.541940 B0:1 B1:-1 CA:0
2329 11:45:23.545374
2330 11:45:23.548397 [DutyScan_Calibration_Flow] k_type=0
2331 11:45:23.556207
2332 11:45:23.556293 ==CLK 0==
2333 11:45:23.559742 Final CLK duty delay cell = 0
2334 11:45:23.562951 [0] MAX Duty = 5094%(X100), DQS PI = 16
2335 11:45:23.566544 [0] MIN Duty = 4875%(X100), DQS PI = 8
2336 11:45:23.566624 [0] AVG Duty = 4984%(X100)
2337 11:45:23.569870
2338 11:45:23.569949 CH0 CLK Duty spec in!! Max-Min= 219%
2339 11:45:23.576284 [DutyScan_Calibration_Flow] ====Done====
2340 11:45:23.576365
2341 11:45:23.579549 [DutyScan_Calibration_Flow] k_type=1
2342 11:45:23.594842
2343 11:45:23.594930 ==DQS 0 ==
2344 11:45:23.597968 Final DQS duty delay cell = -4
2345 11:45:23.601279 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2346 11:45:23.604685 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2347 11:45:23.609181 [-4] AVG Duty = 4968%(X100)
2348 11:45:23.609279
2349 11:45:23.609370 ==DQS 1 ==
2350 11:45:23.611250 Final DQS duty delay cell = 0
2351 11:45:23.614956 [0] MAX Duty = 5124%(X100), DQS PI = 4
2352 11:45:23.617704 [0] MIN Duty = 5000%(X100), DQS PI = 22
2353 11:45:23.621342 [0] AVG Duty = 5062%(X100)
2354 11:45:23.621450
2355 11:45:23.624721 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2356 11:45:23.624802
2357 11:45:23.627637 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2358 11:45:23.630752 [DutyScan_Calibration_Flow] ====Done====
2359 11:45:23.630855
2360 11:45:23.634228 [DutyScan_Calibration_Flow] k_type=3
2361 11:45:23.652411
2362 11:45:23.652518 ==DQM 0 ==
2363 11:45:23.655994 Final DQM duty delay cell = 0
2364 11:45:23.659083 [0] MAX Duty = 5062%(X100), DQS PI = 20
2365 11:45:23.662333 [0] MIN Duty = 4875%(X100), DQS PI = 6
2366 11:45:23.662414 [0] AVG Duty = 4968%(X100)
2367 11:45:23.665613
2368 11:45:23.665694 ==DQM 1 ==
2369 11:45:23.668804 Final DQM duty delay cell = 4
2370 11:45:23.672770 [4] MAX Duty = 5187%(X100), DQS PI = 14
2371 11:45:23.675695 [4] MIN Duty = 5000%(X100), DQS PI = 24
2372 11:45:23.679490 [4] AVG Duty = 5093%(X100)
2373 11:45:23.679571
2374 11:45:23.682414 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2375 11:45:23.682502
2376 11:45:23.685671 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2377 11:45:23.688825 [DutyScan_Calibration_Flow] ====Done====
2378 11:45:23.688905
2379 11:45:23.692216 [DutyScan_Calibration_Flow] k_type=2
2380 11:45:23.708259
2381 11:45:23.708361 ==DQ 0 ==
2382 11:45:23.711325 Final DQ duty delay cell = -4
2383 11:45:23.714861 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2384 11:45:23.718161 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2385 11:45:23.721558 [-4] AVG Duty = 4969%(X100)
2386 11:45:23.721640
2387 11:45:23.721704 ==DQ 1 ==
2388 11:45:23.724567 Final DQ duty delay cell = 0
2389 11:45:23.728280 [0] MAX Duty = 5124%(X100), DQS PI = 54
2390 11:45:23.731198 [0] MIN Duty = 4969%(X100), DQS PI = 42
2391 11:45:23.734455 [0] AVG Duty = 5046%(X100)
2392 11:45:23.734538
2393 11:45:23.738090 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2394 11:45:23.738173
2395 11:45:23.741274 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2396 11:45:23.744410 [DutyScan_Calibration_Flow] ====Done====
2397 11:45:23.744493 ==
2398 11:45:23.748237 Dram Type= 6, Freq= 0, CH_1, rank 0
2399 11:45:23.751112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2400 11:45:23.751195 ==
2401 11:45:23.754452 [Duty_Offset_Calibration]
2402 11:45:23.754534 B0:-1 B1:1 CA:1
2403 11:45:23.754599
2404 11:45:23.757693 [DutyScan_Calibration_Flow] k_type=0
2405 11:45:23.768579
2406 11:45:23.768665 ==CLK 0==
2407 11:45:23.771618 Final CLK duty delay cell = 0
2408 11:45:23.774707 [0] MAX Duty = 5156%(X100), DQS PI = 4
2409 11:45:23.778399 [0] MIN Duty = 5000%(X100), DQS PI = 28
2410 11:45:23.778482 [0] AVG Duty = 5078%(X100)
2411 11:45:23.781873
2412 11:45:23.784859 CH1 CLK Duty spec in!! Max-Min= 156%
2413 11:45:23.788713 [DutyScan_Calibration_Flow] ====Done====
2414 11:45:23.788796
2415 11:45:23.791343 [DutyScan_Calibration_Flow] k_type=1
2416 11:45:23.807476
2417 11:45:23.807571 ==DQS 0 ==
2418 11:45:23.811339 Final DQS duty delay cell = 0
2419 11:45:23.814478 [0] MAX Duty = 5156%(X100), DQS PI = 18
2420 11:45:23.817646 [0] MIN Duty = 4875%(X100), DQS PI = 38
2421 11:45:23.821122 [0] AVG Duty = 5015%(X100)
2422 11:45:23.821230
2423 11:45:23.821322 ==DQS 1 ==
2424 11:45:23.824857 Final DQS duty delay cell = 0
2425 11:45:23.827837 [0] MAX Duty = 5094%(X100), DQS PI = 44
2426 11:45:23.830974 [0] MIN Duty = 4969%(X100), DQS PI = 26
2427 11:45:23.834423 [0] AVG Duty = 5031%(X100)
2428 11:45:23.834535
2429 11:45:23.837925 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2430 11:45:23.838008
2431 11:45:23.841065 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2432 11:45:23.844235 [DutyScan_Calibration_Flow] ====Done====
2433 11:45:23.844315
2434 11:45:23.847597 [DutyScan_Calibration_Flow] k_type=3
2435 11:45:23.863498
2436 11:45:23.863602 ==DQM 0 ==
2437 11:45:23.866842 Final DQM duty delay cell = -4
2438 11:45:23.869735 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2439 11:45:23.873247 [-4] MIN Duty = 4844%(X100), DQS PI = 38
2440 11:45:23.876812 [-4] AVG Duty = 4937%(X100)
2441 11:45:23.876894
2442 11:45:23.876959 ==DQM 1 ==
2443 11:45:23.880124 Final DQM duty delay cell = 0
2444 11:45:23.883837 [0] MAX Duty = 5187%(X100), DQS PI = 34
2445 11:45:23.886653 [0] MIN Duty = 4969%(X100), DQS PI = 4
2446 11:45:23.890011 [0] AVG Duty = 5078%(X100)
2447 11:45:23.890118
2448 11:45:23.893693 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2449 11:45:23.893800
2450 11:45:23.896964 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2451 11:45:23.901115 [DutyScan_Calibration_Flow] ====Done====
2452 11:45:23.901197
2453 11:45:23.903295 [DutyScan_Calibration_Flow] k_type=2
2454 11:45:23.919861
2455 11:45:23.919967 ==DQ 0 ==
2456 11:45:23.923822 Final DQ duty delay cell = 0
2457 11:45:23.927194 [0] MAX Duty = 5156%(X100), DQS PI = 60
2458 11:45:23.930422 [0] MIN Duty = 4907%(X100), DQS PI = 38
2459 11:45:23.930503 [0] AVG Duty = 5031%(X100)
2460 11:45:23.933405
2461 11:45:23.933525 ==DQ 1 ==
2462 11:45:23.936699 Final DQ duty delay cell = 0
2463 11:45:23.939826 [0] MAX Duty = 5124%(X100), DQS PI = 42
2464 11:45:23.943246 [0] MIN Duty = 4969%(X100), DQS PI = 2
2465 11:45:23.943327 [0] AVG Duty = 5046%(X100)
2466 11:45:23.946398
2467 11:45:23.950085 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2468 11:45:23.950167
2469 11:45:23.952930 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2470 11:45:23.956820 [DutyScan_Calibration_Flow] ====Done====
2471 11:45:23.959744 nWR fixed to 30
2472 11:45:23.959873 [ModeRegInit_LP4] CH0 RK0
2473 11:45:23.963654 [ModeRegInit_LP4] CH0 RK1
2474 11:45:23.967026 [ModeRegInit_LP4] CH1 RK0
2475 11:45:23.969932 [ModeRegInit_LP4] CH1 RK1
2476 11:45:23.970013 match AC timing 7
2477 11:45:23.973234 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2478 11:45:23.980006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2479 11:45:23.983651 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2480 11:45:23.986485 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2481 11:45:23.993169 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2482 11:45:23.993255 ==
2483 11:45:23.996584 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 11:45:24.000125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 11:45:24.000208 ==
2486 11:45:24.006784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 11:45:24.013161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2488 11:45:24.020175 [CA 0] Center 39 (9~70) winsize 62
2489 11:45:24.023162 [CA 1] Center 39 (9~70) winsize 62
2490 11:45:24.027245 [CA 2] Center 35 (5~66) winsize 62
2491 11:45:24.029738 [CA 3] Center 35 (5~65) winsize 61
2492 11:45:24.033756 [CA 4] Center 33 (3~64) winsize 62
2493 11:45:24.036583 [CA 5] Center 33 (4~63) winsize 60
2494 11:45:24.036664
2495 11:45:24.039866 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2496 11:45:24.039948
2497 11:45:24.043245 [CATrainingPosCal] consider 1 rank data
2498 11:45:24.046665 u2DelayCellTimex100 = 270/100 ps
2499 11:45:24.049864 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 11:45:24.056961 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 11:45:24.060216 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 11:45:24.063347 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2503 11:45:24.066308 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2504 11:45:24.069735 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2505 11:45:24.069817
2506 11:45:24.073092 CA PerBit enable=1, Macro0, CA PI delay=33
2507 11:45:24.073198
2508 11:45:24.076456 [CBTSetCACLKResult] CA Dly = 33
2509 11:45:24.076541 CS Dly: 8 (0~39)
2510 11:45:24.079475 ==
2511 11:45:24.082883 Dram Type= 6, Freq= 0, CH_0, rank 1
2512 11:45:24.086391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:45:24.086472 ==
2514 11:45:24.092668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 11:45:24.096121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2516 11:45:24.105892 [CA 0] Center 39 (9~70) winsize 62
2517 11:45:24.110426 [CA 1] Center 39 (9~70) winsize 62
2518 11:45:24.112796 [CA 2] Center 35 (5~66) winsize 62
2519 11:45:24.115977 [CA 3] Center 35 (5~65) winsize 61
2520 11:45:24.119552 [CA 4] Center 33 (3~64) winsize 62
2521 11:45:24.122359 [CA 5] Center 33 (3~63) winsize 61
2522 11:45:24.122441
2523 11:45:24.125606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 11:45:24.125689
2525 11:45:24.129356 [CATrainingPosCal] consider 2 rank data
2526 11:45:24.132679 u2DelayCellTimex100 = 270/100 ps
2527 11:45:24.135696 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 11:45:24.139364 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 11:45:24.145619 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 11:45:24.149326 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2531 11:45:24.152583 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2532 11:45:24.155717 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2533 11:45:24.155799
2534 11:45:24.159130 CA PerBit enable=1, Macro0, CA PI delay=33
2535 11:45:24.159213
2536 11:45:24.162205 [CBTSetCACLKResult] CA Dly = 33
2537 11:45:24.162287 CS Dly: 9 (0~41)
2538 11:45:24.165363
2539 11:45:24.168984 ----->DramcWriteLeveling(PI) begin...
2540 11:45:24.169070 ==
2541 11:45:24.172353 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 11:45:24.175909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 11:45:24.175991 ==
2544 11:45:24.178647 Write leveling (Byte 0): 33 => 33
2545 11:45:24.182292 Write leveling (Byte 1): 29 => 29
2546 11:45:24.185226 DramcWriteLeveling(PI) end<-----
2547 11:45:24.185333
2548 11:45:24.185463 ==
2549 11:45:24.188843 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 11:45:24.192297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 11:45:24.192380 ==
2552 11:45:24.195815 [Gating] SW mode calibration
2553 11:45:24.201816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2554 11:45:24.208432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2555 11:45:24.212038 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2556 11:45:24.215362 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2557 11:45:24.221773 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2558 11:45:24.225955 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 11:45:24.228567 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 11:45:24.234937 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 11:45:24.238490 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 11:45:24.241813 0 15 28 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
2563 11:45:24.248569 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
2564 11:45:24.251610 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2565 11:45:24.255308 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 11:45:24.261320 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 11:45:24.264761 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 11:45:24.267908 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 11:45:24.271774 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 11:45:24.278030 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2571 11:45:24.281380 1 1 0 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
2572 11:45:24.284554 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (1 1) (0 0)
2573 11:45:24.291591 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 11:45:24.294948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 11:45:24.298075 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 11:45:24.304885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 11:45:24.307981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 11:45:24.311586 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2579 11:45:24.318260 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2580 11:45:24.321574 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 11:45:24.324997 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 11:45:24.331035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 11:45:24.334566 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 11:45:24.337966 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 11:45:24.344155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 11:45:24.348449 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 11:45:24.351931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 11:45:24.358068 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 11:45:24.360873 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:45:24.363937 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:45:24.370748 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:45:24.373923 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:45:24.377319 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:45:24.384527 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2595 11:45:24.387320 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2596 11:45:24.390753 Total UI for P1: 0, mck2ui 16
2597 11:45:24.394005 best dqsien dly found for B0: ( 1, 3, 28)
2598 11:45:24.397284 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 11:45:24.401181 Total UI for P1: 0, mck2ui 16
2600 11:45:24.403960 best dqsien dly found for B1: ( 1, 4, 0)
2601 11:45:24.407305 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2602 11:45:24.410605 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2603 11:45:24.410711
2604 11:45:24.416994 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2605 11:45:24.420399 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2606 11:45:24.420505 [Gating] SW calibration Done
2607 11:45:24.423911 ==
2608 11:45:24.427618 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 11:45:24.430425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 11:45:24.430512 ==
2611 11:45:24.430579 RX Vref Scan: 0
2612 11:45:24.430639
2613 11:45:24.433524 RX Vref 0 -> 0, step: 1
2614 11:45:24.433607
2615 11:45:24.436977 RX Delay -40 -> 252, step: 8
2616 11:45:24.440330 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2617 11:45:24.443778 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2618 11:45:24.446824 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2619 11:45:24.453386 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2620 11:45:24.456913 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2621 11:45:24.460576 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2622 11:45:24.463372 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2623 11:45:24.466786 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2624 11:45:24.473265 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2625 11:45:24.476755 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2626 11:45:24.480095 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2627 11:45:24.483960 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2628 11:45:24.486514 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2629 11:45:24.493618 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2630 11:45:24.496745 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2631 11:45:24.500213 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2632 11:45:24.500297 ==
2633 11:45:24.503352 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 11:45:24.506742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 11:45:24.510029 ==
2636 11:45:24.510112 DQS Delay:
2637 11:45:24.510195 DQS0 = 0, DQS1 = 0
2638 11:45:24.513095 DQM Delay:
2639 11:45:24.513179 DQM0 = 119, DQM1 = 106
2640 11:45:24.516601 DQ Delay:
2641 11:45:24.519827 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2642 11:45:24.523003 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2643 11:45:24.526318 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2644 11:45:24.529756 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2645 11:45:24.529859
2646 11:45:24.529939
2647 11:45:24.529998 ==
2648 11:45:24.533338 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:45:24.536311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:45:24.536398 ==
2651 11:45:24.536464
2652 11:45:24.540530
2653 11:45:24.540612 TX Vref Scan disable
2654 11:45:24.543406 == TX Byte 0 ==
2655 11:45:24.545989 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 11:45:24.549748 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 11:45:24.552811 == TX Byte 1 ==
2658 11:45:24.556033 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2659 11:45:24.559708 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2660 11:45:24.559791 ==
2661 11:45:24.562541 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 11:45:24.569363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 11:45:24.569488 ==
2664 11:45:24.580076 TX Vref=22, minBit 5, minWin=25, winSum=418
2665 11:45:24.583546 TX Vref=24, minBit 0, minWin=26, winSum=427
2666 11:45:24.587288 TX Vref=26, minBit 4, minWin=26, winSum=434
2667 11:45:24.589967 TX Vref=28, minBit 5, minWin=26, winSum=438
2668 11:45:24.594009 TX Vref=30, minBit 5, minWin=26, winSum=434
2669 11:45:24.600158 TX Vref=32, minBit 4, minWin=26, winSum=433
2670 11:45:24.603406 [TxChooseVref] Worse bit 5, Min win 26, Win sum 438, Final Vref 28
2671 11:45:24.603490
2672 11:45:24.606676 Final TX Range 1 Vref 28
2673 11:45:24.606758
2674 11:45:24.606823 ==
2675 11:45:24.610578 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 11:45:24.613132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 11:45:24.616989 ==
2678 11:45:24.617071
2679 11:45:24.617135
2680 11:45:24.617196 TX Vref Scan disable
2681 11:45:24.619886 == TX Byte 0 ==
2682 11:45:24.623353 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2683 11:45:24.626919 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2684 11:45:24.629748 == TX Byte 1 ==
2685 11:45:24.633314 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2686 11:45:24.639827 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2687 11:45:24.639912
2688 11:45:24.639977 [DATLAT]
2689 11:45:24.640038 Freq=1200, CH0 RK0
2690 11:45:24.640097
2691 11:45:24.643421 DATLAT Default: 0xd
2692 11:45:24.643505 0, 0xFFFF, sum = 0
2693 11:45:24.646440 1, 0xFFFF, sum = 0
2694 11:45:24.649789 2, 0xFFFF, sum = 0
2695 11:45:24.649873 3, 0xFFFF, sum = 0
2696 11:45:24.653104 4, 0xFFFF, sum = 0
2697 11:45:24.653190 5, 0xFFFF, sum = 0
2698 11:45:24.656815 6, 0xFFFF, sum = 0
2699 11:45:24.656913 7, 0xFFFF, sum = 0
2700 11:45:24.659826 8, 0xFFFF, sum = 0
2701 11:45:24.659911 9, 0xFFFF, sum = 0
2702 11:45:24.663503 10, 0xFFFF, sum = 0
2703 11:45:24.663661 11, 0xFFFF, sum = 0
2704 11:45:24.666234 12, 0x0, sum = 1
2705 11:45:24.666314 13, 0x0, sum = 2
2706 11:45:24.669469 14, 0x0, sum = 3
2707 11:45:24.669548 15, 0x0, sum = 4
2708 11:45:24.673436 best_step = 13
2709 11:45:24.673527
2710 11:45:24.673598 ==
2711 11:45:24.676608 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 11:45:24.679710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 11:45:24.679787 ==
2714 11:45:24.679855 RX Vref Scan: 1
2715 11:45:24.679920
2716 11:45:24.683356 Set Vref Range= 32 -> 127
2717 11:45:24.683432
2718 11:45:24.686337 RX Vref 32 -> 127, step: 1
2719 11:45:24.686411
2720 11:45:24.689795 RX Delay -21 -> 252, step: 4
2721 11:45:24.689871
2722 11:45:24.692904 Set Vref, RX VrefLevel [Byte0]: 32
2723 11:45:24.696527 [Byte1]: 32
2724 11:45:24.696631
2725 11:45:24.699433 Set Vref, RX VrefLevel [Byte0]: 33
2726 11:45:24.702932 [Byte1]: 33
2727 11:45:24.706914
2728 11:45:24.706998 Set Vref, RX VrefLevel [Byte0]: 34
2729 11:45:24.709621 [Byte1]: 34
2730 11:45:24.714386
2731 11:45:24.714467 Set Vref, RX VrefLevel [Byte0]: 35
2732 11:45:24.717768 [Byte1]: 35
2733 11:45:24.722312
2734 11:45:24.722394 Set Vref, RX VrefLevel [Byte0]: 36
2735 11:45:24.727008 [Byte1]: 36
2736 11:45:24.730710
2737 11:45:24.730793 Set Vref, RX VrefLevel [Byte0]: 37
2738 11:45:24.733766 [Byte1]: 37
2739 11:45:24.738242
2740 11:45:24.738327 Set Vref, RX VrefLevel [Byte0]: 38
2741 11:45:24.741629 [Byte1]: 38
2742 11:45:24.746545
2743 11:45:24.746630 Set Vref, RX VrefLevel [Byte0]: 39
2744 11:45:24.749350 [Byte1]: 39
2745 11:45:24.754214
2746 11:45:24.754369 Set Vref, RX VrefLevel [Byte0]: 40
2747 11:45:24.757368 [Byte1]: 40
2748 11:45:24.761863
2749 11:45:24.761991 Set Vref, RX VrefLevel [Byte0]: 41
2750 11:45:24.765122 [Byte1]: 41
2751 11:45:24.769978
2752 11:45:24.770091 Set Vref, RX VrefLevel [Byte0]: 42
2753 11:45:24.773324 [Byte1]: 42
2754 11:45:24.777795
2755 11:45:24.781323 Set Vref, RX VrefLevel [Byte0]: 43
2756 11:45:24.781442 [Byte1]: 43
2757 11:45:24.785863
2758 11:45:24.785961 Set Vref, RX VrefLevel [Byte0]: 44
2759 11:45:24.789405 [Byte1]: 44
2760 11:45:24.793680
2761 11:45:24.793787 Set Vref, RX VrefLevel [Byte0]: 45
2762 11:45:24.797232 [Byte1]: 45
2763 11:45:24.801925
2764 11:45:24.802012 Set Vref, RX VrefLevel [Byte0]: 46
2765 11:45:24.805074 [Byte1]: 46
2766 11:45:24.809235
2767 11:45:24.809309 Set Vref, RX VrefLevel [Byte0]: 47
2768 11:45:24.812923 [Byte1]: 47
2769 11:45:24.817194
2770 11:45:24.817297 Set Vref, RX VrefLevel [Byte0]: 48
2771 11:45:24.820741 [Byte1]: 48
2772 11:45:24.825151
2773 11:45:24.825246 Set Vref, RX VrefLevel [Byte0]: 49
2774 11:45:24.828588 [Byte1]: 49
2775 11:45:24.833290
2776 11:45:24.833394 Set Vref, RX VrefLevel [Byte0]: 50
2777 11:45:24.836685 [Byte1]: 50
2778 11:45:24.841571
2779 11:45:24.841661 Set Vref, RX VrefLevel [Byte0]: 51
2780 11:45:24.844932 [Byte1]: 51
2781 11:45:24.849273
2782 11:45:24.849353 Set Vref, RX VrefLevel [Byte0]: 52
2783 11:45:24.852537 [Byte1]: 52
2784 11:45:24.857009
2785 11:45:24.857089 Set Vref, RX VrefLevel [Byte0]: 53
2786 11:45:24.860128 [Byte1]: 53
2787 11:45:24.865004
2788 11:45:24.865084 Set Vref, RX VrefLevel [Byte0]: 54
2789 11:45:24.868290 [Byte1]: 54
2790 11:45:24.873126
2791 11:45:24.873206 Set Vref, RX VrefLevel [Byte0]: 55
2792 11:45:24.876482 [Byte1]: 55
2793 11:45:24.880715
2794 11:45:24.880795 Set Vref, RX VrefLevel [Byte0]: 56
2795 11:45:24.884327 [Byte1]: 56
2796 11:45:24.888889
2797 11:45:24.888969 Set Vref, RX VrefLevel [Byte0]: 57
2798 11:45:24.892233 [Byte1]: 57
2799 11:45:24.896708
2800 11:45:24.896813 Set Vref, RX VrefLevel [Byte0]: 58
2801 11:45:24.899822 [Byte1]: 58
2802 11:45:24.904820
2803 11:45:24.904916 Set Vref, RX VrefLevel [Byte0]: 59
2804 11:45:24.908054 [Byte1]: 59
2805 11:45:24.912560
2806 11:45:24.912655 Set Vref, RX VrefLevel [Byte0]: 60
2807 11:45:24.916000 [Byte1]: 60
2808 11:45:24.920582
2809 11:45:24.920678 Set Vref, RX VrefLevel [Byte0]: 61
2810 11:45:24.924064 [Byte1]: 61
2811 11:45:24.928676
2812 11:45:24.928773 Set Vref, RX VrefLevel [Byte0]: 62
2813 11:45:24.931743 [Byte1]: 62
2814 11:45:24.936287
2815 11:45:24.936382 Set Vref, RX VrefLevel [Byte0]: 63
2816 11:45:24.939758 [Byte1]: 63
2817 11:45:24.944590
2818 11:45:24.944664 Set Vref, RX VrefLevel [Byte0]: 64
2819 11:45:24.947881 [Byte1]: 64
2820 11:45:24.951977
2821 11:45:24.952057 Set Vref, RX VrefLevel [Byte0]: 65
2822 11:45:24.955233 [Byte1]: 65
2823 11:45:24.960397
2824 11:45:24.960477 Set Vref, RX VrefLevel [Byte0]: 66
2825 11:45:24.963596 [Byte1]: 66
2826 11:45:24.968143
2827 11:45:24.968223 Set Vref, RX VrefLevel [Byte0]: 67
2828 11:45:24.971223 [Byte1]: 67
2829 11:45:24.975787
2830 11:45:24.979432 Set Vref, RX VrefLevel [Byte0]: 68
2831 11:45:24.982709 [Byte1]: 68
2832 11:45:24.982789
2833 11:45:24.986071 Set Vref, RX VrefLevel [Byte0]: 69
2834 11:45:24.989080 [Byte1]: 69
2835 11:45:24.989187
2836 11:45:24.992258 Set Vref, RX VrefLevel [Byte0]: 70
2837 11:45:24.995833 [Byte1]: 70
2838 11:45:24.999739
2839 11:45:24.999841 Set Vref, RX VrefLevel [Byte0]: 71
2840 11:45:25.003006 [Byte1]: 71
2841 11:45:25.007635
2842 11:45:25.007738 Set Vref, RX VrefLevel [Byte0]: 72
2843 11:45:25.010905 [Byte1]: 72
2844 11:45:25.015685
2845 11:45:25.015788 Set Vref, RX VrefLevel [Byte0]: 73
2846 11:45:25.018830 [Byte1]: 73
2847 11:45:25.023503
2848 11:45:25.023599 Set Vref, RX VrefLevel [Byte0]: 74
2849 11:45:25.026716 [Byte1]: 74
2850 11:45:25.031446
2851 11:45:25.031528 Set Vref, RX VrefLevel [Byte0]: 75
2852 11:45:25.034997 [Byte1]: 75
2853 11:45:25.039832
2854 11:45:25.039927 Set Vref, RX VrefLevel [Byte0]: 76
2855 11:45:25.045673 [Byte1]: 76
2856 11:45:25.045760
2857 11:45:25.049259 Set Vref, RX VrefLevel [Byte0]: 77
2858 11:45:25.052945 [Byte1]: 77
2859 11:45:25.053050
2860 11:45:25.056230 Set Vref, RX VrefLevel [Byte0]: 78
2861 11:45:25.059061 [Byte1]: 78
2862 11:45:25.062978
2863 11:45:25.063074 Final RX Vref Byte 0 = 61 to rank0
2864 11:45:25.066571 Final RX Vref Byte 1 = 57 to rank0
2865 11:45:25.070094 Final RX Vref Byte 0 = 61 to rank1
2866 11:45:25.073314 Final RX Vref Byte 1 = 57 to rank1==
2867 11:45:25.076542 Dram Type= 6, Freq= 0, CH_0, rank 0
2868 11:45:25.082859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 11:45:25.082944 ==
2870 11:45:25.083043 DQS Delay:
2871 11:45:25.086257 DQS0 = 0, DQS1 = 0
2872 11:45:25.086347 DQM Delay:
2873 11:45:25.086425 DQM0 = 119, DQM1 = 107
2874 11:45:25.089325 DQ Delay:
2875 11:45:25.093220 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2876 11:45:25.096303 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2877 11:45:25.099527 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2878 11:45:25.102674 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2879 11:45:25.102781
2880 11:45:25.102870
2881 11:45:25.112666 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
2882 11:45:25.112754 CH0 RK0: MR19=403, MR18=10FB
2883 11:45:25.119306 CH0_RK0: MR19=0x403, MR18=0x10FB, DQSOSC=403, MR23=63, INC=40, DEC=26
2884 11:45:25.119461
2885 11:45:25.122651 ----->DramcWriteLeveling(PI) begin...
2886 11:45:25.122730 ==
2887 11:45:25.126041 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 11:45:25.132465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 11:45:25.132565 ==
2890 11:45:25.135693 Write leveling (Byte 0): 33 => 33
2891 11:45:25.135777 Write leveling (Byte 1): 31 => 31
2892 11:45:25.139557 DramcWriteLeveling(PI) end<-----
2893 11:45:25.139628
2894 11:45:25.142824 ==
2895 11:45:25.142905 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 11:45:25.149186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 11:45:25.149267 ==
2898 11:45:25.152463 [Gating] SW mode calibration
2899 11:45:25.159027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2900 11:45:25.162550 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2901 11:45:25.169125 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2902 11:45:25.172378 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2903 11:45:25.175873 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 11:45:25.182193 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:45:25.185696 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:45:25.189025 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:45:25.196273 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2908 11:45:25.199030 0 15 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2909 11:45:25.202829 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2910 11:45:25.208792 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 11:45:25.212568 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:45:25.215950 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:45:25.222227 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:45:25.225542 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:45:25.229611 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:45:25.232447 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2917 11:45:25.238754 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2918 11:45:25.242086 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 11:45:25.245628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:45:25.252079 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:45:25.255318 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:45:25.258622 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:45:25.265228 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:45:25.268663 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2925 11:45:25.271925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2926 11:45:25.278725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:45:25.281983 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:45:25.285388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:45:25.291792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:45:25.295313 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:45:25.298482 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:45:25.305301 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:45:25.308240 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:45:25.311988 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:45:25.318351 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:45:25.321704 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:45:25.324868 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:45:25.331605 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:45:25.334980 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:45:25.338583 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2941 11:45:25.344700 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2942 11:45:25.344777 Total UI for P1: 0, mck2ui 16
2943 11:45:25.351727 best dqsien dly found for B0: ( 1, 3, 28)
2944 11:45:25.354855 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:45:25.358178 Total UI for P1: 0, mck2ui 16
2946 11:45:25.361521 best dqsien dly found for B1: ( 1, 3, 30)
2947 11:45:25.364846 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2948 11:45:25.368023 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2949 11:45:25.368121
2950 11:45:25.371548 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2951 11:45:25.375175 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2952 11:45:25.378158 [Gating] SW calibration Done
2953 11:45:25.378245 ==
2954 11:45:25.381159 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 11:45:25.384732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 11:45:25.387912 ==
2957 11:45:25.388017 RX Vref Scan: 0
2958 11:45:25.388106
2959 11:45:25.391480 RX Vref 0 -> 0, step: 1
2960 11:45:25.391577
2961 11:45:25.391665 RX Delay -40 -> 252, step: 8
2962 11:45:25.398181 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2963 11:45:25.401158 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2964 11:45:25.404571 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2965 11:45:25.407907 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2966 11:45:25.411739 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2967 11:45:25.418003 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2968 11:45:25.421118 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2969 11:45:25.424811 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2970 11:45:25.428309 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2971 11:45:25.431292 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2972 11:45:25.437783 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2973 11:45:25.441571 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2974 11:45:25.444660 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2975 11:45:25.448228 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2976 11:45:25.451169 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2977 11:45:25.458101 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2978 11:45:25.458183 ==
2979 11:45:25.461037 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 11:45:25.464542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 11:45:25.464655 ==
2982 11:45:25.464748 DQS Delay:
2983 11:45:25.467786 DQS0 = 0, DQS1 = 0
2984 11:45:25.467899 DQM Delay:
2985 11:45:25.471112 DQM0 = 116, DQM1 = 108
2986 11:45:25.471217 DQ Delay:
2987 11:45:25.474707 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2988 11:45:25.477792 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2989 11:45:25.481308 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2990 11:45:25.484763 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2991 11:45:25.484865
2992 11:45:25.487796
2993 11:45:25.487897 ==
2994 11:45:25.491202 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 11:45:25.494865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 11:45:25.494961 ==
2997 11:45:25.495048
2998 11:45:25.495140
2999 11:45:25.497619 TX Vref Scan disable
3000 11:45:25.497718 == TX Byte 0 ==
3001 11:45:25.504666 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3002 11:45:25.508172 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3003 11:45:25.508276 == TX Byte 1 ==
3004 11:45:25.514834 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3005 11:45:25.517820 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3006 11:45:25.517922 ==
3007 11:45:25.521338 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 11:45:25.524613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 11:45:25.524716 ==
3010 11:45:25.536816 TX Vref=22, minBit 0, minWin=26, winSum=425
3011 11:45:25.539940 TX Vref=24, minBit 1, minWin=26, winSum=427
3012 11:45:25.543266 TX Vref=26, minBit 11, minWin=26, winSum=432
3013 11:45:25.546713 TX Vref=28, minBit 1, minWin=26, winSum=435
3014 11:45:25.549757 TX Vref=30, minBit 10, minWin=26, winSum=433
3015 11:45:25.556764 TX Vref=32, minBit 4, minWin=26, winSum=428
3016 11:45:25.559690 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 28
3017 11:45:25.559790
3018 11:45:25.562909 Final TX Range 1 Vref 28
3019 11:45:25.563006
3020 11:45:25.563101 ==
3021 11:45:25.566362 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 11:45:25.569665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 11:45:25.573191 ==
3024 11:45:25.573286
3025 11:45:25.573382
3026 11:45:25.573488 TX Vref Scan disable
3027 11:45:25.576875 == TX Byte 0 ==
3028 11:45:25.579950 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3029 11:45:25.586850 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3030 11:45:25.586923 == TX Byte 1 ==
3031 11:45:25.589562 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3032 11:45:25.593247 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3033 11:45:25.596759
3034 11:45:25.596854 [DATLAT]
3035 11:45:25.596942 Freq=1200, CH0 RK1
3036 11:45:25.597037
3037 11:45:25.599738 DATLAT Default: 0xd
3038 11:45:25.599832 0, 0xFFFF, sum = 0
3039 11:45:25.603252 1, 0xFFFF, sum = 0
3040 11:45:25.603323 2, 0xFFFF, sum = 0
3041 11:45:25.606663 3, 0xFFFF, sum = 0
3042 11:45:25.609736 4, 0xFFFF, sum = 0
3043 11:45:25.609809 5, 0xFFFF, sum = 0
3044 11:45:25.613229 6, 0xFFFF, sum = 0
3045 11:45:25.613342 7, 0xFFFF, sum = 0
3046 11:45:25.616186 8, 0xFFFF, sum = 0
3047 11:45:25.616289 9, 0xFFFF, sum = 0
3048 11:45:25.619674 10, 0xFFFF, sum = 0
3049 11:45:25.619765 11, 0xFFFF, sum = 0
3050 11:45:25.622967 12, 0x0, sum = 1
3051 11:45:25.623043 13, 0x0, sum = 2
3052 11:45:25.626616 14, 0x0, sum = 3
3053 11:45:25.626688 15, 0x0, sum = 4
3054 11:45:25.626764 best_step = 13
3055 11:45:25.629702
3056 11:45:25.629785 ==
3057 11:45:25.632849 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 11:45:25.636418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 11:45:25.636522 ==
3060 11:45:25.636610 RX Vref Scan: 0
3061 11:45:25.636697
3062 11:45:25.639635 RX Vref 0 -> 0, step: 1
3063 11:45:25.639737
3064 11:45:25.643112 RX Delay -21 -> 252, step: 4
3065 11:45:25.646359 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3066 11:45:25.653336 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3067 11:45:25.656364 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3068 11:45:25.659743 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3069 11:45:25.662978 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3070 11:45:25.666550 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3071 11:45:25.672869 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3072 11:45:25.676173 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3073 11:45:25.679575 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3074 11:45:25.682811 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3075 11:45:25.685965 iDelay=195, Bit 10, Center 114 (47 ~ 182) 136
3076 11:45:25.692778 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3077 11:45:25.696043 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3078 11:45:25.699620 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3079 11:45:25.702605 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3080 11:45:25.709241 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3081 11:45:25.709344 ==
3082 11:45:25.712701 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 11:45:25.715911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 11:45:25.716006 ==
3085 11:45:25.716102 DQS Delay:
3086 11:45:25.719171 DQS0 = 0, DQS1 = 0
3087 11:45:25.719241 DQM Delay:
3088 11:45:25.722587 DQM0 = 116, DQM1 = 109
3089 11:45:25.722684 DQ Delay:
3090 11:45:25.726107 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3091 11:45:25.729830 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3092 11:45:25.732298 DQ8 =98, DQ9 =94, DQ10 =114, DQ11 =104
3093 11:45:25.735821 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3094 11:45:25.735917
3095 11:45:25.736013
3096 11:45:25.745944 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3097 11:45:25.746021 CH0 RK1: MR19=403, MR18=FE9
3098 11:45:25.752345 CH0_RK1: MR19=0x403, MR18=0xFE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3099 11:45:25.755572 [RxdqsGatingPostProcess] freq 1200
3100 11:45:25.762282 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3101 11:45:25.765511 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 11:45:25.769229 best DQS1 dly(2T, 0.5T) = (0, 12)
3103 11:45:25.772948 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 11:45:25.775640 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3105 11:45:25.779471 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 11:45:25.782677 best DQS1 dly(2T, 0.5T) = (0, 11)
3107 11:45:25.785930 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 11:45:25.786032 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3109 11:45:25.788611 Pre-setting of DQS Precalculation
3110 11:45:25.795690 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3111 11:45:25.795794 ==
3112 11:45:25.798884 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 11:45:25.802712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 11:45:25.802811 ==
3115 11:45:25.809056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 11:45:25.815362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 11:45:25.822683 [CA 0] Center 37 (7~67) winsize 61
3118 11:45:25.825860 [CA 1] Center 38 (8~68) winsize 61
3119 11:45:25.829167 [CA 2] Center 34 (4~64) winsize 61
3120 11:45:25.832587 [CA 3] Center 33 (3~64) winsize 62
3121 11:45:25.836158 [CA 4] Center 34 (4~64) winsize 61
3122 11:45:25.839345 [CA 5] Center 34 (4~64) winsize 61
3123 11:45:25.839441
3124 11:45:25.842801 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3125 11:45:25.842898
3126 11:45:25.846052 [CATrainingPosCal] consider 1 rank data
3127 11:45:25.848901 u2DelayCellTimex100 = 270/100 ps
3128 11:45:25.852449 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3129 11:45:25.859746 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3130 11:45:25.862484 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 11:45:25.865845 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3132 11:45:25.868825 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 11:45:25.872725 CA5 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 11:45:25.872821
3135 11:45:25.875517 CA PerBit enable=1, Macro0, CA PI delay=33
3136 11:45:25.875612
3137 11:45:25.879364 [CBTSetCACLKResult] CA Dly = 33
3138 11:45:25.882991 CS Dly: 5 (0~36)
3139 11:45:25.883087 ==
3140 11:45:25.885679 Dram Type= 6, Freq= 0, CH_1, rank 1
3141 11:45:25.888834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 11:45:25.888929 ==
3143 11:45:25.892327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 11:45:25.899039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3145 11:45:25.908126 [CA 0] Center 37 (7~67) winsize 61
3146 11:45:25.911402 [CA 1] Center 38 (8~68) winsize 61
3147 11:45:25.914905 [CA 2] Center 34 (4~65) winsize 62
3148 11:45:25.918320 [CA 3] Center 33 (3~64) winsize 62
3149 11:45:25.921373 [CA 4] Center 33 (3~64) winsize 62
3150 11:45:25.925644 [CA 5] Center 33 (3~64) winsize 62
3151 11:45:25.925717
3152 11:45:25.928181 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3153 11:45:25.928276
3154 11:45:25.931714 [CATrainingPosCal] consider 2 rank data
3155 11:45:25.934805 u2DelayCellTimex100 = 270/100 ps
3156 11:45:25.938119 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3157 11:45:25.945074 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3158 11:45:25.948302 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 11:45:25.951329 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3160 11:45:25.954915 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 11:45:25.957921 CA5 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 11:45:25.958001
3163 11:45:25.961103 CA PerBit enable=1, Macro0, CA PI delay=33
3164 11:45:25.961201
3165 11:45:25.964507 [CBTSetCACLKResult] CA Dly = 33
3166 11:45:25.964606 CS Dly: 7 (0~40)
3167 11:45:25.967741
3168 11:45:25.971238 ----->DramcWriteLeveling(PI) begin...
3169 11:45:25.971312 ==
3170 11:45:25.974429 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 11:45:25.977629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 11:45:25.977702 ==
3173 11:45:25.980809 Write leveling (Byte 0): 25 => 25
3174 11:45:25.984744 Write leveling (Byte 1): 27 => 27
3175 11:45:25.987695 DramcWriteLeveling(PI) end<-----
3176 11:45:25.987796
3177 11:45:25.987884 ==
3178 11:45:25.991497 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 11:45:25.994242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 11:45:25.994312 ==
3181 11:45:25.997729 [Gating] SW mode calibration
3182 11:45:26.004165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3183 11:45:26.010837 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3184 11:45:26.014288 0 15 0 | B1->B0 | 2c2b 3434 | 1 0 | (1 1) (0 0)
3185 11:45:26.017730 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 11:45:26.023953 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:45:26.027296 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:45:26.030583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:45:26.037575 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:45:26.040651 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
3191 11:45:26.043676 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
3192 11:45:26.050548 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 11:45:26.053974 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:45:26.057605 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:45:26.063969 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:45:26.066807 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:45:26.070168 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:45:26.076762 1 0 24 | B1->B0 | 2525 3838 | 0 1 | (0 0) (1 1)
3199 11:45:26.080734 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3200 11:45:26.083487 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 11:45:26.089945 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:45:26.093927 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:45:26.097006 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:45:26.103441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:45:26.106376 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:45:26.110212 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3207 11:45:26.116842 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3208 11:45:26.119690 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:45:26.123249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:45:26.129807 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:45:26.133003 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:45:26.136674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:45:26.143183 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:45:26.146443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:45:26.149648 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:45:26.156194 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:45:26.159765 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:45:26.162881 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:45:26.169759 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:45:26.172814 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:45:26.176596 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:45:26.183016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 11:45:26.186364 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 11:45:26.189327 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:45:26.192743 Total UI for P1: 0, mck2ui 16
3226 11:45:26.195938 best dqsien dly found for B0: ( 1, 3, 26)
3227 11:45:26.199736 Total UI for P1: 0, mck2ui 16
3228 11:45:26.202989 best dqsien dly found for B1: ( 1, 3, 26)
3229 11:45:26.206067 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3230 11:45:26.209261 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3231 11:45:26.209357
3232 11:45:26.212954 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3233 11:45:26.215941 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 11:45:26.219428 [Gating] SW calibration Done
3235 11:45:26.219527 ==
3236 11:45:26.222638 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 11:45:26.229778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 11:45:26.229881 ==
3239 11:45:26.229983 RX Vref Scan: 0
3240 11:45:26.230075
3241 11:45:26.232982 RX Vref 0 -> 0, step: 1
3242 11:45:26.233086
3243 11:45:26.236441 RX Delay -40 -> 252, step: 8
3244 11:45:26.239448 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3245 11:45:26.242541 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3246 11:45:26.245822 iDelay=208, Bit 2, Center 115 (48 ~ 183) 136
3247 11:45:26.249301 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3248 11:45:26.256125 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3249 11:45:26.259277 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3250 11:45:26.262793 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3251 11:45:26.266071 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3252 11:45:26.269238 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3253 11:45:26.276468 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3254 11:45:26.279561 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3255 11:45:26.282965 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3256 11:45:26.285697 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3257 11:45:26.289089 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3258 11:45:26.295794 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3259 11:45:26.298797 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3260 11:45:26.298872 ==
3261 11:45:26.302135 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 11:45:26.305468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 11:45:26.305546 ==
3264 11:45:26.308790 DQS Delay:
3265 11:45:26.308887 DQS0 = 0, DQS1 = 0
3266 11:45:26.312036 DQM Delay:
3267 11:45:26.312134 DQM0 = 120, DQM1 = 110
3268 11:45:26.312228 DQ Delay:
3269 11:45:26.315200 DQ0 =123, DQ1 =115, DQ2 =115, DQ3 =119
3270 11:45:26.318822 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3271 11:45:26.325243 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3272 11:45:26.328800 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3273 11:45:26.328904
3274 11:45:26.328995
3275 11:45:26.329084 ==
3276 11:45:26.331871 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 11:45:26.335168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 11:45:26.335272 ==
3279 11:45:26.335337
3280 11:45:26.335395
3281 11:45:26.338714 TX Vref Scan disable
3282 11:45:26.338783 == TX Byte 0 ==
3283 11:45:26.345566 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3284 11:45:26.348336 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3285 11:45:26.352228 == TX Byte 1 ==
3286 11:45:26.355075 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3287 11:45:26.358555 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3288 11:45:26.358645 ==
3289 11:45:26.362675 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 11:45:26.364943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 11:45:26.365046 ==
3292 11:45:26.378214 TX Vref=22, minBit 3, minWin=25, winSum=413
3293 11:45:26.381223 TX Vref=24, minBit 5, minWin=25, winSum=419
3294 11:45:26.384533 TX Vref=26, minBit 0, minWin=26, winSum=422
3295 11:45:26.388297 TX Vref=28, minBit 0, minWin=26, winSum=425
3296 11:45:26.391618 TX Vref=30, minBit 11, minWin=25, winSum=425
3297 11:45:26.397887 TX Vref=32, minBit 13, minWin=25, winSum=419
3298 11:45:26.401186 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
3299 11:45:26.401350
3300 11:45:26.404414 Final TX Range 1 Vref 28
3301 11:45:26.404507
3302 11:45:26.404572 ==
3303 11:45:26.407870 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 11:45:26.411133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 11:45:26.414713 ==
3306 11:45:26.414789
3307 11:45:26.414851
3308 11:45:26.414909 TX Vref Scan disable
3309 11:45:26.417727 == TX Byte 0 ==
3310 11:45:26.421019 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3311 11:45:26.425155 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3312 11:45:26.428011 == TX Byte 1 ==
3313 11:45:26.431309 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3314 11:45:26.437696 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3315 11:45:26.437798
3316 11:45:26.437894 [DATLAT]
3317 11:45:26.437982 Freq=1200, CH1 RK0
3318 11:45:26.438069
3319 11:45:26.440973 DATLAT Default: 0xd
3320 11:45:26.441069 0, 0xFFFF, sum = 0
3321 11:45:26.444659 1, 0xFFFF, sum = 0
3322 11:45:26.447874 2, 0xFFFF, sum = 0
3323 11:45:26.447974 3, 0xFFFF, sum = 0
3324 11:45:26.451146 4, 0xFFFF, sum = 0
3325 11:45:26.451248 5, 0xFFFF, sum = 0
3326 11:45:26.454604 6, 0xFFFF, sum = 0
3327 11:45:26.454679 7, 0xFFFF, sum = 0
3328 11:45:26.457639 8, 0xFFFF, sum = 0
3329 11:45:26.457715 9, 0xFFFF, sum = 0
3330 11:45:26.460935 10, 0xFFFF, sum = 0
3331 11:45:26.461039 11, 0xFFFF, sum = 0
3332 11:45:26.464433 12, 0x0, sum = 1
3333 11:45:26.464536 13, 0x0, sum = 2
3334 11:45:26.467599 14, 0x0, sum = 3
3335 11:45:26.467701 15, 0x0, sum = 4
3336 11:45:26.471123 best_step = 13
3337 11:45:26.471198
3338 11:45:26.471262 ==
3339 11:45:26.474513 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 11:45:26.477825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 11:45:26.477906 ==
3342 11:45:26.477971 RX Vref Scan: 1
3343 11:45:26.478031
3344 11:45:26.481510 Set Vref Range= 32 -> 127
3345 11:45:26.481610
3346 11:45:26.484563 RX Vref 32 -> 127, step: 1
3347 11:45:26.484644
3348 11:45:26.487801 RX Delay -21 -> 252, step: 4
3349 11:45:26.487881
3350 11:45:26.490791 Set Vref, RX VrefLevel [Byte0]: 32
3351 11:45:26.494534 [Byte1]: 32
3352 11:45:26.494641
3353 11:45:26.497826 Set Vref, RX VrefLevel [Byte0]: 33
3354 11:45:26.501044 [Byte1]: 33
3355 11:45:26.504436
3356 11:45:26.504535 Set Vref, RX VrefLevel [Byte0]: 34
3357 11:45:26.507546 [Byte1]: 34
3358 11:45:26.512198
3359 11:45:26.512298 Set Vref, RX VrefLevel [Byte0]: 35
3360 11:45:26.515860 [Byte1]: 35
3361 11:45:26.520439
3362 11:45:26.520542 Set Vref, RX VrefLevel [Byte0]: 36
3363 11:45:26.523542 [Byte1]: 36
3364 11:45:26.527997
3365 11:45:26.528079 Set Vref, RX VrefLevel [Byte0]: 37
3366 11:45:26.531557 [Byte1]: 37
3367 11:45:26.536269
3368 11:45:26.536377 Set Vref, RX VrefLevel [Byte0]: 38
3369 11:45:26.539599 [Byte1]: 38
3370 11:45:26.544031
3371 11:45:26.544106 Set Vref, RX VrefLevel [Byte0]: 39
3372 11:45:26.547467 [Byte1]: 39
3373 11:45:26.551761
3374 11:45:26.551858 Set Vref, RX VrefLevel [Byte0]: 40
3375 11:45:26.555128 [Byte1]: 40
3376 11:45:26.559878
3377 11:45:26.559977 Set Vref, RX VrefLevel [Byte0]: 41
3378 11:45:26.562897 [Byte1]: 41
3379 11:45:26.567593
3380 11:45:26.567694 Set Vref, RX VrefLevel [Byte0]: 42
3381 11:45:26.571135 [Byte1]: 42
3382 11:45:26.575562
3383 11:45:26.575666 Set Vref, RX VrefLevel [Byte0]: 43
3384 11:45:26.578705 [Byte1]: 43
3385 11:45:26.583911
3386 11:45:26.584014 Set Vref, RX VrefLevel [Byte0]: 44
3387 11:45:26.586860 [Byte1]: 44
3388 11:45:26.591740
3389 11:45:26.591818 Set Vref, RX VrefLevel [Byte0]: 45
3390 11:45:26.595167 [Byte1]: 45
3391 11:45:26.599293
3392 11:45:26.599398 Set Vref, RX VrefLevel [Byte0]: 46
3393 11:45:26.602959 [Byte1]: 46
3394 11:45:26.607303
3395 11:45:26.607408 Set Vref, RX VrefLevel [Byte0]: 47
3396 11:45:26.610414 [Byte1]: 47
3397 11:45:26.615769
3398 11:45:26.615850 Set Vref, RX VrefLevel [Byte0]: 48
3399 11:45:26.618704 [Byte1]: 48
3400 11:45:26.623006
3401 11:45:26.623103 Set Vref, RX VrefLevel [Byte0]: 49
3402 11:45:26.626255 [Byte1]: 49
3403 11:45:26.631222
3404 11:45:26.631321 Set Vref, RX VrefLevel [Byte0]: 50
3405 11:45:26.634358 [Byte1]: 50
3406 11:45:26.638828
3407 11:45:26.638917 Set Vref, RX VrefLevel [Byte0]: 51
3408 11:45:26.642269 [Byte1]: 51
3409 11:45:26.646837
3410 11:45:26.646939 Set Vref, RX VrefLevel [Byte0]: 52
3411 11:45:26.650069 [Byte1]: 52
3412 11:45:26.654991
3413 11:45:26.655068 Set Vref, RX VrefLevel [Byte0]: 53
3414 11:45:26.657883 [Byte1]: 53
3415 11:45:26.662543
3416 11:45:26.662636 Set Vref, RX VrefLevel [Byte0]: 54
3417 11:45:26.666067 [Byte1]: 54
3418 11:45:26.670990
3419 11:45:26.671067 Set Vref, RX VrefLevel [Byte0]: 55
3420 11:45:26.674221 [Byte1]: 55
3421 11:45:26.678763
3422 11:45:26.678877 Set Vref, RX VrefLevel [Byte0]: 56
3423 11:45:26.681716 [Byte1]: 56
3424 11:45:26.686656
3425 11:45:26.686762 Set Vref, RX VrefLevel [Byte0]: 57
3426 11:45:26.689784 [Byte1]: 57
3427 11:45:26.694576
3428 11:45:26.694676 Set Vref, RX VrefLevel [Byte0]: 58
3429 11:45:26.697863 [Byte1]: 58
3430 11:45:26.702389
3431 11:45:26.702473 Set Vref, RX VrefLevel [Byte0]: 59
3432 11:45:26.705828 [Byte1]: 59
3433 11:45:26.710491
3434 11:45:26.710563 Set Vref, RX VrefLevel [Byte0]: 60
3435 11:45:26.713345 [Byte1]: 60
3436 11:45:26.718494
3437 11:45:26.718567 Set Vref, RX VrefLevel [Byte0]: 61
3438 11:45:26.721362 [Byte1]: 61
3439 11:45:26.726626
3440 11:45:26.726703 Set Vref, RX VrefLevel [Byte0]: 62
3441 11:45:26.729727 [Byte1]: 62
3442 11:45:26.734193
3443 11:45:26.734272 Set Vref, RX VrefLevel [Byte0]: 63
3444 11:45:26.737593 [Byte1]: 63
3445 11:45:26.742124
3446 11:45:26.742218 Set Vref, RX VrefLevel [Byte0]: 64
3447 11:45:26.745312 [Byte1]: 64
3448 11:45:26.749922
3449 11:45:26.750003 Set Vref, RX VrefLevel [Byte0]: 65
3450 11:45:26.773765 [Byte1]: 65
3451 11:45:26.773881
3452 11:45:26.773948 Set Vref, RX VrefLevel [Byte0]: 66
3453 11:45:26.774013 [Byte1]: 66
3454 11:45:26.774081
3455 11:45:26.774155 Set Vref, RX VrefLevel [Byte0]: 67
3456 11:45:26.774212 [Byte1]: 67
3457 11:45:26.774326
3458 11:45:26.774381 Final RX Vref Byte 0 = 50 to rank0
3459 11:45:26.776750 Final RX Vref Byte 1 = 51 to rank0
3460 11:45:26.780539 Final RX Vref Byte 0 = 50 to rank1
3461 11:45:26.783716 Final RX Vref Byte 1 = 51 to rank1==
3462 11:45:26.787188 Dram Type= 6, Freq= 0, CH_1, rank 0
3463 11:45:26.793552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 11:45:26.793645 ==
3465 11:45:26.793709 DQS Delay:
3466 11:45:26.796482 DQS0 = 0, DQS1 = 0
3467 11:45:26.796578 DQM Delay:
3468 11:45:26.796673 DQM0 = 117, DQM1 = 111
3469 11:45:26.800329 DQ Delay:
3470 11:45:26.803430 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =112
3471 11:45:26.806652 DQ4 =116, DQ5 =130, DQ6 =126, DQ7 =114
3472 11:45:26.809925 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =98
3473 11:45:26.813145 DQ12 =118, DQ13 =116, DQ14 =122, DQ15 =120
3474 11:45:26.813240
3475 11:45:26.813327
3476 11:45:26.823339 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3477 11:45:26.823442 CH1 RK0: MR19=403, MR18=3F7
3478 11:45:26.829650 CH1_RK0: MR19=0x403, MR18=0x3F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3479 11:45:26.829771
3480 11:45:26.833492 ----->DramcWriteLeveling(PI) begin...
3481 11:45:26.833566 ==
3482 11:45:26.836616 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 11:45:26.839872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 11:45:26.843250 ==
3485 11:45:26.843329 Write leveling (Byte 0): 25 => 25
3486 11:45:26.846524 Write leveling (Byte 1): 28 => 28
3487 11:45:26.849682 DramcWriteLeveling(PI) end<-----
3488 11:45:26.849781
3489 11:45:26.849856 ==
3490 11:45:26.853564 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 11:45:26.859839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 11:45:26.859938 ==
3493 11:45:26.860036 [Gating] SW mode calibration
3494 11:45:26.870159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3495 11:45:26.873251 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3496 11:45:26.879927 0 15 0 | B1->B0 | 3434 3433 | 0 1 | (0 0) (0 0)
3497 11:45:26.882953 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 11:45:26.886048 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 11:45:26.892478 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 11:45:26.895726 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 11:45:26.899764 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 11:45:26.906249 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3503 11:45:26.909617 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
3504 11:45:26.912514 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:45:26.919003 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 11:45:26.922503 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 11:45:26.925697 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 11:45:26.932246 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 11:45:26.935902 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 11:45:26.938882 1 0 24 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (1 1)
3511 11:45:26.945991 1 0 28 | B1->B0 | 4545 3d3d | 0 0 | (0 0) (0 0)
3512 11:45:26.949156 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:45:26.952707 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:45:26.959073 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 11:45:26.962116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 11:45:26.965394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 11:45:26.971999 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 11:45:26.975494 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3519 11:45:26.979095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3520 11:45:26.985390 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:45:26.988414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:45:26.991659 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:45:26.998386 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:45:27.001634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:45:27.005097 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:45:27.011611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:45:27.014860 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:45:27.018113 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:45:27.024863 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:45:27.028225 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:45:27.031142 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:45:27.037994 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:45:27.041101 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:45:27.044182 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3535 11:45:27.051100 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3536 11:45:27.051200 Total UI for P1: 0, mck2ui 16
3537 11:45:27.054359 best dqsien dly found for B1: ( 1, 3, 24)
3538 11:45:27.060741 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:45:27.064176 Total UI for P1: 0, mck2ui 16
3540 11:45:27.067649 best dqsien dly found for B0: ( 1, 3, 28)
3541 11:45:27.070834 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3542 11:45:27.073865 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3543 11:45:27.073949
3544 11:45:27.077350 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3545 11:45:27.080505 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 11:45:27.083912 [Gating] SW calibration Done
3547 11:45:27.084007 ==
3548 11:45:27.086984 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 11:45:27.090310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 11:45:27.093668 ==
3551 11:45:27.093764 RX Vref Scan: 0
3552 11:45:27.093858
3553 11:45:27.097118 RX Vref 0 -> 0, step: 1
3554 11:45:27.097219
3555 11:45:27.100592 RX Delay -40 -> 252, step: 8
3556 11:45:27.103909 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3557 11:45:27.107176 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3558 11:45:27.110392 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3559 11:45:27.113708 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3560 11:45:27.119963 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3561 11:45:27.123273 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3562 11:45:27.126673 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3563 11:45:27.129748 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3564 11:45:27.133436 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3565 11:45:27.139594 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3566 11:45:27.143390 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3567 11:45:27.146607 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3568 11:45:27.149861 iDelay=208, Bit 12, Center 123 (48 ~ 199) 152
3569 11:45:27.152807 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3570 11:45:27.160053 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3571 11:45:27.162901 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3572 11:45:27.162973 ==
3573 11:45:27.166114 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 11:45:27.169395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 11:45:27.169521 ==
3576 11:45:27.173363 DQS Delay:
3577 11:45:27.173498 DQS0 = 0, DQS1 = 0
3578 11:45:27.173560 DQM Delay:
3579 11:45:27.176486 DQM0 = 118, DQM1 = 110
3580 11:45:27.176580 DQ Delay:
3581 11:45:27.179550 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3582 11:45:27.182861 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3583 11:45:27.186322 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3584 11:45:27.192929 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3585 11:45:27.193033
3586 11:45:27.193120
3587 11:45:27.193208 ==
3588 11:45:27.195908 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 11:45:27.199396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 11:45:27.199490 ==
3591 11:45:27.199583
3592 11:45:27.199669
3593 11:45:27.202502 TX Vref Scan disable
3594 11:45:27.205799 == TX Byte 0 ==
3595 11:45:27.208788 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 11:45:27.212813 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 11:45:27.215482 == TX Byte 1 ==
3598 11:45:27.218866 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3599 11:45:27.222218 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3600 11:45:27.222294 ==
3601 11:45:27.225308 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 11:45:27.228585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 11:45:27.232190 ==
3604 11:45:27.242173 TX Vref=22, minBit 1, minWin=25, winSum=425
3605 11:45:27.245831 TX Vref=24, minBit 0, minWin=25, winSum=425
3606 11:45:27.248760 TX Vref=26, minBit 7, minWin=26, winSum=433
3607 11:45:27.252016 TX Vref=28, minBit 0, minWin=27, winSum=434
3608 11:45:27.255062 TX Vref=30, minBit 0, minWin=26, winSum=431
3609 11:45:27.261766 TX Vref=32, minBit 4, minWin=26, winSum=427
3610 11:45:27.265081 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 28
3611 11:45:27.265221
3612 11:45:27.268652 Final TX Range 1 Vref 28
3613 11:45:27.268776
3614 11:45:27.268870 ==
3615 11:45:27.271683 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 11:45:27.275493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 11:45:27.278591 ==
3618 11:45:27.278710
3619 11:45:27.278789
3620 11:45:27.278849 TX Vref Scan disable
3621 11:45:27.281816 == TX Byte 0 ==
3622 11:45:27.285811 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 11:45:27.288709 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 11:45:27.292024 == TX Byte 1 ==
3625 11:45:27.295054 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3626 11:45:27.301872 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3627 11:45:27.302018
3628 11:45:27.302124 [DATLAT]
3629 11:45:27.302216 Freq=1200, CH1 RK1
3630 11:45:27.302304
3631 11:45:27.305047 DATLAT Default: 0xd
3632 11:45:27.305160 0, 0xFFFF, sum = 0
3633 11:45:27.308487 1, 0xFFFF, sum = 0
3634 11:45:27.311752 2, 0xFFFF, sum = 0
3635 11:45:27.311873 3, 0xFFFF, sum = 0
3636 11:45:27.314850 4, 0xFFFF, sum = 0
3637 11:45:27.314959 5, 0xFFFF, sum = 0
3638 11:45:27.317844 6, 0xFFFF, sum = 0
3639 11:45:27.317954 7, 0xFFFF, sum = 0
3640 11:45:27.321077 8, 0xFFFF, sum = 0
3641 11:45:27.321196 9, 0xFFFF, sum = 0
3642 11:45:27.324463 10, 0xFFFF, sum = 0
3643 11:45:27.324584 11, 0xFFFF, sum = 0
3644 11:45:27.328510 12, 0x0, sum = 1
3645 11:45:27.328626 13, 0x0, sum = 2
3646 11:45:27.330974 14, 0x0, sum = 3
3647 11:45:27.331088 15, 0x0, sum = 4
3648 11:45:27.334278 best_step = 13
3649 11:45:27.334393
3650 11:45:27.334492 ==
3651 11:45:27.338117 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 11:45:27.341078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 11:45:27.341186 ==
3654 11:45:27.344423 RX Vref Scan: 0
3655 11:45:27.344528
3656 11:45:27.344611 RX Vref 0 -> 0, step: 1
3657 11:45:27.344675
3658 11:45:27.347673 RX Delay -21 -> 252, step: 4
3659 11:45:27.354333 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3660 11:45:27.358154 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3661 11:45:27.360968 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3662 11:45:27.363865 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3663 11:45:27.367755 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3664 11:45:27.374040 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3665 11:45:27.377209 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3666 11:45:27.380689 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3667 11:45:27.384029 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3668 11:45:27.387342 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3669 11:45:27.394033 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3670 11:45:27.396789 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3671 11:45:27.400148 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3672 11:45:27.403413 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3673 11:45:27.409995 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3674 11:45:27.413257 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3675 11:45:27.413373 ==
3676 11:45:27.416588 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 11:45:27.420328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 11:45:27.420439 ==
3679 11:45:27.423097 DQS Delay:
3680 11:45:27.423199 DQS0 = 0, DQS1 = 0
3681 11:45:27.423308 DQM Delay:
3682 11:45:27.426745 DQM0 = 117, DQM1 = 109
3683 11:45:27.426855 DQ Delay:
3684 11:45:27.429679 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3685 11:45:27.433493 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3686 11:45:27.439761 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3687 11:45:27.442900 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3688 11:45:27.443007
3689 11:45:27.443112
3690 11:45:27.449710 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 414 ps
3691 11:45:27.452685 CH1 RK1: MR19=303, MR18=F5EF
3692 11:45:27.459803 CH1_RK1: MR19=0x303, MR18=0xF5EF, DQSOSC=414, MR23=63, INC=38, DEC=25
3693 11:45:27.463178 [RxdqsGatingPostProcess] freq 1200
3694 11:45:27.469317 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3695 11:45:27.469445 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 11:45:27.472487 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 11:45:27.476012 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 11:45:27.479961 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 11:45:27.482467 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 11:45:27.485965 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 11:45:27.489327 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 11:45:27.492500 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 11:45:27.496031 Pre-setting of DQS Precalculation
3704 11:45:27.502752 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3705 11:45:27.509098 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3706 11:45:27.515479 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3707 11:45:27.515586
3708 11:45:27.515679
3709 11:45:27.519007 [Calibration Summary] 2400 Mbps
3710 11:45:27.519095 CH 0, Rank 0
3711 11:45:27.522212 SW Impedance : PASS
3712 11:45:27.525614 DUTY Scan : NO K
3713 11:45:27.525692 ZQ Calibration : PASS
3714 11:45:27.529083 Jitter Meter : NO K
3715 11:45:27.532158 CBT Training : PASS
3716 11:45:27.532297 Write leveling : PASS
3717 11:45:27.535435 RX DQS gating : PASS
3718 11:45:27.538537 RX DQ/DQS(RDDQC) : PASS
3719 11:45:27.538622 TX DQ/DQS : PASS
3720 11:45:27.541806 RX DATLAT : PASS
3721 11:45:27.545141 RX DQ/DQS(Engine): PASS
3722 11:45:27.545241 TX OE : NO K
3723 11:45:27.545341 All Pass.
3724 11:45:27.548653
3725 11:45:27.548754 CH 0, Rank 1
3726 11:45:27.551961 SW Impedance : PASS
3727 11:45:27.552076 DUTY Scan : NO K
3728 11:45:27.555552 ZQ Calibration : PASS
3729 11:45:27.555661 Jitter Meter : NO K
3730 11:45:27.558469 CBT Training : PASS
3731 11:45:27.561972 Write leveling : PASS
3732 11:45:27.562085 RX DQS gating : PASS
3733 11:45:27.565248 RX DQ/DQS(RDDQC) : PASS
3734 11:45:27.568518 TX DQ/DQS : PASS
3735 11:45:27.568624 RX DATLAT : PASS
3736 11:45:27.571577 RX DQ/DQS(Engine): PASS
3737 11:45:27.574936 TX OE : NO K
3738 11:45:27.575064 All Pass.
3739 11:45:27.575178
3740 11:45:27.575289 CH 1, Rank 0
3741 11:45:27.578302 SW Impedance : PASS
3742 11:45:27.581544 DUTY Scan : NO K
3743 11:45:27.581642 ZQ Calibration : PASS
3744 11:45:27.584720 Jitter Meter : NO K
3745 11:45:27.588167 CBT Training : PASS
3746 11:45:27.588271 Write leveling : PASS
3747 11:45:27.591545 RX DQS gating : PASS
3748 11:45:27.595093 RX DQ/DQS(RDDQC) : PASS
3749 11:45:27.595199 TX DQ/DQS : PASS
3750 11:45:27.598111 RX DATLAT : PASS
3751 11:45:27.601941 RX DQ/DQS(Engine): PASS
3752 11:45:27.602041 TX OE : NO K
3753 11:45:27.602173 All Pass.
3754 11:45:27.605198
3755 11:45:27.605293 CH 1, Rank 1
3756 11:45:27.608275 SW Impedance : PASS
3757 11:45:27.608377 DUTY Scan : NO K
3758 11:45:27.611432 ZQ Calibration : PASS
3759 11:45:27.614483 Jitter Meter : NO K
3760 11:45:27.614561 CBT Training : PASS
3761 11:45:27.618479 Write leveling : PASS
3762 11:45:27.618582 RX DQS gating : PASS
3763 11:45:27.621085 RX DQ/DQS(RDDQC) : PASS
3764 11:45:27.624492 TX DQ/DQS : PASS
3765 11:45:27.624599 RX DATLAT : PASS
3766 11:45:27.627909 RX DQ/DQS(Engine): PASS
3767 11:45:27.631500 TX OE : NO K
3768 11:45:27.631610 All Pass.
3769 11:45:27.631703
3770 11:45:27.634576 DramC Write-DBI off
3771 11:45:27.634677 PER_BANK_REFRESH: Hybrid Mode
3772 11:45:27.637977 TX_TRACKING: ON
3773 11:45:27.647679 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3774 11:45:27.650994 [FAST_K] Save calibration result to emmc
3775 11:45:27.654209 dramc_set_vcore_voltage set vcore to 650000
3776 11:45:27.657321 Read voltage for 600, 5
3777 11:45:27.657459 Vio18 = 0
3778 11:45:27.657538 Vcore = 650000
3779 11:45:27.660597 Vdram = 0
3780 11:45:27.660696 Vddq = 0
3781 11:45:27.660784 Vmddr = 0
3782 11:45:27.667260 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3783 11:45:27.671103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3784 11:45:27.674396 MEM_TYPE=3, freq_sel=19
3785 11:45:27.677346 sv_algorithm_assistance_LP4_1600
3786 11:45:27.680772 ============ PULL DRAM RESETB DOWN ============
3787 11:45:27.683974 ========== PULL DRAM RESETB DOWN end =========
3788 11:45:27.690542 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3789 11:45:27.694235 ===================================
3790 11:45:27.694342 LPDDR4 DRAM CONFIGURATION
3791 11:45:27.697303 ===================================
3792 11:45:27.700664 EX_ROW_EN[0] = 0x0
3793 11:45:27.703750 EX_ROW_EN[1] = 0x0
3794 11:45:27.703847 LP4Y_EN = 0x0
3795 11:45:27.707150 WORK_FSP = 0x0
3796 11:45:27.707247 WL = 0x2
3797 11:45:27.710278 RL = 0x2
3798 11:45:27.710376 BL = 0x2
3799 11:45:27.713535 RPST = 0x0
3800 11:45:27.713624 RD_PRE = 0x0
3801 11:45:27.717317 WR_PRE = 0x1
3802 11:45:27.717439 WR_PST = 0x0
3803 11:45:27.720448 DBI_WR = 0x0
3804 11:45:27.720542 DBI_RD = 0x0
3805 11:45:27.723941 OTF = 0x1
3806 11:45:27.727144 ===================================
3807 11:45:27.730532 ===================================
3808 11:45:27.730635 ANA top config
3809 11:45:27.733849 ===================================
3810 11:45:27.736688 DLL_ASYNC_EN = 0
3811 11:45:27.740706 ALL_SLAVE_EN = 1
3812 11:45:27.743382 NEW_RANK_MODE = 1
3813 11:45:27.743542 DLL_IDLE_MODE = 1
3814 11:45:27.747266 LP45_APHY_COMB_EN = 1
3815 11:45:27.749864 TX_ODT_DIS = 1
3816 11:45:27.753762 NEW_8X_MODE = 1
3817 11:45:27.756843 ===================================
3818 11:45:27.759887 ===================================
3819 11:45:27.763344 data_rate = 1200
3820 11:45:27.763415 CKR = 1
3821 11:45:27.766882 DQ_P2S_RATIO = 8
3822 11:45:27.770073 ===================================
3823 11:45:27.773132 CA_P2S_RATIO = 8
3824 11:45:27.776344 DQ_CA_OPEN = 0
3825 11:45:27.779781 DQ_SEMI_OPEN = 0
3826 11:45:27.783024 CA_SEMI_OPEN = 0
3827 11:45:27.783123 CA_FULL_RATE = 0
3828 11:45:27.786468 DQ_CKDIV4_EN = 1
3829 11:45:27.789745 CA_CKDIV4_EN = 1
3830 11:45:27.793186 CA_PREDIV_EN = 0
3831 11:45:27.796037 PH8_DLY = 0
3832 11:45:27.799396 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3833 11:45:27.799477 DQ_AAMCK_DIV = 4
3834 11:45:27.803115 CA_AAMCK_DIV = 4
3835 11:45:27.805962 CA_ADMCK_DIV = 4
3836 11:45:27.809302 DQ_TRACK_CA_EN = 0
3837 11:45:27.812535 CA_PICK = 600
3838 11:45:27.815927 CA_MCKIO = 600
3839 11:45:27.819306 MCKIO_SEMI = 0
3840 11:45:27.819387 PLL_FREQ = 2288
3841 11:45:27.822594 DQ_UI_PI_RATIO = 32
3842 11:45:27.826109 CA_UI_PI_RATIO = 0
3843 11:45:27.829375 ===================================
3844 11:45:27.832516 ===================================
3845 11:45:27.836634 memory_type:LPDDR4
3846 11:45:27.839340 GP_NUM : 10
3847 11:45:27.839420 SRAM_EN : 1
3848 11:45:27.842782 MD32_EN : 0
3849 11:45:27.846078 ===================================
3850 11:45:27.846180 [ANA_INIT] >>>>>>>>>>>>>>
3851 11:45:27.848941 <<<<<< [CONFIGURE PHASE]: ANA_TX
3852 11:45:27.852291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3853 11:45:27.855895 ===================================
3854 11:45:27.859068 data_rate = 1200,PCW = 0X5800
3855 11:45:27.862179 ===================================
3856 11:45:27.865714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3857 11:45:27.872118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 11:45:27.878714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 11:45:27.882161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3860 11:45:27.885899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3861 11:45:27.889255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3862 11:45:27.892214 [ANA_INIT] flow start
3863 11:45:27.892319 [ANA_INIT] PLL >>>>>>>>
3864 11:45:27.895771 [ANA_INIT] PLL <<<<<<<<
3865 11:45:27.898517 [ANA_INIT] MIDPI >>>>>>>>
3866 11:45:27.898616 [ANA_INIT] MIDPI <<<<<<<<
3867 11:45:27.902222 [ANA_INIT] DLL >>>>>>>>
3868 11:45:27.905190 [ANA_INIT] flow end
3869 11:45:27.908527 ============ LP4 DIFF to SE enter ============
3870 11:45:27.912132 ============ LP4 DIFF to SE exit ============
3871 11:45:27.915355 [ANA_INIT] <<<<<<<<<<<<<
3872 11:45:27.918385 [Flow] Enable top DCM control >>>>>
3873 11:45:27.921601 [Flow] Enable top DCM control <<<<<
3874 11:45:27.925443 Enable DLL master slave shuffle
3875 11:45:27.931737 ==============================================================
3876 11:45:27.931845 Gating Mode config
3877 11:45:27.938152 ==============================================================
3878 11:45:27.938225 Config description:
3879 11:45:27.948171 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3880 11:45:27.955101 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3881 11:45:27.961518 SELPH_MODE 0: By rank 1: By Phase
3882 11:45:27.964605 ==============================================================
3883 11:45:27.968532 GAT_TRACK_EN = 1
3884 11:45:27.971320 RX_GATING_MODE = 2
3885 11:45:27.974864 RX_GATING_TRACK_MODE = 2
3886 11:45:27.977774 SELPH_MODE = 1
3887 11:45:27.981204 PICG_EARLY_EN = 1
3888 11:45:27.984692 VALID_LAT_VALUE = 1
3889 11:45:27.987704 ==============================================================
3890 11:45:27.994164 Enter into Gating configuration >>>>
3891 11:45:27.997938 Exit from Gating configuration <<<<
3892 11:45:27.998018 Enter into DVFS_PRE_config >>>>>
3893 11:45:28.011480 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3894 11:45:28.014390 Exit from DVFS_PRE_config <<<<<
3895 11:45:28.017631 Enter into PICG configuration >>>>
3896 11:45:28.020910 Exit from PICG configuration <<<<
3897 11:45:28.021038 [RX_INPUT] configuration >>>>>
3898 11:45:28.024129 [RX_INPUT] configuration <<<<<
3899 11:45:28.030697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3900 11:45:28.037508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3901 11:45:28.040742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 11:45:28.047638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 11:45:28.053645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 11:45:28.060488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 11:45:28.063647 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3906 11:45:28.066979 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3907 11:45:28.073302 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3908 11:45:28.076813 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3909 11:45:28.079792 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3910 11:45:28.086568 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 11:45:28.089948 ===================================
3912 11:45:28.090050 LPDDR4 DRAM CONFIGURATION
3913 11:45:28.093796 ===================================
3914 11:45:28.097025 EX_ROW_EN[0] = 0x0
3915 11:45:28.097123 EX_ROW_EN[1] = 0x0
3916 11:45:28.099784 LP4Y_EN = 0x0
3917 11:45:28.103442 WORK_FSP = 0x0
3918 11:45:28.103542 WL = 0x2
3919 11:45:28.106373 RL = 0x2
3920 11:45:28.106448 BL = 0x2
3921 11:45:28.109727 RPST = 0x0
3922 11:45:28.109815 RD_PRE = 0x0
3923 11:45:28.113603 WR_PRE = 0x1
3924 11:45:28.113701 WR_PST = 0x0
3925 11:45:28.116931 DBI_WR = 0x0
3926 11:45:28.117030 DBI_RD = 0x0
3927 11:45:28.119673 OTF = 0x1
3928 11:45:28.122817 ===================================
3929 11:45:28.126154 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3930 11:45:28.129806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3931 11:45:28.136451 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 11:45:28.139771 ===================================
3933 11:45:28.139872 LPDDR4 DRAM CONFIGURATION
3934 11:45:28.142705 ===================================
3935 11:45:28.146198 EX_ROW_EN[0] = 0x10
3936 11:45:28.149835 EX_ROW_EN[1] = 0x0
3937 11:45:28.149910 LP4Y_EN = 0x0
3938 11:45:28.152970 WORK_FSP = 0x0
3939 11:45:28.153068 WL = 0x2
3940 11:45:28.155703 RL = 0x2
3941 11:45:28.155797 BL = 0x2
3942 11:45:28.159540 RPST = 0x0
3943 11:45:28.159639 RD_PRE = 0x0
3944 11:45:28.162715 WR_PRE = 0x1
3945 11:45:28.162788 WR_PST = 0x0
3946 11:45:28.165729 DBI_WR = 0x0
3947 11:45:28.165827 DBI_RD = 0x0
3948 11:45:28.169321 OTF = 0x1
3949 11:45:28.172350 ===================================
3950 11:45:28.178864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3951 11:45:28.182293 nWR fixed to 30
3952 11:45:28.185539 [ModeRegInit_LP4] CH0 RK0
3953 11:45:28.185642 [ModeRegInit_LP4] CH0 RK1
3954 11:45:28.188688 [ModeRegInit_LP4] CH1 RK0
3955 11:45:28.192100 [ModeRegInit_LP4] CH1 RK1
3956 11:45:28.192202 match AC timing 17
3957 11:45:28.198504 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3958 11:45:28.201854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 11:45:28.205351 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3960 11:45:28.212013 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3961 11:45:28.215443 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3962 11:45:28.215542 ==
3963 11:45:28.218239 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 11:45:28.221974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 11:45:28.222075 ==
3966 11:45:28.228134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 11:45:28.234697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3968 11:45:28.238357 [CA 0] Center 36 (6~66) winsize 61
3969 11:45:28.241400 [CA 1] Center 36 (6~66) winsize 61
3970 11:45:28.245431 [CA 2] Center 34 (3~65) winsize 63
3971 11:45:28.248011 [CA 3] Center 34 (3~65) winsize 63
3972 11:45:28.251405 [CA 4] Center 33 (3~64) winsize 62
3973 11:45:28.254650 [CA 5] Center 33 (3~64) winsize 62
3974 11:45:28.254747
3975 11:45:28.258034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3976 11:45:28.258111
3977 11:45:28.261386 [CATrainingPosCal] consider 1 rank data
3978 11:45:28.264792 u2DelayCellTimex100 = 270/100 ps
3979 11:45:28.267984 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 11:45:28.271246 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3981 11:45:28.274935 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3982 11:45:28.277921 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3983 11:45:28.281155 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 11:45:28.287846 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 11:45:28.287951
3986 11:45:28.291042 CA PerBit enable=1, Macro0, CA PI delay=33
3987 11:45:28.291198
3988 11:45:28.294683 [CBTSetCACLKResult] CA Dly = 33
3989 11:45:28.294901 CS Dly: 7 (0~38)
3990 11:45:28.295007 ==
3991 11:45:28.297672 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 11:45:28.301300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 11:45:28.304585 ==
3994 11:45:28.307706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 11:45:28.314294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 11:45:28.317653 [CA 0] Center 36 (6~66) winsize 61
3997 11:45:28.320950 [CA 1] Center 36 (6~66) winsize 61
3998 11:45:28.324504 [CA 2] Center 33 (3~64) winsize 62
3999 11:45:28.327351 [CA 3] Center 33 (3~64) winsize 62
4000 11:45:28.331555 [CA 4] Center 33 (3~64) winsize 62
4001 11:45:28.333966 [CA 5] Center 33 (2~64) winsize 63
4002 11:45:28.334066
4003 11:45:28.337347 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 11:45:28.337475
4005 11:45:28.340579 [CATrainingPosCal] consider 2 rank data
4006 11:45:28.343976 u2DelayCellTimex100 = 270/100 ps
4007 11:45:28.347464 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4008 11:45:28.350580 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4009 11:45:28.357570 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 11:45:28.360376 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4011 11:45:28.363836 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 11:45:28.367035 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 11:45:28.367144
4014 11:45:28.370661 CA PerBit enable=1, Macro0, CA PI delay=33
4015 11:45:28.370752
4016 11:45:28.373941 [CBTSetCACLKResult] CA Dly = 33
4017 11:45:28.374024 CS Dly: 6 (0~36)
4018 11:45:28.374112
4019 11:45:28.377120 ----->DramcWriteLeveling(PI) begin...
4020 11:45:28.380479 ==
4021 11:45:28.383632 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 11:45:28.387398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 11:45:28.387504 ==
4024 11:45:28.390645 Write leveling (Byte 0): 34 => 34
4025 11:45:28.393639 Write leveling (Byte 1): 29 => 29
4026 11:45:28.396886 DramcWriteLeveling(PI) end<-----
4027 11:45:28.396982
4028 11:45:28.397073 ==
4029 11:45:28.400103 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 11:45:28.403464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 11:45:28.403576 ==
4032 11:45:28.406903 [Gating] SW mode calibration
4033 11:45:28.413732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 11:45:28.419585 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4035 11:45:28.423519 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 11:45:28.426886 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 11:45:28.433110 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 11:45:28.436531 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 11:45:28.440254 0 9 16 | B1->B0 | 2f2f 2a2a | 1 1 | (1 0) (1 0)
4040 11:45:28.446328 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:45:28.449659 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:45:28.452985 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 11:45:28.459481 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 11:45:28.462822 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 11:45:28.466502 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 11:45:28.472910 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4047 11:45:28.476075 0 10 16 | B1->B0 | 3434 3e3e | 1 0 | (0 0) (1 1)
4048 11:45:28.479090 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:45:28.486094 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:45:28.489136 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:45:28.492586 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 11:45:28.499012 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 11:45:28.502552 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 11:45:28.506141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4055 11:45:28.512536 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4056 11:45:28.515569 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:45:28.518877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:45:28.525722 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:45:28.528578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:45:28.532006 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:45:28.538451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:45:28.542114 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:45:28.544989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:45:28.551630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:45:28.555328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:45:28.558833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:45:28.565064 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:45:28.568322 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:45:28.572169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:45:28.577962 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 11:45:28.581175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4072 11:45:28.584679 Total UI for P1: 0, mck2ui 16
4073 11:45:28.587843 best dqsien dly found for B0: ( 0, 13, 12)
4074 11:45:28.591645 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:45:28.594495 Total UI for P1: 0, mck2ui 16
4076 11:45:28.597680 best dqsien dly found for B1: ( 0, 13, 16)
4077 11:45:28.601197 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4078 11:45:28.604447 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4079 11:45:28.604551
4080 11:45:28.611515 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 11:45:28.614819 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4082 11:45:28.614918 [Gating] SW calibration Done
4083 11:45:28.618071 ==
4084 11:45:28.621070 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 11:45:28.624375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 11:45:28.624481 ==
4087 11:45:28.624573 RX Vref Scan: 0
4088 11:45:28.624659
4089 11:45:28.627686 RX Vref 0 -> 0, step: 1
4090 11:45:28.627780
4091 11:45:28.630851 RX Delay -230 -> 252, step: 16
4092 11:45:28.634148 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4093 11:45:28.637213 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4094 11:45:28.644273 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4095 11:45:28.647086 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4096 11:45:28.650787 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4097 11:45:28.654093 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4098 11:45:28.660544 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4099 11:45:28.663455 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4100 11:45:28.666905 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4101 11:45:28.670381 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4102 11:45:28.676527 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4103 11:45:28.680279 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4104 11:45:28.683518 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4105 11:45:28.686651 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4106 11:45:28.693394 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4107 11:45:28.696672 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4108 11:45:28.696785 ==
4109 11:45:28.699816 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 11:45:28.702973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 11:45:28.703071 ==
4112 11:45:28.707095 DQS Delay:
4113 11:45:28.707190 DQS0 = 0, DQS1 = 0
4114 11:45:28.707287 DQM Delay:
4115 11:45:28.709740 DQM0 = 43, DQM1 = 30
4116 11:45:28.709835 DQ Delay:
4117 11:45:28.713658 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4118 11:45:28.716480 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4119 11:45:28.719730 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4120 11:45:28.723240 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4121 11:45:28.723313
4122 11:45:28.723390
4123 11:45:28.723448 ==
4124 11:45:28.726481 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 11:45:28.732993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 11:45:28.733094 ==
4127 11:45:28.733183
4128 11:45:28.733268
4129 11:45:28.733352 TX Vref Scan disable
4130 11:45:28.736789 == TX Byte 0 ==
4131 11:45:28.740311 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4132 11:45:28.746721 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4133 11:45:28.746833 == TX Byte 1 ==
4134 11:45:28.750314 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4135 11:45:28.756498 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4136 11:45:28.756604 ==
4137 11:45:28.759839 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 11:45:28.763609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 11:45:28.763708 ==
4140 11:45:28.763797
4141 11:45:28.763894
4142 11:45:28.766788 TX Vref Scan disable
4143 11:45:28.769925 == TX Byte 0 ==
4144 11:45:28.773074 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4145 11:45:28.776144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4146 11:45:28.779535 == TX Byte 1 ==
4147 11:45:28.782885 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4148 11:45:28.786028 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4149 11:45:28.786111
4150 11:45:28.789657 [DATLAT]
4151 11:45:28.789731 Freq=600, CH0 RK0
4152 11:45:28.789793
4153 11:45:28.792814 DATLAT Default: 0x9
4154 11:45:28.792910 0, 0xFFFF, sum = 0
4155 11:45:28.795908 1, 0xFFFF, sum = 0
4156 11:45:28.796007 2, 0xFFFF, sum = 0
4157 11:45:28.799550 3, 0xFFFF, sum = 0
4158 11:45:28.799651 4, 0xFFFF, sum = 0
4159 11:45:28.802716 5, 0xFFFF, sum = 0
4160 11:45:28.802813 6, 0xFFFF, sum = 0
4161 11:45:28.806137 7, 0xFFFF, sum = 0
4162 11:45:28.806220 8, 0x0, sum = 1
4163 11:45:28.809198 9, 0x0, sum = 2
4164 11:45:28.809297 10, 0x0, sum = 3
4165 11:45:28.812836 11, 0x0, sum = 4
4166 11:45:28.812933 best_step = 9
4167 11:45:28.813021
4168 11:45:28.813114 ==
4169 11:45:28.816066 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 11:45:28.819202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 11:45:28.822615 ==
4172 11:45:28.822711 RX Vref Scan: 1
4173 11:45:28.822805
4174 11:45:28.825807 RX Vref 0 -> 0, step: 1
4175 11:45:28.825878
4176 11:45:28.829304 RX Delay -195 -> 252, step: 8
4177 11:45:28.829373
4178 11:45:28.832450 Set Vref, RX VrefLevel [Byte0]: 61
4179 11:45:28.835883 [Byte1]: 57
4180 11:45:28.835956
4181 11:45:28.839191 Final RX Vref Byte 0 = 61 to rank0
4182 11:45:28.842413 Final RX Vref Byte 1 = 57 to rank0
4183 11:45:28.845754 Final RX Vref Byte 0 = 61 to rank1
4184 11:45:28.848948 Final RX Vref Byte 1 = 57 to rank1==
4185 11:45:28.852188 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 11:45:28.855687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 11:45:28.855762 ==
4188 11:45:28.858623 DQS Delay:
4189 11:45:28.858721 DQS0 = 0, DQS1 = 0
4190 11:45:28.858810 DQM Delay:
4191 11:45:28.862051 DQM0 = 44, DQM1 = 32
4192 11:45:28.862149 DQ Delay:
4193 11:45:28.865181 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4194 11:45:28.868291 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4195 11:45:28.872078 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4196 11:45:28.874950 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4197 11:45:28.875034
4198 11:45:28.875133
4199 11:45:28.884943 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4200 11:45:28.888294 CH0 RK0: MR19=808, MR18=6D46
4201 11:45:28.891855 CH0_RK0: MR19=0x808, MR18=0x6D46, DQSOSC=389, MR23=63, INC=173, DEC=115
4202 11:45:28.894762
4203 11:45:28.897961 ----->DramcWriteLeveling(PI) begin...
4204 11:45:28.898045 ==
4205 11:45:28.901401 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 11:45:28.905303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 11:45:28.905434 ==
4208 11:45:28.907816 Write leveling (Byte 0): 31 => 31
4209 11:45:28.911094 Write leveling (Byte 1): 31 => 31
4210 11:45:28.914573 DramcWriteLeveling(PI) end<-----
4211 11:45:28.914654
4212 11:45:28.914718 ==
4213 11:45:28.917925 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 11:45:28.921157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 11:45:28.921269 ==
4216 11:45:28.924313 [Gating] SW mode calibration
4217 11:45:28.931007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 11:45:28.937889 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 11:45:28.941087 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 11:45:28.944232 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 11:45:28.950594 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 11:45:28.954035 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4223 11:45:28.957330 0 9 16 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
4224 11:45:28.964523 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:45:28.967287 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:45:28.970549 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 11:45:28.977016 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 11:45:28.980456 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 11:45:28.983701 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 11:45:28.990263 0 10 12 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
4231 11:45:28.993586 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4232 11:45:28.996823 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:45:29.003107 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:45:29.006999 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:45:29.009888 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:45:29.016797 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:45:29.019818 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 11:45:29.023227 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 11:45:29.029646 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 11:45:29.033359 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:45:29.036606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:45:29.042925 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:45:29.046078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:45:29.049630 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:45:29.057001 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:45:29.059573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:45:29.063022 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:45:29.070116 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:45:29.072621 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:45:29.075851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:45:29.082272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:45:29.085692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:45:29.089164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:45:29.095822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4255 11:45:29.099211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:45:29.102560 Total UI for P1: 0, mck2ui 16
4257 11:45:29.105953 best dqsien dly found for B0: ( 0, 13, 12)
4258 11:45:29.108929 Total UI for P1: 0, mck2ui 16
4259 11:45:29.112351 best dqsien dly found for B1: ( 0, 13, 14)
4260 11:45:29.115406 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4261 11:45:29.118725 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4262 11:45:29.118806
4263 11:45:29.122158 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4264 11:45:29.125568 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4265 11:45:29.128998 [Gating] SW calibration Done
4266 11:45:29.129079 ==
4267 11:45:29.132145 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:45:29.138867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:45:29.138985 ==
4270 11:45:29.139052 RX Vref Scan: 0
4271 11:45:29.139113
4272 11:45:29.141960 RX Vref 0 -> 0, step: 1
4273 11:45:29.142040
4274 11:45:29.145178 RX Delay -230 -> 252, step: 16
4275 11:45:29.148485 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4276 11:45:29.151847 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4277 11:45:29.155116 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4278 11:45:29.161907 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4279 11:45:29.165284 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4280 11:45:29.168188 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4281 11:45:29.171499 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4282 11:45:29.178760 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4283 11:45:29.181252 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4284 11:45:29.184553 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4285 11:45:29.188086 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4286 11:45:29.194764 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4287 11:45:29.197841 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4288 11:45:29.201066 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4289 11:45:29.204203 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4290 11:45:29.211300 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4291 11:45:29.211386 ==
4292 11:45:29.214395 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 11:45:29.217521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 11:45:29.217605 ==
4295 11:45:29.217691 DQS Delay:
4296 11:45:29.220883 DQS0 = 0, DQS1 = 0
4297 11:45:29.220966 DQM Delay:
4298 11:45:29.224171 DQM0 = 45, DQM1 = 39
4299 11:45:29.224275 DQ Delay:
4300 11:45:29.227370 DQ0 =41, DQ1 =57, DQ2 =33, DQ3 =33
4301 11:45:29.231040 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4302 11:45:29.234292 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4303 11:45:29.237586 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4304 11:45:29.237667
4305 11:45:29.237730
4306 11:45:29.237789 ==
4307 11:45:29.240901 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 11:45:29.244071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 11:45:29.247438 ==
4310 11:45:29.247518
4311 11:45:29.247580
4312 11:45:29.247639 TX Vref Scan disable
4313 11:45:29.250471 == TX Byte 0 ==
4314 11:45:29.254133 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4315 11:45:29.257306 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4316 11:45:29.260530 == TX Byte 1 ==
4317 11:45:29.264071 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4318 11:45:29.267438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4319 11:45:29.270824 ==
4320 11:45:29.273703 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 11:45:29.277062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 11:45:29.277142 ==
4323 11:45:29.277205
4324 11:45:29.277263
4325 11:45:29.280447 TX Vref Scan disable
4326 11:45:29.280527 == TX Byte 0 ==
4327 11:45:29.287198 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4328 11:45:29.290136 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4329 11:45:29.293405 == TX Byte 1 ==
4330 11:45:29.296910 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4331 11:45:29.300243 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4332 11:45:29.300323
4333 11:45:29.300387 [DATLAT]
4334 11:45:29.303872 Freq=600, CH0 RK1
4335 11:45:29.303952
4336 11:45:29.306825 DATLAT Default: 0x9
4337 11:45:29.306904 0, 0xFFFF, sum = 0
4338 11:45:29.310091 1, 0xFFFF, sum = 0
4339 11:45:29.310172 2, 0xFFFF, sum = 0
4340 11:45:29.313243 3, 0xFFFF, sum = 0
4341 11:45:29.313325 4, 0xFFFF, sum = 0
4342 11:45:29.316609 5, 0xFFFF, sum = 0
4343 11:45:29.316690 6, 0xFFFF, sum = 0
4344 11:45:29.320326 7, 0xFFFF, sum = 0
4345 11:45:29.320407 8, 0x0, sum = 1
4346 11:45:29.323142 9, 0x0, sum = 2
4347 11:45:29.323223 10, 0x0, sum = 3
4348 11:45:29.326552 11, 0x0, sum = 4
4349 11:45:29.326633 best_step = 9
4350 11:45:29.326696
4351 11:45:29.326754 ==
4352 11:45:29.329547 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 11:45:29.332951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 11:45:29.333047 ==
4355 11:45:29.336577 RX Vref Scan: 0
4356 11:45:29.336657
4357 11:45:29.339763 RX Vref 0 -> 0, step: 1
4358 11:45:29.339844
4359 11:45:29.339907 RX Delay -195 -> 252, step: 8
4360 11:45:29.347705 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4361 11:45:29.350901 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4362 11:45:29.354084 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4363 11:45:29.358030 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4364 11:45:29.364070 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4365 11:45:29.367855 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4366 11:45:29.370634 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4367 11:45:29.373970 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4368 11:45:29.380434 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4369 11:45:29.383729 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4370 11:45:29.387338 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4371 11:45:29.390610 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4372 11:45:29.397028 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4373 11:45:29.400198 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4374 11:45:29.403634 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4375 11:45:29.406755 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4376 11:45:29.406837 ==
4377 11:45:29.410175 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 11:45:29.416907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 11:45:29.417020 ==
4380 11:45:29.417087 DQS Delay:
4381 11:45:29.420201 DQS0 = 0, DQS1 = 0
4382 11:45:29.420283 DQM Delay:
4383 11:45:29.420349 DQM0 = 41, DQM1 = 35
4384 11:45:29.423076 DQ Delay:
4385 11:45:29.426292 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4386 11:45:29.429873 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4387 11:45:29.433152 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4388 11:45:29.436415 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4389 11:45:29.436495
4390 11:45:29.436557
4391 11:45:29.443363 [DQSOSCAuto] RK1, (LSB)MR18= 0x661a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4392 11:45:29.446327 CH0 RK1: MR19=808, MR18=661A
4393 11:45:29.452893 CH0_RK1: MR19=0x808, MR18=0x661A, DQSOSC=390, MR23=63, INC=172, DEC=114
4394 11:45:29.456033 [RxdqsGatingPostProcess] freq 600
4395 11:45:29.462846 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4396 11:45:29.462932 Pre-setting of DQS Precalculation
4397 11:45:29.469556 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4398 11:45:29.469638 ==
4399 11:45:29.472657 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 11:45:29.476446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 11:45:29.476529 ==
4402 11:45:29.482393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 11:45:29.489602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4404 11:45:29.492766 [CA 0] Center 35 (5~65) winsize 61
4405 11:45:29.495785 [CA 1] Center 35 (5~66) winsize 62
4406 11:45:29.499001 [CA 2] Center 33 (3~64) winsize 62
4407 11:45:29.502122 [CA 3] Center 33 (3~64) winsize 62
4408 11:45:29.505386 [CA 4] Center 34 (3~65) winsize 63
4409 11:45:29.508730 [CA 5] Center 33 (3~64) winsize 62
4410 11:45:29.508813
4411 11:45:29.512136 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4412 11:45:29.512220
4413 11:45:29.515675 [CATrainingPosCal] consider 1 rank data
4414 11:45:29.518827 u2DelayCellTimex100 = 270/100 ps
4415 11:45:29.522202 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4416 11:45:29.525475 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 11:45:29.528981 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 11:45:29.532283 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 11:45:29.538036 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4420 11:45:29.538648 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 11:45:29.541832
4422 11:45:29.545753 CA PerBit enable=1, Macro0, CA PI delay=33
4423 11:45:29.545836
4424 11:45:29.548582 [CBTSetCACLKResult] CA Dly = 33
4425 11:45:29.548664 CS Dly: 4 (0~35)
4426 11:45:29.548728 ==
4427 11:45:29.551824 Dram Type= 6, Freq= 0, CH_1, rank 1
4428 11:45:29.555260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 11:45:29.555342 ==
4430 11:45:29.562154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 11:45:29.568528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4432 11:45:29.571721 [CA 0] Center 35 (5~66) winsize 62
4433 11:45:29.575640 [CA 1] Center 36 (6~66) winsize 61
4434 11:45:29.578513 [CA 2] Center 34 (4~65) winsize 62
4435 11:45:29.581912 [CA 3] Center 33 (3~64) winsize 62
4436 11:45:29.585115 [CA 4] Center 34 (3~65) winsize 63
4437 11:45:29.588557 [CA 5] Center 33 (3~64) winsize 62
4438 11:45:29.588639
4439 11:45:29.591666 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4440 11:45:29.591748
4441 11:45:29.594939 [CATrainingPosCal] consider 2 rank data
4442 11:45:29.598180 u2DelayCellTimex100 = 270/100 ps
4443 11:45:29.601468 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4444 11:45:29.604724 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 11:45:29.608030 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4446 11:45:29.614856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4447 11:45:29.617708 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4448 11:45:29.621019 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4449 11:45:29.621100
4450 11:45:29.624573 CA PerBit enable=1, Macro0, CA PI delay=33
4451 11:45:29.624654
4452 11:45:29.627647 [CBTSetCACLKResult] CA Dly = 33
4453 11:45:29.627728 CS Dly: 4 (0~36)
4454 11:45:29.627793
4455 11:45:29.631330 ----->DramcWriteLeveling(PI) begin...
4456 11:45:29.634241 ==
4457 11:45:29.637570 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 11:45:29.640754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 11:45:29.640836 ==
4460 11:45:29.644699 Write leveling (Byte 0): 28 => 28
4461 11:45:29.647833 Write leveling (Byte 1): 29 => 29
4462 11:45:29.650740 DramcWriteLeveling(PI) end<-----
4463 11:45:29.650844
4464 11:45:29.650941 ==
4465 11:45:29.654422 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 11:45:29.657955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 11:45:29.658059 ==
4468 11:45:29.660640 [Gating] SW mode calibration
4469 11:45:29.667698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4470 11:45:29.674137 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4471 11:45:29.677930 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 11:45:29.681288 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 11:45:29.687439 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 11:45:29.690803 0 9 12 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 0)
4475 11:45:29.694214 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4476 11:45:29.700420 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:45:29.703611 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 11:45:29.706896 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 11:45:29.713518 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 11:45:29.716813 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 11:45:29.720208 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4482 11:45:29.726792 0 10 12 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
4483 11:45:29.730340 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:45:29.733705 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:45:29.740133 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:45:29.743759 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 11:45:29.746660 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 11:45:29.753124 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 11:45:29.756527 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 11:45:29.759803 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4491 11:45:29.766606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:45:29.769575 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:45:29.773014 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:45:29.779494 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:45:29.782977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:45:29.786301 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:45:29.792502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:45:29.796023 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:45:29.799199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:45:29.806097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:45:29.808988 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:45:29.812265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:45:29.819032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:45:29.822635 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:45:29.825789 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:45:29.832982 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4507 11:45:29.833064 Total UI for P1: 0, mck2ui 16
4508 11:45:29.838706 best dqsien dly found for B0: ( 0, 13, 10)
4509 11:45:29.842221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:45:29.845483 Total UI for P1: 0, mck2ui 16
4511 11:45:29.848638 best dqsien dly found for B1: ( 0, 13, 12)
4512 11:45:29.852233 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4513 11:45:29.855214 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4514 11:45:29.855315
4515 11:45:29.858610 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4516 11:45:29.862050 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4517 11:45:29.865008 [Gating] SW calibration Done
4518 11:45:29.865106 ==
4519 11:45:29.868594 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:45:29.871504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:45:29.875215 ==
4522 11:45:29.875306 RX Vref Scan: 0
4523 11:45:29.875377
4524 11:45:29.878160 RX Vref 0 -> 0, step: 1
4525 11:45:29.878229
4526 11:45:29.882063 RX Delay -230 -> 252, step: 16
4527 11:45:29.884706 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4528 11:45:29.888431 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4529 11:45:29.891411 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4530 11:45:29.897996 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4531 11:45:29.901677 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4532 11:45:29.904815 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4533 11:45:29.907763 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4534 11:45:29.914632 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4535 11:45:29.918086 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4536 11:45:29.921526 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4537 11:45:29.924574 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4538 11:45:29.927716 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4539 11:45:29.934279 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4540 11:45:29.937491 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4541 11:45:29.941099 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4542 11:45:29.944410 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4543 11:45:29.947445 ==
4544 11:45:29.951209 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 11:45:29.954504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 11:45:29.954611 ==
4547 11:45:29.954704 DQS Delay:
4548 11:45:29.957705 DQS0 = 0, DQS1 = 0
4549 11:45:29.957807 DQM Delay:
4550 11:45:29.960843 DQM0 = 44, DQM1 = 34
4551 11:45:29.960951 DQ Delay:
4552 11:45:29.963924 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4553 11:45:29.967543 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4554 11:45:29.971057 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4555 11:45:29.974355 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4556 11:45:29.974460
4557 11:45:29.974554
4558 11:45:29.974642 ==
4559 11:45:29.977328 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 11:45:29.981127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 11:45:29.981232 ==
4562 11:45:29.981326
4563 11:45:29.981453
4564 11:45:29.984163 TX Vref Scan disable
4565 11:45:29.987044 == TX Byte 0 ==
4566 11:45:29.990608 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 11:45:29.993870 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 11:45:29.997060 == TX Byte 1 ==
4569 11:45:30.000593 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 11:45:30.003679 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 11:45:30.003786 ==
4572 11:45:30.007171 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 11:45:30.013741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 11:45:30.013843 ==
4575 11:45:30.013909
4576 11:45:30.014002
4577 11:45:30.014059 TX Vref Scan disable
4578 11:45:30.018082 == TX Byte 0 ==
4579 11:45:30.021811 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 11:45:30.028052 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 11:45:30.028135 == TX Byte 1 ==
4582 11:45:30.031369 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 11:45:30.037770 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 11:45:30.037881
4585 11:45:30.037984 [DATLAT]
4586 11:45:30.038085 Freq=600, CH1 RK0
4587 11:45:30.038185
4588 11:45:30.041352 DATLAT Default: 0x9
4589 11:45:30.044565 0, 0xFFFF, sum = 0
4590 11:45:30.044671 1, 0xFFFF, sum = 0
4591 11:45:30.047671 2, 0xFFFF, sum = 0
4592 11:45:30.047778 3, 0xFFFF, sum = 0
4593 11:45:30.051256 4, 0xFFFF, sum = 0
4594 11:45:30.051367 5, 0xFFFF, sum = 0
4595 11:45:30.054059 6, 0xFFFF, sum = 0
4596 11:45:30.054172 7, 0xFFFF, sum = 0
4597 11:45:30.057401 8, 0x0, sum = 1
4598 11:45:30.057549 9, 0x0, sum = 2
4599 11:45:30.060601 10, 0x0, sum = 3
4600 11:45:30.060686 11, 0x0, sum = 4
4601 11:45:30.060751 best_step = 9
4602 11:45:30.060812
4603 11:45:30.064046 ==
4604 11:45:30.067195 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 11:45:30.071117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 11:45:30.071200 ==
4607 11:45:30.071265 RX Vref Scan: 1
4608 11:45:30.071326
4609 11:45:30.073747 RX Vref 0 -> 0, step: 1
4610 11:45:30.073873
4611 11:45:30.077413 RX Delay -195 -> 252, step: 8
4612 11:45:30.077526
4613 11:45:30.080275 Set Vref, RX VrefLevel [Byte0]: 50
4614 11:45:30.083991 [Byte1]: 51
4615 11:45:30.084095
4616 11:45:30.087053 Final RX Vref Byte 0 = 50 to rank0
4617 11:45:30.090194 Final RX Vref Byte 1 = 51 to rank0
4618 11:45:30.093392 Final RX Vref Byte 0 = 50 to rank1
4619 11:45:30.097248 Final RX Vref Byte 1 = 51 to rank1==
4620 11:45:30.100404 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 11:45:30.103558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 11:45:30.107059 ==
4623 11:45:30.107165 DQS Delay:
4624 11:45:30.107271 DQS0 = 0, DQS1 = 0
4625 11:45:30.110645 DQM Delay:
4626 11:45:30.110748 DQM0 = 46, DQM1 = 34
4627 11:45:30.113645 DQ Delay:
4628 11:45:30.116859 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4629 11:45:30.116962 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4630 11:45:30.120343 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4631 11:45:30.126495 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =44
4632 11:45:30.126601
4633 11:45:30.126703
4634 11:45:30.133329 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4635 11:45:30.136671 CH1 RK0: MR19=808, MR18=4C31
4636 11:45:30.143210 CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112
4637 11:45:30.143319
4638 11:45:30.146300 ----->DramcWriteLeveling(PI) begin...
4639 11:45:30.146407 ==
4640 11:45:30.149880 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:45:30.153309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:45:30.153420 ==
4643 11:45:30.156295 Write leveling (Byte 0): 29 => 29
4644 11:45:30.159634 Write leveling (Byte 1): 30 => 30
4645 11:45:30.162871 DramcWriteLeveling(PI) end<-----
4646 11:45:30.162975
4647 11:45:30.163077 ==
4648 11:45:30.166238 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 11:45:30.169890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:45:30.169972 ==
4651 11:45:30.172888 [Gating] SW mode calibration
4652 11:45:30.179368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4653 11:45:30.185916 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4654 11:45:30.189374 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 11:45:30.196324 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 11:45:30.199527 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 11:45:30.202868 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (1 0)
4658 11:45:30.209265 0 9 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4659 11:45:30.212491 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:45:30.215958 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 11:45:30.222632 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 11:45:30.226237 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 11:45:30.228974 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 11:45:30.235865 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 11:45:30.239121 0 10 12 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
4666 11:45:30.242656 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:45:30.248763 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:45:30.252026 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:45:30.255247 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 11:45:30.261744 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 11:45:30.265108 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 11:45:30.268866 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 11:45:30.275195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 11:45:30.278081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:45:30.281393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:45:30.288327 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:45:30.291489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:45:30.294466 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:45:30.301124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:45:30.304339 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:45:30.307546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:45:30.314365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:45:30.318105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:45:30.321074 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:45:30.327211 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:45:30.330861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:45:30.334174 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:45:30.341073 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:45:30.344336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:45:30.347420 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 11:45:30.350548 Total UI for P1: 0, mck2ui 16
4692 11:45:30.353634 best dqsien dly found for B0: ( 0, 13, 14)
4693 11:45:30.357252 Total UI for P1: 0, mck2ui 16
4694 11:45:30.360699 best dqsien dly found for B1: ( 0, 13, 14)
4695 11:45:30.364142 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4696 11:45:30.370662 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4697 11:45:30.370746
4698 11:45:30.373607 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4699 11:45:30.376996 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4700 11:45:30.380483 [Gating] SW calibration Done
4701 11:45:30.380560 ==
4702 11:45:30.383490 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 11:45:30.386782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 11:45:30.386855 ==
4705 11:45:30.390020 RX Vref Scan: 0
4706 11:45:30.390093
4707 11:45:30.390201 RX Vref 0 -> 0, step: 1
4708 11:45:30.390329
4709 11:45:30.393344 RX Delay -230 -> 252, step: 16
4710 11:45:30.396395 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4711 11:45:30.403087 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4712 11:45:30.406898 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4713 11:45:30.409618 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4714 11:45:30.412909 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4715 11:45:30.419912 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4716 11:45:30.422869 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4717 11:45:30.426030 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4718 11:45:30.429398 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4719 11:45:30.435668 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4720 11:45:30.439484 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4721 11:45:30.442765 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4722 11:45:30.446325 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4723 11:45:30.452356 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4724 11:45:30.455564 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4725 11:45:30.459309 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4726 11:45:30.459416 ==
4727 11:45:30.462720 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 11:45:30.465676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 11:45:30.468956 ==
4730 11:45:30.469039 DQS Delay:
4731 11:45:30.469105 DQS0 = 0, DQS1 = 0
4732 11:45:30.472116 DQM Delay:
4733 11:45:30.472196 DQM0 = 40, DQM1 = 32
4734 11:45:30.475446 DQ Delay:
4735 11:45:30.475544 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4736 11:45:30.478778 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4737 11:45:30.482219 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4738 11:45:30.485305 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =49
4739 11:45:30.489163
4740 11:45:30.489263
4741 11:45:30.489354 ==
4742 11:45:30.491923 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 11:45:30.494770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 11:45:30.494862 ==
4745 11:45:30.494926
4746 11:45:30.495001
4747 11:45:30.498111 TX Vref Scan disable
4748 11:45:30.498210 == TX Byte 0 ==
4749 11:45:30.505276 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4750 11:45:30.508373 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4751 11:45:30.508454 == TX Byte 1 ==
4752 11:45:30.514704 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 11:45:30.518200 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 11:45:30.518295 ==
4755 11:45:30.521264 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 11:45:30.524701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 11:45:30.524782 ==
4758 11:45:30.524845
4759 11:45:30.527912
4760 11:45:30.527992 TX Vref Scan disable
4761 11:45:30.531268 == TX Byte 0 ==
4762 11:45:30.534445 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4763 11:45:30.541836 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4764 11:45:30.541917 == TX Byte 1 ==
4765 11:45:30.544624 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4766 11:45:30.551112 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4767 11:45:30.551196
4768 11:45:30.551269 [DATLAT]
4769 11:45:30.551329 Freq=600, CH1 RK1
4770 11:45:30.551387
4771 11:45:30.554226 DATLAT Default: 0x9
4772 11:45:30.557551 0, 0xFFFF, sum = 0
4773 11:45:30.557631 1, 0xFFFF, sum = 0
4774 11:45:30.560934 2, 0xFFFF, sum = 0
4775 11:45:30.561039 3, 0xFFFF, sum = 0
4776 11:45:30.564115 4, 0xFFFF, sum = 0
4777 11:45:30.564218 5, 0xFFFF, sum = 0
4778 11:45:30.567784 6, 0xFFFF, sum = 0
4779 11:45:30.567881 7, 0xFFFF, sum = 0
4780 11:45:30.570792 8, 0x0, sum = 1
4781 11:45:30.570889 9, 0x0, sum = 2
4782 11:45:30.574142 10, 0x0, sum = 3
4783 11:45:30.574246 11, 0x0, sum = 4
4784 11:45:30.574335 best_step = 9
4785 11:45:30.574419
4786 11:45:30.577362 ==
4787 11:45:30.580584 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 11:45:30.583977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 11:45:30.584072 ==
4790 11:45:30.584159 RX Vref Scan: 0
4791 11:45:30.584252
4792 11:45:30.587804 RX Vref 0 -> 0, step: 1
4793 11:45:30.587881
4794 11:45:30.591151 RX Delay -195 -> 252, step: 8
4795 11:45:30.596927 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4796 11:45:30.600450 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4797 11:45:30.603695 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4798 11:45:30.607226 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4799 11:45:30.610695 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4800 11:45:30.616703 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4801 11:45:30.620182 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4802 11:45:30.623747 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4803 11:45:30.626844 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4804 11:45:30.633352 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4805 11:45:30.636890 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4806 11:45:30.640288 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4807 11:45:30.643427 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4808 11:45:30.650813 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4809 11:45:30.653396 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4810 11:45:30.656615 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4811 11:45:30.656688 ==
4812 11:45:30.659976 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 11:45:30.663335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 11:45:30.666542 ==
4815 11:45:30.666645 DQS Delay:
4816 11:45:30.666734 DQS0 = 0, DQS1 = 0
4817 11:45:30.670260 DQM Delay:
4818 11:45:30.670361 DQM0 = 43, DQM1 = 34
4819 11:45:30.673180 DQ Delay:
4820 11:45:30.673274 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4821 11:45:30.676169 DQ4 =40, DQ5 =56, DQ6 =56, DQ7 =40
4822 11:45:30.679460 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4823 11:45:30.683078 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4824 11:45:30.686683
4825 11:45:30.686778
4826 11:45:30.692831 [DQSOSCAuto] RK1, (LSB)MR18= 0x3025, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4827 11:45:30.696277 CH1 RK1: MR19=808, MR18=3025
4828 11:45:30.702703 CH1_RK1: MR19=0x808, MR18=0x3025, DQSOSC=400, MR23=63, INC=163, DEC=109
4829 11:45:30.706039 [RxdqsGatingPostProcess] freq 600
4830 11:45:30.709444 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4831 11:45:30.712396 Pre-setting of DQS Precalculation
4832 11:45:30.719103 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4833 11:45:30.725555 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4834 11:45:30.732127 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4835 11:45:30.732207
4836 11:45:30.732270
4837 11:45:30.735517 [Calibration Summary] 1200 Mbps
4838 11:45:30.735597 CH 0, Rank 0
4839 11:45:30.738938 SW Impedance : PASS
4840 11:45:30.742170 DUTY Scan : NO K
4841 11:45:30.742251 ZQ Calibration : PASS
4842 11:45:30.745280 Jitter Meter : NO K
4843 11:45:30.748904 CBT Training : PASS
4844 11:45:30.748985 Write leveling : PASS
4845 11:45:30.752135 RX DQS gating : PASS
4846 11:45:30.755208 RX DQ/DQS(RDDQC) : PASS
4847 11:45:30.755289 TX DQ/DQS : PASS
4848 11:45:30.758732 RX DATLAT : PASS
4849 11:45:30.762154 RX DQ/DQS(Engine): PASS
4850 11:45:30.762235 TX OE : NO K
4851 11:45:30.762320 All Pass.
4852 11:45:30.765370
4853 11:45:30.765495 CH 0, Rank 1
4854 11:45:30.768416 SW Impedance : PASS
4855 11:45:30.768508 DUTY Scan : NO K
4856 11:45:30.772314 ZQ Calibration : PASS
4857 11:45:30.775344 Jitter Meter : NO K
4858 11:45:30.775450 CBT Training : PASS
4859 11:45:30.778733 Write leveling : PASS
4860 11:45:30.778807 RX DQS gating : PASS
4861 11:45:30.782077 RX DQ/DQS(RDDQC) : PASS
4862 11:45:30.785222 TX DQ/DQS : PASS
4863 11:45:30.785321 RX DATLAT : PASS
4864 11:45:30.788790 RX DQ/DQS(Engine): PASS
4865 11:45:30.791872 TX OE : NO K
4866 11:45:30.791971 All Pass.
4867 11:45:30.792059
4868 11:45:30.792184 CH 1, Rank 0
4869 11:45:30.794885 SW Impedance : PASS
4870 11:45:30.798111 DUTY Scan : NO K
4871 11:45:30.798210 ZQ Calibration : PASS
4872 11:45:30.801596 Jitter Meter : NO K
4873 11:45:30.804982 CBT Training : PASS
4874 11:45:30.805087 Write leveling : PASS
4875 11:45:30.808008 RX DQS gating : PASS
4876 11:45:30.811527 RX DQ/DQS(RDDQC) : PASS
4877 11:45:30.811598 TX DQ/DQS : PASS
4878 11:45:30.814857 RX DATLAT : PASS
4879 11:45:30.817732 RX DQ/DQS(Engine): PASS
4880 11:45:30.817827 TX OE : NO K
4881 11:45:30.821277 All Pass.
4882 11:45:30.821371
4883 11:45:30.821499 CH 1, Rank 1
4884 11:45:30.824633 SW Impedance : PASS
4885 11:45:30.824732 DUTY Scan : NO K
4886 11:45:30.828030 ZQ Calibration : PASS
4887 11:45:30.831033 Jitter Meter : NO K
4888 11:45:30.831130 CBT Training : PASS
4889 11:45:30.834554 Write leveling : PASS
4890 11:45:30.837947 RX DQS gating : PASS
4891 11:45:30.838037 RX DQ/DQS(RDDQC) : PASS
4892 11:45:30.840842 TX DQ/DQS : PASS
4893 11:45:30.844239 RX DATLAT : PASS
4894 11:45:30.844335 RX DQ/DQS(Engine): PASS
4895 11:45:30.847568 TX OE : NO K
4896 11:45:30.847651 All Pass.
4897 11:45:30.847715
4898 11:45:30.851016 DramC Write-DBI off
4899 11:45:30.854495 PER_BANK_REFRESH: Hybrid Mode
4900 11:45:30.854577 TX_TRACKING: ON
4901 11:45:30.864486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4902 11:45:30.867466 [FAST_K] Save calibration result to emmc
4903 11:45:30.870977 dramc_set_vcore_voltage set vcore to 662500
4904 11:45:30.873935 Read voltage for 933, 3
4905 11:45:30.874017 Vio18 = 0
4906 11:45:30.874097 Vcore = 662500
4907 11:45:30.877627 Vdram = 0
4908 11:45:30.877725 Vddq = 0
4909 11:45:30.877805 Vmddr = 0
4910 11:45:30.883729 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4911 11:45:30.887403 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4912 11:45:30.890598 MEM_TYPE=3, freq_sel=17
4913 11:45:30.893913 sv_algorithm_assistance_LP4_1600
4914 11:45:30.897009 ============ PULL DRAM RESETB DOWN ============
4915 11:45:30.900685 ========== PULL DRAM RESETB DOWN end =========
4916 11:45:30.907453 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4917 11:45:30.910249 ===================================
4918 11:45:30.910332 LPDDR4 DRAM CONFIGURATION
4919 11:45:30.914110 ===================================
4920 11:45:30.917531 EX_ROW_EN[0] = 0x0
4921 11:45:30.920460 EX_ROW_EN[1] = 0x0
4922 11:45:30.920542 LP4Y_EN = 0x0
4923 11:45:30.923692 WORK_FSP = 0x0
4924 11:45:30.923814 WL = 0x3
4925 11:45:30.927196 RL = 0x3
4926 11:45:30.927278 BL = 0x2
4927 11:45:30.930463 RPST = 0x0
4928 11:45:30.930541 RD_PRE = 0x0
4929 11:45:30.933450 WR_PRE = 0x1
4930 11:45:30.933554 WR_PST = 0x0
4931 11:45:30.937480 DBI_WR = 0x0
4932 11:45:30.937577 DBI_RD = 0x0
4933 11:45:30.940387 OTF = 0x1
4934 11:45:30.943585 ===================================
4935 11:45:30.947160 ===================================
4936 11:45:30.947251 ANA top config
4937 11:45:30.950387 ===================================
4938 11:45:30.953336 DLL_ASYNC_EN = 0
4939 11:45:30.956614 ALL_SLAVE_EN = 1
4940 11:45:30.960463 NEW_RANK_MODE = 1
4941 11:45:30.960545 DLL_IDLE_MODE = 1
4942 11:45:30.963192 LP45_APHY_COMB_EN = 1
4943 11:45:30.966663 TX_ODT_DIS = 1
4944 11:45:30.969899 NEW_8X_MODE = 1
4945 11:45:30.973058 ===================================
4946 11:45:30.977333 ===================================
4947 11:45:30.980720 data_rate = 1866
4948 11:45:30.983196 CKR = 1
4949 11:45:30.983302 DQ_P2S_RATIO = 8
4950 11:45:30.986421 ===================================
4951 11:45:30.989784 CA_P2S_RATIO = 8
4952 11:45:30.993287 DQ_CA_OPEN = 0
4953 11:45:30.996611 DQ_SEMI_OPEN = 0
4954 11:45:30.999813 CA_SEMI_OPEN = 0
4955 11:45:31.003021 CA_FULL_RATE = 0
4956 11:45:31.003096 DQ_CKDIV4_EN = 1
4957 11:45:31.006575 CA_CKDIV4_EN = 1
4958 11:45:31.009536 CA_PREDIV_EN = 0
4959 11:45:31.012651 PH8_DLY = 0
4960 11:45:31.016260 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4961 11:45:31.019523 DQ_AAMCK_DIV = 4
4962 11:45:31.019603 CA_AAMCK_DIV = 4
4963 11:45:31.023005 CA_ADMCK_DIV = 4
4964 11:45:31.026293 DQ_TRACK_CA_EN = 0
4965 11:45:31.029306 CA_PICK = 933
4966 11:45:31.032486 CA_MCKIO = 933
4967 11:45:31.036552 MCKIO_SEMI = 0
4968 11:45:31.039637 PLL_FREQ = 3732
4969 11:45:31.039718 DQ_UI_PI_RATIO = 32
4970 11:45:31.042391 CA_UI_PI_RATIO = 0
4971 11:45:31.046355 ===================================
4972 11:45:31.049171 ===================================
4973 11:45:31.052810 memory_type:LPDDR4
4974 11:45:31.056511 GP_NUM : 10
4975 11:45:31.056618 SRAM_EN : 1
4976 11:45:31.059165 MD32_EN : 0
4977 11:45:31.062246 ===================================
4978 11:45:31.065853 [ANA_INIT] >>>>>>>>>>>>>>
4979 11:45:31.065950 <<<<<< [CONFIGURE PHASE]: ANA_TX
4980 11:45:31.069221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4981 11:45:31.072287 ===================================
4982 11:45:31.075827 data_rate = 1866,PCW = 0X8f00
4983 11:45:31.078861 ===================================
4984 11:45:31.082084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4985 11:45:31.088813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 11:45:31.095812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 11:45:31.098730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4988 11:45:31.102518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4989 11:45:31.105724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4990 11:45:31.108980 [ANA_INIT] flow start
4991 11:45:31.109105 [ANA_INIT] PLL >>>>>>>>
4992 11:45:31.112391 [ANA_INIT] PLL <<<<<<<<
4993 11:45:31.115666 [ANA_INIT] MIDPI >>>>>>>>
4994 11:45:31.118701 [ANA_INIT] MIDPI <<<<<<<<
4995 11:45:31.118798 [ANA_INIT] DLL >>>>>>>>
4996 11:45:31.121971 [ANA_INIT] flow end
4997 11:45:31.125297 ============ LP4 DIFF to SE enter ============
4998 11:45:31.128700 ============ LP4 DIFF to SE exit ============
4999 11:45:31.132325 [ANA_INIT] <<<<<<<<<<<<<
5000 11:45:31.135172 [Flow] Enable top DCM control >>>>>
5001 11:45:31.138505 [Flow] Enable top DCM control <<<<<
5002 11:45:31.142061 Enable DLL master slave shuffle
5003 11:45:31.148400 ==============================================================
5004 11:45:31.148509 Gating Mode config
5005 11:45:31.155045 ==============================================================
5006 11:45:31.155146 Config description:
5007 11:45:31.164740 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5008 11:45:31.171671 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5009 11:45:31.178485 SELPH_MODE 0: By rank 1: By Phase
5010 11:45:31.181375 ==============================================================
5011 11:45:31.184860 GAT_TRACK_EN = 1
5012 11:45:31.188386 RX_GATING_MODE = 2
5013 11:45:31.191488 RX_GATING_TRACK_MODE = 2
5014 11:45:31.194987 SELPH_MODE = 1
5015 11:45:31.198126 PICG_EARLY_EN = 1
5016 11:45:31.201168 VALID_LAT_VALUE = 1
5017 11:45:31.208355 ==============================================================
5018 11:45:31.211262 Enter into Gating configuration >>>>
5019 11:45:31.214504 Exit from Gating configuration <<<<
5020 11:45:31.217592 Enter into DVFS_PRE_config >>>>>
5021 11:45:31.227914 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5022 11:45:31.230823 Exit from DVFS_PRE_config <<<<<
5023 11:45:31.233905 Enter into PICG configuration >>>>
5024 11:45:31.237301 Exit from PICG configuration <<<<
5025 11:45:31.240621 [RX_INPUT] configuration >>>>>
5026 11:45:31.240705 [RX_INPUT] configuration <<<<<
5027 11:45:31.247365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5028 11:45:31.254011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5029 11:45:31.260557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 11:45:31.263661 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 11:45:31.270708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 11:45:31.276928 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 11:45:31.280362 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5034 11:45:31.283470 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5035 11:45:31.290042 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5036 11:45:31.294132 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5037 11:45:31.297209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5038 11:45:31.303529 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 11:45:31.307122 ===================================
5040 11:45:31.307220 LPDDR4 DRAM CONFIGURATION
5041 11:45:31.310624 ===================================
5042 11:45:31.313367 EX_ROW_EN[0] = 0x0
5043 11:45:31.313488 EX_ROW_EN[1] = 0x0
5044 11:45:31.316836 LP4Y_EN = 0x0
5045 11:45:31.320146 WORK_FSP = 0x0
5046 11:45:31.320250 WL = 0x3
5047 11:45:31.323613 RL = 0x3
5048 11:45:31.323709 BL = 0x2
5049 11:45:31.326823 RPST = 0x0
5050 11:45:31.326922 RD_PRE = 0x0
5051 11:45:31.330154 WR_PRE = 0x1
5052 11:45:31.330226 WR_PST = 0x0
5053 11:45:31.333185 DBI_WR = 0x0
5054 11:45:31.333281 DBI_RD = 0x0
5055 11:45:31.336602 OTF = 0x1
5056 11:45:31.340194 ===================================
5057 11:45:31.343235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5058 11:45:31.346638 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5059 11:45:31.353168 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 11:45:31.356419 ===================================
5061 11:45:31.356499 LPDDR4 DRAM CONFIGURATION
5062 11:45:31.359783 ===================================
5063 11:45:31.362847 EX_ROW_EN[0] = 0x10
5064 11:45:31.366715 EX_ROW_EN[1] = 0x0
5065 11:45:31.366799 LP4Y_EN = 0x0
5066 11:45:31.369717 WORK_FSP = 0x0
5067 11:45:31.369798 WL = 0x3
5068 11:45:31.373170 RL = 0x3
5069 11:45:31.373260 BL = 0x2
5070 11:45:31.376036 RPST = 0x0
5071 11:45:31.376136 RD_PRE = 0x0
5072 11:45:31.379326 WR_PRE = 0x1
5073 11:45:31.379423 WR_PST = 0x0
5074 11:45:31.382988 DBI_WR = 0x0
5075 11:45:31.383065 DBI_RD = 0x0
5076 11:45:31.386174 OTF = 0x1
5077 11:45:31.389235 ===================================
5078 11:45:31.395846 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5079 11:45:31.399281 nWR fixed to 30
5080 11:45:31.399367 [ModeRegInit_LP4] CH0 RK0
5081 11:45:31.402831 [ModeRegInit_LP4] CH0 RK1
5082 11:45:31.405652 [ModeRegInit_LP4] CH1 RK0
5083 11:45:31.409350 [ModeRegInit_LP4] CH1 RK1
5084 11:45:31.409487 match AC timing 9
5085 11:45:31.415866 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5086 11:45:31.419094 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5087 11:45:31.422139 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5088 11:45:31.428863 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5089 11:45:31.432157 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5090 11:45:31.432238 ==
5091 11:45:31.435348 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 11:45:31.439069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 11:45:31.439151 ==
5094 11:45:31.445293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 11:45:31.451904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 11:45:31.455396 [CA 0] Center 37 (7~68) winsize 62
5097 11:45:31.459117 [CA 1] Center 37 (7~68) winsize 62
5098 11:45:31.462263 [CA 2] Center 34 (4~65) winsize 62
5099 11:45:31.465325 [CA 3] Center 35 (5~65) winsize 61
5100 11:45:31.469031 [CA 4] Center 33 (3~64) winsize 62
5101 11:45:31.472177 [CA 5] Center 33 (3~63) winsize 61
5102 11:45:31.472258
5103 11:45:31.475582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 11:45:31.475664
5105 11:45:31.479042 [CATrainingPosCal] consider 1 rank data
5106 11:45:31.481828 u2DelayCellTimex100 = 270/100 ps
5107 11:45:31.485650 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5108 11:45:31.488905 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 11:45:31.492051 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5110 11:45:31.495075 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5111 11:45:31.498564 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5112 11:45:31.501776 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5113 11:45:31.501858
5114 11:45:31.508341 CA PerBit enable=1, Macro0, CA PI delay=33
5115 11:45:31.508423
5116 11:45:31.511668 [CBTSetCACLKResult] CA Dly = 33
5117 11:45:31.511768 CS Dly: 7 (0~38)
5118 11:45:31.511866 ==
5119 11:45:31.515165 Dram Type= 6, Freq= 0, CH_0, rank 1
5120 11:45:31.518496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 11:45:31.518580 ==
5122 11:45:31.525099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5123 11:45:31.531401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5124 11:45:31.534741 [CA 0] Center 37 (7~68) winsize 62
5125 11:45:31.538084 [CA 1] Center 37 (7~68) winsize 62
5126 11:45:31.541770 [CA 2] Center 34 (4~65) winsize 62
5127 11:45:31.544742 [CA 3] Center 34 (4~65) winsize 62
5128 11:45:31.548211 [CA 4] Center 33 (3~64) winsize 62
5129 11:45:31.551507 [CA 5] Center 33 (3~63) winsize 61
5130 11:45:31.551586
5131 11:45:31.555087 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5132 11:45:31.555170
5133 11:45:31.558004 [CATrainingPosCal] consider 2 rank data
5134 11:45:31.561084 u2DelayCellTimex100 = 270/100 ps
5135 11:45:31.564619 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5136 11:45:31.567714 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5137 11:45:31.571382 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5138 11:45:31.574560 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5139 11:45:31.580946 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5140 11:45:31.584352 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5141 11:45:31.584455
5142 11:45:31.587321 CA PerBit enable=1, Macro0, CA PI delay=33
5143 11:45:31.587397
5144 11:45:31.591192 [CBTSetCACLKResult] CA Dly = 33
5145 11:45:31.591274 CS Dly: 7 (0~39)
5146 11:45:31.591337
5147 11:45:31.593965 ----->DramcWriteLeveling(PI) begin...
5148 11:45:31.594049 ==
5149 11:45:31.597568 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 11:45:31.603800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 11:45:31.603888 ==
5152 11:45:31.607242 Write leveling (Byte 0): 32 => 32
5153 11:45:31.611041 Write leveling (Byte 1): 30 => 30
5154 11:45:31.613575 DramcWriteLeveling(PI) end<-----
5155 11:45:31.613658
5156 11:45:31.613742 ==
5157 11:45:31.617329 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 11:45:31.620901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 11:45:31.620985 ==
5160 11:45:31.624214 [Gating] SW mode calibration
5161 11:45:31.630299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5162 11:45:31.636952 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5163 11:45:31.640201 0 14 0 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
5164 11:45:31.643840 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5165 11:45:31.649951 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 11:45:31.653655 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 11:45:31.656926 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 11:45:31.663358 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 11:45:31.666627 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 11:45:31.670090 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5171 11:45:31.673167 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5172 11:45:31.679605 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5173 11:45:31.683172 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 11:45:31.689448 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 11:45:31.692990 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 11:45:31.696219 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 11:45:31.699856 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 11:45:31.706510 0 15 28 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5179 11:45:31.709707 1 0 0 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
5180 11:45:31.712975 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:45:31.719330 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:45:31.723118 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 11:45:31.725966 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 11:45:31.732768 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 11:45:31.735961 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 11:45:31.739002 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 11:45:31.745784 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5188 11:45:31.749118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:45:31.755347 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:45:31.759101 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:45:31.762275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:45:31.768790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:45:31.772534 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:45:31.775346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:45:31.781867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:45:31.785232 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:45:31.788334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:45:31.794885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:45:31.798240 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:45:31.801582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:45:31.808027 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:45:31.811562 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5203 11:45:31.814790 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 11:45:31.818398 Total UI for P1: 0, mck2ui 16
5205 11:45:31.821559 best dqsien dly found for B0: ( 1, 2, 28)
5206 11:45:31.824973 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5207 11:45:31.831581 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:45:31.834798 Total UI for P1: 0, mck2ui 16
5209 11:45:31.838366 best dqsien dly found for B1: ( 1, 3, 2)
5210 11:45:31.841303 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5211 11:45:31.844857 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5212 11:45:31.844941
5213 11:45:31.848151 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5214 11:45:31.851150 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5215 11:45:31.854587 [Gating] SW calibration Done
5216 11:45:31.854670 ==
5217 11:45:31.857801 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 11:45:31.861273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 11:45:31.861384 ==
5220 11:45:31.864757 RX Vref Scan: 0
5221 11:45:31.864885
5222 11:45:31.867429 RX Vref 0 -> 0, step: 1
5223 11:45:31.867514
5224 11:45:31.867598 RX Delay -80 -> 252, step: 8
5225 11:45:31.874282 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5226 11:45:31.877303 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5227 11:45:31.881147 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5228 11:45:31.884247 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5229 11:45:31.887863 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5230 11:45:31.890867 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5231 11:45:31.897698 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5232 11:45:31.900644 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5233 11:45:31.903990 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5234 11:45:31.906933 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5235 11:45:31.910206 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5236 11:45:31.916847 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5237 11:45:31.920399 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5238 11:45:31.923669 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5239 11:45:31.926978 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5240 11:45:31.933463 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5241 11:45:31.933548 ==
5242 11:45:31.936736 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 11:45:31.940554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 11:45:31.940639 ==
5245 11:45:31.940728 DQS Delay:
5246 11:45:31.943388 DQS0 = 0, DQS1 = 0
5247 11:45:31.943479 DQM Delay:
5248 11:45:31.946694 DQM0 = 96, DQM1 = 86
5249 11:45:31.946777 DQ Delay:
5250 11:45:31.950047 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5251 11:45:31.953799 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5252 11:45:31.956967 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5253 11:45:31.959820 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5254 11:45:31.959903
5255 11:45:31.959968
5256 11:45:31.960028 ==
5257 11:45:31.963370 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:45:31.966628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:45:31.966711 ==
5260 11:45:31.966777
5261 11:45:31.970195
5262 11:45:31.970277 TX Vref Scan disable
5263 11:45:31.973949 == TX Byte 0 ==
5264 11:45:31.977067 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5265 11:45:31.979902 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5266 11:45:31.983077 == TX Byte 1 ==
5267 11:45:31.986269 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5268 11:45:31.990310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5269 11:45:31.990393 ==
5270 11:45:31.992915 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:45:31.999406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:45:31.999490 ==
5273 11:45:31.999559
5274 11:45:31.999641
5275 11:45:31.999721 TX Vref Scan disable
5276 11:45:32.004074 == TX Byte 0 ==
5277 11:45:32.007402 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5278 11:45:32.013843 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5279 11:45:32.013927 == TX Byte 1 ==
5280 11:45:32.017023 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5281 11:45:32.023679 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5282 11:45:32.023760
5283 11:45:32.023855 [DATLAT]
5284 11:45:32.023949 Freq=933, CH0 RK0
5285 11:45:32.024007
5286 11:45:32.027144 DATLAT Default: 0xd
5287 11:45:32.027263 0, 0xFFFF, sum = 0
5288 11:45:32.030341 1, 0xFFFF, sum = 0
5289 11:45:32.033528 2, 0xFFFF, sum = 0
5290 11:45:32.033609 3, 0xFFFF, sum = 0
5291 11:45:32.036779 4, 0xFFFF, sum = 0
5292 11:45:32.036861 5, 0xFFFF, sum = 0
5293 11:45:32.040126 6, 0xFFFF, sum = 0
5294 11:45:32.040208 7, 0xFFFF, sum = 0
5295 11:45:32.043808 8, 0xFFFF, sum = 0
5296 11:45:32.043895 9, 0xFFFF, sum = 0
5297 11:45:32.047103 10, 0x0, sum = 1
5298 11:45:32.047188 11, 0x0, sum = 2
5299 11:45:32.050131 12, 0x0, sum = 3
5300 11:45:32.050252 13, 0x0, sum = 4
5301 11:45:32.050344 best_step = 11
5302 11:45:32.053639
5303 11:45:32.053735 ==
5304 11:45:32.056654 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 11:45:32.059978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 11:45:32.060060 ==
5307 11:45:32.060127 RX Vref Scan: 1
5308 11:45:32.060187
5309 11:45:32.063099 RX Vref 0 -> 0, step: 1
5310 11:45:32.063191
5311 11:45:32.066206 RX Delay -61 -> 252, step: 4
5312 11:45:32.066280
5313 11:45:32.069642 Set Vref, RX VrefLevel [Byte0]: 61
5314 11:45:32.072862 [Byte1]: 57
5315 11:45:32.076731
5316 11:45:32.076803 Final RX Vref Byte 0 = 61 to rank0
5317 11:45:32.079463 Final RX Vref Byte 1 = 57 to rank0
5318 11:45:32.083302 Final RX Vref Byte 0 = 61 to rank1
5319 11:45:32.086979 Final RX Vref Byte 1 = 57 to rank1==
5320 11:45:32.089678 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 11:45:32.096420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 11:45:32.096498 ==
5323 11:45:32.096562 DQS Delay:
5324 11:45:32.099752 DQS0 = 0, DQS1 = 0
5325 11:45:32.099825 DQM Delay:
5326 11:45:32.099886 DQM0 = 97, DQM1 = 87
5327 11:45:32.102978 DQ Delay:
5328 11:45:32.106071 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5329 11:45:32.109038 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5330 11:45:32.112722 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5331 11:45:32.115862 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =90
5332 11:45:32.115938
5333 11:45:32.116000
5334 11:45:32.122483 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5335 11:45:32.126378 CH0 RK0: MR19=505, MR18=2A10
5336 11:45:32.132564 CH0_RK0: MR19=0x505, MR18=0x2A10, DQSOSC=408, MR23=63, INC=65, DEC=43
5337 11:45:32.132641
5338 11:45:32.136002 ----->DramcWriteLeveling(PI) begin...
5339 11:45:32.136095 ==
5340 11:45:32.139112 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 11:45:32.142703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 11:45:32.142785 ==
5343 11:45:32.145901 Write leveling (Byte 0): 33 => 33
5344 11:45:32.149221 Write leveling (Byte 1): 30 => 30
5345 11:45:32.152568 DramcWriteLeveling(PI) end<-----
5346 11:45:32.152647
5347 11:45:32.152709 ==
5348 11:45:32.155630 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 11:45:32.158846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 11:45:32.162569 ==
5351 11:45:32.162648 [Gating] SW mode calibration
5352 11:45:32.168708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 11:45:32.175558 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 11:45:32.178810 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5355 11:45:32.185894 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:45:32.188699 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 11:45:32.193393 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 11:45:32.198538 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 11:45:32.201938 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 11:45:32.205243 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 11:45:32.211660 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 0)
5362 11:45:32.215140 0 15 0 | B1->B0 | 2d2d 2828 | 0 0 | (1 1) (0 0)
5363 11:45:32.218452 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:45:32.225005 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 11:45:32.228423 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 11:45:32.231929 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 11:45:32.238060 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 11:45:32.241912 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 11:45:32.244684 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5370 11:45:32.251631 1 0 0 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
5371 11:45:32.254963 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:45:32.258032 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:45:32.264946 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:45:32.267828 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 11:45:32.270955 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 11:45:32.277637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 11:45:32.280871 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 11:45:32.284480 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:45:32.290977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:45:32.294918 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:45:32.297442 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:45:32.304333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:45:32.307702 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:45:32.310717 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:45:32.317459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:45:32.320828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:45:32.324573 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:45:32.330429 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:45:32.333997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:45:32.337167 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:45:32.343664 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:45:32.347416 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:45:32.350908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5394 11:45:32.357625 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5395 11:45:32.360523 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5396 11:45:32.363627 Total UI for P1: 0, mck2ui 16
5397 11:45:32.367186 best dqsien dly found for B0: ( 1, 2, 30)
5398 11:45:32.370297 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:45:32.373613 Total UI for P1: 0, mck2ui 16
5400 11:45:32.377112 best dqsien dly found for B1: ( 1, 3, 2)
5401 11:45:32.380376 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5402 11:45:32.383498 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5403 11:45:32.383578
5404 11:45:32.386800 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5405 11:45:32.394085 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5406 11:45:32.394166 [Gating] SW calibration Done
5407 11:45:32.394229 ==
5408 11:45:32.396612 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 11:45:32.403222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 11:45:32.403302 ==
5411 11:45:32.403366 RX Vref Scan: 0
5412 11:45:32.403426
5413 11:45:32.406488 RX Vref 0 -> 0, step: 1
5414 11:45:32.406568
5415 11:45:32.410497 RX Delay -80 -> 252, step: 8
5416 11:45:32.412785 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5417 11:45:32.416849 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5418 11:45:32.419894 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5419 11:45:32.426083 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5420 11:45:32.429427 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5421 11:45:32.432594 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5422 11:45:32.436327 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5423 11:45:32.439630 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5424 11:45:32.442636 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5425 11:45:32.449277 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5426 11:45:32.452811 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5427 11:45:32.455712 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5428 11:45:32.459324 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5429 11:45:32.462356 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5430 11:45:32.469142 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5431 11:45:32.472365 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5432 11:45:32.472454 ==
5433 11:45:32.476103 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 11:45:32.478818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 11:45:32.478898 ==
5436 11:45:32.482124 DQS Delay:
5437 11:45:32.482204 DQS0 = 0, DQS1 = 0
5438 11:45:32.482267 DQM Delay:
5439 11:45:32.485796 DQM0 = 97, DQM1 = 89
5440 11:45:32.485879 DQ Delay:
5441 11:45:32.488708 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5442 11:45:32.491893 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5443 11:45:32.495204 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5444 11:45:32.498576 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5445 11:45:32.498656
5446 11:45:32.498749
5447 11:45:32.498808 ==
5448 11:45:32.501999 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 11:45:32.508791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 11:45:32.508899 ==
5451 11:45:32.509023
5452 11:45:32.509109
5453 11:45:32.509213 TX Vref Scan disable
5454 11:45:32.512284 == TX Byte 0 ==
5455 11:45:32.515533 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5456 11:45:32.522480 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5457 11:45:32.522560 == TX Byte 1 ==
5458 11:45:32.525833 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5459 11:45:32.532251 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5460 11:45:32.532382 ==
5461 11:45:32.535364 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:45:32.538906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:45:32.538987 ==
5464 11:45:32.539054
5465 11:45:32.539118
5466 11:45:32.542274 TX Vref Scan disable
5467 11:45:32.542354 == TX Byte 0 ==
5468 11:45:32.548871 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5469 11:45:32.552007 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5470 11:45:32.555294 == TX Byte 1 ==
5471 11:45:32.558824 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5472 11:45:32.562213 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5473 11:45:32.562289
5474 11:45:32.562391 [DATLAT]
5475 11:45:32.565226 Freq=933, CH0 RK1
5476 11:45:32.565300
5477 11:45:32.565361 DATLAT Default: 0xb
5478 11:45:32.568808 0, 0xFFFF, sum = 0
5479 11:45:32.568882 1, 0xFFFF, sum = 0
5480 11:45:32.571876 2, 0xFFFF, sum = 0
5481 11:45:32.575161 3, 0xFFFF, sum = 0
5482 11:45:32.575245 4, 0xFFFF, sum = 0
5483 11:45:32.578492 5, 0xFFFF, sum = 0
5484 11:45:32.578575 6, 0xFFFF, sum = 0
5485 11:45:32.581762 7, 0xFFFF, sum = 0
5486 11:45:32.581844 8, 0xFFFF, sum = 0
5487 11:45:32.585241 9, 0xFFFF, sum = 0
5488 11:45:32.585324 10, 0x0, sum = 1
5489 11:45:32.588497 11, 0x0, sum = 2
5490 11:45:32.588580 12, 0x0, sum = 3
5491 11:45:32.591667 13, 0x0, sum = 4
5492 11:45:32.591750 best_step = 11
5493 11:45:32.591814
5494 11:45:32.591913 ==
5495 11:45:32.594910 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 11:45:32.598230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 11:45:32.598313 ==
5498 11:45:32.601475 RX Vref Scan: 0
5499 11:45:32.601555
5500 11:45:32.604896 RX Vref 0 -> 0, step: 1
5501 11:45:32.604977
5502 11:45:32.605041 RX Delay -61 -> 252, step: 4
5503 11:45:32.612805 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5504 11:45:32.615874 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5505 11:45:32.619388 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5506 11:45:32.622822 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5507 11:45:32.626472 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5508 11:45:32.629562 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5509 11:45:32.635755 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5510 11:45:32.639040 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5511 11:45:32.642498 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5512 11:45:32.645881 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5513 11:45:32.652537 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5514 11:45:32.655674 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5515 11:45:32.659047 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5516 11:45:32.662017 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5517 11:45:32.665195 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5518 11:45:32.668763 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5519 11:45:32.672121 ==
5520 11:45:32.675496 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 11:45:32.678921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 11:45:32.679003 ==
5523 11:45:32.679068 DQS Delay:
5524 11:45:32.682256 DQS0 = 0, DQS1 = 0
5525 11:45:32.682369 DQM Delay:
5526 11:45:32.685245 DQM0 = 95, DQM1 = 88
5527 11:45:32.685375 DQ Delay:
5528 11:45:32.688592 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5529 11:45:32.691979 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5530 11:45:32.695536 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5531 11:45:32.698520 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =92
5532 11:45:32.698602
5533 11:45:32.698666
5534 11:45:32.705252 [DQSOSCAuto] RK1, (LSB)MR18= 0x2af9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5535 11:45:32.708280 CH0 RK1: MR19=504, MR18=2AF9
5536 11:45:32.714940 CH0_RK1: MR19=0x504, MR18=0x2AF9, DQSOSC=408, MR23=63, INC=65, DEC=43
5537 11:45:32.718325 [RxdqsGatingPostProcess] freq 933
5538 11:45:32.724676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 11:45:32.728554 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 11:45:32.731600 best DQS1 dly(2T, 0.5T) = (0, 11)
5541 11:45:32.734611 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 11:45:32.738292 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5543 11:45:32.738374 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 11:45:32.741430 best DQS1 dly(2T, 0.5T) = (0, 11)
5545 11:45:32.744332 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 11:45:32.748318 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5547 11:45:32.751090 Pre-setting of DQS Precalculation
5548 11:45:32.757626 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 11:45:32.757710 ==
5550 11:45:32.760573 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 11:45:32.764269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 11:45:32.764351 ==
5553 11:45:32.770923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 11:45:32.777428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5555 11:45:32.780517 [CA 0] Center 36 (6~67) winsize 62
5556 11:45:32.784309 [CA 1] Center 37 (7~67) winsize 61
5557 11:45:32.787284 [CA 2] Center 34 (4~64) winsize 61
5558 11:45:32.790583 [CA 3] Center 33 (3~64) winsize 62
5559 11:45:32.794018 [CA 4] Center 34 (4~65) winsize 62
5560 11:45:32.797286 [CA 5] Center 33 (3~64) winsize 62
5561 11:45:32.797369
5562 11:45:32.800854 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5563 11:45:32.800936
5564 11:45:32.804135 [CATrainingPosCal] consider 1 rank data
5565 11:45:32.807438 u2DelayCellTimex100 = 270/100 ps
5566 11:45:32.810260 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 11:45:32.814307 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5568 11:45:32.817064 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 11:45:32.820531 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 11:45:32.823883 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 11:45:32.826916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 11:45:32.826998
5573 11:45:32.833705 CA PerBit enable=1, Macro0, CA PI delay=33
5574 11:45:32.833805
5575 11:45:32.836947 [CBTSetCACLKResult] CA Dly = 33
5576 11:45:32.837050 CS Dly: 5 (0~36)
5577 11:45:32.837160 ==
5578 11:45:32.840340 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 11:45:32.843612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 11:45:32.843700 ==
5581 11:45:32.850558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 11:45:32.857132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5583 11:45:32.860441 [CA 0] Center 36 (6~67) winsize 62
5584 11:45:32.863912 [CA 1] Center 36 (6~67) winsize 62
5585 11:45:32.867027 [CA 2] Center 34 (4~65) winsize 62
5586 11:45:32.870039 [CA 3] Center 33 (3~64) winsize 62
5587 11:45:32.873160 [CA 4] Center 34 (3~65) winsize 63
5588 11:45:32.876414 [CA 5] Center 33 (3~64) winsize 62
5589 11:45:32.876495
5590 11:45:32.879771 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5591 11:45:32.879886
5592 11:45:32.883097 [CATrainingPosCal] consider 2 rank data
5593 11:45:32.886405 u2DelayCellTimex100 = 270/100 ps
5594 11:45:32.889719 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 11:45:32.892968 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 11:45:32.895914 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 11:45:32.899239 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 11:45:32.905806 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5599 11:45:32.909084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5600 11:45:32.909198
5601 11:45:32.912897 CA PerBit enable=1, Macro0, CA PI delay=33
5602 11:45:32.912983
5603 11:45:32.916153 [CBTSetCACLKResult] CA Dly = 33
5604 11:45:32.916235 CS Dly: 6 (0~39)
5605 11:45:32.916301
5606 11:45:32.919085 ----->DramcWriteLeveling(PI) begin...
5607 11:45:32.919168 ==
5608 11:45:32.923152 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 11:45:32.928906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 11:45:32.929021 ==
5611 11:45:32.932334 Write leveling (Byte 0): 27 => 27
5612 11:45:32.935498 Write leveling (Byte 1): 27 => 27
5613 11:45:32.935605 DramcWriteLeveling(PI) end<-----
5614 11:45:32.938839
5615 11:45:32.938938 ==
5616 11:45:32.942625 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 11:45:32.945632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:45:32.945715 ==
5619 11:45:32.948978 [Gating] SW mode calibration
5620 11:45:32.955691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 11:45:32.961749 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 11:45:32.965317 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5623 11:45:32.968753 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 11:45:32.975016 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 11:45:32.978464 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 11:45:32.982114 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 11:45:32.988612 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 11:45:32.991463 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
5629 11:45:32.995452 0 14 28 | B1->B0 | 2f2f 2c2c | 0 1 | (1 1) (1 0)
5630 11:45:33.001628 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5631 11:45:33.004860 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 11:45:33.008450 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 11:45:33.014871 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 11:45:33.018089 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 11:45:33.021348 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 11:45:33.028502 0 15 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5637 11:45:33.031103 0 15 28 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (1 1)
5638 11:45:33.034499 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:45:33.038148 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 11:45:33.044563 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 11:45:33.047978 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 11:45:33.054191 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 11:45:33.057902 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 11:45:33.061098 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5645 11:45:33.064259 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5646 11:45:33.070821 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5647 11:45:33.074136 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:45:33.078315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:45:33.084519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:45:33.087469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:45:33.090508 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:45:33.097558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:45:33.100945 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:45:33.104032 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:45:33.110720 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:45:33.113690 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:45:33.116889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:45:33.123533 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:45:33.126785 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5660 11:45:33.133571 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5661 11:45:33.136778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 11:45:33.140065 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:45:33.143127 Total UI for P1: 0, mck2ui 16
5664 11:45:33.146785 best dqsien dly found for B0: ( 1, 2, 24)
5665 11:45:33.149652 Total UI for P1: 0, mck2ui 16
5666 11:45:33.152960 best dqsien dly found for B1: ( 1, 2, 28)
5667 11:45:33.156610 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5668 11:45:33.160190 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5669 11:45:33.160272
5670 11:45:33.163166 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5671 11:45:33.169694 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5672 11:45:33.169777 [Gating] SW calibration Done
5673 11:45:33.169842 ==
5674 11:45:33.173344 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 11:45:33.179929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 11:45:33.180014 ==
5677 11:45:33.180080 RX Vref Scan: 0
5678 11:45:33.180157
5679 11:45:33.183189 RX Vref 0 -> 0, step: 1
5680 11:45:33.183287
5681 11:45:33.185986 RX Delay -80 -> 252, step: 8
5682 11:45:33.189456 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5683 11:45:33.192994 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5684 11:45:33.196111 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5685 11:45:33.202929 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5686 11:45:33.205905 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5687 11:45:33.209203 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5688 11:45:33.212483 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5689 11:45:33.215723 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5690 11:45:33.219417 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5691 11:45:33.225896 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5692 11:45:33.229269 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5693 11:45:33.232213 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5694 11:45:33.235888 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5695 11:45:33.239098 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5696 11:45:33.245838 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5697 11:45:33.249135 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5698 11:45:33.249217 ==
5699 11:45:33.252520 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 11:45:33.255625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 11:45:33.255708 ==
5702 11:45:33.255773 DQS Delay:
5703 11:45:33.259043 DQS0 = 0, DQS1 = 0
5704 11:45:33.259125 DQM Delay:
5705 11:45:33.262235 DQM0 = 101, DQM1 = 91
5706 11:45:33.262329 DQ Delay:
5707 11:45:33.265545 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =103
5708 11:45:33.269089 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5709 11:45:33.272413 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5710 11:45:33.275489 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5711 11:45:33.275571
5712 11:45:33.275634
5713 11:45:33.275694 ==
5714 11:45:33.279131 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 11:45:33.285683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 11:45:33.285765 ==
5717 11:45:33.285830
5718 11:45:33.285890
5719 11:45:33.285947 TX Vref Scan disable
5720 11:45:33.288897 == TX Byte 0 ==
5721 11:45:33.292468 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5722 11:45:33.298866 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5723 11:45:33.299008 == TX Byte 1 ==
5724 11:45:33.301802 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5725 11:45:33.308494 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5726 11:45:33.308579 ==
5727 11:45:33.311812 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 11:45:33.315080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 11:45:33.315163 ==
5730 11:45:33.315228
5731 11:45:33.315289
5732 11:45:33.318118 TX Vref Scan disable
5733 11:45:33.321592 == TX Byte 0 ==
5734 11:45:33.325162 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5735 11:45:33.328687 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5736 11:45:33.331414 == TX Byte 1 ==
5737 11:45:33.334810 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5738 11:45:33.338169 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5739 11:45:33.338275
5740 11:45:33.338341 [DATLAT]
5741 11:45:33.341887 Freq=933, CH1 RK0
5742 11:45:33.341969
5743 11:45:33.345178 DATLAT Default: 0xd
5744 11:45:33.345261 0, 0xFFFF, sum = 0
5745 11:45:33.347975 1, 0xFFFF, sum = 0
5746 11:45:33.348058 2, 0xFFFF, sum = 0
5747 11:45:33.351801 3, 0xFFFF, sum = 0
5748 11:45:33.351884 4, 0xFFFF, sum = 0
5749 11:45:33.355058 5, 0xFFFF, sum = 0
5750 11:45:33.355141 6, 0xFFFF, sum = 0
5751 11:45:33.358058 7, 0xFFFF, sum = 0
5752 11:45:33.358141 8, 0xFFFF, sum = 0
5753 11:45:33.361164 9, 0xFFFF, sum = 0
5754 11:45:33.361246 10, 0x0, sum = 1
5755 11:45:33.364712 11, 0x0, sum = 2
5756 11:45:33.364794 12, 0x0, sum = 3
5757 11:45:33.367696 13, 0x0, sum = 4
5758 11:45:33.367796 best_step = 11
5759 11:45:33.367862
5760 11:45:33.367922 ==
5761 11:45:33.371079 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 11:45:33.374537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 11:45:33.377864 ==
5764 11:45:33.377937 RX Vref Scan: 1
5765 11:45:33.378001
5766 11:45:33.381382 RX Vref 0 -> 0, step: 1
5767 11:45:33.381476
5768 11:45:33.384496 RX Delay -69 -> 252, step: 4
5769 11:45:33.384574
5770 11:45:33.387713 Set Vref, RX VrefLevel [Byte0]: 50
5771 11:45:33.391031 [Byte1]: 51
5772 11:45:33.391133
5773 11:45:33.393940 Final RX Vref Byte 0 = 50 to rank0
5774 11:45:33.397484 Final RX Vref Byte 1 = 51 to rank0
5775 11:45:33.401079 Final RX Vref Byte 0 = 50 to rank1
5776 11:45:33.404249 Final RX Vref Byte 1 = 51 to rank1==
5777 11:45:33.407582 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 11:45:33.410751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 11:45:33.410833 ==
5780 11:45:33.413799 DQS Delay:
5781 11:45:33.413902 DQS0 = 0, DQS1 = 0
5782 11:45:33.413968 DQM Delay:
5783 11:45:33.417144 DQM0 = 101, DQM1 = 93
5784 11:45:33.417212 DQ Delay:
5785 11:45:33.421053 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =96
5786 11:45:33.423728 DQ4 =98, DQ5 =112, DQ6 =112, DQ7 =98
5787 11:45:33.427181 DQ8 =80, DQ9 =86, DQ10 =92, DQ11 =84
5788 11:45:33.430260 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =104
5789 11:45:33.430338
5790 11:45:33.433537
5791 11:45:33.440309 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5792 11:45:33.443718 CH1 RK0: MR19=505, MR18=1E0E
5793 11:45:33.450414 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5794 11:45:33.450511
5795 11:45:33.453254 ----->DramcWriteLeveling(PI) begin...
5796 11:45:33.453373 ==
5797 11:45:33.456871 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 11:45:33.460017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 11:45:33.460091 ==
5800 11:45:33.463647 Write leveling (Byte 0): 27 => 27
5801 11:45:33.466620 Write leveling (Byte 1): 31 => 31
5802 11:45:33.469862 DramcWriteLeveling(PI) end<-----
5803 11:45:33.469941
5804 11:45:33.470007 ==
5805 11:45:33.474028 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 11:45:33.476566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 11:45:33.476646 ==
5808 11:45:33.480543 [Gating] SW mode calibration
5809 11:45:33.486823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5810 11:45:33.493358 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5811 11:45:33.496443 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5812 11:45:33.503302 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 11:45:33.506311 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 11:45:33.509726 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 11:45:33.516337 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 11:45:33.519307 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 11:45:33.522858 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
5818 11:45:33.529050 0 14 28 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
5819 11:45:33.532705 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5820 11:45:33.536126 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 11:45:33.542355 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 11:45:33.546046 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 11:45:33.548980 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 11:45:33.555418 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 11:45:33.558835 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5826 11:45:33.562426 0 15 28 | B1->B0 | 4040 3433 | 0 1 | (0 0) (1 1)
5827 11:45:33.568693 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 11:45:33.572232 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:45:33.575315 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 11:45:33.582863 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 11:45:33.585838 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 11:45:33.588480 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 11:45:33.595303 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5834 11:45:33.598390 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5835 11:45:33.601743 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5836 11:45:33.608660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:45:33.611656 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:45:33.615061 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:45:33.621789 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:45:33.625243 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:45:33.628225 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:45:33.635182 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:45:33.638378 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:45:33.641228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:45:33.647918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:45:33.651486 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:45:33.654767 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:45:33.661344 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:45:33.664528 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:45:33.668135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5851 11:45:33.671016 Total UI for P1: 0, mck2ui 16
5852 11:45:33.674487 best dqsien dly found for B1: ( 1, 2, 26)
5853 11:45:33.677522 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:45:33.680855 Total UI for P1: 0, mck2ui 16
5855 11:45:33.683997 best dqsien dly found for B0: ( 1, 2, 28)
5856 11:45:33.690869 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5857 11:45:33.694409 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5858 11:45:33.694487
5859 11:45:33.697688 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5860 11:45:33.700762 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 11:45:33.704334 [Gating] SW calibration Done
5862 11:45:33.704441 ==
5863 11:45:33.707457 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 11:45:33.710418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 11:45:33.710495 ==
5866 11:45:33.713661 RX Vref Scan: 0
5867 11:45:33.713746
5868 11:45:33.713809 RX Vref 0 -> 0, step: 1
5869 11:45:33.713869
5870 11:45:33.717034 RX Delay -80 -> 252, step: 8
5871 11:45:33.720791 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5872 11:45:33.726980 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5873 11:45:33.730780 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5874 11:45:33.734078 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5875 11:45:33.737105 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5876 11:45:33.740238 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5877 11:45:33.743807 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5878 11:45:33.750196 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5879 11:45:33.753624 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5880 11:45:33.757266 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5881 11:45:33.760414 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5882 11:45:33.763862 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5883 11:45:33.769966 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5884 11:45:33.773350 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5885 11:45:33.776412 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5886 11:45:33.779941 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5887 11:45:33.780022 ==
5888 11:45:33.782943 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 11:45:33.786699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 11:45:33.786779 ==
5891 11:45:33.789974 DQS Delay:
5892 11:45:33.790050 DQS0 = 0, DQS1 = 0
5893 11:45:33.793319 DQM Delay:
5894 11:45:33.793450 DQM0 = 100, DQM1 = 90
5895 11:45:33.796136 DQ Delay:
5896 11:45:33.796211 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5897 11:45:33.799931 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5898 11:45:33.802673 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =79
5899 11:45:33.810033 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5900 11:45:33.810115
5901 11:45:33.810183
5902 11:45:33.810242 ==
5903 11:45:33.812916 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 11:45:33.815787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 11:45:33.815868 ==
5906 11:45:33.815934
5907 11:45:33.815992
5908 11:45:33.819398 TX Vref Scan disable
5909 11:45:33.819472 == TX Byte 0 ==
5910 11:45:33.825777 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5911 11:45:33.829689 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5912 11:45:33.829769 == TX Byte 1 ==
5913 11:45:33.835574 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5914 11:45:33.839009 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5915 11:45:33.839085 ==
5916 11:45:33.842481 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 11:45:33.845922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 11:45:33.846008 ==
5919 11:45:33.846072
5920 11:45:33.848722
5921 11:45:33.848795 TX Vref Scan disable
5922 11:45:33.852438 == TX Byte 0 ==
5923 11:45:33.855674 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5924 11:45:33.858872 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5925 11:45:33.862180 == TX Byte 1 ==
5926 11:45:33.865905 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5927 11:45:33.872098 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5928 11:45:33.872204
5929 11:45:33.872305 [DATLAT]
5930 11:45:33.872397 Freq=933, CH1 RK1
5931 11:45:33.872496
5932 11:45:33.875517 DATLAT Default: 0xb
5933 11:45:33.875629 0, 0xFFFF, sum = 0
5934 11:45:33.878836 1, 0xFFFF, sum = 0
5935 11:45:33.881951 2, 0xFFFF, sum = 0
5936 11:45:33.882027 3, 0xFFFF, sum = 0
5937 11:45:33.885375 4, 0xFFFF, sum = 0
5938 11:45:33.885494 5, 0xFFFF, sum = 0
5939 11:45:33.888490 6, 0xFFFF, sum = 0
5940 11:45:33.888564 7, 0xFFFF, sum = 0
5941 11:45:33.892075 8, 0xFFFF, sum = 0
5942 11:45:33.892152 9, 0xFFFF, sum = 0
5943 11:45:33.895608 10, 0x0, sum = 1
5944 11:45:33.895685 11, 0x0, sum = 2
5945 11:45:33.898338 12, 0x0, sum = 3
5946 11:45:33.898412 13, 0x0, sum = 4
5947 11:45:33.898521 best_step = 11
5948 11:45:33.898580
5949 11:45:33.902014 ==
5950 11:45:33.905680 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 11:45:33.908648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 11:45:33.908729 ==
5953 11:45:33.908796 RX Vref Scan: 0
5954 11:45:33.908855
5955 11:45:33.911792 RX Vref 0 -> 0, step: 1
5956 11:45:33.911866
5957 11:45:33.915027 RX Delay -61 -> 252, step: 4
5958 11:45:33.921830 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5959 11:45:33.925567 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5960 11:45:33.928305 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5961 11:45:33.932192 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
5962 11:45:33.935020 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5963 11:45:33.938294 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5964 11:45:33.945059 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5965 11:45:33.948068 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5966 11:45:33.951634 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
5967 11:45:33.954578 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5968 11:45:33.958124 iDelay=207, Bit 10, Center 90 (-1 ~ 182) 184
5969 11:45:33.961180 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5970 11:45:33.968461 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5971 11:45:33.971428 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
5972 11:45:33.974515 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5973 11:45:33.978041 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5974 11:45:33.978129 ==
5975 11:45:33.981043 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 11:45:33.987896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 11:45:33.987974 ==
5978 11:45:33.988037 DQS Delay:
5979 11:45:33.990880 DQS0 = 0, DQS1 = 0
5980 11:45:33.990955 DQM Delay:
5981 11:45:33.993988 DQM0 = 100, DQM1 = 92
5982 11:45:33.994092 DQ Delay:
5983 11:45:33.997846 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =96
5984 11:45:34.000555 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =96
5985 11:45:34.004226 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =84
5986 11:45:34.007461 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5987 11:45:34.007541
5988 11:45:34.007603
5989 11:45:34.017490 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5990 11:45:34.017569 CH1 RK1: MR19=505, MR18=802
5991 11:45:34.023753 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
5992 11:45:34.027300 [RxdqsGatingPostProcess] freq 933
5993 11:45:34.033812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5994 11:45:34.037046 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 11:45:34.040573 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 11:45:34.040652 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 11:45:34.043824 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 11:45:34.047042 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 11:45:34.050447 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 11:45:34.053528 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 11:45:34.056769 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 11:45:34.060685 Pre-setting of DQS Precalculation
6003 11:45:34.066909 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6004 11:45:34.073400 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6005 11:45:34.079937 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6006 11:45:34.080018
6007 11:45:34.080082
6008 11:45:34.083698 [Calibration Summary] 1866 Mbps
6009 11:45:34.083780 CH 0, Rank 0
6010 11:45:34.086371 SW Impedance : PASS
6011 11:45:34.089907 DUTY Scan : NO K
6012 11:45:34.089992 ZQ Calibration : PASS
6013 11:45:34.093443 Jitter Meter : NO K
6014 11:45:34.096355 CBT Training : PASS
6015 11:45:34.096437 Write leveling : PASS
6016 11:45:34.099517 RX DQS gating : PASS
6017 11:45:34.103138 RX DQ/DQS(RDDQC) : PASS
6018 11:45:34.103236 TX DQ/DQS : PASS
6019 11:45:34.106237 RX DATLAT : PASS
6020 11:45:34.109845 RX DQ/DQS(Engine): PASS
6021 11:45:34.109920 TX OE : NO K
6022 11:45:34.113255 All Pass.
6023 11:45:34.113335
6024 11:45:34.113402 CH 0, Rank 1
6025 11:45:34.116926 SW Impedance : PASS
6026 11:45:34.117001 DUTY Scan : NO K
6027 11:45:34.119825 ZQ Calibration : PASS
6028 11:45:34.123024 Jitter Meter : NO K
6029 11:45:34.123108 CBT Training : PASS
6030 11:45:34.126403 Write leveling : PASS
6031 11:45:34.126479 RX DQS gating : PASS
6032 11:45:34.129959 RX DQ/DQS(RDDQC) : PASS
6033 11:45:34.132911 TX DQ/DQS : PASS
6034 11:45:34.132993 RX DATLAT : PASS
6035 11:45:34.136799 RX DQ/DQS(Engine): PASS
6036 11:45:34.140081 TX OE : NO K
6037 11:45:34.140177 All Pass.
6038 11:45:34.140273
6039 11:45:34.140363 CH 1, Rank 0
6040 11:45:34.143016 SW Impedance : PASS
6041 11:45:34.146225 DUTY Scan : NO K
6042 11:45:34.146305 ZQ Calibration : PASS
6043 11:45:34.150049 Jitter Meter : NO K
6044 11:45:34.153197 CBT Training : PASS
6045 11:45:34.153309 Write leveling : PASS
6046 11:45:34.156559 RX DQS gating : PASS
6047 11:45:34.159521 RX DQ/DQS(RDDQC) : PASS
6048 11:45:34.159599 TX DQ/DQS : PASS
6049 11:45:34.162921 RX DATLAT : PASS
6050 11:45:34.166370 RX DQ/DQS(Engine): PASS
6051 11:45:34.166454 TX OE : NO K
6052 11:45:34.170227 All Pass.
6053 11:45:34.170302
6054 11:45:34.170364 CH 1, Rank 1
6055 11:45:34.173089 SW Impedance : PASS
6056 11:45:34.173166 DUTY Scan : NO K
6057 11:45:34.176337 ZQ Calibration : PASS
6058 11:45:34.179664 Jitter Meter : NO K
6059 11:45:34.179746 CBT Training : PASS
6060 11:45:34.183047 Write leveling : PASS
6061 11:45:34.183129 RX DQS gating : PASS
6062 11:45:34.186136 RX DQ/DQS(RDDQC) : PASS
6063 11:45:34.189517 TX DQ/DQS : PASS
6064 11:45:34.189604 RX DATLAT : PASS
6065 11:45:34.192488 RX DQ/DQS(Engine): PASS
6066 11:45:34.196277 TX OE : NO K
6067 11:45:34.196392 All Pass.
6068 11:45:34.196458
6069 11:45:34.198953 DramC Write-DBI off
6070 11:45:34.199031 PER_BANK_REFRESH: Hybrid Mode
6071 11:45:34.202452 TX_TRACKING: ON
6072 11:45:34.212665 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6073 11:45:34.215894 [FAST_K] Save calibration result to emmc
6074 11:45:34.219076 dramc_set_vcore_voltage set vcore to 650000
6075 11:45:34.222310 Read voltage for 400, 6
6076 11:45:34.222384 Vio18 = 0
6077 11:45:34.222454 Vcore = 650000
6078 11:45:34.226017 Vdram = 0
6079 11:45:34.226116 Vddq = 0
6080 11:45:34.226218 Vmddr = 0
6081 11:45:34.232138 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6082 11:45:34.235821 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6083 11:45:34.238790 MEM_TYPE=3, freq_sel=20
6084 11:45:34.242001 sv_algorithm_assistance_LP4_800
6085 11:45:34.245692 ============ PULL DRAM RESETB DOWN ============
6086 11:45:34.249200 ========== PULL DRAM RESETB DOWN end =========
6087 11:45:34.255790 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6088 11:45:34.258692 ===================================
6089 11:45:34.258776 LPDDR4 DRAM CONFIGURATION
6090 11:45:34.261822 ===================================
6091 11:45:34.265315 EX_ROW_EN[0] = 0x0
6092 11:45:34.269167 EX_ROW_EN[1] = 0x0
6093 11:45:34.269270 LP4Y_EN = 0x0
6094 11:45:34.271897 WORK_FSP = 0x0
6095 11:45:34.271971 WL = 0x2
6096 11:45:34.275121 RL = 0x2
6097 11:45:34.275204 BL = 0x2
6098 11:45:34.278811 RPST = 0x0
6099 11:45:34.278889 RD_PRE = 0x0
6100 11:45:34.281968 WR_PRE = 0x1
6101 11:45:34.282052 WR_PST = 0x0
6102 11:45:34.285602 DBI_WR = 0x0
6103 11:45:34.285677 DBI_RD = 0x0
6104 11:45:34.288481 OTF = 0x1
6105 11:45:34.291685 ===================================
6106 11:45:34.295036 ===================================
6107 11:45:34.295120 ANA top config
6108 11:45:34.298303 ===================================
6109 11:45:34.301521 DLL_ASYNC_EN = 0
6110 11:45:34.305140 ALL_SLAVE_EN = 1
6111 11:45:34.308079 NEW_RANK_MODE = 1
6112 11:45:34.308165 DLL_IDLE_MODE = 1
6113 11:45:34.311968 LP45_APHY_COMB_EN = 1
6114 11:45:34.314612 TX_ODT_DIS = 1
6115 11:45:34.318476 NEW_8X_MODE = 1
6116 11:45:34.321679 ===================================
6117 11:45:34.325000 ===================================
6118 11:45:34.328150 data_rate = 800
6119 11:45:34.328253 CKR = 1
6120 11:45:34.331317 DQ_P2S_RATIO = 4
6121 11:45:34.335083 ===================================
6122 11:45:34.338323 CA_P2S_RATIO = 4
6123 11:45:34.341560 DQ_CA_OPEN = 0
6124 11:45:34.345098 DQ_SEMI_OPEN = 1
6125 11:45:34.347763 CA_SEMI_OPEN = 1
6126 11:45:34.347840 CA_FULL_RATE = 0
6127 11:45:34.351089 DQ_CKDIV4_EN = 0
6128 11:45:34.355067 CA_CKDIV4_EN = 1
6129 11:45:34.357956 CA_PREDIV_EN = 0
6130 11:45:34.361230 PH8_DLY = 0
6131 11:45:34.364304 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6132 11:45:34.364383 DQ_AAMCK_DIV = 0
6133 11:45:34.367955 CA_AAMCK_DIV = 0
6134 11:45:34.370979 CA_ADMCK_DIV = 4
6135 11:45:34.374069 DQ_TRACK_CA_EN = 0
6136 11:45:34.377588 CA_PICK = 800
6137 11:45:34.381080 CA_MCKIO = 400
6138 11:45:34.384183 MCKIO_SEMI = 400
6139 11:45:34.384265 PLL_FREQ = 3016
6140 11:45:34.387457 DQ_UI_PI_RATIO = 32
6141 11:45:34.390713 CA_UI_PI_RATIO = 32
6142 11:45:34.394101 ===================================
6143 11:45:34.397221 ===================================
6144 11:45:34.401117 memory_type:LPDDR4
6145 11:45:34.404212 GP_NUM : 10
6146 11:45:34.404295 SRAM_EN : 1
6147 11:45:34.407251 MD32_EN : 0
6148 11:45:34.410868 ===================================
6149 11:45:34.410944 [ANA_INIT] >>>>>>>>>>>>>>
6150 11:45:34.414388 <<<<<< [CONFIGURE PHASE]: ANA_TX
6151 11:45:34.417251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6152 11:45:34.420882 ===================================
6153 11:45:34.424212 data_rate = 800,PCW = 0X7400
6154 11:45:34.427419 ===================================
6155 11:45:34.430882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6156 11:45:34.437441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 11:45:34.446929 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 11:45:34.453815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6159 11:45:34.457061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6160 11:45:34.460328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6161 11:45:34.460410 [ANA_INIT] flow start
6162 11:45:34.463594 [ANA_INIT] PLL >>>>>>>>
6163 11:45:34.466839 [ANA_INIT] PLL <<<<<<<<
6164 11:45:34.469869 [ANA_INIT] MIDPI >>>>>>>>
6165 11:45:34.469969 [ANA_INIT] MIDPI <<<<<<<<
6166 11:45:34.473161 [ANA_INIT] DLL >>>>>>>>
6167 11:45:34.476325 [ANA_INIT] flow end
6168 11:45:34.480042 ============ LP4 DIFF to SE enter ============
6169 11:45:34.483200 ============ LP4 DIFF to SE exit ============
6170 11:45:34.486576 [ANA_INIT] <<<<<<<<<<<<<
6171 11:45:34.489987 [Flow] Enable top DCM control >>>>>
6172 11:45:34.493163 [Flow] Enable top DCM control <<<<<
6173 11:45:34.496800 Enable DLL master slave shuffle
6174 11:45:34.499657 ==============================================================
6175 11:45:34.502910 Gating Mode config
6176 11:45:34.509273 ==============================================================
6177 11:45:34.509355 Config description:
6178 11:45:34.519603 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6179 11:45:34.525840 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6180 11:45:34.533030 SELPH_MODE 0: By rank 1: By Phase
6181 11:45:34.537809 ==============================================================
6182 11:45:34.539476 GAT_TRACK_EN = 0
6183 11:45:34.542416 RX_GATING_MODE = 2
6184 11:45:34.545799 RX_GATING_TRACK_MODE = 2
6185 11:45:34.548969 SELPH_MODE = 1
6186 11:45:34.552640 PICG_EARLY_EN = 1
6187 11:45:34.555922 VALID_LAT_VALUE = 1
6188 11:45:34.559106 ==============================================================
6189 11:45:34.562261 Enter into Gating configuration >>>>
6190 11:45:34.565679 Exit from Gating configuration <<<<
6191 11:45:34.569066 Enter into DVFS_PRE_config >>>>>
6192 11:45:34.581965 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6193 11:45:34.585377 Exit from DVFS_PRE_config <<<<<
6194 11:45:34.589358 Enter into PICG configuration >>>>
6195 11:45:34.591827 Exit from PICG configuration <<<<
6196 11:45:34.591901 [RX_INPUT] configuration >>>>>
6197 11:45:34.595355 [RX_INPUT] configuration <<<<<
6198 11:45:34.601912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6199 11:45:34.605431 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6200 11:45:34.611942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 11:45:34.618351 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 11:45:34.624862 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 11:45:34.631645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 11:45:34.635371 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6205 11:45:34.638505 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6206 11:45:34.645318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6207 11:45:34.648393 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6208 11:45:34.651769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6209 11:45:34.655433 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 11:45:34.658315 ===================================
6211 11:45:34.661612 LPDDR4 DRAM CONFIGURATION
6212 11:45:34.664881 ===================================
6213 11:45:34.668368 EX_ROW_EN[0] = 0x0
6214 11:45:34.668452 EX_ROW_EN[1] = 0x0
6215 11:45:34.671390 LP4Y_EN = 0x0
6216 11:45:34.671465 WORK_FSP = 0x0
6217 11:45:34.675070 WL = 0x2
6218 11:45:34.675160 RL = 0x2
6219 11:45:34.678298 BL = 0x2
6220 11:45:34.678372 RPST = 0x0
6221 11:45:34.681309 RD_PRE = 0x0
6222 11:45:34.685012 WR_PRE = 0x1
6223 11:45:34.685098 WR_PST = 0x0
6224 11:45:34.687950 DBI_WR = 0x0
6225 11:45:34.688054 DBI_RD = 0x0
6226 11:45:34.691373 OTF = 0x1
6227 11:45:34.694600 ===================================
6228 11:45:34.697814 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6229 11:45:34.701242 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6230 11:45:34.704637 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 11:45:34.707947 ===================================
6232 11:45:34.710960 LPDDR4 DRAM CONFIGURATION
6233 11:45:34.714518 ===================================
6234 11:45:34.717750 EX_ROW_EN[0] = 0x10
6235 11:45:34.717848 EX_ROW_EN[1] = 0x0
6236 11:45:34.721032 LP4Y_EN = 0x0
6237 11:45:34.721113 WORK_FSP = 0x0
6238 11:45:34.724258 WL = 0x2
6239 11:45:34.724338 RL = 0x2
6240 11:45:34.727446 BL = 0x2
6241 11:45:34.727526 RPST = 0x0
6242 11:45:34.731097 RD_PRE = 0x0
6243 11:45:34.731212 WR_PRE = 0x1
6244 11:45:34.734228 WR_PST = 0x0
6245 11:45:34.737692 DBI_WR = 0x0
6246 11:45:34.737788 DBI_RD = 0x0
6247 11:45:34.740579 OTF = 0x1
6248 11:45:34.744091 ===================================
6249 11:45:34.747312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6250 11:45:34.752891 nWR fixed to 30
6251 11:45:34.756065 [ModeRegInit_LP4] CH0 RK0
6252 11:45:34.756162 [ModeRegInit_LP4] CH0 RK1
6253 11:45:34.759488 [ModeRegInit_LP4] CH1 RK0
6254 11:45:34.763019 [ModeRegInit_LP4] CH1 RK1
6255 11:45:34.763142 match AC timing 19
6256 11:45:34.769806 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6257 11:45:34.772690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6258 11:45:34.776028 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6259 11:45:34.782674 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6260 11:45:34.785529 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6261 11:45:34.785628 ==
6262 11:45:34.788776 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:45:34.792007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:45:34.792105 ==
6265 11:45:34.799161 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 11:45:34.805272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6267 11:45:34.808626 [CA 0] Center 36 (8~64) winsize 57
6268 11:45:34.812091 [CA 1] Center 36 (8~64) winsize 57
6269 11:45:34.815171 [CA 2] Center 36 (8~64) winsize 57
6270 11:45:34.818642 [CA 3] Center 36 (8~64) winsize 57
6271 11:45:34.821660 [CA 4] Center 36 (8~64) winsize 57
6272 11:45:34.825095 [CA 5] Center 36 (8~64) winsize 57
6273 11:45:34.825192
6274 11:45:34.827973 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6275 11:45:34.828074
6276 11:45:34.831339 [CATrainingPosCal] consider 1 rank data
6277 11:45:34.835069 u2DelayCellTimex100 = 270/100 ps
6278 11:45:34.838680 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:45:34.841534 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:45:34.844616 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:45:34.848061 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:45:34.851062 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 11:45:34.854344 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 11:45:34.854430
6285 11:45:34.861049 CA PerBit enable=1, Macro0, CA PI delay=36
6286 11:45:34.861129
6287 11:45:34.864494 [CBTSetCACLKResult] CA Dly = 36
6288 11:45:34.864572 CS Dly: 1 (0~32)
6289 11:45:34.864641 ==
6290 11:45:34.867442 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 11:45:34.870922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 11:45:34.871000 ==
6293 11:45:34.877550 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 11:45:34.884413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6295 11:45:34.887445 [CA 0] Center 36 (8~64) winsize 57
6296 11:45:34.890747 [CA 1] Center 36 (8~64) winsize 57
6297 11:45:34.893661 [CA 2] Center 36 (8~64) winsize 57
6298 11:45:34.897390 [CA 3] Center 36 (8~64) winsize 57
6299 11:45:34.900349 [CA 4] Center 36 (8~64) winsize 57
6300 11:45:34.904099 [CA 5] Center 36 (8~64) winsize 57
6301 11:45:34.904180
6302 11:45:34.907440 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6303 11:45:34.907514
6304 11:45:34.910725 [CATrainingPosCal] consider 2 rank data
6305 11:45:34.913770 u2DelayCellTimex100 = 270/100 ps
6306 11:45:34.917240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:45:34.920386 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:45:34.923460 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 11:45:34.926902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 11:45:34.930255 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 11:45:34.933451 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 11:45:34.933541
6313 11:45:34.939928 CA PerBit enable=1, Macro0, CA PI delay=36
6314 11:45:34.940010
6315 11:45:34.940078 [CBTSetCACLKResult] CA Dly = 36
6316 11:45:34.943500 CS Dly: 1 (0~32)
6317 11:45:34.943573
6318 11:45:34.946602 ----->DramcWriteLeveling(PI) begin...
6319 11:45:34.946692 ==
6320 11:45:34.949607 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 11:45:34.953086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 11:45:34.953179 ==
6323 11:45:34.956157 Write leveling (Byte 0): 40 => 8
6324 11:45:34.959510 Write leveling (Byte 1): 32 => 0
6325 11:45:34.962974 DramcWriteLeveling(PI) end<-----
6326 11:45:34.963054
6327 11:45:34.963118 ==
6328 11:45:34.966539 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 11:45:34.969837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 11:45:34.973211 ==
6331 11:45:34.973302 [Gating] SW mode calibration
6332 11:45:34.983255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6333 11:45:34.986038 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6334 11:45:34.989697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 11:45:34.996303 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 11:45:34.999326 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 11:45:35.002853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 11:45:35.009221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 11:45:35.012263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 11:45:35.015843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 11:45:35.022351 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 11:45:35.025743 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 11:45:35.028936 Total UI for P1: 0, mck2ui 16
6344 11:45:35.031969 best dqsien dly found for B0: ( 0, 14, 24)
6345 11:45:35.035226 Total UI for P1: 0, mck2ui 16
6346 11:45:35.038784 best dqsien dly found for B1: ( 0, 14, 24)
6347 11:45:35.042259 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6348 11:45:35.045627 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6349 11:45:35.045701
6350 11:45:35.048936 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 11:45:35.055350 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 11:45:35.055433 [Gating] SW calibration Done
6353 11:45:35.058484 ==
6354 11:45:35.058571 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 11:45:35.064920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 11:45:35.065003 ==
6357 11:45:35.065070 RX Vref Scan: 0
6358 11:45:35.065130
6359 11:45:35.068532 RX Vref 0 -> 0, step: 1
6360 11:45:35.068607
6361 11:45:35.071830 RX Delay -410 -> 252, step: 16
6362 11:45:35.075080 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6363 11:45:35.078305 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6364 11:45:35.084810 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6365 11:45:35.087986 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6366 11:45:35.091801 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6367 11:45:35.097709 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6368 11:45:35.101671 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6369 11:45:35.104620 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6370 11:45:35.107934 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6371 11:45:35.114532 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6372 11:45:35.117568 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6373 11:45:35.121061 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6374 11:45:35.124088 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6375 11:45:35.130957 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6376 11:45:35.134439 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6377 11:45:35.137571 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6378 11:45:35.137648 ==
6379 11:45:35.140781 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 11:45:35.147828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 11:45:35.147909 ==
6382 11:45:35.147973 DQS Delay:
6383 11:45:35.150942 DQS0 = 43, DQS1 = 59
6384 11:45:35.151022 DQM Delay:
6385 11:45:35.151085 DQM0 = 10, DQM1 = 11
6386 11:45:35.154106 DQ Delay:
6387 11:45:35.157305 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6388 11:45:35.157398 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6389 11:45:35.160469 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6390 11:45:35.163702 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6391 11:45:35.163777
6392 11:45:35.166972
6393 11:45:35.167045 ==
6394 11:45:35.170185 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 11:45:35.173963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:45:35.174036 ==
6397 11:45:35.174107
6398 11:45:35.174165
6399 11:45:35.177236 TX Vref Scan disable
6400 11:45:35.177337 == TX Byte 0 ==
6401 11:45:35.180637 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 11:45:35.186626 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 11:45:35.186703 == TX Byte 1 ==
6404 11:45:35.190096 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6405 11:45:35.196672 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6406 11:45:35.196749 ==
6407 11:45:35.200188 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 11:45:35.203041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 11:45:35.203121 ==
6410 11:45:35.203183
6411 11:45:35.203240
6412 11:45:35.206600 TX Vref Scan disable
6413 11:45:35.206697 == TX Byte 0 ==
6414 11:45:35.213327 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 11:45:35.216499 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 11:45:35.216592 == TX Byte 1 ==
6417 11:45:35.223056 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6418 11:45:35.226074 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6419 11:45:35.226151
6420 11:45:35.226225 [DATLAT]
6421 11:45:35.229463 Freq=400, CH0 RK0
6422 11:45:35.229564
6423 11:45:35.229626 DATLAT Default: 0xf
6424 11:45:35.232787 0, 0xFFFF, sum = 0
6425 11:45:35.232862 1, 0xFFFF, sum = 0
6426 11:45:35.236058 2, 0xFFFF, sum = 0
6427 11:45:35.236141 3, 0xFFFF, sum = 0
6428 11:45:35.239768 4, 0xFFFF, sum = 0
6429 11:45:35.239843 5, 0xFFFF, sum = 0
6430 11:45:35.242839 6, 0xFFFF, sum = 0
6431 11:45:35.245888 7, 0xFFFF, sum = 0
6432 11:45:35.245970 8, 0xFFFF, sum = 0
6433 11:45:35.249520 9, 0xFFFF, sum = 0
6434 11:45:35.249601 10, 0xFFFF, sum = 0
6435 11:45:35.252583 11, 0xFFFF, sum = 0
6436 11:45:35.252656 12, 0xFFFF, sum = 0
6437 11:45:35.256154 13, 0x0, sum = 1
6438 11:45:35.256233 14, 0x0, sum = 2
6439 11:45:35.259490 15, 0x0, sum = 3
6440 11:45:35.259565 16, 0x0, sum = 4
6441 11:45:35.262903 best_step = 14
6442 11:45:35.262988
6443 11:45:35.263053 ==
6444 11:45:35.265934 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 11:45:35.269497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 11:45:35.269573 ==
6447 11:45:35.269644 RX Vref Scan: 1
6448 11:45:35.269708
6449 11:45:35.272506 RX Vref 0 -> 0, step: 1
6450 11:45:35.272584
6451 11:45:35.276083 RX Delay -359 -> 252, step: 8
6452 11:45:35.276161
6453 11:45:35.279308 Set Vref, RX VrefLevel [Byte0]: 61
6454 11:45:35.282273 [Byte1]: 57
6455 11:45:35.286665
6456 11:45:35.286741 Final RX Vref Byte 0 = 61 to rank0
6457 11:45:35.289934 Final RX Vref Byte 1 = 57 to rank0
6458 11:45:35.293351 Final RX Vref Byte 0 = 61 to rank1
6459 11:45:35.296689 Final RX Vref Byte 1 = 57 to rank1==
6460 11:45:35.299779 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 11:45:35.306336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 11:45:35.306417 ==
6463 11:45:35.306523 DQS Delay:
6464 11:45:35.309237 DQS0 = 48, DQS1 = 56
6465 11:45:35.309342 DQM Delay:
6466 11:45:35.309480 DQM0 = 11, DQM1 = 8
6467 11:45:35.312592 DQ Delay:
6468 11:45:35.316030 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6469 11:45:35.319296 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6470 11:45:35.319379 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6471 11:45:35.325771 DQ12 =12, DQ13 =12, DQ14 =16, DQ15 =16
6472 11:45:35.325852
6473 11:45:35.325915
6474 11:45:35.332873 [DQSOSCAuto] RK0, (LSB)MR18= 0xbb7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6475 11:45:35.336182 CH0 RK0: MR19=C0C, MR18=BB7E
6476 11:45:35.342287 CH0_RK0: MR19=0xC0C, MR18=0xBB7E, DQSOSC=386, MR23=63, INC=396, DEC=264
6477 11:45:35.342367 ==
6478 11:45:35.345347 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 11:45:35.348763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:45:35.348846 ==
6481 11:45:35.352241 [Gating] SW mode calibration
6482 11:45:35.358635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6483 11:45:35.365250 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6484 11:45:35.368882 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 11:45:35.371849 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 11:45:35.378931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 11:45:35.381566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 11:45:35.385061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 11:45:35.392334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 11:45:35.395023 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 11:45:35.398420 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 11:45:35.405007 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 11:45:35.408896 Total UI for P1: 0, mck2ui 16
6494 11:45:35.411419 best dqsien dly found for B0: ( 0, 14, 24)
6495 11:45:35.414698 Total UI for P1: 0, mck2ui 16
6496 11:45:35.417983 best dqsien dly found for B1: ( 0, 14, 24)
6497 11:45:35.421917 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6498 11:45:35.425058 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6499 11:45:35.425136
6500 11:45:35.427978 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 11:45:35.431719 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 11:45:35.434868 [Gating] SW calibration Done
6503 11:45:35.434944 ==
6504 11:45:35.437769 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 11:45:35.441199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 11:45:35.441275 ==
6507 11:45:35.444506 RX Vref Scan: 0
6508 11:45:35.444583
6509 11:45:35.448410 RX Vref 0 -> 0, step: 1
6510 11:45:35.448490
6511 11:45:35.448601 RX Delay -410 -> 252, step: 16
6512 11:45:35.454797 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6513 11:45:35.458547 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6514 11:45:35.461241 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6515 11:45:35.468110 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6516 11:45:35.471187 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6517 11:45:35.474551 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6518 11:45:35.477652 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6519 11:45:35.484588 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6520 11:45:35.488044 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6521 11:45:35.491274 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6522 11:45:35.494032 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6523 11:45:35.501203 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6524 11:45:35.503945 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6525 11:45:35.507631 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6526 11:45:35.510868 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6527 11:45:35.517169 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6528 11:45:35.517249 ==
6529 11:45:35.520710 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 11:45:35.524316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 11:45:35.524396 ==
6532 11:45:35.524459 DQS Delay:
6533 11:45:35.527234 DQS0 = 43, DQS1 = 59
6534 11:45:35.527310 DQM Delay:
6535 11:45:35.530239 DQM0 = 10, DQM1 = 16
6536 11:45:35.530313 DQ Delay:
6537 11:45:35.533944 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6538 11:45:35.536930 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6539 11:45:35.540224 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6540 11:45:35.543835 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6541 11:45:35.543914
6542 11:45:35.543977
6543 11:45:35.544042 ==
6544 11:45:35.547054 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 11:45:35.550263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 11:45:35.550345 ==
6547 11:45:35.553718
6548 11:45:35.553798
6549 11:45:35.553862 TX Vref Scan disable
6550 11:45:35.557008 == TX Byte 0 ==
6551 11:45:35.560412 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 11:45:35.563623 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 11:45:35.566776 == TX Byte 1 ==
6554 11:45:35.570023 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6555 11:45:35.573312 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6556 11:45:35.573441 ==
6557 11:45:35.576792 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 11:45:35.579761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 11:45:35.583173 ==
6560 11:45:35.583282
6561 11:45:35.583375
6562 11:45:35.583469 TX Vref Scan disable
6563 11:45:35.587507 == TX Byte 0 ==
6564 11:45:35.589595 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6565 11:45:35.593093 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6566 11:45:35.596629 == TX Byte 1 ==
6567 11:45:35.599922 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6568 11:45:35.603383 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6569 11:45:35.603465
6570 11:45:35.606258 [DATLAT]
6571 11:45:35.606341 Freq=400, CH0 RK1
6572 11:45:35.606406
6573 11:45:35.609697 DATLAT Default: 0xe
6574 11:45:35.609778 0, 0xFFFF, sum = 0
6575 11:45:35.612827 1, 0xFFFF, sum = 0
6576 11:45:35.612922 2, 0xFFFF, sum = 0
6577 11:45:35.616154 3, 0xFFFF, sum = 0
6578 11:45:35.616237 4, 0xFFFF, sum = 0
6579 11:45:35.619901 5, 0xFFFF, sum = 0
6580 11:45:35.619983 6, 0xFFFF, sum = 0
6581 11:45:35.622606 7, 0xFFFF, sum = 0
6582 11:45:35.622688 8, 0xFFFF, sum = 0
6583 11:45:35.626742 9, 0xFFFF, sum = 0
6584 11:45:35.626824 10, 0xFFFF, sum = 0
6585 11:45:35.629564 11, 0xFFFF, sum = 0
6586 11:45:35.632697 12, 0xFFFF, sum = 0
6587 11:45:35.632778 13, 0x0, sum = 1
6588 11:45:35.632842 14, 0x0, sum = 2
6589 11:45:35.635682 15, 0x0, sum = 3
6590 11:45:35.635765 16, 0x0, sum = 4
6591 11:45:35.639350 best_step = 14
6592 11:45:35.639421
6593 11:45:35.639481 ==
6594 11:45:35.642430 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 11:45:35.645893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 11:45:35.645974 ==
6597 11:45:35.648861 RX Vref Scan: 0
6598 11:45:35.648942
6599 11:45:35.652188 RX Vref 0 -> 0, step: 1
6600 11:45:35.652269
6601 11:45:35.652364 RX Delay -359 -> 252, step: 8
6602 11:45:35.660846 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6603 11:45:35.664269 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6604 11:45:35.667401 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6605 11:45:35.670836 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6606 11:45:35.677927 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6607 11:45:35.680829 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6608 11:45:35.684070 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6609 11:45:35.687144 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6610 11:45:35.694609 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6611 11:45:35.697235 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6612 11:45:35.700281 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6613 11:45:35.707071 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6614 11:45:35.710792 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6615 11:45:35.713869 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6616 11:45:35.717357 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6617 11:45:35.723676 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6618 11:45:35.723757 ==
6619 11:45:35.727155 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 11:45:35.730316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 11:45:35.730398 ==
6622 11:45:35.730462 DQS Delay:
6623 11:45:35.733780 DQS0 = 44, DQS1 = 56
6624 11:45:35.733860 DQM Delay:
6625 11:45:35.737045 DQM0 = 8, DQM1 = 10
6626 11:45:35.737151 DQ Delay:
6627 11:45:35.740503 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6628 11:45:35.743428 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6629 11:45:35.746913 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6630 11:45:35.749761 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6631 11:45:35.749842
6632 11:45:35.749906
6633 11:45:35.756502 [DQSOSCAuto] RK1, (LSB)MR18= 0xb53f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6634 11:45:35.760259 CH0 RK1: MR19=C0C, MR18=B53F
6635 11:45:35.766670 CH0_RK1: MR19=0xC0C, MR18=0xB53F, DQSOSC=387, MR23=63, INC=394, DEC=262
6636 11:45:35.769429 [RxdqsGatingPostProcess] freq 400
6637 11:45:35.776104 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6638 11:45:35.779388 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 11:45:35.782979 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 11:45:35.786565 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 11:45:35.789988 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 11:45:35.790071 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 11:45:35.793088 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 11:45:35.796533 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 11:45:35.799577 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 11:45:35.802863 Pre-setting of DQS Precalculation
6647 11:45:35.809715 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6648 11:45:35.809796 ==
6649 11:45:35.813092 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:45:35.815961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:45:35.816043 ==
6652 11:45:35.822389 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 11:45:35.830092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6654 11:45:35.832517 [CA 0] Center 36 (8~64) winsize 57
6655 11:45:35.832598 [CA 1] Center 36 (8~64) winsize 57
6656 11:45:35.835741 [CA 2] Center 36 (8~64) winsize 57
6657 11:45:35.839204 [CA 3] Center 36 (8~64) winsize 57
6658 11:45:35.842491 [CA 4] Center 36 (8~64) winsize 57
6659 11:45:35.845639 [CA 5] Center 36 (8~64) winsize 57
6660 11:45:35.845720
6661 11:45:35.848749 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6662 11:45:35.848830
6663 11:45:35.855584 [CATrainingPosCal] consider 1 rank data
6664 11:45:35.855665 u2DelayCellTimex100 = 270/100 ps
6665 11:45:35.862033 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:45:35.865390 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:45:35.868697 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:45:35.872423 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:45:35.875398 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 11:45:35.878673 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 11:45:35.878746
6672 11:45:35.881606 CA PerBit enable=1, Macro0, CA PI delay=36
6673 11:45:35.881677
6674 11:45:35.884984 [CBTSetCACLKResult] CA Dly = 36
6675 11:45:35.888817 CS Dly: 1 (0~32)
6676 11:45:35.888889 ==
6677 11:45:35.892216 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 11:45:35.895105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 11:45:35.895190 ==
6680 11:45:35.902249 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 11:45:35.905555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6682 11:45:35.908840 [CA 0] Center 36 (8~64) winsize 57
6683 11:45:35.912353 [CA 1] Center 36 (8~64) winsize 57
6684 11:45:35.914755 [CA 2] Center 36 (8~64) winsize 57
6685 11:45:35.918017 [CA 3] Center 36 (8~64) winsize 57
6686 11:45:35.921545 [CA 4] Center 36 (8~64) winsize 57
6687 11:45:35.925150 [CA 5] Center 36 (8~64) winsize 57
6688 11:45:35.925230
6689 11:45:35.928287 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6690 11:45:35.928367
6691 11:45:35.931557 [CATrainingPosCal] consider 2 rank data
6692 11:45:35.934459 u2DelayCellTimex100 = 270/100 ps
6693 11:45:35.938218 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:45:35.941686 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:45:35.948094 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 11:45:35.951315 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 11:45:35.954861 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 11:45:35.958251 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 11:45:35.958331
6700 11:45:35.961310 CA PerBit enable=1, Macro0, CA PI delay=36
6701 11:45:35.961462
6702 11:45:35.964889 [CBTSetCACLKResult] CA Dly = 36
6703 11:45:35.964968 CS Dly: 1 (0~32)
6704 11:45:35.965031
6705 11:45:35.968037 ----->DramcWriteLeveling(PI) begin...
6706 11:45:35.971613 ==
6707 11:45:35.974973 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 11:45:35.977993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 11:45:35.978074 ==
6710 11:45:35.981005 Write leveling (Byte 0): 40 => 8
6711 11:45:35.984494 Write leveling (Byte 1): 32 => 0
6712 11:45:35.987989 DramcWriteLeveling(PI) end<-----
6713 11:45:35.988072
6714 11:45:35.988157 ==
6715 11:45:35.991123 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 11:45:35.994327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 11:45:35.994411 ==
6718 11:45:35.998269 [Gating] SW mode calibration
6719 11:45:36.004704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6720 11:45:36.007975 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6721 11:45:36.014151 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 11:45:36.017718 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 11:45:36.021189 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 11:45:36.027357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 11:45:36.030937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 11:45:36.034372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 11:45:36.040822 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 11:45:36.044011 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 11:45:36.050251 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 11:45:36.050336 Total UI for P1: 0, mck2ui 16
6731 11:45:36.054112 best dqsien dly found for B0: ( 0, 14, 24)
6732 11:45:36.057257 Total UI for P1: 0, mck2ui 16
6733 11:45:36.060754 best dqsien dly found for B1: ( 0, 14, 24)
6734 11:45:36.066801 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6735 11:45:36.070470 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6736 11:45:36.070554
6737 11:45:36.074184 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 11:45:36.077029 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 11:45:36.080036 [Gating] SW calibration Done
6740 11:45:36.080120 ==
6741 11:45:36.083488 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 11:45:36.086948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 11:45:36.087045 ==
6744 11:45:36.090171 RX Vref Scan: 0
6745 11:45:36.090260
6746 11:45:36.090328 RX Vref 0 -> 0, step: 1
6747 11:45:36.090387
6748 11:45:36.093401 RX Delay -410 -> 252, step: 16
6749 11:45:36.099681 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6750 11:45:36.103082 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6751 11:45:36.106174 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6752 11:45:36.109856 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6753 11:45:36.116625 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6754 11:45:36.119689 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6755 11:45:36.123216 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6756 11:45:36.126037 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6757 11:45:36.132721 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6758 11:45:36.135971 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6759 11:45:36.139538 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6760 11:45:36.142668 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6761 11:45:36.149069 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6762 11:45:36.152306 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6763 11:45:36.155825 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6764 11:45:36.162595 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6765 11:45:36.162706 ==
6766 11:45:36.165648 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 11:45:36.168955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 11:45:36.169054 ==
6769 11:45:36.169156 DQS Delay:
6770 11:45:36.172466 DQS0 = 43, DQS1 = 51
6771 11:45:36.172566 DQM Delay:
6772 11:45:36.175428 DQM0 = 12, DQM1 = 15
6773 11:45:36.175531 DQ Delay:
6774 11:45:36.178882 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6775 11:45:36.182961 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6776 11:45:36.185613 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6777 11:45:36.189192 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6778 11:45:36.189290
6779 11:45:36.189381
6780 11:45:36.189517 ==
6781 11:45:36.192164 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 11:45:36.195299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:45:36.195397 ==
6784 11:45:36.195498
6785 11:45:36.195593
6786 11:45:36.198774 TX Vref Scan disable
6787 11:45:36.202142 == TX Byte 0 ==
6788 11:45:36.205648 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 11:45:36.209070 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 11:45:36.209170 == TX Byte 1 ==
6791 11:45:36.215440 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6792 11:45:36.218488 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6793 11:45:36.218582 ==
6794 11:45:36.221909 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 11:45:36.225227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 11:45:36.225334 ==
6797 11:45:36.225457
6798 11:45:36.228910
6799 11:45:36.229008 TX Vref Scan disable
6800 11:45:36.232123 == TX Byte 0 ==
6801 11:45:36.234945 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 11:45:36.238666 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 11:45:36.242177 == TX Byte 1 ==
6804 11:45:36.244997 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6805 11:45:36.248400 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6806 11:45:36.248512
6807 11:45:36.248603 [DATLAT]
6808 11:45:36.251844 Freq=400, CH1 RK0
6809 11:45:36.251951
6810 11:45:36.254973 DATLAT Default: 0xf
6811 11:45:36.255074 0, 0xFFFF, sum = 0
6812 11:45:36.258283 1, 0xFFFF, sum = 0
6813 11:45:36.258394 2, 0xFFFF, sum = 0
6814 11:45:36.261367 3, 0xFFFF, sum = 0
6815 11:45:36.261508 4, 0xFFFF, sum = 0
6816 11:45:36.265037 5, 0xFFFF, sum = 0
6817 11:45:36.265149 6, 0xFFFF, sum = 0
6818 11:45:36.268505 7, 0xFFFF, sum = 0
6819 11:45:36.268614 8, 0xFFFF, sum = 0
6820 11:45:36.271729 9, 0xFFFF, sum = 0
6821 11:45:36.271841 10, 0xFFFF, sum = 0
6822 11:45:36.274666 11, 0xFFFF, sum = 0
6823 11:45:36.274767 12, 0xFFFF, sum = 0
6824 11:45:36.278487 13, 0x0, sum = 1
6825 11:45:36.278589 14, 0x0, sum = 2
6826 11:45:36.281473 15, 0x0, sum = 3
6827 11:45:36.281569 16, 0x0, sum = 4
6828 11:45:36.284664 best_step = 14
6829 11:45:36.284759
6830 11:45:36.284859 ==
6831 11:45:36.288535 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 11:45:36.291534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 11:45:36.291618 ==
6834 11:45:36.294712 RX Vref Scan: 1
6835 11:45:36.294793
6836 11:45:36.294856 RX Vref 0 -> 0, step: 1
6837 11:45:36.294916
6838 11:45:36.297920 RX Delay -343 -> 252, step: 8
6839 11:45:36.298000
6840 11:45:36.301354 Set Vref, RX VrefLevel [Byte0]: 50
6841 11:45:36.304452 [Byte1]: 51
6842 11:45:36.309510
6843 11:45:36.309591 Final RX Vref Byte 0 = 50 to rank0
6844 11:45:36.312933 Final RX Vref Byte 1 = 51 to rank0
6845 11:45:36.315832 Final RX Vref Byte 0 = 50 to rank1
6846 11:45:36.319279 Final RX Vref Byte 1 = 51 to rank1==
6847 11:45:36.322780 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 11:45:36.329177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 11:45:36.329259 ==
6850 11:45:36.329323 DQS Delay:
6851 11:45:36.332208 DQS0 = 44, DQS1 = 56
6852 11:45:36.332315 DQM Delay:
6853 11:45:36.332407 DQM0 = 8, DQM1 = 12
6854 11:45:36.335564 DQ Delay:
6855 11:45:36.338884 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6856 11:45:36.338989 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6857 11:45:36.342035 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6858 11:45:36.345504 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6859 11:45:36.348842
6860 11:45:36.348950
6861 11:45:36.355597 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6862 11:45:36.359133 CH1 RK0: MR19=C0C, MR18=9C73
6863 11:45:36.365162 CH1_RK0: MR19=0xC0C, MR18=0x9C73, DQSOSC=390, MR23=63, INC=388, DEC=258
6864 11:45:36.365274 ==
6865 11:45:36.368996 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 11:45:36.371905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:45:36.372015 ==
6868 11:45:36.375222 [Gating] SW mode calibration
6869 11:45:36.381771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6870 11:45:36.388577 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6871 11:45:36.391683 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 11:45:36.395249 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 11:45:36.401527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 11:45:36.404784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 11:45:36.408215 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 11:45:36.414741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 11:45:36.418640 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 11:45:36.422007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 11:45:36.428125 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 11:45:36.428228 Total UI for P1: 0, mck2ui 16
6881 11:45:36.435099 best dqsien dly found for B0: ( 0, 14, 24)
6882 11:45:36.435212 Total UI for P1: 0, mck2ui 16
6883 11:45:36.441358 best dqsien dly found for B1: ( 0, 14, 24)
6884 11:45:36.445149 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6885 11:45:36.447928 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6886 11:45:36.448027
6887 11:45:36.451468 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 11:45:36.454947 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 11:45:36.458264 [Gating] SW calibration Done
6890 11:45:36.458351 ==
6891 11:45:36.461542 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 11:45:36.464597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 11:45:36.464698 ==
6894 11:45:36.467545 RX Vref Scan: 0
6895 11:45:36.467645
6896 11:45:36.467747 RX Vref 0 -> 0, step: 1
6897 11:45:36.471321
6898 11:45:36.471419 RX Delay -410 -> 252, step: 16
6899 11:45:36.477397 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6900 11:45:36.480629 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6901 11:45:36.484041 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6902 11:45:36.487402 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6903 11:45:36.494360 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6904 11:45:36.497210 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6905 11:45:36.500881 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6906 11:45:36.504004 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6907 11:45:36.510524 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6908 11:45:36.513674 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6909 11:45:36.517609 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6910 11:45:36.524475 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6911 11:45:36.527095 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6912 11:45:36.530625 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6913 11:45:36.534174 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6914 11:45:36.540350 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6915 11:45:36.540435 ==
6916 11:45:36.543567 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 11:45:36.546782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 11:45:36.546866 ==
6919 11:45:36.546952 DQS Delay:
6920 11:45:36.550098 DQS0 = 51, DQS1 = 51
6921 11:45:36.550180 DQM Delay:
6922 11:45:36.553356 DQM0 = 20, DQM1 = 13
6923 11:45:36.553469 DQ Delay:
6924 11:45:36.556966 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =24
6925 11:45:36.560415 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6926 11:45:36.563204 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6927 11:45:36.566686 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6928 11:45:36.566760
6929 11:45:36.566842
6930 11:45:36.566905 ==
6931 11:45:36.570498 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 11:45:36.573225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 11:45:36.573332 ==
6934 11:45:36.573460
6935 11:45:36.576526
6936 11:45:36.576618 TX Vref Scan disable
6937 11:45:36.579933 == TX Byte 0 ==
6938 11:45:36.583216 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 11:45:36.586693 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 11:45:36.590015 == TX Byte 1 ==
6941 11:45:36.592913 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6942 11:45:36.596181 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6943 11:45:36.596281 ==
6944 11:45:36.599663 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 11:45:36.603104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 11:45:36.606537 ==
6947 11:45:36.606620
6948 11:45:36.606705
6949 11:45:36.606784 TX Vref Scan disable
6950 11:45:36.609827 == TX Byte 0 ==
6951 11:45:36.613172 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 11:45:36.616245 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 11:45:36.619438 == TX Byte 1 ==
6954 11:45:36.623160 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6955 11:45:36.626326 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6956 11:45:36.626403
6957 11:45:36.626488 [DATLAT]
6958 11:45:36.629244 Freq=400, CH1 RK1
6959 11:45:36.629343
6960 11:45:36.632820 DATLAT Default: 0xe
6961 11:45:36.632904 0, 0xFFFF, sum = 0
6962 11:45:36.635901 1, 0xFFFF, sum = 0
6963 11:45:36.635986 2, 0xFFFF, sum = 0
6964 11:45:36.639618 3, 0xFFFF, sum = 0
6965 11:45:36.639703 4, 0xFFFF, sum = 0
6966 11:45:36.642917 5, 0xFFFF, sum = 0
6967 11:45:36.643001 6, 0xFFFF, sum = 0
6968 11:45:36.646184 7, 0xFFFF, sum = 0
6969 11:45:36.646270 8, 0xFFFF, sum = 0
6970 11:45:36.649272 9, 0xFFFF, sum = 0
6971 11:45:36.649374 10, 0xFFFF, sum = 0
6972 11:45:36.652900 11, 0xFFFF, sum = 0
6973 11:45:36.653003 12, 0xFFFF, sum = 0
6974 11:45:36.656155 13, 0x0, sum = 1
6975 11:45:36.656266 14, 0x0, sum = 2
6976 11:45:36.659098 15, 0x0, sum = 3
6977 11:45:36.659209 16, 0x0, sum = 4
6978 11:45:36.662494 best_step = 14
6979 11:45:36.662573
6980 11:45:36.662636 ==
6981 11:45:36.665988 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 11:45:36.669267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 11:45:36.669378 ==
6984 11:45:36.672391 RX Vref Scan: 0
6985 11:45:36.672497
6986 11:45:36.672586 RX Vref 0 -> 0, step: 1
6987 11:45:36.672679
6988 11:45:36.675848 RX Delay -343 -> 252, step: 8
6989 11:45:36.684004 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6990 11:45:36.687229 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6991 11:45:36.690426 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6992 11:45:36.696702 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6993 11:45:36.700125 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6994 11:45:36.703273 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6995 11:45:36.706913 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6996 11:45:36.713830 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6997 11:45:36.716814 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6998 11:45:36.719864 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6999 11:45:36.723367 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7000 11:45:36.729873 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7001 11:45:36.733279 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7002 11:45:36.736647 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7003 11:45:36.739511 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7004 11:45:36.745979 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7005 11:45:36.746059 ==
7006 11:45:36.750073 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 11:45:36.752546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 11:45:36.752644 ==
7009 11:45:36.756054 DQS Delay:
7010 11:45:36.756150 DQS0 = 44, DQS1 = 56
7011 11:45:36.756250 DQM Delay:
7012 11:45:36.759422 DQM0 = 9, DQM1 = 11
7013 11:45:36.759530 DQ Delay:
7014 11:45:36.762641 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7015 11:45:36.765925 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
7016 11:45:36.768996 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7017 11:45:36.772426 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7018 11:45:36.772528
7019 11:45:36.772629
7020 11:45:36.782550 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 395 ps
7021 11:45:36.782656 CH1 RK1: MR19=C0C, MR18=6F5D
7022 11:45:36.789253 CH1_RK1: MR19=0xC0C, MR18=0x6F5D, DQSOSC=395, MR23=63, INC=378, DEC=252
7023 11:45:36.792269 [RxdqsGatingPostProcess] freq 400
7024 11:45:36.799378 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7025 11:45:36.802242 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 11:45:36.805299 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 11:45:36.808498 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 11:45:36.812208 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 11:45:36.815250 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 11:45:36.815351 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 11:45:36.818451 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 11:45:36.822193 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 11:45:36.825326 Pre-setting of DQS Precalculation
7034 11:45:36.831694 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7035 11:45:36.838221 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7036 11:45:36.844862 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7037 11:45:36.844986
7038 11:45:36.845093
7039 11:45:36.848141 [Calibration Summary] 800 Mbps
7040 11:45:36.851633 CH 0, Rank 0
7041 11:45:36.851737 SW Impedance : PASS
7042 11:45:36.854955 DUTY Scan : NO K
7043 11:45:36.858119 ZQ Calibration : PASS
7044 11:45:36.858224 Jitter Meter : NO K
7045 11:45:36.861343 CBT Training : PASS
7046 11:45:36.861479 Write leveling : PASS
7047 11:45:36.864515 RX DQS gating : PASS
7048 11:45:36.868244 RX DQ/DQS(RDDQC) : PASS
7049 11:45:36.868354 TX DQ/DQS : PASS
7050 11:45:36.871579 RX DATLAT : PASS
7051 11:45:36.874380 RX DQ/DQS(Engine): PASS
7052 11:45:36.874493 TX OE : NO K
7053 11:45:36.877783 All Pass.
7054 11:45:36.877885
7055 11:45:36.877948 CH 0, Rank 1
7056 11:45:36.881292 SW Impedance : PASS
7057 11:45:36.881388 DUTY Scan : NO K
7058 11:45:36.884776 ZQ Calibration : PASS
7059 11:45:36.887936 Jitter Meter : NO K
7060 11:45:36.888036 CBT Training : PASS
7061 11:45:36.891055 Write leveling : NO K
7062 11:45:36.894430 RX DQS gating : PASS
7063 11:45:36.894532 RX DQ/DQS(RDDQC) : PASS
7064 11:45:36.898021 TX DQ/DQS : PASS
7065 11:45:36.900879 RX DATLAT : PASS
7066 11:45:36.900977 RX DQ/DQS(Engine): PASS
7067 11:45:36.903974 TX OE : NO K
7068 11:45:36.904075 All Pass.
7069 11:45:36.904213
7070 11:45:36.907314 CH 1, Rank 0
7071 11:45:36.907417 SW Impedance : PASS
7072 11:45:36.910878 DUTY Scan : NO K
7073 11:45:36.914234 ZQ Calibration : PASS
7074 11:45:36.914317 Jitter Meter : NO K
7075 11:45:36.917790 CBT Training : PASS
7076 11:45:36.920719 Write leveling : PASS
7077 11:45:36.920822 RX DQS gating : PASS
7078 11:45:36.924008 RX DQ/DQS(RDDQC) : PASS
7079 11:45:36.926806 TX DQ/DQS : PASS
7080 11:45:36.926905 RX DATLAT : PASS
7081 11:45:36.930805 RX DQ/DQS(Engine): PASS
7082 11:45:36.933773 TX OE : NO K
7083 11:45:36.933872 All Pass.
7084 11:45:36.933972
7085 11:45:36.934060 CH 1, Rank 1
7086 11:45:36.936968 SW Impedance : PASS
7087 11:45:36.940007 DUTY Scan : NO K
7088 11:45:36.940103 ZQ Calibration : PASS
7089 11:45:36.943416 Jitter Meter : NO K
7090 11:45:36.946831 CBT Training : PASS
7091 11:45:36.946935 Write leveling : NO K
7092 11:45:36.949796 RX DQS gating : PASS
7093 11:45:36.953598 RX DQ/DQS(RDDQC) : PASS
7094 11:45:36.953703 TX DQ/DQS : PASS
7095 11:45:36.956726 RX DATLAT : PASS
7096 11:45:36.959967 RX DQ/DQS(Engine): PASS
7097 11:45:36.960079 TX OE : NO K
7098 11:45:36.960171 All Pass.
7099 11:45:36.963270
7100 11:45:36.963360 DramC Write-DBI off
7101 11:45:36.966496 PER_BANK_REFRESH: Hybrid Mode
7102 11:45:36.966592 TX_TRACKING: ON
7103 11:45:36.976075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7104 11:45:36.979734 [FAST_K] Save calibration result to emmc
7105 11:45:36.982953 dramc_set_vcore_voltage set vcore to 725000
7106 11:45:36.986492 Read voltage for 1600, 0
7107 11:45:36.986579 Vio18 = 0
7108 11:45:36.989271 Vcore = 725000
7109 11:45:36.989370 Vdram = 0
7110 11:45:36.989506 Vddq = 0
7111 11:45:36.992578 Vmddr = 0
7112 11:45:36.995981 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7113 11:45:37.002697 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7114 11:45:37.002781 MEM_TYPE=3, freq_sel=13
7115 11:45:37.006112 sv_algorithm_assistance_LP4_3733
7116 11:45:37.012731 ============ PULL DRAM RESETB DOWN ============
7117 11:45:37.016061 ========== PULL DRAM RESETB DOWN end =========
7118 11:45:37.018963 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7119 11:45:37.022820 ===================================
7120 11:45:37.025882 LPDDR4 DRAM CONFIGURATION
7121 11:45:37.028936 ===================================
7122 11:45:37.032147 EX_ROW_EN[0] = 0x0
7123 11:45:37.032231 EX_ROW_EN[1] = 0x0
7124 11:45:37.035698 LP4Y_EN = 0x0
7125 11:45:37.035781 WORK_FSP = 0x1
7126 11:45:37.038826 WL = 0x5
7127 11:45:37.038909 RL = 0x5
7128 11:45:37.042367 BL = 0x2
7129 11:45:37.042482 RPST = 0x0
7130 11:45:37.045213 RD_PRE = 0x0
7131 11:45:37.045296 WR_PRE = 0x1
7132 11:45:37.048737 WR_PST = 0x1
7133 11:45:37.048820 DBI_WR = 0x0
7134 11:45:37.052004 DBI_RD = 0x0
7135 11:45:37.052087 OTF = 0x1
7136 11:45:37.055326 ===================================
7137 11:45:37.058636 ===================================
7138 11:45:37.061966 ANA top config
7139 11:45:37.065519 ===================================
7140 11:45:37.068570 DLL_ASYNC_EN = 0
7141 11:45:37.068654 ALL_SLAVE_EN = 0
7142 11:45:37.072107 NEW_RANK_MODE = 1
7143 11:45:37.075059 DLL_IDLE_MODE = 1
7144 11:45:37.078481 LP45_APHY_COMB_EN = 1
7145 11:45:37.078588 TX_ODT_DIS = 0
7146 11:45:37.081862 NEW_8X_MODE = 1
7147 11:45:37.085197 ===================================
7148 11:45:37.088353 ===================================
7149 11:45:37.091489 data_rate = 3200
7150 11:45:37.094849 CKR = 1
7151 11:45:37.098156 DQ_P2S_RATIO = 8
7152 11:45:37.101790 ===================================
7153 11:45:37.105281 CA_P2S_RATIO = 8
7154 11:45:37.105365 DQ_CA_OPEN = 0
7155 11:45:37.108283 DQ_SEMI_OPEN = 0
7156 11:45:37.111670 CA_SEMI_OPEN = 0
7157 11:45:37.114856 CA_FULL_RATE = 0
7158 11:45:37.118645 DQ_CKDIV4_EN = 0
7159 11:45:37.121631 CA_CKDIV4_EN = 0
7160 11:45:37.121716 CA_PREDIV_EN = 0
7161 11:45:37.125223 PH8_DLY = 12
7162 11:45:37.128364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7163 11:45:37.131111 DQ_AAMCK_DIV = 4
7164 11:45:37.134880 CA_AAMCK_DIV = 4
7165 11:45:37.138025 CA_ADMCK_DIV = 4
7166 11:45:37.141162 DQ_TRACK_CA_EN = 0
7167 11:45:37.141245 CA_PICK = 1600
7168 11:45:37.144415 CA_MCKIO = 1600
7169 11:45:37.147856 MCKIO_SEMI = 0
7170 11:45:37.150718 PLL_FREQ = 3068
7171 11:45:37.154263 DQ_UI_PI_RATIO = 32
7172 11:45:37.157451 CA_UI_PI_RATIO = 0
7173 11:45:37.160669 ===================================
7174 11:45:37.164207 ===================================
7175 11:45:37.167153 memory_type:LPDDR4
7176 11:45:37.167268 GP_NUM : 10
7177 11:45:37.170575 SRAM_EN : 1
7178 11:45:37.170673 MD32_EN : 0
7179 11:45:37.173772 ===================================
7180 11:45:37.176956 [ANA_INIT] >>>>>>>>>>>>>>
7181 11:45:37.180459 <<<<<< [CONFIGURE PHASE]: ANA_TX
7182 11:45:37.183866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7183 11:45:37.186990 ===================================
7184 11:45:37.190618 data_rate = 3200,PCW = 0X7600
7185 11:45:37.193570 ===================================
7186 11:45:37.196800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7187 11:45:37.203454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 11:45:37.207278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 11:45:37.213586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7190 11:45:37.216795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7191 11:45:37.220051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7192 11:45:37.220150 [ANA_INIT] flow start
7193 11:45:37.223762 [ANA_INIT] PLL >>>>>>>>
7194 11:45:37.226693 [ANA_INIT] PLL <<<<<<<<
7195 11:45:37.230038 [ANA_INIT] MIDPI >>>>>>>>
7196 11:45:37.230134 [ANA_INIT] MIDPI <<<<<<<<
7197 11:45:37.233025 [ANA_INIT] DLL >>>>>>>>
7198 11:45:37.236585 [ANA_INIT] DLL <<<<<<<<
7199 11:45:37.236684 [ANA_INIT] flow end
7200 11:45:37.239637 ============ LP4 DIFF to SE enter ============
7201 11:45:37.246422 ============ LP4 DIFF to SE exit ============
7202 11:45:37.246529 [ANA_INIT] <<<<<<<<<<<<<
7203 11:45:37.249763 [Flow] Enable top DCM control >>>>>
7204 11:45:37.253225 [Flow] Enable top DCM control <<<<<
7205 11:45:37.256646 Enable DLL master slave shuffle
7206 11:45:37.262895 ==============================================================
7207 11:45:37.263001 Gating Mode config
7208 11:45:37.269798 ==============================================================
7209 11:45:37.273372 Config description:
7210 11:45:37.282573 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7211 11:45:37.289107 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7212 11:45:37.292513 SELPH_MODE 0: By rank 1: By Phase
7213 11:45:37.299384 ==============================================================
7214 11:45:37.302224 GAT_TRACK_EN = 1
7215 11:45:37.305579 RX_GATING_MODE = 2
7216 11:45:37.309064 RX_GATING_TRACK_MODE = 2
7217 11:45:37.309164 SELPH_MODE = 1
7218 11:45:37.312830 PICG_EARLY_EN = 1
7219 11:45:37.315766 VALID_LAT_VALUE = 1
7220 11:45:37.322723 ==============================================================
7221 11:45:37.325523 Enter into Gating configuration >>>>
7222 11:45:37.328587 Exit from Gating configuration <<<<
7223 11:45:37.331962 Enter into DVFS_PRE_config >>>>>
7224 11:45:37.341888 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7225 11:45:37.345234 Exit from DVFS_PRE_config <<<<<
7226 11:45:37.348894 Enter into PICG configuration >>>>
7227 11:45:37.352232 Exit from PICG configuration <<<<
7228 11:45:37.355669 [RX_INPUT] configuration >>>>>
7229 11:45:37.358853 [RX_INPUT] configuration <<<<<
7230 11:45:37.361795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7231 11:45:37.368420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7232 11:45:37.374901 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 11:45:37.382061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 11:45:37.388192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 11:45:37.395197 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 11:45:37.398257 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7237 11:45:37.401628 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7238 11:45:37.404896 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7239 11:45:37.408091 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7240 11:45:37.414860 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7241 11:45:37.418160 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 11:45:37.421402 ===================================
7243 11:45:37.425003 LPDDR4 DRAM CONFIGURATION
7244 11:45:37.428562 ===================================
7245 11:45:37.428690 EX_ROW_EN[0] = 0x0
7246 11:45:37.431572 EX_ROW_EN[1] = 0x0
7247 11:45:37.431673 LP4Y_EN = 0x0
7248 11:45:37.434734 WORK_FSP = 0x1
7249 11:45:37.434833 WL = 0x5
7250 11:45:37.438606 RL = 0x5
7251 11:45:37.438705 BL = 0x2
7252 11:45:37.441834 RPST = 0x0
7253 11:45:37.444686 RD_PRE = 0x0
7254 11:45:37.444784 WR_PRE = 0x1
7255 11:45:37.447960 WR_PST = 0x1
7256 11:45:37.448060 DBI_WR = 0x0
7257 11:45:37.451213 DBI_RD = 0x0
7258 11:45:37.451331 OTF = 0x1
7259 11:45:37.454916 ===================================
7260 11:45:37.458097 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7261 11:45:37.464548 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7262 11:45:37.467883 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 11:45:37.471064 ===================================
7264 11:45:37.474503 LPDDR4 DRAM CONFIGURATION
7265 11:45:37.477663 ===================================
7266 11:45:37.477746 EX_ROW_EN[0] = 0x10
7267 11:45:37.480982 EX_ROW_EN[1] = 0x0
7268 11:45:37.481065 LP4Y_EN = 0x0
7269 11:45:37.484248 WORK_FSP = 0x1
7270 11:45:37.484332 WL = 0x5
7271 11:45:37.487601 RL = 0x5
7272 11:45:37.487723 BL = 0x2
7273 11:45:37.490764 RPST = 0x0
7274 11:45:37.494136 RD_PRE = 0x0
7275 11:45:37.494220 WR_PRE = 0x1
7276 11:45:37.497700 WR_PST = 0x1
7277 11:45:37.497783 DBI_WR = 0x0
7278 11:45:37.501008 DBI_RD = 0x0
7279 11:45:37.501091 OTF = 0x1
7280 11:45:37.503948 ===================================
7281 11:45:37.510582 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7282 11:45:37.510688 ==
7283 11:45:37.514060 Dram Type= 6, Freq= 0, CH_0, rank 0
7284 11:45:37.517331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 11:45:37.517463 ==
7286 11:45:37.520603 [Duty_Offset_Calibration]
7287 11:45:37.523759 B0:1 B1:-1 CA:0
7288 11:45:37.523869
7289 11:45:37.526959 [DutyScan_Calibration_Flow] k_type=0
7290 11:45:37.535616
7291 11:45:37.535725 ==CLK 0==
7292 11:45:37.538965 Final CLK duty delay cell = 0
7293 11:45:37.542760 [0] MAX Duty = 5125%(X100), DQS PI = 20
7294 11:45:37.545833 [0] MIN Duty = 4907%(X100), DQS PI = 6
7295 11:45:37.545935 [0] AVG Duty = 5016%(X100)
7296 11:45:37.548769
7297 11:45:37.552077 CH0 CLK Duty spec in!! Max-Min= 218%
7298 11:45:37.555981 [DutyScan_Calibration_Flow] ====Done====
7299 11:45:37.556084
7300 11:45:37.559350 [DutyScan_Calibration_Flow] k_type=1
7301 11:45:37.574667
7302 11:45:37.574769 ==DQS 0 ==
7303 11:45:37.578415 Final DQS duty delay cell = -4
7304 11:45:37.581424 [-4] MAX Duty = 5000%(X100), DQS PI = 36
7305 11:45:37.584692 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7306 11:45:37.588727 [-4] AVG Duty = 4922%(X100)
7307 11:45:37.588830
7308 11:45:37.588934 ==DQS 1 ==
7309 11:45:37.591430 Final DQS duty delay cell = 0
7310 11:45:37.594903 [0] MAX Duty = 5156%(X100), DQS PI = 2
7311 11:45:37.598400 [0] MIN Duty = 5031%(X100), DQS PI = 18
7312 11:45:37.601427 [0] AVG Duty = 5093%(X100)
7313 11:45:37.601540
7314 11:45:37.604818 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7315 11:45:37.604925
7316 11:45:37.608435 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7317 11:45:37.611517 [DutyScan_Calibration_Flow] ====Done====
7318 11:45:37.611597
7319 11:45:37.614948 [DutyScan_Calibration_Flow] k_type=3
7320 11:45:37.632346
7321 11:45:37.632459 ==DQM 0 ==
7322 11:45:37.635385 Final DQM duty delay cell = 0
7323 11:45:37.638830 [0] MAX Duty = 5125%(X100), DQS PI = 22
7324 11:45:37.642003 [0] MIN Duty = 4876%(X100), DQS PI = 10
7325 11:45:37.645561 [0] AVG Duty = 5000%(X100)
7326 11:45:37.645663
7327 11:45:37.645753 ==DQM 1 ==
7328 11:45:37.648436 Final DQM duty delay cell = 0
7329 11:45:37.651836 [0] MAX Duty = 5031%(X100), DQS PI = 52
7330 11:45:37.655315 [0] MIN Duty = 4813%(X100), DQS PI = 20
7331 11:45:37.658764 [0] AVG Duty = 4922%(X100)
7332 11:45:37.658865
7333 11:45:37.661782 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7334 11:45:37.661880
7335 11:45:37.665269 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7336 11:45:37.668358 [DutyScan_Calibration_Flow] ====Done====
7337 11:45:37.668455
7338 11:45:37.672153 [DutyScan_Calibration_Flow] k_type=2
7339 11:45:37.687771
7340 11:45:37.687883 ==DQ 0 ==
7341 11:45:37.690938 Final DQ duty delay cell = -4
7342 11:45:37.694298 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7343 11:45:37.698374 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7344 11:45:37.700992 [-4] AVG Duty = 4953%(X100)
7345 11:45:37.701089
7346 11:45:37.701180 ==DQ 1 ==
7347 11:45:37.704415 Final DQ duty delay cell = -4
7348 11:45:37.707631 [-4] MAX Duty = 4969%(X100), DQS PI = 50
7349 11:45:37.710793 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7350 11:45:37.714930 [-4] AVG Duty = 4922%(X100)
7351 11:45:37.715032
7352 11:45:37.717374 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7353 11:45:37.717505
7354 11:45:37.720861 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7355 11:45:37.724284 [DutyScan_Calibration_Flow] ====Done====
7356 11:45:37.724362 ==
7357 11:45:37.727677 Dram Type= 6, Freq= 0, CH_1, rank 0
7358 11:45:37.730996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7359 11:45:37.731093 ==
7360 11:45:37.733985 [Duty_Offset_Calibration]
7361 11:45:37.737137 B0:-1 B1:1 CA:2
7362 11:45:37.737236
7363 11:45:37.740318 [DutyScan_Calibration_Flow] k_type=0
7364 11:45:37.748887
7365 11:45:37.748989 ==CLK 0==
7366 11:45:37.752426 Final CLK duty delay cell = 0
7367 11:45:37.755345 [0] MAX Duty = 5156%(X100), DQS PI = 20
7368 11:45:37.758449 [0] MIN Duty = 5062%(X100), DQS PI = 0
7369 11:45:37.761758 [0] AVG Duty = 5109%(X100)
7370 11:45:37.761833
7371 11:45:37.765235 CH1 CLK Duty spec in!! Max-Min= 94%
7372 11:45:37.768276 [DutyScan_Calibration_Flow] ====Done====
7373 11:45:37.768374
7374 11:45:37.771683 [DutyScan_Calibration_Flow] k_type=1
7375 11:45:37.788212
7376 11:45:37.788318 ==DQS 0 ==
7377 11:45:37.792096 Final DQS duty delay cell = 0
7378 11:45:37.794864 [0] MAX Duty = 5156%(X100), DQS PI = 22
7379 11:45:37.798716 [0] MIN Duty = 4907%(X100), DQS PI = 40
7380 11:45:37.802070 [0] AVG Duty = 5031%(X100)
7381 11:45:37.802171
7382 11:45:37.802261 ==DQS 1 ==
7383 11:45:37.804768 Final DQS duty delay cell = 0
7384 11:45:37.807971 [0] MAX Duty = 5125%(X100), DQS PI = 40
7385 11:45:37.811347 [0] MIN Duty = 5000%(X100), DQS PI = 22
7386 11:45:37.814882 [0] AVG Duty = 5062%(X100)
7387 11:45:37.814994
7388 11:45:37.818413 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7389 11:45:37.818521
7390 11:45:37.821634 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7391 11:45:37.825273 [DutyScan_Calibration_Flow] ====Done====
7392 11:45:37.825377
7393 11:45:37.827863 [DutyScan_Calibration_Flow] k_type=3
7394 11:45:37.845229
7395 11:45:37.845315 ==DQM 0 ==
7396 11:45:37.848787 Final DQM duty delay cell = 0
7397 11:45:37.852772 [0] MAX Duty = 5187%(X100), DQS PI = 2
7398 11:45:37.855309 [0] MIN Duty = 5000%(X100), DQS PI = 40
7399 11:45:37.858739 [0] AVG Duty = 5093%(X100)
7400 11:45:37.858843
7401 11:45:37.858944 ==DQM 1 ==
7402 11:45:37.861921 Final DQM duty delay cell = 0
7403 11:45:37.865685 [0] MAX Duty = 5187%(X100), DQS PI = 34
7404 11:45:37.868609 [0] MIN Duty = 5000%(X100), DQS PI = 0
7405 11:45:37.871895 [0] AVG Duty = 5093%(X100)
7406 11:45:37.872004
7407 11:45:37.875200 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7408 11:45:37.875308
7409 11:45:37.878230 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7410 11:45:37.882007 [DutyScan_Calibration_Flow] ====Done====
7411 11:45:37.882114
7412 11:45:37.885226 [DutyScan_Calibration_Flow] k_type=2
7413 11:45:37.902144
7414 11:45:37.902261 ==DQ 0 ==
7415 11:45:37.905947 Final DQ duty delay cell = 0
7416 11:45:37.909260 [0] MAX Duty = 5156%(X100), DQS PI = 0
7417 11:45:37.912150 [0] MIN Duty = 4906%(X100), DQS PI = 40
7418 11:45:37.912357 [0] AVG Duty = 5031%(X100)
7419 11:45:37.915144
7420 11:45:37.915271 ==DQ 1 ==
7421 11:45:37.918872 Final DQ duty delay cell = 0
7422 11:45:37.922438 [0] MAX Duty = 5156%(X100), DQS PI = 42
7423 11:45:37.925500 [0] MIN Duty = 4969%(X100), DQS PI = 28
7424 11:45:37.925596 [0] AVG Duty = 5062%(X100)
7425 11:45:37.925733
7426 11:45:37.929058 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7427 11:45:37.932210
7428 11:45:37.935100 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7429 11:45:37.938964 [DutyScan_Calibration_Flow] ====Done====
7430 11:45:37.941862 nWR fixed to 30
7431 11:45:37.941947 [ModeRegInit_LP4] CH0 RK0
7432 11:45:37.945238 [ModeRegInit_LP4] CH0 RK1
7433 11:45:37.948284 [ModeRegInit_LP4] CH1 RK0
7434 11:45:37.951713 [ModeRegInit_LP4] CH1 RK1
7435 11:45:37.951818 match AC timing 5
7436 11:45:37.958081 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7437 11:45:37.962052 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7438 11:45:37.965226 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7439 11:45:37.972134 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7440 11:45:37.974687 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7441 11:45:37.974763 [MiockJmeterHQA]
7442 11:45:37.974825
7443 11:45:37.977894 [DramcMiockJmeter] u1RxGatingPI = 0
7444 11:45:37.981245 0 : 4363, 4137
7445 11:45:37.981347 4 : 4253, 4026
7446 11:45:37.984828 8 : 4253, 4026
7447 11:45:37.984927 12 : 4255, 4029
7448 11:45:37.987723 16 : 4252, 4026
7449 11:45:37.987829 20 : 4363, 4138
7450 11:45:37.987923 24 : 4363, 4137
7451 11:45:37.991728 28 : 4252, 4027
7452 11:45:37.991826 32 : 4253, 4027
7453 11:45:37.994822 36 : 4252, 4027
7454 11:45:37.994929 40 : 4253, 4027
7455 11:45:37.998054 44 : 4253, 4026
7456 11:45:37.998130 48 : 4363, 4138
7457 11:45:38.001338 52 : 4252, 4027
7458 11:45:38.001461 56 : 4252, 4027
7459 11:45:38.001555 60 : 4253, 4027
7460 11:45:38.004460 64 : 4252, 4026
7461 11:45:38.004558 68 : 4250, 4027
7462 11:45:38.007632 72 : 4361, 4137
7463 11:45:38.007733 76 : 4361, 4137
7464 11:45:38.011226 80 : 4250, 4026
7465 11:45:38.011326 84 : 4250, 4027
7466 11:45:38.014375 88 : 4250, 4026
7467 11:45:38.014479 92 : 4250, 341
7468 11:45:38.014570 96 : 4250, 0
7469 11:45:38.017724 100 : 4252, 0
7470 11:45:38.017827 104 : 4360, 0
7471 11:45:38.017923 108 : 4250, 0
7472 11:45:38.020543 112 : 4250, 0
7473 11:45:38.020646 116 : 4250, 0
7474 11:45:38.024318 120 : 4361, 0
7475 11:45:38.024447 124 : 4360, 0
7476 11:45:38.024565 128 : 4250, 0
7477 11:45:38.027615 132 : 4250, 0
7478 11:45:38.027699 136 : 4250, 0
7479 11:45:38.030807 140 : 4252, 0
7480 11:45:38.030888 144 : 4250, 0
7481 11:45:38.030985 148 : 4250, 0
7482 11:45:38.034398 152 : 4252, 0
7483 11:45:38.034480 156 : 4363, 0
7484 11:45:38.037358 160 : 4250, 0
7485 11:45:38.037495 164 : 4250, 0
7486 11:45:38.037590 168 : 4250, 0
7487 11:45:38.040574 172 : 4361, 0
7488 11:45:38.040656 176 : 4360, 0
7489 11:45:38.044163 180 : 4250, 0
7490 11:45:38.044245 184 : 4250, 0
7491 11:45:38.044310 188 : 4250, 0
7492 11:45:38.047592 192 : 4252, 0
7493 11:45:38.047674 196 : 4250, 0
7494 11:45:38.047739 200 : 4250, 0
7495 11:45:38.050424 204 : 4252, 0
7496 11:45:38.050533 208 : 4361, 0
7497 11:45:38.053690 212 : 4250, 0
7498 11:45:38.053799 216 : 4250, 0
7499 11:45:38.053894 220 : 4250, 0
7500 11:45:38.056915 224 : 4361, 411
7501 11:45:38.056997 228 : 4250, 3429
7502 11:45:38.060146 232 : 4361, 4137
7503 11:45:38.060256 236 : 4250, 4027
7504 11:45:38.063825 240 : 4250, 4026
7505 11:45:38.063928 244 : 4250, 4027
7506 11:45:38.066870 248 : 4250, 4026
7507 11:45:38.066969 252 : 4250, 4027
7508 11:45:38.070484 256 : 4250, 4027
7509 11:45:38.070567 260 : 4361, 4137
7510 11:45:38.073654 264 : 4250, 4026
7511 11:45:38.073762 268 : 4250, 4027
7512 11:45:38.076934 272 : 4360, 4137
7513 11:45:38.077016 276 : 4250, 4027
7514 11:45:38.077081 280 : 4250, 4027
7515 11:45:38.080042 284 : 4361, 4137
7516 11:45:38.080153 288 : 4250, 4027
7517 11:45:38.083715 292 : 4250, 4026
7518 11:45:38.083850 296 : 4252, 4027
7519 11:45:38.086855 300 : 4250, 4026
7520 11:45:38.086938 304 : 4250, 4027
7521 11:45:38.090363 308 : 4250, 4026
7522 11:45:38.090446 312 : 4361, 4137
7523 11:45:38.093149 316 : 4250, 4026
7524 11:45:38.093301 320 : 4250, 4027
7525 11:45:38.096689 324 : 4360, 4138
7526 11:45:38.096797 328 : 4250, 4026
7527 11:45:38.100138 332 : 4250, 4027
7528 11:45:38.100219 336 : 4361, 3931
7529 11:45:38.103185 340 : 4250, 2361
7530 11:45:38.103267 344 : 4250, 12
7531 11:45:38.103332
7532 11:45:38.106927 MIOCK jitter meter ch=0
7533 11:45:38.107007
7534 11:45:38.109781 1T = (344-92) = 252 dly cells
7535 11:45:38.113146 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7536 11:45:38.113227 ==
7537 11:45:38.116456 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 11:45:38.123333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 11:45:38.123414 ==
7540 11:45:38.126311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 11:45:38.132977 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 11:45:38.136166 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 11:45:38.142631 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 11:45:38.150871 [CA 0] Center 43 (12~74) winsize 63
7545 11:45:38.154558 [CA 1] Center 42 (12~73) winsize 62
7546 11:45:38.157450 [CA 2] Center 38 (9~68) winsize 60
7547 11:45:38.160732 [CA 3] Center 38 (8~68) winsize 61
7548 11:45:38.164060 [CA 4] Center 36 (7~66) winsize 60
7549 11:45:38.167399 [CA 5] Center 35 (6~65) winsize 60
7550 11:45:38.167503
7551 11:45:38.170407 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 11:45:38.170508
7553 11:45:38.174105 [CATrainingPosCal] consider 1 rank data
7554 11:45:38.177157 u2DelayCellTimex100 = 258/100 ps
7555 11:45:38.184114 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7556 11:45:38.186967 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7557 11:45:38.190306 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7558 11:45:38.193369 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7559 11:45:38.196784 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7560 11:45:38.200339 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7561 11:45:38.200445
7562 11:45:38.203857 CA PerBit enable=1, Macro0, CA PI delay=35
7563 11:45:38.203961
7564 11:45:38.206776 [CBTSetCACLKResult] CA Dly = 35
7565 11:45:38.210242 CS Dly: 12 (0~43)
7566 11:45:38.213787 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 11:45:38.216621 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 11:45:38.216695 ==
7569 11:45:38.219980 Dram Type= 6, Freq= 0, CH_0, rank 1
7570 11:45:38.226724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 11:45:38.226806 ==
7572 11:45:38.229855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7573 11:45:38.236713 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7574 11:45:38.239797 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7575 11:45:38.246094 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7576 11:45:38.254018 [CA 0] Center 43 (13~74) winsize 62
7577 11:45:38.257540 [CA 1] Center 44 (14~74) winsize 61
7578 11:45:38.261105 [CA 2] Center 38 (9~68) winsize 60
7579 11:45:38.264235 [CA 3] Center 38 (9~68) winsize 60
7580 11:45:38.267477 [CA 4] Center 36 (7~66) winsize 60
7581 11:45:38.270650 [CA 5] Center 36 (6~66) winsize 61
7582 11:45:38.270732
7583 11:45:38.274399 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7584 11:45:38.274480
7585 11:45:38.277620 [CATrainingPosCal] consider 2 rank data
7586 11:45:38.280762 u2DelayCellTimex100 = 258/100 ps
7587 11:45:38.287408 CA0 delay=43 (13~74),Diff = 8 PI (30 cell)
7588 11:45:38.290502 CA1 delay=43 (14~73),Diff = 8 PI (30 cell)
7589 11:45:38.293672 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7590 11:45:38.296936 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7591 11:45:38.300275 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7592 11:45:38.304065 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7593 11:45:38.304146
7594 11:45:38.307158 CA PerBit enable=1, Macro0, CA PI delay=35
7595 11:45:38.307265
7596 11:45:38.310190 [CBTSetCACLKResult] CA Dly = 35
7597 11:45:38.313258 CS Dly: 12 (0~43)
7598 11:45:38.316831 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7599 11:45:38.320047 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7600 11:45:38.320128
7601 11:45:38.323422 ----->DramcWriteLeveling(PI) begin...
7602 11:45:38.326694 ==
7603 11:45:38.326776 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 11:45:38.333102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 11:45:38.333183 ==
7606 11:45:38.336667 Write leveling (Byte 0): 37 => 37
7607 11:45:38.339780 Write leveling (Byte 1): 28 => 28
7608 11:45:38.343519 DramcWriteLeveling(PI) end<-----
7609 11:45:38.343600
7610 11:45:38.343664 ==
7611 11:45:38.346170 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 11:45:38.349836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 11:45:38.349917 ==
7614 11:45:38.352759 [Gating] SW mode calibration
7615 11:45:38.359449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7616 11:45:38.366490 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7617 11:45:38.369075 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 11:45:38.372440 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 11:45:38.379161 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 11:45:38.382346 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7621 11:45:38.386019 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7622 11:45:38.392588 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7623 11:45:38.395736 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 11:45:38.399045 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 11:45:38.405686 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 11:45:38.408797 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 11:45:38.412186 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7628 11:45:38.418537 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7629 11:45:38.421928 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7630 11:45:38.425311 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7631 11:45:38.431789 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7632 11:45:38.434940 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 11:45:38.438556 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 11:45:38.445116 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 11:45:38.448262 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 11:45:38.451897 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7637 11:45:38.457890 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7638 11:45:38.461321 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7639 11:45:38.464810 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7640 11:45:38.471657 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 11:45:38.474977 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 11:45:38.477867 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 11:45:38.484464 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 11:45:38.487865 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 11:45:38.491105 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7646 11:45:38.497819 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 11:45:38.501010 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:45:38.504039 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:45:38.510675 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:45:38.514423 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:45:38.517565 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:45:38.524003 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:45:38.527446 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:45:38.530542 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:45:38.537050 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:45:38.540378 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:45:38.543683 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:45:38.550472 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:45:38.553654 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 11:45:38.556822 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 11:45:38.563304 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7662 11:45:38.563384 Total UI for P1: 0, mck2ui 16
7663 11:45:38.569855 best dqsien dly found for B0: ( 1, 9, 10)
7664 11:45:38.573622 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 11:45:38.576560 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 11:45:38.579573 Total UI for P1: 0, mck2ui 16
7667 11:45:38.583043 best dqsien dly found for B1: ( 1, 9, 20)
7668 11:45:38.586131 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7669 11:45:38.589452 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7670 11:45:38.592963
7671 11:45:38.596214 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7672 11:45:38.599470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7673 11:45:38.603098 [Gating] SW calibration Done
7674 11:45:38.603199 ==
7675 11:45:38.605892 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 11:45:38.609706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 11:45:38.609806 ==
7678 11:45:38.612879 RX Vref Scan: 0
7679 11:45:38.612977
7680 11:45:38.613065 RX Vref 0 -> 0, step: 1
7681 11:45:38.613151
7682 11:45:38.615669 RX Delay 0 -> 252, step: 8
7683 11:45:38.619348 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7684 11:45:38.622979 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7685 11:45:38.629321 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7686 11:45:38.632841 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7687 11:45:38.635549 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7688 11:45:38.639100 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7689 11:45:38.642143 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7690 11:45:38.648844 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7691 11:45:38.652370 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7692 11:45:38.655164 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7693 11:45:38.658758 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7694 11:45:38.665623 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7695 11:45:38.668239 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7696 11:45:38.671741 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7697 11:45:38.675123 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7698 11:45:38.681576 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7699 11:45:38.681680 ==
7700 11:45:38.684930 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 11:45:38.688367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 11:45:38.688468 ==
7703 11:45:38.688588 DQS Delay:
7704 11:45:38.691630 DQS0 = 0, DQS1 = 0
7705 11:45:38.691739 DQM Delay:
7706 11:45:38.695013 DQM0 = 136, DQM1 = 126
7707 11:45:38.695121 DQ Delay:
7708 11:45:38.698534 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7709 11:45:38.701307 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =143
7710 11:45:38.704777 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7711 11:45:38.707814 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7712 11:45:38.707915
7713 11:45:38.708012
7714 11:45:38.711154 ==
7715 11:45:38.714683 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 11:45:38.717867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 11:45:38.717971 ==
7718 11:45:38.718037
7719 11:45:38.718127
7720 11:45:38.721216 TX Vref Scan disable
7721 11:45:38.721317 == TX Byte 0 ==
7722 11:45:38.727480 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7723 11:45:38.731357 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7724 11:45:38.731455 == TX Byte 1 ==
7725 11:45:38.737931 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7726 11:45:38.741014 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7727 11:45:38.741124 ==
7728 11:45:38.744435 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 11:45:38.747573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 11:45:38.747678 ==
7731 11:45:38.761512
7732 11:45:38.765272 TX Vref early break, caculate TX vref
7733 11:45:38.768860 TX Vref=16, minBit 9, minWin=22, winSum=365
7734 11:45:38.771498 TX Vref=18, minBit 10, minWin=22, winSum=376
7735 11:45:38.775061 TX Vref=20, minBit 3, minWin=23, winSum=384
7736 11:45:38.778230 TX Vref=22, minBit 4, minWin=23, winSum=393
7737 11:45:38.781544 TX Vref=24, minBit 3, minWin=24, winSum=402
7738 11:45:38.788042 TX Vref=26, minBit 0, minWin=25, winSum=408
7739 11:45:38.791854 TX Vref=28, minBit 4, minWin=25, winSum=416
7740 11:45:38.794983 TX Vref=30, minBit 0, minWin=24, winSum=411
7741 11:45:38.798229 TX Vref=32, minBit 0, minWin=24, winSum=401
7742 11:45:38.801296 TX Vref=34, minBit 7, minWin=23, winSum=394
7743 11:45:38.807757 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7744 11:45:38.807857
7745 11:45:38.810794 Final TX Range 0 Vref 28
7746 11:45:38.810905
7747 11:45:38.811033 ==
7748 11:45:38.814528 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 11:45:38.817896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 11:45:38.817990 ==
7751 11:45:38.818079
7752 11:45:38.818199
7753 11:45:38.821257 TX Vref Scan disable
7754 11:45:38.827435 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7755 11:45:38.827540 == TX Byte 0 ==
7756 11:45:38.830876 u2DelayCellOfst[0]=18 cells (5 PI)
7757 11:45:38.834051 u2DelayCellOfst[1]=18 cells (5 PI)
7758 11:45:38.837237 u2DelayCellOfst[2]=15 cells (4 PI)
7759 11:45:38.840468 u2DelayCellOfst[3]=15 cells (4 PI)
7760 11:45:38.844208 u2DelayCellOfst[4]=11 cells (3 PI)
7761 11:45:38.847514 u2DelayCellOfst[5]=0 cells (0 PI)
7762 11:45:38.850504 u2DelayCellOfst[6]=22 cells (6 PI)
7763 11:45:38.853693 u2DelayCellOfst[7]=22 cells (6 PI)
7764 11:45:38.856914 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7765 11:45:38.860134 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7766 11:45:38.863655 == TX Byte 1 ==
7767 11:45:38.867279 u2DelayCellOfst[8]=0 cells (0 PI)
7768 11:45:38.870519 u2DelayCellOfst[9]=3 cells (1 PI)
7769 11:45:38.873714 u2DelayCellOfst[10]=7 cells (2 PI)
7770 11:45:38.877174 u2DelayCellOfst[11]=3 cells (1 PI)
7771 11:45:38.877254 u2DelayCellOfst[12]=15 cells (4 PI)
7772 11:45:38.880324 u2DelayCellOfst[13]=15 cells (4 PI)
7773 11:45:38.883967 u2DelayCellOfst[14]=18 cells (5 PI)
7774 11:45:38.887255 u2DelayCellOfst[15]=11 cells (3 PI)
7775 11:45:38.894113 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7776 11:45:38.896892 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7777 11:45:38.896998 DramC Write-DBI on
7778 11:45:38.900123 ==
7779 11:45:38.903564 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 11:45:38.906678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 11:45:38.906777 ==
7782 11:45:38.906872
7783 11:45:38.906961
7784 11:45:38.910046 TX Vref Scan disable
7785 11:45:38.910142 == TX Byte 0 ==
7786 11:45:38.916473 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7787 11:45:38.916580 == TX Byte 1 ==
7788 11:45:38.919864 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7789 11:45:38.923172 DramC Write-DBI off
7790 11:45:38.923247
7791 11:45:38.923315 [DATLAT]
7792 11:45:38.926320 Freq=1600, CH0 RK0
7793 11:45:38.926418
7794 11:45:38.926520 DATLAT Default: 0xf
7795 11:45:38.929615 0, 0xFFFF, sum = 0
7796 11:45:38.929705 1, 0xFFFF, sum = 0
7797 11:45:38.933321 2, 0xFFFF, sum = 0
7798 11:45:38.933501 3, 0xFFFF, sum = 0
7799 11:45:38.936282 4, 0xFFFF, sum = 0
7800 11:45:38.939586 5, 0xFFFF, sum = 0
7801 11:45:38.939691 6, 0xFFFF, sum = 0
7802 11:45:38.943152 7, 0xFFFF, sum = 0
7803 11:45:38.943254 8, 0xFFFF, sum = 0
7804 11:45:38.946149 9, 0xFFFF, sum = 0
7805 11:45:38.946254 10, 0xFFFF, sum = 0
7806 11:45:38.949596 11, 0xFFFF, sum = 0
7807 11:45:38.949721 12, 0xFFFF, sum = 0
7808 11:45:38.952679 13, 0xFFFF, sum = 0
7809 11:45:38.952805 14, 0x0, sum = 1
7810 11:45:38.956379 15, 0x0, sum = 2
7811 11:45:38.956504 16, 0x0, sum = 3
7812 11:45:38.959470 17, 0x0, sum = 4
7813 11:45:38.959589 best_step = 15
7814 11:45:38.959682
7815 11:45:38.959770 ==
7816 11:45:38.963018 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 11:45:38.966085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 11:45:38.969386 ==
7819 11:45:38.969507 RX Vref Scan: 1
7820 11:45:38.969604
7821 11:45:38.973341 Set Vref Range= 24 -> 127
7822 11:45:38.973472
7823 11:45:38.976052 RX Vref 24 -> 127, step: 1
7824 11:45:38.976154
7825 11:45:38.976248 RX Delay 19 -> 252, step: 4
7826 11:45:38.976338
7827 11:45:38.979364 Set Vref, RX VrefLevel [Byte0]: 24
7828 11:45:38.982867 [Byte1]: 24
7829 11:45:38.986977
7830 11:45:38.987085 Set Vref, RX VrefLevel [Byte0]: 25
7831 11:45:38.989437 [Byte1]: 25
7832 11:45:38.994102
7833 11:45:38.994207 Set Vref, RX VrefLevel [Byte0]: 26
7834 11:45:38.997156 [Byte1]: 26
7835 11:45:39.001884
7836 11:45:39.001987 Set Vref, RX VrefLevel [Byte0]: 27
7837 11:45:39.004925 [Byte1]: 27
7838 11:45:39.009167
7839 11:45:39.009277 Set Vref, RX VrefLevel [Byte0]: 28
7840 11:45:39.012331 [Byte1]: 28
7841 11:45:39.016715
7842 11:45:39.016822 Set Vref, RX VrefLevel [Byte0]: 29
7843 11:45:39.020081 [Byte1]: 29
7844 11:45:39.024296
7845 11:45:39.024401 Set Vref, RX VrefLevel [Byte0]: 30
7846 11:45:39.027737 [Byte1]: 30
7847 11:45:39.031898
7848 11:45:39.032000 Set Vref, RX VrefLevel [Byte0]: 31
7849 11:45:39.034898 [Byte1]: 31
7850 11:45:39.039915
7851 11:45:39.042390 Set Vref, RX VrefLevel [Byte0]: 32
7852 11:45:39.046024 [Byte1]: 32
7853 11:45:39.046129
7854 11:45:39.049079 Set Vref, RX VrefLevel [Byte0]: 33
7855 11:45:39.052409 [Byte1]: 33
7856 11:45:39.052533
7857 11:45:39.055614 Set Vref, RX VrefLevel [Byte0]: 34
7858 11:45:39.058920 [Byte1]: 34
7859 11:45:39.059023
7860 11:45:39.062561 Set Vref, RX VrefLevel [Byte0]: 35
7861 11:45:39.065609 [Byte1]: 35
7862 11:45:39.069920
7863 11:45:39.070021 Set Vref, RX VrefLevel [Byte0]: 36
7864 11:45:39.073271 [Byte1]: 36
7865 11:45:39.077380
7866 11:45:39.077495 Set Vref, RX VrefLevel [Byte0]: 37
7867 11:45:39.080789 [Byte1]: 37
7868 11:45:39.084780
7869 11:45:39.084881 Set Vref, RX VrefLevel [Byte0]: 38
7870 11:45:39.088101 [Byte1]: 38
7871 11:45:39.092558
7872 11:45:39.092662 Set Vref, RX VrefLevel [Byte0]: 39
7873 11:45:39.095807 [Byte1]: 39
7874 11:45:39.099855
7875 11:45:39.099960 Set Vref, RX VrefLevel [Byte0]: 40
7876 11:45:39.103221 [Byte1]: 40
7877 11:45:39.107489
7878 11:45:39.107604 Set Vref, RX VrefLevel [Byte0]: 41
7879 11:45:39.110824 [Byte1]: 41
7880 11:45:39.115026
7881 11:45:39.115130 Set Vref, RX VrefLevel [Byte0]: 42
7882 11:45:39.118689 [Byte1]: 42
7883 11:45:39.122624
7884 11:45:39.122731 Set Vref, RX VrefLevel [Byte0]: 43
7885 11:45:39.126079 [Byte1]: 43
7886 11:45:39.130394
7887 11:45:39.130474 Set Vref, RX VrefLevel [Byte0]: 44
7888 11:45:39.133832 [Byte1]: 44
7889 11:45:39.137831
7890 11:45:39.137935 Set Vref, RX VrefLevel [Byte0]: 45
7891 11:45:39.141274 [Byte1]: 45
7892 11:45:39.145590
7893 11:45:39.145667 Set Vref, RX VrefLevel [Byte0]: 46
7894 11:45:39.148574 [Byte1]: 46
7895 11:45:39.153016
7896 11:45:39.153131 Set Vref, RX VrefLevel [Byte0]: 47
7897 11:45:39.156379 [Byte1]: 47
7898 11:45:39.160686
7899 11:45:39.160798 Set Vref, RX VrefLevel [Byte0]: 48
7900 11:45:39.163989 [Byte1]: 48
7901 11:45:39.168489
7902 11:45:39.168594 Set Vref, RX VrefLevel [Byte0]: 49
7903 11:45:39.174648 [Byte1]: 49
7904 11:45:39.174752
7905 11:45:39.178401 Set Vref, RX VrefLevel [Byte0]: 50
7906 11:45:39.181352 [Byte1]: 50
7907 11:45:39.181467
7908 11:45:39.184378 Set Vref, RX VrefLevel [Byte0]: 51
7909 11:45:39.187851 [Byte1]: 51
7910 11:45:39.187955
7911 11:45:39.190784 Set Vref, RX VrefLevel [Byte0]: 52
7912 11:45:39.194283 [Byte1]: 52
7913 11:45:39.198626
7914 11:45:39.198732 Set Vref, RX VrefLevel [Byte0]: 53
7915 11:45:39.201575 [Byte1]: 53
7916 11:45:39.206200
7917 11:45:39.206314 Set Vref, RX VrefLevel [Byte0]: 54
7918 11:45:39.209347 [Byte1]: 54
7919 11:45:39.213811
7920 11:45:39.213922 Set Vref, RX VrefLevel [Byte0]: 55
7921 11:45:39.216805 [Byte1]: 55
7922 11:45:39.221150
7923 11:45:39.221261 Set Vref, RX VrefLevel [Byte0]: 56
7924 11:45:39.224444 [Byte1]: 56
7925 11:45:39.228767
7926 11:45:39.228871 Set Vref, RX VrefLevel [Byte0]: 57
7927 11:45:39.232186 [Byte1]: 57
7928 11:45:39.236055
7929 11:45:39.236172 Set Vref, RX VrefLevel [Byte0]: 58
7930 11:45:39.239635 [Byte1]: 58
7931 11:45:39.243758
7932 11:45:39.243859 Set Vref, RX VrefLevel [Byte0]: 59
7933 11:45:39.247212 [Byte1]: 59
7934 11:45:39.252084
7935 11:45:39.252184 Set Vref, RX VrefLevel [Byte0]: 60
7936 11:45:39.254562 [Byte1]: 60
7937 11:45:39.259452
7938 11:45:39.259555 Set Vref, RX VrefLevel [Byte0]: 61
7939 11:45:39.262532 [Byte1]: 61
7940 11:45:39.266513
7941 11:45:39.266616 Set Vref, RX VrefLevel [Byte0]: 62
7942 11:45:39.270523 [Byte1]: 62
7943 11:45:39.273959
7944 11:45:39.274060 Set Vref, RX VrefLevel [Byte0]: 63
7945 11:45:39.277429 [Byte1]: 63
7946 11:45:39.281891
7947 11:45:39.281992 Set Vref, RX VrefLevel [Byte0]: 64
7948 11:45:39.285208 [Byte1]: 64
7949 11:45:39.289128
7950 11:45:39.289232 Set Vref, RX VrefLevel [Byte0]: 65
7951 11:45:39.292334 [Byte1]: 65
7952 11:45:39.297048
7953 11:45:39.297130 Set Vref, RX VrefLevel [Byte0]: 66
7954 11:45:39.300392 [Byte1]: 66
7955 11:45:39.304595
7956 11:45:39.304667 Set Vref, RX VrefLevel [Byte0]: 67
7957 11:45:39.307799 [Byte1]: 67
7958 11:45:39.311776
7959 11:45:39.311876 Set Vref, RX VrefLevel [Byte0]: 68
7960 11:45:39.315576 [Byte1]: 68
7961 11:45:39.319653
7962 11:45:39.319727 Set Vref, RX VrefLevel [Byte0]: 69
7963 11:45:39.322929 [Byte1]: 69
7964 11:45:39.326993
7965 11:45:39.327073 Set Vref, RX VrefLevel [Byte0]: 70
7966 11:45:39.330738 [Byte1]: 70
7967 11:45:39.334862
7968 11:45:39.334935 Set Vref, RX VrefLevel [Byte0]: 71
7969 11:45:39.337847 [Byte1]: 71
7970 11:45:39.342365
7971 11:45:39.342446 Set Vref, RX VrefLevel [Byte0]: 72
7972 11:45:39.345327 [Byte1]: 72
7973 11:45:39.350064
7974 11:45:39.350139 Set Vref, RX VrefLevel [Byte0]: 73
7975 11:45:39.352986 [Byte1]: 73
7976 11:45:39.357853
7977 11:45:39.357926 Set Vref, RX VrefLevel [Byte0]: 74
7978 11:45:39.360964 [Byte1]: 74
7979 11:45:39.365376
7980 11:45:39.365467 Set Vref, RX VrefLevel [Byte0]: 75
7981 11:45:39.368915 [Byte1]: 75
7982 11:45:39.372673
7983 11:45:39.372745 Set Vref, RX VrefLevel [Byte0]: 76
7984 11:45:39.376230 [Byte1]: 76
7985 11:45:39.379985
7986 11:45:39.380061 Set Vref, RX VrefLevel [Byte0]: 77
7987 11:45:39.383821 [Byte1]: 77
7988 11:45:39.387600
7989 11:45:39.387672 Set Vref, RX VrefLevel [Byte0]: 78
7990 11:45:39.390986 [Byte1]: 78
7991 11:45:39.395333
7992 11:45:39.395413 Set Vref, RX VrefLevel [Byte0]: 79
7993 11:45:39.398691 [Byte1]: 79
7994 11:45:39.403063
7995 11:45:39.403135 Final RX Vref Byte 0 = 67 to rank0
7996 11:45:39.406233 Final RX Vref Byte 1 = 58 to rank0
7997 11:45:39.409621 Final RX Vref Byte 0 = 67 to rank1
7998 11:45:39.412633 Final RX Vref Byte 1 = 58 to rank1==
7999 11:45:39.415918 Dram Type= 6, Freq= 0, CH_0, rank 0
8000 11:45:39.422848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 11:45:39.422938 ==
8002 11:45:39.423005 DQS Delay:
8003 11:45:39.425898 DQS0 = 0, DQS1 = 0
8004 11:45:39.425972 DQM Delay:
8005 11:45:39.426033 DQM0 = 134, DQM1 = 123
8006 11:45:39.428988 DQ Delay:
8007 11:45:39.432508 DQ0 =132, DQ1 =138, DQ2 =132, DQ3 =132
8008 11:45:39.435809 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8009 11:45:39.438857 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8010 11:45:39.442445 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8011 11:45:39.442519
8012 11:45:39.442601
8013 11:45:39.442674
8014 11:45:39.446028 [DramC_TX_OE_Calibration] TA2
8015 11:45:39.449020 Original DQ_B0 (3 6) =30, OEN = 27
8016 11:45:39.452255 Original DQ_B1 (3 6) =30, OEN = 27
8017 11:45:39.455562 24, 0x0, End_B0=24 End_B1=24
8018 11:45:39.458778 25, 0x0, End_B0=25 End_B1=25
8019 11:45:39.458851 26, 0x0, End_B0=26 End_B1=26
8020 11:45:39.462126 27, 0x0, End_B0=27 End_B1=27
8021 11:45:39.465292 28, 0x0, End_B0=28 End_B1=28
8022 11:45:39.468678 29, 0x0, End_B0=29 End_B1=29
8023 11:45:39.468777 30, 0x0, End_B0=30 End_B1=30
8024 11:45:39.471834 31, 0x4141, End_B0=30 End_B1=30
8025 11:45:39.475521 Byte0 end_step=30 best_step=27
8026 11:45:39.478484 Byte1 end_step=30 best_step=27
8027 11:45:39.481671 Byte0 TX OE(2T, 0.5T) = (3, 3)
8028 11:45:39.485569 Byte1 TX OE(2T, 0.5T) = (3, 3)
8029 11:45:39.485652
8030 11:45:39.485715
8031 11:45:39.491989 [DQSOSCAuto] RK0, (LSB)MR18= 0x2113, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8032 11:45:39.495266 CH0 RK0: MR19=303, MR18=2113
8033 11:45:39.501596 CH0_RK0: MR19=0x303, MR18=0x2113, DQSOSC=393, MR23=63, INC=23, DEC=15
8034 11:45:39.501676
8035 11:45:39.505105 ----->DramcWriteLeveling(PI) begin...
8036 11:45:39.505189 ==
8037 11:45:39.508269 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 11:45:39.511450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 11:45:39.511545 ==
8040 11:45:39.515197 Write leveling (Byte 0): 35 => 35
8041 11:45:39.517935 Write leveling (Byte 1): 28 => 28
8042 11:45:39.521815 DramcWriteLeveling(PI) end<-----
8043 11:45:39.521895
8044 11:45:39.521958 ==
8045 11:45:39.524816 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 11:45:39.531235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 11:45:39.531316 ==
8048 11:45:39.531379 [Gating] SW mode calibration
8049 11:45:39.541213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8050 11:45:39.544194 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8051 11:45:39.550950 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 11:45:39.554466 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 11:45:39.557525 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 11:45:39.561342 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:45:39.567546 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8056 11:45:39.571128 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8057 11:45:39.574493 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 11:45:39.580708 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:45:39.584335 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:45:39.591078 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:45:39.593945 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8062 11:45:39.597389 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8063 11:45:39.603889 1 5 16 | B1->B0 | 3434 2525 | 1 1 | (1 0) (1 0)
8064 11:45:39.607095 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8065 11:45:39.610014 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:45:39.616653 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:45:39.620126 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:45:39.623259 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:45:39.630126 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:45:39.633770 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8071 11:45:39.636766 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8072 11:45:39.643321 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8073 11:45:39.646731 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 11:45:39.650047 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 11:45:39.657130 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:45:39.660173 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:45:39.662898 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:45:39.669605 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8079 11:45:39.672736 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 11:45:39.675929 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 11:45:39.682838 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 11:45:39.686030 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:45:39.689172 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:45:39.695898 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:45:39.698954 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:45:39.702334 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:45:39.709551 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:45:39.712477 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:45:39.715723 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:45:39.722231 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:45:39.725390 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:45:39.729014 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:45:39.736182 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8094 11:45:39.738819 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8095 11:45:39.742189 Total UI for P1: 0, mck2ui 16
8096 11:45:39.745535 best dqsien dly found for B0: ( 1, 9, 8)
8097 11:45:39.748445 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8098 11:45:39.751935 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 11:45:39.758671 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 11:45:39.761849 Total UI for P1: 0, mck2ui 16
8101 11:45:39.765079 best dqsien dly found for B1: ( 1, 9, 16)
8102 11:45:39.768702 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8103 11:45:39.771628 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8104 11:45:39.771708
8105 11:45:39.775202 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8106 11:45:39.778430 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8107 11:45:39.781595 [Gating] SW calibration Done
8108 11:45:39.781720 ==
8109 11:45:39.784954 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 11:45:39.787999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 11:45:39.791382 ==
8112 11:45:39.791462 RX Vref Scan: 0
8113 11:45:39.791526
8114 11:45:39.794711 RX Vref 0 -> 0, step: 1
8115 11:45:39.794806
8116 11:45:39.794870 RX Delay 0 -> 252, step: 8
8117 11:45:39.801399 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8118 11:45:39.804568 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8119 11:45:39.808232 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8120 11:45:39.810968 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8121 11:45:39.815073 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8122 11:45:39.821287 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8123 11:45:39.824497 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8124 11:45:39.828027 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8125 11:45:39.831212 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8126 11:45:39.834563 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8127 11:45:39.841152 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8128 11:45:39.844468 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8129 11:45:39.847769 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8130 11:45:39.850704 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8131 11:45:39.857735 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8132 11:45:39.860527 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8133 11:45:39.860607 ==
8134 11:45:39.864250 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 11:45:39.867290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 11:45:39.867395 ==
8137 11:45:39.870577 DQS Delay:
8138 11:45:39.870678 DQS0 = 0, DQS1 = 0
8139 11:45:39.870774 DQM Delay:
8140 11:45:39.874095 DQM0 = 133, DQM1 = 129
8141 11:45:39.874207 DQ Delay:
8142 11:45:39.876955 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8143 11:45:39.880218 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8144 11:45:39.887141 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8145 11:45:39.890343 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8146 11:45:39.890450
8147 11:45:39.890518
8148 11:45:39.890577 ==
8149 11:45:39.893505 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 11:45:39.896651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 11:45:39.896757 ==
8152 11:45:39.896848
8153 11:45:39.896947
8154 11:45:39.900319 TX Vref Scan disable
8155 11:45:39.903689 == TX Byte 0 ==
8156 11:45:39.907663 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8157 11:45:39.910119 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8158 11:45:39.913655 == TX Byte 1 ==
8159 11:45:39.916914 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8160 11:45:39.919817 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8161 11:45:39.919920 ==
8162 11:45:39.923196 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 11:45:39.930045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 11:45:39.930149 ==
8165 11:45:39.942887
8166 11:45:39.946194 TX Vref early break, caculate TX vref
8167 11:45:39.949679 TX Vref=16, minBit 3, minWin=21, winSum=372
8168 11:45:39.952983 TX Vref=18, minBit 8, minWin=22, winSum=379
8169 11:45:39.956192 TX Vref=20, minBit 0, minWin=23, winSum=387
8170 11:45:39.959896 TX Vref=22, minBit 0, minWin=24, winSum=397
8171 11:45:39.963228 TX Vref=24, minBit 1, minWin=24, winSum=405
8172 11:45:39.969601 TX Vref=26, minBit 1, minWin=24, winSum=411
8173 11:45:39.972774 TX Vref=28, minBit 0, minWin=24, winSum=407
8174 11:45:39.976103 TX Vref=30, minBit 1, minWin=24, winSum=405
8175 11:45:39.979136 TX Vref=32, minBit 0, minWin=24, winSum=397
8176 11:45:39.982440 TX Vref=34, minBit 0, minWin=23, winSum=392
8177 11:45:39.988872 TX Vref=36, minBit 1, minWin=22, winSum=381
8178 11:45:39.992637 [TxChooseVref] Worse bit 1, Min win 24, Win sum 411, Final Vref 26
8179 11:45:39.992745
8180 11:45:39.995736 Final TX Range 0 Vref 26
8181 11:45:39.995865
8182 11:45:39.995966 ==
8183 11:45:39.998919 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 11:45:40.002535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 11:45:40.005548 ==
8186 11:45:40.005647
8187 11:45:40.005780
8188 11:45:40.005889 TX Vref Scan disable
8189 11:45:40.012607 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8190 11:45:40.012719 == TX Byte 0 ==
8191 11:45:40.015580 u2DelayCellOfst[0]=11 cells (3 PI)
8192 11:45:40.019016 u2DelayCellOfst[1]=15 cells (4 PI)
8193 11:45:40.022321 u2DelayCellOfst[2]=11 cells (3 PI)
8194 11:45:40.025390 u2DelayCellOfst[3]=15 cells (4 PI)
8195 11:45:40.028843 u2DelayCellOfst[4]=7 cells (2 PI)
8196 11:45:40.031818 u2DelayCellOfst[5]=0 cells (0 PI)
8197 11:45:40.035517 u2DelayCellOfst[6]=18 cells (5 PI)
8198 11:45:40.038678 u2DelayCellOfst[7]=15 cells (4 PI)
8199 11:45:40.041982 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8200 11:45:40.044959 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8201 11:45:40.048498 == TX Byte 1 ==
8202 11:45:40.051749 u2DelayCellOfst[8]=0 cells (0 PI)
8203 11:45:40.054774 u2DelayCellOfst[9]=3 cells (1 PI)
8204 11:45:40.058504 u2DelayCellOfst[10]=7 cells (2 PI)
8205 11:45:40.061459 u2DelayCellOfst[11]=3 cells (1 PI)
8206 11:45:40.064718 u2DelayCellOfst[12]=11 cells (3 PI)
8207 11:45:40.068390 u2DelayCellOfst[13]=15 cells (4 PI)
8208 11:45:40.071555 u2DelayCellOfst[14]=18 cells (5 PI)
8209 11:45:40.071670 u2DelayCellOfst[15]=11 cells (3 PI)
8210 11:45:40.078287 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8211 11:45:40.081515 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8212 11:45:40.084803 DramC Write-DBI on
8213 11:45:40.084914 ==
8214 11:45:40.088324 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 11:45:40.091435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 11:45:40.091543 ==
8217 11:45:40.091642
8218 11:45:40.091730
8219 11:45:40.094528 TX Vref Scan disable
8220 11:45:40.094640 == TX Byte 0 ==
8221 11:45:40.101293 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8222 11:45:40.101415 == TX Byte 1 ==
8223 11:45:40.104424 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8224 11:45:40.107759 DramC Write-DBI off
8225 11:45:40.107854
8226 11:45:40.107918 [DATLAT]
8227 11:45:40.111461 Freq=1600, CH0 RK1
8228 11:45:40.111543
8229 11:45:40.111610 DATLAT Default: 0xf
8230 11:45:40.114847 0, 0xFFFF, sum = 0
8231 11:45:40.117983 1, 0xFFFF, sum = 0
8232 11:45:40.118070 2, 0xFFFF, sum = 0
8233 11:45:40.121117 3, 0xFFFF, sum = 0
8234 11:45:40.121193 4, 0xFFFF, sum = 0
8235 11:45:40.125050 5, 0xFFFF, sum = 0
8236 11:45:40.125130 6, 0xFFFF, sum = 0
8237 11:45:40.128274 7, 0xFFFF, sum = 0
8238 11:45:40.128385 8, 0xFFFF, sum = 0
8239 11:45:40.131338 9, 0xFFFF, sum = 0
8240 11:45:40.131451 10, 0xFFFF, sum = 0
8241 11:45:40.134425 11, 0xFFFF, sum = 0
8242 11:45:40.134532 12, 0xFFFF, sum = 0
8243 11:45:40.137866 13, 0xFFFF, sum = 0
8244 11:45:40.137973 14, 0x0, sum = 1
8245 11:45:40.140897 15, 0x0, sum = 2
8246 11:45:40.140999 16, 0x0, sum = 3
8247 11:45:40.144375 17, 0x0, sum = 4
8248 11:45:40.144479 best_step = 15
8249 11:45:40.144569
8250 11:45:40.144655 ==
8251 11:45:40.147369 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 11:45:40.153924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 11:45:40.154035 ==
8254 11:45:40.154128 RX Vref Scan: 0
8255 11:45:40.154231
8256 11:45:40.157189 RX Vref 0 -> 0, step: 1
8257 11:45:40.157295
8258 11:45:40.160582 RX Delay 11 -> 252, step: 4
8259 11:45:40.164276 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8260 11:45:40.167607 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8261 11:45:40.173619 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8262 11:45:40.177211 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8263 11:45:40.180553 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8264 11:45:40.183541 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8265 11:45:40.186962 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8266 11:45:40.193932 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8267 11:45:40.196526 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8268 11:45:40.200284 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8269 11:45:40.203588 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8270 11:45:40.206551 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8271 11:45:40.213353 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8272 11:45:40.216725 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8273 11:45:40.219892 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8274 11:45:40.223394 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8275 11:45:40.223495 ==
8276 11:45:40.226372 Dram Type= 6, Freq= 0, CH_0, rank 1
8277 11:45:40.233172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 11:45:40.233282 ==
8279 11:45:40.233377 DQS Delay:
8280 11:45:40.236410 DQS0 = 0, DQS1 = 0
8281 11:45:40.236513 DQM Delay:
8282 11:45:40.240103 DQM0 = 130, DQM1 = 125
8283 11:45:40.240194 DQ Delay:
8284 11:45:40.242705 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8285 11:45:40.246653 DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =140
8286 11:45:40.249590 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8287 11:45:40.252925 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8288 11:45:40.253033
8289 11:45:40.253124
8290 11:45:40.253219
8291 11:45:40.256013 [DramC_TX_OE_Calibration] TA2
8292 11:45:40.259646 Original DQ_B0 (3 6) =30, OEN = 27
8293 11:45:40.263002 Original DQ_B1 (3 6) =30, OEN = 27
8294 11:45:40.265748 24, 0x0, End_B0=24 End_B1=24
8295 11:45:40.269661 25, 0x0, End_B0=25 End_B1=25
8296 11:45:40.269770 26, 0x0, End_B0=26 End_B1=26
8297 11:45:40.272460 27, 0x0, End_B0=27 End_B1=27
8298 11:45:40.275849 28, 0x0, End_B0=28 End_B1=28
8299 11:45:40.279247 29, 0x0, End_B0=29 End_B1=29
8300 11:45:40.279365 30, 0x0, End_B0=30 End_B1=30
8301 11:45:40.282356 31, 0x4141, End_B0=30 End_B1=30
8302 11:45:40.286246 Byte0 end_step=30 best_step=27
8303 11:45:40.289323 Byte1 end_step=30 best_step=27
8304 11:45:40.292353 Byte0 TX OE(2T, 0.5T) = (3, 3)
8305 11:45:40.295517 Byte1 TX OE(2T, 0.5T) = (3, 3)
8306 11:45:40.295592
8307 11:45:40.295653
8308 11:45:40.302168 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8309 11:45:40.305435 CH0 RK1: MR19=303, MR18=2104
8310 11:45:40.312032 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8311 11:45:40.315590 [RxdqsGatingPostProcess] freq 1600
8312 11:45:40.322452 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8313 11:45:40.322567 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 11:45:40.325142 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 11:45:40.328950 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 11:45:40.331974 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 11:45:40.335306 best DQS0 dly(2T, 0.5T) = (1, 1)
8318 11:45:40.338640 best DQS1 dly(2T, 0.5T) = (1, 1)
8319 11:45:40.341666 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8320 11:45:40.344979 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8321 11:45:40.348435 Pre-setting of DQS Precalculation
8322 11:45:40.352019 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8323 11:45:40.354779 ==
8324 11:45:40.354855 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 11:45:40.361885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 11:45:40.361996 ==
8327 11:45:40.365506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 11:45:40.371705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 11:45:40.374516 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 11:45:40.381173 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 11:45:40.389326 [CA 0] Center 42 (13~72) winsize 60
8332 11:45:40.393018 [CA 1] Center 42 (12~72) winsize 61
8333 11:45:40.395830 [CA 2] Center 38 (9~67) winsize 59
8334 11:45:40.399640 [CA 3] Center 37 (8~66) winsize 59
8335 11:45:40.402738 [CA 4] Center 37 (8~67) winsize 60
8336 11:45:40.406077 [CA 5] Center 37 (8~67) winsize 60
8337 11:45:40.406153
8338 11:45:40.409214 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 11:45:40.409317
8340 11:45:40.415598 [CATrainingPosCal] consider 1 rank data
8341 11:45:40.415674 u2DelayCellTimex100 = 258/100 ps
8342 11:45:40.422576 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8343 11:45:40.425599 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8344 11:45:40.428628 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 11:45:40.431865 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 11:45:40.435808 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 11:45:40.438741 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 11:45:40.438822
8349 11:45:40.441959 CA PerBit enable=1, Macro0, CA PI delay=37
8350 11:45:40.442038
8351 11:45:40.445064 [CBTSetCACLKResult] CA Dly = 37
8352 11:45:40.448496 CS Dly: 9 (0~40)
8353 11:45:40.452251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 11:45:40.455318 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 11:45:40.455398 ==
8356 11:45:40.459040 Dram Type= 6, Freq= 0, CH_1, rank 1
8357 11:45:40.465087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 11:45:40.465194 ==
8359 11:45:40.468200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8360 11:45:40.474951 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8361 11:45:40.478522 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8362 11:45:40.485072 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8363 11:45:40.492626 [CA 0] Center 42 (13~71) winsize 59
8364 11:45:40.495932 [CA 1] Center 42 (13~72) winsize 60
8365 11:45:40.499163 [CA 2] Center 37 (8~67) winsize 60
8366 11:45:40.502943 [CA 3] Center 37 (7~67) winsize 61
8367 11:45:40.505731 [CA 4] Center 37 (8~67) winsize 60
8368 11:45:40.508911 [CA 5] Center 37 (8~66) winsize 59
8369 11:45:40.508991
8370 11:45:40.512516 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8371 11:45:40.512610
8372 11:45:40.519104 [CATrainingPosCal] consider 2 rank data
8373 11:45:40.519184 u2DelayCellTimex100 = 258/100 ps
8374 11:45:40.525329 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8375 11:45:40.528703 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8376 11:45:40.531998 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8377 11:45:40.536075 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8378 11:45:40.538598 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8379 11:45:40.541984 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8380 11:45:40.542061
8381 11:45:40.545282 CA PerBit enable=1, Macro0, CA PI delay=37
8382 11:45:40.545376
8383 11:45:40.548784 [CBTSetCACLKResult] CA Dly = 37
8384 11:45:40.551875 CS Dly: 10 (0~43)
8385 11:45:40.554958 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8386 11:45:40.558210 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8387 11:45:40.558281
8388 11:45:40.561729 ----->DramcWriteLeveling(PI) begin...
8389 11:45:40.561811 ==
8390 11:45:40.565307 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 11:45:40.571756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 11:45:40.571850 ==
8393 11:45:40.574834 Write leveling (Byte 0): 24 => 24
8394 11:45:40.578273 Write leveling (Byte 1): 28 => 28
8395 11:45:40.581319 DramcWriteLeveling(PI) end<-----
8396 11:45:40.581439
8397 11:45:40.581525 ==
8398 11:45:40.584696 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 11:45:40.587969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 11:45:40.588041 ==
8401 11:45:40.591291 [Gating] SW mode calibration
8402 11:45:40.598234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8403 11:45:40.601833 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8404 11:45:40.607851 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:45:40.611256 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:45:40.617639 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:45:40.620913 1 4 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
8408 11:45:40.624558 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 11:45:40.627858 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 11:45:40.634354 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:45:40.637669 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:45:40.640721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:45:40.647714 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:45:40.651030 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8415 11:45:40.654150 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8416 11:45:40.660666 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8417 11:45:40.664231 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 11:45:40.667736 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:45:40.673896 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:45:40.677729 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:45:40.680573 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:45:40.687279 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8423 11:45:40.690732 1 6 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8424 11:45:40.693836 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 11:45:40.700655 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:45:40.703869 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:45:40.707004 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:45:40.713891 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:45:40.716923 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:45:40.720150 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8431 11:45:40.726967 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8432 11:45:40.730349 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 11:45:40.733366 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 11:45:40.740183 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:45:40.743334 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:45:40.746811 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:45:40.753798 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:45:40.756276 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:45:40.759767 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:45:40.766398 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:45:40.769622 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:45:40.772750 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:45:40.779556 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:45:40.783368 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:45:40.786199 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:45:40.792979 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8447 11:45:40.796480 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8448 11:45:40.799274 Total UI for P1: 0, mck2ui 16
8449 11:45:40.802667 best dqsien dly found for B0: ( 1, 9, 8)
8450 11:45:40.806023 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8451 11:45:40.813088 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 11:45:40.813169 Total UI for P1: 0, mck2ui 16
8453 11:45:40.819211 best dqsien dly found for B1: ( 1, 9, 14)
8454 11:45:40.822480 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8455 11:45:40.826286 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8456 11:45:40.826371
8457 11:45:40.829401 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8458 11:45:40.832548 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8459 11:45:40.835745 [Gating] SW calibration Done
8460 11:45:40.835827 ==
8461 11:45:40.839064 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 11:45:40.842388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 11:45:40.842484 ==
8464 11:45:40.845573 RX Vref Scan: 0
8465 11:45:40.845653
8466 11:45:40.845716 RX Vref 0 -> 0, step: 1
8467 11:45:40.845781
8468 11:45:40.849399 RX Delay 0 -> 252, step: 8
8469 11:45:40.852478 iDelay=208, Bit 0, Center 147 (96 ~ 199) 104
8470 11:45:40.859434 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8471 11:45:40.862369 iDelay=208, Bit 2, Center 131 (80 ~ 183) 104
8472 11:45:40.865530 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8473 11:45:40.869315 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8474 11:45:40.872263 iDelay=208, Bit 5, Center 155 (104 ~ 207) 104
8475 11:45:40.878723 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8476 11:45:40.881919 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8477 11:45:40.885069 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8478 11:45:40.888727 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8479 11:45:40.895218 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8480 11:45:40.898545 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8481 11:45:40.901687 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8482 11:45:40.904921 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8483 11:45:40.908025 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8484 11:45:40.914916 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8485 11:45:40.915001 ==
8486 11:45:40.918215 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 11:45:40.921393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 11:45:40.921507 ==
8489 11:45:40.921582 DQS Delay:
8490 11:45:40.924618 DQS0 = 0, DQS1 = 0
8491 11:45:40.924698 DQM Delay:
8492 11:45:40.927934 DQM0 = 140, DQM1 = 129
8493 11:45:40.928017 DQ Delay:
8494 11:45:40.931243 DQ0 =147, DQ1 =135, DQ2 =131, DQ3 =139
8495 11:45:40.934575 DQ4 =135, DQ5 =155, DQ6 =147, DQ7 =135
8496 11:45:40.937769 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8497 11:45:40.944599 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8498 11:45:40.944679
8499 11:45:40.944743
8500 11:45:40.944801 ==
8501 11:45:40.947807 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 11:45:40.951375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 11:45:40.951447 ==
8504 11:45:40.951523
8505 11:45:40.951584
8506 11:45:40.954613 TX Vref Scan disable
8507 11:45:40.954693 == TX Byte 0 ==
8508 11:45:40.960930 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8509 11:45:40.964636 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8510 11:45:40.964717 == TX Byte 1 ==
8511 11:45:40.971313 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8512 11:45:40.974089 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 11:45:40.974166 ==
8514 11:45:40.977414 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 11:45:40.980748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 11:45:40.980840 ==
8517 11:45:40.994693
8518 11:45:40.998124 TX Vref early break, caculate TX vref
8519 11:45:41.001737 TX Vref=16, minBit 0, minWin=22, winSum=378
8520 11:45:41.004512 TX Vref=18, minBit 5, minWin=23, winSum=386
8521 11:45:41.007909 TX Vref=20, minBit 0, minWin=23, winSum=397
8522 11:45:41.011121 TX Vref=22, minBit 0, minWin=24, winSum=406
8523 11:45:41.014344 TX Vref=24, minBit 5, minWin=24, winSum=413
8524 11:45:41.020985 TX Vref=26, minBit 0, minWin=24, winSum=422
8525 11:45:41.024901 TX Vref=28, minBit 0, minWin=24, winSum=422
8526 11:45:41.027733 TX Vref=30, minBit 0, minWin=24, winSum=417
8527 11:45:41.030958 TX Vref=32, minBit 0, minWin=24, winSum=405
8528 11:45:41.034810 TX Vref=34, minBit 1, minWin=23, winSum=396
8529 11:45:41.041358 [TxChooseVref] Worse bit 0, Min win 24, Win sum 422, Final Vref 26
8530 11:45:41.041499
8531 11:45:41.044583 Final TX Range 0 Vref 26
8532 11:45:41.044664
8533 11:45:41.044730 ==
8534 11:45:41.047587 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 11:45:41.050720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 11:45:41.050807 ==
8537 11:45:41.050870
8538 11:45:41.050928
8539 11:45:41.054017 TX Vref Scan disable
8540 11:45:41.060782 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8541 11:45:41.060858 == TX Byte 0 ==
8542 11:45:41.063942 u2DelayCellOfst[0]=22 cells (6 PI)
8543 11:45:41.067540 u2DelayCellOfst[1]=15 cells (4 PI)
8544 11:45:41.070637 u2DelayCellOfst[2]=0 cells (0 PI)
8545 11:45:41.074203 u2DelayCellOfst[3]=11 cells (3 PI)
8546 11:45:41.077256 u2DelayCellOfst[4]=11 cells (3 PI)
8547 11:45:41.080495 u2DelayCellOfst[5]=22 cells (6 PI)
8548 11:45:41.083989 u2DelayCellOfst[6]=22 cells (6 PI)
8549 11:45:41.087614 u2DelayCellOfst[7]=11 cells (3 PI)
8550 11:45:41.090948 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8551 11:45:41.094292 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8552 11:45:41.097005 == TX Byte 1 ==
8553 11:45:41.100343 u2DelayCellOfst[8]=0 cells (0 PI)
8554 11:45:41.100449 u2DelayCellOfst[9]=3 cells (1 PI)
8555 11:45:41.104110 u2DelayCellOfst[10]=11 cells (3 PI)
8556 11:45:41.107314 u2DelayCellOfst[11]=3 cells (1 PI)
8557 11:45:41.111089 u2DelayCellOfst[12]=15 cells (4 PI)
8558 11:45:41.113760 u2DelayCellOfst[13]=15 cells (4 PI)
8559 11:45:41.117065 u2DelayCellOfst[14]=18 cells (5 PI)
8560 11:45:41.120264 u2DelayCellOfst[15]=18 cells (5 PI)
8561 11:45:41.127087 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8562 11:45:41.130389 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8563 11:45:41.130488 DramC Write-DBI on
8564 11:45:41.130590 ==
8565 11:45:41.133581 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 11:45:41.140226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 11:45:41.140342 ==
8568 11:45:41.140439
8569 11:45:41.140516
8570 11:45:41.140606 TX Vref Scan disable
8571 11:45:41.144196 == TX Byte 0 ==
8572 11:45:41.147440 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8573 11:45:41.150951 == TX Byte 1 ==
8574 11:45:41.154216 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8575 11:45:41.157300 DramC Write-DBI off
8576 11:45:41.157428
8577 11:45:41.157511 [DATLAT]
8578 11:45:41.157573 Freq=1600, CH1 RK0
8579 11:45:41.157632
8580 11:45:41.160460 DATLAT Default: 0xf
8581 11:45:41.163719 0, 0xFFFF, sum = 0
8582 11:45:41.163835 1, 0xFFFF, sum = 0
8583 11:45:41.167624 2, 0xFFFF, sum = 0
8584 11:45:41.167720 3, 0xFFFF, sum = 0
8585 11:45:41.170808 4, 0xFFFF, sum = 0
8586 11:45:41.170907 5, 0xFFFF, sum = 0
8587 11:45:41.174052 6, 0xFFFF, sum = 0
8588 11:45:41.174199 7, 0xFFFF, sum = 0
8589 11:45:41.177354 8, 0xFFFF, sum = 0
8590 11:45:41.177476 9, 0xFFFF, sum = 0
8591 11:45:41.180720 10, 0xFFFF, sum = 0
8592 11:45:41.180820 11, 0xFFFF, sum = 0
8593 11:45:41.183856 12, 0xFFFF, sum = 0
8594 11:45:41.183956 13, 0xFFFF, sum = 0
8595 11:45:41.187318 14, 0x0, sum = 1
8596 11:45:41.187404 15, 0x0, sum = 2
8597 11:45:41.190544 16, 0x0, sum = 3
8598 11:45:41.190626 17, 0x0, sum = 4
8599 11:45:41.194074 best_step = 15
8600 11:45:41.194156
8601 11:45:41.194221 ==
8602 11:45:41.197144 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 11:45:41.200478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 11:45:41.200593 ==
8605 11:45:41.203815 RX Vref Scan: 1
8606 11:45:41.203897
8607 11:45:41.203961 Set Vref Range= 24 -> 127
8608 11:45:41.204053
8609 11:45:41.207432 RX Vref 24 -> 127, step: 1
8610 11:45:41.207513
8611 11:45:41.210602 RX Delay 11 -> 252, step: 4
8612 11:45:41.210724
8613 11:45:41.213620 Set Vref, RX VrefLevel [Byte0]: 24
8614 11:45:41.216819 [Byte1]: 24
8615 11:45:41.216901
8616 11:45:41.219975 Set Vref, RX VrefLevel [Byte0]: 25
8617 11:45:41.223826 [Byte1]: 25
8618 11:45:41.227070
8619 11:45:41.227153 Set Vref, RX VrefLevel [Byte0]: 26
8620 11:45:41.230099 [Byte1]: 26
8621 11:45:41.235057
8622 11:45:41.235141 Set Vref, RX VrefLevel [Byte0]: 27
8623 11:45:41.238181 [Byte1]: 27
8624 11:45:41.242473
8625 11:45:41.242556 Set Vref, RX VrefLevel [Byte0]: 28
8626 11:45:41.245284 [Byte1]: 28
8627 11:45:41.250042
8628 11:45:41.250130 Set Vref, RX VrefLevel [Byte0]: 29
8629 11:45:41.253220 [Byte1]: 29
8630 11:45:41.257709
8631 11:45:41.257792 Set Vref, RX VrefLevel [Byte0]: 30
8632 11:45:41.260804 [Byte1]: 30
8633 11:45:41.265004
8634 11:45:41.265095 Set Vref, RX VrefLevel [Byte0]: 31
8635 11:45:41.268098 [Byte1]: 31
8636 11:45:41.272829
8637 11:45:41.272914 Set Vref, RX VrefLevel [Byte0]: 32
8638 11:45:41.276388 [Byte1]: 32
8639 11:45:41.280058
8640 11:45:41.280158 Set Vref, RX VrefLevel [Byte0]: 33
8641 11:45:41.283429 [Byte1]: 33
8642 11:45:41.287670
8643 11:45:41.287795 Set Vref, RX VrefLevel [Byte0]: 34
8644 11:45:41.291360 [Byte1]: 34
8645 11:45:41.295684
8646 11:45:41.295767 Set Vref, RX VrefLevel [Byte0]: 35
8647 11:45:41.299078 [Byte1]: 35
8648 11:45:41.302937
8649 11:45:41.303047 Set Vref, RX VrefLevel [Byte0]: 36
8650 11:45:41.306203 [Byte1]: 36
8651 11:45:41.310989
8652 11:45:41.311072 Set Vref, RX VrefLevel [Byte0]: 37
8653 11:45:41.313839 [Byte1]: 37
8654 11:45:41.318302
8655 11:45:41.318411 Set Vref, RX VrefLevel [Byte0]: 38
8656 11:45:41.321591 [Byte1]: 38
8657 11:45:41.326133
8658 11:45:41.326240 Set Vref, RX VrefLevel [Byte0]: 39
8659 11:45:41.329709 [Byte1]: 39
8660 11:45:41.333551
8661 11:45:41.333633 Set Vref, RX VrefLevel [Byte0]: 40
8662 11:45:41.336902 [Byte1]: 40
8663 11:45:41.341328
8664 11:45:41.341419 Set Vref, RX VrefLevel [Byte0]: 41
8665 11:45:41.344412 [Byte1]: 41
8666 11:45:41.348865
8667 11:45:41.348946 Set Vref, RX VrefLevel [Byte0]: 42
8668 11:45:41.351890 [Byte1]: 42
8669 11:45:41.356245
8670 11:45:41.356326 Set Vref, RX VrefLevel [Byte0]: 43
8671 11:45:41.359559 [Byte1]: 43
8672 11:45:41.363828
8673 11:45:41.363911 Set Vref, RX VrefLevel [Byte0]: 44
8674 11:45:41.367393 [Byte1]: 44
8675 11:45:41.371629
8676 11:45:41.371740 Set Vref, RX VrefLevel [Byte0]: 45
8677 11:45:41.374985 [Byte1]: 45
8678 11:45:41.379035
8679 11:45:41.379116 Set Vref, RX VrefLevel [Byte0]: 46
8680 11:45:41.385476 [Byte1]: 46
8681 11:45:41.385583
8682 11:45:41.388949 Set Vref, RX VrefLevel [Byte0]: 47
8683 11:45:41.392789 [Byte1]: 47
8684 11:45:41.392871
8685 11:45:41.395911 Set Vref, RX VrefLevel [Byte0]: 48
8686 11:45:41.399098 [Byte1]: 48
8687 11:45:41.401936
8688 11:45:41.402017 Set Vref, RX VrefLevel [Byte0]: 49
8689 11:45:41.405426 [Byte1]: 49
8690 11:45:41.409880
8691 11:45:41.409961 Set Vref, RX VrefLevel [Byte0]: 50
8692 11:45:41.413339 [Byte1]: 50
8693 11:45:41.417516
8694 11:45:41.417614 Set Vref, RX VrefLevel [Byte0]: 51
8695 11:45:41.420729 [Byte1]: 51
8696 11:45:41.425140
8697 11:45:41.425288 Set Vref, RX VrefLevel [Byte0]: 52
8698 11:45:41.428186 [Byte1]: 52
8699 11:45:41.432641
8700 11:45:41.432745 Set Vref, RX VrefLevel [Byte0]: 53
8701 11:45:41.435926 [Byte1]: 53
8702 11:45:41.439996
8703 11:45:41.440096 Set Vref, RX VrefLevel [Byte0]: 54
8704 11:45:41.443841 [Byte1]: 54
8705 11:45:41.448116
8706 11:45:41.448215 Set Vref, RX VrefLevel [Byte0]: 55
8707 11:45:41.451056 [Byte1]: 55
8708 11:45:41.455343
8709 11:45:41.455447 Set Vref, RX VrefLevel [Byte0]: 56
8710 11:45:41.458621 [Byte1]: 56
8711 11:45:41.462788
8712 11:45:41.462864 Set Vref, RX VrefLevel [Byte0]: 57
8713 11:45:41.466422 [Byte1]: 57
8714 11:45:41.470687
8715 11:45:41.470782 Set Vref, RX VrefLevel [Byte0]: 58
8716 11:45:41.473937 [Byte1]: 58
8717 11:45:41.478496
8718 11:45:41.478576 Set Vref, RX VrefLevel [Byte0]: 59
8719 11:45:41.481838 [Byte1]: 59
8720 11:45:41.485590
8721 11:45:41.485675 Set Vref, RX VrefLevel [Byte0]: 60
8722 11:45:41.488876 [Byte1]: 60
8723 11:45:41.493294
8724 11:45:41.493404 Set Vref, RX VrefLevel [Byte0]: 61
8725 11:45:41.496489 [Byte1]: 61
8726 11:45:41.500932
8727 11:45:41.501013 Set Vref, RX VrefLevel [Byte0]: 62
8728 11:45:41.504117 [Byte1]: 62
8729 11:45:41.508630
8730 11:45:41.508730 Set Vref, RX VrefLevel [Byte0]: 63
8731 11:45:41.511834 [Byte1]: 63
8732 11:45:41.516111
8733 11:45:41.516183 Set Vref, RX VrefLevel [Byte0]: 64
8734 11:45:41.519816 [Byte1]: 64
8735 11:45:41.523836
8736 11:45:41.523926 Set Vref, RX VrefLevel [Byte0]: 65
8737 11:45:41.527253 [Byte1]: 65
8738 11:45:41.531597
8739 11:45:41.531695 Set Vref, RX VrefLevel [Byte0]: 66
8740 11:45:41.534848 [Byte1]: 66
8741 11:45:41.539062
8742 11:45:41.539161 Set Vref, RX VrefLevel [Byte0]: 67
8743 11:45:41.542541 [Byte1]: 67
8744 11:45:41.546460
8745 11:45:41.546532 Set Vref, RX VrefLevel [Byte0]: 68
8746 11:45:41.550118 [Byte1]: 68
8747 11:45:41.554518
8748 11:45:41.554618 Set Vref, RX VrefLevel [Byte0]: 69
8749 11:45:41.557704 [Byte1]: 69
8750 11:45:41.562324
8751 11:45:41.562426 Set Vref, RX VrefLevel [Byte0]: 70
8752 11:45:41.564986 [Byte1]: 70
8753 11:45:41.569514
8754 11:45:41.569588 Set Vref, RX VrefLevel [Byte0]: 71
8755 11:45:41.572885 [Byte1]: 71
8756 11:45:41.576907
8757 11:45:41.576984 Set Vref, RX VrefLevel [Byte0]: 72
8758 11:45:41.580287 [Byte1]: 72
8759 11:45:41.584511
8760 11:45:41.584588 Set Vref, RX VrefLevel [Byte0]: 73
8761 11:45:41.587912 [Byte1]: 73
8762 11:45:41.592258
8763 11:45:41.592363 Set Vref, RX VrefLevel [Byte0]: 74
8764 11:45:41.595881 [Byte1]: 74
8765 11:45:41.599978
8766 11:45:41.600052 Set Vref, RX VrefLevel [Byte0]: 75
8767 11:45:41.603093 [Byte1]: 75
8768 11:45:41.607407
8769 11:45:41.607520 Set Vref, RX VrefLevel [Byte0]: 76
8770 11:45:41.610868 [Byte1]: 76
8771 11:45:41.614957
8772 11:45:41.615035 Set Vref, RX VrefLevel [Byte0]: 77
8773 11:45:41.618673 [Byte1]: 77
8774 11:45:41.622593
8775 11:45:41.622674 Final RX Vref Byte 0 = 50 to rank0
8776 11:45:41.625909 Final RX Vref Byte 1 = 60 to rank0
8777 11:45:41.629715 Final RX Vref Byte 0 = 50 to rank1
8778 11:45:41.632737 Final RX Vref Byte 1 = 60 to rank1==
8779 11:45:41.636105 Dram Type= 6, Freq= 0, CH_1, rank 0
8780 11:45:41.642676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 11:45:41.642756 ==
8782 11:45:41.642820 DQS Delay:
8783 11:45:41.645899 DQS0 = 0, DQS1 = 0
8784 11:45:41.645972 DQM Delay:
8785 11:45:41.646033 DQM0 = 135, DQM1 = 128
8786 11:45:41.649563 DQ Delay:
8787 11:45:41.652595 DQ0 =142, DQ1 =130, DQ2 =126, DQ3 =130
8788 11:45:41.655935 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =132
8789 11:45:41.658861 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =118
8790 11:45:41.662752 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8791 11:45:41.662825
8792 11:45:41.662903
8793 11:45:41.662962
8794 11:45:41.665785 [DramC_TX_OE_Calibration] TA2
8795 11:45:41.669129 Original DQ_B0 (3 6) =30, OEN = 27
8796 11:45:41.672501 Original DQ_B1 (3 6) =30, OEN = 27
8797 11:45:41.675599 24, 0x0, End_B0=24 End_B1=24
8798 11:45:41.675707 25, 0x0, End_B0=25 End_B1=25
8799 11:45:41.678874 26, 0x0, End_B0=26 End_B1=26
8800 11:45:41.682191 27, 0x0, End_B0=27 End_B1=27
8801 11:45:41.685789 28, 0x0, End_B0=28 End_B1=28
8802 11:45:41.688547 29, 0x0, End_B0=29 End_B1=29
8803 11:45:41.688622 30, 0x0, End_B0=30 End_B1=30
8804 11:45:41.692148 31, 0x4545, End_B0=30 End_B1=30
8805 11:45:41.695443 Byte0 end_step=30 best_step=27
8806 11:45:41.698769 Byte1 end_step=30 best_step=27
8807 11:45:41.702239 Byte0 TX OE(2T, 0.5T) = (3, 3)
8808 11:45:41.705174 Byte1 TX OE(2T, 0.5T) = (3, 3)
8809 11:45:41.705311
8810 11:45:41.705406
8811 11:45:41.712011 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8812 11:45:41.714968 CH1 RK0: MR19=303, MR18=190F
8813 11:45:41.722180 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8814 11:45:41.722284
8815 11:45:41.725007 ----->DramcWriteLeveling(PI) begin...
8816 11:45:41.725123 ==
8817 11:45:41.728733 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 11:45:41.731763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 11:45:41.731845 ==
8820 11:45:41.735206 Write leveling (Byte 0): 24 => 24
8821 11:45:41.738736 Write leveling (Byte 1): 29 => 29
8822 11:45:41.742175 DramcWriteLeveling(PI) end<-----
8823 11:45:41.742256
8824 11:45:41.742320 ==
8825 11:45:41.745289 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 11:45:41.748624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 11:45:41.748706 ==
8828 11:45:41.751818 [Gating] SW mode calibration
8829 11:45:41.758522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8830 11:45:41.764992 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8831 11:45:41.768357 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 11:45:41.774740 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:45:41.777924 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8834 11:45:41.781382 1 4 12 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
8835 11:45:41.788237 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 11:45:41.791129 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 11:45:41.794665 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:45:41.801134 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:45:41.804400 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:45:41.807680 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 11:45:41.814778 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8842 11:45:41.817685 1 5 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 0) (0 1)
8843 11:45:41.820831 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8844 11:45:41.827332 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 11:45:41.830466 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:45:41.834034 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:45:41.840604 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:45:41.843802 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 11:45:41.847154 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8850 11:45:41.854253 1 6 12 | B1->B0 | 4140 2a2a | 1 0 | (0 0) (0 0)
8851 11:45:41.857117 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 11:45:41.860323 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 11:45:41.866713 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 11:45:41.870251 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:45:41.873388 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:45:41.880095 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:45:41.883277 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8858 11:45:41.886873 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8859 11:45:41.893044 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8860 11:45:41.896379 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:45:41.900076 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:45:41.906428 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:45:41.909654 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:45:41.912727 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:45:41.919444 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:45:41.922677 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:45:41.926104 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:45:41.932692 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:45:41.936002 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:45:41.939333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:45:41.945743 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:45:41.949116 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:45:41.955444 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8874 11:45:41.958596 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8875 11:45:41.962437 Total UI for P1: 0, mck2ui 16
8876 11:45:41.965872 best dqsien dly found for B1: ( 1, 9, 8)
8877 11:45:41.968499 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:45:41.972073 Total UI for P1: 0, mck2ui 16
8879 11:45:41.975213 best dqsien dly found for B0: ( 1, 9, 10)
8880 11:45:41.978489 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8881 11:45:41.982090 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8882 11:45:41.982172
8883 11:45:41.985267 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8884 11:45:41.992026 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8885 11:45:41.992107 [Gating] SW calibration Done
8886 11:45:41.992172 ==
8887 11:45:41.995177 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 11:45:42.001808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 11:45:42.001890 ==
8890 11:45:42.001954 RX Vref Scan: 0
8891 11:45:42.002014
8892 11:45:42.004855 RX Vref 0 -> 0, step: 1
8893 11:45:42.004937
8894 11:45:42.008612 RX Delay 0 -> 252, step: 8
8895 11:45:42.011440 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8896 11:45:42.014829 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8897 11:45:42.018223 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8898 11:45:42.024665 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8899 11:45:42.027808 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8900 11:45:42.031650 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8901 11:45:42.034357 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8902 11:45:42.037800 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8903 11:45:42.044503 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8904 11:45:42.048285 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8905 11:45:42.051179 iDelay=208, Bit 10, Center 127 (64 ~ 191) 128
8906 11:45:42.054422 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8907 11:45:42.057759 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8908 11:45:42.064303 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8909 11:45:42.067835 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8910 11:45:42.070578 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8911 11:45:42.070660 ==
8912 11:45:42.074096 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 11:45:42.077361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 11:45:42.080800 ==
8915 11:45:42.080881 DQS Delay:
8916 11:45:42.080946 DQS0 = 0, DQS1 = 0
8917 11:45:42.083760 DQM Delay:
8918 11:45:42.083842 DQM0 = 138, DQM1 = 128
8919 11:45:42.087088 DQ Delay:
8920 11:45:42.090761 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =135
8921 11:45:42.093760 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8922 11:45:42.097151 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8923 11:45:42.100400 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8924 11:45:42.100496
8925 11:45:42.100560
8926 11:45:42.100620 ==
8927 11:45:42.103831 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:45:42.107083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:45:42.110153 ==
8930 11:45:42.110234
8931 11:45:42.110328
8932 11:45:42.110388 TX Vref Scan disable
8933 11:45:42.113594 == TX Byte 0 ==
8934 11:45:42.116752 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8935 11:45:42.120370 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8936 11:45:42.123444 == TX Byte 1 ==
8937 11:45:42.126784 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8938 11:45:42.130277 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8939 11:45:42.133919 ==
8940 11:45:42.136961 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 11:45:42.139881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 11:45:42.139965 ==
8943 11:45:42.152251
8944 11:45:42.155468 TX Vref early break, caculate TX vref
8945 11:45:42.159025 TX Vref=16, minBit 1, minWin=22, winSum=384
8946 11:45:42.162406 TX Vref=18, minBit 0, minWin=23, winSum=395
8947 11:45:42.165711 TX Vref=20, minBit 1, minWin=24, winSum=406
8948 11:45:42.168507 TX Vref=22, minBit 1, minWin=25, winSum=414
8949 11:45:42.171998 TX Vref=24, minBit 1, minWin=25, winSum=420
8950 11:45:42.178845 TX Vref=26, minBit 1, minWin=25, winSum=421
8951 11:45:42.182284 TX Vref=28, minBit 0, minWin=26, winSum=430
8952 11:45:42.185528 TX Vref=30, minBit 0, minWin=24, winSum=418
8953 11:45:42.188451 TX Vref=32, minBit 0, minWin=24, winSum=410
8954 11:45:42.191756 TX Vref=34, minBit 0, minWin=24, winSum=403
8955 11:45:42.198910 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8956 11:45:42.198993
8957 11:45:42.202145 Final TX Range 0 Vref 28
8958 11:45:42.202251
8959 11:45:42.202318 ==
8960 11:45:42.205380 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 11:45:42.208821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 11:45:42.208906 ==
8963 11:45:42.208971
8964 11:45:42.209032
8965 11:45:42.211901 TX Vref Scan disable
8966 11:45:42.218765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8967 11:45:42.218850 == TX Byte 0 ==
8968 11:45:42.221652 u2DelayCellOfst[0]=18 cells (5 PI)
8969 11:45:42.225427 u2DelayCellOfst[1]=11 cells (3 PI)
8970 11:45:42.228838 u2DelayCellOfst[2]=0 cells (0 PI)
8971 11:45:42.231605 u2DelayCellOfst[3]=7 cells (2 PI)
8972 11:45:42.234923 u2DelayCellOfst[4]=7 cells (2 PI)
8973 11:45:42.238181 u2DelayCellOfst[5]=22 cells (6 PI)
8974 11:45:42.242034 u2DelayCellOfst[6]=22 cells (6 PI)
8975 11:45:42.244902 u2DelayCellOfst[7]=7 cells (2 PI)
8976 11:45:42.247955 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8977 11:45:42.251565 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8978 11:45:42.254919 == TX Byte 1 ==
8979 11:45:42.258124 u2DelayCellOfst[8]=0 cells (0 PI)
8980 11:45:42.258244 u2DelayCellOfst[9]=3 cells (1 PI)
8981 11:45:42.261553 u2DelayCellOfst[10]=15 cells (4 PI)
8982 11:45:42.264719 u2DelayCellOfst[11]=3 cells (1 PI)
8983 11:45:42.268181 u2DelayCellOfst[12]=18 cells (5 PI)
8984 11:45:42.271553 u2DelayCellOfst[13]=15 cells (4 PI)
8985 11:45:42.274584 u2DelayCellOfst[14]=18 cells (5 PI)
8986 11:45:42.277715 u2DelayCellOfst[15]=18 cells (5 PI)
8987 11:45:42.284567 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8988 11:45:42.287626 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8989 11:45:42.287714 DramC Write-DBI on
8990 11:45:42.287783 ==
8991 11:45:42.291446 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 11:45:42.297893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 11:45:42.297970 ==
8994 11:45:42.298039
8995 11:45:42.298104
8996 11:45:42.298164 TX Vref Scan disable
8997 11:45:42.301800 == TX Byte 0 ==
8998 11:45:42.305032 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8999 11:45:42.308589 == TX Byte 1 ==
9000 11:45:42.311845 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9001 11:45:42.314954 DramC Write-DBI off
9002 11:45:42.315039
9003 11:45:42.315103 [DATLAT]
9004 11:45:42.315163 Freq=1600, CH1 RK1
9005 11:45:42.315228
9006 11:45:42.318168 DATLAT Default: 0xf
9007 11:45:42.318251 0, 0xFFFF, sum = 0
9008 11:45:42.321311 1, 0xFFFF, sum = 0
9009 11:45:42.325050 2, 0xFFFF, sum = 0
9010 11:45:42.325136 3, 0xFFFF, sum = 0
9011 11:45:42.328564 4, 0xFFFF, sum = 0
9012 11:45:42.328636 5, 0xFFFF, sum = 0
9013 11:45:42.331565 6, 0xFFFF, sum = 0
9014 11:45:42.331636 7, 0xFFFF, sum = 0
9015 11:45:42.334982 8, 0xFFFF, sum = 0
9016 11:45:42.335056 9, 0xFFFF, sum = 0
9017 11:45:42.337799 10, 0xFFFF, sum = 0
9018 11:45:42.337873 11, 0xFFFF, sum = 0
9019 11:45:42.341182 12, 0xFFFF, sum = 0
9020 11:45:42.341258 13, 0xFFFF, sum = 0
9021 11:45:42.344703 14, 0x0, sum = 1
9022 11:45:42.344783 15, 0x0, sum = 2
9023 11:45:42.347890 16, 0x0, sum = 3
9024 11:45:42.347970 17, 0x0, sum = 4
9025 11:45:42.351254 best_step = 15
9026 11:45:42.351328
9027 11:45:42.351390 ==
9028 11:45:42.354460 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 11:45:42.357778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 11:45:42.357853 ==
9031 11:45:42.361124 RX Vref Scan: 0
9032 11:45:42.361196
9033 11:45:42.361256 RX Vref 0 -> 0, step: 1
9034 11:45:42.361323
9035 11:45:42.364437 RX Delay 11 -> 252, step: 4
9036 11:45:42.371190 iDelay=203, Bit 0, Center 140 (91 ~ 190) 100
9037 11:45:42.374639 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9038 11:45:42.377559 iDelay=203, Bit 2, Center 122 (71 ~ 174) 104
9039 11:45:42.380718 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9040 11:45:42.384731 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9041 11:45:42.391025 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9042 11:45:42.394310 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9043 11:45:42.397251 iDelay=203, Bit 7, Center 132 (79 ~ 186) 108
9044 11:45:42.400588 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9045 11:45:42.404174 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9046 11:45:42.410487 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9047 11:45:42.414080 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9048 11:45:42.417288 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9049 11:45:42.420511 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9050 11:45:42.427103 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9051 11:45:42.430321 iDelay=203, Bit 15, Center 136 (79 ~ 194) 116
9052 11:45:42.430398 ==
9053 11:45:42.434102 Dram Type= 6, Freq= 0, CH_1, rank 1
9054 11:45:42.437324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9055 11:45:42.437399 ==
9056 11:45:42.437498 DQS Delay:
9057 11:45:42.440809 DQS0 = 0, DQS1 = 0
9058 11:45:42.440877 DQM Delay:
9059 11:45:42.443702 DQM0 = 134, DQM1 = 126
9060 11:45:42.443770 DQ Delay:
9061 11:45:42.447092 DQ0 =140, DQ1 =126, DQ2 =122, DQ3 =132
9062 11:45:42.450240 DQ4 =134, DQ5 =144, DQ6 =148, DQ7 =132
9063 11:45:42.453586 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9064 11:45:42.460047 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =136
9065 11:45:42.460126
9066 11:45:42.460188
9067 11:45:42.460245
9068 11:45:42.463933 [DramC_TX_OE_Calibration] TA2
9069 11:45:42.464002 Original DQ_B0 (3 6) =30, OEN = 27
9070 11:45:42.466858 Original DQ_B1 (3 6) =30, OEN = 27
9071 11:45:42.469915 24, 0x0, End_B0=24 End_B1=24
9072 11:45:42.473382 25, 0x0, End_B0=25 End_B1=25
9073 11:45:42.476450 26, 0x0, End_B0=26 End_B1=26
9074 11:45:42.480015 27, 0x0, End_B0=27 End_B1=27
9075 11:45:42.480122 28, 0x0, End_B0=28 End_B1=28
9076 11:45:42.483442 29, 0x0, End_B0=29 End_B1=29
9077 11:45:42.486823 30, 0x0, End_B0=30 End_B1=30
9078 11:45:42.489939 31, 0x4141, End_B0=30 End_B1=30
9079 11:45:42.493209 Byte0 end_step=30 best_step=27
9080 11:45:42.493310 Byte1 end_step=30 best_step=27
9081 11:45:42.496759 Byte0 TX OE(2T, 0.5T) = (3, 3)
9082 11:45:42.499690 Byte1 TX OE(2T, 0.5T) = (3, 3)
9083 11:45:42.499784
9084 11:45:42.499871
9085 11:45:42.509711 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9086 11:45:42.509811 CH1 RK1: MR19=303, MR18=B07
9087 11:45:42.516297 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9088 11:45:42.519832 [RxdqsGatingPostProcess] freq 1600
9089 11:45:42.526444 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9090 11:45:42.529737 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 11:45:42.532929 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 11:45:42.536188 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 11:45:42.539466 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 11:45:42.539547 best DQS0 dly(2T, 0.5T) = (1, 1)
9095 11:45:42.542684 best DQS1 dly(2T, 0.5T) = (1, 1)
9096 11:45:42.546410 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9097 11:45:42.549447 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9098 11:45:42.553086 Pre-setting of DQS Precalculation
9099 11:45:42.559248 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9100 11:45:42.565747 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9101 11:45:42.572240 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 11:45:42.572322
9103 11:45:42.572387
9104 11:45:42.575660 [Calibration Summary] 3200 Mbps
9105 11:45:42.575766 CH 0, Rank 0
9106 11:45:42.579134 SW Impedance : PASS
9107 11:45:42.582034 DUTY Scan : NO K
9108 11:45:42.582119 ZQ Calibration : PASS
9109 11:45:42.585453 Jitter Meter : NO K
9110 11:45:42.588947 CBT Training : PASS
9111 11:45:42.589046 Write leveling : PASS
9112 11:45:42.592201 RX DQS gating : PASS
9113 11:45:42.595285 RX DQ/DQS(RDDQC) : PASS
9114 11:45:42.595368 TX DQ/DQS : PASS
9115 11:45:42.598526 RX DATLAT : PASS
9116 11:45:42.601980 RX DQ/DQS(Engine): PASS
9117 11:45:42.602062 TX OE : PASS
9118 11:45:42.605223 All Pass.
9119 11:45:42.605344
9120 11:45:42.605478 CH 0, Rank 1
9121 11:45:42.608988 SW Impedance : PASS
9122 11:45:42.609156 DUTY Scan : NO K
9123 11:45:42.611984 ZQ Calibration : PASS
9124 11:45:42.615361 Jitter Meter : NO K
9125 11:45:42.615444 CBT Training : PASS
9126 11:45:42.618684 Write leveling : PASS
9127 11:45:42.621569 RX DQS gating : PASS
9128 11:45:42.621654 RX DQ/DQS(RDDQC) : PASS
9129 11:45:42.625274 TX DQ/DQS : PASS
9130 11:45:42.628601 RX DATLAT : PASS
9131 11:45:42.628709 RX DQ/DQS(Engine): PASS
9132 11:45:42.631709 TX OE : PASS
9133 11:45:42.631817 All Pass.
9134 11:45:42.631883
9135 11:45:42.634912 CH 1, Rank 0
9136 11:45:42.634983 SW Impedance : PASS
9137 11:45:42.638428 DUTY Scan : NO K
9138 11:45:42.641444 ZQ Calibration : PASS
9139 11:45:42.641555 Jitter Meter : NO K
9140 11:45:42.645053 CBT Training : PASS
9141 11:45:42.645135 Write leveling : PASS
9142 11:45:42.648112 RX DQS gating : PASS
9143 11:45:42.651521 RX DQ/DQS(RDDQC) : PASS
9144 11:45:42.651601 TX DQ/DQS : PASS
9145 11:45:42.654452 RX DATLAT : PASS
9146 11:45:42.658016 RX DQ/DQS(Engine): PASS
9147 11:45:42.658096 TX OE : PASS
9148 11:45:42.661367 All Pass.
9149 11:45:42.661474
9150 11:45:42.661538 CH 1, Rank 1
9151 11:45:42.664763 SW Impedance : PASS
9152 11:45:42.664844 DUTY Scan : NO K
9153 11:45:42.667653 ZQ Calibration : PASS
9154 11:45:42.670926 Jitter Meter : NO K
9155 11:45:42.671053 CBT Training : PASS
9156 11:45:42.674461 Write leveling : PASS
9157 11:45:42.677555 RX DQS gating : PASS
9158 11:45:42.677631 RX DQ/DQS(RDDQC) : PASS
9159 11:45:42.680885 TX DQ/DQS : PASS
9160 11:45:42.684554 RX DATLAT : PASS
9161 11:45:42.684650 RX DQ/DQS(Engine): PASS
9162 11:45:42.687618 TX OE : PASS
9163 11:45:42.687717 All Pass.
9164 11:45:42.687806
9165 11:45:42.690751 DramC Write-DBI on
9166 11:45:42.694498 PER_BANK_REFRESH: Hybrid Mode
9167 11:45:42.694662 TX_TRACKING: ON
9168 11:45:42.704121 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9169 11:45:42.710629 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9170 11:45:42.717567 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9171 11:45:42.723682 [FAST_K] Save calibration result to emmc
9172 11:45:42.723762 sync common calibartion params.
9173 11:45:42.727186 sync cbt_mode0:1, 1:1
9174 11:45:42.730754 dram_init: ddr_geometry: 2
9175 11:45:42.730825 dram_init: ddr_geometry: 2
9176 11:45:42.733863 dram_init: ddr_geometry: 2
9177 11:45:42.736960 0:dram_rank_size:100000000
9178 11:45:42.740649 1:dram_rank_size:100000000
9179 11:45:42.744010 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9180 11:45:42.747283 DFS_SHUFFLE_HW_MODE: ON
9181 11:45:42.750529 dramc_set_vcore_voltage set vcore to 725000
9182 11:45:42.754023 Read voltage for 1600, 0
9183 11:45:42.754104 Vio18 = 0
9184 11:45:42.756972 Vcore = 725000
9185 11:45:42.757084 Vdram = 0
9186 11:45:42.757177 Vddq = 0
9187 11:45:42.757265 Vmddr = 0
9188 11:45:42.760578 switch to 3200 Mbps bootup
9189 11:45:42.763991 [DramcRunTimeConfig]
9190 11:45:42.764091 PHYPLL
9191 11:45:42.766990 DPM_CONTROL_AFTERK: ON
9192 11:45:42.767065 PER_BANK_REFRESH: ON
9193 11:45:42.770351 REFRESH_OVERHEAD_REDUCTION: ON
9194 11:45:42.773382 CMD_PICG_NEW_MODE: OFF
9195 11:45:42.773486 XRTWTW_NEW_MODE: ON
9196 11:45:42.777006 XRTRTR_NEW_MODE: ON
9197 11:45:42.777117 TX_TRACKING: ON
9198 11:45:42.780007 RDSEL_TRACKING: OFF
9199 11:45:42.780087 DQS Precalculation for DVFS: ON
9200 11:45:42.783830 RX_TRACKING: OFF
9201 11:45:42.783910 HW_GATING DBG: ON
9202 11:45:42.787019 ZQCS_ENABLE_LP4: ON
9203 11:45:42.790212 RX_PICG_NEW_MODE: ON
9204 11:45:42.790292 TX_PICG_NEW_MODE: ON
9205 11:45:42.793665 ENABLE_RX_DCM_DPHY: ON
9206 11:45:42.796553 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9207 11:45:42.800069 DUMMY_READ_FOR_TRACKING: OFF
9208 11:45:42.800152 !!! SPM_CONTROL_AFTERK: OFF
9209 11:45:42.803268 !!! SPM could not control APHY
9210 11:45:42.806918 IMPEDANCE_TRACKING: ON
9211 11:45:42.807007 TEMP_SENSOR: ON
9212 11:45:42.809839 HW_SAVE_FOR_SR: OFF
9213 11:45:42.812878 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9214 11:45:42.816134 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9215 11:45:42.816211 Read ODT Tracking: ON
9216 11:45:42.819352 Refresh Rate DeBounce: ON
9217 11:45:42.822744 DFS_NO_QUEUE_FLUSH: ON
9218 11:45:42.827257 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9219 11:45:42.827338 ENABLE_DFS_RUNTIME_MRW: OFF
9220 11:45:42.829208 DDR_RESERVE_NEW_MODE: ON
9221 11:45:42.832824 MR_CBT_SWITCH_FREQ: ON
9222 11:45:42.832905 =========================
9223 11:45:42.852992 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9224 11:45:42.856259 dram_init: ddr_geometry: 2
9225 11:45:42.874531 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9226 11:45:42.877786 dram_init: dram init end (result: 0)
9227 11:45:42.884442 DRAM-K: Full calibration passed in 24692 msecs
9228 11:45:42.887949 MRC: failed to locate region type 0.
9229 11:45:42.888025 DRAM rank0 size:0x100000000,
9230 11:45:42.891146 DRAM rank1 size=0x100000000
9231 11:45:42.900544 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9232 11:45:42.910505 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9233 11:45:42.916930 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9234 11:45:42.923517 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9235 11:45:42.923593 DRAM rank0 size:0x100000000,
9236 11:45:42.927143 DRAM rank1 size=0x100000000
9237 11:45:42.927214 CBMEM:
9238 11:45:42.930321 IMD: root @ 0xfffff000 254 entries.
9239 11:45:42.933816 IMD: root @ 0xffffec00 62 entries.
9240 11:45:42.939863 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9241 11:45:42.943220 WARNING: RO_VPD is uninitialized or empty.
9242 11:45:42.946581 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9243 11:45:42.954722 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9244 11:45:42.967514 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9245 11:45:42.978854 BS: romstage times (exec / console): total (unknown) / 24178 ms
9246 11:45:42.978959
9247 11:45:42.979050
9248 11:45:42.988650 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9249 11:45:42.992062 ARM64: Exception handlers installed.
9250 11:45:42.995180 ARM64: Testing exception
9251 11:45:42.999039 ARM64: Done test exception
9252 11:45:42.999138 Enumerating buses...
9253 11:45:43.002108 Show all devs... Before device enumeration.
9254 11:45:43.005365 Root Device: enabled 1
9255 11:45:43.008464 CPU_CLUSTER: 0: enabled 1
9256 11:45:43.008569 CPU: 00: enabled 1
9257 11:45:43.011830 Compare with tree...
9258 11:45:43.011903 Root Device: enabled 1
9259 11:45:43.015142 CPU_CLUSTER: 0: enabled 1
9260 11:45:43.018877 CPU: 00: enabled 1
9261 11:45:43.018957 Root Device scanning...
9262 11:45:43.021595 scan_static_bus for Root Device
9263 11:45:43.025045 CPU_CLUSTER: 0 enabled
9264 11:45:43.028078 scan_static_bus for Root Device done
9265 11:45:43.031894 scan_bus: bus Root Device finished in 8 msecs
9266 11:45:43.031974 done
9267 11:45:43.038059 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9268 11:45:43.041965 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9269 11:45:43.047893 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9270 11:45:43.051390 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9271 11:45:43.054660 Allocating resources...
9272 11:45:43.058234 Reading resources...
9273 11:45:43.061225 Root Device read_resources bus 0 link: 0
9274 11:45:43.064875 DRAM rank0 size:0x100000000,
9275 11:45:43.064973 DRAM rank1 size=0x100000000
9276 11:45:43.068062 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9277 11:45:43.071204 CPU: 00 missing read_resources
9278 11:45:43.077716 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9279 11:45:43.081197 Root Device read_resources bus 0 link: 0 done
9280 11:45:43.084255 Done reading resources.
9281 11:45:43.087684 Show resources in subtree (Root Device)...After reading.
9282 11:45:43.091135 Root Device child on link 0 CPU_CLUSTER: 0
9283 11:45:43.094444 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 11:45:43.104190 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 11:45:43.104276 CPU: 00
9286 11:45:43.107340 Root Device assign_resources, bus 0 link: 0
9287 11:45:43.110980 CPU_CLUSTER: 0 missing set_resources
9288 11:45:43.117628 Root Device assign_resources, bus 0 link: 0 done
9289 11:45:43.117712 Done setting resources.
9290 11:45:43.123896 Show resources in subtree (Root Device)...After assigning values.
9291 11:45:43.127329 Root Device child on link 0 CPU_CLUSTER: 0
9292 11:45:43.130269 CPU_CLUSTER: 0 child on link 0 CPU: 00
9293 11:45:43.140211 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9294 11:45:43.140297 CPU: 00
9295 11:45:43.143573 Done allocating resources.
9296 11:45:43.150295 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9297 11:45:43.150382 Enabling resources...
9298 11:45:43.153771 done.
9299 11:45:43.156879 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9300 11:45:43.160368 Initializing devices...
9301 11:45:43.160510 Root Device init
9302 11:45:43.163257 init hardware done!
9303 11:45:43.163376 0x00000018: ctrlr->caps
9304 11:45:43.166592 52.000 MHz: ctrlr->f_max
9305 11:45:43.169901 0.400 MHz: ctrlr->f_min
9306 11:45:43.169990 0x40ff8080: ctrlr->voltages
9307 11:45:43.173246 sclk: 390625
9308 11:45:43.173388 Bus Width = 1
9309 11:45:43.176418 sclk: 390625
9310 11:45:43.176521 Bus Width = 1
9311 11:45:43.179729 Early init status = 3
9312 11:45:43.183247 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9313 11:45:43.188237 in-header: 03 fc 00 00 01 00 00 00
9314 11:45:43.191353 in-data: 00
9315 11:45:43.195099 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9316 11:45:43.199382 in-header: 03 fd 00 00 00 00 00 00
9317 11:45:43.202738 in-data:
9318 11:45:43.206169 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9319 11:45:43.211004 in-header: 03 fc 00 00 01 00 00 00
9320 11:45:43.213515 in-data: 00
9321 11:45:43.217164 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9322 11:45:43.224376 in-header: 03 fd 00 00 00 00 00 00
9323 11:45:43.227194 in-data:
9324 11:45:43.230561 [SSUSB] Setting up USB HOST controller...
9325 11:45:43.233701 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9326 11:45:43.237973 [SSUSB] phy power-on done.
9327 11:45:43.240778 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9328 11:45:43.246757 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9329 11:45:43.250501 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9330 11:45:43.257025 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9331 11:45:43.263148 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9332 11:45:43.269831 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9333 11:45:43.276757 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9334 11:45:43.283318 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9335 11:45:43.286274 SPM: binary array size = 0x9dc
9336 11:45:43.293077 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9337 11:45:43.295991 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9338 11:45:43.303050 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9339 11:45:43.309196 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9340 11:45:43.312860 configure_display: Starting display init
9341 11:45:43.347786 anx7625_power_on_init: Init interface.
9342 11:45:43.350678 anx7625_disable_pd_protocol: Disabled PD feature.
9343 11:45:43.354005 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9344 11:45:43.381968 anx7625_start_dp_work: Secure OCM version=00
9345 11:45:43.385019 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9346 11:45:43.399719 sp_tx_get_edid_block: EDID Block = 1
9347 11:45:43.502668 Extracted contents:
9348 11:45:43.505349 header: 00 ff ff ff ff ff ff 00
9349 11:45:43.508945 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9350 11:45:43.512350 version: 01 04
9351 11:45:43.515746 basic params: 95 1f 11 78 0a
9352 11:45:43.518644 chroma info: 76 90 94 55 54 90 27 21 50 54
9353 11:45:43.522179 established: 00 00 00
9354 11:45:43.529074 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9355 11:45:43.531912 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9356 11:45:43.538840 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 11:45:43.545065 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9358 11:45:43.552021 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9359 11:45:43.555421 extensions: 00
9360 11:45:43.555500 checksum: fb
9361 11:45:43.555564
9362 11:45:43.558702 Manufacturer: IVO Model 57d Serial Number 0
9363 11:45:43.562026 Made week 0 of 2020
9364 11:45:43.565287 EDID version: 1.4
9365 11:45:43.565406 Digital display
9366 11:45:43.568594 6 bits per primary color channel
9367 11:45:43.568691 DisplayPort interface
9368 11:45:43.571716 Maximum image size: 31 cm x 17 cm
9369 11:45:43.574776 Gamma: 220%
9370 11:45:43.574851 Check DPMS levels
9371 11:45:43.581235 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9372 11:45:43.584831 First detailed timing is preferred timing
9373 11:45:43.584931 Established timings supported:
9374 11:45:43.588058 Standard timings supported:
9375 11:45:43.591126 Detailed timings
9376 11:45:43.594421 Hex of detail: 383680a07038204018303c0035ae10000019
9377 11:45:43.601140 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9378 11:45:43.604414 0780 0798 07c8 0820 hborder 0
9379 11:45:43.607676 0438 043b 0447 0458 vborder 0
9380 11:45:43.610987 -hsync -vsync
9381 11:45:43.611085 Did detailed timing
9382 11:45:43.618025 Hex of detail: 000000000000000000000000000000000000
9383 11:45:43.621381 Manufacturer-specified data, tag 0
9384 11:45:43.624413 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9385 11:45:43.627656 ASCII string: InfoVision
9386 11:45:43.631130 Hex of detail: 000000fe00523134304e574635205248200a
9387 11:45:43.634317 ASCII string: R140NWF5 RH
9388 11:45:43.634428 Checksum
9389 11:45:43.637984 Checksum: 0xfb (valid)
9390 11:45:43.640893 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9391 11:45:43.644274 DSI data_rate: 832800000 bps
9392 11:45:43.650878 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9393 11:45:43.653904 anx7625_parse_edid: pixelclock(138800).
9394 11:45:43.657424 hactive(1920), hsync(48), hfp(24), hbp(88)
9395 11:45:43.660837 vactive(1080), vsync(12), vfp(3), vbp(17)
9396 11:45:43.663712 anx7625_dsi_config: config dsi.
9397 11:45:43.670924 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9398 11:45:43.684506 anx7625_dsi_config: success to config DSI
9399 11:45:43.687977 anx7625_dp_start: MIPI phy setup OK.
9400 11:45:43.690692 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9401 11:45:43.694212 mtk_ddp_mode_set invalid vrefresh 60
9402 11:45:43.697565 main_disp_path_setup
9403 11:45:43.697645 ovl_layer_smi_id_en
9404 11:45:43.700775 ovl_layer_smi_id_en
9405 11:45:43.700855 ccorr_config
9406 11:45:43.700953 aal_config
9407 11:45:43.704055 gamma_config
9408 11:45:43.704194 postmask_config
9409 11:45:43.707169 dither_config
9410 11:45:43.710725 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9411 11:45:43.717655 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9412 11:45:43.720568 Root Device init finished in 556 msecs
9413 11:45:43.723978 CPU_CLUSTER: 0 init
9414 11:45:43.731115 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9415 11:45:43.737424 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9416 11:45:43.737521 APU_MBOX 0x190000b0 = 0x10001
9417 11:45:43.741074 APU_MBOX 0x190001b0 = 0x10001
9418 11:45:43.743634 APU_MBOX 0x190005b0 = 0x10001
9419 11:45:43.746958 APU_MBOX 0x190006b0 = 0x10001
9420 11:45:43.753561 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9421 11:45:43.763591 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9422 11:45:43.775904 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9423 11:45:43.782125 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9424 11:45:43.794125 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9425 11:45:43.803400 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9426 11:45:43.806194 CPU_CLUSTER: 0 init finished in 81 msecs
9427 11:45:43.809990 Devices initialized
9428 11:45:43.812813 Show all devs... After init.
9429 11:45:43.812923 Root Device: enabled 1
9430 11:45:43.816658 CPU_CLUSTER: 0: enabled 1
9431 11:45:43.820120 CPU: 00: enabled 1
9432 11:45:43.823336 BS: BS_DEV_INIT run times (exec / console): 215 / 447 ms
9433 11:45:43.826457 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9434 11:45:43.829462 ELOG: NV offset 0x57f000 size 0x1000
9435 11:45:43.836176 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9436 11:45:43.843314 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9437 11:45:43.846299 ELOG: Event(17) added with size 13 at 2023-11-24 11:45:44 UTC
9438 11:45:43.852612 out: cmd=0x121: 03 db 21 01 00 00 00 00
9439 11:45:43.855898 in-header: 03 7e 00 00 2c 00 00 00
9440 11:45:43.865790 in-data: e1 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9441 11:45:43.872782 ELOG: Event(A1) added with size 10 at 2023-11-24 11:45:44 UTC
9442 11:45:43.878888 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9443 11:45:43.886060 ELOG: Event(A0) added with size 9 at 2023-11-24 11:45:44 UTC
9444 11:45:43.888827 elog_add_boot_reason: Logged dev mode boot
9445 11:45:43.895537 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9446 11:45:43.895621 Finalize devices...
9447 11:45:43.899001 Devices finalized
9448 11:45:43.902811 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9449 11:45:43.905641 Writing coreboot table at 0xffe64000
9450 11:45:43.908764 0. 000000000010a000-0000000000113fff: RAMSTAGE
9451 11:45:43.915451 1. 0000000040000000-00000000400fffff: RAM
9452 11:45:43.918603 2. 0000000040100000-000000004032afff: RAMSTAGE
9453 11:45:43.921890 3. 000000004032b000-00000000545fffff: RAM
9454 11:45:43.925668 4. 0000000054600000-000000005465ffff: BL31
9455 11:45:43.928714 5. 0000000054660000-00000000ffe63fff: RAM
9456 11:45:43.935538 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9457 11:45:43.938479 7. 0000000100000000-000000023fffffff: RAM
9458 11:45:43.941821 Passing 5 GPIOs to payload:
9459 11:45:43.945605 NAME | PORT | POLARITY | VALUE
9460 11:45:43.951993 EC in RW | 0x000000aa | low | undefined
9461 11:45:43.954914 EC interrupt | 0x00000005 | low | undefined
9462 11:45:43.958309 TPM interrupt | 0x000000ab | high | undefined
9463 11:45:43.964843 SD card detect | 0x00000011 | high | undefined
9464 11:45:43.968811 speaker enable | 0x00000093 | high | undefined
9465 11:45:43.971443 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9466 11:45:43.974762 in-header: 03 f9 00 00 02 00 00 00
9467 11:45:43.978398 in-data: 02 00
9468 11:45:43.981283 ADC[4]: Raw value=903400 ID=7
9469 11:45:43.981384 ADC[3]: Raw value=214021 ID=1
9470 11:45:43.984807 RAM Code: 0x71
9471 11:45:43.988065 ADC[6]: Raw value=75036 ID=0
9472 11:45:43.991686 ADC[5]: Raw value=213652 ID=1
9473 11:45:43.991763 SKU Code: 0x1
9474 11:45:43.997939 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9475 11:45:43.998018 coreboot table: 964 bytes.
9476 11:45:44.001645 IMD ROOT 0. 0xfffff000 0x00001000
9477 11:45:44.004621 IMD SMALL 1. 0xffffe000 0x00001000
9478 11:45:44.007945 RO MCACHE 2. 0xffffc000 0x00001104
9479 11:45:44.011227 CONSOLE 3. 0xfff7c000 0x00080000
9480 11:45:44.014760 FMAP 4. 0xfff7b000 0x00000452
9481 11:45:44.018283 TIME STAMP 5. 0xfff7a000 0x00000910
9482 11:45:44.021455 VBOOT WORK 6. 0xfff66000 0x00014000
9483 11:45:44.024766 RAMOOPS 7. 0xffe66000 0x00100000
9484 11:45:44.028074 COREBOOT 8. 0xffe64000 0x00002000
9485 11:45:44.031140 IMD small region:
9486 11:45:44.034443 IMD ROOT 0. 0xffffec00 0x00000400
9487 11:45:44.037793 VPD 1. 0xffffeb80 0x0000006c
9488 11:45:44.040994 MMC STATUS 2. 0xffffeb60 0x00000004
9489 11:45:44.044138 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9490 11:45:44.047404 Probing TPM: done!
9491 11:45:44.051120 Connected to device vid:did:rid of 1ae0:0028:00
9492 11:45:44.061957 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9493 11:45:44.065919 Initialized TPM device CR50 revision 0
9494 11:45:44.068903 Checking cr50 for pending updates
9495 11:45:44.073015 Reading cr50 TPM mode
9496 11:45:44.081617 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9497 11:45:44.088129 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9498 11:45:44.127999 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9499 11:45:44.131080 Checking segment from ROM address 0x40100000
9500 11:45:44.137833 Checking segment from ROM address 0x4010001c
9501 11:45:44.141147 Loading segment from ROM address 0x40100000
9502 11:45:44.141250 code (compression=0)
9503 11:45:44.151309 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9504 11:45:44.157878 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9505 11:45:44.157981 it's not compressed!
9506 11:45:44.164443 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9507 11:45:44.171032 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9508 11:45:44.188434 Loading segment from ROM address 0x4010001c
9509 11:45:44.188515 Entry Point 0x80000000
9510 11:45:44.192035 Loaded segments
9511 11:45:44.195526 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9512 11:45:44.201730 Jumping to boot code at 0x80000000(0xffe64000)
9513 11:45:44.208762 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9514 11:45:44.215310 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9515 11:45:44.222718 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9516 11:45:44.225991 Checking segment from ROM address 0x40100000
9517 11:45:44.229740 Checking segment from ROM address 0x4010001c
9518 11:45:44.236487 Loading segment from ROM address 0x40100000
9519 11:45:44.236593 code (compression=1)
9520 11:45:44.242801 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9521 11:45:44.252536 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9522 11:45:44.252618 using LZMA
9523 11:45:44.261620 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9524 11:45:44.268050 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9525 11:45:44.271355 Loading segment from ROM address 0x4010001c
9526 11:45:44.271436 Entry Point 0x54601000
9527 11:45:44.274735 Loaded segments
9528 11:45:44.278165 NOTICE: MT8192 bl31_setup
9529 11:45:44.285230 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9530 11:45:44.288471 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9531 11:45:44.291700 WARNING: region 0:
9532 11:45:44.295227 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 11:45:44.295309 WARNING: region 1:
9534 11:45:44.301631 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9535 11:45:44.305012 WARNING: region 2:
9536 11:45:44.308663 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9537 11:45:44.311579 WARNING: region 3:
9538 11:45:44.315356 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 11:45:44.318524 WARNING: region 4:
9540 11:45:44.324749 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 11:45:44.324830 WARNING: region 5:
9542 11:45:44.328459 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 11:45:44.331577 WARNING: region 6:
9544 11:45:44.334648 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 11:45:44.337952 WARNING: region 7:
9546 11:45:44.341238 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 11:45:44.348252 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9548 11:45:44.351647 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9549 11:45:44.354704 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9550 11:45:44.361727 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9551 11:45:44.365205 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9552 11:45:44.368253 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9553 11:45:44.374758 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9554 11:45:44.378177 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9555 11:45:44.384624 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9556 11:45:44.388067 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9557 11:45:44.391745 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9558 11:45:44.397807 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9559 11:45:44.401641 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9560 11:45:44.404436 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9561 11:45:44.411435 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9562 11:45:44.414308 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9563 11:45:44.421310 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9564 11:45:44.424588 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9565 11:45:44.427742 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9566 11:45:44.434666 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9567 11:45:44.437835 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9568 11:45:44.444267 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9569 11:45:44.447806 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9570 11:45:44.451752 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9571 11:45:44.457865 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9572 11:45:44.461149 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9573 11:45:44.467693 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9574 11:45:44.471368 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9575 11:45:44.474481 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9576 11:45:44.480826 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9577 11:45:44.483975 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9578 11:45:44.491056 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9579 11:45:44.494329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9580 11:45:44.497921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9581 11:45:44.500943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9582 11:45:44.507686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9583 11:45:44.510977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9584 11:45:44.514453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9585 11:45:44.517734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9586 11:45:44.523905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9587 11:45:44.527428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9588 11:45:44.530795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9589 11:45:44.534040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9590 11:45:44.540550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9591 11:45:44.543867 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9592 11:45:44.547042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9593 11:45:44.550540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9594 11:45:44.557176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9595 11:45:44.560605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9596 11:45:44.566994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9597 11:45:44.570330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9598 11:45:44.573636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9599 11:45:44.580222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9600 11:45:44.583881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9601 11:45:44.590906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9602 11:45:44.593979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9603 11:45:44.597032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9604 11:45:44.603848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9605 11:45:44.606953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9606 11:45:44.613728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9607 11:45:44.616957 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9608 11:45:44.623833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9609 11:45:44.626581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9610 11:45:44.633148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9611 11:45:44.636529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9612 11:45:44.643201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9613 11:45:44.646867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9614 11:45:44.649754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9615 11:45:44.656397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9616 11:45:44.659810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9617 11:45:44.666760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9618 11:45:44.669636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9619 11:45:44.676841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9620 11:45:44.679900 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9621 11:45:44.683029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9622 11:45:44.689444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9623 11:45:44.692609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9624 11:45:44.699435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9625 11:45:44.702852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9626 11:45:44.709554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9627 11:45:44.712925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9628 11:45:44.719805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9629 11:45:44.722968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9630 11:45:44.726585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9631 11:45:44.733223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9632 11:45:44.736434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9633 11:45:44.742675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9634 11:45:44.746596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9635 11:45:44.752757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9636 11:45:44.755672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9637 11:45:44.759241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9638 11:45:44.766078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9639 11:45:44.769177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9640 11:45:44.776076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9641 11:45:44.779386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9642 11:45:44.785673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9643 11:45:44.789248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9644 11:45:44.792199 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9645 11:45:44.798853 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9646 11:45:44.802489 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9647 11:45:44.805366 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9648 11:45:44.809086 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9649 11:45:44.815457 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9650 11:45:44.818725 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9651 11:45:44.825270 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9652 11:45:44.828719 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9653 11:45:44.831851 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9654 11:45:44.838668 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9655 11:45:44.842531 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9656 11:45:44.848813 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9657 11:45:44.851783 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9658 11:45:44.858765 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9659 11:45:44.861903 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9660 11:45:44.865181 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9661 11:45:44.871630 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9662 11:45:44.875003 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9663 11:45:44.878449 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9664 11:45:44.884763 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9665 11:45:44.888702 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9666 11:45:44.891568 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9667 11:45:44.898076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9668 11:45:44.901378 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9669 11:45:44.905224 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9670 11:45:44.907942 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9671 11:45:44.914856 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9672 11:45:44.918549 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9673 11:45:44.924784 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9674 11:45:44.927981 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9675 11:45:44.931456 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9676 11:45:44.937931 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9677 11:45:44.941573 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9678 11:45:44.944769 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9679 11:45:44.951362 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9680 11:45:44.954825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9681 11:45:44.961226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9682 11:45:44.964534 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9683 11:45:44.971010 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9684 11:45:44.974294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9685 11:45:44.977606 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9686 11:45:44.983971 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9687 11:45:44.987642 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9688 11:45:44.991125 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9689 11:45:44.997592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9690 11:45:45.000778 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9691 11:45:45.007419 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9692 11:45:45.010673 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9693 11:45:45.014290 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9694 11:45:45.020924 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9695 11:45:45.024157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9696 11:45:45.031167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9697 11:45:45.034567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9698 11:45:45.037683 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9699 11:45:45.044230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9700 11:45:45.047838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9701 11:45:45.050609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9702 11:45:45.057501 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9703 11:45:45.061047 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9704 11:45:45.067364 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9705 11:45:45.070731 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9706 11:45:45.074089 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9707 11:45:45.080812 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9708 11:45:45.083726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9709 11:45:45.090672 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9710 11:45:45.094167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9711 11:45:45.097034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9712 11:45:45.104136 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9713 11:45:45.106961 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9714 11:45:45.113390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9715 11:45:45.117052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9716 11:45:45.120313 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9717 11:45:45.127418 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9718 11:45:45.130393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9719 11:45:45.136767 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9720 11:45:45.140213 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9721 11:45:45.142944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9722 11:45:45.149775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9723 11:45:45.153017 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9724 11:45:45.159441 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9725 11:45:45.163283 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9726 11:45:45.166178 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9727 11:45:45.172866 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9728 11:45:45.176257 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9729 11:45:45.182686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9730 11:45:45.186398 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9731 11:45:45.192426 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9732 11:45:45.195685 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9733 11:45:45.199285 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9734 11:45:45.205797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9735 11:45:45.208948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9736 11:45:45.215501 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9737 11:45:45.218899 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9738 11:45:45.222092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9739 11:45:45.228634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9740 11:45:45.231967 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9741 11:45:45.238592 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9742 11:45:45.242102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9743 11:45:45.248652 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9744 11:45:45.251889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9745 11:45:45.255391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9746 11:45:45.262274 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9747 11:45:45.265719 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9748 11:45:45.271475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9749 11:45:45.274840 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9750 11:45:45.281405 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9751 11:45:45.285036 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9752 11:45:45.288501 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9753 11:45:45.294568 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9754 11:45:45.297880 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9755 11:45:45.304689 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9756 11:45:45.307916 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9757 11:45:45.314253 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9758 11:45:45.318010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9759 11:45:45.321608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9760 11:45:45.327755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9761 11:45:45.331299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9762 11:45:45.337765 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9763 11:45:45.341041 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9764 11:45:45.347573 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9765 11:45:45.351239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9766 11:45:45.354196 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9767 11:45:45.360407 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9768 11:45:45.363956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9769 11:45:45.370569 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9770 11:45:45.373966 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9771 11:45:45.380155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9772 11:45:45.383586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9773 11:45:45.387008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9774 11:45:45.393707 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9775 11:45:45.396879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9776 11:45:45.400062 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9777 11:45:45.406798 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9778 11:45:45.409933 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9779 11:45:45.413298 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9780 11:45:45.416875 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9781 11:45:45.423305 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9782 11:45:45.426494 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9783 11:45:45.433182 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9784 11:45:45.436497 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9785 11:45:45.439687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9786 11:45:45.446541 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9787 11:45:45.449694 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9788 11:45:45.453228 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9789 11:45:45.459863 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9790 11:45:45.463345 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9791 11:45:45.466515 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9792 11:45:45.472708 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9793 11:45:45.476232 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9794 11:45:45.482792 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9795 11:45:45.485967 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9796 11:45:45.489935 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9797 11:45:45.496148 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9798 11:45:45.499328 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9799 11:45:45.506326 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9800 11:45:45.509341 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9801 11:45:45.512585 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9802 11:45:45.519382 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9803 11:45:45.522703 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9804 11:45:45.526093 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9805 11:45:45.532904 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9806 11:45:45.535761 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9807 11:45:45.539222 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9808 11:45:45.545370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9809 11:45:45.548723 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9810 11:45:45.552081 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9811 11:45:45.558755 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9812 11:45:45.562014 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9813 11:45:45.568588 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9814 11:45:45.572321 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9815 11:45:45.575588 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9816 11:45:45.581923 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9817 11:45:45.585739 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9818 11:45:45.588317 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9819 11:45:45.592034 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9820 11:45:45.595617 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9821 11:45:45.602216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9822 11:45:45.605014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9823 11:45:45.608165 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9824 11:45:45.611643 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9825 11:45:45.618503 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9826 11:45:45.621873 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9827 11:45:45.624727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9828 11:45:45.631462 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9829 11:45:45.634893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9830 11:45:45.638736 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9831 11:45:45.644944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9832 11:45:45.648563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9833 11:45:45.655035 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9834 11:45:45.658450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9835 11:45:45.664797 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9836 11:45:45.667848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9837 11:45:45.671083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9838 11:45:45.678152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9839 11:45:45.680915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9840 11:45:45.687434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9841 11:45:45.690825 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9842 11:45:45.697376 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9843 11:45:45.700867 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9844 11:45:45.704330 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9845 11:45:45.710911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9846 11:45:45.713938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9847 11:45:45.720932 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9848 11:45:45.724168 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9849 11:45:45.727347 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9850 11:45:45.733828 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9851 11:45:45.737242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9852 11:45:45.744083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9853 11:45:45.747067 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9854 11:45:45.750857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9855 11:45:45.757619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9856 11:45:45.760586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9857 11:45:45.767219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9858 11:45:45.770095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9859 11:45:45.777020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9860 11:45:45.780469 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9861 11:45:45.783529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9862 11:45:45.790190 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9863 11:45:45.793977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9864 11:45:45.799857 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9865 11:45:45.803375 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9866 11:45:45.806805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9867 11:45:45.813528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9868 11:45:45.816545 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9869 11:45:45.823085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9870 11:45:45.826572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9871 11:45:45.829852 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9872 11:45:45.836225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9873 11:45:45.839483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9874 11:45:45.846511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9875 11:45:45.849759 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9876 11:45:45.856581 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9877 11:45:45.859108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9878 11:45:45.863021 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9879 11:45:45.869586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9880 11:45:45.872611 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9881 11:45:45.879443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9882 11:45:45.882820 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9883 11:45:45.889027 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9884 11:45:45.892304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9885 11:45:45.895681 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9886 11:45:45.902379 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9887 11:45:45.905391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9888 11:45:45.912143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9889 11:45:45.915410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9890 11:45:45.918982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9891 11:45:45.925177 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9892 11:45:45.928719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9893 11:45:45.935363 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9894 11:45:45.938877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9895 11:45:45.941910 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9896 11:45:45.948501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9897 11:45:45.952340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9898 11:45:45.958523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9899 11:45:45.961829 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9900 11:45:45.965461 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9901 11:45:45.971703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9902 11:45:45.975330 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9903 11:45:45.981647 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9904 11:45:45.984777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9905 11:45:45.991810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9906 11:45:45.994645 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9907 11:45:46.001429 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9908 11:45:46.005045 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9909 11:45:46.008069 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9910 11:45:46.014664 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9911 11:45:46.018026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9912 11:45:46.024540 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9913 11:45:46.028087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9914 11:45:46.034305 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9915 11:45:46.038258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9916 11:45:46.044413 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9917 11:45:46.047720 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9918 11:45:46.051261 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9919 11:45:46.057849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9920 11:45:46.060827 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9921 11:45:46.067327 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9922 11:45:46.070796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9923 11:45:46.077475 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9924 11:45:46.080502 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9925 11:45:46.087882 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9926 11:45:46.090565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9927 11:45:46.094483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9928 11:45:46.100568 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9929 11:45:46.103620 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9930 11:45:46.110956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9931 11:45:46.113647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9932 11:45:46.120283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9933 11:45:46.124096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9934 11:45:46.130683 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9935 11:45:46.133778 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9936 11:45:46.136942 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9937 11:45:46.143340 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9938 11:45:46.146735 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9939 11:45:46.153510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9940 11:45:46.156833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9941 11:45:46.163166 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9942 11:45:46.166500 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9943 11:45:46.173049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9944 11:45:46.176268 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9945 11:45:46.183250 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9946 11:45:46.186092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9947 11:45:46.189567 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9948 11:45:46.196277 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9949 11:45:46.200009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9950 11:45:46.202621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9951 11:45:46.209141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9952 11:45:46.212423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9953 11:45:46.219570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9954 11:45:46.222971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9955 11:45:46.229023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9956 11:45:46.232578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9957 11:45:46.239446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9958 11:45:46.242666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9959 11:45:46.249123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9960 11:45:46.252316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9961 11:45:46.258987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9962 11:45:46.262318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9963 11:45:46.269233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9964 11:45:46.272256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9965 11:45:46.278593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9966 11:45:46.282244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9967 11:45:46.288919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9968 11:45:46.292489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9969 11:45:46.298445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9970 11:45:46.301899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9971 11:45:46.308947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9972 11:45:46.311911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9973 11:45:46.318601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9974 11:45:46.321975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9975 11:45:46.328284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9976 11:45:46.332105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9977 11:45:46.338441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9978 11:45:46.341351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9979 11:45:46.348324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9980 11:45:46.351906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9981 11:45:46.358026 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9982 11:45:46.358108 INFO: [APUAPC] vio 0
9983 11:45:46.365341 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9984 11:45:46.368478 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9985 11:45:46.371685 INFO: [APUAPC] D0_APC_0: 0x400510
9986 11:45:46.375045 INFO: [APUAPC] D0_APC_1: 0x0
9987 11:45:46.378145 INFO: [APUAPC] D0_APC_2: 0x1540
9988 11:45:46.381357 INFO: [APUAPC] D0_APC_3: 0x0
9989 11:45:46.384700 INFO: [APUAPC] D1_APC_0: 0xffffffff
9990 11:45:46.387675 INFO: [APUAPC] D1_APC_1: 0xffffffff
9991 11:45:46.391006 INFO: [APUAPC] D1_APC_2: 0x3fffff
9992 11:45:46.394842 INFO: [APUAPC] D1_APC_3: 0x0
9993 11:45:46.397815 INFO: [APUAPC] D2_APC_0: 0xffffffff
9994 11:45:46.400818 INFO: [APUAPC] D2_APC_1: 0xffffffff
9995 11:45:46.404558 INFO: [APUAPC] D2_APC_2: 0x3fffff
9996 11:45:46.407461 INFO: [APUAPC] D2_APC_3: 0x0
9997 11:45:46.411155 INFO: [APUAPC] D3_APC_0: 0xffffffff
9998 11:45:46.414139 INFO: [APUAPC] D3_APC_1: 0xffffffff
9999 11:45:46.417256 INFO: [APUAPC] D3_APC_2: 0x3fffff
10000 11:45:46.420461 INFO: [APUAPC] D3_APC_3: 0x0
10001 11:45:46.424007 INFO: [APUAPC] D4_APC_0: 0xffffffff
10002 11:45:46.426967 INFO: [APUAPC] D4_APC_1: 0xffffffff
10003 11:45:46.430647 INFO: [APUAPC] D4_APC_2: 0x3fffff
10004 11:45:46.434190 INFO: [APUAPC] D4_APC_3: 0x0
10005 11:45:46.436926 INFO: [APUAPC] D5_APC_0: 0xffffffff
10006 11:45:46.440427 INFO: [APUAPC] D5_APC_1: 0xffffffff
10007 11:45:46.443802 INFO: [APUAPC] D5_APC_2: 0x3fffff
10008 11:45:46.446790 INFO: [APUAPC] D5_APC_3: 0x0
10009 11:45:46.450451 INFO: [APUAPC] D6_APC_0: 0xffffffff
10010 11:45:46.453718 INFO: [APUAPC] D6_APC_1: 0xffffffff
10011 11:45:46.457108 INFO: [APUAPC] D6_APC_2: 0x3fffff
10012 11:45:46.460282 INFO: [APUAPC] D6_APC_3: 0x0
10013 11:45:46.463598 INFO: [APUAPC] D7_APC_0: 0xffffffff
10014 11:45:46.466864 INFO: [APUAPC] D7_APC_1: 0xffffffff
10015 11:45:46.470362 INFO: [APUAPC] D7_APC_2: 0x3fffff
10016 11:45:46.473064 INFO: [APUAPC] D7_APC_3: 0x0
10017 11:45:46.476599 INFO: [APUAPC] D8_APC_0: 0xffffffff
10018 11:45:46.479614 INFO: [APUAPC] D8_APC_1: 0xffffffff
10019 11:45:46.483178 INFO: [APUAPC] D8_APC_2: 0x3fffff
10020 11:45:46.483276 INFO: [APUAPC] D8_APC_3: 0x0
10021 11:45:46.490024 INFO: [APUAPC] D9_APC_0: 0xffffffff
10022 11:45:46.493238 INFO: [APUAPC] D9_APC_1: 0xffffffff
10023 11:45:46.496358 INFO: [APUAPC] D9_APC_2: 0x3fffff
10024 11:45:46.496454 INFO: [APUAPC] D9_APC_3: 0x0
10025 11:45:46.503241 INFO: [APUAPC] D10_APC_0: 0xffffffff
10026 11:45:46.506011 INFO: [APUAPC] D10_APC_1: 0xffffffff
10027 11:45:46.509354 INFO: [APUAPC] D10_APC_2: 0x3fffff
10028 11:45:46.509462 INFO: [APUAPC] D10_APC_3: 0x0
10029 11:45:46.516659 INFO: [APUAPC] D11_APC_0: 0xffffffff
10030 11:45:46.519645 INFO: [APUAPC] D11_APC_1: 0xffffffff
10031 11:45:46.522651 INFO: [APUAPC] D11_APC_2: 0x3fffff
10032 11:45:46.526022 INFO: [APUAPC] D11_APC_3: 0x0
10033 11:45:46.529613 INFO: [APUAPC] D12_APC_0: 0xffffffff
10034 11:45:46.532464 INFO: [APUAPC] D12_APC_1: 0xffffffff
10035 11:45:46.535771 INFO: [APUAPC] D12_APC_2: 0x3fffff
10036 11:45:46.538961 INFO: [APUAPC] D12_APC_3: 0x0
10037 11:45:46.542273 INFO: [APUAPC] D13_APC_0: 0xffffffff
10038 11:45:46.545437 INFO: [APUAPC] D13_APC_1: 0xffffffff
10039 11:45:46.549219 INFO: [APUAPC] D13_APC_2: 0x3fffff
10040 11:45:46.552212 INFO: [APUAPC] D13_APC_3: 0x0
10041 11:45:46.555360 INFO: [APUAPC] D14_APC_0: 0xffffffff
10042 11:45:46.559345 INFO: [APUAPC] D14_APC_1: 0xffffffff
10043 11:45:46.562075 INFO: [APUAPC] D14_APC_2: 0x3fffff
10044 11:45:46.566150 INFO: [APUAPC] D14_APC_3: 0x0
10045 11:45:46.568826 INFO: [APUAPC] D15_APC_0: 0xffffffff
10046 11:45:46.572743 INFO: [APUAPC] D15_APC_1: 0xffffffff
10047 11:45:46.575791 INFO: [APUAPC] D15_APC_2: 0x3fffff
10048 11:45:46.578625 INFO: [APUAPC] D15_APC_3: 0x0
10049 11:45:46.582355 INFO: [APUAPC] APC_CON: 0x4
10050 11:45:46.582430 INFO: [NOCDAPC] D0_APC_0: 0x0
10051 11:45:46.585587 INFO: [NOCDAPC] D0_APC_1: 0x0
10052 11:45:46.588942 INFO: [NOCDAPC] D1_APC_0: 0x0
10053 11:45:46.592066 INFO: [NOCDAPC] D1_APC_1: 0xfff
10054 11:45:46.595740 INFO: [NOCDAPC] D2_APC_0: 0x0
10055 11:45:46.598676 INFO: [NOCDAPC] D2_APC_1: 0xfff
10056 11:45:46.602194 INFO: [NOCDAPC] D3_APC_0: 0x0
10057 11:45:46.605341 INFO: [NOCDAPC] D3_APC_1: 0xfff
10058 11:45:46.608952 INFO: [NOCDAPC] D4_APC_0: 0x0
10059 11:45:46.611953 INFO: [NOCDAPC] D4_APC_1: 0xfff
10060 11:45:46.615168 INFO: [NOCDAPC] D5_APC_0: 0x0
10061 11:45:46.615270 INFO: [NOCDAPC] D5_APC_1: 0xfff
10062 11:45:46.618346 INFO: [NOCDAPC] D6_APC_0: 0x0
10063 11:45:46.621364 INFO: [NOCDAPC] D6_APC_1: 0xfff
10064 11:45:46.625100 INFO: [NOCDAPC] D7_APC_0: 0x0
10065 11:45:46.628184 INFO: [NOCDAPC] D7_APC_1: 0xfff
10066 11:45:46.631392 INFO: [NOCDAPC] D8_APC_0: 0x0
10067 11:45:46.634676 INFO: [NOCDAPC] D8_APC_1: 0xfff
10068 11:45:46.637903 INFO: [NOCDAPC] D9_APC_0: 0x0
10069 11:45:46.641901 INFO: [NOCDAPC] D9_APC_1: 0xfff
10070 11:45:46.644760 INFO: [NOCDAPC] D10_APC_0: 0x0
10071 11:45:46.648194 INFO: [NOCDAPC] D10_APC_1: 0xfff
10072 11:45:46.651828 INFO: [NOCDAPC] D11_APC_0: 0x0
10073 11:45:46.655094 INFO: [NOCDAPC] D11_APC_1: 0xfff
10074 11:45:46.655185 INFO: [NOCDAPC] D12_APC_0: 0x0
10075 11:45:46.658427 INFO: [NOCDAPC] D12_APC_1: 0xfff
10076 11:45:46.661596 INFO: [NOCDAPC] D13_APC_0: 0x0
10077 11:45:46.664598 INFO: [NOCDAPC] D13_APC_1: 0xfff
10078 11:45:46.668024 INFO: [NOCDAPC] D14_APC_0: 0x0
10079 11:45:46.671614 INFO: [NOCDAPC] D14_APC_1: 0xfff
10080 11:45:46.674438 INFO: [NOCDAPC] D15_APC_0: 0x0
10081 11:45:46.678254 INFO: [NOCDAPC] D15_APC_1: 0xfff
10082 11:45:46.681809 INFO: [NOCDAPC] APC_CON: 0x4
10083 11:45:46.684983 INFO: [APUAPC] set_apusys_apc done
10084 11:45:46.687588 INFO: [DEVAPC] devapc_init done
10085 11:45:46.691158 INFO: GICv3 without legacy support detected.
10086 11:45:46.694503 INFO: ARM GICv3 driver initialized in EL3
10087 11:45:46.697953 INFO: Maximum SPI INTID supported: 639
10088 11:45:46.704158 INFO: BL31: Initializing runtime services
10089 11:45:46.707842 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10090 11:45:46.711223 INFO: SPM: enable CPC mode
10091 11:45:46.717924 INFO: mcdi ready for mcusys-off-idle and system suspend
10092 11:45:46.720894 INFO: BL31: Preparing for EL3 exit to normal world
10093 11:45:46.724004 INFO: Entry point address = 0x80000000
10094 11:45:46.727303 INFO: SPSR = 0x8
10095 11:45:46.733252
10096 11:45:46.733339
10097 11:45:46.733403
10098 11:45:46.735982 Starting depthcharge on Spherion...
10099 11:45:46.736062
10100 11:45:46.736123 Wipe memory regions:
10101 11:45:46.736181
10102 11:45:46.736826 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10103 11:45:46.736926 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10104 11:45:46.737009 Setting prompt string to ['asurada:']
10105 11:45:46.737146 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10106 11:45:46.739311 [0x00000040000000, 0x00000054600000)
10107 11:45:46.861885
10108 11:45:46.862014 [0x00000054660000, 0x00000080000000)
10109 11:45:47.122683
10110 11:45:47.122830 [0x000000821a7280, 0x000000ffe64000)
10111 11:45:47.867617
10112 11:45:47.867767 [0x00000100000000, 0x00000240000000)
10113 11:45:49.757812
10114 11:45:49.760999 Initializing XHCI USB controller at 0x11200000.
10115 11:45:50.742570
10116 11:45:50.742713 R8152: Initializing
10117 11:45:50.742780
10118 11:45:50.745435 Version 9 (ocp_data = 6010)
10119 11:45:50.745531
10120 11:45:50.748820 R8152: Done initializing
10121 11:45:50.748901
10122 11:45:50.748965 Adding net device
10123 11:45:51.271522
10124 11:45:51.274224 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10125 11:45:51.274326
10126 11:45:51.274395
10127 11:45:51.274456
10128 11:45:51.274804 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10130 11:45:51.375171 asurada: tftpboot 192.168.201.1 12074004/tftp-deploy-_a2jwg94/kernel/image.itb 12074004/tftp-deploy-_a2jwg94/kernel/cmdline
10131 11:45:51.375318 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10132 11:45:51.375414 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10133 11:45:51.379760 tftpboot 192.168.201.1 12074004/tftp-deploy-_a2jwg94/kernel/image.ittp-deploy-_a2jwg94/kernel/cmdline
10134 11:45:51.379873
10135 11:45:51.379979 Waiting for link
10136 11:45:51.581822
10137 11:45:51.581971 done.
10138 11:45:51.582049
10139 11:45:51.582115 MAC: f4:f5:e8:50:de:0a
10140 11:45:51.582175
10141 11:45:51.584869 Sending DHCP discover... done.
10142 11:45:51.584947
10143 11:45:51.588295 Waiting for reply... done.
10144 11:45:51.588379
10145 11:45:51.591590 Sending DHCP request... done.
10146 11:45:51.591669
10147 11:45:51.591733 Waiting for reply... done.
10148 11:45:51.591800
10149 11:45:51.595011 My ip is 192.168.201.14
10150 11:45:51.595089
10151 11:45:51.598024 The DHCP server ip is 192.168.201.1
10152 11:45:51.598103
10153 11:45:51.601712 TFTP server IP predefined by user: 192.168.201.1
10154 11:45:51.601813
10155 11:45:51.608129 Bootfile predefined by user: 12074004/tftp-deploy-_a2jwg94/kernel/image.itb
10156 11:45:51.608206
10157 11:45:51.611417 Sending tftp read request... done.
10158 11:45:51.611513
10159 11:45:51.614555 Waiting for the transfer...
10160 11:45:51.614648
10161 11:45:51.855584 00000000 ################################################################
10162 11:45:51.855723
10163 11:45:52.093464 00080000 ################################################################
10164 11:45:52.093598
10165 11:45:52.332062 00100000 ################################################################
10166 11:45:52.332291
10167 11:45:52.578407 00180000 ################################################################
10168 11:45:52.578582
10169 11:45:52.819378 00200000 ################################################################
10170 11:45:52.819513
10171 11:45:53.052810 00280000 ################################################################
10172 11:45:53.052980
10173 11:45:53.283247 00300000 ################################################################
10174 11:45:53.283422
10175 11:45:53.513975 00380000 ################################################################
10176 11:45:53.514144
10177 11:45:53.745694 00400000 ################################################################
10178 11:45:53.745858
10179 11:45:53.979272 00480000 ################################################################
10180 11:45:53.979422
10181 11:45:54.214034 00500000 ################################################################
10182 11:45:54.214211
10183 11:45:54.452669 00580000 ################################################################
10184 11:45:54.452813
10185 11:45:54.694811 00600000 ################################################################
10186 11:45:54.694945
10187 11:45:54.934846 00680000 ################################################################
10188 11:45:54.934994
10189 11:45:55.174632 00700000 ################################################################
10190 11:45:55.174806
10191 11:45:55.416107 00780000 ################################################################
10192 11:45:55.416289
10193 11:45:55.661161 00800000 ################################################################
10194 11:45:55.661342
10195 11:45:55.908056 00880000 ################################################################
10196 11:45:55.908207
10197 11:45:56.151240 00900000 ################################################################
10198 11:45:56.151382
10199 11:45:56.399500 00980000 ################################################################
10200 11:45:56.399657
10201 11:45:56.643595 00a00000 ################################################################
10202 11:45:56.643747
10203 11:45:56.884419 00a80000 ################################################################
10204 11:45:56.884563
10205 11:45:57.138750 00b00000 ################################################################
10206 11:45:57.138890
10207 11:45:57.370946 00b80000 ################################################################
10208 11:45:57.371117
10209 11:45:57.594656 00c00000 ################################################################
10210 11:45:57.594804
10211 11:45:57.828858 00c80000 ################################################################
10212 11:45:57.829000
10213 11:45:58.057006 00d00000 ################################################################
10214 11:45:58.057152
10215 11:45:58.312855 00d80000 ################################################################
10216 11:45:58.313028
10217 11:45:58.563178 00e00000 ################################################################
10218 11:45:58.563342
10219 11:45:58.816150 00e80000 ################################################################
10220 11:45:58.816306
10221 11:45:59.072376 00f00000 ################################################################
10222 11:45:59.073088
10223 11:45:59.367142 00f80000 ################################################################
10224 11:45:59.367278
10225 11:45:59.606905 01000000 ################################################################
10226 11:45:59.607040
10227 11:45:59.838893 01080000 ################################################################
10228 11:45:59.839033
10229 11:46:00.062355 01100000 ################################################################
10230 11:46:00.062488
10231 11:46:00.288757 01180000 ################################################################
10232 11:46:00.288890
10233 11:46:00.513296 01200000 ################################################################
10234 11:46:00.513472
10235 11:46:00.741138 01280000 ################################################################
10236 11:46:00.741266
10237 11:46:00.968307 01300000 ################################################################
10238 11:46:00.968438
10239 11:46:01.195313 01380000 ################################################################
10240 11:46:01.195455
10241 11:46:01.422514 01400000 ################################################################
10242 11:46:01.422652
10243 11:46:01.650463 01480000 ################################################################
10244 11:46:01.650613
10245 11:46:01.875670 01500000 ################################################################
10246 11:46:01.875809
10247 11:46:02.100674 01580000 ################################################################
10248 11:46:02.100837
10249 11:46:02.325668 01600000 ################################################################
10250 11:46:02.325815
10251 11:46:02.552831 01680000 ################################################################
10252 11:46:02.552977
10253 11:46:02.782941 01700000 ################################################################
10254 11:46:02.783087
10255 11:46:03.008583 01780000 ################################################################
10256 11:46:03.008724
10257 11:46:03.237635 01800000 ################################################################
10258 11:46:03.237794
10259 11:46:03.466931 01880000 ################################################################
10260 11:46:03.467063
10261 11:46:03.694759 01900000 ################################################################
10262 11:46:03.694901
10263 11:46:03.927667 01980000 ################################################################
10264 11:46:03.927815
10265 11:46:04.163247 01a00000 ################################################################
10266 11:46:04.163389
10267 11:46:04.390484 01a80000 ################################################################
10268 11:46:04.390623
10269 11:46:04.616325 01b00000 ################################################################
10270 11:46:04.616500
10271 11:46:04.845811 01b80000 ################################################################
10272 11:46:04.845982
10273 11:46:05.076983 01c00000 ################################################################
10274 11:46:05.077147
10275 11:46:05.303490 01c80000 ################################################################
10276 11:46:05.303664
10277 11:46:05.531849 01d00000 ################################################################
10278 11:46:05.532011
10279 11:46:05.762741 01d80000 ################################################################
10280 11:46:05.762911
10281 11:46:05.995152 01e00000 ################################################################
10282 11:46:05.995320
10283 11:46:06.222641 01e80000 ################################################################
10284 11:46:06.222805
10285 11:46:06.451318 01f00000 ################################################################
10286 11:46:06.451489
10287 11:46:06.679028 01f80000 ################################################################
10288 11:46:06.679185
10289 11:46:06.905214 02000000 ################################################################
10290 11:46:06.905357
10291 11:46:07.157073 02080000 ################################################################
10292 11:46:07.157214
10293 11:46:07.427659 02100000 ################################################################
10294 11:46:07.427825
10295 11:46:07.684950 02180000 ################################################################
10296 11:46:07.685092
10297 11:46:07.936259 02200000 ################################################################
10298 11:46:07.936399
10299 11:46:08.175929 02280000 ################################################################
10300 11:46:08.176075
10301 11:46:08.408047 02300000 ################################################################
10302 11:46:08.408185
10303 11:46:08.672674 02380000 ################################################################
10304 11:46:08.672846
10305 11:46:08.927180 02400000 ################################################################
10306 11:46:08.927310
10307 11:46:09.159402 02480000 ################################################################
10308 11:46:09.159558
10309 11:46:09.410138 02500000 ################################################################
10310 11:46:09.410270
10311 11:46:09.662572 02580000 ################################################################
10312 11:46:09.662705
10313 11:46:09.900502 02600000 ################################################################
10314 11:46:09.900633
10315 11:46:10.146615 02680000 ################################################################
10316 11:46:10.146761
10317 11:46:10.399685 02700000 ################################################################
10318 11:46:10.399850
10319 11:46:10.664323 02780000 ################################################################
10320 11:46:10.664453
10321 11:46:10.911820 02800000 ################################################################
10322 11:46:10.911973
10323 11:46:11.174699 02880000 ################################################################
10324 11:46:11.174842
10325 11:46:11.418546 02900000 ################################################################
10326 11:46:11.418690
10327 11:46:11.680199 02980000 ################################################################
10328 11:46:11.680358
10329 11:46:11.945744 02a00000 ################################################################
10330 11:46:11.945882
10331 11:46:12.195176 02a80000 ################################################################
10332 11:46:12.195318
10333 11:46:12.427196 02b00000 ################################################################
10334 11:46:12.427332
10335 11:46:12.655465 02b80000 ################################################################
10336 11:46:12.655629
10337 11:46:12.883637 02c00000 ################################################################
10338 11:46:12.883796
10339 11:46:13.133398 02c80000 ################################################################
10340 11:46:13.133565
10341 11:46:13.363695 02d00000 ################################################################
10342 11:46:13.363829
10343 11:46:13.597825 02d80000 ################################################################
10344 11:46:13.597976
10345 11:46:13.834372 02e00000 ################################################################
10346 11:46:13.834507
10347 11:46:14.094896 02e80000 ################################################################
10348 11:46:14.095026
10349 11:46:14.345559 02f00000 ################################################################
10350 11:46:14.345694
10351 11:46:14.589661 02f80000 ################################################################
10352 11:46:14.589793
10353 11:46:14.826862 03000000 ################################################################
10354 11:46:14.826996
10355 11:46:15.065544 03080000 ################################################################
10356 11:46:15.065681
10357 11:46:15.310398 03100000 ################################################################
10358 11:46:15.310534
10359 11:46:15.544894 03180000 ################################################################
10360 11:46:15.545054
10361 11:46:15.800815 03200000 ################################################################
10362 11:46:15.800958
10363 11:46:16.059267 03280000 ################################################################
10364 11:46:16.059434
10365 11:46:16.311559 03300000 ################################################################
10366 11:46:16.311694
10367 11:46:16.563892 03380000 ################################################################
10368 11:46:16.564030
10369 11:46:16.810726 03400000 ################################################################
10370 11:46:16.810862
10371 11:46:17.065575 03480000 ################################################################
10372 11:46:17.065709
10373 11:46:17.320474 03500000 ################################################################
10374 11:46:17.320606
10375 11:46:17.583550 03580000 ################################################################
10376 11:46:17.583682
10377 11:46:17.816138 03600000 ################################################################
10378 11:46:17.816272
10379 11:46:18.046592 03680000 ################################################################
10380 11:46:18.046727
10381 11:46:18.312900 03700000 ################################################################
10382 11:46:18.313037
10383 11:46:18.578411 03780000 ################################################################
10384 11:46:18.578546
10385 11:46:18.807934 03800000 ################################################################
10386 11:46:18.808069
10387 11:46:19.043524 03880000 ################################################################
10388 11:46:19.043659
10389 11:46:19.297214 03900000 ################################################################
10390 11:46:19.297372
10391 11:46:19.535665 03980000 ################################################################
10392 11:46:19.535798
10393 11:46:19.781062 03a00000 ################################################################
10394 11:46:19.781201
10395 11:46:20.029330 03a80000 ################################################################
10396 11:46:20.029520
10397 11:46:20.287423 03b00000 ################################################################
10398 11:46:20.287561
10399 11:46:20.571310 03b80000 ################################################################
10400 11:46:20.571451
10401 11:46:20.814679 03c00000 ################################################################
10402 11:46:20.814824
10403 11:46:21.074085 03c80000 ################################################################
10404 11:46:21.074318
10405 11:46:21.322701 03d00000 ################################################################
10406 11:46:21.322841
10407 11:46:21.571059 03d80000 ################################################################
10408 11:46:21.571198
10409 11:46:21.827728 03e00000 ################################################################
10410 11:46:21.827882
10411 11:46:22.085689 03e80000 ################################################################
10412 11:46:22.085833
10413 11:46:22.336861 03f00000 ################################################################
10414 11:46:22.337007
10415 11:46:22.580865 03f80000 ################################################################
10416 11:46:22.581007
10417 11:46:22.830236 04000000 ################################################################
10418 11:46:22.830389
10419 11:46:23.085381 04080000 ################################################################
10420 11:46:23.085569
10421 11:46:23.333560 04100000 ################################################################
10422 11:46:23.333705
10423 11:46:23.579872 04180000 ################################################################
10424 11:46:23.580020
10425 11:46:23.833867 04200000 ################################################################
10426 11:46:23.834003
10427 11:46:24.104046 04280000 ################################################################
10428 11:46:24.104184
10429 11:46:24.361732 04300000 ################################################################
10430 11:46:24.361876
10431 11:46:24.588316 04380000 ################################################################
10432 11:46:24.588452
10433 11:46:24.829688 04400000 ################################################################
10434 11:46:24.829822
10435 11:46:25.087235 04480000 ################################################################
10436 11:46:25.087373
10437 11:46:25.350582 04500000 ################################################################
10438 11:46:25.350723
10439 11:46:25.594718 04580000 ################################################################
10440 11:46:25.594887
10441 11:46:25.829343 04600000 ################################################################
10442 11:46:25.829497
10443 11:46:26.056854 04680000 ################################################################
10444 11:46:26.057008
10445 11:46:26.293366 04700000 ################################################################
10446 11:46:26.293510
10447 11:46:26.528243 04780000 ################################################################
10448 11:46:26.528405
10449 11:46:26.758650 04800000 ################################################################
10450 11:46:26.758822
10451 11:46:26.999105 04880000 ################################################################
10452 11:46:26.999239
10453 11:46:27.230471 04900000 ################################################################
10454 11:46:27.230606
10455 11:46:27.457680 04980000 ################################################################
10456 11:46:27.457812
10457 11:46:27.685619 04a00000 ################################################################
10458 11:46:27.685765
10459 11:46:27.937537 04a80000 ################################################################
10460 11:46:27.937678
10461 11:46:28.182485 04b00000 ################################################################
10462 11:46:28.182651
10463 11:46:28.426084 04b80000 ################################################################
10464 11:46:28.426228
10465 11:46:28.655512 04c00000 ################################################################
10466 11:46:28.655688
10467 11:46:28.912870 04c80000 ################################################################
10468 11:46:28.913040
10469 11:46:29.162579 04d00000 ################################################################
10470 11:46:29.162748
10471 11:46:29.394785 04d80000 ################################################################
10472 11:46:29.395017
10473 11:46:29.627879 04e00000 ################################################################
10474 11:46:29.628035
10475 11:46:29.868422 04e80000 ################################################################
10476 11:46:29.868594
10477 11:46:30.107628 04f00000 ################################################################
10478 11:46:30.107768
10479 11:46:30.340785 04f80000 ################################################################
10480 11:46:30.340924
10481 11:46:30.571534 05000000 ################################################################
10482 11:46:30.571674
10483 11:46:30.827179 05080000 ################################################################
10484 11:46:30.827316
10485 11:46:31.081328 05100000 ################################################################
10486 11:46:31.081473
10487 11:46:31.323025 05180000 ################################################################
10488 11:46:31.323159
10489 11:46:31.586932 05200000 ################################################################
10490 11:46:31.587067
10491 11:46:31.827668 05280000 ################################################################
10492 11:46:31.827796
10493 11:46:32.087294 05300000 ################################################################
10494 11:46:32.087432
10495 11:46:32.325855 05380000 ################################################################
10496 11:46:32.326003
10497 11:46:32.547498 05400000 ################################################################
10498 11:46:32.547647
10499 11:46:32.780509 05480000 ################################################################
10500 11:46:32.780692
10501 11:46:33.015193 05500000 ################################################################
10502 11:46:33.015365
10503 11:46:33.251577 05580000 ################################################################
10504 11:46:33.251750
10505 11:46:33.488602 05600000 ################################################################
10506 11:46:33.488750
10507 11:46:33.717443 05680000 ################################################################
10508 11:46:33.717573
10509 11:46:33.957862 05700000 ################################################################
10510 11:46:33.958010
10511 11:46:34.194676 05780000 ################################################################
10512 11:46:34.194819
10513 11:46:34.431209 05800000 ################################################################
10514 11:46:34.431344
10515 11:46:34.667947 05880000 ################################################################
10516 11:46:34.668114
10517 11:46:34.906425 05900000 ################################################################
10518 11:46:34.906570
10519 11:46:35.151032 05980000 ################################################################
10520 11:46:35.151180
10521 11:46:35.391607 05a00000 ################################################################
10522 11:46:35.391787
10523 11:46:35.635268 05a80000 ################################################################
10524 11:46:35.635417
10525 11:46:35.856113 05b00000 ################################################################
10526 11:46:35.856292
10527 11:46:36.083885 05b80000 ################################################################
10528 11:46:36.084058
10529 11:46:36.313303 05c00000 ################################################################
10530 11:46:36.313505
10531 11:46:36.567862 05c80000 ################################################################
10532 11:46:36.568036
10533 11:46:36.820405 05d00000 ################################################################
10534 11:46:36.820532
10535 11:46:37.078775 05d80000 ################################################################
10536 11:46:37.078911
10537 11:46:37.324462 05e00000 ################################################################
10538 11:46:37.324618
10539 11:46:37.577376 05e80000 ################################################################
10540 11:46:37.577534
10541 11:46:37.837254 05f00000 ################################################################
10542 11:46:37.837396
10543 11:46:38.097204 05f80000 ################################################################
10544 11:46:38.097367
10545 11:46:38.353060 06000000 ################################################################
10546 11:46:38.353234
10547 11:46:38.584513 06080000 ################################################################
10548 11:46:38.584653
10549 11:46:38.810731 06100000 ################################################################
10550 11:46:38.810899
10551 11:46:39.044464 06180000 ################################################################
10552 11:46:39.044604
10553 11:46:39.289741 06200000 ################################################################
10554 11:46:39.289903
10555 11:46:39.535004 06280000 ################################################################
10556 11:46:39.535143
10557 11:46:39.788835 06300000 ################################################################
10558 11:46:39.788966
10559 11:46:40.054456 06380000 ################################################################
10560 11:46:40.054598
10561 11:46:40.296773 06400000 ################################################################
10562 11:46:40.296914
10563 11:46:40.547812 06480000 ################################################################
10564 11:46:40.547950
10565 11:46:40.810263 06500000 ################################################################
10566 11:46:40.810427
10567 11:46:41.073137 06580000 ################################################################
10568 11:46:41.073277
10569 11:46:41.341382 06600000 ################################################################
10570 11:46:41.341559
10571 11:46:41.600777 06680000 ################################################################
10572 11:46:41.600919
10573 11:46:41.841926 06700000 ################################################################
10574 11:46:41.842055
10575 11:46:42.070202 06780000 ################################################################
10576 11:46:42.070331
10577 11:46:42.261759 06800000 ############################################### done.
10578 11:46:42.261894
10579 11:46:42.265128 The bootfile was 109429070 bytes long.
10580 11:46:42.265219
10581 11:46:42.268362 Sending tftp read request... done.
10582 11:46:42.268449
10583 11:46:42.268517 Waiting for the transfer...
10584 11:46:42.271861
10585 11:46:42.272031 00000000 # done.
10586 11:46:42.272117
10587 11:46:42.278069 Command line loaded dynamically from TFTP file: 12074004/tftp-deploy-_a2jwg94/kernel/cmdline
10588 11:46:42.278177
10589 11:46:42.291089 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10590 11:46:42.294379
10591 11:46:42.294614 Loading FIT.
10592 11:46:42.294753
10593 11:46:42.297860 Image ramdisk-1 has 98331512 bytes.
10594 11:46:42.298014
10595 11:46:42.300890 Image fdt-1 has 47278 bytes.
10596 11:46:42.301062
10597 11:46:42.304338 Image kernel-1 has 11048246 bytes.
10598 11:46:42.304538
10599 11:46:42.310814 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10600 11:46:42.311131
10601 11:46:42.331075 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10602 11:46:42.331620
10603 11:46:42.334447 Choosing best match conf-1 for compat google,spherion-rev2.
10604 11:46:42.339097
10605 11:46:42.343824 Connected to device vid:did:rid of 1ae0:0028:00
10606 11:46:42.350761
10607 11:46:42.353621 tpm_get_response: command 0x17b, return code 0x0
10608 11:46:42.354084
10609 11:46:42.357002 ec_init: CrosEC protocol v3 supported (256, 248)
10610 11:46:42.362738
10611 11:46:42.365670 tpm_cleanup: add release locality here.
10612 11:46:42.366133
10613 11:46:42.366496 Shutting down all USB controllers.
10614 11:46:42.368732
10615 11:46:42.369188 Removing current net device
10616 11:46:42.369594
10617 11:46:42.375199 Exiting depthcharge with code 4 at timestamp: 85131566
10618 11:46:42.375614
10619 11:46:42.378973 LZMA decompressing kernel-1 to 0x821a6718
10620 11:46:42.379390
10621 11:46:42.382345 LZMA decompressing kernel-1 to 0x40000000
10622 11:46:43.771204
10623 11:46:43.771865 jumping to kernel
10624 11:46:43.774327 end: 2.2.4 bootloader-commands (duration 00:00:57) [common]
10625 11:46:43.774874 start: 2.2.5 auto-login-action (timeout 00:03:28) [common]
10626 11:46:43.775287 Setting prompt string to ['Linux version [0-9]']
10627 11:46:43.775665 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10628 11:46:43.776042 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10629 11:46:43.853694
10630 11:46:43.856538 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10631 11:46:43.860712 start: 2.2.5.1 login-action (timeout 00:03:28) [common]
10632 11:46:43.861295 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10633 11:46:43.861740 Setting prompt string to []
10634 11:46:43.862173 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10635 11:46:43.862562 Using line separator: #'\n'#
10636 11:46:43.862892 No login prompt set.
10637 11:46:43.863236 Parsing kernel messages
10638 11:46:43.863541 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10639 11:46:43.864096 [login-action] Waiting for messages, (timeout 00:03:28)
10640 11:46:43.879669 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10641 11:46:43.882848 [ 0.000000] random: crng init done
10642 11:46:43.889247 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10643 11:46:43.892475 [ 0.000000] efi: UEFI not found.
10644 11:46:43.898995 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10645 11:46:43.909066 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10646 11:46:43.916136 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10647 11:46:43.926329 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10648 11:46:43.932795 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10649 11:46:43.938675 [ 0.000000] printk: bootconsole [mtk8250] enabled
10650 11:46:43.945239 [ 0.000000] NUMA: No NUMA configuration found
10651 11:46:43.952141 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10652 11:46:43.958715 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10653 11:46:43.959271 [ 0.000000] Zone ranges:
10654 11:46:43.965098 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10655 11:46:43.968386 [ 0.000000] DMA32 empty
10656 11:46:43.974714 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10657 11:46:43.978190 [ 0.000000] Movable zone start for each node
10658 11:46:43.982132 [ 0.000000] Early memory node ranges
10659 11:46:43.988073 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10660 11:46:43.994621 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10661 11:46:44.001750 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10662 11:46:44.008000 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10663 11:46:44.014554 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10664 11:46:44.021000 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10665 11:46:44.077281 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10666 11:46:44.084086 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10667 11:46:44.090407 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10668 11:46:44.094839 [ 0.000000] psci: probing for conduit method from DT.
10669 11:46:44.100685 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10670 11:46:44.104044 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10671 11:46:44.110376 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10672 11:46:44.113577 [ 0.000000] psci: SMC Calling Convention v1.2
10673 11:46:44.120243 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10674 11:46:44.123620 [ 0.000000] Detected VIPT I-cache on CPU0
10675 11:46:44.130037 [ 0.000000] CPU features: detected: GIC system register CPU interface
10676 11:46:44.136733 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10677 11:46:44.143614 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10678 11:46:44.149689 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10679 11:46:44.159352 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10680 11:46:44.166021 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10681 11:46:44.169128 [ 0.000000] alternatives: applying boot alternatives
10682 11:46:44.176511 [ 0.000000] Fallback order for Node 0: 0
10683 11:46:44.182673 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10684 11:46:44.186144 [ 0.000000] Policy zone: Normal
10685 11:46:44.199888 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10686 11:46:44.209804 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10687 11:46:44.221806 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10688 11:46:44.231652 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10689 11:46:44.238432 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10690 11:46:44.241575 <6>[ 0.000000] software IO TLB: area num 8.
10691 11:46:44.297637 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10692 11:46:44.447309 <6>[ 0.000000] Memory: 7873596K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 479172K reserved, 32768K cma-reserved)
10693 11:46:44.453452 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10694 11:46:44.460108 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10695 11:46:44.463298 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10696 11:46:44.469755 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10697 11:46:44.476687 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10698 11:46:44.479781 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10699 11:46:44.489337 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10700 11:46:44.496451 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10701 11:46:44.502810 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10702 11:46:44.509226 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10703 11:46:44.512352 <6>[ 0.000000] GICv3: 608 SPIs implemented
10704 11:46:44.515708 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10705 11:46:44.522269 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10706 11:46:44.525642 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10707 11:46:44.532408 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10708 11:46:44.545460 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10709 11:46:44.559062 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10710 11:46:44.564968 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10711 11:46:44.572994 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10712 11:46:44.586445 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10713 11:46:44.593136 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10714 11:46:44.599662 <6>[ 0.009180] Console: colour dummy device 80x25
10715 11:46:44.609827 <6>[ 0.013930] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10716 11:46:44.616146 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10717 11:46:44.619860 <6>[ 0.029244] LSM: Security Framework initializing
10718 11:46:44.626824 <6>[ 0.034210] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10719 11:46:44.636477 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10720 11:46:44.646247 <6>[ 0.051432] cblist_init_generic: Setting adjustable number of callback queues.
10721 11:46:44.650365 <6>[ 0.058921] cblist_init_generic: Setting shift to 3 and lim to 1.
10722 11:46:44.659058 <6>[ 0.065259] cblist_init_generic: Setting adjustable number of callback queues.
10723 11:46:44.665855 <6>[ 0.072732] cblist_init_generic: Setting shift to 3 and lim to 1.
10724 11:46:44.669455 <6>[ 0.079170] rcu: Hierarchical SRCU implementation.
10725 11:46:44.676051 <6>[ 0.084216] rcu: Max phase no-delay instances is 1000.
10726 11:46:44.682977 <6>[ 0.091240] EFI services will not be available.
10727 11:46:44.685384 <6>[ 0.096222] smp: Bringing up secondary CPUs ...
10728 11:46:44.694551 <6>[ 0.101265] Detected VIPT I-cache on CPU1
10729 11:46:44.701200 <6>[ 0.101335] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10730 11:46:44.707685 <6>[ 0.101367] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10731 11:46:44.710578 <6>[ 0.101700] Detected VIPT I-cache on CPU2
10732 11:46:44.720472 <6>[ 0.101748] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10733 11:46:44.727224 <6>[ 0.101764] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10734 11:46:44.730885 <6>[ 0.102019] Detected VIPT I-cache on CPU3
10735 11:46:44.736905 <6>[ 0.102065] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10736 11:46:44.743645 <6>[ 0.102079] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10737 11:46:44.749990 <6>[ 0.102381] CPU features: detected: Spectre-v4
10738 11:46:44.753330 <6>[ 0.102388] CPU features: detected: Spectre-BHB
10739 11:46:44.757252 <6>[ 0.102392] Detected PIPT I-cache on CPU4
10740 11:46:44.763516 <6>[ 0.102449] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10741 11:46:44.770341 <6>[ 0.102466] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10742 11:46:44.777021 <6>[ 0.102760] Detected PIPT I-cache on CPU5
10743 11:46:44.782838 <6>[ 0.102823] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10744 11:46:44.789766 <6>[ 0.102839] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10745 11:46:44.793155 <6>[ 0.103118] Detected PIPT I-cache on CPU6
10746 11:46:44.802716 <6>[ 0.103183] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10747 11:46:44.809473 <6>[ 0.103199] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10748 11:46:44.812694 <6>[ 0.103498] Detected PIPT I-cache on CPU7
10749 11:46:44.819238 <6>[ 0.103564] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10750 11:46:44.826373 <6>[ 0.103580] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10751 11:46:44.832065 <6>[ 0.103628] smp: Brought up 1 node, 8 CPUs
10752 11:46:44.835452 <6>[ 0.245018] SMP: Total of 8 processors activated.
10753 11:46:44.842236 <6>[ 0.249969] CPU features: detected: 32-bit EL0 Support
10754 11:46:44.848577 <6>[ 0.255333] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10755 11:46:44.855943 <6>[ 0.264188] CPU features: detected: Common not Private translations
10756 11:46:44.862443 <6>[ 0.270663] CPU features: detected: CRC32 instructions
10757 11:46:44.868938 <6>[ 0.276014] CPU features: detected: RCpc load-acquire (LDAPR)
10758 11:46:44.872170 <6>[ 0.281974] CPU features: detected: LSE atomic instructions
10759 11:46:44.878853 <6>[ 0.287755] CPU features: detected: Privileged Access Never
10760 11:46:44.885526 <6>[ 0.293535] CPU features: detected: RAS Extension Support
10761 11:46:44.891562 <6>[ 0.299144] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10762 11:46:44.894930 <6>[ 0.306407] CPU: All CPU(s) started at EL2
10763 11:46:44.901718 <6>[ 0.310724] alternatives: applying system-wide alternatives
10764 11:46:44.912068 <6>[ 0.321428] devtmpfs: initialized
10765 11:46:44.928046 <6>[ 0.330384] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10766 11:46:44.934096 <6>[ 0.340345] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10767 11:46:44.940666 <6>[ 0.348368] pinctrl core: initialized pinctrl subsystem
10768 11:46:44.944914 <6>[ 0.355040] DMI not present or invalid.
10769 11:46:44.950958 <6>[ 0.359461] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10770 11:46:44.960701 <6>[ 0.366326] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10771 11:46:44.967066 <6>[ 0.373913] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10772 11:46:44.977164 <6>[ 0.382127] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10773 11:46:44.980639 <6>[ 0.390370] audit: initializing netlink subsys (disabled)
10774 11:46:44.990382 <5>[ 0.396065] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10775 11:46:44.997054 <6>[ 0.396774] thermal_sys: Registered thermal governor 'step_wise'
10776 11:46:45.003654 <6>[ 0.404032] thermal_sys: Registered thermal governor 'power_allocator'
10777 11:46:45.006698 <6>[ 0.410289] cpuidle: using governor menu
10778 11:46:45.013101 <6>[ 0.421250] NET: Registered PF_QIPCRTR protocol family
10779 11:46:45.020084 <6>[ 0.426739] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10780 11:46:45.026677 <6>[ 0.433845] ASID allocator initialised with 32768 entries
10781 11:46:45.030152 <6>[ 0.440407] Serial: AMBA PL011 UART driver
10782 11:46:45.039934 <4>[ 0.449193] Trying to register duplicate clock ID: 134
10783 11:46:45.094525 <6>[ 0.506950] KASLR enabled
10784 11:46:45.108778 <6>[ 0.514686] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10785 11:46:45.115246 <6>[ 0.521702] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10786 11:46:45.121533 <6>[ 0.528192] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10787 11:46:45.128528 <6>[ 0.535198] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10788 11:46:45.134924 <6>[ 0.541684] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10789 11:46:45.142064 <6>[ 0.548688] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10790 11:46:45.148289 <6>[ 0.555176] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10791 11:46:45.155578 <6>[ 0.562180] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10792 11:46:45.158191 <6>[ 0.569677] ACPI: Interpreter disabled.
10793 11:46:45.166598 <6>[ 0.576071] iommu: Default domain type: Translated
10794 11:46:45.173477 <6>[ 0.581183] iommu: DMA domain TLB invalidation policy: strict mode
10795 11:46:45.176647 <5>[ 0.587835] SCSI subsystem initialized
10796 11:46:45.183277 <6>[ 0.591999] usbcore: registered new interface driver usbfs
10797 11:46:45.189995 <6>[ 0.597733] usbcore: registered new interface driver hub
10798 11:46:45.193034 <6>[ 0.603285] usbcore: registered new device driver usb
10799 11:46:45.199931 <6>[ 0.609379] pps_core: LinuxPPS API ver. 1 registered
10800 11:46:45.210234 <6>[ 0.614574] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10801 11:46:45.213524 <6>[ 0.623921] PTP clock support registered
10802 11:46:45.216718 <6>[ 0.628163] EDAC MC: Ver: 3.0.0
10803 11:46:45.224648 <6>[ 0.633308] FPGA manager framework
10804 11:46:45.230704 <6>[ 0.636987] Advanced Linux Sound Architecture Driver Initialized.
10805 11:46:45.234086 <6>[ 0.643753] vgaarb: loaded
10806 11:46:45.240374 <6>[ 0.646926] clocksource: Switched to clocksource arch_sys_counter
10807 11:46:45.244581 <5>[ 0.653358] VFS: Disk quotas dquot_6.6.0
10808 11:46:45.250706 <6>[ 0.657543] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10809 11:46:45.253498 <6>[ 0.664732] pnp: PnP ACPI: disabled
10810 11:46:45.262415 <6>[ 0.671391] NET: Registered PF_INET protocol family
10811 11:46:45.272125 <6>[ 0.676975] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10812 11:46:45.283262 <6>[ 0.689273] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10813 11:46:45.293134 <6>[ 0.698089] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10814 11:46:45.299673 <6>[ 0.706060] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10815 11:46:45.309986 <6>[ 0.714759] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10816 11:46:45.316318 <6>[ 0.724508] TCP: Hash tables configured (established 65536 bind 65536)
10817 11:46:45.322911 <6>[ 0.731366] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10818 11:46:45.332494 <6>[ 0.738567] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10819 11:46:45.339536 <6>[ 0.746261] NET: Registered PF_UNIX/PF_LOCAL protocol family
10820 11:46:45.345810 <6>[ 0.752431] RPC: Registered named UNIX socket transport module.
10821 11:46:45.348790 <6>[ 0.758585] RPC: Registered udp transport module.
10822 11:46:45.355442 <6>[ 0.763518] RPC: Registered tcp transport module.
10823 11:46:45.363251 <6>[ 0.768447] RPC: Registered tcp NFSv4.1 backchannel transport module.
10824 11:46:45.365065 <6>[ 0.775114] PCI: CLS 0 bytes, default 64
10825 11:46:45.368498 <6>[ 0.779499] Unpacking initramfs...
10826 11:46:45.385571 <6>[ 0.791541] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10827 11:46:45.395469 <6>[ 0.800203] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10828 11:46:45.398996 <6>[ 0.808974] kvm [1]: IPA Size Limit: 40 bits
10829 11:46:45.405225 <6>[ 0.813500] kvm [1]: GICv3: no GICV resource entry
10830 11:46:45.408832 <6>[ 0.818522] kvm [1]: disabling GICv2 emulation
10831 11:46:45.414987 <6>[ 0.823210] kvm [1]: GIC system register CPU interface enabled
10832 11:46:45.421635 <6>[ 0.830996] kvm [1]: vgic interrupt IRQ18
10833 11:46:45.424833 <6>[ 0.835373] kvm [1]: VHE mode initialized successfully
10834 11:46:45.432153 <5>[ 0.841769] Initialise system trusted keyrings
10835 11:46:45.439328 <6>[ 0.846545] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10836 11:46:45.447532 <6>[ 0.856547] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10837 11:46:45.454085 <5>[ 0.862940] NFS: Registering the id_resolver key type
10838 11:46:45.457207 <5>[ 0.868239] Key type id_resolver registered
10839 11:46:45.463755 <5>[ 0.872655] Key type id_legacy registered
10840 11:46:45.469972 <6>[ 0.876932] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10841 11:46:45.477057 <6>[ 0.883852] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10842 11:46:45.483459 <6>[ 0.891568] 9p: Installing v9fs 9p2000 file system support
10843 11:46:45.521500 <5>[ 0.930591] Key type asymmetric registered
10844 11:46:45.524870 <5>[ 0.934923] Asymmetric key parser 'x509' registered
10845 11:46:45.534812 <6>[ 0.940082] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10846 11:46:45.538353 <6>[ 0.947699] io scheduler mq-deadline registered
10847 11:46:45.541550 <6>[ 0.952468] io scheduler kyber registered
10848 11:46:45.560449 <6>[ 0.969530] EINJ: ACPI disabled.
10849 11:46:45.592602 <4>[ 0.995284] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10850 11:46:45.602168 <4>[ 1.005917] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10851 11:46:45.617324 <6>[ 1.026658] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10852 11:46:45.625193 <6>[ 1.034659] printk: console [ttyS0] disabled
10853 11:46:45.653796 <6>[ 1.059311] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10854 11:46:45.659329 <6>[ 1.068786] printk: console [ttyS0] enabled
10855 11:46:45.662442 <6>[ 1.068786] printk: console [ttyS0] enabled
10856 11:46:45.669549 <6>[ 1.077683] printk: bootconsole [mtk8250] disabled
10857 11:46:45.672372 <6>[ 1.077683] printk: bootconsole [mtk8250] disabled
10858 11:46:45.679280 <6>[ 1.088933] SuperH (H)SCI(F) driver initialized
10859 11:46:45.682246 <6>[ 1.094216] msm_serial: driver initialized
10860 11:46:45.696999 <6>[ 1.103269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10861 11:46:45.706392 <6>[ 1.111819] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10862 11:46:45.713302 <6>[ 1.120362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10863 11:46:45.722944 <6>[ 1.128994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10864 11:46:45.733033 <6>[ 1.137704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10865 11:46:45.739680 <6>[ 1.146418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10866 11:46:45.749900 <6>[ 1.154959] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10867 11:46:45.756492 <6>[ 1.163773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10868 11:46:45.766534 <6>[ 1.172317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10869 11:46:45.778348 <6>[ 1.188226] loop: module loaded
10870 11:46:45.784687 <6>[ 1.194149] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10871 11:46:45.807735 <4>[ 1.217536] mtk-pmic-keys: Failed to locate of_node [id: -1]
10872 11:46:45.814428 <6>[ 1.224462] megasas: 07.719.03.00-rc1
10873 11:46:45.824690 <6>[ 1.234100] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10874 11:46:45.832998 <6>[ 1.242301] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10875 11:46:45.849380 <6>[ 1.258966] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10876 11:46:45.909400 <6>[ 1.312616] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10877 11:46:49.383159 <6>[ 4.792979] Freeing initrd memory: 96020K
10878 11:46:49.393513 <6>[ 4.803359] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10879 11:46:49.404419 <6>[ 4.814279] tun: Universal TUN/TAP device driver, 1.6
10880 11:46:49.408212 <6>[ 4.820340] thunder_xcv, ver 1.0
10881 11:46:49.410651 <6>[ 4.823847] thunder_bgx, ver 1.0
10882 11:46:49.413928 <6>[ 4.827341] nicpf, ver 1.0
10883 11:46:49.425501 <6>[ 4.831345] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10884 11:46:49.428376 <6>[ 4.838820] hns3: Copyright (c) 2017 Huawei Corporation.
10885 11:46:49.435045 <6>[ 4.844405] hclge is initializing
10886 11:46:49.437846 <6>[ 4.847985] e1000: Intel(R) PRO/1000 Network Driver
10887 11:46:49.444826 <6>[ 4.853114] e1000: Copyright (c) 1999-2006 Intel Corporation.
10888 11:46:49.447850 <6>[ 4.859130] e1000e: Intel(R) PRO/1000 Network Driver
10889 11:46:49.454385 <6>[ 4.864345] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10890 11:46:49.461452 <6>[ 4.870530] igb: Intel(R) Gigabit Ethernet Network Driver
10891 11:46:49.467798 <6>[ 4.876180] igb: Copyright (c) 2007-2014 Intel Corporation.
10892 11:46:49.474075 <6>[ 4.882015] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10893 11:46:49.480873 <6>[ 4.888533] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10894 11:46:49.484399 <6>[ 4.895008] sky2: driver version 1.30
10895 11:46:49.491133 <6>[ 4.900010] VFIO - User Level meta-driver version: 0.3
10896 11:46:49.498503 <6>[ 4.908260] usbcore: registered new interface driver usb-storage
10897 11:46:49.504807 <6>[ 4.914699] usbcore: registered new device driver onboard-usb-hub
10898 11:46:49.513892 <6>[ 4.923875] mt6397-rtc mt6359-rtc: registered as rtc0
10899 11:46:49.523637 <6>[ 4.929342] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:46:50 UTC (1700826410)
10900 11:46:49.527435 <6>[ 4.938904] i2c_dev: i2c /dev entries driver
10901 11:46:49.543931 <6>[ 4.950636] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10902 11:46:49.563979 <6>[ 4.973653] cpu cpu0: EM: created perf domain
10903 11:46:49.567047 <6>[ 4.978590] cpu cpu4: EM: created perf domain
10904 11:46:49.574436 <6>[ 4.984173] sdhci: Secure Digital Host Controller Interface driver
10905 11:46:49.580635 <6>[ 4.990607] sdhci: Copyright(c) Pierre Ossman
10906 11:46:49.587436 <6>[ 4.995560] Synopsys Designware Multimedia Card Interface Driver
10907 11:46:49.593868 <6>[ 5.002195] sdhci-pltfm: SDHCI platform and OF driver helper
10908 11:46:49.597297 <6>[ 5.002327] mmc0: CQHCI version 5.10
10909 11:46:49.604069 <6>[ 5.012594] ledtrig-cpu: registered to indicate activity on CPUs
10910 11:46:49.610716 <6>[ 5.019725] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10911 11:46:49.617307 <6>[ 5.026783] usbcore: registered new interface driver usbhid
10912 11:46:49.620419 <6>[ 5.032609] usbhid: USB HID core driver
10913 11:46:49.630275 <6>[ 5.036794] spi_master spi0: will run message pump with realtime priority
10914 11:46:49.671317 <6>[ 5.074776] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10915 11:46:49.691224 <6>[ 5.090898] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10916 11:46:49.697975 <6>[ 5.106620] mmc0: Command Queue Engine enabled
10917 11:46:49.704210 <6>[ 5.111359] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10918 11:46:49.707959 <6>[ 5.118137] cros-ec-spi spi0.0: Chrome EC device registered
10919 11:46:49.714723 <6>[ 5.118568] mmcblk0: mmc0:0001 DA4128 116 GiB
10920 11:46:49.723724 <6>[ 5.133965] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10921 11:46:49.731055 <6>[ 5.141204] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10922 11:46:49.737933 <6>[ 5.147159] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10923 11:46:49.744419 <6>[ 5.153225] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10924 11:46:49.754733 <6>[ 5.158189] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10925 11:46:49.760884 <6>[ 5.170667] NET: Registered PF_PACKET protocol family
10926 11:46:49.763898 <6>[ 5.176066] 9pnet: Installing 9P2000 support
10927 11:46:49.771324 <5>[ 5.180627] Key type dns_resolver registered
10928 11:46:49.774637 <6>[ 5.185617] registered taskstats version 1
10929 11:46:49.781021 <5>[ 5.190001] Loading compiled-in X.509 certificates
10930 11:46:49.809943 <4>[ 5.213617] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10931 11:46:49.819634 <4>[ 5.224399] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10932 11:46:49.826730 <3>[ 5.235011] debugfs: File 'uA_load' in directory '/' already present!
10933 11:46:49.832904 <3>[ 5.241723] debugfs: File 'min_uV' in directory '/' already present!
10934 11:46:49.839577 <3>[ 5.248336] debugfs: File 'max_uV' in directory '/' already present!
10935 11:46:49.845973 <3>[ 5.254947] debugfs: File 'constraint_flags' in directory '/' already present!
10936 11:46:49.858249 <3>[ 5.264790] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10937 11:46:49.866551 <6>[ 5.276925] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10938 11:46:49.874002 <6>[ 5.283542] xhci-mtk 11200000.usb: xHCI Host Controller
10939 11:46:49.880171 <6>[ 5.289030] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10940 11:46:49.889896 <6>[ 5.296859] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10941 11:46:49.896491 <6>[ 5.306273] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10942 11:46:49.902921 <6>[ 5.312335] xhci-mtk 11200000.usb: xHCI Host Controller
10943 11:46:49.909292 <6>[ 5.317816] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10944 11:46:49.915900 <6>[ 5.325463] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10945 11:46:49.923027 <6>[ 5.333148] hub 1-0:1.0: USB hub found
10946 11:46:49.926061 <6>[ 5.337160] hub 1-0:1.0: 1 port detected
10947 11:46:49.936125 <6>[ 5.341423] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10948 11:46:49.939472 <6>[ 5.349980] hub 2-0:1.0: USB hub found
10949 11:46:49.942481 <6>[ 5.353985] hub 2-0:1.0: 1 port detected
10950 11:46:49.951917 <6>[ 5.362249] mtk-msdc 11f70000.mmc: Got CD GPIO
10951 11:46:49.962239 <6>[ 5.368265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10952 11:46:49.969189 <6>[ 5.376299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10953 11:46:49.978545 <4>[ 5.384185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10954 11:46:49.985778 <6>[ 5.393708] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10955 11:46:49.995451 <6>[ 5.401785] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10956 11:46:50.001729 <6>[ 5.409813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10957 11:46:50.011984 <6>[ 5.417726] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10958 11:46:50.018443 <6>[ 5.425542] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10959 11:46:50.027972 <6>[ 5.433359] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10960 11:46:50.037924 <6>[ 5.443779] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10961 11:46:50.044881 <6>[ 5.452149] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10962 11:46:50.054478 <6>[ 5.460489] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10963 11:46:50.060988 <6>[ 5.468829] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10964 11:46:50.070829 <6>[ 5.477172] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10965 11:46:50.077621 <6>[ 5.485512] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10966 11:46:50.087381 <6>[ 5.493851] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10967 11:46:50.093800 <6>[ 5.502189] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10968 11:46:50.103950 <6>[ 5.510528] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10969 11:46:50.110364 <6>[ 5.518866] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10970 11:46:50.120159 <6>[ 5.527205] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10971 11:46:50.129966 <6>[ 5.535543] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10972 11:46:50.136592 <6>[ 5.543893] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10973 11:46:50.146731 <6>[ 5.552234] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10974 11:46:50.153209 <6>[ 5.560574] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10975 11:46:50.159741 <6>[ 5.569357] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10976 11:46:50.166430 <6>[ 5.576627] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10977 11:46:50.173403 <6>[ 5.583493] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10978 11:46:50.183498 <6>[ 5.590333] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10979 11:46:50.189961 <6>[ 5.597353] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10980 11:46:50.196623 <6>[ 5.604208] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10981 11:46:50.206643 <6>[ 5.613336] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10982 11:46:50.216438 <6>[ 5.622455] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10983 11:46:50.226024 <6>[ 5.631749] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10984 11:46:50.236016 <6>[ 5.641220] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10985 11:46:50.247466 <6>[ 5.650688] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10986 11:46:50.252679 <6>[ 5.659808] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10987 11:46:50.262983 <6>[ 5.669277] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10988 11:46:50.272502 <6>[ 5.678395] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10989 11:46:50.282415 <6>[ 5.687689] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10990 11:46:50.292563 <6>[ 5.697852] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10991 11:46:50.303092 <6>[ 5.709490] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10992 11:46:50.332798 <6>[ 5.739353] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10993 11:46:50.361055 <6>[ 5.771180] hub 2-1:1.0: USB hub found
10994 11:46:50.364392 <6>[ 5.775676] hub 2-1:1.0: 3 ports detected
10995 11:46:50.373494 <6>[ 5.783080] hub 2-1:1.0: USB hub found
10996 11:46:50.376258 <6>[ 5.787426] hub 2-1:1.0: 3 ports detected
10997 11:46:50.484817 <6>[ 5.891219] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10998 11:46:50.639473 <6>[ 6.049341] hub 1-1:1.0: USB hub found
10999 11:46:50.642526 <6>[ 6.053838] hub 1-1:1.0: 4 ports detected
11000 11:46:50.653081 <6>[ 6.062767] hub 1-1:1.0: USB hub found
11001 11:46:50.656516 <6>[ 6.067096] hub 1-1:1.0: 4 ports detected
11002 11:46:50.976881 <6>[ 6.383246] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
11003 11:46:51.107190 <6>[ 6.517496] hub 1-1.1:1.0: USB hub found
11004 11:46:51.110579 <6>[ 6.521857] hub 1-1.1:1.0: 4 ports detected
11005 11:46:51.224618 <6>[ 6.631338] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
11006 11:46:51.357195 <6>[ 6.767068] hub 1-1.4:1.0: USB hub found
11007 11:46:51.360374 <6>[ 6.771735] hub 1-1.4:1.0: 2 ports detected
11008 11:46:51.369370 <6>[ 6.779668] hub 1-1.4:1.0: USB hub found
11009 11:46:51.372678 <6>[ 6.784269] hub 1-1.4:1.0: 2 ports detected
11010 11:46:51.436983 <6>[ 6.843236] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
11011 11:46:51.628245 <6>[ 7.035245] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
11012 11:46:51.713437 <3>[ 7.123440] usb 1-1.1.4: device descriptor read/64, error -32
11013 11:46:51.905503 <3>[ 7.315438] usb 1-1.1.4: device descriptor read/64, error -32
11014 11:46:52.100323 <6>[ 7.507247] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
11015 11:46:52.185260 <3>[ 7.595437] usb 1-1.1.4: device descriptor read/64, error -32
11016 11:46:52.377340 <3>[ 7.787305] usb 1-1.1.4: device descriptor read/64, error -32
11017 11:46:52.489234 <6>[ 7.899784] usb 1-1.1-port4: attempt power cycle
11018 11:46:52.571997 <6>[ 7.979238] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
11019 11:46:52.764025 <6>[ 8.171249] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
11020 11:46:53.160116 <6>[ 8.567248] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
11021 11:46:53.167343 <4>[ 8.574740] usb 1-1.1.4: Device not responding to setup address.
11022 11:46:53.376206 <4>[ 8.787199] usb 1-1.1.4: Device not responding to setup address.
11023 11:46:53.588657 <3>[ 8.999285] usb 1-1.1.4: device not accepting address 10, error -71
11024 11:46:53.675851 <6>[ 9.083249] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
11025 11:46:53.682688 <4>[ 9.090740] usb 1-1.1.4: Device not responding to setup address.
11026 11:46:53.893025 <4>[ 9.303470] usb 1-1.1.4: Device not responding to setup address.
11027 11:46:54.104450 <3>[ 9.515240] usb 1-1.1.4: device not accepting address 11, error -71
11028 11:46:54.111398 <3>[ 9.522300] usb 1-1.1-port4: unable to enumerate USB device
11029 11:47:02.585299 <6>[ 18.000279] ALSA device list:
11030 11:47:02.592462 <6>[ 18.003572] No soundcards found.
11031 11:47:02.599901 <6>[ 18.011683] Freeing unused kernel memory: 8384K
11032 11:47:02.603247 <6>[ 18.016673] Run /init as init process
11033 11:47:02.655028 <6>[ 18.066860] NET: Registered PF_INET6 protocol family
11034 11:47:02.661804 <6>[ 18.072981] Segment Routing with IPv6
11035 11:47:02.665636 <6>[ 18.076919] In-situ OAM (IOAM) with IPv6
11036 11:47:02.699353 <30>[ 18.091539] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
11037 11:47:02.702745 <30>[ 18.115476] systemd[1]: Detected architecture arm64.
11038 11:47:02.706072
11039 11:47:02.709269 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
11040 11:47:02.709374
11041 11:47:02.724471 <30>[ 18.135563] systemd[1]: Set hostname to <debian-bullseye-arm64>.
11042 11:47:02.845287 <30>[ 18.253947] systemd[1]: Queued start job for default target Graphical Interface.
11043 11:47:02.876037 <30>[ 18.288047] systemd[1]: Created slice system-getty.slice.
11044 11:47:02.882694 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
11045 11:47:02.900208 <30>[ 18.311722] systemd[1]: Created slice system-modprobe.slice.
11046 11:47:02.906650 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
11047 11:47:02.924692 <30>[ 18.336372] systemd[1]: Created slice system-serial\x2dgetty.slice.
11048 11:47:02.934822 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
11049 11:47:02.948357 <30>[ 18.360278] systemd[1]: Created slice User and Session Slice.
11050 11:47:02.955195 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
11051 11:47:02.975521 <30>[ 18.383760] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
11052 11:47:02.984897 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
11053 11:47:03.003492 <30>[ 18.411797] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
11054 11:47:03.009906 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
11055 11:47:03.033852 <30>[ 18.439212] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
11056 11:47:03.040422 <30>[ 18.451387] systemd[1]: Reached target Local Encrypted Volumes.
11057 11:47:03.047646 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
11058 11:47:03.064254 <30>[ 18.475645] systemd[1]: Reached target Paths.
11059 11:47:03.070492 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
11060 11:47:03.083483 <30>[ 18.495266] systemd[1]: Reached target Remote File Systems.
11061 11:47:03.089771 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
11062 11:47:03.107263 <30>[ 18.519264] systemd[1]: Reached target Slices.
11063 11:47:03.114127 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
11064 11:47:03.127718 <30>[ 18.539275] systemd[1]: Reached target Swap.
11065 11:47:03.130700 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
11066 11:47:03.151811 <30>[ 18.559778] systemd[1]: Listening on initctl Compatibility Named Pipe.
11067 11:47:03.157902 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
11068 11:47:03.164543 <30>[ 18.575246] systemd[1]: Listening on Journal Audit Socket.
11069 11:47:03.170939 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
11070 11:47:03.188980 <30>[ 18.600489] systemd[1]: Listening on Journal Socket (/dev/log).
11071 11:47:03.195244 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
11072 11:47:03.212235 <30>[ 18.623859] systemd[1]: Listening on Journal Socket.
11073 11:47:03.218531 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
11074 11:47:03.231936 <30>[ 18.643884] systemd[1]: Listening on udev Control Socket.
11075 11:47:03.239101 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11076 11:47:03.256683 <30>[ 18.668314] systemd[1]: Listening on udev Kernel Socket.
11077 11:47:03.263375 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11078 11:47:03.320060 <30>[ 18.731374] systemd[1]: Mounting Huge Pages File System...
11079 11:47:03.326092 Mounting [0;1;39mHuge Pages File System[0m...
11080 11:47:03.344136 <30>[ 18.755814] systemd[1]: Mounting POSIX Message Queue File System...
11081 11:47:03.350817 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11082 11:47:03.371605 <30>[ 18.783282] systemd[1]: Mounting Kernel Debug File System...
11083 11:47:03.377917 Mounting [0;1;39mKernel Debug File System[0m...
11084 11:47:03.395028 <30>[ 18.803379] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11085 11:47:03.409058 <30>[ 18.816982] systemd[1]: Starting Create list of static device nodes for the current kernel...
11086 11:47:03.415058 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11087 11:47:03.435742 <30>[ 18.848033] systemd[1]: Starting Load Kernel Module configfs...
11088 11:47:03.442431 Starting [0;1;39mLoad Kernel Module configfs[0m...
11089 11:47:03.463979 <30>[ 18.875572] systemd[1]: Starting Load Kernel Module drm...
11090 11:47:03.470378 Starting [0;1;39mLoad Kernel Module drm[0m...
11091 11:47:03.487260 <30>[ 18.895377] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11092 11:47:03.502388 <30>[ 18.913905] systemd[1]: Starting Journal Service...
11093 11:47:03.508324 Starting [0;1;39mJournal Service[0m...
11094 11:47:03.526555 <30>[ 18.937746] systemd[1]: Starting Load Kernel Modules...
11095 11:47:03.532341 Starting [0;1;39mLoad Kernel Modules[0m...
11096 11:47:03.559573 <30>[ 18.968373] systemd[1]: Starting Remount Root and Kernel File Systems...
11097 11:47:03.566838 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11098 11:47:03.582310 <30>[ 18.994316] systemd[1]: Starting Coldplug All udev Devices...
11099 11:47:03.588857 Starting [0;1;39mColdplug All udev Devices[0m...
11100 11:47:03.610638 <30>[ 19.022506] systemd[1]: Started Journal Service.
11101 11:47:03.617094 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11102 11:47:03.633612 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11103 11:47:03.657163 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11104 11:47:03.677036 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11105 11:47:03.696574 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11106 11:47:03.713173 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11107 11:47:03.733370 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11108 11:47:03.754023 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11109 11:47:03.773690 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11110 11:47:03.787375 See 'systemctl status systemd-remount-fs.service' for details.
11111 11:47:03.832703 Mounting [0;1;39mKernel Configuration File System[0m...
11112 11:47:03.855010 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11113 11:47:03.867028 <46>[ 19.275981] systemd-journald[177]: Received client request to flush runtime journal.
11114 11:47:03.879728 Starting [0;1;39mLoad/Save Random Seed[0m...
11115 11:47:03.903304 Starting [0;1;39mApply Kernel Variables[0m...
11116 11:47:03.928565 Starting [0;1;39mCreate System Users[0m...
11117 11:47:03.950568 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11118 11:47:03.968134 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11119 11:47:03.988480 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11120 11:47:04.005581 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11121 11:47:04.021657 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11122 11:47:04.041218 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11123 11:47:04.104794 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11124 11:47:04.126753 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11125 11:47:04.139900 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11126 11:47:04.155904 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11127 11:47:04.187826 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11128 11:47:04.215770 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11129 11:47:04.236563 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11130 11:47:04.261054 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11131 11:47:04.306441 Starting [0;1;39mNetwork Time Synchronization[0m...
11132 11:47:04.326941 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11133 11:47:04.360119 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11134 11:47:04.395526 [[0;32m OK [<6>[ 19.804321] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11135 11:47:04.402180 0m] Started [0;1;39mNetwork Time Synchronization[0m.
11136 11:47:04.411259 <6>[ 19.822995] remoteproc remoteproc0: scp is available
11137 11:47:04.418161 <6>[ 19.830078] remoteproc remoteproc0: powering up scp
11138 11:47:04.428829 <6>[ 19.835958] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11139 11:47:04.434614 <6>[ 19.844850] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11140 11:47:04.437844 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11141 11:47:04.467285 <3>[ 19.875507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11142 11:47:04.474289 <3>[ 19.883930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11143 11:47:04.483676 <6>[ 19.891807] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11144 11:47:04.493163 [[0;32m OK [<3>[ 19.892065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11145 11:47:04.503040 0m] Created slic<6>[ 19.899670] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11146 11:47:04.509713 <6>[ 19.899685] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11147 11:47:04.519327 e [0;1;39msyste<3>[ 19.921268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11148 11:47:04.529446 m-systemd\x2dbac<3>[ 19.937476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11149 11:47:04.539010 klight.slice[0m<3>[ 19.946816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11150 11:47:04.539097 .
11151 11:47:04.549541 <3>[ 19.956325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11152 11:47:04.552250 <6>[ 19.957453] mc: Linux media interface: v0.10
11153 11:47:04.558997 <3>[ 19.964630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11154 11:47:04.566102 <6>[ 19.976373] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11155 11:47:04.575621 <6>[ 19.977307] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11156 11:47:04.583187 <6>[ 19.992942] remoteproc remoteproc0: remote processor scp is now up
11157 11:47:04.592209 [[0;32m OK [<3>[ 20.000524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11158 11:47:04.598897 0m] Reached targ<6>[ 20.002436] Bluetooth: Core ver 2.22
11159 11:47:04.605182 et [0;1;39mSyst<6>[ 20.005928] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11160 11:47:04.615103 <4>[ 20.006098] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11161 11:47:04.621803 <4>[ 20.006173] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11162 11:47:04.632329 em Time Set[0m.<3>[ 20.016622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11163 11:47:04.632415
11164 11:47:04.634784 <6>[ 20.029287] NET: Registered PF_BLUETOOTH protocol family
11165 11:47:04.645162 <3>[ 20.030635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11166 11:47:04.651932 <4>[ 20.033090] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11167 11:47:04.658688 <4>[ 20.033090] Fallback method does not support PEC.
11168 11:47:04.665094 <6>[ 20.037899] Bluetooth: HCI device and connection manager initialized
11169 11:47:04.672158 <3>[ 20.047383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11170 11:47:04.678670 <6>[ 20.053643] Bluetooth: HCI socket layer initialized
11171 11:47:04.681880 <6>[ 20.054616] videodev: Linux video capture interface: v2.00
11172 11:47:04.691714 <3>[ 20.067605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11173 11:47:04.698474 <6>[ 20.074871] Bluetooth: L2CAP socket layer initialized
11174 11:47:04.701597 <6>[ 20.075225] usbcore: registered new interface driver r8152
11175 11:47:04.708591 <6>[ 20.075582] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11176 11:47:04.715614 <6>[ 20.075589] pci_bus 0000:00: root bus resource [bus 00-ff]
11177 11:47:04.722118 <6>[ 20.075595] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11178 11:47:04.732741 <6>[ 20.075601] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11179 11:47:04.738823 <6>[ 20.075639] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11180 11:47:04.745033 <6>[ 20.075660] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11181 11:47:04.751856 <6>[ 20.075747] pci 0000:00:00.0: supports D1 D2
11182 11:47:04.758639 <6>[ 20.075750] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11183 11:47:04.765529 <3>[ 20.077630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11184 11:47:04.775513 <3>[ 20.081529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11185 11:47:04.778767 <6>[ 20.089603] Bluetooth: SCO socket layer initialized
11186 11:47:04.788581 <6>[ 20.092275] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11187 11:47:04.795902 <3>[ 20.094794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11188 11:47:04.801807 <6>[ 20.099040] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11189 11:47:04.809441 <6>[ 20.099069] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11190 11:47:04.816423 <6>[ 20.099087] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11191 11:47:04.825575 <6>[ 20.099101] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11192 11:47:04.829005 <6>[ 20.099214] pci 0000:01:00.0: supports D1 D2
11193 11:47:04.835633 <6>[ 20.099216] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11194 11:47:04.845581 <3>[ 20.103093] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11195 11:47:04.851899 <3>[ 20.108540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11196 11:47:04.861784 <3>[ 20.108545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11197 11:47:04.868682 <3>[ 20.108606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11198 11:47:04.875053 <6>[ 20.115619] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11199 11:47:04.885165 <6>[ 20.115651] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11200 11:47:04.895136 <3>[ 20.139326] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11201 11:47:04.901404 <6>[ 20.139651] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11202 11:47:04.911691 <3>[ 20.175236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11203 11:47:04.918554 <6>[ 20.183408] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11204 11:47:04.929158 <6>[ 20.183423] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11205 11:47:04.936332 <6>[ 20.183436] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11206 11:47:04.942850 <6>[ 20.183448] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11207 11:47:04.950358 <6>[ 20.187171] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
11208 11:47:04.959670 <6>[ 20.197966] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11209 11:47:04.962899 <6>[ 20.204915] pci 0000:00:00.0: PCI bridge to [bus 01]
11210 11:47:04.972875 <6>[ 20.204922] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11211 11:47:04.979365 <6>[ 20.205117] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11212 11:47:04.990116 <6>[ 20.216078] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11213 11:47:04.996479 <6>[ 20.216136] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11214 11:47:05.003434 <6>[ 20.219822] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11215 11:47:05.013590 <3>[ 20.227173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11216 11:47:05.020131 <6>[ 20.227191] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11217 11:47:05.026477 <6>[ 20.234803] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11218 11:47:05.033558 <6>[ 20.242476] usbcore: registered new interface driver cdc_ether
11219 11:47:05.040003 <6>[ 20.264473] usbcore: registered new interface driver btusb
11220 11:47:05.048128 <5>[ 20.265798] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11221 11:47:05.053365 <6>[ 20.270433] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11222 11:47:05.063375 <4>[ 20.270672] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11223 11:47:05.070199 <3>[ 20.270682] Bluetooth: hci0: Failed to load firmware file (-2)
11224 11:47:05.076609 <3>[ 20.270686] Bluetooth: hci0: Failed to set up firmware (-2)
11225 11:47:05.086518 <4>[ 20.270690] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11226 11:47:05.093319 <5>[ 20.277833] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11227 11:47:05.103249 <4>[ 20.277891] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11228 11:47:05.106691 <6>[ 20.277897] cfg80211: failed to load regulatory.db
11229 11:47:05.115343 <6>[ 20.287132] usbcore: registered new interface driver r8153_ecm
11230 11:47:05.121208 <6>[ 20.295778] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11231 11:47:05.130980 <6>[ 20.296228] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11232 11:47:05.137707 <6>[ 20.296360] usbcore: registered new interface driver uvcvideo
11233 11:47:05.147731 <4>[ 20.306137] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11234 11:47:05.157899 <3>[ 20.345054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11235 11:47:05.164765 <4>[ 20.352486] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11236 11:47:05.174296 <3>[ 20.371589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11237 11:47:05.180915 <6>[ 20.372198] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11238 11:47:05.188651 <6>[ 20.372318] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11239 11:47:05.191261 <6>[ 20.391058] mt7921e 0000:01:00.0: ASIC revision: 79610010
11240 11:47:05.201629 <3>[ 20.419344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11241 11:47:05.204900 <6>[ 20.435222] r8152 1-1.1.1:1.0 eth0: v1.12.13
11242 11:47:05.215357 <3>[ 20.438717] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
11243 11:47:05.221574 <3>[ 20.463733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11244 11:47:05.227881 <6>[ 20.484457] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11245 11:47:05.241368 <4>[ 20.534270] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11246 11:47:05.247737 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11247 11:47:05.303289 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11248 11:47:05.336398 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11249 11:47:05.359945 <4>[ 20.765318] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11250 11:47:05.475123 <4>[ 20.880708] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11251 11:47:05.483880 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11252 11:47:05.499161 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11253 11:47:05.518809 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11254 11:47:05.534247 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11255 11:47:05.547119 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11256 11:47:05.571251 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11257 11:47:05.590138 [[0;32m OK [<4>[ 20.996816] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11258 11:47:05.593429 0m] Reached target [0;1;39mSockets[0m.
11259 11:47:05.611831 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11260 11:47:05.631082 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11261 11:47:05.675512 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11262 11:47:05.712999 <4>[ 21.118704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11263 11:47:05.727102 Starting [0;1;39mUser Login Management[0m...
11264 11:47:05.746343 Starting [0;1;39mPermit User Sessions[0m...
11265 11:47:05.762434 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11266 11:47:05.791737 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11267 11:47:05.814368 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11268 11:47:05.832899 [[0;32m OK [0m] Reached target [0;1;39mLogi<4>[ 21.237961] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11269 11:47:05.835911 n Prompts[0m.
11270 11:47:05.855874 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11271 11:47:05.876206 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11272 11:47:05.890571 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11273 11:47:05.909533 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11274 11:47:05.928219 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11275 11:47:05.952109 <4>[ 21.357585] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11276 11:47:05.977017 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11277 11:47:06.015486 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11278 11:47:06.072238 <4>[ 21.477970] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11279 11:47:06.072381
11280 11:47:06.072478
11281 11:47:06.079318 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11282 11:47:06.079404
11283 11:47:06.082190 debian-bullseye-arm64 login: root (automatic login)
11284 11:47:06.082275
11285 11:47:06.082361
11286 11:47:06.115884 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11287 11:47:06.116002
11288 11:47:06.122613 The programs included with the Debian GNU/Linux system are free software;
11289 11:47:06.129107 the exact distribution terms for each program are described in the
11290 11:47:06.132501 individual files in /usr/share/doc/*/copyright.
11291 11:47:06.132585
11292 11:47:06.139847 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11293 11:47:06.143142 permitted by applicable law.
11294 11:47:06.143701 Matched prompt #10: / #
11296 11:47:06.143925 Setting prompt string to ['/ #']
11297 11:47:06.144076 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11299 11:47:06.144405 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11300 11:47:06.144500 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
11301 11:47:06.144569 Setting prompt string to ['/ #']
11302 11:47:06.144628 Forcing a shell prompt, looking for ['/ #']
11304 11:47:06.194845 / #
11305 11:47:06.195009 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11306 11:47:06.195105 Waiting using forced prompt support (timeout 00:02:30)
11307 11:47:06.195233 <4>[ 21.597883] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11308 11:47:06.200050
11309 11:47:06.241871 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11310 11:47:06.242052 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
11311 11:47:06.242176 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11312 11:47:06.242300 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
11313 11:47:06.242405 end: 2 depthcharge-action (duration 00:01:54) [common]
11314 11:47:06.242493 start: 3 lava-test-retry (timeout 00:05:00) [common]
11315 11:47:06.242577 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11316 11:47:06.242662 Using namespace: common
11318 11:47:06.343009 / # #
11319 11:47:06.343200 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11320 11:47:06.343348 #<4>[ 21.717446] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11321 11:47:06.348347
11322 11:47:06.348629 Using /lava-12074004
11324 11:47:06.449023 / # export SHELL=/bin/sh
11325 11:47:06.449233 export SHELL=/bin/sh<3>[ 21.835117] mt7921e 0000:01:00.0: hardware init failed
11326 11:47:06.454393
11328 11:47:06.554901 / # . /lava-12074004/environment
11329 11:47:06.560412 . /lava-12074004/environment
11331 11:47:06.661078 / # /lava-12074004/bin/lava-test-runner /lava-12074004/0
11332 11:47:06.661419 Test shell timeout: 10s (minimum of the action and connection timeout)
11333 11:47:06.666359 /lava-12074004/bin/lava-test-runner /lava-12074004/0
11334 11:47:06.686560 + export TESTRUN_ID=0_sleep
11335 11:47:06.689610 + cd /lava-12074004/0/tests/0_sleep
11336 11:47:06.693227 + cat uuid
11337 11:47:06.693360 + UUID=12074004_1.5.2.3.1
11338 11:47:06.696387 + set +x
11339 11:47:06.699845 <LAVA_SIGNAL_STARTRUN 0_sleep 12074004_1.5.2.3.1>
11340 11:47:06.700163 Received signal: <STARTRUN> 0_sleep 12074004_1.5.2.3.1
11341 11:47:06.700293 Starting test lava.0_sleep (12074004_1.5.2.3.1)
11342 11:47:06.700444 Skipping test definition patterns.
11343 11:47:06.702890 + ./config/lava/sleep/sleep.sh mem freeze
11344 11:47:06.706434 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11346 11:47:06.709378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11347 11:47:06.713017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11348 11:47:06.713270 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11350 11:47:06.716105 rtcwake: assuming RTC uses UTC ...
11351 11:47:06.723167 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:13 2023
11352 11:47:06.725970 <6>[ 22.139567] PM: suspend entry (deep)
11353 11:47:06.732767 <6>[ 22.143995] Filesystems sync: 0.000 seconds
11354 11:47:06.739969 <6>[ 22.150622] Freezing user space processes
11355 11:47:06.745780 <6>[ 22.156955] Freezing user space processes completed (elapsed 0.002 seconds)
11356 11:47:06.749135 <6>[ 22.164221] OOM killer disabled.
11357 11:47:06.755849 <6>[ 22.167711] Freezing remaining freezable tasks
11358 11:47:06.765709 <6>[ 22.173838] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11359 11:47:06.772239 <6>[ 22.181498] printk: Suspending console(s) (use no_console_suspend to debug)
11360 11:47:10.277354 <3>[ 25.423310] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11361 11:47:10.290264 <3>[ 25.423350] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11362 11:47:10.296789 <3>[ 25.423409] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11363 11:47:10.303550 <3>[ 25.423470] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11364 11:47:10.313568 <3>[ 25.423841] PM: Some devices failed to suspend, or early wake event detected
11365 11:47:10.320009 <4>[ 25.440498] typec port0-partner: PM: parent port0 should not be sleeping
11366 11:47:10.326700 <4>[ 25.458976] typec port0-cable: PM: parent port0 should not be sleeping
11367 11:47:10.329835 <6>[ 25.743315] OOM killer enabled.
11368 11:47:10.337033 <6>[ 25.746717] Restarting tasks ... done.
11369 11:47:10.339682 <5>[ 25.753044] random: crng reseeded on system resumption
11370 11:47:10.346553 <6>[ 25.762538] PM: suspend exit
11371 11:47:10.351239 rtcwake: write error
11372 11:47:10.359080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11373 11:47:10.359524 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11375 11:47:10.362374 rtcwake: assuming RTC uses UTC ...
11376 11:47:10.368685 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:17 2023
11377 11:47:10.381670 <6>[ 25.794165] PM: suspend entry (deep)
11378 11:47:10.385204 <6>[ 25.798070] Filesystems sync: 0.000 seconds
11379 11:47:10.388330 <6>[ 25.803190] Freezing user space processes
11380 11:47:10.400086 <6>[ 25.809069] Freezing user space processes completed (elapsed 0.001 seconds)
11381 11:47:10.403068 <6>[ 25.816293] OOM killer disabled.
11382 11:47:10.406484 <6>[ 25.819774] Freezing remaining freezable tasks
11383 11:47:10.422629 <6>[ 25.831156] usb 1-1.1.4: new full-speed USB device number 12 using xhci-mtk
11384 11:47:10.506593 <3>[ 25.919211] usb 1-1.1.4: device descriptor read/64, error -32
11385 11:47:10.698805 <3>[ 26.111263] usb 1-1.1.4: device descriptor read/64, error -32
11386 11:47:10.893959 <6>[ 26.303073] usb 1-1.1.4: new full-speed USB device number 13 using xhci-mtk
11387 11:47:10.979002 <3>[ 26.391273] usb 1-1.1.4: device descriptor read/64, error -32
11388 11:47:11.170718 <3>[ 26.583398] usb 1-1.1.4: device descriptor read/64, error -32
11389 11:47:11.284059 <6>[ 26.695580] usb 1-1.1-port4: attempt power cycle
11390 11:47:11.893823 <6>[ 27.303117] usb 1-1.1.4: new full-speed USB device number 14 using xhci-mtk
11391 11:47:11.900859 <4>[ 27.310542] usb 1-1.1.4: Device not responding to setup address.
11392 11:47:12.110815 <4>[ 27.523368] usb 1-1.1.4: Device not responding to setup address.
11393 11:47:12.322473 <3>[ 27.735104] usb 1-1.1.4: device not accepting address 14, error -71
11394 11:47:12.409739 <6>[ 27.819250] usb 1-1.1.4: new full-speed USB device number 15 using xhci-mtk
11395 11:47:12.416224 <4>[ 27.826649] usb 1-1.1.4: Device not responding to setup address.
11396 11:47:12.626704 <4>[ 28.039525] usb 1-1.1.4: Device not responding to setup address.
11397 11:47:12.838599 <3>[ 28.251241] usb 1-1.1.4: device not accepting address 15, error -71
11398 11:47:12.845523 <3>[ 28.258264] usb 1-1.1-port4: unable to enumerate USB device
11399 11:47:12.863331 <6>[ 28.272586] Freezing remaining freezable tasks completed (elapsed 2.448 seconds)
11400 11:47:12.869573 <6>[ 28.280295] printk: Suspending console(s) (use no_console_suspend to debug)
11401 11:47:16.164399 <3>[ 31.311263] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11402 11:47:16.174076 <3>[ 31.311298] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11403 11:47:16.184225 <3>[ 31.311348] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11404 11:47:16.190341 <3>[ 31.311395] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11405 11:47:16.201320 <3>[ 31.311682] PM: Some devices failed to suspend, or early wake event detected
11406 11:47:16.203998 <6>[ 31.617382] OOM killer enabled.
11407 11:47:16.210585 <6>[ 31.620798] Restarting tasks ... done.
11408 11:47:16.217120 <5>[ 31.628619] random: crng reseeded on system resumption
11409 11:47:16.220314 <6>[ 31.634750] PM: suspend exit
11410 11:47:16.220425 rtcwake: write error
11411 11:47:16.230402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11412 11:47:16.230705 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11414 11:47:16.233372 rtcwake: assuming RTC uses UTC ...
11415 11:47:16.240015 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:22 2023
11416 11:47:16.252847 <6>[ 31.666159] PM: suspend entry (deep)
11417 11:47:16.255986 <6>[ 31.670071] Filesystems sync: 0.000 seconds
11418 11:47:16.263066 <6>[ 31.675205] Freezing user space processes
11419 11:47:16.269285 <6>[ 31.681103] Freezing user space processes completed (elapsed 0.001 seconds)
11420 11:47:16.273036 <6>[ 31.688326] OOM killer disabled.
11421 11:47:16.279030 <6>[ 31.691808] Freezing remaining freezable tasks
11422 11:47:16.293271 <6>[ 31.703159] usb 1-1.1.4: new full-speed USB device number 16 using xhci-mtk
11423 11:47:16.377758 <3>[ 31.791183] usb 1-1.1.4: device descriptor read/64, error -32
11424 11:47:16.570521 <3>[ 31.983456] usb 1-1.1.4: device descriptor read/64, error -32
11425 11:47:16.764940 <6>[ 32.175109] usb 1-1.1.4: new full-speed USB device number 17 using xhci-mtk
11426 11:47:16.850228 <3>[ 32.263443] usb 1-1.1.4: device descriptor read/64, error -32
11427 11:47:17.042119 <3>[ 32.455290] usb 1-1.1.4: device descriptor read/64, error -32
11428 11:47:17.154418 <6>[ 32.567645] usb 1-1.1-port4: attempt power cycle
11429 11:47:17.765163 <6>[ 33.175110] usb 1-1.1.4: new full-speed USB device number 18 using xhci-mtk
11430 11:47:17.771289 <4>[ 33.182501] usb 1-1.1.4: Device not responding to setup address.
11431 11:47:17.982023 <4>[ 33.395339] usb 1-1.1.4: Device not responding to setup address.
11432 11:47:18.193707 <3>[ 33.607242] usb 1-1.1.4: device not accepting address 18, error -71
11433 11:47:18.280752 <6>[ 33.691249] usb 1-1.1.4: new full-speed USB device number 19 using xhci-mtk
11434 11:47:18.287215 <4>[ 33.698640] usb 1-1.1.4: Device not responding to setup address.
11435 11:47:18.497651 <4>[ 33.911480] usb 1-1.1.4: Device not responding to setup address.
11436 11:47:18.709673 <3>[ 34.123110] usb 1-1.1.4: device not accepting address 19, error -71
11437 11:47:18.716531 <3>[ 34.130136] usb 1-1.1-port4: unable to enumerate USB device
11438 11:47:18.727036 <6>[ 34.136296] Freezing remaining freezable tasks completed (elapsed 2.439 seconds)
11439 11:47:18.733643 <6>[ 34.143994] printk: Suspending console(s) (use no_console_suspend to debug)
11440 11:47:22.051284 <3>[ 37.199307] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11441 11:47:22.061175 <3>[ 37.199342] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11442 11:47:22.071748 <3>[ 37.199392] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11443 11:47:22.078377 <3>[ 37.199438] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11444 11:47:22.087742 <3>[ 37.199724] PM: Some devices failed to suspend, or early wake event detected
11445 11:47:22.091613 <6>[ 37.505150] OOM killer enabled.
11446 11:47:22.097314 <6>[ 37.508572] Restarting tasks ... done.
11447 11:47:22.104178 <5>[ 37.516333] random: crng reseeded on system resumption
11448 11:47:22.107862 <6>[ 37.524013] PM: suspend exit
11449 11:47:22.111373 rtcwake: write error
11450 11:47:22.118306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11451 11:47:22.118566 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11453 11:47:22.121071 rtcwake: assuming RTC uses UTC ...
11454 11:47:22.127911 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:28 2023
11455 11:47:22.140523 <6>[ 37.554604] PM: suspend entry (deep)
11456 11:47:22.144010 <6>[ 37.558498] Filesystems sync: 0.000 seconds
11457 11:47:22.147588 <6>[ 37.563591] Freezing user space processes
11458 11:47:22.159177 <6>[ 37.569598] Freezing user space processes completed (elapsed 0.001 seconds)
11459 11:47:22.162334 <6>[ 37.576835] OOM killer disabled.
11460 11:47:22.165405 <6>[ 37.580318] Freezing remaining freezable tasks
11461 11:47:22.176461 <6>[ 37.587158] usb 1-1.1.4: new full-speed USB device number 20 using xhci-mtk
11462 11:47:22.261305 <3>[ 37.675185] usb 1-1.1.4: device descriptor read/64, error -32
11463 11:47:22.453932 <3>[ 37.867276] usb 1-1.1.4: device descriptor read/64, error -32
11464 11:47:22.648323 <6>[ 38.059120] usb 1-1.1.4: new full-speed USB device number 21 using xhci-mtk
11465 11:47:22.733826 <3>[ 38.147448] usb 1-1.1.4: device descriptor read/64, error -32
11466 11:47:22.925437 <3>[ 38.339295] usb 1-1.1.4: device descriptor read/64, error -32
11467 11:47:23.037696 <6>[ 38.451647] usb 1-1.1-port4: attempt power cycle
11468 11:47:23.648297 <6>[ 39.059104] usb 1-1.1.4: new full-speed USB device number 22 using xhci-mtk
11469 11:47:23.654788 <4>[ 39.066579] usb 1-1.1.4: Device not responding to setup address.
11470 11:47:23.865324 <4>[ 39.279327] usb 1-1.1.4: Device not responding to setup address.
11471 11:47:24.076905 <3>[ 39.491134] usb 1-1.1.4: device not accepting address 22, error -71
11472 11:47:24.163915 <6>[ 39.575114] usb 1-1.1.4: new full-speed USB device number 23 using xhci-mtk
11473 11:47:24.171195 <4>[ 39.582613] usb 1-1.1.4: Device not responding to setup address.
11474 11:47:24.380891 <4>[ 39.795341] usb 1-1.1.4: Device not responding to setup address.
11475 11:47:24.593116 <3>[ 40.007288] usb 1-1.1.4: device not accepting address 23, error -71
11476 11:47:24.600355 <3>[ 40.014231] usb 1-1.1-port4: unable to enumerate USB device
11477 11:47:24.613215 <6>[ 40.024179] Freezing remaining freezable tasks completed (elapsed 2.439 seconds)
11478 11:47:24.619566 <6>[ 40.031877] printk: Suspending console(s) (use no_console_suspend to debug)
11479 11:47:27.943078 <3>[ 43.087311] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11480 11:47:27.952953 <3>[ 43.087345] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11481 11:47:27.962771 <3>[ 43.087396] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11482 11:47:27.969188 <3>[ 43.087442] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11483 11:47:27.979299 <3>[ 43.087787] PM: Some devices failed to suspend, or early wake event detected
11484 11:47:27.982754 <6>[ 43.397532] OOM killer enabled.
11485 11:47:27.985979 <6>[ 43.400945] Restarting tasks ... done.
11486 11:47:27.992719 <5>[ 43.407292] random: crng reseeded on system resumption
11487 11:47:27.996525 <6>[ 43.413903] PM: suspend exit
11488 11:47:27.999111 rtcwake: write error
11489 11:47:28.007529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11490 11:47:28.007895 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11492 11:47:28.010522 rtcwake: assuming RTC uses UTC ...
11493 11:47:28.017331 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:34 2023
11494 11:47:28.029825 <6>[ 43.444469] PM: suspend entry (deep)
11495 11:47:28.033613 <6>[ 43.448366] Filesystems sync: 0.000 seconds
11496 11:47:28.036169 <6>[ 43.453429] Freezing user space processes
11497 11:47:28.047980 <6>[ 43.459043] Freezing user space processes completed (elapsed 0.001 seconds)
11498 11:47:28.050995 <6>[ 43.466260] OOM killer disabled.
11499 11:47:28.055087 <6>[ 43.469740] Freezing remaining freezable tasks
11500 11:47:28.067919 <6>[ 43.479098] usb 1-1.1.4: new full-speed USB device number 24 using xhci-mtk
11501 11:47:28.152683 <3>[ 43.567208] usb 1-1.1.4: device descriptor read/64, error -32
11502 11:47:28.344648 <3>[ 43.759417] usb 1-1.1.4: device descriptor read/64, error -32
11503 11:47:28.539646 <6>[ 43.951093] usb 1-1.1.4: new full-speed USB device number 25 using xhci-mtk
11504 11:47:28.624537 <3>[ 44.039414] usb 1-1.1.4: device descriptor read/64, error -32
11505 11:47:28.816832 <3>[ 44.231297] usb 1-1.1.4: device descriptor read/64, error -32
11506 11:47:28.928670 <6>[ 44.343639] usb 1-1.1-port4: attempt power cycle
11507 11:47:29.539602 <6>[ 44.951118] usb 1-1.1.4: new full-speed USB device number 26 using xhci-mtk
11508 11:47:29.546002 <4>[ 44.958505] usb 1-1.1.4: Device not responding to setup address.
11509 11:47:29.756353 <4>[ 45.171378] usb 1-1.1.4: Device not responding to setup address.
11510 11:47:29.968225 <3>[ 45.383241] usb 1-1.1.4: device not accepting address 26, error -71
11511 11:47:30.055901 <6>[ 45.467250] usb 1-1.1.4: new full-speed USB device number 27 using xhci-mtk
11512 11:47:30.062147 <4>[ 45.474642] usb 1-1.1.4: Device not responding to setup address.
11513 11:47:30.273938 <4>[ 45.687494] usb 1-1.1.4: Device not responding to setup address.
11514 11:47:30.484698 <3>[ 45.899102] usb 1-1.1.4: device not accepting address 27, error -71
11515 11:47:30.491190 <3>[ 45.906135] usb 1-1.1-port4: unable to enumerate USB device
11516 11:47:30.501277 <6>[ 45.912364] Freezing remaining freezable tasks completed (elapsed 2.437 seconds)
11517 11:47:30.507729 <6>[ 45.920106] printk: Suspending console(s) (use no_console_suspend to debug)
11518 11:47:33.826949 <6>[ 48.207360] vpu: disabling
11519 11:47:33.830421 <6>[ 48.207503] vproc2: disabling
11520 11:47:33.833770 <6>[ 48.207563] vproc1: disabling
11521 11:47:33.837181 <6>[ 48.207622] vaud18: disabling
11522 11:47:33.840112 <6>[ 48.207891] vsram_others: disabling
11523 11:47:33.843347 <6>[ 48.208106] va09: disabling
11524 11:47:33.846853 <6>[ 48.208190] vsram_md: disabling
11525 11:47:33.850079 <6>[ 48.208330] Vgpu: disabling
11526 11:47:33.857008 <3>[ 48.975262] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11527 11:47:33.867107 <3>[ 48.975297] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11528 11:47:33.877054 <3>[ 48.975347] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11529 11:47:33.883104 <3>[ 48.975394] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11530 11:47:33.889921 <3>[ 48.975664] PM: Some devices failed to suspend, or early wake event detected
11531 11:47:33.893135 <6>[ 49.311440] OOM killer enabled.
11532 11:47:33.901353 <6>[ 49.314840] Restarting tasks ... done.
11533 11:47:33.904824 <5>[ 49.320706] random: crng reseeded on system resumption
11534 11:47:33.908183 <6>[ 49.327006] PM: suspend exit
11535 11:47:33.911872 rtcwake: write error
11536 11:47:33.919249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11537 11:47:33.919518 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11539 11:47:33.922367 rtcwake: assuming RTC uses UTC ...
11540 11:47:33.929250 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:40 2023
11541 11:47:33.942565 <6>[ 49.357546] PM: suspend entry (deep)
11542 11:47:33.945439 <6>[ 49.361461] Filesystems sync: 0.000 seconds
11543 11:47:33.952419 <6>[ 49.366643] Freezing user space processes
11544 11:47:33.959063 <6>[ 49.372816] Freezing user space processes completed (elapsed 0.001 seconds)
11545 11:47:33.962025 <6>[ 49.380102] OOM killer disabled.
11546 11:47:33.968812 <6>[ 49.383597] Freezing remaining freezable tasks
11547 11:47:33.986874 <6>[ 49.399013] usb 1-1.1.4: new full-speed USB device number 28 using xhci-mtk
11548 11:47:34.068777 <3>[ 49.483297] usb 1-1.1.4: device descriptor read/64, error -32
11549 11:47:34.260123 <3>[ 49.675457] usb 1-1.1.4: device descriptor read/64, error -32
11550 11:47:34.455092 <6>[ 49.867122] usb 1-1.1.4: new full-speed USB device number 29 using xhci-mtk
11551 11:47:34.540921 <3>[ 49.955463] usb 1-1.1.4: device descriptor read/64, error -32
11552 11:47:34.731977 <3>[ 50.147299] usb 1-1.1.4: device descriptor read/64, error -32
11553 11:47:34.844105 <6>[ 50.259636] usb 1-1.1-port4: attempt power cycle
11554 11:47:35.455256 <6>[ 50.867119] usb 1-1.1.4: new full-speed USB device number 30 using xhci-mtk
11555 11:47:35.461662 <4>[ 50.874509] usb 1-1.1.4: Device not responding to setup address.
11556 11:47:35.672090 <4>[ 51.087408] usb 1-1.1.4: Device not responding to setup address.
11557 11:47:35.883745 <3>[ 51.299240] usb 1-1.1.4: device not accepting address 30, error -71
11558 11:47:35.971381 <6>[ 51.383250] usb 1-1.1.4: new full-speed USB device number 31 using xhci-mtk
11559 11:47:35.977776 <4>[ 51.390642] usb 1-1.1.4: Device not responding to setup address.
11560 11:47:36.187700 <4>[ 51.603314] usb 1-1.1.4: Device not responding to setup address.
11561 11:47:36.399824 <3>[ 51.815108] usb 1-1.1.4: device not accepting address 31, error -71
11562 11:47:36.406345 <3>[ 51.822149] usb 1-1.1-port4: unable to enumerate USB device
11563 11:47:36.416424 <6>[ 51.828959] Freezing remaining freezable tasks completed (elapsed 2.440 seconds)
11564 11:47:36.423527 <6>[ 51.836665] printk: Suspending console(s) (use no_console_suspend to debug)
11565 11:47:39.723917 <3>[ 54.863259] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11566 11:47:39.735858 <3>[ 54.863293] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11567 11:47:39.742480 <3>[ 54.863344] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11568 11:47:39.749149 <3>[ 54.863390] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11569 11:47:39.758468 <3>[ 54.863676] PM: Some devices failed to suspend, or early wake event detected
11570 11:47:39.761750 <6>[ 55.177717] OOM killer enabled.
11571 11:47:39.770565 <6>[ 55.181133] Restarting tasks ... done.
11572 11:47:39.777249 <5>[ 55.191949] random: crng reseeded on system resumption
11573 11:47:39.780675 <6>[ 55.198517] PM: suspend exit
11574 11:47:39.783602 rtcwake: write error
11575 11:47:39.790513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11576 11:47:39.791216 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11578 11:47:39.793812 rtcwake: assuming RTC uses UTC ...
11579 11:47:39.800507 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:46 2023
11580 11:47:39.813585 <6>[ 55.228747] PM: suspend entry (deep)
11581 11:47:39.817023 <6>[ 55.232668] Filesystems sync: 0.000 seconds
11582 11:47:39.819731 <6>[ 55.237755] Freezing user space processes
11583 11:47:39.831935 <6>[ 55.243697] Freezing user space processes completed (elapsed 0.001 seconds)
11584 11:47:39.834912 <6>[ 55.250918] OOM killer disabled.
11585 11:47:39.837940 <6>[ 55.254395] Freezing remaining freezable tasks
11586 11:47:39.851001 <6>[ 55.263224] usb 1-1.1.4: new full-speed USB device number 32 using xhci-mtk
11587 11:47:39.935626 <3>[ 55.351149] usb 1-1.1.4: device descriptor read/64, error -32
11588 11:47:40.128230 <3>[ 55.543456] usb 1-1.1.4: device descriptor read/64, error -32
11589 11:47:40.323141 <6>[ 55.735121] usb 1-1.1.4: new full-speed USB device number 33 using xhci-mtk
11590 11:47:40.408119 <3>[ 55.823456] usb 1-1.1.4: device descriptor read/64, error -32
11591 11:47:40.599799 <3>[ 56.015298] usb 1-1.1.4: device descriptor read/64, error -32
11592 11:47:40.712619 <6>[ 56.127611] usb 1-1.1-port4: attempt power cycle
11593 11:47:41.322182 <6>[ 56.735113] usb 1-1.1.4: new full-speed USB device number 34 using xhci-mtk
11594 11:47:41.328807 <4>[ 56.742498] usb 1-1.1.4: Device not responding to setup address.
11595 11:47:41.539562 <4>[ 56.955319] usb 1-1.1.4: Device not responding to setup address.
11596 11:47:41.751145 <3>[ 57.167108] usb 1-1.1.4: device not accepting address 34, error -71
11597 11:47:41.839060 <6>[ 57.251116] usb 1-1.1.4: new full-speed USB device number 35 using xhci-mtk
11598 11:47:41.845383 <4>[ 57.258501] usb 1-1.1.4: Device not responding to setup address.
11599 11:47:42.056143 <4>[ 57.471489] usb 1-1.1.4: Device not responding to setup address.
11600 11:47:42.267414 <3>[ 57.683242] usb 1-1.1.4: device not accepting address 35, error -71
11601 11:47:42.274575 <3>[ 57.690258] usb 1-1.1-port4: unable to enumerate USB device
11602 11:47:42.292392 <6>[ 57.704590] Freezing remaining freezable tasks completed (elapsed 2.445 seconds)
11603 11:47:42.299066 <6>[ 57.712300] printk: Suspending console(s) (use no_console_suspend to debug)
11604 11:47:45.605813 <3>[ 60.751259] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11605 11:47:45.615419 <3>[ 60.751293] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11606 11:47:45.625929 <3>[ 60.751343] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11607 11:47:45.631801 <3>[ 60.751390] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11608 11:47:45.641885 <3>[ 60.751675] PM: Some devices failed to suspend, or early wake event detected
11609 11:47:45.645662 <6>[ 61.061443] OOM killer enabled.
11610 11:47:45.648474 <6>[ 61.064858] Restarting tasks ... done.
11611 11:47:45.654776 <5>[ 61.070955] random: crng reseeded on system resumption
11612 11:47:45.658406 <6>[ 61.077334] PM: suspend exit
11613 11:47:45.661941 rtcwake: write error
11614 11:47:45.668337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11615 11:47:45.669085 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11617 11:47:45.671643 rtcwake: assuming RTC uses UTC ...
11618 11:47:45.678852 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:52 2023
11619 11:47:45.693152 <6>[ 61.109275] PM: suspend entry (deep)
11620 11:47:45.696672 <6>[ 61.113325] Filesystems sync: 0.000 seconds
11621 11:47:45.702761 <6>[ 61.118596] Freezing user space processes
11622 11:47:45.709643 <6>[ 61.124960] Freezing user space processes completed (elapsed 0.002 seconds)
11623 11:47:45.712851 <6>[ 61.132208] OOM killer disabled.
11624 11:47:45.719442 <6>[ 61.135705] Freezing remaining freezable tasks
11625 11:47:45.734100 <6>[ 61.147079] usb 1-1.1.4: new full-speed USB device number 36 using xhci-mtk
11626 11:47:45.815101 <3>[ 61.231306] usb 1-1.1.4: device descriptor read/64, error -32
11627 11:47:46.007366 <3>[ 61.423320] usb 1-1.1.4: device descriptor read/64, error -32
11628 11:47:46.202133 <6>[ 61.615130] usb 1-1.1.4: new full-speed USB device number 37 using xhci-mtk
11629 11:47:46.287238 <3>[ 61.703293] usb 1-1.1.4: device descriptor read/64, error -32
11630 11:47:46.479082 <3>[ 61.895441] usb 1-1.1.4: device descriptor read/64, error -32
11631 11:47:46.591525 <6>[ 62.007793] usb 1-1.1-port4: attempt power cycle
11632 11:47:47.202325 <6>[ 62.615251] usb 1-1.1.4: new full-speed USB device number 38 using xhci-mtk
11633 11:47:47.208926 <4>[ 62.622674] usb 1-1.1.4: Device not responding to setup address.
11634 11:47:47.418892 <4>[ 62.835486] usb 1-1.1.4: Device not responding to setup address.
11635 11:47:47.631007 <3>[ 63.047108] usb 1-1.1.4: device not accepting address 38, error -71
11636 11:47:47.717805 <6>[ 63.131118] usb 1-1.1.4: new full-speed USB device number 39 using xhci-mtk
11637 11:47:47.724610 <4>[ 63.138508] usb 1-1.1.4: Device not responding to setup address.
11638 11:47:47.935311 <4>[ 63.351342] usb 1-1.1.4: Device not responding to setup address.
11639 11:47:48.146913 <3>[ 63.563162] usb 1-1.1.4: device not accepting address 39, error -71
11640 11:47:48.153744 <3>[ 63.570197] usb 1-1.1-port4: unable to enumerate USB device
11641 11:47:48.171533 <6>[ 63.584531] Freezing remaining freezable tasks completed (elapsed 2.444 seconds)
11642 11:47:48.178542 <6>[ 63.592235] printk: Suspending console(s) (use no_console_suspend to debug)
11643 11:47:51.496610 <3>[ 66.639307] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11644 11:47:51.509300 <3>[ 66.639346] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11645 11:47:51.516473 <3>[ 66.639397] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11646 11:47:51.523193 <3>[ 66.639445] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11647 11:47:51.532801 <3>[ 66.639776] PM: Some devices failed to suspend, or early wake event detected
11648 11:47:51.536084 <6>[ 66.953309] OOM killer enabled.
11649 11:47:51.542766 <6>[ 66.956728] Restarting tasks ... done.
11650 11:47:51.549692 <5>[ 66.966727] random: crng reseeded on system resumption
11651 11:47:51.553138 <6>[ 66.973351] PM: suspend exit
11652 11:47:51.557175 rtcwake: write error
11653 11:47:51.565399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11654 11:47:51.566199 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11656 11:47:51.568751 rtcwake: assuming RTC uses UTC ...
11657 11:47:51.575177 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:47:58 2023
11658 11:47:51.588017 <6>[ 67.004499] PM: suspend entry (deep)
11659 11:47:51.591250 <6>[ 67.008393] Filesystems sync: 0.000 seconds
11660 11:47:51.594112 <6>[ 67.013431] Freezing user space processes
11661 11:47:51.605581 <6>[ 67.019080] Freezing user space processes completed (elapsed 0.001 seconds)
11662 11:47:51.608886 <6>[ 67.026297] OOM killer disabled.
11663 11:47:51.612461 <6>[ 67.029779] Freezing remaining freezable tasks
11664 11:47:51.634423 <6>[ 67.047237] usb 1-1.1.4: new full-speed USB device number 40 using xhci-mtk
11665 11:47:51.718501 <3>[ 67.135215] usb 1-1.1.4: device descriptor read/64, error -32
11666 11:47:51.910648 <3>[ 67.327451] usb 1-1.1.4: device descriptor read/64, error -32
11667 11:47:52.105590 <6>[ 67.519131] usb 1-1.1.4: new full-speed USB device number 41 using xhci-mtk
11668 11:47:52.189966 <3>[ 67.607306] usb 1-1.1.4: device descriptor read/64, error -32
11669 11:47:52.382851 <3>[ 67.799438] usb 1-1.1.4: device descriptor read/64, error -32
11670 11:47:52.494685 <6>[ 67.911798] usb 1-1.1-port4: attempt power cycle
11671 11:47:53.105571 <6>[ 68.519252] usb 1-1.1.4: new full-speed USB device number 42 using xhci-mtk
11672 11:47:53.112345 <4>[ 68.526644] usb 1-1.1.4: Device not responding to setup address.
11673 11:47:53.322723 <4>[ 68.739482] usb 1-1.1.4: Device not responding to setup address.
11674 11:47:53.533783 <3>[ 68.951129] usb 1-1.1.4: device not accepting address 42, error -71
11675 11:47:53.622135 <6>[ 69.035118] usb 1-1.1.4: new full-speed USB device number 43 using xhci-mtk
11676 11:47:53.628237 <4>[ 69.042508] usb 1-1.1.4: Device not responding to setup address.
11677 11:47:53.838554 <4>[ 69.255333] usb 1-1.1.4: Device not responding to setup address.
11678 11:47:54.050245 <3>[ 69.467112] usb 1-1.1.4: device not accepting address 43, error -71
11679 11:47:54.057022 <3>[ 69.474133] usb 1-1.1-port4: unable to enumerate USB device
11680 11:47:54.074868 <6>[ 69.488466] Freezing remaining freezable tasks completed (elapsed 2.453 seconds)
11681 11:47:54.081636 <6>[ 69.496168] printk: Suspending console(s) (use no_console_suspend to debug)
11682 11:47:57.384166 <3>[ 72.527306] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11683 11:47:57.397022 <3>[ 72.527351] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11684 11:47:57.403624 <3>[ 72.527410] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11685 11:47:57.410122 <3>[ 72.527457] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11686 11:47:57.419897 <3>[ 72.527699] PM: Some devices failed to suspend, or early wake event detected
11687 11:47:57.423309 <6>[ 72.841705] OOM killer enabled.
11688 11:47:57.430216 <6>[ 72.845119] Restarting tasks ... done.
11689 11:47:57.433375 <5>[ 72.851359] random: crng reseeded on system resumption
11690 11:47:57.436821 <6>[ 72.858103] PM: suspend exit
11691 11:47:57.439913 rtcwake: write error
11692 11:47:57.447361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11693 11:47:57.447624 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11695 11:47:57.450857 rtcwake: assuming RTC uses UTC ...
11696 11:47:57.457525 rtcwake: wakeup from "mem" using rtc0 at Fri Nov 24 11:48:04 2023
11697 11:47:57.470352 <6>[ 72.888379] PM: suspend entry (deep)
11698 11:47:57.473892 <6>[ 72.892272] Filesystems sync: 0.000 seconds
11699 11:47:57.477480 <6>[ 72.897279] Freezing user space processes
11700 11:47:57.488372 <6>[ 72.903219] Freezing user space processes completed (elapsed 0.001 seconds)
11701 11:47:57.492607 <6>[ 72.910450] OOM killer disabled.
11702 11:47:57.495348 <6>[ 72.913931] Freezing remaining freezable tasks
11703 11:47:57.516122 <6>[ 72.931105] usb 1-1.1.4: new full-speed USB device number 44 using xhci-mtk
11704 11:47:57.601225 <3>[ 73.019130] usb 1-1.1.4: device descriptor read/64, error -32
11705 11:47:57.793317 <3>[ 73.211460] usb 1-1.1.4: device descriptor read/64, error -32
11706 11:47:57.988926 <6>[ 73.403124] usb 1-1.1.4: new full-speed USB device number 45 using xhci-mtk
11707 11:47:58.073568 <3>[ 73.491490] usb 1-1.1.4: device descriptor read/64, error -32
11708 11:47:58.265361 <3>[ 73.683463] usb 1-1.1.4: device descriptor read/64, error -32
11709 11:47:58.377569 <6>[ 73.795643] usb 1-1.1-port4: attempt power cycle
11710 11:47:58.988140 <6>[ 74.403117] usb 1-1.1.4: new full-speed USB device number 46 using xhci-mtk
11711 11:47:58.995601 <4>[ 74.410509] usb 1-1.1.4: Device not responding to setup address.
11712 11:47:59.206167 <4>[ 74.623873] usb 1-1.1.4: Device not responding to setup address.
11713 11:47:59.417232 <3>[ 74.835243] usb 1-1.1.4: device not accepting address 46, error -71
11714 11:47:59.504184 <6>[ 74.919250] usb 1-1.1.4: new full-speed USB device number 47 using xhci-mtk
11715 11:47:59.510860 <4>[ 74.926644] usb 1-1.1.4: Device not responding to setup address.
11716 11:47:59.721312 <4>[ 75.139332] usb 1-1.1.4: Device not responding to setup address.
11717 11:47:59.932787 <3>[ 75.351180] usb 1-1.1.4: device not accepting address 47, error -71
11718 11:47:59.939601 <3>[ 75.358154] usb 1-1.1-port4: unable to enumerate USB device
11719 11:47:59.952660 <6>[ 75.367794] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11720 11:47:59.959528 <6>[ 75.375499] printk: Suspending console(s) (use no_console_suspend to debug)
11721 11:48:03.270833 <3>[ 78.415261] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11722 11:48:03.284156 <3>[ 78.415295] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11723 11:48:03.291354 <3>[ 78.415345] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11724 11:48:03.298110 <3>[ 78.415392] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11725 11:48:03.307309 <3>[ 78.415749] PM: Some devices failed to suspend, or early wake event detected
11726 11:48:03.310587 <6>[ 78.729650] OOM killer enabled.
11727 11:48:03.321174 <6>[ 78.733056] Restarting tasks ... done.
11728 11:48:03.323729 <5>[ 78.743483] random: crng reseeded on system resumption
11729 11:48:03.328088 <6>[ 78.750221] PM: suspend exit
11730 11:48:03.331387 rtcwake: write error
11731 11:48:03.339169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11732 11:48:03.339436 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11734 11:48:03.342440 rtcwake: assuming RTC uses UTC ...
11735 11:48:03.348691 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:10 2023
11736 11:48:03.363317 <6>[ 78.781821] PM: suspend entry (s2idle)
11737 11:48:03.367436 <6>[ 78.785908] Filesystems sync: 0.000 seconds
11738 11:48:03.373093 <6>[ 78.790977] Freezing user space processes
11739 11:48:03.379732 <6>[ 78.796878] Freezing user space processes completed (elapsed 0.001 seconds)
11740 11:48:03.382878 <6>[ 78.804113] OOM killer disabled.
11741 11:48:03.389448 <6>[ 78.807593] Freezing remaining freezable tasks
11742 11:48:03.403586 <6>[ 78.819081] usb 1-1.1.4: new full-speed USB device number 48 using xhci-mtk
11743 11:48:03.488665 <3>[ 78.907208] usb 1-1.1.4: device descriptor read/64, error -32
11744 11:48:03.681056 <3>[ 79.099798] usb 1-1.1.4: device descriptor read/64, error -32
11745 11:48:03.876359 <6>[ 79.291310] usb 1-1.1.4: new full-speed USB device number 49 using xhci-mtk
11746 11:48:03.960438 <3>[ 79.379386] usb 1-1.1.4: device descriptor read/64, error -32
11747 11:48:04.153125 <3>[ 79.571805] usb 1-1.1.4: device descriptor read/64, error -32
11748 11:48:04.264685 <6>[ 79.683554] usb 1-1.1-port4: attempt power cycle
11749 11:48:04.875799 <6>[ 80.291285] usb 1-1.1.4: new full-speed USB device number 50 using xhci-mtk
11750 11:48:04.882450 <4>[ 80.298951] usb 1-1.1.4: Device not responding to setup address.
11751 11:48:05.092868 <4>[ 80.511826] usb 1-1.1.4: Device not responding to setup address.
11752 11:48:05.304602 <3>[ 80.723588] usb 1-1.1.4: device not accepting address 50, error -71
11753 11:48:05.391744 <6>[ 80.807399] usb 1-1.1.4: new full-speed USB device number 51 using xhci-mtk
11754 11:48:05.398700 <4>[ 80.814841] usb 1-1.1.4: Device not responding to setup address.
11755 11:48:05.608136 <4>[ 81.027332] usb 1-1.1.4: Device not responding to setup address.
11756 11:48:05.819887 <3>[ 81.239090] usb 1-1.1.4: device not accepting address 51, error -71
11757 11:48:05.827637 <3>[ 81.246294] usb 1-1.1-port4: unable to enumerate USB device
11758 11:48:05.843628 <6>[ 81.259235] Freezing remaining freezable tasks completed (elapsed 2.446 seconds)
11759 11:48:05.850219 <6>[ 81.266947] printk: Suspending console(s) (use no_console_suspend to debug)
11760 11:48:09.154278 <3>[ 84.303261] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11761 11:48:09.164843 <3>[ 84.303296] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11762 11:48:09.174055 <3>[ 84.303346] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11763 11:48:09.180635 <3>[ 84.303397] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11764 11:48:09.190763 <3>[ 84.303680] PM: Some devices failed to suspend, or early wake event detected
11765 11:48:09.194129 <6>[ 84.613645] OOM killer enabled.
11766 11:48:09.197221 <6>[ 84.617060] Restarting tasks ... done.
11767 11:48:09.205543 <5>[ 84.624918] random: crng reseeded on system resumption
11768 11:48:09.209156 <6>[ 84.631268] PM: suspend exit
11769 11:48:09.212269 rtcwake: write error
11770 11:48:09.220000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11771 11:48:09.220290 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11773 11:48:09.222742 rtcwake: assuming RTC uses UTC ...
11774 11:48:09.229755 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:15 2023
11775 11:48:09.242167 <6>[ 84.661572] PM: suspend entry (s2idle)
11776 11:48:09.245278 <6>[ 84.665700] Filesystems sync: 0.000 seconds
11777 11:48:09.252067 <6>[ 84.670724] Freezing user space processes
11778 11:48:09.258940 <6>[ 84.676792] Freezing user space processes completed (elapsed 0.001 seconds)
11779 11:48:09.262180 <6>[ 84.684032] OOM killer disabled.
11780 11:48:09.268584 <6>[ 84.687519] Freezing remaining freezable tasks
11781 11:48:09.282760 <6>[ 84.699135] usb 1-1.1.4: new full-speed USB device number 52 using xhci-mtk
11782 11:48:09.367669 <3>[ 84.787181] usb 1-1.1.4: device descriptor read/64, error -32
11783 11:48:09.559973 <3>[ 84.979247] usb 1-1.1.4: device descriptor read/64, error -32
11784 11:48:09.755124 <6>[ 85.171021] usb 1-1.1.4: new full-speed USB device number 53 using xhci-mtk
11785 11:48:09.839895 <3>[ 85.259385] usb 1-1.1.4: device descriptor read/64, error -32
11786 11:48:10.032021 <3>[ 85.451659] usb 1-1.1.4: device descriptor read/64, error -32
11787 11:48:10.143877 <6>[ 85.563547] usb 1-1.1-port4: attempt power cycle
11788 11:48:10.755467 <6>[ 86.171081] usb 1-1.1.4: new full-speed USB device number 54 using xhci-mtk
11789 11:48:10.761286 <4>[ 86.178521] usb 1-1.1.4: Device not responding to setup address.
11790 11:48:10.972332 <4>[ 86.391826] usb 1-1.1.4: Device not responding to setup address.
11791 11:48:11.183175 <3>[ 86.603023] usb 1-1.1.4: device not accepting address 54, error -71
11792 11:48:11.271142 <6>[ 86.687201] usb 1-1.1.4: new full-speed USB device number 55 using xhci-mtk
11793 11:48:11.277237 <4>[ 86.694586] usb 1-1.1.4: Device not responding to setup address.
11794 11:48:11.487976 <4>[ 86.907337] usb 1-1.1.4: Device not responding to setup address.
11795 11:48:11.699763 <3>[ 87.119087] usb 1-1.1.4: device not accepting address 55, error -71
11796 11:48:11.707397 <3>[ 87.126267] usb 1-1.1-port4: unable to enumerate USB device
11797 11:48:11.723433 <6>[ 87.139234] Freezing remaining freezable tasks completed (elapsed 2.447 seconds)
11798 11:48:11.730177 <6>[ 87.146946] printk: Suspending console(s) (use no_console_suspend to debug)
11799 11:48:15.041829 <3>[ 90.191261] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11800 11:48:15.051481 <3>[ 90.191295] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11801 11:48:15.061777 <3>[ 90.191345] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11802 11:48:15.068067 <3>[ 90.191391] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11803 11:48:15.078135 <3>[ 90.191734] PM: Some devices failed to suspend, or early wake event detected
11804 11:48:15.081435 <6>[ 90.501479] OOM killer enabled.
11805 11:48:15.084817 <6>[ 90.504892] Restarting tasks ... done.
11806 11:48:15.093342 <5>[ 90.512881] random: crng reseeded on system resumption
11807 11:48:15.096606 <6>[ 90.519139] PM: suspend exit
11808 11:48:15.099298 rtcwake: write error
11809 11:48:15.107399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11810 11:48:15.107654 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11812 11:48:15.110717 rtcwake: assuming RTC uses UTC ...
11813 11:48:15.117342 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:21 2023
11814 11:48:15.130076 <6>[ 90.549948] PM: suspend entry (s2idle)
11815 11:48:15.133197 <6>[ 90.554034] Filesystems sync: 0.000 seconds
11816 11:48:15.139623 <6>[ 90.559120] Freezing user space processes
11817 11:48:15.146698 <6>[ 90.565051] Freezing user space processes completed (elapsed 0.001 seconds)
11818 11:48:15.149612 <6>[ 90.572291] OOM killer disabled.
11819 11:48:15.156659 <6>[ 90.575772] Freezing remaining freezable tasks
11820 11:48:15.170176 <6>[ 90.587130] usb 1-1.1.4: new full-speed USB device number 56 using xhci-mtk
11821 11:48:15.255384 <3>[ 90.675163] usb 1-1.1.4: device descriptor read/64, error -32
11822 11:48:15.447982 <3>[ 90.867514] usb 1-1.1.4: device descriptor read/64, error -32
11823 11:48:15.642574 <6>[ 91.059247] usb 1-1.1.4: new full-speed USB device number 57 using xhci-mtk
11824 11:48:15.727551 <3>[ 91.147386] usb 1-1.1.4: device descriptor read/64, error -32
11825 11:48:15.919941 <3>[ 91.339826] usb 1-1.1.4: device descriptor read/64, error -32
11826 11:48:16.031723 <6>[ 91.451555] usb 1-1.1-port4: attempt power cycle
11827 11:48:16.642275 <6>[ 92.059285] usb 1-1.1.4: new full-speed USB device number 58 using xhci-mtk
11828 11:48:16.648961 <4>[ 92.066951] usb 1-1.1.4: Device not responding to setup address.
11829 11:48:16.860114 <4>[ 92.279820] usb 1-1.1.4: Device not responding to setup address.
11830 11:48:17.072270 <3>[ 92.491603] usb 1-1.1.4: device not accepting address 58, error -71
11831 11:48:17.159017 <6>[ 92.575397] usb 1-1.1.4: new full-speed USB device number 59 using xhci-mtk
11832 11:48:17.165351 <4>[ 92.582837] usb 1-1.1.4: Device not responding to setup address.
11833 11:48:17.375259 <4>[ 92.795335] usb 1-1.1.4: Device not responding to setup address.
11834 11:48:17.587512 <3>[ 93.007096] usb 1-1.1.4: device not accepting address 59, error -71
11835 11:48:17.594126 <3>[ 93.014302] usb 1-1.1-port4: unable to enumerate USB device
11836 11:48:17.610089 <6>[ 93.027234] Freezing remaining freezable tasks completed (elapsed 2.446 seconds)
11837 11:48:17.616680 <6>[ 93.034945] printk: Suspending console(s) (use no_console_suspend to debug)
11838 11:48:20.929019 <3>[ 96.079260] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11839 11:48:20.938892 <3>[ 96.079294] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11840 11:48:20.948681 <3>[ 96.079344] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11841 11:48:20.955372 <3>[ 96.079391] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11842 11:48:20.966187 <3>[ 96.079677] PM: Some devices failed to suspend, or early wake event detected
11843 11:48:20.968684 <6>[ 96.389377] OOM killer enabled.
11844 11:48:20.972610 <6>[ 96.392792] Restarting tasks ... done.
11845 11:48:20.978675 <5>[ 96.398881] random: crng reseeded on system resumption
11846 11:48:20.982150 <6>[ 96.405156] PM: suspend exit
11847 11:48:20.985144 rtcwake: write error
11848 11:48:20.993526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11849 11:48:20.994296 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11851 11:48:20.995717 rtcwake: assuming RTC uses UTC ...
11852 11:48:21.002879 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:27 2023
11853 11:48:21.015965 <6>[ 96.435880] PM: suspend entry (s2idle)
11854 11:48:21.018787 <6>[ 96.439953] Filesystems sync: 0.000 seconds
11855 11:48:21.025498 <6>[ 96.445008] Freezing user space processes
11856 11:48:21.032029 <6>[ 96.450898] Freezing user space processes completed (elapsed 0.001 seconds)
11857 11:48:21.035511 <6>[ 96.458134] OOM killer disabled.
11858 11:48:21.041813 <6>[ 96.461614] Freezing remaining freezable tasks
11859 11:48:21.058165 <6>[ 96.475126] usb 1-1.1.4: new full-speed USB device number 60 using xhci-mtk
11860 11:48:21.142841 <3>[ 96.563342] usb 1-1.1.4: device descriptor read/64, error -32
11861 11:48:21.334839 <3>[ 96.755306] usb 1-1.1.4: device descriptor read/64, error -32
11862 11:48:21.529884 <6>[ 96.947261] usb 1-1.1.4: new full-speed USB device number 61 using xhci-mtk
11863 11:48:21.614346 <3>[ 97.035289] usb 1-1.1.4: device descriptor read/64, error -32
11864 11:48:21.806938 <3>[ 97.227446] usb 1-1.1.4: device descriptor read/64, error -32
11865 11:48:21.919088 <6>[ 97.339787] usb 1-1.1-port4: attempt power cycle
11866 11:48:22.530696 <6>[ 97.947252] usb 1-1.1.4: new full-speed USB device number 62 using xhci-mtk
11867 11:48:22.536180 <4>[ 97.954645] usb 1-1.1.4: Device not responding to setup address.
11868 11:48:22.746987 <4>[ 98.167486] usb 1-1.1.4: Device not responding to setup address.
11869 11:48:22.958273 <3>[ 98.379130] usb 1-1.1.4: device not accepting address 62, error -71
11870 11:48:23.045801 <6>[ 98.463116] usb 1-1.1.4: new full-speed USB device number 63 using xhci-mtk
11871 11:48:23.052380 <4>[ 98.470505] usb 1-1.1.4: Device not responding to setup address.
11872 11:48:23.262408 <4>[ 98.683342] usb 1-1.1.4: Device not responding to setup address.
11873 11:48:23.474572 <3>[ 98.895240] usb 1-1.1.4: device not accepting address 63, error -71
11874 11:48:23.481870 <3>[ 98.902287] usb 1-1.1-port4: unable to enumerate USB device
11875 11:48:23.499520 <6>[ 98.916620] Freezing remaining freezable tasks completed (elapsed 2.450 seconds)
11876 11:48:23.505912 <6>[ 98.924331] printk: Suspending console(s) (use no_console_suspend to debug)
11877 11:48:26.820474 <3>[ 101.967260] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11878 11:48:26.830369 <3>[ 101.967294] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11879 11:48:26.839992 <3>[ 101.967345] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11880 11:48:26.846894 <3>[ 101.967394] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11881 11:48:26.857215 <3>[ 101.967690] PM: Some devices failed to suspend, or early wake event detected
11882 11:48:26.859969 <6>[ 102.281487] OOM killer enabled.
11883 11:48:26.867578 <6>[ 102.284911] Restarting tasks ... done.
11884 11:48:26.870165 <5>[ 102.292568] random: crng reseeded on system resumption
11885 11:48:26.875436 <6>[ 102.299671] PM: suspend exit
11886 11:48:26.878891 rtcwake: write error
11887 11:48:26.887030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11888 11:48:26.887646 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11890 11:48:26.890386 rtcwake: assuming RTC uses UTC ...
11891 11:48:26.897304 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:33 2023
11892 11:48:26.909468 <6>[ 102.330792] PM: suspend entry (s2idle)
11893 11:48:26.912720 <6>[ 102.334870] Filesystems sync: 0.000 seconds
11894 11:48:26.919703 <6>[ 102.339916] Freezing user space processes
11895 11:48:26.926335 <6>[ 102.345835] Freezing user space processes completed (elapsed 0.001 seconds)
11896 11:48:26.929788 <6>[ 102.353067] OOM killer disabled.
11897 11:48:26.936308 <6>[ 102.356547] Freezing remaining freezable tasks
11898 11:48:26.943334 <6>[ 102.363157] usb 1-1.1.4: new full-speed USB device number 64 using xhci-mtk
11899 11:48:27.029987 <3>[ 102.451161] usb 1-1.1.4: device descriptor read/64, error -32
11900 11:48:27.222680 <3>[ 102.643417] usb 1-1.1.4: device descriptor read/64, error -32
11901 11:48:27.417325 <6>[ 102.835106] usb 1-1.1.4: new full-speed USB device number 65 using xhci-mtk
11902 11:48:27.502637 <3>[ 102.923430] usb 1-1.1.4: device descriptor read/64, error -32
11903 11:48:27.693739 <3>[ 103.115263] usb 1-1.1.4: device descriptor read/64, error -32
11904 11:48:27.806381 <6>[ 103.227584] usb 1-1.1-port4: attempt power cycle
11905 11:48:28.417461 <6>[ 103.835249] usb 1-1.1.4: new full-speed USB device number 66 using xhci-mtk
11906 11:48:28.423752 <4>[ 103.842647] usb 1-1.1.4: Device not responding to setup address.
11907 11:48:28.633824 <4>[ 104.055335] usb 1-1.1.4: Device not responding to setup address.
11908 11:48:28.845695 <3>[ 104.267108] usb 1-1.1.4: device not accepting address 66, error -71
11909 11:48:28.933436 <6>[ 104.351123] usb 1-1.1.4: new full-speed USB device number 67 using xhci-mtk
11910 11:48:28.939345 <4>[ 104.358530] usb 1-1.1.4: Device not responding to setup address.
11911 11:48:29.150694 <4>[ 104.571479] usb 1-1.1.4: Device not responding to setup address.
11912 11:48:29.361898 <3>[ 104.783241] usb 1-1.1.4: device not accepting address 67, error -71
11913 11:48:29.368782 <3>[ 104.790288] usb 1-1.1-port4: unable to enumerate USB device
11914 11:48:29.386977 <6>[ 104.804617] Freezing remaining freezable tasks completed (elapsed 2.443 seconds)
11915 11:48:29.393587 <6>[ 104.812317] printk: Suspending console(s) (use no_console_suspend to debug)
11916 11:48:32.704475 <3>[ 107.855262] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11917 11:48:32.714228 <3>[ 107.855296] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11918 11:48:32.723664 <3>[ 107.855346] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11919 11:48:32.730664 <3>[ 107.855393] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11920 11:48:32.737111 <3>[ 107.855753] PM: Some devices failed to suspend, or early wake event detected
11921 11:48:32.743729 <6>[ 108.165401] OOM killer enabled.
11922 11:48:32.747512 <6>[ 108.168816] Restarting tasks ... done.
11923 11:48:32.753584 <5>[ 108.174948] random: crng reseeded on system resumption
11924 11:48:32.757324 <6>[ 108.181401] PM: suspend exit
11925 11:48:32.760385 rtcwake: write error
11926 11:48:32.767257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11927 11:48:32.768062 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11929 11:48:32.770916 rtcwake: assuming RTC uses UTC ...
11930 11:48:32.777063 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:39 2023
11931 11:48:32.789625 <6>[ 108.211309] PM: suspend entry (s2idle)
11932 11:48:32.793018 <6>[ 108.215397] Filesystems sync: 0.000 seconds
11933 11:48:32.799997 <6>[ 108.220451] Freezing user space processes
11934 11:48:32.806082 <6>[ 108.226391] Freezing user space processes completed (elapsed 0.001 seconds)
11935 11:48:32.809748 <6>[ 108.233622] OOM killer disabled.
11936 11:48:32.816009 <6>[ 108.237104] Freezing remaining freezable tasks
11937 11:48:32.840823 <6>[ 108.259172] usb 1-1.1.4: new full-speed USB device number 68 using xhci-mtk
11938 11:48:32.925468 <3>[ 108.347364] usb 1-1.1.4: device descriptor read/64, error -32
11939 11:48:33.117469 <3>[ 108.539302] usb 1-1.1.4: device descriptor read/64, error -32
11940 11:48:33.312826 <6>[ 108.731252] usb 1-1.1.4: new full-speed USB device number 69 using xhci-mtk
11941 11:48:33.397654 <3>[ 108.819397] usb 1-1.1.4: device descriptor read/64, error -32
11942 11:48:33.589143 <3>[ 109.011299] usb 1-1.1.4: device descriptor read/64, error -32
11943 11:48:33.701688 <6>[ 109.123864] usb 1-1.1-port4: attempt power cycle
11944 11:48:34.312846 <6>[ 109.731101] usb 1-1.1.4: new full-speed USB device number 70 using xhci-mtk
11945 11:48:34.318538 <4>[ 109.738497] usb 1-1.1.4: Device not responding to setup address.
11946 11:48:34.529183 <4>[ 109.951335] usb 1-1.1.4: Device not responding to setup address.
11947 11:48:34.741423 <3>[ 110.163106] usb 1-1.1.4: device not accepting address 70, error -71
11948 11:48:34.827975 <6>[ 110.247123] usb 1-1.1.4: new full-speed USB device number 71 using xhci-mtk
11949 11:48:34.834526 <4>[ 110.254524] usb 1-1.1.4: Device not responding to setup address.
11950 11:48:35.044957 <4>[ 110.467480] usb 1-1.1.4: Device not responding to setup address.
11951 11:48:35.256981 <3>[ 110.679243] usb 1-1.1.4: device not accepting address 71, error -71
11952 11:48:35.264138 <3>[ 110.686285] usb 1-1.1-port4: unable to enumerate USB device
11953 11:48:35.281774 <6>[ 110.700617] Freezing remaining freezable tasks completed (elapsed 2.458 seconds)
11954 11:48:35.288020 <6>[ 110.708337] printk: Suspending console(s) (use no_console_suspend to debug)
11955 11:48:38.595187 <3>[ 113.743260] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11956 11:48:38.604722 <3>[ 113.743294] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11957 11:48:38.614763 <3>[ 113.743345] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11958 11:48:38.621226 <3>[ 113.743391] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11959 11:48:38.631366 <3>[ 113.743721] PM: Some devices failed to suspend, or early wake event detected
11960 11:48:38.634839 <6>[ 114.057509] OOM killer enabled.
11961 11:48:38.637762 <6>[ 114.060923] Restarting tasks ... done.
11962 11:48:38.644793 <5>[ 114.067145] random: crng reseeded on system resumption
11963 11:48:38.647786 <6>[ 114.073979] PM: suspend exit
11964 11:48:38.651177 rtcwake: write error
11965 11:48:38.659112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11966 11:48:38.659375 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11968 11:48:38.662576 rtcwake: assuming RTC uses UTC ...
11969 11:48:38.669017 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:45 2023
11970 11:48:38.682220 <6>[ 114.104573] PM: suspend entry (s2idle)
11971 11:48:38.685772 <6>[ 114.108655] Filesystems sync: 0.000 seconds
11972 11:48:38.692083 <6>[ 114.113690] Freezing user space processes
11973 11:48:38.699111 <6>[ 114.119545] Freezing user space processes completed (elapsed 0.001 seconds)
11974 11:48:38.701843 <6>[ 114.126764] OOM killer disabled.
11975 11:48:38.708100 <6>[ 114.130243] Freezing remaining freezable tasks
11976 11:48:38.731703 <6>[ 114.151088] usb 1-1.1.4: new full-speed USB device number 72 using xhci-mtk
11977 11:48:38.817308 <3>[ 114.239352] usb 1-1.1.4: device descriptor read/64, error -32
11978 11:48:39.009004 <3>[ 114.431310] usb 1-1.1.4: device descriptor read/64, error -32
11979 11:48:39.204477 <6>[ 114.623257] usb 1-1.1.4: new full-speed USB device number 73 using xhci-mtk
11980 11:48:39.288670 <3>[ 114.711257] usb 1-1.1.4: device descriptor read/64, error -32
11981 11:48:39.481162 <3>[ 114.903444] usb 1-1.1.4: device descriptor read/64, error -32
11982 11:48:39.593511 <6>[ 115.015788] usb 1-1.1-port4: attempt power cycle
11983 11:48:40.204166 <6>[ 115.623250] usb 1-1.1.4: new full-speed USB device number 74 using xhci-mtk
11984 11:48:40.210613 <4>[ 115.630642] usb 1-1.1.4: Device not responding to setup address.
11985 11:48:40.420946 <4>[ 115.843412] usb 1-1.1.4: Device not responding to setup address.
11986 11:48:40.633000 <3>[ 116.055504] usb 1-1.1.4: device not accepting address 74, error -71
11987 11:48:40.719891 <6>[ 116.139116] usb 1-1.1.4: new full-speed USB device number 75 using xhci-mtk
11988 11:48:40.726633 <4>[ 116.146520] usb 1-1.1.4: Device not responding to setup address.
11989 11:48:40.936987 <4>[ 116.359497] usb 1-1.1.4: Device not responding to setup address.
11990 11:48:41.148801 <3>[ 116.571248] usb 1-1.1.4: device not accepting address 75, error -71
11991 11:48:41.155918 <3>[ 116.578284] usb 1-1.1-port4: unable to enumerate USB device
11992 11:48:41.165167 <6>[ 116.584410] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11993 11:48:41.172077 <6>[ 116.592114] printk: Suspending console(s) (use no_console_suspend to debug)
11994 11:48:44.482473 <3>[ 119.631277] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11995 11:48:44.492893 <3>[ 119.631313] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11996 11:48:44.503354 <3>[ 119.631362] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11997 11:48:44.509225 <3>[ 119.631410] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11998 11:48:44.515508 <3>[ 119.631759] PM: Some devices failed to suspend, or early wake event detected
11999 11:48:44.523749 <6>[ 119.945380] OOM killer enabled.
12000 11:48:44.525957 <6>[ 119.948797] Restarting tasks ... done.
12001 11:48:44.532186 <5>[ 119.954863] random: crng reseeded on system resumption
12002 11:48:44.535804 <6>[ 119.961297] PM: suspend exit
12003 11:48:44.538814 rtcwake: write error
12004 11:48:44.546746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
12005 11:48:44.547481 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
12007 11:48:44.549948 rtcwake: assuming RTC uses UTC ...
12008 11:48:44.556363 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:51 2023
12009 11:48:44.569243 <6>[ 119.991601] PM: suspend entry (s2idle)
12010 11:48:44.571780 <6>[ 119.995689] Filesystems sync: 0.000 seconds
12011 11:48:44.578626 <6>[ 120.000730] Freezing user space processes
12012 11:48:44.585607 <6>[ 120.006702] Freezing user space processes completed (elapsed 0.001 seconds)
12013 11:48:44.588576 <6>[ 120.013936] OOM killer disabled.
12014 11:48:44.595187 <6>[ 120.017417] Freezing remaining freezable tasks
12015 11:48:44.611358 <6>[ 120.031042] usb 1-1.1.4: new full-speed USB device number 76 using xhci-mtk
12016 11:48:44.696721 <3>[ 120.119586] usb 1-1.1.4: device descriptor read/64, error -32
12017 11:48:44.889161 <3>[ 120.311462] usb 1-1.1.4: device descriptor read/64, error -32
12018 11:48:45.083512 <6>[ 120.503098] usb 1-1.1.4: new full-speed USB device number 77 using xhci-mtk
12019 11:48:45.168461 <3>[ 120.591385] usb 1-1.1.4: device descriptor read/64, error -32
12020 11:48:45.360337 <3>[ 120.783527] usb 1-1.1.4: device descriptor read/64, error -32
12021 11:48:45.472667 <6>[ 120.895638] usb 1-1.1-port4: attempt power cycle
12022 11:48:46.083743 <6>[ 121.503097] usb 1-1.1.4: new full-speed USB device number 78 using xhci-mtk
12023 11:48:46.090231 <4>[ 121.510735] usb 1-1.1.4: Device not responding to setup address.
12024 11:48:46.300544 <4>[ 121.723334] usb 1-1.1.4: Device not responding to setup address.
12025 11:48:46.511692 <3>[ 121.935097] usb 1-1.1.4: device not accepting address 78, error -71
12026 11:48:46.599114 <6>[ 122.019202] usb 1-1.1.4: new full-speed USB device number 79 using xhci-mtk
12027 11:48:46.605975 <4>[ 122.026711] usb 1-1.1.4: Device not responding to setup address.
12028 11:48:46.816433 <4>[ 122.239304] usb 1-1.1.4: Device not responding to setup address.
12029 11:48:47.028620 <3>[ 122.451192] usb 1-1.1.4: device not accepting address 79, error -71
12030 11:48:47.035661 <3>[ 122.458217] usb 1-1.1-port4: unable to enumerate USB device
12031 11:48:47.051530 <6>[ 122.471234] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
12032 11:48:47.057862 <6>[ 122.478946] printk: Suspending console(s) (use no_console_suspend to debug)
12033 11:48:50.365623 <3>[ 125.519367] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
12034 11:48:50.375828 <3>[ 125.519405] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12035 11:48:50.385311 <3>[ 125.519462] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12036 11:48:50.392509 <3>[ 125.519509] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12037 11:48:50.402897 <3>[ 125.519782] PM: Some devices failed to suspend, or early wake event detected
12038 11:48:50.405324 <6>[ 125.829238] OOM killer enabled.
12039 11:48:50.408945 <6>[ 125.832652] Restarting tasks ... done.
12040 11:48:50.415313 <5>[ 125.838798] random: crng reseeded on system resumption
12041 11:48:50.419090 <6>[ 125.845738] PM: suspend exit
12042 11:48:50.422482 rtcwake: write error
12043 11:48:50.429916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
12044 11:48:50.430629 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
12046 11:48:50.433303 rtcwake: assuming RTC uses UTC ...
12047 11:48:50.440140 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:48:57 2023
12048 11:48:50.452670 <6>[ 125.876388] PM: suspend entry (s2idle)
12049 11:48:50.456422 <6>[ 125.880453] Filesystems sync: 0.000 seconds
12050 11:48:50.462513 <6>[ 125.885522] Freezing user space processes
12051 11:48:50.469628 <6>[ 125.891059] Freezing user space processes completed (elapsed 0.001 seconds)
12052 11:48:50.472531 <6>[ 125.898279] OOM killer disabled.
12053 11:48:50.479447 <6>[ 125.901759] Freezing remaining freezable tasks
12054 11:48:50.495108 <6>[ 125.915172] usb 1-1.1.4: new full-speed USB device number 80 using xhci-mtk
12055 11:48:50.579559 <3>[ 126.003331] usb 1-1.1.4: device descriptor read/64, error -32
12056 11:48:50.772013 <3>[ 126.195276] usb 1-1.1.4: device descriptor read/64, error -32
12057 11:48:50.966935 <6>[ 126.387137] usb 1-1.1.4: new full-speed USB device number 81 using xhci-mtk
12058 11:48:51.051709 <3>[ 126.475307] usb 1-1.1.4: device descriptor read/64, error -32
12059 11:48:51.243692 <3>[ 126.667442] usb 1-1.1.4: device descriptor read/64, error -32
12060 11:48:51.356145 <6>[ 126.779797] usb 1-1.1-port4: attempt power cycle
12061 11:48:51.966524 <6>[ 127.387251] usb 1-1.1.4: new full-speed USB device number 82 using xhci-mtk
12062 11:48:51.973514 <4>[ 127.394645] usb 1-1.1.4: Device not responding to setup address.
12063 11:48:52.183371 <4>[ 127.607478] usb 1-1.1.4: Device not responding to setup address.
12064 11:48:52.395739 <3>[ 127.819268] usb 1-1.1.4: device not accepting address 82, error -71
12065 11:48:52.482386 <6>[ 127.903101] usb 1-1.1.4: new full-speed USB device number 83 using xhci-mtk
12066 11:48:52.488719 <4>[ 127.910499] usb 1-1.1.4: Device not responding to setup address.
12067 11:48:52.699362 <4>[ 128.123365] usb 1-1.1.4: Device not responding to setup address.
12068 11:48:52.910921 <3>[ 128.335098] usb 1-1.1.4: device not accepting address 83, error -71
12069 11:48:52.918520 <3>[ 128.342161] usb 1-1.1-port4: unable to enumerate USB device
12070 11:48:52.930298 <6>[ 128.350955] Freezing remaining freezable tasks completed (elapsed 2.444 seconds)
12071 11:48:52.936673 <6>[ 128.358637] printk: Suspending console(s) (use no_console_suspend to debug)
12072 11:48:56.253248 <3>[ 131.407307] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
12073 11:48:56.263466 <3>[ 131.407344] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12074 11:48:56.273125 <3>[ 131.407408] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12075 11:48:56.279953 <3>[ 131.407453] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12076 11:48:56.286378 <3>[ 131.407601] PM: Some devices failed to suspend, or early wake event detected
12077 11:48:56.293006 <6>[ 131.717432] OOM killer enabled.
12078 11:48:56.302606 <6>[ 131.720835] Restarting tasks ... done.
12079 11:48:56.306010 <5>[ 131.731128] random: crng reseeded on system resumption
12080 11:48:56.309996 <6>[ 131.737744] PM: suspend exit
12081 11:48:56.313536 rtcwake: write error
12082 11:48:56.322033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
12083 11:48:56.322746 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
12085 11:48:56.324706 rtcwake: assuming RTC uses UTC ...
12086 11:48:56.331263 rtcwake: wakeup from "freeze" using rtc0 at Fri Nov 24 11:49:03 2023
12087 11:48:56.344325 <6>[ 131.768135] PM: suspend entry (s2idle)
12088 11:48:56.347781 <6>[ 131.772200] Filesystems sync: 0.000 seconds
12089 11:48:56.354099 <6>[ 131.777250] Freezing user space processes
12090 11:48:56.360795 <6>[ 131.783229] Freezing user space processes completed (elapsed 0.001 seconds)
12091 11:48:56.364243 <6>[ 131.790464] OOM killer disabled.
12092 11:48:56.370028 <6>[ 131.793945] Freezing remaining freezable tasks
12093 11:48:56.382175 <6>[ 131.803158] usb 1-1.1.4: new full-speed USB device number 84 using xhci-mtk
12094 11:48:56.467338 <3>[ 131.891133] usb 1-1.1.4: device descriptor read/64, error -32
12095 11:48:56.659077 <3>[ 132.083797] usb 1-1.1.4: device descriptor read/64, error -32
12096 11:48:56.854312 <6>[ 132.275318] usb 1-1.1.4: new full-speed USB device number 85 using xhci-mtk
12097 11:48:56.938496 <3>[ 132.363386] usb 1-1.1.4: device descriptor read/64, error -32
12098 11:48:57.130702 <3>[ 132.555794] usb 1-1.1.4: device descriptor read/64, error -32
12099 11:48:57.242785 <6>[ 132.667543] usb 1-1.1-port4: attempt power cycle
12100 11:48:57.854541 <6>[ 133.275285] usb 1-1.1.4: new full-speed USB device number 86 using xhci-mtk
12101 11:48:57.860479 <4>[ 133.282960] usb 1-1.1.4: Device not responding to setup address.
12102 11:48:58.072097 <4>[ 133.495838] usb 1-1.1.4: Device not responding to setup address.
12103 11:48:58.283333 <3>[ 133.707590] usb 1-1.1.4: device not accepting address 86, error -71
12104 11:48:58.370092 <6>[ 133.791415] usb 1-1.1.4: new full-speed USB device number 87 using xhci-mtk
12105 11:48:58.376969 <4>[ 133.798913] usb 1-1.1.4: Device not responding to setup address.
12106 11:48:58.587355 <4>[ 134.011864] usb 1-1.1.4: Device not responding to setup address.
12107 11:48:58.799073 <3>[ 134.223586] usb 1-1.1.4: device not accepting address 87, error -71
12108 11:48:58.805982 <3>[ 134.230569] usb 1-1.1-port4: unable to enumerate USB device
12109 11:48:58.821803 <6>[ 134.243234] Freezing remaining freezable tasks completed (elapsed 2.444 seconds)
12110 11:48:58.828754 <6>[ 134.250946] printk: Suspending console(s) (use no_console_suspend to debug)
12111 11:49:02.140309 <3>[ 137.295264] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
12112 11:49:02.153992 <3>[ 137.295300] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12113 11:49:02.161023 <3>[ 137.295349] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12114 11:49:02.167072 <3>[ 137.295395] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12115 11:49:02.176934 <3>[ 137.295724] PM: Some devices failed to suspend, or early wake event detected
12116 11:49:02.180162 <6>[ 137.605445] OOM killer enabled.
12117 11:49:02.195024 <6>[ 137.608866] Restarting tasks ... done.
12118 11:49:02.197810 <5>[ 137.623387] random: crng reseeded on system resumption
12119 11:49:02.203544 <6>[ 137.631760] PM: suspend exit
12120 11:49:02.207320 rtcwake: write error
12121 11:49:02.215261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
12122 11:49:02.216116 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
12124 11:49:02.218610 + set +x
12125 11:49:02.221505 <LAVA_SIGNAL_ENDRUN 0_sleep 12074004_1.5.2.3.1>
12126 11:49:02.221999 <LAVA_TEST_RUNNER EXIT>
12127 11:49:02.222700 Received signal: <ENDRUN> 0_sleep 12074004_1.5.2.3.1
12128 11:49:02.223135 Ending use of test pattern.
12129 11:49:02.223461 Ending test lava.0_sleep (12074004_1.5.2.3.1), duration 115.52
12131 11:49:02.224804 ok: lava_test_shell seems to have completed
12132 11:49:02.225936 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
12133 11:49:02.226425 end: 3.1 lava-test-shell (duration 00:01:56) [common]
12134 11:49:02.226861 end: 3 lava-test-retry (duration 00:01:56) [common]
12135 11:49:02.227305 start: 4 finalize (timeout 00:05:39) [common]
12136 11:49:02.227757 start: 4.1 power-off (timeout 00:00:30) [common]
12137 11:49:02.228509 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12138 11:49:02.351219 >> Command sent successfully.
12139 11:49:02.363186 Returned 0 in 0 seconds
12140 11:49:02.464449 end: 4.1 power-off (duration 00:00:00) [common]
12142 11:49:02.466122 start: 4.2 read-feedback (timeout 00:05:38) [common]
12143 11:49:02.467435 Listened to connection for namespace 'common' for up to 1s
12145 11:49:02.468879 Listened to connection for namespace 'common' for up to 1s
12146 11:49:03.468055 Finalising connection for namespace 'common'
12147 11:49:03.468737 Disconnecting from shell: Finalise
12148 11:49:03.569758 end: 4.2 read-feedback (duration 00:00:01) [common]
12149 11:49:03.570400 end: 4 finalize (duration 00:00:01) [common]
12150 11:49:03.570971 Cleaning after the job
12151 11:49:03.571542 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/ramdisk
12152 11:49:03.614509 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/kernel
12153 11:49:03.642593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/dtb
12154 11:49:03.642825 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074004/tftp-deploy-_a2jwg94/modules
12155 11:49:03.650334 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074004
12156 11:49:03.824050 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074004
12157 11:49:03.824230 Job finished correctly