Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 21
- Boot result: PASS
- Errors: 1
1 11:47:30.383468 lava-dispatcher, installed at version: 2023.10
2 11:47:30.383676 start: 0 validate
3 11:47:30.383814 Start time: 2023-11-24 11:47:30.383806+00:00 (UTC)
4 11:47:30.383930 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:47:30.384069 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:47:30.652716 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:47:30.652885 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:47:30.919572 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:47:30.919755 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:47:31.179672 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:47:31.179833 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:47:31.446829 validate duration: 1.06
14 11:47:31.447175 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:47:31.447305 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:47:31.447435 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:47:31.447590 Not decompressing ramdisk as can be used compressed.
18 11:47:31.447719 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 11:47:31.447813 saving as /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/ramdisk/rootfs.cpio.gz
20 11:47:31.447917 total size: 26246609 (25 MB)
21 11:47:31.449478 progress 0 % (0 MB)
22 11:47:31.457102 progress 5 % (1 MB)
23 11:47:31.464546 progress 10 % (2 MB)
24 11:47:31.471892 progress 15 % (3 MB)
25 11:47:31.478960 progress 20 % (5 MB)
26 11:47:31.485977 progress 25 % (6 MB)
27 11:47:31.492965 progress 30 % (7 MB)
28 11:47:31.500122 progress 35 % (8 MB)
29 11:47:31.507216 progress 40 % (10 MB)
30 11:47:31.514167 progress 45 % (11 MB)
31 11:47:31.521129 progress 50 % (12 MB)
32 11:47:31.528246 progress 55 % (13 MB)
33 11:47:31.535346 progress 60 % (15 MB)
34 11:47:31.542510 progress 65 % (16 MB)
35 11:47:31.549565 progress 70 % (17 MB)
36 11:47:31.556622 progress 75 % (18 MB)
37 11:47:31.563685 progress 80 % (20 MB)
38 11:47:31.570574 progress 85 % (21 MB)
39 11:47:31.577595 progress 90 % (22 MB)
40 11:47:31.584533 progress 95 % (23 MB)
41 11:47:31.591508 progress 100 % (25 MB)
42 11:47:31.591759 25 MB downloaded in 0.14 s (174.01 MB/s)
43 11:47:31.591918 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:47:31.592161 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:47:31.592246 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:47:31.592328 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:47:31.592467 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:47:31.592540 saving as /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/kernel/Image
50 11:47:31.592601 total size: 49107456 (46 MB)
51 11:47:31.592661 No compression specified
52 11:47:31.594220 progress 0 % (0 MB)
53 11:47:31.607491 progress 5 % (2 MB)
54 11:47:31.620772 progress 10 % (4 MB)
55 11:47:31.633974 progress 15 % (7 MB)
56 11:47:31.647327 progress 20 % (9 MB)
57 11:47:31.660527 progress 25 % (11 MB)
58 11:47:31.673700 progress 30 % (14 MB)
59 11:47:31.686896 progress 35 % (16 MB)
60 11:47:31.700476 progress 40 % (18 MB)
61 11:47:31.713757 progress 45 % (21 MB)
62 11:47:31.726948 progress 50 % (23 MB)
63 11:47:31.740422 progress 55 % (25 MB)
64 11:47:31.753681 progress 60 % (28 MB)
65 11:47:31.766840 progress 65 % (30 MB)
66 11:47:31.780069 progress 70 % (32 MB)
67 11:47:31.793168 progress 75 % (35 MB)
68 11:47:31.806804 progress 80 % (37 MB)
69 11:47:31.820312 progress 85 % (39 MB)
70 11:47:31.833551 progress 90 % (42 MB)
71 11:47:31.846536 progress 95 % (44 MB)
72 11:47:31.859417 progress 100 % (46 MB)
73 11:47:31.859627 46 MB downloaded in 0.27 s (175.39 MB/s)
74 11:47:31.859777 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:47:31.860019 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:47:31.860106 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:47:31.860197 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:47:31.860337 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:47:31.860405 saving as /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/dtb/mt8192-asurada-spherion-r0.dtb
81 11:47:31.860471 total size: 47278 (0 MB)
82 11:47:31.860534 No compression specified
83 11:47:31.861726 progress 69 % (0 MB)
84 11:47:31.862031 progress 100 % (0 MB)
85 11:47:31.862188 0 MB downloaded in 0.00 s (26.31 MB/s)
86 11:47:31.862312 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:47:31.862593 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:47:31.862707 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:47:31.862822 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:47:31.862965 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:47:31.863040 saving as /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/modules/modules.tar
93 11:47:31.863101 total size: 8624756 (8 MB)
94 11:47:31.863162 Using unxz to decompress xz
95 11:47:31.867931 progress 0 % (0 MB)
96 11:47:31.888917 progress 5 % (0 MB)
97 11:47:31.912463 progress 10 % (0 MB)
98 11:47:31.936171 progress 15 % (1 MB)
99 11:47:31.959643 progress 20 % (1 MB)
100 11:47:31.983462 progress 25 % (2 MB)
101 11:47:32.009002 progress 30 % (2 MB)
102 11:47:32.035297 progress 35 % (2 MB)
103 11:47:32.058648 progress 40 % (3 MB)
104 11:47:32.082996 progress 45 % (3 MB)
105 11:47:32.108051 progress 50 % (4 MB)
106 11:47:32.132217 progress 55 % (4 MB)
107 11:47:32.156928 progress 60 % (4 MB)
108 11:47:32.184501 progress 65 % (5 MB)
109 11:47:32.209440 progress 70 % (5 MB)
110 11:47:32.232781 progress 75 % (6 MB)
111 11:47:32.260441 progress 80 % (6 MB)
112 11:47:32.286576 progress 85 % (7 MB)
113 11:47:32.311656 progress 90 % (7 MB)
114 11:47:32.343480 progress 95 % (7 MB)
115 11:47:32.371464 progress 100 % (8 MB)
116 11:47:32.376366 8 MB downloaded in 0.51 s (16.03 MB/s)
117 11:47:32.376627 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:47:32.377026 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:47:32.377149 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:47:32.377278 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:47:32.377390 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:47:32.377505 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:47:32.377783 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn
125 11:47:32.377956 makedir: /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin
126 11:47:32.378092 makedir: /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/tests
127 11:47:32.378204 makedir: /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/results
128 11:47:32.378321 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-add-keys
129 11:47:32.378494 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-add-sources
130 11:47:32.378661 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-background-process-start
131 11:47:32.378825 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-background-process-stop
132 11:47:32.379035 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-common-functions
133 11:47:32.379168 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-echo-ipv4
134 11:47:32.379302 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-install-packages
135 11:47:32.379428 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-installed-packages
136 11:47:32.379556 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-os-build
137 11:47:32.379680 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-probe-channel
138 11:47:32.379808 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-probe-ip
139 11:47:32.379966 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-target-ip
140 11:47:32.380139 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-target-mac
141 11:47:32.380280 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-target-storage
142 11:47:32.380448 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-case
143 11:47:32.380609 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-event
144 11:47:32.380768 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-feedback
145 11:47:32.380928 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-raise
146 11:47:32.381086 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-reference
147 11:47:32.381246 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-runner
148 11:47:32.381405 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-set
149 11:47:32.381562 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-test-shell
150 11:47:32.381727 Updating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-install-packages (oe)
151 11:47:32.381912 Updating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/bin/lava-installed-packages (oe)
152 11:47:32.382042 Creating /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/environment
153 11:47:32.382150 LAVA metadata
154 11:47:32.382222 - LAVA_JOB_ID=12074050
155 11:47:32.382287 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:47:32.382396 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:47:32.382490 skipped lava-vland-overlay
158 11:47:32.382594 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:47:32.382705 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:47:32.382801 skipped lava-multinode-overlay
161 11:47:32.382955 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:47:32.383074 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:47:32.383181 Loading test definitions
164 11:47:32.383307 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:47:32.383410 Using /lava-12074050 at stage 0
166 11:47:32.383834 uuid=12074050_1.5.2.3.1 testdef=None
167 11:47:32.383955 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:47:32.384077 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:47:32.384815 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:47:32.385169 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:47:32.386053 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:47:32.386299 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:47:32.387254 runner path: /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12074050_1.5.2.3.1
176 11:47:32.387413 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:47:32.387623 Creating lava-test-runner.conf files
179 11:47:32.387689 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074050/lava-overlay-u4aedobn/lava-12074050/0 for stage 0
180 11:47:32.387779 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:47:32.387874 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:47:32.387961 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:47:32.395796 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:47:32.395903 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:47:32.395988 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:47:32.396084 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:47:32.396203 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:47:33.113032 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:47:33.113432 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:47:33.113545 extracting modules file /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074050/extract-overlay-ramdisk-_5dmcf_v/ramdisk
191 11:47:33.366298 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:47:33.366474 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:47:33.366577 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074050/compress-overlay-aypt1r98/overlay-1.5.2.4.tar.gz to ramdisk
194 11:47:33.366650 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074050/compress-overlay-aypt1r98/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074050/extract-overlay-ramdisk-_5dmcf_v/ramdisk
195 11:47:33.373323 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:47:33.373437 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:47:33.373529 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:47:33.373622 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:47:33.373700 Building ramdisk /var/lib/lava/dispatcher/tmp/12074050/extract-overlay-ramdisk-_5dmcf_v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074050/extract-overlay-ramdisk-_5dmcf_v/ramdisk
200 11:47:33.985979 >> 228427 blocks
201 11:47:37.923664 rename /var/lib/lava/dispatcher/tmp/12074050/extract-overlay-ramdisk-_5dmcf_v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/ramdisk/ramdisk.cpio.gz
202 11:47:37.924123 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:47:37.924247 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 11:47:37.924355 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 11:47:37.924466 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/kernel/Image'
206 11:47:50.385666 Returned 0 in 12 seconds
207 11:47:50.486309 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/kernel/image.itb
208 11:47:51.118192 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:47:51.118592 output: Created: Fri Nov 24 11:47:50 2023
210 11:47:51.118673 output: Image 0 (kernel-1)
211 11:47:51.118769 output: Description:
212 11:47:51.118834 output: Created: Fri Nov 24 11:47:50 2023
213 11:47:51.118944 output: Type: Kernel Image
214 11:47:51.119020 output: Compression: lzma compressed
215 11:47:51.119079 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
216 11:47:51.119164 output: Architecture: AArch64
217 11:47:51.119220 output: OS: Linux
218 11:47:51.119274 output: Load Address: 0x00000000
219 11:47:51.119351 output: Entry Point: 0x00000000
220 11:47:51.119420 output: Hash algo: crc32
221 11:47:51.119490 output: Hash value: 43cfb6ad
222 11:47:51.119564 output: Image 1 (fdt-1)
223 11:47:51.119617 output: Description: mt8192-asurada-spherion-r0
224 11:47:51.119683 output: Created: Fri Nov 24 11:47:50 2023
225 11:47:51.119749 output: Type: Flat Device Tree
226 11:47:51.119827 output: Compression: uncompressed
227 11:47:51.119914 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:47:51.119966 output: Architecture: AArch64
229 11:47:51.120017 output: Hash algo: crc32
230 11:47:51.120096 output: Hash value: cc4352de
231 11:47:51.120148 output: Image 2 (ramdisk-1)
232 11:47:51.120198 output: Description: unavailable
233 11:47:51.120284 output: Created: Fri Nov 24 11:47:50 2023
234 11:47:51.120336 output: Type: RAMDisk Image
235 11:47:51.120387 output: Compression: Unknown Compression
236 11:47:51.120451 output: Data Size: 39378501 Bytes = 38455.57 KiB = 37.55 MiB
237 11:47:51.120504 output: Architecture: AArch64
238 11:47:51.120555 output: OS: Linux
239 11:47:51.120607 output: Load Address: unavailable
240 11:47:51.120659 output: Entry Point: unavailable
241 11:47:51.120709 output: Hash algo: crc32
242 11:47:51.120761 output: Hash value: 119afcae
243 11:47:51.120812 output: Default Configuration: 'conf-1'
244 11:47:51.120864 output: Configuration 0 (conf-1)
245 11:47:51.120915 output: Description: mt8192-asurada-spherion-r0
246 11:47:51.120967 output: Kernel: kernel-1
247 11:47:51.121018 output: Init Ramdisk: ramdisk-1
248 11:47:51.121070 output: FDT: fdt-1
249 11:47:51.121121 output: Loadables: kernel-1
250 11:47:51.121172 output:
251 11:47:51.121371 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:47:51.121465 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:47:51.121569 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 11:47:51.121666 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 11:47:51.121746 No LXC device requested
256 11:47:51.121828 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:47:51.121910 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 11:47:51.121988 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:47:51.122077 Checking files for TFTP limit of 4294967296 bytes.
260 11:47:51.122644 end: 1 tftp-deploy (duration 00:00:20) [common]
261 11:47:51.122746 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:47:51.122834 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:47:51.123019 substitutions:
264 11:47:51.123124 - {DTB}: 12074050/tftp-deploy-tn_pzva9/dtb/mt8192-asurada-spherion-r0.dtb
265 11:47:51.123228 - {INITRD}: 12074050/tftp-deploy-tn_pzva9/ramdisk/ramdisk.cpio.gz
266 11:47:51.123343 - {KERNEL}: 12074050/tftp-deploy-tn_pzva9/kernel/Image
267 11:47:51.123441 - {LAVA_MAC}: None
268 11:47:51.123570 - {PRESEED_CONFIG}: None
269 11:47:51.123665 - {PRESEED_LOCAL}: None
270 11:47:51.123763 - {RAMDISK}: 12074050/tftp-deploy-tn_pzva9/ramdisk/ramdisk.cpio.gz
271 11:47:51.123864 - {ROOT_PART}: None
272 11:47:51.123953 - {ROOT}: None
273 11:47:51.124022 - {SERVER_IP}: 192.168.201.1
274 11:47:51.124076 - {TEE}: None
275 11:47:51.124129 Parsed boot commands:
276 11:47:51.124210 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:47:51.124411 Parsed boot commands: tftpboot 192.168.201.1 12074050/tftp-deploy-tn_pzva9/kernel/image.itb 12074050/tftp-deploy-tn_pzva9/kernel/cmdline
278 11:47:51.124500 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:47:51.124620 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:47:51.124726 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:47:51.124826 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:47:51.124894 Not connected, no need to disconnect.
283 11:47:51.125002 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:47:51.125078 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:47:51.125182 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 11:47:51.129314 Setting prompt string to ['lava-test: # ']
287 11:47:51.129704 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:47:51.129825 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:47:51.129951 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:47:51.130046 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:47:51.130255 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 11:47:56.278726 >> Command sent successfully.
293 11:47:56.289200 Returned 0 in 5 seconds
294 11:47:56.390403 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:47:56.391981 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:47:56.392440 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:47:56.392887 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:47:56.393278 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:47:56.393854 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:47:56.395304 [Enter `^Ec?' for help]
302 11:47:56.558293
303 11:47:56.559050
304 11:47:56.559448 F0: 102B 0000
305 11:47:56.559797
306 11:47:56.560118 F3: 1001 0000 [0200]
307 11:47:56.561407
308 11:47:56.561831 F3: 1001 0000
309 11:47:56.562173
310 11:47:56.562474 F7: 102D 0000
311 11:47:56.562812
312 11:47:56.564858 F1: 0000 0000
313 11:47:56.565213
314 11:47:56.565533 V0: 0000 0000 [0001]
315 11:47:56.565843
316 11:47:56.568410 00: 0007 8000
317 11:47:56.568885
318 11:47:56.569228 01: 0000 0000
319 11:47:56.569550
320 11:47:56.571752 BP: 0C00 0209 [0000]
321 11:47:56.572171
322 11:47:56.572536 G0: 1182 0000
323 11:47:56.572911
324 11:47:56.575362 EC: 0000 0021 [4000]
325 11:47:56.575793
326 11:47:56.576149 S7: 0000 0000 [0000]
327 11:47:56.576529
328 11:47:56.578921 CC: 0000 0000 [0001]
329 11:47:56.579473
330 11:47:56.579835 T0: 0000 0040 [010F]
331 11:47:56.580190
332 11:47:56.580533 Jump to BL
333 11:47:56.580834
334 11:47:56.605379
335 11:47:56.605466
336 11:47:56.605532
337 11:47:56.612470 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:47:56.616182 ARM64: Exception handlers installed.
339 11:47:56.619731 ARM64: Testing exception
340 11:47:56.623274 ARM64: Done test exception
341 11:47:56.629408 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:47:56.639578 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:47:56.646998 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:47:56.656501 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:47:56.663336 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:47:56.670155 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:47:56.682150 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:47:56.688469 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:47:56.707949 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:47:56.711038 WDT: Last reset was cold boot
351 11:47:56.714611 SPI1(PAD0) initialized at 2873684 Hz
352 11:47:56.717938 SPI5(PAD0) initialized at 992727 Hz
353 11:47:56.721240 VBOOT: Loading verstage.
354 11:47:56.727950 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:47:56.731321 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:47:56.734406 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:47:56.738471 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:47:56.745206 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:47:56.751758 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:47:56.762635 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 11:47:56.762738
362 11:47:56.762819
363 11:47:56.772949 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:47:56.776383 ARM64: Exception handlers installed.
365 11:47:56.779987 ARM64: Testing exception
366 11:47:56.780138 ARM64: Done test exception
367 11:47:56.786405 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:47:56.789930 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:47:56.804883 Probing TPM: . done!
370 11:47:56.805269 TPM ready after 0 ms
371 11:47:56.812118 Connected to device vid:did:rid of 1ae0:0028:00
372 11:47:56.819014 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:47:56.876678 Initialized TPM device CR50 revision 0
374 11:47:56.886760 tlcl_send_startup: Startup return code is 0
375 11:47:56.887251 TPM: setup succeeded
376 11:47:56.898149 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:47:56.906608 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:47:56.918647 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:47:56.928899 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:47:56.932388 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:47:56.938098 in-header: 03 07 00 00 08 00 00 00
382 11:47:56.941610 in-data: aa e4 47 04 13 02 00 00
383 11:47:56.945615 Chrome EC: UHEPI supported
384 11:47:56.952856 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:47:56.956242 in-header: 03 ad 00 00 08 00 00 00
386 11:47:56.956346 in-data: 00 20 20 08 00 00 00 00
387 11:47:56.960099 Phase 1
388 11:47:56.963957 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:47:56.967441 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:47:56.974949 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:47:56.977796 Recovery requested (1009000e)
392 11:47:56.984551 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:47:56.990064 tlcl_extend: response is 0
394 11:47:56.998104 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:47:57.003301 tlcl_extend: response is 0
396 11:47:57.010268 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:47:57.030797 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 11:47:57.037956 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:47:57.038037
400 11:47:57.038103
401 11:47:57.049103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:47:57.052241 ARM64: Exception handlers installed.
403 11:47:57.052335 ARM64: Testing exception
404 11:47:57.055525 ARM64: Done test exception
405 11:47:57.076288 pmic_efuse_setting: Set efuses in 11 msecs
406 11:47:57.079835 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:47:57.086695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:47:57.090044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:47:57.096569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:47:57.100106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:47:57.104016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:47:57.107906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:47:57.115609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:47:57.119435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:47:57.123096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:47:57.126932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:47:57.134079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:47:57.137758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:47:57.141320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:47:57.148860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:47:57.152877 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:47:57.160116 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:47:57.164026 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:47:57.171021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:47:57.178520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:47:57.182263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:47:57.189539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:47:57.193169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:47:57.200996 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:47:57.204296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:47:57.208333 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:47:57.216018 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:47:57.219531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:47:57.226847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:47:57.230592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:47:57.234319 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:47:57.242011 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:47:57.245265 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:47:57.248967 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:47:57.256450 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:47:57.259822 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:47:57.263703 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:47:57.271014 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:47:57.275241 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:47:57.278830 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:47:57.282329 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:47:57.289963 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:47:57.294305 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:47:57.297313 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:47:57.301016 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:47:57.304759 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:47:57.308753 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:47:57.316258 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:47:57.319945 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:47:57.323343 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:47:57.326820 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:47:57.330498 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:47:57.338619 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:47:57.349892 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:47:57.353473 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:47:57.360761 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:47:57.368228 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:47:57.372419 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:47:57.379492 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:47:57.383385 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:47:57.390795 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x26
467 11:47:57.394091 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:47:57.402219 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:47:57.405073 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:47:57.414083 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 11:47:57.423745 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 11:47:57.433000 [RTC]rtc_get_frequency_meter,154: input=19, output=883
473 11:47:57.441992 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 11:47:57.451681 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 11:47:57.461224 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 11:47:57.471010 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 11:47:57.475144 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 11:47:57.478736 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 11:47:57.482783 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:47:57.490658 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:47:57.494532 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:47:57.497229 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:47:57.501317 ADC[4]: Raw value=902436 ID=7
484 11:47:57.501432 ADC[3]: Raw value=213336 ID=1
485 11:47:57.505750 RAM Code: 0x71
486 11:47:57.509066 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:47:57.512740 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:47:57.523585 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:47:57.527702 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:47:57.531844 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:47:57.535043 in-header: 03 07 00 00 08 00 00 00
492 11:47:57.539377 in-data: aa e4 47 04 13 02 00 00
493 11:47:57.542765 Chrome EC: UHEPI supported
494 11:47:57.546558 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:47:57.550340 in-header: 03 ed 00 00 08 00 00 00
496 11:47:57.554295 in-data: 80 20 60 08 00 00 00 00
497 11:47:57.557974 MRC: failed to locate region type 0.
498 11:47:57.565291 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:47:57.568987 DRAM-K: Running full calibration
500 11:47:57.572408 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:47:57.576984 header.status = 0x0
502 11:47:57.579904 header.version = 0x6 (expected: 0x6)
503 11:47:57.584307 header.size = 0xd00 (expected: 0xd00)
504 11:47:57.584389 header.flags = 0x0
505 11:47:57.590846 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:47:57.608071 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 11:47:57.615550 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:47:57.615630 dram_init: ddr_geometry: 2
509 11:47:57.619749 [EMI] MDL number = 2
510 11:47:57.622975 [EMI] Get MDL freq = 0
511 11:47:57.623049 dram_init: ddr_type: 0
512 11:47:57.627039 is_discrete_lpddr4: 1
513 11:47:57.627122 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:47:57.630734
515 11:47:57.630932
516 11:47:57.631053 [Bian_co] ETT version 0.0.0.1
517 11:47:57.638197 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:47:57.638332
519 11:47:57.642156 dramc_set_vcore_voltage set vcore to 650000
520 11:47:57.642352 Read voltage for 800, 4
521 11:47:57.642495 Vio18 = 0
522 11:47:57.645117 Vcore = 650000
523 11:47:57.645335 Vdram = 0
524 11:47:57.645514 Vddq = 0
525 11:47:57.649076 Vmddr = 0
526 11:47:57.649163 dram_init: config_dvfs: 1
527 11:47:57.655502 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:47:57.658724 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:47:57.662254 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 11:47:57.668985 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 11:47:57.672077 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 11:47:57.675669 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 11:47:57.679047 MEM_TYPE=3, freq_sel=18
534 11:47:57.682241 sv_algorithm_assistance_LP4_1600
535 11:47:57.685806 ============ PULL DRAM RESETB DOWN ============
536 11:47:57.688832 ========== PULL DRAM RESETB DOWN end =========
537 11:47:57.692433 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:47:57.695532 ===================================
539 11:47:57.699081 LPDDR4 DRAM CONFIGURATION
540 11:47:57.702851 ===================================
541 11:47:57.706192 EX_ROW_EN[0] = 0x0
542 11:47:57.706372 EX_ROW_EN[1] = 0x0
543 11:47:57.709915 LP4Y_EN = 0x0
544 11:47:57.710105 WORK_FSP = 0x0
545 11:47:57.712897 WL = 0x2
546 11:47:57.713106 RL = 0x2
547 11:47:57.715833 BL = 0x2
548 11:47:57.715999 RPST = 0x0
549 11:47:57.719126 RD_PRE = 0x0
550 11:47:57.719308 WR_PRE = 0x1
551 11:47:57.722808 WR_PST = 0x0
552 11:47:57.723022 DBI_WR = 0x0
553 11:47:57.725490 DBI_RD = 0x0
554 11:47:57.725582 OTF = 0x1
555 11:47:57.728934 ===================================
556 11:47:57.732430 ===================================
557 11:47:57.735820 ANA top config
558 11:47:57.739152 ===================================
559 11:47:57.742339 DLL_ASYNC_EN = 0
560 11:47:57.742425 ALL_SLAVE_EN = 1
561 11:47:57.745903 NEW_RANK_MODE = 1
562 11:47:57.749856 DLL_IDLE_MODE = 1
563 11:47:57.752651 LP45_APHY_COMB_EN = 1
564 11:47:57.752737 TX_ODT_DIS = 1
565 11:47:57.756114 NEW_8X_MODE = 1
566 11:47:57.759175 ===================================
567 11:47:57.762667 ===================================
568 11:47:57.765816 data_rate = 1600
569 11:47:57.769175 CKR = 1
570 11:47:57.772804 DQ_P2S_RATIO = 8
571 11:47:57.776379 ===================================
572 11:47:57.776472 CA_P2S_RATIO = 8
573 11:47:57.779589 DQ_CA_OPEN = 0
574 11:47:57.782520 DQ_SEMI_OPEN = 0
575 11:47:57.786309 CA_SEMI_OPEN = 0
576 11:47:57.789646 CA_FULL_RATE = 0
577 11:47:57.793130 DQ_CKDIV4_EN = 1
578 11:47:57.793259 CA_CKDIV4_EN = 1
579 11:47:57.796066 CA_PREDIV_EN = 0
580 11:47:57.799730 PH8_DLY = 0
581 11:47:57.803082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:47:57.806106 DQ_AAMCK_DIV = 4
583 11:47:57.806189 CA_AAMCK_DIV = 4
584 11:47:57.809907 CA_ADMCK_DIV = 4
585 11:47:57.813254 DQ_TRACK_CA_EN = 0
586 11:47:57.816643 CA_PICK = 800
587 11:47:57.820095 CA_MCKIO = 800
588 11:47:57.822796 MCKIO_SEMI = 0
589 11:47:57.826412 PLL_FREQ = 3068
590 11:47:57.826495 DQ_UI_PI_RATIO = 32
591 11:47:57.830723 CA_UI_PI_RATIO = 0
592 11:47:57.834031 ===================================
593 11:47:57.837723 ===================================
594 11:47:57.841673 memory_type:LPDDR4
595 11:47:57.841759 GP_NUM : 10
596 11:47:57.845399 SRAM_EN : 1
597 11:47:57.845486 MD32_EN : 0
598 11:47:57.849068 ===================================
599 11:47:57.852748 [ANA_INIT] >>>>>>>>>>>>>>
600 11:47:57.852924 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:47:57.856780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:47:57.860897 ===================================
603 11:47:57.864350 data_rate = 1600,PCW = 0X7600
604 11:47:57.867134 ===================================
605 11:47:57.870689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:47:57.877587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:47:57.880767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:47:57.887408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:47:57.890910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:47:57.893879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:47:57.893966 [ANA_INIT] flow start
612 11:47:57.897545 [ANA_INIT] PLL >>>>>>>>
613 11:47:57.900954 [ANA_INIT] PLL <<<<<<<<
614 11:47:57.901041 [ANA_INIT] MIDPI >>>>>>>>
615 11:47:57.904062 [ANA_INIT] MIDPI <<<<<<<<
616 11:47:57.908087 [ANA_INIT] DLL >>>>>>>>
617 11:47:57.908173 [ANA_INIT] flow end
618 11:47:57.910736 ============ LP4 DIFF to SE enter ============
619 11:47:57.917658 ============ LP4 DIFF to SE exit ============
620 11:47:57.917744 [ANA_INIT] <<<<<<<<<<<<<
621 11:47:57.921209 [Flow] Enable top DCM control >>>>>
622 11:47:57.924456 [Flow] Enable top DCM control <<<<<
623 11:47:57.927582 Enable DLL master slave shuffle
624 11:47:57.934211 ==============================================================
625 11:47:57.934401 Gating Mode config
626 11:47:57.940991 ==============================================================
627 11:47:57.944307 Config description:
628 11:47:57.951277 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:47:57.958110 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:47:57.964531 SELPH_MODE 0: By rank 1: By Phase
631 11:47:57.971259 ==============================================================
632 11:47:57.971346 GAT_TRACK_EN = 1
633 11:47:57.975111 RX_GATING_MODE = 2
634 11:47:57.978047 RX_GATING_TRACK_MODE = 2
635 11:47:57.981627 SELPH_MODE = 1
636 11:47:57.984846 PICG_EARLY_EN = 1
637 11:47:57.988327 VALID_LAT_VALUE = 1
638 11:47:57.995372 ==============================================================
639 11:47:57.998494 Enter into Gating configuration >>>>
640 11:47:58.001584 Exit from Gating configuration <<<<
641 11:47:58.001744 Enter into DVFS_PRE_config >>>>>
642 11:47:58.015029 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:47:58.018832 Exit from DVFS_PRE_config <<<<<
644 11:47:58.021992 Enter into PICG configuration >>>>
645 11:47:58.025286 Exit from PICG configuration <<<<
646 11:47:58.025370 [RX_INPUT] configuration >>>>>
647 11:47:58.028541 [RX_INPUT] configuration <<<<<
648 11:47:58.035270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:47:58.039132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:47:58.045900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:47:58.053004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:47:58.059412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:47:58.066782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:47:58.069611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:47:58.073311 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:47:58.076273 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:47:58.079633 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:47:58.086124 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:47:58.089234 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:47:58.092985 ===================================
661 11:47:58.096657 LPDDR4 DRAM CONFIGURATION
662 11:47:58.099979 ===================================
663 11:47:58.100064 EX_ROW_EN[0] = 0x0
664 11:47:58.102676 EX_ROW_EN[1] = 0x0
665 11:47:58.102760 LP4Y_EN = 0x0
666 11:47:58.106714 WORK_FSP = 0x0
667 11:47:58.106798 WL = 0x2
668 11:47:58.109456 RL = 0x2
669 11:47:58.109538 BL = 0x2
670 11:47:58.113030 RPST = 0x0
671 11:47:58.113114 RD_PRE = 0x0
672 11:47:58.116190 WR_PRE = 0x1
673 11:47:58.116274 WR_PST = 0x0
674 11:47:58.120174 DBI_WR = 0x0
675 11:47:58.120260 DBI_RD = 0x0
676 11:47:58.123106 OTF = 0x1
677 11:47:58.126344 ===================================
678 11:47:58.130441 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:47:58.133480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:47:58.140214 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:47:58.143405 ===================================
682 11:47:58.143607 LPDDR4 DRAM CONFIGURATION
683 11:47:58.146722 ===================================
684 11:47:58.150451 EX_ROW_EN[0] = 0x10
685 11:47:58.153321 EX_ROW_EN[1] = 0x0
686 11:47:58.153408 LP4Y_EN = 0x0
687 11:47:58.157065 WORK_FSP = 0x0
688 11:47:58.157151 WL = 0x2
689 11:47:58.160223 RL = 0x2
690 11:47:58.160309 BL = 0x2
691 11:47:58.163465 RPST = 0x0
692 11:47:58.163551 RD_PRE = 0x0
693 11:47:58.166626 WR_PRE = 0x1
694 11:47:58.166712 WR_PST = 0x0
695 11:47:58.170196 DBI_WR = 0x0
696 11:47:58.170283 DBI_RD = 0x0
697 11:47:58.173345 OTF = 0x1
698 11:47:58.176988 ===================================
699 11:47:58.180336 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:47:58.185870 nWR fixed to 40
701 11:47:58.189385 [ModeRegInit_LP4] CH0 RK0
702 11:47:58.189494 [ModeRegInit_LP4] CH0 RK1
703 11:47:58.192246 [ModeRegInit_LP4] CH1 RK0
704 11:47:58.196056 [ModeRegInit_LP4] CH1 RK1
705 11:47:58.196141 match AC timing 13
706 11:47:58.202689 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:47:58.205954 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:47:58.209604 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:47:58.216079 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:47:58.219088 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:47:58.219174 [EMI DOE] emi_dcm 0
712 11:47:58.226382 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:47:58.226468 ==
714 11:47:58.229604 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:47:58.232791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:47:58.232878 ==
717 11:47:58.239566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:47:58.242756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:47:58.253269 [CA 0] Center 37 (7~68) winsize 62
720 11:47:58.256709 [CA 1] Center 37 (6~68) winsize 63
721 11:47:58.259898 [CA 2] Center 35 (5~66) winsize 62
722 11:47:58.263610 [CA 3] Center 34 (4~65) winsize 62
723 11:47:58.266920 [CA 4] Center 34 (3~65) winsize 63
724 11:47:58.269927 [CA 5] Center 33 (3~64) winsize 62
725 11:47:58.270019
726 11:47:58.273795 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:47:58.273939
728 11:47:58.277218 [CATrainingPosCal] consider 1 rank data
729 11:47:58.280552 u2DelayCellTimex100 = 270/100 ps
730 11:47:58.283954 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:47:58.287194 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:47:58.290319 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:47:58.297272 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:47:58.300399 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 11:47:58.303629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:47:58.303805
737 11:47:58.307093 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:47:58.307271
739 11:47:58.310243 [CBTSetCACLKResult] CA Dly = 33
740 11:47:58.310448 CS Dly: 6 (0~37)
741 11:47:58.310611 ==
742 11:47:58.313419 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:47:58.320659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:47:58.321134 ==
745 11:47:58.324908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:47:58.330351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:47:58.339992 [CA 0] Center 37 (6~68) winsize 63
748 11:47:58.343423 [CA 1] Center 37 (7~68) winsize 62
749 11:47:58.346602 [CA 2] Center 35 (5~66) winsize 62
750 11:47:58.350251 [CA 3] Center 35 (4~66) winsize 63
751 11:47:58.353610 [CA 4] Center 34 (3~65) winsize 63
752 11:47:58.356936 [CA 5] Center 33 (3~64) winsize 62
753 11:47:58.357365
754 11:47:58.360318 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:47:58.360750
756 11:47:58.363550 [CATrainingPosCal] consider 2 rank data
757 11:47:58.366970 u2DelayCellTimex100 = 270/100 ps
758 11:47:58.370539 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:47:58.373286 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:47:58.376720 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:47:58.384121 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:47:58.386958 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 11:47:58.390370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:47:58.390803
765 11:47:58.393999 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:47:58.394425
767 11:47:58.397052 [CBTSetCACLKResult] CA Dly = 33
768 11:47:58.397547 CS Dly: 6 (0~38)
769 11:47:58.397892
770 11:47:58.400760 ----->DramcWriteLeveling(PI) begin...
771 11:47:58.401197 ==
772 11:47:58.403404 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:47:58.410479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:47:58.410968 ==
775 11:47:58.414772 Write leveling (Byte 0): 31 => 31
776 11:47:58.415249 Write leveling (Byte 1): 30 => 30
777 11:47:58.417936 DramcWriteLeveling(PI) end<-----
778 11:47:58.418363
779 11:47:58.418761 ==
780 11:47:58.422017 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:47:58.425609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:47:58.426057 ==
783 11:47:58.428992 [Gating] SW mode calibration
784 11:47:58.435492 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:47:58.442522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:47:58.446270 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:47:58.449658 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:47:58.452735 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 11:47:58.458979 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 11:47:58.462693 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:47:58.465990 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:47:58.472743 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:47:58.475890 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:47:58.479366 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:47:58.486139 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:47:58.489742 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:47:58.492859 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:47:58.499669 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:47:58.502720 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:47:58.506059 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:47:58.513001 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:47:58.516242 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:47:58.519639 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:47:58.526323 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 11:47:58.529549 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:47:58.532983 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:47:58.536095 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:47:58.543235 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:47:58.546553 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:47:58.549784 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:47:58.556453 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:47:58.559938 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:47:58.563028 0 9 12 | B1->B0 | 2525 2e2e | 1 1 | (1 1) (1 1)
814 11:47:58.570190 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:47:58.573495 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:47:58.577011 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:47:58.580159 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:47:58.586596 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:47:58.590100 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 11:47:58.593140 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
821 11:47:58.599869 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
822 11:47:58.603679 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:47:58.606899 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:47:58.613411 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:47:58.616956 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:47:58.620234 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:47:58.627276 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:47:58.630560 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
829 11:47:58.633537 0 11 12 | B1->B0 | 3939 4040 | 0 0 | (0 0) (0 0)
830 11:47:58.636950 0 11 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
831 11:47:58.644039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:47:58.647191 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:47:58.650719 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:47:58.658417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:47:58.661087 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:47:58.664754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 11:47:58.671443 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:47:58.674616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:47:58.677773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:47:58.684515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:47:58.687955 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:47:58.691203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:47:58.697965 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:47:58.701297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:47:58.704722 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:47:58.707843 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:47:58.714544 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:47:58.718094 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:47:58.721443 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:47:58.728358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:47:58.731832 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:47:58.734894 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 11:47:58.741555 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 11:47:58.742000 Total UI for P1: 0, mck2ui 16
855 11:47:58.744929 best dqsien dly found for B0: ( 0, 14, 10)
856 11:47:58.748170 Total UI for P1: 0, mck2ui 16
857 11:47:58.751402 best dqsien dly found for B1: ( 0, 14, 10)
858 11:47:58.755191 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 11:47:58.761459 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 11:47:58.761904
861 11:47:58.765271 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 11:47:58.768799 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 11:47:58.771992 [Gating] SW calibration Done
864 11:47:58.772436 ==
865 11:47:58.775387 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:47:58.778342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:47:58.778788 ==
868 11:47:58.779279 RX Vref Scan: 0
869 11:47:58.781797
870 11:47:58.782236 RX Vref 0 -> 0, step: 1
871 11:47:58.782686
872 11:47:58.785093 RX Delay -130 -> 252, step: 16
873 11:47:58.788560 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:47:58.791704 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 11:47:58.798402 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:47:58.802013 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:47:58.805790 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 11:47:58.808820 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:47:58.812512 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:47:58.818977 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:47:58.822564 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:47:58.826175 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 11:47:58.829235 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 11:47:58.832384 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:47:58.838745 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:47:58.842238 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 11:47:58.845640 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 11:47:58.848822 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 11:47:58.849265 ==
890 11:47:58.852231 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:47:58.855832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:47:58.859049 ==
893 11:47:58.859515 DQS Delay:
894 11:47:58.859993 DQS0 = 0, DQS1 = 0
895 11:47:58.862598 DQM Delay:
896 11:47:58.863083 DQM0 = 88, DQM1 = 82
897 11:47:58.863542 DQ Delay:
898 11:47:58.865914 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 11:47:58.869245 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
900 11:47:58.872667 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
901 11:47:58.876157 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
902 11:47:58.876596
903 11:47:58.877043
904 11:47:58.879599 ==
905 11:47:58.882708 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:47:58.886239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:47:58.886687 ==
908 11:47:58.887178
909 11:47:58.887604
910 11:47:58.889066 TX Vref Scan disable
911 11:47:58.889512 == TX Byte 0 ==
912 11:47:58.892977 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 11:47:58.899150 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 11:47:58.899596 == TX Byte 1 ==
915 11:47:58.903120 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 11:47:58.909579 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 11:47:58.910028 ==
918 11:47:58.912488 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:47:58.916150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:47:58.916596 ==
921 11:47:58.929476 TX Vref=22, minBit 5, minWin=27, winSum=441
922 11:47:58.932313 TX Vref=24, minBit 5, minWin=27, winSum=442
923 11:47:58.936192 TX Vref=26, minBit 12, minWin=27, winSum=451
924 11:47:58.939483 TX Vref=28, minBit 12, minWin=27, winSum=453
925 11:47:58.942391 TX Vref=30, minBit 3, minWin=28, winSum=459
926 11:47:58.949040 TX Vref=32, minBit 12, minWin=27, winSum=454
927 11:47:58.952807 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 30
928 11:47:58.953252
929 11:47:58.955838 Final TX Range 1 Vref 30
930 11:47:58.956284
931 11:47:58.956732 ==
932 11:47:58.959375 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:47:58.962569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:47:58.963062 ==
935 11:47:58.963511
936 11:47:58.965904
937 11:47:58.966349 TX Vref Scan disable
938 11:47:58.969250 == TX Byte 0 ==
939 11:47:58.972452 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 11:47:58.975838 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 11:47:58.979752 == TX Byte 1 ==
942 11:47:58.983162 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 11:47:58.986405 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 11:47:58.986830
945 11:47:58.989584 [DATLAT]
946 11:47:58.990040 Freq=800, CH0 RK0
947 11:47:58.990421
948 11:47:58.993291 DATLAT Default: 0xa
949 11:47:58.993717 0, 0xFFFF, sum = 0
950 11:47:58.996551 1, 0xFFFF, sum = 0
951 11:47:58.996993 2, 0xFFFF, sum = 0
952 11:47:59.000016 3, 0xFFFF, sum = 0
953 11:47:59.000443 4, 0xFFFF, sum = 0
954 11:47:59.003176 5, 0xFFFF, sum = 0
955 11:47:59.003612 6, 0xFFFF, sum = 0
956 11:47:59.006572 7, 0xFFFF, sum = 0
957 11:47:59.007075 8, 0xFFFF, sum = 0
958 11:47:59.009579 9, 0x0, sum = 1
959 11:47:59.010013 10, 0x0, sum = 2
960 11:47:59.013266 11, 0x0, sum = 3
961 11:47:59.013700 12, 0x0, sum = 4
962 11:47:59.016458 best_step = 10
963 11:47:59.016883
964 11:47:59.017218 ==
965 11:47:59.020017 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:47:59.023331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:47:59.023763 ==
968 11:47:59.026608 RX Vref Scan: 1
969 11:47:59.027063
970 11:47:59.027401 Set Vref Range= 32 -> 127
971 11:47:59.027715
972 11:47:59.030112 RX Vref 32 -> 127, step: 1
973 11:47:59.030538
974 11:47:59.033380 RX Delay -95 -> 252, step: 8
975 11:47:59.033945
976 11:47:59.036584 Set Vref, RX VrefLevel [Byte0]: 32
977 11:47:59.040288 [Byte1]: 32
978 11:47:59.040727
979 11:47:59.043922 Set Vref, RX VrefLevel [Byte0]: 33
980 11:47:59.047354 [Byte1]: 33
981 11:47:59.047793
982 11:47:59.050674 Set Vref, RX VrefLevel [Byte0]: 34
983 11:47:59.054119 [Byte1]: 34
984 11:47:59.054557
985 11:47:59.057586 Set Vref, RX VrefLevel [Byte0]: 35
986 11:47:59.061358 [Byte1]: 35
987 11:47:59.064680
988 11:47:59.065119 Set Vref, RX VrefLevel [Byte0]: 36
989 11:47:59.068127 [Byte1]: 36
990 11:47:59.072426
991 11:47:59.072866 Set Vref, RX VrefLevel [Byte0]: 37
992 11:47:59.076236 [Byte1]: 37
993 11:47:59.080818
994 11:47:59.081279 Set Vref, RX VrefLevel [Byte0]: 38
995 11:47:59.083699 [Byte1]: 38
996 11:47:59.087987
997 11:47:59.088429 Set Vref, RX VrefLevel [Byte0]: 39
998 11:47:59.091663 [Byte1]: 39
999 11:47:59.095686
1000 11:47:59.096126 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:47:59.098681 [Byte1]: 40
1002 11:47:59.103022
1003 11:47:59.103465 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:47:59.106779 [Byte1]: 41
1005 11:47:59.110989
1006 11:47:59.111426 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:47:59.113783 [Byte1]: 42
1008 11:47:59.117891
1009 11:47:59.118332 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:47:59.121531 [Byte1]: 43
1011 11:47:59.125834
1012 11:47:59.126276 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:47:59.128442 [Byte1]: 44
1014 11:47:59.132825
1015 11:47:59.132910 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:47:59.135950 [Byte1]: 45
1017 11:47:59.140613
1018 11:47:59.140705 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:47:59.144090 [Byte1]: 46
1020 11:47:59.147913
1021 11:47:59.148027 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:47:59.151265 [Byte1]: 47
1023 11:47:59.155684
1024 11:47:59.155770 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:47:59.158858 [Byte1]: 48
1026 11:47:59.163320
1027 11:47:59.163409 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:47:59.166789 [Byte1]: 49
1029 11:47:59.170933
1030 11:47:59.171016 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:47:59.174186 [Byte1]: 50
1032 11:47:59.178218
1033 11:47:59.178302 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:47:59.181548 [Byte1]: 51
1035 11:47:59.185938
1036 11:47:59.186022 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:47:59.189120 [Byte1]: 52
1038 11:47:59.193572
1039 11:47:59.193655 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:47:59.197093 [Byte1]: 53
1041 11:47:59.201849
1042 11:47:59.201932 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:47:59.204831 [Byte1]: 54
1044 11:47:59.209346
1045 11:47:59.209520 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:47:59.212165 [Byte1]: 55
1047 11:47:59.216716
1048 11:47:59.216898 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:47:59.219805 [Byte1]: 56
1050 11:47:59.224591
1051 11:47:59.224766 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:47:59.227777 [Byte1]: 57
1053 11:47:59.231995
1054 11:47:59.232228 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:47:59.235493 [Byte1]: 58
1056 11:47:59.239468
1057 11:47:59.239729 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:47:59.242690 [Byte1]: 59
1059 11:47:59.247122
1060 11:47:59.247412 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:47:59.250359 [Byte1]: 60
1062 11:47:59.255021
1063 11:47:59.255440 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:47:59.257878 [Byte1]: 61
1065 11:47:59.262150
1066 11:47:59.262547 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:47:59.265452 [Byte1]: 62
1068 11:47:59.270040
1069 11:47:59.270515 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:47:59.272882 [Byte1]: 63
1071 11:47:59.277558
1072 11:47:59.278040 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:47:59.280969 [Byte1]: 64
1074 11:47:59.284877
1075 11:47:59.285307 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:47:59.288361 [Byte1]: 65
1077 11:47:59.292787
1078 11:47:59.293218 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:47:59.295957 [Byte1]: 66
1080 11:47:59.299996
1081 11:47:59.300428 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:47:59.303396 [Byte1]: 67
1083 11:47:59.308205
1084 11:47:59.308723 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:47:59.311041 [Byte1]: 68
1086 11:47:59.315656
1087 11:47:59.316073 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:47:59.318970 [Byte1]: 69
1089 11:47:59.323261
1090 11:47:59.323704 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:47:59.326588 [Byte1]: 70
1092 11:47:59.330665
1093 11:47:59.331108 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:47:59.333970 [Byte1]: 71
1095 11:47:59.338460
1096 11:47:59.338932 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:47:59.341473 [Byte1]: 72
1098 11:47:59.345923
1099 11:47:59.346449 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:47:59.349667 [Byte1]: 73
1101 11:47:59.353439
1102 11:47:59.353853 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:47:59.356713 [Byte1]: 74
1104 11:47:59.361262
1105 11:47:59.361678 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:47:59.364495 [Byte1]: 75
1107 11:47:59.368820
1108 11:47:59.369234 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:47:59.371792 [Byte1]: 76
1110 11:47:59.376022
1111 11:47:59.376438 Set Vref, RX VrefLevel [Byte0]: 77
1112 11:47:59.379914 [Byte1]: 77
1113 11:47:59.383632
1114 11:47:59.384050 Set Vref, RX VrefLevel [Byte0]: 78
1115 11:47:59.387196 [Byte1]: 78
1116 11:47:59.391845
1117 11:47:59.392264 Set Vref, RX VrefLevel [Byte0]: 79
1118 11:47:59.394462 [Byte1]: 79
1119 11:47:59.399138
1120 11:47:59.399683 Final RX Vref Byte 0 = 65 to rank0
1121 11:47:59.402179 Final RX Vref Byte 1 = 59 to rank0
1122 11:47:59.405814 Final RX Vref Byte 0 = 65 to rank1
1123 11:47:59.409280 Final RX Vref Byte 1 = 59 to rank1==
1124 11:47:59.412367 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 11:47:59.415817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 11:47:59.419495 ==
1127 11:47:59.419987 DQS Delay:
1128 11:47:59.420480 DQS0 = 0, DQS1 = 0
1129 11:47:59.422666 DQM Delay:
1130 11:47:59.423152 DQM0 = 88, DQM1 = 79
1131 11:47:59.425614 DQ Delay:
1132 11:47:59.426030 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1133 11:47:59.428892 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =92
1134 11:47:59.432668 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1135 11:47:59.435818 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1136 11:47:59.436236
1137 11:47:59.439408
1138 11:47:59.446308 [DQSOSCAuto] RK0, (LSB)MR18= 0x2810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1139 11:47:59.449719 CH0 RK0: MR19=606, MR18=2810
1140 11:47:59.453269 CH0_RK0: MR19=0x606, MR18=0x2810, DQSOSC=399, MR23=63, INC=92, DEC=61
1141 11:47:59.455962
1142 11:47:59.459964 ----->DramcWriteLeveling(PI) begin...
1143 11:47:59.460540 ==
1144 11:47:59.462822 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 11:47:59.466442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 11:47:59.466937 ==
1147 11:47:59.470028 Write leveling (Byte 0): 33 => 33
1148 11:47:59.473095 Write leveling (Byte 1): 28 => 28
1149 11:47:59.476569 DramcWriteLeveling(PI) end<-----
1150 11:47:59.477028
1151 11:47:59.477394 ==
1152 11:47:59.479875 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 11:47:59.482693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 11:47:59.483195 ==
1155 11:47:59.486496 [Gating] SW mode calibration
1156 11:47:59.493300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 11:47:59.536855 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 11:47:59.537297 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 11:47:59.538018 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1160 11:47:59.538381 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1161 11:47:59.538696 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:47:59.539050 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:47:59.539351 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:47:59.539639 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:47:59.539949 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:47:59.540306 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:47:59.581455 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:47:59.582251 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:47:59.582612 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:47:59.582974 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:47:59.583347 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:47:59.583661 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:47:59.584011 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:47:59.584364 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:47:59.584666 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 11:47:59.585009 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1177 11:47:59.591463 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:47:59.594983 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:47:59.598268 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:47:59.598687 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:47:59.605207 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:47:59.608042 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:47:59.611480 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:47:59.614928 0 9 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
1185 11:47:59.621564 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1186 11:47:59.624877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:47:59.628301 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:47:59.634849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 11:47:59.638267 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 11:47:59.641436 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 11:47:59.648632 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1192 11:47:59.651672 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1193 11:47:59.655051 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:47:59.662070 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:47:59.665772 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:47:59.669361 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:47:59.673425 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:47:59.677705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:47:59.680975 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1200 11:47:59.688148 0 11 8 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (1 1)
1201 11:47:59.691756 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
1202 11:47:59.695070 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:47:59.698695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:47:59.705319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:47:59.708215 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 11:47:59.711657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:47:59.718613 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:47:59.721926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1209 11:47:59.725376 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:47:59.731951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:47:59.735121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:47:59.738580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:47:59.741867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:47:59.748626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:47:59.752072 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:47:59.755695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:47:59.762273 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:47:59.765601 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:47:59.768718 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:47:59.775271 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:47:59.778586 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:47:59.781995 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:47:59.789009 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1224 11:47:59.792187 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 11:47:59.795876 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 11:47:59.799226 Total UI for P1: 0, mck2ui 16
1227 11:47:59.802329 best dqsien dly found for B0: ( 0, 14, 6)
1228 11:47:59.806032 Total UI for P1: 0, mck2ui 16
1229 11:47:59.809012 best dqsien dly found for B1: ( 0, 14, 8)
1230 11:47:59.812538 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1231 11:47:59.815892 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 11:47:59.815974
1233 11:47:59.819309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1234 11:47:59.822212 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 11:47:59.825625 [Gating] SW calibration Done
1236 11:47:59.825706 ==
1237 11:47:59.829039 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 11:47:59.832402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 11:47:59.836052 ==
1240 11:47:59.836133 RX Vref Scan: 0
1241 11:47:59.836199
1242 11:47:59.839263 RX Vref 0 -> 0, step: 1
1243 11:47:59.839343
1244 11:47:59.842307 RX Delay -130 -> 252, step: 16
1245 11:47:59.845940 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1246 11:47:59.849247 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1247 11:47:59.852853 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1248 11:47:59.855765 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1249 11:47:59.862443 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1250 11:47:59.865792 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1251 11:47:59.869479 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1252 11:47:59.872759 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1253 11:47:59.876138 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1254 11:47:59.879450 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1255 11:47:59.886073 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1256 11:47:59.889395 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1257 11:47:59.892592 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1258 11:47:59.895967 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1259 11:47:59.902708 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1260 11:47:59.906630 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1261 11:47:59.906712 ==
1262 11:47:59.909411 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 11:47:59.912960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 11:47:59.913042 ==
1265 11:47:59.913108 DQS Delay:
1266 11:47:59.916449 DQS0 = 0, DQS1 = 0
1267 11:47:59.916530 DQM Delay:
1268 11:47:59.920057 DQM0 = 85, DQM1 = 76
1269 11:47:59.920138 DQ Delay:
1270 11:47:59.923311 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1271 11:47:59.926489 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1272 11:47:59.930059 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1273 11:47:59.933400 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1274 11:47:59.933481
1275 11:47:59.933545
1276 11:47:59.933605 ==
1277 11:47:59.936724 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 11:47:59.940182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 11:47:59.940264 ==
1280 11:47:59.940328
1281 11:47:59.943396
1282 11:47:59.943477 TX Vref Scan disable
1283 11:47:59.946780 == TX Byte 0 ==
1284 11:47:59.949975 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1285 11:47:59.953519 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1286 11:47:59.956422 == TX Byte 1 ==
1287 11:47:59.959868 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1288 11:47:59.963418 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1289 11:47:59.963499 ==
1290 11:47:59.966622 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:47:59.973367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:47:59.973449 ==
1293 11:47:59.985407 TX Vref=22, minBit 3, minWin=27, winSum=442
1294 11:47:59.988585 TX Vref=24, minBit 9, minWin=27, winSum=449
1295 11:47:59.991803 TX Vref=26, minBit 9, minWin=27, winSum=449
1296 11:47:59.995130 TX Vref=28, minBit 12, minWin=27, winSum=452
1297 11:47:59.998422 TX Vref=30, minBit 12, minWin=27, winSum=455
1298 11:48:00.005334 TX Vref=32, minBit 13, minWin=27, winSum=456
1299 11:48:00.008910 [TxChooseVref] Worse bit 13, Min win 27, Win sum 456, Final Vref 32
1300 11:48:00.008997
1301 11:48:00.011848 Final TX Range 1 Vref 32
1302 11:48:00.011924
1303 11:48:00.011986 ==
1304 11:48:00.015266 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 11:48:00.018436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 11:48:00.021931 ==
1307 11:48:00.022012
1308 11:48:00.022084
1309 11:48:00.022144 TX Vref Scan disable
1310 11:48:00.025919 == TX Byte 0 ==
1311 11:48:00.029259 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1312 11:48:00.032160 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1313 11:48:00.036285 == TX Byte 1 ==
1314 11:48:00.038915 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1315 11:48:00.042414 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1316 11:48:00.045603
1317 11:48:00.045709 [DATLAT]
1318 11:48:00.045800 Freq=800, CH0 RK1
1319 11:48:00.045888
1320 11:48:00.049008 DATLAT Default: 0xa
1321 11:48:00.049089 0, 0xFFFF, sum = 0
1322 11:48:00.052913 1, 0xFFFF, sum = 0
1323 11:48:00.053001 2, 0xFFFF, sum = 0
1324 11:48:00.056172 3, 0xFFFF, sum = 0
1325 11:48:00.056258 4, 0xFFFF, sum = 0
1326 11:48:00.059563 5, 0xFFFF, sum = 0
1327 11:48:00.059634 6, 0xFFFF, sum = 0
1328 11:48:00.062331 7, 0xFFFF, sum = 0
1329 11:48:00.062403 8, 0xFFFF, sum = 0
1330 11:48:00.066369 9, 0x0, sum = 1
1331 11:48:00.066439 10, 0x0, sum = 2
1332 11:48:00.069232 11, 0x0, sum = 3
1333 11:48:00.069305 12, 0x0, sum = 4
1334 11:48:00.072952 best_step = 10
1335 11:48:00.073031
1336 11:48:00.073096 ==
1337 11:48:00.076175 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 11:48:00.079339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 11:48:00.079418 ==
1340 11:48:00.082612 RX Vref Scan: 0
1341 11:48:00.082691
1342 11:48:00.082753 RX Vref 0 -> 0, step: 1
1343 11:48:00.082812
1344 11:48:00.086005 RX Delay -95 -> 252, step: 8
1345 11:48:00.092739 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1346 11:48:00.096022 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1347 11:48:00.099460 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1348 11:48:00.103067 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1349 11:48:00.106350 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1350 11:48:00.112624 iDelay=209, Bit 5, Center 72 (-39 ~ 184) 224
1351 11:48:00.116070 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1352 11:48:00.119771 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1353 11:48:00.123181 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1354 11:48:00.127133 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1355 11:48:00.129711 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1356 11:48:00.136345 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1357 11:48:00.139873 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1358 11:48:00.143288 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1359 11:48:00.146703 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1360 11:48:00.149856 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1361 11:48:00.153069 ==
1362 11:48:00.153150 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:48:00.159681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:48:00.159794 ==
1365 11:48:00.159886 DQS Delay:
1366 11:48:00.163096 DQS0 = 0, DQS1 = 0
1367 11:48:00.163166 DQM Delay:
1368 11:48:00.166502 DQM0 = 86, DQM1 = 77
1369 11:48:00.166571 DQ Delay:
1370 11:48:00.169978 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1371 11:48:00.173178 DQ4 =88, DQ5 =72, DQ6 =96, DQ7 =96
1372 11:48:00.176911 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1373 11:48:00.180147 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1374 11:48:00.180228
1375 11:48:00.180291
1376 11:48:00.187205 [DQSOSCAuto] RK1, (LSB)MR18= 0x331c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1377 11:48:00.190311 CH0 RK1: MR19=606, MR18=331C
1378 11:48:00.197031 CH0_RK1: MR19=0x606, MR18=0x331C, DQSOSC=396, MR23=63, INC=94, DEC=62
1379 11:48:00.200341 [RxdqsGatingPostProcess] freq 800
1380 11:48:00.203929 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 11:48:00.207126 Pre-setting of DQS Precalculation
1382 11:48:00.214183 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 11:48:00.214263 ==
1384 11:48:00.217133 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 11:48:00.220666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 11:48:00.220747 ==
1387 11:48:00.227381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 11:48:00.230692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 11:48:00.241499 [CA 0] Center 36 (6~67) winsize 62
1390 11:48:00.244162 [CA 1] Center 36 (6~67) winsize 62
1391 11:48:00.247794 [CA 2] Center 34 (4~64) winsize 61
1392 11:48:00.251130 [CA 3] Center 33 (3~64) winsize 62
1393 11:48:00.254027 [CA 4] Center 34 (3~65) winsize 63
1394 11:48:00.257276 [CA 5] Center 33 (3~64) winsize 62
1395 11:48:00.257356
1396 11:48:00.260646 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 11:48:00.260726
1398 11:48:00.264041 [CATrainingPosCal] consider 1 rank data
1399 11:48:00.267619 u2DelayCellTimex100 = 270/100 ps
1400 11:48:00.271009 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1401 11:48:00.274479 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1402 11:48:00.277304 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1403 11:48:00.284496 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 11:48:00.287628 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1405 11:48:00.291336 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1406 11:48:00.291455
1407 11:48:00.294327 CA PerBit enable=1, Macro0, CA PI delay=33
1408 11:48:00.294406
1409 11:48:00.297954 [CBTSetCACLKResult] CA Dly = 33
1410 11:48:00.298035 CS Dly: 5 (0~36)
1411 11:48:00.298099 ==
1412 11:48:00.301375 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 11:48:00.307628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 11:48:00.307716 ==
1415 11:48:00.310954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 11:48:00.318394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 11:48:00.327025 [CA 0] Center 36 (5~67) winsize 63
1418 11:48:00.331445 [CA 1] Center 36 (5~67) winsize 63
1419 11:48:00.334677 [CA 2] Center 34 (4~64) winsize 61
1420 11:48:00.338358 [CA 3] Center 33 (3~64) winsize 62
1421 11:48:00.342543 [CA 4] Center 34 (3~65) winsize 63
1422 11:48:00.342627 [CA 5] Center 33 (3~64) winsize 62
1423 11:48:00.342711
1424 11:48:00.346083 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1425 11:48:00.346165
1426 11:48:00.349885 [CATrainingPosCal] consider 2 rank data
1427 11:48:00.353962 u2DelayCellTimex100 = 270/100 ps
1428 11:48:00.357588 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1429 11:48:00.361782 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1430 11:48:00.364901 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1431 11:48:00.368330 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1432 11:48:00.371623 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1433 11:48:00.375037 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1434 11:48:00.375116
1435 11:48:00.378296 CA PerBit enable=1, Macro0, CA PI delay=33
1436 11:48:00.381503
1437 11:48:00.381582 [CBTSetCACLKResult] CA Dly = 33
1438 11:48:00.384849 CS Dly: 5 (0~36)
1439 11:48:00.384929
1440 11:48:00.388429 ----->DramcWriteLeveling(PI) begin...
1441 11:48:00.388510 ==
1442 11:48:00.391838 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:48:00.395085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:48:00.395165 ==
1445 11:48:00.398280 Write leveling (Byte 0): 27 => 27
1446 11:48:00.401955 Write leveling (Byte 1): 29 => 29
1447 11:48:00.405153 DramcWriteLeveling(PI) end<-----
1448 11:48:00.405233
1449 11:48:00.405327 ==
1450 11:48:00.408734 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 11:48:00.412314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 11:48:00.412396 ==
1453 11:48:00.415556 [Gating] SW mode calibration
1454 11:48:00.422105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 11:48:00.429133 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 11:48:00.432460 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 11:48:00.435778 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1458 11:48:00.442551 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1459 11:48:00.445598 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:48:00.449177 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:48:00.455609 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:48:00.459021 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:48:00.462776 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:48:00.469061 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:48:00.472424 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:48:00.476155 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:48:00.479104 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1468 11:48:00.486042 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:48:00.489476 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:48:00.492905 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:48:00.499445 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:48:00.503403 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:48:00.506440 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:48:00.512887 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1475 11:48:00.516520 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:48:00.519639 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:48:00.526113 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:48:00.529617 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:48:00.532782 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:48:00.536253 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:48:00.543036 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:48:00.546433 0 9 8 | B1->B0 | 2828 2626 | 1 1 | (1 1) (1 1)
1483 11:48:00.549931 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:48:00.556405 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:48:00.560157 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 11:48:00.563783 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1487 11:48:00.570229 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 11:48:00.573806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 11:48:00.576981 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1490 11:48:00.584037 0 10 8 | B1->B0 | 2d2d 2f2f | 0 0 | (1 0) (1 0)
1491 11:48:00.586977 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:48:00.590239 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:48:00.593384 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:48:00.599971 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1495 11:48:00.603453 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:48:00.606901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:48:00.613889 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1498 11:48:00.617088 0 11 8 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
1499 11:48:00.620387 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:48:00.627195 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:48:00.630479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:48:00.634129 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 11:48:00.640400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 11:48:00.643968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:48:00.647605 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 11:48:00.651025 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1507 11:48:00.657658 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:48:00.660941 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:48:00.664243 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:48:00.671081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:48:00.674040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:48:00.677426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:48:00.684503 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:48:00.687803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:48:00.690697 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:48:00.697698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:48:00.701086 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:48:00.704399 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:48:00.707842 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:48:00.714709 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:48:00.718047 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:48:00.721395 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1523 11:48:00.724518 Total UI for P1: 0, mck2ui 16
1524 11:48:00.728150 best dqsien dly found for B0: ( 0, 14, 6)
1525 11:48:00.734458 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 11:48:00.734539 Total UI for P1: 0, mck2ui 16
1527 11:48:00.741623 best dqsien dly found for B1: ( 0, 14, 8)
1528 11:48:00.744509 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1529 11:48:00.748089 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1530 11:48:00.748170
1531 11:48:00.751302 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1532 11:48:00.754703 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1533 11:48:00.758012 [Gating] SW calibration Done
1534 11:48:00.758097 ==
1535 11:48:00.761703 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 11:48:00.764835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1537 11:48:00.764911 ==
1538 11:48:00.764975 RX Vref Scan: 0
1539 11:48:00.768314
1540 11:48:00.768390 RX Vref 0 -> 0, step: 1
1541 11:48:00.768472
1542 11:48:00.771625 RX Delay -130 -> 252, step: 16
1543 11:48:00.775247 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1544 11:48:00.778327 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1545 11:48:00.784962 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1546 11:48:00.788458 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1547 11:48:00.791832 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1548 11:48:00.795077 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1549 11:48:00.798632 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1550 11:48:00.802559 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1551 11:48:00.808602 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1552 11:48:00.811927 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1553 11:48:00.815225 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1554 11:48:00.819092 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1555 11:48:00.821889 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1556 11:48:00.829356 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1557 11:48:00.832611 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1558 11:48:00.836075 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1559 11:48:00.836250 ==
1560 11:48:00.839616 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 11:48:00.842405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 11:48:00.842608 ==
1563 11:48:00.845877 DQS Delay:
1564 11:48:00.846117 DQS0 = 0, DQS1 = 0
1565 11:48:00.849621 DQM Delay:
1566 11:48:00.849920 DQM0 = 81, DQM1 = 75
1567 11:48:00.850157 DQ Delay:
1568 11:48:00.852539 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1569 11:48:00.855881 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1570 11:48:00.859187 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1571 11:48:00.862782 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1572 11:48:00.862900
1573 11:48:00.862970
1574 11:48:00.863046 ==
1575 11:48:00.866245 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 11:48:00.872338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 11:48:00.872420 ==
1578 11:48:00.872485
1579 11:48:00.872544
1580 11:48:00.872603 TX Vref Scan disable
1581 11:48:00.876168 == TX Byte 0 ==
1582 11:48:00.879886 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1583 11:48:00.886155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1584 11:48:00.886237 == TX Byte 1 ==
1585 11:48:00.889618 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1586 11:48:00.896678 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1587 11:48:00.896773 ==
1588 11:48:00.899790 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:48:00.903087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:48:00.903198 ==
1591 11:48:00.915596 TX Vref=22, minBit 8, minWin=26, winSum=433
1592 11:48:00.919088 TX Vref=24, minBit 11, minWin=26, winSum=438
1593 11:48:00.922514 TX Vref=26, minBit 0, minWin=27, winSum=442
1594 11:48:00.925798 TX Vref=28, minBit 10, minWin=27, winSum=449
1595 11:48:00.929033 TX Vref=30, minBit 13, minWin=27, winSum=452
1596 11:48:00.932632 TX Vref=32, minBit 9, minWin=27, winSum=454
1597 11:48:00.939168 [TxChooseVref] Worse bit 9, Min win 27, Win sum 454, Final Vref 32
1598 11:48:00.939251
1599 11:48:00.942858 Final TX Range 1 Vref 32
1600 11:48:00.942983
1601 11:48:00.943048 ==
1602 11:48:00.945760 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 11:48:00.949449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 11:48:00.949532 ==
1605 11:48:00.949597
1606 11:48:00.949657
1607 11:48:00.952997 TX Vref Scan disable
1608 11:48:00.955898 == TX Byte 0 ==
1609 11:48:00.959253 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 11:48:00.963105 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 11:48:00.966549 == TX Byte 1 ==
1612 11:48:00.969545 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1613 11:48:00.973425 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1614 11:48:00.973613
1615 11:48:00.976428 [DATLAT]
1616 11:48:00.976577 Freq=800, CH1 RK0
1617 11:48:00.976666
1618 11:48:00.979624 DATLAT Default: 0xa
1619 11:48:00.979745 0, 0xFFFF, sum = 0
1620 11:48:00.983064 1, 0xFFFF, sum = 0
1621 11:48:00.983214 2, 0xFFFF, sum = 0
1622 11:48:00.986569 3, 0xFFFF, sum = 0
1623 11:48:00.986769 4, 0xFFFF, sum = 0
1624 11:48:00.989550 5, 0xFFFF, sum = 0
1625 11:48:00.989704 6, 0xFFFF, sum = 0
1626 11:48:00.992799 7, 0xFFFF, sum = 0
1627 11:48:00.992975 8, 0xFFFF, sum = 0
1628 11:48:00.996355 9, 0x0, sum = 1
1629 11:48:00.996531 10, 0x0, sum = 2
1630 11:48:01.000008 11, 0x0, sum = 3
1631 11:48:01.000252 12, 0x0, sum = 4
1632 11:48:01.003436 best_step = 10
1633 11:48:01.003676
1634 11:48:01.003865 ==
1635 11:48:01.006618 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 11:48:01.009718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 11:48:01.010038 ==
1638 11:48:01.010303 RX Vref Scan: 1
1639 11:48:01.013505
1640 11:48:01.013876 Set Vref Range= 32 -> 127
1641 11:48:01.014251
1642 11:48:01.017018 RX Vref 32 -> 127, step: 1
1643 11:48:01.017374
1644 11:48:01.020447 RX Delay -95 -> 252, step: 8
1645 11:48:01.020863
1646 11:48:01.023737 Set Vref, RX VrefLevel [Byte0]: 32
1647 11:48:01.026698 [Byte1]: 32
1648 11:48:01.027213
1649 11:48:01.030339 Set Vref, RX VrefLevel [Byte0]: 33
1650 11:48:01.033835 [Byte1]: 33
1651 11:48:01.034260
1652 11:48:01.037235 Set Vref, RX VrefLevel [Byte0]: 34
1653 11:48:01.040031 [Byte1]: 34
1654 11:48:01.044078
1655 11:48:01.044469 Set Vref, RX VrefLevel [Byte0]: 35
1656 11:48:01.047308 [Byte1]: 35
1657 11:48:01.052131
1658 11:48:01.052547 Set Vref, RX VrefLevel [Byte0]: 36
1659 11:48:01.054688 [Byte1]: 36
1660 11:48:01.059262
1661 11:48:01.059655 Set Vref, RX VrefLevel [Byte0]: 37
1662 11:48:01.062745 [Byte1]: 37
1663 11:48:01.066646
1664 11:48:01.067130 Set Vref, RX VrefLevel [Byte0]: 38
1665 11:48:01.069942 [Byte1]: 38
1666 11:48:01.074565
1667 11:48:01.075207 Set Vref, RX VrefLevel [Byte0]: 39
1668 11:48:01.077495 [Byte1]: 39
1669 11:48:01.082432
1670 11:48:01.085604 Set Vref, RX VrefLevel [Byte0]: 40
1671 11:48:01.086211 [Byte1]: 40
1672 11:48:01.089384
1673 11:48:01.089866 Set Vref, RX VrefLevel [Byte0]: 41
1674 11:48:01.092913 [Byte1]: 41
1675 11:48:01.096967
1676 11:48:01.097421 Set Vref, RX VrefLevel [Byte0]: 42
1677 11:48:01.100949 [Byte1]: 42
1678 11:48:01.105043
1679 11:48:01.105677 Set Vref, RX VrefLevel [Byte0]: 43
1680 11:48:01.108418 [Byte1]: 43
1681 11:48:01.112172
1682 11:48:01.112646 Set Vref, RX VrefLevel [Byte0]: 44
1683 11:48:01.115880 [Byte1]: 44
1684 11:48:01.119810
1685 11:48:01.120304 Set Vref, RX VrefLevel [Byte0]: 45
1686 11:48:01.123716 [Byte1]: 45
1687 11:48:01.127387
1688 11:48:01.127878 Set Vref, RX VrefLevel [Byte0]: 46
1689 11:48:01.130903 [Byte1]: 46
1690 11:48:01.135091
1691 11:48:01.135520 Set Vref, RX VrefLevel [Byte0]: 47
1692 11:48:01.138452 [Byte1]: 47
1693 11:48:01.143005
1694 11:48:01.143426 Set Vref, RX VrefLevel [Byte0]: 48
1695 11:48:01.146505 [Byte1]: 48
1696 11:48:01.150631
1697 11:48:01.151095 Set Vref, RX VrefLevel [Byte0]: 49
1698 11:48:01.153863 [Byte1]: 49
1699 11:48:01.157967
1700 11:48:01.158385 Set Vref, RX VrefLevel [Byte0]: 50
1701 11:48:01.161547 [Byte1]: 50
1702 11:48:01.165301
1703 11:48:01.165716 Set Vref, RX VrefLevel [Byte0]: 51
1704 11:48:01.168513 [Byte1]: 51
1705 11:48:01.173262
1706 11:48:01.173680 Set Vref, RX VrefLevel [Byte0]: 52
1707 11:48:01.176813 [Byte1]: 52
1708 11:48:01.180892
1709 11:48:01.181306 Set Vref, RX VrefLevel [Byte0]: 53
1710 11:48:01.184207 [Byte1]: 53
1711 11:48:01.188298
1712 11:48:01.188716 Set Vref, RX VrefLevel [Byte0]: 54
1713 11:48:01.191634 [Byte1]: 54
1714 11:48:01.196204
1715 11:48:01.196624 Set Vref, RX VrefLevel [Byte0]: 55
1716 11:48:01.199192 [Byte1]: 55
1717 11:48:01.203757
1718 11:48:01.204174 Set Vref, RX VrefLevel [Byte0]: 56
1719 11:48:01.206634 [Byte1]: 56
1720 11:48:01.210950
1721 11:48:01.211397 Set Vref, RX VrefLevel [Byte0]: 57
1722 11:48:01.217326 [Byte1]: 57
1723 11:48:01.217807
1724 11:48:01.221084 Set Vref, RX VrefLevel [Byte0]: 58
1725 11:48:01.224418 [Byte1]: 58
1726 11:48:01.224827
1727 11:48:01.228133 Set Vref, RX VrefLevel [Byte0]: 59
1728 11:48:01.230770 [Byte1]: 59
1729 11:48:01.231250
1730 11:48:01.234307 Set Vref, RX VrefLevel [Byte0]: 60
1731 11:48:01.237467 [Byte1]: 60
1732 11:48:01.241466
1733 11:48:01.241948 Set Vref, RX VrefLevel [Byte0]: 61
1734 11:48:01.244717 [Byte1]: 61
1735 11:48:01.249406
1736 11:48:01.249864 Set Vref, RX VrefLevel [Byte0]: 62
1737 11:48:01.252227 [Byte1]: 62
1738 11:48:01.256597
1739 11:48:01.257067 Set Vref, RX VrefLevel [Byte0]: 63
1740 11:48:01.259866 [Byte1]: 63
1741 11:48:01.264039
1742 11:48:01.264456 Set Vref, RX VrefLevel [Byte0]: 64
1743 11:48:01.267795 [Byte1]: 64
1744 11:48:01.271735
1745 11:48:01.272151 Set Vref, RX VrefLevel [Byte0]: 65
1746 11:48:01.275116 [Byte1]: 65
1747 11:48:01.279508
1748 11:48:01.279925 Set Vref, RX VrefLevel [Byte0]: 66
1749 11:48:01.282447 [Byte1]: 66
1750 11:48:01.286948
1751 11:48:01.287027 Set Vref, RX VrefLevel [Byte0]: 67
1752 11:48:01.290036 [Byte1]: 67
1753 11:48:01.294409
1754 11:48:01.294517 Set Vref, RX VrefLevel [Byte0]: 68
1755 11:48:01.297741 [Byte1]: 68
1756 11:48:01.302014
1757 11:48:01.302094 Set Vref, RX VrefLevel [Byte0]: 69
1758 11:48:01.305034 [Byte1]: 69
1759 11:48:01.309558
1760 11:48:01.309632 Set Vref, RX VrefLevel [Byte0]: 70
1761 11:48:01.313392 [Byte1]: 70
1762 11:48:01.317329
1763 11:48:01.317400 Set Vref, RX VrefLevel [Byte0]: 71
1764 11:48:01.320379 [Byte1]: 71
1765 11:48:01.325012
1766 11:48:01.325091 Set Vref, RX VrefLevel [Byte0]: 72
1767 11:48:01.328204 [Byte1]: 72
1768 11:48:01.332537
1769 11:48:01.332617 Set Vref, RX VrefLevel [Byte0]: 73
1770 11:48:01.335331 [Byte1]: 73
1771 11:48:01.339639
1772 11:48:01.339719 Set Vref, RX VrefLevel [Byte0]: 74
1773 11:48:01.343312 [Byte1]: 74
1774 11:48:01.347726
1775 11:48:01.347828 Set Vref, RX VrefLevel [Byte0]: 75
1776 11:48:01.350800 [Byte1]: 75
1777 11:48:01.354870
1778 11:48:01.354950 Set Vref, RX VrefLevel [Byte0]: 76
1779 11:48:01.358338 [Byte1]: 76
1780 11:48:01.362547
1781 11:48:01.362642 Set Vref, RX VrefLevel [Byte0]: 77
1782 11:48:01.366148 [Byte1]: 77
1783 11:48:01.370085
1784 11:48:01.370172 Set Vref, RX VrefLevel [Byte0]: 78
1785 11:48:01.373385 [Byte1]: 78
1786 11:48:01.378306
1787 11:48:01.378412 Set Vref, RX VrefLevel [Byte0]: 79
1788 11:48:01.381478 [Byte1]: 79
1789 11:48:01.385357
1790 11:48:01.385465 Final RX Vref Byte 0 = 61 to rank0
1791 11:48:01.388974 Final RX Vref Byte 1 = 58 to rank0
1792 11:48:01.392114 Final RX Vref Byte 0 = 61 to rank1
1793 11:48:01.395623 Final RX Vref Byte 1 = 58 to rank1==
1794 11:48:01.399143 Dram Type= 6, Freq= 0, CH_1, rank 0
1795 11:48:01.402682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 11:48:01.405501 ==
1797 11:48:01.405671 DQS Delay:
1798 11:48:01.405804 DQS0 = 0, DQS1 = 0
1799 11:48:01.408847 DQM Delay:
1800 11:48:01.409043 DQM0 = 83, DQM1 = 73
1801 11:48:01.412794 DQ Delay:
1802 11:48:01.413018 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1803 11:48:01.416366 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1804 11:48:01.419743 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1805 11:48:01.422654 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1806 11:48:01.422983
1807 11:48:01.423337
1808 11:48:01.432755 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1809 11:48:01.436507 CH1 RK0: MR19=606, MR18=2E03
1810 11:48:01.439926 CH1_RK0: MR19=0x606, MR18=0x2E03, DQSOSC=398, MR23=63, INC=93, DEC=62
1811 11:48:01.440397
1812 11:48:01.442978 ----->DramcWriteLeveling(PI) begin...
1813 11:48:01.446469 ==
1814 11:48:01.449951 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 11:48:01.453314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 11:48:01.453730 ==
1817 11:48:01.456962 Write leveling (Byte 0): 26 => 26
1818 11:48:01.460274 Write leveling (Byte 1): 27 => 27
1819 11:48:01.463022 DramcWriteLeveling(PI) end<-----
1820 11:48:01.463434
1821 11:48:01.463760 ==
1822 11:48:01.466436 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 11:48:01.470090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 11:48:01.470461 ==
1825 11:48:01.473497 [Gating] SW mode calibration
1826 11:48:01.479925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1827 11:48:01.483459 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1828 11:48:01.489930 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1829 11:48:01.493153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1830 11:48:01.496752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:48:01.503309 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:48:01.506784 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:48:01.510020 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:48:01.516865 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:48:01.520195 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:48:01.523421 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:48:01.527284 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:48:01.533555 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:48:01.537237 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:48:01.540701 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:48:01.546956 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:48:01.550580 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:48:01.553833 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:48:01.560262 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:48:01.563718 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1846 11:48:01.567522 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:48:01.574257 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:48:01.577573 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:48:01.581010 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:48:01.584075 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:48:01.591038 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:48:01.594302 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:48:01.597537 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1854 11:48:01.604684 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1855 11:48:01.607448 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 11:48:01.611482 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 11:48:01.618015 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 11:48:01.621170 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 11:48:01.624420 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 11:48:01.631308 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1861 11:48:01.634774 0 10 4 | B1->B0 | 3232 2c2c | 1 1 | (1 0) (1 0)
1862 11:48:01.637814 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:48:01.644438 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:48:01.648146 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:48:01.651188 0 10 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1866 11:48:01.654623 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1867 11:48:01.661381 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:48:01.664920 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:48:01.668246 0 11 4 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
1870 11:48:01.674502 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1871 11:48:01.677592 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 11:48:01.681019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 11:48:01.687942 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 11:48:01.691234 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 11:48:01.694920 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 11:48:01.701517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 11:48:01.704424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1878 11:48:01.708081 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1879 11:48:01.714694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:48:01.717943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:48:01.721411 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:48:01.725013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 11:48:01.731725 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 11:48:01.735168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 11:48:01.738046 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 11:48:01.744565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 11:48:01.748052 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 11:48:01.751604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 11:48:01.758304 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 11:48:01.761236 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 11:48:01.764821 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 11:48:01.771999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1893 11:48:01.774976 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1894 11:48:01.778401 Total UI for P1: 0, mck2ui 16
1895 11:48:01.781736 best dqsien dly found for B0: ( 0, 14, 0)
1896 11:48:01.785054 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 11:48:01.788527 Total UI for P1: 0, mck2ui 16
1898 11:48:01.792092 best dqsien dly found for B1: ( 0, 14, 4)
1899 11:48:01.794901 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1900 11:48:01.798358 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1901 11:48:01.798812
1902 11:48:01.801985 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1903 11:48:01.805348 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1904 11:48:01.808333 [Gating] SW calibration Done
1905 11:48:01.808788 ==
1906 11:48:01.812175 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 11:48:01.819248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 11:48:01.819769 ==
1909 11:48:01.820148 RX Vref Scan: 0
1910 11:48:01.820484
1911 11:48:01.822147 RX Vref 0 -> 0, step: 1
1912 11:48:01.822601
1913 11:48:01.825293 RX Delay -130 -> 252, step: 16
1914 11:48:01.828616 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1915 11:48:01.832188 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1916 11:48:01.835784 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1917 11:48:01.838838 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1918 11:48:01.845231 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1919 11:48:01.849003 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1920 11:48:01.852410 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1921 11:48:01.855980 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1922 11:48:01.859371 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1923 11:48:01.862546 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1924 11:48:01.869115 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1925 11:48:01.872421 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1926 11:48:01.876246 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1927 11:48:01.879772 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1928 11:48:01.882611 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1929 11:48:01.890056 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1930 11:48:01.890613 ==
1931 11:48:01.893229 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 11:48:01.895899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 11:48:01.896359 ==
1934 11:48:01.896723 DQS Delay:
1935 11:48:01.899759 DQS0 = 0, DQS1 = 0
1936 11:48:01.900216 DQM Delay:
1937 11:48:01.902823 DQM0 = 82, DQM1 = 79
1938 11:48:01.903507 DQ Delay:
1939 11:48:01.905915 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1940 11:48:01.909848 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1941 11:48:01.912904 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1942 11:48:01.916608 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
1943 11:48:01.917278
1944 11:48:01.917647
1945 11:48:01.917986 ==
1946 11:48:01.920082 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 11:48:01.923420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 11:48:01.923859 ==
1949 11:48:01.924354
1950 11:48:01.924810
1951 11:48:01.926780 TX Vref Scan disable
1952 11:48:01.929577 == TX Byte 0 ==
1953 11:48:01.933106 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1954 11:48:01.936303 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1955 11:48:01.939597 == TX Byte 1 ==
1956 11:48:01.943000 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1957 11:48:01.946523 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1958 11:48:01.946987 ==
1959 11:48:01.950011 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:48:01.953291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:48:01.956470 ==
1962 11:48:01.967658 TX Vref=22, minBit 12, minWin=26, winSum=437
1963 11:48:01.970757 TX Vref=24, minBit 8, minWin=27, winSum=442
1964 11:48:01.974170 TX Vref=26, minBit 0, minWin=27, winSum=446
1965 11:48:01.978132 TX Vref=28, minBit 10, minWin=27, winSum=449
1966 11:48:01.981213 TX Vref=30, minBit 15, minWin=27, winSum=452
1967 11:48:01.987392 TX Vref=32, minBit 10, minWin=27, winSum=452
1968 11:48:01.991047 [TxChooseVref] Worse bit 15, Min win 27, Win sum 452, Final Vref 30
1969 11:48:01.991504
1970 11:48:01.994289 Final TX Range 1 Vref 30
1971 11:48:01.994700
1972 11:48:01.995105 ==
1973 11:48:01.997663 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 11:48:02.001249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 11:48:02.001745 ==
1976 11:48:02.004633
1977 11:48:02.005084
1978 11:48:02.005439 TX Vref Scan disable
1979 11:48:02.007924 == TX Byte 0 ==
1980 11:48:02.011148 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1981 11:48:02.014252 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1982 11:48:02.017800 == TX Byte 1 ==
1983 11:48:02.021598 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1984 11:48:02.024633 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1985 11:48:02.027971
1986 11:48:02.028440 [DATLAT]
1987 11:48:02.029020 Freq=800, CH1 RK1
1988 11:48:02.029448
1989 11:48:02.031257 DATLAT Default: 0xa
1990 11:48:02.031830 0, 0xFFFF, sum = 0
1991 11:48:02.034792 1, 0xFFFF, sum = 0
1992 11:48:02.035274 2, 0xFFFF, sum = 0
1993 11:48:02.038250 3, 0xFFFF, sum = 0
1994 11:48:02.038718 4, 0xFFFF, sum = 0
1995 11:48:02.041671 5, 0xFFFF, sum = 0
1996 11:48:02.042031 6, 0xFFFF, sum = 0
1997 11:48:02.044659 7, 0xFFFF, sum = 0
1998 11:48:02.045075 8, 0xFFFF, sum = 0
1999 11:48:02.048106 9, 0x0, sum = 1
2000 11:48:02.048520 10, 0x0, sum = 2
2001 11:48:02.051636 11, 0x0, sum = 3
2002 11:48:02.052052 12, 0x0, sum = 4
2003 11:48:02.055179 best_step = 10
2004 11:48:02.055604
2005 11:48:02.055932 ==
2006 11:48:02.058337 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:48:02.061828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:48:02.062239 ==
2009 11:48:02.064705 RX Vref Scan: 0
2010 11:48:02.065127
2011 11:48:02.065455 RX Vref 0 -> 0, step: 1
2012 11:48:02.065760
2013 11:48:02.068518 RX Delay -95 -> 252, step: 8
2014 11:48:02.075263 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2015 11:48:02.078280 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2016 11:48:02.081674 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2017 11:48:02.085018 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2018 11:48:02.088580 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2019 11:48:02.091663 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2020 11:48:02.098207 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2021 11:48:02.101805 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2022 11:48:02.105304 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2023 11:48:02.108626 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2024 11:48:02.112321 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2025 11:48:02.118532 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2026 11:48:02.122184 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2027 11:48:02.125539 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2028 11:48:02.128743 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2029 11:48:02.132132 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2030 11:48:02.132569 ==
2031 11:48:02.135409 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 11:48:02.142018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 11:48:02.142455 ==
2034 11:48:02.142928 DQS Delay:
2035 11:48:02.145665 DQS0 = 0, DQS1 = 0
2036 11:48:02.146101 DQM Delay:
2037 11:48:02.146546 DQM0 = 80, DQM1 = 75
2038 11:48:02.148606 DQ Delay:
2039 11:48:02.152323 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2040 11:48:02.155830 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2041 11:48:02.158735 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2042 11:48:02.162620 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2043 11:48:02.163205
2044 11:48:02.163652
2045 11:48:02.169456 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2046 11:48:02.172428 CH1 RK1: MR19=606, MR18=1D29
2047 11:48:02.179370 CH1_RK1: MR19=0x606, MR18=0x1D29, DQSOSC=399, MR23=63, INC=92, DEC=61
2048 11:48:02.182102 [RxdqsGatingPostProcess] freq 800
2049 11:48:02.185614 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2050 11:48:02.189158 Pre-setting of DQS Precalculation
2051 11:48:02.195516 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2052 11:48:02.202445 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2053 11:48:02.209954 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2054 11:48:02.210392
2055 11:48:02.210834
2056 11:48:02.212156 [Calibration Summary] 1600 Mbps
2057 11:48:02.212594 CH 0, Rank 0
2058 11:48:02.215705 SW Impedance : PASS
2059 11:48:02.219093 DUTY Scan : NO K
2060 11:48:02.219528 ZQ Calibration : PASS
2061 11:48:02.222520 Jitter Meter : NO K
2062 11:48:02.222995 CBT Training : PASS
2063 11:48:02.225903 Write leveling : PASS
2064 11:48:02.229382 RX DQS gating : PASS
2065 11:48:02.229820 RX DQ/DQS(RDDQC) : PASS
2066 11:48:02.232666 TX DQ/DQS : PASS
2067 11:48:02.235836 RX DATLAT : PASS
2068 11:48:02.236144 RX DQ/DQS(Engine): PASS
2069 11:48:02.238915 TX OE : NO K
2070 11:48:02.239149 All Pass.
2071 11:48:02.239385
2072 11:48:02.242300 CH 0, Rank 1
2073 11:48:02.242533 SW Impedance : PASS
2074 11:48:02.245867 DUTY Scan : NO K
2075 11:48:02.249244 ZQ Calibration : PASS
2076 11:48:02.249493 Jitter Meter : NO K
2077 11:48:02.252708 CBT Training : PASS
2078 11:48:02.255494 Write leveling : PASS
2079 11:48:02.255781 RX DQS gating : PASS
2080 11:48:02.259162 RX DQ/DQS(RDDQC) : PASS
2081 11:48:02.259520 TX DQ/DQS : PASS
2082 11:48:02.262610 RX DATLAT : PASS
2083 11:48:02.265959 RX DQ/DQS(Engine): PASS
2084 11:48:02.266260 TX OE : NO K
2085 11:48:02.269170 All Pass.
2086 11:48:02.269391
2087 11:48:02.269576 CH 1, Rank 0
2088 11:48:02.272517 SW Impedance : PASS
2089 11:48:02.272739 DUTY Scan : NO K
2090 11:48:02.276253 ZQ Calibration : PASS
2091 11:48:02.279471 Jitter Meter : NO K
2092 11:48:02.279692 CBT Training : PASS
2093 11:48:02.283005 Write leveling : PASS
2094 11:48:02.286554 RX DQS gating : PASS
2095 11:48:02.286798 RX DQ/DQS(RDDQC) : PASS
2096 11:48:02.289277 TX DQ/DQS : PASS
2097 11:48:02.289511 RX DATLAT : PASS
2098 11:48:02.292835 RX DQ/DQS(Engine): PASS
2099 11:48:02.296030 TX OE : NO K
2100 11:48:02.296263 All Pass.
2101 11:48:02.296501
2102 11:48:02.296725 CH 1, Rank 1
2103 11:48:02.299647 SW Impedance : PASS
2104 11:48:02.302978 DUTY Scan : NO K
2105 11:48:02.303275 ZQ Calibration : PASS
2106 11:48:02.306511 Jitter Meter : NO K
2107 11:48:02.309962 CBT Training : PASS
2108 11:48:02.310435 Write leveling : PASS
2109 11:48:02.313165 RX DQS gating : PASS
2110 11:48:02.316342 RX DQ/DQS(RDDQC) : PASS
2111 11:48:02.316823 TX DQ/DQS : PASS
2112 11:48:02.319611 RX DATLAT : PASS
2113 11:48:02.323415 RX DQ/DQS(Engine): PASS
2114 11:48:02.323852 TX OE : NO K
2115 11:48:02.324336 All Pass.
2116 11:48:02.326317
2117 11:48:02.326749 DramC Write-DBI off
2118 11:48:02.330030 PER_BANK_REFRESH: Hybrid Mode
2119 11:48:02.330461 TX_TRACKING: ON
2120 11:48:02.332982 [GetDramInforAfterCalByMRR] Vendor 6.
2121 11:48:02.336963 [GetDramInforAfterCalByMRR] Revision 606.
2122 11:48:02.343219 [GetDramInforAfterCalByMRR] Revision 2 0.
2123 11:48:02.343651 MR0 0x3b3b
2124 11:48:02.344093 MR8 0x5151
2125 11:48:02.346619 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 11:48:02.347121
2127 11:48:02.349925 MR0 0x3b3b
2128 11:48:02.350354 MR8 0x5151
2129 11:48:02.353628 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2130 11:48:02.354061
2131 11:48:02.363491 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2132 11:48:02.366570 [FAST_K] Save calibration result to emmc
2133 11:48:02.370099 [FAST_K] Save calibration result to emmc
2134 11:48:02.373313 dram_init: config_dvfs: 1
2135 11:48:02.376589 dramc_set_vcore_voltage set vcore to 662500
2136 11:48:02.377024 Read voltage for 1200, 2
2137 11:48:02.380461 Vio18 = 0
2138 11:48:02.380892 Vcore = 662500
2139 11:48:02.381328 Vdram = 0
2140 11:48:02.383331 Vddq = 0
2141 11:48:02.383765 Vmddr = 0
2142 11:48:02.386794 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2143 11:48:02.393961 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2144 11:48:02.397177 MEM_TYPE=3, freq_sel=15
2145 11:48:02.400321 sv_algorithm_assistance_LP4_1600
2146 11:48:02.403918 ============ PULL DRAM RESETB DOWN ============
2147 11:48:02.406629 ========== PULL DRAM RESETB DOWN end =========
2148 11:48:02.410084 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2149 11:48:02.413389 ===================================
2150 11:48:02.417100 LPDDR4 DRAM CONFIGURATION
2151 11:48:02.420264 ===================================
2152 11:48:02.423846 EX_ROW_EN[0] = 0x0
2153 11:48:02.424386 EX_ROW_EN[1] = 0x0
2154 11:48:02.427230 LP4Y_EN = 0x0
2155 11:48:02.427768 WORK_FSP = 0x0
2156 11:48:02.430684 WL = 0x4
2157 11:48:02.431266 RL = 0x4
2158 11:48:02.433622 BL = 0x2
2159 11:48:02.434055 RPST = 0x0
2160 11:48:02.437222 RD_PRE = 0x0
2161 11:48:02.437769 WR_PRE = 0x1
2162 11:48:02.440365 WR_PST = 0x0
2163 11:48:02.440835 DBI_WR = 0x0
2164 11:48:02.443759 DBI_RD = 0x0
2165 11:48:02.444195 OTF = 0x1
2166 11:48:02.447048 ===================================
2167 11:48:02.450329 ===================================
2168 11:48:02.454364 ANA top config
2169 11:48:02.457220 ===================================
2170 11:48:02.460444 DLL_ASYNC_EN = 0
2171 11:48:02.460910 ALL_SLAVE_EN = 0
2172 11:48:02.463771 NEW_RANK_MODE = 1
2173 11:48:02.467422 DLL_IDLE_MODE = 1
2174 11:48:02.470736 LP45_APHY_COMB_EN = 1
2175 11:48:02.471205 TX_ODT_DIS = 1
2176 11:48:02.474487 NEW_8X_MODE = 1
2177 11:48:02.477691 ===================================
2178 11:48:02.480521 ===================================
2179 11:48:02.484224 data_rate = 2400
2180 11:48:02.487419 CKR = 1
2181 11:48:02.490915 DQ_P2S_RATIO = 8
2182 11:48:02.493851 ===================================
2183 11:48:02.494261 CA_P2S_RATIO = 8
2184 11:48:02.497571 DQ_CA_OPEN = 0
2185 11:48:02.500625 DQ_SEMI_OPEN = 0
2186 11:48:02.504223 CA_SEMI_OPEN = 0
2187 11:48:02.507549 CA_FULL_RATE = 0
2188 11:48:02.511052 DQ_CKDIV4_EN = 0
2189 11:48:02.511540 CA_CKDIV4_EN = 0
2190 11:48:02.514738 CA_PREDIV_EN = 0
2191 11:48:02.518023 PH8_DLY = 17
2192 11:48:02.521349 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2193 11:48:02.524438 DQ_AAMCK_DIV = 4
2194 11:48:02.524919 CA_AAMCK_DIV = 4
2195 11:48:02.527902 CA_ADMCK_DIV = 4
2196 11:48:02.531243 DQ_TRACK_CA_EN = 0
2197 11:48:02.534685 CA_PICK = 1200
2198 11:48:02.538305 CA_MCKIO = 1200
2199 11:48:02.541851 MCKIO_SEMI = 0
2200 11:48:02.544781 PLL_FREQ = 2366
2201 11:48:02.545329 DQ_UI_PI_RATIO = 32
2202 11:48:02.548084 CA_UI_PI_RATIO = 0
2203 11:48:02.551211 ===================================
2204 11:48:02.555141 ===================================
2205 11:48:02.558226 memory_type:LPDDR4
2206 11:48:02.561664 GP_NUM : 10
2207 11:48:02.562206 SRAM_EN : 1
2208 11:48:02.564668 MD32_EN : 0
2209 11:48:02.568233 ===================================
2210 11:48:02.568708 [ANA_INIT] >>>>>>>>>>>>>>
2211 11:48:02.571370 <<<<<< [CONFIGURE PHASE]: ANA_TX
2212 11:48:02.575077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2213 11:48:02.578763 ===================================
2214 11:48:02.581699 data_rate = 2400,PCW = 0X5b00
2215 11:48:02.584968 ===================================
2216 11:48:02.588354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2217 11:48:02.594965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2218 11:48:02.598601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2219 11:48:02.605503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2220 11:48:02.608461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2221 11:48:02.611926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2222 11:48:02.612352 [ANA_INIT] flow start
2223 11:48:02.615435 [ANA_INIT] PLL >>>>>>>>
2224 11:48:02.618620 [ANA_INIT] PLL <<<<<<<<
2225 11:48:02.619096 [ANA_INIT] MIDPI >>>>>>>>
2226 11:48:02.621898 [ANA_INIT] MIDPI <<<<<<<<
2227 11:48:02.625392 [ANA_INIT] DLL >>>>>>>>
2228 11:48:02.628861 [ANA_INIT] DLL <<<<<<<<
2229 11:48:02.629273 [ANA_INIT] flow end
2230 11:48:02.632244 ============ LP4 DIFF to SE enter ============
2231 11:48:02.638897 ============ LP4 DIFF to SE exit ============
2232 11:48:02.639334 [ANA_INIT] <<<<<<<<<<<<<
2233 11:48:02.641931 [Flow] Enable top DCM control >>>>>
2234 11:48:02.645482 [Flow] Enable top DCM control <<<<<
2235 11:48:02.648671 Enable DLL master slave shuffle
2236 11:48:02.655632 ==============================================================
2237 11:48:02.656063 Gating Mode config
2238 11:48:02.662249 ==============================================================
2239 11:48:02.662665 Config description:
2240 11:48:02.672050 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2241 11:48:02.678910 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2242 11:48:02.685914 SELPH_MODE 0: By rank 1: By Phase
2243 11:48:02.689018 ==============================================================
2244 11:48:02.692089 GAT_TRACK_EN = 1
2245 11:48:02.696152 RX_GATING_MODE = 2
2246 11:48:02.699405 RX_GATING_TRACK_MODE = 2
2247 11:48:02.702568 SELPH_MODE = 1
2248 11:48:02.705959 PICG_EARLY_EN = 1
2249 11:48:02.709092 VALID_LAT_VALUE = 1
2250 11:48:02.712502 ==============================================================
2251 11:48:02.715688 Enter into Gating configuration >>>>
2252 11:48:02.719143 Exit from Gating configuration <<<<
2253 11:48:02.722347 Enter into DVFS_PRE_config >>>>>
2254 11:48:02.735670 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2255 11:48:02.739216 Exit from DVFS_PRE_config <<<<<
2256 11:48:02.739396 Enter into PICG configuration >>>>
2257 11:48:02.742822 Exit from PICG configuration <<<<
2258 11:48:02.745998 [RX_INPUT] configuration >>>>>
2259 11:48:02.749396 [RX_INPUT] configuration <<<<<
2260 11:48:02.755828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2261 11:48:02.759071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2262 11:48:02.766155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 11:48:02.772926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 11:48:02.779053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2265 11:48:02.786130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2266 11:48:02.789767 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2267 11:48:02.792921 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2268 11:48:02.796073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2269 11:48:02.802676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2270 11:48:02.806262 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2271 11:48:02.809829 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 11:48:02.813069 ===================================
2273 11:48:02.816492 LPDDR4 DRAM CONFIGURATION
2274 11:48:02.819754 ===================================
2275 11:48:02.819836 EX_ROW_EN[0] = 0x0
2276 11:48:02.823086 EX_ROW_EN[1] = 0x0
2277 11:48:02.823174 LP4Y_EN = 0x0
2278 11:48:02.826418 WORK_FSP = 0x0
2279 11:48:02.826505 WL = 0x4
2280 11:48:02.829975 RL = 0x4
2281 11:48:02.830100 BL = 0x2
2282 11:48:02.832976 RPST = 0x0
2283 11:48:02.833079 RD_PRE = 0x0
2284 11:48:02.836525 WR_PRE = 0x1
2285 11:48:02.839920 WR_PST = 0x0
2286 11:48:02.840026 DBI_WR = 0x0
2287 11:48:02.842868 DBI_RD = 0x0
2288 11:48:02.842990 OTF = 0x1
2289 11:48:02.846150 ===================================
2290 11:48:02.850079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2291 11:48:02.852915 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2292 11:48:02.859891 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2293 11:48:02.863799 ===================================
2294 11:48:02.863977 LPDDR4 DRAM CONFIGURATION
2295 11:48:02.866925 ===================================
2296 11:48:02.870214 EX_ROW_EN[0] = 0x10
2297 11:48:02.873510 EX_ROW_EN[1] = 0x0
2298 11:48:02.873844 LP4Y_EN = 0x0
2299 11:48:02.876805 WORK_FSP = 0x0
2300 11:48:02.877053 WL = 0x4
2301 11:48:02.880280 RL = 0x4
2302 11:48:02.880693 BL = 0x2
2303 11:48:02.883803 RPST = 0x0
2304 11:48:02.884238 RD_PRE = 0x0
2305 11:48:02.886903 WR_PRE = 0x1
2306 11:48:02.887360 WR_PST = 0x0
2307 11:48:02.890525 DBI_WR = 0x0
2308 11:48:02.891123 DBI_RD = 0x0
2309 11:48:02.893550 OTF = 0x1
2310 11:48:02.897034 ===================================
2311 11:48:02.904006 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2312 11:48:02.904467 ==
2313 11:48:02.907362 Dram Type= 6, Freq= 0, CH_0, rank 0
2314 11:48:02.911009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2315 11:48:02.911464 ==
2316 11:48:02.914275 [Duty_Offset_Calibration]
2317 11:48:02.914945 B0:2 B1:-1 CA:1
2318 11:48:02.915322
2319 11:48:02.917458 [DutyScan_Calibration_Flow] k_type=0
2320 11:48:02.926390
2321 11:48:02.926985 ==CLK 0==
2322 11:48:02.929698 Final CLK duty delay cell = -4
2323 11:48:02.933480 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2324 11:48:02.936919 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2325 11:48:02.940262 [-4] AVG Duty = 4953%(X100)
2326 11:48:02.940844
2327 11:48:02.943459 CH0 CLK Duty spec in!! Max-Min= 156%
2328 11:48:02.946643 [DutyScan_Calibration_Flow] ====Done====
2329 11:48:02.947263
2330 11:48:02.950343 [DutyScan_Calibration_Flow] k_type=1
2331 11:48:02.964417
2332 11:48:02.964944 ==DQS 0 ==
2333 11:48:02.967526 Final DQS duty delay cell = -4
2334 11:48:02.970910 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2335 11:48:02.974612 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2336 11:48:02.978098 [-4] AVG Duty = 4938%(X100)
2337 11:48:02.978535
2338 11:48:02.979012 ==DQS 1 ==
2339 11:48:02.981154 Final DQS duty delay cell = -4
2340 11:48:02.984465 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2341 11:48:02.987906 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2342 11:48:02.991299 [-4] AVG Duty = 5062%(X100)
2343 11:48:02.991798
2344 11:48:02.994775 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2345 11:48:02.995352
2346 11:48:02.997934 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2347 11:48:03.001181 [DutyScan_Calibration_Flow] ====Done====
2348 11:48:03.001591
2349 11:48:03.004294 [DutyScan_Calibration_Flow] k_type=3
2350 11:48:03.021285
2351 11:48:03.021366 ==DQM 0 ==
2352 11:48:03.024464 Final DQM duty delay cell = 0
2353 11:48:03.028297 [0] MAX Duty = 5000%(X100), DQS PI = 54
2354 11:48:03.031553 [0] MIN Duty = 4907%(X100), DQS PI = 2
2355 11:48:03.031626 [0] AVG Duty = 4953%(X100)
2356 11:48:03.035003
2357 11:48:03.035104 ==DQM 1 ==
2358 11:48:03.037856 Final DQM duty delay cell = 0
2359 11:48:03.041597 [0] MAX Duty = 5156%(X100), DQS PI = 62
2360 11:48:03.044886 [0] MIN Duty = 4969%(X100), DQS PI = 10
2361 11:48:03.044956 [0] AVG Duty = 5062%(X100)
2362 11:48:03.045017
2363 11:48:03.048170 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2364 11:48:03.051234
2365 11:48:03.054709 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2366 11:48:03.057909 [DutyScan_Calibration_Flow] ====Done====
2367 11:48:03.057989
2368 11:48:03.061152 [DutyScan_Calibration_Flow] k_type=2
2369 11:48:03.077277
2370 11:48:03.077354 ==DQ 0 ==
2371 11:48:03.080396 Final DQ duty delay cell = -4
2372 11:48:03.083598 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2373 11:48:03.087070 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2374 11:48:03.090488 [-4] AVG Duty = 4969%(X100)
2375 11:48:03.090593
2376 11:48:03.090682 ==DQ 1 ==
2377 11:48:03.094034 Final DQ duty delay cell = 0
2378 11:48:03.097007 [0] MAX Duty = 5031%(X100), DQS PI = 18
2379 11:48:03.100493 [0] MIN Duty = 4907%(X100), DQS PI = 46
2380 11:48:03.100562 [0] AVG Duty = 4969%(X100)
2381 11:48:03.100621
2382 11:48:03.103752 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2383 11:48:03.107209
2384 11:48:03.110517 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2385 11:48:03.114039 [DutyScan_Calibration_Flow] ====Done====
2386 11:48:03.114111 ==
2387 11:48:03.117344 Dram Type= 6, Freq= 0, CH_1, rank 0
2388 11:48:03.120712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2389 11:48:03.120781 ==
2390 11:48:03.124245 [Duty_Offset_Calibration]
2391 11:48:03.124313 B0:1 B1:1 CA:2
2392 11:48:03.124372
2393 11:48:03.127294 [DutyScan_Calibration_Flow] k_type=0
2394 11:48:03.137585
2395 11:48:03.137659 ==CLK 0==
2396 11:48:03.140799 Final CLK duty delay cell = 0
2397 11:48:03.143753 [0] MAX Duty = 5156%(X100), DQS PI = 24
2398 11:48:03.147512 [0] MIN Duty = 4938%(X100), DQS PI = 46
2399 11:48:03.147589 [0] AVG Duty = 5047%(X100)
2400 11:48:03.147650
2401 11:48:03.150563 CH1 CLK Duty spec in!! Max-Min= 218%
2402 11:48:03.157749 [DutyScan_Calibration_Flow] ====Done====
2403 11:48:03.157823
2404 11:48:03.160591 [DutyScan_Calibration_Flow] k_type=1
2405 11:48:03.176297
2406 11:48:03.176380 ==DQS 0 ==
2407 11:48:03.180035 Final DQS duty delay cell = 0
2408 11:48:03.183085 [0] MAX Duty = 5031%(X100), DQS PI = 18
2409 11:48:03.186614 [0] MIN Duty = 4844%(X100), DQS PI = 50
2410 11:48:03.186694 [0] AVG Duty = 4937%(X100)
2411 11:48:03.189901
2412 11:48:03.189990 ==DQS 1 ==
2413 11:48:03.193130 Final DQS duty delay cell = 0
2414 11:48:03.196463 [0] MAX Duty = 5031%(X100), DQS PI = 36
2415 11:48:03.199942 [0] MIN Duty = 4907%(X100), DQS PI = 8
2416 11:48:03.200016 [0] AVG Duty = 4969%(X100)
2417 11:48:03.200079
2418 11:48:03.206573 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2419 11:48:03.206675
2420 11:48:03.210169 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2421 11:48:03.213622 [DutyScan_Calibration_Flow] ====Done====
2422 11:48:03.213696
2423 11:48:03.217084 [DutyScan_Calibration_Flow] k_type=3
2424 11:48:03.233170
2425 11:48:03.233244 ==DQM 0 ==
2426 11:48:03.236401 Final DQM duty delay cell = 0
2427 11:48:03.240027 [0] MAX Duty = 5093%(X100), DQS PI = 18
2428 11:48:03.243615 [0] MIN Duty = 4875%(X100), DQS PI = 48
2429 11:48:03.243684 [0] AVG Duty = 4984%(X100)
2430 11:48:03.246573
2431 11:48:03.246640 ==DQM 1 ==
2432 11:48:03.250079 Final DQM duty delay cell = 0
2433 11:48:03.253153 [0] MAX Duty = 5125%(X100), DQS PI = 0
2434 11:48:03.256660 [0] MIN Duty = 4969%(X100), DQS PI = 4
2435 11:48:03.256732 [0] AVG Duty = 5047%(X100)
2436 11:48:03.256793
2437 11:48:03.259925 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2438 11:48:03.263441
2439 11:48:03.266976 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2440 11:48:03.270138 [DutyScan_Calibration_Flow] ====Done====
2441 11:48:03.270239
2442 11:48:03.273179 [DutyScan_Calibration_Flow] k_type=2
2443 11:48:03.289916
2444 11:48:03.290002 ==DQ 0 ==
2445 11:48:03.293083 Final DQ duty delay cell = 0
2446 11:48:03.296302 [0] MAX Duty = 5124%(X100), DQS PI = 18
2447 11:48:03.299522 [0] MIN Duty = 4907%(X100), DQS PI = 50
2448 11:48:03.299616 [0] AVG Duty = 5015%(X100)
2449 11:48:03.299694
2450 11:48:03.303066 ==DQ 1 ==
2451 11:48:03.306694 Final DQ duty delay cell = 0
2452 11:48:03.309602 [0] MAX Duty = 5093%(X100), DQS PI = 40
2453 11:48:03.313156 [0] MIN Duty = 5000%(X100), DQS PI = 50
2454 11:48:03.313275 [0] AVG Duty = 5046%(X100)
2455 11:48:03.313391
2456 11:48:03.316656 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2457 11:48:03.316776
2458 11:48:03.320151 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2459 11:48:03.323278 [DutyScan_Calibration_Flow] ====Done====
2460 11:48:03.328513 nWR fixed to 30
2461 11:48:03.331839 [ModeRegInit_LP4] CH0 RK0
2462 11:48:03.332035 [ModeRegInit_LP4] CH0 RK1
2463 11:48:03.335784 [ModeRegInit_LP4] CH1 RK0
2464 11:48:03.338684 [ModeRegInit_LP4] CH1 RK1
2465 11:48:03.338995 match AC timing 7
2466 11:48:03.345320 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2467 11:48:03.348806 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2468 11:48:03.352352 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2469 11:48:03.359379 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2470 11:48:03.362631 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2471 11:48:03.363092 ==
2472 11:48:03.365967 Dram Type= 6, Freq= 0, CH_0, rank 0
2473 11:48:03.369249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 11:48:03.369702 ==
2475 11:48:03.376063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 11:48:03.382800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2477 11:48:03.389794 [CA 0] Center 40 (10~71) winsize 62
2478 11:48:03.393270 [CA 1] Center 39 (9~70) winsize 62
2479 11:48:03.396407 [CA 2] Center 36 (6~67) winsize 62
2480 11:48:03.400344 [CA 3] Center 36 (5~67) winsize 63
2481 11:48:03.403756 [CA 4] Center 35 (5~65) winsize 61
2482 11:48:03.406474 [CA 5] Center 34 (4~64) winsize 61
2483 11:48:03.406947
2484 11:48:03.410145 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2485 11:48:03.410579
2486 11:48:03.413049 [CATrainingPosCal] consider 1 rank data
2487 11:48:03.417257 u2DelayCellTimex100 = 270/100 ps
2488 11:48:03.420367 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2489 11:48:03.423405 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2490 11:48:03.430134 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2491 11:48:03.433081 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2492 11:48:03.436682 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2493 11:48:03.440299 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2494 11:48:03.440733
2495 11:48:03.443385 CA PerBit enable=1, Macro0, CA PI delay=34
2496 11:48:03.443823
2497 11:48:03.446981 [CBTSetCACLKResult] CA Dly = 34
2498 11:48:03.447416 CS Dly: 7 (0~38)
2499 11:48:03.447852 ==
2500 11:48:03.450003 Dram Type= 6, Freq= 0, CH_0, rank 1
2501 11:48:03.456371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 11:48:03.456456 ==
2503 11:48:03.459917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2504 11:48:03.465900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2505 11:48:03.476020 [CA 0] Center 40 (10~70) winsize 61
2506 11:48:03.478820 [CA 1] Center 39 (9~70) winsize 62
2507 11:48:03.482026 [CA 2] Center 36 (6~67) winsize 62
2508 11:48:03.485431 [CA 3] Center 35 (5~66) winsize 62
2509 11:48:03.488840 [CA 4] Center 34 (4~65) winsize 62
2510 11:48:03.492235 [CA 5] Center 34 (4~64) winsize 61
2511 11:48:03.492316
2512 11:48:03.495861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2513 11:48:03.495945
2514 11:48:03.498938 [CATrainingPosCal] consider 2 rank data
2515 11:48:03.502226 u2DelayCellTimex100 = 270/100 ps
2516 11:48:03.505634 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2517 11:48:03.509030 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2518 11:48:03.515722 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2519 11:48:03.518818 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2520 11:48:03.522271 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2521 11:48:03.525980 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2522 11:48:03.526077
2523 11:48:03.529381 CA PerBit enable=1, Macro0, CA PI delay=34
2524 11:48:03.529465
2525 11:48:03.532290 [CBTSetCACLKResult] CA Dly = 34
2526 11:48:03.532375 CS Dly: 8 (0~41)
2527 11:48:03.532461
2528 11:48:03.536157 ----->DramcWriteLeveling(PI) begin...
2529 11:48:03.536242 ==
2530 11:48:03.539085 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 11:48:03.546410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 11:48:03.546496 ==
2533 11:48:03.549444 Write leveling (Byte 0): 32 => 32
2534 11:48:03.552598 Write leveling (Byte 1): 28 => 28
2535 11:48:03.552682 DramcWriteLeveling(PI) end<-----
2536 11:48:03.552767
2537 11:48:03.555906 ==
2538 11:48:03.559132 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 11:48:03.562617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 11:48:03.562702 ==
2541 11:48:03.565932 [Gating] SW mode calibration
2542 11:48:03.572681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2543 11:48:03.576238 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2544 11:48:03.582976 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 11:48:03.586175 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2546 11:48:03.589632 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 11:48:03.595881 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 11:48:03.599603 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 11:48:03.602649 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 11:48:03.609294 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 11:48:03.612911 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 11:48:03.616409 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2553 11:48:03.620128 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
2554 11:48:03.626985 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 11:48:03.630101 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 11:48:03.634021 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 11:48:03.640255 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 11:48:03.643447 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 11:48:03.647282 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 11:48:03.653760 1 1 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2561 11:48:03.656913 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2562 11:48:03.660531 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 11:48:03.664065 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 11:48:03.670127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 11:48:03.673900 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 11:48:03.676730 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 11:48:03.683577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 11:48:03.687004 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2569 11:48:03.690533 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2570 11:48:03.696828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:48:03.700278 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:48:03.703634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:48:03.710744 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 11:48:03.713763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 11:48:03.717029 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 11:48:03.720709 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 11:48:03.727315 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 11:48:03.730731 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 11:48:03.733899 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 11:48:03.740795 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 11:48:03.745378 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 11:48:03.747838 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 11:48:03.754470 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2584 11:48:03.757878 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2585 11:48:03.761219 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 11:48:03.764656 Total UI for P1: 0, mck2ui 16
2587 11:48:03.767702 best dqsien dly found for B0: ( 1, 3, 30)
2588 11:48:03.771246 Total UI for P1: 0, mck2ui 16
2589 11:48:03.774556 best dqsien dly found for B1: ( 1, 4, 0)
2590 11:48:03.777909 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2591 11:48:03.781581 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2592 11:48:03.782005
2593 11:48:03.785339 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2594 11:48:03.788122 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2595 11:48:03.791821 [Gating] SW calibration Done
2596 11:48:03.792257 ==
2597 11:48:03.795321 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 11:48:03.798428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 11:48:03.801541 ==
2600 11:48:03.801977 RX Vref Scan: 0
2601 11:48:03.802418
2602 11:48:03.804943 RX Vref 0 -> 0, step: 1
2603 11:48:03.805377
2604 11:48:03.805814 RX Delay -40 -> 252, step: 8
2605 11:48:03.811769 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2606 11:48:03.815314 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2607 11:48:03.819049 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2608 11:48:03.822233 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2609 11:48:03.825180 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2610 11:48:03.831714 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2611 11:48:03.835462 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2612 11:48:03.838636 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2613 11:48:03.842166 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2614 11:48:03.845363 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2615 11:48:03.848395 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2616 11:48:03.855317 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2617 11:48:03.858811 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2618 11:48:03.862076 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2619 11:48:03.865596 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2620 11:48:03.868572 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2621 11:48:03.871972 ==
2622 11:48:03.875692 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 11:48:03.878899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 11:48:03.878998 ==
2625 11:48:03.879084 DQS Delay:
2626 11:48:03.881922 DQS0 = 0, DQS1 = 0
2627 11:48:03.882007 DQM Delay:
2628 11:48:03.885742 DQM0 = 115, DQM1 = 107
2629 11:48:03.885827 DQ Delay:
2630 11:48:03.889578 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2631 11:48:03.892219 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2632 11:48:03.895669 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2633 11:48:03.898773 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2634 11:48:03.898917
2635 11:48:03.899004
2636 11:48:03.899085 ==
2637 11:48:03.902154 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:48:03.906070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:48:03.908708 ==
2640 11:48:03.908797
2641 11:48:03.908887
2642 11:48:03.908974 TX Vref Scan disable
2643 11:48:03.912029 == TX Byte 0 ==
2644 11:48:03.915790 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 11:48:03.919501 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 11:48:03.922973 == TX Byte 1 ==
2647 11:48:03.926498 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2648 11:48:03.929253 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2649 11:48:03.929685 ==
2650 11:48:03.933308 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:48:03.939336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:48:03.939777 ==
2653 11:48:03.950810 TX Vref=22, minBit 7, minWin=24, winSum=415
2654 11:48:03.953845 TX Vref=24, minBit 1, minWin=24, winSum=424
2655 11:48:03.957564 TX Vref=26, minBit 0, minWin=26, winSum=424
2656 11:48:03.961370 TX Vref=28, minBit 0, minWin=26, winSum=427
2657 11:48:03.963972 TX Vref=30, minBit 0, minWin=26, winSum=429
2658 11:48:03.967331 TX Vref=32, minBit 0, minWin=26, winSum=431
2659 11:48:03.974082 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 32
2660 11:48:03.974517
2661 11:48:03.977702 Final TX Range 1 Vref 32
2662 11:48:03.978136
2663 11:48:03.978578 ==
2664 11:48:03.980613 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 11:48:03.984091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 11:48:03.984526 ==
2667 11:48:03.984966
2668 11:48:03.985380
2669 11:48:03.987565 TX Vref Scan disable
2670 11:48:03.990712 == TX Byte 0 ==
2671 11:48:03.994039 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2672 11:48:03.997535 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2673 11:48:04.001078 == TX Byte 1 ==
2674 11:48:04.004329 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2675 11:48:04.007877 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2676 11:48:04.008435
2677 11:48:04.010742 [DATLAT]
2678 11:48:04.011228 Freq=1200, CH0 RK0
2679 11:48:04.011565
2680 11:48:04.014248 DATLAT Default: 0xd
2681 11:48:04.014667 0, 0xFFFF, sum = 0
2682 11:48:04.017343 1, 0xFFFF, sum = 0
2683 11:48:04.017917 2, 0xFFFF, sum = 0
2684 11:48:04.020884 3, 0xFFFF, sum = 0
2685 11:48:04.021313 4, 0xFFFF, sum = 0
2686 11:48:04.024558 5, 0xFFFF, sum = 0
2687 11:48:04.024983 6, 0xFFFF, sum = 0
2688 11:48:04.027629 7, 0xFFFF, sum = 0
2689 11:48:04.028051 8, 0xFFFF, sum = 0
2690 11:48:04.031161 9, 0xFFFF, sum = 0
2691 11:48:04.031589 10, 0xFFFF, sum = 0
2692 11:48:04.034326 11, 0xFFFF, sum = 0
2693 11:48:04.034753 12, 0x0, sum = 1
2694 11:48:04.037589 13, 0x0, sum = 2
2695 11:48:04.038016 14, 0x0, sum = 3
2696 11:48:04.041182 15, 0x0, sum = 4
2697 11:48:04.041609 best_step = 13
2698 11:48:04.041943
2699 11:48:04.042252 ==
2700 11:48:04.044554 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 11:48:04.048082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 11:48:04.051718 ==
2703 11:48:04.052251 RX Vref Scan: 1
2704 11:48:04.052592
2705 11:48:04.054394 Set Vref Range= 32 -> 127
2706 11:48:04.054814
2707 11:48:04.058118 RX Vref 32 -> 127, step: 1
2708 11:48:04.058539
2709 11:48:04.058897 RX Delay -21 -> 252, step: 4
2710 11:48:04.059217
2711 11:48:04.061702 Set Vref, RX VrefLevel [Byte0]: 32
2712 11:48:04.064514 [Byte1]: 32
2713 11:48:04.068581
2714 11:48:04.069000 Set Vref, RX VrefLevel [Byte0]: 33
2715 11:48:04.072192 [Byte1]: 33
2716 11:48:04.076375
2717 11:48:04.076829 Set Vref, RX VrefLevel [Byte0]: 34
2718 11:48:04.080096 [Byte1]: 34
2719 11:48:04.084528
2720 11:48:04.084946 Set Vref, RX VrefLevel [Byte0]: 35
2721 11:48:04.088090 [Byte1]: 35
2722 11:48:04.092519
2723 11:48:04.092938 Set Vref, RX VrefLevel [Byte0]: 36
2724 11:48:04.095817 [Byte1]: 36
2725 11:48:04.100545
2726 11:48:04.100969 Set Vref, RX VrefLevel [Byte0]: 37
2727 11:48:04.103773 [Byte1]: 37
2728 11:48:04.108829
2729 11:48:04.109344 Set Vref, RX VrefLevel [Byte0]: 38
2730 11:48:04.111875 [Byte1]: 38
2731 11:48:04.116215
2732 11:48:04.116636 Set Vref, RX VrefLevel [Byte0]: 39
2733 11:48:04.120024 [Byte1]: 39
2734 11:48:04.124265
2735 11:48:04.124685 Set Vref, RX VrefLevel [Byte0]: 40
2736 11:48:04.127699 [Byte1]: 40
2737 11:48:04.132152
2738 11:48:04.132572 Set Vref, RX VrefLevel [Byte0]: 41
2739 11:48:04.135479 [Byte1]: 41
2740 11:48:04.140420
2741 11:48:04.140929 Set Vref, RX VrefLevel [Byte0]: 42
2742 11:48:04.143324 [Byte1]: 42
2743 11:48:04.148549
2744 11:48:04.148968 Set Vref, RX VrefLevel [Byte0]: 43
2745 11:48:04.151470 [Byte1]: 43
2746 11:48:04.155995
2747 11:48:04.156412 Set Vref, RX VrefLevel [Byte0]: 44
2748 11:48:04.159056 [Byte1]: 44
2749 11:48:04.164009
2750 11:48:04.164426 Set Vref, RX VrefLevel [Byte0]: 45
2751 11:48:04.167391 [Byte1]: 45
2752 11:48:04.171624
2753 11:48:04.172040 Set Vref, RX VrefLevel [Byte0]: 46
2754 11:48:04.175272 [Byte1]: 46
2755 11:48:04.179839
2756 11:48:04.180255 Set Vref, RX VrefLevel [Byte0]: 47
2757 11:48:04.183280 [Byte1]: 47
2758 11:48:04.187798
2759 11:48:04.188214 Set Vref, RX VrefLevel [Byte0]: 48
2760 11:48:04.190922 [Byte1]: 48
2761 11:48:04.195367
2762 11:48:04.195788 Set Vref, RX VrefLevel [Byte0]: 49
2763 11:48:04.198796 [Byte1]: 49
2764 11:48:04.203295
2765 11:48:04.203739 Set Vref, RX VrefLevel [Byte0]: 50
2766 11:48:04.207142 [Byte1]: 50
2767 11:48:04.211443
2768 11:48:04.211859 Set Vref, RX VrefLevel [Byte0]: 51
2769 11:48:04.214857 [Byte1]: 51
2770 11:48:04.219477
2771 11:48:04.219896 Set Vref, RX VrefLevel [Byte0]: 52
2772 11:48:04.222519 [Byte1]: 52
2773 11:48:04.227773
2774 11:48:04.228286 Set Vref, RX VrefLevel [Byte0]: 53
2775 11:48:04.231071 [Byte1]: 53
2776 11:48:04.235471
2777 11:48:04.235888 Set Vref, RX VrefLevel [Byte0]: 54
2778 11:48:04.238750 [Byte1]: 54
2779 11:48:04.243087
2780 11:48:04.243615 Set Vref, RX VrefLevel [Byte0]: 55
2781 11:48:04.246654 [Byte1]: 55
2782 11:48:04.250988
2783 11:48:04.251514 Set Vref, RX VrefLevel [Byte0]: 56
2784 11:48:04.254404 [Byte1]: 56
2785 11:48:04.259074
2786 11:48:04.259491 Set Vref, RX VrefLevel [Byte0]: 57
2787 11:48:04.262406 [Byte1]: 57
2788 11:48:04.267088
2789 11:48:04.267505 Set Vref, RX VrefLevel [Byte0]: 58
2790 11:48:04.270336 [Byte1]: 58
2791 11:48:04.275098
2792 11:48:04.275517 Set Vref, RX VrefLevel [Byte0]: 59
2793 11:48:04.278008 [Byte1]: 59
2794 11:48:04.282741
2795 11:48:04.283244 Set Vref, RX VrefLevel [Byte0]: 60
2796 11:48:04.286419 [Byte1]: 60
2797 11:48:04.290959
2798 11:48:04.291381 Set Vref, RX VrefLevel [Byte0]: 61
2799 11:48:04.294258 [Byte1]: 61
2800 11:48:04.298642
2801 11:48:04.299135 Set Vref, RX VrefLevel [Byte0]: 62
2802 11:48:04.301851 [Byte1]: 62
2803 11:48:04.306695
2804 11:48:04.307163 Set Vref, RX VrefLevel [Byte0]: 63
2805 11:48:04.310122 [Byte1]: 63
2806 11:48:04.314983
2807 11:48:04.315403 Set Vref, RX VrefLevel [Byte0]: 64
2808 11:48:04.318107 [Byte1]: 64
2809 11:48:04.322519
2810 11:48:04.322993 Set Vref, RX VrefLevel [Byte0]: 65
2811 11:48:04.325735 [Byte1]: 65
2812 11:48:04.330539
2813 11:48:04.330991 Set Vref, RX VrefLevel [Byte0]: 66
2814 11:48:04.333775 [Byte1]: 66
2815 11:48:04.339014
2816 11:48:04.339520 Set Vref, RX VrefLevel [Byte0]: 67
2817 11:48:04.341988 [Byte1]: 67
2818 11:48:04.346498
2819 11:48:04.347054 Set Vref, RX VrefLevel [Byte0]: 68
2820 11:48:04.350035 [Byte1]: 68
2821 11:48:04.354259
2822 11:48:04.354773 Final RX Vref Byte 0 = 53 to rank0
2823 11:48:04.357814 Final RX Vref Byte 1 = 51 to rank0
2824 11:48:04.361003 Final RX Vref Byte 0 = 53 to rank1
2825 11:48:04.364466 Final RX Vref Byte 1 = 51 to rank1==
2826 11:48:04.368102 Dram Type= 6, Freq= 0, CH_0, rank 0
2827 11:48:04.374240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 11:48:04.374979 ==
2829 11:48:04.375338 DQS Delay:
2830 11:48:04.375657 DQS0 = 0, DQS1 = 0
2831 11:48:04.377273 DQM Delay:
2832 11:48:04.377690 DQM0 = 115, DQM1 = 105
2833 11:48:04.380502 DQ Delay:
2834 11:48:04.383786 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2835 11:48:04.387479 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2836 11:48:04.391153 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2837 11:48:04.394164 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2838 11:48:04.394251
2839 11:48:04.394320
2840 11:48:04.400430 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2841 11:48:04.404094 CH0 RK0: MR19=403, MR18=1F1
2842 11:48:04.410931 CH0_RK0: MR19=0x403, MR18=0x1F1, DQSOSC=409, MR23=63, INC=39, DEC=26
2843 11:48:04.411408
2844 11:48:04.414218 ----->DramcWriteLeveling(PI) begin...
2845 11:48:04.414649 ==
2846 11:48:04.417803 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 11:48:04.421705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 11:48:04.422129 ==
2849 11:48:04.424452 Write leveling (Byte 0): 30 => 30
2850 11:48:04.427833 Write leveling (Byte 1): 29 => 29
2851 11:48:04.431210 DramcWriteLeveling(PI) end<-----
2852 11:48:04.431678
2853 11:48:04.432018 ==
2854 11:48:04.434770 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 11:48:04.437884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 11:48:04.438308 ==
2857 11:48:04.441451 [Gating] SW mode calibration
2858 11:48:04.448268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2859 11:48:04.454428 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2860 11:48:04.457941 0 15 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
2861 11:48:04.461204 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2862 11:48:04.467845 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 11:48:04.471513 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 11:48:04.474747 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 11:48:04.481454 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 11:48:04.485021 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2867 11:48:04.488205 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2868 11:48:04.494845 1 0 0 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
2869 11:48:04.498305 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2870 11:48:04.501625 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 11:48:04.508347 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 11:48:04.511730 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 11:48:04.515108 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 11:48:04.521635 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2875 11:48:04.525207 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2876 11:48:04.528425 1 1 0 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
2877 11:48:04.532266 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 11:48:04.538620 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 11:48:04.542028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 11:48:04.545249 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 11:48:04.552160 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 11:48:04.555668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 11:48:04.558727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2884 11:48:04.565724 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 11:48:04.569187 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:48:04.571885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:48:04.578805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:48:04.582235 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:48:04.585474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:48:04.589011 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:48:04.595583 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 11:48:04.598934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 11:48:04.602702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 11:48:04.609104 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 11:48:04.612529 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 11:48:04.616113 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:48:04.622452 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:48:04.625498 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 11:48:04.629108 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2900 11:48:04.635614 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2901 11:48:04.636038 Total UI for P1: 0, mck2ui 16
2902 11:48:04.639425 best dqsien dly found for B0: ( 1, 3, 26)
2903 11:48:04.645866 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 11:48:04.649068 Total UI for P1: 0, mck2ui 16
2905 11:48:04.652692 best dqsien dly found for B1: ( 1, 4, 0)
2906 11:48:04.656140 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2907 11:48:04.659243 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2908 11:48:04.659669
2909 11:48:04.662852 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2910 11:48:04.666166 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2911 11:48:04.670067 [Gating] SW calibration Done
2912 11:48:04.670602 ==
2913 11:48:04.672913 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 11:48:04.676756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 11:48:04.677287 ==
2916 11:48:04.679556 RX Vref Scan: 0
2917 11:48:04.680004
2918 11:48:04.680336 RX Vref 0 -> 0, step: 1
2919 11:48:04.680643
2920 11:48:04.682630 RX Delay -40 -> 252, step: 8
2921 11:48:04.686409 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2922 11:48:04.693559 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2923 11:48:04.696784 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2924 11:48:04.699684 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2925 11:48:04.703463 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 11:48:04.706625 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2927 11:48:04.710259 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2928 11:48:04.716899 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 11:48:04.719993 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2930 11:48:04.723513 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2931 11:48:04.726917 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 11:48:04.729710 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2933 11:48:04.736964 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2934 11:48:04.739892 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2935 11:48:04.743718 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2936 11:48:04.746533 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2937 11:48:04.747285 ==
2938 11:48:04.749823 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 11:48:04.753694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 11:48:04.756965 ==
2941 11:48:04.757386 DQS Delay:
2942 11:48:04.757722 DQS0 = 0, DQS1 = 0
2943 11:48:04.759983 DQM Delay:
2944 11:48:04.760402 DQM0 = 115, DQM1 = 106
2945 11:48:04.763257 DQ Delay:
2946 11:48:04.766929 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2947 11:48:04.769949 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2948 11:48:04.773662 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2949 11:48:04.776853 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2950 11:48:04.777273
2951 11:48:04.777623
2952 11:48:04.777957 ==
2953 11:48:04.780239 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 11:48:04.783758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 11:48:04.784395 ==
2956 11:48:04.784925
2957 11:48:04.785384
2958 11:48:04.786930 TX Vref Scan disable
2959 11:48:04.790209 == TX Byte 0 ==
2960 11:48:04.793564 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2961 11:48:04.796873 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2962 11:48:04.797297 == TX Byte 1 ==
2963 11:48:04.804222 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2964 11:48:04.807557 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2965 11:48:04.807979 ==
2966 11:48:04.810351 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 11:48:04.814011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 11:48:04.814435 ==
2969 11:48:04.826986 TX Vref=22, minBit 1, minWin=25, winSum=422
2970 11:48:04.830759 TX Vref=24, minBit 1, minWin=26, winSum=433
2971 11:48:04.834009 TX Vref=26, minBit 2, minWin=26, winSum=433
2972 11:48:04.837511 TX Vref=28, minBit 5, minWin=26, winSum=435
2973 11:48:04.840262 TX Vref=30, minBit 5, minWin=26, winSum=436
2974 11:48:04.843554 TX Vref=32, minBit 5, minWin=26, winSum=437
2975 11:48:04.850436 [TxChooseVref] Worse bit 5, Min win 26, Win sum 437, Final Vref 32
2976 11:48:04.851026
2977 11:48:04.853756 Final TX Range 1 Vref 32
2978 11:48:04.854218
2979 11:48:04.854583 ==
2980 11:48:04.857180 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 11:48:04.860490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 11:48:04.860916 ==
2983 11:48:04.861249
2984 11:48:04.861558
2985 11:48:04.863445 TX Vref Scan disable
2986 11:48:04.867170 == TX Byte 0 ==
2987 11:48:04.870750 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2988 11:48:04.873893 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2989 11:48:04.877339 == TX Byte 1 ==
2990 11:48:04.880520 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2991 11:48:04.884147 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2992 11:48:04.884625
2993 11:48:04.887652 [DATLAT]
2994 11:48:04.888106 Freq=1200, CH0 RK1
2995 11:48:04.888452
2996 11:48:04.890819 DATLAT Default: 0xd
2997 11:48:04.891268 0, 0xFFFF, sum = 0
2998 11:48:04.894122 1, 0xFFFF, sum = 0
2999 11:48:04.894661 2, 0xFFFF, sum = 0
3000 11:48:04.897205 3, 0xFFFF, sum = 0
3001 11:48:04.897771 4, 0xFFFF, sum = 0
3002 11:48:04.900134 5, 0xFFFF, sum = 0
3003 11:48:04.900604 6, 0xFFFF, sum = 0
3004 11:48:04.903765 7, 0xFFFF, sum = 0
3005 11:48:04.904232 8, 0xFFFF, sum = 0
3006 11:48:04.907577 9, 0xFFFF, sum = 0
3007 11:48:04.908004 10, 0xFFFF, sum = 0
3008 11:48:04.910772 11, 0xFFFF, sum = 0
3009 11:48:04.911226 12, 0x0, sum = 1
3010 11:48:04.913585 13, 0x0, sum = 2
3011 11:48:04.914011 14, 0x0, sum = 3
3012 11:48:04.917414 15, 0x0, sum = 4
3013 11:48:04.917942 best_step = 13
3014 11:48:04.918273
3015 11:48:04.918577 ==
3016 11:48:04.920801 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 11:48:04.927282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 11:48:04.927803 ==
3019 11:48:04.928140 RX Vref Scan: 0
3020 11:48:04.928446
3021 11:48:04.930509 RX Vref 0 -> 0, step: 1
3022 11:48:04.930994
3023 11:48:04.933880 RX Delay -21 -> 252, step: 4
3024 11:48:04.937506 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3025 11:48:04.940693 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3026 11:48:04.948088 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3027 11:48:04.950687 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3028 11:48:04.954096 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 11:48:04.957898 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3030 11:48:04.960848 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3031 11:48:04.964266 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3032 11:48:04.971084 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3033 11:48:04.974065 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3034 11:48:04.977961 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3035 11:48:04.980848 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 11:48:04.984673 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 11:48:04.990890 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3038 11:48:04.994307 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3039 11:48:04.997865 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3040 11:48:04.998386 ==
3041 11:48:05.000900 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 11:48:05.004326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 11:48:05.004745 ==
3044 11:48:05.007605 DQS Delay:
3045 11:48:05.008020 DQS0 = 0, DQS1 = 0
3046 11:48:05.008350 DQM Delay:
3047 11:48:05.011417 DQM0 = 113, DQM1 = 104
3048 11:48:05.011833 DQ Delay:
3049 11:48:05.014997 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3050 11:48:05.018173 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3051 11:48:05.034334 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3052 11:48:05.034965 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3053 11:48:05.035347
3054 11:48:05.035684
3055 11:48:05.036364 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3056 11:48:05.038312 CH0 RK1: MR19=403, MR18=F2
3057 11:48:05.041342 CH0_RK1: MR19=0x403, MR18=0xF2, DQSOSC=410, MR23=63, INC=39, DEC=26
3058 11:48:05.045325 [RxdqsGatingPostProcess] freq 1200
3059 11:48:05.051323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 11:48:05.055129 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 11:48:05.058393 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 11:48:05.061702 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 11:48:05.065218 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 11:48:05.068342 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 11:48:05.071858 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 11:48:05.074966 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 11:48:05.075384 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 11:48:05.078376 Pre-setting of DQS Precalculation
3069 11:48:05.085170 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 11:48:05.085640 ==
3071 11:48:05.088269 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 11:48:05.091699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 11:48:05.092117 ==
3074 11:48:05.098739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 11:48:05.105441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 11:48:05.112285 [CA 0] Center 38 (8~68) winsize 61
3077 11:48:05.115424 [CA 1] Center 38 (8~68) winsize 61
3078 11:48:05.118702 [CA 2] Center 35 (6~65) winsize 60
3079 11:48:05.122958 [CA 3] Center 34 (4~65) winsize 62
3080 11:48:05.125685 [CA 4] Center 34 (4~65) winsize 62
3081 11:48:05.129117 [CA 5] Center 34 (4~64) winsize 61
3082 11:48:05.129568
3083 11:48:05.132275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 11:48:05.132704
3085 11:48:05.135367 [CATrainingPosCal] consider 1 rank data
3086 11:48:05.138911 u2DelayCellTimex100 = 270/100 ps
3087 11:48:05.142218 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 11:48:05.146467 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3089 11:48:05.148917 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3090 11:48:05.155215 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 11:48:05.158880 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3092 11:48:05.162551 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3093 11:48:05.162835
3094 11:48:05.165298 CA PerBit enable=1, Macro0, CA PI delay=34
3095 11:48:05.165532
3096 11:48:05.168582 [CBTSetCACLKResult] CA Dly = 34
3097 11:48:05.168773 CS Dly: 6 (0~37)
3098 11:48:05.168949 ==
3099 11:48:05.172328 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 11:48:05.178679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 11:48:05.178840 ==
3102 11:48:05.182309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 11:48:05.188616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 11:48:05.197413 [CA 0] Center 38 (8~68) winsize 61
3105 11:48:05.200969 [CA 1] Center 38 (9~68) winsize 60
3106 11:48:05.204085 [CA 2] Center 34 (4~65) winsize 62
3107 11:48:05.207712 [CA 3] Center 34 (4~65) winsize 62
3108 11:48:05.210966 [CA 4] Center 34 (4~65) winsize 62
3109 11:48:05.213953 [CA 5] Center 33 (3~63) winsize 61
3110 11:48:05.214034
3111 11:48:05.217883 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 11:48:05.217969
3113 11:48:05.221058 [CATrainingPosCal] consider 2 rank data
3114 11:48:05.224458 u2DelayCellTimex100 = 270/100 ps
3115 11:48:05.228048 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 11:48:05.230735 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3117 11:48:05.234132 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3118 11:48:05.241157 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 11:48:05.244242 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3120 11:48:05.247397 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3121 11:48:05.247480
3122 11:48:05.251126 CA PerBit enable=1, Macro0, CA PI delay=33
3123 11:48:05.251208
3124 11:48:05.254270 [CBTSetCACLKResult] CA Dly = 33
3125 11:48:05.254351 CS Dly: 8 (0~41)
3126 11:48:05.254415
3127 11:48:05.257817 ----->DramcWriteLeveling(PI) begin...
3128 11:48:05.257900 ==
3129 11:48:05.261350 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:48:05.267656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:48:05.267745 ==
3132 11:48:05.271253 Write leveling (Byte 0): 26 => 26
3133 11:48:05.271335 Write leveling (Byte 1): 30 => 30
3134 11:48:05.274880 DramcWriteLeveling(PI) end<-----
3135 11:48:05.274977
3136 11:48:05.277850 ==
3137 11:48:05.277932 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 11:48:05.284459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 11:48:05.284542 ==
3140 11:48:05.287864 [Gating] SW mode calibration
3141 11:48:05.294227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 11:48:05.297942 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 11:48:05.304844 0 15 0 | B1->B0 | 2b2b 2323 | 0 1 | (0 0) (1 1)
3144 11:48:05.308005 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 11:48:05.311520 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 11:48:05.317981 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3147 11:48:05.321381 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 11:48:05.324558 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 11:48:05.331494 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 11:48:05.334334 0 15 28 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3151 11:48:05.338213 1 0 0 | B1->B0 | 2525 2d2d | 0 1 | (1 0) (1 0)
3152 11:48:05.341386 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 11:48:05.348364 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 11:48:05.351455 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 11:48:05.354379 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 11:48:05.361236 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 11:48:05.364663 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 11:48:05.367994 1 0 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3159 11:48:05.375128 1 1 0 | B1->B0 | 4444 3636 | 0 0 | (0 0) (0 0)
3160 11:48:05.378235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 11:48:05.381909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 11:48:05.388158 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 11:48:05.391654 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 11:48:05.394895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 11:48:05.398479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 11:48:05.404968 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3167 11:48:05.408403 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3168 11:48:05.411819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:48:05.418564 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:48:05.421708 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:48:05.425205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:48:05.432361 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:48:05.435538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:48:05.438686 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:48:05.445508 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 11:48:05.448560 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 11:48:05.451968 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 11:48:05.455588 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 11:48:05.462119 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 11:48:05.465373 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:48:05.468803 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:48:05.476212 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3183 11:48:05.479064 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3184 11:48:05.482193 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 11:48:05.485633 Total UI for P1: 0, mck2ui 16
3186 11:48:05.488836 best dqsien dly found for B0: ( 1, 3, 30)
3187 11:48:05.492219 Total UI for P1: 0, mck2ui 16
3188 11:48:05.495739 best dqsien dly found for B1: ( 1, 4, 0)
3189 11:48:05.499354 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3190 11:48:05.502553 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3191 11:48:05.502657
3192 11:48:05.506099 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3193 11:48:05.513115 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3194 11:48:05.513199 [Gating] SW calibration Done
3195 11:48:05.513264 ==
3196 11:48:05.516097 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:48:05.523018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:48:05.523101 ==
3199 11:48:05.523166 RX Vref Scan: 0
3200 11:48:05.523225
3201 11:48:05.525861 RX Vref 0 -> 0, step: 1
3202 11:48:05.525942
3203 11:48:05.529404 RX Delay -40 -> 252, step: 8
3204 11:48:05.532866 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 11:48:05.536275 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 11:48:05.540024 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3207 11:48:05.542600 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3208 11:48:05.549761 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 11:48:05.552809 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3210 11:48:05.556197 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3211 11:48:05.559324 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3212 11:48:05.563291 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3213 11:48:05.566432 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3214 11:48:05.572893 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3215 11:48:05.576027 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3216 11:48:05.579559 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3217 11:48:05.582768 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3218 11:48:05.589654 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 11:48:05.592924 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 11:48:05.593006 ==
3221 11:48:05.596277 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:48:05.600107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 11:48:05.600216 ==
3224 11:48:05.600312 DQS Delay:
3225 11:48:05.603331 DQS0 = 0, DQS1 = 0
3226 11:48:05.603415 DQM Delay:
3227 11:48:05.606018 DQM0 = 115, DQM1 = 108
3228 11:48:05.606099 DQ Delay:
3229 11:48:05.609441 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3230 11:48:05.612950 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3231 11:48:05.616282 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3232 11:48:05.619614 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3233 11:48:05.619728
3234 11:48:05.619816
3235 11:48:05.623224 ==
3236 11:48:05.626269 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 11:48:05.629592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 11:48:05.629703 ==
3239 11:48:05.629790
3240 11:48:05.629884
3241 11:48:05.632920 TX Vref Scan disable
3242 11:48:05.633019 == TX Byte 0 ==
3243 11:48:05.636469 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 11:48:05.643411 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 11:48:05.643521 == TX Byte 1 ==
3246 11:48:05.646731 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3247 11:48:05.652991 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3248 11:48:05.653073 ==
3249 11:48:05.656599 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 11:48:05.659623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 11:48:05.659731 ==
3252 11:48:05.671915 TX Vref=22, minBit 1, minWin=24, winSum=409
3253 11:48:05.675251 TX Vref=24, minBit 0, minWin=25, winSum=415
3254 11:48:05.678506 TX Vref=26, minBit 0, minWin=26, winSum=425
3255 11:48:05.681660 TX Vref=28, minBit 0, minWin=26, winSum=424
3256 11:48:05.684783 TX Vref=30, minBit 1, minWin=26, winSum=430
3257 11:48:05.688205 TX Vref=32, minBit 3, minWin=26, winSum=429
3258 11:48:05.695462 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3259 11:48:05.695548
3260 11:48:05.698580 Final TX Range 1 Vref 30
3261 11:48:05.698689
3262 11:48:05.698786 ==
3263 11:48:05.702020 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:48:05.705299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:48:05.705382 ==
3266 11:48:05.705446
3267 11:48:05.705506
3268 11:48:05.708432 TX Vref Scan disable
3269 11:48:05.712154 == TX Byte 0 ==
3270 11:48:05.715156 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3271 11:48:05.718291 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3272 11:48:05.721980 == TX Byte 1 ==
3273 11:48:05.725348 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3274 11:48:05.728453 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3275 11:48:05.728565
3276 11:48:05.731977 [DATLAT]
3277 11:48:05.732059 Freq=1200, CH1 RK0
3278 11:48:05.732124
3279 11:48:05.735321 DATLAT Default: 0xd
3280 11:48:05.735402 0, 0xFFFF, sum = 0
3281 11:48:05.739127 1, 0xFFFF, sum = 0
3282 11:48:05.739211 2, 0xFFFF, sum = 0
3283 11:48:05.742342 3, 0xFFFF, sum = 0
3284 11:48:05.742424 4, 0xFFFF, sum = 0
3285 11:48:05.745840 5, 0xFFFF, sum = 0
3286 11:48:05.745923 6, 0xFFFF, sum = 0
3287 11:48:05.749062 7, 0xFFFF, sum = 0
3288 11:48:05.749145 8, 0xFFFF, sum = 0
3289 11:48:05.752457 9, 0xFFFF, sum = 0
3290 11:48:05.752540 10, 0xFFFF, sum = 0
3291 11:48:05.755746 11, 0xFFFF, sum = 0
3292 11:48:05.755829 12, 0x0, sum = 1
3293 11:48:05.758624 13, 0x0, sum = 2
3294 11:48:05.758706 14, 0x0, sum = 3
3295 11:48:05.762144 15, 0x0, sum = 4
3296 11:48:05.762228 best_step = 13
3297 11:48:05.762292
3298 11:48:05.762352 ==
3299 11:48:05.765470 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 11:48:05.772307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 11:48:05.772395 ==
3302 11:48:05.772494 RX Vref Scan: 1
3303 11:48:05.772587
3304 11:48:05.775896 Set Vref Range= 32 -> 127
3305 11:48:05.776007
3306 11:48:05.779359 RX Vref 32 -> 127, step: 1
3307 11:48:05.779468
3308 11:48:05.779562 RX Delay -21 -> 252, step: 4
3309 11:48:05.779651
3310 11:48:05.782543 Set Vref, RX VrefLevel [Byte0]: 32
3311 11:48:05.785872 [Byte1]: 32
3312 11:48:05.790015
3313 11:48:05.790096 Set Vref, RX VrefLevel [Byte0]: 33
3314 11:48:05.793136 [Byte1]: 33
3315 11:48:05.797980
3316 11:48:05.798063 Set Vref, RX VrefLevel [Byte0]: 34
3317 11:48:05.801219 [Byte1]: 34
3318 11:48:05.805773
3319 11:48:05.805854 Set Vref, RX VrefLevel [Byte0]: 35
3320 11:48:05.808996 [Byte1]: 35
3321 11:48:05.813842
3322 11:48:05.813926 Set Vref, RX VrefLevel [Byte0]: 36
3323 11:48:05.817444 [Byte1]: 36
3324 11:48:05.821412
3325 11:48:05.821524 Set Vref, RX VrefLevel [Byte0]: 37
3326 11:48:05.824841 [Byte1]: 37
3327 11:48:05.829798
3328 11:48:05.829904 Set Vref, RX VrefLevel [Byte0]: 38
3329 11:48:05.832785 [Byte1]: 38
3330 11:48:05.837667
3331 11:48:05.837774 Set Vref, RX VrefLevel [Byte0]: 39
3332 11:48:05.840672 [Byte1]: 39
3333 11:48:05.845559
3334 11:48:05.845666 Set Vref, RX VrefLevel [Byte0]: 40
3335 11:48:05.848789 [Byte1]: 40
3336 11:48:05.853692
3337 11:48:05.853802 Set Vref, RX VrefLevel [Byte0]: 41
3338 11:48:05.856429 [Byte1]: 41
3339 11:48:05.861323
3340 11:48:05.861429 Set Vref, RX VrefLevel [Byte0]: 42
3341 11:48:05.864565 [Byte1]: 42
3342 11:48:05.869200
3343 11:48:05.869339 Set Vref, RX VrefLevel [Byte0]: 43
3344 11:48:05.872628 [Byte1]: 43
3345 11:48:05.877213
3346 11:48:05.877298 Set Vref, RX VrefLevel [Byte0]: 44
3347 11:48:05.880496 [Byte1]: 44
3348 11:48:05.885215
3349 11:48:05.885295 Set Vref, RX VrefLevel [Byte0]: 45
3350 11:48:05.888599 [Byte1]: 45
3351 11:48:05.893314
3352 11:48:05.893395 Set Vref, RX VrefLevel [Byte0]: 46
3353 11:48:05.896152 [Byte1]: 46
3354 11:48:05.900659
3355 11:48:05.900739 Set Vref, RX VrefLevel [Byte0]: 47
3356 11:48:05.904211 [Byte1]: 47
3357 11:48:05.909193
3358 11:48:05.909290 Set Vref, RX VrefLevel [Byte0]: 48
3359 11:48:05.912032 [Byte1]: 48
3360 11:48:05.916790
3361 11:48:05.916871 Set Vref, RX VrefLevel [Byte0]: 49
3362 11:48:05.920077 [Byte1]: 49
3363 11:48:05.924889
3364 11:48:05.924969 Set Vref, RX VrefLevel [Byte0]: 50
3365 11:48:05.928041 [Byte1]: 50
3366 11:48:05.932541
3367 11:48:05.932694 Set Vref, RX VrefLevel [Byte0]: 51
3368 11:48:05.935802 [Byte1]: 51
3369 11:48:05.940597
3370 11:48:05.940677 Set Vref, RX VrefLevel [Byte0]: 52
3371 11:48:05.944092 [Byte1]: 52
3372 11:48:05.948472
3373 11:48:05.948578 Set Vref, RX VrefLevel [Byte0]: 53
3374 11:48:05.951814 [Byte1]: 53
3375 11:48:05.956201
3376 11:48:05.956383 Set Vref, RX VrefLevel [Byte0]: 54
3377 11:48:05.959686 [Byte1]: 54
3378 11:48:05.964259
3379 11:48:05.964442 Set Vref, RX VrefLevel [Byte0]: 55
3380 11:48:05.967708 [Byte1]: 55
3381 11:48:05.972499
3382 11:48:05.972693 Set Vref, RX VrefLevel [Byte0]: 56
3383 11:48:05.975380 [Byte1]: 56
3384 11:48:05.980028
3385 11:48:05.980205 Set Vref, RX VrefLevel [Byte0]: 57
3386 11:48:05.983871 [Byte1]: 57
3387 11:48:05.988431
3388 11:48:05.988653 Set Vref, RX VrefLevel [Byte0]: 58
3389 11:48:05.991228 [Byte1]: 58
3390 11:48:05.995904
3391 11:48:05.996126 Set Vref, RX VrefLevel [Byte0]: 59
3392 11:48:05.999245 [Byte1]: 59
3393 11:48:06.004067
3394 11:48:06.004239 Set Vref, RX VrefLevel [Byte0]: 60
3395 11:48:06.007508 [Byte1]: 60
3396 11:48:06.012095
3397 11:48:06.012267 Set Vref, RX VrefLevel [Byte0]: 61
3398 11:48:06.015012 [Byte1]: 61
3399 11:48:06.019751
3400 11:48:06.019866 Set Vref, RX VrefLevel [Byte0]: 62
3401 11:48:06.022928 [Byte1]: 62
3402 11:48:06.027744
3403 11:48:06.027849 Set Vref, RX VrefLevel [Byte0]: 63
3404 11:48:06.030899 [Byte1]: 63
3405 11:48:06.035480
3406 11:48:06.035561 Set Vref, RX VrefLevel [Byte0]: 64
3407 11:48:06.038771 [Byte1]: 64
3408 11:48:06.043384
3409 11:48:06.043467 Set Vref, RX VrefLevel [Byte0]: 65
3410 11:48:06.046556 [Byte1]: 65
3411 11:48:06.051048
3412 11:48:06.051154 Set Vref, RX VrefLevel [Byte0]: 66
3413 11:48:06.054767 [Byte1]: 66
3414 11:48:06.059192
3415 11:48:06.059291 Set Vref, RX VrefLevel [Byte0]: 67
3416 11:48:06.062474 [Byte1]: 67
3417 11:48:06.067326
3418 11:48:06.067406 Set Vref, RX VrefLevel [Byte0]: 68
3419 11:48:06.070191 [Byte1]: 68
3420 11:48:06.074962
3421 11:48:06.075068 Set Vref, RX VrefLevel [Byte0]: 69
3422 11:48:06.078308 [Byte1]: 69
3423 11:48:06.082824
3424 11:48:06.082914 Set Vref, RX VrefLevel [Byte0]: 70
3425 11:48:06.086378 [Byte1]: 70
3426 11:48:06.090993
3427 11:48:06.091073 Set Vref, RX VrefLevel [Byte0]: 71
3428 11:48:06.094425 [Byte1]: 71
3429 11:48:06.098840
3430 11:48:06.099024 Set Vref, RX VrefLevel [Byte0]: 72
3431 11:48:06.102465 [Byte1]: 72
3432 11:48:06.106889
3433 11:48:06.107073 Final RX Vref Byte 0 = 54 to rank0
3434 11:48:06.110068 Final RX Vref Byte 1 = 53 to rank0
3435 11:48:06.114034 Final RX Vref Byte 0 = 54 to rank1
3436 11:48:06.117022 Final RX Vref Byte 1 = 53 to rank1==
3437 11:48:06.120171 Dram Type= 6, Freq= 0, CH_1, rank 0
3438 11:48:06.123555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 11:48:06.127454 ==
3440 11:48:06.127618 DQS Delay:
3441 11:48:06.127740 DQS0 = 0, DQS1 = 0
3442 11:48:06.130646 DQM Delay:
3443 11:48:06.130893 DQM0 = 115, DQM1 = 110
3444 11:48:06.133687 DQ Delay:
3445 11:48:06.137255 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3446 11:48:06.140793 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3447 11:48:06.143765 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3448 11:48:06.147562 DQ12 =118, DQ13 =114, DQ14 =118, DQ15 =114
3449 11:48:06.147888
3450 11:48:06.148145
3451 11:48:06.154377 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3452 11:48:06.157202 CH1 RK0: MR19=303, MR18=FEE3
3453 11:48:06.163979 CH1_RK0: MR19=0x303, MR18=0xFEE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3454 11:48:06.164416
3455 11:48:06.167744 ----->DramcWriteLeveling(PI) begin...
3456 11:48:06.168303 ==
3457 11:48:06.170765 Dram Type= 6, Freq= 0, CH_1, rank 1
3458 11:48:06.174499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 11:48:06.174916 ==
3460 11:48:06.177816 Write leveling (Byte 0): 27 => 27
3461 11:48:06.181501 Write leveling (Byte 1): 29 => 29
3462 11:48:06.184591 DramcWriteLeveling(PI) end<-----
3463 11:48:06.185070
3464 11:48:06.185379 ==
3465 11:48:06.187867 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 11:48:06.191647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 11:48:06.192032 ==
3468 11:48:06.194236 [Gating] SW mode calibration
3469 11:48:06.201315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3470 11:48:06.207716 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3471 11:48:06.211639 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
3472 11:48:06.218221 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 11:48:06.221397 0 15 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3474 11:48:06.224708 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 11:48:06.228051 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 11:48:06.234393 0 15 20 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3477 11:48:06.238234 0 15 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
3478 11:48:06.241338 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3479 11:48:06.248130 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 11:48:06.251210 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 11:48:06.254562 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3482 11:48:06.261327 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 11:48:06.265285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 11:48:06.267767 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 11:48:06.274979 1 0 24 | B1->B0 | 2626 4343 | 0 0 | (0 0) (0 0)
3486 11:48:06.278415 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3487 11:48:06.281490 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 11:48:06.287895 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 11:48:06.291370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 11:48:06.294775 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 11:48:06.301580 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 11:48:06.304562 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3493 11:48:06.308259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3494 11:48:06.311321 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3495 11:48:06.318285 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:48:06.321817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:48:06.324847 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:48:06.331416 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 11:48:06.334656 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 11:48:06.337890 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 11:48:06.344622 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 11:48:06.347657 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 11:48:06.350898 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 11:48:06.358020 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 11:48:06.361282 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 11:48:06.364690 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 11:48:06.371801 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 11:48:06.374538 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3509 11:48:06.377750 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3510 11:48:06.384943 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3511 11:48:06.387861 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 11:48:06.391290 Total UI for P1: 0, mck2ui 16
3513 11:48:06.395033 best dqsien dly found for B0: ( 1, 3, 24)
3514 11:48:06.398149 Total UI for P1: 0, mck2ui 16
3515 11:48:06.401281 best dqsien dly found for B1: ( 1, 3, 28)
3516 11:48:06.404420 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3517 11:48:06.407725 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3518 11:48:06.408134
3519 11:48:06.411396 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3520 11:48:06.414717 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3521 11:48:06.418050 [Gating] SW calibration Done
3522 11:48:06.418460 ==
3523 11:48:06.421230 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 11:48:06.424498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 11:48:06.424928 ==
3526 11:48:06.427726 RX Vref Scan: 0
3527 11:48:06.428284
3528 11:48:06.431092 RX Vref 0 -> 0, step: 1
3529 11:48:06.431619
3530 11:48:06.432098 RX Delay -40 -> 252, step: 8
3531 11:48:06.437850 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3532 11:48:06.441312 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3533 11:48:06.444528 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3534 11:48:06.448036 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3535 11:48:06.451675 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3536 11:48:06.458232 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3537 11:48:06.461480 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3538 11:48:06.464936 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3539 11:48:06.467725 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3540 11:48:06.471004 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3541 11:48:06.477564 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3542 11:48:06.481188 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3543 11:48:06.484601 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3544 11:48:06.487805 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3545 11:48:06.491060 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3546 11:48:06.497861 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3547 11:48:06.498275 ==
3548 11:48:06.501195 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 11:48:06.504559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 11:48:06.505161 ==
3551 11:48:06.505624 DQS Delay:
3552 11:48:06.507991 DQS0 = 0, DQS1 = 0
3553 11:48:06.508550 DQM Delay:
3554 11:48:06.511223 DQM0 = 112, DQM1 = 110
3555 11:48:06.511763 DQ Delay:
3556 11:48:06.514708 DQ0 =111, DQ1 =103, DQ2 =103, DQ3 =115
3557 11:48:06.517852 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3558 11:48:06.521354 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3559 11:48:06.524938 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3560 11:48:06.525503
3561 11:48:06.525977
3562 11:48:06.526426 ==
3563 11:48:06.527998 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 11:48:06.535100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 11:48:06.535557 ==
3566 11:48:06.536032
3567 11:48:06.536489
3568 11:48:06.536832 TX Vref Scan disable
3569 11:48:06.538121 == TX Byte 0 ==
3570 11:48:06.541993 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3571 11:48:06.545158 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3572 11:48:06.548019 == TX Byte 1 ==
3573 11:48:06.551728 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3574 11:48:06.558503 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3575 11:48:06.558964 ==
3576 11:48:06.561920 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 11:48:06.564995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 11:48:06.565522 ==
3579 11:48:06.576198 TX Vref=22, minBit 2, minWin=25, winSum=417
3580 11:48:06.579258 TX Vref=24, minBit 3, minWin=25, winSum=424
3581 11:48:06.582937 TX Vref=26, minBit 0, minWin=26, winSum=428
3582 11:48:06.586505 TX Vref=28, minBit 3, minWin=25, winSum=429
3583 11:48:06.589875 TX Vref=30, minBit 2, minWin=26, winSum=429
3584 11:48:06.592947 TX Vref=32, minBit 0, minWin=26, winSum=431
3585 11:48:06.599742 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 32
3586 11:48:06.600317
3587 11:48:06.603218 Final TX Range 1 Vref 32
3588 11:48:06.603634
3589 11:48:06.603965 ==
3590 11:48:06.606425 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 11:48:06.609559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 11:48:06.609976 ==
3593 11:48:06.610306
3594 11:48:06.610610
3595 11:48:06.612692 TX Vref Scan disable
3596 11:48:06.616027 == TX Byte 0 ==
3597 11:48:06.619580 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3598 11:48:06.622645 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3599 11:48:06.626562 == TX Byte 1 ==
3600 11:48:06.629351 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3601 11:48:06.633057 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3602 11:48:06.633477
3603 11:48:06.636547 [DATLAT]
3604 11:48:06.637230 Freq=1200, CH1 RK1
3605 11:48:06.637731
3606 11:48:06.639264 DATLAT Default: 0xd
3607 11:48:06.639819 0, 0xFFFF, sum = 0
3608 11:48:06.642547 1, 0xFFFF, sum = 0
3609 11:48:06.643148 2, 0xFFFF, sum = 0
3610 11:48:06.645826 3, 0xFFFF, sum = 0
3611 11:48:06.646248 4, 0xFFFF, sum = 0
3612 11:48:06.649576 5, 0xFFFF, sum = 0
3613 11:48:06.652764 6, 0xFFFF, sum = 0
3614 11:48:06.653490 7, 0xFFFF, sum = 0
3615 11:48:06.655923 8, 0xFFFF, sum = 0
3616 11:48:06.656349 9, 0xFFFF, sum = 0
3617 11:48:06.659307 10, 0xFFFF, sum = 0
3618 11:48:06.659733 11, 0xFFFF, sum = 0
3619 11:48:06.662561 12, 0x0, sum = 1
3620 11:48:06.663016 13, 0x0, sum = 2
3621 11:48:06.665915 14, 0x0, sum = 3
3622 11:48:06.666419 15, 0x0, sum = 4
3623 11:48:06.666761 best_step = 13
3624 11:48:06.667110
3625 11:48:06.669588 ==
3626 11:48:06.672842 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:48:06.675935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:48:06.676454 ==
3629 11:48:06.676785 RX Vref Scan: 0
3630 11:48:06.677093
3631 11:48:06.679754 RX Vref 0 -> 0, step: 1
3632 11:48:06.680406
3633 11:48:06.682915 RX Delay -21 -> 252, step: 4
3634 11:48:06.686086 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3635 11:48:06.692902 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3636 11:48:06.695634 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3637 11:48:06.698946 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3638 11:48:06.702503 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3639 11:48:06.705522 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3640 11:48:06.711977 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3641 11:48:06.715470 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3642 11:48:06.719406 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3643 11:48:06.722457 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3644 11:48:06.725823 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3645 11:48:06.728785 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3646 11:48:06.735651 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3647 11:48:06.738971 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3648 11:48:06.742662 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3649 11:48:06.745668 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3650 11:48:06.746200 ==
3651 11:48:06.749019 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 11:48:06.755749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 11:48:06.756268 ==
3654 11:48:06.756631 DQS Delay:
3655 11:48:06.758831 DQS0 = 0, DQS1 = 0
3656 11:48:06.759264 DQM Delay:
3657 11:48:06.762514 DQM0 = 113, DQM1 = 109
3658 11:48:06.762970 DQ Delay:
3659 11:48:06.765468 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3660 11:48:06.768844 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3661 11:48:06.771917 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3662 11:48:06.775368 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3663 11:48:06.775864
3664 11:48:06.776369
3665 11:48:06.785561 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3666 11:48:06.785992 CH1 RK1: MR19=304, MR18=FA01
3667 11:48:06.792407 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3668 11:48:06.795512 [RxdqsGatingPostProcess] freq 1200
3669 11:48:06.801895 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3670 11:48:06.805418 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 11:48:06.809411 best DQS1 dly(2T, 0.5T) = (0, 12)
3672 11:48:06.812587 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 11:48:06.815601 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3674 11:48:06.816121 best DQS0 dly(2T, 0.5T) = (0, 11)
3675 11:48:06.818936 best DQS1 dly(2T, 0.5T) = (0, 11)
3676 11:48:06.822173 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3677 11:48:06.825940 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3678 11:48:06.828911 Pre-setting of DQS Precalculation
3679 11:48:06.835763 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3680 11:48:06.842340 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3681 11:48:06.848931 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3682 11:48:06.849353
3683 11:48:06.849846
3684 11:48:06.852191 [Calibration Summary] 2400 Mbps
3685 11:48:06.852733 CH 0, Rank 0
3686 11:48:06.855613 SW Impedance : PASS
3687 11:48:06.859258 DUTY Scan : NO K
3688 11:48:06.859692 ZQ Calibration : PASS
3689 11:48:06.862319 Jitter Meter : NO K
3690 11:48:06.866222 CBT Training : PASS
3691 11:48:06.866637 Write leveling : PASS
3692 11:48:06.869159 RX DQS gating : PASS
3693 11:48:06.872408 RX DQ/DQS(RDDQC) : PASS
3694 11:48:06.872820 TX DQ/DQS : PASS
3695 11:48:06.875551 RX DATLAT : PASS
3696 11:48:06.876016 RX DQ/DQS(Engine): PASS
3697 11:48:06.878700 TX OE : NO K
3698 11:48:06.879238 All Pass.
3699 11:48:06.879715
3700 11:48:06.882170 CH 0, Rank 1
3701 11:48:06.882535 SW Impedance : PASS
3702 11:48:06.885813 DUTY Scan : NO K
3703 11:48:06.888924 ZQ Calibration : PASS
3704 11:48:06.889491 Jitter Meter : NO K
3705 11:48:06.892390 CBT Training : PASS
3706 11:48:06.895827 Write leveling : PASS
3707 11:48:06.896370 RX DQS gating : PASS
3708 11:48:06.898917 RX DQ/DQS(RDDQC) : PASS
3709 11:48:06.902266 TX DQ/DQS : PASS
3710 11:48:06.902964 RX DATLAT : PASS
3711 11:48:06.905924 RX DQ/DQS(Engine): PASS
3712 11:48:06.908997 TX OE : NO K
3713 11:48:06.909567 All Pass.
3714 11:48:06.910057
3715 11:48:06.910424 CH 1, Rank 0
3716 11:48:06.912579 SW Impedance : PASS
3717 11:48:06.915651 DUTY Scan : NO K
3718 11:48:06.916291 ZQ Calibration : PASS
3719 11:48:06.918856 Jitter Meter : NO K
3720 11:48:06.919316 CBT Training : PASS
3721 11:48:06.922312 Write leveling : PASS
3722 11:48:06.925633 RX DQS gating : PASS
3723 11:48:06.926162 RX DQ/DQS(RDDQC) : PASS
3724 11:48:06.928596 TX DQ/DQS : PASS
3725 11:48:06.932361 RX DATLAT : PASS
3726 11:48:06.932774 RX DQ/DQS(Engine): PASS
3727 11:48:06.935559 TX OE : NO K
3728 11:48:06.935861 All Pass.
3729 11:48:06.936132
3730 11:48:06.938405 CH 1, Rank 1
3731 11:48:06.938651 SW Impedance : PASS
3732 11:48:06.941926 DUTY Scan : NO K
3733 11:48:06.945741 ZQ Calibration : PASS
3734 11:48:06.945935 Jitter Meter : NO K
3735 11:48:06.948875 CBT Training : PASS
3736 11:48:06.951892 Write leveling : PASS
3737 11:48:06.952085 RX DQS gating : PASS
3738 11:48:06.955517 RX DQ/DQS(RDDQC) : PASS
3739 11:48:06.958757 TX DQ/DQS : PASS
3740 11:48:06.958953 RX DATLAT : PASS
3741 11:48:06.961845 RX DQ/DQS(Engine): PASS
3742 11:48:06.962015 TX OE : NO K
3743 11:48:06.965858 All Pass.
3744 11:48:06.966054
3745 11:48:06.966211 DramC Write-DBI off
3746 11:48:06.968982 PER_BANK_REFRESH: Hybrid Mode
3747 11:48:06.971951 TX_TRACKING: ON
3748 11:48:06.978643 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3749 11:48:06.981833 [FAST_K] Save calibration result to emmc
3750 11:48:06.985520 dramc_set_vcore_voltage set vcore to 650000
3751 11:48:06.988642 Read voltage for 600, 5
3752 11:48:06.988782 Vio18 = 0
3753 11:48:06.991985 Vcore = 650000
3754 11:48:06.992124 Vdram = 0
3755 11:48:06.992247 Vddq = 0
3756 11:48:06.995607 Vmddr = 0
3757 11:48:06.998832 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3758 11:48:07.005358 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3759 11:48:07.005436 MEM_TYPE=3, freq_sel=19
3760 11:48:07.008656 sv_algorithm_assistance_LP4_1600
3761 11:48:07.015622 ============ PULL DRAM RESETB DOWN ============
3762 11:48:07.018619 ========== PULL DRAM RESETB DOWN end =========
3763 11:48:07.022423 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3764 11:48:07.025582 ===================================
3765 11:48:07.029029 LPDDR4 DRAM CONFIGURATION
3766 11:48:07.032088 ===================================
3767 11:48:07.032185 EX_ROW_EN[0] = 0x0
3768 11:48:07.035405 EX_ROW_EN[1] = 0x0
3769 11:48:07.038844 LP4Y_EN = 0x0
3770 11:48:07.038952 WORK_FSP = 0x0
3771 11:48:07.041908 WL = 0x2
3772 11:48:07.041974 RL = 0x2
3773 11:48:07.045277 BL = 0x2
3774 11:48:07.045345 RPST = 0x0
3775 11:48:07.049013 RD_PRE = 0x0
3776 11:48:07.049104 WR_PRE = 0x1
3777 11:48:07.052094 WR_PST = 0x0
3778 11:48:07.052160 DBI_WR = 0x0
3779 11:48:07.055269 DBI_RD = 0x0
3780 11:48:07.055333 OTF = 0x1
3781 11:48:07.058625 ===================================
3782 11:48:07.061750 ===================================
3783 11:48:07.065453 ANA top config
3784 11:48:07.069193 ===================================
3785 11:48:07.069260 DLL_ASYNC_EN = 0
3786 11:48:07.071965 ALL_SLAVE_EN = 1
3787 11:48:07.075542 NEW_RANK_MODE = 1
3788 11:48:07.078598 DLL_IDLE_MODE = 1
3789 11:48:07.078692 LP45_APHY_COMB_EN = 1
3790 11:48:07.082298 TX_ODT_DIS = 1
3791 11:48:07.085511 NEW_8X_MODE = 1
3792 11:48:07.088558 ===================================
3793 11:48:07.092205 ===================================
3794 11:48:07.095527 data_rate = 1200
3795 11:48:07.098784 CKR = 1
3796 11:48:07.101974 DQ_P2S_RATIO = 8
3797 11:48:07.105553 ===================================
3798 11:48:07.105625 CA_P2S_RATIO = 8
3799 11:48:07.108650 DQ_CA_OPEN = 0
3800 11:48:07.112100 DQ_SEMI_OPEN = 0
3801 11:48:07.115583 CA_SEMI_OPEN = 0
3802 11:48:07.118948 CA_FULL_RATE = 0
3803 11:48:07.119022 DQ_CKDIV4_EN = 1
3804 11:48:07.122150 CA_CKDIV4_EN = 1
3805 11:48:07.125803 CA_PREDIV_EN = 0
3806 11:48:07.129109 PH8_DLY = 0
3807 11:48:07.132313 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3808 11:48:07.135426 DQ_AAMCK_DIV = 4
3809 11:48:07.135494 CA_AAMCK_DIV = 4
3810 11:48:07.138947 CA_ADMCK_DIV = 4
3811 11:48:07.142138 DQ_TRACK_CA_EN = 0
3812 11:48:07.145712 CA_PICK = 600
3813 11:48:07.148714 CA_MCKIO = 600
3814 11:48:07.152142 MCKIO_SEMI = 0
3815 11:48:07.155605 PLL_FREQ = 2288
3816 11:48:07.155673 DQ_UI_PI_RATIO = 32
3817 11:48:07.158506 CA_UI_PI_RATIO = 0
3818 11:48:07.162243 ===================================
3819 11:48:07.165543 ===================================
3820 11:48:07.168983 memory_type:LPDDR4
3821 11:48:07.172105 GP_NUM : 10
3822 11:48:07.172197 SRAM_EN : 1
3823 11:48:07.175449 MD32_EN : 0
3824 11:48:07.178654 ===================================
3825 11:48:07.181900 [ANA_INIT] >>>>>>>>>>>>>>
3826 11:48:07.181997 <<<<<< [CONFIGURE PHASE]: ANA_TX
3827 11:48:07.185280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3828 11:48:07.188509 ===================================
3829 11:48:07.192152 data_rate = 1200,PCW = 0X5800
3830 11:48:07.195303 ===================================
3831 11:48:07.198476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3832 11:48:07.205292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3833 11:48:07.211830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3834 11:48:07.215495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3835 11:48:07.218624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3836 11:48:07.221872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3837 11:48:07.225044 [ANA_INIT] flow start
3838 11:48:07.225141 [ANA_INIT] PLL >>>>>>>>
3839 11:48:07.228738 [ANA_INIT] PLL <<<<<<<<
3840 11:48:07.232298 [ANA_INIT] MIDPI >>>>>>>>
3841 11:48:07.232397 [ANA_INIT] MIDPI <<<<<<<<
3842 11:48:07.235019 [ANA_INIT] DLL >>>>>>>>
3843 11:48:07.238891 [ANA_INIT] flow end
3844 11:48:07.241905 ============ LP4 DIFF to SE enter ============
3845 11:48:07.245225 ============ LP4 DIFF to SE exit ============
3846 11:48:07.248421 [ANA_INIT] <<<<<<<<<<<<<
3847 11:48:07.251914 [Flow] Enable top DCM control >>>>>
3848 11:48:07.255294 [Flow] Enable top DCM control <<<<<
3849 11:48:07.258826 Enable DLL master slave shuffle
3850 11:48:07.261913 ==============================================================
3851 11:48:07.265366 Gating Mode config
3852 11:48:07.272064 ==============================================================
3853 11:48:07.272133 Config description:
3854 11:48:07.281892 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3855 11:48:07.288536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3856 11:48:07.291880 SELPH_MODE 0: By rank 1: By Phase
3857 11:48:07.298328 ==============================================================
3858 11:48:07.302219 GAT_TRACK_EN = 1
3859 11:48:07.305381 RX_GATING_MODE = 2
3860 11:48:07.308729 RX_GATING_TRACK_MODE = 2
3861 11:48:07.311940 SELPH_MODE = 1
3862 11:48:07.315238 PICG_EARLY_EN = 1
3863 11:48:07.318734 VALID_LAT_VALUE = 1
3864 11:48:07.321722 ==============================================================
3865 11:48:07.325317 Enter into Gating configuration >>>>
3866 11:48:07.328467 Exit from Gating configuration <<<<
3867 11:48:07.331810 Enter into DVFS_PRE_config >>>>>
3868 11:48:07.342193 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3869 11:48:07.345496 Exit from DVFS_PRE_config <<<<<
3870 11:48:07.348577 Enter into PICG configuration >>>>
3871 11:48:07.351832 Exit from PICG configuration <<<<
3872 11:48:07.355497 [RX_INPUT] configuration >>>>>
3873 11:48:07.358672 [RX_INPUT] configuration <<<<<
3874 11:48:07.362202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3875 11:48:07.368605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3876 11:48:07.375456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 11:48:07.382195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 11:48:07.388332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 11:48:07.395244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 11:48:07.398383 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3881 11:48:07.402069 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3882 11:48:07.405366 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3883 11:48:07.408505 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3884 11:48:07.415474 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3885 11:48:07.418453 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 11:48:07.421800 ===================================
3887 11:48:07.425552 LPDDR4 DRAM CONFIGURATION
3888 11:48:07.428710 ===================================
3889 11:48:07.428820 EX_ROW_EN[0] = 0x0
3890 11:48:07.431782 EX_ROW_EN[1] = 0x0
3891 11:48:07.431862 LP4Y_EN = 0x0
3892 11:48:07.435270 WORK_FSP = 0x0
3893 11:48:07.435354 WL = 0x2
3894 11:48:07.438630 RL = 0x2
3895 11:48:07.438710 BL = 0x2
3896 11:48:07.441951 RPST = 0x0
3897 11:48:07.442031 RD_PRE = 0x0
3898 11:48:07.445413 WR_PRE = 0x1
3899 11:48:07.448853 WR_PST = 0x0
3900 11:48:07.448968 DBI_WR = 0x0
3901 11:48:07.452600 DBI_RD = 0x0
3902 11:48:07.452680 OTF = 0x1
3903 11:48:07.455358 ===================================
3904 11:48:07.458500 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3905 11:48:07.461783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3906 11:48:07.468402 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 11:48:07.472314 ===================================
3908 11:48:07.474992 LPDDR4 DRAM CONFIGURATION
3909 11:48:07.475073 ===================================
3910 11:48:07.478761 EX_ROW_EN[0] = 0x10
3911 11:48:07.482081 EX_ROW_EN[1] = 0x0
3912 11:48:07.482162 LP4Y_EN = 0x0
3913 11:48:07.485246 WORK_FSP = 0x0
3914 11:48:07.485326 WL = 0x2
3915 11:48:07.488803 RL = 0x2
3916 11:48:07.488883 BL = 0x2
3917 11:48:07.492195 RPST = 0x0
3918 11:48:07.492275 RD_PRE = 0x0
3919 11:48:07.495485 WR_PRE = 0x1
3920 11:48:07.495568 WR_PST = 0x0
3921 11:48:07.498400 DBI_WR = 0x0
3922 11:48:07.498480 DBI_RD = 0x0
3923 11:48:07.501670 OTF = 0x1
3924 11:48:07.505434 ===================================
3925 11:48:07.511982 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3926 11:48:07.515443 nWR fixed to 30
3927 11:48:07.518644 [ModeRegInit_LP4] CH0 RK0
3928 11:48:07.518724 [ModeRegInit_LP4] CH0 RK1
3929 11:48:07.521633 [ModeRegInit_LP4] CH1 RK0
3930 11:48:07.525503 [ModeRegInit_LP4] CH1 RK1
3931 11:48:07.525584 match AC timing 17
3932 11:48:07.531807 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3933 11:48:07.535456 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3934 11:48:07.538338 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3935 11:48:07.545247 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3936 11:48:07.548542 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3937 11:48:07.548624 ==
3938 11:48:07.551696 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 11:48:07.554950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 11:48:07.555032 ==
3941 11:48:07.562296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 11:48:07.568505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3943 11:48:07.571880 [CA 0] Center 36 (6~66) winsize 61
3944 11:48:07.575187 [CA 1] Center 36 (6~66) winsize 61
3945 11:48:07.578639 [CA 2] Center 34 (4~65) winsize 62
3946 11:48:07.582318 [CA 3] Center 34 (4~65) winsize 62
3947 11:48:07.585816 [CA 4] Center 33 (3~64) winsize 62
3948 11:48:07.588802 [CA 5] Center 33 (3~64) winsize 62
3949 11:48:07.588903
3950 11:48:07.592213 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3951 11:48:07.592313
3952 11:48:07.595184 [CATrainingPosCal] consider 1 rank data
3953 11:48:07.598504 u2DelayCellTimex100 = 270/100 ps
3954 11:48:07.602091 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3955 11:48:07.605613 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3956 11:48:07.608927 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 11:48:07.612457 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 11:48:07.615971 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 11:48:07.619096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 11:48:07.619293
3961 11:48:07.622323 CA PerBit enable=1, Macro0, CA PI delay=33
3962 11:48:07.622525
3963 11:48:07.625829 [CBTSetCACLKResult] CA Dly = 33
3964 11:48:07.629051 CS Dly: 4 (0~35)
3965 11:48:07.629347 ==
3966 11:48:07.632496 Dram Type= 6, Freq= 0, CH_0, rank 1
3967 11:48:07.635977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 11:48:07.636375 ==
3969 11:48:07.642742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3970 11:48:07.649053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3971 11:48:07.652683 [CA 0] Center 36 (6~67) winsize 62
3972 11:48:07.655776 [CA 1] Center 36 (6~66) winsize 61
3973 11:48:07.659063 [CA 2] Center 34 (4~65) winsize 62
3974 11:48:07.662582 [CA 3] Center 34 (4~65) winsize 62
3975 11:48:07.665665 [CA 4] Center 33 (3~64) winsize 62
3976 11:48:07.666045 [CA 5] Center 33 (3~64) winsize 62
3977 11:48:07.669236
3978 11:48:07.672987 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3979 11:48:07.673197
3980 11:48:07.676304 [CATrainingPosCal] consider 2 rank data
3981 11:48:07.678889 u2DelayCellTimex100 = 270/100 ps
3982 11:48:07.682560 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3983 11:48:07.685638 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3984 11:48:07.689386 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3985 11:48:07.692099 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 11:48:07.695651 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3987 11:48:07.699082 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 11:48:07.699163
3989 11:48:07.702133 CA PerBit enable=1, Macro0, CA PI delay=33
3990 11:48:07.702214
3991 11:48:07.705777 [CBTSetCACLKResult] CA Dly = 33
3992 11:48:07.708894 CS Dly: 4 (0~36)
3993 11:48:07.708974
3994 11:48:07.712478 ----->DramcWriteLeveling(PI) begin...
3995 11:48:07.712560 ==
3996 11:48:07.715684 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 11:48:07.719155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 11:48:07.719236 ==
3999 11:48:07.722365 Write leveling (Byte 0): 31 => 31
4000 11:48:07.725720 Write leveling (Byte 1): 30 => 30
4001 11:48:07.728961 DramcWriteLeveling(PI) end<-----
4002 11:48:07.729041
4003 11:48:07.729105 ==
4004 11:48:07.731979 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 11:48:07.735491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 11:48:07.735573 ==
4007 11:48:07.738980 [Gating] SW mode calibration
4008 11:48:07.745477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4009 11:48:07.752456 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4010 11:48:07.755417 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 11:48:07.759453 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 11:48:07.765382 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 11:48:07.768984 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 11:48:07.772023 0 9 16 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 0)
4015 11:48:07.778797 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 11:48:07.782032 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 11:48:07.786056 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 11:48:07.792219 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 11:48:07.795540 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 11:48:07.799199 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 11:48:07.806014 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 11:48:07.809200 0 10 16 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4023 11:48:07.812549 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 11:48:07.818806 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 11:48:07.822227 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 11:48:07.825715 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 11:48:07.832433 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 11:48:07.835444 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 11:48:07.838955 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 11:48:07.842363 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 11:48:07.849333 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:48:07.852262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:48:07.855929 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:48:07.862511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:48:07.865750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 11:48:07.868947 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 11:48:07.875636 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 11:48:07.879255 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 11:48:07.882327 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 11:48:07.889269 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 11:48:07.892303 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 11:48:07.895656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 11:48:07.902529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 11:48:07.905744 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 11:48:07.909106 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 11:48:07.915855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4047 11:48:07.919469 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:48:07.922838 Total UI for P1: 0, mck2ui 16
4049 11:48:07.926191 best dqsien dly found for B0: ( 0, 13, 16)
4050 11:48:07.929397 Total UI for P1: 0, mck2ui 16
4051 11:48:07.932646 best dqsien dly found for B1: ( 0, 13, 16)
4052 11:48:07.936289 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4053 11:48:07.939609 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4054 11:48:07.939784
4055 11:48:07.942489 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4056 11:48:07.946296 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4057 11:48:07.949088 [Gating] SW calibration Done
4058 11:48:07.949258 ==
4059 11:48:07.952789 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 11:48:07.956465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 11:48:07.956731 ==
4062 11:48:07.959357 RX Vref Scan: 0
4063 11:48:07.959569
4064 11:48:07.962454 RX Vref 0 -> 0, step: 1
4065 11:48:07.962664
4066 11:48:07.962824 RX Delay -230 -> 252, step: 16
4067 11:48:07.969160 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4068 11:48:07.972875 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4069 11:48:07.976135 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4070 11:48:07.979630 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4071 11:48:07.982714 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4072 11:48:07.989415 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4073 11:48:07.992544 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4074 11:48:07.996004 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4075 11:48:07.999317 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4076 11:48:08.005891 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4077 11:48:08.009478 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4078 11:48:08.012560 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4079 11:48:08.016138 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4080 11:48:08.022327 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4081 11:48:08.026170 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4082 11:48:08.029467 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4083 11:48:08.029571 ==
4084 11:48:08.032585 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 11:48:08.035488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 11:48:08.035565 ==
4087 11:48:08.038829 DQS Delay:
4088 11:48:08.038964 DQS0 = 0, DQS1 = 0
4089 11:48:08.042591 DQM Delay:
4090 11:48:08.042692 DQM0 = 39, DQM1 = 31
4091 11:48:08.042790 DQ Delay:
4092 11:48:08.045885 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4093 11:48:08.049475 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4094 11:48:08.052510 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4095 11:48:08.056190 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4096 11:48:08.056293
4097 11:48:08.056383
4098 11:48:08.059483 ==
4099 11:48:08.059556 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 11:48:08.065799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 11:48:08.065960 ==
4102 11:48:08.066054
4103 11:48:08.066119
4104 11:48:08.069102 TX Vref Scan disable
4105 11:48:08.069202 == TX Byte 0 ==
4106 11:48:08.075476 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4107 11:48:08.079093 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4108 11:48:08.079220 == TX Byte 1 ==
4109 11:48:08.082572 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4110 11:48:08.089050 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4111 11:48:08.089153 ==
4112 11:48:08.092408 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 11:48:08.095581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 11:48:08.095654 ==
4115 11:48:08.095716
4116 11:48:08.095775
4117 11:48:08.098999 TX Vref Scan disable
4118 11:48:08.102258 == TX Byte 0 ==
4119 11:48:08.105913 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4120 11:48:08.108986 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4121 11:48:08.112426 == TX Byte 1 ==
4122 11:48:08.115595 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4123 11:48:08.119110 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4124 11:48:08.119188
4125 11:48:08.122715 [DATLAT]
4126 11:48:08.122813 Freq=600, CH0 RK0
4127 11:48:08.122916
4128 11:48:08.125676 DATLAT Default: 0x9
4129 11:48:08.125771 0, 0xFFFF, sum = 0
4130 11:48:08.128953 1, 0xFFFF, sum = 0
4131 11:48:08.129051 2, 0xFFFF, sum = 0
4132 11:48:08.132255 3, 0xFFFF, sum = 0
4133 11:48:08.132354 4, 0xFFFF, sum = 0
4134 11:48:08.135709 5, 0xFFFF, sum = 0
4135 11:48:08.135785 6, 0xFFFF, sum = 0
4136 11:48:08.139012 7, 0xFFFF, sum = 0
4137 11:48:08.139082 8, 0x0, sum = 1
4138 11:48:08.142324 9, 0x0, sum = 2
4139 11:48:08.142395 10, 0x0, sum = 3
4140 11:48:08.145962 11, 0x0, sum = 4
4141 11:48:08.146036 best_step = 9
4142 11:48:08.146096
4143 11:48:08.146152 ==
4144 11:48:08.149050 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 11:48:08.152084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 11:48:08.152155 ==
4147 11:48:08.155425 RX Vref Scan: 1
4148 11:48:08.155496
4149 11:48:08.159128 RX Vref 0 -> 0, step: 1
4150 11:48:08.159199
4151 11:48:08.159258 RX Delay -195 -> 252, step: 8
4152 11:48:08.159314
4153 11:48:08.162377 Set Vref, RX VrefLevel [Byte0]: 53
4154 11:48:08.165772 [Byte1]: 51
4155 11:48:08.170665
4156 11:48:08.170735 Final RX Vref Byte 0 = 53 to rank0
4157 11:48:08.174011 Final RX Vref Byte 1 = 51 to rank0
4158 11:48:08.177020 Final RX Vref Byte 0 = 53 to rank1
4159 11:48:08.180507 Final RX Vref Byte 1 = 51 to rank1==
4160 11:48:08.183779 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 11:48:08.190240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:48:08.190317 ==
4163 11:48:08.190381 DQS Delay:
4164 11:48:08.190439 DQS0 = 0, DQS1 = 0
4165 11:48:08.194062 DQM Delay:
4166 11:48:08.194131 DQM0 = 42, DQM1 = 34
4167 11:48:08.197003 DQ Delay:
4168 11:48:08.200338 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4169 11:48:08.200408 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4170 11:48:08.203681 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4171 11:48:08.206806 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4172 11:48:08.210489
4173 11:48:08.210558
4174 11:48:08.217474 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4175 11:48:08.220342 CH0 RK0: MR19=808, MR18=3E1E
4176 11:48:08.227148 CH0_RK0: MR19=0x808, MR18=0x3E1E, DQSOSC=398, MR23=63, INC=165, DEC=110
4177 11:48:08.227248
4178 11:48:08.230663 ----->DramcWriteLeveling(PI) begin...
4179 11:48:08.230762 ==
4180 11:48:08.233574 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 11:48:08.236983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 11:48:08.237083 ==
4183 11:48:08.240672 Write leveling (Byte 0): 33 => 33
4184 11:48:08.243940 Write leveling (Byte 1): 33 => 33
4185 11:48:08.247097 DramcWriteLeveling(PI) end<-----
4186 11:48:08.247171
4187 11:48:08.247234 ==
4188 11:48:08.250780 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 11:48:08.253898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 11:48:08.253972 ==
4191 11:48:08.257116 [Gating] SW mode calibration
4192 11:48:08.263885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4193 11:48:08.271084 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4194 11:48:08.274355 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4195 11:48:08.277903 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 11:48:08.284695 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 11:48:08.287628 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4198 11:48:08.290960 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4199 11:48:08.294751 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 11:48:08.301297 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 11:48:08.304932 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 11:48:08.307741 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 11:48:08.314772 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 11:48:08.318026 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 11:48:08.321423 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
4206 11:48:08.328355 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (1 1) (0 0)
4207 11:48:08.331396 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 11:48:08.334818 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 11:48:08.341394 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 11:48:08.344533 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 11:48:08.347855 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 11:48:08.354624 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 11:48:08.358286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4214 11:48:08.361778 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4215 11:48:08.367905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:48:08.371401 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:48:08.374665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:48:08.381191 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 11:48:08.384531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:48:08.387963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 11:48:08.394342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 11:48:08.398015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 11:48:08.401303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 11:48:08.404984 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 11:48:08.411526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 11:48:08.414574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 11:48:08.417848 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 11:48:08.424706 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 11:48:08.428499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4230 11:48:08.431680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:48:08.435264 Total UI for P1: 0, mck2ui 16
4232 11:48:08.438158 best dqsien dly found for B0: ( 0, 13, 12)
4233 11:48:08.441241 Total UI for P1: 0, mck2ui 16
4234 11:48:08.444980 best dqsien dly found for B1: ( 0, 13, 14)
4235 11:48:08.448947 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4236 11:48:08.451708 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4237 11:48:08.452132
4238 11:48:08.458232 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4239 11:48:08.461604 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4240 11:48:08.462018 [Gating] SW calibration Done
4241 11:48:08.465118 ==
4242 11:48:08.468668 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 11:48:08.471550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 11:48:08.471970 ==
4245 11:48:08.472305 RX Vref Scan: 0
4246 11:48:08.472612
4247 11:48:08.474877 RX Vref 0 -> 0, step: 1
4248 11:48:08.475295
4249 11:48:08.478787 RX Delay -230 -> 252, step: 16
4250 11:48:08.482219 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4251 11:48:08.485000 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4252 11:48:08.491603 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4253 11:48:08.495101 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4254 11:48:08.498483 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4255 11:48:08.501693 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4256 11:48:08.505103 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4257 11:48:08.511870 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4258 11:48:08.515130 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4259 11:48:08.518165 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4260 11:48:08.521424 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4261 11:48:08.528665 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4262 11:48:08.531751 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4263 11:48:08.534929 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4264 11:48:08.538420 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4265 11:48:08.541630 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4266 11:48:08.544858 ==
4267 11:48:08.548233 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:48:08.551841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:48:08.552257 ==
4270 11:48:08.552586 DQS Delay:
4271 11:48:08.554997 DQS0 = 0, DQS1 = 0
4272 11:48:08.555412 DQM Delay:
4273 11:48:08.558092 DQM0 = 40, DQM1 = 33
4274 11:48:08.558506 DQ Delay:
4275 11:48:08.561481 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4276 11:48:08.564789 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4277 11:48:08.568599 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4278 11:48:08.571573 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4279 11:48:08.571989
4280 11:48:08.572317
4281 11:48:08.572621 ==
4282 11:48:08.575181 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 11:48:08.578576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 11:48:08.579039 ==
4285 11:48:08.579379
4286 11:48:08.579685
4287 11:48:08.581434 TX Vref Scan disable
4288 11:48:08.584731 == TX Byte 0 ==
4289 11:48:08.588265 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4290 11:48:08.591937 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4291 11:48:08.595398 == TX Byte 1 ==
4292 11:48:08.598337 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4293 11:48:08.601791 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4294 11:48:08.602291 ==
4295 11:48:08.604980 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 11:48:08.608205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 11:48:08.611575 ==
4298 11:48:08.611986
4299 11:48:08.612314
4300 11:48:08.612617 TX Vref Scan disable
4301 11:48:08.615389 == TX Byte 0 ==
4302 11:48:08.619003 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4303 11:48:08.622489 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4304 11:48:08.625559 == TX Byte 1 ==
4305 11:48:08.629224 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4306 11:48:08.632126 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4307 11:48:08.632738
4308 11:48:08.636072 [DATLAT]
4309 11:48:08.636694 Freq=600, CH0 RK1
4310 11:48:08.637238
4311 11:48:08.638916 DATLAT Default: 0x9
4312 11:48:08.639365 0, 0xFFFF, sum = 0
4313 11:48:08.642858 1, 0xFFFF, sum = 0
4314 11:48:08.643389 2, 0xFFFF, sum = 0
4315 11:48:08.645663 3, 0xFFFF, sum = 0
4316 11:48:08.646203 4, 0xFFFF, sum = 0
4317 11:48:08.648942 5, 0xFFFF, sum = 0
4318 11:48:08.649569 6, 0xFFFF, sum = 0
4319 11:48:08.652443 7, 0xFFFF, sum = 0
4320 11:48:08.653062 8, 0x0, sum = 1
4321 11:48:08.655744 9, 0x0, sum = 2
4322 11:48:08.656389 10, 0x0, sum = 3
4323 11:48:08.658837 11, 0x0, sum = 4
4324 11:48:08.659418 best_step = 9
4325 11:48:08.659868
4326 11:48:08.660198 ==
4327 11:48:08.662128 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 11:48:08.669119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 11:48:08.669747 ==
4330 11:48:08.670295 RX Vref Scan: 0
4331 11:48:08.670850
4332 11:48:08.672196 RX Vref 0 -> 0, step: 1
4333 11:48:08.672793
4334 11:48:08.675610 RX Delay -179 -> 252, step: 8
4335 11:48:08.678691 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4336 11:48:08.682456 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4337 11:48:08.688802 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4338 11:48:08.692219 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4339 11:48:08.696190 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4340 11:48:08.699119 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4341 11:48:08.705671 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4342 11:48:08.709025 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4343 11:48:08.712552 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4344 11:48:08.715634 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4345 11:48:08.719272 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4346 11:48:08.725905 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4347 11:48:08.729409 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4348 11:48:08.732505 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4349 11:48:08.735705 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4350 11:48:08.742716 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4351 11:48:08.743275 ==
4352 11:48:08.745704 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 11:48:08.748903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 11:48:08.749279 ==
4355 11:48:08.749766 DQS Delay:
4356 11:48:08.752650 DQS0 = 0, DQS1 = 0
4357 11:48:08.753279 DQM Delay:
4358 11:48:08.755614 DQM0 = 39, DQM1 = 33
4359 11:48:08.756084 DQ Delay:
4360 11:48:08.759334 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4361 11:48:08.762751 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4362 11:48:08.765729 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4363 11:48:08.768867 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4364 11:48:08.769446
4365 11:48:08.769969
4366 11:48:08.775315 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4367 11:48:08.779099 CH0 RK1: MR19=808, MR18=4E2F
4368 11:48:08.785261 CH0_RK1: MR19=0x808, MR18=0x4E2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4369 11:48:08.788734 [RxdqsGatingPostProcess] freq 600
4370 11:48:08.795613 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4371 11:48:08.798928 Pre-setting of DQS Precalculation
4372 11:48:08.802444 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4373 11:48:08.802853 ==
4374 11:48:08.805738 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 11:48:08.809038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:48:08.809118 ==
4377 11:48:08.815423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 11:48:08.822665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 11:48:08.825521 [CA 0] Center 35 (5~65) winsize 61
4380 11:48:08.828862 [CA 1] Center 35 (5~66) winsize 62
4381 11:48:08.832223 [CA 2] Center 34 (4~64) winsize 61
4382 11:48:08.835368 [CA 3] Center 33 (3~64) winsize 62
4383 11:48:08.838991 [CA 4] Center 34 (3~65) winsize 63
4384 11:48:08.842185 [CA 5] Center 33 (3~64) winsize 62
4385 11:48:08.842265
4386 11:48:08.845318 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 11:48:08.845397
4388 11:48:08.848992 [CATrainingPosCal] consider 1 rank data
4389 11:48:08.852105 u2DelayCellTimex100 = 270/100 ps
4390 11:48:08.855258 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4391 11:48:08.859061 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 11:48:08.862064 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4393 11:48:08.866113 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 11:48:08.869282 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4395 11:48:08.872065 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 11:48:08.872175
4397 11:48:08.878761 CA PerBit enable=1, Macro0, CA PI delay=33
4398 11:48:08.878877
4399 11:48:08.878965 [CBTSetCACLKResult] CA Dly = 33
4400 11:48:08.882302 CS Dly: 3 (0~34)
4401 11:48:08.882410 ==
4402 11:48:08.885794 Dram Type= 6, Freq= 0, CH_1, rank 1
4403 11:48:08.888989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 11:48:08.889398 ==
4405 11:48:08.895767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4406 11:48:08.902592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4407 11:48:08.906231 [CA 0] Center 35 (5~66) winsize 62
4408 11:48:08.909243 [CA 1] Center 36 (6~66) winsize 61
4409 11:48:08.912128 [CA 2] Center 34 (3~65) winsize 63
4410 11:48:08.915750 [CA 3] Center 33 (3~64) winsize 62
4411 11:48:08.918897 [CA 4] Center 34 (4~65) winsize 62
4412 11:48:08.922266 [CA 5] Center 33 (3~64) winsize 62
4413 11:48:08.922346
4414 11:48:08.925611 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4415 11:48:08.925691
4416 11:48:08.928759 [CATrainingPosCal] consider 2 rank data
4417 11:48:08.932097 u2DelayCellTimex100 = 270/100 ps
4418 11:48:08.935781 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4419 11:48:08.938839 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4420 11:48:08.942178 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4421 11:48:08.945735 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 11:48:08.949245 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 11:48:08.952682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 11:48:08.952861
4425 11:48:08.959011 CA PerBit enable=1, Macro0, CA PI delay=33
4426 11:48:08.959145
4427 11:48:08.959241 [CBTSetCACLKResult] CA Dly = 33
4428 11:48:08.962490 CS Dly: 4 (0~36)
4429 11:48:08.962609
4430 11:48:08.965891 ----->DramcWriteLeveling(PI) begin...
4431 11:48:08.966030 ==
4432 11:48:08.968904 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 11:48:08.972297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 11:48:08.972447 ==
4435 11:48:08.976217 Write leveling (Byte 0): 30 => 30
4436 11:48:08.979260 Write leveling (Byte 1): 30 => 30
4437 11:48:08.982927 DramcWriteLeveling(PI) end<-----
4438 11:48:08.983172
4439 11:48:08.983389 ==
4440 11:48:08.986355 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 11:48:08.989648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 11:48:08.989942 ==
4443 11:48:08.992839 [Gating] SW mode calibration
4444 11:48:08.999703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4445 11:48:09.006159 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4446 11:48:09.009860 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4447 11:48:09.016356 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 11:48:09.019640 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 11:48:09.022737 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4450 11:48:09.026065 0 9 16 | B1->B0 | 2727 2525 | 0 1 | (0 0) (1 0)
4451 11:48:09.032945 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 11:48:09.036044 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 11:48:09.039465 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4454 11:48:09.046398 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 11:48:09.049505 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 11:48:09.052912 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 11:48:09.059471 0 10 12 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
4458 11:48:09.062944 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4459 11:48:09.066373 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 11:48:09.072674 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 11:48:09.076522 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 11:48:09.079386 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 11:48:09.086000 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 11:48:09.089596 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 11:48:09.092949 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 11:48:09.099551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4467 11:48:09.102972 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:48:09.106423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:48:09.109845 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:48:09.116367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:48:09.119677 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 11:48:09.123509 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 11:48:09.130197 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 11:48:09.133702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 11:48:09.136664 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 11:48:09.143626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 11:48:09.146526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 11:48:09.150005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 11:48:09.156549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 11:48:09.159983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 11:48:09.163310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4482 11:48:09.170303 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:48:09.170724 Total UI for P1: 0, mck2ui 16
4484 11:48:09.176442 best dqsien dly found for B0: ( 0, 13, 12)
4485 11:48:09.176866 Total UI for P1: 0, mck2ui 16
4486 11:48:09.180203 best dqsien dly found for B1: ( 0, 13, 14)
4487 11:48:09.186673 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4488 11:48:09.190091 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4489 11:48:09.190508
4490 11:48:09.193072 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4491 11:48:09.196720 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4492 11:48:09.199932 [Gating] SW calibration Done
4493 11:48:09.200352 ==
4494 11:48:09.203295 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 11:48:09.206468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 11:48:09.206929 ==
4497 11:48:09.210148 RX Vref Scan: 0
4498 11:48:09.210566
4499 11:48:09.210945 RX Vref 0 -> 0, step: 1
4500 11:48:09.211270
4501 11:48:09.213248 RX Delay -230 -> 252, step: 16
4502 11:48:09.216851 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4503 11:48:09.223302 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4504 11:48:09.226470 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4505 11:48:09.230165 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4506 11:48:09.233430 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4507 11:48:09.236815 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4508 11:48:09.243672 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4509 11:48:09.247011 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4510 11:48:09.250162 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4511 11:48:09.253209 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4512 11:48:09.260266 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4513 11:48:09.263272 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4514 11:48:09.266556 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4515 11:48:09.269652 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4516 11:48:09.276674 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4517 11:48:09.280156 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4518 11:48:09.280611 ==
4519 11:48:09.283099 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:48:09.286742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:48:09.287282 ==
4522 11:48:09.287619 DQS Delay:
4523 11:48:09.289883 DQS0 = 0, DQS1 = 0
4524 11:48:09.290293 DQM Delay:
4525 11:48:09.293397 DQM0 = 45, DQM1 = 36
4526 11:48:09.293808 DQ Delay:
4527 11:48:09.296932 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4528 11:48:09.299922 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4529 11:48:09.303352 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4530 11:48:09.306569 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4531 11:48:09.307035
4532 11:48:09.307376
4533 11:48:09.307683 ==
4534 11:48:09.310234 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 11:48:09.313490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 11:48:09.313909 ==
4537 11:48:09.314239
4538 11:48:09.316867
4539 11:48:09.317275 TX Vref Scan disable
4540 11:48:09.320067 == TX Byte 0 ==
4541 11:48:09.323930 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4542 11:48:09.327209 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4543 11:48:09.330326 == TX Byte 1 ==
4544 11:48:09.333766 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4545 11:48:09.336603 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4546 11:48:09.337147 ==
4547 11:48:09.340596 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 11:48:09.347408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 11:48:09.347824 ==
4550 11:48:09.348154
4551 11:48:09.348459
4552 11:48:09.348751 TX Vref Scan disable
4553 11:48:09.351451 == TX Byte 0 ==
4554 11:48:09.354756 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 11:48:09.358370 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 11:48:09.361556 == TX Byte 1 ==
4557 11:48:09.364862 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4558 11:48:09.368290 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4559 11:48:09.372055
4560 11:48:09.372514 [DATLAT]
4561 11:48:09.372857 Freq=600, CH1 RK0
4562 11:48:09.373166
4563 11:48:09.374596 DATLAT Default: 0x9
4564 11:48:09.375050 0, 0xFFFF, sum = 0
4565 11:48:09.377823 1, 0xFFFF, sum = 0
4566 11:48:09.378240 2, 0xFFFF, sum = 0
4567 11:48:09.381634 3, 0xFFFF, sum = 0
4568 11:48:09.382052 4, 0xFFFF, sum = 0
4569 11:48:09.384846 5, 0xFFFF, sum = 0
4570 11:48:09.385261 6, 0xFFFF, sum = 0
4571 11:48:09.388073 7, 0xFFFF, sum = 0
4572 11:48:09.388492 8, 0x0, sum = 1
4573 11:48:09.391256 9, 0x0, sum = 2
4574 11:48:09.391674 10, 0x0, sum = 3
4575 11:48:09.394644 11, 0x0, sum = 4
4576 11:48:09.395150 best_step = 9
4577 11:48:09.395490
4578 11:48:09.395859 ==
4579 11:48:09.398473 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 11:48:09.404787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 11:48:09.405202 ==
4582 11:48:09.405528 RX Vref Scan: 1
4583 11:48:09.405829
4584 11:48:09.408177 RX Vref 0 -> 0, step: 1
4585 11:48:09.408589
4586 11:48:09.411968 RX Delay -195 -> 252, step: 8
4587 11:48:09.412377
4588 11:48:09.414778 Set Vref, RX VrefLevel [Byte0]: 54
4589 11:48:09.418155 [Byte1]: 53
4590 11:48:09.418648
4591 11:48:09.421233 Final RX Vref Byte 0 = 54 to rank0
4592 11:48:09.424704 Final RX Vref Byte 1 = 53 to rank0
4593 11:48:09.428674 Final RX Vref Byte 0 = 54 to rank1
4594 11:48:09.431331 Final RX Vref Byte 1 = 53 to rank1==
4595 11:48:09.434601 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 11:48:09.437772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 11:48:09.437859 ==
4598 11:48:09.441494 DQS Delay:
4599 11:48:09.441578 DQS0 = 0, DQS1 = 0
4600 11:48:09.441664 DQM Delay:
4601 11:48:09.444657 DQM0 = 41, DQM1 = 34
4602 11:48:09.444742 DQ Delay:
4603 11:48:09.448071 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4604 11:48:09.451233 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4605 11:48:09.454783 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4606 11:48:09.458338 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4607 11:48:09.458445
4608 11:48:09.458554
4609 11:48:09.468253 [DQSOSCAuto] RK0, (LSB)MR18= 0x460c, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4610 11:48:09.468385 CH1 RK0: MR19=808, MR18=460C
4611 11:48:09.474404 CH1_RK0: MR19=0x808, MR18=0x460C, DQSOSC=396, MR23=63, INC=167, DEC=111
4612 11:48:09.474489
4613 11:48:09.477920 ----->DramcWriteLeveling(PI) begin...
4614 11:48:09.478006 ==
4615 11:48:09.481411 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 11:48:09.488191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 11:48:09.488276 ==
4618 11:48:09.491130 Write leveling (Byte 0): 29 => 29
4619 11:48:09.494511 Write leveling (Byte 1): 30 => 30
4620 11:48:09.494595 DramcWriteLeveling(PI) end<-----
4621 11:48:09.494681
4622 11:48:09.497815 ==
4623 11:48:09.501237 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 11:48:09.505052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 11:48:09.505132 ==
4626 11:48:09.507941 [Gating] SW mode calibration
4627 11:48:09.514608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4628 11:48:09.517588 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4629 11:48:09.524379 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 11:48:09.527814 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 11:48:09.530977 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4632 11:48:09.537800 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
4633 11:48:09.541115 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 11:48:09.544395 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 11:48:09.551346 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 11:48:09.554622 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 11:48:09.557801 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 11:48:09.561787 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 11:48:09.567994 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 11:48:09.571716 0 10 12 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
4641 11:48:09.574739 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4642 11:48:09.581125 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 11:48:09.585231 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 11:48:09.588122 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 11:48:09.595149 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 11:48:09.598000 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 11:48:09.601763 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 11:48:09.608794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4649 11:48:09.611806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:48:09.614832 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:48:09.621619 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:48:09.624897 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:48:09.628557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 11:48:09.631919 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 11:48:09.638493 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 11:48:09.641515 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 11:48:09.645006 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 11:48:09.651819 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 11:48:09.655078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 11:48:09.658235 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 11:48:09.665488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 11:48:09.668571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 11:48:09.671697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 11:48:09.678274 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4665 11:48:09.678379 Total UI for P1: 0, mck2ui 16
4666 11:48:09.685076 best dqsien dly found for B0: ( 0, 13, 10)
4667 11:48:09.688771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4668 11:48:09.691810 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:48:09.695444 Total UI for P1: 0, mck2ui 16
4670 11:48:09.698399 best dqsien dly found for B1: ( 0, 13, 14)
4671 11:48:09.701956 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4672 11:48:09.705315 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4673 11:48:09.705423
4674 11:48:09.708631 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4675 11:48:09.714901 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4676 11:48:09.715034 [Gating] SW calibration Done
4677 11:48:09.715138 ==
4678 11:48:09.718779 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 11:48:09.725388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 11:48:09.725561 ==
4681 11:48:09.725698 RX Vref Scan: 0
4682 11:48:09.725824
4683 11:48:09.728531 RX Vref 0 -> 0, step: 1
4684 11:48:09.728727
4685 11:48:09.731669 RX Delay -230 -> 252, step: 16
4686 11:48:09.734968 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4687 11:48:09.738629 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4688 11:48:09.744880 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4689 11:48:09.748613 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4690 11:48:09.751743 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4691 11:48:09.755543 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4692 11:48:09.758994 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4693 11:48:09.765249 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4694 11:48:09.768239 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4695 11:48:09.771734 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4696 11:48:09.775257 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4697 11:48:09.782054 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4698 11:48:09.785292 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4699 11:48:09.788630 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4700 11:48:09.791949 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4701 11:48:09.794943 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4702 11:48:09.798774 ==
4703 11:48:09.801784 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 11:48:09.804960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 11:48:09.805041 ==
4706 11:48:09.805105 DQS Delay:
4707 11:48:09.808453 DQS0 = 0, DQS1 = 0
4708 11:48:09.808533 DQM Delay:
4709 11:48:09.811604 DQM0 = 42, DQM1 = 37
4710 11:48:09.811685 DQ Delay:
4711 11:48:09.815529 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4712 11:48:09.818726 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4713 11:48:09.821807 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4714 11:48:09.825527 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4715 11:48:09.825608
4716 11:48:09.825671
4717 11:48:09.825730 ==
4718 11:48:09.828906 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 11:48:09.831881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 11:48:09.831962 ==
4721 11:48:09.832026
4722 11:48:09.832085
4723 11:48:09.835088 TX Vref Scan disable
4724 11:48:09.838902 == TX Byte 0 ==
4725 11:48:09.841572 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4726 11:48:09.845050 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4727 11:48:09.848230 == TX Byte 1 ==
4728 11:48:09.851889 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4729 11:48:09.855023 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4730 11:48:09.855113 ==
4731 11:48:09.858751 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 11:48:09.861787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 11:48:09.865117 ==
4734 11:48:09.865202
4735 11:48:09.865267
4736 11:48:09.865326 TX Vref Scan disable
4737 11:48:09.868826 == TX Byte 0 ==
4738 11:48:09.871964 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4739 11:48:09.875694 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4740 11:48:09.879040 == TX Byte 1 ==
4741 11:48:09.882167 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4742 11:48:09.885669 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4743 11:48:09.889155
4744 11:48:09.889241 [DATLAT]
4745 11:48:09.889312 Freq=600, CH1 RK1
4746 11:48:09.889404
4747 11:48:09.892306 DATLAT Default: 0x9
4748 11:48:09.892393 0, 0xFFFF, sum = 0
4749 11:48:09.895743 1, 0xFFFF, sum = 0
4750 11:48:09.895838 2, 0xFFFF, sum = 0
4751 11:48:09.899264 3, 0xFFFF, sum = 0
4752 11:48:09.899367 4, 0xFFFF, sum = 0
4753 11:48:09.901995 5, 0xFFFF, sum = 0
4754 11:48:09.905536 6, 0xFFFF, sum = 0
4755 11:48:09.905653 7, 0xFFFF, sum = 0
4756 11:48:09.905744 8, 0x0, sum = 1
4757 11:48:09.908785 9, 0x0, sum = 2
4758 11:48:09.908909 10, 0x0, sum = 3
4759 11:48:09.912454 11, 0x0, sum = 4
4760 11:48:09.912578 best_step = 9
4761 11:48:09.912703
4762 11:48:09.912796 ==
4763 11:48:09.915276 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 11:48:09.922337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 11:48:09.922490 ==
4766 11:48:09.922611 RX Vref Scan: 0
4767 11:48:09.922724
4768 11:48:09.926067 RX Vref 0 -> 0, step: 1
4769 11:48:09.926238
4770 11:48:09.928844 RX Delay -179 -> 252, step: 8
4771 11:48:09.932017 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4772 11:48:09.938842 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4773 11:48:09.941995 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4774 11:48:09.945738 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4775 11:48:09.948995 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4776 11:48:09.952283 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4777 11:48:09.959664 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4778 11:48:09.962668 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4779 11:48:09.965908 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4780 11:48:09.969158 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4781 11:48:09.975635 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4782 11:48:09.979613 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4783 11:48:09.982397 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4784 11:48:09.985642 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4785 11:48:09.989684 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4786 11:48:09.995680 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4787 11:48:09.996112 ==
4788 11:48:09.999353 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 11:48:10.002408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 11:48:10.002845 ==
4791 11:48:10.003333 DQS Delay:
4792 11:48:10.006261 DQS0 = 0, DQS1 = 0
4793 11:48:10.006695 DQM Delay:
4794 11:48:10.009002 DQM0 = 38, DQM1 = 32
4795 11:48:10.009411 DQ Delay:
4796 11:48:10.012590 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4797 11:48:10.015702 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4798 11:48:10.018882 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4799 11:48:10.022616 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4800 11:48:10.022695
4801 11:48:10.022759
4802 11:48:10.028764 [DQSOSCAuto] RK1, (LSB)MR18= 0x3948, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4803 11:48:10.032932 CH1 RK1: MR19=808, MR18=3948
4804 11:48:10.039134 CH1_RK1: MR19=0x808, MR18=0x3948, DQSOSC=396, MR23=63, INC=167, DEC=111
4805 11:48:10.042354 [RxdqsGatingPostProcess] freq 600
4806 11:48:10.048952 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4807 11:48:10.052486 Pre-setting of DQS Precalculation
4808 11:48:10.055639 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4809 11:48:10.062184 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4810 11:48:10.068901 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4811 11:48:10.069002
4812 11:48:10.069080
4813 11:48:10.072219 [Calibration Summary] 1200 Mbps
4814 11:48:10.075659 CH 0, Rank 0
4815 11:48:10.075768 SW Impedance : PASS
4816 11:48:10.078947 DUTY Scan : NO K
4817 11:48:10.082668 ZQ Calibration : PASS
4818 11:48:10.082829 Jitter Meter : NO K
4819 11:48:10.085702 CBT Training : PASS
4820 11:48:10.089585 Write leveling : PASS
4821 11:48:10.089737 RX DQS gating : PASS
4822 11:48:10.092900 RX DQ/DQS(RDDQC) : PASS
4823 11:48:10.093086 TX DQ/DQS : PASS
4824 11:48:10.096051 RX DATLAT : PASS
4825 11:48:10.099501 RX DQ/DQS(Engine): PASS
4826 11:48:10.099703 TX OE : NO K
4827 11:48:10.102235 All Pass.
4828 11:48:10.102435
4829 11:48:10.102592 CH 0, Rank 1
4830 11:48:10.106057 SW Impedance : PASS
4831 11:48:10.106297 DUTY Scan : NO K
4832 11:48:10.109716 ZQ Calibration : PASS
4833 11:48:10.112681 Jitter Meter : NO K
4834 11:48:10.113051 CBT Training : PASS
4835 11:48:10.116063 Write leveling : PASS
4836 11:48:10.119528 RX DQS gating : PASS
4837 11:48:10.119946 RX DQ/DQS(RDDQC) : PASS
4838 11:48:10.122972 TX DQ/DQS : PASS
4839 11:48:10.125827 RX DATLAT : PASS
4840 11:48:10.126245 RX DQ/DQS(Engine): PASS
4841 11:48:10.129974 TX OE : NO K
4842 11:48:10.130532 All Pass.
4843 11:48:10.130932
4844 11:48:10.132700 CH 1, Rank 0
4845 11:48:10.133120 SW Impedance : PASS
4846 11:48:10.136440 DUTY Scan : NO K
4847 11:48:10.136873 ZQ Calibration : PASS
4848 11:48:10.139655 Jitter Meter : NO K
4849 11:48:10.143178 CBT Training : PASS
4850 11:48:10.143597 Write leveling : PASS
4851 11:48:10.146331 RX DQS gating : PASS
4852 11:48:10.149558 RX DQ/DQS(RDDQC) : PASS
4853 11:48:10.149977 TX DQ/DQS : PASS
4854 11:48:10.152655 RX DATLAT : PASS
4855 11:48:10.156075 RX DQ/DQS(Engine): PASS
4856 11:48:10.156495 TX OE : NO K
4857 11:48:10.159803 All Pass.
4858 11:48:10.160222
4859 11:48:10.160556 CH 1, Rank 1
4860 11:48:10.162942 SW Impedance : PASS
4861 11:48:10.163365 DUTY Scan : NO K
4862 11:48:10.166245 ZQ Calibration : PASS
4863 11:48:10.169790 Jitter Meter : NO K
4864 11:48:10.170207 CBT Training : PASS
4865 11:48:10.173144 Write leveling : PASS
4866 11:48:10.176344 RX DQS gating : PASS
4867 11:48:10.176762 RX DQ/DQS(RDDQC) : PASS
4868 11:48:10.179142 TX DQ/DQS : PASS
4869 11:48:10.179561 RX DATLAT : PASS
4870 11:48:10.182635 RX DQ/DQS(Engine): PASS
4871 11:48:10.185775 TX OE : NO K
4872 11:48:10.186196 All Pass.
4873 11:48:10.186533
4874 11:48:10.189441 DramC Write-DBI off
4875 11:48:10.189875 PER_BANK_REFRESH: Hybrid Mode
4876 11:48:10.192551 TX_TRACKING: ON
4877 11:48:10.202384 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4878 11:48:10.206367 [FAST_K] Save calibration result to emmc
4879 11:48:10.209452 dramc_set_vcore_voltage set vcore to 662500
4880 11:48:10.209972 Read voltage for 933, 3
4881 11:48:10.212789 Vio18 = 0
4882 11:48:10.213231 Vcore = 662500
4883 11:48:10.213567 Vdram = 0
4884 11:48:10.215839 Vddq = 0
4885 11:48:10.216255 Vmddr = 0
4886 11:48:10.219390 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4887 11:48:10.226103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4888 11:48:10.229290 MEM_TYPE=3, freq_sel=17
4889 11:48:10.233084 sv_algorithm_assistance_LP4_1600
4890 11:48:10.236198 ============ PULL DRAM RESETB DOWN ============
4891 11:48:10.239897 ========== PULL DRAM RESETB DOWN end =========
4892 11:48:10.242601 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4893 11:48:10.246368 ===================================
4894 11:48:10.249477 LPDDR4 DRAM CONFIGURATION
4895 11:48:10.252826 ===================================
4896 11:48:10.256387 EX_ROW_EN[0] = 0x0
4897 11:48:10.256807 EX_ROW_EN[1] = 0x0
4898 11:48:10.259802 LP4Y_EN = 0x0
4899 11:48:10.260219 WORK_FSP = 0x0
4900 11:48:10.262903 WL = 0x3
4901 11:48:10.263330 RL = 0x3
4902 11:48:10.266077 BL = 0x2
4903 11:48:10.266498 RPST = 0x0
4904 11:48:10.269743 RD_PRE = 0x0
4905 11:48:10.270165 WR_PRE = 0x1
4906 11:48:10.272964 WR_PST = 0x0
4907 11:48:10.273383 DBI_WR = 0x0
4908 11:48:10.276558 DBI_RD = 0x0
4909 11:48:10.276978 OTF = 0x1
4910 11:48:10.279733 ===================================
4911 11:48:10.283124 ===================================
4912 11:48:10.286551 ANA top config
4913 11:48:10.290090 ===================================
4914 11:48:10.293586 DLL_ASYNC_EN = 0
4915 11:48:10.294021 ALL_SLAVE_EN = 1
4916 11:48:10.296443 NEW_RANK_MODE = 1
4917 11:48:10.300115 DLL_IDLE_MODE = 1
4918 11:48:10.302979 LP45_APHY_COMB_EN = 1
4919 11:48:10.303452 TX_ODT_DIS = 1
4920 11:48:10.306160 NEW_8X_MODE = 1
4921 11:48:10.310092 ===================================
4922 11:48:10.313246 ===================================
4923 11:48:10.316636 data_rate = 1866
4924 11:48:10.319876 CKR = 1
4925 11:48:10.323370 DQ_P2S_RATIO = 8
4926 11:48:10.326270 ===================================
4927 11:48:10.329859 CA_P2S_RATIO = 8
4928 11:48:10.330281 DQ_CA_OPEN = 0
4929 11:48:10.333299 DQ_SEMI_OPEN = 0
4930 11:48:10.336396 CA_SEMI_OPEN = 0
4931 11:48:10.339697 CA_FULL_RATE = 0
4932 11:48:10.343366 DQ_CKDIV4_EN = 1
4933 11:48:10.346306 CA_CKDIV4_EN = 1
4934 11:48:10.346724 CA_PREDIV_EN = 0
4935 11:48:10.350326 PH8_DLY = 0
4936 11:48:10.353270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4937 11:48:10.356290 DQ_AAMCK_DIV = 4
4938 11:48:10.359713 CA_AAMCK_DIV = 4
4939 11:48:10.362979 CA_ADMCK_DIV = 4
4940 11:48:10.363402 DQ_TRACK_CA_EN = 0
4941 11:48:10.366162 CA_PICK = 933
4942 11:48:10.369594 CA_MCKIO = 933
4943 11:48:10.373203 MCKIO_SEMI = 0
4944 11:48:10.376897 PLL_FREQ = 3732
4945 11:48:10.379646 DQ_UI_PI_RATIO = 32
4946 11:48:10.383195 CA_UI_PI_RATIO = 0
4947 11:48:10.386694 ===================================
4948 11:48:10.387147 ===================================
4949 11:48:10.389695 memory_type:LPDDR4
4950 11:48:10.392838 GP_NUM : 10
4951 11:48:10.393264 SRAM_EN : 1
4952 11:48:10.396133 MD32_EN : 0
4953 11:48:10.399949 ===================================
4954 11:48:10.402939 [ANA_INIT] >>>>>>>>>>>>>>
4955 11:48:10.406259 <<<<<< [CONFIGURE PHASE]: ANA_TX
4956 11:48:10.409373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4957 11:48:10.412713 ===================================
4958 11:48:10.413258 data_rate = 1866,PCW = 0X8f00
4959 11:48:10.416406 ===================================
4960 11:48:10.419644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4961 11:48:10.426215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 11:48:10.432790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 11:48:10.436210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4964 11:48:10.439423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4965 11:48:10.443149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4966 11:48:10.446259 [ANA_INIT] flow start
4967 11:48:10.449674 [ANA_INIT] PLL >>>>>>>>
4968 11:48:10.450093 [ANA_INIT] PLL <<<<<<<<
4969 11:48:10.452958 [ANA_INIT] MIDPI >>>>>>>>
4970 11:48:10.456100 [ANA_INIT] MIDPI <<<<<<<<
4971 11:48:10.456519 [ANA_INIT] DLL >>>>>>>>
4972 11:48:10.459473 [ANA_INIT] flow end
4973 11:48:10.462836 ============ LP4 DIFF to SE enter ============
4974 11:48:10.465956 ============ LP4 DIFF to SE exit ============
4975 11:48:10.469486 [ANA_INIT] <<<<<<<<<<<<<
4976 11:48:10.472851 [Flow] Enable top DCM control >>>>>
4977 11:48:10.475969 [Flow] Enable top DCM control <<<<<
4978 11:48:10.479374 Enable DLL master slave shuffle
4979 11:48:10.485985 ==============================================================
4980 11:48:10.486405 Gating Mode config
4981 11:48:10.492964 ==============================================================
4982 11:48:10.493388 Config description:
4983 11:48:10.502663 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4984 11:48:10.509438 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4985 11:48:10.516061 SELPH_MODE 0: By rank 1: By Phase
4986 11:48:10.519355 ==============================================================
4987 11:48:10.522550 GAT_TRACK_EN = 1
4988 11:48:10.526095 RX_GATING_MODE = 2
4989 11:48:10.529523 RX_GATING_TRACK_MODE = 2
4990 11:48:10.532508 SELPH_MODE = 1
4991 11:48:10.535996 PICG_EARLY_EN = 1
4992 11:48:10.539224 VALID_LAT_VALUE = 1
4993 11:48:10.542598 ==============================================================
4994 11:48:10.546243 Enter into Gating configuration >>>>
4995 11:48:10.549531 Exit from Gating configuration <<<<
4996 11:48:10.552998 Enter into DVFS_PRE_config >>>>>
4997 11:48:10.566161 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4998 11:48:10.569809 Exit from DVFS_PRE_config <<<<<
4999 11:48:10.570221 Enter into PICG configuration >>>>
5000 11:48:10.572843 Exit from PICG configuration <<<<
5001 11:48:10.576586 [RX_INPUT] configuration >>>>>
5002 11:48:10.579542 [RX_INPUT] configuration <<<<<
5003 11:48:10.586801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5004 11:48:10.589981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5005 11:48:10.596676 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 11:48:10.602983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 11:48:10.609993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 11:48:10.616473 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 11:48:10.620130 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5010 11:48:10.623329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5011 11:48:10.626590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5012 11:48:10.632770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5013 11:48:10.636789 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5014 11:48:10.639851 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 11:48:10.642989 ===================================
5016 11:48:10.646352 LPDDR4 DRAM CONFIGURATION
5017 11:48:10.649916 ===================================
5018 11:48:10.650443 EX_ROW_EN[0] = 0x0
5019 11:48:10.653320 EX_ROW_EN[1] = 0x0
5020 11:48:10.656798 LP4Y_EN = 0x0
5021 11:48:10.657260 WORK_FSP = 0x0
5022 11:48:10.660493 WL = 0x3
5023 11:48:10.661056 RL = 0x3
5024 11:48:10.663743 BL = 0x2
5025 11:48:10.664205 RPST = 0x0
5026 11:48:10.666837 RD_PRE = 0x0
5027 11:48:10.667435 WR_PRE = 0x1
5028 11:48:10.670256 WR_PST = 0x0
5029 11:48:10.670808 DBI_WR = 0x0
5030 11:48:10.673498 DBI_RD = 0x0
5031 11:48:10.674064 OTF = 0x1
5032 11:48:10.676697 ===================================
5033 11:48:10.680026 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5034 11:48:10.686567 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5035 11:48:10.689954 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 11:48:10.693626 ===================================
5037 11:48:10.697027 LPDDR4 DRAM CONFIGURATION
5038 11:48:10.700220 ===================================
5039 11:48:10.700679 EX_ROW_EN[0] = 0x10
5040 11:48:10.703514 EX_ROW_EN[1] = 0x0
5041 11:48:10.703971 LP4Y_EN = 0x0
5042 11:48:10.707114 WORK_FSP = 0x0
5043 11:48:10.707566 WL = 0x3
5044 11:48:10.710270 RL = 0x3
5045 11:48:10.710678 BL = 0x2
5046 11:48:10.713252 RPST = 0x0
5047 11:48:10.713662 RD_PRE = 0x0
5048 11:48:10.716668 WR_PRE = 0x1
5049 11:48:10.717080 WR_PST = 0x0
5050 11:48:10.719963 DBI_WR = 0x0
5051 11:48:10.720375 DBI_RD = 0x0
5052 11:48:10.723581 OTF = 0x1
5053 11:48:10.726521 ===================================
5054 11:48:10.733031 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5055 11:48:10.736438 nWR fixed to 30
5056 11:48:10.740036 [ModeRegInit_LP4] CH0 RK0
5057 11:48:10.740455 [ModeRegInit_LP4] CH0 RK1
5058 11:48:10.743086 [ModeRegInit_LP4] CH1 RK0
5059 11:48:10.746729 [ModeRegInit_LP4] CH1 RK1
5060 11:48:10.747209 match AC timing 9
5061 11:48:10.753241 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5062 11:48:10.756722 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5063 11:48:10.760561 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5064 11:48:10.766926 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5065 11:48:10.770125 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5066 11:48:10.770548 ==
5067 11:48:10.773335 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 11:48:10.777075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 11:48:10.777591 ==
5070 11:48:10.783452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 11:48:10.790264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5072 11:48:10.794181 [CA 0] Center 38 (8~69) winsize 62
5073 11:48:10.796645 [CA 1] Center 38 (8~69) winsize 62
5074 11:48:10.800032 [CA 2] Center 35 (5~66) winsize 62
5075 11:48:10.803314 [CA 3] Center 35 (4~66) winsize 63
5076 11:48:10.806932 [CA 4] Center 34 (4~64) winsize 61
5077 11:48:10.810286 [CA 5] Center 34 (4~64) winsize 61
5078 11:48:10.810707
5079 11:48:10.813403 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5080 11:48:10.813826
5081 11:48:10.816579 [CATrainingPosCal] consider 1 rank data
5082 11:48:10.820073 u2DelayCellTimex100 = 270/100 ps
5083 11:48:10.823166 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 11:48:10.826771 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 11:48:10.830043 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5086 11:48:10.833331 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5087 11:48:10.836898 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5088 11:48:10.840312 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 11:48:10.840819
5090 11:48:10.843441 CA PerBit enable=1, Macro0, CA PI delay=34
5091 11:48:10.847218
5092 11:48:10.847655 [CBTSetCACLKResult] CA Dly = 34
5093 11:48:10.850496 CS Dly: 6 (0~37)
5094 11:48:10.850971 ==
5095 11:48:10.853453 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 11:48:10.857621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:48:10.858183 ==
5098 11:48:10.863597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 11:48:10.870962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 11:48:10.873521 [CA 0] Center 38 (7~69) winsize 63
5101 11:48:10.877317 [CA 1] Center 38 (7~69) winsize 63
5102 11:48:10.880491 [CA 2] Center 35 (5~66) winsize 62
5103 11:48:10.884080 [CA 3] Center 35 (5~66) winsize 62
5104 11:48:10.887197 [CA 4] Center 34 (4~64) winsize 61
5105 11:48:10.890391 [CA 5] Center 33 (3~64) winsize 62
5106 11:48:10.890952
5107 11:48:10.894247 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 11:48:10.894780
5109 11:48:10.897126 [CATrainingPosCal] consider 2 rank data
5110 11:48:10.900582 u2DelayCellTimex100 = 270/100 ps
5111 11:48:10.903857 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5112 11:48:10.906936 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5113 11:48:10.910075 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5114 11:48:10.913720 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5115 11:48:10.916612 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5116 11:48:10.920676 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5117 11:48:10.921100
5118 11:48:10.923699 CA PerBit enable=1, Macro0, CA PI delay=34
5119 11:48:10.926710
5120 11:48:10.927176 [CBTSetCACLKResult] CA Dly = 34
5121 11:48:10.930056 CS Dly: 7 (0~39)
5122 11:48:10.930492
5123 11:48:10.933590 ----->DramcWriteLeveling(PI) begin...
5124 11:48:10.934029 ==
5125 11:48:10.936935 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 11:48:10.939980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 11:48:10.940448 ==
5128 11:48:10.943393 Write leveling (Byte 0): 34 => 34
5129 11:48:10.946672 Write leveling (Byte 1): 25 => 25
5130 11:48:10.949986 DramcWriteLeveling(PI) end<-----
5131 11:48:10.950422
5132 11:48:10.950902 ==
5133 11:48:10.953279 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 11:48:10.956657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 11:48:10.959843 ==
5136 11:48:10.960284 [Gating] SW mode calibration
5137 11:48:10.966575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5138 11:48:10.972992 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5139 11:48:10.976314 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5140 11:48:10.983366 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5141 11:48:10.986734 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 11:48:10.989911 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 11:48:10.996859 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 11:48:11.000113 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 11:48:11.003294 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 11:48:11.009764 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
5147 11:48:11.013697 0 15 0 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
5148 11:48:11.016561 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5149 11:48:11.023228 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 11:48:11.026892 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 11:48:11.030320 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 11:48:11.033350 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 11:48:11.040049 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 11:48:11.043304 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5155 11:48:11.046509 1 0 0 | B1->B0 | 3131 4040 | 1 0 | (1 1) (0 0)
5156 11:48:11.053218 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 11:48:11.056587 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 11:48:11.060040 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 11:48:11.066192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 11:48:11.069919 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 11:48:11.073218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 11:48:11.080092 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5163 11:48:11.083039 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5164 11:48:11.086819 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 11:48:11.093405 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:48:11.096058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:48:11.099676 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:48:11.106550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 11:48:11.109512 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 11:48:11.112847 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 11:48:11.119569 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 11:48:11.123040 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 11:48:11.126130 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 11:48:11.133032 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 11:48:11.136074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 11:48:11.139725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 11:48:11.142891 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 11:48:11.149610 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5179 11:48:11.153306 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5180 11:48:11.156789 Total UI for P1: 0, mck2ui 16
5181 11:48:11.159515 best dqsien dly found for B0: ( 1, 2, 30)
5182 11:48:11.162997 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 11:48:11.166464 Total UI for P1: 0, mck2ui 16
5184 11:48:11.169624 best dqsien dly found for B1: ( 1, 2, 30)
5185 11:48:11.173110 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5186 11:48:11.176355 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5187 11:48:11.176780
5188 11:48:11.183412 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5189 11:48:11.186552 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5190 11:48:11.187003 [Gating] SW calibration Done
5191 11:48:11.190029 ==
5192 11:48:11.190455 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 11:48:11.196669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 11:48:11.197090 ==
5195 11:48:11.197429 RX Vref Scan: 0
5196 11:48:11.197742
5197 11:48:11.200314 RX Vref 0 -> 0, step: 1
5198 11:48:11.200733
5199 11:48:11.203459 RX Delay -80 -> 252, step: 8
5200 11:48:11.206958 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5201 11:48:11.210171 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5202 11:48:11.213118 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5203 11:48:11.216324 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5204 11:48:11.223340 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5205 11:48:11.226807 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5206 11:48:11.229983 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5207 11:48:11.233235 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5208 11:48:11.236871 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5209 11:48:11.243493 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5210 11:48:11.246471 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5211 11:48:11.249813 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5212 11:48:11.254034 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5213 11:48:11.256923 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5214 11:48:11.260182 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5215 11:48:11.266936 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5216 11:48:11.267349 ==
5217 11:48:11.270292 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 11:48:11.273412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 11:48:11.273867 ==
5220 11:48:11.274198 DQS Delay:
5221 11:48:11.276521 DQS0 = 0, DQS1 = 0
5222 11:48:11.277118 DQM Delay:
5223 11:48:11.280185 DQM0 = 97, DQM1 = 87
5224 11:48:11.280596 DQ Delay:
5225 11:48:11.283136 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5226 11:48:11.286807 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5227 11:48:11.289966 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5228 11:48:11.293216 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5229 11:48:11.293751
5230 11:48:11.294275
5231 11:48:11.294737 ==
5232 11:48:11.296768 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 11:48:11.300440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 11:48:11.300872 ==
5235 11:48:11.301204
5236 11:48:11.301511
5237 11:48:11.303396 TX Vref Scan disable
5238 11:48:11.306698 == TX Byte 0 ==
5239 11:48:11.310132 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5240 11:48:11.313708 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5241 11:48:11.316609 == TX Byte 1 ==
5242 11:48:11.320174 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5243 11:48:11.323397 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5244 11:48:11.323808 ==
5245 11:48:11.326517 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 11:48:11.333372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 11:48:11.333812 ==
5248 11:48:11.334289
5249 11:48:11.334646
5250 11:48:11.335032 TX Vref Scan disable
5251 11:48:11.337643 == TX Byte 0 ==
5252 11:48:11.340858 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5253 11:48:11.344228 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5254 11:48:11.347610 == TX Byte 1 ==
5255 11:48:11.350836 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5256 11:48:11.354403 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5257 11:48:11.357434
5258 11:48:11.357845 [DATLAT]
5259 11:48:11.358176 Freq=933, CH0 RK0
5260 11:48:11.358487
5261 11:48:11.360931 DATLAT Default: 0xd
5262 11:48:11.361284 0, 0xFFFF, sum = 0
5263 11:48:11.364004 1, 0xFFFF, sum = 0
5264 11:48:11.364421 2, 0xFFFF, sum = 0
5265 11:48:11.367828 3, 0xFFFF, sum = 0
5266 11:48:11.368252 4, 0xFFFF, sum = 0
5267 11:48:11.370910 5, 0xFFFF, sum = 0
5268 11:48:11.371334 6, 0xFFFF, sum = 0
5269 11:48:11.374454 7, 0xFFFF, sum = 0
5270 11:48:11.374916 8, 0xFFFF, sum = 0
5271 11:48:11.377768 9, 0xFFFF, sum = 0
5272 11:48:11.378185 10, 0x0, sum = 1
5273 11:48:11.380932 11, 0x0, sum = 2
5274 11:48:11.381349 12, 0x0, sum = 3
5275 11:48:11.384665 13, 0x0, sum = 4
5276 11:48:11.385082 best_step = 11
5277 11:48:11.385410
5278 11:48:11.385714 ==
5279 11:48:11.387862 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 11:48:11.394196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 11:48:11.394610 ==
5282 11:48:11.394985 RX Vref Scan: 1
5283 11:48:11.395301
5284 11:48:11.397746 RX Vref 0 -> 0, step: 1
5285 11:48:11.398156
5286 11:48:11.401046 RX Delay -61 -> 252, step: 4
5287 11:48:11.401458
5288 11:48:11.404177 Set Vref, RX VrefLevel [Byte0]: 53
5289 11:48:11.407913 [Byte1]: 51
5290 11:48:11.408323
5291 11:48:11.411408 Final RX Vref Byte 0 = 53 to rank0
5292 11:48:11.414517 Final RX Vref Byte 1 = 51 to rank0
5293 11:48:11.417593 Final RX Vref Byte 0 = 53 to rank1
5294 11:48:11.420835 Final RX Vref Byte 1 = 51 to rank1==
5295 11:48:11.424765 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 11:48:11.427902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 11:48:11.428313 ==
5298 11:48:11.431642 DQS Delay:
5299 11:48:11.432046 DQS0 = 0, DQS1 = 0
5300 11:48:11.432367 DQM Delay:
5301 11:48:11.434196 DQM0 = 96, DQM1 = 87
5302 11:48:11.434712 DQ Delay:
5303 11:48:11.437793 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5304 11:48:11.441091 DQ4 =98, DQ5 =84, DQ6 =104, DQ7 =102
5305 11:48:11.444335 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =80
5306 11:48:11.448025 DQ12 =92, DQ13 =88, DQ14 =98, DQ15 =98
5307 11:48:11.448446
5308 11:48:11.448777
5309 11:48:11.458060 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5310 11:48:11.458479 CH0 RK0: MR19=504, MR18=14FF
5311 11:48:11.464567 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5312 11:48:11.465153
5313 11:48:11.468385 ----->DramcWriteLeveling(PI) begin...
5314 11:48:11.468788 ==
5315 11:48:11.471285 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 11:48:11.477945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 11:48:11.478309 ==
5318 11:48:11.481178 Write leveling (Byte 0): 30 => 30
5319 11:48:11.484341 Write leveling (Byte 1): 29 => 29
5320 11:48:11.484655 DramcWriteLeveling(PI) end<-----
5321 11:48:11.484886
5322 11:48:11.487975 ==
5323 11:48:11.491715 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 11:48:11.495083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 11:48:11.495560 ==
5326 11:48:11.498473 [Gating] SW mode calibration
5327 11:48:11.504899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5328 11:48:11.507987 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5329 11:48:11.515031 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5330 11:48:11.517939 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5331 11:48:11.521328 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 11:48:11.527830 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 11:48:11.531445 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 11:48:11.534842 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 11:48:11.541259 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 11:48:11.544891 0 14 28 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (1 0)
5337 11:48:11.548242 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5338 11:48:11.554916 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 11:48:11.558538 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 11:48:11.561730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 11:48:11.568315 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 11:48:11.571628 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 11:48:11.575055 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 11:48:11.578242 0 15 28 | B1->B0 | 2929 3f3f | 0 0 | (0 0) (0 0)
5345 11:48:11.584751 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5346 11:48:11.588484 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 11:48:11.591301 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 11:48:11.598325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 11:48:11.601823 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 11:48:11.604942 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 11:48:11.611395 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 11:48:11.615336 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5353 11:48:11.618296 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 11:48:11.624821 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:48:11.628151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:48:11.631812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:48:11.638381 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:48:11.641531 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 11:48:11.645328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 11:48:11.648341 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 11:48:11.654747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 11:48:11.658565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 11:48:11.661962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 11:48:11.668470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 11:48:11.671560 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:48:11.675174 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:48:11.681846 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5368 11:48:11.685017 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5369 11:48:11.688935 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5370 11:48:11.691675 Total UI for P1: 0, mck2ui 16
5371 11:48:11.694977 best dqsien dly found for B0: ( 1, 2, 26)
5372 11:48:11.702168 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:48:11.702598 Total UI for P1: 0, mck2ui 16
5374 11:48:11.705277 best dqsien dly found for B1: ( 1, 2, 30)
5375 11:48:11.711579 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5376 11:48:11.715067 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5377 11:48:11.715489
5378 11:48:11.718360 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5379 11:48:11.722018 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5380 11:48:11.725275 [Gating] SW calibration Done
5381 11:48:11.725695 ==
5382 11:48:11.728303 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 11:48:11.731859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 11:48:11.732281 ==
5385 11:48:11.734956 RX Vref Scan: 0
5386 11:48:11.735383
5387 11:48:11.735821 RX Vref 0 -> 0, step: 1
5388 11:48:11.736233
5389 11:48:11.738286 RX Delay -80 -> 252, step: 8
5390 11:48:11.741960 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5391 11:48:11.745143 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5392 11:48:11.751747 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5393 11:48:11.755001 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5394 11:48:11.758464 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5395 11:48:11.762109 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5396 11:48:11.765451 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5397 11:48:11.768450 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5398 11:48:11.775540 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5399 11:48:11.778468 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5400 11:48:11.781766 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5401 11:48:11.784866 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5402 11:48:11.788534 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5403 11:48:11.791831 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5404 11:48:11.798652 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5405 11:48:11.802608 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5406 11:48:11.803195 ==
5407 11:48:11.805302 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 11:48:11.808360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 11:48:11.808829 ==
5410 11:48:11.809198 DQS Delay:
5411 11:48:11.811961 DQS0 = 0, DQS1 = 0
5412 11:48:11.812425 DQM Delay:
5413 11:48:11.815189 DQM0 = 96, DQM1 = 87
5414 11:48:11.815650 DQ Delay:
5415 11:48:11.818193 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =91
5416 11:48:11.821988 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5417 11:48:11.825500 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5418 11:48:11.829198 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5419 11:48:11.829713
5420 11:48:11.830049
5421 11:48:11.830365 ==
5422 11:48:11.831851 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 11:48:11.838357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 11:48:11.838925 ==
5425 11:48:11.839318
5426 11:48:11.839638
5427 11:48:11.839938 TX Vref Scan disable
5428 11:48:11.841570 == TX Byte 0 ==
5429 11:48:11.845245 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5430 11:48:11.848102 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5431 11:48:11.851930 == TX Byte 1 ==
5432 11:48:11.855230 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5433 11:48:11.858596 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5434 11:48:11.861837 ==
5435 11:48:11.865069 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 11:48:11.868326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 11:48:11.868751 ==
5438 11:48:11.869087
5439 11:48:11.869396
5440 11:48:11.871516 TX Vref Scan disable
5441 11:48:11.871936 == TX Byte 0 ==
5442 11:48:11.878320 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5443 11:48:11.881534 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5444 11:48:11.882073 == TX Byte 1 ==
5445 11:48:11.888283 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5446 11:48:11.891856 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5447 11:48:11.892274
5448 11:48:11.892610 [DATLAT]
5449 11:48:11.895239 Freq=933, CH0 RK1
5450 11:48:11.895659
5451 11:48:11.895992 DATLAT Default: 0xb
5452 11:48:11.898424 0, 0xFFFF, sum = 0
5453 11:48:11.898852 1, 0xFFFF, sum = 0
5454 11:48:11.901986 2, 0xFFFF, sum = 0
5455 11:48:11.902506 3, 0xFFFF, sum = 0
5456 11:48:11.904803 4, 0xFFFF, sum = 0
5457 11:48:11.905228 5, 0xFFFF, sum = 0
5458 11:48:11.908250 6, 0xFFFF, sum = 0
5459 11:48:11.908674 7, 0xFFFF, sum = 0
5460 11:48:11.911670 8, 0xFFFF, sum = 0
5461 11:48:11.912137 9, 0xFFFF, sum = 0
5462 11:48:11.915323 10, 0x0, sum = 1
5463 11:48:11.915748 11, 0x0, sum = 2
5464 11:48:11.918522 12, 0x0, sum = 3
5465 11:48:11.918987 13, 0x0, sum = 4
5466 11:48:11.921775 best_step = 11
5467 11:48:11.922257
5468 11:48:11.922777 ==
5469 11:48:11.925235 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 11:48:11.928552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 11:48:11.928975 ==
5472 11:48:11.931859 RX Vref Scan: 0
5473 11:48:11.932276
5474 11:48:11.932614 RX Vref 0 -> 0, step: 1
5475 11:48:11.932931
5476 11:48:11.934922 RX Delay -61 -> 252, step: 4
5477 11:48:11.943157 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5478 11:48:11.945371 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5479 11:48:11.948892 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5480 11:48:11.951834 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5481 11:48:11.955532 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5482 11:48:11.958941 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5483 11:48:11.965982 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5484 11:48:11.969011 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5485 11:48:11.972367 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5486 11:48:11.975864 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5487 11:48:11.979324 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5488 11:48:11.982382 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5489 11:48:11.988803 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5490 11:48:11.992229 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5491 11:48:11.995886 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5492 11:48:11.998943 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5493 11:48:11.999376 ==
5494 11:48:12.001987 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 11:48:12.005562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 11:48:12.008900 ==
5497 11:48:12.009323 DQS Delay:
5498 11:48:12.009660 DQS0 = 0, DQS1 = 0
5499 11:48:12.011944 DQM Delay:
5500 11:48:12.012364 DQM0 = 95, DQM1 = 88
5501 11:48:12.015412 DQ Delay:
5502 11:48:12.015868 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5503 11:48:12.019015 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =102
5504 11:48:12.022692 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5505 11:48:12.025593 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =94
5506 11:48:12.028991
5507 11:48:12.029440
5508 11:48:12.035852 [DQSOSCAuto] RK1, (LSB)MR18= 0x1907, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5509 11:48:12.039257 CH0 RK1: MR19=505, MR18=1907
5510 11:48:12.045775 CH0_RK1: MR19=0x505, MR18=0x1907, DQSOSC=413, MR23=63, INC=63, DEC=42
5511 11:48:12.049188 [RxdqsGatingPostProcess] freq 933
5512 11:48:12.052275 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5513 11:48:12.055477 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 11:48:12.058834 best DQS1 dly(2T, 0.5T) = (0, 10)
5515 11:48:12.062733 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 11:48:12.065563 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5517 11:48:12.068762 best DQS0 dly(2T, 0.5T) = (0, 10)
5518 11:48:12.072476 best DQS1 dly(2T, 0.5T) = (0, 10)
5519 11:48:12.076283 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5520 11:48:12.078971 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5521 11:48:12.082581 Pre-setting of DQS Precalculation
5522 11:48:12.086123 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5523 11:48:12.086678 ==
5524 11:48:12.089447 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 11:48:12.092812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 11:48:12.093371 ==
5527 11:48:12.099464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 11:48:12.105919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5529 11:48:12.109232 [CA 0] Center 36 (6~67) winsize 62
5530 11:48:12.112349 [CA 1] Center 36 (6~67) winsize 62
5531 11:48:12.115888 [CA 2] Center 34 (4~64) winsize 61
5532 11:48:12.119108 [CA 3] Center 33 (3~64) winsize 62
5533 11:48:12.122069 [CA 4] Center 33 (3~64) winsize 62
5534 11:48:12.125828 [CA 5] Center 33 (3~64) winsize 62
5535 11:48:12.125910
5536 11:48:12.129093 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5537 11:48:12.129181
5538 11:48:12.132342 [CATrainingPosCal] consider 1 rank data
5539 11:48:12.135461 u2DelayCellTimex100 = 270/100 ps
5540 11:48:12.139098 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5541 11:48:12.142294 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 11:48:12.145870 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5543 11:48:12.149286 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5544 11:48:12.152121 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5545 11:48:12.155763 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 11:48:12.155980
5547 11:48:12.162690 CA PerBit enable=1, Macro0, CA PI delay=33
5548 11:48:12.162963
5549 11:48:12.163121 [CBTSetCACLKResult] CA Dly = 33
5550 11:48:12.165649 CS Dly: 4 (0~35)
5551 11:48:12.165902 ==
5552 11:48:12.168806 Dram Type= 6, Freq= 0, CH_1, rank 1
5553 11:48:12.172282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 11:48:12.172575 ==
5555 11:48:12.179427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 11:48:12.186076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5557 11:48:12.190065 [CA 0] Center 36 (6~67) winsize 62
5558 11:48:12.192541 [CA 1] Center 36 (6~67) winsize 62
5559 11:48:12.195892 [CA 2] Center 33 (3~64) winsize 62
5560 11:48:12.199267 [CA 3] Center 33 (3~64) winsize 62
5561 11:48:12.203052 [CA 4] Center 34 (4~64) winsize 61
5562 11:48:12.206403 [CA 5] Center 32 (2~63) winsize 62
5563 11:48:12.207041
5564 11:48:12.209547 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5565 11:48:12.210026
5566 11:48:12.212730 [CATrainingPosCal] consider 2 rank data
5567 11:48:12.216789 u2DelayCellTimex100 = 270/100 ps
5568 11:48:12.219542 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 11:48:12.222889 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 11:48:12.226436 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 11:48:12.229489 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 11:48:12.232789 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 11:48:12.236123 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5574 11:48:12.236577
5575 11:48:12.243017 CA PerBit enable=1, Macro0, CA PI delay=33
5576 11:48:12.243486
5577 11:48:12.243854 [CBTSetCACLKResult] CA Dly = 33
5578 11:48:12.246176 CS Dly: 5 (0~38)
5579 11:48:12.246629
5580 11:48:12.249249 ----->DramcWriteLeveling(PI) begin...
5581 11:48:12.249670 ==
5582 11:48:12.252566 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 11:48:12.255789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 11:48:12.256217 ==
5585 11:48:12.259447 Write leveling (Byte 0): 23 => 23
5586 11:48:12.263320 Write leveling (Byte 1): 29 => 29
5587 11:48:12.266071 DramcWriteLeveling(PI) end<-----
5588 11:48:12.266580
5589 11:48:12.266985 ==
5590 11:48:12.269443 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 11:48:12.273185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 11:48:12.276274 ==
5593 11:48:12.276726 [Gating] SW mode calibration
5594 11:48:12.283032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5595 11:48:12.289432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5596 11:48:12.293086 0 14 0 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
5597 11:48:12.299978 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 11:48:12.302659 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 11:48:12.306565 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 11:48:12.312553 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 11:48:12.316147 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 11:48:12.319330 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5603 11:48:12.326560 0 14 28 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
5604 11:48:12.329367 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5605 11:48:12.332967 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 11:48:12.335970 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 11:48:12.342455 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5608 11:48:12.346178 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 11:48:12.349202 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 11:48:12.355915 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 11:48:12.359371 0 15 28 | B1->B0 | 2e2e 2b2b | 1 1 | (0 0) (0 0)
5612 11:48:12.362927 1 0 0 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
5613 11:48:12.369299 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 11:48:12.372607 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 11:48:12.375858 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 11:48:12.382440 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 11:48:12.386183 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 11:48:12.389325 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 11:48:12.396249 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5620 11:48:12.399303 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5621 11:48:12.402477 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:48:12.409677 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:48:12.413145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:48:12.416245 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:48:12.419804 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:48:12.426307 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 11:48:12.429679 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 11:48:12.433477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 11:48:12.439819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 11:48:12.443215 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 11:48:12.446546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 11:48:12.452901 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 11:48:12.456835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 11:48:12.459763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 11:48:12.466972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5636 11:48:12.467535 Total UI for P1: 0, mck2ui 16
5637 11:48:12.473006 best dqsien dly found for B1: ( 1, 2, 26)
5638 11:48:12.476625 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:48:12.479838 Total UI for P1: 0, mck2ui 16
5640 11:48:12.483036 best dqsien dly found for B0: ( 1, 2, 28)
5641 11:48:12.486589 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5642 11:48:12.489665 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5643 11:48:12.490083
5644 11:48:12.492927 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5645 11:48:12.496254 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5646 11:48:12.499464 [Gating] SW calibration Done
5647 11:48:12.499873 ==
5648 11:48:12.503045 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 11:48:12.506383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 11:48:12.506816 ==
5651 11:48:12.510014 RX Vref Scan: 0
5652 11:48:12.510425
5653 11:48:12.512936 RX Vref 0 -> 0, step: 1
5654 11:48:12.513347
5655 11:48:12.513673 RX Delay -80 -> 252, step: 8
5656 11:48:12.519284 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5657 11:48:12.522792 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5658 11:48:12.525868 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5659 11:48:12.529282 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5660 11:48:12.533046 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5661 11:48:12.536097 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5662 11:48:12.542526 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5663 11:48:12.546034 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5664 11:48:12.549204 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5665 11:48:12.552676 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5666 11:48:12.556349 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5667 11:48:12.562488 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5668 11:48:12.566376 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5669 11:48:12.569398 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5670 11:48:12.573482 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5671 11:48:12.576440 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5672 11:48:12.576853 ==
5673 11:48:12.579694 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 11:48:12.583495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 11:48:12.586851 ==
5676 11:48:12.587433 DQS Delay:
5677 11:48:12.587763 DQS0 = 0, DQS1 = 0
5678 11:48:12.590109 DQM Delay:
5679 11:48:12.590542 DQM0 = 95, DQM1 = 88
5680 11:48:12.593061 DQ Delay:
5681 11:48:12.593473 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5682 11:48:12.596415 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5683 11:48:12.599766 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5684 11:48:12.603256 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5685 11:48:12.603775
5686 11:48:12.606626
5687 11:48:12.607078 ==
5688 11:48:12.610054 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 11:48:12.613054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 11:48:12.613476 ==
5691 11:48:12.613818
5692 11:48:12.614129
5693 11:48:12.616883 TX Vref Scan disable
5694 11:48:12.617400 == TX Byte 0 ==
5695 11:48:12.623584 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5696 11:48:12.626486 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5697 11:48:12.626920 == TX Byte 1 ==
5698 11:48:12.633101 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5699 11:48:12.636511 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5700 11:48:12.636926 ==
5701 11:48:12.639848 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 11:48:12.642978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 11:48:12.643400 ==
5704 11:48:12.643734
5705 11:48:12.644042
5706 11:48:12.646153 TX Vref Scan disable
5707 11:48:12.649812 == TX Byte 0 ==
5708 11:48:12.653143 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5709 11:48:12.656585 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5710 11:48:12.660023 == TX Byte 1 ==
5711 11:48:12.663139 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5712 11:48:12.666198 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5713 11:48:12.666617
5714 11:48:12.670126 [DATLAT]
5715 11:48:12.670545 Freq=933, CH1 RK0
5716 11:48:12.670925
5717 11:48:12.673810 DATLAT Default: 0xd
5718 11:48:12.674322 0, 0xFFFF, sum = 0
5719 11:48:12.676756 1, 0xFFFF, sum = 0
5720 11:48:12.677181 2, 0xFFFF, sum = 0
5721 11:48:12.679565 3, 0xFFFF, sum = 0
5722 11:48:12.680084 4, 0xFFFF, sum = 0
5723 11:48:12.682935 5, 0xFFFF, sum = 0
5724 11:48:12.683362 6, 0xFFFF, sum = 0
5725 11:48:12.686557 7, 0xFFFF, sum = 0
5726 11:48:12.687045 8, 0xFFFF, sum = 0
5727 11:48:12.689682 9, 0xFFFF, sum = 0
5728 11:48:12.690110 10, 0x0, sum = 1
5729 11:48:12.693278 11, 0x0, sum = 2
5730 11:48:12.693698 12, 0x0, sum = 3
5731 11:48:12.696459 13, 0x0, sum = 4
5732 11:48:12.696880 best_step = 11
5733 11:48:12.697214
5734 11:48:12.697518 ==
5735 11:48:12.699747 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 11:48:12.703155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 11:48:12.706948 ==
5738 11:48:12.707462 RX Vref Scan: 1
5739 11:48:12.707801
5740 11:48:12.709782 RX Vref 0 -> 0, step: 1
5741 11:48:12.710196
5742 11:48:12.712881 RX Delay -61 -> 252, step: 4
5743 11:48:12.713308
5744 11:48:12.716638 Set Vref, RX VrefLevel [Byte0]: 54
5745 11:48:12.717054 [Byte1]: 53
5746 11:48:12.721509
5747 11:48:12.721918 Final RX Vref Byte 0 = 54 to rank0
5748 11:48:12.725221 Final RX Vref Byte 1 = 53 to rank0
5749 11:48:12.728047 Final RX Vref Byte 0 = 54 to rank1
5750 11:48:12.731889 Final RX Vref Byte 1 = 53 to rank1==
5751 11:48:12.735443 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 11:48:12.738378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 11:48:12.741589 ==
5754 11:48:12.742001 DQS Delay:
5755 11:48:12.742330 DQS0 = 0, DQS1 = 0
5756 11:48:12.745141 DQM Delay:
5757 11:48:12.745550 DQM0 = 98, DQM1 = 90
5758 11:48:12.748253 DQ Delay:
5759 11:48:12.751734 DQ0 =102, DQ1 =90, DQ2 =86, DQ3 =100
5760 11:48:12.755465 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =92
5761 11:48:12.758664 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5762 11:48:12.761806 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =94
5763 11:48:12.762314
5764 11:48:12.762645
5765 11:48:12.768491 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5766 11:48:12.771934 CH1 RK0: MR19=504, MR18=14F1
5767 11:48:12.778143 CH1_RK0: MR19=0x504, MR18=0x14F1, DQSOSC=415, MR23=63, INC=62, DEC=41
5768 11:48:12.778700
5769 11:48:12.781404 ----->DramcWriteLeveling(PI) begin...
5770 11:48:12.781867 ==
5771 11:48:12.784612 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 11:48:12.788316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 11:48:12.788890 ==
5774 11:48:12.791741 Write leveling (Byte 0): 31 => 31
5775 11:48:12.794971 Write leveling (Byte 1): 29 => 29
5776 11:48:12.798272 DramcWriteLeveling(PI) end<-----
5777 11:48:12.798827
5778 11:48:12.799287 ==
5779 11:48:12.801527 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 11:48:12.804713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:48:12.805269 ==
5782 11:48:12.808136 [Gating] SW mode calibration
5783 11:48:12.815161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5784 11:48:12.821904 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5785 11:48:12.824784 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 11:48:12.831762 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 11:48:12.835003 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 11:48:12.838345 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5789 11:48:12.841244 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 11:48:12.848300 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5791 11:48:12.851514 0 14 24 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
5792 11:48:12.855058 0 14 28 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
5793 11:48:12.861695 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 11:48:12.864910 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 11:48:12.868642 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 11:48:12.875031 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 11:48:12.877850 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 11:48:12.881575 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5799 11:48:12.888346 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5800 11:48:12.891633 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5801 11:48:12.894602 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 11:48:12.901563 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 11:48:12.904963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 11:48:12.907926 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 11:48:12.915015 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 11:48:12.918226 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 11:48:12.921512 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5808 11:48:12.928136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5809 11:48:12.931384 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:48:12.935314 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:48:12.938195 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:48:12.944867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:48:12.948066 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:48:12.951363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 11:48:12.958172 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 11:48:12.961421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 11:48:12.965004 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 11:48:12.971460 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 11:48:12.975406 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 11:48:12.978207 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 11:48:12.985006 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 11:48:12.988264 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 11:48:12.991348 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5824 11:48:12.998419 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:48:12.999046 Total UI for P1: 0, mck2ui 16
5826 11:48:13.005164 best dqsien dly found for B0: ( 1, 2, 24)
5827 11:48:13.005974 Total UI for P1: 0, mck2ui 16
5828 11:48:13.008034 best dqsien dly found for B1: ( 1, 2, 24)
5829 11:48:13.015008 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5830 11:48:13.018223 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5831 11:48:13.018771
5832 11:48:13.021667 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5833 11:48:13.024888 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 11:48:13.028535 [Gating] SW calibration Done
5835 11:48:13.029086 ==
5836 11:48:13.031817 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 11:48:13.035114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 11:48:13.035671 ==
5839 11:48:13.038356 RX Vref Scan: 0
5840 11:48:13.038878
5841 11:48:13.039283 RX Vref 0 -> 0, step: 1
5842 11:48:13.039630
5843 11:48:13.041763 RX Delay -80 -> 252, step: 8
5844 11:48:13.045002 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5845 11:48:13.048498 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5846 11:48:13.055407 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5847 11:48:13.058394 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5848 11:48:13.061823 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5849 11:48:13.065043 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5850 11:48:13.068206 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5851 11:48:13.072178 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5852 11:48:13.075533 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5853 11:48:13.082154 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5854 11:48:13.085623 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5855 11:48:13.088739 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5856 11:48:13.091859 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5857 11:48:13.095267 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5858 11:48:13.101930 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5859 11:48:13.105513 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5860 11:48:13.106084 ==
5861 11:48:13.108357 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 11:48:13.111599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 11:48:13.112234 ==
5864 11:48:13.112823 DQS Delay:
5865 11:48:13.114992 DQS0 = 0, DQS1 = 0
5866 11:48:13.115451 DQM Delay:
5867 11:48:13.118369 DQM0 = 94, DQM1 = 89
5868 11:48:13.118820 DQ Delay:
5869 11:48:13.122133 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5870 11:48:13.125112 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5871 11:48:13.128757 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5872 11:48:13.132121 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5873 11:48:13.132674
5874 11:48:13.133037
5875 11:48:13.133370 ==
5876 11:48:13.135522 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 11:48:13.138259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 11:48:13.142004 ==
5879 11:48:13.142583
5880 11:48:13.143137
5881 11:48:13.143591 TX Vref Scan disable
5882 11:48:13.145229 == TX Byte 0 ==
5883 11:48:13.148957 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5884 11:48:13.152107 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5885 11:48:13.155311 == TX Byte 1 ==
5886 11:48:13.158585 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5887 11:48:13.161855 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5888 11:48:13.162579 ==
5889 11:48:13.165009 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 11:48:13.171738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 11:48:13.172197 ==
5892 11:48:13.172560
5893 11:48:13.172895
5894 11:48:13.173216 TX Vref Scan disable
5895 11:48:13.176177 == TX Byte 0 ==
5896 11:48:13.179693 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5897 11:48:13.182589 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5898 11:48:13.186361 == TX Byte 1 ==
5899 11:48:13.189716 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5900 11:48:13.192799 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5901 11:48:13.196445
5902 11:48:13.196999 [DATLAT]
5903 11:48:13.197364 Freq=933, CH1 RK1
5904 11:48:13.197699
5905 11:48:13.199553 DATLAT Default: 0xb
5906 11:48:13.200031 0, 0xFFFF, sum = 0
5907 11:48:13.203049 1, 0xFFFF, sum = 0
5908 11:48:13.203514 2, 0xFFFF, sum = 0
5909 11:48:13.206402 3, 0xFFFF, sum = 0
5910 11:48:13.207010 4, 0xFFFF, sum = 0
5911 11:48:13.209988 5, 0xFFFF, sum = 0
5912 11:48:13.212783 6, 0xFFFF, sum = 0
5913 11:48:13.213245 7, 0xFFFF, sum = 0
5914 11:48:13.216481 8, 0xFFFF, sum = 0
5915 11:48:13.216945 9, 0xFFFF, sum = 0
5916 11:48:13.219728 10, 0x0, sum = 1
5917 11:48:13.220214 11, 0x0, sum = 2
5918 11:48:13.220581 12, 0x0, sum = 3
5919 11:48:13.222909 13, 0x0, sum = 4
5920 11:48:13.223372 best_step = 11
5921 11:48:13.223735
5922 11:48:13.224077 ==
5923 11:48:13.226138 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 11:48:13.232590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 11:48:13.233010 ==
5926 11:48:13.233342 RX Vref Scan: 0
5927 11:48:13.233650
5928 11:48:13.236355 RX Vref 0 -> 0, step: 1
5929 11:48:13.236863
5930 11:48:13.239424 RX Delay -61 -> 252, step: 4
5931 11:48:13.243065 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5932 11:48:13.249636 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5933 11:48:13.252768 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5934 11:48:13.256814 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5935 11:48:13.259453 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5936 11:48:13.263331 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5937 11:48:13.266116 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5938 11:48:13.273035 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5939 11:48:13.276311 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5940 11:48:13.279142 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5941 11:48:13.282490 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5942 11:48:13.286327 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5943 11:48:13.289521 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5944 11:48:13.296056 iDelay=199, Bit 13, Center 96 (3 ~ 190) 188
5945 11:48:13.299252 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5946 11:48:13.302713 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5947 11:48:13.303244 ==
5948 11:48:13.306166 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 11:48:13.309175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 11:48:13.309612 ==
5951 11:48:13.312433 DQS Delay:
5952 11:48:13.312872 DQS0 = 0, DQS1 = 0
5953 11:48:13.313309 DQM Delay:
5954 11:48:13.315932 DQM0 = 94, DQM1 = 90
5955 11:48:13.316366 DQ Delay:
5956 11:48:13.319415 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =94
5957 11:48:13.322455 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =90
5958 11:48:13.325852 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5959 11:48:13.329411 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =98
5960 11:48:13.329842
5961 11:48:13.330283
5962 11:48:13.339335 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5963 11:48:13.339834 CH1 RK1: MR19=505, MR18=E17
5964 11:48:13.345842 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
5965 11:48:13.349102 [RxdqsGatingPostProcess] freq 933
5966 11:48:13.355988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5967 11:48:13.359071 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 11:48:13.362593 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 11:48:13.365669 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 11:48:13.369633 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 11:48:13.372879 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 11:48:13.373297 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 11:48:13.376197 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 11:48:13.379665 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 11:48:13.382797 Pre-setting of DQS Precalculation
5976 11:48:13.389674 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5977 11:48:13.396521 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5978 11:48:13.402948 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5979 11:48:13.403369
5980 11:48:13.403700
5981 11:48:13.406067 [Calibration Summary] 1866 Mbps
5982 11:48:13.406484 CH 0, Rank 0
5983 11:48:13.409409 SW Impedance : PASS
5984 11:48:13.412955 DUTY Scan : NO K
5985 11:48:13.413398 ZQ Calibration : PASS
5986 11:48:13.416143 Jitter Meter : NO K
5987 11:48:13.419459 CBT Training : PASS
5988 11:48:13.419899 Write leveling : PASS
5989 11:48:13.422745 RX DQS gating : PASS
5990 11:48:13.426170 RX DQ/DQS(RDDQC) : PASS
5991 11:48:13.426588 TX DQ/DQS : PASS
5992 11:48:13.429768 RX DATLAT : PASS
5993 11:48:13.432918 RX DQ/DQS(Engine): PASS
5994 11:48:13.433350 TX OE : NO K
5995 11:48:13.433795 All Pass.
5996 11:48:13.434213
5997 11:48:13.436186 CH 0, Rank 1
5998 11:48:13.436618 SW Impedance : PASS
5999 11:48:13.439402 DUTY Scan : NO K
6000 11:48:13.442937 ZQ Calibration : PASS
6001 11:48:13.443377 Jitter Meter : NO K
6002 11:48:13.446223 CBT Training : PASS
6003 11:48:13.449629 Write leveling : PASS
6004 11:48:13.450108 RX DQS gating : PASS
6005 11:48:13.453140 RX DQ/DQS(RDDQC) : PASS
6006 11:48:13.456034 TX DQ/DQS : PASS
6007 11:48:13.456445 RX DATLAT : PASS
6008 11:48:13.459556 RX DQ/DQS(Engine): PASS
6009 11:48:13.463288 TX OE : NO K
6010 11:48:13.463699 All Pass.
6011 11:48:13.464048
6012 11:48:13.464363 CH 1, Rank 0
6013 11:48:13.466522 SW Impedance : PASS
6014 11:48:13.469737 DUTY Scan : NO K
6015 11:48:13.470146 ZQ Calibration : PASS
6016 11:48:13.473089 Jitter Meter : NO K
6017 11:48:13.476523 CBT Training : PASS
6018 11:48:13.476936 Write leveling : PASS
6019 11:48:13.479346 RX DQS gating : PASS
6020 11:48:13.479425 RX DQ/DQS(RDDQC) : PASS
6021 11:48:13.482379 TX DQ/DQS : PASS
6022 11:48:13.485677 RX DATLAT : PASS
6023 11:48:13.485757 RX DQ/DQS(Engine): PASS
6024 11:48:13.489374 TX OE : NO K
6025 11:48:13.489460 All Pass.
6026 11:48:13.489528
6027 11:48:13.492838 CH 1, Rank 1
6028 11:48:13.492939 SW Impedance : PASS
6029 11:48:13.495976 DUTY Scan : NO K
6030 11:48:13.499062 ZQ Calibration : PASS
6031 11:48:13.499161 Jitter Meter : NO K
6032 11:48:13.502529 CBT Training : PASS
6033 11:48:13.505990 Write leveling : PASS
6034 11:48:13.506097 RX DQS gating : PASS
6035 11:48:13.509095 RX DQ/DQS(RDDQC) : PASS
6036 11:48:13.512361 TX DQ/DQS : PASS
6037 11:48:13.512479 RX DATLAT : PASS
6038 11:48:13.516194 RX DQ/DQS(Engine): PASS
6039 11:48:13.519537 TX OE : NO K
6040 11:48:13.519684 All Pass.
6041 11:48:13.519802
6042 11:48:13.519912 DramC Write-DBI off
6043 11:48:13.522876 PER_BANK_REFRESH: Hybrid Mode
6044 11:48:13.526460 TX_TRACKING: ON
6045 11:48:13.532668 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6046 11:48:13.535881 [FAST_K] Save calibration result to emmc
6047 11:48:13.542529 dramc_set_vcore_voltage set vcore to 650000
6048 11:48:13.542849 Read voltage for 400, 6
6049 11:48:13.543193 Vio18 = 0
6050 11:48:13.546407 Vcore = 650000
6051 11:48:13.546790 Vdram = 0
6052 11:48:13.547296 Vddq = 0
6053 11:48:13.549326 Vmddr = 0
6054 11:48:13.553007 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6055 11:48:13.559325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6056 11:48:13.559779 MEM_TYPE=3, freq_sel=20
6057 11:48:13.563252 sv_algorithm_assistance_LP4_800
6058 11:48:13.569793 ============ PULL DRAM RESETB DOWN ============
6059 11:48:13.572702 ========== PULL DRAM RESETB DOWN end =========
6060 11:48:13.576562 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6061 11:48:13.579266 ===================================
6062 11:48:13.583188 LPDDR4 DRAM CONFIGURATION
6063 11:48:13.586073 ===================================
6064 11:48:13.589593 EX_ROW_EN[0] = 0x0
6065 11:48:13.590078 EX_ROW_EN[1] = 0x0
6066 11:48:13.592897 LP4Y_EN = 0x0
6067 11:48:13.593374 WORK_FSP = 0x0
6068 11:48:13.596097 WL = 0x2
6069 11:48:13.596523 RL = 0x2
6070 11:48:13.600101 BL = 0x2
6071 11:48:13.600579 RPST = 0x0
6072 11:48:13.603107 RD_PRE = 0x0
6073 11:48:13.603623 WR_PRE = 0x1
6074 11:48:13.606392 WR_PST = 0x0
6075 11:48:13.606798 DBI_WR = 0x0
6076 11:48:13.609825 DBI_RD = 0x0
6077 11:48:13.610234 OTF = 0x1
6078 11:48:13.613085 ===================================
6079 11:48:13.616315 ===================================
6080 11:48:13.620110 ANA top config
6081 11:48:13.623281 ===================================
6082 11:48:13.623691 DLL_ASYNC_EN = 0
6083 11:48:13.626911 ALL_SLAVE_EN = 1
6084 11:48:13.630100 NEW_RANK_MODE = 1
6085 11:48:13.632900 DLL_IDLE_MODE = 1
6086 11:48:13.636623 LP45_APHY_COMB_EN = 1
6087 11:48:13.637133 TX_ODT_DIS = 1
6088 11:48:13.639488 NEW_8X_MODE = 1
6089 11:48:13.642974 ===================================
6090 11:48:13.646437 ===================================
6091 11:48:13.649602 data_rate = 800
6092 11:48:13.652898 CKR = 1
6093 11:48:13.656192 DQ_P2S_RATIO = 4
6094 11:48:13.659781 ===================================
6095 11:48:13.660244 CA_P2S_RATIO = 4
6096 11:48:13.663231 DQ_CA_OPEN = 0
6097 11:48:13.666215 DQ_SEMI_OPEN = 1
6098 11:48:13.669621 CA_SEMI_OPEN = 1
6099 11:48:13.673443 CA_FULL_RATE = 0
6100 11:48:13.676990 DQ_CKDIV4_EN = 0
6101 11:48:13.677401 CA_CKDIV4_EN = 1
6102 11:48:13.679640 CA_PREDIV_EN = 0
6103 11:48:13.683448 PH8_DLY = 0
6104 11:48:13.686932 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6105 11:48:13.689804 DQ_AAMCK_DIV = 0
6106 11:48:13.690215 CA_AAMCK_DIV = 0
6107 11:48:13.693152 CA_ADMCK_DIV = 4
6108 11:48:13.696595 DQ_TRACK_CA_EN = 0
6109 11:48:13.699800 CA_PICK = 800
6110 11:48:13.703259 CA_MCKIO = 400
6111 11:48:13.706387 MCKIO_SEMI = 400
6112 11:48:13.709805 PLL_FREQ = 3016
6113 11:48:13.710246 DQ_UI_PI_RATIO = 32
6114 11:48:13.714005 CA_UI_PI_RATIO = 32
6115 11:48:13.716746 ===================================
6116 11:48:13.720236 ===================================
6117 11:48:13.723447 memory_type:LPDDR4
6118 11:48:13.726675 GP_NUM : 10
6119 11:48:13.727133 SRAM_EN : 1
6120 11:48:13.729953 MD32_EN : 0
6121 11:48:13.733153 ===================================
6122 11:48:13.736826 [ANA_INIT] >>>>>>>>>>>>>>
6123 11:48:13.737342 <<<<<< [CONFIGURE PHASE]: ANA_TX
6124 11:48:13.739854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6125 11:48:13.743686 ===================================
6126 11:48:13.746603 data_rate = 800,PCW = 0X7400
6127 11:48:13.749999 ===================================
6128 11:48:13.753933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6129 11:48:13.760593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 11:48:13.770135 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 11:48:13.776679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6132 11:48:13.780012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6133 11:48:13.783530 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6134 11:48:13.783941 [ANA_INIT] flow start
6135 11:48:13.786676 [ANA_INIT] PLL >>>>>>>>
6136 11:48:13.790169 [ANA_INIT] PLL <<<<<<<<
6137 11:48:13.790599 [ANA_INIT] MIDPI >>>>>>>>
6138 11:48:13.793378 [ANA_INIT] MIDPI <<<<<<<<
6139 11:48:13.796705 [ANA_INIT] DLL >>>>>>>>
6140 11:48:13.797119 [ANA_INIT] flow end
6141 11:48:13.803263 ============ LP4 DIFF to SE enter ============
6142 11:48:13.806785 ============ LP4 DIFF to SE exit ============
6143 11:48:13.809962 [ANA_INIT] <<<<<<<<<<<<<
6144 11:48:13.813379 [Flow] Enable top DCM control >>>>>
6145 11:48:13.813818 [Flow] Enable top DCM control <<<<<
6146 11:48:13.817221 Enable DLL master slave shuffle
6147 11:48:13.823483 ==============================================================
6148 11:48:13.827046 Gating Mode config
6149 11:48:13.830109 ==============================================================
6150 11:48:13.833792 Config description:
6151 11:48:13.843704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6152 11:48:13.850686 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6153 11:48:13.854197 SELPH_MODE 0: By rank 1: By Phase
6154 11:48:13.860566 ==============================================================
6155 11:48:13.864065 GAT_TRACK_EN = 0
6156 11:48:13.867035 RX_GATING_MODE = 2
6157 11:48:13.867455 RX_GATING_TRACK_MODE = 2
6158 11:48:13.870297 SELPH_MODE = 1
6159 11:48:13.873564 PICG_EARLY_EN = 1
6160 11:48:13.877070 VALID_LAT_VALUE = 1
6161 11:48:13.884054 ==============================================================
6162 11:48:13.887297 Enter into Gating configuration >>>>
6163 11:48:13.890459 Exit from Gating configuration <<<<
6164 11:48:13.893944 Enter into DVFS_PRE_config >>>>>
6165 11:48:13.903726 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6166 11:48:13.907415 Exit from DVFS_PRE_config <<<<<
6167 11:48:13.910426 Enter into PICG configuration >>>>
6168 11:48:13.913848 Exit from PICG configuration <<<<
6169 11:48:13.917050 [RX_INPUT] configuration >>>>>
6170 11:48:13.920403 [RX_INPUT] configuration <<<<<
6171 11:48:13.923821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6172 11:48:13.930499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6173 11:48:13.937051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 11:48:13.940852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 11:48:13.947051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 11:48:13.953801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 11:48:13.957273 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6178 11:48:13.960355 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6179 11:48:13.967222 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6180 11:48:13.970528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6181 11:48:13.974493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6182 11:48:13.980522 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 11:48:13.983727 ===================================
6184 11:48:13.984139 LPDDR4 DRAM CONFIGURATION
6185 11:48:13.987177 ===================================
6186 11:48:13.990448 EX_ROW_EN[0] = 0x0
6187 11:48:13.990857 EX_ROW_EN[1] = 0x0
6188 11:48:13.994072 LP4Y_EN = 0x0
6189 11:48:13.994479 WORK_FSP = 0x0
6190 11:48:13.997179 WL = 0x2
6191 11:48:13.997591 RL = 0x2
6192 11:48:14.000264 BL = 0x2
6193 11:48:14.003763 RPST = 0x0
6194 11:48:14.004199 RD_PRE = 0x0
6195 11:48:14.007246 WR_PRE = 0x1
6196 11:48:14.007656 WR_PST = 0x0
6197 11:48:14.010442 DBI_WR = 0x0
6198 11:48:14.010955 DBI_RD = 0x0
6199 11:48:14.013661 OTF = 0x1
6200 11:48:14.017509 ===================================
6201 11:48:14.020507 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6202 11:48:14.024120 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6203 11:48:14.027260 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 11:48:14.030778 ===================================
6205 11:48:14.033936 LPDDR4 DRAM CONFIGURATION
6206 11:48:14.037142 ===================================
6207 11:48:14.040613 EX_ROW_EN[0] = 0x10
6208 11:48:14.041028 EX_ROW_EN[1] = 0x0
6209 11:48:14.044016 LP4Y_EN = 0x0
6210 11:48:14.044465 WORK_FSP = 0x0
6211 11:48:14.047051 WL = 0x2
6212 11:48:14.047473 RL = 0x2
6213 11:48:14.050958 BL = 0x2
6214 11:48:14.051379 RPST = 0x0
6215 11:48:14.053871 RD_PRE = 0x0
6216 11:48:14.054290 WR_PRE = 0x1
6217 11:48:14.057556 WR_PST = 0x0
6218 11:48:14.058081 DBI_WR = 0x0
6219 11:48:14.060634 DBI_RD = 0x0
6220 11:48:14.063482 OTF = 0x1
6221 11:48:14.066915 ===================================
6222 11:48:14.071097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6223 11:48:14.075538 nWR fixed to 30
6224 11:48:14.079456 [ModeRegInit_LP4] CH0 RK0
6225 11:48:14.079979 [ModeRegInit_LP4] CH0 RK1
6226 11:48:14.082239 [ModeRegInit_LP4] CH1 RK0
6227 11:48:14.086142 [ModeRegInit_LP4] CH1 RK1
6228 11:48:14.086661 match AC timing 19
6229 11:48:14.092492 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6230 11:48:14.095857 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6231 11:48:14.099240 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6232 11:48:14.105295 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6233 11:48:14.108792 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6234 11:48:14.109211 ==
6235 11:48:14.112080 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 11:48:14.115147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 11:48:14.115569 ==
6238 11:48:14.122300 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 11:48:14.129064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6240 11:48:14.133039 [CA 0] Center 36 (8~64) winsize 57
6241 11:48:14.136044 [CA 1] Center 36 (8~64) winsize 57
6242 11:48:14.136567 [CA 2] Center 36 (8~64) winsize 57
6243 11:48:14.139040 [CA 3] Center 36 (8~64) winsize 57
6244 11:48:14.142582 [CA 4] Center 36 (8~64) winsize 57
6245 11:48:14.145890 [CA 5] Center 36 (8~64) winsize 57
6246 11:48:14.146314
6247 11:48:14.149045 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6248 11:48:14.149571
6249 11:48:14.155799 [CATrainingPosCal] consider 1 rank data
6250 11:48:14.156309 u2DelayCellTimex100 = 270/100 ps
6251 11:48:14.159143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:48:14.166010 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:48:14.169408 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:48:14.172678 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:48:14.175688 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:48:14.179312 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 11:48:14.179729
6258 11:48:14.183001 CA PerBit enable=1, Macro0, CA PI delay=36
6259 11:48:14.183526
6260 11:48:14.186133 [CBTSetCACLKResult] CA Dly = 36
6261 11:48:14.186656 CS Dly: 1 (0~32)
6262 11:48:14.189640 ==
6263 11:48:14.190160 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 11:48:14.196203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 11:48:14.196735 ==
6266 11:48:14.199522 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 11:48:14.205967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 11:48:14.209646 [CA 0] Center 36 (8~64) winsize 57
6269 11:48:14.212780 [CA 1] Center 36 (8~64) winsize 57
6270 11:48:14.216265 [CA 2] Center 36 (8~64) winsize 57
6271 11:48:14.219605 [CA 3] Center 36 (8~64) winsize 57
6272 11:48:14.222303 [CA 4] Center 36 (8~64) winsize 57
6273 11:48:14.225584 [CA 5] Center 36 (8~64) winsize 57
6274 11:48:14.226009
6275 11:48:14.229017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 11:48:14.229563
6277 11:48:14.232850 [CATrainingPosCal] consider 2 rank data
6278 11:48:14.235822 u2DelayCellTimex100 = 270/100 ps
6279 11:48:14.239501 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:48:14.242853 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:48:14.245844 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:48:14.249298 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 11:48:14.252738 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 11:48:14.256455 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 11:48:14.256874
6286 11:48:14.262818 CA PerBit enable=1, Macro0, CA PI delay=36
6287 11:48:14.263392
6288 11:48:14.265889 [CBTSetCACLKResult] CA Dly = 36
6289 11:48:14.266408 CS Dly: 1 (0~32)
6290 11:48:14.266747
6291 11:48:14.269689 ----->DramcWriteLeveling(PI) begin...
6292 11:48:14.270218 ==
6293 11:48:14.272662 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 11:48:14.275629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 11:48:14.276048 ==
6296 11:48:14.279684 Write leveling (Byte 0): 40 => 8
6297 11:48:14.283052 Write leveling (Byte 1): 32 => 0
6298 11:48:14.285940 DramcWriteLeveling(PI) end<-----
6299 11:48:14.286354
6300 11:48:14.286680 ==
6301 11:48:14.289694 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 11:48:14.292796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 11:48:14.295987 ==
6304 11:48:14.296432 [Gating] SW mode calibration
6305 11:48:14.302640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6306 11:48:14.309493 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6307 11:48:14.312785 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 11:48:14.319675 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 11:48:14.322922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 11:48:14.326406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 11:48:14.332810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 11:48:14.336546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 11:48:14.339561 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 11:48:14.345889 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 11:48:14.349801 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 11:48:14.353006 Total UI for P1: 0, mck2ui 16
6317 11:48:14.356223 best dqsien dly found for B0: ( 0, 14, 24)
6318 11:48:14.359815 Total UI for P1: 0, mck2ui 16
6319 11:48:14.362734 best dqsien dly found for B1: ( 0, 14, 24)
6320 11:48:14.366283 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6321 11:48:14.369807 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6322 11:48:14.370359
6323 11:48:14.372999 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 11:48:14.376712 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 11:48:14.380046 [Gating] SW calibration Done
6326 11:48:14.380601 ==
6327 11:48:14.382801 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 11:48:14.386204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 11:48:14.386750 ==
6330 11:48:14.389972 RX Vref Scan: 0
6331 11:48:14.390522
6332 11:48:14.392860 RX Vref 0 -> 0, step: 1
6333 11:48:14.393412
6334 11:48:14.393772 RX Delay -410 -> 252, step: 16
6335 11:48:14.399757 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6336 11:48:14.402802 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6337 11:48:14.406436 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6338 11:48:14.409556 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6339 11:48:14.416254 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6340 11:48:14.419742 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6341 11:48:14.422765 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6342 11:48:14.426067 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6343 11:48:14.433149 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6344 11:48:14.435939 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6345 11:48:14.439583 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6346 11:48:14.442713 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6347 11:48:14.449549 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6348 11:48:14.453426 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6349 11:48:14.456264 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6350 11:48:14.459726 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6351 11:48:14.462768 ==
6352 11:48:14.466357 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:48:14.469950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:48:14.470516 ==
6355 11:48:14.470940 DQS Delay:
6356 11:48:14.473260 DQS0 = 35, DQS1 = 51
6357 11:48:14.473820 DQM Delay:
6358 11:48:14.476639 DQM0 = 8, DQM1 = 10
6359 11:48:14.477212 DQ Delay:
6360 11:48:14.480060 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6361 11:48:14.483360 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6362 11:48:14.486485 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6363 11:48:14.489506 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6364 11:48:14.490064
6365 11:48:14.490436
6366 11:48:14.490783 ==
6367 11:48:14.493460 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:48:14.496679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:48:14.497144 ==
6370 11:48:14.497515
6371 11:48:14.497857
6372 11:48:14.499969 TX Vref Scan disable
6373 11:48:14.500427 == TX Byte 0 ==
6374 11:48:14.502999 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 11:48:14.509552 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 11:48:14.510104 == TX Byte 1 ==
6377 11:48:14.512966 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6378 11:48:14.519801 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6379 11:48:14.520256 ==
6380 11:48:14.523171 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 11:48:14.526377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 11:48:14.526791 ==
6383 11:48:14.527155
6384 11:48:14.527459
6385 11:48:14.529541 TX Vref Scan disable
6386 11:48:14.529951 == TX Byte 0 ==
6387 11:48:14.536604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 11:48:14.540061 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 11:48:14.540474 == TX Byte 1 ==
6390 11:48:14.545990 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 11:48:14.549767 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 11:48:14.550188
6393 11:48:14.550521 [DATLAT]
6394 11:48:14.552648 Freq=400, CH0 RK0
6395 11:48:14.553161
6396 11:48:14.553502 DATLAT Default: 0xf
6397 11:48:14.556240 0, 0xFFFF, sum = 0
6398 11:48:14.556665 1, 0xFFFF, sum = 0
6399 11:48:14.559545 2, 0xFFFF, sum = 0
6400 11:48:14.560141 3, 0xFFFF, sum = 0
6401 11:48:14.562734 4, 0xFFFF, sum = 0
6402 11:48:14.563367 5, 0xFFFF, sum = 0
6403 11:48:14.566314 6, 0xFFFF, sum = 0
6404 11:48:14.566689 7, 0xFFFF, sum = 0
6405 11:48:14.569893 8, 0xFFFF, sum = 0
6406 11:48:14.570309 9, 0xFFFF, sum = 0
6407 11:48:14.573005 10, 0xFFFF, sum = 0
6408 11:48:14.573418 11, 0xFFFF, sum = 0
6409 11:48:14.576636 12, 0xFFFF, sum = 0
6410 11:48:14.577150 13, 0x0, sum = 1
6411 11:48:14.580287 14, 0x0, sum = 2
6412 11:48:14.580798 15, 0x0, sum = 3
6413 11:48:14.583352 16, 0x0, sum = 4
6414 11:48:14.583771 best_step = 14
6415 11:48:14.584101
6416 11:48:14.584408 ==
6417 11:48:14.586657 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 11:48:14.593724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:48:14.594231 ==
6420 11:48:14.594567 RX Vref Scan: 1
6421 11:48:14.594961
6422 11:48:14.596642 RX Vref 0 -> 0, step: 1
6423 11:48:14.597053
6424 11:48:14.600145 RX Delay -343 -> 252, step: 8
6425 11:48:14.600557
6426 11:48:14.603232 Set Vref, RX VrefLevel [Byte0]: 53
6427 11:48:14.606965 [Byte1]: 51
6428 11:48:14.607551
6429 11:48:14.610548 Final RX Vref Byte 0 = 53 to rank0
6430 11:48:14.613184 Final RX Vref Byte 1 = 51 to rank0
6431 11:48:14.616483 Final RX Vref Byte 0 = 53 to rank1
6432 11:48:14.620466 Final RX Vref Byte 1 = 51 to rank1==
6433 11:48:14.623102 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 11:48:14.627022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 11:48:14.627582 ==
6436 11:48:14.629888 DQS Delay:
6437 11:48:14.630447 DQS0 = 44, DQS1 = 60
6438 11:48:14.633331 DQM Delay:
6439 11:48:14.633893 DQM0 = 11, DQM1 = 15
6440 11:48:14.634266 DQ Delay:
6441 11:48:14.636852 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6442 11:48:14.640435 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6443 11:48:14.643257 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6444 11:48:14.646982 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6445 11:48:14.647448
6446 11:48:14.647819
6447 11:48:14.656719 [DQSOSCAuto] RK0, (LSB)MR18= 0x8756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6448 11:48:14.659855 CH0 RK0: MR19=C0C, MR18=8756
6449 11:48:14.663461 CH0_RK0: MR19=0xC0C, MR18=0x8756, DQSOSC=392, MR23=63, INC=384, DEC=256
6450 11:48:14.667348 ==
6451 11:48:14.667916 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 11:48:14.673807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 11:48:14.674372 ==
6454 11:48:14.676766 [Gating] SW mode calibration
6455 11:48:14.683345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6456 11:48:14.687230 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6457 11:48:14.693276 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 11:48:14.696495 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 11:48:14.699848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 11:48:14.707100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 11:48:14.709927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 11:48:14.713374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 11:48:14.716924 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 11:48:14.723483 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 11:48:14.726568 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 11:48:14.730426 Total UI for P1: 0, mck2ui 16
6467 11:48:14.733415 best dqsien dly found for B0: ( 0, 14, 24)
6468 11:48:14.736873 Total UI for P1: 0, mck2ui 16
6469 11:48:14.740425 best dqsien dly found for B1: ( 0, 14, 24)
6470 11:48:14.743822 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6471 11:48:14.747021 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6472 11:48:14.747663
6473 11:48:14.749866 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 11:48:14.753644 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 11:48:14.757280 [Gating] SW calibration Done
6476 11:48:14.757844 ==
6477 11:48:14.759978 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 11:48:14.766989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 11:48:14.767548 ==
6480 11:48:14.767922 RX Vref Scan: 0
6481 11:48:14.768270
6482 11:48:14.770292 RX Vref 0 -> 0, step: 1
6483 11:48:14.770755
6484 11:48:14.774016 RX Delay -410 -> 252, step: 16
6485 11:48:14.777007 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6486 11:48:14.780257 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6487 11:48:14.783516 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6488 11:48:14.790388 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6489 11:48:14.793458 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6490 11:48:14.797464 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6491 11:48:14.800451 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6492 11:48:14.807117 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6493 11:48:14.810463 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6494 11:48:14.813640 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6495 11:48:14.817175 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6496 11:48:14.823228 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6497 11:48:14.826843 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6498 11:48:14.829693 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6499 11:48:14.833156 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6500 11:48:14.839723 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6501 11:48:14.839806 ==
6502 11:48:14.843072 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:48:14.846433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:48:14.846516 ==
6505 11:48:14.846581 DQS Delay:
6506 11:48:14.849734 DQS0 = 43, DQS1 = 51
6507 11:48:14.849821 DQM Delay:
6508 11:48:14.853045 DQM0 = 11, DQM1 = 10
6509 11:48:14.853139 DQ Delay:
6510 11:48:14.856808 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6511 11:48:14.860664 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6512 11:48:14.863391 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6513 11:48:14.867085 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6514 11:48:14.867276
6515 11:48:14.867376
6516 11:48:14.867465 ==
6517 11:48:14.870549 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 11:48:14.873414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 11:48:14.873633 ==
6520 11:48:14.873753
6521 11:48:14.873859
6522 11:48:14.876732 TX Vref Scan disable
6523 11:48:14.876951 == TX Byte 0 ==
6524 11:48:14.883888 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6525 11:48:14.887116 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6526 11:48:14.887376 == TX Byte 1 ==
6527 11:48:14.893595 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6528 11:48:14.897298 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6529 11:48:14.897633 ==
6530 11:48:14.900467 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 11:48:14.903828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 11:48:14.904225 ==
6533 11:48:14.904533
6534 11:48:14.904819
6535 11:48:14.906992 TX Vref Scan disable
6536 11:48:14.907482 == TX Byte 0 ==
6537 11:48:14.913801 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6538 11:48:14.917343 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6539 11:48:14.917963 == TX Byte 1 ==
6540 11:48:14.923795 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6541 11:48:14.927292 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6542 11:48:14.927756
6543 11:48:14.928120 [DATLAT]
6544 11:48:14.931003 Freq=400, CH0 RK1
6545 11:48:14.931583
6546 11:48:14.931955 DATLAT Default: 0xe
6547 11:48:14.933945 0, 0xFFFF, sum = 0
6548 11:48:14.934413 1, 0xFFFF, sum = 0
6549 11:48:14.937441 2, 0xFFFF, sum = 0
6550 11:48:14.938011 3, 0xFFFF, sum = 0
6551 11:48:14.940774 4, 0xFFFF, sum = 0
6552 11:48:14.941363 5, 0xFFFF, sum = 0
6553 11:48:14.943804 6, 0xFFFF, sum = 0
6554 11:48:14.944276 7, 0xFFFF, sum = 0
6555 11:48:14.947509 8, 0xFFFF, sum = 0
6556 11:48:14.948156 9, 0xFFFF, sum = 0
6557 11:48:14.950853 10, 0xFFFF, sum = 0
6558 11:48:14.951368 11, 0xFFFF, sum = 0
6559 11:48:14.954087 12, 0xFFFF, sum = 0
6560 11:48:14.954681 13, 0x0, sum = 1
6561 11:48:14.957355 14, 0x0, sum = 2
6562 11:48:14.957825 15, 0x0, sum = 3
6563 11:48:14.960864 16, 0x0, sum = 4
6564 11:48:14.961333 best_step = 14
6565 11:48:14.961704
6566 11:48:14.962048 ==
6567 11:48:14.964441 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:48:14.970056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:48:14.970137 ==
6570 11:48:14.970202 RX Vref Scan: 0
6571 11:48:14.970263
6572 11:48:14.973985 RX Vref 0 -> 0, step: 1
6573 11:48:14.974065
6574 11:48:14.976825 RX Delay -343 -> 252, step: 8
6575 11:48:14.983842 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6576 11:48:14.987102 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6577 11:48:14.990390 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6578 11:48:14.993576 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6579 11:48:15.000323 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6580 11:48:15.003671 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6581 11:48:15.006871 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6582 11:48:15.010684 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6583 11:48:15.017166 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6584 11:48:15.020477 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6585 11:48:15.023834 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6586 11:48:15.027169 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6587 11:48:15.034044 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6588 11:48:15.037402 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6589 11:48:15.041095 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6590 11:48:15.043649 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6591 11:48:15.047168 ==
6592 11:48:15.047431 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 11:48:15.054293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 11:48:15.054678 ==
6595 11:48:15.055088 DQS Delay:
6596 11:48:15.057453 DQS0 = 48, DQS1 = 60
6597 11:48:15.057838 DQM Delay:
6598 11:48:15.061193 DQM0 = 13, DQM1 = 13
6599 11:48:15.061780 DQ Delay:
6600 11:48:15.064522 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6601 11:48:15.067306 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6602 11:48:15.071167 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6603 11:48:15.074195 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6604 11:48:15.074657
6605 11:48:15.075072
6606 11:48:15.081132 [DQSOSCAuto] RK1, (LSB)MR18= 0x9a6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6607 11:48:15.084301 CH0 RK1: MR19=C0C, MR18=9A6D
6608 11:48:15.091173 CH0_RK1: MR19=0xC0C, MR18=0x9A6D, DQSOSC=390, MR23=63, INC=388, DEC=258
6609 11:48:15.093747 [RxdqsGatingPostProcess] freq 400
6610 11:48:15.097328 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6611 11:48:15.100351 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 11:48:15.103401 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 11:48:15.107106 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 11:48:15.110761 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 11:48:15.113759 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 11:48:15.116910 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 11:48:15.120537 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 11:48:15.123981 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 11:48:15.126625 Pre-setting of DQS Precalculation
6620 11:48:15.130075 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6621 11:48:15.130157 ==
6622 11:48:15.133769 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 11:48:15.140566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 11:48:15.140739 ==
6625 11:48:15.143665 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 11:48:15.150359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6627 11:48:15.154128 [CA 0] Center 36 (8~64) winsize 57
6628 11:48:15.157393 [CA 1] Center 36 (8~64) winsize 57
6629 11:48:15.160721 [CA 2] Center 36 (8~64) winsize 57
6630 11:48:15.164260 [CA 3] Center 36 (8~64) winsize 57
6631 11:48:15.167285 [CA 4] Center 36 (8~64) winsize 57
6632 11:48:15.170707 [CA 5] Center 36 (8~64) winsize 57
6633 11:48:15.170988
6634 11:48:15.174505 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6635 11:48:15.174789
6636 11:48:15.177642 [CATrainingPosCal] consider 1 rank data
6637 11:48:15.180646 u2DelayCellTimex100 = 270/100 ps
6638 11:48:15.184570 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:48:15.187983 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:48:15.190974 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:48:15.194481 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:48:15.198167 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:48:15.201551 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 11:48:15.202105
6645 11:48:15.204385 CA PerBit enable=1, Macro0, CA PI delay=36
6646 11:48:15.207675
6647 11:48:15.208225 [CBTSetCACLKResult] CA Dly = 36
6648 11:48:15.211582 CS Dly: 1 (0~32)
6649 11:48:15.212134 ==
6650 11:48:15.214994 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 11:48:15.218631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 11:48:15.219254 ==
6653 11:48:15.224150 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 11:48:15.230768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 11:48:15.234354 [CA 0] Center 36 (8~64) winsize 57
6656 11:48:15.237738 [CA 1] Center 36 (8~64) winsize 57
6657 11:48:15.238198 [CA 2] Center 36 (8~64) winsize 57
6658 11:48:15.241236 [CA 3] Center 36 (8~64) winsize 57
6659 11:48:15.244602 [CA 4] Center 36 (8~64) winsize 57
6660 11:48:15.247679 [CA 5] Center 36 (8~64) winsize 57
6661 11:48:15.248099
6662 11:48:15.251490 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 11:48:15.251909
6664 11:48:15.257611 [CATrainingPosCal] consider 2 rank data
6665 11:48:15.258030 u2DelayCellTimex100 = 270/100 ps
6666 11:48:15.261129 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:48:15.267051 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:48:15.270484 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:48:15.273869 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 11:48:15.277558 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 11:48:15.280897 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 11:48:15.280979
6673 11:48:15.284446 CA PerBit enable=1, Macro0, CA PI delay=36
6674 11:48:15.284866
6675 11:48:15.287584 [CBTSetCACLKResult] CA Dly = 36
6676 11:48:15.288003 CS Dly: 1 (0~32)
6677 11:48:15.291512
6678 11:48:15.294198 ----->DramcWriteLeveling(PI) begin...
6679 11:48:15.294625 ==
6680 11:48:15.297759 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 11:48:15.301545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 11:48:15.302064 ==
6683 11:48:15.304448 Write leveling (Byte 0): 40 => 8
6684 11:48:15.308114 Write leveling (Byte 1): 40 => 8
6685 11:48:15.311576 DramcWriteLeveling(PI) end<-----
6686 11:48:15.312132
6687 11:48:15.312504 ==
6688 11:48:15.314976 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 11:48:15.318031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 11:48:15.318593 ==
6691 11:48:15.321244 [Gating] SW mode calibration
6692 11:48:15.328236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6693 11:48:15.331208 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6694 11:48:15.337988 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6695 11:48:15.341793 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6696 11:48:15.345042 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 11:48:15.351334 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 11:48:15.354786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 11:48:15.358083 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 11:48:15.364649 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 11:48:15.368313 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 11:48:15.371240 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 11:48:15.374358 Total UI for P1: 0, mck2ui 16
6704 11:48:15.377681 best dqsien dly found for B0: ( 0, 14, 24)
6705 11:48:15.381494 Total UI for P1: 0, mck2ui 16
6706 11:48:15.384555 best dqsien dly found for B1: ( 0, 14, 24)
6707 11:48:15.387561 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6708 11:48:15.390504 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6709 11:48:15.390585
6710 11:48:15.397394 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 11:48:15.400932 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 11:48:15.401020 [Gating] SW calibration Done
6713 11:48:15.404972 ==
6714 11:48:15.405389 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 11:48:15.411343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 11:48:15.411766 ==
6717 11:48:15.412101 RX Vref Scan: 0
6718 11:48:15.412412
6719 11:48:15.414418 RX Vref 0 -> 0, step: 1
6720 11:48:15.414837
6721 11:48:15.417704 RX Delay -410 -> 252, step: 16
6722 11:48:15.421226 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6723 11:48:15.424780 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6724 11:48:15.431057 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6725 11:48:15.434693 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6726 11:48:15.438313 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6727 11:48:15.441578 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6728 11:48:15.448586 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6729 11:48:15.451450 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6730 11:48:15.454782 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6731 11:48:15.458349 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6732 11:48:15.465067 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6733 11:48:15.468249 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6734 11:48:15.471525 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6735 11:48:15.475015 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6736 11:48:15.481560 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6737 11:48:15.484697 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6738 11:48:15.485192 ==
6739 11:48:15.487697 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:48:15.491397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:48:15.491958 ==
6742 11:48:15.494139 DQS Delay:
6743 11:48:15.494603 DQS0 = 51, DQS1 = 59
6744 11:48:15.497394 DQM Delay:
6745 11:48:15.497475 DQM0 = 19, DQM1 = 16
6746 11:48:15.497540 DQ Delay:
6747 11:48:15.500889 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6748 11:48:15.504123 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6749 11:48:15.507506 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6750 11:48:15.510503 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6751 11:48:15.510585
6752 11:48:15.510650
6753 11:48:15.510709 ==
6754 11:48:15.513760 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:48:15.520553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:48:15.520636 ==
6757 11:48:15.520701
6758 11:48:15.520761
6759 11:48:15.520819 TX Vref Scan disable
6760 11:48:15.524305 == TX Byte 0 ==
6761 11:48:15.527288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 11:48:15.530464 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 11:48:15.533932 == TX Byte 1 ==
6764 11:48:15.537129 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 11:48:15.540499 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 11:48:15.540581 ==
6767 11:48:15.543968 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 11:48:15.550285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 11:48:15.550385 ==
6770 11:48:15.550464
6771 11:48:15.550525
6772 11:48:15.550616 TX Vref Scan disable
6773 11:48:15.554013 == TX Byte 0 ==
6774 11:48:15.557708 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 11:48:15.560686 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 11:48:15.564252 == TX Byte 1 ==
6777 11:48:15.567220 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 11:48:15.570940 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 11:48:15.571022
6780 11:48:15.574020 [DATLAT]
6781 11:48:15.574102 Freq=400, CH1 RK0
6782 11:48:15.574167
6783 11:48:15.577597 DATLAT Default: 0xf
6784 11:48:15.577678 0, 0xFFFF, sum = 0
6785 11:48:15.580614 1, 0xFFFF, sum = 0
6786 11:48:15.580698 2, 0xFFFF, sum = 0
6787 11:48:15.584309 3, 0xFFFF, sum = 0
6788 11:48:15.584397 4, 0xFFFF, sum = 0
6789 11:48:15.587305 5, 0xFFFF, sum = 0
6790 11:48:15.587387 6, 0xFFFF, sum = 0
6791 11:48:15.590998 7, 0xFFFF, sum = 0
6792 11:48:15.591082 8, 0xFFFF, sum = 0
6793 11:48:15.594186 9, 0xFFFF, sum = 0
6794 11:48:15.594268 10, 0xFFFF, sum = 0
6795 11:48:15.597420 11, 0xFFFF, sum = 0
6796 11:48:15.600782 12, 0xFFFF, sum = 0
6797 11:48:15.600866 13, 0x0, sum = 1
6798 11:48:15.600932 14, 0x0, sum = 2
6799 11:48:15.604022 15, 0x0, sum = 3
6800 11:48:15.604104 16, 0x0, sum = 4
6801 11:48:15.607585 best_step = 14
6802 11:48:15.607667
6803 11:48:15.607732 ==
6804 11:48:15.611092 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 11:48:15.613990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:48:15.614073 ==
6807 11:48:15.617419 RX Vref Scan: 1
6808 11:48:15.617502
6809 11:48:15.617566 RX Vref 0 -> 0, step: 1
6810 11:48:15.617627
6811 11:48:15.620553 RX Delay -359 -> 252, step: 8
6812 11:48:15.620635
6813 11:48:15.624302 Set Vref, RX VrefLevel [Byte0]: 54
6814 11:48:15.627342 [Byte1]: 53
6815 11:48:15.632127
6816 11:48:15.632211 Final RX Vref Byte 0 = 54 to rank0
6817 11:48:15.636022 Final RX Vref Byte 1 = 53 to rank0
6818 11:48:15.639087 Final RX Vref Byte 0 = 54 to rank1
6819 11:48:15.642379 Final RX Vref Byte 1 = 53 to rank1==
6820 11:48:15.645469 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 11:48:15.652190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 11:48:15.652275 ==
6823 11:48:15.652341 DQS Delay:
6824 11:48:15.652402 DQS0 = 48, DQS1 = 60
6825 11:48:15.655566 DQM Delay:
6826 11:48:15.655648 DQM0 = 12, DQM1 = 13
6827 11:48:15.658806 DQ Delay:
6828 11:48:15.662772 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6829 11:48:15.662854 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6830 11:48:15.665731 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6831 11:48:15.668923 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6832 11:48:15.669005
6833 11:48:15.669069
6834 11:48:15.679182 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d36, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6835 11:48:15.682822 CH1 RK0: MR19=C0C, MR18=8D36
6836 11:48:15.689185 CH1_RK0: MR19=0xC0C, MR18=0x8D36, DQSOSC=392, MR23=63, INC=384, DEC=256
6837 11:48:15.689268 ==
6838 11:48:15.692460 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 11:48:15.695909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 11:48:15.695991 ==
6841 11:48:15.698881 [Gating] SW mode calibration
6842 11:48:15.705729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6843 11:48:15.709526 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6844 11:48:15.715837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 11:48:15.719507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 11:48:15.722384 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 11:48:15.728985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 11:48:15.732601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 11:48:15.736450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 11:48:15.742382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 11:48:15.745911 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 11:48:15.749214 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 11:48:15.752572 Total UI for P1: 0, mck2ui 16
6854 11:48:15.756018 best dqsien dly found for B0: ( 0, 14, 24)
6855 11:48:15.759320 Total UI for P1: 0, mck2ui 16
6856 11:48:15.762746 best dqsien dly found for B1: ( 0, 14, 24)
6857 11:48:15.766073 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6858 11:48:15.769357 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6859 11:48:15.769439
6860 11:48:15.772544 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 11:48:15.779348 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 11:48:15.779429 [Gating] SW calibration Done
6863 11:48:15.779495 ==
6864 11:48:15.782818 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 11:48:15.789246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 11:48:15.789328 ==
6867 11:48:15.789393 RX Vref Scan: 0
6868 11:48:15.789454
6869 11:48:15.792800 RX Vref 0 -> 0, step: 1
6870 11:48:15.792881
6871 11:48:15.795975 RX Delay -410 -> 252, step: 16
6872 11:48:15.799709 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6873 11:48:15.802476 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6874 11:48:15.809571 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6875 11:48:15.812899 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6876 11:48:15.816596 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6877 11:48:15.819805 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6878 11:48:15.826388 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6879 11:48:15.829680 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6880 11:48:15.832814 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6881 11:48:15.836461 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6882 11:48:15.842795 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6883 11:48:15.846260 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6884 11:48:15.849668 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6885 11:48:15.852780 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6886 11:48:15.859823 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6887 11:48:15.863217 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6888 11:48:15.863638 ==
6889 11:48:15.866678 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:48:15.869895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:48:15.870319 ==
6892 11:48:15.872960 DQS Delay:
6893 11:48:15.873377 DQS0 = 51, DQS1 = 59
6894 11:48:15.873710 DQM Delay:
6895 11:48:15.876484 DQM0 = 17, DQM1 = 19
6896 11:48:15.876906 DQ Delay:
6897 11:48:15.879743 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6898 11:48:15.883606 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6899 11:48:15.886731 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6900 11:48:15.890007 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =24
6901 11:48:15.890425
6902 11:48:15.890756
6903 11:48:15.891147 ==
6904 11:48:15.893254 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 11:48:15.896997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 11:48:15.900021 ==
6907 11:48:15.900439
6908 11:48:15.900768
6909 11:48:15.901076 TX Vref Scan disable
6910 11:48:15.903186 == TX Byte 0 ==
6911 11:48:15.906821 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6912 11:48:15.909998 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6913 11:48:15.913523 == TX Byte 1 ==
6914 11:48:15.917002 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6915 11:48:15.920017 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6916 11:48:15.920435 ==
6917 11:48:15.923506 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 11:48:15.926777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 11:48:15.929902 ==
6920 11:48:15.930321
6921 11:48:15.930651
6922 11:48:15.931028 TX Vref Scan disable
6923 11:48:15.933212 == TX Byte 0 ==
6924 11:48:15.937049 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6925 11:48:15.940169 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6926 11:48:15.943296 == TX Byte 1 ==
6927 11:48:15.946545 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6928 11:48:15.949865 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6929 11:48:15.950286
6930 11:48:15.950624 [DATLAT]
6931 11:48:15.953145 Freq=400, CH1 RK1
6932 11:48:15.953563
6933 11:48:15.956381 DATLAT Default: 0xe
6934 11:48:15.956462 0, 0xFFFF, sum = 0
6935 11:48:15.959946 1, 0xFFFF, sum = 0
6936 11:48:15.960029 2, 0xFFFF, sum = 0
6937 11:48:15.963308 3, 0xFFFF, sum = 0
6938 11:48:15.963390 4, 0xFFFF, sum = 0
6939 11:48:15.966641 5, 0xFFFF, sum = 0
6940 11:48:15.966730 6, 0xFFFF, sum = 0
6941 11:48:15.969521 7, 0xFFFF, sum = 0
6942 11:48:15.969616 8, 0xFFFF, sum = 0
6943 11:48:15.972809 9, 0xFFFF, sum = 0
6944 11:48:15.972907 10, 0xFFFF, sum = 0
6945 11:48:15.976469 11, 0xFFFF, sum = 0
6946 11:48:15.976574 12, 0xFFFF, sum = 0
6947 11:48:15.979850 13, 0x0, sum = 1
6948 11:48:15.979963 14, 0x0, sum = 2
6949 11:48:15.983235 15, 0x0, sum = 3
6950 11:48:15.983349 16, 0x0, sum = 4
6951 11:48:15.986575 best_step = 14
6952 11:48:15.986696
6953 11:48:15.986792 ==
6954 11:48:15.989586 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:48:15.993168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:48:15.993305 ==
6957 11:48:15.996463 RX Vref Scan: 0
6958 11:48:15.996614
6959 11:48:15.996735 RX Vref 0 -> 0, step: 1
6960 11:48:15.996849
6961 11:48:16.000205 RX Delay -359 -> 252, step: 8
6962 11:48:16.007708 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6963 11:48:16.010934 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6964 11:48:16.014251 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6965 11:48:16.017891 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6966 11:48:16.024396 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6967 11:48:16.027633 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6968 11:48:16.030962 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6969 11:48:16.034583 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6970 11:48:16.041362 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6971 11:48:16.044760 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6972 11:48:16.047840 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6973 11:48:16.051264 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6974 11:48:16.058104 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6975 11:48:16.061365 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6976 11:48:16.064485 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6977 11:48:16.068171 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6978 11:48:16.071431 ==
6979 11:48:16.071878 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 11:48:16.078249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 11:48:16.078673 ==
6982 11:48:16.079066 DQS Delay:
6983 11:48:16.081080 DQS0 = 52, DQS1 = 56
6984 11:48:16.081497 DQM Delay:
6985 11:48:16.084453 DQM0 = 12, DQM1 = 9
6986 11:48:16.084874 DQ Delay:
6987 11:48:16.088121 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6988 11:48:16.091213 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6989 11:48:16.091631 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6990 11:48:16.098111 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6991 11:48:16.098533
6992 11:48:16.098889
6993 11:48:16.104821 [DQSOSCAuto] RK1, (LSB)MR18= 0x7489, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6994 11:48:16.107843 CH1 RK1: MR19=C0C, MR18=7489
6995 11:48:16.114825 CH1_RK1: MR19=0xC0C, MR18=0x7489, DQSOSC=392, MR23=63, INC=384, DEC=256
6996 11:48:16.117685 [RxdqsGatingPostProcess] freq 400
6997 11:48:16.121648 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6998 11:48:16.124798 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 11:48:16.127831 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 11:48:16.131334 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 11:48:16.134739 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 11:48:16.137927 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 11:48:16.141399 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 11:48:16.144741 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 11:48:16.148371 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 11:48:16.151562 Pre-setting of DQS Precalculation
7007 11:48:16.154793 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7008 11:48:16.161444 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7009 11:48:16.171575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7010 11:48:16.171974
7011 11:48:16.172304
7012 11:48:16.172607 [Calibration Summary] 800 Mbps
7013 11:48:16.174632 CH 0, Rank 0
7014 11:48:16.175126 SW Impedance : PASS
7015 11:48:16.178807 DUTY Scan : NO K
7016 11:48:16.181628 ZQ Calibration : PASS
7017 11:48:16.182142 Jitter Meter : NO K
7018 11:48:16.184793 CBT Training : PASS
7019 11:48:16.187953 Write leveling : PASS
7020 11:48:16.188449 RX DQS gating : PASS
7021 11:48:16.191315 RX DQ/DQS(RDDQC) : PASS
7022 11:48:16.194605 TX DQ/DQS : PASS
7023 11:48:16.195090 RX DATLAT : PASS
7024 11:48:16.197987 RX DQ/DQS(Engine): PASS
7025 11:48:16.201250 TX OE : NO K
7026 11:48:16.201677 All Pass.
7027 11:48:16.202052
7028 11:48:16.202364 CH 0, Rank 1
7029 11:48:16.204629 SW Impedance : PASS
7030 11:48:16.207825 DUTY Scan : NO K
7031 11:48:16.208240 ZQ Calibration : PASS
7032 11:48:16.211302 Jitter Meter : NO K
7033 11:48:16.214718 CBT Training : PASS
7034 11:48:16.215109 Write leveling : NO K
7035 11:48:16.217854 RX DQS gating : PASS
7036 11:48:16.218319 RX DQ/DQS(RDDQC) : PASS
7037 11:48:16.221515 TX DQ/DQS : PASS
7038 11:48:16.224335 RX DATLAT : PASS
7039 11:48:16.224755 RX DQ/DQS(Engine): PASS
7040 11:48:16.227785 TX OE : NO K
7041 11:48:16.228197 All Pass.
7042 11:48:16.228519
7043 11:48:16.231789 CH 1, Rank 0
7044 11:48:16.232197 SW Impedance : PASS
7045 11:48:16.234917 DUTY Scan : NO K
7046 11:48:16.238091 ZQ Calibration : PASS
7047 11:48:16.238499 Jitter Meter : NO K
7048 11:48:16.241385 CBT Training : PASS
7049 11:48:16.245008 Write leveling : PASS
7050 11:48:16.245514 RX DQS gating : PASS
7051 11:48:16.248206 RX DQ/DQS(RDDQC) : PASS
7052 11:48:16.251279 TX DQ/DQS : PASS
7053 11:48:16.251694 RX DATLAT : PASS
7054 11:48:16.254653 RX DQ/DQS(Engine): PASS
7055 11:48:16.255154 TX OE : NO K
7056 11:48:16.258622 All Pass.
7057 11:48:16.259195
7058 11:48:16.259534 CH 1, Rank 1
7059 11:48:16.261265 SW Impedance : PASS
7060 11:48:16.261676 DUTY Scan : NO K
7061 11:48:16.265006 ZQ Calibration : PASS
7062 11:48:16.268662 Jitter Meter : NO K
7063 11:48:16.269169 CBT Training : PASS
7064 11:48:16.271268 Write leveling : NO K
7065 11:48:16.274755 RX DQS gating : PASS
7066 11:48:16.275344 RX DQ/DQS(RDDQC) : PASS
7067 11:48:16.278146 TX DQ/DQS : PASS
7068 11:48:16.281789 RX DATLAT : PASS
7069 11:48:16.282298 RX DQ/DQS(Engine): PASS
7070 11:48:16.284782 TX OE : NO K
7071 11:48:16.285291 All Pass.
7072 11:48:16.285744
7073 11:48:16.288138 DramC Write-DBI off
7074 11:48:16.292022 PER_BANK_REFRESH: Hybrid Mode
7075 11:48:16.292545 TX_TRACKING: ON
7076 11:48:16.301380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7077 11:48:16.304718 [FAST_K] Save calibration result to emmc
7078 11:48:16.308301 dramc_set_vcore_voltage set vcore to 725000
7079 11:48:16.311552 Read voltage for 1600, 0
7080 11:48:16.312068 Vio18 = 0
7081 11:48:16.312403 Vcore = 725000
7082 11:48:16.315151 Vdram = 0
7083 11:48:16.315561 Vddq = 0
7084 11:48:16.315905 Vmddr = 0
7085 11:48:16.321583 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7086 11:48:16.324894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7087 11:48:16.328243 MEM_TYPE=3, freq_sel=13
7088 11:48:16.330968 sv_algorithm_assistance_LP4_3733
7089 11:48:16.334369 ============ PULL DRAM RESETB DOWN ============
7090 11:48:16.337706 ========== PULL DRAM RESETB DOWN end =========
7091 11:48:16.344182 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7092 11:48:16.347717 ===================================
7093 11:48:16.347798 LPDDR4 DRAM CONFIGURATION
7094 11:48:16.351194 ===================================
7095 11:48:16.354526 EX_ROW_EN[0] = 0x0
7096 11:48:16.357876 EX_ROW_EN[1] = 0x0
7097 11:48:16.357956 LP4Y_EN = 0x0
7098 11:48:16.361525 WORK_FSP = 0x1
7099 11:48:16.361604 WL = 0x5
7100 11:48:16.364712 RL = 0x5
7101 11:48:16.364792 BL = 0x2
7102 11:48:16.367696 RPST = 0x0
7103 11:48:16.367775 RD_PRE = 0x0
7104 11:48:16.371616 WR_PRE = 0x1
7105 11:48:16.371696 WR_PST = 0x1
7106 11:48:16.374519 DBI_WR = 0x0
7107 11:48:16.374599 DBI_RD = 0x0
7108 11:48:16.377667 OTF = 0x1
7109 11:48:16.380934 ===================================
7110 11:48:16.384306 ===================================
7111 11:48:16.384386 ANA top config
7112 11:48:16.387593 ===================================
7113 11:48:16.391372 DLL_ASYNC_EN = 0
7114 11:48:16.394456 ALL_SLAVE_EN = 0
7115 11:48:16.394535 NEW_RANK_MODE = 1
7116 11:48:16.397997 DLL_IDLE_MODE = 1
7117 11:48:16.401502 LP45_APHY_COMB_EN = 1
7118 11:48:16.404693 TX_ODT_DIS = 0
7119 11:48:16.404773 NEW_8X_MODE = 1
7120 11:48:16.408036 ===================================
7121 11:48:16.411335 ===================================
7122 11:48:16.414430 data_rate = 3200
7123 11:48:16.417779 CKR = 1
7124 11:48:16.421351 DQ_P2S_RATIO = 8
7125 11:48:16.424641 ===================================
7126 11:48:16.427969 CA_P2S_RATIO = 8
7127 11:48:16.431141 DQ_CA_OPEN = 0
7128 11:48:16.431221 DQ_SEMI_OPEN = 0
7129 11:48:16.434475 CA_SEMI_OPEN = 0
7130 11:48:16.438045 CA_FULL_RATE = 0
7131 11:48:16.441193 DQ_CKDIV4_EN = 0
7132 11:48:16.444271 CA_CKDIV4_EN = 0
7133 11:48:16.447746 CA_PREDIV_EN = 0
7134 11:48:16.447826 PH8_DLY = 12
7135 11:48:16.451274 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7136 11:48:16.454965 DQ_AAMCK_DIV = 4
7137 11:48:16.457845 CA_AAMCK_DIV = 4
7138 11:48:16.461191 CA_ADMCK_DIV = 4
7139 11:48:16.464445 DQ_TRACK_CA_EN = 0
7140 11:48:16.468001 CA_PICK = 1600
7141 11:48:16.468080 CA_MCKIO = 1600
7142 11:48:16.471145 MCKIO_SEMI = 0
7143 11:48:16.474595 PLL_FREQ = 3068
7144 11:48:16.478163 DQ_UI_PI_RATIO = 32
7145 11:48:16.481687 CA_UI_PI_RATIO = 0
7146 11:48:16.484520 ===================================
7147 11:48:16.487925 ===================================
7148 11:48:16.491365 memory_type:LPDDR4
7149 11:48:16.491444 GP_NUM : 10
7150 11:48:16.494619 SRAM_EN : 1
7151 11:48:16.494704 MD32_EN : 0
7152 11:48:16.497992 ===================================
7153 11:48:16.501323 [ANA_INIT] >>>>>>>>>>>>>>
7154 11:48:16.504789 <<<<<< [CONFIGURE PHASE]: ANA_TX
7155 11:48:16.508077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7156 11:48:16.511447 ===================================
7157 11:48:16.515190 data_rate = 3200,PCW = 0X7600
7158 11:48:16.517785 ===================================
7159 11:48:16.521553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7160 11:48:16.524668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 11:48:16.531233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 11:48:16.534471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7163 11:48:16.537873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7164 11:48:16.541115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7165 11:48:16.544803 [ANA_INIT] flow start
7166 11:48:16.548041 [ANA_INIT] PLL >>>>>>>>
7167 11:48:16.548128 [ANA_INIT] PLL <<<<<<<<
7168 11:48:16.551962 [ANA_INIT] MIDPI >>>>>>>>
7169 11:48:16.554693 [ANA_INIT] MIDPI <<<<<<<<
7170 11:48:16.557919 [ANA_INIT] DLL >>>>>>>>
7171 11:48:16.557991 [ANA_INIT] DLL <<<<<<<<
7172 11:48:16.561626 [ANA_INIT] flow end
7173 11:48:16.564813 ============ LP4 DIFF to SE enter ============
7174 11:48:16.568085 ============ LP4 DIFF to SE exit ============
7175 11:48:16.571468 [ANA_INIT] <<<<<<<<<<<<<
7176 11:48:16.575025 [Flow] Enable top DCM control >>>>>
7177 11:48:16.578217 [Flow] Enable top DCM control <<<<<
7178 11:48:16.581414 Enable DLL master slave shuffle
7179 11:48:16.588151 ==============================================================
7180 11:48:16.588233 Gating Mode config
7181 11:48:16.594713 ==============================================================
7182 11:48:16.594809 Config description:
7183 11:48:16.605540 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7184 11:48:16.611702 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7185 11:48:16.618145 SELPH_MODE 0: By rank 1: By Phase
7186 11:48:16.621682 ==============================================================
7187 11:48:16.625112 GAT_TRACK_EN = 1
7188 11:48:16.628296 RX_GATING_MODE = 2
7189 11:48:16.632288 RX_GATING_TRACK_MODE = 2
7190 11:48:16.635040 SELPH_MODE = 1
7191 11:48:16.638269 PICG_EARLY_EN = 1
7192 11:48:16.642022 VALID_LAT_VALUE = 1
7193 11:48:16.645185 ==============================================================
7194 11:48:16.648476 Enter into Gating configuration >>>>
7195 11:48:16.651911 Exit from Gating configuration <<<<
7196 11:48:16.655099 Enter into DVFS_PRE_config >>>>>
7197 11:48:16.668721 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7198 11:48:16.669270 Exit from DVFS_PRE_config <<<<<
7199 11:48:16.671586 Enter into PICG configuration >>>>
7200 11:48:16.675337 Exit from PICG configuration <<<<
7201 11:48:16.678354 [RX_INPUT] configuration >>>>>
7202 11:48:16.681519 [RX_INPUT] configuration <<<<<
7203 11:48:16.688393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7204 11:48:16.691710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7205 11:48:16.698388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 11:48:16.705501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 11:48:16.711529 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 11:48:16.718471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 11:48:16.721713 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7210 11:48:16.725151 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7211 11:48:16.728942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7212 11:48:16.735042 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7213 11:48:16.738487 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7214 11:48:16.741889 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 11:48:16.745236 ===================================
7216 11:48:16.749031 LPDDR4 DRAM CONFIGURATION
7217 11:48:16.751788 ===================================
7218 11:48:16.752205 EX_ROW_EN[0] = 0x0
7219 11:48:16.755367 EX_ROW_EN[1] = 0x0
7220 11:48:16.755782 LP4Y_EN = 0x0
7221 11:48:16.758492 WORK_FSP = 0x1
7222 11:48:16.758966 WL = 0x5
7223 11:48:16.761799 RL = 0x5
7224 11:48:16.765456 BL = 0x2
7225 11:48:16.765872 RPST = 0x0
7226 11:48:16.768354 RD_PRE = 0x0
7227 11:48:16.768912 WR_PRE = 0x1
7228 11:48:16.772120 WR_PST = 0x1
7229 11:48:16.772535 DBI_WR = 0x0
7230 11:48:16.774989 DBI_RD = 0x0
7231 11:48:16.775405 OTF = 0x1
7232 11:48:16.778786 ===================================
7233 11:48:16.782036 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7234 11:48:16.785573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7235 11:48:16.792245 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 11:48:16.795249 ===================================
7237 11:48:16.798850 LPDDR4 DRAM CONFIGURATION
7238 11:48:16.802170 ===================================
7239 11:48:16.802582 EX_ROW_EN[0] = 0x10
7240 11:48:16.805219 EX_ROW_EN[1] = 0x0
7241 11:48:16.805634 LP4Y_EN = 0x0
7242 11:48:16.808848 WORK_FSP = 0x1
7243 11:48:16.809264 WL = 0x5
7244 11:48:16.811801 RL = 0x5
7245 11:48:16.812214 BL = 0x2
7246 11:48:16.815119 RPST = 0x0
7247 11:48:16.815534 RD_PRE = 0x0
7248 11:48:16.818544 WR_PRE = 0x1
7249 11:48:16.818990 WR_PST = 0x1
7250 11:48:16.821790 DBI_WR = 0x0
7251 11:48:16.822207 DBI_RD = 0x0
7252 11:48:16.825273 OTF = 0x1
7253 11:48:16.829023 ===================================
7254 11:48:16.835018 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7255 11:48:16.835435 ==
7256 11:48:16.838538 Dram Type= 6, Freq= 0, CH_0, rank 0
7257 11:48:16.841976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7258 11:48:16.842394 ==
7259 11:48:16.845288 [Duty_Offset_Calibration]
7260 11:48:16.845705 B0:2 B1:-1 CA:1
7261 11:48:16.846037
7262 11:48:16.848412 [DutyScan_Calibration_Flow] k_type=0
7263 11:48:16.858792
7264 11:48:16.859270 ==CLK 0==
7265 11:48:16.862505 Final CLK duty delay cell = -4
7266 11:48:16.865947 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7267 11:48:16.868695 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7268 11:48:16.872148 [-4] AVG Duty = 4937%(X100)
7269 11:48:16.872563
7270 11:48:16.875792 CH0 CLK Duty spec in!! Max-Min= 187%
7271 11:48:16.878911 [DutyScan_Calibration_Flow] ====Done====
7272 11:48:16.879331
7273 11:48:16.882761 [DutyScan_Calibration_Flow] k_type=1
7274 11:48:16.898668
7275 11:48:16.899171 ==DQS 0 ==
7276 11:48:16.901505 Final DQS duty delay cell = 0
7277 11:48:16.905002 [0] MAX Duty = 5125%(X100), DQS PI = 20
7278 11:48:16.908425 [0] MIN Duty = 5000%(X100), DQS PI = 14
7279 11:48:16.911419 [0] AVG Duty = 5062%(X100)
7280 11:48:16.911834
7281 11:48:16.912164 ==DQS 1 ==
7282 11:48:16.914920 Final DQS duty delay cell = -4
7283 11:48:16.918205 [-4] MAX Duty = 5125%(X100), DQS PI = 2
7284 11:48:16.921255 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7285 11:48:16.925286 [-4] AVG Duty = 5078%(X100)
7286 11:48:16.925701
7287 11:48:16.928187 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7288 11:48:16.928603
7289 11:48:16.931245 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7290 11:48:16.935155 [DutyScan_Calibration_Flow] ====Done====
7291 11:48:16.935573
7292 11:48:16.938414 [DutyScan_Calibration_Flow] k_type=3
7293 11:48:16.955468
7294 11:48:16.955896 ==DQM 0 ==
7295 11:48:16.958610 Final DQM duty delay cell = 0
7296 11:48:16.961967 [0] MAX Duty = 5000%(X100), DQS PI = 20
7297 11:48:16.965749 [0] MIN Duty = 4875%(X100), DQS PI = 4
7298 11:48:16.966168 [0] AVG Duty = 4937%(X100)
7299 11:48:16.968946
7300 11:48:16.969356 ==DQM 1 ==
7301 11:48:16.971942 Final DQM duty delay cell = 0
7302 11:48:16.975622 [0] MAX Duty = 5218%(X100), DQS PI = 58
7303 11:48:16.978975 [0] MIN Duty = 4969%(X100), DQS PI = 18
7304 11:48:16.979389 [0] AVG Duty = 5093%(X100)
7305 11:48:16.982085
7306 11:48:16.985372 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7307 11:48:16.985787
7308 11:48:16.989357 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7309 11:48:16.992518 [DutyScan_Calibration_Flow] ====Done====
7310 11:48:16.992932
7311 11:48:16.995961 [DutyScan_Calibration_Flow] k_type=2
7312 11:48:17.011880
7313 11:48:17.012310 ==DQ 0 ==
7314 11:48:17.015387 Final DQ duty delay cell = -4
7315 11:48:17.018190 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7316 11:48:17.021664 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7317 11:48:17.025273 [-4] AVG Duty = 4922%(X100)
7318 11:48:17.025809
7319 11:48:17.026320 ==DQ 1 ==
7320 11:48:17.028540 Final DQ duty delay cell = 0
7321 11:48:17.031846 [0] MAX Duty = 5031%(X100), DQS PI = 30
7322 11:48:17.034964 [0] MIN Duty = 4907%(X100), DQS PI = 18
7323 11:48:17.035382 [0] AVG Duty = 4969%(X100)
7324 11:48:17.038229
7325 11:48:17.041587 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7326 11:48:17.042003
7327 11:48:17.045317 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7328 11:48:17.048344 [DutyScan_Calibration_Flow] ====Done====
7329 11:48:17.048760 ==
7330 11:48:17.051707 Dram Type= 6, Freq= 0, CH_1, rank 0
7331 11:48:17.055020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 11:48:17.055442 ==
7333 11:48:17.058382 [Duty_Offset_Calibration]
7334 11:48:17.058797 B0:1 B1:1 CA:2
7335 11:48:17.059184
7336 11:48:17.061900 [DutyScan_Calibration_Flow] k_type=0
7337 11:48:17.071921
7338 11:48:17.072333 ==CLK 0==
7339 11:48:17.075780 Final CLK duty delay cell = 0
7340 11:48:17.078556 [0] MAX Duty = 5187%(X100), DQS PI = 26
7341 11:48:17.082071 [0] MIN Duty = 4938%(X100), DQS PI = 48
7342 11:48:17.082487 [0] AVG Duty = 5062%(X100)
7343 11:48:17.085360
7344 11:48:17.088805 CH1 CLK Duty spec in!! Max-Min= 249%
7345 11:48:17.091907 [DutyScan_Calibration_Flow] ====Done====
7346 11:48:17.091988
7347 11:48:17.094722 [DutyScan_Calibration_Flow] k_type=1
7348 11:48:17.111687
7349 11:48:17.111788 ==DQS 0 ==
7350 11:48:17.114890 Final DQS duty delay cell = 0
7351 11:48:17.118238 [0] MAX Duty = 5062%(X100), DQS PI = 22
7352 11:48:17.121190 [0] MIN Duty = 4813%(X100), DQS PI = 52
7353 11:48:17.121274 [0] AVG Duty = 4937%(X100)
7354 11:48:17.125011
7355 11:48:17.125091 ==DQS 1 ==
7356 11:48:17.128257 Final DQS duty delay cell = 0
7357 11:48:17.131593 [0] MAX Duty = 5031%(X100), DQS PI = 34
7358 11:48:17.135121 [0] MIN Duty = 4938%(X100), DQS PI = 12
7359 11:48:17.135203 [0] AVG Duty = 4984%(X100)
7360 11:48:17.138190
7361 11:48:17.141964 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7362 11:48:17.142046
7363 11:48:17.145288 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7364 11:48:17.148299 [DutyScan_Calibration_Flow] ====Done====
7365 11:48:17.148381
7366 11:48:17.151602 [DutyScan_Calibration_Flow] k_type=3
7367 11:48:17.168007
7368 11:48:17.168088 ==DQM 0 ==
7369 11:48:17.171601 Final DQM duty delay cell = 0
7370 11:48:17.174908 [0] MAX Duty = 5156%(X100), DQS PI = 20
7371 11:48:17.178501 [0] MIN Duty = 4813%(X100), DQS PI = 50
7372 11:48:17.181702 [0] AVG Duty = 4984%(X100)
7373 11:48:17.181783
7374 11:48:17.181848 ==DQM 1 ==
7375 11:48:17.184823 Final DQM duty delay cell = 0
7376 11:48:17.188439 [0] MAX Duty = 5156%(X100), DQS PI = 10
7377 11:48:17.191680 [0] MIN Duty = 4907%(X100), DQS PI = 20
7378 11:48:17.195035 [0] AVG Duty = 5031%(X100)
7379 11:48:17.195455
7380 11:48:17.198780 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7381 11:48:17.199260
7382 11:48:17.201605 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7383 11:48:17.205095 [DutyScan_Calibration_Flow] ====Done====
7384 11:48:17.205176
7385 11:48:17.208280 [DutyScan_Calibration_Flow] k_type=2
7386 11:48:17.225455
7387 11:48:17.225539 ==DQ 0 ==
7388 11:48:17.228491 Final DQ duty delay cell = 0
7389 11:48:17.232151 [0] MAX Duty = 5156%(X100), DQS PI = 22
7390 11:48:17.235279 [0] MIN Duty = 4907%(X100), DQS PI = 52
7391 11:48:17.235361 [0] AVG Duty = 5031%(X100)
7392 11:48:17.235426
7393 11:48:17.238456 ==DQ 1 ==
7394 11:48:17.242248 Final DQ duty delay cell = 0
7395 11:48:17.245752 [0] MAX Duty = 5093%(X100), DQS PI = 8
7396 11:48:17.248889 [0] MIN Duty = 5031%(X100), DQS PI = 2
7397 11:48:17.249070 [0] AVG Duty = 5062%(X100)
7398 11:48:17.249161
7399 11:48:17.252156 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7400 11:48:17.252309
7401 11:48:17.255705 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7402 11:48:17.259045 [DutyScan_Calibration_Flow] ====Done====
7403 11:48:17.264355 nWR fixed to 30
7404 11:48:17.267346 [ModeRegInit_LP4] CH0 RK0
7405 11:48:17.267550 [ModeRegInit_LP4] CH0 RK1
7406 11:48:17.270843 [ModeRegInit_LP4] CH1 RK0
7407 11:48:17.274201 [ModeRegInit_LP4] CH1 RK1
7408 11:48:17.274421 match AC timing 5
7409 11:48:17.280898 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7410 11:48:17.283893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7411 11:48:17.287260 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7412 11:48:17.294145 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7413 11:48:17.297587 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7414 11:48:17.297971 [MiockJmeterHQA]
7415 11:48:17.298278
7416 11:48:17.300976 [DramcMiockJmeter] u1RxGatingPI = 0
7417 11:48:17.304431 0 : 4366, 4137
7418 11:48:17.304855 4 : 4253, 4026
7419 11:48:17.307675 8 : 4368, 4140
7420 11:48:17.308106 12 : 4253, 4026
7421 11:48:17.311203 16 : 4363, 4137
7422 11:48:17.311630 20 : 4253, 4027
7423 11:48:17.311970 24 : 4252, 4027
7424 11:48:17.314609 28 : 4255, 4029
7425 11:48:17.315085 32 : 4252, 4029
7426 11:48:17.317876 36 : 4250, 4027
7427 11:48:17.318326 40 : 4363, 4137
7428 11:48:17.321012 44 : 4255, 4029
7429 11:48:17.321438 48 : 4253, 4027
7430 11:48:17.321779 52 : 4257, 4030
7431 11:48:17.324683 56 : 4250, 4027
7432 11:48:17.325106 60 : 4250, 4027
7433 11:48:17.327758 64 : 4366, 4142
7434 11:48:17.328183 68 : 4361, 4138
7435 11:48:17.331018 72 : 4250, 4027
7436 11:48:17.331449 76 : 4252, 4029
7437 11:48:17.334455 80 : 4250, 4027
7438 11:48:17.334918 84 : 4250, 4026
7439 11:48:17.335271 88 : 4361, 4137
7440 11:48:17.338012 92 : 4250, 4027
7441 11:48:17.338437 96 : 4250, 3331
7442 11:48:17.341449 100 : 4361, 0
7443 11:48:17.341893 104 : 4250, 0
7444 11:48:17.342231 108 : 4363, 0
7445 11:48:17.344398 112 : 4252, 0
7446 11:48:17.344822 116 : 4250, 0
7447 11:48:17.347928 120 : 4258, 0
7448 11:48:17.348351 124 : 4250, 0
7449 11:48:17.348729 128 : 4361, 0
7450 11:48:17.351466 132 : 4252, 0
7451 11:48:17.351892 136 : 4249, 0
7452 11:48:17.354673 140 : 4253, 0
7453 11:48:17.355160 144 : 4366, 0
7454 11:48:17.355506 148 : 4250, 0
7455 11:48:17.357979 152 : 4360, 0
7456 11:48:17.358404 156 : 4363, 0
7457 11:48:17.358744 160 : 4253, 0
7458 11:48:17.361367 164 : 4250, 0
7459 11:48:17.361794 168 : 4364, 0
7460 11:48:17.364363 172 : 4253, 0
7461 11:48:17.364788 176 : 4364, 0
7462 11:48:17.365128 180 : 4250, 0
7463 11:48:17.367883 184 : 4250, 0
7464 11:48:17.368310 188 : 4363, 0
7465 11:48:17.371142 192 : 4363, 0
7466 11:48:17.371568 196 : 4252, 0
7467 11:48:17.371912 200 : 4252, 0
7468 11:48:17.374978 204 : 4363, 0
7469 11:48:17.375522 208 : 4365, 0
7470 11:48:17.377769 212 : 4253, 100
7471 11:48:17.378194 216 : 4250, 3789
7472 11:48:17.378532 220 : 4253, 4029
7473 11:48:17.381293 224 : 4363, 4140
7474 11:48:17.381718 228 : 4253, 4029
7475 11:48:17.384539 232 : 4363, 4137
7476 11:48:17.384962 236 : 4253, 4029
7477 11:48:17.388329 240 : 4249, 4027
7478 11:48:17.388754 244 : 4250, 4027
7479 11:48:17.391422 248 : 4252, 4030
7480 11:48:17.391843 252 : 4250, 4027
7481 11:48:17.394513 256 : 4252, 4029
7482 11:48:17.394981 260 : 4363, 4140
7483 11:48:17.397902 264 : 4250, 4027
7484 11:48:17.398328 268 : 4252, 4027
7485 11:48:17.401296 272 : 4252, 4029
7486 11:48:17.401722 276 : 4250, 4027
7487 11:48:17.402062 280 : 4255, 4029
7488 11:48:17.404480 284 : 4250, 4027
7489 11:48:17.404902 288 : 4254, 4030
7490 11:48:17.407954 292 : 4361, 4138
7491 11:48:17.408380 296 : 4252, 4029
7492 11:48:17.411245 300 : 4250, 4027
7493 11:48:17.411670 304 : 4252, 4029
7494 11:48:17.415028 308 : 4250, 4026
7495 11:48:17.415458 312 : 4252, 4030
7496 11:48:17.417786 316 : 4257, 4032
7497 11:48:17.418212 320 : 4250, 4027
7498 11:48:17.421741 324 : 4365, 4140
7499 11:48:17.422166 328 : 4361, 4137
7500 11:48:17.422506 332 : 4247, 3032
7501 11:48:17.424709 336 : 4255, 59
7502 11:48:17.425141
7503 11:48:17.427803 MIOCK jitter meter ch=0
7504 11:48:17.428223
7505 11:48:17.431347 1T = (336-100) = 236 dly cells
7506 11:48:17.434389 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7507 11:48:17.434470 ==
7508 11:48:17.437725 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 11:48:17.444195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7510 11:48:17.444277 ==
7511 11:48:17.448004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7512 11:48:17.450790 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7513 11:48:17.457763 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7514 11:48:17.464214 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7515 11:48:17.471526 [CA 0] Center 44 (14~75) winsize 62
7516 11:48:17.475223 [CA 1] Center 44 (14~74) winsize 61
7517 11:48:17.478557 [CA 2] Center 39 (10~68) winsize 59
7518 11:48:17.481745 [CA 3] Center 39 (10~68) winsize 59
7519 11:48:17.484971 [CA 4] Center 37 (7~67) winsize 61
7520 11:48:17.488390 [CA 5] Center 37 (7~67) winsize 61
7521 11:48:17.488471
7522 11:48:17.491756 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7523 11:48:17.491843
7524 11:48:17.495376 [CATrainingPosCal] consider 1 rank data
7525 11:48:17.498780 u2DelayCellTimex100 = 275/100 ps
7526 11:48:17.502061 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7527 11:48:17.508654 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7528 11:48:17.511793 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7529 11:48:17.515395 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7530 11:48:17.519098 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7531 11:48:17.521853 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7532 11:48:17.522003
7533 11:48:17.525325 CA PerBit enable=1, Macro0, CA PI delay=37
7534 11:48:17.525498
7535 11:48:17.528580 [CBTSetCACLKResult] CA Dly = 37
7536 11:48:17.531846 CS Dly: 11 (0~42)
7537 11:48:17.535373 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7538 11:48:17.538349 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7539 11:48:17.538588 ==
7540 11:48:17.541827 Dram Type= 6, Freq= 0, CH_0, rank 1
7541 11:48:17.545755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 11:48:17.548457 ==
7543 11:48:17.552459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 11:48:17.555665 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 11:48:17.562196 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 11:48:17.565458 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 11:48:17.575872 [CA 0] Center 44 (14~74) winsize 61
7548 11:48:17.578972 [CA 1] Center 43 (13~74) winsize 62
7549 11:48:17.582754 [CA 2] Center 39 (10~69) winsize 60
7550 11:48:17.585581 [CA 3] Center 38 (9~68) winsize 60
7551 11:48:17.589164 [CA 4] Center 37 (7~67) winsize 61
7552 11:48:17.592793 [CA 5] Center 37 (7~67) winsize 61
7553 11:48:17.593214
7554 11:48:17.596126 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 11:48:17.596543
7556 11:48:17.599289 [CATrainingPosCal] consider 2 rank data
7557 11:48:17.602228 u2DelayCellTimex100 = 275/100 ps
7558 11:48:17.605643 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7559 11:48:17.612474 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7560 11:48:17.615986 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7561 11:48:17.619283 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7562 11:48:17.622351 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7563 11:48:17.625570 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7564 11:48:17.626013
7565 11:48:17.629170 CA PerBit enable=1, Macro0, CA PI delay=37
7566 11:48:17.629717
7567 11:48:17.632262 [CBTSetCACLKResult] CA Dly = 37
7568 11:48:17.635982 CS Dly: 12 (0~44)
7569 11:48:17.639106 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 11:48:17.642416 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 11:48:17.642834
7572 11:48:17.645569 ----->DramcWriteLeveling(PI) begin...
7573 11:48:17.645993 ==
7574 11:48:17.648926 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 11:48:17.652461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 11:48:17.655794 ==
7577 11:48:17.656212 Write leveling (Byte 0): 32 => 32
7578 11:48:17.659090 Write leveling (Byte 1): 28 => 28
7579 11:48:17.662888 DramcWriteLeveling(PI) end<-----
7580 11:48:17.663314
7581 11:48:17.663648 ==
7582 11:48:17.665553 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 11:48:17.672549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 11:48:17.672973 ==
7585 11:48:17.673310 [Gating] SW mode calibration
7586 11:48:17.682235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7587 11:48:17.685782 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7588 11:48:17.689255 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 11:48:17.695647 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 11:48:17.699272 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 11:48:17.702281 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 11:48:17.709322 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 11:48:17.712400 1 4 20 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
7594 11:48:17.715638 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7595 11:48:17.722299 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 11:48:17.725520 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 11:48:17.729007 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 11:48:17.735853 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 11:48:17.739215 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 11:48:17.742463 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7601 11:48:17.749424 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7602 11:48:17.752392 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7603 11:48:17.755967 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 11:48:17.762678 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 11:48:17.766093 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 11:48:17.769392 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 11:48:17.775776 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7608 11:48:17.779700 1 6 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7609 11:48:17.782628 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7610 11:48:17.785623 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7611 11:48:17.792456 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 11:48:17.795867 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 11:48:17.799175 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 11:48:17.806001 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 11:48:17.809484 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 11:48:17.812686 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 11:48:17.819188 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7618 11:48:17.822296 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 11:48:17.825827 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 11:48:17.832790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 11:48:17.835799 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:48:17.839342 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:48:17.845944 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:48:17.849626 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:48:17.852789 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:48:17.859672 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 11:48:17.862577 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 11:48:17.866376 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 11:48:17.869180 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:48:17.876218 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 11:48:17.879292 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 11:48:17.883022 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 11:48:17.886032 Total UI for P1: 0, mck2ui 16
7634 11:48:17.889708 best dqsien dly found for B0: ( 1, 9, 14)
7635 11:48:17.895984 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 11:48:17.899294 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 11:48:17.902967 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 11:48:17.905761 Total UI for P1: 0, mck2ui 16
7639 11:48:17.909295 best dqsien dly found for B1: ( 1, 9, 20)
7640 11:48:17.913080 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7641 11:48:17.915889 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7642 11:48:17.916310
7643 11:48:17.922781 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7644 11:48:17.925907 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7645 11:48:17.929546 [Gating] SW calibration Done
7646 11:48:17.929965 ==
7647 11:48:17.932559 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 11:48:17.935707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 11:48:17.936127 ==
7650 11:48:17.936457 RX Vref Scan: 0
7651 11:48:17.936768
7652 11:48:17.939034 RX Vref 0 -> 0, step: 1
7653 11:48:17.939453
7654 11:48:17.942520 RX Delay 0 -> 252, step: 8
7655 11:48:17.945950 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7656 11:48:17.949354 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7657 11:48:17.952959 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7658 11:48:17.959521 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7659 11:48:17.962670 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7660 11:48:17.965952 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7661 11:48:17.969176 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7662 11:48:17.972705 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7663 11:48:17.979434 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7664 11:48:17.982818 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7665 11:48:17.986331 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7666 11:48:17.989488 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7667 11:48:17.992494 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7668 11:48:18.000162 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7669 11:48:18.003333 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7670 11:48:18.006029 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7671 11:48:18.006450 ==
7672 11:48:18.009461 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 11:48:18.012510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 11:48:18.012930 ==
7675 11:48:18.016035 DQS Delay:
7676 11:48:18.016451 DQS0 = 0, DQS1 = 0
7677 11:48:18.019233 DQM Delay:
7678 11:48:18.019704 DQM0 = 132, DQM1 = 123
7679 11:48:18.020060 DQ Delay:
7680 11:48:18.022668 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7681 11:48:18.029271 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7682 11:48:18.032587 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7683 11:48:18.036155 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7684 11:48:18.036576
7685 11:48:18.036908
7686 11:48:18.037214 ==
7687 11:48:18.039430 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 11:48:18.043214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 11:48:18.043634 ==
7690 11:48:18.043967
7691 11:48:18.044275
7692 11:48:18.046760 TX Vref Scan disable
7693 11:48:18.049699 == TX Byte 0 ==
7694 11:48:18.052970 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7695 11:48:18.056290 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7696 11:48:18.059505 == TX Byte 1 ==
7697 11:48:18.062755 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7698 11:48:18.066148 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7699 11:48:18.066571 ==
7700 11:48:18.069656 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 11:48:18.072989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 11:48:18.073411 ==
7703 11:48:18.088541
7704 11:48:18.092123 TX Vref early break, caculate TX vref
7705 11:48:18.095578 TX Vref=16, minBit 0, minWin=21, winSum=358
7706 11:48:18.098604 TX Vref=18, minBit 0, minWin=22, winSum=372
7707 11:48:18.102027 TX Vref=20, minBit 0, minWin=22, winSum=375
7708 11:48:18.105190 TX Vref=22, minBit 7, minWin=22, winSum=388
7709 11:48:18.108541 TX Vref=24, minBit 1, minWin=23, winSum=403
7710 11:48:18.115593 TX Vref=26, minBit 1, minWin=24, winSum=407
7711 11:48:18.118617 TX Vref=28, minBit 4, minWin=24, winSum=417
7712 11:48:18.122351 TX Vref=30, minBit 4, minWin=24, winSum=417
7713 11:48:18.125713 TX Vref=32, minBit 0, minWin=24, winSum=411
7714 11:48:18.128919 TX Vref=34, minBit 4, minWin=23, winSum=398
7715 11:48:18.131946 TX Vref=36, minBit 4, minWin=22, winSum=388
7716 11:48:18.138752 [TxChooseVref] Worse bit 4, Min win 24, Win sum 417, Final Vref 28
7717 11:48:18.139206
7718 11:48:18.142665 Final TX Range 0 Vref 28
7719 11:48:18.143136
7720 11:48:18.143516 ==
7721 11:48:18.145652 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 11:48:18.148669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 11:48:18.149091 ==
7724 11:48:18.149422
7725 11:48:18.149732
7726 11:48:18.152043 TX Vref Scan disable
7727 11:48:18.159221 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7728 11:48:18.159642 == TX Byte 0 ==
7729 11:48:18.162148 u2DelayCellOfst[0]=14 cells (4 PI)
7730 11:48:18.165786 u2DelayCellOfst[1]=17 cells (5 PI)
7731 11:48:18.168944 u2DelayCellOfst[2]=10 cells (3 PI)
7732 11:48:18.172397 u2DelayCellOfst[3]=14 cells (4 PI)
7733 11:48:18.175859 u2DelayCellOfst[4]=7 cells (2 PI)
7734 11:48:18.179098 u2DelayCellOfst[5]=0 cells (0 PI)
7735 11:48:18.182734 u2DelayCellOfst[6]=17 cells (5 PI)
7736 11:48:18.183196 u2DelayCellOfst[7]=17 cells (5 PI)
7737 11:48:18.189026 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7738 11:48:18.192174 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7739 11:48:18.192596 == TX Byte 1 ==
7740 11:48:18.195418 u2DelayCellOfst[8]=0 cells (0 PI)
7741 11:48:18.199375 u2DelayCellOfst[9]=0 cells (0 PI)
7742 11:48:18.202281 u2DelayCellOfst[10]=7 cells (2 PI)
7743 11:48:18.205636 u2DelayCellOfst[11]=0 cells (0 PI)
7744 11:48:18.209213 u2DelayCellOfst[12]=14 cells (4 PI)
7745 11:48:18.212374 u2DelayCellOfst[13]=10 cells (3 PI)
7746 11:48:18.215637 u2DelayCellOfst[14]=17 cells (5 PI)
7747 11:48:18.219275 u2DelayCellOfst[15]=10 cells (3 PI)
7748 11:48:18.222623 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7749 11:48:18.225780 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7750 11:48:18.229608 DramC Write-DBI on
7751 11:48:18.230027 ==
7752 11:48:18.232295 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 11:48:18.236209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 11:48:18.236629 ==
7755 11:48:18.236964
7756 11:48:18.237272
7757 11:48:18.239375 TX Vref Scan disable
7758 11:48:18.242309 == TX Byte 0 ==
7759 11:48:18.246147 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7760 11:48:18.248953 == TX Byte 1 ==
7761 11:48:18.252232 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7762 11:48:18.252682 DramC Write-DBI off
7763 11:48:18.253017
7764 11:48:18.255865 [DATLAT]
7765 11:48:18.256280 Freq=1600, CH0 RK0
7766 11:48:18.256614
7767 11:48:18.258765 DATLAT Default: 0xf
7768 11:48:18.259229 0, 0xFFFF, sum = 0
7769 11:48:18.262124 1, 0xFFFF, sum = 0
7770 11:48:18.262598 2, 0xFFFF, sum = 0
7771 11:48:18.265615 3, 0xFFFF, sum = 0
7772 11:48:18.266038 4, 0xFFFF, sum = 0
7773 11:48:18.269270 5, 0xFFFF, sum = 0
7774 11:48:18.269739 6, 0xFFFF, sum = 0
7775 11:48:18.272717 7, 0xFFFF, sum = 0
7776 11:48:18.273143 8, 0xFFFF, sum = 0
7777 11:48:18.275772 9, 0xFFFF, sum = 0
7778 11:48:18.279420 10, 0xFFFF, sum = 0
7779 11:48:18.279844 11, 0xFFFF, sum = 0
7780 11:48:18.282520 12, 0xFFFF, sum = 0
7781 11:48:18.282971 13, 0xFFFF, sum = 0
7782 11:48:18.285754 14, 0x0, sum = 1
7783 11:48:18.286178 15, 0x0, sum = 2
7784 11:48:18.288922 16, 0x0, sum = 3
7785 11:48:18.289349 17, 0x0, sum = 4
7786 11:48:18.289686 best_step = 15
7787 11:48:18.289998
7788 11:48:18.292480 ==
7789 11:48:18.295702 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 11:48:18.299384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 11:48:18.299806 ==
7792 11:48:18.300140 RX Vref Scan: 1
7793 11:48:18.300452
7794 11:48:18.302118 Set Vref Range= 24 -> 127
7795 11:48:18.302537
7796 11:48:18.305758 RX Vref 24 -> 127, step: 1
7797 11:48:18.306177
7798 11:48:18.309353 RX Delay 11 -> 252, step: 4
7799 11:48:18.309770
7800 11:48:18.312366 Set Vref, RX VrefLevel [Byte0]: 24
7801 11:48:18.316006 [Byte1]: 24
7802 11:48:18.316427
7803 11:48:18.319279 Set Vref, RX VrefLevel [Byte0]: 25
7804 11:48:18.321928 [Byte1]: 25
7805 11:48:18.322361
7806 11:48:18.325697 Set Vref, RX VrefLevel [Byte0]: 26
7807 11:48:18.328712 [Byte1]: 26
7808 11:48:18.332194
7809 11:48:18.332609 Set Vref, RX VrefLevel [Byte0]: 27
7810 11:48:18.335669 [Byte1]: 27
7811 11:48:18.340510
7812 11:48:18.340928 Set Vref, RX VrefLevel [Byte0]: 28
7813 11:48:18.343643 [Byte1]: 28
7814 11:48:18.347597
7815 11:48:18.348013 Set Vref, RX VrefLevel [Byte0]: 29
7816 11:48:18.350718 [Byte1]: 29
7817 11:48:18.355054
7818 11:48:18.355488 Set Vref, RX VrefLevel [Byte0]: 30
7819 11:48:18.358494 [Byte1]: 30
7820 11:48:18.362793
7821 11:48:18.363282 Set Vref, RX VrefLevel [Byte0]: 31
7822 11:48:18.366055 [Byte1]: 31
7823 11:48:18.370320
7824 11:48:18.370907 Set Vref, RX VrefLevel [Byte0]: 32
7825 11:48:18.373652 [Byte1]: 32
7826 11:48:18.377836
7827 11:48:18.378270 Set Vref, RX VrefLevel [Byte0]: 33
7828 11:48:18.381220 [Byte1]: 33
7829 11:48:18.385675
7830 11:48:18.386127 Set Vref, RX VrefLevel [Byte0]: 34
7831 11:48:18.389181 [Byte1]: 34
7832 11:48:18.393084
7833 11:48:18.393635 Set Vref, RX VrefLevel [Byte0]: 35
7834 11:48:18.396340 [Byte1]: 35
7835 11:48:18.400592
7836 11:48:18.401163 Set Vref, RX VrefLevel [Byte0]: 36
7837 11:48:18.403979 [Byte1]: 36
7838 11:48:18.408739
7839 11:48:18.409182 Set Vref, RX VrefLevel [Byte0]: 37
7840 11:48:18.412002 [Byte1]: 37
7841 11:48:18.415981
7842 11:48:18.416436 Set Vref, RX VrefLevel [Byte0]: 38
7843 11:48:18.419319 [Byte1]: 38
7844 11:48:18.423355
7845 11:48:18.423789 Set Vref, RX VrefLevel [Byte0]: 39
7846 11:48:18.426732 [Byte1]: 39
7847 11:48:18.431363
7848 11:48:18.431814 Set Vref, RX VrefLevel [Byte0]: 40
7849 11:48:18.434355 [Byte1]: 40
7850 11:48:18.438690
7851 11:48:18.439231 Set Vref, RX VrefLevel [Byte0]: 41
7852 11:48:18.441968 [Byte1]: 41
7853 11:48:18.446339
7854 11:48:18.446767 Set Vref, RX VrefLevel [Byte0]: 42
7855 11:48:18.449820 [Byte1]: 42
7856 11:48:18.454221
7857 11:48:18.454650 Set Vref, RX VrefLevel [Byte0]: 43
7858 11:48:18.457761 [Byte1]: 43
7859 11:48:18.461598
7860 11:48:18.462026 Set Vref, RX VrefLevel [Byte0]: 44
7861 11:48:18.465110 [Byte1]: 44
7862 11:48:18.469083
7863 11:48:18.469548 Set Vref, RX VrefLevel [Byte0]: 45
7864 11:48:18.472987 [Byte1]: 45
7865 11:48:18.477055
7866 11:48:18.477487 Set Vref, RX VrefLevel [Byte0]: 46
7867 11:48:18.480313 [Byte1]: 46
7868 11:48:18.484505
7869 11:48:18.484947 Set Vref, RX VrefLevel [Byte0]: 47
7870 11:48:18.488189 [Byte1]: 47
7871 11:48:18.492258
7872 11:48:18.492725 Set Vref, RX VrefLevel [Byte0]: 48
7873 11:48:18.495558 [Byte1]: 48
7874 11:48:18.499945
7875 11:48:18.500403 Set Vref, RX VrefLevel [Byte0]: 49
7876 11:48:18.503237 [Byte1]: 49
7877 11:48:18.507187
7878 11:48:18.507677 Set Vref, RX VrefLevel [Byte0]: 50
7879 11:48:18.510714 [Byte1]: 50
7880 11:48:18.514828
7881 11:48:18.515284 Set Vref, RX VrefLevel [Byte0]: 51
7882 11:48:18.518972 [Byte1]: 51
7883 11:48:18.522408
7884 11:48:18.522999 Set Vref, RX VrefLevel [Byte0]: 52
7885 11:48:18.525843 [Byte1]: 52
7886 11:48:18.529954
7887 11:48:18.530510 Set Vref, RX VrefLevel [Byte0]: 53
7888 11:48:18.533663 [Byte1]: 53
7889 11:48:18.537747
7890 11:48:18.538296 Set Vref, RX VrefLevel [Byte0]: 54
7891 11:48:18.541198 [Byte1]: 54
7892 11:48:18.545601
7893 11:48:18.546040 Set Vref, RX VrefLevel [Byte0]: 55
7894 11:48:18.548821 [Byte1]: 55
7895 11:48:18.553271
7896 11:48:18.553701 Set Vref, RX VrefLevel [Byte0]: 56
7897 11:48:18.557192 [Byte1]: 56
7898 11:48:18.560856
7899 11:48:18.561306 Set Vref, RX VrefLevel [Byte0]: 57
7900 11:48:18.563955 [Byte1]: 57
7901 11:48:18.568514
7902 11:48:18.568950 Set Vref, RX VrefLevel [Byte0]: 58
7903 11:48:18.571685 [Byte1]: 58
7904 11:48:18.576145
7905 11:48:18.576716 Set Vref, RX VrefLevel [Byte0]: 59
7906 11:48:18.579472 [Byte1]: 59
7907 11:48:18.583320
7908 11:48:18.583737 Set Vref, RX VrefLevel [Byte0]: 60
7909 11:48:18.586965 [Byte1]: 60
7910 11:48:18.591182
7911 11:48:18.591627 Set Vref, RX VrefLevel [Byte0]: 61
7912 11:48:18.594351 [Byte1]: 61
7913 11:48:18.598687
7914 11:48:18.599170 Set Vref, RX VrefLevel [Byte0]: 62
7915 11:48:18.601977 [Byte1]: 62
7916 11:48:18.606176
7917 11:48:18.606589 Set Vref, RX VrefLevel [Byte0]: 63
7918 11:48:18.609869 [Byte1]: 63
7919 11:48:18.614034
7920 11:48:18.614540 Set Vref, RX VrefLevel [Byte0]: 64
7921 11:48:18.617656 [Byte1]: 64
7922 11:48:18.621805
7923 11:48:18.622311 Set Vref, RX VrefLevel [Byte0]: 65
7924 11:48:18.625250 [Byte1]: 65
7925 11:48:18.629377
7926 11:48:18.629901 Set Vref, RX VrefLevel [Byte0]: 66
7927 11:48:18.632969 [Byte1]: 66
7928 11:48:18.637221
7929 11:48:18.637766 Set Vref, RX VrefLevel [Byte0]: 67
7930 11:48:18.640396 [Byte1]: 67
7931 11:48:18.644196
7932 11:48:18.644751 Set Vref, RX VrefLevel [Byte0]: 68
7933 11:48:18.648121 [Byte1]: 68
7934 11:48:18.651707
7935 11:48:18.652127 Set Vref, RX VrefLevel [Byte0]: 69
7936 11:48:18.655418 [Byte1]: 69
7937 11:48:18.659376
7938 11:48:18.659788 Set Vref, RX VrefLevel [Byte0]: 70
7939 11:48:18.662583 [Byte1]: 70
7940 11:48:18.667306
7941 11:48:18.667744 Set Vref, RX VrefLevel [Byte0]: 71
7942 11:48:18.670238 [Byte1]: 71
7943 11:48:18.674804
7944 11:48:18.675285 Set Vref, RX VrefLevel [Byte0]: 72
7945 11:48:18.678312 [Byte1]: 72
7946 11:48:18.682598
7947 11:48:18.683141 Set Vref, RX VrefLevel [Byte0]: 73
7948 11:48:18.685460 [Byte1]: 73
7949 11:48:18.689999
7950 11:48:18.690448 Set Vref, RX VrefLevel [Byte0]: 74
7951 11:48:18.693590 [Byte1]: 74
7952 11:48:18.697576
7953 11:48:18.698147 Set Vref, RX VrefLevel [Byte0]: 75
7954 11:48:18.701123 [Byte1]: 75
7955 11:48:18.705322
7956 11:48:18.705759 Set Vref, RX VrefLevel [Byte0]: 76
7957 11:48:18.709060 [Byte1]: 76
7958 11:48:18.712863
7959 11:48:18.713277 Set Vref, RX VrefLevel [Byte0]: 77
7960 11:48:18.715922 [Byte1]: 77
7961 11:48:18.720340
7962 11:48:18.720799 Final RX Vref Byte 0 = 57 to rank0
7963 11:48:18.724417 Final RX Vref Byte 1 = 61 to rank0
7964 11:48:18.727388 Final RX Vref Byte 0 = 57 to rank1
7965 11:48:18.730531 Final RX Vref Byte 1 = 61 to rank1==
7966 11:48:18.733543 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 11:48:18.740726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 11:48:18.741160 ==
7969 11:48:18.741664 DQS Delay:
7970 11:48:18.742021 DQS0 = 0, DQS1 = 0
7971 11:48:18.744358 DQM Delay:
7972 11:48:18.744799 DQM0 = 129, DQM1 = 121
7973 11:48:18.746916 DQ Delay:
7974 11:48:18.750484 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7975 11:48:18.753896 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7976 11:48:18.757140 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7977 11:48:18.760443 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =132
7978 11:48:18.761006
7979 11:48:18.761360
7980 11:48:18.761724
7981 11:48:18.763656 [DramC_TX_OE_Calibration] TA2
7982 11:48:18.767348 Original DQ_B0 (3 6) =30, OEN = 27
7983 11:48:18.770700 Original DQ_B1 (3 6) =30, OEN = 27
7984 11:48:18.773712 24, 0x0, End_B0=24 End_B1=24
7985 11:48:18.774138 25, 0x0, End_B0=25 End_B1=25
7986 11:48:18.777224 26, 0x0, End_B0=26 End_B1=26
7987 11:48:18.781074 27, 0x0, End_B0=27 End_B1=27
7988 11:48:18.784043 28, 0x0, End_B0=28 End_B1=28
7989 11:48:18.784468 29, 0x0, End_B0=29 End_B1=29
7990 11:48:18.787149 30, 0x0, End_B0=30 End_B1=30
7991 11:48:18.791309 31, 0x4141, End_B0=30 End_B1=30
7992 11:48:18.793966 Byte0 end_step=30 best_step=27
7993 11:48:18.797129 Byte1 end_step=30 best_step=27
7994 11:48:18.800484 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 11:48:18.800907 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 11:48:18.801239
7997 11:48:18.801547
7998 11:48:18.810955 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7999 11:48:18.814236 CH0 RK0: MR19=303, MR18=1408
8000 11:48:18.817249 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8001 11:48:18.820561
8002 11:48:18.823786 ----->DramcWriteLeveling(PI) begin...
8003 11:48:18.824222 ==
8004 11:48:18.827330 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 11:48:18.830784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 11:48:18.831343 ==
8007 11:48:18.834084 Write leveling (Byte 0): 33 => 33
8008 11:48:18.837242 Write leveling (Byte 1): 27 => 27
8009 11:48:18.841007 DramcWriteLeveling(PI) end<-----
8010 11:48:18.841424
8011 11:48:18.841771 ==
8012 11:48:18.844659 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 11:48:18.847389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 11:48:18.847822 ==
8015 11:48:18.851039 [Gating] SW mode calibration
8016 11:48:18.857694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 11:48:18.864086 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 11:48:18.867420 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 11:48:18.870427 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 11:48:18.873744 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8021 11:48:18.880719 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8022 11:48:18.883786 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8023 11:48:18.887236 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8024 11:48:18.893944 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 11:48:18.897297 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 11:48:18.900342 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 11:48:18.907687 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 11:48:18.910598 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8029 11:48:18.913855 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8030 11:48:18.920343 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8031 11:48:18.923901 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8032 11:48:18.927814 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8033 11:48:18.934500 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 11:48:18.937715 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 11:48:18.940511 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 11:48:18.947741 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8037 11:48:18.950626 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8038 11:48:18.954226 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8039 11:48:18.957662 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8040 11:48:18.964340 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 11:48:18.967620 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 11:48:18.970964 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 11:48:18.977469 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 11:48:18.980725 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 11:48:18.984534 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 11:48:18.990718 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 11:48:18.993797 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 11:48:18.996947 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 11:48:19.003740 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:48:19.007048 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:48:19.010420 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:48:19.017003 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:48:19.020346 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 11:48:19.023879 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 11:48:19.030385 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 11:48:19.033653 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 11:48:19.037120 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 11:48:19.043976 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 11:48:19.047241 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8060 11:48:19.050401 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 11:48:19.057501 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 11:48:19.060304 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 11:48:19.063543 Total UI for P1: 0, mck2ui 16
8064 11:48:19.066999 best dqsien dly found for B0: ( 1, 9, 8)
8065 11:48:19.070395 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 11:48:19.073680 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 11:48:19.076849 Total UI for P1: 0, mck2ui 16
8068 11:48:19.080232 best dqsien dly found for B1: ( 1, 9, 20)
8069 11:48:19.083721 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8070 11:48:19.090089 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8071 11:48:19.090186
8072 11:48:19.093668 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8073 11:48:19.096887 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8074 11:48:19.100410 [Gating] SW calibration Done
8075 11:48:19.100484 ==
8076 11:48:19.103700 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 11:48:19.106968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 11:48:19.107076 ==
8079 11:48:19.107169 RX Vref Scan: 0
8080 11:48:19.110307
8081 11:48:19.110421 RX Vref 0 -> 0, step: 1
8082 11:48:19.110519
8083 11:48:19.113643 RX Delay 0 -> 252, step: 8
8084 11:48:19.116984 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8085 11:48:19.120719 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8086 11:48:19.127142 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8087 11:48:19.130595 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8088 11:48:19.134423 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8089 11:48:19.137463 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8090 11:48:19.141093 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8091 11:48:19.144705 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8092 11:48:19.151383 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8093 11:48:19.154142 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8094 11:48:19.157185 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8095 11:48:19.160765 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8096 11:48:19.163991 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8097 11:48:19.171056 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8098 11:48:19.174034 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8099 11:48:19.177704 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8100 11:48:19.178088 ==
8101 11:48:19.180965 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 11:48:19.184165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 11:48:19.184578 ==
8104 11:48:19.187475 DQS Delay:
8105 11:48:19.187884 DQS0 = 0, DQS1 = 0
8106 11:48:19.191408 DQM Delay:
8107 11:48:19.191817 DQM0 = 131, DQM1 = 124
8108 11:48:19.194498 DQ Delay:
8109 11:48:19.198104 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8110 11:48:19.201175 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8111 11:48:19.204242 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8112 11:48:19.207607 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8113 11:48:19.208017
8114 11:48:19.208338
8115 11:48:19.208640 ==
8116 11:48:19.210842 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 11:48:19.214445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 11:48:19.215060 ==
8119 11:48:19.215606
8120 11:48:19.216126
8121 11:48:19.217422 TX Vref Scan disable
8122 11:48:19.221000 == TX Byte 0 ==
8123 11:48:19.224544 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8124 11:48:19.227715 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8125 11:48:19.231411 == TX Byte 1 ==
8126 11:48:19.234261 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8127 11:48:19.237642 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8128 11:48:19.238052 ==
8129 11:48:19.241831 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 11:48:19.244496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 11:48:19.244913 ==
8132 11:48:19.259279
8133 11:48:19.262781 TX Vref early break, caculate TX vref
8134 11:48:19.265985 TX Vref=16, minBit 3, minWin=22, winSum=367
8135 11:48:19.269477 TX Vref=18, minBit 3, minWin=22, winSum=375
8136 11:48:19.272578 TX Vref=20, minBit 0, minWin=23, winSum=388
8137 11:48:19.276497 TX Vref=22, minBit 9, minWin=23, winSum=395
8138 11:48:19.279659 TX Vref=24, minBit 0, minWin=24, winSum=399
8139 11:48:19.286342 TX Vref=26, minBit 0, minWin=25, winSum=415
8140 11:48:19.289776 TX Vref=28, minBit 2, minWin=25, winSum=419
8141 11:48:19.293332 TX Vref=30, minBit 0, minWin=24, winSum=418
8142 11:48:19.296394 TX Vref=32, minBit 0, minWin=24, winSum=408
8143 11:48:19.299715 TX Vref=34, minBit 0, minWin=24, winSum=396
8144 11:48:19.306892 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 28
8145 11:48:19.307442
8146 11:48:19.310005 Final TX Range 0 Vref 28
8147 11:48:19.310457
8148 11:48:19.310816 ==
8149 11:48:19.313229 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 11:48:19.316175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 11:48:19.316643 ==
8152 11:48:19.316977
8153 11:48:19.317278
8154 11:48:19.319738 TX Vref Scan disable
8155 11:48:19.323293 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8156 11:48:19.326362 == TX Byte 0 ==
8157 11:48:19.329673 u2DelayCellOfst[0]=14 cells (4 PI)
8158 11:48:19.332753 u2DelayCellOfst[1]=17 cells (5 PI)
8159 11:48:19.336288 u2DelayCellOfst[2]=10 cells (3 PI)
8160 11:48:19.339809 u2DelayCellOfst[3]=10 cells (3 PI)
8161 11:48:19.343654 u2DelayCellOfst[4]=10 cells (3 PI)
8162 11:48:19.344067 u2DelayCellOfst[5]=0 cells (0 PI)
8163 11:48:19.346553 u2DelayCellOfst[6]=17 cells (5 PI)
8164 11:48:19.350309 u2DelayCellOfst[7]=17 cells (5 PI)
8165 11:48:19.356494 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8166 11:48:19.360010 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8167 11:48:19.360513 == TX Byte 1 ==
8168 11:48:19.363096 u2DelayCellOfst[8]=0 cells (0 PI)
8169 11:48:19.366345 u2DelayCellOfst[9]=0 cells (0 PI)
8170 11:48:19.369646 u2DelayCellOfst[10]=7 cells (2 PI)
8171 11:48:19.373112 u2DelayCellOfst[11]=0 cells (0 PI)
8172 11:48:19.376774 u2DelayCellOfst[12]=10 cells (3 PI)
8173 11:48:19.379702 u2DelayCellOfst[13]=10 cells (3 PI)
8174 11:48:19.383371 u2DelayCellOfst[14]=14 cells (4 PI)
8175 11:48:19.387027 u2DelayCellOfst[15]=10 cells (3 PI)
8176 11:48:19.389921 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8177 11:48:19.393036 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8178 11:48:19.396009 DramC Write-DBI on
8179 11:48:19.396117 ==
8180 11:48:19.399975 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 11:48:19.402568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 11:48:19.402661 ==
8183 11:48:19.402727
8184 11:48:19.402786
8185 11:48:19.405916 TX Vref Scan disable
8186 11:48:19.409575 == TX Byte 0 ==
8187 11:48:19.412965 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8188 11:48:19.413055 == TX Byte 1 ==
8189 11:48:19.419627 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8190 11:48:19.419702 DramC Write-DBI off
8191 11:48:19.419775
8192 11:48:19.422838 [DATLAT]
8193 11:48:19.422941 Freq=1600, CH0 RK1
8194 11:48:19.423037
8195 11:48:19.426286 DATLAT Default: 0xf
8196 11:48:19.426383 0, 0xFFFF, sum = 0
8197 11:48:19.429345 1, 0xFFFF, sum = 0
8198 11:48:19.429421 2, 0xFFFF, sum = 0
8199 11:48:19.433245 3, 0xFFFF, sum = 0
8200 11:48:19.433346 4, 0xFFFF, sum = 0
8201 11:48:19.436391 5, 0xFFFF, sum = 0
8202 11:48:19.436471 6, 0xFFFF, sum = 0
8203 11:48:19.440032 7, 0xFFFF, sum = 0
8204 11:48:19.440449 8, 0xFFFF, sum = 0
8205 11:48:19.443121 9, 0xFFFF, sum = 0
8206 11:48:19.443537 10, 0xFFFF, sum = 0
8207 11:48:19.446950 11, 0xFFFF, sum = 0
8208 11:48:19.447367 12, 0xFFFF, sum = 0
8209 11:48:19.450743 13, 0xFFFF, sum = 0
8210 11:48:19.451312 14, 0x0, sum = 1
8211 11:48:19.453814 15, 0x0, sum = 2
8212 11:48:19.454230 16, 0x0, sum = 3
8213 11:48:19.457003 17, 0x0, sum = 4
8214 11:48:19.457424 best_step = 15
8215 11:48:19.457752
8216 11:48:19.458054 ==
8217 11:48:19.460382 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 11:48:19.466959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 11:48:19.467597 ==
8220 11:48:19.468086 RX Vref Scan: 0
8221 11:48:19.468543
8222 11:48:19.470382 RX Vref 0 -> 0, step: 1
8223 11:48:19.470897
8224 11:48:19.473452 RX Delay 11 -> 252, step: 4
8225 11:48:19.476600 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8226 11:48:19.480156 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8227 11:48:19.483801 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8228 11:48:19.489889 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8229 11:48:19.493423 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8230 11:48:19.496881 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8231 11:48:19.500135 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8232 11:48:19.503328 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8233 11:48:19.510136 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8234 11:48:19.513649 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8235 11:48:19.517404 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8236 11:48:19.520350 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8237 11:48:19.523843 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8238 11:48:19.530814 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8239 11:48:19.533804 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8240 11:48:19.537528 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8241 11:48:19.537988 ==
8242 11:48:19.540286 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 11:48:19.544056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 11:48:19.544554 ==
8245 11:48:19.546904 DQS Delay:
8246 11:48:19.547361 DQS0 = 0, DQS1 = 0
8247 11:48:19.547687 DQM Delay:
8248 11:48:19.550511 DQM0 = 126, DQM1 = 122
8249 11:48:19.551128 DQ Delay:
8250 11:48:19.553754 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8251 11:48:19.557149 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8252 11:48:19.563775 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8253 11:48:19.567100 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8254 11:48:19.567518
8255 11:48:19.568098
8256 11:48:19.568465
8257 11:48:19.570184 [DramC_TX_OE_Calibration] TA2
8258 11:48:19.573608 Original DQ_B0 (3 6) =30, OEN = 27
8259 11:48:19.576865 Original DQ_B1 (3 6) =30, OEN = 27
8260 11:48:19.577524 24, 0x0, End_B0=24 End_B1=24
8261 11:48:19.580325 25, 0x0, End_B0=25 End_B1=25
8262 11:48:19.583890 26, 0x0, End_B0=26 End_B1=26
8263 11:48:19.587459 27, 0x0, End_B0=27 End_B1=27
8264 11:48:19.587926 28, 0x0, End_B0=28 End_B1=28
8265 11:48:19.590632 29, 0x0, End_B0=29 End_B1=29
8266 11:48:19.593644 30, 0x0, End_B0=30 End_B1=30
8267 11:48:19.596768 31, 0x5151, End_B0=30 End_B1=30
8268 11:48:19.600328 Byte0 end_step=30 best_step=27
8269 11:48:19.603755 Byte1 end_step=30 best_step=27
8270 11:48:19.604208 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 11:48:19.607024 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 11:48:19.607462
8273 11:48:19.607820
8274 11:48:19.616940 [DQSOSCAuto] RK1, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8275 11:48:19.617452 CH0 RK1: MR19=303, MR18=190E
8276 11:48:19.623924 CH0_RK1: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8277 11:48:19.626944 [RxdqsGatingPostProcess] freq 1600
8278 11:48:19.633698 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 11:48:19.637613 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 11:48:19.640812 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 11:48:19.643775 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 11:48:19.646951 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 11:48:19.647367 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 11:48:19.650691 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 11:48:19.653961 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 11:48:19.657396 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 11:48:19.660422 Pre-setting of DQS Precalculation
8288 11:48:19.667440 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 11:48:19.668009 ==
8290 11:48:19.670564 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 11:48:19.674136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 11:48:19.674580 ==
8293 11:48:19.680482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 11:48:19.683673 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 11:48:19.687158 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 11:48:19.693992 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 11:48:19.701877 [CA 0] Center 42 (13~71) winsize 59
8298 11:48:19.706135 [CA 1] Center 42 (13~71) winsize 59
8299 11:48:19.708733 [CA 2] Center 37 (8~66) winsize 59
8300 11:48:19.712500 [CA 3] Center 36 (7~65) winsize 59
8301 11:48:19.715741 [CA 4] Center 37 (7~67) winsize 61
8302 11:48:19.718578 [CA 5] Center 36 (7~66) winsize 60
8303 11:48:19.719013
8304 11:48:19.721953 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 11:48:19.722368
8306 11:48:19.725485 [CATrainingPosCal] consider 1 rank data
8307 11:48:19.728800 u2DelayCellTimex100 = 275/100 ps
8308 11:48:19.732314 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8309 11:48:19.738992 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8310 11:48:19.742105 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8311 11:48:19.745549 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8312 11:48:19.748619 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8313 11:48:19.752105 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 11:48:19.752560
8315 11:48:19.755761 CA PerBit enable=1, Macro0, CA PI delay=36
8316 11:48:19.756195
8317 11:48:19.758941 [CBTSetCACLKResult] CA Dly = 36
8318 11:48:19.759380 CS Dly: 9 (0~40)
8319 11:48:19.765425 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 11:48:19.768629 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 11:48:19.769122 ==
8322 11:48:19.771939 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 11:48:19.775411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 11:48:19.775854 ==
8325 11:48:19.782040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 11:48:19.785452 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 11:48:19.788830 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 11:48:19.795294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 11:48:19.805215 [CA 0] Center 43 (15~72) winsize 58
8330 11:48:19.809142 [CA 1] Center 43 (14~72) winsize 59
8331 11:48:19.811963 [CA 2] Center 38 (9~67) winsize 59
8332 11:48:19.815159 [CA 3] Center 37 (8~67) winsize 60
8333 11:48:19.818670 [CA 4] Center 38 (9~68) winsize 60
8334 11:48:19.822504 [CA 5] Center 37 (8~66) winsize 59
8335 11:48:19.822968
8336 11:48:19.825302 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8337 11:48:19.825726
8338 11:48:19.828711 [CATrainingPosCal] consider 2 rank data
8339 11:48:19.831912 u2DelayCellTimex100 = 275/100 ps
8340 11:48:19.835413 CA0 delay=43 (15~71),Diff = 7 PI (24 cell)
8341 11:48:19.841934 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8342 11:48:19.845199 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8343 11:48:19.848617 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8344 11:48:19.851540 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8345 11:48:19.854818 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 11:48:19.854935
8347 11:48:19.857874 CA PerBit enable=1, Macro0, CA PI delay=36
8348 11:48:19.857944
8349 11:48:19.861463 [CBTSetCACLKResult] CA Dly = 36
8350 11:48:19.864868 CS Dly: 11 (0~44)
8351 11:48:19.868283 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 11:48:19.871429 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 11:48:19.871504
8354 11:48:19.874537 ----->DramcWriteLeveling(PI) begin...
8355 11:48:19.874609 ==
8356 11:48:19.878730 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 11:48:19.881798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 11:48:19.885368 ==
8359 11:48:19.885505 Write leveling (Byte 0): 25 => 25
8360 11:48:19.888120 Write leveling (Byte 1): 28 => 28
8361 11:48:19.892101 DramcWriteLeveling(PI) end<-----
8362 11:48:19.892512
8363 11:48:19.892940 ==
8364 11:48:19.895459 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 11:48:19.901937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 11:48:19.902437 ==
8367 11:48:19.902770 [Gating] SW mode calibration
8368 11:48:19.911857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 11:48:19.914882 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 11:48:19.918103 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 11:48:19.925282 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 11:48:19.928692 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 11:48:19.931776 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:48:19.938829 1 4 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8375 11:48:19.941710 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8376 11:48:19.945016 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 11:48:19.951949 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 11:48:19.955151 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 11:48:19.958442 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 11:48:19.965195 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 11:48:19.968455 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8382 11:48:19.971723 1 5 16 | B1->B0 | 2828 2d2d | 0 0 | (1 0) (1 0)
8383 11:48:19.979026 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 11:48:19.982200 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 11:48:19.985595 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 11:48:19.992087 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 11:48:19.995205 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 11:48:19.999037 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 11:48:20.001915 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 11:48:20.008120 1 6 16 | B1->B0 | 3f3f 3737 | 0 0 | (0 0) (0 0)
8391 11:48:20.011947 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 11:48:20.015178 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 11:48:20.021520 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 11:48:20.024826 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 11:48:20.027987 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 11:48:20.035288 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 11:48:20.038460 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 11:48:20.041994 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 11:48:20.048445 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:48:20.051972 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:48:20.055012 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:48:20.062047 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:48:20.065193 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:48:20.068568 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:48:20.072196 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 11:48:20.078629 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 11:48:20.082237 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:48:20.086701 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:48:20.092291 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 11:48:20.095614 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 11:48:20.099134 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 11:48:20.105298 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 11:48:20.108696 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 11:48:20.112188 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 11:48:20.119220 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 11:48:20.119607 Total UI for P1: 0, mck2ui 16
8417 11:48:20.125466 best dqsien dly found for B0: ( 1, 9, 14)
8418 11:48:20.125861 Total UI for P1: 0, mck2ui 16
8419 11:48:20.128989 best dqsien dly found for B1: ( 1, 9, 14)
8420 11:48:20.135680 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8421 11:48:20.138956 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8422 11:48:20.139327
8423 11:48:20.141963 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8424 11:48:20.145687 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8425 11:48:20.148946 [Gating] SW calibration Done
8426 11:48:20.149311 ==
8427 11:48:20.152590 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 11:48:20.155820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 11:48:20.156237 ==
8430 11:48:20.159182 RX Vref Scan: 0
8431 11:48:20.159595
8432 11:48:20.159921 RX Vref 0 -> 0, step: 1
8433 11:48:20.160228
8434 11:48:20.162228 RX Delay 0 -> 252, step: 8
8435 11:48:20.165993 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8436 11:48:20.172301 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8437 11:48:20.175505 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8438 11:48:20.178754 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8439 11:48:20.182430 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8440 11:48:20.185856 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8441 11:48:20.188787 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8442 11:48:20.195772 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8443 11:48:20.199192 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8444 11:48:20.202183 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8445 11:48:20.205402 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8446 11:48:20.208896 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8447 11:48:20.215844 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8448 11:48:20.218765 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8449 11:48:20.222313 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8450 11:48:20.225341 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8451 11:48:20.225707 ==
8452 11:48:20.228584 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:48:20.235668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:48:20.235751 ==
8455 11:48:20.235815 DQS Delay:
8456 11:48:20.238850 DQS0 = 0, DQS1 = 0
8457 11:48:20.238942 DQM Delay:
8458 11:48:20.239007 DQM0 = 135, DQM1 = 128
8459 11:48:20.242173 DQ Delay:
8460 11:48:20.245313 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8461 11:48:20.248589 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8462 11:48:20.252015 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8463 11:48:20.255167 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8464 11:48:20.255316
8465 11:48:20.255404
8466 11:48:20.255483 ==
8467 11:48:20.258311 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 11:48:20.262375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 11:48:20.265586 ==
8470 11:48:20.265779
8471 11:48:20.265878
8472 11:48:20.265970 TX Vref Scan disable
8473 11:48:20.268743 == TX Byte 0 ==
8474 11:48:20.271846 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8475 11:48:20.275696 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8476 11:48:20.278325 == TX Byte 1 ==
8477 11:48:20.282358 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8478 11:48:20.285187 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8479 11:48:20.288085 ==
8480 11:48:20.288167 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 11:48:20.294784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 11:48:20.294889 ==
8483 11:48:20.308035
8484 11:48:20.311404 TX Vref early break, caculate TX vref
8485 11:48:20.314826 TX Vref=16, minBit 8, minWin=21, winSum=360
8486 11:48:20.318194 TX Vref=18, minBit 8, minWin=21, winSum=373
8487 11:48:20.321920 TX Vref=20, minBit 8, minWin=21, winSum=383
8488 11:48:20.325219 TX Vref=22, minBit 8, minWin=22, winSum=391
8489 11:48:20.329482 TX Vref=24, minBit 5, minWin=24, winSum=402
8490 11:48:20.335204 TX Vref=26, minBit 5, minWin=24, winSum=410
8491 11:48:20.338631 TX Vref=28, minBit 8, minWin=25, winSum=417
8492 11:48:20.341802 TX Vref=30, minBit 1, minWin=25, winSum=416
8493 11:48:20.345641 TX Vref=32, minBit 15, minWin=24, winSum=411
8494 11:48:20.348451 TX Vref=34, minBit 11, minWin=23, winSum=398
8495 11:48:20.351843 TX Vref=36, minBit 8, minWin=23, winSum=389
8496 11:48:20.358367 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8497 11:48:20.358793
8498 11:48:20.361791 Final TX Range 0 Vref 28
8499 11:48:20.362210
8500 11:48:20.362540 ==
8501 11:48:20.365291 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 11:48:20.368949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 11:48:20.369372 ==
8504 11:48:20.369704
8505 11:48:20.370014
8506 11:48:20.371792 TX Vref Scan disable
8507 11:48:20.378426 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8508 11:48:20.378848 == TX Byte 0 ==
8509 11:48:20.381657 u2DelayCellOfst[0]=14 cells (4 PI)
8510 11:48:20.384889 u2DelayCellOfst[1]=10 cells (3 PI)
8511 11:48:20.388322 u2DelayCellOfst[2]=0 cells (0 PI)
8512 11:48:20.391534 u2DelayCellOfst[3]=7 cells (2 PI)
8513 11:48:20.394773 u2DelayCellOfst[4]=7 cells (2 PI)
8514 11:48:20.397813 u2DelayCellOfst[5]=21 cells (6 PI)
8515 11:48:20.401149 u2DelayCellOfst[6]=17 cells (5 PI)
8516 11:48:20.405167 u2DelayCellOfst[7]=7 cells (2 PI)
8517 11:48:20.408617 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 11:48:20.412365 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8519 11:48:20.414776 == TX Byte 1 ==
8520 11:48:20.415320 u2DelayCellOfst[8]=0 cells (0 PI)
8521 11:48:20.418736 u2DelayCellOfst[9]=7 cells (2 PI)
8522 11:48:20.422188 u2DelayCellOfst[10]=10 cells (3 PI)
8523 11:48:20.424976 u2DelayCellOfst[11]=7 cells (2 PI)
8524 11:48:20.428791 u2DelayCellOfst[12]=14 cells (4 PI)
8525 11:48:20.432267 u2DelayCellOfst[13]=17 cells (5 PI)
8526 11:48:20.435832 u2DelayCellOfst[14]=17 cells (5 PI)
8527 11:48:20.439022 u2DelayCellOfst[15]=17 cells (5 PI)
8528 11:48:20.441906 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8529 11:48:20.448389 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 11:48:20.448851 DramC Write-DBI on
8531 11:48:20.449217 ==
8532 11:48:20.452019 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 11:48:20.454658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 11:48:20.454739 ==
8535 11:48:20.458504
8536 11:48:20.458584
8537 11:48:20.458648 TX Vref Scan disable
8538 11:48:20.461663 == TX Byte 0 ==
8539 11:48:20.464850 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8540 11:48:20.468552 == TX Byte 1 ==
8541 11:48:20.471813 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8542 11:48:20.471896 DramC Write-DBI off
8543 11:48:20.471961
8544 11:48:20.474815 [DATLAT]
8545 11:48:20.474935 Freq=1600, CH1 RK0
8546 11:48:20.475001
8547 11:48:20.478582 DATLAT Default: 0xf
8548 11:48:20.478663 0, 0xFFFF, sum = 0
8549 11:48:20.481520 1, 0xFFFF, sum = 0
8550 11:48:20.481602 2, 0xFFFF, sum = 0
8551 11:48:20.485271 3, 0xFFFF, sum = 0
8552 11:48:20.485353 4, 0xFFFF, sum = 0
8553 11:48:20.488864 5, 0xFFFF, sum = 0
8554 11:48:20.488947 6, 0xFFFF, sum = 0
8555 11:48:20.491819 7, 0xFFFF, sum = 0
8556 11:48:20.491901 8, 0xFFFF, sum = 0
8557 11:48:20.494896 9, 0xFFFF, sum = 0
8558 11:48:20.498898 10, 0xFFFF, sum = 0
8559 11:48:20.499060 11, 0xFFFF, sum = 0
8560 11:48:20.502187 12, 0xFFFF, sum = 0
8561 11:48:20.502315 13, 0xFFFF, sum = 0
8562 11:48:20.505464 14, 0x0, sum = 1
8563 11:48:20.505637 15, 0x0, sum = 2
8564 11:48:20.508567 16, 0x0, sum = 3
8565 11:48:20.508708 17, 0x0, sum = 4
8566 11:48:20.508800 best_step = 15
8567 11:48:20.508881
8568 11:48:20.512663 ==
8569 11:48:20.512853 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 11:48:20.518735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 11:48:20.518877 ==
8572 11:48:20.518978 RX Vref Scan: 1
8573 11:48:20.519069
8574 11:48:20.522251 Set Vref Range= 24 -> 127
8575 11:48:20.522372
8576 11:48:20.525418 RX Vref 24 -> 127, step: 1
8577 11:48:20.525500
8578 11:48:20.528383 RX Delay 19 -> 252, step: 4
8579 11:48:20.528464
8580 11:48:20.532552 Set Vref, RX VrefLevel [Byte0]: 24
8581 11:48:20.535099 [Byte1]: 24
8582 11:48:20.535181
8583 11:48:20.538386 Set Vref, RX VrefLevel [Byte0]: 25
8584 11:48:20.541987 [Byte1]: 25
8585 11:48:20.542069
8586 11:48:20.545333 Set Vref, RX VrefLevel [Byte0]: 26
8587 11:48:20.548279 [Byte1]: 26
8588 11:48:20.548360
8589 11:48:20.552144 Set Vref, RX VrefLevel [Byte0]: 27
8590 11:48:20.555155 [Byte1]: 27
8591 11:48:20.559060
8592 11:48:20.559142 Set Vref, RX VrefLevel [Byte0]: 28
8593 11:48:20.562390 [Byte1]: 28
8594 11:48:20.566718
8595 11:48:20.566799 Set Vref, RX VrefLevel [Byte0]: 29
8596 11:48:20.570232 [Byte1]: 29
8597 11:48:20.574670
8598 11:48:20.574850 Set Vref, RX VrefLevel [Byte0]: 30
8599 11:48:20.577933 [Byte1]: 30
8600 11:48:20.581825
8601 11:48:20.581969 Set Vref, RX VrefLevel [Byte0]: 31
8602 11:48:20.585213 [Byte1]: 31
8603 11:48:20.589790
8604 11:48:20.589989 Set Vref, RX VrefLevel [Byte0]: 32
8605 11:48:20.593245 [Byte1]: 32
8606 11:48:20.597602
8607 11:48:20.597837 Set Vref, RX VrefLevel [Byte0]: 33
8608 11:48:20.600731 [Byte1]: 33
8609 11:48:20.604939
8610 11:48:20.605189 Set Vref, RX VrefLevel [Byte0]: 34
8611 11:48:20.608549 [Byte1]: 34
8612 11:48:20.612585
8613 11:48:20.612894 Set Vref, RX VrefLevel [Byte0]: 35
8614 11:48:20.615782 [Byte1]: 35
8615 11:48:20.620468
8616 11:48:20.620867 Set Vref, RX VrefLevel [Byte0]: 36
8617 11:48:20.623740 [Byte1]: 36
8618 11:48:20.627611
8619 11:48:20.628056 Set Vref, RX VrefLevel [Byte0]: 37
8620 11:48:20.630955 [Byte1]: 37
8621 11:48:20.634661
8622 11:48:20.634743 Set Vref, RX VrefLevel [Byte0]: 38
8623 11:48:20.638172 [Byte1]: 38
8624 11:48:20.642402
8625 11:48:20.642484 Set Vref, RX VrefLevel [Byte0]: 39
8626 11:48:20.645649 [Byte1]: 39
8627 11:48:20.649955
8628 11:48:20.650035 Set Vref, RX VrefLevel [Byte0]: 40
8629 11:48:20.653484 [Byte1]: 40
8630 11:48:20.657363
8631 11:48:20.657445 Set Vref, RX VrefLevel [Byte0]: 41
8632 11:48:20.661163 [Byte1]: 41
8633 11:48:20.665772
8634 11:48:20.665853 Set Vref, RX VrefLevel [Byte0]: 42
8635 11:48:20.668472 [Byte1]: 42
8636 11:48:20.672860
8637 11:48:20.672942 Set Vref, RX VrefLevel [Byte0]: 43
8638 11:48:20.676341 [Byte1]: 43
8639 11:48:20.680667
8640 11:48:20.680748 Set Vref, RX VrefLevel [Byte0]: 44
8641 11:48:20.684126 [Byte1]: 44
8642 11:48:20.687992
8643 11:48:20.688079 Set Vref, RX VrefLevel [Byte0]: 45
8644 11:48:20.691385 [Byte1]: 45
8645 11:48:20.695961
8646 11:48:20.696053 Set Vref, RX VrefLevel [Byte0]: 46
8647 11:48:20.698643 [Byte1]: 46
8648 11:48:20.702888
8649 11:48:20.702999 Set Vref, RX VrefLevel [Byte0]: 47
8650 11:48:20.706297 [Byte1]: 47
8651 11:48:20.710684
8652 11:48:20.710805 Set Vref, RX VrefLevel [Byte0]: 48
8653 11:48:20.713804 [Byte1]: 48
8654 11:48:20.718353
8655 11:48:20.718503 Set Vref, RX VrefLevel [Byte0]: 49
8656 11:48:20.721774 [Byte1]: 49
8657 11:48:20.726261
8658 11:48:20.726433 Set Vref, RX VrefLevel [Byte0]: 50
8659 11:48:20.729515 [Byte1]: 50
8660 11:48:20.733880
8661 11:48:20.734207 Set Vref, RX VrefLevel [Byte0]: 51
8662 11:48:20.736985 [Byte1]: 51
8663 11:48:20.741369
8664 11:48:20.741666 Set Vref, RX VrefLevel [Byte0]: 52
8665 11:48:20.744653 [Byte1]: 52
8666 11:48:20.748641
8667 11:48:20.749072 Set Vref, RX VrefLevel [Byte0]: 53
8668 11:48:20.752089 [Byte1]: 53
8669 11:48:20.756060
8670 11:48:20.756141 Set Vref, RX VrefLevel [Byte0]: 54
8671 11:48:20.759465 [Byte1]: 54
8672 11:48:20.763703
8673 11:48:20.763784 Set Vref, RX VrefLevel [Byte0]: 55
8674 11:48:20.766787 [Byte1]: 55
8675 11:48:20.771184
8676 11:48:20.771265 Set Vref, RX VrefLevel [Byte0]: 56
8677 11:48:20.774803 [Byte1]: 56
8678 11:48:20.779219
8679 11:48:20.779652 Set Vref, RX VrefLevel [Byte0]: 57
8680 11:48:20.782686 [Byte1]: 57
8681 11:48:20.787115
8682 11:48:20.787534 Set Vref, RX VrefLevel [Byte0]: 58
8683 11:48:20.790683 [Byte1]: 58
8684 11:48:20.794642
8685 11:48:20.795234 Set Vref, RX VrefLevel [Byte0]: 59
8686 11:48:20.797800 [Byte1]: 59
8687 11:48:20.802143
8688 11:48:20.802655 Set Vref, RX VrefLevel [Byte0]: 60
8689 11:48:20.805683 [Byte1]: 60
8690 11:48:20.809540
8691 11:48:20.809962 Set Vref, RX VrefLevel [Byte0]: 61
8692 11:48:20.812557 [Byte1]: 61
8693 11:48:20.816765
8694 11:48:20.817181 Set Vref, RX VrefLevel [Byte0]: 62
8695 11:48:20.820034 [Byte1]: 62
8696 11:48:20.824127
8697 11:48:20.824208 Set Vref, RX VrefLevel [Byte0]: 63
8698 11:48:20.827261 [Byte1]: 63
8699 11:48:20.831556
8700 11:48:20.831637 Set Vref, RX VrefLevel [Byte0]: 64
8701 11:48:20.835165 [Byte1]: 64
8702 11:48:20.839646
8703 11:48:20.839726 Set Vref, RX VrefLevel [Byte0]: 65
8704 11:48:20.843131 [Byte1]: 65
8705 11:48:20.846708
8706 11:48:20.846787 Set Vref, RX VrefLevel [Byte0]: 66
8707 11:48:20.850357 [Byte1]: 66
8708 11:48:20.854564
8709 11:48:20.854643 Set Vref, RX VrefLevel [Byte0]: 67
8710 11:48:20.858020 [Byte1]: 67
8711 11:48:20.862272
8712 11:48:20.862352 Set Vref, RX VrefLevel [Byte0]: 68
8713 11:48:20.865308 [Byte1]: 68
8714 11:48:20.869652
8715 11:48:20.869732 Set Vref, RX VrefLevel [Byte0]: 69
8716 11:48:20.873039 [Byte1]: 69
8717 11:48:20.877203
8718 11:48:20.877283 Set Vref, RX VrefLevel [Byte0]: 70
8719 11:48:20.880705 [Byte1]: 70
8720 11:48:20.884546
8721 11:48:20.884625 Set Vref, RX VrefLevel [Byte0]: 71
8722 11:48:20.888028 [Byte1]: 71
8723 11:48:20.892745
8724 11:48:20.892825 Set Vref, RX VrefLevel [Byte0]: 72
8725 11:48:20.895919 [Byte1]: 72
8726 11:48:20.900187
8727 11:48:20.900266 Set Vref, RX VrefLevel [Byte0]: 73
8728 11:48:20.903740 [Byte1]: 73
8729 11:48:20.907642
8730 11:48:20.907721 Set Vref, RX VrefLevel [Byte0]: 74
8731 11:48:20.910797 [Byte1]: 74
8732 11:48:20.915515
8733 11:48:20.915596 Set Vref, RX VrefLevel [Byte0]: 75
8734 11:48:20.918513 [Byte1]: 75
8735 11:48:20.922770
8736 11:48:20.922881 Set Vref, RX VrefLevel [Byte0]: 76
8737 11:48:20.926122 [Byte1]: 76
8738 11:48:20.930200
8739 11:48:20.930280 Final RX Vref Byte 0 = 60 to rank0
8740 11:48:20.933879 Final RX Vref Byte 1 = 58 to rank0
8741 11:48:20.936764 Final RX Vref Byte 0 = 60 to rank1
8742 11:48:20.940533 Final RX Vref Byte 1 = 58 to rank1==
8743 11:48:20.943973 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 11:48:20.947153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 11:48:20.950207 ==
8746 11:48:20.950287 DQS Delay:
8747 11:48:20.950352 DQS0 = 0, DQS1 = 0
8748 11:48:20.953913 DQM Delay:
8749 11:48:20.953993 DQM0 = 131, DQM1 = 124
8750 11:48:20.957155 DQ Delay:
8751 11:48:20.960907 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8752 11:48:20.963676 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8753 11:48:20.966935 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =120
8754 11:48:20.970244 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8755 11:48:20.970325
8756 11:48:20.970388
8757 11:48:20.970447
8758 11:48:20.973555 [DramC_TX_OE_Calibration] TA2
8759 11:48:20.977240 Original DQ_B0 (3 6) =30, OEN = 27
8760 11:48:20.980822 Original DQ_B1 (3 6) =30, OEN = 27
8761 11:48:20.980904 24, 0x0, End_B0=24 End_B1=24
8762 11:48:20.983729 25, 0x0, End_B0=25 End_B1=25
8763 11:48:20.987011 26, 0x0, End_B0=26 End_B1=26
8764 11:48:20.990573 27, 0x0, End_B0=27 End_B1=27
8765 11:48:20.993594 28, 0x0, End_B0=28 End_B1=28
8766 11:48:20.993692 29, 0x0, End_B0=29 End_B1=29
8767 11:48:20.996953 30, 0x0, End_B0=30 End_B1=30
8768 11:48:21.000281 31, 0x4141, End_B0=30 End_B1=30
8769 11:48:21.003894 Byte0 end_step=30 best_step=27
8770 11:48:21.007362 Byte1 end_step=30 best_step=27
8771 11:48:21.010887 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 11:48:21.011016 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 11:48:21.011144
8774 11:48:21.011265
8775 11:48:21.020112 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8776 11:48:21.023683 CH1 RK0: MR19=303, MR18=1701
8777 11:48:21.030400 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8778 11:48:21.030610
8779 11:48:21.033896 ----->DramcWriteLeveling(PI) begin...
8780 11:48:21.034150 ==
8781 11:48:21.036946 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 11:48:21.040394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:48:21.040707 ==
8784 11:48:21.044000 Write leveling (Byte 0): 24 => 24
8785 11:48:21.047704 Write leveling (Byte 1): 26 => 26
8786 11:48:21.050831 DramcWriteLeveling(PI) end<-----
8787 11:48:21.051310
8788 11:48:21.051751 ==
8789 11:48:21.054377 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 11:48:21.057116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 11:48:21.057558 ==
8792 11:48:21.060781 [Gating] SW mode calibration
8793 11:48:21.067410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 11:48:21.074063 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 11:48:21.077288 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 11:48:21.080633 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 11:48:21.087417 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8798 11:48:21.090925 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
8799 11:48:21.093986 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 11:48:21.097560 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 11:48:21.104142 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 11:48:21.107432 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 11:48:21.110705 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 11:48:21.117817 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8805 11:48:21.121256 1 5 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
8806 11:48:21.124458 1 5 12 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8807 11:48:21.131086 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 11:48:21.134221 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 11:48:21.137654 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 11:48:21.144091 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 11:48:21.147410 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 11:48:21.150724 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 11:48:21.157873 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8814 11:48:21.160748 1 6 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
8815 11:48:21.164506 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 11:48:21.170906 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 11:48:21.174663 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 11:48:21.177938 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 11:48:21.181196 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 11:48:21.188033 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 11:48:21.191304 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8822 11:48:21.194687 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8823 11:48:21.201183 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:48:21.204464 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:48:21.208053 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:48:21.214632 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:48:21.218212 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:48:21.221206 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 11:48:21.227984 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 11:48:21.231311 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 11:48:21.234850 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 11:48:21.241260 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 11:48:21.244911 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 11:48:21.248370 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 11:48:21.251442 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 11:48:21.257830 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8837 11:48:21.261350 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8838 11:48:21.264563 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8839 11:48:21.268011 Total UI for P1: 0, mck2ui 16
8840 11:48:21.271154 best dqsien dly found for B0: ( 1, 9, 6)
8841 11:48:21.278062 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8842 11:48:21.281368 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:48:21.284454 Total UI for P1: 0, mck2ui 16
8844 11:48:21.288287 best dqsien dly found for B1: ( 1, 9, 14)
8845 11:48:21.291105 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8846 11:48:21.295304 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8847 11:48:21.295817
8848 11:48:21.298121 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8849 11:48:21.301580 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8850 11:48:21.304545 [Gating] SW calibration Done
8851 11:48:21.304998 ==
8852 11:48:21.308321 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 11:48:21.314261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 11:48:21.314753 ==
8855 11:48:21.315134 RX Vref Scan: 0
8856 11:48:21.315449
8857 11:48:21.317525 RX Vref 0 -> 0, step: 1
8858 11:48:21.317935
8859 11:48:21.321317 RX Delay 0 -> 252, step: 8
8860 11:48:21.324721 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8861 11:48:21.327805 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8862 11:48:21.331131 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8863 11:48:21.334471 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8864 11:48:21.337773 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8865 11:48:21.344579 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8866 11:48:21.348115 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8867 11:48:21.351470 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8868 11:48:21.354587 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8869 11:48:21.358462 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8870 11:48:21.364925 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8871 11:48:21.368377 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8872 11:48:21.371547 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8873 11:48:21.374603 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8874 11:48:21.378337 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8875 11:48:21.384879 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8876 11:48:21.385292 ==
8877 11:48:21.388125 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 11:48:21.391368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 11:48:21.391782 ==
8880 11:48:21.392107 DQS Delay:
8881 11:48:21.394618 DQS0 = 0, DQS1 = 0
8882 11:48:21.395153 DQM Delay:
8883 11:48:21.398016 DQM0 = 132, DQM1 = 128
8884 11:48:21.398426 DQ Delay:
8885 11:48:21.401537 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8886 11:48:21.404953 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8887 11:48:21.408318 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8888 11:48:21.411371 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8889 11:48:21.411786
8890 11:48:21.414511
8891 11:48:21.414959 ==
8892 11:48:21.418503 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 11:48:21.421624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 11:48:21.422041 ==
8895 11:48:21.422369
8896 11:48:21.422674
8897 11:48:21.425085 TX Vref Scan disable
8898 11:48:21.425495 == TX Byte 0 ==
8899 11:48:21.428032 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8900 11:48:21.435089 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 11:48:21.435655 == TX Byte 1 ==
8902 11:48:21.438260 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 11:48:21.444879 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 11:48:21.445293 ==
8905 11:48:21.447834 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 11:48:21.451171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 11:48:21.451655 ==
8908 11:48:21.465483
8909 11:48:21.468950 TX Vref early break, caculate TX vref
8910 11:48:21.471891 TX Vref=16, minBit 0, minWin=23, winSum=382
8911 11:48:21.475674 TX Vref=18, minBit 0, minWin=24, winSum=392
8912 11:48:21.478629 TX Vref=20, minBit 5, minWin=24, winSum=402
8913 11:48:21.481983 TX Vref=22, minBit 0, minWin=25, winSum=413
8914 11:48:21.485491 TX Vref=24, minBit 0, minWin=25, winSum=418
8915 11:48:21.492014 TX Vref=26, minBit 1, minWin=26, winSum=426
8916 11:48:21.495686 TX Vref=28, minBit 0, minWin=25, winSum=425
8917 11:48:21.498644 TX Vref=30, minBit 0, minWin=25, winSum=424
8918 11:48:21.502558 TX Vref=32, minBit 5, minWin=25, winSum=420
8919 11:48:21.505819 TX Vref=34, minBit 0, minWin=24, winSum=413
8920 11:48:21.509084 TX Vref=36, minBit 0, minWin=24, winSum=402
8921 11:48:21.515779 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 26
8922 11:48:21.516295
8923 11:48:21.519409 Final TX Range 0 Vref 26
8924 11:48:21.519950
8925 11:48:21.520320 ==
8926 11:48:21.521949 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 11:48:21.525475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 11:48:21.525886 ==
8929 11:48:21.526213
8930 11:48:21.526510
8931 11:48:21.528817 TX Vref Scan disable
8932 11:48:21.535729 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8933 11:48:21.536138 == TX Byte 0 ==
8934 11:48:21.539256 u2DelayCellOfst[0]=17 cells (5 PI)
8935 11:48:21.542161 u2DelayCellOfst[1]=10 cells (3 PI)
8936 11:48:21.546049 u2DelayCellOfst[2]=0 cells (0 PI)
8937 11:48:21.549221 u2DelayCellOfst[3]=7 cells (2 PI)
8938 11:48:21.552506 u2DelayCellOfst[4]=7 cells (2 PI)
8939 11:48:21.555854 u2DelayCellOfst[5]=17 cells (5 PI)
8940 11:48:21.559569 u2DelayCellOfst[6]=17 cells (5 PI)
8941 11:48:21.560026 u2DelayCellOfst[7]=3 cells (1 PI)
8942 11:48:21.565771 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8943 11:48:21.569156 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8944 11:48:21.569610 == TX Byte 1 ==
8945 11:48:21.572490 u2DelayCellOfst[8]=0 cells (0 PI)
8946 11:48:21.575429 u2DelayCellOfst[9]=7 cells (2 PI)
8947 11:48:21.578718 u2DelayCellOfst[10]=14 cells (4 PI)
8948 11:48:21.582374 u2DelayCellOfst[11]=7 cells (2 PI)
8949 11:48:21.585744 u2DelayCellOfst[12]=17 cells (5 PI)
8950 11:48:21.589395 u2DelayCellOfst[13]=17 cells (5 PI)
8951 11:48:21.592212 u2DelayCellOfst[14]=17 cells (5 PI)
8952 11:48:21.595583 u2DelayCellOfst[15]=17 cells (5 PI)
8953 11:48:21.598778 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8954 11:48:21.605521 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8955 11:48:21.605936 DramC Write-DBI on
8956 11:48:21.606291 ==
8957 11:48:21.608827 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 11:48:21.612191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 11:48:21.612609 ==
8960 11:48:21.615358
8961 11:48:21.615765
8962 11:48:21.616094 TX Vref Scan disable
8963 11:48:21.618676 == TX Byte 0 ==
8964 11:48:21.622394 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8965 11:48:21.625279 == TX Byte 1 ==
8966 11:48:21.628417 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8967 11:48:21.628642 DramC Write-DBI off
8968 11:48:21.628820
8969 11:48:21.632339 [DATLAT]
8970 11:48:21.632660 Freq=1600, CH1 RK1
8971 11:48:21.632853
8972 11:48:21.635095 DATLAT Default: 0xf
8973 11:48:21.635273 0, 0xFFFF, sum = 0
8974 11:48:21.638676 1, 0xFFFF, sum = 0
8975 11:48:21.638828 2, 0xFFFF, sum = 0
8976 11:48:21.642203 3, 0xFFFF, sum = 0
8977 11:48:21.642354 4, 0xFFFF, sum = 0
8978 11:48:21.645429 5, 0xFFFF, sum = 0
8979 11:48:21.645580 6, 0xFFFF, sum = 0
8980 11:48:21.648773 7, 0xFFFF, sum = 0
8981 11:48:21.648927 8, 0xFFFF, sum = 0
8982 11:48:21.651953 9, 0xFFFF, sum = 0
8983 11:48:21.655200 10, 0xFFFF, sum = 0
8984 11:48:21.655352 11, 0xFFFF, sum = 0
8985 11:48:21.658825 12, 0xFFFF, sum = 0
8986 11:48:21.658997 13, 0xFFFF, sum = 0
8987 11:48:21.662088 14, 0x0, sum = 1
8988 11:48:21.662238 15, 0x0, sum = 2
8989 11:48:21.665787 16, 0x0, sum = 3
8990 11:48:21.665938 17, 0x0, sum = 4
8991 11:48:21.666060 best_step = 15
8992 11:48:21.666170
8993 11:48:21.668563 ==
8994 11:48:21.671975 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 11:48:21.675567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 11:48:21.675717 ==
8997 11:48:21.675835 RX Vref Scan: 0
8998 11:48:21.675945
8999 11:48:21.679039 RX Vref 0 -> 0, step: 1
9000 11:48:21.679189
9001 11:48:21.681982 RX Delay 11 -> 252, step: 4
9002 11:48:21.685345 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9003 11:48:21.688878 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9004 11:48:21.695780 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9005 11:48:21.699024 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9006 11:48:21.701946 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9007 11:48:21.705459 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9008 11:48:21.708675 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9009 11:48:21.715832 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9010 11:48:21.718509 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9011 11:48:21.721757 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9012 11:48:21.725011 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9013 11:48:21.728686 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9014 11:48:21.735153 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9015 11:48:21.738465 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9016 11:48:21.742053 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9017 11:48:21.745216 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9018 11:48:21.745297 ==
9019 11:48:21.748416 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 11:48:21.755699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 11:48:21.755780 ==
9022 11:48:21.755843 DQS Delay:
9023 11:48:21.755903 DQS0 = 0, DQS1 = 0
9024 11:48:21.758434 DQM Delay:
9025 11:48:21.758513 DQM0 = 129, DQM1 = 126
9026 11:48:21.762020 DQ Delay:
9027 11:48:21.765499 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9028 11:48:21.768711 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9029 11:48:21.772337 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
9030 11:48:21.775278 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9031 11:48:21.775359
9032 11:48:21.775423
9033 11:48:21.775482
9034 11:48:21.778261 [DramC_TX_OE_Calibration] TA2
9035 11:48:21.781510 Original DQ_B0 (3 6) =30, OEN = 27
9036 11:48:21.784993 Original DQ_B1 (3 6) =30, OEN = 27
9037 11:48:21.788214 24, 0x0, End_B0=24 End_B1=24
9038 11:48:21.788295 25, 0x0, End_B0=25 End_B1=25
9039 11:48:21.791710 26, 0x0, End_B0=26 End_B1=26
9040 11:48:21.794879 27, 0x0, End_B0=27 End_B1=27
9041 11:48:21.798293 28, 0x0, End_B0=28 End_B1=28
9042 11:48:21.798375 29, 0x0, End_B0=29 End_B1=29
9043 11:48:21.801953 30, 0x0, End_B0=30 End_B1=30
9044 11:48:21.805128 31, 0x5151, End_B0=30 End_B1=30
9045 11:48:21.808688 Byte0 end_step=30 best_step=27
9046 11:48:21.811557 Byte1 end_step=30 best_step=27
9047 11:48:21.815382 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 11:48:21.815468 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 11:48:21.818574
9050 11:48:21.818654
9051 11:48:21.825430 [DQSOSCAuto] RK1, (LSB)MR18= 0x1118, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
9052 11:48:21.828780 CH1 RK1: MR19=303, MR18=1118
9053 11:48:21.834849 CH1_RK1: MR19=0x303, MR18=0x1118, DQSOSC=397, MR23=63, INC=23, DEC=15
9054 11:48:21.838143 [RxdqsGatingPostProcess] freq 1600
9055 11:48:21.841571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 11:48:21.844867 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 11:48:21.848290 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 11:48:21.851676 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 11:48:21.854663 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 11:48:21.858351 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 11:48:21.861706 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 11:48:21.864789 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 11:48:21.868071 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 11:48:21.871292 Pre-setting of DQS Precalculation
9065 11:48:21.874773 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 11:48:21.881866 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 11:48:21.888810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 11:48:21.888892
9069 11:48:21.888956
9070 11:48:21.891943 [Calibration Summary] 3200 Mbps
9071 11:48:21.895236 CH 0, Rank 0
9072 11:48:21.895317 SW Impedance : PASS
9073 11:48:21.898214 DUTY Scan : NO K
9074 11:48:21.901495 ZQ Calibration : PASS
9075 11:48:21.901576 Jitter Meter : NO K
9076 11:48:21.905208 CBT Training : PASS
9077 11:48:21.908488 Write leveling : PASS
9078 11:48:21.908570 RX DQS gating : PASS
9079 11:48:21.911951 RX DQ/DQS(RDDQC) : PASS
9080 11:48:21.912033 TX DQ/DQS : PASS
9081 11:48:21.914832 RX DATLAT : PASS
9082 11:48:21.918529 RX DQ/DQS(Engine): PASS
9083 11:48:21.918610 TX OE : PASS
9084 11:48:21.921642 All Pass.
9085 11:48:21.921723
9086 11:48:21.921788 CH 0, Rank 1
9087 11:48:21.925484 SW Impedance : PASS
9088 11:48:21.925565 DUTY Scan : NO K
9089 11:48:21.928372 ZQ Calibration : PASS
9090 11:48:21.932055 Jitter Meter : NO K
9091 11:48:21.932136 CBT Training : PASS
9092 11:48:21.935266 Write leveling : PASS
9093 11:48:21.938351 RX DQS gating : PASS
9094 11:48:21.938432 RX DQ/DQS(RDDQC) : PASS
9095 11:48:21.941750 TX DQ/DQS : PASS
9096 11:48:21.945007 RX DATLAT : PASS
9097 11:48:21.945088 RX DQ/DQS(Engine): PASS
9098 11:48:21.948300 TX OE : PASS
9099 11:48:21.948381 All Pass.
9100 11:48:21.948446
9101 11:48:21.951812 CH 1, Rank 0
9102 11:48:21.951893 SW Impedance : PASS
9103 11:48:21.955188 DUTY Scan : NO K
9104 11:48:21.955269 ZQ Calibration : PASS
9105 11:48:21.958210 Jitter Meter : NO K
9106 11:48:21.961711 CBT Training : PASS
9107 11:48:21.961792 Write leveling : PASS
9108 11:48:21.965147 RX DQS gating : PASS
9109 11:48:21.968571 RX DQ/DQS(RDDQC) : PASS
9110 11:48:21.968652 TX DQ/DQS : PASS
9111 11:48:21.971900 RX DATLAT : PASS
9112 11:48:21.975382 RX DQ/DQS(Engine): PASS
9113 11:48:21.975463 TX OE : PASS
9114 11:48:21.978323 All Pass.
9115 11:48:21.978410
9116 11:48:21.978479 CH 1, Rank 1
9117 11:48:21.981826 SW Impedance : PASS
9118 11:48:21.981913 DUTY Scan : NO K
9119 11:48:21.985178 ZQ Calibration : PASS
9120 11:48:21.988509 Jitter Meter : NO K
9121 11:48:21.988611 CBT Training : PASS
9122 11:48:21.991760 Write leveling : PASS
9123 11:48:21.991861 RX DQS gating : PASS
9124 11:48:21.995514 RX DQ/DQS(RDDQC) : PASS
9125 11:48:21.998374 TX DQ/DQS : PASS
9126 11:48:21.998496 RX DATLAT : PASS
9127 11:48:22.001864 RX DQ/DQS(Engine): PASS
9128 11:48:22.005389 TX OE : PASS
9129 11:48:22.005525 All Pass.
9130 11:48:22.005631
9131 11:48:22.008894 DramC Write-DBI on
9132 11:48:22.009045 PER_BANK_REFRESH: Hybrid Mode
9133 11:48:22.012096 TX_TRACKING: ON
9134 11:48:22.018910 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 11:48:22.028589 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 11:48:22.035578 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 11:48:22.039187 [FAST_K] Save calibration result to emmc
9138 11:48:22.042312 sync common calibartion params.
9139 11:48:22.045563 sync cbt_mode0:1, 1:1
9140 11:48:22.045983 dram_init: ddr_geometry: 2
9141 11:48:22.049362 dram_init: ddr_geometry: 2
9142 11:48:22.052195 dram_init: ddr_geometry: 2
9143 11:48:22.052613 0:dram_rank_size:100000000
9144 11:48:22.055691 1:dram_rank_size:100000000
9145 11:48:22.062223 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 11:48:22.065653 DFS_SHUFFLE_HW_MODE: ON
9147 11:48:22.069201 dramc_set_vcore_voltage set vcore to 725000
9148 11:48:22.069621 Read voltage for 1600, 0
9149 11:48:22.072708 Vio18 = 0
9150 11:48:22.073123 Vcore = 725000
9151 11:48:22.073455 Vdram = 0
9152 11:48:22.075840 Vddq = 0
9153 11:48:22.076260 Vmddr = 0
9154 11:48:22.079032 switch to 3200 Mbps bootup
9155 11:48:22.079448 [DramcRunTimeConfig]
9156 11:48:22.079780 PHYPLL
9157 11:48:22.082547 DPM_CONTROL_AFTERK: ON
9158 11:48:22.085637 PER_BANK_REFRESH: ON
9159 11:48:22.086049 REFRESH_OVERHEAD_REDUCTION: ON
9160 11:48:22.088908 CMD_PICG_NEW_MODE: OFF
9161 11:48:22.092694 XRTWTW_NEW_MODE: ON
9162 11:48:22.093131 XRTRTR_NEW_MODE: ON
9163 11:48:22.093481 TX_TRACKING: ON
9164 11:48:22.095638 RDSEL_TRACKING: OFF
9165 11:48:22.098951 DQS Precalculation for DVFS: ON
9166 11:48:22.099370 RX_TRACKING: OFF
9167 11:48:22.102488 HW_GATING DBG: ON
9168 11:48:22.102935 ZQCS_ENABLE_LP4: ON
9169 11:48:22.105652 RX_PICG_NEW_MODE: ON
9170 11:48:22.108863 TX_PICG_NEW_MODE: ON
9171 11:48:22.109281 ENABLE_RX_DCM_DPHY: ON
9172 11:48:22.112892 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 11:48:22.115840 DUMMY_READ_FOR_TRACKING: OFF
9174 11:48:22.119360 !!! SPM_CONTROL_AFTERK: OFF
9175 11:48:22.119787 !!! SPM could not control APHY
9176 11:48:22.122365 IMPEDANCE_TRACKING: ON
9177 11:48:22.122734 TEMP_SENSOR: ON
9178 11:48:22.126274 HW_SAVE_FOR_SR: OFF
9179 11:48:22.128987 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 11:48:22.132862 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 11:48:22.135710 Read ODT Tracking: ON
9182 11:48:22.136178 Refresh Rate DeBounce: ON
9183 11:48:22.139099 DFS_NO_QUEUE_FLUSH: ON
9184 11:48:22.142278 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 11:48:22.145883 ENABLE_DFS_RUNTIME_MRW: OFF
9186 11:48:22.146324 DDR_RESERVE_NEW_MODE: ON
9187 11:48:22.149234 MR_CBT_SWITCH_FREQ: ON
9188 11:48:22.152372 =========================
9189 11:48:22.170124 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 11:48:22.173460 dram_init: ddr_geometry: 2
9191 11:48:22.191666 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 11:48:22.194850 dram_init: dram init end (result: 0)
9193 11:48:22.201828 DRAM-K: Full calibration passed in 24622 msecs
9194 11:48:22.205008 MRC: failed to locate region type 0.
9195 11:48:22.205543 DRAM rank0 size:0x100000000,
9196 11:48:22.208813 DRAM rank1 size=0x100000000
9197 11:48:22.218380 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 11:48:22.225288 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 11:48:22.231588 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 11:48:22.238362 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 11:48:22.241480 DRAM rank0 size:0x100000000,
9202 11:48:22.245537 DRAM rank1 size=0x100000000
9203 11:48:22.245967 CBMEM:
9204 11:48:22.248179 IMD: root @ 0xfffff000 254 entries.
9205 11:48:22.251637 IMD: root @ 0xffffec00 62 entries.
9206 11:48:22.254955 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 11:48:22.258216 WARNING: RO_VPD is uninitialized or empty.
9208 11:48:22.264818 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 11:48:22.271820 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 11:48:22.284427 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9211 11:48:22.295979 BS: romstage times (exec / console): total (unknown) / 24121 ms
9212 11:48:22.296397
9213 11:48:22.296722
9214 11:48:22.306133 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 11:48:22.309478 ARM64: Exception handlers installed.
9216 11:48:22.312352 ARM64: Testing exception
9217 11:48:22.316024 ARM64: Done test exception
9218 11:48:22.316488 Enumerating buses...
9219 11:48:22.319468 Show all devs... Before device enumeration.
9220 11:48:22.322707 Root Device: enabled 1
9221 11:48:22.325765 CPU_CLUSTER: 0: enabled 1
9222 11:48:22.326207 CPU: 00: enabled 1
9223 11:48:22.329498 Compare with tree...
9224 11:48:22.329910 Root Device: enabled 1
9225 11:48:22.332561 CPU_CLUSTER: 0: enabled 1
9226 11:48:22.335766 CPU: 00: enabled 1
9227 11:48:22.336186 Root Device scanning...
9228 11:48:22.339237 scan_static_bus for Root Device
9229 11:48:22.342917 CPU_CLUSTER: 0 enabled
9230 11:48:22.346223 scan_static_bus for Root Device done
9231 11:48:22.349238 scan_bus: bus Root Device finished in 8 msecs
9232 11:48:22.349717 done
9233 11:48:22.356165 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 11:48:22.359082 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 11:48:22.366010 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 11:48:22.369314 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 11:48:22.372611 Allocating resources...
9238 11:48:22.373022 Reading resources...
9239 11:48:22.379135 Root Device read_resources bus 0 link: 0
9240 11:48:22.379566 DRAM rank0 size:0x100000000,
9241 11:48:22.383040 DRAM rank1 size=0x100000000
9242 11:48:22.385945 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 11:48:22.389538 CPU: 00 missing read_resources
9244 11:48:22.392642 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 11:48:22.399038 Root Device read_resources bus 0 link: 0 done
9246 11:48:22.399466 Done reading resources.
9247 11:48:22.406182 Show resources in subtree (Root Device)...After reading.
9248 11:48:22.409255 Root Device child on link 0 CPU_CLUSTER: 0
9249 11:48:22.412533 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 11:48:22.422594 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 11:48:22.423063 CPU: 00
9252 11:48:22.426196 Root Device assign_resources, bus 0 link: 0
9253 11:48:22.429208 CPU_CLUSTER: 0 missing set_resources
9254 11:48:22.432399 Root Device assign_resources, bus 0 link: 0 done
9255 11:48:22.436312 Done setting resources.
9256 11:48:22.443175 Show resources in subtree (Root Device)...After assigning values.
9257 11:48:22.446155 Root Device child on link 0 CPU_CLUSTER: 0
9258 11:48:22.449263 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 11:48:22.459020 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 11:48:22.459462 CPU: 00
9261 11:48:22.462491 Done allocating resources.
9262 11:48:22.466141 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 11:48:22.469409 Enabling resources...
9264 11:48:22.469830 done.
9265 11:48:22.472619 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 11:48:22.475797 Initializing devices...
9267 11:48:22.479339 Root Device init
9268 11:48:22.479762 init hardware done!
9269 11:48:22.482368 0x00000018: ctrlr->caps
9270 11:48:22.483031 52.000 MHz: ctrlr->f_max
9271 11:48:22.486103 0.400 MHz: ctrlr->f_min
9272 11:48:22.489055 0x40ff8080: ctrlr->voltages
9273 11:48:22.489472 sclk: 390625
9274 11:48:22.492907 Bus Width = 1
9275 11:48:22.493317 sclk: 390625
9276 11:48:22.493642 Bus Width = 1
9277 11:48:22.496206 Early init status = 3
9278 11:48:22.499393 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 11:48:22.503819 in-header: 03 fc 00 00 01 00 00 00
9280 11:48:22.507045 in-data: 00
9281 11:48:22.509821 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 11:48:22.514901 in-header: 03 fd 00 00 00 00 00 00
9283 11:48:22.517863 in-data:
9284 11:48:22.521612 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 11:48:22.524881 in-header: 03 fc 00 00 01 00 00 00
9286 11:48:22.528170 in-data: 00
9287 11:48:22.531278 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 11:48:22.536190 in-header: 03 fd 00 00 00 00 00 00
9289 11:48:22.539467 in-data:
9290 11:48:22.542530 [SSUSB] Setting up USB HOST controller...
9291 11:48:22.546222 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 11:48:22.549461 [SSUSB] phy power-on done.
9293 11:48:22.552546 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 11:48:22.559135 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 11:48:22.562897 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 11:48:22.569623 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 11:48:22.575795 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9298 11:48:22.582479 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 11:48:22.589391 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 11:48:22.595892 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 11:48:22.598969 SPM: binary array size = 0x9dc
9302 11:48:22.602496 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 11:48:22.609278 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 11:48:22.615879 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 11:48:22.619431 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 11:48:22.622449 configure_display: Starting display init
9307 11:48:22.658803 anx7625_power_on_init: Init interface.
9308 11:48:22.662175 anx7625_disable_pd_protocol: Disabled PD feature.
9309 11:48:22.665706 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 11:48:22.693073 anx7625_start_dp_work: Secure OCM version=00
9311 11:48:22.696644 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 11:48:22.711270 sp_tx_get_edid_block: EDID Block = 1
9313 11:48:22.814253 Extracted contents:
9314 11:48:22.818156 header: 00 ff ff ff ff ff ff 00
9315 11:48:22.821379 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 11:48:22.824550 version: 01 04
9317 11:48:22.828225 basic params: 95 1f 11 78 0a
9318 11:48:22.831096 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 11:48:22.833956 established: 00 00 00
9320 11:48:22.840881 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 11:48:22.844244 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 11:48:22.850887 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 11:48:22.857566 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 11:48:22.864302 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 11:48:22.867595 extensions: 00
9326 11:48:22.868008 checksum: fb
9327 11:48:22.868338
9328 11:48:22.870910 Manufacturer: IVO Model 57d Serial Number 0
9329 11:48:22.874419 Made week 0 of 2020
9330 11:48:22.874893 EDID version: 1.4
9331 11:48:22.877210 Digital display
9332 11:48:22.880714 6 bits per primary color channel
9333 11:48:22.881174 DisplayPort interface
9334 11:48:22.884051 Maximum image size: 31 cm x 17 cm
9335 11:48:22.887816 Gamma: 220%
9336 11:48:22.888231 Check DPMS levels
9337 11:48:22.890947 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 11:48:22.894165 First detailed timing is preferred timing
9339 11:48:22.897942 Established timings supported:
9340 11:48:22.901308 Standard timings supported:
9341 11:48:22.901723 Detailed timings
9342 11:48:22.907698 Hex of detail: 383680a07038204018303c0035ae10000019
9343 11:48:22.910853 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 11:48:22.917271 0780 0798 07c8 0820 hborder 0
9345 11:48:22.920944 0438 043b 0447 0458 vborder 0
9346 11:48:22.921360 -hsync -vsync
9347 11:48:22.924002 Did detailed timing
9348 11:48:22.927415 Hex of detail: 000000000000000000000000000000000000
9349 11:48:22.930689 Manufacturer-specified data, tag 0
9350 11:48:22.937479 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 11:48:22.937897 ASCII string: InfoVision
9352 11:48:22.944118 Hex of detail: 000000fe00523134304e574635205248200a
9353 11:48:22.947398 ASCII string: R140NWF5 RH
9354 11:48:22.947813 Checksum
9355 11:48:22.948142 Checksum: 0xfb (valid)
9356 11:48:22.953727 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 11:48:22.957072 DSI data_rate: 832800000 bps
9358 11:48:22.960501 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 11:48:22.963725 anx7625_parse_edid: pixelclock(138800).
9360 11:48:22.970470 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 11:48:22.973709 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 11:48:22.976905 anx7625_dsi_config: config dsi.
9363 11:48:22.983570 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 11:48:22.996420 anx7625_dsi_config: success to config DSI
9365 11:48:22.999347 anx7625_dp_start: MIPI phy setup OK.
9366 11:48:23.003108 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 11:48:23.006282 mtk_ddp_mode_set invalid vrefresh 60
9368 11:48:23.009936 main_disp_path_setup
9369 11:48:23.010231 ovl_layer_smi_id_en
9370 11:48:23.013349 ovl_layer_smi_id_en
9371 11:48:23.013645 ccorr_config
9372 11:48:23.013878 aal_config
9373 11:48:23.016627 gamma_config
9374 11:48:23.016920 postmask_config
9375 11:48:23.017155 dither_config
9376 11:48:23.023099 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 11:48:23.030064 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 11:48:23.032959 Root Device init finished in 551 msecs
9379 11:48:23.033498 CPU_CLUSTER: 0 init
9380 11:48:23.043381 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 11:48:23.046239 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 11:48:23.049781 APU_MBOX 0x190000b0 = 0x10001
9383 11:48:23.052891 APU_MBOX 0x190001b0 = 0x10001
9384 11:48:23.056264 APU_MBOX 0x190005b0 = 0x10001
9385 11:48:23.060196 APU_MBOX 0x190006b0 = 0x10001
9386 11:48:23.063194 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 11:48:23.075213 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9388 11:48:23.087824 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 11:48:23.094776 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 11:48:23.106312 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9391 11:48:23.115323 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 11:48:23.118702 CPU_CLUSTER: 0 init finished in 81 msecs
9393 11:48:23.122469 Devices initialized
9394 11:48:23.125096 Show all devs... After init.
9395 11:48:23.125514 Root Device: enabled 1
9396 11:48:23.128533 CPU_CLUSTER: 0: enabled 1
9397 11:48:23.132201 CPU: 00: enabled 1
9398 11:48:23.135143 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9399 11:48:23.138253 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 11:48:23.141595 ELOG: NV offset 0x57f000 size 0x1000
9401 11:48:23.148105 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9402 11:48:23.154844 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 11:48:23.158365 ELOG: Event(17) added with size 13 at 2023-11-24 11:48:23 UTC
9404 11:48:23.161748 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 11:48:23.165495 in-header: 03 af 00 00 2c 00 00 00
9406 11:48:23.179186 in-data: b0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 11:48:23.185906 ELOG: Event(A1) added with size 10 at 2023-11-24 11:48:23 UTC
9408 11:48:23.192591 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9409 11:48:23.195844 ELOG: Event(A0) added with size 9 at 2023-11-24 11:48:23 UTC
9410 11:48:23.202604 elog_add_boot_reason: Logged dev mode boot
9411 11:48:23.206312 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 11:48:23.209413 Finalize devices...
9413 11:48:23.209835 Devices finalized
9414 11:48:23.215735 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 11:48:23.219379 Writing coreboot table at 0xffe64000
9416 11:48:23.222469 0. 000000000010a000-0000000000113fff: RAMSTAGE
9417 11:48:23.225981 1. 0000000040000000-00000000400fffff: RAM
9418 11:48:23.229486 2. 0000000040100000-000000004032afff: RAMSTAGE
9419 11:48:23.232488 3. 000000004032b000-00000000545fffff: RAM
9420 11:48:23.239325 4. 0000000054600000-000000005465ffff: BL31
9421 11:48:23.242983 5. 0000000054660000-00000000ffe63fff: RAM
9422 11:48:23.245784 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9423 11:48:23.252388 7. 0000000100000000-000000023fffffff: RAM
9424 11:48:23.252813 Passing 5 GPIOs to payload:
9425 11:48:23.259475 NAME | PORT | POLARITY | VALUE
9426 11:48:23.262833 EC in RW | 0x000000aa | low | undefined
9427 11:48:23.266335 EC interrupt | 0x00000005 | low | undefined
9428 11:48:23.272498 TPM interrupt | 0x000000ab | high | undefined
9429 11:48:23.276075 SD card detect | 0x00000011 | high | undefined
9430 11:48:23.282589 speaker enable | 0x00000093 | high | undefined
9431 11:48:23.285655 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9432 11:48:23.289249 in-header: 03 f9 00 00 02 00 00 00
9433 11:48:23.289669 in-data: 02 00
9434 11:48:23.292693 ADC[4]: Raw value=900590 ID=7
9435 11:48:23.296232 ADC[3]: Raw value=213336 ID=1
9436 11:48:23.296651 RAM Code: 0x71
9437 11:48:23.299427 ADC[6]: Raw value=74557 ID=0
9438 11:48:23.302956 ADC[5]: Raw value=212229 ID=1
9439 11:48:23.303377 SKU Code: 0x1
9440 11:48:23.309314 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd5
9441 11:48:23.312707 coreboot table: 964 bytes.
9442 11:48:23.316223 IMD ROOT 0. 0xfffff000 0x00001000
9443 11:48:23.319297 IMD SMALL 1. 0xffffe000 0x00001000
9444 11:48:23.322708 RO MCACHE 2. 0xffffc000 0x00001104
9445 11:48:23.326315 CONSOLE 3. 0xfff7c000 0x00080000
9446 11:48:23.329432 FMAP 4. 0xfff7b000 0x00000452
9447 11:48:23.332888 TIME STAMP 5. 0xfff7a000 0x00000910
9448 11:48:23.333311 VBOOT WORK 6. 0xfff66000 0x00014000
9449 11:48:23.336093 RAMOOPS 7. 0xffe66000 0x00100000
9450 11:48:23.339786 COREBOOT 8. 0xffe64000 0x00002000
9451 11:48:23.342901 IMD small region:
9452 11:48:23.346534 IMD ROOT 0. 0xffffec00 0x00000400
9453 11:48:23.349743 VPD 1. 0xffffeb80 0x0000006c
9454 11:48:23.352989 MMC STATUS 2. 0xffffeb60 0x00000004
9455 11:48:23.359406 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9456 11:48:23.359856 Probing TPM: done!
9457 11:48:23.366417 Connected to device vid:did:rid of 1ae0:0028:00
9458 11:48:23.373314 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9459 11:48:23.376467 Initialized TPM device CR50 revision 0
9460 11:48:23.379833 Checking cr50 for pending updates
9461 11:48:23.385265 Reading cr50 TPM mode
9462 11:48:23.393650 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9463 11:48:23.400615 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 11:48:23.440426 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9465 11:48:23.444094 Checking segment from ROM address 0x40100000
9466 11:48:23.447403 Checking segment from ROM address 0x4010001c
9467 11:48:23.454240 Loading segment from ROM address 0x40100000
9468 11:48:23.454748 code (compression=0)
9469 11:48:23.460724 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 11:48:23.471170 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 11:48:23.471663 it's not compressed!
9472 11:48:23.477256 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 11:48:23.480960 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 11:48:23.501238 Loading segment from ROM address 0x4010001c
9475 11:48:23.501655 Entry Point 0x80000000
9476 11:48:23.504539 Loaded segments
9477 11:48:23.507747 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 11:48:23.514569 Jumping to boot code at 0x80000000(0xffe64000)
9479 11:48:23.521865 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 11:48:23.527844 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 11:48:23.535343 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9482 11:48:23.538813 Checking segment from ROM address 0x40100000
9483 11:48:23.542324 Checking segment from ROM address 0x4010001c
9484 11:48:23.548768 Loading segment from ROM address 0x40100000
9485 11:48:23.549214 code (compression=1)
9486 11:48:23.555472 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 11:48:23.565374 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 11:48:23.566009 using LZMA
9489 11:48:23.573649 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 11:48:23.580632 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 11:48:23.583993 Loading segment from ROM address 0x4010001c
9492 11:48:23.584435 Entry Point 0x54601000
9493 11:48:23.587354 Loaded segments
9494 11:48:23.590302 NOTICE: MT8192 bl31_setup
9495 11:48:23.597625 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 11:48:23.601083 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 11:48:23.604217 WARNING: region 0:
9498 11:48:23.607363 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 11:48:23.607912 WARNING: region 1:
9500 11:48:23.614407 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 11:48:23.617290 WARNING: region 2:
9502 11:48:23.621008 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 11:48:23.624235 WARNING: region 3:
9504 11:48:23.627621 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 11:48:23.630978 WARNING: region 4:
9506 11:48:23.634405 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 11:48:23.637365 WARNING: region 5:
9508 11:48:23.641244 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 11:48:23.644386 WARNING: region 6:
9510 11:48:23.647652 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 11:48:23.648073 WARNING: region 7:
9512 11:48:23.654378 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 11:48:23.661222 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 11:48:23.664129 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 11:48:23.667972 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 11:48:23.671073 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 11:48:23.678105 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 11:48:23.681518 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 11:48:23.688043 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 11:48:23.691343 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 11:48:23.694961 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 11:48:23.701509 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 11:48:23.705016 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 11:48:23.707900 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 11:48:23.714831 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 11:48:23.718457 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 11:48:23.721045 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 11:48:23.728262 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 11:48:23.731212 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 11:48:23.738220 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 11:48:23.741389 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 11:48:23.744848 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 11:48:23.751555 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 11:48:23.754763 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 11:48:23.758085 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 11:48:23.764807 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 11:48:23.768361 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 11:48:23.774784 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 11:48:23.778525 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 11:48:23.781863 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 11:48:23.789080 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 11:48:23.792354 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 11:48:23.795617 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 11:48:23.801919 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 11:48:23.806024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 11:48:23.809219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 11:48:23.815723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 11:48:23.819243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 11:48:23.822322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 11:48:23.825670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 11:48:23.829284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 11:48:23.835882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 11:48:23.839279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 11:48:23.842433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 11:48:23.846197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 11:48:23.852772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 11:48:23.856467 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 11:48:23.859997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 11:48:23.862654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 11:48:23.869514 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 11:48:23.873190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 11:48:23.879904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 11:48:23.882916 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 11:48:23.886441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 11:48:23.893434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 11:48:23.896207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 11:48:23.903493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 11:48:23.906339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 11:48:23.909858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 11:48:23.916484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 11:48:23.920264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 11:48:23.926392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 11:48:23.929926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 11:48:23.936867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 11:48:23.939875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 11:48:23.943653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 11:48:23.950119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 11:48:23.953785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 11:48:23.960133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 11:48:23.963369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 11:48:23.967364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 11:48:23.973502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 11:48:23.977112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 11:48:23.983584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 11:48:23.987061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 11:48:23.993828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 11:48:23.997388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 11:48:24.000856 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 11:48:24.007335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 11:48:24.010713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 11:48:24.017608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 11:48:24.020444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 11:48:24.027153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 11:48:24.030504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 11:48:24.037223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 11:48:24.040529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 11:48:24.044227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 11:48:24.050819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 11:48:24.054023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 11:48:24.060823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 11:48:24.063656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 11:48:24.067062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 11:48:24.074367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 11:48:24.077751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 11:48:24.083663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 11:48:24.087834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 11:48:24.094252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 11:48:24.097874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 11:48:24.101211 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 11:48:24.104168 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 11:48:24.111133 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 11:48:24.114676 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 11:48:24.117649 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 11:48:24.124126 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 11:48:24.127822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 11:48:24.131203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 11:48:24.137533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 11:48:24.141236 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 11:48:24.147364 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 11:48:24.151330 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 11:48:24.154451 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 11:48:24.161282 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 11:48:24.164368 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 11:48:24.171296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 11:48:24.174253 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 11:48:24.178175 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 11:48:24.184606 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 11:48:24.187884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 11:48:24.191260 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 11:48:24.197995 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 11:48:24.201123 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 11:48:24.205187 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 11:48:24.207826 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 11:48:24.215028 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 11:48:24.217954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 11:48:24.221268 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 11:48:24.225103 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 11:48:24.231778 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 11:48:24.235468 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 11:48:24.242163 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 11:48:24.245269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 11:48:24.248331 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 11:48:24.255514 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 11:48:24.258345 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 11:48:24.261926 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 11:48:24.268014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 11:48:24.271719 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 11:48:24.278486 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 11:48:24.281640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 11:48:24.285069 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 11:48:24.291647 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 11:48:24.295384 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 11:48:24.298554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 11:48:24.305320 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 11:48:24.309028 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 11:48:24.315215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 11:48:24.318430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 11:48:24.321891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 11:48:24.328952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 11:48:24.331879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 11:48:24.338795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 11:48:24.342430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 11:48:24.345262 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 11:48:24.352196 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 11:48:24.355953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 11:48:24.358811 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 11:48:24.366062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 11:48:24.368885 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 11:48:24.375896 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 11:48:24.379064 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 11:48:24.382506 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 11:48:24.389616 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 11:48:24.392240 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 11:48:24.395804 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 11:48:24.402511 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 11:48:24.405825 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 11:48:24.412835 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 11:48:24.415688 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 11:48:24.419354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 11:48:24.425908 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 11:48:24.429246 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 11:48:24.432474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 11:48:24.440021 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 11:48:24.442533 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 11:48:24.449788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 11:48:24.453099 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 11:48:24.455736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 11:48:24.462841 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 11:48:24.465871 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 11:48:24.472832 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 11:48:24.476321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 11:48:24.479443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 11:48:24.486458 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 11:48:24.489878 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 11:48:24.493131 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 11:48:24.499660 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 11:48:24.503013 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 11:48:24.509660 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 11:48:24.512877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 11:48:24.516141 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 11:48:24.522825 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 11:48:24.526414 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 11:48:24.532543 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 11:48:24.536291 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 11:48:24.539622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 11:48:24.545843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 11:48:24.549465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 11:48:24.556308 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 11:48:24.559728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 11:48:24.562992 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 11:48:24.569487 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 11:48:24.573321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 11:48:24.580263 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 11:48:24.583133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 11:48:24.586537 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 11:48:24.593099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 11:48:24.596802 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 11:48:24.603241 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 11:48:24.606744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 11:48:24.609825 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 11:48:24.616611 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 11:48:24.619927 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 11:48:24.626756 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 11:48:24.630394 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 11:48:24.636703 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 11:48:24.639908 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 11:48:24.643543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 11:48:24.650359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 11:48:24.653977 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 11:48:24.660053 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 11:48:24.663077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 11:48:24.666515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 11:48:24.674180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 11:48:24.676359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 11:48:24.683784 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 11:48:24.686751 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 11:48:24.690073 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 11:48:24.696479 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 11:48:24.699720 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 11:48:24.706619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 11:48:24.710314 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 11:48:24.713781 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 11:48:24.716786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 11:48:24.723321 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 11:48:24.726688 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 11:48:24.730304 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 11:48:24.736397 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 11:48:24.739908 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 11:48:24.743566 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 11:48:24.749932 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 11:48:24.753024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 11:48:24.756198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 11:48:24.763503 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 11:48:24.766938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 11:48:24.773452 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 11:48:24.776255 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 11:48:24.779700 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 11:48:24.783344 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 11:48:24.790258 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 11:48:24.793260 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 11:48:24.796496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 11:48:24.803340 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 11:48:24.806414 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 11:48:24.813504 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 11:48:24.816258 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 11:48:24.819565 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 11:48:24.826855 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 11:48:24.830171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 11:48:24.833354 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 11:48:24.840326 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 11:48:24.843316 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 11:48:24.846583 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 11:48:24.853728 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 11:48:24.856902 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 11:48:24.863340 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 11:48:24.866921 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 11:48:24.869838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 11:48:24.876720 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 11:48:24.880348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 11:48:24.883065 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 11:48:24.889715 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 11:48:24.893432 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 11:48:24.896886 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 11:48:24.899904 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 11:48:24.904046 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 11:48:24.910479 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 11:48:24.913624 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 11:48:24.916637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 11:48:24.920080 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 11:48:24.926771 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 11:48:24.930573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 11:48:24.933741 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 11:48:24.937243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 11:48:24.943571 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 11:48:24.946790 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 11:48:24.953974 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 11:48:24.957566 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 11:48:24.960405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 11:48:24.967093 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 11:48:24.971076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 11:48:24.977452 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 11:48:24.980694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 11:48:24.983603 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 11:48:24.991058 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 11:48:24.993982 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 11:48:25.001064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 11:48:25.004124 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 11:48:25.007318 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 11:48:25.014269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 11:48:25.017102 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 11:48:25.023607 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 11:48:25.027419 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 11:48:25.030308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 11:48:25.037300 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 11:48:25.040475 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 11:48:25.046926 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 11:48:25.050009 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 11:48:25.053908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 11:48:25.059996 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 11:48:25.063757 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 11:48:25.069995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 11:48:25.073594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 11:48:25.076518 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 11:48:25.083154 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 11:48:25.086290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 11:48:25.093234 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 11:48:25.096511 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 11:48:25.099612 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 11:48:25.106528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 11:48:25.109744 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 11:48:25.116906 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 11:48:25.119958 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 11:48:25.126391 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 11:48:25.130185 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 11:48:25.133345 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 11:48:25.139992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 11:48:25.143237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 11:48:25.146292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 11:48:25.153598 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 11:48:25.156427 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 11:48:25.162770 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 11:48:25.166514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 11:48:25.169825 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 11:48:25.176454 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 11:48:25.179703 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 11:48:25.186645 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 11:48:25.189702 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 11:48:25.196842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 11:48:25.200007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 11:48:25.203258 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 11:48:25.209975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 11:48:25.213156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 11:48:25.216417 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 11:48:25.223264 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 11:48:25.226561 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 11:48:25.233501 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 11:48:25.236607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 11:48:25.239918 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 11:48:25.246612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 11:48:25.250282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 11:48:25.256652 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 11:48:25.260399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 11:48:25.263323 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 11:48:25.270515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 11:48:25.273781 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 11:48:25.280306 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 11:48:25.283739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 11:48:25.287062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 11:48:25.293814 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 11:48:25.296673 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 11:48:25.303683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 11:48:25.306755 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 11:48:25.313718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 11:48:25.316885 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 11:48:25.320187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 11:48:25.326762 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 11:48:25.330399 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 11:48:25.337123 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 11:48:25.340387 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 11:48:25.347178 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 11:48:25.350572 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 11:48:25.353881 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 11:48:25.360420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 11:48:25.364482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 11:48:25.370437 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 11:48:25.373871 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 11:48:25.380691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 11:48:25.384290 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 11:48:25.387091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 11:48:25.393816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 11:48:25.397439 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 11:48:25.403741 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 11:48:25.407025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 11:48:25.413896 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 11:48:25.416996 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 11:48:25.420310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 11:48:25.427886 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 11:48:25.430985 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 11:48:25.437668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 11:48:25.440524 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 11:48:25.444230 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 11:48:25.450556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 11:48:25.454217 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 11:48:25.461336 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 11:48:25.464208 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 11:48:25.470957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 11:48:25.474576 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 11:48:25.477310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 11:48:25.484450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 11:48:25.487366 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 11:48:25.494611 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 11:48:25.497455 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 11:48:25.504658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 11:48:25.507487 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 11:48:25.510548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 11:48:25.517181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 11:48:25.520639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 11:48:25.527881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 11:48:25.530778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 11:48:25.537481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 11:48:25.540868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 11:48:25.547349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 11:48:25.550672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 11:48:25.554438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 11:48:25.560734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 11:48:25.564522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 11:48:25.571011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 11:48:25.574521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 11:48:25.580849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 11:48:25.584380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 11:48:25.590857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 11:48:25.594124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 11:48:25.601418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 11:48:25.604324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 11:48:25.611115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 11:48:25.614227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 11:48:25.620853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 11:48:25.624502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 11:48:25.630985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 11:48:25.634819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 11:48:25.640755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 11:48:25.644519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 11:48:25.651349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 11:48:25.654500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 11:48:25.660831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 11:48:25.664206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 11:48:25.667628 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 11:48:25.670690 INFO: [APUAPC] vio 0
9949 11:48:25.677315 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 11:48:25.680781 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 11:48:25.684514 INFO: [APUAPC] D0_APC_0: 0x400510
9952 11:48:25.687455 INFO: [APUAPC] D0_APC_1: 0x0
9953 11:48:25.691289 INFO: [APUAPC] D0_APC_2: 0x1540
9954 11:48:25.694062 INFO: [APUAPC] D0_APC_3: 0x0
9955 11:48:25.697527 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 11:48:25.700908 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 11:48:25.704084 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 11:48:25.704166 INFO: [APUAPC] D1_APC_3: 0x0
9959 11:48:25.707663 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 11:48:25.714490 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 11:48:25.714572 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 11:48:25.717516 INFO: [APUAPC] D2_APC_3: 0x0
9963 11:48:25.721038 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 11:48:25.724623 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 11:48:25.727924 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 11:48:25.731455 INFO: [APUAPC] D3_APC_3: 0x0
9967 11:48:25.734555 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 11:48:25.737505 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 11:48:25.741114 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 11:48:25.744144 INFO: [APUAPC] D4_APC_3: 0x0
9971 11:48:25.747717 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 11:48:25.750813 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 11:48:25.754226 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 11:48:25.757493 INFO: [APUAPC] D5_APC_3: 0x0
9975 11:48:25.760928 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 11:48:25.764415 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 11:48:25.767770 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 11:48:25.771164 INFO: [APUAPC] D6_APC_3: 0x0
9979 11:48:25.774494 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 11:48:25.777787 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 11:48:25.781152 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 11:48:25.784274 INFO: [APUAPC] D7_APC_3: 0x0
9983 11:48:25.787998 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 11:48:25.791526 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 11:48:25.795035 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 11:48:25.798257 INFO: [APUAPC] D8_APC_3: 0x0
9987 11:48:25.801553 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 11:48:25.805145 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 11:48:25.808297 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 11:48:25.811913 INFO: [APUAPC] D9_APC_3: 0x0
9991 11:48:25.815101 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 11:48:25.818377 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 11:48:25.821382 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 11:48:25.825352 INFO: [APUAPC] D10_APC_3: 0x0
9995 11:48:25.828002 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 11:48:25.831508 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 11:48:25.835505 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 11:48:25.838437 INFO: [APUAPC] D11_APC_3: 0x0
9999 11:48:25.841725 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 11:48:25.845327 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 11:48:25.849330 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 11:48:25.851833 INFO: [APUAPC] D12_APC_3: 0x0
10003 11:48:25.855449 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 11:48:25.858823 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 11:48:25.862278 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 11:48:25.865136 INFO: [APUAPC] D13_APC_3: 0x0
10007 11:48:25.868652 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 11:48:25.871964 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 11:48:25.875326 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 11:48:25.877801 INFO: [APUAPC] D14_APC_3: 0x0
10011 11:48:25.881837 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 11:48:25.884596 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 11:48:25.887770 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 11:48:25.891120 INFO: [APUAPC] D15_APC_3: 0x0
10015 11:48:25.891265 INFO: [APUAPC] APC_CON: 0x4
10016 11:48:25.894631 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 11:48:25.897972 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 11:48:25.901121 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 11:48:25.904505 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 11:48:25.907759 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 11:48:25.911679 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 11:48:25.914609 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 11:48:25.918140 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 11:48:25.921318 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 11:48:25.924388 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 11:48:25.924517 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 11:48:25.928092 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 11:48:25.931410 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 11:48:25.934650 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 11:48:25.938082 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 11:48:25.941711 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 11:48:25.944943 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 11:48:25.947908 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 11:48:25.951052 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 11:48:25.954679 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 11:48:25.954850 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 11:48:25.958027 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 11:48:25.961637 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 11:48:25.964722 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 11:48:25.968072 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 11:48:25.971286 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 11:48:25.974664 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 11:48:25.978599 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 11:48:25.981859 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 11:48:25.984580 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 11:48:25.988318 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 11:48:25.991499 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 11:48:25.995290 INFO: [NOCDAPC] APC_CON: 0x4
10049 11:48:25.998171 INFO: [APUAPC] set_apusys_apc done
10050 11:48:26.001777 INFO: [DEVAPC] devapc_init done
10051 11:48:26.005222 INFO: GICv3 without legacy support detected.
10052 11:48:26.008205 INFO: ARM GICv3 driver initialized in EL3
10053 11:48:26.011679 INFO: Maximum SPI INTID supported: 639
10054 11:48:26.015064 INFO: BL31: Initializing runtime services
10055 11:48:26.022019 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 11:48:26.024819 INFO: SPM: enable CPC mode
10057 11:48:26.028222 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 11:48:26.034761 INFO: BL31: Preparing for EL3 exit to normal world
10059 11:48:26.038232 INFO: Entry point address = 0x80000000
10060 11:48:26.038736 INFO: SPSR = 0x8
10061 11:48:26.045667
10062 11:48:26.046219
10063 11:48:26.046583
10064 11:48:26.048691 Starting depthcharge on Spherion...
10065 11:48:26.049149
10066 11:48:26.049509 Wipe memory regions:
10067 11:48:26.049843
10068 11:48:26.052551 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10069 11:48:26.053080 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10070 11:48:26.053529 Setting prompt string to ['asurada:']
10071 11:48:26.053939 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10072 11:48:26.054640 [0x00000040000000, 0x00000054600000)
10073 11:48:26.174980
10074 11:48:26.175536 [0x00000054660000, 0x00000080000000)
10075 11:48:26.435750
10076 11:48:26.436322 [0x000000821a7280, 0x000000ffe64000)
10077 11:48:27.180149
10078 11:48:27.180696 [0x00000100000000, 0x00000240000000)
10079 11:48:29.070509
10080 11:48:29.073575 Initializing XHCI USB controller at 0x11200000.
10081 11:48:30.111755
10082 11:48:30.115332 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10083 11:48:30.115886
10084 11:48:30.116247
10085 11:48:30.116581
10086 11:48:30.117384 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 11:48:30.218691 asurada: tftpboot 192.168.201.1 12074050/tftp-deploy-tn_pzva9/kernel/image.itb 12074050/tftp-deploy-tn_pzva9/kernel/cmdline
10089 11:48:30.219436 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 11:48:30.220065 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10091 11:48:30.224414 tftpboot 192.168.201.1 12074050/tftp-deploy-tn_pzva9/kernel/image.ittp-deploy-tn_pzva9/kernel/cmdline
10092 11:48:30.224882
10093 11:48:30.225244 Waiting for link
10094 11:48:30.384553
10095 11:48:30.384693 R8152: Initializing
10096 11:48:30.384760
10097 11:48:30.388452 Version 6 (ocp_data = 5c30)
10098 11:48:30.388532
10099 11:48:30.391402 R8152: Done initializing
10100 11:48:30.391482
10101 11:48:30.391545 Adding net device
10102 11:48:32.321015
10103 11:48:32.321166 done.
10104 11:48:32.321233
10105 11:48:32.321292 MAC: 00:24:32:30:78:52
10106 11:48:32.321351
10107 11:48:32.324794 Sending DHCP discover... done.
10108 11:48:32.324875
10109 11:48:32.327766 Waiting for reply... done.
10110 11:48:32.327861
10111 11:48:32.330997 Sending DHCP request... done.
10112 11:48:32.331076
10113 11:48:32.335399 Waiting for reply... done.
10114 11:48:32.335478
10115 11:48:32.335541 My ip is 192.168.201.14
10116 11:48:32.335599
10117 11:48:32.338415 The DHCP server ip is 192.168.201.1
10118 11:48:32.338495
10119 11:48:32.345196 TFTP server IP predefined by user: 192.168.201.1
10120 11:48:32.345276
10121 11:48:32.351681 Bootfile predefined by user: 12074050/tftp-deploy-tn_pzva9/kernel/image.itb
10122 11:48:32.351763
10123 11:48:32.351826 Sending tftp read request... done.
10124 11:48:32.354967
10125 11:48:32.358594 Waiting for the transfer...
10126 11:48:32.358677
10127 11:48:32.928903 00000000 ################################################################
10128 11:48:32.929055
10129 11:48:33.500021 00080000 ################################################################
10130 11:48:33.500211
10131 11:48:34.065384 00100000 ################################################################
10132 11:48:34.065570
10133 11:48:34.634179 00180000 ################################################################
10134 11:48:34.634341
10135 11:48:35.204624 00200000 ################################################################
10136 11:48:35.204785
10137 11:48:35.779127 00280000 ################################################################
10138 11:48:35.779277
10139 11:48:36.336471 00300000 ################################################################
10140 11:48:36.336611
10141 11:48:36.903385 00380000 ################################################################
10142 11:48:36.903535
10143 11:48:37.467491 00400000 ################################################################
10144 11:48:37.467643
10145 11:48:38.027301 00480000 ################################################################
10146 11:48:38.027448
10147 11:48:38.586322 00500000 ################################################################
10148 11:48:38.586468
10149 11:48:39.150306 00580000 ################################################################
10150 11:48:39.150454
10151 11:48:39.709073 00600000 ################################################################
10152 11:48:39.709225
10153 11:48:40.268678 00680000 ################################################################
10154 11:48:40.268815
10155 11:48:40.841300 00700000 ################################################################
10156 11:48:40.841445
10157 11:48:41.443407 00780000 ################################################################
10158 11:48:41.443578
10159 11:48:42.037934 00800000 ################################################################
10160 11:48:42.038105
10161 11:48:42.615396 00880000 ################################################################
10162 11:48:42.615545
10163 11:48:43.172388 00900000 ################################################################
10164 11:48:43.172534
10165 11:48:43.747806 00980000 ################################################################
10166 11:48:43.747963
10167 11:48:44.370151 00a00000 ################################################################
10168 11:48:44.370619
10169 11:48:45.010403 00a80000 ################################################################
10170 11:48:45.010924
10171 11:48:45.597138 00b00000 ################################################################
10172 11:48:45.597288
10173 11:48:46.166565 00b80000 ################################################################
10174 11:48:46.166746
10175 11:48:46.748217 00c00000 ################################################################
10176 11:48:46.748377
10177 11:48:47.402755 00c80000 ################################################################
10178 11:48:47.403248
10179 11:48:48.010836 00d00000 ################################################################
10180 11:48:48.011381
10181 11:48:48.622304 00d80000 ################################################################
10182 11:48:48.622480
10183 11:48:49.209031 00e00000 ################################################################
10184 11:48:49.209181
10185 11:48:49.769186 00e80000 ################################################################
10186 11:48:49.769385
10187 11:48:50.329287 00f00000 ################################################################
10188 11:48:50.329437
10189 11:48:50.909256 00f80000 ################################################################
10190 11:48:50.909399
10191 11:48:51.473573 01000000 ################################################################
10192 11:48:51.473706
10193 11:48:52.037878 01080000 ################################################################
10194 11:48:52.038015
10195 11:48:52.595745 01100000 ################################################################
10196 11:48:52.595891
10197 11:48:53.168059 01180000 ################################################################
10198 11:48:53.168203
10199 11:48:53.760478 01200000 ################################################################
10200 11:48:53.760630
10201 11:48:54.343095 01280000 ################################################################
10202 11:48:54.343243
10203 11:48:54.915801 01300000 ################################################################
10204 11:48:54.915952
10205 11:48:55.486219 01380000 ################################################################
10206 11:48:55.486409
10207 11:48:56.039896 01400000 ################################################################
10208 11:48:56.040042
10209 11:48:56.618304 01480000 ################################################################
10210 11:48:56.618451
10211 11:48:57.195071 01500000 ################################################################
10212 11:48:57.195217
10213 11:48:57.748021 01580000 ################################################################
10214 11:48:57.748170
10215 11:48:58.301804 01600000 ################################################################
10216 11:48:58.301958
10217 11:48:58.836539 01680000 ################################################################
10218 11:48:58.836695
10219 11:48:59.413565 01700000 ################################################################
10220 11:48:59.413769
10221 11:48:59.960022 01780000 ################################################################
10222 11:48:59.960179
10223 11:49:00.518402 01800000 ################################################################
10224 11:49:00.518562
10225 11:49:01.076251 01880000 ################################################################
10226 11:49:01.076411
10227 11:49:01.609278 01900000 ################################################################
10228 11:49:01.609437
10229 11:49:02.139079 01980000 ################################################################
10230 11:49:02.139289
10231 11:49:02.672660 01a00000 ################################################################
10232 11:49:02.672826
10233 11:49:03.218940 01a80000 ################################################################
10234 11:49:03.219098
10235 11:49:03.754876 01b00000 ################################################################
10236 11:49:03.755036
10237 11:49:04.302145 01b80000 ################################################################
10238 11:49:04.302333
10239 11:49:04.836610 01c00000 ################################################################
10240 11:49:04.836777
10241 11:49:05.370640 01c80000 ################################################################
10242 11:49:05.370799
10243 11:49:05.915977 01d00000 ################################################################
10244 11:49:05.916142
10245 11:49:06.454065 01d80000 ################################################################
10246 11:49:06.454221
10247 11:49:06.996207 01e00000 ################################################################
10248 11:49:06.996366
10249 11:49:07.543277 01e80000 ################################################################
10250 11:49:07.543435
10251 11:49:08.075963 01f00000 ################################################################
10252 11:49:08.076120
10253 11:49:08.601768 01f80000 ################################################################
10254 11:49:08.601934
10255 11:49:09.155043 02000000 ################################################################
10256 11:49:09.155200
10257 11:49:09.686705 02080000 ################################################################
10258 11:49:09.686870
10259 11:49:10.218766 02100000 ################################################################
10260 11:49:10.218965
10261 11:49:10.775343 02180000 ################################################################
10262 11:49:10.775493
10263 11:49:11.342609 02200000 ################################################################
10264 11:49:11.342768
10265 11:49:11.913726 02280000 ################################################################
10266 11:49:11.913882
10267 11:49:12.486634 02300000 ################################################################
10268 11:49:12.486787
10269 11:49:13.050887 02380000 ################################################################
10270 11:49:13.051073
10271 11:49:13.630342 02400000 ################################################################
10272 11:49:13.630518
10273 11:49:14.264336 02480000 ################################################################
10274 11:49:14.264822
10275 11:49:14.921476 02500000 ################################################################
10276 11:49:14.921656
10277 11:49:15.570975 02580000 ################################################################
10278 11:49:15.571493
10279 11:49:16.291703 02600000 ################################################################
10280 11:49:16.292250
10281 11:49:17.002743 02680000 ################################################################
10282 11:49:17.003294
10283 11:49:17.704452 02700000 ################################################################
10284 11:49:17.704970
10285 11:49:18.335543 02780000 ################################################################
10286 11:49:18.335681
10287 11:49:18.958707 02800000 ################################################################
10288 11:49:18.958844
10289 11:49:19.604212 02880000 ################################################################
10290 11:49:19.604374
10291 11:49:20.278214 02900000 ################################################################
10292 11:49:20.278713
10293 11:49:20.954275 02980000 ################################################################
10294 11:49:20.954411
10295 11:49:21.642948 02a00000 ################################################################
10296 11:49:21.643078
10297 11:49:22.196674 02a80000 ################################################################
10298 11:49:22.196820
10299 11:49:22.754640 02b00000 ################################################################
10300 11:49:22.754789
10301 11:49:23.331805 02b80000 ################################################################
10302 11:49:23.331943
10303 11:49:23.857843 02c00000 ################################################################
10304 11:49:23.857977
10305 11:49:24.371779 02c80000 ################################################################
10306 11:49:24.371921
10307 11:49:24.887437 02d00000 ################################################################
10308 11:49:24.887574
10309 11:49:25.403513 02d80000 ################################################################
10310 11:49:25.403657
10311 11:49:25.916079 02e00000 ################################################################
10312 11:49:25.916216
10313 11:49:26.431463 02e80000 ################################################################
10314 11:49:26.431622
10315 11:49:26.947223 02f00000 ################################################################
10316 11:49:26.947359
10317 11:49:27.463263 02f80000 ################################################################
10318 11:49:27.463395
10319 11:49:27.605654 03000000 ################## done.
10320 11:49:27.605865
10321 11:49:27.609158 The bootfile was 50476062 bytes long.
10322 11:49:27.609364
10323 11:49:27.612472 Sending tftp read request... done.
10324 11:49:27.612601
10325 11:49:27.612719 Waiting for the transfer...
10326 11:49:27.612812
10327 11:49:27.615819 00000000 # done.
10328 11:49:27.615910
10329 11:49:27.622168 Command line loaded dynamically from TFTP file: 12074050/tftp-deploy-tn_pzva9/kernel/cmdline
10330 11:49:27.622265
10331 11:49:27.635660 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10332 11:49:27.635773
10333 11:49:27.639055 Loading FIT.
10334 11:49:27.639158
10335 11:49:27.642872 Image ramdisk-1 has 39378501 bytes.
10336 11:49:27.643051
10337 11:49:27.643139 Image fdt-1 has 47278 bytes.
10338 11:49:27.643201
10339 11:49:27.645866 Image kernel-1 has 11048246 bytes.
10340 11:49:27.645979
10341 11:49:27.655687 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 11:49:27.655806
10343 11:49:27.672550 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 11:49:27.672639
10345 11:49:27.679038 Choosing best match conf-1 for compat google,spherion-rev2.
10346 11:49:27.683130
10347 11:49:27.687734 Connected to device vid:did:rid of 1ae0:0028:00
10348 11:49:27.695698
10349 11:49:27.699616 tpm_get_response: command 0x17b, return code 0x0
10350 11:49:27.699699
10351 11:49:27.702945 ec_init: CrosEC protocol v3 supported (256, 248)
10352 11:49:27.706298
10353 11:49:27.710088 tpm_cleanup: add release locality here.
10354 11:49:27.710173
10355 11:49:27.710240 Shutting down all USB controllers.
10356 11:49:27.713266
10357 11:49:27.713379 Removing current net device
10358 11:49:27.713453
10359 11:49:27.719725 Exiting depthcharge with code 4 at timestamp: 91111681
10360 11:49:27.719821
10361 11:49:27.723450 LZMA decompressing kernel-1 to 0x821a6718
10362 11:49:27.723547
10363 11:49:27.726648 LZMA decompressing kernel-1 to 0x40000000
10364 11:49:29.115228
10365 11:49:29.115372 jumping to kernel
10366 11:49:29.115883 end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10367 11:49:29.115982 start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10368 11:49:29.116058 Setting prompt string to ['Linux version [0-9]']
10369 11:49:29.116159 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 11:49:29.116273 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 11:49:29.197242
10372 11:49:29.200242 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 11:49:29.203903 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10374 11:49:29.204002 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 11:49:29.204074 Setting prompt string to []
10376 11:49:29.204154 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 11:49:29.204230 Using line separator: #'\n'#
10378 11:49:29.204289 No login prompt set.
10379 11:49:29.204351 Parsing kernel messages
10380 11:49:29.204406 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 11:49:29.204562 [login-action] Waiting for messages, (timeout 00:03:22)
10382 11:49:29.224101 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10383 11:49:29.227223 [ 0.000000] random: crng init done
10384 11:49:29.230922 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10385 11:49:29.233909 [ 0.000000] efi: UEFI not found.
10386 11:49:29.243647 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10387 11:49:29.250256 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10388 11:49:29.260890 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10389 11:49:29.270340 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10390 11:49:29.276935 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10391 11:49:29.280015 [ 0.000000] printk: bootconsole [mtk8250] enabled
10392 11:49:29.288967 [ 0.000000] NUMA: No NUMA configuration found
10393 11:49:29.295151 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10394 11:49:29.301885 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10395 11:49:29.301991 [ 0.000000] Zone ranges:
10396 11:49:29.308575 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10397 11:49:29.312173 [ 0.000000] DMA32 empty
10398 11:49:29.318870 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10399 11:49:29.322456 [ 0.000000] Movable zone start for each node
10400 11:49:29.325309 [ 0.000000] Early memory node ranges
10401 11:49:29.332120 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10402 11:49:29.339051 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10403 11:49:29.345591 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10404 11:49:29.352436 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10405 11:49:29.355585 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10406 11:49:29.365935 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10407 11:49:29.421351 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10408 11:49:29.428033 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10409 11:49:29.434337 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10410 11:49:29.438034 [ 0.000000] psci: probing for conduit method from DT.
10411 11:49:29.444743 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10412 11:49:29.448259 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10413 11:49:29.454665 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10414 11:49:29.458375 [ 0.000000] psci: SMC Calling Convention v1.2
10415 11:49:29.464666 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10416 11:49:29.467905 [ 0.000000] Detected VIPT I-cache on CPU0
10417 11:49:29.474689 [ 0.000000] CPU features: detected: GIC system register CPU interface
10418 11:49:29.481673 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10419 11:49:29.488474 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10420 11:49:29.494959 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10421 11:49:29.501033 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10422 11:49:29.507777 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10423 11:49:29.514551 [ 0.000000] alternatives: applying boot alternatives
10424 11:49:29.518138 [ 0.000000] Fallback order for Node 0: 0
10425 11:49:29.524929 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10426 11:49:29.528393 [ 0.000000] Policy zone: Normal
10427 11:49:29.544521 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10428 11:49:29.554536 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10429 11:49:29.565702 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10430 11:49:29.576093 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10431 11:49:29.582156 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10432 11:49:29.585488 <6>[ 0.000000] software IO TLB: area num 8.
10433 11:49:29.642269 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10434 11:49:29.791308 <6>[ 0.000000] Memory: 7931168K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 421600K reserved, 32768K cma-reserved)
10435 11:49:29.797839 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10436 11:49:29.804607 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10437 11:49:29.808108 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10438 11:49:29.815187 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10439 11:49:29.821172 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10440 11:49:29.824730 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10441 11:49:29.834557 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10442 11:49:29.841004 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10443 11:49:29.844577 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10444 11:49:29.852033 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10445 11:49:29.855457 <6>[ 0.000000] GICv3: 608 SPIs implemented
10446 11:49:29.862141 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10447 11:49:29.865278 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10448 11:49:29.868388 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10449 11:49:29.879011 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10450 11:49:29.888749 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10451 11:49:29.902186 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10452 11:49:29.909048 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10453 11:49:29.917682 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10454 11:49:29.931298 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10455 11:49:29.937570 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10456 11:49:29.944449 <6>[ 0.009182] Console: colour dummy device 80x25
10457 11:49:29.954749 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10458 11:49:29.958121 <6>[ 0.024380] pid_max: default: 32768 minimum: 301
10459 11:49:29.964274 <6>[ 0.029252] LSM: Security Framework initializing
10460 11:49:29.971209 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 11:49:29.981181 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 11:49:29.987965 <6>[ 0.051402] cblist_init_generic: Setting adjustable number of callback queues.
10463 11:49:29.994549 <6>[ 0.058845] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 11:49:30.001321 <6>[ 0.065183] cblist_init_generic: Setting adjustable number of callback queues.
10465 11:49:30.008011 <6>[ 0.072610] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 11:49:30.014972 <6>[ 0.079048] rcu: Hierarchical SRCU implementation.
10467 11:49:30.017629 <6>[ 0.084063] rcu: Max phase no-delay instances is 1000.
10468 11:49:30.026243 <6>[ 0.091120] EFI services will not be available.
10469 11:49:30.029545 <6>[ 0.096073] smp: Bringing up secondary CPUs ...
10470 11:49:30.038735 <6>[ 0.101117] Detected VIPT I-cache on CPU1
10471 11:49:30.045097 <6>[ 0.101187] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10472 11:49:30.051646 <6>[ 0.101219] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10473 11:49:30.055024 <6>[ 0.101556] Detected VIPT I-cache on CPU2
10474 11:49:30.061676 <6>[ 0.101608] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10475 11:49:30.068398 <6>[ 0.101626] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10476 11:49:30.074834 <6>[ 0.101883] Detected VIPT I-cache on CPU3
10477 11:49:30.082166 <6>[ 0.101929] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10478 11:49:30.088172 <6>[ 0.101944] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10479 11:49:30.091784 <6>[ 0.102245] CPU features: detected: Spectre-v4
10480 11:49:30.098179 <6>[ 0.102252] CPU features: detected: Spectre-BHB
10481 11:49:30.101835 <6>[ 0.102257] Detected PIPT I-cache on CPU4
10482 11:49:30.108178 <6>[ 0.102316] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10483 11:49:30.115049 <6>[ 0.102332] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10484 11:49:30.118403 <6>[ 0.102620] Detected PIPT I-cache on CPU5
10485 11:49:30.128226 <6>[ 0.102685] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10486 11:49:30.134798 <6>[ 0.102701] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10487 11:49:30.138352 <6>[ 0.102980] Detected PIPT I-cache on CPU6
10488 11:49:30.145319 <6>[ 0.103048] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10489 11:49:30.152026 <6>[ 0.103064] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10490 11:49:30.155395 <6>[ 0.103360] Detected PIPT I-cache on CPU7
10491 11:49:30.165390 <6>[ 0.103426] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10492 11:49:30.171955 <6>[ 0.103442] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10493 11:49:30.175024 <6>[ 0.103490] smp: Brought up 1 node, 8 CPUs
10494 11:49:30.178611 <6>[ 0.244913] SMP: Total of 8 processors activated.
10495 11:49:30.184994 <6>[ 0.249864] CPU features: detected: 32-bit EL0 Support
10496 11:49:30.195153 <6>[ 0.255227] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10497 11:49:30.201842 <6>[ 0.264027] CPU features: detected: Common not Private translations
10498 11:49:30.205173 <6>[ 0.270503] CPU features: detected: CRC32 instructions
10499 11:49:30.211758 <6>[ 0.275854] CPU features: detected: RCpc load-acquire (LDAPR)
10500 11:49:30.218431 <6>[ 0.281814] CPU features: detected: LSE atomic instructions
10501 11:49:30.221926 <6>[ 0.287595] CPU features: detected: Privileged Access Never
10502 11:49:30.228351 <6>[ 0.293375] CPU features: detected: RAS Extension Support
10503 11:49:30.234907 <6>[ 0.298983] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10504 11:49:30.242249 <6>[ 0.306248] CPU: All CPU(s) started at EL2
10505 11:49:30.244927 <6>[ 0.310565] alternatives: applying system-wide alternatives
10506 11:49:30.255705 <6>[ 0.321271] devtmpfs: initialized
10507 11:49:30.268637 <6>[ 0.330193] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10508 11:49:30.278597 <6>[ 0.340154] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10509 11:49:30.285186 <6>[ 0.348332] pinctrl core: initialized pinctrl subsystem
10510 11:49:30.288047 <6>[ 0.355120] DMI not present or invalid.
10511 11:49:30.294933 <6>[ 0.359534] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10512 11:49:30.304541 <6>[ 0.366400] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10513 11:49:30.311310 <6>[ 0.373980] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10514 11:49:30.321197 <6>[ 0.382199] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10515 11:49:30.324492 <6>[ 0.390439] audit: initializing netlink subsys (disabled)
10516 11:49:30.334852 <5>[ 0.396132] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10517 11:49:30.341287 <6>[ 0.396868] thermal_sys: Registered thermal governor 'step_wise'
10518 11:49:30.347878 <6>[ 0.404099] thermal_sys: Registered thermal governor 'power_allocator'
10519 11:49:30.351582 <6>[ 0.410356] cpuidle: using governor menu
10520 11:49:30.357656 <6>[ 0.421320] NET: Registered PF_QIPCRTR protocol family
10521 11:49:30.364341 <6>[ 0.426803] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10522 11:49:30.367806 <6>[ 0.433908] ASID allocator initialised with 32768 entries
10523 11:49:30.375542 <6>[ 0.440520] Serial: AMBA PL011 UART driver
10524 11:49:30.384268 <4>[ 0.449701] Trying to register duplicate clock ID: 134
10525 11:49:30.441542 <6>[ 0.509979] KASLR enabled
10526 11:49:30.455921 <6>[ 0.517724] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10527 11:49:30.462519 <6>[ 0.524738] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10528 11:49:30.468991 <6>[ 0.531226] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10529 11:49:30.475807 <6>[ 0.538230] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10530 11:49:30.482401 <6>[ 0.544719] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10531 11:49:30.489239 <6>[ 0.551724] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10532 11:49:30.495784 <6>[ 0.558210] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10533 11:49:30.502582 <6>[ 0.565215] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10534 11:49:30.505982 <6>[ 0.572722] ACPI: Interpreter disabled.
10535 11:49:30.513686 <6>[ 0.579204] iommu: Default domain type: Translated
10536 11:49:30.520523 <6>[ 0.584319] iommu: DMA domain TLB invalidation policy: strict mode
10537 11:49:30.523727 <5>[ 0.590974] SCSI subsystem initialized
10538 11:49:30.530755 <6>[ 0.595136] usbcore: registered new interface driver usbfs
10539 11:49:30.537305 <6>[ 0.600867] usbcore: registered new interface driver hub
10540 11:49:30.540222 <6>[ 0.606419] usbcore: registered new device driver usb
10541 11:49:30.547636 <6>[ 0.612556] pps_core: LinuxPPS API ver. 1 registered
10542 11:49:30.557377 <6>[ 0.617750] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10543 11:49:30.561149 <6>[ 0.627098] PTP clock support registered
10544 11:49:30.564004 <6>[ 0.631344] EDAC MC: Ver: 3.0.0
10545 11:49:30.571193 <6>[ 0.636544] FPGA manager framework
10546 11:49:30.574710 <6>[ 0.640220] Advanced Linux Sound Architecture Driver Initialized.
10547 11:49:30.578245 <6>[ 0.646986] vgaarb: loaded
10548 11:49:30.585242 <6>[ 0.650160] clocksource: Switched to clocksource arch_sys_counter
10549 11:49:30.591742 <5>[ 0.656590] VFS: Disk quotas dquot_6.6.0
10550 11:49:30.598402 <6>[ 0.660773] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10551 11:49:30.601389 <6>[ 0.667958] pnp: PnP ACPI: disabled
10552 11:49:30.609321 <6>[ 0.674596] NET: Registered PF_INET protocol family
10553 11:49:30.619301 <6>[ 0.680181] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10554 11:49:30.630502 <6>[ 0.692460] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10555 11:49:30.640431 <6>[ 0.701270] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10556 11:49:30.646951 <6>[ 0.709241] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10557 11:49:30.653871 <6>[ 0.717939] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10558 11:49:30.665862 <6>[ 0.727684] TCP: Hash tables configured (established 65536 bind 65536)
10559 11:49:30.672856 <6>[ 0.734546] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 11:49:30.679074 <6>[ 0.741746] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 11:49:30.685912 <6>[ 0.749446] NET: Registered PF_UNIX/PF_LOCAL protocol family
10562 11:49:30.692292 <6>[ 0.755627] RPC: Registered named UNIX socket transport module.
10563 11:49:30.695897 <6>[ 0.761780] RPC: Registered udp transport module.
10564 11:49:30.702688 <6>[ 0.766714] RPC: Registered tcp transport module.
10565 11:49:30.708972 <6>[ 0.771645] RPC: Registered tcp NFSv4.1 backchannel transport module.
10566 11:49:30.712327 <6>[ 0.778314] PCI: CLS 0 bytes, default 64
10567 11:49:30.715536 <6>[ 0.782709] Unpacking initramfs...
10568 11:49:30.740738 <6>[ 0.802269] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10569 11:49:30.750509 <6>[ 0.810922] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10570 11:49:30.753683 <6>[ 0.819802] kvm [1]: IPA Size Limit: 40 bits
10571 11:49:30.760123 <6>[ 0.824330] kvm [1]: GICv3: no GICV resource entry
10572 11:49:30.763942 <6>[ 0.829354] kvm [1]: disabling GICv2 emulation
10573 11:49:30.770456 <6>[ 0.834041] kvm [1]: GIC system register CPU interface enabled
10574 11:49:30.773911 <6>[ 0.840217] kvm [1]: vgic interrupt IRQ18
10575 11:49:30.780461 <6>[ 0.844569] kvm [1]: VHE mode initialized successfully
10576 11:49:30.787191 <5>[ 0.850990] Initialise system trusted keyrings
10577 11:49:30.793690 <6>[ 0.855843] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10578 11:49:30.800871 <6>[ 0.865838] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10579 11:49:30.807392 <5>[ 0.872266] NFS: Registering the id_resolver key type
10580 11:49:30.810850 <5>[ 0.877569] Key type id_resolver registered
10581 11:49:30.817465 <5>[ 0.881985] Key type id_legacy registered
10582 11:49:30.823883 <6>[ 0.886268] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10583 11:49:30.830449 <6>[ 0.893191] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10584 11:49:30.836818 <6>[ 0.900896] 9p: Installing v9fs 9p2000 file system support
10585 11:49:30.872906 <5>[ 0.938193] Key type asymmetric registered
10586 11:49:30.876448 <5>[ 0.942523] Asymmetric key parser 'x509' registered
10587 11:49:30.886232 <6>[ 0.947706] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10588 11:49:30.889538 <6>[ 0.955323] io scheduler mq-deadline registered
10589 11:49:30.893171 <6>[ 0.960090] io scheduler kyber registered
10590 11:49:30.912213 <6>[ 0.977482] EINJ: ACPI disabled.
10591 11:49:30.944836 <4>[ 1.003658] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 11:49:30.955349 <4>[ 1.014317] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 11:49:30.970016 <6>[ 1.035180] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10594 11:49:30.977950 <6>[ 1.043148] printk: console [ttyS0] disabled
10595 11:49:31.005528 <6>[ 1.067791] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10596 11:49:31.012367 <6>[ 1.077267] printk: console [ttyS0] enabled
10597 11:49:31.015664 <6>[ 1.077267] printk: console [ttyS0] enabled
10598 11:49:31.022496 <6>[ 1.086161] printk: bootconsole [mtk8250] disabled
10599 11:49:31.025906 <6>[ 1.086161] printk: bootconsole [mtk8250] disabled
10600 11:49:31.032579 <6>[ 1.097435] SuperH (H)SCI(F) driver initialized
10601 11:49:31.035887 <6>[ 1.102761] msm_serial: driver initialized
10602 11:49:31.049971 <6>[ 1.111928] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10603 11:49:31.059986 <6>[ 1.120491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10604 11:49:31.067035 <6>[ 1.129033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10605 11:49:31.076659 <6>[ 1.137663] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10606 11:49:31.083384 <6>[ 1.146372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10607 11:49:31.093169 <6>[ 1.155085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10608 11:49:31.103272 <6>[ 1.163631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10609 11:49:31.110065 <6>[ 1.172435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10610 11:49:31.119676 <6>[ 1.180980] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10611 11:49:31.131527 <6>[ 1.196704] loop: module loaded
10612 11:49:31.138247 <6>[ 1.202868] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10613 11:49:31.160745 <4>[ 1.226289] mtk-pmic-keys: Failed to locate of_node [id: -1]
10614 11:49:31.167800 <6>[ 1.233232] megasas: 07.719.03.00-rc1
10615 11:49:31.177916 <6>[ 1.243043] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10616 11:49:31.184484 <6>[ 1.249577] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10617 11:49:31.201035 <6>[ 1.266423] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10618 11:49:31.257769 <6>[ 1.316578] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10619 11:49:32.307319 <6>[ 2.372854] Freeing initrd memory: 38448K
10620 11:49:32.318052 <6>[ 2.383332] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10621 11:49:32.328609 <6>[ 2.394183] tun: Universal TUN/TAP device driver, 1.6
10622 11:49:32.332020 <6>[ 2.400264] thunder_xcv, ver 1.0
10623 11:49:32.335426 <6>[ 2.403771] thunder_bgx, ver 1.0
10624 11:49:32.338721 <6>[ 2.407268] nicpf, ver 1.0
10625 11:49:32.349559 <6>[ 2.411308] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10626 11:49:32.352549 <6>[ 2.418784] hns3: Copyright (c) 2017 Huawei Corporation.
10627 11:49:32.359381 <6>[ 2.424375] hclge is initializing
10628 11:49:32.362456 <6>[ 2.427949] e1000: Intel(R) PRO/1000 Network Driver
10629 11:49:32.369285 <6>[ 2.433078] e1000: Copyright (c) 1999-2006 Intel Corporation.
10630 11:49:32.372447 <6>[ 2.439091] e1000e: Intel(R) PRO/1000 Network Driver
10631 11:49:32.379674 <6>[ 2.444306] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10632 11:49:32.386148 <6>[ 2.450490] igb: Intel(R) Gigabit Ethernet Network Driver
10633 11:49:32.392786 <6>[ 2.456140] igb: Copyright (c) 2007-2014 Intel Corporation.
10634 11:49:32.399149 <6>[ 2.461976] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10635 11:49:32.406149 <6>[ 2.468493] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10636 11:49:32.408791 <6>[ 2.474964] sky2: driver version 1.30
10637 11:49:32.415677 <6>[ 2.480027] VFIO - User Level meta-driver version: 0.3
10638 11:49:32.422936 <6>[ 2.488399] usbcore: registered new interface driver usb-storage
10639 11:49:32.429966 <6>[ 2.494853] usbcore: registered new device driver onboard-usb-hub
10640 11:49:32.439023 <6>[ 2.504064] mt6397-rtc mt6359-rtc: registered as rtc0
10641 11:49:32.448917 <6>[ 2.509528] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:49:33 UTC (1700826573)
10642 11:49:32.451764 <6>[ 2.519115] i2c_dev: i2c /dev entries driver
10643 11:49:32.469352 <6>[ 2.531015] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10644 11:49:32.488372 <6>[ 2.554012] cpu cpu0: EM: created perf domain
10645 11:49:32.491947 <6>[ 2.558936] cpu cpu4: EM: created perf domain
10646 11:49:32.499002 <6>[ 2.564518] sdhci: Secure Digital Host Controller Interface driver
10647 11:49:32.505887 <6>[ 2.570950] sdhci: Copyright(c) Pierre Ossman
10648 11:49:32.512882 <6>[ 2.575917] Synopsys Designware Multimedia Card Interface Driver
10649 11:49:32.518837 <6>[ 2.582569] sdhci-pltfm: SDHCI platform and OF driver helper
10650 11:49:32.522438 <6>[ 2.582663] mmc0: CQHCI version 5.10
10651 11:49:32.528813 <6>[ 2.592817] ledtrig-cpu: registered to indicate activity on CPUs
10652 11:49:32.535439 <6>[ 2.599826] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10653 11:49:32.542296 <6>[ 2.606884] usbcore: registered new interface driver usbhid
10654 11:49:32.545831 <6>[ 2.612708] usbhid: USB HID core driver
10655 11:49:32.552422 <6>[ 2.616913] spi_master spi0: will run message pump with realtime priority
10656 11:49:32.597075 <6>[ 2.655645] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10657 11:49:32.616554 <6>[ 2.671792] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10658 11:49:32.620087 <6>[ 2.686514] mmc0: Command Queue Engine enabled
10659 11:49:32.626538 <6>[ 2.686517] cros-ec-spi spi0.0: Chrome EC device registered
10660 11:49:32.633378 <6>[ 2.686539] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10661 11:49:32.639892 <6>[ 2.704366] mmcblk0: mmc0:0001 DA4128 116 GiB
10662 11:49:32.649765 <6>[ 2.714989] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10663 11:49:32.657377 <6>[ 2.722719] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10664 11:49:32.667013 <6>[ 2.728396] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 11:49:32.674125 <6>[ 2.728709] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10666 11:49:32.677313 <6>[ 2.739133] NET: Registered PF_PACKET protocol family
10667 11:49:32.683603 <6>[ 2.743638] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10668 11:49:32.690286 <6>[ 2.748329] 9pnet: Installing 9P2000 support
10669 11:49:32.693907 <5>[ 2.759322] Key type dns_resolver registered
10670 11:49:32.696980 <6>[ 2.764290] registered taskstats version 1
10671 11:49:32.703182 <5>[ 2.768665] Loading compiled-in X.509 certificates
10672 11:49:32.732549 <4>[ 2.791521] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10673 11:49:32.742419 <4>[ 2.802443] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 11:49:32.749283 <3>[ 2.812990] debugfs: File 'uA_load' in directory '/' already present!
10675 11:49:32.756224 <3>[ 2.819748] debugfs: File 'min_uV' in directory '/' already present!
10676 11:49:32.762534 <3>[ 2.826386] debugfs: File 'max_uV' in directory '/' already present!
10677 11:49:32.769522 <3>[ 2.833012] debugfs: File 'constraint_flags' in directory '/' already present!
10678 11:49:32.780403 <3>[ 2.842727] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 11:49:32.789219 <6>[ 2.854897] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 11:49:32.796413 <6>[ 2.861653] xhci-mtk 11200000.usb: xHCI Host Controller
10681 11:49:32.802731 <6>[ 2.867160] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 11:49:32.812870 <6>[ 2.875001] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 11:49:32.819426 <6>[ 2.884427] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 11:49:32.826313 <6>[ 2.890490] xhci-mtk 11200000.usb: xHCI Host Controller
10685 11:49:32.832984 <6>[ 2.895965] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 11:49:32.839367 <6>[ 2.903610] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 11:49:32.846179 <6>[ 2.911441] hub 1-0:1.0: USB hub found
10688 11:49:32.849270 <6>[ 2.915467] hub 1-0:1.0: 1 port detected
10689 11:49:32.859473 <6>[ 2.919713] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 11:49:32.862182 <6>[ 2.928437] hub 2-0:1.0: USB hub found
10691 11:49:32.865491 <6>[ 2.932459] hub 2-0:1.0: 1 port detected
10692 11:49:32.874756 <6>[ 2.940288] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 11:49:32.885192 <6>[ 2.946857] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10694 11:49:32.891623 <6>[ 2.954877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10695 11:49:32.901242 <4>[ 2.962783] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10696 11:49:32.911242 <6>[ 2.972311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10697 11:49:32.917759 <6>[ 2.980388] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 11:49:32.924462 <6>[ 2.988407] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 11:49:32.934647 <6>[ 2.996325] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 11:49:32.941232 <6>[ 3.004145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10701 11:49:32.951486 <6>[ 3.011962] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10702 11:49:32.961375 <6>[ 3.022485] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 11:49:32.967547 <6>[ 3.030848] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 11:49:32.977617 <6>[ 3.039188] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 11:49:32.984180 <6>[ 3.047527] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 11:49:32.995099 <6>[ 3.055865] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 11:49:33.000935 <6>[ 3.064203] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 11:49:33.010751 <6>[ 3.072541] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 11:49:33.017260 <6>[ 3.080879] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 11:49:33.027410 <6>[ 3.089218] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 11:49:33.034058 <6>[ 3.097557] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 11:49:33.044224 <6>[ 3.105895] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 11:49:33.050665 <6>[ 3.114247] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 11:49:33.060690 <6>[ 3.122588] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 11:49:33.067302 <6>[ 3.130927] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 11:49:33.077217 <6>[ 3.139265] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 11:49:33.083953 <6>[ 3.148021] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 11:49:33.090682 <6>[ 3.155187] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 11:49:33.097186 <6>[ 3.161956] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 11:49:33.103976 <6>[ 3.168719] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 11:49:33.110644 <6>[ 3.175656] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 11:49:33.120785 <6>[ 3.182498] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 11:49:33.130402 <6>[ 3.191625] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 11:49:33.140591 <6>[ 3.200743] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 11:49:33.150698 <6>[ 3.210037] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 11:49:33.156769 <6>[ 3.219508] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 11:49:33.167006 <6>[ 3.228979] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 11:49:33.177287 <6>[ 3.238100] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 11:49:33.187108 <6>[ 3.247588] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 11:49:33.197023 <6>[ 3.256708] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 11:49:33.206865 <6>[ 3.266001] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 11:49:33.216610 <6>[ 3.276162] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 11:49:33.226975 <6>[ 3.287730] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 11:49:33.256403 <6>[ 3.318656] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10735 11:49:33.283779 <6>[ 3.349214] hub 2-1:1.0: USB hub found
10736 11:49:33.286705 <6>[ 3.353640] hub 2-1:1.0: 3 ports detected
10737 11:49:33.295054 <6>[ 3.360516] hub 2-1:1.0: USB hub found
10738 11:49:33.298008 <6>[ 3.364875] hub 2-1:1.0: 3 ports detected
10739 11:49:33.407968 <6>[ 3.470448] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10740 11:49:33.563330 <6>[ 3.628523] hub 1-1:1.0: USB hub found
10741 11:49:33.566007 <6>[ 3.633011] hub 1-1:1.0: 4 ports detected
10742 11:49:33.576293 <6>[ 3.641677] hub 1-1:1.0: USB hub found
10743 11:49:33.579455 <6>[ 3.646214] hub 1-1:1.0: 4 ports detected
10744 11:49:33.648392 <6>[ 3.710508] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10745 11:49:33.900176 <6>[ 3.962493] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10746 11:49:34.032625 <6>[ 4.098131] hub 1-1.4:1.0: USB hub found
10747 11:49:34.036463 <6>[ 4.102779] hub 1-1.4:1.0: 2 ports detected
10748 11:49:34.045334 <6>[ 4.110694] hub 1-1.4:1.0: USB hub found
10749 11:49:34.048508 <6>[ 4.115306] hub 1-1.4:1.0: 2 ports detected
10750 11:49:34.343918 <6>[ 4.406455] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10751 11:49:34.536304 <6>[ 4.598454] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10752 11:49:45.497915 <6>[ 15.567431] ALSA device list:
10753 11:49:45.504071 <6>[ 15.570721] No soundcards found.
10754 11:49:45.512408 <6>[ 15.578667] Freeing unused kernel memory: 8384K
10755 11:49:45.515521 <6>[ 15.583652] Run /init as init process
10756 11:49:45.564217 <6>[ 15.630833] NET: Registered PF_INET6 protocol family
10757 11:49:45.571469 <6>[ 15.637002] Segment Routing with IPv6
10758 11:49:45.573862 <6>[ 15.640952] In-situ OAM (IOAM) with IPv6
10759 11:49:45.609543 <30>[ 15.656580] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10760 11:49:45.613106 <30>[ 15.680505] systemd[1]: Detected architecture arm64.
10761 11:49:45.613529
10762 11:49:45.619506 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10763 11:49:45.619923
10764 11:49:45.635854 <30>[ 15.702459] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10765 11:49:45.802026 <30>[ 15.865272] systemd[1]: Queued start job for default target Graphical Interface.
10766 11:49:45.848635 <30>[ 15.915169] systemd[1]: Created slice system-getty.slice.
10767 11:49:45.855351 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10768 11:49:45.872244 <30>[ 15.938999] systemd[1]: Created slice system-modprobe.slice.
10769 11:49:45.879083 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10770 11:49:45.896829 <30>[ 15.963741] systemd[1]: Created slice system-serial\x2dgetty.slice.
10771 11:49:45.907435 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10772 11:49:45.920231 <30>[ 15.986848] systemd[1]: Created slice User and Session Slice.
10773 11:49:45.926691 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10774 11:49:45.948093 <30>[ 16.011138] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10775 11:49:45.954634 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10776 11:49:45.976062 <30>[ 16.039127] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10777 11:49:45.982535 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10778 11:49:46.006943 <30>[ 16.066938] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10779 11:49:46.013503 <30>[ 16.079196] systemd[1]: Reached target Local Encrypted Volumes.
10780 11:49:46.020350 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10781 11:49:46.036232 <30>[ 16.103003] systemd[1]: Reached target Paths.
10782 11:49:46.039261 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10783 11:49:46.055881 <30>[ 16.122437] systemd[1]: Reached target Remote File Systems.
10784 11:49:46.061798 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10785 11:49:46.075231 <30>[ 16.142421] systemd[1]: Reached target Slices.
10786 11:49:46.078650 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10787 11:49:46.095655 <30>[ 16.162463] systemd[1]: Reached target Swap.
10788 11:49:46.099169 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10789 11:49:46.118993 <30>[ 16.182899] systemd[1]: Listening on initctl Compatibility Named Pipe.
10790 11:49:46.125643 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10791 11:49:46.140905 <30>[ 16.207861] systemd[1]: Listening on Journal Audit Socket.
10792 11:49:46.147438 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10793 11:49:46.164525 <30>[ 16.231595] systemd[1]: Listening on Journal Socket (/dev/log).
10794 11:49:46.171419 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10795 11:49:46.188646 <30>[ 16.255644] systemd[1]: Listening on Journal Socket.
10796 11:49:46.195159 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10797 11:49:46.208159 <30>[ 16.275136] systemd[1]: Listening on Network Service Netlink Socket.
10798 11:49:46.218012 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10799 11:49:46.232854 <30>[ 16.299685] systemd[1]: Listening on udev Control Socket.
10800 11:49:46.239508 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10801 11:49:46.256248 <30>[ 16.323491] systemd[1]: Listening on udev Kernel Socket.
10802 11:49:46.263183 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10803 11:49:46.315734 <30>[ 16.382683] systemd[1]: Mounting Huge Pages File System...
10804 11:49:46.322350 Mounting [0;1;39mHuge Pages File System[0m...
10805 11:49:46.339357 <30>[ 16.406460] systemd[1]: Mounting POSIX Message Queue File System...
10806 11:49:46.346110 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10807 11:49:46.366661 <30>[ 16.433953] systemd[1]: Mounting Kernel Debug File System...
10808 11:49:46.373343 Mounting [0;1;39mKernel Debug File System[0m...
10809 11:49:46.390884 <30>[ 16.454661] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10810 11:49:46.403846 <30>[ 16.467741] systemd[1]: Starting Create list of static device nodes for the current kernel...
10811 11:49:46.410360 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10812 11:49:46.431599 <30>[ 16.498378] systemd[1]: Starting Load Kernel Module configfs...
10813 11:49:46.437828 Starting [0;1;39mLoad Kernel Module configfs[0m...
10814 11:49:46.455338 <30>[ 16.522237] systemd[1]: Starting Load Kernel Module drm...
10815 11:49:46.461627 Starting [0;1;39mLoad Kernel Module drm[0m...
10816 11:49:46.478539 <30>[ 16.542542] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10817 11:49:46.493260 <30>[ 16.560252] systemd[1]: Starting Journal Service...
10818 11:49:46.496524 Starting [0;1;39mJournal Service[0m...
10819 11:49:46.514116 <30>[ 16.581226] systemd[1]: Starting Load Kernel Modules...
10820 11:49:46.520565 Starting [0;1;39mLoad Kernel Modules[0m...
10821 11:49:46.541857 <30>[ 16.605302] systemd[1]: Starting Remount Root and Kernel File Systems...
10822 11:49:46.548052 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10823 11:49:46.566723 <30>[ 16.633687] systemd[1]: Starting Coldplug All udev Devices...
10824 11:49:46.572978 Starting [0;1;39mColdplug All udev Devices[0m...
10825 11:49:46.590509 <30>[ 16.657551] systemd[1]: Started Journal Service.
10826 11:49:46.597050 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10827 11:49:46.614056 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10828 11:49:46.632330 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10829 11:49:46.648815 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10830 11:49:46.668535 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10831 11:49:46.686831 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10832 11:49:46.704738 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10833 11:49:46.721365 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10834 11:49:46.741849 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10835 11:49:46.755470 See 'systemctl status systemd-remount-fs.service' for details.
10836 11:49:46.800837 Mounting [0;1;39mKernel Configuration File System[0m...
10837 11:49:46.817937 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10838 11:49:46.831616 <46>[ 16.895217] systemd-journald[182]: Received client request to flush runtime journal.
10839 11:49:46.840664 Starting [0;1;39mLoad/Save Random Seed[0m...
10840 11:49:46.859099 Starting [0;1;39mApply Kernel Variables[0m...
10841 11:49:46.878830 Starting [0;1;39mCreate System Users[0m...
10842 11:49:46.899809 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10843 11:49:46.916358 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10844 11:49:46.936449 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10845 11:49:46.949027 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10846 11:49:46.965056 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10847 11:49:46.980917 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10848 11:49:47.024056 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10849 11:49:47.043970 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10850 11:49:47.055935 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10851 11:49:47.071409 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10852 11:49:47.132139 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10853 11:49:47.156916 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10854 11:49:47.180266 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10855 11:49:47.201372 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10856 11:49:47.252163 Starting [0;1;39mNetwork Service[0m...
10857 11:49:47.273505 Starting [0;1;39mNetwork Time Synchronization[0m...
10858 11:49:47.293206 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10859 11:49:47.336171 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10860 11:49:47.361311 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10861 11:49:47.378341 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10862 11:49:47.399431 <4>[ 17.463409] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10863 11:49:47.406368 [[0;32m OK [<6>[ 17.472045] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10864 11:49:47.416220 0m] Found device<4>[ 17.475989] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10865 11:49:47.426113 [0;1;39m/dev/t<6>[ 17.480020] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10866 11:49:47.426196 tyS0[0m.
10867 11:49:47.436101 <6>[ 17.489215] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10868 11:49:47.442367 <6>[ 17.498691] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10869 11:49:47.452513 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10870 11:49:47.461709 <6>[ 17.528893] remoteproc remoteproc0: scp is available
10871 11:49:47.468465 <3>[ 17.529140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 11:49:47.475225 <6>[ 17.534263] remoteproc remoteproc0: powering up scp
10873 11:49:47.481807 <3>[ 17.542303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 11:49:47.491886 <3>[ 17.542319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 11:49:47.498608 <3>[ 17.557817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 11:49:47.508627 <6>[ 17.563822] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10877 11:49:47.515443 <3>[ 17.572190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 11:49:47.521550 <6>[ 17.580309] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10879 11:49:47.531280 <3>[ 17.588574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 11:49:47.538117 <3>[ 17.602308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 11:49:47.544598 <3>[ 17.610409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 11:49:47.561568 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<3>[ 17.623926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 11:49:47.561674
10884 11:49:47.564388 <6>[ 17.627469] mc: Linux media interface: v0.10
10885 11:49:47.574659 <6>[ 17.627594] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10886 11:49:47.581060 <6>[ 17.630283] usbcore: registered new interface driver r8152
10887 11:49:47.588180 <6>[ 17.633377] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10888 11:49:47.594511 <3>[ 17.638343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 11:49:47.601569 <6>[ 17.646194] pci_bus 0000:00: root bus resource [bus 00-ff]
10890 11:49:47.607998 <6>[ 17.646203] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10891 11:49:47.617678 <6>[ 17.646206] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10892 11:49:47.624295 <6>[ 17.646262] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10893 11:49:47.631179 <6>[ 17.646280] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10894 11:49:47.634585 <6>[ 17.646354] pci 0000:00:00.0: supports D1 D2
10895 11:49:47.644437 <3>[ 17.652081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 11:49:47.650984 <6>[ 17.659023] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10897 11:49:47.657609 <6>[ 17.661838] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10898 11:49:47.668045 <3>[ 17.667008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 11:49:47.674824 <3>[ 17.667186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 11:49:47.681732 <6>[ 17.674443] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10901 11:49:47.688544 <6>[ 17.674442] videodev: Linux video capture interface: v2.00
10902 11:49:47.698823 <6>[ 17.675490] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10903 11:49:47.708569 <6>[ 17.675785] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10904 11:49:47.715390 <3>[ 17.680699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 11:49:47.721735 <6>[ 17.690162] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10906 11:49:47.732168 <3>[ 17.696276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 11:49:47.738428 <6>[ 17.703920] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10908 11:49:47.745295 <3>[ 17.708264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 11:49:47.756250 <6>[ 17.714730] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10910 11:49:47.759172 <6>[ 17.714739] remoteproc remoteproc0: remote processor scp is now up
10911 11:49:47.769151 <6>[ 17.714741] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10912 11:49:47.775861 <6>[ 17.716351] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10913 11:49:47.782788 <6>[ 17.717762] usbcore: registered new interface driver cdc_ether
10914 11:49:47.789510 <4>[ 17.718738] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10915 11:49:47.796822 <4>[ 17.718738] Fallback method does not support PEC.
10916 11:49:47.803464 <3>[ 17.723198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 11:49:47.810442 <6>[ 17.730874] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10918 11:49:47.816469 <6>[ 17.738791] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10919 11:49:47.826834 <3>[ 17.739046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 11:49:47.830840 <6>[ 17.739599] usbcore: registered new interface driver r8153_ecm
10921 11:49:47.841472 <3>[ 17.745620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:49:47.844998 <6>[ 17.747130] pci 0000:01:00.0: supports D1 D2
10923 11:49:47.855630 <4>[ 17.764815] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10924 11:49:47.862594 <3>[ 17.769881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:49:47.869233 <6>[ 17.771093] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10926 11:49:47.872304 <6>[ 17.791748] Bluetooth: Core ver 2.22
10927 11:49:47.882475 <4>[ 17.795189] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10928 11:49:47.889704 <6>[ 17.801324] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10929 11:49:47.896938 <6>[ 17.803757] NET: Registered PF_BLUETOOTH protocol family
10930 11:49:47.906328 <6>[ 17.809068] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10931 11:49:47.913310 <6>[ 17.809220] usbcore: registered new interface driver uvcvideo
10932 11:49:47.920235 <6>[ 17.810287] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10933 11:49:47.927134 <6>[ 17.818194] Bluetooth: HCI device and connection manager initialized
10934 11:49:47.934516 <6>[ 17.826935] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10935 11:49:47.944397 <3>[ 17.828390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:49:47.951128 <6>[ 17.829962] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10937 11:49:47.954283 <6>[ 17.833218] Bluetooth: HCI socket layer initialized
10938 11:49:47.964052 <6>[ 17.840193] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10939 11:49:47.967317 <6>[ 17.848544] Bluetooth: L2CAP socket layer initialized
10940 11:49:47.977459 <6>[ 17.853804] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10941 11:49:47.984013 <6>[ 17.853821] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10942 11:49:47.994249 <6>[ 17.853836] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10943 11:49:48.000374 <6>[ 17.856629] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10944 11:49:48.010346 <6>[ 17.858806] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10945 11:49:48.013977 <6>[ 17.868160] Bluetooth: SCO socket layer initialized
10946 11:49:48.023858 <3>[ 17.872549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:49:48.027197 <6>[ 17.875573] pci 0000:00:00.0: PCI bridge to [bus 01]
10948 11:49:48.036727 <3>[ 17.913972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 11:49:48.046725 <3>[ 17.914839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10950 11:49:48.053646 <6>[ 17.917702] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10951 11:49:48.063492 <3>[ 17.929197] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:49:48.070449 <6>[ 17.935914] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10953 11:49:48.073365 <6>[ 17.936333] usbcore: registered new interface driver btusb
10954 11:49:48.083721 <4>[ 17.943089] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10955 11:49:48.090373 <6>[ 17.947489] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10956 11:49:48.096781 <3>[ 17.954427] Bluetooth: hci0: Failed to load firmware file (-2)
10957 11:49:48.103367 <6>[ 17.961683] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10958 11:49:48.113655 <3>[ 17.964622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:49:48.116985 <3>[ 17.967036] Bluetooth: hci0: Failed to set up firmware (-2)
10960 11:49:48.123816 <6>[ 17.979478] r8152 2-1.3:1.0 eth0: v1.12.13
10961 11:49:48.130645 <3>[ 17.985292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:49:48.140521 <4>[ 17.985488] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10963 11:49:48.146946 <6>[ 17.998404] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10964 11:49:48.157038 <3>[ 18.006914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:49:48.163688 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10966 11:49:48.185597 <5>[ 18.248898] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10967 11:49:48.201731 <5>[ 18.268177] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10968 11:49:48.212285 <4>[ 18.275203] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10969 11:49:48.218652 <6>[ 18.284152] cfg80211: failed to load regulatory.db
10970 11:49:48.225361 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10971 11:49:48.252164 Starting [0;1;39mNetwork Name Resolution[0m...
10972 11:49:48.272142 <6>[ 18.335567] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10973 11:49:48.279116 <6>[ 18.343097] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10974 11:49:48.285314 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10975 11:49:48.303412 <6>[ 18.370270] mt7921e 0000:01:00.0: ASIC revision: 79610010
10976 11:49:48.323230 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10977 11:49:48.410203 <4>[ 18.470193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 11:49:48.461317 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10979 11:49:48.475713 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10980 11:49:48.495852 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10981 11:49:48.507956 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10982 11:49:48.535476 [[0;32m OK [0m] Started [0;1;39mDiscard unu<4>[ 18.595408] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 11:49:48.538785 sed blocks once a week[0m.
10984 11:49:48.557008 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10985 11:49:48.572243 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10986 11:49:48.595698 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10987 11:49:48.611924 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10988 11:49:48.628305 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10989 11:49:48.655633 [[0;32m OK [0m] Listening on [0;1;39mLoad/S<4>[ 18.715526] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 11:49:48.658969 ave RF …itch Status /dev/rfkill Watch[0m.
10991 11:49:48.733244 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10992 11:49:48.779520 <4>[ 18.839498] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 11:49:48.813135 Starting [0;1;39mUser Login Management[0m...
10994 11:49:48.832844 Starting [0;1;39mPermit User Sessions[0m...
10995 11:49:48.853431 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10996 11:49:48.870017 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10997 11:49:48.887667 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10998 11:49:48.900999 <4>[ 18.960687] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 11:49:48.909748 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11000 11:49:48.961753 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11001 11:49:48.979056 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11002 11:49:48.996337 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11003 11:49:49.019964 [[0;32m OK [<4>[ 19.080649] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11004 11:49:49.026576 0m] Reached target [0;1;39mMulti-User System[0m.
11005 11:49:49.041628 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11006 11:49:49.098117 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11007 11:49:49.145914 [[0;32m OK [0m] Finished [0<4>[ 19.204060] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 11:49:49.148765 ;1;39mUpdate UTMP about System Runlevel Changes[0m.
11009 11:49:49.184401
11010 11:49:49.184969
11011 11:49:49.187715 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11012 11:49:49.188177
11013 11:49:49.190964 debian-bullseye-arm64 login: root (automatic login)
11014 11:49:49.191462
11015 11:49:49.191940
11016 11:49:49.209309 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11017 11:49:49.209881
11018 11:49:49.215614 The programs included with the Debian GNU/Linux system are free software;
11019 11:49:49.222550 the exact distribution terms for each program are described in the
11020 11:49:49.225837 individual files in /usr/share/doc/*/copyright.
11021 11:49:49.226390
11022 11:49:49.231843 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11023 11:49:49.235410 permitted by applicable law.
11024 11:49:49.236927 Matched prompt #10: / #
11026 11:49:49.238025 Setting prompt string to ['/ #']
11027 11:49:49.238487 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11029 11:49:49.239596 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11030 11:49:49.240190 start: 2.2.6 expect-shell-connection (timeout 00:03:02) [common]
11031 11:49:49.240587 Setting prompt string to ['/ #']
11032 11:49:49.240930 Forcing a shell prompt, looking for ['/ #']
11034 11:49:49.291785 / #
11035 11:49:49.292418 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11036 11:49:49.292965 Waiting using forced prompt support (timeout 00:02:30)
11037 11:49:49.293483 <4>[ 19.326808] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11038 11:49:49.298436
11039 11:49:49.299389 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 11:49:49.299911 start: 2.2.7 export-device-env (timeout 00:03:02) [common]
11041 11:49:49.300451 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11042 11:49:49.300919 end: 2.2 depthcharge-retry (duration 00:01:58) [common]
11043 11:49:49.301381 end: 2 depthcharge-action (duration 00:01:58) [common]
11044 11:49:49.301859 start: 3 lava-test-retry (timeout 00:07:42) [common]
11045 11:49:49.302344 start: 3.1 lava-test-shell (timeout 00:07:42) [common]
11046 11:49:49.302775 Using namespace: common
11048 11:49:49.404169 / # #
11049 11:49:49.404810 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11050 11:49:49.405523 #<4>[ 19.447049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11051 11:49:49.410473
11052 11:49:49.411396 Using /lava-12074050
11054 11:49:49.512807 / # export SHELL=/bin/sh
11055 11:49:49.513587 export SHELL=/bin/sh<4>[ 19.567016] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11056 11:49:49.519593
11058 11:49:49.621424 / # . /lava-12074050/environment
11059 11:49:49.622217 <6>[ 19.602778] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11060 11:49:49.622678 <6>[ 19.610832] r8152 2-1.3:1.0 enx002432307852: carrier on
11061 11:49:49.623162 . /lava-12074050/environment<3>[ 19.684543] mt7921e 0000:01:00.0: hardware init failed
11062 11:49:49.663502
11064 11:49:49.765379 / # /lava-12074050/bin/lava-test-runner /lava-12074050/0
11065 11:49:49.766037 Test shell timeout: 10s (minimum of the action and connection timeout)
11066 11:49:49.772210 /lava-12074050/bin/lava-test-runner /lava-12074050/0
11067 11:49:49.796118 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11068 11:49:49.802987 + cd /lava-12074050/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11069 11:49:49.803557 + cat uuid
11070 11:49:49.805647 + UUID=12074050_1.5.2.3.1
11071 11:49:49.806207 + set +x
11072 11:49:49.812510 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12074050_1.5.2.3.1>
11073 11:49:49.813360 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12074050_1.5.2.3.1
11074 11:49:49.813759 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12074050_1.5.2.3.1)
11075 11:49:49.814208 Skipping test definition patterns.
11076 11:49:49.816216 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11077 11:49:49.822526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11078 11:49:49.823124 device: /dev/video2
11079 11:49:49.823768 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11081 11:49:49.832907 <4>[ 19.894657] use of bytesused == 0 is deprecated and will be removed in the future,
11082 11:49:49.835814 <4>[ 19.902973] use the actual size instead.
11083 11:49:49.849913 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11084 11:49:49.861502 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11085 11:49:49.867802
11086 11:49:49.882997 Compliance test for mtk-vcodec-enc device /dev/video2:
11087 11:49:49.890142
11088 11:49:49.900829 Driver Info:
11089 11:49:49.911782 Driver name : mtk-vcodec-enc
11090 11:49:49.925465 Card type : MT8192 video encoder
11091 11:49:49.941203 Bus info : platform:17020000.vcodec
11092 11:49:49.947947 Driver version : 6.1.62
11093 11:49:49.963139 Capabilities : 0x84204000
11094 11:49:49.975221 Video Memory-to-Memory Multiplanar
11095 11:49:49.987082 Streaming
11096 11:49:49.998822 Extended Pix Format
11097 11:49:50.013420 Device Capabilities
11098 11:49:50.025976 Device Caps : 0x04204000
11099 11:49:50.039134 Video Memory-to-Memory Multiplanar
11100 11:49:50.053289 Streaming
11101 11:49:50.065247 Extended Pix Format
11102 11:49:50.081219 Detected Stateful Encoder
11103 11:49:50.092025
11104 11:49:50.108344 Required ioctls:
11105 11:49:50.123755 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11106 11:49:50.124337 test VIDIOC_QUERYCAP: OK
11107 11:49:50.125140 Received signal: <TESTSET> START Required-ioctls
11108 11:49:50.125690 Starting test_set Required-ioctls
11109 11:49:50.149156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11110 11:49:50.149852 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11112 11:49:50.152766 test invalid ioctls: OK
11113 11:49:50.175778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11114 11:49:50.176351
11115 11:49:50.177057 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11117 11:49:50.188029 Allow for multiple opens:
11118 11:49:50.194754 <LAVA_SIGNAL_TESTSET STOP>
11119 11:49:50.195538 Received signal: <TESTSET> STOP
11120 11:49:50.195892 Closing test_set Required-ioctls
11121 11:49:50.205334 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11122 11:49:50.206115 Received signal: <TESTSET> START Allow-for-multiple-opens
11123 11:49:50.206474 Starting test_set Allow-for-multiple-opens
11124 11:49:50.208236 test second /dev/video2 open: OK
11125 11:49:50.229512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11126 11:49:50.230182 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11128 11:49:50.232338 test VIDIOC_QUERYCAP: OK
11129 11:49:50.255033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11130 11:49:50.255840 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11132 11:49:50.258248 test VIDIOC_G/S_PRIORITY: OK
11133 11:49:50.284539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11134 11:49:50.285248 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11136 11:49:50.287998 test for unlimited opens: OK
11137 11:49:50.309684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11138 11:49:50.309994
11139 11:49:50.310456 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11141 11:49:50.318591 Debug ioctls:
11142 11:49:50.326219 <LAVA_SIGNAL_TESTSET STOP>
11143 11:49:50.326471 Received signal: <TESTSET> STOP
11144 11:49:50.326543 Closing test_set Allow-for-multiple-opens
11145 11:49:50.335219 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11146 11:49:50.335471 Received signal: <TESTSET> START Debug-ioctls
11147 11:49:50.335543 Starting test_set Debug-ioctls
11148 11:49:50.338854 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11149 11:49:50.360032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11150 11:49:50.360387 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11152 11:49:50.366941 test VIDIOC_LOG_STATUS: OK (Not Supported)
11153 11:49:50.384340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11154 11:49:50.384561
11155 11:49:50.384897 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11157 11:49:50.395639 Input ioctls:
11158 11:49:50.404095 <LAVA_SIGNAL_TESTSET STOP>
11159 11:49:50.404649 Received signal: <TESTSET> STOP
11160 11:49:50.404919 Closing test_set Debug-ioctls
11161 11:49:50.414547 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11162 11:49:50.415425 Received signal: <TESTSET> START Input-ioctls
11163 11:49:50.415824 Starting test_set Input-ioctls
11164 11:49:50.417827 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11165 11:49:50.443841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11166 11:49:50.444583 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11168 11:49:50.447118 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11169 11:49:50.466688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11170 11:49:50.466973 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11172 11:49:50.473305 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11173 11:49:50.493202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11174 11:49:50.493486 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11176 11:49:50.496795 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11177 11:49:50.519004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11178 11:49:50.519675 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11180 11:49:50.522727 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11181 11:49:50.545248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11182 11:49:50.545935 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11184 11:49:50.548133 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11185 11:49:50.569895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11186 11:49:50.570565 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11188 11:49:50.573223 Inputs: 0 Audio Inputs: 0 Tuners: 0
11189 11:49:50.581069
11190 11:49:50.601858 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11191 11:49:50.624046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11192 11:49:50.624480 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11194 11:49:50.631073 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11195 11:49:50.650392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11196 11:49:50.650824 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11198 11:49:50.657084 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11199 11:49:50.676108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11200 11:49:50.676532 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11202 11:49:50.682820 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11203 11:49:50.702382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11204 11:49:50.702813 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11206 11:49:50.708979 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11207 11:49:50.727741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11208 11:49:50.728167 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11210 11:49:50.731853
11211 11:49:50.750314 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11212 11:49:50.772711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11213 11:49:50.773173 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11215 11:49:50.779697 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11216 11:49:50.805966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11217 11:49:50.806408 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11219 11:49:50.808877 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11220 11:49:50.833176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11221 11:49:50.833616 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11223 11:49:50.836631 test VIDIOC_G/S_EDID: OK (Not Supported)
11224 11:49:50.858098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11225 11:49:50.858328
11226 11:49:50.858767 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11228 11:49:50.869231 Control ioctls:
11229 11:49:50.876500 <LAVA_SIGNAL_TESTSET STOP>
11230 11:49:50.876935 Received signal: <TESTSET> STOP
11231 11:49:50.877134 Closing test_set Input-ioctls
11232 11:49:50.886004 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11233 11:49:50.886439 Received signal: <TESTSET> START Control-ioctls
11234 11:49:50.886640 Starting test_set Control-ioctls
11235 11:49:50.889254 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11236 11:49:50.919261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11237 11:49:50.919519 test VIDIOC_QUERYCTRL: OK
11238 11:49:50.919934 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11240 11:49:50.942076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11241 11:49:50.942507 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11243 11:49:50.945478 test VIDIOC_G/S_CTRL: OK
11244 11:49:50.966202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11245 11:49:50.966993 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11247 11:49:50.969582 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11248 11:49:50.996540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11249 11:49:50.997255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11251 11:49:51.006511 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11252 11:49:51.009734 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11253 11:49:51.034187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11254 11:49:51.034568 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11256 11:49:51.037450 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11257 11:49:51.054793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11258 11:49:51.055195 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11260 11:49:51.057665 Standard Controls: 16 Private Controls: 0
11261 11:49:51.068548
11262 11:49:51.080634 Format ioctls:
11263 11:49:51.087848 <LAVA_SIGNAL_TESTSET STOP>
11264 11:49:51.088226 Received signal: <TESTSET> STOP
11265 11:49:51.088378 Closing test_set Control-ioctls
11266 11:49:51.097551 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11267 11:49:51.097933 Received signal: <TESTSET> START Format-ioctls
11268 11:49:51.098099 Starting test_set Format-ioctls
11269 11:49:51.101197 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11270 11:49:51.125819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11271 11:49:51.126521 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11273 11:49:51.129107 test VIDIOC_G/S_PARM: OK
11274 11:49:51.148819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11275 11:49:51.149255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11277 11:49:51.152260 test VIDIOC_G_FBUF: OK (Not Supported)
11278 11:49:51.173727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11279 11:49:51.174105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11281 11:49:51.176593 test VIDIOC_G_FMT: OK
11282 11:49:51.197778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11283 11:49:51.198221 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11285 11:49:51.200992 test VIDIOC_TRY_FMT: OK
11286 11:49:51.223291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11287 11:49:51.223665 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11289 11:49:51.232885 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11290 11:49:51.233064 test VIDIOC_S_FMT: FAIL
11291 11:49:51.258804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11292 11:49:51.259224 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11294 11:49:51.261595 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11295 11:49:51.299856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11296 11:49:51.300278 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11298 11:49:51.303730 test Cropping: OK
11299 11:49:51.325013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11300 11:49:51.325393 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11302 11:49:51.327847 test Composing: OK (Not Supported)
11303 11:49:51.349802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11304 11:49:51.350181 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11306 11:49:51.352918 test Scaling: OK (Not Supported)
11307 11:49:51.374803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11308 11:49:51.375185
11309 11:49:51.375696 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11311 11:49:51.389748 Codec ioctls:
11312 11:49:51.398029 <LAVA_SIGNAL_TESTSET STOP>
11313 11:49:51.398724 Received signal: <TESTSET> STOP
11314 11:49:51.399175 Closing test_set Format-ioctls
11315 11:49:51.407387 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11316 11:49:51.408071 Received signal: <TESTSET> START Codec-ioctls
11317 11:49:51.408444 Starting test_set Codec-ioctls
11318 11:49:51.410333 test VIDIOC_(TRY_)ENCODER_CMD: OK
11319 11:49:51.434140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11320 11:49:51.434992 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11322 11:49:51.440540 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11323 11:49:51.461146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11324 11:49:51.462095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11326 11:49:51.467396 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11327 11:49:51.484161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11328 11:49:51.484701
11329 11:49:51.485454 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11331 11:49:51.498309 Buffer ioctls:
11332 11:49:51.506539 <LAVA_SIGNAL_TESTSET STOP>
11333 11:49:51.507442 Received signal: <TESTSET> STOP
11334 11:49:51.507840 Closing test_set Codec-ioctls
11335 11:49:51.515967 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11336 11:49:51.516683 Received signal: <TESTSET> START Buffer-ioctls
11337 11:49:51.517065 Starting test_set Buffer-ioctls
11338 11:49:51.519404 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11339 11:49:51.544466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11340 11:49:51.545083 test VIDIOC_EXPBUF: OK
11341 11:49:51.545872 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11343 11:49:51.567904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11344 11:49:51.568488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11346 11:49:51.571455 test Requests: OK (Not Supported)
11347 11:49:51.595263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11348 11:49:51.595699
11349 11:49:51.596335 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11351 11:49:51.605373 Test input 0:
11352 11:49:51.614382
11353 11:49:51.625845 Streaming ioctls:
11354 11:49:51.635208 <LAVA_SIGNAL_TESTSET STOP>
11355 11:49:51.635733 Received signal: <TESTSET> STOP
11356 11:49:51.635983 Closing test_set Buffer-ioctls
11357 11:49:51.645747 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11358 11:49:51.646268 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11359 11:49:51.646520 Starting test_set Streaming-ioctls_Test-input-0
11360 11:49:51.649159 test read/write: OK (Not Supported)
11361 11:49:51.673915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11362 11:49:51.674674 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11364 11:49:51.680577 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11365 11:49:51.692691 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11366 11:49:51.697639 test blocking wait: FAIL
11367 11:49:51.728991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11368 11:49:51.730021 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11370 11:49:51.739021 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11371 11:49:51.741793 test MMAP (select): FAIL
11372 11:49:51.768304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11373 11:49:51.769135 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11375 11:49:51.775041 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11376 11:49:51.778193 test MMAP (epoll): FAIL
11377 11:49:51.806191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11378 11:49:51.807010 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11380 11:49:51.812631 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11381 11:49:51.825461 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11382 11:49:51.829839 test USERPTR (select): FAIL
11383 11:49:51.856162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11384 11:49:51.857001 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11386 11:49:51.862942 test DMABUF: Cannot test, specify --expbuf-device
11387 11:49:51.867020
11388 11:49:51.884647 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11389 11:49:51.889003 <LAVA_TEST_RUNNER EXIT>
11390 11:49:51.889768 ok: lava_test_shell seems to have completed
11391 11:49:51.890190 Marking unfinished test run as failed
11393 11:49:51.895588 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11394 11:49:51.896241 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11395 11:49:51.896721 end: 3 lava-test-retry (duration 00:00:03) [common]
11396 11:49:51.897202 start: 4 finalize (timeout 00:07:40) [common]
11397 11:49:51.897687 start: 4.1 power-off (timeout 00:00:30) [common]
11398 11:49:51.898511 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11399 11:49:52.020566 >> Command sent successfully.
11400 11:49:52.025019 Returned 0 in 0 seconds
11401 11:49:52.126006 end: 4.1 power-off (duration 00:00:00) [common]
11403 11:49:52.127738 start: 4.2 read-feedback (timeout 00:07:39) [common]
11404 11:49:52.129029 Listened to connection for namespace 'common' for up to 1s
11405 11:49:53.129667 Finalising connection for namespace 'common'
11406 11:49:53.130448 Disconnecting from shell: Finalise
11407 11:49:53.130908 / #
11408 11:49:53.231945 end: 4.2 read-feedback (duration 00:00:01) [common]
11409 11:49:53.232684 end: 4 finalize (duration 00:00:01) [common]
11410 11:49:53.233288 Cleaning after the job
11411 11:49:53.233814 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/ramdisk
11412 11:49:53.258828 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/kernel
11413 11:49:53.277670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/dtb
11414 11:49:53.277979 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074050/tftp-deploy-tn_pzva9/modules
11415 11:49:53.288384 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074050
11416 11:49:53.356693 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074050
11417 11:49:53.356869 Job finished correctly