Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 39
- Kernel Warnings: 26
- Boot result: PASS
- Errors: 1
1 11:52:45.273386 lava-dispatcher, installed at version: 2023.10
2 11:52:45.273641 start: 0 validate
3 11:52:45.273777 Start time: 2023-11-23 11:52:45.273769+00:00 (UTC)
4 11:52:45.273907 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:52:45.274041 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:52:45.541910 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:52:45.542083 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:53:00.548307 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:53:00.548623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:53:00.810975 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:53:00.811806 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:53:01.333049 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:53:01.333855 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:53:04.847605 validate duration: 19.57
16 11:53:04.847859 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:53:04.847959 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:53:04.848047 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:53:04.848173 Not decompressing ramdisk as can be used compressed.
20 11:53:04.848256 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 11:53:04.848320 saving as /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/ramdisk/initrd.cpio.gz
22 11:53:04.848384 total size: 4665412 (4 MB)
23 11:53:05.113231 progress 0 % (0 MB)
24 11:53:05.114752 progress 5 % (0 MB)
25 11:53:05.116028 progress 10 % (0 MB)
26 11:53:05.117292 progress 15 % (0 MB)
27 11:53:05.118611 progress 20 % (0 MB)
28 11:53:05.119855 progress 25 % (1 MB)
29 11:53:05.121094 progress 30 % (1 MB)
30 11:53:05.122388 progress 35 % (1 MB)
31 11:53:05.123628 progress 40 % (1 MB)
32 11:53:05.125025 progress 45 % (2 MB)
33 11:53:05.126348 progress 50 % (2 MB)
34 11:53:05.127584 progress 55 % (2 MB)
35 11:53:05.128836 progress 60 % (2 MB)
36 11:53:05.130124 progress 65 % (2 MB)
37 11:53:05.131375 progress 70 % (3 MB)
38 11:53:05.132645 progress 75 % (3 MB)
39 11:53:05.133918 progress 80 % (3 MB)
40 11:53:05.135325 progress 85 % (3 MB)
41 11:53:05.136605 progress 90 % (4 MB)
42 11:53:05.137922 progress 95 % (4 MB)
43 11:53:05.139230 progress 100 % (4 MB)
44 11:53:05.139389 4 MB downloaded in 0.29 s (15.29 MB/s)
45 11:53:05.139546 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:53:05.139791 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:53:05.139877 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:53:05.139961 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:53:05.140103 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:53:05.140172 saving as /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/kernel/Image
52 11:53:05.140233 total size: 49107456 (46 MB)
53 11:53:05.140294 No compression specified
54 11:53:05.141433 progress 0 % (0 MB)
55 11:53:05.154559 progress 5 % (2 MB)
56 11:53:05.167666 progress 10 % (4 MB)
57 11:53:05.180592 progress 15 % (7 MB)
58 11:53:05.193349 progress 20 % (9 MB)
59 11:53:05.206161 progress 25 % (11 MB)
60 11:53:05.219140 progress 30 % (14 MB)
61 11:53:05.232361 progress 35 % (16 MB)
62 11:53:05.245360 progress 40 % (18 MB)
63 11:53:05.258724 progress 45 % (21 MB)
64 11:53:05.272194 progress 50 % (23 MB)
65 11:53:05.285363 progress 55 % (25 MB)
66 11:53:05.298473 progress 60 % (28 MB)
67 11:53:05.312217 progress 65 % (30 MB)
68 11:53:05.326220 progress 70 % (32 MB)
69 11:53:05.339494 progress 75 % (35 MB)
70 11:53:05.353329 progress 80 % (37 MB)
71 11:53:05.366739 progress 85 % (39 MB)
72 11:53:05.379853 progress 90 % (42 MB)
73 11:53:05.392819 progress 95 % (44 MB)
74 11:53:05.405644 progress 100 % (46 MB)
75 11:53:05.405904 46 MB downloaded in 0.27 s (176.28 MB/s)
76 11:53:05.406066 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:53:05.406303 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:53:05.406392 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:53:05.406483 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:53:05.406631 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:53:05.406703 saving as /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/dtb/mt8192-asurada-spherion-r0.dtb
83 11:53:05.406798 total size: 47278 (0 MB)
84 11:53:05.406902 No compression specified
85 11:53:05.408065 progress 69 % (0 MB)
86 11:53:05.408351 progress 100 % (0 MB)
87 11:53:05.408513 0 MB downloaded in 0.00 s (26.32 MB/s)
88 11:53:05.408642 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:53:05.408877 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:53:05.408963 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:53:05.409047 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:53:05.409169 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 11:53:05.409238 saving as /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/nfsrootfs/full.rootfs.tar
95 11:53:05.409300 total size: 125290964 (119 MB)
96 11:53:05.409364 Using unxz to decompress xz
97 11:53:05.413671 progress 0 % (0 MB)
98 11:53:05.750774 progress 5 % (6 MB)
99 11:53:06.092898 progress 10 % (11 MB)
100 11:53:06.440818 progress 15 % (17 MB)
101 11:53:06.634010 progress 20 % (23 MB)
102 11:53:06.817817 progress 25 % (29 MB)
103 11:53:07.188137 progress 30 % (35 MB)
104 11:53:07.563250 progress 35 % (41 MB)
105 11:53:07.960384 progress 40 % (47 MB)
106 11:53:08.353438 progress 45 % (53 MB)
107 11:53:08.754418 progress 50 % (59 MB)
108 11:53:09.114841 progress 55 % (65 MB)
109 11:53:09.490366 progress 60 % (71 MB)
110 11:53:09.846646 progress 65 % (77 MB)
111 11:53:10.240435 progress 70 % (83 MB)
112 11:53:10.642946 progress 75 % (89 MB)
113 11:53:11.080473 progress 80 % (95 MB)
114 11:53:11.509661 progress 85 % (101 MB)
115 11:53:11.804954 progress 90 % (107 MB)
116 11:53:12.162431 progress 95 % (113 MB)
117 11:53:12.560820 progress 100 % (119 MB)
118 11:53:12.566644 119 MB downloaded in 7.16 s (16.69 MB/s)
119 11:53:12.567073 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:53:12.567497 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:53:12.567623 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:53:12.567759 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:53:12.567973 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:53:12.568079 saving as /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/modules/modules.tar
126 11:53:12.568178 total size: 8621364 (8 MB)
127 11:53:12.568278 Using unxz to decompress xz
128 11:53:12.836693 progress 0 % (0 MB)
129 11:53:12.865135 progress 5 % (0 MB)
130 11:53:12.897128 progress 10 % (0 MB)
131 11:53:12.923506 progress 15 % (1 MB)
132 11:53:12.950086 progress 20 % (1 MB)
133 11:53:12.976346 progress 25 % (2 MB)
134 11:53:13.004940 progress 30 % (2 MB)
135 11:53:13.035357 progress 35 % (2 MB)
136 11:53:13.061790 progress 40 % (3 MB)
137 11:53:13.087164 progress 45 % (3 MB)
138 11:53:13.113461 progress 50 % (4 MB)
139 11:53:13.139231 progress 55 % (4 MB)
140 11:53:13.165540 progress 60 % (4 MB)
141 11:53:13.194234 progress 65 % (5 MB)
142 11:53:13.220701 progress 70 % (5 MB)
143 11:53:13.246621 progress 75 % (6 MB)
144 11:53:13.274520 progress 80 % (6 MB)
145 11:53:13.301201 progress 85 % (7 MB)
146 11:53:13.327172 progress 90 % (7 MB)
147 11:53:13.357996 progress 95 % (7 MB)
148 11:53:13.389406 progress 100 % (8 MB)
149 11:53:13.394454 8 MB downloaded in 0.83 s (9.95 MB/s)
150 11:53:13.394760 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:53:13.395049 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:53:13.395145 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:53:13.395243 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:53:15.667782 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq
156 11:53:15.668000 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:53:15.668108 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:53:15.668286 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s
159 11:53:15.668420 makedir: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin
160 11:53:15.668523 makedir: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/tests
161 11:53:15.668623 makedir: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/results
162 11:53:15.668724 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-add-keys
163 11:53:15.668875 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-add-sources
164 11:53:15.669007 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-background-process-start
165 11:53:15.669136 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-background-process-stop
166 11:53:15.669263 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-common-functions
167 11:53:15.669408 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-echo-ipv4
168 11:53:15.669537 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-install-packages
169 11:53:15.670040 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-installed-packages
170 11:53:15.670172 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-os-build
171 11:53:15.670300 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-probe-channel
172 11:53:15.670464 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-probe-ip
173 11:53:15.670685 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-target-ip
174 11:53:15.670849 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-target-mac
175 11:53:15.671011 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-target-storage
176 11:53:15.671159 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-case
177 11:53:15.671292 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-event
178 11:53:15.671422 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-feedback
179 11:53:15.671563 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-raise
180 11:53:15.671689 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-reference
181 11:53:15.671814 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-runner
182 11:53:15.671939 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-set
183 11:53:15.672064 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-test-shell
184 11:53:15.672192 Updating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-install-packages (oe)
185 11:53:15.672347 Updating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/bin/lava-installed-packages (oe)
186 11:53:15.672472 Creating /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/environment
187 11:53:15.672569 LAVA metadata
188 11:53:15.672641 - LAVA_JOB_ID=12066534
189 11:53:15.672704 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:53:15.672818 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 11:53:15.672886 skipped lava-vland-overlay
192 11:53:15.672961 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:53:15.673041 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 11:53:15.673104 skipped lava-multinode-overlay
195 11:53:15.673176 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:53:15.673254 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 11:53:15.673348 Loading test definitions
198 11:53:15.673442 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 11:53:15.673515 Using /lava-12066534 at stage 0
200 11:53:15.673881 uuid=12066534_1.6.2.3.1 testdef=None
201 11:53:15.673987 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:53:15.674072 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 11:53:15.674582 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:53:15.674806 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 11:53:15.675477 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:53:15.675791 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 11:53:15.676413 runner path: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/0/tests/0_dmesg test_uuid 12066534_1.6.2.3.1
210 11:53:15.676573 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:53:15.676798 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 11:53:15.676870 Using /lava-12066534 at stage 1
214 11:53:15.677181 uuid=12066534_1.6.2.3.5 testdef=None
215 11:53:15.677302 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 11:53:15.677386 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 11:53:15.677903 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 11:53:15.678120 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 11:53:15.678765 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 11:53:15.678993 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 11:53:15.679619 runner path: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/1/tests/1_bootrr test_uuid 12066534_1.6.2.3.5
224 11:53:15.679774 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 11:53:15.679977 Creating lava-test-runner.conf files
227 11:53:15.680041 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/0 for stage 0
228 11:53:15.680132 - 0_dmesg
229 11:53:15.680211 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066534/lava-overlay-1zwgvi_s/lava-12066534/1 for stage 1
230 11:53:15.680303 - 1_bootrr
231 11:53:15.680397 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 11:53:15.680482 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 11:53:15.687852 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 11:53:15.688008 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 11:53:15.688104 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 11:53:15.688192 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 11:53:15.688280 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 11:53:15.811377 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 11:53:15.811759 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 11:53:15.811883 extracting modules file /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq
241 11:53:16.040219 extracting modules file /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066534/extract-overlay-ramdisk-uwwm28uo/ramdisk
242 11:53:16.276924 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 11:53:16.277111 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 11:53:16.277217 [common] Applying overlay to NFS
245 11:53:16.277290 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066534/compress-overlay-wa_lm_3n/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq
246 11:53:16.285611 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 11:53:16.285799 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 11:53:16.285893 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 11:53:16.285979 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 11:53:16.286060 Building ramdisk /var/lib/lava/dispatcher/tmp/12066534/extract-overlay-ramdisk-uwwm28uo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066534/extract-overlay-ramdisk-uwwm28uo/ramdisk
251 11:53:16.617554 >> 119398 blocks
252 11:53:18.562872 rename /var/lib/lava/dispatcher/tmp/12066534/extract-overlay-ramdisk-uwwm28uo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/ramdisk/ramdisk.cpio.gz
253 11:53:18.563443 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 11:53:18.563617 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 11:53:18.563771 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 11:53:18.563932 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/kernel/Image'
257 11:53:31.484587 Returned 0 in 12 seconds
258 11:53:31.585283 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/kernel/image.itb
259 11:53:31.940165 output: FIT description: Kernel Image image with one or more FDT blobs
260 11:53:31.940608 output: Created: Thu Nov 23 11:53:31 2023
261 11:53:31.940719 output: Image 0 (kernel-1)
262 11:53:31.940819 output: Description:
263 11:53:31.940915 output: Created: Thu Nov 23 11:53:31 2023
264 11:53:31.941008 output: Type: Kernel Image
265 11:53:31.941098 output: Compression: lzma compressed
266 11:53:31.941187 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
267 11:53:31.941276 output: Architecture: AArch64
268 11:53:31.941366 output: OS: Linux
269 11:53:31.941454 output: Load Address: 0x00000000
270 11:53:31.941546 output: Entry Point: 0x00000000
271 11:53:31.941649 output: Hash algo: crc32
272 11:53:31.941743 output: Hash value: e6d7c86f
273 11:53:31.941836 output: Image 1 (fdt-1)
274 11:53:31.941927 output: Description: mt8192-asurada-spherion-r0
275 11:53:31.942016 output: Created: Thu Nov 23 11:53:31 2023
276 11:53:31.942105 output: Type: Flat Device Tree
277 11:53:31.942193 output: Compression: uncompressed
278 11:53:31.942280 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 11:53:31.942366 output: Architecture: AArch64
280 11:53:31.942454 output: Hash algo: crc32
281 11:53:31.942541 output: Hash value: cc4352de
282 11:53:31.942628 output: Image 2 (ramdisk-1)
283 11:53:31.942716 output: Description: unavailable
284 11:53:31.942803 output: Created: Thu Nov 23 11:53:31 2023
285 11:53:31.942892 output: Type: RAMDisk Image
286 11:53:31.942979 output: Compression: Unknown Compression
287 11:53:31.943067 output: Data Size: 17790036 Bytes = 17373.08 KiB = 16.97 MiB
288 11:53:31.943156 output: Architecture: AArch64
289 11:53:31.943243 output: OS: Linux
290 11:53:31.943324 output: Load Address: unavailable
291 11:53:31.943409 output: Entry Point: unavailable
292 11:53:31.943495 output: Hash algo: crc32
293 11:53:31.943582 output: Hash value: 088d22c2
294 11:53:31.943669 output: Default Configuration: 'conf-1'
295 11:53:31.943756 output: Configuration 0 (conf-1)
296 11:53:31.943844 output: Description: mt8192-asurada-spherion-r0
297 11:53:31.943931 output: Kernel: kernel-1
298 11:53:31.944019 output: Init Ramdisk: ramdisk-1
299 11:53:31.944106 output: FDT: fdt-1
300 11:53:31.944193 output: Loadables: kernel-1
301 11:53:31.944280 output:
302 11:53:31.944568 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 11:53:31.944715 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 11:53:31.944861 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 11:53:31.944999 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 11:53:31.945118 No LXC device requested
307 11:53:31.945237 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 11:53:31.945368 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 11:53:31.945486 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 11:53:31.945599 Checking files for TFTP limit of 4294967296 bytes.
311 11:53:31.946283 end: 1 tftp-deploy (duration 00:00:27) [common]
312 11:53:31.946427 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 11:53:31.946558 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 11:53:31.946738 substitutions:
315 11:53:31.946837 - {DTB}: 12066534/tftp-deploy-01176oom/dtb/mt8192-asurada-spherion-r0.dtb
316 11:53:31.946933 - {INITRD}: 12066534/tftp-deploy-01176oom/ramdisk/ramdisk.cpio.gz
317 11:53:31.947025 - {KERNEL}: 12066534/tftp-deploy-01176oom/kernel/Image
318 11:53:31.947115 - {LAVA_MAC}: None
319 11:53:31.947205 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq
320 11:53:31.947296 - {NFS_SERVER_IP}: 192.168.201.1
321 11:53:31.947385 - {PRESEED_CONFIG}: None
322 11:53:31.947474 - {PRESEED_LOCAL}: None
323 11:53:31.947564 - {RAMDISK}: 12066534/tftp-deploy-01176oom/ramdisk/ramdisk.cpio.gz
324 11:53:31.947654 - {ROOT_PART}: None
325 11:53:31.947743 - {ROOT}: None
326 11:53:31.947832 - {SERVER_IP}: 192.168.201.1
327 11:53:31.947921 - {TEE}: None
328 11:53:31.948007 Parsed boot commands:
329 11:53:31.948090 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 11:53:31.948338 Parsed boot commands: tftpboot 192.168.201.1 12066534/tftp-deploy-01176oom/kernel/image.itb 12066534/tftp-deploy-01176oom/kernel/cmdline
331 11:53:31.948468 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 11:53:31.948597 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 11:53:31.948733 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 11:53:31.948862 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 11:53:31.948970 Not connected, no need to disconnect.
336 11:53:31.949087 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 11:53:31.949215 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 11:53:31.949315 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
339 11:53:31.953969 Setting prompt string to ['lava-test: # ']
340 11:53:31.954429 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 11:53:31.954577 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 11:53:31.954712 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 11:53:31.954845 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 11:53:31.955153 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
345 11:53:37.089008 >> Command sent successfully.
346 11:53:37.091527 Returned 0 in 5 seconds
347 11:53:37.192019 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 11:53:37.192414 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 11:53:37.192551 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 11:53:37.192679 Setting prompt string to 'Starting depthcharge on Spherion...'
352 11:53:37.192781 Changing prompt to 'Starting depthcharge on Spherion...'
353 11:53:37.192854 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 11:53:37.193129 [Enter `^Ec?' for help]
355 11:53:37.367089
356 11:53:37.367272
357 11:53:37.367350 F0: 102B 0000
358 11:53:37.367448
359 11:53:37.367540 F3: 1001 0000 [0200]
360 11:53:37.370608
361 11:53:37.370722 F3: 1001 0000
362 11:53:37.370823
363 11:53:37.370900 F7: 102D 0000
364 11:53:37.370992
365 11:53:37.373643 F1: 0000 0000
366 11:53:37.373764
367 11:53:37.373864 V0: 0000 0000 [0001]
368 11:53:37.373951
369 11:53:37.377402 00: 0007 8000
370 11:53:37.377539
371 11:53:37.377635 01: 0000 0000
372 11:53:37.377702
373 11:53:37.380294 BP: 0C00 0209 [0000]
374 11:53:37.380386
375 11:53:37.380454 G0: 1182 0000
376 11:53:37.380518
377 11:53:37.384236 EC: 0000 0021 [4000]
378 11:53:37.384339
379 11:53:37.384411 S7: 0000 0000 [0000]
380 11:53:37.384474
381 11:53:37.387602 CC: 0000 0000 [0001]
382 11:53:37.387717
383 11:53:37.387817 T0: 0000 0040 [010F]
384 11:53:37.387910
385 11:53:37.388013 Jump to BL
386 11:53:37.388102
387 11:53:37.414909
388 11:53:37.415090
389 11:53:37.415189
390 11:53:37.422411 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 11:53:37.426030 ARM64: Exception handlers installed.
392 11:53:37.429677 ARM64: Testing exception
393 11:53:37.429805 ARM64: Done test exception
394 11:53:37.439700 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 11:53:37.450367 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 11:53:37.456630 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 11:53:37.466725 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 11:53:37.473369 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 11:53:37.480187 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 11:53:37.491582 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 11:53:37.498225 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 11:53:37.516773 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 11:53:37.520637 WDT: Last reset was cold boot
404 11:53:37.523928 SPI1(PAD0) initialized at 2873684 Hz
405 11:53:37.527144 SPI5(PAD0) initialized at 992727 Hz
406 11:53:37.530683 VBOOT: Loading verstage.
407 11:53:37.537447 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 11:53:37.540350 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 11:53:37.543883 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 11:53:37.547279 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:53:37.554800 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 11:53:37.561593 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 11:53:37.571943 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 11:53:37.572101
415 11:53:37.572176
416 11:53:37.582825 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 11:53:37.586412 ARM64: Exception handlers installed.
418 11:53:37.589543 ARM64: Testing exception
419 11:53:37.589676 ARM64: Done test exception
420 11:53:37.595998 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 11:53:37.599398 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:53:37.613101 Probing TPM: . done!
423 11:53:37.613259 TPM ready after 0 ms
424 11:53:37.620324 Connected to device vid:did:rid of 1ae0:0028:00
425 11:53:37.627870 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 11:53:37.685889 Initialized TPM device CR50 revision 0
427 11:53:37.697376 tlcl_send_startup: Startup return code is 0
428 11:53:37.697532 TPM: setup succeeded
429 11:53:37.708742 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 11:53:37.717374 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 11:53:37.729494 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 11:53:37.739786 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 11:53:37.743615 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 11:53:37.747590 in-header: 03 07 00 00 08 00 00 00
435 11:53:37.751062 in-data: aa e4 47 04 13 02 00 00
436 11:53:37.751198 Chrome EC: UHEPI supported
437 11:53:37.758449 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 11:53:37.762321 in-header: 03 95 00 00 08 00 00 00
439 11:53:37.765806 in-data: 18 20 20 08 00 00 00 00
440 11:53:37.765922 Phase 1
441 11:53:37.773559 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 11:53:37.777088 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 11:53:37.784354 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 11:53:37.784525 Recovery requested (1009000e)
445 11:53:37.797297 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 11:53:37.800677 tlcl_extend: response is 0
447 11:53:37.809810 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 11:53:37.815544 tlcl_extend: response is 0
449 11:53:37.822141 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 11:53:37.842019 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 11:53:37.848797 BS: bootblock times (exec / console): total (unknown) / 149 ms
452 11:53:37.848935
453 11:53:37.849036
454 11:53:37.858948 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 11:53:37.862608 ARM64: Exception handlers installed.
456 11:53:37.865760 ARM64: Testing exception
457 11:53:37.865862 ARM64: Done test exception
458 11:53:37.888023 pmic_efuse_setting: Set efuses in 11 msecs
459 11:53:37.890984 pmwrap_interface_init: Select PMIF_VLD_RDY
460 11:53:37.897784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 11:53:37.901122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 11:53:37.905261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 11:53:37.913259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 11:53:37.916613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 11:53:37.920350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 11:53:37.927216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 11:53:37.931229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 11:53:37.934994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 11:53:37.938570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 11:53:37.946096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 11:53:37.949927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 11:53:37.953494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 11:53:37.960957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 11:53:37.964521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 11:53:37.971483 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 11:53:37.975572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 11:53:37.982916 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 11:53:37.986733 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 11:53:37.994435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 11:53:37.997941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 11:53:38.005976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 11:53:38.009431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 11:53:38.017136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 11:53:38.020719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 11:53:38.027707 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 11:53:38.031327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 11:53:38.038753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 11:53:38.042604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 11:53:38.046402 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 11:53:38.053456 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 11:53:38.057540 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 11:53:38.061190 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 11:53:38.068350 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 11:53:38.072069 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 11:53:38.076236 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 11:53:38.083218 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 11:53:38.086874 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 11:53:38.090557 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 11:53:38.094377 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 11:53:38.101710 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 11:53:38.105054 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 11:53:38.109317 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 11:53:38.112706 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 11:53:38.116727 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 11:53:38.120266 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 11:53:38.127357 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 11:53:38.131178 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 11:53:38.134837 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 11:53:38.138634 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 11:53:38.142267 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 11:53:38.149644 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 11:53:38.161034 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 11:53:38.164306 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 11:53:38.171971 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 11:53:38.178894 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 11:53:38.186162 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 11:53:38.190191 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 11:53:38.193688 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 11:53:38.201263 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
520 11:53:38.205158 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 11:53:38.212952 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 11:53:38.216500 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 11:53:38.225727 [RTC]rtc_get_frequency_meter,154: input=15, output=758
524 11:53:38.235149 [RTC]rtc_get_frequency_meter,154: input=23, output=943
525 11:53:38.244414 [RTC]rtc_get_frequency_meter,154: input=19, output=851
526 11:53:38.254270 [RTC]rtc_get_frequency_meter,154: input=17, output=807
527 11:53:38.263872 [RTC]rtc_get_frequency_meter,154: input=16, output=782
528 11:53:38.273162 [RTC]rtc_get_frequency_meter,154: input=16, output=782
529 11:53:38.283173 [RTC]rtc_get_frequency_meter,154: input=17, output=804
530 11:53:38.285733 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 11:53:38.293438 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 11:53:38.297318 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 11:53:38.301052 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 11:53:38.305136 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 11:53:38.308559 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 11:53:38.311990 ADC[4]: Raw value=906942 ID=7
537 11:53:38.315805 ADC[3]: Raw value=213810 ID=1
538 11:53:38.315944 RAM Code: 0x71
539 11:53:38.319890 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 11:53:38.327110 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 11:53:38.334651 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 11:53:38.342299 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 11:53:38.342452 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 11:53:38.346012 in-header: 03 07 00 00 08 00 00 00
545 11:53:38.349602 in-data: aa e4 47 04 13 02 00 00
546 11:53:38.353282 Chrome EC: UHEPI supported
547 11:53:38.360361 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 11:53:38.364267 in-header: 03 95 00 00 08 00 00 00
549 11:53:38.368323 in-data: 18 20 20 08 00 00 00 00
550 11:53:38.371639 MRC: failed to locate region type 0.
551 11:53:38.375277 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 11:53:38.379316 DRAM-K: Running full calibration
553 11:53:38.386412 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:53:38.390005 header.status = 0x0
555 11:53:38.390129 header.version = 0x6 (expected: 0x6)
556 11:53:38.394212 header.size = 0xd00 (expected: 0xd00)
557 11:53:38.397455 header.flags = 0x0
558 11:53:38.404948 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 11:53:38.421809 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 11:53:38.429912 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 11:53:38.430073 dram_init: ddr_geometry: 2
562 11:53:38.433483 [EMI] MDL number = 2
563 11:53:38.433626 [EMI] Get MDL freq = 0
564 11:53:38.436685 dram_init: ddr_type: 0
565 11:53:38.436820 is_discrete_lpddr4: 1
566 11:53:38.440853 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 11:53:38.440982
568 11:53:38.441067
569 11:53:38.444596 [Bian_co] ETT version 0.0.0.1
570 11:53:38.448235 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 11:53:38.448375
572 11:53:38.451917 dramc_set_vcore_voltage set vcore to 650000
573 11:53:38.455402 Read voltage for 800, 4
574 11:53:38.455548 Vio18 = 0
575 11:53:38.459947 Vcore = 650000
576 11:53:38.460114 Vdram = 0
577 11:53:38.460213 Vddq = 0
578 11:53:38.460316 Vmddr = 0
579 11:53:38.463322 dram_init: config_dvfs: 1
580 11:53:38.466930 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 11:53:38.474399 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 11:53:38.478186 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
583 11:53:38.481922 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
584 11:53:38.485867 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
585 11:53:38.489195 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
586 11:53:38.489330 MEM_TYPE=3, freq_sel=18
587 11:53:38.492270 sv_algorithm_assistance_LP4_1600
588 11:53:38.499267 ============ PULL DRAM RESETB DOWN ============
589 11:53:38.502941 ========== PULL DRAM RESETB DOWN end =========
590 11:53:38.505793 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 11:53:38.509423 ===================================
592 11:53:38.513550 LPDDR4 DRAM CONFIGURATION
593 11:53:38.517073 ===================================
594 11:53:38.517211 EX_ROW_EN[0] = 0x0
595 11:53:38.520543 EX_ROW_EN[1] = 0x0
596 11:53:38.520657 LP4Y_EN = 0x0
597 11:53:38.524809 WORK_FSP = 0x0
598 11:53:38.524931 WL = 0x2
599 11:53:38.528150 RL = 0x2
600 11:53:38.528259 BL = 0x2
601 11:53:38.531804 RPST = 0x0
602 11:53:38.531908 RD_PRE = 0x0
603 11:53:38.535168 WR_PRE = 0x1
604 11:53:38.535279 WR_PST = 0x0
605 11:53:38.538153 DBI_WR = 0x0
606 11:53:38.538252 DBI_RD = 0x0
607 11:53:38.541994 OTF = 0x1
608 11:53:38.544817 ===================================
609 11:53:38.548081 ===================================
610 11:53:38.548197 ANA top config
611 11:53:38.552139 ===================================
612 11:53:38.554808 DLL_ASYNC_EN = 0
613 11:53:38.558344 ALL_SLAVE_EN = 1
614 11:53:38.558463 NEW_RANK_MODE = 1
615 11:53:38.561345 DLL_IDLE_MODE = 1
616 11:53:38.564836 LP45_APHY_COMB_EN = 1
617 11:53:38.568635 TX_ODT_DIS = 1
618 11:53:38.568756 NEW_8X_MODE = 1
619 11:53:38.571762 ===================================
620 11:53:38.575261 ===================================
621 11:53:38.578537 data_rate = 1600
622 11:53:38.582256 CKR = 1
623 11:53:38.585251 DQ_P2S_RATIO = 8
624 11:53:38.588443 ===================================
625 11:53:38.591986 CA_P2S_RATIO = 8
626 11:53:38.592105 DQ_CA_OPEN = 0
627 11:53:38.595228 DQ_SEMI_OPEN = 0
628 11:53:38.598775 CA_SEMI_OPEN = 0
629 11:53:38.601759 CA_FULL_RATE = 0
630 11:53:38.605451 DQ_CKDIV4_EN = 1
631 11:53:38.608382 CA_CKDIV4_EN = 1
632 11:53:38.608498 CA_PREDIV_EN = 0
633 11:53:38.611675 PH8_DLY = 0
634 11:53:38.615506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 11:53:38.618642 DQ_AAMCK_DIV = 4
636 11:53:38.621883 CA_AAMCK_DIV = 4
637 11:53:38.625181 CA_ADMCK_DIV = 4
638 11:53:38.625321 DQ_TRACK_CA_EN = 0
639 11:53:38.628887 CA_PICK = 800
640 11:53:38.632194 CA_MCKIO = 800
641 11:53:38.635981 MCKIO_SEMI = 0
642 11:53:38.640060 PLL_FREQ = 3068
643 11:53:38.640205 DQ_UI_PI_RATIO = 32
644 11:53:38.643791 CA_UI_PI_RATIO = 0
645 11:53:38.646662 ===================================
646 11:53:38.650950 ===================================
647 11:53:38.651083 memory_type:LPDDR4
648 11:53:38.654829 GP_NUM : 10
649 11:53:38.658883 SRAM_EN : 1
650 11:53:38.659015 MD32_EN : 0
651 11:53:38.663321 ===================================
652 11:53:38.666231 [ANA_INIT] >>>>>>>>>>>>>>
653 11:53:38.666357 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 11:53:38.669794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 11:53:38.672884 ===================================
656 11:53:38.676359 data_rate = 1600,PCW = 0X7600
657 11:53:38.679709 ===================================
658 11:53:38.682900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 11:53:38.689943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 11:53:38.693114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 11:53:38.699719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 11:53:38.703314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 11:53:38.706405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 11:53:38.706523 [ANA_INIT] flow start
665 11:53:38.709502 [ANA_INIT] PLL >>>>>>>>
666 11:53:38.712950 [ANA_INIT] PLL <<<<<<<<
667 11:53:38.716618 [ANA_INIT] MIDPI >>>>>>>>
668 11:53:38.716753 [ANA_INIT] MIDPI <<<<<<<<
669 11:53:38.719927 [ANA_INIT] DLL >>>>>>>>
670 11:53:38.723276 [ANA_INIT] flow end
671 11:53:38.726420 ============ LP4 DIFF to SE enter ============
672 11:53:38.730251 ============ LP4 DIFF to SE exit ============
673 11:53:38.733043 [ANA_INIT] <<<<<<<<<<<<<
674 11:53:38.736628 [Flow] Enable top DCM control >>>>>
675 11:53:38.739609 [Flow] Enable top DCM control <<<<<
676 11:53:38.742927 Enable DLL master slave shuffle
677 11:53:38.746421 ==============================================================
678 11:53:38.749697 Gating Mode config
679 11:53:38.753402 ==============================================================
680 11:53:38.756555 Config description:
681 11:53:38.766576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 11:53:38.773342 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 11:53:38.776310 SELPH_MODE 0: By rank 1: By Phase
684 11:53:38.783504 ==============================================================
685 11:53:38.786436 GAT_TRACK_EN = 1
686 11:53:38.790028 RX_GATING_MODE = 2
687 11:53:38.793251 RX_GATING_TRACK_MODE = 2
688 11:53:38.796897 SELPH_MODE = 1
689 11:53:38.797019 PICG_EARLY_EN = 1
690 11:53:38.799986 VALID_LAT_VALUE = 1
691 11:53:38.806604 ==============================================================
692 11:53:38.809847 Enter into Gating configuration >>>>
693 11:53:38.812963 Exit from Gating configuration <<<<
694 11:53:38.816421 Enter into DVFS_PRE_config >>>>>
695 11:53:38.826389 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 11:53:38.829898 Exit from DVFS_PRE_config <<<<<
697 11:53:38.833522 Enter into PICG configuration >>>>
698 11:53:38.836632 Exit from PICG configuration <<<<
699 11:53:38.840172 [RX_INPUT] configuration >>>>>
700 11:53:38.843487 [RX_INPUT] configuration <<<<<
701 11:53:38.846830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 11:53:38.853558 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 11:53:38.860292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 11:53:38.867080 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 11:53:38.870244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 11:53:38.876919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 11:53:38.880173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 11:53:38.886541 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 11:53:38.890258 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 11:53:38.893144 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 11:53:38.896565 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 11:53:38.903502 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 11:53:38.906717 ===================================
714 11:53:38.906871 LPDDR4 DRAM CONFIGURATION
715 11:53:38.909968 ===================================
716 11:53:38.913344 EX_ROW_EN[0] = 0x0
717 11:53:38.916996 EX_ROW_EN[1] = 0x0
718 11:53:38.917173 LP4Y_EN = 0x0
719 11:53:38.919872 WORK_FSP = 0x0
720 11:53:38.920015 WL = 0x2
721 11:53:38.923265 RL = 0x2
722 11:53:38.923407 BL = 0x2
723 11:53:38.927048 RPST = 0x0
724 11:53:38.927187 RD_PRE = 0x0
725 11:53:38.930138 WR_PRE = 0x1
726 11:53:38.930269 WR_PST = 0x0
727 11:53:38.933248 DBI_WR = 0x0
728 11:53:38.933378 DBI_RD = 0x0
729 11:53:38.937465 OTF = 0x1
730 11:53:38.940340 ===================================
731 11:53:38.943952 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 11:53:38.946881 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 11:53:38.954115 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 11:53:38.954300 ===================================
735 11:53:38.956966 LPDDR4 DRAM CONFIGURATION
736 11:53:38.960224 ===================================
737 11:53:38.963608 EX_ROW_EN[0] = 0x10
738 11:53:38.963764 EX_ROW_EN[1] = 0x0
739 11:53:38.967059 LP4Y_EN = 0x0
740 11:53:38.967199 WORK_FSP = 0x0
741 11:53:38.971106 WL = 0x2
742 11:53:38.971249 RL = 0x2
743 11:53:38.973848 BL = 0x2
744 11:53:38.973978 RPST = 0x0
745 11:53:38.977131 RD_PRE = 0x0
746 11:53:38.977254 WR_PRE = 0x1
747 11:53:38.980723 WR_PST = 0x0
748 11:53:38.980855 DBI_WR = 0x0
749 11:53:38.984401 DBI_RD = 0x0
750 11:53:38.984535 OTF = 0x1
751 11:53:38.987105 ===================================
752 11:53:38.993689 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 11:53:38.998897 nWR fixed to 40
754 11:53:39.002547 [ModeRegInit_LP4] CH0 RK0
755 11:53:39.002711 [ModeRegInit_LP4] CH0 RK1
756 11:53:39.005838 [ModeRegInit_LP4] CH1 RK0
757 11:53:39.008976 [ModeRegInit_LP4] CH1 RK1
758 11:53:39.009124 match AC timing 13
759 11:53:39.015713 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 11:53:39.019368 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 11:53:39.022366 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 11:53:39.029010 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 11:53:39.032670 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 11:53:39.032841 [EMI DOE] emi_dcm 0
765 11:53:39.039144 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 11:53:39.039334 ==
767 11:53:39.042635 Dram Type= 6, Freq= 0, CH_0, rank 0
768 11:53:39.045594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 11:53:39.045738 ==
770 11:53:39.052960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 11:53:39.056049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 11:53:39.066158 [CA 0] Center 36 (6~67) winsize 62
773 11:53:39.069594 [CA 1] Center 36 (6~67) winsize 62
774 11:53:39.072880 [CA 2] Center 34 (4~65) winsize 62
775 11:53:39.076597 [CA 3] Center 33 (3~64) winsize 62
776 11:53:39.079475 [CA 4] Center 33 (3~64) winsize 62
777 11:53:39.083071 [CA 5] Center 32 (2~62) winsize 61
778 11:53:39.083225
779 11:53:39.086246 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 11:53:39.086374
781 11:53:39.089703 [CATrainingPosCal] consider 1 rank data
782 11:53:39.092825 u2DelayCellTimex100 = 270/100 ps
783 11:53:39.096249 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
784 11:53:39.099411 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
785 11:53:39.106026 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
786 11:53:39.109792 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
787 11:53:39.112786 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
788 11:53:39.116682 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
789 11:53:39.116859
790 11:53:39.120788 CA PerBit enable=1, Macro0, CA PI delay=32
791 11:53:39.120949
792 11:53:39.122961 [CBTSetCACLKResult] CA Dly = 32
793 11:53:39.123080 CS Dly: 4 (0~35)
794 11:53:39.126377 ==
795 11:53:39.126513 Dram Type= 6, Freq= 0, CH_0, rank 1
796 11:53:39.132814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 11:53:39.133000 ==
798 11:53:39.136160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 11:53:39.142628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 11:53:39.152608 [CA 0] Center 36 (6~67) winsize 62
801 11:53:39.155746 [CA 1] Center 36 (6~67) winsize 62
802 11:53:39.159144 [CA 2] Center 34 (3~65) winsize 63
803 11:53:39.162519 [CA 3] Center 34 (4~65) winsize 62
804 11:53:39.166132 [CA 4] Center 32 (2~63) winsize 62
805 11:53:39.169513 [CA 5] Center 32 (2~63) winsize 62
806 11:53:39.169683
807 11:53:39.172760 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 11:53:39.172888
809 11:53:39.175747 [CATrainingPosCal] consider 2 rank data
810 11:53:39.179227 u2DelayCellTimex100 = 270/100 ps
811 11:53:39.182669 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
812 11:53:39.186429 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
813 11:53:39.192853 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
814 11:53:39.195893 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
815 11:53:39.199639 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
816 11:53:39.202645 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
817 11:53:39.202792
818 11:53:39.206216 CA PerBit enable=1, Macro0, CA PI delay=32
819 11:53:39.206361
820 11:53:39.209904 [CBTSetCACLKResult] CA Dly = 32
821 11:53:39.210038 CS Dly: 5 (0~37)
822 11:53:39.210146
823 11:53:39.213278 ----->DramcWriteLeveling(PI) begin...
824 11:53:39.213418 ==
825 11:53:39.217306 Dram Type= 6, Freq= 0, CH_0, rank 0
826 11:53:39.220381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 11:53:39.224451 ==
828 11:53:39.224617 Write leveling (Byte 0): 31 => 31
829 11:53:39.227979 Write leveling (Byte 1): 31 => 31
830 11:53:39.231971 DramcWriteLeveling(PI) end<-----
831 11:53:39.232128
832 11:53:39.232232 ==
833 11:53:39.234841 Dram Type= 6, Freq= 0, CH_0, rank 0
834 11:53:39.238011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 11:53:39.238168 ==
836 11:53:39.241993 [Gating] SW mode calibration
837 11:53:39.248939 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 11:53:39.255541 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 11:53:39.259155 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 11:53:39.262048 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 11:53:39.268738 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 11:53:39.272063 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:53:39.275697 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:53:39.278856 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:53:39.285609 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:53:39.288932 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:53:39.292373 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:53:39.299082 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:53:39.302063 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 11:53:39.305717 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:53:39.312569 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:53:39.315588 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:53:39.318783 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:53:39.326315 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:53:39.329657 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:53:39.332632 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 11:53:39.339125 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 11:53:39.342869 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:53:39.346311 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:53:39.349004 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:53:39.355700 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:53:39.359112 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:53:39.362363 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:53:39.369111 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:53:39.372658 0 9 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
866 11:53:39.376157 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
867 11:53:39.382732 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 11:53:39.385918 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 11:53:39.389443 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 11:53:39.396026 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 11:53:39.399485 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 11:53:39.402715 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
873 11:53:39.409330 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
874 11:53:39.412548 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:53:39.416042 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:53:39.422682 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:53:39.426157 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:53:39.429834 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:53:39.432620 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 11:53:39.439330 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
881 11:53:39.442557 0 11 8 | B1->B0 | 3030 4545 | 1 0 | (1 1) (0 0)
882 11:53:39.446176 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
883 11:53:39.452799 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 11:53:39.455815 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 11:53:39.459427 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 11:53:39.466025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 11:53:39.469353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 11:53:39.472807 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 11:53:39.479757 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
890 11:53:39.482697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 11:53:39.485870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 11:53:39.492776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 11:53:39.495985 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 11:53:39.499484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 11:53:39.506157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 11:53:39.509587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 11:53:39.513092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 11:53:39.516194 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:53:39.523317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:53:39.526379 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:53:39.529601 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:53:39.536256 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:53:39.539827 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:53:39.542943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 11:53:39.549845 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 11:53:39.550051 Total UI for P1: 0, mck2ui 16
907 11:53:39.556584 best dqsien dly found for B0: ( 0, 14, 4)
908 11:53:39.559645 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
909 11:53:39.563173 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 11:53:39.566743 Total UI for P1: 0, mck2ui 16
911 11:53:39.570868 best dqsien dly found for B1: ( 0, 14, 10)
912 11:53:39.573660 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
913 11:53:39.577060 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 11:53:39.577201
915 11:53:39.580595 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
916 11:53:39.583793 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 11:53:39.587199 [Gating] SW calibration Done
918 11:53:39.587354 ==
919 11:53:39.590417 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:53:39.593663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:53:39.597287 ==
922 11:53:39.597430 RX Vref Scan: 0
923 11:53:39.597531
924 11:53:39.600253 RX Vref 0 -> 0, step: 1
925 11:53:39.600370
926 11:53:39.603818 RX Delay -130 -> 252, step: 16
927 11:53:39.607038 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
928 11:53:39.610424 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
929 11:53:39.613850 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
930 11:53:39.616746 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
931 11:53:39.623938 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
932 11:53:39.626640 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
933 11:53:39.630432 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
934 11:53:39.633541 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
935 11:53:39.636957 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
936 11:53:39.643706 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
937 11:53:39.647048 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
938 11:53:39.650389 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
939 11:53:39.653812 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
940 11:53:39.656664 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
941 11:53:39.663746 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
942 11:53:39.667059 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
943 11:53:39.667201 ==
944 11:53:39.669945 Dram Type= 6, Freq= 0, CH_0, rank 0
945 11:53:39.673482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 11:53:39.673633 ==
947 11:53:39.676857 DQS Delay:
948 11:53:39.676976 DQS0 = 0, DQS1 = 0
949 11:53:39.677080 DQM Delay:
950 11:53:39.680189 DQM0 = 91, DQM1 = 86
951 11:53:39.680312 DQ Delay:
952 11:53:39.683368 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
953 11:53:39.687141 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
954 11:53:39.690868 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
955 11:53:39.693720 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
956 11:53:39.693855
957 11:53:39.693949
958 11:53:39.694032 ==
959 11:53:39.696836 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:53:39.700626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:53:39.703989 ==
962 11:53:39.704126
963 11:53:39.704231
964 11:53:39.704334 TX Vref Scan disable
965 11:53:39.706964 == TX Byte 0 ==
966 11:53:39.710055 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
967 11:53:39.713845 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
968 11:53:39.717524 == TX Byte 1 ==
969 11:53:39.720516 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
970 11:53:39.723604 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
971 11:53:39.726909 ==
972 11:53:39.727052 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:53:39.733896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:53:39.734069 ==
975 11:53:39.745815 TX Vref=22, minBit 5, minWin=27, winSum=447
976 11:53:39.748920 TX Vref=24, minBit 8, minWin=27, winSum=449
977 11:53:39.752608 TX Vref=26, minBit 9, minWin=27, winSum=449
978 11:53:39.755642 TX Vref=28, minBit 0, minWin=28, winSum=457
979 11:53:39.759422 TX Vref=30, minBit 2, minWin=28, winSum=457
980 11:53:39.762854 TX Vref=32, minBit 10, minWin=27, winSum=453
981 11:53:39.769159 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
982 11:53:39.769344
983 11:53:39.772415 Final TX Range 1 Vref 28
984 11:53:39.772547
985 11:53:39.772658 ==
986 11:53:39.776078 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:53:39.779171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:53:39.779310 ==
989 11:53:39.779421
990 11:53:39.779516
991 11:53:39.783146 TX Vref Scan disable
992 11:53:39.786167 == TX Byte 0 ==
993 11:53:39.789516 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
994 11:53:39.792396 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
995 11:53:39.796009 == TX Byte 1 ==
996 11:53:39.799622 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
997 11:53:39.802818 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
998 11:53:39.802972
999 11:53:39.805908 [DATLAT]
1000 11:53:39.806040 Freq=800, CH0 RK0
1001 11:53:39.806149
1002 11:53:39.809586 DATLAT Default: 0xa
1003 11:53:39.809714 0, 0xFFFF, sum = 0
1004 11:53:39.812523 1, 0xFFFF, sum = 0
1005 11:53:39.812661 2, 0xFFFF, sum = 0
1006 11:53:39.816348 3, 0xFFFF, sum = 0
1007 11:53:39.816486 4, 0xFFFF, sum = 0
1008 11:53:39.819326 5, 0xFFFF, sum = 0
1009 11:53:39.819475 6, 0xFFFF, sum = 0
1010 11:53:39.822659 7, 0xFFFF, sum = 0
1011 11:53:39.822798 8, 0xFFFF, sum = 0
1012 11:53:39.826014 9, 0x0, sum = 1
1013 11:53:39.826149 10, 0x0, sum = 2
1014 11:53:39.829633 11, 0x0, sum = 3
1015 11:53:39.829773 12, 0x0, sum = 4
1016 11:53:39.832665 best_step = 10
1017 11:53:39.832786
1018 11:53:39.832893 ==
1019 11:53:39.836089 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 11:53:39.839371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 11:53:39.839518 ==
1022 11:53:39.843285 RX Vref Scan: 1
1023 11:53:39.843431
1024 11:53:39.843532 Set Vref Range= 32 -> 127
1025 11:53:39.843643
1026 11:53:39.846608 RX Vref 32 -> 127, step: 1
1027 11:53:39.846724
1028 11:53:39.849745 RX Delay -79 -> 252, step: 8
1029 11:53:39.849880
1030 11:53:39.852821 Set Vref, RX VrefLevel [Byte0]: 32
1031 11:53:39.856592 [Byte1]: 32
1032 11:53:39.856745
1033 11:53:39.859398 Set Vref, RX VrefLevel [Byte0]: 33
1034 11:53:39.862695 [Byte1]: 33
1035 11:53:39.862848
1036 11:53:39.866489 Set Vref, RX VrefLevel [Byte0]: 34
1037 11:53:39.869525 [Byte1]: 34
1038 11:53:39.873423
1039 11:53:39.873583 Set Vref, RX VrefLevel [Byte0]: 35
1040 11:53:39.876961 [Byte1]: 35
1041 11:53:39.881704
1042 11:53:39.881872 Set Vref, RX VrefLevel [Byte0]: 36
1043 11:53:39.884636 [Byte1]: 36
1044 11:53:39.888793
1045 11:53:39.888954 Set Vref, RX VrefLevel [Byte0]: 37
1046 11:53:39.892466 [Byte1]: 37
1047 11:53:39.896634
1048 11:53:39.896806 Set Vref, RX VrefLevel [Byte0]: 38
1049 11:53:39.900434 [Byte1]: 38
1050 11:53:39.904129
1051 11:53:39.904300 Set Vref, RX VrefLevel [Byte0]: 39
1052 11:53:39.907597 [Byte1]: 39
1053 11:53:39.912158
1054 11:53:39.912331 Set Vref, RX VrefLevel [Byte0]: 40
1055 11:53:39.915267 [Byte1]: 40
1056 11:53:39.918854
1057 11:53:39.919016 Set Vref, RX VrefLevel [Byte0]: 41
1058 11:53:39.922087 [Byte1]: 41
1059 11:53:39.926424
1060 11:53:39.926574 Set Vref, RX VrefLevel [Byte0]: 42
1061 11:53:39.929434 [Byte1]: 42
1062 11:53:39.933727
1063 11:53:39.933883 Set Vref, RX VrefLevel [Byte0]: 43
1064 11:53:39.937379 [Byte1]: 43
1065 11:53:39.941616
1066 11:53:39.941778 Set Vref, RX VrefLevel [Byte0]: 44
1067 11:53:39.944635 [Byte1]: 44
1068 11:53:39.948876
1069 11:53:39.949024 Set Vref, RX VrefLevel [Byte0]: 45
1070 11:53:39.952631 [Byte1]: 45
1071 11:53:39.956397
1072 11:53:39.956547 Set Vref, RX VrefLevel [Byte0]: 46
1073 11:53:39.959808 [Byte1]: 46
1074 11:53:39.964310
1075 11:53:39.964472 Set Vref, RX VrefLevel [Byte0]: 47
1076 11:53:39.967450 [Byte1]: 47
1077 11:53:39.971434
1078 11:53:39.971606 Set Vref, RX VrefLevel [Byte0]: 48
1079 11:53:39.974598 [Byte1]: 48
1080 11:53:39.979000
1081 11:53:39.979166 Set Vref, RX VrefLevel [Byte0]: 49
1082 11:53:39.982271 [Byte1]: 49
1083 11:53:39.986587
1084 11:53:39.986713 Set Vref, RX VrefLevel [Byte0]: 50
1085 11:53:39.990236 [Byte1]: 50
1086 11:53:39.994413
1087 11:53:39.994527 Set Vref, RX VrefLevel [Byte0]: 51
1088 11:53:39.997325 [Byte1]: 51
1089 11:53:40.002256
1090 11:53:40.002413 Set Vref, RX VrefLevel [Byte0]: 52
1091 11:53:40.005184 [Byte1]: 52
1092 11:53:40.009247
1093 11:53:40.009405 Set Vref, RX VrefLevel [Byte0]: 53
1094 11:53:40.012758 [Byte1]: 53
1095 11:53:40.016802
1096 11:53:40.016963 Set Vref, RX VrefLevel [Byte0]: 54
1097 11:53:40.020183 [Byte1]: 54
1098 11:53:40.024306
1099 11:53:40.024468 Set Vref, RX VrefLevel [Byte0]: 55
1100 11:53:40.027934 [Byte1]: 55
1101 11:53:40.032259
1102 11:53:40.032416 Set Vref, RX VrefLevel [Byte0]: 56
1103 11:53:40.035321 [Byte1]: 56
1104 11:53:40.039643
1105 11:53:40.039799 Set Vref, RX VrefLevel [Byte0]: 57
1106 11:53:40.042905 [Byte1]: 57
1107 11:53:40.047080
1108 11:53:40.047236 Set Vref, RX VrefLevel [Byte0]: 58
1109 11:53:40.050100 [Byte1]: 58
1110 11:53:40.054505
1111 11:53:40.054651 Set Vref, RX VrefLevel [Byte0]: 59
1112 11:53:40.058146 [Byte1]: 59
1113 11:53:40.062205
1114 11:53:40.062362 Set Vref, RX VrefLevel [Byte0]: 60
1115 11:53:40.065274 [Byte1]: 60
1116 11:53:40.069704
1117 11:53:40.069828 Set Vref, RX VrefLevel [Byte0]: 61
1118 11:53:40.073335 [Byte1]: 61
1119 11:53:40.077235
1120 11:53:40.077384 Set Vref, RX VrefLevel [Byte0]: 62
1121 11:53:40.080654 [Byte1]: 62
1122 11:53:40.084759
1123 11:53:40.084879 Set Vref, RX VrefLevel [Byte0]: 63
1124 11:53:40.088090 [Byte1]: 63
1125 11:53:40.092511
1126 11:53:40.092637 Set Vref, RX VrefLevel [Byte0]: 64
1127 11:53:40.096001 [Byte1]: 64
1128 11:53:40.099704
1129 11:53:40.099819 Set Vref, RX VrefLevel [Byte0]: 65
1130 11:53:40.103663 [Byte1]: 65
1131 11:53:40.107268
1132 11:53:40.107386 Set Vref, RX VrefLevel [Byte0]: 66
1133 11:53:40.110846 [Byte1]: 66
1134 11:53:40.114930
1135 11:53:40.115092 Set Vref, RX VrefLevel [Byte0]: 67
1136 11:53:40.118303 [Byte1]: 67
1137 11:53:40.122606
1138 11:53:40.122779 Set Vref, RX VrefLevel [Byte0]: 68
1139 11:53:40.126032 [Byte1]: 68
1140 11:53:40.129804
1141 11:53:40.129970 Set Vref, RX VrefLevel [Byte0]: 69
1142 11:53:40.133367 [Byte1]: 69
1143 11:53:40.137793
1144 11:53:40.137952 Set Vref, RX VrefLevel [Byte0]: 70
1145 11:53:40.140800 [Byte1]: 70
1146 11:53:40.145434
1147 11:53:40.145612 Set Vref, RX VrefLevel [Byte0]: 71
1148 11:53:40.148509 [Byte1]: 71
1149 11:53:40.152798
1150 11:53:40.152949 Set Vref, RX VrefLevel [Byte0]: 72
1151 11:53:40.156032 [Byte1]: 72
1152 11:53:40.160492
1153 11:53:40.160653 Set Vref, RX VrefLevel [Byte0]: 73
1154 11:53:40.163831 [Byte1]: 73
1155 11:53:40.167802
1156 11:53:40.167952 Set Vref, RX VrefLevel [Byte0]: 74
1157 11:53:40.171384 [Byte1]: 74
1158 11:53:40.175542
1159 11:53:40.175700 Set Vref, RX VrefLevel [Byte0]: 75
1160 11:53:40.178818 [Byte1]: 75
1161 11:53:40.183074
1162 11:53:40.183233 Set Vref, RX VrefLevel [Byte0]: 76
1163 11:53:40.186527 [Byte1]: 76
1164 11:53:40.190830
1165 11:53:40.190994 Set Vref, RX VrefLevel [Byte0]: 77
1166 11:53:40.193649 [Byte1]: 77
1167 11:53:40.197834
1168 11:53:40.197997 Set Vref, RX VrefLevel [Byte0]: 78
1169 11:53:40.201469 [Byte1]: 78
1170 11:53:40.205885
1171 11:53:40.206046 Final RX Vref Byte 0 = 58 to rank0
1172 11:53:40.208995 Final RX Vref Byte 1 = 58 to rank0
1173 11:53:40.212053 Final RX Vref Byte 0 = 58 to rank1
1174 11:53:40.215742 Final RX Vref Byte 1 = 58 to rank1==
1175 11:53:40.218957 Dram Type= 6, Freq= 0, CH_0, rank 0
1176 11:53:40.222408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 11:53:40.225712 ==
1178 11:53:40.225865 DQS Delay:
1179 11:53:40.225966 DQS0 = 0, DQS1 = 0
1180 11:53:40.229372 DQM Delay:
1181 11:53:40.229499 DQM0 = 92, DQM1 = 84
1182 11:53:40.232061 DQ Delay:
1183 11:53:40.235734 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1184 11:53:40.239258 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1185 11:53:40.239410 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1186 11:53:40.242370 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1187 11:53:40.245722
1188 11:53:40.245869
1189 11:53:40.252477 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1190 11:53:40.255763 CH0 RK0: MR19=606, MR18=4C42
1191 11:53:40.262779 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1192 11:53:40.262972
1193 11:53:40.265962 ----->DramcWriteLeveling(PI) begin...
1194 11:53:40.266096 ==
1195 11:53:40.269504 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 11:53:40.272369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 11:53:40.272520 ==
1198 11:53:40.275678 Write leveling (Byte 0): 34 => 34
1199 11:53:40.278756 Write leveling (Byte 1): 30 => 30
1200 11:53:40.282371 DramcWriteLeveling(PI) end<-----
1201 11:53:40.282524
1202 11:53:40.282627 ==
1203 11:53:40.285766 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 11:53:40.330148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 11:53:40.330354 ==
1206 11:53:40.330462 [Gating] SW mode calibration
1207 11:53:40.330762 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1208 11:53:40.330865 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1209 11:53:40.330972 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 11:53:40.331392 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 11:53:40.331699 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1212 11:53:40.331811 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:53:40.331921 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:53:40.332024 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:53:40.373792 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:53:40.374177 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:53:40.374673 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:53:40.374977 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:53:40.375086 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:53:40.375189 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:53:40.375297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:53:40.375416 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:53:40.375525 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:53:40.375619 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:53:40.414684 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:53:40.415079 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1227 11:53:40.415202 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1228 11:53:40.415299 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:53:40.415402 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:53:40.415510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:53:40.415614 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:53:40.415722 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:53:40.418843 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:53:40.418977 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:53:40.422413 0 9 8 | B1->B0 | 2b2b 2525 | 0 1 | (0 0) (1 1)
1236 11:53:40.428889 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 11:53:40.432040 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 11:53:40.435588 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 11:53:40.442633 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 11:53:40.445820 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 11:53:40.449038 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:53:40.455559 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1243 11:53:40.459411 0 10 8 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
1244 11:53:40.463323 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:53:40.466904 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:53:40.470964 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:53:40.477639 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:53:40.480941 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:53:40.484118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:53:40.488517 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1251 11:53:40.494924 0 11 8 | B1->B0 | 3b3b 3939 | 1 0 | (0 0) (0 0)
1252 11:53:40.498754 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 11:53:40.501829 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 11:53:40.508557 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 11:53:40.511674 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 11:53:40.514728 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:53:40.518593 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:53:40.524809 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:53:40.528305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1260 11:53:40.531550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:53:40.538549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:53:40.541603 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:53:40.545523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:53:40.551917 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:53:40.554877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:53:40.558656 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:53:40.565285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:53:40.568718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:53:40.571933 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:53:40.578791 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:53:40.581680 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:53:40.585403 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:53:40.591565 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:53:40.595125 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1275 11:53:40.598335 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1276 11:53:40.605235 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 11:53:40.605469 Total UI for P1: 0, mck2ui 16
1278 11:53:40.608217 best dqsien dly found for B0: ( 0, 14, 6)
1279 11:53:40.611657 Total UI for P1: 0, mck2ui 16
1280 11:53:40.614764 best dqsien dly found for B1: ( 0, 14, 6)
1281 11:53:40.618640 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1282 11:53:40.621819 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1283 11:53:40.625347
1284 11:53:40.628695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1285 11:53:40.632026 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1286 11:53:40.635417 [Gating] SW calibration Done
1287 11:53:40.635543 ==
1288 11:53:40.638847 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 11:53:40.641954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 11:53:40.642042 ==
1291 11:53:40.642112 RX Vref Scan: 0
1292 11:53:40.642172
1293 11:53:40.645797 RX Vref 0 -> 0, step: 1
1294 11:53:40.645914
1295 11:53:40.648694 RX Delay -130 -> 252, step: 16
1296 11:53:40.652206 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1297 11:53:40.655710 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1298 11:53:40.661978 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1299 11:53:40.665693 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1300 11:53:40.668869 iDelay=222, Bit 4, Center 101 (-2 ~ 205) 208
1301 11:53:40.672141 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1302 11:53:40.675171 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1303 11:53:40.678337 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1304 11:53:40.685091 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1305 11:53:40.689021 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1306 11:53:40.691979 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1307 11:53:40.695131 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1308 11:53:40.701864 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1309 11:53:40.705351 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1310 11:53:40.709030 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1311 11:53:40.711812 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1312 11:53:40.711909 ==
1313 11:53:40.715172 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 11:53:40.718569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 11:53:40.718668 ==
1316 11:53:40.721915 DQS Delay:
1317 11:53:40.722018 DQS0 = 0, DQS1 = 0
1318 11:53:40.725584 DQM Delay:
1319 11:53:40.725711 DQM0 = 95, DQM1 = 84
1320 11:53:40.725817 DQ Delay:
1321 11:53:40.728779 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1322 11:53:40.731878 DQ4 =101, DQ5 =85, DQ6 =101, DQ7 =109
1323 11:53:40.735593 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1324 11:53:40.738812 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1325 11:53:40.738945
1326 11:53:40.742015
1327 11:53:40.742137 ==
1328 11:53:40.745279 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 11:53:40.748832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 11:53:40.748965 ==
1331 11:53:40.749065
1332 11:53:40.749166
1333 11:53:40.752036 TX Vref Scan disable
1334 11:53:40.752125 == TX Byte 0 ==
1335 11:53:40.758824 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1336 11:53:40.762006 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1337 11:53:40.762107 == TX Byte 1 ==
1338 11:53:40.769015 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1339 11:53:40.771923 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1340 11:53:40.772032 ==
1341 11:53:40.775706 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 11:53:40.779116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 11:53:40.779226 ==
1344 11:53:40.792622 TX Vref=22, minBit 9, minWin=27, winSum=444
1345 11:53:40.796352 TX Vref=24, minBit 1, minWin=28, winSum=453
1346 11:53:40.799356 TX Vref=26, minBit 1, minWin=28, winSum=455
1347 11:53:40.802702 TX Vref=28, minBit 8, minWin=27, winSum=454
1348 11:53:40.806165 TX Vref=30, minBit 7, minWin=28, winSum=459
1349 11:53:40.809279 TX Vref=32, minBit 1, minWin=28, winSum=455
1350 11:53:40.816393 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1351 11:53:40.816558
1352 11:53:40.819237 Final TX Range 1 Vref 30
1353 11:53:40.819361
1354 11:53:40.819459 ==
1355 11:53:40.822832 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 11:53:40.826356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 11:53:40.826482 ==
1358 11:53:40.826580
1359 11:53:40.826681
1360 11:53:40.829375 TX Vref Scan disable
1361 11:53:40.833007 == TX Byte 0 ==
1362 11:53:40.836071 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1363 11:53:40.839468 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1364 11:53:40.843075 == TX Byte 1 ==
1365 11:53:40.846023 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1366 11:53:40.849798 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1367 11:53:40.849896
1368 11:53:40.853004 [DATLAT]
1369 11:53:40.853091 Freq=800, CH0 RK1
1370 11:53:40.853159
1371 11:53:40.856082 DATLAT Default: 0xa
1372 11:53:40.856168 0, 0xFFFF, sum = 0
1373 11:53:40.859723 1, 0xFFFF, sum = 0
1374 11:53:40.859808 2, 0xFFFF, sum = 0
1375 11:53:40.862739 3, 0xFFFF, sum = 0
1376 11:53:40.862865 4, 0xFFFF, sum = 0
1377 11:53:40.866254 5, 0xFFFF, sum = 0
1378 11:53:40.866380 6, 0xFFFF, sum = 0
1379 11:53:40.869834 7, 0xFFFF, sum = 0
1380 11:53:40.869997 8, 0xFFFF, sum = 0
1381 11:53:40.873283 9, 0x0, sum = 1
1382 11:53:40.873396 10, 0x0, sum = 2
1383 11:53:40.876321 11, 0x0, sum = 3
1384 11:53:40.876439 12, 0x0, sum = 4
1385 11:53:40.879664 best_step = 10
1386 11:53:40.879782
1387 11:53:40.879876 ==
1388 11:53:40.883328 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 11:53:40.886277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 11:53:40.886407 ==
1391 11:53:40.890077 RX Vref Scan: 0
1392 11:53:40.890221
1393 11:53:40.890320 RX Vref 0 -> 0, step: 1
1394 11:53:40.890420
1395 11:53:40.893162 RX Delay -79 -> 252, step: 8
1396 11:53:40.899720 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1397 11:53:40.902855 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1398 11:53:40.906540 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1399 11:53:40.909797 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1400 11:53:40.913598 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1401 11:53:40.916485 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1402 11:53:40.923305 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1403 11:53:40.926252 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1404 11:53:40.929850 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1405 11:53:40.933264 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1406 11:53:40.936289 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1407 11:53:40.943420 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1408 11:53:40.946365 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1409 11:53:40.949852 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1410 11:53:40.952990 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1411 11:53:40.956917 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1412 11:53:40.959804 ==
1413 11:53:40.963198 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 11:53:40.966551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 11:53:40.966671 ==
1416 11:53:40.966782 DQS Delay:
1417 11:53:40.969936 DQS0 = 0, DQS1 = 0
1418 11:53:40.970059 DQM Delay:
1419 11:53:40.973664 DQM0 = 92, DQM1 = 83
1420 11:53:40.973792 DQ Delay:
1421 11:53:40.976961 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1422 11:53:40.980029 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1423 11:53:40.983493 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1424 11:53:40.986545 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1425 11:53:40.986669
1426 11:53:40.986773
1427 11:53:40.993291 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1428 11:53:40.996678 CH0 RK1: MR19=606, MR18=4617
1429 11:53:41.003249 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1430 11:53:41.007213 [RxdqsGatingPostProcess] freq 800
1431 11:53:41.010552 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1432 11:53:41.013288 Pre-setting of DQS Precalculation
1433 11:53:41.020001 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1434 11:53:41.020163 ==
1435 11:53:41.023716 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 11:53:41.026733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 11:53:41.026858 ==
1438 11:53:41.033697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1439 11:53:41.040131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1440 11:53:41.048305 [CA 0] Center 36 (6~67) winsize 62
1441 11:53:41.050846 [CA 1] Center 36 (6~67) winsize 62
1442 11:53:41.054519 [CA 2] Center 35 (4~66) winsize 63
1443 11:53:41.057414 [CA 3] Center 34 (4~65) winsize 62
1444 11:53:41.061209 [CA 4] Center 34 (4~65) winsize 62
1445 11:53:41.064122 [CA 5] Center 34 (4~65) winsize 62
1446 11:53:41.064243
1447 11:53:41.067783 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1448 11:53:41.067901
1449 11:53:41.071038 [CATrainingPosCal] consider 1 rank data
1450 11:53:41.074583 u2DelayCellTimex100 = 270/100 ps
1451 11:53:41.077646 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 11:53:41.080708 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 11:53:41.088006 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1454 11:53:41.091203 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 11:53:41.094401 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 11:53:41.098034 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 11:53:41.098178
1458 11:53:41.101125 CA PerBit enable=1, Macro0, CA PI delay=34
1459 11:53:41.101241
1460 11:53:41.104366 [CBTSetCACLKResult] CA Dly = 34
1461 11:53:41.104483 CS Dly: 5 (0~36)
1462 11:53:41.104580 ==
1463 11:53:41.107660 Dram Type= 6, Freq= 0, CH_1, rank 1
1464 11:53:41.114660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 11:53:41.114819 ==
1466 11:53:41.117958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 11:53:41.124593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 11:53:41.134862 [CA 0] Center 36 (6~67) winsize 62
1469 11:53:41.138021 [CA 1] Center 36 (6~67) winsize 62
1470 11:53:41.142280 [CA 2] Center 35 (5~66) winsize 62
1471 11:53:41.146032 [CA 3] Center 34 (4~65) winsize 62
1472 11:53:41.149684 [CA 4] Center 35 (4~66) winsize 63
1473 11:53:41.149831 [CA 5] Center 34 (4~65) winsize 62
1474 11:53:41.149933
1475 11:53:41.153196 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1476 11:53:41.156874
1477 11:53:41.157016 [CATrainingPosCal] consider 2 rank data
1478 11:53:41.160068 u2DelayCellTimex100 = 270/100 ps
1479 11:53:41.163700 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 11:53:41.170432 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 11:53:41.173748 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1482 11:53:41.176712 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 11:53:41.180187 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 11:53:41.183413 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 11:53:41.183546
1486 11:53:41.186836 CA PerBit enable=1, Macro0, CA PI delay=34
1487 11:53:41.186952
1488 11:53:41.190407 [CBTSetCACLKResult] CA Dly = 34
1489 11:53:41.190526 CS Dly: 6 (0~38)
1490 11:53:41.193372
1491 11:53:41.193486 ----->DramcWriteLeveling(PI) begin...
1492 11:53:41.196872 ==
1493 11:53:41.200626 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 11:53:41.203617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 11:53:41.203749 ==
1496 11:53:41.207040 Write leveling (Byte 0): 28 => 28
1497 11:53:41.210217 Write leveling (Byte 1): 28 => 28
1498 11:53:41.213806 DramcWriteLeveling(PI) end<-----
1499 11:53:41.213944
1500 11:53:41.214042 ==
1501 11:53:41.217377 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 11:53:41.220517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 11:53:41.220656 ==
1504 11:53:41.224153 [Gating] SW mode calibration
1505 11:53:41.230399 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1506 11:53:41.233553 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1507 11:53:41.240496 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1508 11:53:41.243757 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1509 11:53:41.247266 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:53:41.253714 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:53:41.257529 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:53:41.260153 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:53:41.267331 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:53:41.270438 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:53:41.273546 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:53:41.280393 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:53:41.284201 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:53:41.287759 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:53:41.294257 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:53:41.297408 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:53:41.300477 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:53:41.303711 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:53:41.310746 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:53:41.314265 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1525 11:53:41.317344 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1526 11:53:41.324187 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:53:41.327455 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:53:41.330609 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:53:41.337237 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:53:41.340340 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:53:41.344014 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:53:41.350821 0 9 4 | B1->B0 | 2323 2929 | 1 1 | (1 1) (1 1)
1533 11:53:41.354100 0 9 8 | B1->B0 | 3131 3232 | 1 1 | (1 1) (1 1)
1534 11:53:41.357460 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 11:53:41.364336 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 11:53:41.367127 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 11:53:41.370636 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:53:41.377070 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:53:41.380781 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:53:41.384415 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 0)
1541 11:53:41.390849 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
1542 11:53:41.393968 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:53:41.397715 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:53:41.400724 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:53:41.407276 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:53:41.410736 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:53:41.414031 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:53:41.421040 0 11 4 | B1->B0 | 2c2c 3333 | 0 1 | (0 0) (0 0)
1549 11:53:41.423969 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1550 11:53:41.427405 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 11:53:41.434048 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 11:53:41.437884 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 11:53:41.441018 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:53:41.447618 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:53:41.451134 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:53:41.454367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1557 11:53:41.461222 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:53:41.464414 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 11:53:41.467963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:53:41.471202 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:53:41.477573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:53:41.481286 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:53:41.484015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:53:41.490852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:53:41.494248 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:53:41.497482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:53:41.504298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:53:41.507922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:53:41.511088 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:53:41.517372 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:53:41.521126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:53:41.524184 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1573 11:53:41.531305 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 11:53:41.531451 Total UI for P1: 0, mck2ui 16
1575 11:53:41.537697 best dqsien dly found for B0: ( 0, 14, 4)
1576 11:53:41.537837 Total UI for P1: 0, mck2ui 16
1577 11:53:41.540932 best dqsien dly found for B1: ( 0, 14, 4)
1578 11:53:41.547662 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1579 11:53:41.551226 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1580 11:53:41.551348
1581 11:53:41.554530 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 11:53:41.557747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 11:53:41.561365 [Gating] SW calibration Done
1584 11:53:41.561485 ==
1585 11:53:41.564512 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 11:53:41.567887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 11:53:41.568000 ==
1588 11:53:41.568072 RX Vref Scan: 0
1589 11:53:41.568136
1590 11:53:41.570920 RX Vref 0 -> 0, step: 1
1591 11:53:41.571006
1592 11:53:41.574557 RX Delay -130 -> 252, step: 16
1593 11:53:41.577829 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1594 11:53:41.581235 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1595 11:53:41.587613 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1596 11:53:41.591279 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1597 11:53:41.594425 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1598 11:53:41.598083 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1599 11:53:41.601261 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1600 11:53:41.607927 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1601 11:53:41.611190 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1602 11:53:41.614638 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1603 11:53:41.617902 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1604 11:53:41.621347 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1605 11:53:41.627985 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1606 11:53:41.631233 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1607 11:53:41.635023 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1608 11:53:41.638140 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1609 11:53:41.638259 ==
1610 11:53:41.641516 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 11:53:41.644473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 11:53:41.647903 ==
1613 11:53:41.648014 DQS Delay:
1614 11:53:41.648083 DQS0 = 0, DQS1 = 0
1615 11:53:41.651247 DQM Delay:
1616 11:53:41.651351 DQM0 = 95, DQM1 = 91
1617 11:53:41.654852 DQ Delay:
1618 11:53:41.654957 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1619 11:53:41.658043 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1620 11:53:41.661549 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1621 11:53:41.668056 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1622 11:53:41.668193
1623 11:53:41.668293
1624 11:53:41.668377 ==
1625 11:53:41.671417 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 11:53:41.675056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 11:53:41.675173 ==
1628 11:53:41.675277
1629 11:53:41.675379
1630 11:53:41.678092 TX Vref Scan disable
1631 11:53:41.678231 == TX Byte 0 ==
1632 11:53:41.684773 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1633 11:53:41.688472 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1634 11:53:41.688579 == TX Byte 1 ==
1635 11:53:41.694651 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1636 11:53:41.698624 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1637 11:53:41.698718 ==
1638 11:53:41.702006 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 11:53:41.705323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 11:53:41.705413 ==
1641 11:53:41.718260 TX Vref=22, minBit 3, minWin=26, winSum=441
1642 11:53:41.721882 TX Vref=24, minBit 0, minWin=27, winSum=443
1643 11:53:41.725161 TX Vref=26, minBit 3, minWin=26, winSum=445
1644 11:53:41.728770 TX Vref=28, minBit 1, minWin=27, winSum=448
1645 11:53:41.731908 TX Vref=30, minBit 1, minWin=27, winSum=449
1646 11:53:41.735056 TX Vref=32, minBit 1, minWin=27, winSum=452
1647 11:53:41.741792 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 32
1648 11:53:41.741898
1649 11:53:41.745793 Final TX Range 1 Vref 32
1650 11:53:41.745888
1651 11:53:41.745977 ==
1652 11:53:41.748707 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 11:53:41.752087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 11:53:41.752181 ==
1655 11:53:41.752269
1656 11:53:41.752352
1657 11:53:41.755571 TX Vref Scan disable
1658 11:53:41.758873 == TX Byte 0 ==
1659 11:53:41.761855 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1660 11:53:41.765511 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1661 11:53:41.768762 == TX Byte 1 ==
1662 11:53:41.772426 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 11:53:41.775723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 11:53:41.775814
1665 11:53:41.778516 [DATLAT]
1666 11:53:41.778604 Freq=800, CH1 RK0
1667 11:53:41.778691
1668 11:53:41.781859 DATLAT Default: 0xa
1669 11:53:41.781947 0, 0xFFFF, sum = 0
1670 11:53:41.785465 1, 0xFFFF, sum = 0
1671 11:53:41.785588 2, 0xFFFF, sum = 0
1672 11:53:41.788550 3, 0xFFFF, sum = 0
1673 11:53:41.788639 4, 0xFFFF, sum = 0
1674 11:53:41.792221 5, 0xFFFF, sum = 0
1675 11:53:41.792310 6, 0xFFFF, sum = 0
1676 11:53:41.795224 7, 0xFFFF, sum = 0
1677 11:53:41.795313 8, 0xFFFF, sum = 0
1678 11:53:41.798883 9, 0x0, sum = 1
1679 11:53:41.798970 10, 0x0, sum = 2
1680 11:53:41.802612 11, 0x0, sum = 3
1681 11:53:41.802699 12, 0x0, sum = 4
1682 11:53:41.805356 best_step = 10
1683 11:53:41.805428
1684 11:53:41.805492 ==
1685 11:53:41.808922 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 11:53:41.811971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 11:53:41.812059 ==
1688 11:53:41.815656 RX Vref Scan: 1
1689 11:53:41.815745
1690 11:53:41.815814 Set Vref Range= 32 -> 127
1691 11:53:41.815878
1692 11:53:41.818637 RX Vref 32 -> 127, step: 1
1693 11:53:41.818723
1694 11:53:41.822083 RX Delay -79 -> 252, step: 8
1695 11:53:41.822172
1696 11:53:41.825521 Set Vref, RX VrefLevel [Byte0]: 32
1697 11:53:41.828989 [Byte1]: 32
1698 11:53:41.829078
1699 11:53:41.832238 Set Vref, RX VrefLevel [Byte0]: 33
1700 11:53:41.835275 [Byte1]: 33
1701 11:53:41.838666
1702 11:53:41.838754 Set Vref, RX VrefLevel [Byte0]: 34
1703 11:53:41.841997 [Byte1]: 34
1704 11:53:41.846055
1705 11:53:41.846147 Set Vref, RX VrefLevel [Byte0]: 35
1706 11:53:41.849290 [Byte1]: 35
1707 11:53:41.853515
1708 11:53:41.853640 Set Vref, RX VrefLevel [Byte0]: 36
1709 11:53:41.856867 [Byte1]: 36
1710 11:53:41.861165
1711 11:53:41.861280 Set Vref, RX VrefLevel [Byte0]: 37
1712 11:53:41.864678 [Byte1]: 37
1713 11:53:41.868805
1714 11:53:41.868928 Set Vref, RX VrefLevel [Byte0]: 38
1715 11:53:41.872219 [Byte1]: 38
1716 11:53:41.876291
1717 11:53:41.876401 Set Vref, RX VrefLevel [Byte0]: 39
1718 11:53:41.879459 [Byte1]: 39
1719 11:53:41.883934
1720 11:53:41.884050 Set Vref, RX VrefLevel [Byte0]: 40
1721 11:53:41.887438 [Byte1]: 40
1722 11:53:41.891428
1723 11:53:41.891518 Set Vref, RX VrefLevel [Byte0]: 41
1724 11:53:41.894560 [Byte1]: 41
1725 11:53:41.899419
1726 11:53:41.899507 Set Vref, RX VrefLevel [Byte0]: 42
1727 11:53:41.902369 [Byte1]: 42
1728 11:53:41.906501
1729 11:53:41.906584 Set Vref, RX VrefLevel [Byte0]: 43
1730 11:53:41.910266 [Byte1]: 43
1731 11:53:41.914598
1732 11:53:41.914702 Set Vref, RX VrefLevel [Byte0]: 44
1733 11:53:41.917304 [Byte1]: 44
1734 11:53:41.921596
1735 11:53:41.921688 Set Vref, RX VrefLevel [Byte0]: 45
1736 11:53:41.924667 [Byte1]: 45
1737 11:53:41.928957
1738 11:53:41.929065 Set Vref, RX VrefLevel [Byte0]: 46
1739 11:53:41.932582 [Byte1]: 46
1740 11:53:41.936963
1741 11:53:41.937077 Set Vref, RX VrefLevel [Byte0]: 47
1742 11:53:41.939935 [Byte1]: 47
1743 11:53:41.944215
1744 11:53:41.944311 Set Vref, RX VrefLevel [Byte0]: 48
1745 11:53:41.947360 [Byte1]: 48
1746 11:53:41.951585
1747 11:53:41.951741 Set Vref, RX VrefLevel [Byte0]: 49
1748 11:53:41.955298 [Byte1]: 49
1749 11:53:41.959716
1750 11:53:41.959831 Set Vref, RX VrefLevel [Byte0]: 50
1751 11:53:41.962467 [Byte1]: 50
1752 11:53:41.966881
1753 11:53:41.966994 Set Vref, RX VrefLevel [Byte0]: 51
1754 11:53:41.970209 [Byte1]: 51
1755 11:53:41.974647
1756 11:53:41.974756 Set Vref, RX VrefLevel [Byte0]: 52
1757 11:53:41.977821 [Byte1]: 52
1758 11:53:41.981981
1759 11:53:41.982064 Set Vref, RX VrefLevel [Byte0]: 53
1760 11:53:41.985138 [Byte1]: 53
1761 11:53:41.989545
1762 11:53:41.989642 Set Vref, RX VrefLevel [Byte0]: 54
1763 11:53:41.992939 [Byte1]: 54
1764 11:53:41.996800
1765 11:53:42.000190 Set Vref, RX VrefLevel [Byte0]: 55
1766 11:53:42.000302 [Byte1]: 55
1767 11:53:42.005164
1768 11:53:42.005246 Set Vref, RX VrefLevel [Byte0]: 56
1769 11:53:42.008431 [Byte1]: 56
1770 11:53:42.012174
1771 11:53:42.012280 Set Vref, RX VrefLevel [Byte0]: 57
1772 11:53:42.015607 [Byte1]: 57
1773 11:53:42.019956
1774 11:53:42.020041 Set Vref, RX VrefLevel [Byte0]: 58
1775 11:53:42.022760 [Byte1]: 58
1776 11:53:42.027280
1777 11:53:42.027368 Set Vref, RX VrefLevel [Byte0]: 59
1778 11:53:42.030926 [Byte1]: 59
1779 11:53:42.035118
1780 11:53:42.035204 Set Vref, RX VrefLevel [Byte0]: 60
1781 11:53:42.038101 [Byte1]: 60
1782 11:53:42.042685
1783 11:53:42.042774 Set Vref, RX VrefLevel [Byte0]: 61
1784 11:53:42.045369 [Byte1]: 61
1785 11:53:42.049954
1786 11:53:42.050039 Set Vref, RX VrefLevel [Byte0]: 62
1787 11:53:42.053348 [Byte1]: 62
1788 11:53:42.057906
1789 11:53:42.057992 Set Vref, RX VrefLevel [Byte0]: 63
1790 11:53:42.060838 [Byte1]: 63
1791 11:53:42.065450
1792 11:53:42.065562 Set Vref, RX VrefLevel [Byte0]: 64
1793 11:53:42.068178 [Byte1]: 64
1794 11:53:42.072351
1795 11:53:42.072440 Set Vref, RX VrefLevel [Byte0]: 65
1796 11:53:42.075660 [Byte1]: 65
1797 11:53:42.080248
1798 11:53:42.080360 Set Vref, RX VrefLevel [Byte0]: 66
1799 11:53:42.083600 [Byte1]: 66
1800 11:53:42.087703
1801 11:53:42.087791 Set Vref, RX VrefLevel [Byte0]: 67
1802 11:53:42.091034 [Byte1]: 67
1803 11:53:42.094986
1804 11:53:42.095069 Set Vref, RX VrefLevel [Byte0]: 68
1805 11:53:42.098440 [Byte1]: 68
1806 11:53:42.102528
1807 11:53:42.102617 Set Vref, RX VrefLevel [Byte0]: 69
1808 11:53:42.106178 [Byte1]: 69
1809 11:53:42.110076
1810 11:53:42.110162 Set Vref, RX VrefLevel [Byte0]: 70
1811 11:53:42.113674 [Byte1]: 70
1812 11:53:42.117875
1813 11:53:42.117991 Set Vref, RX VrefLevel [Byte0]: 71
1814 11:53:42.121744 [Byte1]: 71
1815 11:53:42.125262
1816 11:53:42.125376 Set Vref, RX VrefLevel [Byte0]: 72
1817 11:53:42.128490 [Byte1]: 72
1818 11:53:42.132974
1819 11:53:42.133092 Final RX Vref Byte 0 = 56 to rank0
1820 11:53:42.136187 Final RX Vref Byte 1 = 58 to rank0
1821 11:53:42.139703 Final RX Vref Byte 0 = 56 to rank1
1822 11:53:42.142607 Final RX Vref Byte 1 = 58 to rank1==
1823 11:53:42.146302 Dram Type= 6, Freq= 0, CH_1, rank 0
1824 11:53:42.152463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 11:53:42.152555 ==
1826 11:53:42.152644 DQS Delay:
1827 11:53:42.156072 DQS0 = 0, DQS1 = 0
1828 11:53:42.156153 DQM Delay:
1829 11:53:42.156217 DQM0 = 95, DQM1 = 89
1830 11:53:42.159301 DQ Delay:
1831 11:53:42.163133 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1832 11:53:42.165902 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1833 11:53:42.169652 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1834 11:53:42.172680 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1835 11:53:42.172771
1836 11:53:42.172838
1837 11:53:42.179571 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1838 11:53:42.182430 CH1 RK0: MR19=606, MR18=2A46
1839 11:53:42.189296 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1840 11:53:42.189429
1841 11:53:42.192871 ----->DramcWriteLeveling(PI) begin...
1842 11:53:42.192963 ==
1843 11:53:42.195978 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 11:53:42.199379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 11:53:42.199472 ==
1846 11:53:42.203271 Write leveling (Byte 0): 25 => 25
1847 11:53:42.206072 Write leveling (Byte 1): 29 => 29
1848 11:53:42.209386 DramcWriteLeveling(PI) end<-----
1849 11:53:42.209474
1850 11:53:42.209541 ==
1851 11:53:42.212737 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 11:53:42.215762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 11:53:42.215851 ==
1854 11:53:42.219429 [Gating] SW mode calibration
1855 11:53:42.225885 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1856 11:53:42.232515 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1857 11:53:42.236258 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1858 11:53:42.239392 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1859 11:53:42.246322 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1860 11:53:42.249549 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:53:42.252942 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:53:42.259575 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:53:42.262704 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:53:42.266253 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:53:42.272906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:53:42.276040 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:53:42.279762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:53:42.286366 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:53:42.289472 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:53:42.292972 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:53:42.299282 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:53:42.302723 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:53:42.306269 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:53:42.312702 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1875 11:53:42.315971 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:53:42.319633 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:53:42.322694 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:53:42.329470 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:53:42.333080 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:53:42.336111 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:53:42.343200 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:53:42.346536 0 9 4 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
1883 11:53:42.349784 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1884 11:53:42.356235 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 11:53:42.359920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 11:53:42.363146 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 11:53:42.369610 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 11:53:42.372968 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 11:53:42.376432 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1890 11:53:42.382681 0 10 4 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
1891 11:53:42.386492 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1892 11:53:42.389491 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:53:42.393127 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:53:42.399548 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:53:42.403115 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:53:42.406685 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:53:42.413250 0 11 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1898 11:53:42.416259 0 11 4 | B1->B0 | 3939 2e2e | 0 0 | (0 0) (0 0)
1899 11:53:42.419737 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1900 11:53:42.426239 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 11:53:42.430122 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 11:53:42.433158 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 11:53:42.439664 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 11:53:42.443358 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 11:53:42.446297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 11:53:42.452801 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1907 11:53:42.456206 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1908 11:53:42.459775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:53:42.466536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:53:42.470143 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:53:42.473440 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:53:42.476520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 11:53:42.483337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 11:53:42.486507 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 11:53:42.489945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:53:42.496707 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:53:42.500299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:53:42.503290 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:53:42.509909 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:53:42.513058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:53:42.516635 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1922 11:53:42.523233 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 11:53:42.523388 Total UI for P1: 0, mck2ui 16
1924 11:53:42.529861 best dqsien dly found for B0: ( 0, 14, 0)
1925 11:53:42.530021 Total UI for P1: 0, mck2ui 16
1926 11:53:42.533814 best dqsien dly found for B1: ( 0, 14, 0)
1927 11:53:42.539866 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1928 11:53:42.543376 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1929 11:53:42.543523
1930 11:53:42.546981 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1931 11:53:42.549925 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1932 11:53:42.553510 [Gating] SW calibration Done
1933 11:53:42.553680 ==
1934 11:53:42.557225 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 11:53:42.560296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 11:53:42.560428 ==
1937 11:53:42.560526 RX Vref Scan: 0
1938 11:53:42.560614
1939 11:53:42.563811 RX Vref 0 -> 0, step: 1
1940 11:53:42.563937
1941 11:53:42.566984 RX Delay -130 -> 252, step: 16
1942 11:53:42.570218 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1943 11:53:42.573483 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1944 11:53:42.580324 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1945 11:53:42.583845 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1946 11:53:42.586909 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1947 11:53:42.589996 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1948 11:53:42.593547 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1949 11:53:42.600159 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1950 11:53:42.603613 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1951 11:53:42.606680 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1952 11:53:42.610528 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1953 11:53:42.613724 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1954 11:53:42.620519 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1955 11:53:42.623099 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1956 11:53:42.626817 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1957 11:53:42.630090 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1958 11:53:42.630236 ==
1959 11:53:42.633563 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:53:42.639780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:53:42.639947 ==
1962 11:53:42.640043 DQS Delay:
1963 11:53:42.643430 DQS0 = 0, DQS1 = 0
1964 11:53:42.643543 DQM Delay:
1965 11:53:42.643613 DQM0 = 93, DQM1 = 90
1966 11:53:42.646390 DQ Delay:
1967 11:53:42.650127 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1968 11:53:42.653341 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1969 11:53:42.656601 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1970 11:53:42.660298 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1971 11:53:42.660413
1972 11:53:42.660512
1973 11:53:42.660605 ==
1974 11:53:42.663259 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 11:53:42.666396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 11:53:42.666512 ==
1977 11:53:42.666610
1978 11:53:42.666707
1979 11:53:42.670100 TX Vref Scan disable
1980 11:53:42.673184 == TX Byte 0 ==
1981 11:53:42.676656 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1982 11:53:42.679807 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1983 11:53:42.683282 == TX Byte 1 ==
1984 11:53:42.686582 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1985 11:53:42.690149 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1986 11:53:42.690268 ==
1987 11:53:42.693266 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 11:53:42.696340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 11:53:42.696432 ==
1990 11:53:42.710866 TX Vref=22, minBit 0, minWin=27, winSum=443
1991 11:53:42.714880 TX Vref=24, minBit 0, minWin=27, winSum=444
1992 11:53:42.717573 TX Vref=26, minBit 0, minWin=27, winSum=446
1993 11:53:42.721171 TX Vref=28, minBit 0, minWin=27, winSum=448
1994 11:53:42.724667 TX Vref=30, minBit 0, minWin=27, winSum=450
1995 11:53:42.727833 TX Vref=32, minBit 0, minWin=27, winSum=447
1996 11:53:42.734709 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 30
1997 11:53:42.734852
1998 11:53:42.737860 Final TX Range 1 Vref 30
1999 11:53:42.737978
2000 11:53:42.738075 ==
2001 11:53:42.741212 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 11:53:42.744462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 11:53:42.744578 ==
2004 11:53:42.744676
2005 11:53:42.744770
2006 11:53:42.747825 TX Vref Scan disable
2007 11:53:42.750974 == TX Byte 0 ==
2008 11:53:42.754528 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2009 11:53:42.758028 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2010 11:53:42.760980 == TX Byte 1 ==
2011 11:53:42.764698 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2012 11:53:42.767717 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2013 11:53:42.767832
2014 11:53:42.771347 [DATLAT]
2015 11:53:42.771457 Freq=800, CH1 RK1
2016 11:53:42.771549
2017 11:53:42.774332 DATLAT Default: 0xa
2018 11:53:42.774444 0, 0xFFFF, sum = 0
2019 11:53:42.777830 1, 0xFFFF, sum = 0
2020 11:53:42.777944 2, 0xFFFF, sum = 0
2021 11:53:42.781037 3, 0xFFFF, sum = 0
2022 11:53:42.781149 4, 0xFFFF, sum = 0
2023 11:53:42.784569 5, 0xFFFF, sum = 0
2024 11:53:42.784682 6, 0xFFFF, sum = 0
2025 11:53:42.787803 7, 0xFFFF, sum = 0
2026 11:53:42.790956 8, 0xFFFF, sum = 0
2027 11:53:42.791074 9, 0x0, sum = 1
2028 11:53:42.791172 10, 0x0, sum = 2
2029 11:53:42.794485 11, 0x0, sum = 3
2030 11:53:42.794603 12, 0x0, sum = 4
2031 11:53:42.797600 best_step = 10
2032 11:53:42.797710
2033 11:53:42.797806 ==
2034 11:53:42.801274 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 11:53:42.804569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 11:53:42.804696 ==
2037 11:53:42.808109 RX Vref Scan: 0
2038 11:53:42.808221
2039 11:53:42.808318 RX Vref 0 -> 0, step: 1
2040 11:53:42.808414
2041 11:53:42.811131 RX Delay -63 -> 252, step: 8
2042 11:53:42.817876 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2043 11:53:42.821463 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2044 11:53:42.824708 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2045 11:53:42.827733 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2046 11:53:42.831038 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2047 11:53:42.834070 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2048 11:53:42.840861 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2049 11:53:42.844350 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2050 11:53:42.848051 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2051 11:53:42.851124 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2052 11:53:42.854276 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2053 11:53:42.860861 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2054 11:53:42.864284 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2055 11:53:42.867588 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2056 11:53:42.870963 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2057 11:53:42.874465 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2058 11:53:42.874589 ==
2059 11:53:42.877595 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 11:53:42.884289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 11:53:42.884424 ==
2062 11:53:42.884524 DQS Delay:
2063 11:53:42.887990 DQS0 = 0, DQS1 = 0
2064 11:53:42.888106 DQM Delay:
2065 11:53:42.888203 DQM0 = 97, DQM1 = 90
2066 11:53:42.890789 DQ Delay:
2067 11:53:42.894121 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2068 11:53:42.897764 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2069 11:53:42.901006 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2070 11:53:42.904180 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2071 11:53:42.904311
2072 11:53:42.904411
2073 11:53:42.910673 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2074 11:53:42.914596 CH1 RK1: MR19=606, MR18=440E
2075 11:53:42.920883 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2076 11:53:42.924102 [RxdqsGatingPostProcess] freq 800
2077 11:53:42.927665 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2078 11:53:42.930826 Pre-setting of DQS Precalculation
2079 11:53:42.937512 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2080 11:53:42.944196 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2081 11:53:42.950976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2082 11:53:42.951119
2083 11:53:42.951215
2084 11:53:42.954197 [Calibration Summary] 1600 Mbps
2085 11:53:42.954310 CH 0, Rank 0
2086 11:53:42.957683 SW Impedance : PASS
2087 11:53:42.961270 DUTY Scan : NO K
2088 11:53:42.961390 ZQ Calibration : PASS
2089 11:53:42.964155 Jitter Meter : NO K
2090 11:53:42.967785 CBT Training : PASS
2091 11:53:42.967903 Write leveling : PASS
2092 11:53:42.971259 RX DQS gating : PASS
2093 11:53:42.974613 RX DQ/DQS(RDDQC) : PASS
2094 11:53:42.974738 TX DQ/DQS : PASS
2095 11:53:42.977789 RX DATLAT : PASS
2096 11:53:42.981349 RX DQ/DQS(Engine): PASS
2097 11:53:42.981479 TX OE : NO K
2098 11:53:42.981585 All Pass.
2099 11:53:42.984259
2100 11:53:42.984389 CH 0, Rank 1
2101 11:53:42.987852 SW Impedance : PASS
2102 11:53:42.987974 DUTY Scan : NO K
2103 11:53:42.990940 ZQ Calibration : PASS
2104 11:53:42.991069 Jitter Meter : NO K
2105 11:53:42.994791 CBT Training : PASS
2106 11:53:42.997754 Write leveling : PASS
2107 11:53:42.997879 RX DQS gating : PASS
2108 11:53:43.001262 RX DQ/DQS(RDDQC) : PASS
2109 11:53:43.004277 TX DQ/DQS : PASS
2110 11:53:43.004395 RX DATLAT : PASS
2111 11:53:43.008307 RX DQ/DQS(Engine): PASS
2112 11:53:43.011591 TX OE : NO K
2113 11:53:43.011711 All Pass.
2114 11:53:43.011807
2115 11:53:43.011893 CH 1, Rank 0
2116 11:53:43.014302 SW Impedance : PASS
2117 11:53:43.018104 DUTY Scan : NO K
2118 11:53:43.018213 ZQ Calibration : PASS
2119 11:53:43.021806 Jitter Meter : NO K
2120 11:53:43.024926 CBT Training : PASS
2121 11:53:43.025046 Write leveling : PASS
2122 11:53:43.028372 RX DQS gating : PASS
2123 11:53:43.028485 RX DQ/DQS(RDDQC) : PASS
2124 11:53:43.031451 TX DQ/DQS : PASS
2125 11:53:43.034855 RX DATLAT : PASS
2126 11:53:43.034968 RX DQ/DQS(Engine): PASS
2127 11:53:43.038440 TX OE : NO K
2128 11:53:43.038550 All Pass.
2129 11:53:43.038638
2130 11:53:43.041472 CH 1, Rank 1
2131 11:53:43.041591 SW Impedance : PASS
2132 11:53:43.044795 DUTY Scan : NO K
2133 11:53:43.048361 ZQ Calibration : PASS
2134 11:53:43.048478 Jitter Meter : NO K
2135 11:53:43.051557 CBT Training : PASS
2136 11:53:43.055007 Write leveling : PASS
2137 11:53:43.055114 RX DQS gating : PASS
2138 11:53:43.058001 RX DQ/DQS(RDDQC) : PASS
2139 11:53:43.061775 TX DQ/DQS : PASS
2140 11:53:43.061882 RX DATLAT : PASS
2141 11:53:43.064743 RX DQ/DQS(Engine): PASS
2142 11:53:43.064851 TX OE : NO K
2143 11:53:43.068070 All Pass.
2144 11:53:43.068178
2145 11:53:43.068270 DramC Write-DBI off
2146 11:53:43.071835 PER_BANK_REFRESH: Hybrid Mode
2147 11:53:43.074689 TX_TRACKING: ON
2148 11:53:43.078073 [GetDramInforAfterCalByMRR] Vendor 6.
2149 11:53:43.081465 [GetDramInforAfterCalByMRR] Revision 606.
2150 11:53:43.084783 [GetDramInforAfterCalByMRR] Revision 2 0.
2151 11:53:43.084899 MR0 0x3b3b
2152 11:53:43.084993 MR8 0x5151
2153 11:53:43.088363 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2154 11:53:43.091794
2155 11:53:43.091919 MR0 0x3b3b
2156 11:53:43.092016 MR8 0x5151
2157 11:53:43.094909 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 11:53:43.095025
2159 11:53:43.105307 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2160 11:53:43.108776 [FAST_K] Save calibration result to emmc
2161 11:53:43.111895 [FAST_K] Save calibration result to emmc
2162 11:53:43.115430 dram_init: config_dvfs: 1
2163 11:53:43.118249 dramc_set_vcore_voltage set vcore to 662500
2164 11:53:43.121803 Read voltage for 1200, 2
2165 11:53:43.121933 Vio18 = 0
2166 11:53:43.122029 Vcore = 662500
2167 11:53:43.125570 Vdram = 0
2168 11:53:43.125702 Vddq = 0
2169 11:53:43.125800 Vmddr = 0
2170 11:53:43.131617 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2171 11:53:43.135299 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2172 11:53:43.138459 MEM_TYPE=3, freq_sel=15
2173 11:53:43.142182 sv_algorithm_assistance_LP4_1600
2174 11:53:43.145181 ============ PULL DRAM RESETB DOWN ============
2175 11:53:43.148978 ========== PULL DRAM RESETB DOWN end =========
2176 11:53:43.155046 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2177 11:53:43.158550 ===================================
2178 11:53:43.158685 LPDDR4 DRAM CONFIGURATION
2179 11:53:43.162108 ===================================
2180 11:53:43.165281 EX_ROW_EN[0] = 0x0
2181 11:53:43.168406 EX_ROW_EN[1] = 0x0
2182 11:53:43.168521 LP4Y_EN = 0x0
2183 11:53:43.171923 WORK_FSP = 0x0
2184 11:53:43.172041 WL = 0x4
2185 11:53:43.175384 RL = 0x4
2186 11:53:43.175504 BL = 0x2
2187 11:53:43.178718 RPST = 0x0
2188 11:53:43.178833 RD_PRE = 0x0
2189 11:53:43.182256 WR_PRE = 0x1
2190 11:53:43.182370 WR_PST = 0x0
2191 11:53:43.185290 DBI_WR = 0x0
2192 11:53:43.185397 DBI_RD = 0x0
2193 11:53:43.188425 OTF = 0x1
2194 11:53:43.191715 ===================================
2195 11:53:43.195214 ===================================
2196 11:53:43.195337 ANA top config
2197 11:53:43.198565 ===================================
2198 11:53:43.201968 DLL_ASYNC_EN = 0
2199 11:53:43.205278 ALL_SLAVE_EN = 0
2200 11:53:43.205406 NEW_RANK_MODE = 1
2201 11:53:43.208814 DLL_IDLE_MODE = 1
2202 11:53:43.212150 LP45_APHY_COMB_EN = 1
2203 11:53:43.215803 TX_ODT_DIS = 1
2204 11:53:43.218558 NEW_8X_MODE = 1
2205 11:53:43.222137 ===================================
2206 11:53:43.222268 ===================================
2207 11:53:43.225650 data_rate = 2400
2208 11:53:43.228591 CKR = 1
2209 11:53:43.232261 DQ_P2S_RATIO = 8
2210 11:53:43.235326 ===================================
2211 11:53:43.238848 CA_P2S_RATIO = 8
2212 11:53:43.242535 DQ_CA_OPEN = 0
2213 11:53:43.242667 DQ_SEMI_OPEN = 0
2214 11:53:43.245516 CA_SEMI_OPEN = 0
2215 11:53:43.249168 CA_FULL_RATE = 0
2216 11:53:43.252097 DQ_CKDIV4_EN = 0
2217 11:53:43.255825 CA_CKDIV4_EN = 0
2218 11:53:43.258958 CA_PREDIV_EN = 0
2219 11:53:43.259089 PH8_DLY = 17
2220 11:53:43.262436 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2221 11:53:43.265892 DQ_AAMCK_DIV = 4
2222 11:53:43.268753 CA_AAMCK_DIV = 4
2223 11:53:43.272556 CA_ADMCK_DIV = 4
2224 11:53:43.275644 DQ_TRACK_CA_EN = 0
2225 11:53:43.275773 CA_PICK = 1200
2226 11:53:43.279212 CA_MCKIO = 1200
2227 11:53:43.281893 MCKIO_SEMI = 0
2228 11:53:43.285836 PLL_FREQ = 2366
2229 11:53:43.289018 DQ_UI_PI_RATIO = 32
2230 11:53:43.292140 CA_UI_PI_RATIO = 0
2231 11:53:43.295854 ===================================
2232 11:53:43.299226 ===================================
2233 11:53:43.302464 memory_type:LPDDR4
2234 11:53:43.302596 GP_NUM : 10
2235 11:53:43.305564 SRAM_EN : 1
2236 11:53:43.305696 MD32_EN : 0
2237 11:53:43.308844 ===================================
2238 11:53:43.312176 [ANA_INIT] >>>>>>>>>>>>>>
2239 11:53:43.315601 <<<<<< [CONFIGURE PHASE]: ANA_TX
2240 11:53:43.318824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2241 11:53:43.322242 ===================================
2242 11:53:43.325311 data_rate = 2400,PCW = 0X5b00
2243 11:53:43.328869 ===================================
2244 11:53:43.332149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2245 11:53:43.335705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2246 11:53:43.342622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 11:53:43.345773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2248 11:53:43.349070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2249 11:53:43.352269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2250 11:53:43.356003 [ANA_INIT] flow start
2251 11:53:43.359103 [ANA_INIT] PLL >>>>>>>>
2252 11:53:43.359235 [ANA_INIT] PLL <<<<<<<<
2253 11:53:43.362723 [ANA_INIT] MIDPI >>>>>>>>
2254 11:53:43.366115 [ANA_INIT] MIDPI <<<<<<<<
2255 11:53:43.369165 [ANA_INIT] DLL >>>>>>>>
2256 11:53:43.369290 [ANA_INIT] DLL <<<<<<<<
2257 11:53:43.372946 [ANA_INIT] flow end
2258 11:53:43.375737 ============ LP4 DIFF to SE enter ============
2259 11:53:43.379010 ============ LP4 DIFF to SE exit ============
2260 11:53:43.382548 [ANA_INIT] <<<<<<<<<<<<<
2261 11:53:43.385674 [Flow] Enable top DCM control >>>>>
2262 11:53:43.389212 [Flow] Enable top DCM control <<<<<
2263 11:53:43.392647 Enable DLL master slave shuffle
2264 11:53:43.396092 ==============================================================
2265 11:53:43.399091 Gating Mode config
2266 11:53:43.405775 ==============================================================
2267 11:53:43.405943 Config description:
2268 11:53:43.416013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2269 11:53:43.422794 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2270 11:53:43.425971 SELPH_MODE 0: By rank 1: By Phase
2271 11:53:43.432624 ==============================================================
2272 11:53:43.435783 GAT_TRACK_EN = 1
2273 11:53:43.439348 RX_GATING_MODE = 2
2274 11:53:43.442703 RX_GATING_TRACK_MODE = 2
2275 11:53:43.446087 SELPH_MODE = 1
2276 11:53:43.449365 PICG_EARLY_EN = 1
2277 11:53:43.452428 VALID_LAT_VALUE = 1
2278 11:53:43.456264 ==============================================================
2279 11:53:43.459253 Enter into Gating configuration >>>>
2280 11:53:43.462820 Exit from Gating configuration <<<<
2281 11:53:43.465980 Enter into DVFS_PRE_config >>>>>
2282 11:53:43.476261 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2283 11:53:43.479360 Exit from DVFS_PRE_config <<<<<
2284 11:53:43.482781 Enter into PICG configuration >>>>
2285 11:53:43.485970 Exit from PICG configuration <<<<
2286 11:53:43.489552 [RX_INPUT] configuration >>>>>
2287 11:53:43.492680 [RX_INPUT] configuration <<<<<
2288 11:53:43.499414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2289 11:53:43.502395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2290 11:53:43.509004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2291 11:53:43.515873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2292 11:53:43.522537 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 11:53:43.529129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 11:53:43.532719 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2295 11:53:43.536099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2296 11:53:43.539389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2297 11:53:43.542684 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2298 11:53:43.549400 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2299 11:53:43.552998 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 11:53:43.556151 ===================================
2301 11:53:43.559311 LPDDR4 DRAM CONFIGURATION
2302 11:53:43.562605 ===================================
2303 11:53:43.562719 EX_ROW_EN[0] = 0x0
2304 11:53:43.565787 EX_ROW_EN[1] = 0x0
2305 11:53:43.565883 LP4Y_EN = 0x0
2306 11:53:43.569658 WORK_FSP = 0x0
2307 11:53:43.569766 WL = 0x4
2308 11:53:43.572776 RL = 0x4
2309 11:53:43.572882 BL = 0x2
2310 11:53:43.576043 RPST = 0x0
2311 11:53:43.576160 RD_PRE = 0x0
2312 11:53:43.579358 WR_PRE = 0x1
2313 11:53:43.579468 WR_PST = 0x0
2314 11:53:43.583048 DBI_WR = 0x0
2315 11:53:43.585880 DBI_RD = 0x0
2316 11:53:43.585993 OTF = 0x1
2317 11:53:43.589443 ===================================
2318 11:53:43.593192 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2319 11:53:43.596168 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2320 11:53:43.602971 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 11:53:43.605987 ===================================
2322 11:53:43.606117 LPDDR4 DRAM CONFIGURATION
2323 11:53:43.609698 ===================================
2324 11:53:43.613021 EX_ROW_EN[0] = 0x10
2325 11:53:43.616678 EX_ROW_EN[1] = 0x0
2326 11:53:43.616802 LP4Y_EN = 0x0
2327 11:53:43.619911 WORK_FSP = 0x0
2328 11:53:43.620038 WL = 0x4
2329 11:53:43.623198 RL = 0x4
2330 11:53:43.623319 BL = 0x2
2331 11:53:43.625894 RPST = 0x0
2332 11:53:43.626017 RD_PRE = 0x0
2333 11:53:43.629677 WR_PRE = 0x1
2334 11:53:43.629793 WR_PST = 0x0
2335 11:53:43.632852 DBI_WR = 0x0
2336 11:53:43.632962 DBI_RD = 0x0
2337 11:53:43.636376 OTF = 0x1
2338 11:53:43.639563 ===================================
2339 11:53:43.646517 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2340 11:53:43.646661 ==
2341 11:53:43.649546 Dram Type= 6, Freq= 0, CH_0, rank 0
2342 11:53:43.653239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2343 11:53:43.653359 ==
2344 11:53:43.656199 [Duty_Offset_Calibration]
2345 11:53:43.656309 B0:2 B1:1 CA:1
2346 11:53:43.656402
2347 11:53:43.659674 [DutyScan_Calibration_Flow] k_type=0
2348 11:53:43.669902
2349 11:53:43.670074 ==CLK 0==
2350 11:53:43.672797 Final CLK duty delay cell = 0
2351 11:53:43.676504 [0] MAX Duty = 5218%(X100), DQS PI = 24
2352 11:53:43.679623 [0] MIN Duty = 4875%(X100), DQS PI = 0
2353 11:53:43.679738 [0] AVG Duty = 5046%(X100)
2354 11:53:43.683327
2355 11:53:43.683422 CH0 CLK Duty spec in!! Max-Min= 343%
2356 11:53:43.689746 [DutyScan_Calibration_Flow] ====Done====
2357 11:53:43.689865
2358 11:53:43.693086 [DutyScan_Calibration_Flow] k_type=1
2359 11:53:43.707572
2360 11:53:43.707737 ==DQS 0 ==
2361 11:53:43.710681 Final DQS duty delay cell = -4
2362 11:53:43.713730 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2363 11:53:43.717367 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2364 11:53:43.720900 [-4] AVG Duty = 4937%(X100)
2365 11:53:43.721018
2366 11:53:43.721112 ==DQS 1 ==
2367 11:53:43.724087 Final DQS duty delay cell = -4
2368 11:53:43.727785 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2369 11:53:43.730842 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2370 11:53:43.734046 [-4] AVG Duty = 4906%(X100)
2371 11:53:43.734139
2372 11:53:43.737728 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2373 11:53:43.737816
2374 11:53:43.741215 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2375 11:53:43.744465 [DutyScan_Calibration_Flow] ====Done====
2376 11:53:43.744553
2377 11:53:43.747360 [DutyScan_Calibration_Flow] k_type=3
2378 11:53:43.764562
2379 11:53:43.764703 ==DQM 0 ==
2380 11:53:43.767883 Final DQM duty delay cell = 0
2381 11:53:43.771027 [0] MAX Duty = 5156%(X100), DQS PI = 28
2382 11:53:43.774885 [0] MIN Duty = 4906%(X100), DQS PI = 52
2383 11:53:43.775012 [0] AVG Duty = 5031%(X100)
2384 11:53:43.778262
2385 11:53:43.778379 ==DQM 1 ==
2386 11:53:43.781436 Final DQM duty delay cell = 0
2387 11:53:43.784856 [0] MAX Duty = 5124%(X100), DQS PI = 8
2388 11:53:43.787795 [0] MIN Duty = 5031%(X100), DQS PI = 36
2389 11:53:43.787911 [0] AVG Duty = 5077%(X100)
2390 11:53:43.791540
2391 11:53:43.794552 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2392 11:53:43.794661
2393 11:53:43.797958 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2394 11:53:43.801384 [DutyScan_Calibration_Flow] ====Done====
2395 11:53:43.801486
2396 11:53:43.804704 [DutyScan_Calibration_Flow] k_type=2
2397 11:53:43.821191
2398 11:53:43.821353 ==DQ 0 ==
2399 11:53:43.824252 Final DQ duty delay cell = 0
2400 11:53:43.827431 [0] MAX Duty = 5062%(X100), DQS PI = 32
2401 11:53:43.831127 [0] MIN Duty = 4906%(X100), DQS PI = 0
2402 11:53:43.831244 [0] AVG Duty = 4984%(X100)
2403 11:53:43.831338
2404 11:53:43.834135 ==DQ 1 ==
2405 11:53:43.837938 Final DQ duty delay cell = 0
2406 11:53:43.841008 [0] MAX Duty = 5093%(X100), DQS PI = 8
2407 11:53:43.844379 [0] MIN Duty = 4969%(X100), DQS PI = 16
2408 11:53:43.844499 [0] AVG Duty = 5031%(X100)
2409 11:53:43.844593
2410 11:53:43.847611 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2411 11:53:43.847703
2412 11:53:43.850912 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2413 11:53:43.857802 [DutyScan_Calibration_Flow] ====Done====
2414 11:53:43.857896 ==
2415 11:53:43.861130 Dram Type= 6, Freq= 0, CH_1, rank 0
2416 11:53:43.864690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2417 11:53:43.864776 ==
2418 11:53:43.867827 [Duty_Offset_Calibration]
2419 11:53:43.867917 B0:1 B1:0 CA:0
2420 11:53:43.867985
2421 11:53:43.870725 [DutyScan_Calibration_Flow] k_type=0
2422 11:53:43.879878
2423 11:53:43.879977 ==CLK 0==
2424 11:53:43.883327 Final CLK duty delay cell = -4
2425 11:53:43.886878 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2426 11:53:43.890272 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2427 11:53:43.893081 [-4] AVG Duty = 4969%(X100)
2428 11:53:43.893209
2429 11:53:43.897138 CH1 CLK Duty spec in!! Max-Min= 124%
2430 11:53:43.900387 [DutyScan_Calibration_Flow] ====Done====
2431 11:53:43.900478
2432 11:53:43.903632 [DutyScan_Calibration_Flow] k_type=1
2433 11:53:43.919769
2434 11:53:43.919912 ==DQS 0 ==
2435 11:53:43.922993 Final DQS duty delay cell = 0
2436 11:53:43.926725 [0] MAX Duty = 5094%(X100), DQS PI = 26
2437 11:53:43.930236 [0] MIN Duty = 4875%(X100), DQS PI = 0
2438 11:53:43.930339 [0] AVG Duty = 4984%(X100)
2439 11:53:43.933534
2440 11:53:43.933647 ==DQS 1 ==
2441 11:53:43.936381 Final DQS duty delay cell = 0
2442 11:53:43.940135 [0] MAX Duty = 5187%(X100), DQS PI = 20
2443 11:53:43.943114 [0] MIN Duty = 4969%(X100), DQS PI = 8
2444 11:53:43.943205 [0] AVG Duty = 5078%(X100)
2445 11:53:43.943274
2446 11:53:43.950124 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2447 11:53:43.950220
2448 11:53:43.953500 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2449 11:53:43.956751 [DutyScan_Calibration_Flow] ====Done====
2450 11:53:43.956843
2451 11:53:43.959969 [DutyScan_Calibration_Flow] k_type=3
2452 11:53:43.976090
2453 11:53:43.976251 ==DQM 0 ==
2454 11:53:43.979700 Final DQM duty delay cell = 0
2455 11:53:43.982754 [0] MAX Duty = 5156%(X100), DQS PI = 6
2456 11:53:43.986386 [0] MIN Duty = 5031%(X100), DQS PI = 46
2457 11:53:43.986475 [0] AVG Duty = 5093%(X100)
2458 11:53:43.989845
2459 11:53:43.989933 ==DQM 1 ==
2460 11:53:43.993054 Final DQM duty delay cell = 0
2461 11:53:43.996064 [0] MAX Duty = 5031%(X100), DQS PI = 16
2462 11:53:43.999483 [0] MIN Duty = 4907%(X100), DQS PI = 34
2463 11:53:43.999579 [0] AVG Duty = 4969%(X100)
2464 11:53:44.002855
2465 11:53:44.006205 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2466 11:53:44.006312
2467 11:53:44.009720 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2468 11:53:44.013328 [DutyScan_Calibration_Flow] ====Done====
2469 11:53:44.013426
2470 11:53:44.016046 [DutyScan_Calibration_Flow] k_type=2
2471 11:53:44.032027
2472 11:53:44.032206 ==DQ 0 ==
2473 11:53:44.035479 Final DQ duty delay cell = -4
2474 11:53:44.039051 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2475 11:53:44.042037 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2476 11:53:44.045527 [-4] AVG Duty = 4984%(X100)
2477 11:53:44.045658
2478 11:53:44.045739 ==DQ 1 ==
2479 11:53:44.048705 Final DQ duty delay cell = 0
2480 11:53:44.052414 [0] MAX Duty = 5125%(X100), DQS PI = 20
2481 11:53:44.055370 [0] MIN Duty = 4969%(X100), DQS PI = 12
2482 11:53:44.055491 [0] AVG Duty = 5047%(X100)
2483 11:53:44.058669
2484 11:53:44.062024 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2485 11:53:44.062112
2486 11:53:44.065395 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2487 11:53:44.068615 [DutyScan_Calibration_Flow] ====Done====
2488 11:53:44.072075 nWR fixed to 30
2489 11:53:44.072188 [ModeRegInit_LP4] CH0 RK0
2490 11:53:44.075214 [ModeRegInit_LP4] CH0 RK1
2491 11:53:44.078698 [ModeRegInit_LP4] CH1 RK0
2492 11:53:44.081879 [ModeRegInit_LP4] CH1 RK1
2493 11:53:44.081992 match AC timing 7
2494 11:53:44.088747 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2495 11:53:44.092064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2496 11:53:44.095412 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2497 11:53:44.101982 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2498 11:53:44.105768 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2499 11:53:44.105873 ==
2500 11:53:44.109052 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 11:53:44.111945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 11:53:44.112052 ==
2503 11:53:44.118768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2504 11:53:44.125326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2505 11:53:44.132198 [CA 0] Center 39 (8~70) winsize 63
2506 11:53:44.136157 [CA 1] Center 39 (8~70) winsize 63
2507 11:53:44.139057 [CA 2] Center 35 (5~66) winsize 62
2508 11:53:44.142244 [CA 3] Center 34 (4~65) winsize 62
2509 11:53:44.145521 [CA 4] Center 33 (3~64) winsize 62
2510 11:53:44.148971 [CA 5] Center 32 (3~62) winsize 60
2511 11:53:44.149091
2512 11:53:44.152607 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2513 11:53:44.152719
2514 11:53:44.155921 [CATrainingPosCal] consider 1 rank data
2515 11:53:44.159285 u2DelayCellTimex100 = 270/100 ps
2516 11:53:44.162095 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2517 11:53:44.165712 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2518 11:53:44.172529 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2519 11:53:44.175567 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2520 11:53:44.179206 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2521 11:53:44.182255 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2522 11:53:44.182360
2523 11:53:44.186051 CA PerBit enable=1, Macro0, CA PI delay=32
2524 11:53:44.186141
2525 11:53:44.188887 [CBTSetCACLKResult] CA Dly = 32
2526 11:53:44.188979 CS Dly: 6 (0~37)
2527 11:53:44.189047 ==
2528 11:53:44.192807 Dram Type= 6, Freq= 0, CH_0, rank 1
2529 11:53:44.199141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 11:53:44.199295 ==
2531 11:53:44.202542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 11:53:44.209407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2533 11:53:44.217968 [CA 0] Center 38 (8~69) winsize 62
2534 11:53:44.221596 [CA 1] Center 38 (8~69) winsize 62
2535 11:53:44.224965 [CA 2] Center 35 (4~66) winsize 63
2536 11:53:44.228088 [CA 3] Center 34 (4~65) winsize 62
2537 11:53:44.231448 [CA 4] Center 33 (3~64) winsize 62
2538 11:53:44.235009 [CA 5] Center 32 (3~62) winsize 60
2539 11:53:44.235108
2540 11:53:44.238138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2541 11:53:44.238246
2542 11:53:44.241472 [CATrainingPosCal] consider 2 rank data
2543 11:53:44.245069 u2DelayCellTimex100 = 270/100 ps
2544 11:53:44.248259 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2545 11:53:44.251930 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2546 11:53:44.254670 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2547 11:53:44.261445 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2548 11:53:44.264748 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2549 11:53:44.268316 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2550 11:53:44.268420
2551 11:53:44.272277 CA PerBit enable=1, Macro0, CA PI delay=32
2552 11:53:44.272376
2553 11:53:44.274889 [CBTSetCACLKResult] CA Dly = 32
2554 11:53:44.274985 CS Dly: 6 (0~38)
2555 11:53:44.275053
2556 11:53:44.278261 ----->DramcWriteLeveling(PI) begin...
2557 11:53:44.278354 ==
2558 11:53:44.281602 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 11:53:44.288697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 11:53:44.288824 ==
2561 11:53:44.291729 Write leveling (Byte 0): 34 => 34
2562 11:53:44.295346 Write leveling (Byte 1): 29 => 29
2563 11:53:44.295450 DramcWriteLeveling(PI) end<-----
2564 11:53:44.295519
2565 11:53:44.298308 ==
2566 11:53:44.301709 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 11:53:44.305226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 11:53:44.305328 ==
2569 11:53:44.308511 [Gating] SW mode calibration
2570 11:53:44.315506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2571 11:53:44.318379 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2572 11:53:44.325165 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2573 11:53:44.328508 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2574 11:53:44.331727 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 11:53:44.338331 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 11:53:44.341896 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 11:53:44.345229 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 11:53:44.351731 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2579 11:53:44.355458 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2580 11:53:44.358696 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2581 11:53:44.365301 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 11:53:44.368492 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 11:53:44.371578 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 11:53:44.375230 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 11:53:44.382041 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 11:53:44.384934 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2587 11:53:44.388384 1 0 28 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2588 11:53:44.395106 1 1 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2589 11:53:44.398666 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 11:53:44.401519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 11:53:44.408470 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 11:53:44.412039 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 11:53:44.415771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 11:53:44.422235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 11:53:44.425707 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2596 11:53:44.428362 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2597 11:53:44.435125 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:53:44.438678 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:53:44.442255 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:53:44.445263 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:53:44.452032 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:53:44.455305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:53:44.458778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 11:53:44.465398 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 11:53:44.469138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 11:53:44.472300 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 11:53:44.478803 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 11:53:44.482002 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 11:53:44.485233 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:53:44.491935 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:53:44.495469 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2612 11:53:44.499128 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2613 11:53:44.501795 Total UI for P1: 0, mck2ui 16
2614 11:53:44.505322 best dqsien dly found for B0: ( 1, 3, 28)
2615 11:53:44.512344 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 11:53:44.512475 Total UI for P1: 0, mck2ui 16
2617 11:53:44.515414 best dqsien dly found for B1: ( 1, 4, 0)
2618 11:53:44.522027 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2619 11:53:44.525689 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2620 11:53:44.525794
2621 11:53:44.529188 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2622 11:53:44.532332 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2623 11:53:44.535168 [Gating] SW calibration Done
2624 11:53:44.535258 ==
2625 11:53:44.538556 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 11:53:44.542249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 11:53:44.542339 ==
2628 11:53:44.545860 RX Vref Scan: 0
2629 11:53:44.545950
2630 11:53:44.546017 RX Vref 0 -> 0, step: 1
2631 11:53:44.546079
2632 11:53:44.549039 RX Delay -40 -> 252, step: 8
2633 11:53:44.552159 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2634 11:53:44.555359 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2635 11:53:44.561918 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2636 11:53:44.565506 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2637 11:53:44.568809 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2638 11:53:44.571860 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2639 11:53:44.575531 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2640 11:53:44.582105 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2641 11:53:44.585913 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2642 11:53:44.588575 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2643 11:53:44.591947 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2644 11:53:44.595767 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2645 11:53:44.602054 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2646 11:53:44.605706 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2647 11:53:44.608686 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2648 11:53:44.611984 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2649 11:53:44.612113 ==
2650 11:53:44.615508 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:53:44.622200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:53:44.622312 ==
2653 11:53:44.622387 DQS Delay:
2654 11:53:44.622451 DQS0 = 0, DQS1 = 0
2655 11:53:44.625788 DQM Delay:
2656 11:53:44.625913 DQM0 = 121, DQM1 = 113
2657 11:53:44.628816 DQ Delay:
2658 11:53:44.632466 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2659 11:53:44.635581 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2660 11:53:44.638781 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2661 11:53:44.642096 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2662 11:53:44.642180
2663 11:53:44.642245
2664 11:53:44.642324 ==
2665 11:53:44.645563 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 11:53:44.648972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 11:53:44.649100 ==
2668 11:53:44.649199
2669 11:53:44.649307
2670 11:53:44.652466 TX Vref Scan disable
2671 11:53:44.655666 == TX Byte 0 ==
2672 11:53:44.658731 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2673 11:53:44.662316 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2674 11:53:44.665854 == TX Byte 1 ==
2675 11:53:44.668972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2676 11:53:44.672274 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2677 11:53:44.672380 ==
2678 11:53:44.675441 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 11:53:44.682329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 11:53:44.682436 ==
2681 11:53:44.693347 TX Vref=22, minBit 4, minWin=24, winSum=410
2682 11:53:44.696813 TX Vref=24, minBit 0, minWin=25, winSum=414
2683 11:53:44.699830 TX Vref=26, minBit 3, minWin=25, winSum=421
2684 11:53:44.702579 TX Vref=28, minBit 0, minWin=26, winSum=422
2685 11:53:44.706334 TX Vref=30, minBit 0, minWin=26, winSum=425
2686 11:53:44.709596 TX Vref=32, minBit 1, minWin=26, winSum=422
2687 11:53:44.716635 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2688 11:53:44.716756
2689 11:53:44.719436 Final TX Range 1 Vref 30
2690 11:53:44.719541
2691 11:53:44.719634 ==
2692 11:53:44.722652 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 11:53:44.726482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 11:53:44.726567 ==
2695 11:53:44.726634
2696 11:53:44.729998
2697 11:53:44.730075 TX Vref Scan disable
2698 11:53:44.733112 == TX Byte 0 ==
2699 11:53:44.736574 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2700 11:53:44.739453 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2701 11:53:44.743109 == TX Byte 1 ==
2702 11:53:44.746576 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2703 11:53:44.749838 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2704 11:53:44.749924
2705 11:53:44.752882 [DATLAT]
2706 11:53:44.752958 Freq=1200, CH0 RK0
2707 11:53:44.753021
2708 11:53:44.756524 DATLAT Default: 0xd
2709 11:53:44.756598 0, 0xFFFF, sum = 0
2710 11:53:44.759414 1, 0xFFFF, sum = 0
2711 11:53:44.759489 2, 0xFFFF, sum = 0
2712 11:53:44.762809 3, 0xFFFF, sum = 0
2713 11:53:44.762884 4, 0xFFFF, sum = 0
2714 11:53:44.766543 5, 0xFFFF, sum = 0
2715 11:53:44.766623 6, 0xFFFF, sum = 0
2716 11:53:44.769739 7, 0xFFFF, sum = 0
2717 11:53:44.769815 8, 0xFFFF, sum = 0
2718 11:53:44.773381 9, 0xFFFF, sum = 0
2719 11:53:44.776229 10, 0xFFFF, sum = 0
2720 11:53:44.776310 11, 0xFFFF, sum = 0
2721 11:53:44.776376 12, 0x0, sum = 1
2722 11:53:44.780032 13, 0x0, sum = 2
2723 11:53:44.780115 14, 0x0, sum = 3
2724 11:53:44.782902 15, 0x0, sum = 4
2725 11:53:44.782978 best_step = 13
2726 11:53:44.783047
2727 11:53:44.783108 ==
2728 11:53:44.786432 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 11:53:44.792831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 11:53:44.792919 ==
2731 11:53:44.792986 RX Vref Scan: 1
2732 11:53:44.793065
2733 11:53:44.796419 Set Vref Range= 32 -> 127
2734 11:53:44.796499
2735 11:53:44.800018 RX Vref 32 -> 127, step: 1
2736 11:53:44.800143
2737 11:53:44.802900 RX Delay -13 -> 252, step: 4
2738 11:53:44.802980
2739 11:53:44.806325 Set Vref, RX VrefLevel [Byte0]: 32
2740 11:53:44.806407 [Byte1]: 32
2741 11:53:44.811576
2742 11:53:44.811685 Set Vref, RX VrefLevel [Byte0]: 33
2743 11:53:44.814438 [Byte1]: 33
2744 11:53:44.819230
2745 11:53:44.819352 Set Vref, RX VrefLevel [Byte0]: 34
2746 11:53:44.822395 [Byte1]: 34
2747 11:53:44.827055
2748 11:53:44.827151 Set Vref, RX VrefLevel [Byte0]: 35
2749 11:53:44.830417 [Byte1]: 35
2750 11:53:44.835091
2751 11:53:44.835209 Set Vref, RX VrefLevel [Byte0]: 36
2752 11:53:44.838082 [Byte1]: 36
2753 11:53:44.842808
2754 11:53:44.842892 Set Vref, RX VrefLevel [Byte0]: 37
2755 11:53:44.845689 [Byte1]: 37
2756 11:53:44.850441
2757 11:53:44.850527 Set Vref, RX VrefLevel [Byte0]: 38
2758 11:53:44.854118 [Byte1]: 38
2759 11:53:44.858308
2760 11:53:44.858416 Set Vref, RX VrefLevel [Byte0]: 39
2761 11:53:44.861780 [Byte1]: 39
2762 11:53:44.866401
2763 11:53:44.866511 Set Vref, RX VrefLevel [Byte0]: 40
2764 11:53:44.869977 [Byte1]: 40
2765 11:53:44.874115
2766 11:53:44.874227 Set Vref, RX VrefLevel [Byte0]: 41
2767 11:53:44.877629 [Byte1]: 41
2768 11:53:44.882410
2769 11:53:44.882495 Set Vref, RX VrefLevel [Byte0]: 42
2770 11:53:44.885514 [Byte1]: 42
2771 11:53:44.889830
2772 11:53:44.889943 Set Vref, RX VrefLevel [Byte0]: 43
2773 11:53:44.893289 [Byte1]: 43
2774 11:53:44.897882
2775 11:53:44.898000 Set Vref, RX VrefLevel [Byte0]: 44
2776 11:53:44.901348 [Byte1]: 44
2777 11:53:44.905594
2778 11:53:44.905683 Set Vref, RX VrefLevel [Byte0]: 45
2779 11:53:44.908855 [Byte1]: 45
2780 11:53:44.913521
2781 11:53:44.913629 Set Vref, RX VrefLevel [Byte0]: 46
2782 11:53:44.917054 [Byte1]: 46
2783 11:53:44.921573
2784 11:53:44.921680 Set Vref, RX VrefLevel [Byte0]: 47
2785 11:53:44.924672 [Byte1]: 47
2786 11:53:44.929614
2787 11:53:44.929714 Set Vref, RX VrefLevel [Byte0]: 48
2788 11:53:44.932587 [Byte1]: 48
2789 11:53:44.937171
2790 11:53:44.937275 Set Vref, RX VrefLevel [Byte0]: 49
2791 11:53:44.940818 [Byte1]: 49
2792 11:53:44.945494
2793 11:53:44.945622 Set Vref, RX VrefLevel [Byte0]: 50
2794 11:53:44.948390 [Byte1]: 50
2795 11:53:44.953196
2796 11:53:44.953276 Set Vref, RX VrefLevel [Byte0]: 51
2797 11:53:44.956656 [Byte1]: 51
2798 11:53:44.960903
2799 11:53:44.960986 Set Vref, RX VrefLevel [Byte0]: 52
2800 11:53:44.964624 [Byte1]: 52
2801 11:53:44.969169
2802 11:53:44.969247 Set Vref, RX VrefLevel [Byte0]: 53
2803 11:53:44.972020 [Byte1]: 53
2804 11:53:44.976643
2805 11:53:44.976758 Set Vref, RX VrefLevel [Byte0]: 54
2806 11:53:44.980100 [Byte1]: 54
2807 11:53:44.984587
2808 11:53:44.984668 Set Vref, RX VrefLevel [Byte0]: 55
2809 11:53:44.988279 [Byte1]: 55
2810 11:53:44.992557
2811 11:53:44.992662 Set Vref, RX VrefLevel [Byte0]: 56
2812 11:53:44.996149 [Byte1]: 56
2813 11:53:45.000221
2814 11:53:45.000300 Set Vref, RX VrefLevel [Byte0]: 57
2815 11:53:45.003810 [Byte1]: 57
2816 11:53:45.008534
2817 11:53:45.008617 Set Vref, RX VrefLevel [Byte0]: 58
2818 11:53:45.011708 [Byte1]: 58
2819 11:53:45.015941
2820 11:53:45.016023 Set Vref, RX VrefLevel [Byte0]: 59
2821 11:53:45.019565 [Byte1]: 59
2822 11:53:45.024346
2823 11:53:45.024438 Set Vref, RX VrefLevel [Byte0]: 60
2824 11:53:45.027211 [Byte1]: 60
2825 11:53:45.031866
2826 11:53:45.031962 Set Vref, RX VrefLevel [Byte0]: 61
2827 11:53:45.035528 [Byte1]: 61
2828 11:53:45.039747
2829 11:53:45.039850 Set Vref, RX VrefLevel [Byte0]: 62
2830 11:53:45.043519 [Byte1]: 62
2831 11:53:45.047690
2832 11:53:45.047797 Set Vref, RX VrefLevel [Byte0]: 63
2833 11:53:45.050934 [Byte1]: 63
2834 11:53:45.055619
2835 11:53:45.055744 Set Vref, RX VrefLevel [Byte0]: 64
2836 11:53:45.059434 [Byte1]: 64
2837 11:53:45.063950
2838 11:53:45.064053 Set Vref, RX VrefLevel [Byte0]: 65
2839 11:53:45.066869 [Byte1]: 65
2840 11:53:45.071286
2841 11:53:45.071383 Set Vref, RX VrefLevel [Byte0]: 66
2842 11:53:45.074647 [Byte1]: 66
2843 11:53:45.079484
2844 11:53:45.079581 Set Vref, RX VrefLevel [Byte0]: 67
2845 11:53:45.082719 [Byte1]: 67
2846 11:53:45.087153
2847 11:53:45.087244 Set Vref, RX VrefLevel [Byte0]: 68
2848 11:53:45.091085 [Byte1]: 68
2849 11:53:45.095385
2850 11:53:45.095477 Set Vref, RX VrefLevel [Byte0]: 69
2851 11:53:45.098643 [Byte1]: 69
2852 11:53:45.102863
2853 11:53:45.102958 Final RX Vref Byte 0 = 55 to rank0
2854 11:53:45.106468 Final RX Vref Byte 1 = 58 to rank0
2855 11:53:45.109673 Final RX Vref Byte 0 = 55 to rank1
2856 11:53:45.112784 Final RX Vref Byte 1 = 58 to rank1==
2857 11:53:45.116423 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 11:53:45.122728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 11:53:45.122869 ==
2860 11:53:45.122972 DQS Delay:
2861 11:53:45.123040 DQS0 = 0, DQS1 = 0
2862 11:53:45.126706 DQM Delay:
2863 11:53:45.126805 DQM0 = 120, DQM1 = 114
2864 11:53:45.129626 DQ Delay:
2865 11:53:45.133169 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2866 11:53:45.136675 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2867 11:53:45.139976 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =106
2868 11:53:45.143100 DQ12 =120, DQ13 =120, DQ14 =128, DQ15 =124
2869 11:53:45.143181
2870 11:53:45.143245
2871 11:53:45.149763 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2872 11:53:45.152978 CH0 RK0: MR19=404, MR18=130C
2873 11:53:45.159979 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2874 11:53:45.160079
2875 11:53:45.163488 ----->DramcWriteLeveling(PI) begin...
2876 11:53:45.163572 ==
2877 11:53:45.166616 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 11:53:45.169643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 11:53:45.173370 ==
2880 11:53:45.173471 Write leveling (Byte 0): 34 => 34
2881 11:53:45.176252 Write leveling (Byte 1): 29 => 29
2882 11:53:45.179763 DramcWriteLeveling(PI) end<-----
2883 11:53:45.179855
2884 11:53:45.179921 ==
2885 11:53:45.183354 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 11:53:45.189646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 11:53:45.189778 ==
2888 11:53:45.193526 [Gating] SW mode calibration
2889 11:53:45.200128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 11:53:45.203034 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 11:53:45.206684 0 15 0 | B1->B0 | 3333 302f | 1 1 | (1 1) (0 0)
2892 11:53:45.213432 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 11:53:45.216396 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 11:53:45.219883 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 11:53:45.226746 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 11:53:45.229795 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 11:53:45.233427 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 11:53:45.240095 0 15 28 | B1->B0 | 2e2e 2b2b | 1 0 | (1 0) (0 0)
2899 11:53:45.243543 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
2900 11:53:45.246936 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 11:53:45.253600 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 11:53:45.256667 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 11:53:45.260608 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 11:53:45.267482 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 11:53:45.270270 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 11:53:45.274054 1 0 28 | B1->B0 | 3a3a 3a39 | 0 1 | (0 0) (0 0)
2907 11:53:45.276820 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2908 11:53:45.283380 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 11:53:45.286664 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 11:53:45.290354 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 11:53:45.296608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 11:53:45.300105 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 11:53:45.303631 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 11:53:45.310297 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2915 11:53:45.313788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 11:53:45.316825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 11:53:45.323790 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 11:53:45.327427 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 11:53:45.330624 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:53:45.337323 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 11:53:45.340188 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 11:53:45.343910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 11:53:45.347161 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 11:53:45.353997 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:53:45.356981 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:53:45.360601 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:53:45.367223 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:53:45.370146 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:53:45.373985 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:53:45.380462 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2931 11:53:45.383624 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2932 11:53:45.387503 Total UI for P1: 0, mck2ui 16
2933 11:53:45.391008 best dqsien dly found for B1: ( 1, 3, 28)
2934 11:53:45.393643 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 11:53:45.396795 Total UI for P1: 0, mck2ui 16
2936 11:53:45.400259 best dqsien dly found for B0: ( 1, 3, 30)
2937 11:53:45.403961 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2938 11:53:45.406853 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2939 11:53:45.406941
2940 11:53:45.413767 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2941 11:53:45.417114 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2942 11:53:45.417199 [Gating] SW calibration Done
2943 11:53:45.420143 ==
2944 11:53:45.420227 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 11:53:45.427226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 11:53:45.427364 ==
2947 11:53:45.427464 RX Vref Scan: 0
2948 11:53:45.427558
2949 11:53:45.430541 RX Vref 0 -> 0, step: 1
2950 11:53:45.430654
2951 11:53:45.433768 RX Delay -40 -> 252, step: 8
2952 11:53:45.437277 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2953 11:53:45.440354 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2954 11:53:45.443733 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2955 11:53:45.450376 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2956 11:53:45.454441 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2957 11:53:45.457441 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2958 11:53:45.460995 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 11:53:45.464298 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2960 11:53:45.467630 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
2961 11:53:45.474386 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2962 11:53:45.477207 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2963 11:53:45.480861 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2964 11:53:45.484001 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2965 11:53:45.487652 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2966 11:53:45.494360 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2967 11:53:45.497373 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2968 11:53:45.497465 ==
2969 11:53:45.501109 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 11:53:45.504159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 11:53:45.504244 ==
2972 11:53:45.507707 DQS Delay:
2973 11:53:45.507790 DQS0 = 0, DQS1 = 0
2974 11:53:45.507855 DQM Delay:
2975 11:53:45.510810 DQM0 = 122, DQM1 = 114
2976 11:53:45.510891 DQ Delay:
2977 11:53:45.514062 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2978 11:53:45.517654 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2979 11:53:45.520591 DQ8 =107, DQ9 =99, DQ10 =115, DQ11 =107
2980 11:53:45.527275 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2981 11:53:45.527409
2982 11:53:45.527506
2983 11:53:45.527585 ==
2984 11:53:45.531030 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 11:53:45.534372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 11:53:45.534457 ==
2987 11:53:45.534529
2988 11:53:45.534593
2989 11:53:45.537554 TX Vref Scan disable
2990 11:53:45.537648 == TX Byte 0 ==
2991 11:53:45.544087 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2992 11:53:45.547715 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2993 11:53:45.547806 == TX Byte 1 ==
2994 11:53:45.554401 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2995 11:53:45.557677 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2996 11:53:45.557762 ==
2997 11:53:45.560838 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 11:53:45.564608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 11:53:45.564700 ==
3000 11:53:45.577457 TX Vref=22, minBit 1, minWin=24, winSum=408
3001 11:53:45.580576 TX Vref=24, minBit 3, minWin=25, winSum=417
3002 11:53:45.583867 TX Vref=26, minBit 3, minWin=25, winSum=420
3003 11:53:45.587701 TX Vref=28, minBit 3, minWin=26, winSum=426
3004 11:53:45.590416 TX Vref=30, minBit 1, minWin=26, winSum=424
3005 11:53:45.594315 TX Vref=32, minBit 12, minWin=25, winSum=425
3006 11:53:45.600655 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 28
3007 11:53:45.600761
3008 11:53:45.603970 Final TX Range 1 Vref 28
3009 11:53:45.604057
3010 11:53:45.604124 ==
3011 11:53:45.607478 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 11:53:45.610730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 11:53:45.610815 ==
3014 11:53:45.610889
3015 11:53:45.614363
3016 11:53:45.614439 TX Vref Scan disable
3017 11:53:45.617675 == TX Byte 0 ==
3018 11:53:45.620773 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3019 11:53:45.623896 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3020 11:53:45.627719 == TX Byte 1 ==
3021 11:53:45.630649 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3022 11:53:45.634060 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3023 11:53:45.634153
3024 11:53:45.637603 [DATLAT]
3025 11:53:45.637686 Freq=1200, CH0 RK1
3026 11:53:45.637754
3027 11:53:45.640753 DATLAT Default: 0xd
3028 11:53:45.640829 0, 0xFFFF, sum = 0
3029 11:53:45.644307 1, 0xFFFF, sum = 0
3030 11:53:45.644381 2, 0xFFFF, sum = 0
3031 11:53:45.647492 3, 0xFFFF, sum = 0
3032 11:53:45.647577 4, 0xFFFF, sum = 0
3033 11:53:45.651124 5, 0xFFFF, sum = 0
3034 11:53:45.651204 6, 0xFFFF, sum = 0
3035 11:53:45.654183 7, 0xFFFF, sum = 0
3036 11:53:45.654269 8, 0xFFFF, sum = 0
3037 11:53:45.657424 9, 0xFFFF, sum = 0
3038 11:53:45.657501 10, 0xFFFF, sum = 0
3039 11:53:45.660889 11, 0xFFFF, sum = 0
3040 11:53:45.664099 12, 0x0, sum = 1
3041 11:53:45.664178 13, 0x0, sum = 2
3042 11:53:45.664244 14, 0x0, sum = 3
3043 11:53:45.667603 15, 0x0, sum = 4
3044 11:53:45.667679 best_step = 13
3045 11:53:45.667742
3046 11:53:45.667810 ==
3047 11:53:45.670757 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 11:53:45.677354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 11:53:45.677455 ==
3050 11:53:45.677530 RX Vref Scan: 0
3051 11:53:45.677603
3052 11:53:45.681568 RX Vref 0 -> 0, step: 1
3053 11:53:45.681662
3054 11:53:45.684449 RX Delay -13 -> 252, step: 4
3055 11:53:45.687879 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3056 11:53:45.690767 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3057 11:53:45.697716 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3058 11:53:45.700962 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3059 11:53:45.704747 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3060 11:53:45.707451 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3061 11:53:45.710971 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3062 11:53:45.717673 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3063 11:53:45.720579 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3064 11:53:45.724218 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3065 11:53:45.727445 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3066 11:53:45.730526 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3067 11:53:45.737296 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3068 11:53:45.740980 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3069 11:53:45.744346 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3070 11:53:45.747368 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3071 11:53:45.747459 ==
3072 11:53:45.750692 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 11:53:45.757277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 11:53:45.757373 ==
3075 11:53:45.757442 DQS Delay:
3076 11:53:45.757504 DQS0 = 0, DQS1 = 0
3077 11:53:45.760523 DQM Delay:
3078 11:53:45.760622 DQM0 = 121, DQM1 = 112
3079 11:53:45.763968 DQ Delay:
3080 11:53:45.767568 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3081 11:53:45.770575 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3082 11:53:45.774257 DQ8 =102, DQ9 =98, DQ10 =114, DQ11 =104
3083 11:53:45.777350 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3084 11:53:45.777444
3085 11:53:45.777510
3086 11:53:45.784145 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3087 11:53:45.787876 CH0 RK1: MR19=403, MR18=DEE
3088 11:53:45.793904 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3089 11:53:45.797592 [RxdqsGatingPostProcess] freq 1200
3090 11:53:45.804616 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 11:53:45.804728 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 11:53:45.808111 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 11:53:45.810979 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 11:53:45.814181 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 11:53:45.817649 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 11:53:45.820785 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 11:53:45.824735 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 11:53:45.827969 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 11:53:45.831198 Pre-setting of DQS Precalculation
3100 11:53:45.834097 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 11:53:45.837826 ==
3102 11:53:45.841083 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 11:53:45.843970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 11:53:45.844053 ==
3105 11:53:45.847508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 11:53:45.854105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 11:53:45.863162 [CA 0] Center 37 (7~68) winsize 62
3108 11:53:45.866843 [CA 1] Center 37 (7~68) winsize 62
3109 11:53:45.870357 [CA 2] Center 35 (5~65) winsize 61
3110 11:53:45.873671 [CA 3] Center 34 (4~64) winsize 61
3111 11:53:45.876961 [CA 4] Center 34 (4~64) winsize 61
3112 11:53:45.880042 [CA 5] Center 33 (3~63) winsize 61
3113 11:53:45.880125
3114 11:53:45.883677 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3115 11:53:45.883756
3116 11:53:45.886693 [CATrainingPosCal] consider 1 rank data
3117 11:53:45.890313 u2DelayCellTimex100 = 270/100 ps
3118 11:53:45.893506 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 11:53:45.897235 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 11:53:45.903355 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3121 11:53:45.907052 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 11:53:45.910085 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 11:53:45.913537 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 11:53:45.913626
3125 11:53:45.916893 CA PerBit enable=1, Macro0, CA PI delay=33
3126 11:53:45.916974
3127 11:53:45.920102 [CBTSetCACLKResult] CA Dly = 33
3128 11:53:45.920188 CS Dly: 8 (0~39)
3129 11:53:45.920254 ==
3130 11:53:45.923486 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 11:53:45.931410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 11:53:45.931525 ==
3133 11:53:45.933774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 11:53:45.939997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 11:53:45.949100 [CA 0] Center 37 (7~68) winsize 62
3136 11:53:45.952333 [CA 1] Center 37 (7~68) winsize 62
3137 11:53:45.956042 [CA 2] Center 35 (5~65) winsize 61
3138 11:53:45.959367 [CA 3] Center 34 (4~65) winsize 62
3139 11:53:45.962345 [CA 4] Center 34 (4~65) winsize 62
3140 11:53:45.966182 [CA 5] Center 34 (4~64) winsize 61
3141 11:53:45.966273
3142 11:53:45.969289 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3143 11:53:45.969377
3144 11:53:45.972857 [CATrainingPosCal] consider 2 rank data
3145 11:53:45.975890 u2DelayCellTimex100 = 270/100 ps
3146 11:53:45.979562 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 11:53:45.982913 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 11:53:45.986077 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3149 11:53:45.992632 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 11:53:45.996172 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 11:53:45.999010 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3152 11:53:45.999103
3153 11:53:46.002721 CA PerBit enable=1, Macro0, CA PI delay=33
3154 11:53:46.002827
3155 11:53:46.005598 [CBTSetCACLKResult] CA Dly = 33
3156 11:53:46.005684 CS Dly: 9 (0~41)
3157 11:53:46.005751
3158 11:53:46.009419 ----->DramcWriteLeveling(PI) begin...
3159 11:53:46.012275 ==
3160 11:53:46.012363 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 11:53:46.019190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 11:53:46.019288 ==
3163 11:53:46.022801 Write leveling (Byte 0): 25 => 25
3164 11:53:46.025909 Write leveling (Byte 1): 27 => 27
3165 11:53:46.025997 DramcWriteLeveling(PI) end<-----
3166 11:53:46.029465
3167 11:53:46.029592 ==
3168 11:53:46.032506 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 11:53:46.036154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 11:53:46.036265 ==
3171 11:53:46.039320 [Gating] SW mode calibration
3172 11:53:46.045699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 11:53:46.049335 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 11:53:46.055709 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 11:53:46.059860 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 11:53:46.062716 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 11:53:46.069225 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 11:53:46.072332 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 11:53:46.076032 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 11:53:46.082454 0 15 24 | B1->B0 | 3131 3030 | 1 1 | (1 1) (1 0)
3181 11:53:46.085956 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3182 11:53:46.089676 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 11:53:46.095741 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 11:53:46.099523 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 11:53:46.102549 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 11:53:46.109388 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 11:53:46.112603 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 11:53:46.116044 1 0 24 | B1->B0 | 3636 4444 | 1 0 | (0 0) (0 0)
3189 11:53:46.122504 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 11:53:46.126084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 11:53:46.129055 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 11:53:46.132843 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 11:53:46.139352 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 11:53:46.143116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 11:53:46.146138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 11:53:46.152458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3197 11:53:46.156091 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 11:53:46.159196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 11:53:46.165870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 11:53:46.169310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 11:53:46.172878 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 11:53:46.179398 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 11:53:46.182397 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 11:53:46.185601 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 11:53:46.192594 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 11:53:46.196377 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 11:53:46.199356 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:53:46.206181 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:53:46.209398 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:53:46.212520 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:53:46.215988 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3212 11:53:46.222566 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 11:53:46.226186 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 11:53:46.229120 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 11:53:46.232966 Total UI for P1: 0, mck2ui 16
3216 11:53:46.236534 best dqsien dly found for B0: ( 1, 3, 24)
3217 11:53:46.239408 Total UI for P1: 0, mck2ui 16
3218 11:53:46.242571 best dqsien dly found for B1: ( 1, 3, 24)
3219 11:53:46.246244 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3220 11:53:46.249405 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3221 11:53:46.249511
3222 11:53:46.256168 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3223 11:53:46.259830 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3224 11:53:46.259937 [Gating] SW calibration Done
3225 11:53:46.262841 ==
3226 11:53:46.266008 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 11:53:46.269698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 11:53:46.269811 ==
3229 11:53:46.269882 RX Vref Scan: 0
3230 11:53:46.269962
3231 11:53:46.273414 RX Vref 0 -> 0, step: 1
3232 11:53:46.273521
3233 11:53:46.276130 RX Delay -40 -> 252, step: 8
3234 11:53:46.279520 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3235 11:53:46.283115 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3236 11:53:46.286160 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3237 11:53:46.293249 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3238 11:53:46.296284 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3239 11:53:46.300001 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3240 11:53:46.303371 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3241 11:53:46.306176 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3242 11:53:46.313094 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3243 11:53:46.316177 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3244 11:53:46.319782 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3245 11:53:46.323357 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3246 11:53:46.326666 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3247 11:53:46.333602 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3248 11:53:46.336350 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3249 11:53:46.339628 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3250 11:53:46.339737 ==
3251 11:53:46.343262 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 11:53:46.346893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 11:53:46.346978 ==
3254 11:53:46.350015 DQS Delay:
3255 11:53:46.350093 DQS0 = 0, DQS1 = 0
3256 11:53:46.350159 DQM Delay:
3257 11:53:46.353342 DQM0 = 119, DQM1 = 116
3258 11:53:46.353419 DQ Delay:
3259 11:53:46.357007 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3260 11:53:46.359963 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3261 11:53:46.366796 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3262 11:53:46.369708 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3263 11:53:46.369802
3264 11:53:46.369869
3265 11:53:46.369931 ==
3266 11:53:46.373613 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 11:53:46.376882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 11:53:46.376972 ==
3269 11:53:46.377039
3270 11:53:46.377101
3271 11:53:46.379698 TX Vref Scan disable
3272 11:53:46.379808 == TX Byte 0 ==
3273 11:53:46.386866 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3274 11:53:46.390038 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3275 11:53:46.390145 == TX Byte 1 ==
3276 11:53:46.396641 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3277 11:53:46.399650 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3278 11:53:46.399756 ==
3279 11:53:46.403365 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 11:53:46.406897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 11:53:46.407002 ==
3282 11:53:46.419217 TX Vref=22, minBit 11, minWin=24, winSum=409
3283 11:53:46.422985 TX Vref=24, minBit 9, minWin=25, winSum=415
3284 11:53:46.425935 TX Vref=26, minBit 1, minWin=25, winSum=421
3285 11:53:46.429185 TX Vref=28, minBit 9, minWin=25, winSum=426
3286 11:53:46.432951 TX Vref=30, minBit 9, minWin=25, winSum=429
3287 11:53:46.436166 TX Vref=32, minBit 9, minWin=26, winSum=427
3288 11:53:46.442559 [TxChooseVref] Worse bit 9, Min win 26, Win sum 427, Final Vref 32
3289 11:53:46.442655
3290 11:53:46.445656 Final TX Range 1 Vref 32
3291 11:53:46.445743
3292 11:53:46.445809 ==
3293 11:53:46.449312 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 11:53:46.452833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 11:53:46.452921 ==
3296 11:53:46.455966
3297 11:53:46.456052
3298 11:53:46.456118 TX Vref Scan disable
3299 11:53:46.459380 == TX Byte 0 ==
3300 11:53:46.463022 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3301 11:53:46.466237 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3302 11:53:46.469303 == TX Byte 1 ==
3303 11:53:46.472768 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 11:53:46.476060 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 11:53:46.476171
3306 11:53:46.479185 [DATLAT]
3307 11:53:46.479266 Freq=1200, CH1 RK0
3308 11:53:46.479355
3309 11:53:46.482924 DATLAT Default: 0xd
3310 11:53:46.483013 0, 0xFFFF, sum = 0
3311 11:53:46.486147 1, 0xFFFF, sum = 0
3312 11:53:46.486226 2, 0xFFFF, sum = 0
3313 11:53:46.489638 3, 0xFFFF, sum = 0
3314 11:53:46.489750 4, 0xFFFF, sum = 0
3315 11:53:46.493003 5, 0xFFFF, sum = 0
3316 11:53:46.493090 6, 0xFFFF, sum = 0
3317 11:53:46.495889 7, 0xFFFF, sum = 0
3318 11:53:46.495966 8, 0xFFFF, sum = 0
3319 11:53:46.499800 9, 0xFFFF, sum = 0
3320 11:53:46.502709 10, 0xFFFF, sum = 0
3321 11:53:46.502788 11, 0xFFFF, sum = 0
3322 11:53:46.505867 12, 0x0, sum = 1
3323 11:53:46.505944 13, 0x0, sum = 2
3324 11:53:46.506029 14, 0x0, sum = 3
3325 11:53:46.509653 15, 0x0, sum = 4
3326 11:53:46.509731 best_step = 13
3327 11:53:46.509816
3328 11:53:46.509897 ==
3329 11:53:46.512593 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 11:53:46.519674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 11:53:46.519772 ==
3332 11:53:46.519842 RX Vref Scan: 1
3333 11:53:46.519905
3334 11:53:46.522721 Set Vref Range= 32 -> 127
3335 11:53:46.522807
3336 11:53:46.526538 RX Vref 32 -> 127, step: 1
3337 11:53:46.526627
3338 11:53:46.529740 RX Delay -5 -> 252, step: 4
3339 11:53:46.529835
3340 11:53:46.533044 Set Vref, RX VrefLevel [Byte0]: 32
3341 11:53:46.536074 [Byte1]: 32
3342 11:53:46.536164
3343 11:53:46.539760 Set Vref, RX VrefLevel [Byte0]: 33
3344 11:53:46.542692 [Byte1]: 33
3345 11:53:46.542772
3346 11:53:46.546300 Set Vref, RX VrefLevel [Byte0]: 34
3347 11:53:46.549280 [Byte1]: 34
3348 11:53:46.553751
3349 11:53:46.553858 Set Vref, RX VrefLevel [Byte0]: 35
3350 11:53:46.556580 [Byte1]: 35
3351 11:53:46.561139
3352 11:53:46.561229 Set Vref, RX VrefLevel [Byte0]: 36
3353 11:53:46.564412 [Byte1]: 36
3354 11:53:46.568802
3355 11:53:46.568899 Set Vref, RX VrefLevel [Byte0]: 37
3356 11:53:46.572618 [Byte1]: 37
3357 11:53:46.577140
3358 11:53:46.577222 Set Vref, RX VrefLevel [Byte0]: 38
3359 11:53:46.580046 [Byte1]: 38
3360 11:53:46.585121
3361 11:53:46.585217 Set Vref, RX VrefLevel [Byte0]: 39
3362 11:53:46.588037 [Byte1]: 39
3363 11:53:46.592263
3364 11:53:46.592341 Set Vref, RX VrefLevel [Byte0]: 40
3365 11:53:46.595758 [Byte1]: 40
3366 11:53:46.600365
3367 11:53:46.600448 Set Vref, RX VrefLevel [Byte0]: 41
3368 11:53:46.603712 [Byte1]: 41
3369 11:53:46.608238
3370 11:53:46.608329 Set Vref, RX VrefLevel [Byte0]: 42
3371 11:53:46.611600 [Byte1]: 42
3372 11:53:46.616153
3373 11:53:46.616263 Set Vref, RX VrefLevel [Byte0]: 43
3374 11:53:46.619250 [Byte1]: 43
3375 11:53:46.623848
3376 11:53:46.623929 Set Vref, RX VrefLevel [Byte0]: 44
3377 11:53:46.627500 [Byte1]: 44
3378 11:53:46.631756
3379 11:53:46.631837 Set Vref, RX VrefLevel [Byte0]: 45
3380 11:53:46.635231 [Byte1]: 45
3381 11:53:46.639313
3382 11:53:46.639390 Set Vref, RX VrefLevel [Byte0]: 46
3383 11:53:46.643000 [Byte1]: 46
3384 11:53:46.647218
3385 11:53:46.647296 Set Vref, RX VrefLevel [Byte0]: 47
3386 11:53:46.650874 [Byte1]: 47
3387 11:53:46.655253
3388 11:53:46.655329 Set Vref, RX VrefLevel [Byte0]: 48
3389 11:53:46.658914 [Byte1]: 48
3390 11:53:46.663352
3391 11:53:46.663521 Set Vref, RX VrefLevel [Byte0]: 49
3392 11:53:46.666650 [Byte1]: 49
3393 11:53:46.671489
3394 11:53:46.671619 Set Vref, RX VrefLevel [Byte0]: 50
3395 11:53:46.674306 [Byte1]: 50
3396 11:53:46.678698
3397 11:53:46.678859 Set Vref, RX VrefLevel [Byte0]: 51
3398 11:53:46.682223 [Byte1]: 51
3399 11:53:46.686846
3400 11:53:46.686971 Set Vref, RX VrefLevel [Byte0]: 52
3401 11:53:46.690058 [Byte1]: 52
3402 11:53:46.695008
3403 11:53:46.695106 Set Vref, RX VrefLevel [Byte0]: 53
3404 11:53:46.697778 [Byte1]: 53
3405 11:53:46.703060
3406 11:53:46.703186 Set Vref, RX VrefLevel [Byte0]: 54
3407 11:53:46.705522 [Byte1]: 54
3408 11:53:46.710353
3409 11:53:46.710483 Set Vref, RX VrefLevel [Byte0]: 55
3410 11:53:46.713741 [Byte1]: 55
3411 11:53:46.717890
3412 11:53:46.717976 Set Vref, RX VrefLevel [Byte0]: 56
3413 11:53:46.721276 [Byte1]: 56
3414 11:53:46.726279
3415 11:53:46.726370 Set Vref, RX VrefLevel [Byte0]: 57
3416 11:53:46.729570 [Byte1]: 57
3417 11:53:46.734011
3418 11:53:46.734098 Set Vref, RX VrefLevel [Byte0]: 58
3419 11:53:46.737125 [Byte1]: 58
3420 11:53:46.741650
3421 11:53:46.741756 Set Vref, RX VrefLevel [Byte0]: 59
3422 11:53:46.744853 [Byte1]: 59
3423 11:53:46.749715
3424 11:53:46.749803 Set Vref, RX VrefLevel [Byte0]: 60
3425 11:53:46.752735 [Byte1]: 60
3426 11:53:46.757208
3427 11:53:46.757292 Set Vref, RX VrefLevel [Byte0]: 61
3428 11:53:46.760675 [Byte1]: 61
3429 11:53:46.765904
3430 11:53:46.765989 Set Vref, RX VrefLevel [Byte0]: 62
3431 11:53:46.768600 [Byte1]: 62
3432 11:53:46.772871
3433 11:53:46.772989 Set Vref, RX VrefLevel [Byte0]: 63
3434 11:53:46.776491 [Byte1]: 63
3435 11:53:46.781004
3436 11:53:46.781092 Set Vref, RX VrefLevel [Byte0]: 64
3437 11:53:46.784070 [Byte1]: 64
3438 11:53:46.788737
3439 11:53:46.788849 Set Vref, RX VrefLevel [Byte0]: 65
3440 11:53:46.792127 [Byte1]: 65
3441 11:53:46.796810
3442 11:53:46.796917 Set Vref, RX VrefLevel [Byte0]: 66
3443 11:53:46.799779 [Byte1]: 66
3444 11:53:46.804261
3445 11:53:46.804346 Set Vref, RX VrefLevel [Byte0]: 67
3446 11:53:46.807646 [Byte1]: 67
3447 11:53:46.812353
3448 11:53:46.812441 Set Vref, RX VrefLevel [Byte0]: 68
3449 11:53:46.815435 [Byte1]: 68
3450 11:53:46.820322
3451 11:53:46.820410 Set Vref, RX VrefLevel [Byte0]: 69
3452 11:53:46.823827 [Byte1]: 69
3453 11:53:46.828406
3454 11:53:46.828508 Final RX Vref Byte 0 = 54 to rank0
3455 11:53:46.831532 Final RX Vref Byte 1 = 52 to rank0
3456 11:53:46.835543 Final RX Vref Byte 0 = 54 to rank1
3457 11:53:46.838296 Final RX Vref Byte 1 = 52 to rank1==
3458 11:53:46.841479 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 11:53:46.844763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 11:53:46.848187 ==
3461 11:53:46.848297 DQS Delay:
3462 11:53:46.848395 DQS0 = 0, DQS1 = 0
3463 11:53:46.851229 DQM Delay:
3464 11:53:46.851329 DQM0 = 120, DQM1 = 117
3465 11:53:46.854997 DQ Delay:
3466 11:53:46.858351 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3467 11:53:46.861542 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3468 11:53:46.865219 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3469 11:53:46.868542 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3470 11:53:46.868656
3471 11:53:46.868755
3472 11:53:46.874714 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3473 11:53:46.878377 CH1 RK0: MR19=404, MR18=315
3474 11:53:46.885075 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27
3475 11:53:46.885192
3476 11:53:46.888176 ----->DramcWriteLeveling(PI) begin...
3477 11:53:46.888264 ==
3478 11:53:46.891717 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 11:53:46.894729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 11:53:46.894816 ==
3481 11:53:46.898420 Write leveling (Byte 0): 26 => 26
3482 11:53:46.901357 Write leveling (Byte 1): 29 => 29
3483 11:53:46.904893 DramcWriteLeveling(PI) end<-----
3484 11:53:46.904986
3485 11:53:46.905053 ==
3486 11:53:46.908315 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:53:46.911608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:53:46.915050 ==
3489 11:53:46.915133 [Gating] SW mode calibration
3490 11:53:46.921764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 11:53:46.928652 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 11:53:46.931505 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 11:53:46.938251 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 11:53:46.941640 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 11:53:46.945282 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 11:53:46.951722 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 11:53:46.954881 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 11:53:46.958623 0 15 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 1)
3499 11:53:46.965151 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3500 11:53:46.968246 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 11:53:46.972007 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 11:53:46.975282 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 11:53:46.982115 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 11:53:46.985152 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:53:46.988683 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3506 11:53:46.995331 1 0 24 | B1->B0 | 3e3e 2b2b | 0 1 | (0 0) (0 0)
3507 11:53:46.998266 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 11:53:47.001679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 11:53:47.008288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 11:53:47.011734 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:53:47.015534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 11:53:47.021791 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:53:47.024841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3514 11:53:47.028570 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 11:53:47.035354 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3516 11:53:47.038732 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 11:53:47.041762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:53:47.048141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:53:47.051926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:53:47.055085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:53:47.061549 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:53:47.065284 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:53:47.068198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:53:47.071739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:53:47.078798 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:53:47.082036 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:53:47.085096 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:53:47.092005 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:53:47.094904 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3530 11:53:47.098126 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3531 11:53:47.104514 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3532 11:53:47.108144 Total UI for P1: 0, mck2ui 16
3533 11:53:47.111541 best dqsien dly found for B1: ( 1, 3, 22)
3534 11:53:47.114880 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:53:47.117843 Total UI for P1: 0, mck2ui 16
3536 11:53:47.121095 best dqsien dly found for B0: ( 1, 3, 28)
3537 11:53:47.124614 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3538 11:53:47.127905 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3539 11:53:47.128020
3540 11:53:47.131364 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3541 11:53:47.134848 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3542 11:53:47.138058 [Gating] SW calibration Done
3543 11:53:47.138162 ==
3544 11:53:47.141504 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 11:53:47.147807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 11:53:47.147921 ==
3547 11:53:47.148018 RX Vref Scan: 0
3548 11:53:47.148109
3549 11:53:47.151710 RX Vref 0 -> 0, step: 1
3550 11:53:47.151811
3551 11:53:47.154974 RX Delay -40 -> 252, step: 8
3552 11:53:47.157955 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3553 11:53:47.161130 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3554 11:53:47.164771 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3555 11:53:47.167786 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3556 11:53:47.174375 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3557 11:53:47.177716 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3558 11:53:47.181460 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3559 11:53:47.184750 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3560 11:53:47.187866 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3561 11:53:47.194839 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3562 11:53:47.197977 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3563 11:53:47.201214 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3564 11:53:47.204456 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3565 11:53:47.208165 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3566 11:53:47.214782 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3567 11:53:47.217908 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3568 11:53:47.218018 ==
3569 11:53:47.220979 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:53:47.224860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:53:47.224965 ==
3572 11:53:47.227957 DQS Delay:
3573 11:53:47.228068 DQS0 = 0, DQS1 = 0
3574 11:53:47.228160 DQM Delay:
3575 11:53:47.231246 DQM0 = 120, DQM1 = 118
3576 11:53:47.231353 DQ Delay:
3577 11:53:47.234524 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3578 11:53:47.237552 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3579 11:53:47.244112 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3580 11:53:47.247437 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3581 11:53:47.247539
3582 11:53:47.247646
3583 11:53:47.247746 ==
3584 11:53:47.250766 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:53:47.254193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:53:47.254293 ==
3587 11:53:47.254386
3588 11:53:47.254473
3589 11:53:47.257437 TX Vref Scan disable
3590 11:53:47.261030 == TX Byte 0 ==
3591 11:53:47.264213 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 11:53:47.267538 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 11:53:47.270702 == TX Byte 1 ==
3594 11:53:47.274342 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 11:53:47.277613 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 11:53:47.277728 ==
3597 11:53:47.281200 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:53:47.283981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:53:47.284113 ==
3600 11:53:47.297047 TX Vref=22, minBit 1, minWin=26, winSum=422
3601 11:53:47.300796 TX Vref=24, minBit 1, minWin=26, winSum=427
3602 11:53:47.304048 TX Vref=26, minBit 1, minWin=26, winSum=428
3603 11:53:47.307195 TX Vref=28, minBit 9, minWin=26, winSum=434
3604 11:53:47.310412 TX Vref=30, minBit 9, minWin=26, winSum=434
3605 11:53:47.314115 TX Vref=32, minBit 9, minWin=26, winSum=436
3606 11:53:47.320452 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3607 11:53:47.320567
3608 11:53:47.323981 Final TX Range 1 Vref 32
3609 11:53:47.324092
3610 11:53:47.324183 ==
3611 11:53:47.327109 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:53:47.330517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:53:47.330629 ==
3614 11:53:47.334060
3615 11:53:47.334180
3616 11:53:47.334271 TX Vref Scan disable
3617 11:53:47.337201 == TX Byte 0 ==
3618 11:53:47.340179 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 11:53:47.343956 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 11:53:47.347223 == TX Byte 1 ==
3621 11:53:47.350471 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 11:53:47.353489 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 11:53:47.356793
3624 11:53:47.356896 [DATLAT]
3625 11:53:47.356988 Freq=1200, CH1 RK1
3626 11:53:47.357075
3627 11:53:47.360457 DATLAT Default: 0xd
3628 11:53:47.360552 0, 0xFFFF, sum = 0
3629 11:53:47.363498 1, 0xFFFF, sum = 0
3630 11:53:47.363602 2, 0xFFFF, sum = 0
3631 11:53:47.366890 3, 0xFFFF, sum = 0
3632 11:53:47.366990 4, 0xFFFF, sum = 0
3633 11:53:47.370445 5, 0xFFFF, sum = 0
3634 11:53:47.373474 6, 0xFFFF, sum = 0
3635 11:53:47.373600 7, 0xFFFF, sum = 0
3636 11:53:47.377101 8, 0xFFFF, sum = 0
3637 11:53:47.377222 9, 0xFFFF, sum = 0
3638 11:53:47.380071 10, 0xFFFF, sum = 0
3639 11:53:47.380196 11, 0xFFFF, sum = 0
3640 11:53:47.383776 12, 0x0, sum = 1
3641 11:53:47.383882 13, 0x0, sum = 2
3642 11:53:47.386892 14, 0x0, sum = 3
3643 11:53:47.386993 15, 0x0, sum = 4
3644 11:53:47.387083 best_step = 13
3645 11:53:47.387179
3646 11:53:47.390144 ==
3647 11:53:47.393683 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 11:53:47.396759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 11:53:47.396857 ==
3650 11:53:47.396936 RX Vref Scan: 0
3651 11:53:47.397022
3652 11:53:47.400179 RX Vref 0 -> 0, step: 1
3653 11:53:47.400279
3654 11:53:47.403397 RX Delay -5 -> 252, step: 4
3655 11:53:47.406909 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3656 11:53:47.413702 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3657 11:53:47.416519 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3658 11:53:47.419901 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3659 11:53:47.423520 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3660 11:53:47.426890 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3661 11:53:47.433038 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3662 11:53:47.436995 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3663 11:53:47.440125 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3664 11:53:47.443282 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3665 11:53:47.446459 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3666 11:53:47.453066 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3667 11:53:47.456711 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3668 11:53:47.459851 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3669 11:53:47.463705 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3670 11:53:47.466804 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3671 11:53:47.469956 ==
3672 11:53:47.470056 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 11:53:47.476936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 11:53:47.477040 ==
3675 11:53:47.477162 DQS Delay:
3676 11:53:47.479574 DQS0 = 0, DQS1 = 0
3677 11:53:47.479703 DQM Delay:
3678 11:53:47.483665 DQM0 = 120, DQM1 = 118
3679 11:53:47.483764 DQ Delay:
3680 11:53:47.486428 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3681 11:53:47.489982 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3682 11:53:47.493035 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3683 11:53:47.497239 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3684 11:53:47.497336
3685 11:53:47.497416
3686 11:53:47.506575 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3687 11:53:47.506681 CH1 RK1: MR19=403, MR18=EEB
3688 11:53:47.513016 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3689 11:53:47.516679 [RxdqsGatingPostProcess] freq 1200
3690 11:53:47.523208 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 11:53:47.526487 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 11:53:47.530359 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 11:53:47.534076 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 11:53:47.536709 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 11:53:47.540000 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 11:53:47.540152 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 11:53:47.543427 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 11:53:47.546502 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 11:53:47.549545 Pre-setting of DQS Precalculation
3700 11:53:47.556308 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 11:53:47.563251 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 11:53:47.569512 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 11:53:47.569624
3704 11:53:47.569722
3705 11:53:47.573142 [Calibration Summary] 2400 Mbps
3706 11:53:47.576327 CH 0, Rank 0
3707 11:53:47.576426 SW Impedance : PASS
3708 11:53:47.579738 DUTY Scan : NO K
3709 11:53:47.582549 ZQ Calibration : PASS
3710 11:53:47.582649 Jitter Meter : NO K
3711 11:53:47.586143 CBT Training : PASS
3712 11:53:47.586249 Write leveling : PASS
3713 11:53:47.589208 RX DQS gating : PASS
3714 11:53:47.592850 RX DQ/DQS(RDDQC) : PASS
3715 11:53:47.592949 TX DQ/DQS : PASS
3716 11:53:47.596124 RX DATLAT : PASS
3717 11:53:47.599763 RX DQ/DQS(Engine): PASS
3718 11:53:47.599870 TX OE : NO K
3719 11:53:47.602975 All Pass.
3720 11:53:47.603082
3721 11:53:47.603174 CH 0, Rank 1
3722 11:53:47.606258 SW Impedance : PASS
3723 11:53:47.606358 DUTY Scan : NO K
3724 11:53:47.609434 ZQ Calibration : PASS
3725 11:53:47.612597 Jitter Meter : NO K
3726 11:53:47.612697 CBT Training : PASS
3727 11:53:47.615811 Write leveling : PASS
3728 11:53:47.619408 RX DQS gating : PASS
3729 11:53:47.619511 RX DQ/DQS(RDDQC) : PASS
3730 11:53:47.622671 TX DQ/DQS : PASS
3731 11:53:47.626409 RX DATLAT : PASS
3732 11:53:47.626509 RX DQ/DQS(Engine): PASS
3733 11:53:47.629349 TX OE : NO K
3734 11:53:47.629449 All Pass.
3735 11:53:47.629550
3736 11:53:47.633014 CH 1, Rank 0
3737 11:53:47.633126 SW Impedance : PASS
3738 11:53:47.635937 DUTY Scan : NO K
3739 11:53:47.636041 ZQ Calibration : PASS
3740 11:53:47.639617 Jitter Meter : NO K
3741 11:53:47.642764 CBT Training : PASS
3742 11:53:47.642878 Write leveling : PASS
3743 11:53:47.646100 RX DQS gating : PASS
3744 11:53:47.649682 RX DQ/DQS(RDDQC) : PASS
3745 11:53:47.649869 TX DQ/DQS : PASS
3746 11:53:47.652659 RX DATLAT : PASS
3747 11:53:47.655898 RX DQ/DQS(Engine): PASS
3748 11:53:47.656017 TX OE : NO K
3749 11:53:47.659521 All Pass.
3750 11:53:47.659643
3751 11:53:47.659740 CH 1, Rank 1
3752 11:53:47.662759 SW Impedance : PASS
3753 11:53:47.662870 DUTY Scan : NO K
3754 11:53:47.665740 ZQ Calibration : PASS
3755 11:53:47.668906 Jitter Meter : NO K
3756 11:53:47.669023 CBT Training : PASS
3757 11:53:47.672359 Write leveling : PASS
3758 11:53:47.675744 RX DQS gating : PASS
3759 11:53:47.675869 RX DQ/DQS(RDDQC) : PASS
3760 11:53:47.679123 TX DQ/DQS : PASS
3761 11:53:47.679230 RX DATLAT : PASS
3762 11:53:47.682519 RX DQ/DQS(Engine): PASS
3763 11:53:47.685942 TX OE : NO K
3764 11:53:47.686068 All Pass.
3765 11:53:47.686179
3766 11:53:47.689557 DramC Write-DBI off
3767 11:53:47.689692 PER_BANK_REFRESH: Hybrid Mode
3768 11:53:47.692321 TX_TRACKING: ON
3769 11:53:47.702152 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 11:53:47.705883 [FAST_K] Save calibration result to emmc
3771 11:53:47.708780 dramc_set_vcore_voltage set vcore to 650000
3772 11:53:47.708883 Read voltage for 600, 5
3773 11:53:47.712781 Vio18 = 0
3774 11:53:47.712882 Vcore = 650000
3775 11:53:47.713012 Vdram = 0
3776 11:53:47.715851 Vddq = 0
3777 11:53:47.715963 Vmddr = 0
3778 11:53:47.722175 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 11:53:47.725378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 11:53:47.728999 MEM_TYPE=3, freq_sel=19
3781 11:53:47.732212 sv_algorithm_assistance_LP4_1600
3782 11:53:47.735418 ============ PULL DRAM RESETB DOWN ============
3783 11:53:47.738800 ========== PULL DRAM RESETB DOWN end =========
3784 11:53:47.745442 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 11:53:47.748835 ===================================
3786 11:53:47.748970 LPDDR4 DRAM CONFIGURATION
3787 11:53:47.752266 ===================================
3788 11:53:47.755419 EX_ROW_EN[0] = 0x0
3789 11:53:47.759071 EX_ROW_EN[1] = 0x0
3790 11:53:47.759173 LP4Y_EN = 0x0
3791 11:53:47.761982 WORK_FSP = 0x0
3792 11:53:47.762084 WL = 0x2
3793 11:53:47.765418 RL = 0x2
3794 11:53:47.765534 BL = 0x2
3795 11:53:47.768909 RPST = 0x0
3796 11:53:47.768995 RD_PRE = 0x0
3797 11:53:47.772137 WR_PRE = 0x1
3798 11:53:47.772247 WR_PST = 0x0
3799 11:53:47.775306 DBI_WR = 0x0
3800 11:53:47.775389 DBI_RD = 0x0
3801 11:53:47.778534 OTF = 0x1
3802 11:53:47.781485 ===================================
3803 11:53:47.785015 ===================================
3804 11:53:47.785131 ANA top config
3805 11:53:47.788745 ===================================
3806 11:53:47.792198 DLL_ASYNC_EN = 0
3807 11:53:47.795428 ALL_SLAVE_EN = 1
3808 11:53:47.795515 NEW_RANK_MODE = 1
3809 11:53:47.798828 DLL_IDLE_MODE = 1
3810 11:53:47.801784 LP45_APHY_COMB_EN = 1
3811 11:53:47.804916 TX_ODT_DIS = 1
3812 11:53:47.808594 NEW_8X_MODE = 1
3813 11:53:47.811635 ===================================
3814 11:53:47.815100 ===================================
3815 11:53:47.815188 data_rate = 1200
3816 11:53:47.818301 CKR = 1
3817 11:53:47.821473 DQ_P2S_RATIO = 8
3818 11:53:47.825037 ===================================
3819 11:53:47.828503 CA_P2S_RATIO = 8
3820 11:53:47.831726 DQ_CA_OPEN = 0
3821 11:53:47.834851 DQ_SEMI_OPEN = 0
3822 11:53:47.834939 CA_SEMI_OPEN = 0
3823 11:53:47.838104 CA_FULL_RATE = 0
3824 11:53:47.841696 DQ_CKDIV4_EN = 1
3825 11:53:47.844940 CA_CKDIV4_EN = 1
3826 11:53:47.847902 CA_PREDIV_EN = 0
3827 11:53:47.851599 PH8_DLY = 0
3828 11:53:47.851686 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 11:53:47.854621 DQ_AAMCK_DIV = 4
3830 11:53:47.858112 CA_AAMCK_DIV = 4
3831 11:53:47.861571 CA_ADMCK_DIV = 4
3832 11:53:47.864876 DQ_TRACK_CA_EN = 0
3833 11:53:47.868065 CA_PICK = 600
3834 11:53:47.871264 CA_MCKIO = 600
3835 11:53:47.871350 MCKIO_SEMI = 0
3836 11:53:47.875035 PLL_FREQ = 2288
3837 11:53:47.878305 DQ_UI_PI_RATIO = 32
3838 11:53:47.881453 CA_UI_PI_RATIO = 0
3839 11:53:47.884913 ===================================
3840 11:53:47.888032 ===================================
3841 11:53:47.891405 memory_type:LPDDR4
3842 11:53:47.891539 GP_NUM : 10
3843 11:53:47.894910 SRAM_EN : 1
3844 11:53:47.897871 MD32_EN : 0
3845 11:53:47.901052 ===================================
3846 11:53:47.901137 [ANA_INIT] >>>>>>>>>>>>>>
3847 11:53:47.904749 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 11:53:47.907802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 11:53:47.911530 ===================================
3850 11:53:47.914576 data_rate = 1200,PCW = 0X5800
3851 11:53:47.917869 ===================================
3852 11:53:47.921496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 11:53:47.928016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 11:53:47.931156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 11:53:47.937924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 11:53:47.940945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 11:53:47.944647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 11:53:47.944751 [ANA_INIT] flow start
3859 11:53:47.947908 [ANA_INIT] PLL >>>>>>>>
3860 11:53:47.951258 [ANA_INIT] PLL <<<<<<<<
3861 11:53:47.951362 [ANA_INIT] MIDPI >>>>>>>>
3862 11:53:47.954628 [ANA_INIT] MIDPI <<<<<<<<
3863 11:53:47.957817 [ANA_INIT] DLL >>>>>>>>
3864 11:53:47.957922 [ANA_INIT] flow end
3865 11:53:47.964620 ============ LP4 DIFF to SE enter ============
3866 11:53:47.967621 ============ LP4 DIFF to SE exit ============
3867 11:53:47.970865 [ANA_INIT] <<<<<<<<<<<<<
3868 11:53:47.974546 [Flow] Enable top DCM control >>>>>
3869 11:53:47.977783 [Flow] Enable top DCM control <<<<<
3870 11:53:47.977892 Enable DLL master slave shuffle
3871 11:53:47.984088 ==============================================================
3872 11:53:47.987777 Gating Mode config
3873 11:53:47.991043 ==============================================================
3874 11:53:47.994780 Config description:
3875 11:53:48.004360 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 11:53:48.011203 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 11:53:48.014188 SELPH_MODE 0: By rank 1: By Phase
3878 11:53:48.020678 ==============================================================
3879 11:53:48.024645 GAT_TRACK_EN = 1
3880 11:53:48.027774 RX_GATING_MODE = 2
3881 11:53:48.030956 RX_GATING_TRACK_MODE = 2
3882 11:53:48.034030 SELPH_MODE = 1
3883 11:53:48.034142 PICG_EARLY_EN = 1
3884 11:53:48.037254 VALID_LAT_VALUE = 1
3885 11:53:48.044088 ==============================================================
3886 11:53:48.047330 Enter into Gating configuration >>>>
3887 11:53:48.050657 Exit from Gating configuration <<<<
3888 11:53:48.053888 Enter into DVFS_PRE_config >>>>>
3889 11:53:48.063921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 11:53:48.067124 Exit from DVFS_PRE_config <<<<<
3891 11:53:48.070791 Enter into PICG configuration >>>>
3892 11:53:48.073824 Exit from PICG configuration <<<<
3893 11:53:48.077175 [RX_INPUT] configuration >>>>>
3894 11:53:48.080395 [RX_INPUT] configuration <<<<<
3895 11:53:48.083784 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 11:53:48.090418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 11:53:48.096999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 11:53:48.103427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 11:53:48.110543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 11:53:48.113857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 11:53:48.120467 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 11:53:48.123742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 11:53:48.126941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 11:53:48.130439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 11:53:48.136736 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 11:53:48.140627 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 11:53:48.143859 ===================================
3908 11:53:48.147096 LPDDR4 DRAM CONFIGURATION
3909 11:53:48.150231 ===================================
3910 11:53:48.150339 EX_ROW_EN[0] = 0x0
3911 11:53:48.153544 EX_ROW_EN[1] = 0x0
3912 11:53:48.153663 LP4Y_EN = 0x0
3913 11:53:48.157154 WORK_FSP = 0x0
3914 11:53:48.157253 WL = 0x2
3915 11:53:48.160561 RL = 0x2
3916 11:53:48.160656 BL = 0x2
3917 11:53:48.163579 RPST = 0x0
3918 11:53:48.163673 RD_PRE = 0x0
3919 11:53:48.166748 WR_PRE = 0x1
3920 11:53:48.166857 WR_PST = 0x0
3921 11:53:48.170735 DBI_WR = 0x0
3922 11:53:48.173938 DBI_RD = 0x0
3923 11:53:48.174006 OTF = 0x1
3924 11:53:48.177251 ===================================
3925 11:53:48.180397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 11:53:48.184089 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 11:53:48.190203 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 11:53:48.193444 ===================================
3929 11:53:48.193566 LPDDR4 DRAM CONFIGURATION
3930 11:53:48.196965 ===================================
3931 11:53:48.200032 EX_ROW_EN[0] = 0x10
3932 11:53:48.203569 EX_ROW_EN[1] = 0x0
3933 11:53:48.203670 LP4Y_EN = 0x0
3934 11:53:48.207073 WORK_FSP = 0x0
3935 11:53:48.207144 WL = 0x2
3936 11:53:48.209847 RL = 0x2
3937 11:53:48.209917 BL = 0x2
3938 11:53:48.214093 RPST = 0x0
3939 11:53:48.214189 RD_PRE = 0x0
3940 11:53:48.216930 WR_PRE = 0x1
3941 11:53:48.217025 WR_PST = 0x0
3942 11:53:48.220496 DBI_WR = 0x0
3943 11:53:48.220590 DBI_RD = 0x0
3944 11:53:48.223439 OTF = 0x1
3945 11:53:48.226749 ===================================
3946 11:53:48.233505 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 11:53:48.236828 nWR fixed to 30
3948 11:53:48.240150 [ModeRegInit_LP4] CH0 RK0
3949 11:53:48.240249 [ModeRegInit_LP4] CH0 RK1
3950 11:53:48.243363 [ModeRegInit_LP4] CH1 RK0
3951 11:53:48.246733 [ModeRegInit_LP4] CH1 RK1
3952 11:53:48.246854 match AC timing 17
3953 11:53:48.253164 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 11:53:48.256952 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 11:53:48.260157 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 11:53:48.266410 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 11:53:48.270298 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 11:53:48.270419 ==
3959 11:53:48.273726 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:53:48.276850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:53:48.276956 ==
3962 11:53:48.283274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 11:53:48.289934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3964 11:53:48.293311 [CA 0] Center 36 (5~67) winsize 63
3965 11:53:48.296308 [CA 1] Center 36 (5~67) winsize 63
3966 11:53:48.300092 [CA 2] Center 33 (3~64) winsize 62
3967 11:53:48.303224 [CA 3] Center 33 (2~64) winsize 63
3968 11:53:48.306282 [CA 4] Center 33 (2~64) winsize 63
3969 11:53:48.309959 [CA 5] Center 32 (2~63) winsize 62
3970 11:53:48.310035
3971 11:53:48.313314 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3972 11:53:48.313423
3973 11:53:48.316582 [CATrainingPosCal] consider 1 rank data
3974 11:53:48.319972 u2DelayCellTimex100 = 270/100 ps
3975 11:53:48.322744 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3976 11:53:48.326475 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3977 11:53:48.329314 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3978 11:53:48.332954 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3979 11:53:48.336708 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3980 11:53:48.339332 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3981 11:53:48.343193
3982 11:53:48.345986 CA PerBit enable=1, Macro0, CA PI delay=32
3983 11:53:48.346074
3984 11:53:48.349489 [CBTSetCACLKResult] CA Dly = 32
3985 11:53:48.349582 CS Dly: 4 (0~35)
3986 11:53:48.349654 ==
3987 11:53:48.352841 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 11:53:48.356020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:53:48.356107 ==
3990 11:53:48.362756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 11:53:48.369490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 11:53:48.372735 [CA 0] Center 35 (5~66) winsize 62
3993 11:53:48.376531 [CA 1] Center 35 (5~66) winsize 62
3994 11:53:48.379822 [CA 2] Center 34 (3~65) winsize 63
3995 11:53:48.383077 [CA 3] Center 33 (3~64) winsize 62
3996 11:53:48.386215 [CA 4] Center 33 (2~64) winsize 63
3997 11:53:48.389448 [CA 5] Center 32 (2~63) winsize 62
3998 11:53:48.389559
3999 11:53:48.392812 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 11:53:48.392912
4001 11:53:48.396248 [CATrainingPosCal] consider 2 rank data
4002 11:53:48.399469 u2DelayCellTimex100 = 270/100 ps
4003 11:53:48.402473 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4004 11:53:48.406402 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4005 11:53:48.409714 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4006 11:53:48.412702 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4007 11:53:48.415875 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4008 11:53:48.422902 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4009 11:53:48.423008
4010 11:53:48.426057 CA PerBit enable=1, Macro0, CA PI delay=32
4011 11:53:48.426155
4012 11:53:48.429392 [CBTSetCACLKResult] CA Dly = 32
4013 11:53:48.429496 CS Dly: 4 (0~36)
4014 11:53:48.429609
4015 11:53:48.432697 ----->DramcWriteLeveling(PI) begin...
4016 11:53:48.432800 ==
4017 11:53:48.436076 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 11:53:48.439689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:53:48.442662 ==
4020 11:53:48.442769 Write leveling (Byte 0): 34 => 34
4021 11:53:48.445940 Write leveling (Byte 1): 33 => 33
4022 11:53:48.449089 DramcWriteLeveling(PI) end<-----
4023 11:53:48.449195
4024 11:53:48.449286 ==
4025 11:53:48.452976 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 11:53:48.459325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 11:53:48.459453 ==
4028 11:53:48.462767 [Gating] SW mode calibration
4029 11:53:48.468990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 11:53:48.472736 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 11:53:48.479077 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 11:53:48.482622 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 11:53:48.485585 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 11:53:48.489480 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
4035 11:53:48.495606 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 1) (0 0)
4036 11:53:48.499309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:53:48.502302 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:53:48.508775 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:53:48.512542 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:53:48.515750 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:53:48.522681 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:53:48.525965 0 10 12 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
4043 11:53:48.529250 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4044 11:53:48.535842 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:53:48.538855 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 11:53:48.542418 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:53:48.548655 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:53:48.551914 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:53:48.555729 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:53:48.561674 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4051 11:53:48.565408 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4052 11:53:48.568722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:53:48.575618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:53:48.578921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:53:48.582167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:53:48.588498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:53:48.592087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:53:48.595229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:53:48.602036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:53:48.604932 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:53:48.608400 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:53:48.615147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:53:48.618313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:53:48.621498 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:53:48.628190 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:53:48.631302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4067 11:53:48.634996 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4068 11:53:48.638101 Total UI for P1: 0, mck2ui 16
4069 11:53:48.641256 best dqsien dly found for B0: ( 0, 13, 12)
4070 11:53:48.648228 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:53:48.648330 Total UI for P1: 0, mck2ui 16
4072 11:53:48.654824 best dqsien dly found for B1: ( 0, 13, 16)
4073 11:53:48.658038 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4074 11:53:48.661902 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4075 11:53:48.661984
4076 11:53:48.665022 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4077 11:53:48.668343 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4078 11:53:48.671683 [Gating] SW calibration Done
4079 11:53:48.671786 ==
4080 11:53:48.674920 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 11:53:48.678118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 11:53:48.678257 ==
4083 11:53:48.682036 RX Vref Scan: 0
4084 11:53:48.682169
4085 11:53:48.682282 RX Vref 0 -> 0, step: 1
4086 11:53:48.682370
4087 11:53:48.685211 RX Delay -230 -> 252, step: 16
4088 11:53:48.688412 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4089 11:53:48.694941 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4090 11:53:48.698068 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4091 11:53:48.701952 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4092 11:53:48.705048 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4093 11:53:48.711157 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4094 11:53:48.714883 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4095 11:53:48.718143 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 11:53:48.721299 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4097 11:53:48.724992 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4098 11:53:48.731587 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4099 11:53:48.734757 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4100 11:53:48.738406 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4101 11:53:48.741238 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4102 11:53:48.748055 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4103 11:53:48.751261 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4104 11:53:48.751347 ==
4105 11:53:48.754885 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 11:53:48.758083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 11:53:48.758181 ==
4108 11:53:48.761277 DQS Delay:
4109 11:53:48.761362 DQS0 = 0, DQS1 = 0
4110 11:53:48.761428 DQM Delay:
4111 11:53:48.764995 DQM0 = 51, DQM1 = 46
4112 11:53:48.765104 DQ Delay:
4113 11:53:48.767892 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4114 11:53:48.771537 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4115 11:53:48.774972 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4116 11:53:48.778023 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4117 11:53:48.778108
4118 11:53:48.778174
4119 11:53:48.778235 ==
4120 11:53:48.781225 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:53:48.788549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:53:48.788673 ==
4123 11:53:48.788771
4124 11:53:48.788861
4125 11:53:48.788949 TX Vref Scan disable
4126 11:53:48.791520 == TX Byte 0 ==
4127 11:53:48.794734 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4128 11:53:48.797927 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4129 11:53:48.801681 == TX Byte 1 ==
4130 11:53:48.805022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4131 11:53:48.808238 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4132 11:53:48.811403 ==
4133 11:53:48.814432 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:53:48.818138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:53:48.818286 ==
4136 11:53:48.818365
4137 11:53:48.818473
4138 11:53:48.821668 TX Vref Scan disable
4139 11:53:48.824702 == TX Byte 0 ==
4140 11:53:48.828037 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4141 11:53:48.831044 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4142 11:53:48.834312 == TX Byte 1 ==
4143 11:53:48.837914 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4144 11:53:48.840968 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4145 11:53:48.841085
4146 11:53:48.841195 [DATLAT]
4147 11:53:48.844861 Freq=600, CH0 RK0
4148 11:53:48.844957
4149 11:53:48.845025 DATLAT Default: 0x9
4150 11:53:48.847967 0, 0xFFFF, sum = 0
4151 11:53:48.851363 1, 0xFFFF, sum = 0
4152 11:53:48.851455 2, 0xFFFF, sum = 0
4153 11:53:48.854523 3, 0xFFFF, sum = 0
4154 11:53:48.854616 4, 0xFFFF, sum = 0
4155 11:53:48.857598 5, 0xFFFF, sum = 0
4156 11:53:48.857693 6, 0xFFFF, sum = 0
4157 11:53:48.861121 7, 0xFFFF, sum = 0
4158 11:53:48.861217 8, 0x0, sum = 1
4159 11:53:48.864199 9, 0x0, sum = 2
4160 11:53:48.864290 10, 0x0, sum = 3
4161 11:53:48.864360 11, 0x0, sum = 4
4162 11:53:48.871702 best_step = 9
4163 11:53:48.871816
4164 11:53:48.871890 ==
4165 11:53:48.872159 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 11:53:48.874426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 11:53:48.874513 ==
4168 11:53:48.877680 RX Vref Scan: 1
4169 11:53:48.877807
4170 11:53:48.877900 RX Vref 0 -> 0, step: 1
4171 11:53:48.877989
4172 11:53:48.881035 RX Delay -163 -> 252, step: 8
4173 11:53:48.881127
4174 11:53:48.884200 Set Vref, RX VrefLevel [Byte0]: 55
4175 11:53:48.888246 [Byte1]: 58
4176 11:53:48.891930
4177 11:53:48.892048 Final RX Vref Byte 0 = 55 to rank0
4178 11:53:48.895495 Final RX Vref Byte 1 = 58 to rank0
4179 11:53:48.898597 Final RX Vref Byte 0 = 55 to rank1
4180 11:53:48.901831 Final RX Vref Byte 1 = 58 to rank1==
4181 11:53:48.904901 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 11:53:48.911908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 11:53:48.912028 ==
4184 11:53:48.912101 DQS Delay:
4185 11:53:48.912165 DQS0 = 0, DQS1 = 0
4186 11:53:48.915359 DQM Delay:
4187 11:53:48.915447 DQM0 = 54, DQM1 = 46
4188 11:53:48.918543 DQ Delay:
4189 11:53:48.921829 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4190 11:53:48.921935 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4191 11:53:48.925402 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4192 11:53:48.928868 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =52
4193 11:53:48.931552
4194 11:53:48.931643
4195 11:53:48.938301 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4196 11:53:48.941914 CH0 RK0: MR19=808, MR18=6D5F
4197 11:53:48.948373 CH0_RK0: MR19=0x808, MR18=0x6D5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4198 11:53:48.948490
4199 11:53:48.951918 ----->DramcWriteLeveling(PI) begin...
4200 11:53:48.952033 ==
4201 11:53:48.955310 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 11:53:48.958473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 11:53:48.958585 ==
4204 11:53:48.961360 Write leveling (Byte 0): 36 => 36
4205 11:53:48.965069 Write leveling (Byte 1): 31 => 31
4206 11:53:48.968029 DramcWriteLeveling(PI) end<-----
4207 11:53:48.968152
4208 11:53:48.968246 ==
4209 11:53:48.971274 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:53:48.975085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:53:48.975198 ==
4212 11:53:48.978648 [Gating] SW mode calibration
4213 11:53:48.984777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 11:53:48.991298 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 11:53:48.994939 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 11:53:49.001185 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 11:53:49.005256 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 11:53:49.007814 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4219 11:53:49.011562 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
4220 11:53:49.017900 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:53:49.021447 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:53:49.024991 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:53:49.031658 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:53:49.034498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:53:49.038275 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:53:49.044601 0 10 12 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
4227 11:53:49.047535 0 10 16 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
4228 11:53:49.050959 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:53:49.058092 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:53:49.060970 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:53:49.064128 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:53:49.070874 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:53:49.074440 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:53:49.077547 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4235 11:53:49.084630 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4236 11:53:49.087836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:53:49.091325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:53:49.097282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:53:49.100731 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:53:49.104539 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:53:49.110979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:53:49.114185 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:53:49.117354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:53:49.124677 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:53:49.127477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:53:49.130686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:53:49.137416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:53:49.141238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:53:49.143909 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:53:49.150783 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4251 11:53:49.154210 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:53:49.157152 Total UI for P1: 0, mck2ui 16
4253 11:53:49.160748 best dqsien dly found for B0: ( 0, 13, 12)
4254 11:53:49.164272 Total UI for P1: 0, mck2ui 16
4255 11:53:49.167268 best dqsien dly found for B1: ( 0, 13, 12)
4256 11:53:49.170857 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4257 11:53:49.173944 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4258 11:53:49.174030
4259 11:53:49.177140 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 11:53:49.180775 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4261 11:53:49.183874 [Gating] SW calibration Done
4262 11:53:49.183959 ==
4263 11:53:49.186948 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 11:53:49.190948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 11:53:49.191034 ==
4266 11:53:49.193982 RX Vref Scan: 0
4267 11:53:49.194067
4268 11:53:49.197349 RX Vref 0 -> 0, step: 1
4269 11:53:49.197432
4270 11:53:49.197497 RX Delay -230 -> 252, step: 16
4271 11:53:49.203846 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4272 11:53:49.207232 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4273 11:53:49.210897 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4274 11:53:49.214658 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4275 11:53:49.217815 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4276 11:53:49.224389 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4277 11:53:49.227662 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4278 11:53:49.230828 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4279 11:53:49.233815 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4280 11:53:49.240944 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4281 11:53:49.244336 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4282 11:53:49.247295 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4283 11:53:49.250803 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4284 11:53:49.257273 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4285 11:53:49.260536 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4286 11:53:49.263632 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4287 11:53:49.263710 ==
4288 11:53:49.267035 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 11:53:49.270675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 11:53:49.273877 ==
4291 11:53:49.273962 DQS Delay:
4292 11:53:49.274027 DQS0 = 0, DQS1 = 0
4293 11:53:49.276903 DQM Delay:
4294 11:53:49.276981 DQM0 = 52, DQM1 = 42
4295 11:53:49.279983 DQ Delay:
4296 11:53:49.283413 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4297 11:53:49.283501 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4298 11:53:49.286824 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4299 11:53:49.290255 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4300 11:53:49.293346
4301 11:53:49.293429
4302 11:53:49.293493 ==
4303 11:53:49.296978 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:53:49.300195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:53:49.300276 ==
4306 11:53:49.300343
4307 11:53:49.300417
4308 11:53:49.303534 TX Vref Scan disable
4309 11:53:49.303617 == TX Byte 0 ==
4310 11:53:49.309866 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4311 11:53:49.313250 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4312 11:53:49.313335 == TX Byte 1 ==
4313 11:53:49.320122 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4314 11:53:49.323406 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4315 11:53:49.323491 ==
4316 11:53:49.326934 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:53:49.330334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:53:49.330419 ==
4319 11:53:49.330485
4320 11:53:49.330546
4321 11:53:49.333188 TX Vref Scan disable
4322 11:53:49.336710 == TX Byte 0 ==
4323 11:53:49.339923 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4324 11:53:49.346172 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4325 11:53:49.346285 == TX Byte 1 ==
4326 11:53:49.349908 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4327 11:53:49.356203 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4328 11:53:49.356332
4329 11:53:49.356428 [DATLAT]
4330 11:53:49.356530 Freq=600, CH0 RK1
4331 11:53:49.356621
4332 11:53:49.360044 DATLAT Default: 0x9
4333 11:53:49.360131 0, 0xFFFF, sum = 0
4334 11:53:49.363292 1, 0xFFFF, sum = 0
4335 11:53:49.366229 2, 0xFFFF, sum = 0
4336 11:53:49.366316 3, 0xFFFF, sum = 0
4337 11:53:49.369584 4, 0xFFFF, sum = 0
4338 11:53:49.369672 5, 0xFFFF, sum = 0
4339 11:53:49.373354 6, 0xFFFF, sum = 0
4340 11:53:49.373439 7, 0xFFFF, sum = 0
4341 11:53:49.376460 8, 0x0, sum = 1
4342 11:53:49.376544 9, 0x0, sum = 2
4343 11:53:49.376610 10, 0x0, sum = 3
4344 11:53:49.379449 11, 0x0, sum = 4
4345 11:53:49.379532 best_step = 9
4346 11:53:49.379598
4347 11:53:49.379674 ==
4348 11:53:49.382840 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 11:53:49.389808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:53:49.389894 ==
4351 11:53:49.389992 RX Vref Scan: 0
4352 11:53:49.390052
4353 11:53:49.393140 RX Vref 0 -> 0, step: 1
4354 11:53:49.393221
4355 11:53:49.396261 RX Delay -179 -> 252, step: 8
4356 11:53:49.399677 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4357 11:53:49.406081 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4358 11:53:49.409507 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4359 11:53:49.412758 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4360 11:53:49.416343 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4361 11:53:49.419511 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4362 11:53:49.425857 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4363 11:53:49.429149 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4364 11:53:49.432408 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4365 11:53:49.435748 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4366 11:53:49.439686 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4367 11:53:49.445892 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4368 11:53:49.449136 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4369 11:53:49.452749 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4370 11:53:49.455857 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4371 11:53:49.462928 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4372 11:53:49.463026 ==
4373 11:53:49.466066 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 11:53:49.469059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 11:53:49.469140 ==
4376 11:53:49.469205 DQS Delay:
4377 11:53:49.472334 DQS0 = 0, DQS1 = 0
4378 11:53:49.472444 DQM Delay:
4379 11:53:49.476502 DQM0 = 53, DQM1 = 46
4380 11:53:49.476584 DQ Delay:
4381 11:53:49.479391 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4382 11:53:49.482744 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4383 11:53:49.486015 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4384 11:53:49.489446 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4385 11:53:49.489529
4386 11:53:49.489636
4387 11:53:49.496345 [DQSOSCAuto] RK1, (LSB)MR18= 0x6627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4388 11:53:49.499301 CH0 RK1: MR19=808, MR18=6627
4389 11:53:49.505874 CH0_RK1: MR19=0x808, MR18=0x6627, DQSOSC=390, MR23=63, INC=172, DEC=114
4390 11:53:49.509534 [RxdqsGatingPostProcess] freq 600
4391 11:53:49.516150 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 11:53:49.519394 Pre-setting of DQS Precalculation
4393 11:53:49.522760 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 11:53:49.523149 ==
4395 11:53:49.526034 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:53:49.529233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:53:49.529668 ==
4398 11:53:49.535643 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 11:53:49.542635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4400 11:53:49.545689 [CA 0] Center 35 (5~66) winsize 62
4401 11:53:49.549232 [CA 1] Center 36 (5~67) winsize 63
4402 11:53:49.552363 [CA 2] Center 34 (4~65) winsize 62
4403 11:53:49.555963 [CA 3] Center 34 (4~65) winsize 62
4404 11:53:49.559043 [CA 4] Center 34 (4~65) winsize 62
4405 11:53:49.562995 [CA 5] Center 33 (3~64) winsize 62
4406 11:53:49.563386
4407 11:53:49.566075 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4408 11:53:49.566342
4409 11:53:49.569250 [CATrainingPosCal] consider 1 rank data
4410 11:53:49.572540 u2DelayCellTimex100 = 270/100 ps
4411 11:53:49.575409 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 11:53:49.579397 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4413 11:53:49.582460 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 11:53:49.585571 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 11:53:49.588876 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 11:53:49.591972 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 11:53:49.595282
4418 11:53:49.598506 CA PerBit enable=1, Macro0, CA PI delay=33
4419 11:53:49.598607
4420 11:53:49.602414 [CBTSetCACLKResult] CA Dly = 33
4421 11:53:49.602506 CS Dly: 5 (0~36)
4422 11:53:49.602578 ==
4423 11:53:49.605506 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 11:53:49.608678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 11:53:49.608767 ==
4426 11:53:49.615046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 11:53:49.621994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4428 11:53:49.625005 [CA 0] Center 36 (5~67) winsize 63
4429 11:53:49.628257 [CA 1] Center 36 (5~67) winsize 63
4430 11:53:49.632100 [CA 2] Center 34 (4~65) winsize 62
4431 11:53:49.635157 [CA 3] Center 34 (3~65) winsize 63
4432 11:53:49.638276 [CA 4] Center 35 (4~66) winsize 63
4433 11:53:49.641905 [CA 5] Center 34 (3~65) winsize 63
4434 11:53:49.641988
4435 11:53:49.645299 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4436 11:53:49.645382
4437 11:53:49.648255 [CATrainingPosCal] consider 2 rank data
4438 11:53:49.651791 u2DelayCellTimex100 = 270/100 ps
4439 11:53:49.655048 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 11:53:49.658555 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4441 11:53:49.661886 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 11:53:49.664810 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 11:53:49.672047 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 11:53:49.675347 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 11:53:49.675442
4446 11:53:49.678565 CA PerBit enable=1, Macro0, CA PI delay=33
4447 11:53:49.678669
4448 11:53:49.681799 [CBTSetCACLKResult] CA Dly = 33
4449 11:53:49.681911 CS Dly: 6 (0~38)
4450 11:53:49.682000
4451 11:53:49.685005 ----->DramcWriteLeveling(PI) begin...
4452 11:53:49.685118 ==
4453 11:53:49.688291 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 11:53:49.694890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:53:49.695027 ==
4456 11:53:49.698567 Write leveling (Byte 0): 31 => 31
4457 11:53:49.701856 Write leveling (Byte 1): 31 => 31
4458 11:53:49.702032 DramcWriteLeveling(PI) end<-----
4459 11:53:49.705112
4460 11:53:49.705284 ==
4461 11:53:49.708205 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:53:49.711310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:53:49.711555 ==
4464 11:53:49.715294 [Gating] SW mode calibration
4465 11:53:49.721376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 11:53:49.724905 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 11:53:49.731294 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 11:53:49.734998 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 11:53:49.738204 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 11:53:49.744750 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (1 1) (1 1)
4471 11:53:49.748621 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:53:49.751996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 11:53:49.758556 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 11:53:49.761682 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 11:53:49.764748 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 11:53:49.771352 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:53:49.775014 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4478 11:53:49.778754 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4479 11:53:49.785352 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:53:49.788297 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:53:49.791761 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 11:53:49.798305 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:53:49.801909 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:53:49.804544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:53:49.811565 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:53:49.814800 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4487 11:53:49.817985 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:53:49.825120 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:53:49.828128 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:53:49.831028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:53:49.834592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:53:49.840956 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:53:49.844764 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:53:49.848250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:53:49.854226 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:53:49.857794 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:53:49.861063 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:53:49.868019 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:53:49.871129 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:53:49.873995 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:53:49.880920 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:53:49.884437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 11:53:49.887871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:53:49.891140 Total UI for P1: 0, mck2ui 16
4505 11:53:49.894216 best dqsien dly found for B0: ( 0, 13, 12)
4506 11:53:49.897939 Total UI for P1: 0, mck2ui 16
4507 11:53:49.901447 best dqsien dly found for B1: ( 0, 13, 12)
4508 11:53:49.904570 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4509 11:53:49.907948 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 11:53:49.910566
4511 11:53:49.914096 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4512 11:53:49.917148 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 11:53:49.921019 [Gating] SW calibration Done
4514 11:53:49.921690 ==
4515 11:53:49.924182 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 11:53:49.927550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 11:53:49.927978 ==
4518 11:53:49.928314 RX Vref Scan: 0
4519 11:53:49.930701
4520 11:53:49.931124 RX Vref 0 -> 0, step: 1
4521 11:53:49.931458
4522 11:53:49.934461 RX Delay -230 -> 252, step: 16
4523 11:53:49.937061 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4524 11:53:49.943902 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4525 11:53:49.947652 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4526 11:53:49.950540 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4527 11:53:49.954285 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4528 11:53:49.957524 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4529 11:53:49.964174 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4530 11:53:49.966907 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4531 11:53:49.971358 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4532 11:53:49.974048 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4533 11:53:49.980508 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4534 11:53:49.984410 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4535 11:53:49.987263 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4536 11:53:49.990917 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4537 11:53:49.997375 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4538 11:53:50.000453 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4539 11:53:50.000973 ==
4540 11:53:50.003790 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 11:53:50.007490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 11:53:50.008013 ==
4543 11:53:50.010390 DQS Delay:
4544 11:53:50.010812 DQS0 = 0, DQS1 = 0
4545 11:53:50.011145 DQM Delay:
4546 11:53:50.013814 DQM0 = 50, DQM1 = 46
4547 11:53:50.014240 DQ Delay:
4548 11:53:50.017133 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4549 11:53:50.029074 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4550 11:53:50.029182 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4551 11:53:50.029255 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4552 11:53:50.029321
4553 11:53:50.029384
4554 11:53:50.029445 ==
4555 11:53:50.029969 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:53:50.036391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:53:50.036592 ==
4558 11:53:50.036710
4559 11:53:50.036802
4560 11:53:50.036886 TX Vref Scan disable
4561 11:53:50.039819 == TX Byte 0 ==
4562 11:53:50.043219 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4563 11:53:50.047437 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4564 11:53:50.050281 == TX Byte 1 ==
4565 11:53:50.053753 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 11:53:50.060484 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 11:53:50.061003 ==
4568 11:53:50.063357 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:53:50.067153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:53:50.067590 ==
4571 11:53:50.067925
4572 11:53:50.068237
4573 11:53:50.070046 TX Vref Scan disable
4574 11:53:50.070469 == TX Byte 0 ==
4575 11:53:50.077277 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4576 11:53:50.080153 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4577 11:53:50.080679 == TX Byte 1 ==
4578 11:53:50.086527 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4579 11:53:50.090494 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4580 11:53:50.091025
4581 11:53:50.091364 [DATLAT]
4582 11:53:50.093798 Freq=600, CH1 RK0
4583 11:53:50.094320
4584 11:53:50.094657 DATLAT Default: 0x9
4585 11:53:50.096815 0, 0xFFFF, sum = 0
4586 11:53:50.097413 1, 0xFFFF, sum = 0
4587 11:53:50.100470 2, 0xFFFF, sum = 0
4588 11:53:50.103110 3, 0xFFFF, sum = 0
4589 11:53:50.103545 4, 0xFFFF, sum = 0
4590 11:53:50.107128 5, 0xFFFF, sum = 0
4591 11:53:50.107661 6, 0xFFFF, sum = 0
4592 11:53:50.109973 7, 0xFFFF, sum = 0
4593 11:53:50.110402 8, 0x0, sum = 1
4594 11:53:50.110743 9, 0x0, sum = 2
4595 11:53:50.113112 10, 0x0, sum = 3
4596 11:53:50.113742 11, 0x0, sum = 4
4597 11:53:50.116493 best_step = 9
4598 11:53:50.116913
4599 11:53:50.117246 ==
4600 11:53:50.120059 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:53:50.122845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:53:50.123274 ==
4603 11:53:50.126908 RX Vref Scan: 1
4604 11:53:50.127417
4605 11:53:50.127750 RX Vref 0 -> 0, step: 1
4606 11:53:50.128062
4607 11:53:50.129965 RX Delay -163 -> 252, step: 8
4608 11:53:50.130389
4609 11:53:50.133427 Set Vref, RX VrefLevel [Byte0]: 54
4610 11:53:50.136293 [Byte1]: 52
4611 11:53:50.140568
4612 11:53:50.141087 Final RX Vref Byte 0 = 54 to rank0
4613 11:53:50.144385 Final RX Vref Byte 1 = 52 to rank0
4614 11:53:50.147489 Final RX Vref Byte 0 = 54 to rank1
4615 11:53:50.150350 Final RX Vref Byte 1 = 52 to rank1==
4616 11:53:50.153682 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 11:53:50.160342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 11:53:50.160764 ==
4619 11:53:50.161096 DQS Delay:
4620 11:53:50.161403 DQS0 = 0, DQS1 = 0
4621 11:53:50.163822 DQM Delay:
4622 11:53:50.164346 DQM0 = 47, DQM1 = 44
4623 11:53:50.167273 DQ Delay:
4624 11:53:50.170629 DQ0 =48, DQ1 =44, DQ2 =36, DQ3 =44
4625 11:53:50.174156 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4626 11:53:50.176806 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4627 11:53:50.180172 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4628 11:53:50.180703
4629 11:53:50.181295
4630 11:53:50.187045 [DQSOSCAuto] RK0, (LSB)MR18= 0x476d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4631 11:53:50.190130 CH1 RK0: MR19=808, MR18=476D
4632 11:53:50.196681 CH1_RK0: MR19=0x808, MR18=0x476D, DQSOSC=389, MR23=63, INC=173, DEC=115
4633 11:53:50.197318
4634 11:53:50.199832 ----->DramcWriteLeveling(PI) begin...
4635 11:53:50.200256 ==
4636 11:53:50.203696 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 11:53:50.206799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 11:53:50.207288 ==
4639 11:53:50.210008 Write leveling (Byte 0): 29 => 29
4640 11:53:50.213231 Write leveling (Byte 1): 30 => 30
4641 11:53:50.216442 DramcWriteLeveling(PI) end<-----
4642 11:53:50.216861
4643 11:53:50.217190 ==
4644 11:53:50.220561 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:53:50.223421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:53:50.223842 ==
4647 11:53:50.226981 [Gating] SW mode calibration
4648 11:53:50.233258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 11:53:50.240120 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 11:53:50.243745 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 11:53:50.249981 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 11:53:50.253190 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 11:53:50.257186 0 9 12 | B1->B0 | 3030 3030 | 0 1 | (0 0) (1 0)
4654 11:53:50.263166 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 11:53:50.266391 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 11:53:50.269724 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 11:53:50.276534 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 11:53:50.279944 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 11:53:50.282998 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:53:50.290058 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4661 11:53:50.293702 0 10 12 | B1->B0 | 3b3b 3434 | 0 0 | (0 0) (0 0)
4662 11:53:50.296260 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 11:53:50.303135 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:53:50.306211 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 11:53:50.309810 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 11:53:50.316439 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:53:50.319358 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:53:50.322523 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4669 11:53:50.325980 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 11:53:50.332324 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:53:50.336279 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:53:50.339047 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:53:50.346390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:53:50.349378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:53:50.352747 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:53:50.359054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:53:50.362222 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:53:50.366269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:53:50.372600 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:53:50.375723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:53:50.378946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:53:50.385809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:53:50.389499 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:53:50.392386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4685 11:53:50.399081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4686 11:53:50.402261 Total UI for P1: 0, mck2ui 16
4687 11:53:50.405318 best dqsien dly found for B1: ( 0, 13, 8)
4688 11:53:50.408529 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:53:50.412178 Total UI for P1: 0, mck2ui 16
4690 11:53:50.415632 best dqsien dly found for B0: ( 0, 13, 12)
4691 11:53:50.418959 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4692 11:53:50.422163 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4693 11:53:50.422580
4694 11:53:50.425550 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4695 11:53:50.428864 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4696 11:53:50.432194 [Gating] SW calibration Done
4697 11:53:50.432691 ==
4698 11:53:50.435705 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 11:53:50.438412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 11:53:50.442240 ==
4701 11:53:50.442762 RX Vref Scan: 0
4702 11:53:50.443095
4703 11:53:50.445158 RX Vref 0 -> 0, step: 1
4704 11:53:50.445616
4705 11:53:50.448635 RX Delay -230 -> 252, step: 16
4706 11:53:50.451886 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4707 11:53:50.455608 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4708 11:53:50.458403 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4709 11:53:50.465056 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4710 11:53:50.468768 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4711 11:53:50.471780 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4712 11:53:50.475573 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4713 11:53:50.478588 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4714 11:53:50.485463 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4715 11:53:50.488679 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4716 11:53:50.491924 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4717 11:53:50.494653 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4718 11:53:50.501833 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4719 11:53:50.505256 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4720 11:53:50.508504 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4721 11:53:50.511410 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4722 11:53:50.511827 ==
4723 11:53:50.514702 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:53:50.522035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:53:50.522554 ==
4726 11:53:50.522885 DQS Delay:
4727 11:53:50.524647 DQS0 = 0, DQS1 = 0
4728 11:53:50.525162 DQM Delay:
4729 11:53:50.528570 DQM0 = 50, DQM1 = 48
4730 11:53:50.529090 DQ Delay:
4731 11:53:50.531794 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4732 11:53:50.534924 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4733 11:53:50.537681 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4734 11:53:50.540882 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4735 11:53:50.541298
4736 11:53:50.541669
4737 11:53:50.541982 ==
4738 11:53:50.544285 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:53:50.548081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:53:50.548606 ==
4741 11:53:50.548942
4742 11:53:50.549248
4743 11:53:50.551189 TX Vref Scan disable
4744 11:53:50.554839 == TX Byte 0 ==
4745 11:53:50.557925 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4746 11:53:50.561542 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4747 11:53:50.564724 == TX Byte 1 ==
4748 11:53:50.568114 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4749 11:53:50.571263 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4750 11:53:50.571784 ==
4751 11:53:50.574438 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 11:53:50.578290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 11:53:50.581546 ==
4754 11:53:50.582185
4755 11:53:50.582532
4756 11:53:50.582838 TX Vref Scan disable
4757 11:53:50.585471 == TX Byte 0 ==
4758 11:53:50.588767 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 11:53:50.591863 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 11:53:50.595003 == TX Byte 1 ==
4761 11:53:50.598363 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 11:53:50.605146 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 11:53:50.605685
4764 11:53:50.606016 [DATLAT]
4765 11:53:50.606322 Freq=600, CH1 RK1
4766 11:53:50.606615
4767 11:53:50.608644 DATLAT Default: 0x9
4768 11:53:50.609160 0, 0xFFFF, sum = 0
4769 11:53:50.611631 1, 0xFFFF, sum = 0
4770 11:53:50.612050 2, 0xFFFF, sum = 0
4771 11:53:50.614813 3, 0xFFFF, sum = 0
4772 11:53:50.618136 4, 0xFFFF, sum = 0
4773 11:53:50.618559 5, 0xFFFF, sum = 0
4774 11:53:50.621967 6, 0xFFFF, sum = 0
4775 11:53:50.622489 7, 0xFFFF, sum = 0
4776 11:53:50.622878 8, 0x0, sum = 1
4777 11:53:50.624861 9, 0x0, sum = 2
4778 11:53:50.625406 10, 0x0, sum = 3
4779 11:53:50.628279 11, 0x0, sum = 4
4780 11:53:50.628803 best_step = 9
4781 11:53:50.629229
4782 11:53:50.629791 ==
4783 11:53:50.631443 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:53:50.637663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:53:50.638082 ==
4786 11:53:50.638413 RX Vref Scan: 0
4787 11:53:50.638764
4788 11:53:50.641287 RX Vref 0 -> 0, step: 1
4789 11:53:50.641751
4790 11:53:50.644992 RX Delay -163 -> 252, step: 8
4791 11:53:50.648126 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4792 11:53:50.654980 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4793 11:53:50.657932 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4794 11:53:50.661408 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4795 11:53:50.665100 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4796 11:53:50.668220 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4797 11:53:50.671646 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4798 11:53:50.678101 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4799 11:53:50.681714 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4800 11:53:50.684499 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4801 11:53:50.688158 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4802 11:53:50.694608 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4803 11:53:50.698537 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4804 11:53:50.701841 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4805 11:53:50.704734 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4806 11:53:50.708169 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4807 11:53:50.711411 ==
4808 11:53:50.711981 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 11:53:50.718511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 11:53:50.719050 ==
4811 11:53:50.719387 DQS Delay:
4812 11:53:50.721535 DQS0 = 0, DQS1 = 0
4813 11:53:50.721996 DQM Delay:
4814 11:53:50.724565 DQM0 = 49, DQM1 = 45
4815 11:53:50.724987 DQ Delay:
4816 11:53:50.728317 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4817 11:53:50.731505 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4818 11:53:50.734355 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4819 11:53:50.738265 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4820 11:53:50.738791
4821 11:53:50.739127
4822 11:53:50.744460 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4823 11:53:50.748088 CH1 RK1: MR19=808, MR18=6921
4824 11:53:50.754532 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4825 11:53:50.758120 [RxdqsGatingPostProcess] freq 600
4826 11:53:50.764576 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 11:53:50.765103 Pre-setting of DQS Precalculation
4828 11:53:50.771135 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 11:53:50.777763 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 11:53:50.784042 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 11:53:50.784556
4832 11:53:50.784890
4833 11:53:50.787841 [Calibration Summary] 1200 Mbps
4834 11:53:50.790899 CH 0, Rank 0
4835 11:53:50.791323 SW Impedance : PASS
4836 11:53:50.794329 DUTY Scan : NO K
4837 11:53:50.794859 ZQ Calibration : PASS
4838 11:53:50.798111 Jitter Meter : NO K
4839 11:53:50.801035 CBT Training : PASS
4840 11:53:50.801462 Write leveling : PASS
4841 11:53:50.804179 RX DQS gating : PASS
4842 11:53:50.807736 RX DQ/DQS(RDDQC) : PASS
4843 11:53:50.808161 TX DQ/DQS : PASS
4844 11:53:50.810985 RX DATLAT : PASS
4845 11:53:50.814159 RX DQ/DQS(Engine): PASS
4846 11:53:50.814675 TX OE : NO K
4847 11:53:50.817611 All Pass.
4848 11:53:50.818067
4849 11:53:50.818400 CH 0, Rank 1
4850 11:53:50.821033 SW Impedance : PASS
4851 11:53:50.821558 DUTY Scan : NO K
4852 11:53:50.824618 ZQ Calibration : PASS
4853 11:53:50.827888 Jitter Meter : NO K
4854 11:53:50.828331 CBT Training : PASS
4855 11:53:50.830783 Write leveling : PASS
4856 11:53:50.834409 RX DQS gating : PASS
4857 11:53:50.834905 RX DQ/DQS(RDDQC) : PASS
4858 11:53:50.837662 TX DQ/DQS : PASS
4859 11:53:50.838089 RX DATLAT : PASS
4860 11:53:50.840876 RX DQ/DQS(Engine): PASS
4861 11:53:50.844080 TX OE : NO K
4862 11:53:50.844506 All Pass.
4863 11:53:50.844841
4864 11:53:50.845149 CH 1, Rank 0
4865 11:53:50.847321 SW Impedance : PASS
4866 11:53:50.851168 DUTY Scan : NO K
4867 11:53:50.851618 ZQ Calibration : PASS
4868 11:53:50.854361 Jitter Meter : NO K
4869 11:53:50.857555 CBT Training : PASS
4870 11:53:50.858018 Write leveling : PASS
4871 11:53:50.860910 RX DQS gating : PASS
4872 11:53:50.864688 RX DQ/DQS(RDDQC) : PASS
4873 11:53:50.865213 TX DQ/DQS : PASS
4874 11:53:50.867840 RX DATLAT : PASS
4875 11:53:50.870984 RX DQ/DQS(Engine): PASS
4876 11:53:50.871420 TX OE : NO K
4877 11:53:50.871759 All Pass.
4878 11:53:50.874114
4879 11:53:50.874538 CH 1, Rank 1
4880 11:53:50.877559 SW Impedance : PASS
4881 11:53:50.878023 DUTY Scan : NO K
4882 11:53:50.880739 ZQ Calibration : PASS
4883 11:53:50.881160 Jitter Meter : NO K
4884 11:53:50.883866 CBT Training : PASS
4885 11:53:50.887740 Write leveling : PASS
4886 11:53:50.888164 RX DQS gating : PASS
4887 11:53:50.890631 RX DQ/DQS(RDDQC) : PASS
4888 11:53:50.894197 TX DQ/DQS : PASS
4889 11:53:50.894617 RX DATLAT : PASS
4890 11:53:50.897320 RX DQ/DQS(Engine): PASS
4891 11:53:50.901289 TX OE : NO K
4892 11:53:50.901775 All Pass.
4893 11:53:50.902174
4894 11:53:50.904288 DramC Write-DBI off
4895 11:53:50.904739 PER_BANK_REFRESH: Hybrid Mode
4896 11:53:50.907476 TX_TRACKING: ON
4897 11:53:50.913849 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 11:53:50.920376 [FAST_K] Save calibration result to emmc
4899 11:53:50.924273 dramc_set_vcore_voltage set vcore to 662500
4900 11:53:50.924769 Read voltage for 933, 3
4901 11:53:50.927762 Vio18 = 0
4902 11:53:50.928307 Vcore = 662500
4903 11:53:50.928646 Vdram = 0
4904 11:53:50.930543 Vddq = 0
4905 11:53:50.930958 Vmddr = 0
4906 11:53:50.933997 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 11:53:50.940785 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 11:53:50.943964 MEM_TYPE=3, freq_sel=17
4909 11:53:50.947125 sv_algorithm_assistance_LP4_1600
4910 11:53:50.950822 ============ PULL DRAM RESETB DOWN ============
4911 11:53:50.954326 ========== PULL DRAM RESETB DOWN end =========
4912 11:53:50.960671 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 11:53:50.963916 ===================================
4914 11:53:50.964435 LPDDR4 DRAM CONFIGURATION
4915 11:53:50.967324 ===================================
4916 11:53:50.970814 EX_ROW_EN[0] = 0x0
4917 11:53:50.971280 EX_ROW_EN[1] = 0x0
4918 11:53:50.973878 LP4Y_EN = 0x0
4919 11:53:50.974300 WORK_FSP = 0x0
4920 11:53:50.977293 WL = 0x3
4921 11:53:50.977759 RL = 0x3
4922 11:53:50.980482 BL = 0x2
4923 11:53:50.980905 RPST = 0x0
4924 11:53:50.983737 RD_PRE = 0x0
4925 11:53:50.987703 WR_PRE = 0x1
4926 11:53:50.988228 WR_PST = 0x0
4927 11:53:50.990257 DBI_WR = 0x0
4928 11:53:50.990681 DBI_RD = 0x0
4929 11:53:50.993909 OTF = 0x1
4930 11:53:50.996932 ===================================
4931 11:53:51.000564 ===================================
4932 11:53:51.001030 ANA top config
4933 11:53:51.003758 ===================================
4934 11:53:51.006820 DLL_ASYNC_EN = 0
4935 11:53:51.010812 ALL_SLAVE_EN = 1
4936 11:53:51.011236 NEW_RANK_MODE = 1
4937 11:53:51.013819 DLL_IDLE_MODE = 1
4938 11:53:51.016914 LP45_APHY_COMB_EN = 1
4939 11:53:51.020579 TX_ODT_DIS = 1
4940 11:53:51.021112 NEW_8X_MODE = 1
4941 11:53:51.024081 ===================================
4942 11:53:51.027167 ===================================
4943 11:53:51.030831 data_rate = 1866
4944 11:53:51.033992 CKR = 1
4945 11:53:51.036927 DQ_P2S_RATIO = 8
4946 11:53:51.040875 ===================================
4947 11:53:51.044155 CA_P2S_RATIO = 8
4948 11:53:51.047057 DQ_CA_OPEN = 0
4949 11:53:51.047470 DQ_SEMI_OPEN = 0
4950 11:53:51.050658 CA_SEMI_OPEN = 0
4951 11:53:51.053870 CA_FULL_RATE = 0
4952 11:53:51.056977 DQ_CKDIV4_EN = 1
4953 11:53:51.060439 CA_CKDIV4_EN = 1
4954 11:53:51.064791 CA_PREDIV_EN = 0
4955 11:53:51.065308 PH8_DLY = 0
4956 11:53:51.067701 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 11:53:51.070606 DQ_AAMCK_DIV = 4
4958 11:53:51.073959 CA_AAMCK_DIV = 4
4959 11:53:51.076714 CA_ADMCK_DIV = 4
4960 11:53:51.077131 DQ_TRACK_CA_EN = 0
4961 11:53:51.080371 CA_PICK = 933
4962 11:53:51.083906 CA_MCKIO = 933
4963 11:53:51.087310 MCKIO_SEMI = 0
4964 11:53:51.090475 PLL_FREQ = 3732
4965 11:53:51.093656 DQ_UI_PI_RATIO = 32
4966 11:53:51.096878 CA_UI_PI_RATIO = 0
4967 11:53:51.100781 ===================================
4968 11:53:51.103678 ===================================
4969 11:53:51.104105 memory_type:LPDDR4
4970 11:53:51.107026 GP_NUM : 10
4971 11:53:51.110436 SRAM_EN : 1
4972 11:53:51.110960 MD32_EN : 0
4973 11:53:51.113569 ===================================
4974 11:53:51.117312 [ANA_INIT] >>>>>>>>>>>>>>
4975 11:53:51.120805 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 11:53:51.123787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 11:53:51.126686 ===================================
4978 11:53:51.130867 data_rate = 1866,PCW = 0X8f00
4979 11:53:51.133683 ===================================
4980 11:53:51.136954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 11:53:51.140273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 11:53:51.146815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 11:53:51.149893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 11:53:51.153434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 11:53:51.156841 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 11:53:51.159782 [ANA_INIT] flow start
4987 11:53:51.163127 [ANA_INIT] PLL >>>>>>>>
4988 11:53:51.163548 [ANA_INIT] PLL <<<<<<<<
4989 11:53:51.166515 [ANA_INIT] MIDPI >>>>>>>>
4990 11:53:51.169663 [ANA_INIT] MIDPI <<<<<<<<
4991 11:53:51.173128 [ANA_INIT] DLL >>>>>>>>
4992 11:53:51.173688 [ANA_INIT] flow end
4993 11:53:51.176834 ============ LP4 DIFF to SE enter ============
4994 11:53:51.183225 ============ LP4 DIFF to SE exit ============
4995 11:53:51.183763 [ANA_INIT] <<<<<<<<<<<<<
4996 11:53:51.187275 [Flow] Enable top DCM control >>>>>
4997 11:53:51.189867 [Flow] Enable top DCM control <<<<<
4998 11:53:51.193378 Enable DLL master slave shuffle
4999 11:53:51.199275 ==============================================================
5000 11:53:51.199703 Gating Mode config
5001 11:53:51.206336 ==============================================================
5002 11:53:51.209548 Config description:
5003 11:53:51.219388 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 11:53:51.225460 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 11:53:51.229004 SELPH_MODE 0: By rank 1: By Phase
5006 11:53:51.236112 ==============================================================
5007 11:53:51.238938 GAT_TRACK_EN = 1
5008 11:53:51.242112 RX_GATING_MODE = 2
5009 11:53:51.245432 RX_GATING_TRACK_MODE = 2
5010 11:53:51.245889 SELPH_MODE = 1
5011 11:53:51.249545 PICG_EARLY_EN = 1
5012 11:53:51.252582 VALID_LAT_VALUE = 1
5013 11:53:51.258615 ==============================================================
5014 11:53:51.262331 Enter into Gating configuration >>>>
5015 11:53:51.265563 Exit from Gating configuration <<<<
5016 11:53:51.268639 Enter into DVFS_PRE_config >>>>>
5017 11:53:51.278471 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 11:53:51.282340 Exit from DVFS_PRE_config <<<<<
5019 11:53:51.285784 Enter into PICG configuration >>>>
5020 11:53:51.288397 Exit from PICG configuration <<<<
5021 11:53:51.291669 [RX_INPUT] configuration >>>>>
5022 11:53:51.295404 [RX_INPUT] configuration <<<<<
5023 11:53:51.298668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 11:53:51.305130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 11:53:51.311604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 11:53:51.318549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 11:53:51.325188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 11:53:51.328315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 11:53:51.335252 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 11:53:51.338581 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 11:53:51.341449 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 11:53:51.344918 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 11:53:51.351850 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 11:53:51.355128 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 11:53:51.358460 ===================================
5036 11:53:51.361375 LPDDR4 DRAM CONFIGURATION
5037 11:53:51.364864 ===================================
5038 11:53:51.365281 EX_ROW_EN[0] = 0x0
5039 11:53:51.368289 EX_ROW_EN[1] = 0x0
5040 11:53:51.368751 LP4Y_EN = 0x0
5041 11:53:51.371260 WORK_FSP = 0x0
5042 11:53:51.371677 WL = 0x3
5043 11:53:51.374949 RL = 0x3
5044 11:53:51.375364 BL = 0x2
5045 11:53:51.377776 RPST = 0x0
5046 11:53:51.381464 RD_PRE = 0x0
5047 11:53:51.381911 WR_PRE = 0x1
5048 11:53:51.384632 WR_PST = 0x0
5049 11:53:51.385051 DBI_WR = 0x0
5050 11:53:51.387568 DBI_RD = 0x0
5051 11:53:51.387985 OTF = 0x1
5052 11:53:51.391017 ===================================
5053 11:53:51.394161 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 11:53:51.401320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 11:53:51.404681 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 11:53:51.407775 ===================================
5057 11:53:51.411136 LPDDR4 DRAM CONFIGURATION
5058 11:53:51.414458 ===================================
5059 11:53:51.414877 EX_ROW_EN[0] = 0x10
5060 11:53:51.418334 EX_ROW_EN[1] = 0x0
5061 11:53:51.418800 LP4Y_EN = 0x0
5062 11:53:51.421076 WORK_FSP = 0x0
5063 11:53:51.421492 WL = 0x3
5064 11:53:51.424423 RL = 0x3
5065 11:53:51.424840 BL = 0x2
5066 11:53:51.427565 RPST = 0x0
5067 11:53:51.430930 RD_PRE = 0x0
5068 11:53:51.431354 WR_PRE = 0x1
5069 11:53:51.434207 WR_PST = 0x0
5070 11:53:51.434623 DBI_WR = 0x0
5071 11:53:51.437622 DBI_RD = 0x0
5072 11:53:51.438056 OTF = 0x1
5073 11:53:51.440825 ===================================
5074 11:53:51.447602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 11:53:51.451110 nWR fixed to 30
5076 11:53:51.454537 [ModeRegInit_LP4] CH0 RK0
5077 11:53:51.454955 [ModeRegInit_LP4] CH0 RK1
5078 11:53:51.457646 [ModeRegInit_LP4] CH1 RK0
5079 11:53:51.461366 [ModeRegInit_LP4] CH1 RK1
5080 11:53:51.461868 match AC timing 9
5081 11:53:51.467933 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 11:53:51.471001 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 11:53:51.475106 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 11:53:51.480731 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 11:53:51.484029 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 11:53:51.484548 ==
5087 11:53:51.487849 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:53:51.491000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:53:51.491585 ==
5090 11:53:51.497708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 11:53:51.504565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5092 11:53:51.507940 [CA 0] Center 37 (6~68) winsize 63
5093 11:53:51.510900 [CA 1] Center 37 (6~68) winsize 63
5094 11:53:51.514290 [CA 2] Center 34 (4~65) winsize 62
5095 11:53:51.517392 [CA 3] Center 33 (3~64) winsize 62
5096 11:53:51.520608 [CA 4] Center 33 (3~64) winsize 62
5097 11:53:51.524522 [CA 5] Center 32 (2~62) winsize 61
5098 11:53:51.525033
5099 11:53:51.527831 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5100 11:53:51.528356
5101 11:53:51.530785 [CATrainingPosCal] consider 1 rank data
5102 11:53:51.534043 u2DelayCellTimex100 = 270/100 ps
5103 11:53:51.537645 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5104 11:53:51.540742 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5105 11:53:51.543866 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5106 11:53:51.546966 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5107 11:53:51.550115 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5108 11:53:51.556907 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5109 11:53:51.557347
5110 11:53:51.560305 CA PerBit enable=1, Macro0, CA PI delay=32
5111 11:53:51.560726
5112 11:53:51.563885 [CBTSetCACLKResult] CA Dly = 32
5113 11:53:51.564267 CS Dly: 5 (0~36)
5114 11:53:51.564590 ==
5115 11:53:51.567306 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 11:53:51.570461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 11:53:51.573960 ==
5118 11:53:51.577028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 11:53:51.583307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 11:53:51.586702 [CA 0] Center 37 (6~68) winsize 63
5121 11:53:51.590193 [CA 1] Center 37 (6~68) winsize 63
5122 11:53:51.593417 [CA 2] Center 34 (4~65) winsize 62
5123 11:53:51.597042 [CA 3] Center 34 (3~65) winsize 63
5124 11:53:51.600300 [CA 4] Center 33 (3~63) winsize 61
5125 11:53:51.603257 [CA 5] Center 32 (2~62) winsize 61
5126 11:53:51.603674
5127 11:53:51.606869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 11:53:51.607428
5129 11:53:51.610176 [CATrainingPosCal] consider 2 rank data
5130 11:53:51.613417 u2DelayCellTimex100 = 270/100 ps
5131 11:53:51.617000 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5132 11:53:51.620527 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5133 11:53:51.623828 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5134 11:53:51.627157 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5135 11:53:51.633555 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5136 11:53:51.636797 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5137 11:53:51.637209
5138 11:53:51.639970 CA PerBit enable=1, Macro0, CA PI delay=32
5139 11:53:51.640389
5140 11:53:51.643297 [CBTSetCACLKResult] CA Dly = 32
5141 11:53:51.643714 CS Dly: 5 (0~37)
5142 11:53:51.644041
5143 11:53:51.646808 ----->DramcWriteLeveling(PI) begin...
5144 11:53:51.647270 ==
5145 11:53:51.649963 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 11:53:51.656847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:53:51.657281 ==
5148 11:53:51.660491 Write leveling (Byte 0): 33 => 33
5149 11:53:51.661117 Write leveling (Byte 1): 28 => 28
5150 11:53:51.663147 DramcWriteLeveling(PI) end<-----
5151 11:53:51.663728
5152 11:53:51.666685 ==
5153 11:53:51.670046 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 11:53:51.673159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 11:53:51.673624 ==
5156 11:53:51.676755 [Gating] SW mode calibration
5157 11:53:51.683107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 11:53:51.686421 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 11:53:51.692991 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5160 11:53:51.697327 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 11:53:51.700362 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 11:53:51.706777 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 11:53:51.710086 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 11:53:51.713567 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 11:53:51.720050 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5166 11:53:51.723030 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
5167 11:53:51.726387 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5168 11:53:51.733493 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 11:53:51.736615 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 11:53:51.739623 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 11:53:51.746270 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 11:53:51.749462 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 11:53:51.752751 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5174 11:53:51.756141 0 15 28 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
5175 11:53:51.763464 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5176 11:53:51.766032 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 11:53:51.769409 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 11:53:51.775878 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 11:53:51.779668 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 11:53:51.782749 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:53:51.789268 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:53:51.792724 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5183 11:53:51.796006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 11:53:51.802956 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:53:51.806492 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:53:51.809165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:53:51.815835 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:53:51.818986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:53:51.822313 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:53:51.829034 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:53:51.832107 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:53:51.835569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:53:51.842296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:53:51.845805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:53:51.848845 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:53:51.855857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:53:51.859161 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:53:51.862350 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5199 11:53:51.869054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 11:53:51.869469 Total UI for P1: 0, mck2ui 16
5201 11:53:51.875382 best dqsien dly found for B0: ( 1, 2, 28)
5202 11:53:51.878634 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:53:51.882545 Total UI for P1: 0, mck2ui 16
5204 11:53:51.885927 best dqsien dly found for B1: ( 1, 3, 0)
5205 11:53:51.888851 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5206 11:53:51.892459 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5207 11:53:51.892965
5208 11:53:51.895311 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5209 11:53:51.898788 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5210 11:53:51.901929 [Gating] SW calibration Done
5211 11:53:51.902344 ==
5212 11:53:51.905507 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 11:53:51.908866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 11:53:51.912015 ==
5215 11:53:51.912437 RX Vref Scan: 0
5216 11:53:51.912772
5217 11:53:51.915379 RX Vref 0 -> 0, step: 1
5218 11:53:51.915814
5219 11:53:51.916139 RX Delay -80 -> 252, step: 8
5220 11:53:51.922182 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5221 11:53:51.925537 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5222 11:53:51.928944 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5223 11:53:51.932085 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5224 11:53:51.935291 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5225 11:53:51.942239 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5226 11:53:51.945328 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5227 11:53:51.948786 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5228 11:53:51.952032 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5229 11:53:51.955514 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5230 11:53:51.958665 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5231 11:53:51.965256 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5232 11:53:51.968668 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5233 11:53:51.971935 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5234 11:53:51.975074 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5235 11:53:51.978126 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5236 11:53:51.981394 ==
5237 11:53:51.984491 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:53:51.988242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:53:51.988467 ==
5240 11:53:51.988646 DQS Delay:
5241 11:53:51.991774 DQS0 = 0, DQS1 = 0
5242 11:53:51.992068 DQM Delay:
5243 11:53:51.995124 DQM0 = 104, DQM1 = 95
5244 11:53:51.995348 DQ Delay:
5245 11:53:51.998344 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5246 11:53:52.001409 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5247 11:53:52.004686 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5248 11:53:52.008338 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5249 11:53:52.008562
5250 11:53:52.008814
5251 11:53:52.009071 ==
5252 11:53:52.011571 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 11:53:52.014677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 11:53:52.017907 ==
5255 11:53:52.018135
5256 11:53:52.018308
5257 11:53:52.018577 TX Vref Scan disable
5258 11:53:52.021554 == TX Byte 0 ==
5259 11:53:52.024526 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5260 11:53:52.027683 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5261 11:53:52.031298 == TX Byte 1 ==
5262 11:53:52.034856 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5263 11:53:52.038190 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5264 11:53:52.041401 ==
5265 11:53:52.041707 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:53:52.048038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:53:52.048133 ==
5268 11:53:52.048199
5269 11:53:52.048259
5270 11:53:52.051102 TX Vref Scan disable
5271 11:53:52.051208 == TX Byte 0 ==
5272 11:53:52.057741 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5273 11:53:52.060860 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5274 11:53:52.060942 == TX Byte 1 ==
5275 11:53:52.067669 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5276 11:53:52.071113 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5277 11:53:52.071218
5278 11:53:52.071300 [DATLAT]
5279 11:53:52.074114 Freq=933, CH0 RK0
5280 11:53:52.074195
5281 11:53:52.074259 DATLAT Default: 0xd
5282 11:53:52.078398 0, 0xFFFF, sum = 0
5283 11:53:52.078480 1, 0xFFFF, sum = 0
5284 11:53:52.081364 2, 0xFFFF, sum = 0
5285 11:53:52.081446 3, 0xFFFF, sum = 0
5286 11:53:52.083966 4, 0xFFFF, sum = 0
5287 11:53:52.084074 5, 0xFFFF, sum = 0
5288 11:53:52.087715 6, 0xFFFF, sum = 0
5289 11:53:52.087813 7, 0xFFFF, sum = 0
5290 11:53:52.091457 8, 0xFFFF, sum = 0
5291 11:53:52.091540 9, 0xFFFF, sum = 0
5292 11:53:52.094800 10, 0x0, sum = 1
5293 11:53:52.094881 11, 0x0, sum = 2
5294 11:53:52.097306 12, 0x0, sum = 3
5295 11:53:52.097387 13, 0x0, sum = 4
5296 11:53:52.101456 best_step = 11
5297 11:53:52.101561
5298 11:53:52.101696 ==
5299 11:53:52.104193 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 11:53:52.108183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 11:53:52.108599 ==
5302 11:53:52.111328 RX Vref Scan: 1
5303 11:53:52.111743
5304 11:53:52.112068 RX Vref 0 -> 0, step: 1
5305 11:53:52.112374
5306 11:53:52.115035 RX Delay -53 -> 252, step: 4
5307 11:53:52.115451
5308 11:53:52.118258 Set Vref, RX VrefLevel [Byte0]: 55
5309 11:53:52.121243 [Byte1]: 58
5310 11:53:52.125236
5311 11:53:52.125726 Final RX Vref Byte 0 = 55 to rank0
5312 11:53:52.128583 Final RX Vref Byte 1 = 58 to rank0
5313 11:53:52.131831 Final RX Vref Byte 0 = 55 to rank1
5314 11:53:52.135822 Final RX Vref Byte 1 = 58 to rank1==
5315 11:53:52.138913 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 11:53:52.145037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 11:53:52.145457 ==
5318 11:53:52.145829 DQS Delay:
5319 11:53:52.146141 DQS0 = 0, DQS1 = 0
5320 11:53:52.148533 DQM Delay:
5321 11:53:52.148944 DQM0 = 104, DQM1 = 98
5322 11:53:52.152035 DQ Delay:
5323 11:53:52.155430 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =102
5324 11:53:52.158661 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5325 11:53:52.162136 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5326 11:53:52.165454 DQ12 =102, DQ13 =104, DQ14 =108, DQ15 =106
5327 11:53:52.165956
5328 11:53:52.166293
5329 11:53:52.171808 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5330 11:53:52.174984 CH0 RK0: MR19=505, MR18=322A
5331 11:53:52.182131 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5332 11:53:52.182591
5333 11:53:52.185031 ----->DramcWriteLeveling(PI) begin...
5334 11:53:52.185551 ==
5335 11:53:52.188900 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 11:53:52.191787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 11:53:52.192246 ==
5338 11:53:52.195515 Write leveling (Byte 0): 32 => 32
5339 11:53:52.198750 Write leveling (Byte 1): 30 => 30
5340 11:53:52.201809 DramcWriteLeveling(PI) end<-----
5341 11:53:52.202229
5342 11:53:52.202562 ==
5343 11:53:52.205233 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:53:52.212208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:53:52.212649 ==
5346 11:53:52.213063 [Gating] SW mode calibration
5347 11:53:52.221858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 11:53:52.225302 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 11:53:52.228218 0 14 0 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
5350 11:53:52.235052 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 11:53:52.238014 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 11:53:52.241693 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 11:53:52.248077 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 11:53:52.251397 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:53:52.254495 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
5356 11:53:52.261587 0 14 28 | B1->B0 | 2d2d 2b2b | 0 0 | (0 1) (0 1)
5357 11:53:52.264560 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5358 11:53:52.267812 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 11:53:52.274734 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 11:53:52.277609 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 11:53:52.280982 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:53:52.287598 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:53:52.291598 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5364 11:53:52.294551 0 15 28 | B1->B0 | 3636 3535 | 0 0 | (0 0) (0 0)
5365 11:53:52.301238 1 0 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
5366 11:53:52.304663 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 11:53:52.308018 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 11:53:52.314112 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:53:52.317975 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:53:52.321156 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:53:52.327466 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:53:52.330714 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5373 11:53:52.334389 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5374 11:53:52.340567 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:53:52.344098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:53:52.347293 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:53:52.350770 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:53:52.357822 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:53:52.361090 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:53:52.364081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:53:52.370583 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:53:52.374258 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:53:52.377280 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:53:52.384110 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:53:52.387203 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:53:52.390788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:53:52.397260 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:53:52.400695 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5389 11:53:52.404315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5390 11:53:52.407549 Total UI for P1: 0, mck2ui 16
5391 11:53:52.410994 best dqsien dly found for B0: ( 1, 2, 28)
5392 11:53:52.417294 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 11:53:52.417560 Total UI for P1: 0, mck2ui 16
5394 11:53:52.424335 best dqsien dly found for B1: ( 1, 3, 0)
5395 11:53:52.427860 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5396 11:53:52.430916 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5397 11:53:52.431165
5398 11:53:52.433771 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 11:53:52.437634 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5400 11:53:52.440887 [Gating] SW calibration Done
5401 11:53:52.441077 ==
5402 11:53:52.444173 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 11:53:52.446865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 11:53:52.447108 ==
5405 11:53:52.450836 RX Vref Scan: 0
5406 11:53:52.451026
5407 11:53:52.451176 RX Vref 0 -> 0, step: 1
5408 11:53:52.451317
5409 11:53:52.453926 RX Delay -80 -> 252, step: 8
5410 11:53:52.457473 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5411 11:53:52.463895 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5412 11:53:52.467220 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5413 11:53:52.470666 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5414 11:53:52.473543 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5415 11:53:52.476829 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5416 11:53:52.480896 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5417 11:53:52.487003 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5418 11:53:52.490524 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5419 11:53:52.493736 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5420 11:53:52.496825 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5421 11:53:52.500371 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5422 11:53:52.503562 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5423 11:53:52.510400 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5424 11:53:52.513482 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5425 11:53:52.516920 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5426 11:53:52.517020 ==
5427 11:53:52.520201 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 11:53:52.523344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 11:53:52.523483 ==
5430 11:53:52.526984 DQS Delay:
5431 11:53:52.527098 DQS0 = 0, DQS1 = 0
5432 11:53:52.530074 DQM Delay:
5433 11:53:52.530199 DQM0 = 103, DQM1 = 95
5434 11:53:52.530325 DQ Delay:
5435 11:53:52.533591 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5436 11:53:52.536653 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5437 11:53:52.540327 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5438 11:53:52.546930 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5439 11:53:52.547110
5440 11:53:52.547292
5441 11:53:52.547462 ==
5442 11:53:52.550274 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 11:53:52.553515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 11:53:52.553750 ==
5445 11:53:52.553961
5446 11:53:52.554159
5447 11:53:52.556875 TX Vref Scan disable
5448 11:53:52.557082 == TX Byte 0 ==
5449 11:53:52.563090 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5450 11:53:52.566437 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5451 11:53:52.566646 == TX Byte 1 ==
5452 11:53:52.573209 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5453 11:53:52.576652 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5454 11:53:52.576961 ==
5455 11:53:52.579932 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:53:52.583234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:53:52.583437 ==
5458 11:53:52.583598
5459 11:53:52.583747
5460 11:53:52.586656 TX Vref Scan disable
5461 11:53:52.590115 == TX Byte 0 ==
5462 11:53:52.593062 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5463 11:53:52.596620 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5464 11:53:52.599603 == TX Byte 1 ==
5465 11:53:52.603424 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5466 11:53:52.606658 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5467 11:53:52.606861
5468 11:53:52.610102 [DATLAT]
5469 11:53:52.610324 Freq=933, CH0 RK1
5470 11:53:52.610507
5471 11:53:52.612816 DATLAT Default: 0xb
5472 11:53:52.613027 0, 0xFFFF, sum = 0
5473 11:53:52.616197 1, 0xFFFF, sum = 0
5474 11:53:52.616424 2, 0xFFFF, sum = 0
5475 11:53:52.619588 3, 0xFFFF, sum = 0
5476 11:53:52.619825 4, 0xFFFF, sum = 0
5477 11:53:52.622892 5, 0xFFFF, sum = 0
5478 11:53:52.623093 6, 0xFFFF, sum = 0
5479 11:53:52.626819 7, 0xFFFF, sum = 0
5480 11:53:52.627020 8, 0xFFFF, sum = 0
5481 11:53:52.629446 9, 0xFFFF, sum = 0
5482 11:53:52.629748 10, 0x0, sum = 1
5483 11:53:52.633269 11, 0x0, sum = 2
5484 11:53:52.633470 12, 0x0, sum = 3
5485 11:53:52.636246 13, 0x0, sum = 4
5486 11:53:52.636446 best_step = 11
5487 11:53:52.636601
5488 11:53:52.636745 ==
5489 11:53:52.639890 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 11:53:52.646850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 11:53:52.647049 ==
5492 11:53:52.647204 RX Vref Scan: 0
5493 11:53:52.647349
5494 11:53:52.649741 RX Vref 0 -> 0, step: 1
5495 11:53:52.649940
5496 11:53:52.653570 RX Delay -45 -> 252, step: 4
5497 11:53:52.656302 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5498 11:53:52.660215 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5499 11:53:52.666699 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5500 11:53:52.669830 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5501 11:53:52.673215 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5502 11:53:52.676465 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5503 11:53:52.680320 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5504 11:53:52.686790 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5505 11:53:52.690051 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5506 11:53:52.693470 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5507 11:53:52.696878 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5508 11:53:52.699822 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5509 11:53:52.702595 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5510 11:53:52.709559 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5511 11:53:52.713188 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5512 11:53:52.716441 iDelay=199, Bit 15, Center 102 (23 ~ 182) 160
5513 11:53:52.716524 ==
5514 11:53:52.719602 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 11:53:52.722877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 11:53:52.726288 ==
5517 11:53:52.726382 DQS Delay:
5518 11:53:52.726457 DQS0 = 0, DQS1 = 0
5519 11:53:52.729365 DQM Delay:
5520 11:53:52.729489 DQM0 = 104, DQM1 = 96
5521 11:53:52.732811 DQ Delay:
5522 11:53:52.735881 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5523 11:53:52.739414 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5524 11:53:52.742800 DQ8 =88, DQ9 =86, DQ10 =96, DQ11 =90
5525 11:53:52.746119 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =102
5526 11:53:52.746244
5527 11:53:52.746350
5528 11:53:52.752930 [DQSOSCAuto] RK1, (LSB)MR18= 0x2800, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5529 11:53:52.756295 CH0 RK1: MR19=505, MR18=2800
5530 11:53:52.762539 CH0_RK1: MR19=0x505, MR18=0x2800, DQSOSC=409, MR23=63, INC=64, DEC=43
5531 11:53:52.766643 [RxdqsGatingPostProcess] freq 933
5532 11:53:52.769552 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 11:53:52.772932 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 11:53:52.776257 best DQS1 dly(2T, 0.5T) = (0, 11)
5535 11:53:52.779361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 11:53:52.782865 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5537 11:53:52.785794 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 11:53:52.789753 best DQS1 dly(2T, 0.5T) = (0, 11)
5539 11:53:52.792902 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 11:53:52.796073 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5541 11:53:52.799406 Pre-setting of DQS Precalculation
5542 11:53:52.802503 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 11:53:52.806197 ==
5544 11:53:52.809392 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 11:53:52.812844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 11:53:52.813252 ==
5547 11:53:52.816270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 11:53:52.822589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5549 11:53:52.826340 [CA 0] Center 36 (6~67) winsize 62
5550 11:53:52.829681 [CA 1] Center 36 (6~67) winsize 62
5551 11:53:52.832909 [CA 2] Center 34 (4~65) winsize 62
5552 11:53:52.836317 [CA 3] Center 34 (4~65) winsize 62
5553 11:53:52.839437 [CA 4] Center 34 (4~65) winsize 62
5554 11:53:52.842915 [CA 5] Center 33 (3~64) winsize 62
5555 11:53:52.843412
5556 11:53:52.846377 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5557 11:53:52.846655
5558 11:53:52.849677 [CATrainingPosCal] consider 1 rank data
5559 11:53:52.852984 u2DelayCellTimex100 = 270/100 ps
5560 11:53:52.856210 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 11:53:52.862600 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 11:53:52.866236 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 11:53:52.869544 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5564 11:53:52.872921 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 11:53:52.876226 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 11:53:52.876441
5567 11:53:52.879229 CA PerBit enable=1, Macro0, CA PI delay=33
5568 11:53:52.879443
5569 11:53:52.882429 [CBTSetCACLKResult] CA Dly = 33
5570 11:53:52.882645 CS Dly: 7 (0~38)
5571 11:53:52.885891 ==
5572 11:53:52.886128 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 11:53:52.892932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 11:53:52.893157 ==
5575 11:53:52.895974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 11:53:52.902520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5577 11:53:52.905970 [CA 0] Center 36 (6~67) winsize 62
5578 11:53:52.909532 [CA 1] Center 37 (6~68) winsize 63
5579 11:53:52.912619 [CA 2] Center 35 (4~66) winsize 63
5580 11:53:52.916186 [CA 3] Center 34 (4~65) winsize 62
5581 11:53:52.919323 [CA 4] Center 34 (4~65) winsize 62
5582 11:53:52.922699 [CA 5] Center 34 (4~64) winsize 61
5583 11:53:52.922922
5584 11:53:52.926052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5585 11:53:52.926276
5586 11:53:52.929198 [CATrainingPosCal] consider 2 rank data
5587 11:53:52.932870 u2DelayCellTimex100 = 270/100 ps
5588 11:53:52.936104 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5589 11:53:52.939418 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5590 11:53:52.946395 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5591 11:53:52.949728 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5592 11:53:52.952876 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5593 11:53:52.956157 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5594 11:53:52.956368
5595 11:53:52.959501 CA PerBit enable=1, Macro0, CA PI delay=34
5596 11:53:52.959712
5597 11:53:52.962862 [CBTSetCACLKResult] CA Dly = 34
5598 11:53:52.963074 CS Dly: 8 (0~40)
5599 11:53:52.963240
5600 11:53:52.966092 ----->DramcWriteLeveling(PI) begin...
5601 11:53:52.969846 ==
5602 11:53:52.970059 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 11:53:52.975756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 11:53:52.975969 ==
5605 11:53:52.979701 Write leveling (Byte 0): 25 => 25
5606 11:53:52.982968 Write leveling (Byte 1): 26 => 26
5607 11:53:52.986182 DramcWriteLeveling(PI) end<-----
5608 11:53:52.986416
5609 11:53:52.986682 ==
5610 11:53:52.989407 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 11:53:52.992754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 11:53:52.992988 ==
5613 11:53:52.995902 [Gating] SW mode calibration
5614 11:53:53.002862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 11:53:53.006009 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 11:53:53.012965 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 11:53:53.015827 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 11:53:53.019102 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 11:53:53.026106 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 11:53:53.029309 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 11:53:53.032484 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5622 11:53:53.039444 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
5623 11:53:53.042252 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
5624 11:53:53.045895 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 11:53:53.052304 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 11:53:53.055810 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 11:53:53.059151 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 11:53:53.066028 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 11:53:53.068980 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 11:53:53.072157 0 15 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5631 11:53:53.079029 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5632 11:53:53.082012 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 11:53:53.085951 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 11:53:53.092256 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 11:53:53.095513 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 11:53:53.099130 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 11:53:53.105804 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:53:53.108954 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5639 11:53:53.112446 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:53:53.119255 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:53:53.122734 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:53:53.125940 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:53:53.129384 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:53:53.135566 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:53:53.138918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:53:53.142092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:53:53.148741 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:53:53.152159 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:53:53.155481 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:53:53.162614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:53:53.165570 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:53:53.168927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:53:53.175300 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:53:53.178810 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5655 11:53:53.181922 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 11:53:53.185396 Total UI for P1: 0, mck2ui 16
5657 11:53:53.189318 best dqsien dly found for B0: ( 1, 2, 24)
5658 11:53:53.192035 Total UI for P1: 0, mck2ui 16
5659 11:53:53.195683 best dqsien dly found for B1: ( 1, 2, 24)
5660 11:53:53.198881 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5661 11:53:53.201804 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5662 11:53:53.201884
5663 11:53:53.208460 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 11:53:53.211864 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5665 11:53:53.211974 [Gating] SW calibration Done
5666 11:53:53.215139 ==
5667 11:53:53.218715 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 11:53:53.221997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 11:53:53.222081 ==
5670 11:53:53.222147 RX Vref Scan: 0
5671 11:53:53.222248
5672 11:53:53.225076 RX Vref 0 -> 0, step: 1
5673 11:53:53.225187
5674 11:53:53.228242 RX Delay -80 -> 252, step: 8
5675 11:53:53.232112 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5676 11:53:53.235393 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5677 11:53:53.238504 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5678 11:53:53.244998 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5679 11:53:53.248491 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5680 11:53:53.251701 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5681 11:53:53.254993 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5682 11:53:53.258333 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5683 11:53:53.261508 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5684 11:53:53.268253 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5685 11:53:53.271496 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5686 11:53:53.275176 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5687 11:53:53.278306 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5688 11:53:53.281868 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5689 11:53:53.288396 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5690 11:53:53.291896 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5691 11:53:53.292007 ==
5692 11:53:53.294723 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 11:53:53.298302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 11:53:53.298415 ==
5695 11:53:53.298523 DQS Delay:
5696 11:53:53.301800 DQS0 = 0, DQS1 = 0
5697 11:53:53.301885 DQM Delay:
5698 11:53:53.304559 DQM0 = 102, DQM1 = 98
5699 11:53:53.304665 DQ Delay:
5700 11:53:53.308580 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5701 11:53:53.311704 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5702 11:53:53.314764 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5703 11:53:53.318201 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5704 11:53:53.318283
5705 11:53:53.318348
5706 11:53:53.318412 ==
5707 11:53:53.321946 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 11:53:53.328000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 11:53:53.328085 ==
5710 11:53:53.328150
5711 11:53:53.328212
5712 11:53:53.328295 TX Vref Scan disable
5713 11:53:53.331788 == TX Byte 0 ==
5714 11:53:53.335571 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5715 11:53:53.339116 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5716 11:53:53.341929 == TX Byte 1 ==
5717 11:53:53.345071 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5718 11:53:53.351755 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5719 11:53:53.351843 ==
5720 11:53:53.355152 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:53:53.358617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:53:53.358701 ==
5723 11:53:53.358766
5724 11:53:53.358829
5725 11:53:53.361933 TX Vref Scan disable
5726 11:53:53.362015 == TX Byte 0 ==
5727 11:53:53.368550 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5728 11:53:53.371730 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5729 11:53:53.371849 == TX Byte 1 ==
5730 11:53:53.378657 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5731 11:53:53.381943 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5732 11:53:53.382032
5733 11:53:53.382102 [DATLAT]
5734 11:53:53.384852 Freq=933, CH1 RK0
5735 11:53:53.384959
5736 11:53:53.385034 DATLAT Default: 0xd
5737 11:53:53.388768 0, 0xFFFF, sum = 0
5738 11:53:53.388867 1, 0xFFFF, sum = 0
5739 11:53:53.391804 2, 0xFFFF, sum = 0
5740 11:53:53.391909 3, 0xFFFF, sum = 0
5741 11:53:53.395261 4, 0xFFFF, sum = 0
5742 11:53:53.395344 5, 0xFFFF, sum = 0
5743 11:53:53.398439 6, 0xFFFF, sum = 0
5744 11:53:53.401750 7, 0xFFFF, sum = 0
5745 11:53:53.401883 8, 0xFFFF, sum = 0
5746 11:53:53.404968 9, 0xFFFF, sum = 0
5747 11:53:53.405094 10, 0x0, sum = 1
5748 11:53:53.405205 11, 0x0, sum = 2
5749 11:53:53.408333 12, 0x0, sum = 3
5750 11:53:53.408466 13, 0x0, sum = 4
5751 11:53:53.411546 best_step = 11
5752 11:53:53.411632
5753 11:53:53.411696 ==
5754 11:53:53.414590 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 11:53:53.418078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 11:53:53.418187 ==
5757 11:53:53.421390 RX Vref Scan: 1
5758 11:53:53.421475
5759 11:53:53.421540 RX Vref 0 -> 0, step: 1
5760 11:53:53.425244
5761 11:53:53.425324 RX Delay -45 -> 252, step: 4
5762 11:53:53.425388
5763 11:53:53.428327 Set Vref, RX VrefLevel [Byte0]: 54
5764 11:53:53.431874 [Byte1]: 52
5765 11:53:53.436044
5766 11:53:53.436132 Final RX Vref Byte 0 = 54 to rank0
5767 11:53:53.438972 Final RX Vref Byte 1 = 52 to rank0
5768 11:53:53.442535 Final RX Vref Byte 0 = 54 to rank1
5769 11:53:53.445731 Final RX Vref Byte 1 = 52 to rank1==
5770 11:53:53.449298 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 11:53:53.455681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:53:53.455832 ==
5773 11:53:53.456007 DQS Delay:
5774 11:53:53.456142 DQS0 = 0, DQS1 = 0
5775 11:53:53.458795 DQM Delay:
5776 11:53:53.458917 DQM0 = 103, DQM1 = 99
5777 11:53:53.462532 DQ Delay:
5778 11:53:53.465897 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5779 11:53:53.469080 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5780 11:53:53.472533 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5781 11:53:53.476158 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
5782 11:53:53.476360
5783 11:53:53.476518
5784 11:53:53.482557 [DQSOSCAuto] RK0, (LSB)MR18= 0x142b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5785 11:53:53.485798 CH1 RK0: MR19=505, MR18=142B
5786 11:53:53.492286 CH1_RK0: MR19=0x505, MR18=0x142B, DQSOSC=408, MR23=63, INC=65, DEC=43
5787 11:53:53.492527
5788 11:53:53.495581 ----->DramcWriteLeveling(PI) begin...
5789 11:53:53.495823 ==
5790 11:53:53.499685 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 11:53:53.502266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 11:53:53.502506 ==
5793 11:53:53.505561 Write leveling (Byte 0): 24 => 24
5794 11:53:53.509606 Write leveling (Byte 1): 25 => 25
5795 11:53:53.512255 DramcWriteLeveling(PI) end<-----
5796 11:53:53.512576
5797 11:53:53.512817 ==
5798 11:53:53.515550 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 11:53:53.522482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:53:53.522906 ==
5801 11:53:53.523252 [Gating] SW mode calibration
5802 11:53:53.532899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 11:53:53.536072 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 11:53:53.539298 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 11:53:53.545908 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 11:53:53.549223 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 11:53:53.552641 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 11:53:53.559524 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 11:53:53.562499 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 11:53:53.565741 0 14 24 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
5811 11:53:53.572645 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
5812 11:53:53.575816 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 11:53:53.578871 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 11:53:53.585398 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 11:53:53.588855 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 11:53:53.592196 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 11:53:53.599274 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 11:53:53.602935 0 15 24 | B1->B0 | 3636 2c2c | 0 1 | (1 1) (1 1)
5819 11:53:53.605607 0 15 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5820 11:53:53.612091 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 11:53:53.615841 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 11:53:53.618963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 11:53:53.625969 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 11:53:53.628609 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:53:53.631887 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 11:53:53.635137 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 11:53:53.641851 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5828 11:53:53.645633 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 11:53:53.649165 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 11:53:53.655611 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 11:53:53.658861 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:53:53.661730 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:53:53.668370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:53:53.671762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:53:53.675598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:53:53.682040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:53:53.685356 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:53:53.688513 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:53:53.695107 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:53:53.699113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:53:53.702245 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:53:53.708606 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5843 11:53:53.712127 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 11:53:53.715455 Total UI for P1: 0, mck2ui 16
5845 11:53:53.718611 best dqsien dly found for B0: ( 1, 2, 26)
5846 11:53:53.722462 Total UI for P1: 0, mck2ui 16
5847 11:53:53.725373 best dqsien dly found for B1: ( 1, 2, 24)
5848 11:53:53.728972 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5849 11:53:53.732068 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5850 11:53:53.732676
5851 11:53:53.735433 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5852 11:53:53.738596 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 11:53:53.741758 [Gating] SW calibration Done
5854 11:53:53.742331 ==
5855 11:53:53.745186 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 11:53:53.748849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 11:53:53.749476 ==
5858 11:53:53.751734 RX Vref Scan: 0
5859 11:53:53.752181
5860 11:53:53.755196 RX Vref 0 -> 0, step: 1
5861 11:53:53.755640
5862 11:53:53.756082 RX Delay -80 -> 252, step: 8
5863 11:53:53.761974 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5864 11:53:53.765273 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5865 11:53:53.768997 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5866 11:53:53.771929 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5867 11:53:53.775492 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5868 11:53:53.778695 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5869 11:53:53.785023 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5870 11:53:53.788569 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5871 11:53:53.792069 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5872 11:53:53.796067 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5873 11:53:53.798298 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5874 11:53:53.801949 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5875 11:53:53.808361 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5876 11:53:53.811566 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5877 11:53:53.814953 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5878 11:53:53.818627 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5879 11:53:53.818875 ==
5880 11:53:53.821535 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 11:53:53.828513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 11:53:53.828744 ==
5883 11:53:53.828924 DQS Delay:
5884 11:53:53.829092 DQS0 = 0, DQS1 = 0
5885 11:53:53.831627 DQM Delay:
5886 11:53:53.831853 DQM0 = 103, DQM1 = 98
5887 11:53:53.835593 DQ Delay:
5888 11:53:53.838403 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5889 11:53:53.841617 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5890 11:53:53.845147 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5891 11:53:53.848156 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5892 11:53:53.848424
5893 11:53:53.848608
5894 11:53:53.848776 ==
5895 11:53:53.851881 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 11:53:53.855133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 11:53:53.855371 ==
5898 11:53:53.855592
5899 11:53:53.855762
5900 11:53:53.858593 TX Vref Scan disable
5901 11:53:53.858841 == TX Byte 0 ==
5902 11:53:53.865048 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5903 11:53:53.870963 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5904 11:53:53.871255 == TX Byte 1 ==
5905 11:53:53.875059 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5906 11:53:53.878243 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5907 11:53:53.878522 ==
5908 11:53:53.881468 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 11:53:53.885295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 11:53:53.885597 ==
5911 11:53:53.885839
5912 11:53:53.888521
5913 11:53:53.888796 TX Vref Scan disable
5914 11:53:53.891765 == TX Byte 0 ==
5915 11:53:53.895002 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5916 11:53:53.898555 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5917 11:53:53.901563 == TX Byte 1 ==
5918 11:53:53.905124 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5919 11:53:53.908458 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5920 11:53:53.911905
5921 11:53:53.912187 [DATLAT]
5922 11:53:53.912408 Freq=933, CH1 RK1
5923 11:53:53.912615
5924 11:53:53.915068 DATLAT Default: 0xb
5925 11:53:53.915351 0, 0xFFFF, sum = 0
5926 11:53:53.918183 1, 0xFFFF, sum = 0
5927 11:53:53.918465 2, 0xFFFF, sum = 0
5928 11:53:53.921941 3, 0xFFFF, sum = 0
5929 11:53:53.922222 4, 0xFFFF, sum = 0
5930 11:53:53.925090 5, 0xFFFF, sum = 0
5931 11:53:53.928468 6, 0xFFFF, sum = 0
5932 11:53:53.928751 7, 0xFFFF, sum = 0
5933 11:53:53.932180 8, 0xFFFF, sum = 0
5934 11:53:53.932687 9, 0xFFFF, sum = 0
5935 11:53:53.934828 10, 0x0, sum = 1
5936 11:53:53.935194 11, 0x0, sum = 2
5937 11:53:53.935487 12, 0x0, sum = 3
5938 11:53:53.938592 13, 0x0, sum = 4
5939 11:53:53.939021 best_step = 11
5940 11:53:53.939355
5941 11:53:53.941858 ==
5942 11:53:53.942297 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 11:53:53.948376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 11:53:53.948805 ==
5945 11:53:53.949137 RX Vref Scan: 0
5946 11:53:53.949449
5947 11:53:53.951825 RX Vref 0 -> 0, step: 1
5948 11:53:53.952250
5949 11:53:53.954797 RX Delay -45 -> 252, step: 4
5950 11:53:53.958005 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5951 11:53:53.964594 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5952 11:53:53.968385 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5953 11:53:53.971689 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5954 11:53:53.974637 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5955 11:53:53.978114 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5956 11:53:53.984540 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5957 11:53:53.987870 iDelay=203, Bit 7, Center 100 (15 ~ 186) 172
5958 11:53:53.991567 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5959 11:53:53.994990 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5960 11:53:53.998218 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5961 11:53:54.001404 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5962 11:53:54.007999 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5963 11:53:54.011383 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5964 11:53:54.014774 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5965 11:53:54.017997 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5966 11:53:54.018429 ==
5967 11:53:54.021132 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 11:53:54.027755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 11:53:54.028290 ==
5970 11:53:54.028850 DQS Delay:
5971 11:53:54.031366 DQS0 = 0, DQS1 = 0
5972 11:53:54.031788 DQM Delay:
5973 11:53:54.032122 DQM0 = 104, DQM1 = 100
5974 11:53:54.034550 DQ Delay:
5975 11:53:54.038141 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5976 11:53:54.041671 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =100
5977 11:53:54.044703 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =94
5978 11:53:54.048155 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5979 11:53:54.048590
5980 11:53:54.049018
5981 11:53:54.054412 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5982 11:53:54.057728 CH1 RK1: MR19=505, MR18=3003
5983 11:53:54.064441 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5984 11:53:54.068351 [RxdqsGatingPostProcess] freq 933
5985 11:53:54.074535 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 11:53:54.077862 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 11:53:54.078383 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 11:53:54.080980 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 11:53:54.084641 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 11:53:54.087871 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 11:53:54.091091 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 11:53:54.094233 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 11:53:54.098413 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 11:53:54.101357 Pre-setting of DQS Precalculation
5995 11:53:54.107966 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 11:53:54.114232 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 11:53:54.121003 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 11:53:54.121423
5999 11:53:54.121900
6000 11:53:54.124495 [Calibration Summary] 1866 Mbps
6001 11:53:54.124958 CH 0, Rank 0
6002 11:53:54.127456 SW Impedance : PASS
6003 11:53:54.131076 DUTY Scan : NO K
6004 11:53:54.131372 ZQ Calibration : PASS
6005 11:53:54.134638 Jitter Meter : NO K
6006 11:53:54.137229 CBT Training : PASS
6007 11:53:54.137450 Write leveling : PASS
6008 11:53:54.140781 RX DQS gating : PASS
6009 11:53:54.144035 RX DQ/DQS(RDDQC) : PASS
6010 11:53:54.144214 TX DQ/DQS : PASS
6011 11:53:54.147132 RX DATLAT : PASS
6012 11:53:54.147310 RX DQ/DQS(Engine): PASS
6013 11:53:54.150397 TX OE : NO K
6014 11:53:54.150548 All Pass.
6015 11:53:54.150664
6016 11:53:54.153597 CH 0, Rank 1
6017 11:53:54.153680 SW Impedance : PASS
6018 11:53:54.157069 DUTY Scan : NO K
6019 11:53:54.160760 ZQ Calibration : PASS
6020 11:53:54.160863 Jitter Meter : NO K
6021 11:53:54.163817 CBT Training : PASS
6022 11:53:54.167294 Write leveling : PASS
6023 11:53:54.167380 RX DQS gating : PASS
6024 11:53:54.170557 RX DQ/DQS(RDDQC) : PASS
6025 11:53:54.173838 TX DQ/DQS : PASS
6026 11:53:54.173921 RX DATLAT : PASS
6027 11:53:54.177088 RX DQ/DQS(Engine): PASS
6028 11:53:54.180650 TX OE : NO K
6029 11:53:54.180738 All Pass.
6030 11:53:54.180803
6031 11:53:54.180862 CH 1, Rank 0
6032 11:53:54.184032 SW Impedance : PASS
6033 11:53:54.186686 DUTY Scan : NO K
6034 11:53:54.186767 ZQ Calibration : PASS
6035 11:53:54.190776 Jitter Meter : NO K
6036 11:53:54.193494 CBT Training : PASS
6037 11:53:54.193631 Write leveling : PASS
6038 11:53:54.196673 RX DQS gating : PASS
6039 11:53:54.200840 RX DQ/DQS(RDDQC) : PASS
6040 11:53:54.200918 TX DQ/DQS : PASS
6041 11:53:54.203279 RX DATLAT : PASS
6042 11:53:54.203354 RX DQ/DQS(Engine): PASS
6043 11:53:54.207408 TX OE : NO K
6044 11:53:54.207519 All Pass.
6045 11:53:54.207624
6046 11:53:54.210870 CH 1, Rank 1
6047 11:53:54.211001 SW Impedance : PASS
6048 11:53:54.214018 DUTY Scan : NO K
6049 11:53:54.217129 ZQ Calibration : PASS
6050 11:53:54.217229 Jitter Meter : NO K
6051 11:53:54.220191 CBT Training : PASS
6052 11:53:54.223740 Write leveling : PASS
6053 11:53:54.223842 RX DQS gating : PASS
6054 11:53:54.227316 RX DQ/DQS(RDDQC) : PASS
6055 11:53:54.230061 TX DQ/DQS : PASS
6056 11:53:54.230183 RX DATLAT : PASS
6057 11:53:54.233963 RX DQ/DQS(Engine): PASS
6058 11:53:54.237281 TX OE : NO K
6059 11:53:54.237402 All Pass.
6060 11:53:54.237496
6061 11:53:54.237594 DramC Write-DBI off
6062 11:53:54.240718 PER_BANK_REFRESH: Hybrid Mode
6063 11:53:54.243674 TX_TRACKING: ON
6064 11:53:54.249728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 11:53:54.253609 [FAST_K] Save calibration result to emmc
6066 11:53:54.259887 dramc_set_vcore_voltage set vcore to 650000
6067 11:53:54.260063 Read voltage for 400, 6
6068 11:53:54.263060 Vio18 = 0
6069 11:53:54.263221 Vcore = 650000
6070 11:53:54.263368 Vdram = 0
6071 11:53:54.266587 Vddq = 0
6072 11:53:54.266742 Vmddr = 0
6073 11:53:54.269791 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 11:53:54.276328 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 11:53:54.279742 MEM_TYPE=3, freq_sel=20
6076 11:53:54.282945 sv_algorithm_assistance_LP4_800
6077 11:53:54.286253 ============ PULL DRAM RESETB DOWN ============
6078 11:53:54.289539 ========== PULL DRAM RESETB DOWN end =========
6079 11:53:54.293451 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 11:53:54.296167 ===================================
6081 11:53:54.300141 LPDDR4 DRAM CONFIGURATION
6082 11:53:54.302886 ===================================
6083 11:53:54.306353 EX_ROW_EN[0] = 0x0
6084 11:53:54.306475 EX_ROW_EN[1] = 0x0
6085 11:53:54.309597 LP4Y_EN = 0x0
6086 11:53:54.309721 WORK_FSP = 0x0
6087 11:53:54.312935 WL = 0x2
6088 11:53:54.313057 RL = 0x2
6089 11:53:54.316318 BL = 0x2
6090 11:53:54.316442 RPST = 0x0
6091 11:53:54.319638 RD_PRE = 0x0
6092 11:53:54.319752 WR_PRE = 0x1
6093 11:53:54.323013 WR_PST = 0x0
6094 11:53:54.323174 DBI_WR = 0x0
6095 11:53:54.326532 DBI_RD = 0x0
6096 11:53:54.329605 OTF = 0x1
6097 11:53:54.329727 ===================================
6098 11:53:54.333552 ===================================
6099 11:53:54.336463 ANA top config
6100 11:53:54.339535 ===================================
6101 11:53:54.343324 DLL_ASYNC_EN = 0
6102 11:53:54.343447 ALL_SLAVE_EN = 1
6103 11:53:54.346372 NEW_RANK_MODE = 1
6104 11:53:54.349483 DLL_IDLE_MODE = 1
6105 11:53:54.353275 LP45_APHY_COMB_EN = 1
6106 11:53:54.356023 TX_ODT_DIS = 1
6107 11:53:54.356162 NEW_8X_MODE = 1
6108 11:53:54.359306 ===================================
6109 11:53:54.362729 ===================================
6110 11:53:54.365811 data_rate = 800
6111 11:53:54.369516 CKR = 1
6112 11:53:54.372909 DQ_P2S_RATIO = 4
6113 11:53:54.375813 ===================================
6114 11:53:54.379573 CA_P2S_RATIO = 4
6115 11:53:54.382916 DQ_CA_OPEN = 0
6116 11:53:54.383033 DQ_SEMI_OPEN = 1
6117 11:53:54.385833 CA_SEMI_OPEN = 1
6118 11:53:54.389407 CA_FULL_RATE = 0
6119 11:53:54.392703 DQ_CKDIV4_EN = 0
6120 11:53:54.396492 CA_CKDIV4_EN = 1
6121 11:53:54.399412 CA_PREDIV_EN = 0
6122 11:53:54.399497 PH8_DLY = 0
6123 11:53:54.402842 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 11:53:54.406058 DQ_AAMCK_DIV = 0
6125 11:53:54.409720 CA_AAMCK_DIV = 0
6126 11:53:54.412275 CA_ADMCK_DIV = 4
6127 11:53:54.415932 DQ_TRACK_CA_EN = 0
6128 11:53:54.416017 CA_PICK = 800
6129 11:53:54.419107 CA_MCKIO = 400
6130 11:53:54.422428 MCKIO_SEMI = 400
6131 11:53:54.425672 PLL_FREQ = 3016
6132 11:53:54.429063 DQ_UI_PI_RATIO = 32
6133 11:53:54.432365 CA_UI_PI_RATIO = 32
6134 11:53:54.435739 ===================================
6135 11:53:54.438982 ===================================
6136 11:53:54.442309 memory_type:LPDDR4
6137 11:53:54.442407 GP_NUM : 10
6138 11:53:54.445217 SRAM_EN : 1
6139 11:53:54.445318 MD32_EN : 0
6140 11:53:54.448492 ===================================
6141 11:53:54.451876 [ANA_INIT] >>>>>>>>>>>>>>
6142 11:53:54.455309 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 11:53:54.458474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 11:53:54.461929 ===================================
6145 11:53:54.465254 data_rate = 800,PCW = 0X7400
6146 11:53:54.468654 ===================================
6147 11:53:54.472027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 11:53:54.478850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 11:53:54.488551 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 11:53:54.492172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 11:53:54.495357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 11:53:54.498501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 11:53:54.502218 [ANA_INIT] flow start
6154 11:53:54.505446 [ANA_INIT] PLL >>>>>>>>
6155 11:53:54.505662 [ANA_INIT] PLL <<<<<<<<
6156 11:53:54.508650 [ANA_INIT] MIDPI >>>>>>>>
6157 11:53:54.511943 [ANA_INIT] MIDPI <<<<<<<<
6158 11:53:54.515513 [ANA_INIT] DLL >>>>>>>>
6159 11:53:54.515721 [ANA_INIT] flow end
6160 11:53:54.518721 ============ LP4 DIFF to SE enter ============
6161 11:53:54.525152 ============ LP4 DIFF to SE exit ============
6162 11:53:54.525350 [ANA_INIT] <<<<<<<<<<<<<
6163 11:53:54.528425 [Flow] Enable top DCM control >>>>>
6164 11:53:54.531776 [Flow] Enable top DCM control <<<<<
6165 11:53:54.535030 Enable DLL master slave shuffle
6166 11:53:54.541772 ==============================================================
6167 11:53:54.541907 Gating Mode config
6168 11:53:54.548333 ==============================================================
6169 11:53:54.551548 Config description:
6170 11:53:54.558674 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 11:53:54.565301 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 11:53:54.571338 SELPH_MODE 0: By rank 1: By Phase
6173 11:53:54.578463 ==============================================================
6174 11:53:54.578551 GAT_TRACK_EN = 0
6175 11:53:54.581724 RX_GATING_MODE = 2
6176 11:53:54.584942 RX_GATING_TRACK_MODE = 2
6177 11:53:54.588384 SELPH_MODE = 1
6178 11:53:54.591923 PICG_EARLY_EN = 1
6179 11:53:54.595007 VALID_LAT_VALUE = 1
6180 11:53:54.601473 ==============================================================
6181 11:53:54.605171 Enter into Gating configuration >>>>
6182 11:53:54.608581 Exit from Gating configuration <<<<
6183 11:53:54.612041 Enter into DVFS_PRE_config >>>>>
6184 11:53:54.621780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 11:53:54.625450 Exit from DVFS_PRE_config <<<<<
6186 11:53:54.628427 Enter into PICG configuration >>>>
6187 11:53:54.631751 Exit from PICG configuration <<<<
6188 11:53:54.635094 [RX_INPUT] configuration >>>>>
6189 11:53:54.635220 [RX_INPUT] configuration <<<<<
6190 11:53:54.641906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 11:53:54.648327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 11:53:54.651709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 11:53:54.658349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 11:53:54.664941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 11:53:54.672036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 11:53:54.674922 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 11:53:54.678512 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 11:53:54.684743 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 11:53:54.688515 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 11:53:54.692065 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 11:53:54.698654 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 11:53:54.702014 ===================================
6203 11:53:54.702344 LPDDR4 DRAM CONFIGURATION
6204 11:53:54.705556 ===================================
6205 11:53:54.708448 EX_ROW_EN[0] = 0x0
6206 11:53:54.708792 EX_ROW_EN[1] = 0x0
6207 11:53:54.711579 LP4Y_EN = 0x0
6208 11:53:54.712027 WORK_FSP = 0x0
6209 11:53:54.714873 WL = 0x2
6210 11:53:54.717978 RL = 0x2
6211 11:53:54.718297 BL = 0x2
6212 11:53:54.721638 RPST = 0x0
6213 11:53:54.722079 RD_PRE = 0x0
6214 11:53:54.724768 WR_PRE = 0x1
6215 11:53:54.725086 WR_PST = 0x0
6216 11:53:54.728648 DBI_WR = 0x0
6217 11:53:54.729092 DBI_RD = 0x0
6218 11:53:54.731609 OTF = 0x1
6219 11:53:54.735246 ===================================
6220 11:53:54.738318 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 11:53:54.742027 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 11:53:54.745014 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 11:53:54.748340 ===================================
6224 11:53:54.751955 LPDDR4 DRAM CONFIGURATION
6225 11:53:54.754954 ===================================
6226 11:53:54.758493 EX_ROW_EN[0] = 0x10
6227 11:53:54.758970 EX_ROW_EN[1] = 0x0
6228 11:53:54.761433 LP4Y_EN = 0x0
6229 11:53:54.761900 WORK_FSP = 0x0
6230 11:53:54.764742 WL = 0x2
6231 11:53:54.765128 RL = 0x2
6232 11:53:54.768177 BL = 0x2
6233 11:53:54.768504 RPST = 0x0
6234 11:53:54.771337 RD_PRE = 0x0
6235 11:53:54.771757 WR_PRE = 0x1
6236 11:53:54.774609 WR_PST = 0x0
6237 11:53:54.774938 DBI_WR = 0x0
6238 11:53:54.778093 DBI_RD = 0x0
6239 11:53:54.781914 OTF = 0x1
6240 11:53:54.784871 ===================================
6241 11:53:54.788389 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 11:53:54.793570 nWR fixed to 30
6243 11:53:54.796919 [ModeRegInit_LP4] CH0 RK0
6244 11:53:54.797339 [ModeRegInit_LP4] CH0 RK1
6245 11:53:54.799842 [ModeRegInit_LP4] CH1 RK0
6246 11:53:54.803200 [ModeRegInit_LP4] CH1 RK1
6247 11:53:54.803525 match AC timing 19
6248 11:53:54.809607 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 11:53:54.812882 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 11:53:54.816533 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 11:53:54.823010 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 11:53:54.826364 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 11:53:54.826693 ==
6254 11:53:54.829641 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:53:54.832925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:53:54.833256 ==
6257 11:53:54.839914 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 11:53:54.846465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 11:53:54.850123 [CA 0] Center 36 (8~64) winsize 57
6260 11:53:54.853201 [CA 1] Center 36 (8~64) winsize 57
6261 11:53:54.856318 [CA 2] Center 36 (8~64) winsize 57
6262 11:53:54.856728 [CA 3] Center 36 (8~64) winsize 57
6263 11:53:54.860122 [CA 4] Center 36 (8~64) winsize 57
6264 11:53:54.862850 [CA 5] Center 36 (8~64) winsize 57
6265 11:53:54.863149
6266 11:53:54.869461 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 11:53:54.869743
6268 11:53:54.873184 [CATrainingPosCal] consider 1 rank data
6269 11:53:54.876309 u2DelayCellTimex100 = 270/100 ps
6270 11:53:54.879455 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:53:54.882554 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:53:54.885943 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:53:54.889827 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:53:54.892811 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:53:54.896492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:53:54.896828
6277 11:53:54.899740 CA PerBit enable=1, Macro0, CA PI delay=36
6278 11:53:54.899986
6279 11:53:54.902730 [CBTSetCACLKResult] CA Dly = 36
6280 11:53:54.906007 CS Dly: 1 (0~32)
6281 11:53:54.906244 ==
6282 11:53:54.909862 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 11:53:54.912441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 11:53:54.912690 ==
6285 11:53:54.919057 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 11:53:54.922337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 11:53:54.926213 [CA 0] Center 36 (8~64) winsize 57
6288 11:53:54.929367 [CA 1] Center 36 (8~64) winsize 57
6289 11:53:54.932615 [CA 2] Center 36 (8~64) winsize 57
6290 11:53:54.936182 [CA 3] Center 36 (8~64) winsize 57
6291 11:53:54.939000 [CA 4] Center 36 (8~64) winsize 57
6292 11:53:54.942743 [CA 5] Center 36 (8~64) winsize 57
6293 11:53:54.942987
6294 11:53:54.945808 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 11:53:54.945964
6296 11:53:54.948966 [CATrainingPosCal] consider 2 rank data
6297 11:53:54.952220 u2DelayCellTimex100 = 270/100 ps
6298 11:53:54.955516 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:53:54.958996 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:53:54.965680 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:53:54.968727 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:53:54.972105 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:53:54.975692 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:53:54.976032
6305 11:53:54.978916 CA PerBit enable=1, Macro0, CA PI delay=36
6306 11:53:54.979267
6307 11:53:54.982088 [CBTSetCACLKResult] CA Dly = 36
6308 11:53:54.982393 CS Dly: 1 (0~32)
6309 11:53:54.982613
6310 11:53:54.985498 ----->DramcWriteLeveling(PI) begin...
6311 11:53:54.988931 ==
6312 11:53:54.989307 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 11:53:54.995788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 11:53:54.996211 ==
6315 11:53:54.998846 Write leveling (Byte 0): 40 => 8
6316 11:53:55.002600 Write leveling (Byte 1): 40 => 8
6317 11:53:55.002863 DramcWriteLeveling(PI) end<-----
6318 11:53:55.006233
6319 11:53:55.006433 ==
6320 11:53:55.008971 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 11:53:55.012175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 11:53:55.012405 ==
6323 11:53:55.015781 [Gating] SW mode calibration
6324 11:53:55.022239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 11:53:55.025509 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 11:53:55.031854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 11:53:55.035179 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 11:53:55.039030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 11:53:55.045290 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 11:53:55.048357 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 11:53:55.051867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 11:53:55.058227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 11:53:55.061933 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 11:53:55.065154 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 11:53:55.068465 Total UI for P1: 0, mck2ui 16
6336 11:53:55.071758 best dqsien dly found for B0: ( 0, 14, 24)
6337 11:53:55.075648 Total UI for P1: 0, mck2ui 16
6338 11:53:55.078884 best dqsien dly found for B1: ( 0, 14, 24)
6339 11:53:55.081968 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 11:53:55.085292 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 11:53:55.085420
6342 11:53:55.091503 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 11:53:55.094790 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 11:53:55.098556 [Gating] SW calibration Done
6345 11:53:55.098647 ==
6346 11:53:55.101416 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 11:53:55.104870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 11:53:55.104995 ==
6349 11:53:55.105104 RX Vref Scan: 0
6350 11:53:55.105210
6351 11:53:55.108011 RX Vref 0 -> 0, step: 1
6352 11:53:55.108129
6353 11:53:55.111688 RX Delay -410 -> 252, step: 16
6354 11:53:55.114874 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6355 11:53:55.121754 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6356 11:53:55.124648 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6357 11:53:55.128302 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6358 11:53:55.131665 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6359 11:53:55.137864 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6360 11:53:55.141318 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6361 11:53:55.145227 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6362 11:53:55.148357 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6363 11:53:55.151677 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6364 11:53:55.158405 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6365 11:53:55.161608 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6366 11:53:55.164671 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6367 11:53:55.171654 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6368 11:53:55.174705 iDelay=230, Bit 14, Center -3 (-234 ~ 229) 464
6369 11:53:55.178023 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6370 11:53:55.178107 ==
6371 11:53:55.181354 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 11:53:55.185014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 11:53:55.185105 ==
6374 11:53:55.187930 DQS Delay:
6375 11:53:55.188019 DQS0 = 27, DQS1 = 35
6376 11:53:55.191151 DQM Delay:
6377 11:53:55.191250 DQM0 = 11, DQM1 = 13
6378 11:53:55.195048 DQ Delay:
6379 11:53:55.195143 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6380 11:53:55.198140 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6381 11:53:55.201294 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6382 11:53:55.204737 DQ12 =16, DQ13 =16, DQ14 =32, DQ15 =16
6383 11:53:55.204863
6384 11:53:55.204961
6385 11:53:55.205051 ==
6386 11:53:55.208119 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 11:53:55.215076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 11:53:55.215244 ==
6389 11:53:55.215438
6390 11:53:55.215621
6391 11:53:55.215790 TX Vref Scan disable
6392 11:53:55.217938 == TX Byte 0 ==
6393 11:53:55.221187 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 11:53:55.224892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 11:53:55.227941 == TX Byte 1 ==
6396 11:53:55.231690 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 11:53:55.234890 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 11:53:55.237973 ==
6399 11:53:55.238301 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 11:53:55.244606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 11:53:55.244939 ==
6402 11:53:55.245199
6403 11:53:55.245440
6404 11:53:55.248413 TX Vref Scan disable
6405 11:53:55.248743 == TX Byte 0 ==
6406 11:53:55.251329 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 11:53:55.254740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 11:53:55.258068 == TX Byte 1 ==
6409 11:53:55.261127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 11:53:55.264594 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 11:53:55.264931
6412 11:53:55.268491 [DATLAT]
6413 11:53:55.268818 Freq=400, CH0 RK0
6414 11:53:55.269222
6415 11:53:55.271579 DATLAT Default: 0xf
6416 11:53:55.271937 0, 0xFFFF, sum = 0
6417 11:53:55.274601 1, 0xFFFF, sum = 0
6418 11:53:55.275047 2, 0xFFFF, sum = 0
6419 11:53:55.278286 3, 0xFFFF, sum = 0
6420 11:53:55.278735 4, 0xFFFF, sum = 0
6421 11:53:55.281335 5, 0xFFFF, sum = 0
6422 11:53:55.281684 6, 0xFFFF, sum = 0
6423 11:53:55.285073 7, 0xFFFF, sum = 0
6424 11:53:55.288110 8, 0xFFFF, sum = 0
6425 11:53:55.288478 9, 0xFFFF, sum = 0
6426 11:53:55.291768 10, 0xFFFF, sum = 0
6427 11:53:55.292191 11, 0xFFFF, sum = 0
6428 11:53:55.294721 12, 0xFFFF, sum = 0
6429 11:53:55.295053 13, 0x0, sum = 1
6430 11:53:55.298396 14, 0x0, sum = 2
6431 11:53:55.298725 15, 0x0, sum = 3
6432 11:53:55.301340 16, 0x0, sum = 4
6433 11:53:55.301710 best_step = 14
6434 11:53:55.301975
6435 11:53:55.302216 ==
6436 11:53:55.304789 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 11:53:55.308309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 11:53:55.308650 ==
6439 11:53:55.311144 RX Vref Scan: 1
6440 11:53:55.311471
6441 11:53:55.314504 RX Vref 0 -> 0, step: 1
6442 11:53:55.314832
6443 11:53:55.315090 RX Delay -311 -> 252, step: 8
6444 11:53:55.315332
6445 11:53:55.317689 Set Vref, RX VrefLevel [Byte0]: 55
6446 11:53:55.321021 [Byte1]: 58
6447 11:53:55.327028
6448 11:53:55.327463 Final RX Vref Byte 0 = 55 to rank0
6449 11:53:55.329902 Final RX Vref Byte 1 = 58 to rank0
6450 11:53:55.332776 Final RX Vref Byte 0 = 55 to rank1
6451 11:53:55.336236 Final RX Vref Byte 1 = 58 to rank1==
6452 11:53:55.339580 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 11:53:55.346210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 11:53:55.346645 ==
6455 11:53:55.346916 DQS Delay:
6456 11:53:55.349442 DQS0 = 28, DQS1 = 32
6457 11:53:55.349967 DQM Delay:
6458 11:53:55.350364 DQM0 = 10, DQM1 = 8
6459 11:53:55.353208 DQ Delay:
6460 11:53:55.356283 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6461 11:53:55.356723 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6462 11:53:55.359643 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6463 11:53:55.362859 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =12
6464 11:53:55.363208
6465 11:53:55.363475
6466 11:53:55.372831 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6467 11:53:55.375916 CH0 RK0: MR19=C0C, MR18=CBB6
6468 11:53:55.383447 CH0_RK0: MR19=0xC0C, MR18=0xCBB6, DQSOSC=384, MR23=63, INC=400, DEC=267
6469 11:53:55.383799 ==
6470 11:53:55.386685 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 11:53:55.389710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 11:53:55.390046 ==
6473 11:53:55.393122 [Gating] SW mode calibration
6474 11:53:55.399656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 11:53:55.406077 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 11:53:55.409555 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 11:53:55.412578 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 11:53:55.419019 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 11:53:55.422355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 11:53:55.425480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 11:53:55.432425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 11:53:55.435543 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 11:53:55.438960 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 11:53:55.445667 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 11:53:55.445999 Total UI for P1: 0, mck2ui 16
6486 11:53:55.449231 best dqsien dly found for B0: ( 0, 14, 24)
6487 11:53:55.452276 Total UI for P1: 0, mck2ui 16
6488 11:53:55.455461 best dqsien dly found for B1: ( 0, 14, 24)
6489 11:53:55.461903 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 11:53:55.465165 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 11:53:55.465623
6492 11:53:55.468895 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 11:53:55.472129 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 11:53:55.475238 [Gating] SW calibration Done
6495 11:53:55.475579 ==
6496 11:53:55.478685 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 11:53:55.481866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 11:53:55.482215 ==
6499 11:53:55.485519 RX Vref Scan: 0
6500 11:53:55.485986
6501 11:53:55.486354 RX Vref 0 -> 0, step: 1
6502 11:53:55.486657
6503 11:53:55.488835 RX Delay -410 -> 252, step: 16
6504 11:53:55.495296 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6505 11:53:55.498475 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6506 11:53:55.502325 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6507 11:53:55.505459 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6508 11:53:55.508706 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6509 11:53:55.515259 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6510 11:53:55.518677 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6511 11:53:55.521784 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6512 11:53:55.525470 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6513 11:53:55.532097 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6514 11:53:55.534944 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6515 11:53:55.538489 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6516 11:53:55.544940 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6517 11:53:55.548537 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6518 11:53:55.551682 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6519 11:53:55.555043 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6520 11:53:55.555459 ==
6521 11:53:55.558557 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 11:53:55.565225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 11:53:55.565671 ==
6524 11:53:55.566003 DQS Delay:
6525 11:53:55.568664 DQS0 = 27, DQS1 = 35
6526 11:53:55.569181 DQM Delay:
6527 11:53:55.569512 DQM0 = 12, DQM1 = 10
6528 11:53:55.571867 DQ Delay:
6529 11:53:55.575287 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6530 11:53:55.578201 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6531 11:53:55.578630 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6532 11:53:55.582074 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6533 11:53:55.582496
6534 11:53:55.585125
6535 11:53:55.585538 ==
6536 11:53:55.588735 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 11:53:55.592026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 11:53:55.592557 ==
6539 11:53:55.592910
6540 11:53:55.593310
6541 11:53:55.595103 TX Vref Scan disable
6542 11:53:55.595526 == TX Byte 0 ==
6543 11:53:55.598002 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6544 11:53:55.605031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6545 11:53:55.605457 == TX Byte 1 ==
6546 11:53:55.608508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6547 11:53:55.615106 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6548 11:53:55.615627 ==
6549 11:53:55.618504 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 11:53:55.621679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 11:53:55.622097 ==
6552 11:53:55.622428
6553 11:53:55.622799
6554 11:53:55.625206 TX Vref Scan disable
6555 11:53:55.625768 == TX Byte 0 ==
6556 11:53:55.628410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6557 11:53:55.635169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6558 11:53:55.635689 == TX Byte 1 ==
6559 11:53:55.638815 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6560 11:53:55.644799 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6561 11:53:55.645389
6562 11:53:55.645807 [DATLAT]
6563 11:53:55.646146 Freq=400, CH0 RK1
6564 11:53:55.646473
6565 11:53:55.648542 DATLAT Default: 0xe
6566 11:53:55.651916 0, 0xFFFF, sum = 0
6567 11:53:55.652438 1, 0xFFFF, sum = 0
6568 11:53:55.655254 2, 0xFFFF, sum = 0
6569 11:53:55.655674 3, 0xFFFF, sum = 0
6570 11:53:55.658113 4, 0xFFFF, sum = 0
6571 11:53:55.658536 5, 0xFFFF, sum = 0
6572 11:53:55.661646 6, 0xFFFF, sum = 0
6573 11:53:55.662127 7, 0xFFFF, sum = 0
6574 11:53:55.664857 8, 0xFFFF, sum = 0
6575 11:53:55.665288 9, 0xFFFF, sum = 0
6576 11:53:55.668287 10, 0xFFFF, sum = 0
6577 11:53:55.668713 11, 0xFFFF, sum = 0
6578 11:53:55.671296 12, 0xFFFF, sum = 0
6579 11:53:55.671813 13, 0x0, sum = 1
6580 11:53:55.674696 14, 0x0, sum = 2
6581 11:53:55.675122 15, 0x0, sum = 3
6582 11:53:55.678470 16, 0x0, sum = 4
6583 11:53:55.678900 best_step = 14
6584 11:53:55.679231
6585 11:53:55.679539 ==
6586 11:53:55.681534 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 11:53:55.685041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 11:53:55.688472 ==
6589 11:53:55.688996 RX Vref Scan: 0
6590 11:53:55.689337
6591 11:53:55.692041 RX Vref 0 -> 0, step: 1
6592 11:53:55.692566
6593 11:53:55.694685 RX Delay -311 -> 252, step: 8
6594 11:53:55.698813 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6595 11:53:55.705665 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6596 11:53:55.708629 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6597 11:53:55.711894 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6598 11:53:55.715427 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6599 11:53:55.721490 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6600 11:53:55.724837 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6601 11:53:55.728201 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6602 11:53:55.731856 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6603 11:53:55.738389 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6604 11:53:55.741502 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6605 11:53:55.745210 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6606 11:53:55.748734 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6607 11:53:55.754537 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6608 11:53:55.757962 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6609 11:53:55.761529 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6610 11:53:55.762157 ==
6611 11:53:55.765284 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 11:53:55.771677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:53:55.772247 ==
6614 11:53:55.772618 DQS Delay:
6615 11:53:55.775149 DQS0 = 24, DQS1 = 32
6616 11:53:55.775727 DQM Delay:
6617 11:53:55.776097 DQM0 = 7, DQM1 = 10
6618 11:53:55.777882 DQ Delay:
6619 11:53:55.781337 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6620 11:53:55.781918 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6621 11:53:55.784560 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6622 11:53:55.787815 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6623 11:53:55.788387
6624 11:53:55.788890
6625 11:53:55.798097 [DQSOSCAuto] RK1, (LSB)MR18= 0xb95b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6626 11:53:55.801650 CH0 RK1: MR19=C0C, MR18=B95B
6627 11:53:55.807930 CH0_RK1: MR19=0xC0C, MR18=0xB95B, DQSOSC=386, MR23=63, INC=396, DEC=264
6628 11:53:55.811059 [RxdqsGatingPostProcess] freq 400
6629 11:53:55.814622 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 11:53:55.817375 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 11:53:55.821481 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 11:53:55.824306 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 11:53:55.827740 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 11:53:55.830947 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 11:53:55.833951 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 11:53:55.837265 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 11:53:55.840761 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 11:53:55.844478 Pre-setting of DQS Precalculation
6639 11:53:55.847687 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 11:53:55.848262 ==
6641 11:53:55.851004 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 11:53:55.854519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:53:55.857455 ==
6644 11:53:55.860775 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 11:53:55.867164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6646 11:53:55.870566 [CA 0] Center 36 (8~64) winsize 57
6647 11:53:55.874319 [CA 1] Center 36 (8~64) winsize 57
6648 11:53:55.877660 [CA 2] Center 36 (8~64) winsize 57
6649 11:53:55.880704 [CA 3] Center 36 (8~64) winsize 57
6650 11:53:55.884275 [CA 4] Center 36 (8~64) winsize 57
6651 11:53:55.887747 [CA 5] Center 36 (8~64) winsize 57
6652 11:53:55.888314
6653 11:53:55.890325 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6654 11:53:55.890800
6655 11:53:55.893970 [CATrainingPosCal] consider 1 rank data
6656 11:53:55.897740 u2DelayCellTimex100 = 270/100 ps
6657 11:53:55.901188 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:53:55.903823 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:53:55.907226 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:53:55.910917 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:53:55.913911 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:53:55.917054 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:53:55.917677
6664 11:53:55.920667 CA PerBit enable=1, Macro0, CA PI delay=36
6665 11:53:55.924188
6666 11:53:55.924655 [CBTSetCACLKResult] CA Dly = 36
6667 11:53:55.927445 CS Dly: 1 (0~32)
6668 11:53:55.927910 ==
6669 11:53:55.930881 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 11:53:55.934040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 11:53:55.934512 ==
6672 11:53:55.940747 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 11:53:55.947372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 11:53:55.951054 [CA 0] Center 36 (8~64) winsize 57
6675 11:53:55.953958 [CA 1] Center 36 (8~64) winsize 57
6676 11:53:55.954597 [CA 2] Center 36 (8~64) winsize 57
6677 11:53:55.957313 [CA 3] Center 36 (8~64) winsize 57
6678 11:53:55.960231 [CA 4] Center 36 (8~64) winsize 57
6679 11:53:55.963669 [CA 5] Center 36 (8~64) winsize 57
6680 11:53:55.964127
6681 11:53:55.966888 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 11:53:55.967344
6683 11:53:55.974172 [CATrainingPosCal] consider 2 rank data
6684 11:53:55.974737 u2DelayCellTimex100 = 270/100 ps
6685 11:53:55.980543 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:53:55.983903 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:53:55.986789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:53:55.990563 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:53:55.993691 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:53:55.997687 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:53:55.998256
6692 11:53:56.000104 CA PerBit enable=1, Macro0, CA PI delay=36
6693 11:53:56.000668
6694 11:53:56.004333 [CBTSetCACLKResult] CA Dly = 36
6695 11:53:56.007379 CS Dly: 1 (0~32)
6696 11:53:56.007941
6697 11:53:56.010229 ----->DramcWriteLeveling(PI) begin...
6698 11:53:56.010938 ==
6699 11:53:56.013456 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 11:53:56.016900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 11:53:56.017564 ==
6702 11:53:56.020281 Write leveling (Byte 0): 40 => 8
6703 11:53:56.023403 Write leveling (Byte 1): 40 => 8
6704 11:53:56.026821 DramcWriteLeveling(PI) end<-----
6705 11:53:56.027295
6706 11:53:56.027766 ==
6707 11:53:56.030149 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 11:53:56.033726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 11:53:56.034287 ==
6710 11:53:56.037257 [Gating] SW mode calibration
6711 11:53:56.043780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 11:53:56.050271 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 11:53:56.053397 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 11:53:56.056579 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 11:53:56.063522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 11:53:56.067234 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 11:53:56.069925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 11:53:56.076472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 11:53:56.080625 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 11:53:56.083523 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 11:53:56.086882 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 11:53:56.090012 Total UI for P1: 0, mck2ui 16
6723 11:53:56.093469 best dqsien dly found for B0: ( 0, 14, 24)
6724 11:53:56.097419 Total UI for P1: 0, mck2ui 16
6725 11:53:56.100155 best dqsien dly found for B1: ( 0, 14, 24)
6726 11:53:56.103913 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 11:53:56.110561 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 11:53:56.111144
6729 11:53:56.113472 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 11:53:56.117201 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 11:53:56.120337 [Gating] SW calibration Done
6732 11:53:56.120916 ==
6733 11:53:56.123161 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 11:53:56.126885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 11:53:56.127376 ==
6736 11:53:56.130086 RX Vref Scan: 0
6737 11:53:56.130659
6738 11:53:56.131140 RX Vref 0 -> 0, step: 1
6739 11:53:56.131590
6740 11:53:56.133021 RX Delay -410 -> 252, step: 16
6741 11:53:56.136991 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6742 11:53:56.143271 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6743 11:53:56.147065 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6744 11:53:56.149970 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6745 11:53:56.153712 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6746 11:53:56.159895 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6747 11:53:56.163010 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6748 11:53:56.166285 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6749 11:53:56.169792 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6750 11:53:56.176391 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6751 11:53:56.179858 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6752 11:53:56.183127 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6753 11:53:56.186346 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6754 11:53:56.193513 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6755 11:53:56.196950 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6756 11:53:56.200294 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6757 11:53:56.200855 ==
6758 11:53:56.202966 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 11:53:56.209963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 11:53:56.210551 ==
6761 11:53:56.211082 DQS Delay:
6762 11:53:56.213467 DQS0 = 27, DQS1 = 35
6763 11:53:56.214101 DQM Delay:
6764 11:53:56.214626 DQM0 = 11, DQM1 = 13
6765 11:53:56.216669 DQ Delay:
6766 11:53:56.220026 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6767 11:53:56.220584 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6768 11:53:56.223520 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6769 11:53:56.226974 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6770 11:53:56.227570
6771 11:53:56.227933
6772 11:53:56.229738 ==
6773 11:53:56.233346 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 11:53:56.236409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 11:53:56.236873 ==
6776 11:53:56.237233
6777 11:53:56.237564
6778 11:53:56.239506 TX Vref Scan disable
6779 11:53:56.239963 == TX Byte 0 ==
6780 11:53:56.242828 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 11:53:56.249751 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 11:53:56.250311 == TX Byte 1 ==
6783 11:53:56.253157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 11:53:56.259475 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 11:53:56.260038 ==
6786 11:53:56.262612 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 11:53:56.266228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 11:53:56.266762 ==
6789 11:53:56.267133
6790 11:53:56.267468
6791 11:53:56.269357 TX Vref Scan disable
6792 11:53:56.269931 == TX Byte 0 ==
6793 11:53:56.272910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 11:53:56.279461 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 11:53:56.280029 == TX Byte 1 ==
6796 11:53:56.282866 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 11:53:56.289352 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 11:53:56.289860
6799 11:53:56.290228 [DATLAT]
6800 11:53:56.290577 Freq=400, CH1 RK0
6801 11:53:56.291000
6802 11:53:56.292625 DATLAT Default: 0xf
6803 11:53:56.296025 0, 0xFFFF, sum = 0
6804 11:53:56.296454 1, 0xFFFF, sum = 0
6805 11:53:56.299306 2, 0xFFFF, sum = 0
6806 11:53:56.299830 3, 0xFFFF, sum = 0
6807 11:53:56.302573 4, 0xFFFF, sum = 0
6808 11:53:56.303145 5, 0xFFFF, sum = 0
6809 11:53:56.306329 6, 0xFFFF, sum = 0
6810 11:53:56.306897 7, 0xFFFF, sum = 0
6811 11:53:56.309187 8, 0xFFFF, sum = 0
6812 11:53:56.309698 9, 0xFFFF, sum = 0
6813 11:53:56.312408 10, 0xFFFF, sum = 0
6814 11:53:56.312881 11, 0xFFFF, sum = 0
6815 11:53:56.316091 12, 0xFFFF, sum = 0
6816 11:53:56.316566 13, 0x0, sum = 1
6817 11:53:56.319451 14, 0x0, sum = 2
6818 11:53:56.319923 15, 0x0, sum = 3
6819 11:53:56.322370 16, 0x0, sum = 4
6820 11:53:56.322798 best_step = 14
6821 11:53:56.323148
6822 11:53:56.323461 ==
6823 11:53:56.325713 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 11:53:56.329093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 11:53:56.332214 ==
6826 11:53:56.332636 RX Vref Scan: 1
6827 11:53:56.332968
6828 11:53:56.336020 RX Vref 0 -> 0, step: 1
6829 11:53:56.336443
6830 11:53:56.339147 RX Delay -311 -> 252, step: 8
6831 11:53:56.339570
6832 11:53:56.342235 Set Vref, RX VrefLevel [Byte0]: 54
6833 11:53:56.345438 [Byte1]: 52
6834 11:53:56.345993
6835 11:53:56.349566 Final RX Vref Byte 0 = 54 to rank0
6836 11:53:56.352756 Final RX Vref Byte 1 = 52 to rank0
6837 11:53:56.356103 Final RX Vref Byte 0 = 54 to rank1
6838 11:53:56.359221 Final RX Vref Byte 1 = 52 to rank1==
6839 11:53:56.362066 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 11:53:56.365519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 11:53:56.366024 ==
6842 11:53:56.368767 DQS Delay:
6843 11:53:56.369189 DQS0 = 28, DQS1 = 32
6844 11:53:56.372183 DQM Delay:
6845 11:53:56.372606 DQM0 = 9, DQM1 = 11
6846 11:53:56.372940 DQ Delay:
6847 11:53:56.375285 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6848 11:53:56.379120 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6849 11:53:56.381929 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6850 11:53:56.385573 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6851 11:53:56.386041
6852 11:53:56.386371
6853 11:53:56.395479 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6854 11:53:56.395979 CH1 RK0: MR19=C0C, MR18=94CD
6855 11:53:56.401797 CH1_RK0: MR19=0xC0C, MR18=0x94CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6856 11:53:56.402320 ==
6857 11:53:56.405340 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 11:53:56.412259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 11:53:56.412781 ==
6860 11:53:56.415683 [Gating] SW mode calibration
6861 11:53:56.421842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 11:53:56.425239 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 11:53:56.432562 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 11:53:56.435507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 11:53:56.438893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 11:53:56.445112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 11:53:56.448509 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 11:53:56.451678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 11:53:56.458567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 11:53:56.461821 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 11:53:56.465236 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 11:53:56.468131 Total UI for P1: 0, mck2ui 16
6873 11:53:56.472172 best dqsien dly found for B0: ( 0, 14, 24)
6874 11:53:56.475212 Total UI for P1: 0, mck2ui 16
6875 11:53:56.478428 best dqsien dly found for B1: ( 0, 14, 24)
6876 11:53:56.481652 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 11:53:56.485382 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 11:53:56.485993
6879 11:53:56.488578 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 11:53:56.495484 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 11:53:56.495945 [Gating] SW calibration Done
6882 11:53:56.496303 ==
6883 11:53:56.498690 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 11:53:56.505076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 11:53:56.505678 ==
6886 11:53:56.506053 RX Vref Scan: 0
6887 11:53:56.506392
6888 11:53:56.508373 RX Vref 0 -> 0, step: 1
6889 11:53:56.508929
6890 11:53:56.512062 RX Delay -410 -> 252, step: 16
6891 11:53:56.515131 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6892 11:53:56.518145 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6893 11:53:56.525164 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6894 11:53:56.528199 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6895 11:53:56.532137 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6896 11:53:56.535176 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6897 11:53:56.541544 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6898 11:53:56.544965 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6899 11:53:56.548420 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6900 11:53:56.551700 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6901 11:53:56.558484 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6902 11:53:56.561288 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6903 11:53:56.564745 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6904 11:53:56.568788 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6905 11:53:56.574608 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6906 11:53:56.578650 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6907 11:53:56.579223 ==
6908 11:53:56.581287 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 11:53:56.584892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 11:53:56.585439 ==
6911 11:53:56.588574 DQS Delay:
6912 11:53:56.589073 DQS0 = 35, DQS1 = 35
6913 11:53:56.589434 DQM Delay:
6914 11:53:56.591604 DQM0 = 18, DQM1 = 14
6915 11:53:56.592179 DQ Delay:
6916 11:53:56.595221 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6917 11:53:56.598451 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6918 11:53:56.601683 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6919 11:53:56.604865 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6920 11:53:56.605281
6921 11:53:56.605653
6922 11:53:56.605971 ==
6923 11:53:56.608691 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 11:53:56.611575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 11:53:56.614789 ==
6926 11:53:56.615274
6927 11:53:56.615600
6928 11:53:56.615945 TX Vref Scan disable
6929 11:53:56.618257 == TX Byte 0 ==
6930 11:53:56.621404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6931 11:53:56.624721 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6932 11:53:56.628095 == TX Byte 1 ==
6933 11:53:56.631347 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6934 11:53:56.635281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6935 11:53:56.635809 ==
6936 11:53:56.638306 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 11:53:56.645014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 11:53:56.645564 ==
6939 11:53:56.645955
6940 11:53:56.646264
6941 11:53:56.646558 TX Vref Scan disable
6942 11:53:56.647924 == TX Byte 0 ==
6943 11:53:56.651482 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6944 11:53:56.655223 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6945 11:53:56.658396 == TX Byte 1 ==
6946 11:53:56.661402 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6947 11:53:56.664537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6948 11:53:56.665013
6949 11:53:56.667839 [DATLAT]
6950 11:53:56.668276 Freq=400, CH1 RK1
6951 11:53:56.668621
6952 11:53:56.671567 DATLAT Default: 0xe
6953 11:53:56.671980 0, 0xFFFF, sum = 0
6954 11:53:56.674700 1, 0xFFFF, sum = 0
6955 11:53:56.675135 2, 0xFFFF, sum = 0
6956 11:53:56.678010 3, 0xFFFF, sum = 0
6957 11:53:56.678431 4, 0xFFFF, sum = 0
6958 11:53:56.681130 5, 0xFFFF, sum = 0
6959 11:53:56.681549 6, 0xFFFF, sum = 0
6960 11:53:56.684678 7, 0xFFFF, sum = 0
6961 11:53:56.685256 8, 0xFFFF, sum = 0
6962 11:53:56.687633 9, 0xFFFF, sum = 0
6963 11:53:56.688171 10, 0xFFFF, sum = 0
6964 11:53:56.690939 11, 0xFFFF, sum = 0
6965 11:53:56.691349 12, 0xFFFF, sum = 0
6966 11:53:56.694581 13, 0x0, sum = 1
6967 11:53:56.695020 14, 0x0, sum = 2
6968 11:53:56.697660 15, 0x0, sum = 3
6969 11:53:56.698116 16, 0x0, sum = 4
6970 11:53:56.700914 best_step = 14
6971 11:53:56.701322
6972 11:53:56.701750 ==
6973 11:53:56.704215 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 11:53:56.707592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 11:53:56.708154 ==
6976 11:53:56.711041 RX Vref Scan: 0
6977 11:53:56.711451
6978 11:53:56.711911 RX Vref 0 -> 0, step: 1
6979 11:53:56.712242
6980 11:53:56.714228 RX Delay -311 -> 252, step: 8
6981 11:53:56.722476 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6982 11:53:56.725517 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6983 11:53:56.729183 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6984 11:53:56.732166 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6985 11:53:56.739087 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6986 11:53:56.742449 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6987 11:53:56.745626 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6988 11:53:56.748766 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6989 11:53:56.755883 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6990 11:53:56.758919 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6991 11:53:56.762462 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6992 11:53:56.765509 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6993 11:53:56.772029 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6994 11:53:56.776119 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6995 11:53:56.779480 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6996 11:53:56.782425 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6997 11:53:56.785414 ==
6998 11:53:56.788731 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 11:53:56.792069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 11:53:56.792496 ==
7001 11:53:56.792826 DQS Delay:
7002 11:53:56.795871 DQS0 = 28, DQS1 = 36
7003 11:53:56.796388 DQM Delay:
7004 11:53:56.798630 DQM0 = 10, DQM1 = 14
7005 11:53:56.799048 DQ Delay:
7006 11:53:56.802129 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7007 11:53:56.805684 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7008 11:53:56.808977 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7009 11:53:56.812498 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7010 11:53:56.813017
7011 11:53:56.813350
7012 11:53:56.819168 [DQSOSCAuto] RK1, (LSB)MR18= 0xc557, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7013 11:53:56.822373 CH1 RK1: MR19=C0C, MR18=C557
7014 11:53:56.828822 CH1_RK1: MR19=0xC0C, MR18=0xC557, DQSOSC=385, MR23=63, INC=398, DEC=265
7015 11:53:56.832262 [RxdqsGatingPostProcess] freq 400
7016 11:53:56.835160 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 11:53:56.838213 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 11:53:56.842090 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 11:53:56.845792 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 11:53:56.849149 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 11:53:56.851819 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 11:53:56.855682 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 11:53:56.858707 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 11:53:56.861649 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 11:53:56.864923 Pre-setting of DQS Precalculation
7026 11:53:56.871658 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 11:53:56.878858 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 11:53:56.884914 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 11:53:56.885472
7030 11:53:56.885869
7031 11:53:56.888296 [Calibration Summary] 800 Mbps
7032 11:53:56.888852 CH 0, Rank 0
7033 11:53:56.891792 SW Impedance : PASS
7034 11:53:56.892416 DUTY Scan : NO K
7035 11:53:56.894869 ZQ Calibration : PASS
7036 11:53:56.898114 Jitter Meter : NO K
7037 11:53:56.898576 CBT Training : PASS
7038 11:53:56.901258 Write leveling : PASS
7039 11:53:56.904963 RX DQS gating : PASS
7040 11:53:56.905426 RX DQ/DQS(RDDQC) : PASS
7041 11:53:56.908072 TX DQ/DQS : PASS
7042 11:53:56.911866 RX DATLAT : PASS
7043 11:53:56.912424 RX DQ/DQS(Engine): PASS
7044 11:53:56.915139 TX OE : NO K
7045 11:53:56.915699 All Pass.
7046 11:53:56.916065
7047 11:53:56.918053 CH 0, Rank 1
7048 11:53:56.918680 SW Impedance : PASS
7049 11:53:56.921266 DUTY Scan : NO K
7050 11:53:56.924320 ZQ Calibration : PASS
7051 11:53:56.924782 Jitter Meter : NO K
7052 11:53:56.927847 CBT Training : PASS
7053 11:53:56.931416 Write leveling : NO K
7054 11:53:56.931970 RX DQS gating : PASS
7055 11:53:56.934636 RX DQ/DQS(RDDQC) : PASS
7056 11:53:56.937931 TX DQ/DQS : PASS
7057 11:53:56.938396 RX DATLAT : PASS
7058 11:53:56.941686 RX DQ/DQS(Engine): PASS
7059 11:53:56.942291 TX OE : NO K
7060 11:53:56.944565 All Pass.
7061 11:53:56.945115
7062 11:53:56.945479 CH 1, Rank 0
7063 11:53:56.948280 SW Impedance : PASS
7064 11:53:56.948840 DUTY Scan : NO K
7065 11:53:56.951357 ZQ Calibration : PASS
7066 11:53:56.954656 Jitter Meter : NO K
7067 11:53:56.955217 CBT Training : PASS
7068 11:53:56.958066 Write leveling : PASS
7069 11:53:56.961379 RX DQS gating : PASS
7070 11:53:56.961897 RX DQ/DQS(RDDQC) : PASS
7071 11:53:56.964475 TX DQ/DQS : PASS
7072 11:53:56.967632 RX DATLAT : PASS
7073 11:53:56.968099 RX DQ/DQS(Engine): PASS
7074 11:53:56.971038 TX OE : NO K
7075 11:53:56.971597 All Pass.
7076 11:53:56.971966
7077 11:53:56.974583 CH 1, Rank 1
7078 11:53:56.975086 SW Impedance : PASS
7079 11:53:56.978150 DUTY Scan : NO K
7080 11:53:56.980891 ZQ Calibration : PASS
7081 11:53:56.981369 Jitter Meter : NO K
7082 11:53:56.984422 CBT Training : PASS
7083 11:53:56.987932 Write leveling : NO K
7084 11:53:56.988395 RX DQS gating : PASS
7085 11:53:56.991060 RX DQ/DQS(RDDQC) : PASS
7086 11:53:56.991522 TX DQ/DQS : PASS
7087 11:53:56.994283 RX DATLAT : PASS
7088 11:53:56.997629 RX DQ/DQS(Engine): PASS
7089 11:53:56.998194 TX OE : NO K
7090 11:53:57.001447 All Pass.
7091 11:53:57.002050
7092 11:53:57.002421 DramC Write-DBI off
7093 11:53:57.004273 PER_BANK_REFRESH: Hybrid Mode
7094 11:53:57.007553 TX_TRACKING: ON
7095 11:53:57.014688 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 11:53:57.018165 [FAST_K] Save calibration result to emmc
7097 11:53:57.021222 dramc_set_vcore_voltage set vcore to 725000
7098 11:53:57.024064 Read voltage for 1600, 0
7099 11:53:57.024528 Vio18 = 0
7100 11:53:57.027243 Vcore = 725000
7101 11:53:57.027702 Vdram = 0
7102 11:53:57.028067 Vddq = 0
7103 11:53:57.031407 Vmddr = 0
7104 11:53:57.034349 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 11:53:57.040924 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 11:53:57.041498 MEM_TYPE=3, freq_sel=13
7107 11:53:57.044142 sv_algorithm_assistance_LP4_3733
7108 11:53:57.050828 ============ PULL DRAM RESETB DOWN ============
7109 11:53:57.054247 ========== PULL DRAM RESETB DOWN end =========
7110 11:53:57.057715 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 11:53:57.060609 ===================================
7112 11:53:57.063969 LPDDR4 DRAM CONFIGURATION
7113 11:53:57.067447 ===================================
7114 11:53:57.070250 EX_ROW_EN[0] = 0x0
7115 11:53:57.070663 EX_ROW_EN[1] = 0x0
7116 11:53:57.073713 LP4Y_EN = 0x0
7117 11:53:57.074127 WORK_FSP = 0x1
7118 11:53:57.077229 WL = 0x5
7119 11:53:57.077668 RL = 0x5
7120 11:53:57.080592 BL = 0x2
7121 11:53:57.081081 RPST = 0x0
7122 11:53:57.083969 RD_PRE = 0x0
7123 11:53:57.084382 WR_PRE = 0x1
7124 11:53:57.087027 WR_PST = 0x1
7125 11:53:57.087446 DBI_WR = 0x0
7126 11:53:57.090381 DBI_RD = 0x0
7127 11:53:57.090799 OTF = 0x1
7128 11:53:57.093689 ===================================
7129 11:53:57.097274 ===================================
7130 11:53:57.100913 ANA top config
7131 11:53:57.103695 ===================================
7132 11:53:57.107267 DLL_ASYNC_EN = 0
7133 11:53:57.107836 ALL_SLAVE_EN = 0
7134 11:53:57.110841 NEW_RANK_MODE = 1
7135 11:53:57.113741 DLL_IDLE_MODE = 1
7136 11:53:57.117310 LP45_APHY_COMB_EN = 1
7137 11:53:57.117821 TX_ODT_DIS = 0
7138 11:53:57.120316 NEW_8X_MODE = 1
7139 11:53:57.124171 ===================================
7140 11:53:57.127290 ===================================
7141 11:53:57.130483 data_rate = 3200
7142 11:53:57.134057 CKR = 1
7143 11:53:57.136905 DQ_P2S_RATIO = 8
7144 11:53:57.140651 ===================================
7145 11:53:57.143734 CA_P2S_RATIO = 8
7146 11:53:57.144198 DQ_CA_OPEN = 0
7147 11:53:57.147142 DQ_SEMI_OPEN = 0
7148 11:53:57.150873 CA_SEMI_OPEN = 0
7149 11:53:57.153794 CA_FULL_RATE = 0
7150 11:53:57.157513 DQ_CKDIV4_EN = 0
7151 11:53:57.160738 CA_CKDIV4_EN = 0
7152 11:53:57.161308 CA_PREDIV_EN = 0
7153 11:53:57.163826 PH8_DLY = 12
7154 11:53:57.167032 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 11:53:57.170284 DQ_AAMCK_DIV = 4
7156 11:53:57.174243 CA_AAMCK_DIV = 4
7157 11:53:57.177326 CA_ADMCK_DIV = 4
7158 11:53:57.177955 DQ_TRACK_CA_EN = 0
7159 11:53:57.180445 CA_PICK = 1600
7160 11:53:57.183618 CA_MCKIO = 1600
7161 11:53:57.186848 MCKIO_SEMI = 0
7162 11:53:57.191144 PLL_FREQ = 3068
7163 11:53:57.193769 DQ_UI_PI_RATIO = 32
7164 11:53:57.197474 CA_UI_PI_RATIO = 0
7165 11:53:57.200696 ===================================
7166 11:53:57.203570 ===================================
7167 11:53:57.204016 memory_type:LPDDR4
7168 11:53:57.207411 GP_NUM : 10
7169 11:53:57.207873 SRAM_EN : 1
7170 11:53:57.210297 MD32_EN : 0
7171 11:53:57.213619 ===================================
7172 11:53:57.216956 [ANA_INIT] >>>>>>>>>>>>>>
7173 11:53:57.220666 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 11:53:57.223714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 11:53:57.226891 ===================================
7176 11:53:57.230127 data_rate = 3200,PCW = 0X7600
7177 11:53:57.233695 ===================================
7178 11:53:57.237006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 11:53:57.240167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 11:53:57.247075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 11:53:57.250237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 11:53:57.253503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 11:53:57.257242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 11:53:57.260483 [ANA_INIT] flow start
7185 11:53:57.263698 [ANA_INIT] PLL >>>>>>>>
7186 11:53:57.264155 [ANA_INIT] PLL <<<<<<<<
7187 11:53:57.266716 [ANA_INIT] MIDPI >>>>>>>>
7188 11:53:57.270617 [ANA_INIT] MIDPI <<<<<<<<
7189 11:53:57.271074 [ANA_INIT] DLL >>>>>>>>
7190 11:53:57.274000 [ANA_INIT] DLL <<<<<<<<
7191 11:53:57.277346 [ANA_INIT] flow end
7192 11:53:57.280636 ============ LP4 DIFF to SE enter ============
7193 11:53:57.283940 ============ LP4 DIFF to SE exit ============
7194 11:53:57.286761 [ANA_INIT] <<<<<<<<<<<<<
7195 11:53:57.290266 [Flow] Enable top DCM control >>>>>
7196 11:53:57.293989 [Flow] Enable top DCM control <<<<<
7197 11:53:57.297431 Enable DLL master slave shuffle
7198 11:53:57.300268 ==============================================================
7199 11:53:57.303878 Gating Mode config
7200 11:53:57.307089 ==============================================================
7201 11:53:57.310166 Config description:
7202 11:53:57.320669 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 11:53:57.326896 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 11:53:57.330514 SELPH_MODE 0: By rank 1: By Phase
7205 11:53:57.337952 ==============================================================
7206 11:53:57.340466 GAT_TRACK_EN = 1
7207 11:53:57.343552 RX_GATING_MODE = 2
7208 11:53:57.347653 RX_GATING_TRACK_MODE = 2
7209 11:53:57.350466 SELPH_MODE = 1
7210 11:53:57.353917 PICG_EARLY_EN = 1
7211 11:53:57.354352 VALID_LAT_VALUE = 1
7212 11:53:57.360251 ==============================================================
7213 11:53:57.363884 Enter into Gating configuration >>>>
7214 11:53:57.366790 Exit from Gating configuration <<<<
7215 11:53:57.370278 Enter into DVFS_PRE_config >>>>>
7216 11:53:57.380667 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 11:53:57.383585 Exit from DVFS_PRE_config <<<<<
7218 11:53:57.386851 Enter into PICG configuration >>>>
7219 11:53:57.390128 Exit from PICG configuration <<<<
7220 11:53:57.393956 [RX_INPUT] configuration >>>>>
7221 11:53:57.396923 [RX_INPUT] configuration <<<<<
7222 11:53:57.400362 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 11:53:57.407241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 11:53:57.413226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 11:53:57.419903 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 11:53:57.426897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 11:53:57.433355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 11:53:57.437045 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 11:53:57.440262 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 11:53:57.443250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 11:53:57.446846 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 11:53:57.453551 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 11:53:57.456970 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 11:53:57.460190 ===================================
7235 11:53:57.463398 LPDDR4 DRAM CONFIGURATION
7236 11:53:57.466590 ===================================
7237 11:53:57.467037 EX_ROW_EN[0] = 0x0
7238 11:53:57.470099 EX_ROW_EN[1] = 0x0
7239 11:53:57.470512 LP4Y_EN = 0x0
7240 11:53:57.473423 WORK_FSP = 0x1
7241 11:53:57.473917 WL = 0x5
7242 11:53:57.476929 RL = 0x5
7243 11:53:57.477453 BL = 0x2
7244 11:53:57.479947 RPST = 0x0
7245 11:53:57.483416 RD_PRE = 0x0
7246 11:53:57.483860 WR_PRE = 0x1
7247 11:53:57.487038 WR_PST = 0x1
7248 11:53:57.487491 DBI_WR = 0x0
7249 11:53:57.490074 DBI_RD = 0x0
7250 11:53:57.490492 OTF = 0x1
7251 11:53:57.493228 ===================================
7252 11:53:57.496348 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 11:53:57.500018 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 11:53:57.506861 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 11:53:57.509945 ===================================
7256 11:53:57.513305 LPDDR4 DRAM CONFIGURATION
7257 11:53:57.516460 ===================================
7258 11:53:57.516882 EX_ROW_EN[0] = 0x10
7259 11:53:57.519758 EX_ROW_EN[1] = 0x0
7260 11:53:57.520179 LP4Y_EN = 0x0
7261 11:53:57.523422 WORK_FSP = 0x1
7262 11:53:57.523943 WL = 0x5
7263 11:53:57.526429 RL = 0x5
7264 11:53:57.527012 BL = 0x2
7265 11:53:57.530205 RPST = 0x0
7266 11:53:57.530723 RD_PRE = 0x0
7267 11:53:57.533461 WR_PRE = 0x1
7268 11:53:57.534027 WR_PST = 0x1
7269 11:53:57.536704 DBI_WR = 0x0
7270 11:53:57.537378 DBI_RD = 0x0
7271 11:53:57.539725 OTF = 0x1
7272 11:53:57.543383 ===================================
7273 11:53:57.549981 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 11:53:57.550499 ==
7275 11:53:57.553649 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 11:53:57.556832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 11:53:57.557330 ==
7278 11:53:57.560211 [Duty_Offset_Calibration]
7279 11:53:57.560738 B0:2 B1:1 CA:1
7280 11:53:57.561100
7281 11:53:57.563219 [DutyScan_Calibration_Flow] k_type=0
7282 11:53:57.574123
7283 11:53:57.574534 ==CLK 0==
7284 11:53:57.577626 Final CLK duty delay cell = 0
7285 11:53:57.580791 [0] MAX Duty = 5187%(X100), DQS PI = 22
7286 11:53:57.584320 [0] MIN Duty = 4907%(X100), DQS PI = 0
7287 11:53:57.584841 [0] AVG Duty = 5047%(X100)
7288 11:53:57.585213
7289 11:53:57.587289 CH0 CLK Duty spec in!! Max-Min= 280%
7290 11:53:57.594477 [DutyScan_Calibration_Flow] ====Done====
7291 11:53:57.594988
7292 11:53:57.597554 [DutyScan_Calibration_Flow] k_type=1
7293 11:53:57.613296
7294 11:53:57.613878 ==DQS 0 ==
7295 11:53:57.616758 Final DQS duty delay cell = -4
7296 11:53:57.619598 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7297 11:53:57.623324 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7298 11:53:57.626247 [-4] AVG Duty = 4891%(X100)
7299 11:53:57.626876
7300 11:53:57.627352 ==DQS 1 ==
7301 11:53:57.629889 Final DQS duty delay cell = 0
7302 11:53:57.633020 [0] MAX Duty = 5187%(X100), DQS PI = 2
7303 11:53:57.636645 [0] MIN Duty = 5031%(X100), DQS PI = 52
7304 11:53:57.639749 [0] AVG Duty = 5109%(X100)
7305 11:53:57.640265
7306 11:53:57.642733 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7307 11:53:57.643195
7308 11:53:57.646504 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7309 11:53:57.649715 [DutyScan_Calibration_Flow] ====Done====
7310 11:53:57.650141
7311 11:53:57.652685 [DutyScan_Calibration_Flow] k_type=3
7312 11:53:57.670079
7313 11:53:57.670742 ==DQM 0 ==
7314 11:53:57.673235 Final DQM duty delay cell = 0
7315 11:53:57.676562 [0] MAX Duty = 5218%(X100), DQS PI = 34
7316 11:53:57.679683 [0] MIN Duty = 4907%(X100), DQS PI = 56
7317 11:53:57.682846 [0] AVG Duty = 5062%(X100)
7318 11:53:57.683272
7319 11:53:57.683606 ==DQM 1 ==
7320 11:53:57.686081 Final DQM duty delay cell = -4
7321 11:53:57.690054 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7322 11:53:57.693068 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7323 11:53:57.696488 [-4] AVG Duty = 4922%(X100)
7324 11:53:57.696925
7325 11:53:57.699786 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7326 11:53:57.700225
7327 11:53:57.702875 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7328 11:53:57.706017 [DutyScan_Calibration_Flow] ====Done====
7329 11:53:57.706451
7330 11:53:57.709710 [DutyScan_Calibration_Flow] k_type=2
7331 11:53:57.727448
7332 11:53:57.727885 ==DQ 0 ==
7333 11:53:57.730528 Final DQ duty delay cell = 0
7334 11:53:57.733743 [0] MAX Duty = 5062%(X100), DQS PI = 24
7335 11:53:57.737489 [0] MIN Duty = 4907%(X100), DQS PI = 0
7336 11:53:57.737962 [0] AVG Duty = 4984%(X100)
7337 11:53:57.740580
7338 11:53:57.740999 ==DQ 1 ==
7339 11:53:57.743735 Final DQ duty delay cell = 0
7340 11:53:57.747155 [0] MAX Duty = 5125%(X100), DQS PI = 4
7341 11:53:57.750767 [0] MIN Duty = 4907%(X100), DQS PI = 34
7342 11:53:57.751030 [0] AVG Duty = 5016%(X100)
7343 11:53:57.751096
7344 11:53:57.753485 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7345 11:53:57.756756
7346 11:53:57.759820 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7347 11:53:57.763628 [DutyScan_Calibration_Flow] ====Done====
7348 11:53:57.763710 ==
7349 11:53:57.766937 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 11:53:57.769699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 11:53:57.769782 ==
7352 11:53:57.773426 [Duty_Offset_Calibration]
7353 11:53:57.773508 B0:1 B1:0 CA:0
7354 11:53:57.773572
7355 11:53:57.776505 [DutyScan_Calibration_Flow] k_type=0
7356 11:53:57.786234
7357 11:53:57.786316 ==CLK 0==
7358 11:53:57.789714 Final CLK duty delay cell = -4
7359 11:53:57.792632 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7360 11:53:57.796364 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7361 11:53:57.799247 [-4] AVG Duty = 4922%(X100)
7362 11:53:57.799355
7363 11:53:57.803131 CH1 CLK Duty spec in!! Max-Min= 156%
7364 11:53:57.806309 [DutyScan_Calibration_Flow] ====Done====
7365 11:53:57.806391
7366 11:53:57.809388 [DutyScan_Calibration_Flow] k_type=1
7367 11:53:57.826057
7368 11:53:57.826140 ==DQS 0 ==
7369 11:53:57.829461 Final DQS duty delay cell = 0
7370 11:53:57.832680 [0] MAX Duty = 5094%(X100), DQS PI = 16
7371 11:53:57.835909 [0] MIN Duty = 4844%(X100), DQS PI = 50
7372 11:53:57.839223 [0] AVG Duty = 4969%(X100)
7373 11:53:57.839304
7374 11:53:57.839368 ==DQS 1 ==
7375 11:53:57.843070 Final DQS duty delay cell = 0
7376 11:53:57.845947 [0] MAX Duty = 5249%(X100), DQS PI = 16
7377 11:53:57.849953 [0] MIN Duty = 4969%(X100), DQS PI = 8
7378 11:53:57.850035 [0] AVG Duty = 5109%(X100)
7379 11:53:57.853312
7380 11:53:57.856365 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7381 11:53:57.856447
7382 11:53:57.859754 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7383 11:53:57.862747 [DutyScan_Calibration_Flow] ====Done====
7384 11:53:57.862833
7385 11:53:57.866012 [DutyScan_Calibration_Flow] k_type=3
7386 11:53:57.882892
7387 11:53:57.882976 ==DQM 0 ==
7388 11:53:57.886489 Final DQM duty delay cell = 0
7389 11:53:57.890290 [0] MAX Duty = 5218%(X100), DQS PI = 18
7390 11:53:57.893119 [0] MIN Duty = 4969%(X100), DQS PI = 48
7391 11:53:57.896749 [0] AVG Duty = 5093%(X100)
7392 11:53:57.896832
7393 11:53:57.896899 ==DQM 1 ==
7394 11:53:57.899780 Final DQM duty delay cell = 0
7395 11:53:57.903005 [0] MAX Duty = 5093%(X100), DQS PI = 16
7396 11:53:57.906338 [0] MIN Duty = 4938%(X100), DQS PI = 6
7397 11:53:57.906425 [0] AVG Duty = 5015%(X100)
7398 11:53:57.909825
7399 11:53:57.913263 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7400 11:53:57.913370
7401 11:53:57.916800 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7402 11:53:57.919866 [DutyScan_Calibration_Flow] ====Done====
7403 11:53:57.919947
7404 11:53:57.922921 [DutyScan_Calibration_Flow] k_type=2
7405 11:53:57.939279
7406 11:53:57.939363 ==DQ 0 ==
7407 11:53:57.942483 Final DQ duty delay cell = -4
7408 11:53:57.945839 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7409 11:53:57.949414 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7410 11:53:57.952488 [-4] AVG Duty = 4968%(X100)
7411 11:53:57.952593
7412 11:53:57.952685 ==DQ 1 ==
7413 11:53:57.955507 Final DQ duty delay cell = 0
7414 11:53:57.959107 [0] MAX Duty = 5124%(X100), DQS PI = 16
7415 11:53:57.962225 [0] MIN Duty = 4969%(X100), DQS PI = 10
7416 11:53:57.965556 [0] AVG Duty = 5046%(X100)
7417 11:53:57.965646
7418 11:53:57.969341 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7419 11:53:57.969447
7420 11:53:57.972731 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7421 11:53:57.975887 [DutyScan_Calibration_Flow] ====Done====
7422 11:53:57.979083 nWR fixed to 30
7423 11:53:57.982670 [ModeRegInit_LP4] CH0 RK0
7424 11:53:57.982752 [ModeRegInit_LP4] CH0 RK1
7425 11:53:57.985226 [ModeRegInit_LP4] CH1 RK0
7426 11:53:57.989112 [ModeRegInit_LP4] CH1 RK1
7427 11:53:57.989213 match AC timing 5
7428 11:53:57.995636 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 11:53:57.998919 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 11:53:58.001886 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 11:53:58.008674 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 11:53:58.012711 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 11:53:58.012793 [MiockJmeterHQA]
7434 11:53:58.012858
7435 11:53:58.015791 [DramcMiockJmeter] u1RxGatingPI = 0
7436 11:53:58.018987 0 : 4252, 4026
7437 11:53:58.019071 4 : 4363, 4137
7438 11:53:58.022212 8 : 4255, 4030
7439 11:53:58.022328 12 : 4252, 4027
7440 11:53:58.022424 16 : 4253, 4027
7441 11:53:58.025512 20 : 4252, 4027
7442 11:53:58.025656 24 : 4253, 4026
7443 11:53:58.028906 28 : 4257, 4029
7444 11:53:58.029011 32 : 4252, 4027
7445 11:53:58.032164 36 : 4255, 4029
7446 11:53:58.032267 40 : 4255, 4029
7447 11:53:58.035634 44 : 4363, 4137
7448 11:53:58.035737 48 : 4363, 4138
7449 11:53:58.035829 52 : 4255, 4029
7450 11:53:58.038617 56 : 4252, 4027
7451 11:53:58.038694 60 : 4252, 4027
7452 11:53:58.041909 64 : 4252, 4029
7453 11:53:58.041987 68 : 4252, 4030
7454 11:53:58.045330 72 : 4252, 4027
7455 11:53:58.045436 76 : 4252, 4029
7456 11:53:58.048380 80 : 4255, 4029
7457 11:53:58.048471 84 : 4250, 4027
7458 11:53:58.048538 88 : 4253, 179
7459 11:53:58.051747 92 : 4360, 0
7460 11:53:58.051853 96 : 4252, 0
7461 11:53:58.055323 100 : 4250, 0
7462 11:53:58.055435 104 : 4250, 0
7463 11:53:58.055528 108 : 4363, 0
7464 11:53:58.058857 112 : 4361, 0
7465 11:53:58.058931 116 : 4363, 0
7466 11:53:58.058992 120 : 4252, 0
7467 11:53:58.062069 124 : 4250, 0
7468 11:53:58.062147 128 : 4250, 0
7469 11:53:58.065467 132 : 4360, 0
7470 11:53:58.065596 136 : 4250, 0
7471 11:53:58.065698 140 : 4250, 0
7472 11:53:58.068455 144 : 4253, 0
7473 11:53:58.068556 148 : 4250, 0
7474 11:53:58.071649 152 : 4250, 0
7475 11:53:58.071758 156 : 4252, 0
7476 11:53:58.071855 160 : 4253, 0
7477 11:53:58.075065 164 : 4360, 0
7478 11:53:58.075168 168 : 4360, 0
7479 11:53:58.078183 172 : 4249, 0
7480 11:53:58.078283 176 : 4250, 0
7481 11:53:58.078374 180 : 4250, 0
7482 11:53:58.082059 184 : 4253, 0
7483 11:53:58.082160 188 : 4250, 0
7484 11:53:58.085278 192 : 4250, 0
7485 11:53:58.085381 196 : 4250, 0
7486 11:53:58.085485 200 : 4363, 0
7487 11:53:58.088253 204 : 4250, 1263
7488 11:53:58.088355 208 : 4250, 3990
7489 11:53:58.092148 212 : 4252, 4030
7490 11:53:58.092245 216 : 4249, 4027
7491 11:53:58.095239 220 : 4250, 4026
7492 11:53:58.095314 224 : 4250, 4027
7493 11:53:58.098393 228 : 4249, 4027
7494 11:53:58.098493 232 : 4252, 4029
7495 11:53:58.098593 236 : 4250, 4027
7496 11:53:58.101910 240 : 4249, 4027
7497 11:53:58.102024 244 : 4360, 4138
7498 11:53:58.105023 248 : 4250, 4027
7499 11:53:58.105122 252 : 4361, 4137
7500 11:53:58.108406 256 : 4249, 4027
7501 11:53:58.108511 260 : 4250, 4027
7502 11:53:58.111905 264 : 4250, 4027
7503 11:53:58.112002 268 : 4250, 4026
7504 11:53:58.115249 272 : 4250, 4026
7505 11:53:58.115321 276 : 4252, 4027
7506 11:53:58.118279 280 : 4249, 4027
7507 11:53:58.118347 284 : 4252, 4029
7508 11:53:58.121563 288 : 4250, 4027
7509 11:53:58.121672 292 : 4249, 4027
7510 11:53:58.121734 296 : 4360, 4138
7511 11:53:58.124677 300 : 4250, 4027
7512 11:53:58.124747 304 : 4361, 4137
7513 11:53:58.128391 308 : 4249, 3987
7514 11:53:58.128491 312 : 4250, 2145
7515 11:53:58.131874 316 : 4249, 22
7516 11:53:58.131980
7517 11:53:58.132073 MIOCK jitter meter ch=0
7518 11:53:58.134864
7519 11:53:58.134970 1T = (316-88) = 228 dly cells
7520 11:53:58.141727 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7521 11:53:58.141833 ==
7522 11:53:58.144974 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 11:53:58.148060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 11:53:58.148143 ==
7525 11:53:58.154884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 11:53:58.158083 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 11:53:58.164745 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 11:53:58.168349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 11:53:58.178575 [CA 0] Center 42 (12~73) winsize 62
7530 11:53:58.181797 [CA 1] Center 42 (12~73) winsize 62
7531 11:53:58.185048 [CA 2] Center 37 (8~67) winsize 60
7532 11:53:58.188086 [CA 3] Center 37 (7~67) winsize 61
7533 11:53:58.191812 [CA 4] Center 36 (6~66) winsize 61
7534 11:53:58.194947 [CA 5] Center 35 (6~64) winsize 59
7535 11:53:58.195049
7536 11:53:58.198323 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 11:53:58.198399
7538 11:53:58.201836 [CATrainingPosCal] consider 1 rank data
7539 11:53:58.204585 u2DelayCellTimex100 = 285/100 ps
7540 11:53:58.208090 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7541 11:53:58.215474 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7542 11:53:58.218087 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7543 11:53:58.221295 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7544 11:53:58.224681 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7545 11:53:58.228728 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7546 11:53:58.228832
7547 11:53:58.231878 CA PerBit enable=1, Macro0, CA PI delay=35
7548 11:53:58.231977
7549 11:53:58.234832 [CBTSetCACLKResult] CA Dly = 35
7550 11:53:58.234934 CS Dly: 9 (0~40)
7551 11:53:58.241650 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 11:53:58.244672 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 11:53:58.244777 ==
7554 11:53:58.248016 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 11:53:58.251676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 11:53:58.251777 ==
7557 11:53:58.258080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 11:53:58.261765 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 11:53:58.268402 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 11:53:58.271365 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 11:53:58.281752 [CA 0] Center 42 (12~73) winsize 62
7562 11:53:58.284554 [CA 1] Center 42 (12~73) winsize 62
7563 11:53:58.288196 [CA 2] Center 37 (8~67) winsize 60
7564 11:53:58.291280 [CA 3] Center 38 (8~68) winsize 61
7565 11:53:58.294964 [CA 4] Center 35 (6~65) winsize 60
7566 11:53:58.298174 [CA 5] Center 35 (5~65) winsize 61
7567 11:53:58.298251
7568 11:53:58.301332 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7569 11:53:58.301431
7570 11:53:58.304845 [CATrainingPosCal] consider 2 rank data
7571 11:53:58.307925 u2DelayCellTimex100 = 285/100 ps
7572 11:53:58.311655 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7573 11:53:58.318134 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7574 11:53:58.321543 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7575 11:53:58.324806 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7576 11:53:58.327988 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7577 11:53:58.331640 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7578 11:53:58.331743
7579 11:53:58.334739 CA PerBit enable=1, Macro0, CA PI delay=35
7580 11:53:58.334820
7581 11:53:58.338502 [CBTSetCACLKResult] CA Dly = 35
7582 11:53:58.341789 CS Dly: 10 (0~42)
7583 11:53:58.345138 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 11:53:58.348052 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 11:53:58.348153
7586 11:53:58.351223 ----->DramcWriteLeveling(PI) begin...
7587 11:53:58.351320 ==
7588 11:53:58.354954 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 11:53:58.358207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 11:53:58.361455 ==
7591 11:53:58.361555 Write leveling (Byte 0): 35 => 35
7592 11:53:58.364750 Write leveling (Byte 1): 27 => 27
7593 11:53:58.367979 DramcWriteLeveling(PI) end<-----
7594 11:53:58.368082
7595 11:53:58.368172 ==
7596 11:53:58.370936 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 11:53:58.378046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 11:53:58.378126 ==
7599 11:53:58.381066 [Gating] SW mode calibration
7600 11:53:58.387608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 11:53:58.390990 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 11:53:58.397502 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7603 11:53:58.400768 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7604 11:53:58.404518 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7605 11:53:58.410958 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7606 11:53:58.414170 1 4 16 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
7607 11:53:58.417769 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7608 11:53:58.423985 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7609 11:53:58.427691 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 11:53:58.430809 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7611 11:53:58.434219 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7612 11:53:58.441115 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7613 11:53:58.444060 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7614 11:53:58.447394 1 5 16 | B1->B0 | 3434 3231 | 1 1 | (1 0) (0 0)
7615 11:53:58.454260 1 5 20 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
7616 11:53:58.457404 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7617 11:53:58.460668 1 5 28 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7618 11:53:58.467395 1 6 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7619 11:53:58.470999 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7620 11:53:58.474135 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7621 11:53:58.481083 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7622 11:53:58.484273 1 6 16 | B1->B0 | 3131 4645 | 0 1 | (1 1) (0 0)
7623 11:53:58.487780 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7624 11:53:58.494281 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 11:53:58.497342 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 11:53:58.500993 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 11:53:58.507528 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 11:53:58.510703 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 11:53:58.514079 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 11:53:58.520703 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 11:53:58.523791 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 11:53:58.527577 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 11:53:58.533931 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 11:53:58.537178 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 11:53:58.541237 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 11:53:58.543780 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 11:53:58.550989 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 11:53:58.553810 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 11:53:58.557030 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 11:53:58.563907 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 11:53:58.567251 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 11:53:58.570471 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 11:53:58.577305 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:53:58.580793 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 11:53:58.583953 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 11:53:58.590334 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 11:53:58.593820 Total UI for P1: 0, mck2ui 16
7648 11:53:58.597361 best dqsien dly found for B0: ( 1, 9, 10)
7649 11:53:58.600659 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 11:53:58.603632 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 11:53:58.607365 Total UI for P1: 0, mck2ui 16
7652 11:53:58.610509 best dqsien dly found for B1: ( 1, 9, 18)
7653 11:53:58.614155 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7654 11:53:58.617445 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7655 11:53:58.617552
7656 11:53:58.624173 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7657 11:53:58.627236 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7658 11:53:58.630826 [Gating] SW calibration Done
7659 11:53:58.630908 ==
7660 11:53:58.633807 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 11:53:58.636986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 11:53:58.637068 ==
7663 11:53:58.637132 RX Vref Scan: 0
7664 11:53:58.637193
7665 11:53:58.640386 RX Vref 0 -> 0, step: 1
7666 11:53:58.640467
7667 11:53:58.643809 RX Delay 0 -> 252, step: 8
7668 11:53:58.646841 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7669 11:53:58.650044 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7670 11:53:58.656691 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7671 11:53:58.659996 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7672 11:53:58.663979 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7673 11:53:58.667212 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7674 11:53:58.670207 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7675 11:53:58.673164 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7676 11:53:58.679994 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7677 11:53:58.683128 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7678 11:53:58.686809 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7679 11:53:58.689938 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7680 11:53:58.696457 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7681 11:53:58.699947 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7682 11:53:58.703419 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7683 11:53:58.706452 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7684 11:53:58.706557 ==
7685 11:53:58.709672 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 11:53:58.716333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 11:53:58.716438 ==
7688 11:53:58.716530 DQS Delay:
7689 11:53:58.716622 DQS0 = 0, DQS1 = 0
7690 11:53:58.719511 DQM Delay:
7691 11:53:58.719586 DQM0 = 137, DQM1 = 130
7692 11:53:58.723321 DQ Delay:
7693 11:53:58.726168 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7694 11:53:58.729804 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7695 11:53:58.732858 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7696 11:53:58.736001 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7697 11:53:58.736100
7698 11:53:58.736190
7699 11:53:58.736280 ==
7700 11:53:58.739648 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 11:53:58.742898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 11:53:58.746323 ==
7703 11:53:58.746396
7704 11:53:58.746478
7705 11:53:58.746567 TX Vref Scan disable
7706 11:53:58.749270 == TX Byte 0 ==
7707 11:53:58.752573 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7708 11:53:58.755829 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7709 11:53:58.759159 == TX Byte 1 ==
7710 11:53:58.762540 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7711 11:53:58.765948 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7712 11:53:58.769304 ==
7713 11:53:58.769409 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 11:53:58.775650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 11:53:58.775756 ==
7716 11:53:58.787982
7717 11:53:58.791360 TX Vref early break, caculate TX vref
7718 11:53:58.794489 TX Vref=16, minBit 7, minWin=22, winSum=378
7719 11:53:58.797366 TX Vref=18, minBit 0, minWin=23, winSum=387
7720 11:53:58.801133 TX Vref=20, minBit 0, minWin=24, winSum=400
7721 11:53:58.804323 TX Vref=22, minBit 0, minWin=24, winSum=407
7722 11:53:58.807391 TX Vref=24, minBit 0, minWin=25, winSum=413
7723 11:53:58.814534 TX Vref=26, minBit 2, minWin=25, winSum=424
7724 11:53:58.817741 TX Vref=28, minBit 6, minWin=25, winSum=426
7725 11:53:58.820892 TX Vref=30, minBit 1, minWin=24, winSum=413
7726 11:53:58.824460 TX Vref=32, minBit 0, minWin=24, winSum=401
7727 11:53:58.830894 [TxChooseVref] Worse bit 6, Min win 25, Win sum 426, Final Vref 28
7728 11:53:58.831000
7729 11:53:58.834392 Final TX Range 0 Vref 28
7730 11:53:58.834495
7731 11:53:58.834585 ==
7732 11:53:58.837303 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 11:53:58.840916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 11:53:58.841020 ==
7735 11:53:58.841114
7736 11:53:58.841209
7737 11:53:58.844137 TX Vref Scan disable
7738 11:53:58.847433 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7739 11:53:58.851149 == TX Byte 0 ==
7740 11:53:58.854282 u2DelayCellOfst[0]=10 cells (3 PI)
7741 11:53:58.857403 u2DelayCellOfst[1]=17 cells (5 PI)
7742 11:53:58.861002 u2DelayCellOfst[2]=10 cells (3 PI)
7743 11:53:58.864135 u2DelayCellOfst[3]=10 cells (3 PI)
7744 11:53:58.867305 u2DelayCellOfst[4]=6 cells (2 PI)
7745 11:53:58.867386 u2DelayCellOfst[5]=0 cells (0 PI)
7746 11:53:58.871317 u2DelayCellOfst[6]=17 cells (5 PI)
7747 11:53:58.874307 u2DelayCellOfst[7]=17 cells (5 PI)
7748 11:53:58.880919 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7749 11:53:58.884072 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7750 11:53:58.884153 == TX Byte 1 ==
7751 11:53:58.887394 u2DelayCellOfst[8]=0 cells (0 PI)
7752 11:53:58.891015 u2DelayCellOfst[9]=0 cells (0 PI)
7753 11:53:58.894302 u2DelayCellOfst[10]=6 cells (2 PI)
7754 11:53:58.897373 u2DelayCellOfst[11]=3 cells (1 PI)
7755 11:53:58.900744 u2DelayCellOfst[12]=13 cells (4 PI)
7756 11:53:58.904079 u2DelayCellOfst[13]=10 cells (3 PI)
7757 11:53:58.907295 u2DelayCellOfst[14]=17 cells (5 PI)
7758 11:53:58.910669 u2DelayCellOfst[15]=13 cells (4 PI)
7759 11:53:58.913824 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7760 11:53:58.917340 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7761 11:53:58.921020 DramC Write-DBI on
7762 11:53:58.921094 ==
7763 11:53:58.924001 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 11:53:58.927042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 11:53:58.927145 ==
7766 11:53:58.927236
7767 11:53:58.927360
7768 11:53:58.930879 TX Vref Scan disable
7769 11:53:58.934099 == TX Byte 0 ==
7770 11:53:58.937525 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7771 11:53:58.940301 == TX Byte 1 ==
7772 11:53:58.944011 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7773 11:53:58.944102 DramC Write-DBI off
7774 11:53:58.944165
7775 11:53:58.946850 [DATLAT]
7776 11:53:58.946933 Freq=1600, CH0 RK0
7777 11:53:58.946994
7778 11:53:58.950464 DATLAT Default: 0xf
7779 11:53:58.950533 0, 0xFFFF, sum = 0
7780 11:53:58.953743 1, 0xFFFF, sum = 0
7781 11:53:58.953855 2, 0xFFFF, sum = 0
7782 11:53:58.956904 3, 0xFFFF, sum = 0
7783 11:53:58.956978 4, 0xFFFF, sum = 0
7784 11:53:58.960669 5, 0xFFFF, sum = 0
7785 11:53:58.960767 6, 0xFFFF, sum = 0
7786 11:53:58.963908 7, 0xFFFF, sum = 0
7787 11:53:58.964002 8, 0xFFFF, sum = 0
7788 11:53:58.966973 9, 0xFFFF, sum = 0
7789 11:53:58.970056 10, 0xFFFF, sum = 0
7790 11:53:58.970152 11, 0xFFFF, sum = 0
7791 11:53:58.973518 12, 0xFFFF, sum = 0
7792 11:53:58.973650 13, 0xFFFF, sum = 0
7793 11:53:58.976940 14, 0x0, sum = 1
7794 11:53:58.977044 15, 0x0, sum = 2
7795 11:53:58.980113 16, 0x0, sum = 3
7796 11:53:58.980220 17, 0x0, sum = 4
7797 11:53:58.983288 best_step = 15
7798 11:53:58.983369
7799 11:53:58.983461 ==
7800 11:53:58.986792 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 11:53:58.989754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 11:53:58.989840 ==
7803 11:53:58.989930 RX Vref Scan: 1
7804 11:53:58.989998
7805 11:53:58.993350 Set Vref Range= 24 -> 127
7806 11:53:58.993451
7807 11:53:58.996890 RX Vref 24 -> 127, step: 1
7808 11:53:58.996989
7809 11:53:59.000023 RX Delay 27 -> 252, step: 4
7810 11:53:59.000126
7811 11:53:59.003455 Set Vref, RX VrefLevel [Byte0]: 24
7812 11:53:59.006535 [Byte1]: 24
7813 11:53:59.006631
7814 11:53:59.009851 Set Vref, RX VrefLevel [Byte0]: 25
7815 11:53:59.013099 [Byte1]: 25
7816 11:53:59.013196
7817 11:53:59.016965 Set Vref, RX VrefLevel [Byte0]: 26
7818 11:53:59.020130 [Byte1]: 26
7819 11:53:59.023196
7820 11:53:59.023277 Set Vref, RX VrefLevel [Byte0]: 27
7821 11:53:59.026886 [Byte1]: 27
7822 11:53:59.030916
7823 11:53:59.030994 Set Vref, RX VrefLevel [Byte0]: 28
7824 11:53:59.034187 [Byte1]: 28
7825 11:53:59.038354
7826 11:53:59.038435 Set Vref, RX VrefLevel [Byte0]: 29
7827 11:53:59.041513 [Byte1]: 29
7828 11:53:59.045943
7829 11:53:59.046025 Set Vref, RX VrefLevel [Byte0]: 30
7830 11:53:59.050012 [Byte1]: 30
7831 11:53:59.053304
7832 11:53:59.053386 Set Vref, RX VrefLevel [Byte0]: 31
7833 11:53:59.056935 [Byte1]: 31
7834 11:53:59.061192
7835 11:53:59.061294 Set Vref, RX VrefLevel [Byte0]: 32
7836 11:53:59.064145 [Byte1]: 32
7837 11:53:59.068726
7838 11:53:59.068799 Set Vref, RX VrefLevel [Byte0]: 33
7839 11:53:59.072124 [Byte1]: 33
7840 11:53:59.076419
7841 11:53:59.076502 Set Vref, RX VrefLevel [Byte0]: 34
7842 11:53:59.079661 [Byte1]: 34
7843 11:53:59.084083
7844 11:53:59.084165 Set Vref, RX VrefLevel [Byte0]: 35
7845 11:53:59.086835 [Byte1]: 35
7846 11:53:59.091308
7847 11:53:59.091391 Set Vref, RX VrefLevel [Byte0]: 36
7848 11:53:59.094594 [Byte1]: 36
7849 11:53:59.098593
7850 11:53:59.098674 Set Vref, RX VrefLevel [Byte0]: 37
7851 11:53:59.102284 [Byte1]: 37
7852 11:53:59.106096
7853 11:53:59.106177 Set Vref, RX VrefLevel [Byte0]: 38
7854 11:53:59.109339 [Byte1]: 38
7855 11:53:59.113879
7856 11:53:59.113960 Set Vref, RX VrefLevel [Byte0]: 39
7857 11:53:59.117051 [Byte1]: 39
7858 11:53:59.121539
7859 11:53:59.121630 Set Vref, RX VrefLevel [Byte0]: 40
7860 11:53:59.124831 [Byte1]: 40
7861 11:53:59.129339
7862 11:53:59.129421 Set Vref, RX VrefLevel [Byte0]: 41
7863 11:53:59.132074 [Byte1]: 41
7864 11:53:59.136155
7865 11:53:59.136237 Set Vref, RX VrefLevel [Byte0]: 42
7866 11:53:59.139775 [Byte1]: 42
7867 11:53:59.144084
7868 11:53:59.144164 Set Vref, RX VrefLevel [Byte0]: 43
7869 11:53:59.147440 [Byte1]: 43
7870 11:53:59.151697
7871 11:53:59.151798 Set Vref, RX VrefLevel [Byte0]: 44
7872 11:53:59.154620 [Byte1]: 44
7873 11:53:59.158852
7874 11:53:59.158955 Set Vref, RX VrefLevel [Byte0]: 45
7875 11:53:59.162481 [Byte1]: 45
7876 11:53:59.166583
7877 11:53:59.166679 Set Vref, RX VrefLevel [Byte0]: 46
7878 11:53:59.169764 [Byte1]: 46
7879 11:53:59.173912
7880 11:53:59.173983 Set Vref, RX VrefLevel [Byte0]: 47
7881 11:53:59.177553 [Byte1]: 47
7882 11:53:59.181396
7883 11:53:59.181491 Set Vref, RX VrefLevel [Byte0]: 48
7884 11:53:59.184810 [Byte1]: 48
7885 11:53:59.188959
7886 11:53:59.189033 Set Vref, RX VrefLevel [Byte0]: 49
7887 11:53:59.192514 [Byte1]: 49
7888 11:53:59.196965
7889 11:53:59.197039 Set Vref, RX VrefLevel [Byte0]: 50
7890 11:53:59.199954 [Byte1]: 50
7891 11:53:59.204384
7892 11:53:59.204486 Set Vref, RX VrefLevel [Byte0]: 51
7893 11:53:59.207572 [Byte1]: 51
7894 11:53:59.211474
7895 11:53:59.211573 Set Vref, RX VrefLevel [Byte0]: 52
7896 11:53:59.215356 [Byte1]: 52
7897 11:53:59.219180
7898 11:53:59.219279 Set Vref, RX VrefLevel [Byte0]: 53
7899 11:53:59.222388 [Byte1]: 53
7900 11:53:59.226763
7901 11:53:59.226842 Set Vref, RX VrefLevel [Byte0]: 54
7902 11:53:59.230134 [Byte1]: 54
7903 11:53:59.234132
7904 11:53:59.234216 Set Vref, RX VrefLevel [Byte0]: 55
7905 11:53:59.237484 [Byte1]: 55
7906 11:53:59.241843
7907 11:53:59.241914 Set Vref, RX VrefLevel [Byte0]: 56
7908 11:53:59.244891 [Byte1]: 56
7909 11:53:59.249390
7910 11:53:59.249460 Set Vref, RX VrefLevel [Byte0]: 57
7911 11:53:59.252449 [Byte1]: 57
7912 11:53:59.257092
7913 11:53:59.257164 Set Vref, RX VrefLevel [Byte0]: 58
7914 11:53:59.260705 [Byte1]: 58
7915 11:53:59.264506
7916 11:53:59.264577 Set Vref, RX VrefLevel [Byte0]: 59
7917 11:53:59.267887 [Byte1]: 59
7918 11:53:59.272004
7919 11:53:59.272100 Set Vref, RX VrefLevel [Byte0]: 60
7920 11:53:59.275451 [Byte1]: 60
7921 11:53:59.280084
7922 11:53:59.280180 Set Vref, RX VrefLevel [Byte0]: 61
7923 11:53:59.282947 [Byte1]: 61
7924 11:53:59.286828
7925 11:53:59.286897 Set Vref, RX VrefLevel [Byte0]: 62
7926 11:53:59.290347 [Byte1]: 62
7927 11:53:59.294877
7928 11:53:59.294947 Set Vref, RX VrefLevel [Byte0]: 63
7929 11:53:59.298067 [Byte1]: 63
7930 11:53:59.302180
7931 11:53:59.302254 Set Vref, RX VrefLevel [Byte0]: 64
7932 11:53:59.305530 [Byte1]: 64
7933 11:53:59.310035
7934 11:53:59.310119 Set Vref, RX VrefLevel [Byte0]: 65
7935 11:53:59.313251 [Byte1]: 65
7936 11:53:59.316886
7937 11:53:59.316982 Set Vref, RX VrefLevel [Byte0]: 66
7938 11:53:59.320588 [Byte1]: 66
7939 11:53:59.324584
7940 11:53:59.324683 Set Vref, RX VrefLevel [Byte0]: 67
7941 11:53:59.327918 [Byte1]: 67
7942 11:53:59.332183
7943 11:53:59.332279 Set Vref, RX VrefLevel [Byte0]: 68
7944 11:53:59.335492 [Byte1]: 68
7945 11:53:59.339807
7946 11:53:59.339877 Set Vref, RX VrefLevel [Byte0]: 69
7947 11:53:59.343330 [Byte1]: 69
7948 11:53:59.347486
7949 11:53:59.347559 Set Vref, RX VrefLevel [Byte0]: 70
7950 11:53:59.350667 [Byte1]: 70
7951 11:53:59.354593
7952 11:53:59.354663 Set Vref, RX VrefLevel [Byte0]: 71
7953 11:53:59.358772 [Byte1]: 71
7954 11:53:59.362401
7955 11:53:59.362487 Set Vref, RX VrefLevel [Byte0]: 72
7956 11:53:59.369422 [Byte1]: 72
7957 11:53:59.369528
7958 11:53:59.372435 Set Vref, RX VrefLevel [Byte0]: 73
7959 11:53:59.375512 [Byte1]: 73
7960 11:53:59.375585
7961 11:53:59.378856 Final RX Vref Byte 0 = 57 to rank0
7962 11:53:59.382364 Final RX Vref Byte 1 = 63 to rank0
7963 11:53:59.385499 Final RX Vref Byte 0 = 57 to rank1
7964 11:53:59.388598 Final RX Vref Byte 1 = 63 to rank1==
7965 11:53:59.392618 Dram Type= 6, Freq= 0, CH_0, rank 0
7966 11:53:59.395685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 11:53:59.395766 ==
7968 11:53:59.399054 DQS Delay:
7969 11:53:59.399135 DQS0 = 0, DQS1 = 0
7970 11:53:59.399198 DQM Delay:
7971 11:53:59.402292 DQM0 = 133, DQM1 = 128
7972 11:53:59.402373 DQ Delay:
7973 11:53:59.405746 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7974 11:53:59.409037 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7975 11:53:59.411965 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
7976 11:53:59.418838 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7977 11:53:59.418919
7978 11:53:59.418982
7979 11:53:59.419041
7980 11:53:59.419097 [DramC_TX_OE_Calibration] TA2
7981 11:53:59.422293 Original DQ_B0 (3 6) =30, OEN = 27
7982 11:53:59.425881 Original DQ_B1 (3 6) =30, OEN = 27
7983 11:53:59.428668 24, 0x0, End_B0=24 End_B1=24
7984 11:53:59.432009 25, 0x0, End_B0=25 End_B1=25
7985 11:53:59.435348 26, 0x0, End_B0=26 End_B1=26
7986 11:53:59.435432 27, 0x0, End_B0=27 End_B1=27
7987 11:53:59.438646 28, 0x0, End_B0=28 End_B1=28
7988 11:53:59.442013 29, 0x0, End_B0=29 End_B1=29
7989 11:53:59.445337 30, 0x0, End_B0=30 End_B1=30
7990 11:53:59.449045 31, 0x4141, End_B0=30 End_B1=30
7991 11:53:59.452081 Byte0 end_step=30 best_step=27
7992 11:53:59.452166 Byte1 end_step=30 best_step=27
7993 11:53:59.455300 Byte0 TX OE(2T, 0.5T) = (3, 3)
7994 11:53:59.458530 Byte1 TX OE(2T, 0.5T) = (3, 3)
7995 11:53:59.458613
7996 11:53:59.458711
7997 11:53:59.468899 [DQSOSCAuto] RK0, (LSB)MR18= 0x231e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
7998 11:53:59.468985 CH0 RK0: MR19=303, MR18=231E
7999 11:53:59.475288 CH0_RK0: MR19=0x303, MR18=0x231E, DQSOSC=392, MR23=63, INC=24, DEC=16
8000 11:53:59.475376
8001 11:53:59.478930 ----->DramcWriteLeveling(PI) begin...
8002 11:53:59.479015 ==
8003 11:53:59.481943 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 11:53:59.489088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 11:53:59.489173 ==
8006 11:53:59.491958 Write leveling (Byte 0): 36 => 36
8007 11:53:59.492041 Write leveling (Byte 1): 28 => 28
8008 11:53:59.495728 DramcWriteLeveling(PI) end<-----
8009 11:53:59.495821
8010 11:53:59.495895 ==
8011 11:53:59.498893 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 11:53:59.505347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 11:53:59.505454 ==
8014 11:53:59.508420 [Gating] SW mode calibration
8015 11:53:59.515332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8016 11:53:59.518383 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8017 11:53:59.525364 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8018 11:53:59.528532 1 4 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8019 11:53:59.532131 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 11:53:59.538710 1 4 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
8021 11:53:59.542149 1 4 16 | B1->B0 | 2d2d 3737 | 1 1 | (1 1) (0 0)
8022 11:53:59.545170 1 4 20 | B1->B0 | 3434 3b3b | 1 0 | (1 1) (1 1)
8023 11:53:59.552170 1 4 24 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (1 1)
8024 11:53:59.554955 1 4 28 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8025 11:53:59.558627 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8026 11:53:59.565029 1 5 4 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (1 1)
8027 11:53:59.568309 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
8028 11:53:59.571913 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (0 1)
8029 11:53:59.574902 1 5 16 | B1->B0 | 2d2d 2c2b | 0 1 | (1 0) (1 0)
8030 11:53:59.581510 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8031 11:53:59.585055 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
8032 11:53:59.588362 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8033 11:53:59.594957 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8034 11:53:59.598427 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8035 11:53:59.601481 1 6 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8036 11:53:59.608383 1 6 12 | B1->B0 | 2525 3837 | 1 1 | (0 0) (0 0)
8037 11:53:59.611601 1 6 16 | B1->B0 | 3f3f 4645 | 1 1 | (0 0) (0 0)
8038 11:53:59.615111 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8039 11:53:59.621603 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 11:53:59.624853 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 11:53:59.628418 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 11:53:59.634752 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 11:53:59.637974 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 11:53:59.641565 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8045 11:53:59.648091 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8046 11:53:59.651299 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:53:59.654750 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:53:59.661597 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:53:59.664681 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:53:59.667655 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:53:59.674706 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:53:59.677607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:53:59.681408 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 11:53:59.687724 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 11:53:59.691143 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 11:53:59.694308 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 11:53:59.701438 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 11:53:59.704416 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 11:53:59.708003 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 11:53:59.714302 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8061 11:53:59.717973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 11:53:59.721102 Total UI for P1: 0, mck2ui 16
8063 11:53:59.724405 best dqsien dly found for B0: ( 1, 9, 12)
8064 11:53:59.727545 Total UI for P1: 0, mck2ui 16
8065 11:53:59.730751 best dqsien dly found for B1: ( 1, 9, 12)
8066 11:53:59.734459 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8067 11:53:59.737952 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8068 11:53:59.738035
8069 11:53:59.741118 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8070 11:53:59.744451 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8071 11:53:59.747851 [Gating] SW calibration Done
8072 11:53:59.747933 ==
8073 11:53:59.751354 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 11:53:59.754119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 11:53:59.754220 ==
8076 11:53:59.758032 RX Vref Scan: 0
8077 11:53:59.758114
8078 11:53:59.761265 RX Vref 0 -> 0, step: 1
8079 11:53:59.761347
8080 11:53:59.761411 RX Delay 0 -> 252, step: 8
8081 11:53:59.767513 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8082 11:53:59.770864 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8083 11:53:59.774147 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8084 11:53:59.777314 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8085 11:53:59.780643 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8086 11:53:59.787314 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8087 11:53:59.790831 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8088 11:53:59.793757 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8089 11:53:59.797184 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8090 11:53:59.800638 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8091 11:53:59.806961 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8092 11:53:59.810553 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8093 11:53:59.813857 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8094 11:53:59.817285 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8095 11:53:59.820308 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8096 11:53:59.827255 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8097 11:53:59.827338 ==
8098 11:53:59.830746 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 11:53:59.833958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 11:53:59.834041 ==
8101 11:53:59.834106 DQS Delay:
8102 11:53:59.837202 DQS0 = 0, DQS1 = 0
8103 11:53:59.837283 DQM Delay:
8104 11:53:59.840931 DQM0 = 137, DQM1 = 129
8105 11:53:59.841012 DQ Delay:
8106 11:53:59.843863 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8107 11:53:59.847598 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8108 11:53:59.851149 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
8109 11:53:59.854081 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8110 11:53:59.854157
8111 11:53:59.857123
8112 11:53:59.857192 ==
8113 11:53:59.860707 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 11:53:59.863948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 11:53:59.864029 ==
8116 11:53:59.864092
8117 11:53:59.864151
8118 11:53:59.867436 TX Vref Scan disable
8119 11:53:59.867516 == TX Byte 0 ==
8120 11:53:59.873988 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8121 11:53:59.877287 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8122 11:53:59.877369 == TX Byte 1 ==
8123 11:53:59.883685 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8124 11:53:59.886923 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8125 11:53:59.887004 ==
8126 11:53:59.890080 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 11:53:59.893824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 11:53:59.893906 ==
8129 11:53:59.908326
8130 11:53:59.911155 TX Vref early break, caculate TX vref
8131 11:53:59.914917 TX Vref=16, minBit 0, minWin=22, winSum=382
8132 11:53:59.917809 TX Vref=18, minBit 1, minWin=23, winSum=398
8133 11:53:59.921488 TX Vref=20, minBit 7, minWin=24, winSum=409
8134 11:53:59.924624 TX Vref=22, minBit 1, minWin=25, winSum=416
8135 11:53:59.928096 TX Vref=24, minBit 1, minWin=24, winSum=419
8136 11:53:59.934354 TX Vref=26, minBit 1, minWin=25, winSum=430
8137 11:53:59.937912 TX Vref=28, minBit 0, minWin=25, winSum=420
8138 11:53:59.941307 TX Vref=30, minBit 2, minWin=24, winSum=416
8139 11:53:59.944638 TX Vref=32, minBit 1, minWin=24, winSum=409
8140 11:53:59.947871 TX Vref=34, minBit 1, minWin=24, winSum=401
8141 11:53:59.954510 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8142 11:53:59.954594
8143 11:53:59.957596 Final TX Range 0 Vref 26
8144 11:53:59.957676
8145 11:53:59.957739 ==
8146 11:53:59.961499 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 11:53:59.964704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 11:53:59.964786 ==
8149 11:53:59.964851
8150 11:53:59.964910
8151 11:53:59.967710 TX Vref Scan disable
8152 11:53:59.974809 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8153 11:53:59.974892 == TX Byte 0 ==
8154 11:53:59.977870 u2DelayCellOfst[0]=10 cells (3 PI)
8155 11:53:59.980849 u2DelayCellOfst[1]=17 cells (5 PI)
8156 11:53:59.984784 u2DelayCellOfst[2]=10 cells (3 PI)
8157 11:53:59.987502 u2DelayCellOfst[3]=10 cells (3 PI)
8158 11:53:59.991296 u2DelayCellOfst[4]=6 cells (2 PI)
8159 11:53:59.994502 u2DelayCellOfst[5]=0 cells (0 PI)
8160 11:53:59.997890 u2DelayCellOfst[6]=13 cells (4 PI)
8161 11:53:59.997972 u2DelayCellOfst[7]=13 cells (4 PI)
8162 11:54:00.004594 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8163 11:54:00.007765 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8164 11:54:00.007847 == TX Byte 1 ==
8165 11:54:00.010969 u2DelayCellOfst[8]=3 cells (1 PI)
8166 11:54:00.014799 u2DelayCellOfst[9]=0 cells (0 PI)
8167 11:54:00.018115 u2DelayCellOfst[10]=6 cells (2 PI)
8168 11:54:00.021074 u2DelayCellOfst[11]=3 cells (1 PI)
8169 11:54:00.024263 u2DelayCellOfst[12]=10 cells (3 PI)
8170 11:54:00.027439 u2DelayCellOfst[13]=10 cells (3 PI)
8171 11:54:00.031262 u2DelayCellOfst[14]=13 cells (4 PI)
8172 11:54:00.034190 u2DelayCellOfst[15]=10 cells (3 PI)
8173 11:54:00.037695 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8174 11:54:00.044022 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8175 11:54:00.044105 DramC Write-DBI on
8176 11:54:00.044170 ==
8177 11:54:00.047667 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 11:54:00.050906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 11:54:00.054368 ==
8180 11:54:00.054450
8181 11:54:00.054514
8182 11:54:00.054573 TX Vref Scan disable
8183 11:54:00.057526 == TX Byte 0 ==
8184 11:54:00.060802 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8185 11:54:00.064167 == TX Byte 1 ==
8186 11:54:00.067504 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8187 11:54:00.067587 DramC Write-DBI off
8188 11:54:00.071015
8189 11:54:00.071123 [DATLAT]
8190 11:54:00.071216 Freq=1600, CH0 RK1
8191 11:54:00.071305
8192 11:54:00.074459 DATLAT Default: 0xf
8193 11:54:00.074542 0, 0xFFFF, sum = 0
8194 11:54:00.077735 1, 0xFFFF, sum = 0
8195 11:54:00.077818 2, 0xFFFF, sum = 0
8196 11:54:00.080815 3, 0xFFFF, sum = 0
8197 11:54:00.084515 4, 0xFFFF, sum = 0
8198 11:54:00.084599 5, 0xFFFF, sum = 0
8199 11:54:00.087540 6, 0xFFFF, sum = 0
8200 11:54:00.087623 7, 0xFFFF, sum = 0
8201 11:54:00.091257 8, 0xFFFF, sum = 0
8202 11:54:00.091367 9, 0xFFFF, sum = 0
8203 11:54:00.094608 10, 0xFFFF, sum = 0
8204 11:54:00.094691 11, 0xFFFF, sum = 0
8205 11:54:00.097513 12, 0xFFFF, sum = 0
8206 11:54:00.097623 13, 0xFFFF, sum = 0
8207 11:54:00.100796 14, 0x0, sum = 1
8208 11:54:00.100879 15, 0x0, sum = 2
8209 11:54:00.103964 16, 0x0, sum = 3
8210 11:54:00.104047 17, 0x0, sum = 4
8211 11:54:00.107712 best_step = 15
8212 11:54:00.107793
8213 11:54:00.107857 ==
8214 11:54:00.110731 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 11:54:00.114082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 11:54:00.114165 ==
8217 11:54:00.114231 RX Vref Scan: 0
8218 11:54:00.117457
8219 11:54:00.117538 RX Vref 0 -> 0, step: 1
8220 11:54:00.117614
8221 11:54:00.121051 RX Delay 19 -> 252, step: 4
8222 11:54:00.124242 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8223 11:54:00.131203 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8224 11:54:00.134398 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8225 11:54:00.137554 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8226 11:54:00.140808 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8227 11:54:00.144078 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8228 11:54:00.150754 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8229 11:54:00.154000 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8230 11:54:00.157262 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8231 11:54:00.160901 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8232 11:54:00.163907 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8233 11:54:00.170887 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8234 11:54:00.173497 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8235 11:54:00.176874 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8236 11:54:00.180758 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8237 11:54:00.184126 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8238 11:54:00.187162 ==
8239 11:54:00.187244 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 11:54:00.193690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 11:54:00.193774 ==
8242 11:54:00.193838 DQS Delay:
8243 11:54:00.197444 DQS0 = 0, DQS1 = 0
8244 11:54:00.197526 DQM Delay:
8245 11:54:00.200436 DQM0 = 134, DQM1 = 127
8246 11:54:00.200518 DQ Delay:
8247 11:54:00.203889 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8248 11:54:00.207019 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8249 11:54:00.210081 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8250 11:54:00.213818 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8251 11:54:00.213900
8252 11:54:00.213964
8253 11:54:00.214024
8254 11:54:00.216976 [DramC_TX_OE_Calibration] TA2
8255 11:54:00.220244 Original DQ_B0 (3 6) =30, OEN = 27
8256 11:54:00.223352 Original DQ_B1 (3 6) =30, OEN = 27
8257 11:54:00.227006 24, 0x0, End_B0=24 End_B1=24
8258 11:54:00.230430 25, 0x0, End_B0=25 End_B1=25
8259 11:54:00.230535 26, 0x0, End_B0=26 End_B1=26
8260 11:54:00.233562 27, 0x0, End_B0=27 End_B1=27
8261 11:54:00.236650 28, 0x0, End_B0=28 End_B1=28
8262 11:54:00.240395 29, 0x0, End_B0=29 End_B1=29
8263 11:54:00.240492 30, 0x0, End_B0=30 End_B1=30
8264 11:54:00.243890 31, 0x4141, End_B0=30 End_B1=30
8265 11:54:00.246683 Byte0 end_step=30 best_step=27
8266 11:54:00.250052 Byte1 end_step=30 best_step=27
8267 11:54:00.253514 Byte0 TX OE(2T, 0.5T) = (3, 3)
8268 11:54:00.257017 Byte1 TX OE(2T, 0.5T) = (3, 3)
8269 11:54:00.257112
8270 11:54:00.257187
8271 11:54:00.264003 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8272 11:54:00.267003 CH0 RK1: MR19=303, MR18=1F07
8273 11:54:00.273712 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8274 11:54:00.276757 [RxdqsGatingPostProcess] freq 1600
8275 11:54:00.283572 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8276 11:54:00.283701 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 11:54:00.286726 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 11:54:00.290636 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 11:54:00.293234 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 11:54:00.296615 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 11:54:00.300453 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 11:54:00.303549 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 11:54:00.306800 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 11:54:00.310304 Pre-setting of DQS Precalculation
8285 11:54:00.313313 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8286 11:54:00.313736 ==
8287 11:54:00.316605 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 11:54:00.323712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 11:54:00.324177 ==
8290 11:54:00.327057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8291 11:54:00.333508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8292 11:54:00.336946 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8293 11:54:00.343538 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8294 11:54:00.351287 [CA 0] Center 42 (13~72) winsize 60
8295 11:54:00.354017 [CA 1] Center 42 (13~72) winsize 60
8296 11:54:00.357986 [CA 2] Center 39 (10~68) winsize 59
8297 11:54:00.360795 [CA 3] Center 38 (9~67) winsize 59
8298 11:54:00.364223 [CA 4] Center 38 (9~68) winsize 60
8299 11:54:00.368163 [CA 5] Center 37 (8~67) winsize 60
8300 11:54:00.368547
8301 11:54:00.371074 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8302 11:54:00.371457
8303 11:54:00.374273 [CATrainingPosCal] consider 1 rank data
8304 11:54:00.377337 u2DelayCellTimex100 = 285/100 ps
8305 11:54:00.380847 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8306 11:54:00.387493 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8307 11:54:00.390840 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8308 11:54:00.394090 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8309 11:54:00.397682 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8310 11:54:00.400813 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8311 11:54:00.401209
8312 11:54:00.404479 CA PerBit enable=1, Macro0, CA PI delay=37
8313 11:54:00.404998
8314 11:54:00.407614 [CBTSetCACLKResult] CA Dly = 37
8315 11:54:00.411208 CS Dly: 11 (0~42)
8316 11:54:00.414299 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8317 11:54:00.417521 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8318 11:54:00.417943 ==
8319 11:54:00.420914 Dram Type= 6, Freq= 0, CH_1, rank 1
8320 11:54:00.424313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 11:54:00.427549 ==
8322 11:54:00.430905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 11:54:00.434286 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 11:54:00.440853 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 11:54:00.444120 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 11:54:00.453968 [CA 0] Center 41 (12~71) winsize 60
8327 11:54:00.457340 [CA 1] Center 42 (12~72) winsize 61
8328 11:54:00.460551 [CA 2] Center 38 (9~68) winsize 60
8329 11:54:00.463796 [CA 3] Center 38 (8~68) winsize 61
8330 11:54:00.467229 [CA 4] Center 38 (8~68) winsize 61
8331 11:54:00.470394 [CA 5] Center 37 (8~67) winsize 60
8332 11:54:00.470498
8333 11:54:00.473776 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8334 11:54:00.473870
8335 11:54:00.477777 [CATrainingPosCal] consider 2 rank data
8336 11:54:00.480563 u2DelayCellTimex100 = 285/100 ps
8337 11:54:00.483648 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8338 11:54:00.490807 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8339 11:54:00.493517 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8340 11:54:00.496943 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8341 11:54:00.500241 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8342 11:54:00.503986 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8343 11:54:00.504071
8344 11:54:00.506703 CA PerBit enable=1, Macro0, CA PI delay=37
8345 11:54:00.506787
8346 11:54:00.510270 [CBTSetCACLKResult] CA Dly = 37
8347 11:54:00.513474 CS Dly: 12 (0~45)
8348 11:54:00.516990 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 11:54:00.520316 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 11:54:00.520398
8351 11:54:00.523852 ----->DramcWriteLeveling(PI) begin...
8352 11:54:00.523941 ==
8353 11:54:00.527020 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 11:54:00.533536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 11:54:00.533652 ==
8356 11:54:00.536927 Write leveling (Byte 0): 27 => 27
8357 11:54:00.537039 Write leveling (Byte 1): 27 => 27
8358 11:54:00.540418 DramcWriteLeveling(PI) end<-----
8359 11:54:00.540535
8360 11:54:00.543345 ==
8361 11:54:00.543467 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 11:54:00.550076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 11:54:00.550212 ==
8364 11:54:00.553166 [Gating] SW mode calibration
8365 11:54:00.560297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8366 11:54:00.563288 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8367 11:54:00.570443 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 11:54:00.573335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 11:54:00.577219 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8370 11:54:00.583632 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8371 11:54:00.587111 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 11:54:00.590331 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 11:54:00.597194 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 11:54:00.600168 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 11:54:00.603704 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 11:54:00.610704 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 11:54:00.613694 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8378 11:54:00.617129 1 5 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
8379 11:54:00.620111 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:54:00.626831 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 11:54:00.630477 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 11:54:00.633439 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 11:54:00.639873 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 11:54:00.643286 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 11:54:00.646801 1 6 8 | B1->B0 | 2c2c 3f3f | 0 1 | (0 0) (0 0)
8386 11:54:00.653043 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8387 11:54:00.656859 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:54:00.660120 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:54:00.666998 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 11:54:00.670048 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 11:54:00.673314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 11:54:00.680055 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 11:54:00.683017 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 11:54:00.686587 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 11:54:00.692915 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:54:00.696819 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:54:00.700109 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:54:00.706395 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:54:00.710130 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:54:00.712970 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:54:00.719454 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:54:00.723255 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:54:00.726305 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:54:00.732931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:54:00.735951 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 11:54:00.739729 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 11:54:00.742962 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:54:00.749261 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:54:00.752993 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 11:54:00.756049 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8411 11:54:00.762512 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 11:54:00.766543 Total UI for P1: 0, mck2ui 16
8413 11:54:00.769529 best dqsien dly found for B0: ( 1, 9, 10)
8414 11:54:00.772759 Total UI for P1: 0, mck2ui 16
8415 11:54:00.775959 best dqsien dly found for B1: ( 1, 9, 10)
8416 11:54:00.779634 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8417 11:54:00.782543 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8418 11:54:00.782621
8419 11:54:00.785935 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8420 11:54:00.789315 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8421 11:54:00.792671 [Gating] SW calibration Done
8422 11:54:00.792755 ==
8423 11:54:00.796555 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 11:54:00.799128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 11:54:00.799213 ==
8426 11:54:00.802889 RX Vref Scan: 0
8427 11:54:00.803005
8428 11:54:00.806207 RX Vref 0 -> 0, step: 1
8429 11:54:00.806316
8430 11:54:00.806401 RX Delay 0 -> 252, step: 8
8431 11:54:00.812370 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8432 11:54:00.816105 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8433 11:54:00.819124 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8434 11:54:00.822394 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8435 11:54:00.825518 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8436 11:54:00.832184 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8437 11:54:00.835741 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8438 11:54:00.839107 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8439 11:54:00.842328 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8440 11:54:00.845856 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8441 11:54:00.849084 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8442 11:54:00.855571 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8443 11:54:00.859138 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8444 11:54:00.862378 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8445 11:54:00.865700 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8446 11:54:00.872433 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8447 11:54:00.872515 ==
8448 11:54:00.875763 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 11:54:00.878842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 11:54:00.878925 ==
8451 11:54:00.878990 DQS Delay:
8452 11:54:00.882179 DQS0 = 0, DQS1 = 0
8453 11:54:00.882264 DQM Delay:
8454 11:54:00.885337 DQM0 = 136, DQM1 = 133
8455 11:54:00.885418 DQ Delay:
8456 11:54:00.889000 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8457 11:54:00.892191 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8458 11:54:00.895750 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8459 11:54:00.898838 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8460 11:54:00.898921
8461 11:54:00.898984
8462 11:54:00.902138 ==
8463 11:54:00.902220 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 11:54:00.908737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 11:54:00.908819 ==
8466 11:54:00.908885
8467 11:54:00.908944
8468 11:54:00.912117 TX Vref Scan disable
8469 11:54:00.912199 == TX Byte 0 ==
8470 11:54:00.915688 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8471 11:54:00.921950 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8472 11:54:00.922033 == TX Byte 1 ==
8473 11:54:00.925213 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8474 11:54:00.931869 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8475 11:54:00.931952 ==
8476 11:54:00.935438 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 11:54:00.938642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 11:54:00.938725 ==
8479 11:54:00.951641
8480 11:54:00.954544 TX Vref early break, caculate TX vref
8481 11:54:00.958118 TX Vref=16, minBit 9, minWin=22, winSum=376
8482 11:54:00.960964 TX Vref=18, minBit 1, minWin=23, winSum=389
8483 11:54:00.964720 TX Vref=20, minBit 6, minWin=23, winSum=397
8484 11:54:00.967898 TX Vref=22, minBit 0, minWin=24, winSum=408
8485 11:54:00.971120 TX Vref=24, minBit 1, minWin=25, winSum=416
8486 11:54:00.977865 TX Vref=26, minBit 1, minWin=25, winSum=425
8487 11:54:00.981055 TX Vref=28, minBit 0, minWin=25, winSum=425
8488 11:54:00.984359 TX Vref=30, minBit 6, minWin=24, winSum=416
8489 11:54:00.987617 TX Vref=32, minBit 6, minWin=24, winSum=412
8490 11:54:00.990999 TX Vref=34, minBit 0, minWin=23, winSum=402
8491 11:54:00.997925 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8492 11:54:00.998009
8493 11:54:01.001270 Final TX Range 0 Vref 26
8494 11:54:01.001353
8495 11:54:01.001418 ==
8496 11:54:01.004459 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 11:54:01.007584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 11:54:01.007667 ==
8499 11:54:01.007732
8500 11:54:01.007791
8501 11:54:01.011284 TX Vref Scan disable
8502 11:54:01.018168 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8503 11:54:01.018246 == TX Byte 0 ==
8504 11:54:01.020986 u2DelayCellOfst[0]=20 cells (6 PI)
8505 11:54:01.024404 u2DelayCellOfst[1]=13 cells (4 PI)
8506 11:54:01.027617 u2DelayCellOfst[2]=0 cells (0 PI)
8507 11:54:01.031280 u2DelayCellOfst[3]=10 cells (3 PI)
8508 11:54:01.034575 u2DelayCellOfst[4]=10 cells (3 PI)
8509 11:54:01.037678 u2DelayCellOfst[5]=20 cells (6 PI)
8510 11:54:01.040895 u2DelayCellOfst[6]=20 cells (6 PI)
8511 11:54:01.040980 u2DelayCellOfst[7]=10 cells (3 PI)
8512 11:54:01.047935 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8513 11:54:01.051448 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8514 11:54:01.051529 == TX Byte 1 ==
8515 11:54:01.054181 u2DelayCellOfst[8]=0 cells (0 PI)
8516 11:54:01.057825 u2DelayCellOfst[9]=3 cells (1 PI)
8517 11:54:01.061039 u2DelayCellOfst[10]=13 cells (4 PI)
8518 11:54:01.064352 u2DelayCellOfst[11]=6 cells (2 PI)
8519 11:54:01.067787 u2DelayCellOfst[12]=13 cells (4 PI)
8520 11:54:01.070952 u2DelayCellOfst[13]=13 cells (4 PI)
8521 11:54:01.074054 u2DelayCellOfst[14]=17 cells (5 PI)
8522 11:54:01.077931 u2DelayCellOfst[15]=17 cells (5 PI)
8523 11:54:01.080991 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8524 11:54:01.087914 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8525 11:54:01.088021 DramC Write-DBI on
8526 11:54:01.088121 ==
8527 11:54:01.091077 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 11:54:01.094625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 11:54:01.094714 ==
8530 11:54:01.097526
8531 11:54:01.097640
8532 11:54:01.097703 TX Vref Scan disable
8533 11:54:01.100681 == TX Byte 0 ==
8534 11:54:01.104617 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8535 11:54:01.107671 == TX Byte 1 ==
8536 11:54:01.110736 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8537 11:54:01.110839 DramC Write-DBI off
8538 11:54:01.110927
8539 11:54:01.114444 [DATLAT]
8540 11:54:01.114541 Freq=1600, CH1 RK0
8541 11:54:01.114628
8542 11:54:01.117748 DATLAT Default: 0xf
8543 11:54:01.117818 0, 0xFFFF, sum = 0
8544 11:54:01.120947 1, 0xFFFF, sum = 0
8545 11:54:01.121017 2, 0xFFFF, sum = 0
8546 11:54:01.124074 3, 0xFFFF, sum = 0
8547 11:54:01.124175 4, 0xFFFF, sum = 0
8548 11:54:01.127832 5, 0xFFFF, sum = 0
8549 11:54:01.127902 6, 0xFFFF, sum = 0
8550 11:54:01.130947 7, 0xFFFF, sum = 0
8551 11:54:01.134282 8, 0xFFFF, sum = 0
8552 11:54:01.134383 9, 0xFFFF, sum = 0
8553 11:54:01.137753 10, 0xFFFF, sum = 0
8554 11:54:01.137870 11, 0xFFFF, sum = 0
8555 11:54:01.141037 12, 0xFFFF, sum = 0
8556 11:54:01.141115 13, 0xFFFF, sum = 0
8557 11:54:01.144752 14, 0x0, sum = 1
8558 11:54:01.144832 15, 0x0, sum = 2
8559 11:54:01.147627 16, 0x0, sum = 3
8560 11:54:01.147712 17, 0x0, sum = 4
8561 11:54:01.147798 best_step = 15
8562 11:54:01.150781
8563 11:54:01.150864 ==
8564 11:54:01.154017 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 11:54:01.157613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 11:54:01.157698 ==
8567 11:54:01.157782 RX Vref Scan: 1
8568 11:54:01.157862
8569 11:54:01.160646 Set Vref Range= 24 -> 127
8570 11:54:01.160729
8571 11:54:01.164317 RX Vref 24 -> 127, step: 1
8572 11:54:01.164416
8573 11:54:01.167580 RX Delay 27 -> 252, step: 4
8574 11:54:01.167665
8575 11:54:01.170840 Set Vref, RX VrefLevel [Byte0]: 24
8576 11:54:01.173964 [Byte1]: 24
8577 11:54:01.174048
8578 11:54:01.177596 Set Vref, RX VrefLevel [Byte0]: 25
8579 11:54:01.180816 [Byte1]: 25
8580 11:54:01.180895
8581 11:54:01.184464 Set Vref, RX VrefLevel [Byte0]: 26
8582 11:54:01.187691 [Byte1]: 26
8583 11:54:01.191318
8584 11:54:01.191406 Set Vref, RX VrefLevel [Byte0]: 27
8585 11:54:01.194396 [Byte1]: 27
8586 11:54:01.198277
8587 11:54:01.198354 Set Vref, RX VrefLevel [Byte0]: 28
8588 11:54:01.201812 [Byte1]: 28
8589 11:54:01.206099
8590 11:54:01.206175 Set Vref, RX VrefLevel [Byte0]: 29
8591 11:54:01.209306 [Byte1]: 29
8592 11:54:01.213787
8593 11:54:01.213893 Set Vref, RX VrefLevel [Byte0]: 30
8594 11:54:01.216755 [Byte1]: 30
8595 11:54:01.221322
8596 11:54:01.221420 Set Vref, RX VrefLevel [Byte0]: 31
8597 11:54:01.224455 [Byte1]: 31
8598 11:54:01.228935
8599 11:54:01.229007 Set Vref, RX VrefLevel [Byte0]: 32
8600 11:54:01.231976 [Byte1]: 32
8601 11:54:01.235916
8602 11:54:01.235989 Set Vref, RX VrefLevel [Byte0]: 33
8603 11:54:01.239218 [Byte1]: 33
8604 11:54:01.243769
8605 11:54:01.243874 Set Vref, RX VrefLevel [Byte0]: 34
8606 11:54:01.246686 [Byte1]: 34
8607 11:54:01.250835
8608 11:54:01.250933 Set Vref, RX VrefLevel [Byte0]: 35
8609 11:54:01.254322 [Byte1]: 35
8610 11:54:01.258656
8611 11:54:01.258727 Set Vref, RX VrefLevel [Byte0]: 36
8612 11:54:01.261959 [Byte1]: 36
8613 11:54:01.266251
8614 11:54:01.266333 Set Vref, RX VrefLevel [Byte0]: 37
8615 11:54:01.269539 [Byte1]: 37
8616 11:54:01.273705
8617 11:54:01.273787 Set Vref, RX VrefLevel [Byte0]: 38
8618 11:54:01.276709 [Byte1]: 38
8619 11:54:01.281280
8620 11:54:01.281362 Set Vref, RX VrefLevel [Byte0]: 39
8621 11:54:01.284565 [Byte1]: 39
8622 11:54:01.288785
8623 11:54:01.288866 Set Vref, RX VrefLevel [Byte0]: 40
8624 11:54:01.292312 [Byte1]: 40
8625 11:54:01.296413
8626 11:54:01.296494 Set Vref, RX VrefLevel [Byte0]: 41
8627 11:54:01.299633 [Byte1]: 41
8628 11:54:01.303768
8629 11:54:01.303849 Set Vref, RX VrefLevel [Byte0]: 42
8630 11:54:01.307424 [Byte1]: 42
8631 11:54:01.312043
8632 11:54:01.312125 Set Vref, RX VrefLevel [Byte0]: 43
8633 11:54:01.314896 [Byte1]: 43
8634 11:54:01.318630
8635 11:54:01.318711 Set Vref, RX VrefLevel [Byte0]: 44
8636 11:54:01.322439 [Byte1]: 44
8637 11:54:01.326325
8638 11:54:01.326407 Set Vref, RX VrefLevel [Byte0]: 45
8639 11:54:01.329451 [Byte1]: 45
8640 11:54:01.333917
8641 11:54:01.333999 Set Vref, RX VrefLevel [Byte0]: 46
8642 11:54:01.337135 [Byte1]: 46
8643 11:54:01.341631
8644 11:54:01.341712 Set Vref, RX VrefLevel [Byte0]: 47
8645 11:54:01.344895 [Byte1]: 47
8646 11:54:01.349338
8647 11:54:01.349420 Set Vref, RX VrefLevel [Byte0]: 48
8648 11:54:01.352416 [Byte1]: 48
8649 11:54:01.356491
8650 11:54:01.356572 Set Vref, RX VrefLevel [Byte0]: 49
8651 11:54:01.360195 [Byte1]: 49
8652 11:54:01.364245
8653 11:54:01.364327 Set Vref, RX VrefLevel [Byte0]: 50
8654 11:54:01.367806 [Byte1]: 50
8655 11:54:01.371941
8656 11:54:01.372022 Set Vref, RX VrefLevel [Byte0]: 51
8657 11:54:01.374792 [Byte1]: 51
8658 11:54:01.379190
8659 11:54:01.379287 Set Vref, RX VrefLevel [Byte0]: 52
8660 11:54:01.382161 [Byte1]: 52
8661 11:54:01.386797
8662 11:54:01.386898 Set Vref, RX VrefLevel [Byte0]: 53
8663 11:54:01.390183 [Byte1]: 53
8664 11:54:01.394409
8665 11:54:01.394485 Set Vref, RX VrefLevel [Byte0]: 54
8666 11:54:01.397556 [Byte1]: 54
8667 11:54:01.402093
8668 11:54:01.402175 Set Vref, RX VrefLevel [Byte0]: 55
8669 11:54:01.405327 [Byte1]: 55
8670 11:54:01.409427
8671 11:54:01.409509 Set Vref, RX VrefLevel [Byte0]: 56
8672 11:54:01.412575 [Byte1]: 56
8673 11:54:01.416939
8674 11:54:01.417020 Set Vref, RX VrefLevel [Byte0]: 57
8675 11:54:01.420319 [Byte1]: 57
8676 11:54:01.424395
8677 11:54:01.424477 Set Vref, RX VrefLevel [Byte0]: 58
8678 11:54:01.427406 [Byte1]: 58
8679 11:54:01.431875
8680 11:54:01.431957 Set Vref, RX VrefLevel [Byte0]: 59
8681 11:54:01.435244 [Byte1]: 59
8682 11:54:01.439415
8683 11:54:01.439496 Set Vref, RX VrefLevel [Byte0]: 60
8684 11:54:01.442847 [Byte1]: 60
8685 11:54:01.447387
8686 11:54:01.447469 Set Vref, RX VrefLevel [Byte0]: 61
8687 11:54:01.450652 [Byte1]: 61
8688 11:54:01.454740
8689 11:54:01.454842 Set Vref, RX VrefLevel [Byte0]: 62
8690 11:54:01.457803 [Byte1]: 62
8691 11:54:01.462364
8692 11:54:01.462468 Set Vref, RX VrefLevel [Byte0]: 63
8693 11:54:01.465445 [Byte1]: 63
8694 11:54:01.469194
8695 11:54:01.469293 Set Vref, RX VrefLevel [Byte0]: 64
8696 11:54:01.473117 [Byte1]: 64
8697 11:54:01.476782
8698 11:54:01.476888 Set Vref, RX VrefLevel [Byte0]: 65
8699 11:54:01.480517 [Byte1]: 65
8700 11:54:01.484673
8701 11:54:01.484772 Set Vref, RX VrefLevel [Byte0]: 66
8702 11:54:01.488232 [Byte1]: 66
8703 11:54:01.491947
8704 11:54:01.492053 Set Vref, RX VrefLevel [Byte0]: 67
8705 11:54:01.495747 [Byte1]: 67
8706 11:54:01.499609
8707 11:54:01.499682 Set Vref, RX VrefLevel [Byte0]: 68
8708 11:54:01.502766 [Byte1]: 68
8709 11:54:01.507023
8710 11:54:01.507094 Set Vref, RX VrefLevel [Byte0]: 69
8711 11:54:01.510702 [Byte1]: 69
8712 11:54:01.515182
8713 11:54:01.515254 Set Vref, RX VrefLevel [Byte0]: 70
8714 11:54:01.518199 [Byte1]: 70
8715 11:54:01.522418
8716 11:54:01.522516 Set Vref, RX VrefLevel [Byte0]: 71
8717 11:54:01.525471 [Byte1]: 71
8718 11:54:01.529904
8719 11:54:01.530007 Set Vref, RX VrefLevel [Byte0]: 72
8720 11:54:01.532843 [Byte1]: 72
8721 11:54:01.537114
8722 11:54:01.537195 Set Vref, RX VrefLevel [Byte0]: 73
8723 11:54:01.540680 [Byte1]: 73
8724 11:54:01.544943
8725 11:54:01.545045 Set Vref, RX VrefLevel [Byte0]: 74
8726 11:54:01.547943 [Byte1]: 74
8727 11:54:01.552613
8728 11:54:01.552697 Set Vref, RX VrefLevel [Byte0]: 75
8729 11:54:01.555818 [Byte1]: 75
8730 11:54:01.559702
8731 11:54:01.559786 Final RX Vref Byte 0 = 58 to rank0
8732 11:54:01.563533 Final RX Vref Byte 1 = 58 to rank0
8733 11:54:01.566622 Final RX Vref Byte 0 = 58 to rank1
8734 11:54:01.569751 Final RX Vref Byte 1 = 58 to rank1==
8735 11:54:01.573482 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 11:54:01.580068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 11:54:01.580153 ==
8738 11:54:01.580251 DQS Delay:
8739 11:54:01.583203 DQS0 = 0, DQS1 = 0
8740 11:54:01.583290 DQM Delay:
8741 11:54:01.583375 DQM0 = 134, DQM1 = 131
8742 11:54:01.586267 DQ Delay:
8743 11:54:01.589889 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8744 11:54:01.592936 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8745 11:54:01.596310 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124
8746 11:54:01.599679 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8747 11:54:01.599763
8748 11:54:01.599848
8749 11:54:01.599946
8750 11:54:01.602828 [DramC_TX_OE_Calibration] TA2
8751 11:54:01.606626 Original DQ_B0 (3 6) =30, OEN = 27
8752 11:54:01.609735 Original DQ_B1 (3 6) =30, OEN = 27
8753 11:54:01.612733 24, 0x0, End_B0=24 End_B1=24
8754 11:54:01.612818 25, 0x0, End_B0=25 End_B1=25
8755 11:54:01.616054 26, 0x0, End_B0=26 End_B1=26
8756 11:54:01.619511 27, 0x0, End_B0=27 End_B1=27
8757 11:54:01.622880 28, 0x0, End_B0=28 End_B1=28
8758 11:54:01.626442 29, 0x0, End_B0=29 End_B1=29
8759 11:54:01.626528 30, 0x0, End_B0=30 End_B1=30
8760 11:54:01.629846 31, 0x4545, End_B0=30 End_B1=30
8761 11:54:01.632743 Byte0 end_step=30 best_step=27
8762 11:54:01.636099 Byte1 end_step=30 best_step=27
8763 11:54:01.639428 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 11:54:01.642737 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 11:54:01.642819
8766 11:54:01.642903
8767 11:54:01.649347 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8768 11:54:01.652830 CH1 RK0: MR19=303, MR18=1422
8769 11:54:01.659317 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8770 11:54:01.659408
8771 11:54:01.662600 ----->DramcWriteLeveling(PI) begin...
8772 11:54:01.662676 ==
8773 11:54:01.665984 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 11:54:01.669780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 11:54:01.669854 ==
8776 11:54:01.672976 Write leveling (Byte 0): 25 => 25
8777 11:54:01.675958 Write leveling (Byte 1): 28 => 28
8778 11:54:01.679261 DramcWriteLeveling(PI) end<-----
8779 11:54:01.679339
8780 11:54:01.679402 ==
8781 11:54:01.682527 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 11:54:01.685751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:54:01.685849 ==
8784 11:54:01.689560 [Gating] SW mode calibration
8785 11:54:01.695997 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 11:54:01.702478 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 11:54:01.705858 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 11:54:01.712815 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:54:01.715959 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8790 11:54:01.719020 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8791 11:54:01.722644 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 11:54:01.729141 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 11:54:01.732502 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 11:54:01.735970 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 11:54:01.742308 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 11:54:01.745688 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 11:54:01.749173 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8798 11:54:01.755835 1 5 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
8799 11:54:01.759014 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8800 11:54:01.762399 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 11:54:01.769405 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 11:54:01.772673 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 11:54:01.775982 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 11:54:01.782233 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 11:54:01.785941 1 6 8 | B1->B0 | 3d3d 2323 | 0 0 | (0 0) (0 0)
8806 11:54:01.789218 1 6 12 | B1->B0 | 4646 4140 | 0 1 | (0 0) (0 0)
8807 11:54:01.795585 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 11:54:01.799569 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 11:54:01.802650 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 11:54:01.808987 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 11:54:01.812631 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 11:54:01.815604 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:54:01.822370 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8814 11:54:01.825539 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8815 11:54:01.829029 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8816 11:54:01.835771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:54:01.838921 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:54:01.841981 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:54:01.845853 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 11:54:01.852135 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:54:01.855629 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:54:01.858990 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 11:54:01.866010 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:54:01.869196 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:54:01.872478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:54:01.879198 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:54:01.882383 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:54:01.886011 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 11:54:01.892370 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8830 11:54:01.895645 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8831 11:54:01.898787 Total UI for P1: 0, mck2ui 16
8832 11:54:01.902106 best dqsien dly found for B1: ( 1, 9, 8)
8833 11:54:01.905766 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 11:54:01.908878 Total UI for P1: 0, mck2ui 16
8835 11:54:01.912177 best dqsien dly found for B0: ( 1, 9, 12)
8836 11:54:01.915350 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8837 11:54:01.919006 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8838 11:54:01.919089
8839 11:54:01.922126 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8840 11:54:01.929077 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8841 11:54:01.929162 [Gating] SW calibration Done
8842 11:54:01.932097 ==
8843 11:54:01.932181 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 11:54:01.938687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 11:54:01.938772 ==
8846 11:54:01.938858 RX Vref Scan: 0
8847 11:54:01.938939
8848 11:54:01.941977 RX Vref 0 -> 0, step: 1
8849 11:54:01.942086
8850 11:54:01.945050 RX Delay 0 -> 252, step: 8
8851 11:54:01.948880 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8852 11:54:01.951982 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8853 11:54:01.955275 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8854 11:54:01.961988 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8855 11:54:01.964924 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8856 11:54:01.968201 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8857 11:54:01.971866 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8858 11:54:01.974756 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8859 11:54:01.981327 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8860 11:54:01.985254 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8861 11:54:01.988070 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8862 11:54:01.991496 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8863 11:54:01.994796 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8864 11:54:02.001482 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8865 11:54:02.005030 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8866 11:54:02.008019 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8867 11:54:02.008104 ==
8868 11:54:02.011330 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 11:54:02.014703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 11:54:02.017877 ==
8871 11:54:02.017986 DQS Delay:
8872 11:54:02.018087 DQS0 = 0, DQS1 = 0
8873 11:54:02.021705 DQM Delay:
8874 11:54:02.021789 DQM0 = 136, DQM1 = 133
8875 11:54:02.024836 DQ Delay:
8876 11:54:02.027915 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8877 11:54:02.031545 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8878 11:54:02.035022 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8879 11:54:02.037840 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8880 11:54:02.037925
8881 11:54:02.038009
8882 11:54:02.038089 ==
8883 11:54:02.041351 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 11:54:02.044615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 11:54:02.044699 ==
8886 11:54:02.044784
8887 11:54:02.047790
8888 11:54:02.047873 TX Vref Scan disable
8889 11:54:02.051735 == TX Byte 0 ==
8890 11:54:02.054624 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8891 11:54:02.057985 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8892 11:54:02.060991 == TX Byte 1 ==
8893 11:54:02.064983 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8894 11:54:02.067991 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8895 11:54:02.068076 ==
8896 11:54:02.071602 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 11:54:02.077708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 11:54:02.077819 ==
8899 11:54:02.090577
8900 11:54:02.093551 TX Vref early break, caculate TX vref
8901 11:54:02.096844 TX Vref=16, minBit 0, minWin=23, winSum=387
8902 11:54:02.100094 TX Vref=18, minBit 6, minWin=23, winSum=390
8903 11:54:02.103238 TX Vref=20, minBit 0, minWin=23, winSum=398
8904 11:54:02.106821 TX Vref=22, minBit 0, minWin=24, winSum=409
8905 11:54:02.110169 TX Vref=24, minBit 0, minWin=25, winSum=420
8906 11:54:02.116478 TX Vref=26, minBit 0, minWin=26, winSum=428
8907 11:54:02.119919 TX Vref=28, minBit 0, minWin=25, winSum=425
8908 11:54:02.123470 TX Vref=30, minBit 1, minWin=25, winSum=422
8909 11:54:02.126948 TX Vref=32, minBit 0, minWin=24, winSum=413
8910 11:54:02.130216 TX Vref=34, minBit 6, minWin=24, winSum=408
8911 11:54:02.136470 TX Vref=36, minBit 1, minWin=23, winSum=395
8912 11:54:02.139560 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8913 11:54:02.139644
8914 11:54:02.143191 Final TX Range 0 Vref 26
8915 11:54:02.143275
8916 11:54:02.143360 ==
8917 11:54:02.146651 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 11:54:02.149545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 11:54:02.149637 ==
8920 11:54:02.153091
8921 11:54:02.153174
8922 11:54:02.153258 TX Vref Scan disable
8923 11:54:02.159890 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8924 11:54:02.159974 == TX Byte 0 ==
8925 11:54:02.163085 u2DelayCellOfst[0]=17 cells (5 PI)
8926 11:54:02.166763 u2DelayCellOfst[1]=13 cells (4 PI)
8927 11:54:02.170023 u2DelayCellOfst[2]=0 cells (0 PI)
8928 11:54:02.173351 u2DelayCellOfst[3]=6 cells (2 PI)
8929 11:54:02.176122 u2DelayCellOfst[4]=10 cells (3 PI)
8930 11:54:02.179969 u2DelayCellOfst[5]=20 cells (6 PI)
8931 11:54:02.183071 u2DelayCellOfst[6]=17 cells (5 PI)
8932 11:54:02.186709 u2DelayCellOfst[7]=6 cells (2 PI)
8933 11:54:02.189708 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 11:54:02.193055 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8935 11:54:02.196132 == TX Byte 1 ==
8936 11:54:02.199941 u2DelayCellOfst[8]=0 cells (0 PI)
8937 11:54:02.203424 u2DelayCellOfst[9]=6 cells (2 PI)
8938 11:54:02.203501 u2DelayCellOfst[10]=13 cells (4 PI)
8939 11:54:02.206615 u2DelayCellOfst[11]=10 cells (3 PI)
8940 11:54:02.209885 u2DelayCellOfst[12]=17 cells (5 PI)
8941 11:54:02.213115 u2DelayCellOfst[13]=17 cells (5 PI)
8942 11:54:02.216670 u2DelayCellOfst[14]=20 cells (6 PI)
8943 11:54:02.219484 u2DelayCellOfst[15]=20 cells (6 PI)
8944 11:54:02.226022 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8945 11:54:02.229530 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8946 11:54:02.229653 DramC Write-DBI on
8947 11:54:02.229737 ==
8948 11:54:02.232800 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 11:54:02.239393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 11:54:02.239478 ==
8951 11:54:02.239564
8952 11:54:02.239645
8953 11:54:02.239723 TX Vref Scan disable
8954 11:54:02.243580 == TX Byte 0 ==
8955 11:54:02.247060 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8956 11:54:02.250099 == TX Byte 1 ==
8957 11:54:02.253457 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8958 11:54:02.256966 DramC Write-DBI off
8959 11:54:02.257049
8960 11:54:02.257135 [DATLAT]
8961 11:54:02.257217 Freq=1600, CH1 RK1
8962 11:54:02.257297
8963 11:54:02.260474 DATLAT Default: 0xf
8964 11:54:02.260557 0, 0xFFFF, sum = 0
8965 11:54:02.263914 1, 0xFFFF, sum = 0
8966 11:54:02.263999 2, 0xFFFF, sum = 0
8967 11:54:02.267112 3, 0xFFFF, sum = 0
8968 11:54:02.270116 4, 0xFFFF, sum = 0
8969 11:54:02.270202 5, 0xFFFF, sum = 0
8970 11:54:02.273817 6, 0xFFFF, sum = 0
8971 11:54:02.273902 7, 0xFFFF, sum = 0
8972 11:54:02.277081 8, 0xFFFF, sum = 0
8973 11:54:02.277166 9, 0xFFFF, sum = 0
8974 11:54:02.280172 10, 0xFFFF, sum = 0
8975 11:54:02.280257 11, 0xFFFF, sum = 0
8976 11:54:02.283788 12, 0xFFFF, sum = 0
8977 11:54:02.283874 13, 0xFFFF, sum = 0
8978 11:54:02.286813 14, 0x0, sum = 1
8979 11:54:02.286898 15, 0x0, sum = 2
8980 11:54:02.290595 16, 0x0, sum = 3
8981 11:54:02.290680 17, 0x0, sum = 4
8982 11:54:02.293741 best_step = 15
8983 11:54:02.293825
8984 11:54:02.293909 ==
8985 11:54:02.296834 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 11:54:02.299990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 11:54:02.300075 ==
8988 11:54:02.300160 RX Vref Scan: 0
8989 11:54:02.303732
8990 11:54:02.303815 RX Vref 0 -> 0, step: 1
8991 11:54:02.303899
8992 11:54:02.307086 RX Delay 19 -> 252, step: 4
8993 11:54:02.310361 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8994 11:54:02.316852 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8995 11:54:02.320020 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8996 11:54:02.323386 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8997 11:54:02.326976 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8998 11:54:02.330283 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8999 11:54:02.333536 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9000 11:54:02.339894 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9001 11:54:02.343571 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9002 11:54:02.347122 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9003 11:54:02.350348 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9004 11:54:02.353778 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9005 11:54:02.360562 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9006 11:54:02.363541 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9007 11:54:02.367056 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9008 11:54:02.370425 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9009 11:54:02.370510 ==
9010 11:54:02.373693 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 11:54:02.380410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 11:54:02.380497 ==
9013 11:54:02.380563 DQS Delay:
9014 11:54:02.380624 DQS0 = 0, DQS1 = 0
9015 11:54:02.383809 DQM Delay:
9016 11:54:02.383891 DQM0 = 134, DQM1 = 130
9017 11:54:02.387111 DQ Delay:
9018 11:54:02.390038 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
9019 11:54:02.393733 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9020 11:54:02.397070 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9021 11:54:02.400199 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9022 11:54:02.400280
9023 11:54:02.400343
9024 11:54:02.400402
9025 11:54:02.403992 [DramC_TX_OE_Calibration] TA2
9026 11:54:02.406612 Original DQ_B0 (3 6) =30, OEN = 27
9027 11:54:02.410370 Original DQ_B1 (3 6) =30, OEN = 27
9028 11:54:02.413510 24, 0x0, End_B0=24 End_B1=24
9029 11:54:02.413658 25, 0x0, End_B0=25 End_B1=25
9030 11:54:02.416873 26, 0x0, End_B0=26 End_B1=26
9031 11:54:02.420178 27, 0x0, End_B0=27 End_B1=27
9032 11:54:02.423226 28, 0x0, End_B0=28 End_B1=28
9033 11:54:02.426600 29, 0x0, End_B0=29 End_B1=29
9034 11:54:02.426682 30, 0x0, End_B0=30 End_B1=30
9035 11:54:02.429728 31, 0x4141, End_B0=30 End_B1=30
9036 11:54:02.432934 Byte0 end_step=30 best_step=27
9037 11:54:02.436686 Byte1 end_step=30 best_step=27
9038 11:54:02.440092 Byte0 TX OE(2T, 0.5T) = (3, 3)
9039 11:54:02.443255 Byte1 TX OE(2T, 0.5T) = (3, 3)
9040 11:54:02.443336
9041 11:54:02.443398
9042 11:54:02.449798 [DQSOSCAuto] RK1, (LSB)MR18= 0x2509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9043 11:54:02.453066 CH1 RK1: MR19=303, MR18=2509
9044 11:54:02.459577 CH1_RK1: MR19=0x303, MR18=0x2509, DQSOSC=391, MR23=63, INC=24, DEC=16
9045 11:54:02.463258 [RxdqsGatingPostProcess] freq 1600
9046 11:54:02.466314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9047 11:54:02.469941 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 11:54:02.472987 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 11:54:02.476269 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 11:54:02.479486 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 11:54:02.483167 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 11:54:02.486054 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 11:54:02.489460 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 11:54:02.492800 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 11:54:02.496254 Pre-setting of DQS Precalculation
9056 11:54:02.499185 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9057 11:54:02.506026 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9058 11:54:02.515947 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 11:54:02.516028
9060 11:54:02.516092
9061 11:54:02.519464 [Calibration Summary] 3200 Mbps
9062 11:54:02.519545 CH 0, Rank 0
9063 11:54:02.522545 SW Impedance : PASS
9064 11:54:02.522626 DUTY Scan : NO K
9065 11:54:02.526263 ZQ Calibration : PASS
9066 11:54:02.526343 Jitter Meter : NO K
9067 11:54:02.529447 CBT Training : PASS
9068 11:54:02.532546 Write leveling : PASS
9069 11:54:02.532626 RX DQS gating : PASS
9070 11:54:02.535743 RX DQ/DQS(RDDQC) : PASS
9071 11:54:02.539301 TX DQ/DQS : PASS
9072 11:54:02.539409 RX DATLAT : PASS
9073 11:54:02.542632 RX DQ/DQS(Engine): PASS
9074 11:54:02.545951 TX OE : PASS
9075 11:54:02.546031 All Pass.
9076 11:54:02.546096
9077 11:54:02.546156 CH 0, Rank 1
9078 11:54:02.549093 SW Impedance : PASS
9079 11:54:02.552394 DUTY Scan : NO K
9080 11:54:02.552477 ZQ Calibration : PASS
9081 11:54:02.556271 Jitter Meter : NO K
9082 11:54:02.559586 CBT Training : PASS
9083 11:54:02.559747 Write leveling : PASS
9084 11:54:02.562574 RX DQS gating : PASS
9085 11:54:02.565828 RX DQ/DQS(RDDQC) : PASS
9086 11:54:02.565915 TX DQ/DQS : PASS
9087 11:54:02.569346 RX DATLAT : PASS
9088 11:54:02.569450 RX DQ/DQS(Engine): PASS
9089 11:54:02.572680 TX OE : PASS
9090 11:54:02.572761 All Pass.
9091 11:54:02.572825
9092 11:54:02.575720 CH 1, Rank 0
9093 11:54:02.575826 SW Impedance : PASS
9094 11:54:02.579138 DUTY Scan : NO K
9095 11:54:02.582234 ZQ Calibration : PASS
9096 11:54:02.582317 Jitter Meter : NO K
9097 11:54:02.585584 CBT Training : PASS
9098 11:54:02.588851 Write leveling : PASS
9099 11:54:02.588935 RX DQS gating : PASS
9100 11:54:02.592262 RX DQ/DQS(RDDQC) : PASS
9101 11:54:02.595740 TX DQ/DQS : PASS
9102 11:54:02.595827 RX DATLAT : PASS
9103 11:54:02.598957 RX DQ/DQS(Engine): PASS
9104 11:54:02.602654 TX OE : PASS
9105 11:54:02.602740 All Pass.
9106 11:54:02.602821
9107 11:54:02.602914 CH 1, Rank 1
9108 11:54:02.605818 SW Impedance : PASS
9109 11:54:02.608841 DUTY Scan : NO K
9110 11:54:02.608917 ZQ Calibration : PASS
9111 11:54:02.612198 Jitter Meter : NO K
9112 11:54:02.615716 CBT Training : PASS
9113 11:54:02.615815 Write leveling : PASS
9114 11:54:02.618908 RX DQS gating : PASS
9115 11:54:02.622078 RX DQ/DQS(RDDQC) : PASS
9116 11:54:02.622183 TX DQ/DQS : PASS
9117 11:54:02.625686 RX DATLAT : PASS
9118 11:54:02.625804 RX DQ/DQS(Engine): PASS
9119 11:54:02.628994 TX OE : PASS
9120 11:54:02.629077 All Pass.
9121 11:54:02.629142
9122 11:54:02.632401 DramC Write-DBI on
9123 11:54:02.636633 PER_BANK_REFRESH: Hybrid Mode
9124 11:54:02.636715 TX_TRACKING: ON
9125 11:54:02.645444 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9126 11:54:02.652337 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9127 11:54:02.661968 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9128 11:54:02.665245 [FAST_K] Save calibration result to emmc
9129 11:54:02.665328 sync common calibartion params.
9130 11:54:02.668603 sync cbt_mode0:1, 1:1
9131 11:54:02.672318 dram_init: ddr_geometry: 2
9132 11:54:02.675563 dram_init: ddr_geometry: 2
9133 11:54:02.675644 dram_init: ddr_geometry: 2
9134 11:54:02.678925 0:dram_rank_size:100000000
9135 11:54:02.681906 1:dram_rank_size:100000000
9136 11:54:02.685147 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9137 11:54:02.688986 DFS_SHUFFLE_HW_MODE: ON
9138 11:54:02.692449 dramc_set_vcore_voltage set vcore to 725000
9139 11:54:02.695292 Read voltage for 1600, 0
9140 11:54:02.695389 Vio18 = 0
9141 11:54:02.698997 Vcore = 725000
9142 11:54:02.699079 Vdram = 0
9143 11:54:02.699144 Vddq = 0
9144 11:54:02.699203 Vmddr = 0
9145 11:54:02.701774 switch to 3200 Mbps bootup
9146 11:54:02.705491 [DramcRunTimeConfig]
9147 11:54:02.705602 PHYPLL
9148 11:54:02.708353 DPM_CONTROL_AFTERK: ON
9149 11:54:02.708453 PER_BANK_REFRESH: ON
9150 11:54:02.712004 REFRESH_OVERHEAD_REDUCTION: ON
9151 11:54:02.715457 CMD_PICG_NEW_MODE: OFF
9152 11:54:02.715539 XRTWTW_NEW_MODE: ON
9153 11:54:02.718611 XRTRTR_NEW_MODE: ON
9154 11:54:02.718692 TX_TRACKING: ON
9155 11:54:02.721832 RDSEL_TRACKING: OFF
9156 11:54:02.721914 DQS Precalculation for DVFS: ON
9157 11:54:02.725383 RX_TRACKING: OFF
9158 11:54:02.725464 HW_GATING DBG: ON
9159 11:54:02.728495 ZQCS_ENABLE_LP4: ON
9160 11:54:02.731768 RX_PICG_NEW_MODE: ON
9161 11:54:02.731850 TX_PICG_NEW_MODE: ON
9162 11:54:02.735003 ENABLE_RX_DCM_DPHY: ON
9163 11:54:02.738363 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9164 11:54:02.738444 DUMMY_READ_FOR_TRACKING: OFF
9165 11:54:02.742147 !!! SPM_CONTROL_AFTERK: OFF
9166 11:54:02.745492 !!! SPM could not control APHY
9167 11:54:02.748603 IMPEDANCE_TRACKING: ON
9168 11:54:02.748685 TEMP_SENSOR: ON
9169 11:54:02.752055 HW_SAVE_FOR_SR: OFF
9170 11:54:02.754931 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9171 11:54:02.758249 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9172 11:54:02.758331 Read ODT Tracking: ON
9173 11:54:02.761713 Refresh Rate DeBounce: ON
9174 11:54:02.765051 DFS_NO_QUEUE_FLUSH: ON
9175 11:54:02.768176 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9176 11:54:02.768258 ENABLE_DFS_RUNTIME_MRW: OFF
9177 11:54:02.771761 DDR_RESERVE_NEW_MODE: ON
9178 11:54:02.774945 MR_CBT_SWITCH_FREQ: ON
9179 11:54:02.775027 =========================
9180 11:54:02.795047 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9181 11:54:02.798084 dram_init: ddr_geometry: 2
9182 11:54:02.816664 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9183 11:54:02.819676 dram_init: dram init end (result: 0)
9184 11:54:02.826384 DRAM-K: Full calibration passed in 24434 msecs
9185 11:54:02.830056 MRC: failed to locate region type 0.
9186 11:54:02.830139 DRAM rank0 size:0x100000000,
9187 11:54:02.833382 DRAM rank1 size=0x100000000
9188 11:54:02.842789 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9189 11:54:02.849908 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9190 11:54:02.856336 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9191 11:54:02.862909 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9192 11:54:02.866628 DRAM rank0 size:0x100000000,
9193 11:54:02.869476 DRAM rank1 size=0x100000000
9194 11:54:02.869558 CBMEM:
9195 11:54:02.873014 IMD: root @ 0xfffff000 254 entries.
9196 11:54:02.876445 IMD: root @ 0xffffec00 62 entries.
9197 11:54:02.879332 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9198 11:54:02.882595 WARNING: RO_VPD is uninitialized or empty.
9199 11:54:02.889599 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9200 11:54:02.896562 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9201 11:54:02.909169 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9202 11:54:02.920501 BS: romstage times (exec / console): total (unknown) / 23972 ms
9203 11:54:02.920585
9204 11:54:02.920649
9205 11:54:02.930397 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9206 11:54:02.933880 ARM64: Exception handlers installed.
9207 11:54:02.937598 ARM64: Testing exception
9208 11:54:02.941101 ARM64: Done test exception
9209 11:54:02.941183 Enumerating buses...
9210 11:54:02.944313 Show all devs... Before device enumeration.
9211 11:54:02.947553 Root Device: enabled 1
9212 11:54:02.950602 CPU_CLUSTER: 0: enabled 1
9213 11:54:02.950684 CPU: 00: enabled 1
9214 11:54:02.953832 Compare with tree...
9215 11:54:02.953914 Root Device: enabled 1
9216 11:54:02.957491 CPU_CLUSTER: 0: enabled 1
9217 11:54:02.960758 CPU: 00: enabled 1
9218 11:54:02.960840 Root Device scanning...
9219 11:54:02.964073 scan_static_bus for Root Device
9220 11:54:02.967474 CPU_CLUSTER: 0 enabled
9221 11:54:02.971043 scan_static_bus for Root Device done
9222 11:54:02.974372 scan_bus: bus Root Device finished in 8 msecs
9223 11:54:02.974454 done
9224 11:54:02.980863 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9225 11:54:02.984237 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9226 11:54:02.991066 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9227 11:54:02.994027 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9228 11:54:02.997419 Allocating resources...
9229 11:54:02.997527 Reading resources...
9230 11:54:03.003918 Root Device read_resources bus 0 link: 0
9231 11:54:03.004001 DRAM rank0 size:0x100000000,
9232 11:54:03.007163 DRAM rank1 size=0x100000000
9233 11:54:03.010898 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9234 11:54:03.013728 CPU: 00 missing read_resources
9235 11:54:03.017539 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9236 11:54:03.023946 Root Device read_resources bus 0 link: 0 done
9237 11:54:03.024028 Done reading resources.
9238 11:54:03.030295 Show resources in subtree (Root Device)...After reading.
9239 11:54:03.033779 Root Device child on link 0 CPU_CLUSTER: 0
9240 11:54:03.037188 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 11:54:03.047004 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 11:54:03.047088 CPU: 00
9243 11:54:03.050328 Root Device assign_resources, bus 0 link: 0
9244 11:54:03.053374 CPU_CLUSTER: 0 missing set_resources
9245 11:54:03.057281 Root Device assign_resources, bus 0 link: 0 done
9246 11:54:03.060388 Done setting resources.
9247 11:54:03.066735 Show resources in subtree (Root Device)...After assigning values.
9248 11:54:03.070611 Root Device child on link 0 CPU_CLUSTER: 0
9249 11:54:03.073719 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 11:54:03.083685 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 11:54:03.083769 CPU: 00
9252 11:54:03.086799 Done allocating resources.
9253 11:54:03.090525 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9254 11:54:03.093718 Enabling resources...
9255 11:54:03.093825 done.
9256 11:54:03.100234 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9257 11:54:03.100317 Initializing devices...
9258 11:54:03.103535 Root Device init
9259 11:54:03.103617 init hardware done!
9260 11:54:03.106984 0x00000018: ctrlr->caps
9261 11:54:03.110099 52.000 MHz: ctrlr->f_max
9262 11:54:03.110184 0.400 MHz: ctrlr->f_min
9263 11:54:03.113317 0x40ff8080: ctrlr->voltages
9264 11:54:03.113400 sclk: 390625
9265 11:54:03.116712 Bus Width = 1
9266 11:54:03.116793 sclk: 390625
9267 11:54:03.116857 Bus Width = 1
9268 11:54:03.120378 Early init status = 3
9269 11:54:03.127006 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9270 11:54:03.130005 in-header: 03 fb 00 00 01 00 00 00
9271 11:54:03.130087 in-data: 01
9272 11:54:03.137205 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9273 11:54:03.140011 in-header: 03 fb 00 00 01 00 00 00
9274 11:54:03.140122 in-data: 01
9275 11:54:03.143553 [SSUSB] Setting up USB HOST controller...
9276 11:54:03.149968 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9277 11:54:03.150047 [SSUSB] phy power-on done.
9278 11:54:03.156455 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9279 11:54:03.159754 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9280 11:54:03.166509 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9281 11:54:03.173479 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9282 11:54:03.176583 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9283 11:54:03.184388 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9284 11:54:03.191276 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9285 11:54:03.197746 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9286 11:54:03.201072 SPM: binary array size = 0x9dc
9287 11:54:03.207529 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9288 11:54:03.211259 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9289 11:54:03.217795 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9290 11:54:03.223937 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9291 11:54:03.227217 configure_display: Starting display init
9292 11:54:03.261993 anx7625_power_on_init: Init interface.
9293 11:54:03.265376 anx7625_disable_pd_protocol: Disabled PD feature.
9294 11:54:03.268893 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9295 11:54:03.296545 anx7625_start_dp_work: Secure OCM version=00
9296 11:54:03.299674 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9297 11:54:03.314564 sp_tx_get_edid_block: EDID Block = 1
9298 11:54:03.416974 Extracted contents:
9299 11:54:03.420275 header: 00 ff ff ff ff ff ff 00
9300 11:54:03.423600 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9301 11:54:03.426727 version: 01 04
9302 11:54:03.430373 basic params: 95 1f 11 78 0a
9303 11:54:03.433510 chroma info: 76 90 94 55 54 90 27 21 50 54
9304 11:54:03.436838 established: 00 00 00
9305 11:54:03.444128 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9306 11:54:03.447171 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9307 11:54:03.453851 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9308 11:54:03.460362 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9309 11:54:03.467190 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9310 11:54:03.470361 extensions: 00
9311 11:54:03.470443 checksum: fb
9312 11:54:03.470509
9313 11:54:03.473368 Manufacturer: IVO Model 57d Serial Number 0
9314 11:54:03.476863 Made week 0 of 2020
9315 11:54:03.476945 EDID version: 1.4
9316 11:54:03.480450 Digital display
9317 11:54:03.483922 6 bits per primary color channel
9318 11:54:03.484007 DisplayPort interface
9319 11:54:03.487117 Maximum image size: 31 cm x 17 cm
9320 11:54:03.490265 Gamma: 220%
9321 11:54:03.490347 Check DPMS levels
9322 11:54:03.493210 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9323 11:54:03.496772 First detailed timing is preferred timing
9324 11:54:03.500235 Established timings supported:
9325 11:54:03.503660 Standard timings supported:
9326 11:54:03.503742 Detailed timings
9327 11:54:03.510587 Hex of detail: 383680a07038204018303c0035ae10000019
9328 11:54:03.513710 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9329 11:54:03.516982 0780 0798 07c8 0820 hborder 0
9330 11:54:03.523343 0438 043b 0447 0458 vborder 0
9331 11:54:03.523424 -hsync -vsync
9332 11:54:03.527057 Did detailed timing
9333 11:54:03.530339 Hex of detail: 000000000000000000000000000000000000
9334 11:54:03.533760 Manufacturer-specified data, tag 0
9335 11:54:03.539973 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9336 11:54:03.540054 ASCII string: InfoVision
9337 11:54:03.546942 Hex of detail: 000000fe00523134304e574635205248200a
9338 11:54:03.550479 ASCII string: R140NWF5 RH
9339 11:54:03.550559 Checksum
9340 11:54:03.550622 Checksum: 0xfb (valid)
9341 11:54:03.557007 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9342 11:54:03.560315 DSI data_rate: 832800000 bps
9343 11:54:03.563959 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9344 11:54:03.566616 anx7625_parse_edid: pixelclock(138800).
9345 11:54:03.573454 hactive(1920), hsync(48), hfp(24), hbp(88)
9346 11:54:03.576747 vactive(1080), vsync(12), vfp(3), vbp(17)
9347 11:54:03.580085 anx7625_dsi_config: config dsi.
9348 11:54:03.586664 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9349 11:54:03.598790 anx7625_dsi_config: success to config DSI
9350 11:54:03.602075 anx7625_dp_start: MIPI phy setup OK.
9351 11:54:03.605772 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9352 11:54:03.609298 mtk_ddp_mode_set invalid vrefresh 60
9353 11:54:03.612773 main_disp_path_setup
9354 11:54:03.612853 ovl_layer_smi_id_en
9355 11:54:03.615906 ovl_layer_smi_id_en
9356 11:54:03.615986 ccorr_config
9357 11:54:03.616050 aal_config
9358 11:54:03.619357 gamma_config
9359 11:54:03.619437 postmask_config
9360 11:54:03.622512 dither_config
9361 11:54:03.625817 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9362 11:54:03.632205 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9363 11:54:03.635965 Root Device init finished in 529 msecs
9364 11:54:03.636046 CPU_CLUSTER: 0 init
9365 11:54:03.645750 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9366 11:54:03.648842 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9367 11:54:03.652446 APU_MBOX 0x190000b0 = 0x10001
9368 11:54:03.655518 APU_MBOX 0x190001b0 = 0x10001
9369 11:54:03.659308 APU_MBOX 0x190005b0 = 0x10001
9370 11:54:03.662629 APU_MBOX 0x190006b0 = 0x10001
9371 11:54:03.665854 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9372 11:54:03.678280 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9373 11:54:03.690830 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9374 11:54:03.697343 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9375 11:54:03.708969 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9376 11:54:03.717936 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9377 11:54:03.721363 CPU_CLUSTER: 0 init finished in 81 msecs
9378 11:54:03.724318 Devices initialized
9379 11:54:03.728134 Show all devs... After init.
9380 11:54:03.728219 Root Device: enabled 1
9381 11:54:03.731268 CPU_CLUSTER: 0: enabled 1
9382 11:54:03.734572 CPU: 00: enabled 1
9383 11:54:03.737739 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9384 11:54:03.741017 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9385 11:54:03.744159 ELOG: NV offset 0x57f000 size 0x1000
9386 11:54:03.751358 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9387 11:54:03.757913 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9388 11:54:03.760971 ELOG: Event(17) added with size 13 at 2023-11-23 11:51:53 UTC
9389 11:54:03.764679 out: cmd=0x121: 03 db 21 01 00 00 00 00
9390 11:54:03.768039 in-header: 03 0d 00 00 2c 00 00 00
9391 11:54:03.781145 in-data: 52 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9392 11:54:03.787974 ELOG: Event(A1) added with size 10 at 2023-11-23 11:51:53 UTC
9393 11:54:03.794994 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9394 11:54:03.801180 ELOG: Event(A0) added with size 9 at 2023-11-23 11:51:53 UTC
9395 11:54:03.804889 elog_add_boot_reason: Logged dev mode boot
9396 11:54:03.807976 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9397 11:54:03.811337 Finalize devices...
9398 11:54:03.811418 Devices finalized
9399 11:54:03.817845 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9400 11:54:03.821520 Writing coreboot table at 0xffe64000
9401 11:54:03.824481 0. 000000000010a000-0000000000113fff: RAMSTAGE
9402 11:54:03.827826 1. 0000000040000000-00000000400fffff: RAM
9403 11:54:03.831119 2. 0000000040100000-000000004032afff: RAMSTAGE
9404 11:54:03.837687 3. 000000004032b000-00000000545fffff: RAM
9405 11:54:03.841683 4. 0000000054600000-000000005465ffff: BL31
9406 11:54:03.844951 5. 0000000054660000-00000000ffe63fff: RAM
9407 11:54:03.848188 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9408 11:54:03.854829 7. 0000000100000000-000000023fffffff: RAM
9409 11:54:03.854910 Passing 5 GPIOs to payload:
9410 11:54:03.861072 NAME | PORT | POLARITY | VALUE
9411 11:54:03.864778 EC in RW | 0x000000aa | low | undefined
9412 11:54:03.871300 EC interrupt | 0x00000005 | low | undefined
9413 11:54:03.874537 TPM interrupt | 0x000000ab | high | undefined
9414 11:54:03.878075 SD card detect | 0x00000011 | high | undefined
9415 11:54:03.884797 speaker enable | 0x00000093 | high | undefined
9416 11:54:03.887757 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9417 11:54:03.890880 in-header: 03 f9 00 00 02 00 00 00
9418 11:54:03.890961 in-data: 02 00
9419 11:54:03.894575 ADC[4]: Raw value=904726 ID=7
9420 11:54:03.897816 ADC[3]: Raw value=213810 ID=1
9421 11:54:03.897896 RAM Code: 0x71
9422 11:54:03.900818 ADC[6]: Raw value=75332 ID=0
9423 11:54:03.904422 ADC[5]: Raw value=212703 ID=1
9424 11:54:03.904502 SKU Code: 0x1
9425 11:54:03.911017 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b2c3
9426 11:54:03.914821 coreboot table: 964 bytes.
9427 11:54:03.917473 IMD ROOT 0. 0xfffff000 0x00001000
9428 11:54:03.921017 IMD SMALL 1. 0xffffe000 0x00001000
9429 11:54:03.924105 RO MCACHE 2. 0xffffc000 0x00001104
9430 11:54:03.927630 CONSOLE 3. 0xfff7c000 0x00080000
9431 11:54:03.930628 FMAP 4. 0xfff7b000 0x00000452
9432 11:54:03.934357 TIME STAMP 5. 0xfff7a000 0x00000910
9433 11:54:03.937356 VBOOT WORK 6. 0xfff66000 0x00014000
9434 11:54:03.940816 RAMOOPS 7. 0xffe66000 0x00100000
9435 11:54:03.944288 COREBOOT 8. 0xffe64000 0x00002000
9436 11:54:03.944369 IMD small region:
9437 11:54:03.947774 IMD ROOT 0. 0xffffec00 0x00000400
9438 11:54:03.951078 VPD 1. 0xffffeb80 0x0000006c
9439 11:54:03.954376 MMC STATUS 2. 0xffffeb60 0x00000004
9440 11:54:03.961234 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9441 11:54:03.961316 Probing TPM: done!
9442 11:54:03.967723 Connected to device vid:did:rid of 1ae0:0028:00
9443 11:54:03.974574 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9444 11:54:03.981622 Initialized TPM device CR50 revision 0
9445 11:54:03.981704 Checking cr50 for pending updates
9446 11:54:03.987944 Reading cr50 TPM mode
9447 11:54:03.996000 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9448 11:54:04.003191 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9449 11:54:04.042931 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9450 11:54:04.046378 Checking segment from ROM address 0x40100000
9451 11:54:04.049491 Checking segment from ROM address 0x4010001c
9452 11:54:04.056169 Loading segment from ROM address 0x40100000
9453 11:54:04.056251 code (compression=0)
9454 11:54:04.066367 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9455 11:54:04.072761 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9456 11:54:04.072842 it's not compressed!
9457 11:54:04.079853 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9458 11:54:04.082942 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9459 11:54:04.103285 Loading segment from ROM address 0x4010001c
9460 11:54:04.103369 Entry Point 0x80000000
9461 11:54:04.106374 Loaded segments
9462 11:54:04.110006 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9463 11:54:04.116810 Jumping to boot code at 0x80000000(0xffe64000)
9464 11:54:04.123139 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9465 11:54:04.130024 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9466 11:54:04.137496 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9467 11:54:04.140921 Checking segment from ROM address 0x40100000
9468 11:54:04.144192 Checking segment from ROM address 0x4010001c
9469 11:54:04.150882 Loading segment from ROM address 0x40100000
9470 11:54:04.150963 code (compression=1)
9471 11:54:04.157891 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9472 11:54:04.167546 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9473 11:54:04.167627 using LZMA
9474 11:54:04.176444 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9475 11:54:04.182953 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9476 11:54:04.186032 Loading segment from ROM address 0x4010001c
9477 11:54:04.186113 Entry Point 0x54601000
9478 11:54:04.189833 Loaded segments
9479 11:54:04.192763 NOTICE: MT8192 bl31_setup
9480 11:54:04.199867 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9481 11:54:04.202990 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9482 11:54:04.206199 WARNING: region 0:
9483 11:54:04.209993 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 11:54:04.210074 WARNING: region 1:
9485 11:54:04.216288 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9486 11:54:04.219714 WARNING: region 2:
9487 11:54:04.222765 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9488 11:54:04.226389 WARNING: region 3:
9489 11:54:04.229498 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 11:54:04.233422 WARNING: region 4:
9491 11:54:04.236513 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 11:54:04.239626 WARNING: region 5:
9493 11:54:04.243348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 11:54:04.246357 WARNING: region 6:
9495 11:54:04.250057 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 11:54:04.250138 WARNING: region 7:
9497 11:54:04.256197 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 11:54:04.263476 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9499 11:54:04.266714 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9500 11:54:04.269558 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9501 11:54:04.276334 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9502 11:54:04.279764 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9503 11:54:04.283338 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9504 11:54:04.289836 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9505 11:54:04.292903 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9506 11:54:04.299974 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9507 11:54:04.303158 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9508 11:54:04.306374 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9509 11:54:04.313274 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9510 11:54:04.316716 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9511 11:54:04.319854 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9512 11:54:04.326002 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9513 11:54:04.329769 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9514 11:54:04.332810 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9515 11:54:04.339587 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9516 11:54:04.342857 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9517 11:54:04.349405 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9518 11:54:04.352748 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9519 11:54:04.356310 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9520 11:54:04.363209 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9521 11:54:04.366352 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9522 11:54:04.373257 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9523 11:54:04.376413 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9524 11:54:04.379586 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9525 11:54:04.386703 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9526 11:54:04.390099 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9527 11:54:04.393622 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9528 11:54:04.399930 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9529 11:54:04.403023 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9530 11:54:04.406548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9531 11:54:04.413221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9532 11:54:04.416237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9533 11:54:04.420171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9534 11:54:04.423415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9535 11:54:04.429758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9536 11:54:04.433255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9537 11:54:04.436276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9538 11:54:04.439900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9539 11:54:04.446650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9540 11:54:04.449755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9541 11:54:04.453340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9542 11:54:04.456582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9543 11:54:04.463188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9544 11:54:04.466720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9545 11:54:04.470197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9546 11:54:04.476470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9547 11:54:04.479708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9548 11:54:04.486724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9549 11:54:04.490062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9550 11:54:04.493143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9551 11:54:04.500035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9552 11:54:04.502892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9553 11:54:04.509703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9554 11:54:04.513292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9555 11:54:04.516740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9556 11:54:04.523698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9557 11:54:04.526482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9558 11:54:04.533138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9559 11:54:04.536646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9560 11:54:04.543480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9561 11:54:04.546569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9562 11:54:04.553100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9563 11:54:04.556890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9564 11:54:04.559841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9565 11:54:04.566647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9566 11:54:04.569997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9567 11:54:04.576824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9568 11:54:04.580035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9569 11:54:04.583554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9570 11:54:04.589805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9571 11:54:04.593777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9572 11:54:04.600010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9573 11:54:04.603289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9574 11:54:04.609978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9575 11:54:04.613522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9576 11:54:04.620584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9577 11:54:04.623199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9578 11:54:04.626701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9579 11:54:04.633724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9580 11:54:04.636894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9581 11:54:04.643953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9582 11:54:04.647040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9583 11:54:04.650009 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9584 11:54:04.657042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9585 11:54:04.660149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9586 11:54:04.667157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9587 11:54:04.670150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9588 11:54:04.677066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9589 11:54:04.680187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9590 11:54:04.683388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9591 11:54:04.690114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9592 11:54:04.693509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9593 11:54:04.700338 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9594 11:54:04.703683 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9595 11:54:04.706851 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9596 11:54:04.713893 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9597 11:54:04.716767 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9598 11:54:04.720063 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9599 11:54:04.723838 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9600 11:54:04.730347 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9601 11:54:04.733435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9602 11:54:04.740336 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9603 11:54:04.743776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9604 11:54:04.747171 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9605 11:54:04.753284 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9606 11:54:04.757005 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9607 11:54:04.763272 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9608 11:54:04.767152 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9609 11:54:04.770431 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9610 11:54:04.777146 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9611 11:54:04.780308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9612 11:54:04.786694 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9613 11:54:04.790618 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9614 11:54:04.793740 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9615 11:54:04.800111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9616 11:54:04.803871 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9617 11:54:04.807516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9618 11:54:04.810434 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9619 11:54:04.816945 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9620 11:54:04.820415 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9621 11:54:04.823520 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9622 11:54:04.827069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9623 11:54:04.833370 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9624 11:54:04.837395 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9625 11:54:04.843498 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9626 11:54:04.846966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9627 11:54:04.850231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9628 11:54:04.857061 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9629 11:54:04.860887 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9630 11:54:04.864084 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9631 11:54:04.870847 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9632 11:54:04.874086 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9633 11:54:04.880690 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9634 11:54:04.883776 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9635 11:54:04.886993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9636 11:54:04.893942 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9637 11:54:04.897144 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9638 11:54:04.904009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9639 11:54:04.907465 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9640 11:54:04.910412 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9641 11:54:04.917766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9642 11:54:04.920331 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9643 11:54:04.923848 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9644 11:54:04.930463 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9645 11:54:04.933531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9646 11:54:04.940855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9647 11:54:04.943740 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9648 11:54:04.946916 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9649 11:54:04.953742 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9650 11:54:04.956933 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9651 11:54:04.963866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9652 11:54:04.967738 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9653 11:54:04.970873 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9654 11:54:04.977341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9655 11:54:04.980524 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9656 11:54:04.984171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9657 11:54:04.990849 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9658 11:54:04.994228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9659 11:54:05.000639 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9660 11:54:05.003684 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9661 11:54:05.007356 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9662 11:54:05.013845 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9663 11:54:05.017088 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9664 11:54:05.023912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9665 11:54:05.026825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9666 11:54:05.030754 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9667 11:54:05.037213 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9668 11:54:05.040222 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9669 11:54:05.046992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9670 11:54:05.050293 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9671 11:54:05.053896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9672 11:54:05.060525 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9673 11:54:05.063760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9674 11:54:05.066772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9675 11:54:05.073436 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9676 11:54:05.076667 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9677 11:54:05.083377 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9678 11:54:05.087411 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9679 11:54:05.090020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9680 11:54:05.096822 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9681 11:54:05.100450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9682 11:54:05.107074 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9683 11:54:05.110136 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9684 11:54:05.113634 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9685 11:54:05.120524 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9686 11:54:05.123670 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9687 11:54:05.130299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9688 11:54:05.133754 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9689 11:54:05.136922 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9690 11:54:05.143420 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9691 11:54:05.146493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9692 11:54:05.153480 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9693 11:54:05.156554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9694 11:54:05.160096 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9695 11:54:05.166776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9696 11:54:05.170165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9697 11:54:05.176845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9698 11:54:05.180120 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9699 11:54:05.186576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9700 11:54:05.189729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9701 11:54:05.193758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9702 11:54:05.200098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9703 11:54:05.203165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9704 11:54:05.209571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9705 11:54:05.213072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9706 11:54:05.219981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9707 11:54:05.223137 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9708 11:54:05.226222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9709 11:54:05.233347 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9710 11:54:05.236490 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9711 11:54:05.242921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9712 11:54:05.246094 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9713 11:54:05.249411 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9714 11:54:05.256122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9715 11:54:05.259401 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9716 11:54:05.266345 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9717 11:54:05.269624 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9718 11:54:05.276304 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9719 11:54:05.279405 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9720 11:54:05.283078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9721 11:54:05.289417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9722 11:54:05.292886 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9723 11:54:05.299515 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9724 11:54:05.302961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9725 11:54:05.306123 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9726 11:54:05.312713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9727 11:54:05.315932 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9728 11:54:05.319349 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9729 11:54:05.323133 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9730 11:54:05.329163 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9731 11:54:05.332911 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9732 11:54:05.336209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9733 11:54:05.342431 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9734 11:54:05.345859 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9735 11:54:05.352442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9736 11:54:05.356040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9737 11:54:05.359246 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9738 11:54:05.362954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9739 11:54:05.369445 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9740 11:54:05.372837 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9741 11:54:05.376092 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9742 11:54:05.382927 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9743 11:54:05.386080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9744 11:54:05.392675 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9745 11:54:05.396088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9746 11:54:05.399063 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9747 11:54:05.405751 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9748 11:54:05.409463 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9749 11:54:05.415828 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9750 11:54:05.419066 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9751 11:54:05.423047 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9752 11:54:05.429060 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9753 11:54:05.432369 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9754 11:54:05.435850 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9755 11:54:05.442103 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9756 11:54:05.445899 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9757 11:54:05.449044 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9758 11:54:05.455617 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9759 11:54:05.458729 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9760 11:54:05.465330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9761 11:54:05.469104 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9762 11:54:05.472358 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9763 11:54:05.478630 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9764 11:54:05.481751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9765 11:54:05.488982 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9766 11:54:05.491899 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9767 11:54:05.495041 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9768 11:54:05.498497 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9769 11:54:05.502125 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9770 11:54:05.508266 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9771 11:54:05.512127 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9772 11:54:05.515444 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9773 11:54:05.518779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9774 11:54:05.525295 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9775 11:54:05.528084 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9776 11:54:05.531995 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9777 11:54:05.535010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9778 11:54:05.541632 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9779 11:54:05.544723 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9780 11:54:05.548191 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9781 11:54:05.555067 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9782 11:54:05.558409 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9783 11:54:05.564811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9784 11:54:05.568570 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9785 11:54:05.574945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9786 11:54:05.578074 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9787 11:54:05.581477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9788 11:54:05.588280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9789 11:54:05.591709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9790 11:54:05.594849 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9791 11:54:05.601968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9792 11:54:05.605155 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9793 11:54:05.611430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9794 11:54:05.615157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9795 11:54:05.618180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9796 11:54:05.624473 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9797 11:54:05.628278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9798 11:54:05.634893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9799 11:54:05.638147 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9800 11:54:05.644708 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9801 11:54:05.648163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9802 11:54:05.651396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9803 11:54:05.657864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9804 11:54:05.661343 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9805 11:54:05.667881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9806 11:54:05.671292 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9807 11:54:05.674165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9808 11:54:05.680752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9809 11:54:05.684751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9810 11:54:05.690972 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9811 11:54:05.694240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9812 11:54:05.697480 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9813 11:54:05.704259 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9814 11:54:05.707638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9815 11:54:05.714307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9816 11:54:05.717341 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9817 11:54:05.724260 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9818 11:54:05.727428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9819 11:54:05.730976 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9820 11:54:05.737580 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9821 11:54:05.740760 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9822 11:54:05.747818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9823 11:54:05.751022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9824 11:54:05.754410 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9825 11:54:05.761022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9826 11:54:05.764344 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9827 11:54:05.771056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9828 11:54:05.773982 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9829 11:54:05.777323 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9830 11:54:05.784264 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9831 11:54:05.787332 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9832 11:54:05.793916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9833 11:54:05.797336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9834 11:54:05.803945 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9835 11:54:05.807006 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9836 11:54:05.810361 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9837 11:54:05.817513 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9838 11:54:05.820483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9839 11:54:05.826966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9840 11:54:05.830231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9841 11:54:05.833964 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9842 11:54:05.840665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9843 11:54:05.843877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9844 11:54:05.847192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9845 11:54:05.853671 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9846 11:54:05.857473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9847 11:54:05.863783 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9848 11:54:05.867746 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9849 11:54:05.873953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9850 11:54:05.877003 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9851 11:54:05.880272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9852 11:54:05.887225 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9853 11:54:05.890677 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9854 11:54:05.897002 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9855 11:54:05.899982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9856 11:54:05.906731 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9857 11:54:05.910210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9858 11:54:05.916988 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9859 11:54:05.920044 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9860 11:54:05.923272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9861 11:54:05.930075 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9862 11:54:05.932979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9863 11:54:05.939769 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9864 11:54:05.943025 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9865 11:54:05.949983 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9866 11:54:05.953067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9867 11:54:05.957022 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9868 11:54:05.963375 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9869 11:54:05.966431 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9870 11:54:05.973425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9871 11:54:05.976693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9872 11:54:05.982844 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9873 11:54:05.986559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9874 11:54:05.989512 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9875 11:54:05.996558 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9876 11:54:05.999722 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9877 11:54:06.006987 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9878 11:54:06.009983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9879 11:54:06.016373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9880 11:54:06.019565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9881 11:54:06.023044 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9882 11:54:06.029919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9883 11:54:06.032733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9884 11:54:06.039542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9885 11:54:06.042930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9886 11:54:06.049361 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9887 11:54:06.052945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9888 11:54:06.059606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9889 11:54:06.062721 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9890 11:54:06.066536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9891 11:54:06.072828 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9892 11:54:06.075834 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9893 11:54:06.082781 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9894 11:54:06.086139 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9895 11:54:06.092481 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9896 11:54:06.096221 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9897 11:54:06.099706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9898 11:54:06.105866 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9899 11:54:06.109128 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9900 11:54:06.116238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9901 11:54:06.119350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9902 11:54:06.122569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9903 11:54:06.129390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9904 11:54:06.132589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9905 11:54:06.139599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9906 11:54:06.142204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9907 11:54:06.148884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9908 11:54:06.152304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9909 11:54:06.159091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9910 11:54:06.162306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9911 11:54:06.169089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9912 11:54:06.172402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9913 11:54:06.179088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9914 11:54:06.182921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9915 11:54:06.189018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9916 11:54:06.192653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9917 11:54:06.198659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9918 11:54:06.202440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9919 11:54:06.208626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9920 11:54:06.212206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9921 11:54:06.218605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9922 11:54:06.221821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9923 11:54:06.228345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9924 11:54:06.232069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9925 11:54:06.238544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9926 11:54:06.242498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9927 11:54:06.248817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9928 11:54:06.251693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9929 11:54:06.258463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9930 11:54:06.261931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9931 11:54:06.268976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9932 11:54:06.272193 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9933 11:54:06.275322 INFO: [APUAPC] vio 0
9934 11:54:06.278414 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9935 11:54:06.281838 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9936 11:54:06.285277 INFO: [APUAPC] D0_APC_0: 0x400510
9937 11:54:06.288504 INFO: [APUAPC] D0_APC_1: 0x0
9938 11:54:06.291982 INFO: [APUAPC] D0_APC_2: 0x1540
9939 11:54:06.295527 INFO: [APUAPC] D0_APC_3: 0x0
9940 11:54:06.298678 INFO: [APUAPC] D1_APC_0: 0xffffffff
9941 11:54:06.301743 INFO: [APUAPC] D1_APC_1: 0xffffffff
9942 11:54:06.304987 INFO: [APUAPC] D1_APC_2: 0x3fffff
9943 11:54:06.308725 INFO: [APUAPC] D1_APC_3: 0x0
9944 11:54:06.311902 INFO: [APUAPC] D2_APC_0: 0xffffffff
9945 11:54:06.314875 INFO: [APUAPC] D2_APC_1: 0xffffffff
9946 11:54:06.318465 INFO: [APUAPC] D2_APC_2: 0x3fffff
9947 11:54:06.321554 INFO: [APUAPC] D2_APC_3: 0x0
9948 11:54:06.325254 INFO: [APUAPC] D3_APC_0: 0xffffffff
9949 11:54:06.328462 INFO: [APUAPC] D3_APC_1: 0xffffffff
9950 11:54:06.331683 INFO: [APUAPC] D3_APC_2: 0x3fffff
9951 11:54:06.334861 INFO: [APUAPC] D3_APC_3: 0x0
9952 11:54:06.338737 INFO: [APUAPC] D4_APC_0: 0xffffffff
9953 11:54:06.341984 INFO: [APUAPC] D4_APC_1: 0xffffffff
9954 11:54:06.345109 INFO: [APUAPC] D4_APC_2: 0x3fffff
9955 11:54:06.348348 INFO: [APUAPC] D4_APC_3: 0x0
9956 11:54:06.352019 INFO: [APUAPC] D5_APC_0: 0xffffffff
9957 11:54:06.355093 INFO: [APUAPC] D5_APC_1: 0xffffffff
9958 11:54:06.358344 INFO: [APUAPC] D5_APC_2: 0x3fffff
9959 11:54:06.361436 INFO: [APUAPC] D5_APC_3: 0x0
9960 11:54:06.364956 INFO: [APUAPC] D6_APC_0: 0xffffffff
9961 11:54:06.368260 INFO: [APUAPC] D6_APC_1: 0xffffffff
9962 11:54:06.371739 INFO: [APUAPC] D6_APC_2: 0x3fffff
9963 11:54:06.374761 INFO: [APUAPC] D6_APC_3: 0x0
9964 11:54:06.378544 INFO: [APUAPC] D7_APC_0: 0xffffffff
9965 11:54:06.381717 INFO: [APUAPC] D7_APC_1: 0xffffffff
9966 11:54:06.384680 INFO: [APUAPC] D7_APC_2: 0x3fffff
9967 11:54:06.384762 INFO: [APUAPC] D7_APC_3: 0x0
9968 11:54:06.391639 INFO: [APUAPC] D8_APC_0: 0xffffffff
9969 11:54:06.394540 INFO: [APUAPC] D8_APC_1: 0xffffffff
9970 11:54:06.398018 INFO: [APUAPC] D8_APC_2: 0x3fffff
9971 11:54:06.398101 INFO: [APUAPC] D8_APC_3: 0x0
9972 11:54:06.401562 INFO: [APUAPC] D9_APC_0: 0xffffffff
9973 11:54:06.408332 INFO: [APUAPC] D9_APC_1: 0xffffffff
9974 11:54:06.411051 INFO: [APUAPC] D9_APC_2: 0x3fffff
9975 11:54:06.411134 INFO: [APUAPC] D9_APC_3: 0x0
9976 11:54:06.414810 INFO: [APUAPC] D10_APC_0: 0xffffffff
9977 11:54:06.421150 INFO: [APUAPC] D10_APC_1: 0xffffffff
9978 11:54:06.424710 INFO: [APUAPC] D10_APC_2: 0x3fffff
9979 11:54:06.424793 INFO: [APUAPC] D10_APC_3: 0x0
9980 11:54:06.427723 INFO: [APUAPC] D11_APC_0: 0xffffffff
9981 11:54:06.434530 INFO: [APUAPC] D11_APC_1: 0xffffffff
9982 11:54:06.437882 INFO: [APUAPC] D11_APC_2: 0x3fffff
9983 11:54:06.437965 INFO: [APUAPC] D11_APC_3: 0x0
9984 11:54:06.441357 INFO: [APUAPC] D12_APC_0: 0xffffffff
9985 11:54:06.448016 INFO: [APUAPC] D12_APC_1: 0xffffffff
9986 11:54:06.451077 INFO: [APUAPC] D12_APC_2: 0x3fffff
9987 11:54:06.451158 INFO: [APUAPC] D12_APC_3: 0x0
9988 11:54:06.457602 INFO: [APUAPC] D13_APC_0: 0xffffffff
9989 11:54:06.460749 INFO: [APUAPC] D13_APC_1: 0xffffffff
9990 11:54:06.464700 INFO: [APUAPC] D13_APC_2: 0x3fffff
9991 11:54:06.464783 INFO: [APUAPC] D13_APC_3: 0x0
9992 11:54:06.470868 INFO: [APUAPC] D14_APC_0: 0xffffffff
9993 11:54:06.474699 INFO: [APUAPC] D14_APC_1: 0xffffffff
9994 11:54:06.477556 INFO: [APUAPC] D14_APC_2: 0x3fffff
9995 11:54:06.477661 INFO: [APUAPC] D14_APC_3: 0x0
9996 11:54:06.484444 INFO: [APUAPC] D15_APC_0: 0xffffffff
9997 11:54:06.487985 INFO: [APUAPC] D15_APC_1: 0xffffffff
9998 11:54:06.490823 INFO: [APUAPC] D15_APC_2: 0x3fffff
9999 11:54:06.494141 INFO: [APUAPC] D15_APC_3: 0x0
10000 11:54:06.494245 INFO: [APUAPC] APC_CON: 0x4
10001 11:54:06.497803 INFO: [NOCDAPC] D0_APC_0: 0x0
10002 11:54:06.500890 INFO: [NOCDAPC] D0_APC_1: 0x0
10003 11:54:06.504080 INFO: [NOCDAPC] D1_APC_0: 0x0
10004 11:54:06.507367 INFO: [NOCDAPC] D1_APC_1: 0xfff
10005 11:54:06.511099 INFO: [NOCDAPC] D2_APC_0: 0x0
10006 11:54:06.514049 INFO: [NOCDAPC] D2_APC_1: 0xfff
10007 11:54:06.517632 INFO: [NOCDAPC] D3_APC_0: 0x0
10008 11:54:06.521057 INFO: [NOCDAPC] D3_APC_1: 0xfff
10009 11:54:06.521139 INFO: [NOCDAPC] D4_APC_0: 0x0
10010 11:54:06.524200 INFO: [NOCDAPC] D4_APC_1: 0xfff
10011 11:54:06.527290 INFO: [NOCDAPC] D5_APC_0: 0x0
10012 11:54:06.530804 INFO: [NOCDAPC] D5_APC_1: 0xfff
10013 11:54:06.533808 INFO: [NOCDAPC] D6_APC_0: 0x0
10014 11:54:06.537474 INFO: [NOCDAPC] D6_APC_1: 0xfff
10015 11:54:06.540736 INFO: [NOCDAPC] D7_APC_0: 0x0
10016 11:54:06.543945 INFO: [NOCDAPC] D7_APC_1: 0xfff
10017 11:54:06.547069 INFO: [NOCDAPC] D8_APC_0: 0x0
10018 11:54:06.550985 INFO: [NOCDAPC] D8_APC_1: 0xfff
10019 11:54:06.554395 INFO: [NOCDAPC] D9_APC_0: 0x0
10020 11:54:06.554477 INFO: [NOCDAPC] D9_APC_1: 0xfff
10021 11:54:06.557362 INFO: [NOCDAPC] D10_APC_0: 0x0
10022 11:54:06.560839 INFO: [NOCDAPC] D10_APC_1: 0xfff
10023 11:54:06.563692 INFO: [NOCDAPC] D11_APC_0: 0x0
10024 11:54:06.567546 INFO: [NOCDAPC] D11_APC_1: 0xfff
10025 11:54:06.570532 INFO: [NOCDAPC] D12_APC_0: 0x0
10026 11:54:06.573898 INFO: [NOCDAPC] D12_APC_1: 0xfff
10027 11:54:06.577160 INFO: [NOCDAPC] D13_APC_0: 0x0
10028 11:54:06.580428 INFO: [NOCDAPC] D13_APC_1: 0xfff
10029 11:54:06.584028 INFO: [NOCDAPC] D14_APC_0: 0x0
10030 11:54:06.587235 INFO: [NOCDAPC] D14_APC_1: 0xfff
10031 11:54:06.590372 INFO: [NOCDAPC] D15_APC_0: 0x0
10032 11:54:06.594021 INFO: [NOCDAPC] D15_APC_1: 0xfff
10033 11:54:06.597590 INFO: [NOCDAPC] APC_CON: 0x4
10034 11:54:06.600446 INFO: [APUAPC] set_apusys_apc done
10035 11:54:06.600549 INFO: [DEVAPC] devapc_init done
10036 11:54:06.607418 INFO: GICv3 without legacy support detected.
10037 11:54:06.610752 INFO: ARM GICv3 driver initialized in EL3
10038 11:54:06.613970 INFO: Maximum SPI INTID supported: 639
10039 11:54:06.617139 INFO: BL31: Initializing runtime services
10040 11:54:06.624086 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10041 11:54:06.626964 INFO: SPM: enable CPC mode
10042 11:54:06.630656 INFO: mcdi ready for mcusys-off-idle and system suspend
10043 11:54:06.637275 INFO: BL31: Preparing for EL3 exit to normal world
10044 11:54:06.640881 INFO: Entry point address = 0x80000000
10045 11:54:06.640963 INFO: SPSR = 0x8
10046 11:54:06.648092
10047 11:54:06.648174
10048 11:54:06.648239
10049 11:54:06.650779 Starting depthcharge on Spherion...
10050 11:54:06.650862
10051 11:54:06.650930 Wipe memory regions:
10052 11:54:06.651008
10053 11:54:06.651665 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10054 11:54:06.651768 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10055 11:54:06.652081 Setting prompt string to ['asurada:']
10056 11:54:06.652166 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10057 11:54:06.654199 [0x00000040000000, 0x00000054600000)
10058 11:54:06.776702
10059 11:54:06.776831 [0x00000054660000, 0x00000080000000)
10060 11:54:07.037547
10061 11:54:07.037690 [0x000000821a7280, 0x000000ffe64000)
10062 11:54:07.782300
10063 11:54:07.782433 [0x00000100000000, 0x00000240000000)
10064 11:54:09.672615
10065 11:54:09.675904 Initializing XHCI USB controller at 0x11200000.
10066 11:54:10.713855
10067 11:54:10.717094 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10068 11:54:10.717187
10069 11:54:10.717281
10070 11:54:10.717370
10071 11:54:10.717693 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 11:54:10.817991 asurada: tftpboot 192.168.201.1 12066534/tftp-deploy-01176oom/kernel/image.itb 12066534/tftp-deploy-01176oom/kernel/cmdline
10074 11:54:10.818167 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 11:54:10.818286 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10076 11:54:10.822747 tftpboot 192.168.201.1 12066534/tftp-deploy-01176oom/kernel/image.ittp-deploy-01176oom/kernel/cmdline
10077 11:54:10.822862
10078 11:54:10.822957 Waiting for link
10079 11:54:10.983020
10080 11:54:10.983142 R8152: Initializing
10081 11:54:10.983227
10082 11:54:10.986286 Version 9 (ocp_data = 6010)
10083 11:54:10.986402
10084 11:54:10.989543 R8152: Done initializing
10085 11:54:10.989680
10086 11:54:10.989770 Adding net device
10087 11:54:12.862300
10088 11:54:12.862436 done.
10089 11:54:12.862502
10090 11:54:12.862563 MAC: 00:e0:4c:78:7a:aa
10091 11:54:12.862621
10092 11:54:12.865344 Sending DHCP discover... done.
10093 11:54:12.865427
10094 11:54:12.868668 Waiting for reply... done.
10095 11:54:12.868751
10096 11:54:12.872004 Sending DHCP request... done.
10097 11:54:12.872086
10098 11:54:12.872151 Waiting for reply... done.
10099 11:54:12.872212
10100 11:54:12.875622 My ip is 192.168.201.12
10101 11:54:12.875704
10102 11:54:12.878764 The DHCP server ip is 192.168.201.1
10103 11:54:12.878847
10104 11:54:12.881777 TFTP server IP predefined by user: 192.168.201.1
10105 11:54:12.881859
10106 11:54:12.888794 Bootfile predefined by user: 12066534/tftp-deploy-01176oom/kernel/image.itb
10107 11:54:12.888877
10108 11:54:12.891899 Sending tftp read request... done.
10109 11:54:12.891981
10110 11:54:12.895200 Waiting for the transfer...
10111 11:54:12.895285
10112 11:54:13.168221 00000000 ################################################################
10113 11:54:13.168353
10114 11:54:13.460782 00080000 ################################################################
10115 11:54:13.460919
10116 11:54:13.749350 00100000 ################################################################
10117 11:54:13.749494
10118 11:54:14.007753 00180000 ################################################################
10119 11:54:14.007882
10120 11:54:14.261452 00200000 ################################################################
10121 11:54:14.261604
10122 11:54:14.530468 00280000 ################################################################
10123 11:54:14.530612
10124 11:54:14.825210 00300000 ################################################################
10125 11:54:14.825356
10126 11:54:15.077101 00380000 ################################################################
10127 11:54:15.077237
10128 11:54:15.326824 00400000 ################################################################
10129 11:54:15.326977
10130 11:54:15.590007 00480000 ################################################################
10131 11:54:15.590139
10132 11:54:15.841643 00500000 ################################################################
10133 11:54:15.841792
10134 11:54:16.100844 00580000 ################################################################
10135 11:54:16.100981
10136 11:54:16.373921 00600000 ################################################################
10137 11:54:16.374087
10138 11:54:16.645782 00680000 ################################################################
10139 11:54:16.645951
10140 11:54:16.939357 00700000 ################################################################
10141 11:54:16.939492
10142 11:54:17.207992 00780000 ################################################################
10143 11:54:17.208124
10144 11:54:17.474287 00800000 ################################################################
10145 11:54:17.474462
10146 11:54:17.736761 00880000 ################################################################
10147 11:54:17.736892
10148 11:54:17.986008 00900000 ################################################################
10149 11:54:17.986167
10150 11:54:18.236536 00980000 ################################################################
10151 11:54:18.236668
10152 11:54:18.489115 00a00000 ################################################################
10153 11:54:18.489249
10154 11:54:18.773549 00a80000 ################################################################
10155 11:54:18.773730
10156 11:54:19.062419 00b00000 ################################################################
10157 11:54:19.062569
10158 11:54:19.329932 00b80000 ################################################################
10159 11:54:19.330072
10160 11:54:19.629064 00c00000 ################################################################
10161 11:54:19.629193
10162 11:54:19.929336 00c80000 ################################################################
10163 11:54:19.929471
10164 11:54:20.213654 00d00000 ################################################################
10165 11:54:20.213799
10166 11:54:20.514699 00d80000 ################################################################
10167 11:54:20.514840
10168 11:54:20.811415 00e00000 ################################################################
10169 11:54:20.811583
10170 11:54:21.105288 00e80000 ################################################################
10171 11:54:21.105428
10172 11:54:21.385534 00f00000 ################################################################
10173 11:54:21.385715
10174 11:54:21.665325 00f80000 ################################################################
10175 11:54:21.665474
10176 11:54:21.954073 01000000 ################################################################
10177 11:54:21.954216
10178 11:54:22.240810 01080000 ################################################################
10179 11:54:22.240956
10180 11:54:22.494343 01100000 ################################################################
10181 11:54:22.494481
10182 11:54:22.735280 01180000 ################################################################
10183 11:54:22.735435
10184 11:54:22.977427 01200000 ################################################################
10185 11:54:22.977583
10186 11:54:23.219082 01280000 ################################################################
10187 11:54:23.219305
10188 11:54:23.462198 01300000 ################################################################
10189 11:54:23.462356
10190 11:54:23.705197 01380000 ################################################################
10191 11:54:23.705346
10192 11:54:23.949021 01400000 ################################################################
10193 11:54:23.949179
10194 11:54:24.192349 01480000 ################################################################
10195 11:54:24.192505
10196 11:54:24.436349 01500000 ################################################################
10197 11:54:24.436488
10198 11:54:24.680281 01580000 ################################################################
10199 11:54:24.680415
10200 11:54:24.923953 01600000 ################################################################
10201 11:54:24.924137
10202 11:54:25.167629 01680000 ################################################################
10203 11:54:25.167799
10204 11:54:25.410240 01700000 ################################################################
10205 11:54:25.410380
10206 11:54:25.653153 01780000 ################################################################
10207 11:54:25.653312
10208 11:54:25.896068 01800000 ################################################################
10209 11:54:25.896198
10210 11:54:26.138640 01880000 ################################################################
10211 11:54:26.138808
10212 11:54:26.380252 01900000 ################################################################
10213 11:54:26.380387
10214 11:54:26.623586 01980000 ################################################################
10215 11:54:26.623752
10216 11:54:26.866696 01a00000 ################################################################
10217 11:54:26.866861
10218 11:54:27.108811 01a80000 ################################################################
10219 11:54:27.108976
10220 11:54:27.351702 01b00000 ################################################################
10221 11:54:27.351866
10222 11:54:27.374869 01b80000 ####### done.
10223 11:54:27.374987
10224 11:54:27.378209 The bootfile was 28886530 bytes long.
10225 11:54:27.378309
10226 11:54:27.381913 Sending tftp read request... done.
10227 11:54:27.382016
10228 11:54:27.384884 Waiting for the transfer...
10229 11:54:27.384991
10230 11:54:27.385085 00000000 # done.
10231 11:54:27.385187
10232 11:54:27.394581 Command line loaded dynamically from TFTP file: 12066534/tftp-deploy-01176oom/kernel/cmdline
10233 11:54:27.394696
10234 11:54:27.414906 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10235 11:54:27.415028
10236 11:54:27.418241 Loading FIT.
10237 11:54:27.418342
10238 11:54:27.421190 Image ramdisk-1 has 17790036 bytes.
10239 11:54:27.421301
10240 11:54:27.421403 Image fdt-1 has 47278 bytes.
10241 11:54:27.421495
10242 11:54:27.424470 Image kernel-1 has 11047184 bytes.
10243 11:54:27.424578
10244 11:54:27.434596 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10245 11:54:27.434709
10246 11:54:27.451016 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10247 11:54:27.451135
10248 11:54:27.457398 Choosing best match conf-1 for compat google,spherion-rev2.
10249 11:54:27.461327
10250 11:54:27.465878 Connected to device vid:did:rid of 1ae0:0028:00
10251 11:54:27.474246
10252 11:54:27.477404 tpm_get_response: command 0x17b, return code 0x0
10253 11:54:27.477514
10254 11:54:27.483858 ec_init: CrosEC protocol v3 supported (256, 248)
10255 11:54:27.483971
10256 11:54:27.487392 tpm_cleanup: add release locality here.
10257 11:54:27.487498
10258 11:54:27.490846 Shutting down all USB controllers.
10259 11:54:27.490963
10260 11:54:27.494029 Removing current net device
10261 11:54:27.494131
10262 11:54:27.497532 Exiting depthcharge with code 4 at timestamp: 50081556
10263 11:54:27.497678
10264 11:54:27.503857 LZMA decompressing kernel-1 to 0x821a6718
10265 11:54:27.503965
10266 11:54:27.506991 LZMA decompressing kernel-1 to 0x40000000
10267 11:54:28.894696
10268 11:54:28.894869 jumping to kernel
10269 11:54:28.895703 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10270 11:54:28.895838 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10271 11:54:28.895944 Setting prompt string to ['Linux version [0-9]']
10272 11:54:28.896053 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10273 11:54:28.896158 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10274 11:54:28.977001
10275 11:54:28.980712 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10276 11:54:28.984093 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10277 11:54:28.984212 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10278 11:54:28.984313 Setting prompt string to []
10279 11:54:28.984425 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10280 11:54:28.984538 Using line separator: #'\n'#
10281 11:54:28.984631 No login prompt set.
10282 11:54:28.984726 Parsing kernel messages
10283 11:54:28.984820 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10284 11:54:28.984997 [login-action] Waiting for messages, (timeout 00:04:03)
10285 11:54:29.003682 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10286 11:54:29.006969 [ 0.000000] random: crng init done
10287 11:54:29.013893 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10288 11:54:29.014002 [ 0.000000] efi: UEFI not found.
10289 11:54:29.023512 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10290 11:54:29.029823 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10291 11:54:29.039986 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10292 11:54:29.049741 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10293 11:54:29.057164 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10294 11:54:29.063238 [ 0.000000] printk: bootconsole [mtk8250] enabled
10295 11:54:29.069723 [ 0.000000] NUMA: No NUMA configuration found
10296 11:54:29.076176 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10297 11:54:29.079375 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10298 11:54:29.082688 [ 0.000000] Zone ranges:
10299 11:54:29.089972 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10300 11:54:29.092595 [ 0.000000] DMA32 empty
10301 11:54:29.099701 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10302 11:54:29.102957 [ 0.000000] Movable zone start for each node
10303 11:54:29.105843 [ 0.000000] Early memory node ranges
10304 11:54:29.112666 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10305 11:54:29.119172 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10306 11:54:29.126141 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10307 11:54:29.132384 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10308 11:54:29.139224 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10309 11:54:29.145560 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10310 11:54:29.201916 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10311 11:54:29.208157 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10312 11:54:29.214871 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10313 11:54:29.217990 [ 0.000000] psci: probing for conduit method from DT.
10314 11:54:29.224893 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10315 11:54:29.227901 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10316 11:54:29.234525 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10317 11:54:29.237738 [ 0.000000] psci: SMC Calling Convention v1.2
10318 11:54:29.244621 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10319 11:54:29.247752 [ 0.000000] Detected VIPT I-cache on CPU0
10320 11:54:29.254369 [ 0.000000] CPU features: detected: GIC system register CPU interface
10321 11:54:29.261237 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10322 11:54:29.267658 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10323 11:54:29.274284 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10324 11:54:29.283999 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10325 11:54:29.291040 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10326 11:54:29.294180 [ 0.000000] alternatives: applying boot alternatives
10327 11:54:29.300668 [ 0.000000] Fallback order for Node 0: 0
10328 11:54:29.307187 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10329 11:54:29.310717 [ 0.000000] Policy zone: Normal
10330 11:54:29.333320 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10331 11:54:29.343489 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10332 11:54:29.354157 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10333 11:54:29.364386 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10334 11:54:29.370728 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10335 11:54:29.374550 <6>[ 0.000000] software IO TLB: area num 8.
10336 11:54:29.431147 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10337 11:54:29.580995 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10338 11:54:29.587787 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10339 11:54:29.594150 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10340 11:54:29.597641 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10341 11:54:29.604238 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10342 11:54:29.610719 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10343 11:54:29.613787 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10344 11:54:29.623832 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10345 11:54:29.630777 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10346 11:54:29.633735 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10347 11:54:29.641725 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10348 11:54:29.644977 <6>[ 0.000000] GICv3: 608 SPIs implemented
10349 11:54:29.651540 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10350 11:54:29.655130 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10351 11:54:29.661389 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10352 11:54:29.667966 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10353 11:54:29.677866 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10354 11:54:29.691199 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10355 11:54:29.698126 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10356 11:54:29.707009 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10357 11:54:29.720657 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10358 11:54:29.726871 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10359 11:54:29.733877 <6>[ 0.009178] Console: colour dummy device 80x25
10360 11:54:29.744046 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10361 11:54:29.750181 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10362 11:54:29.753355 <6>[ 0.029217] LSM: Security Framework initializing
10363 11:54:29.760360 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10364 11:54:29.770342 <6>[ 0.041967] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10365 11:54:29.776959 <6>[ 0.051432] cblist_init_generic: Setting adjustable number of callback queues.
10366 11:54:29.783227 <6>[ 0.058877] cblist_init_generic: Setting shift to 3 and lim to 1.
10367 11:54:29.793528 <6>[ 0.065254] cblist_init_generic: Setting adjustable number of callback queues.
10368 11:54:29.799887 <6>[ 0.072681] cblist_init_generic: Setting shift to 3 and lim to 1.
10369 11:54:29.803813 <6>[ 0.079080] rcu: Hierarchical SRCU implementation.
10370 11:54:29.809942 <6>[ 0.084096] rcu: Max phase no-delay instances is 1000.
10371 11:54:29.816351 <6>[ 0.091116] EFI services will not be available.
10372 11:54:29.819741 <6>[ 0.096072] smp: Bringing up secondary CPUs ...
10373 11:54:29.828268 <6>[ 0.101116] Detected VIPT I-cache on CPU1
10374 11:54:29.834605 <6>[ 0.101185] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10375 11:54:29.841322 <6>[ 0.101216] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10376 11:54:29.844554 <6>[ 0.101557] Detected VIPT I-cache on CPU2
10377 11:54:29.851103 <6>[ 0.101609] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10378 11:54:29.857898 <6>[ 0.101627] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10379 11:54:29.864528 <6>[ 0.101889] Detected VIPT I-cache on CPU3
10380 11:54:29.871114 <6>[ 0.101936] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10381 11:54:29.877916 <6>[ 0.101949] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10382 11:54:29.880983 <6>[ 0.102253] CPU features: detected: Spectre-v4
10383 11:54:29.888242 <6>[ 0.102261] CPU features: detected: Spectre-BHB
10384 11:54:29.891076 <6>[ 0.102266] Detected PIPT I-cache on CPU4
10385 11:54:29.897887 <6>[ 0.102323] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10386 11:54:29.904260 <6>[ 0.102339] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10387 11:54:29.910815 <6>[ 0.102630] Detected PIPT I-cache on CPU5
10388 11:54:29.917393 <6>[ 0.102694] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10389 11:54:29.923842 <6>[ 0.102710] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10390 11:54:29.927444 <6>[ 0.102990] Detected PIPT I-cache on CPU6
10391 11:54:29.933813 <6>[ 0.103056] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10392 11:54:29.940745 <6>[ 0.103072] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10393 11:54:29.947080 <6>[ 0.103366] Detected PIPT I-cache on CPU7
10394 11:54:29.953876 <6>[ 0.103429] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10395 11:54:29.960370 <6>[ 0.103445] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10396 11:54:29.963623 <6>[ 0.103493] smp: Brought up 1 node, 8 CPUs
10397 11:54:29.970632 <6>[ 0.244989] SMP: Total of 8 processors activated.
10398 11:54:29.973632 <6>[ 0.249910] CPU features: detected: 32-bit EL0 Support
10399 11:54:29.983480 <6>[ 0.255273] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10400 11:54:29.990403 <6>[ 0.264073] CPU features: detected: Common not Private translations
10401 11:54:29.996712 <6>[ 0.270549] CPU features: detected: CRC32 instructions
10402 11:54:30.000132 <6>[ 0.275901] CPU features: detected: RCpc load-acquire (LDAPR)
10403 11:54:30.006499 <6>[ 0.281897] CPU features: detected: LSE atomic instructions
10404 11:54:30.013345 <6>[ 0.287678] CPU features: detected: Privileged Access Never
10405 11:54:30.019770 <6>[ 0.293458] CPU features: detected: RAS Extension Support
10406 11:54:30.027206 <6>[ 0.299067] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10407 11:54:30.030005 <6>[ 0.306285] CPU: All CPU(s) started at EL2
10408 11:54:30.036748 <6>[ 0.310628] alternatives: applying system-wide alternatives
10409 11:54:30.045920 <6>[ 0.321330] devtmpfs: initialized
10410 11:54:30.061243 <6>[ 0.330264] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10411 11:54:30.068020 <6>[ 0.340227] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10412 11:54:30.074511 <6>[ 0.348468] pinctrl core: initialized pinctrl subsystem
10413 11:54:30.078083 <6>[ 0.355135] DMI not present or invalid.
10414 11:54:30.084566 <6>[ 0.359547] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10415 11:54:30.094821 <6>[ 0.366400] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10416 11:54:30.101337 <6>[ 0.373982] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10417 11:54:30.110991 <6>[ 0.382205] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10418 11:54:30.114447 <6>[ 0.390452] audit: initializing netlink subsys (disabled)
10419 11:54:30.124135 <5>[ 0.396144] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10420 11:54:30.131085 <6>[ 0.396840] thermal_sys: Registered thermal governor 'step_wise'
10421 11:54:30.137464 <6>[ 0.404110] thermal_sys: Registered thermal governor 'power_allocator'
10422 11:54:30.140941 <6>[ 0.410366] cpuidle: using governor menu
10423 11:54:30.147215 <6>[ 0.421328] NET: Registered PF_QIPCRTR protocol family
10424 11:54:30.154025 <6>[ 0.426821] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10425 11:54:30.160765 <6>[ 0.433923] ASID allocator initialised with 32768 entries
10426 11:54:30.164029 <6>[ 0.440479] Serial: AMBA PL011 UART driver
10427 11:54:30.173688 <4>[ 0.449268] Trying to register duplicate clock ID: 134
10428 11:54:30.227916 <6>[ 0.506876] KASLR enabled
10429 11:54:30.242461 <6>[ 0.514576] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10430 11:54:30.249290 <6>[ 0.521590] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10431 11:54:30.255691 <6>[ 0.528078] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10432 11:54:30.261910 <6>[ 0.535083] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10433 11:54:30.268807 <6>[ 0.541569] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10434 11:54:30.275339 <6>[ 0.548573] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10435 11:54:30.282062 <6>[ 0.555059] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10436 11:54:30.288317 <6>[ 0.562062] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10437 11:54:30.291991 <6>[ 0.569559] ACPI: Interpreter disabled.
10438 11:54:30.300776 <6>[ 0.575977] iommu: Default domain type: Translated
10439 11:54:30.307057 <6>[ 0.581088] iommu: DMA domain TLB invalidation policy: strict mode
10440 11:54:30.310873 <5>[ 0.587743] SCSI subsystem initialized
10441 11:54:30.317250 <6>[ 0.591906] usbcore: registered new interface driver usbfs
10442 11:54:30.323707 <6>[ 0.597639] usbcore: registered new interface driver hub
10443 11:54:30.327231 <6>[ 0.603193] usbcore: registered new device driver usb
10444 11:54:30.333594 <6>[ 0.609295] pps_core: LinuxPPS API ver. 1 registered
10445 11:54:30.343802 <6>[ 0.614490] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10446 11:54:30.347004 <6>[ 0.623838] PTP clock support registered
10447 11:54:30.350152 <6>[ 0.628081] EDAC MC: Ver: 3.0.0
10448 11:54:30.358044 <6>[ 0.633256] FPGA manager framework
10449 11:54:30.361024 <6>[ 0.636935] Advanced Linux Sound Architecture Driver Initialized.
10450 11:54:30.364735 <6>[ 0.643707] vgaarb: loaded
10451 11:54:30.371410 <6>[ 0.646880] clocksource: Switched to clocksource arch_sys_counter
10452 11:54:30.378191 <5>[ 0.653312] VFS: Disk quotas dquot_6.6.0
10453 11:54:30.384687 <6>[ 0.657498] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10454 11:54:30.387911 <6>[ 0.664685] pnp: PnP ACPI: disabled
10455 11:54:30.395917 <6>[ 0.671340] NET: Registered PF_INET protocol family
10456 11:54:30.405970 <6>[ 0.676931] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10457 11:54:30.417254 <6>[ 0.689232] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10458 11:54:30.427272 <6>[ 0.698046] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10459 11:54:30.433587 <6>[ 0.706018] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10460 11:54:30.440395 <6>[ 0.714715] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10461 11:54:30.452592 <6>[ 0.724478] TCP: Hash tables configured (established 65536 bind 65536)
10462 11:54:30.458831 <6>[ 0.731337] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10463 11:54:30.465337 <6>[ 0.738540] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10464 11:54:30.472340 <6>[ 0.746231] NET: Registered PF_UNIX/PF_LOCAL protocol family
10465 11:54:30.478858 <6>[ 0.752376] RPC: Registered named UNIX socket transport module.
10466 11:54:30.482004 <6>[ 0.758530] RPC: Registered udp transport module.
10467 11:54:30.488888 <6>[ 0.763462] RPC: Registered tcp transport module.
10468 11:54:30.495305 <6>[ 0.768395] RPC: Registered tcp NFSv4.1 backchannel transport module.
10469 11:54:30.498713 <6>[ 0.775063] PCI: CLS 0 bytes, default 64
10470 11:54:30.502118 <6>[ 0.779405] Unpacking initramfs...
10471 11:54:30.512335 <6>[ 0.783200] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10472 11:54:30.518773 <6>[ 0.791827] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10473 11:54:30.525281 <6>[ 0.800647] kvm [1]: IPA Size Limit: 40 bits
10474 11:54:30.528718 <6>[ 0.805171] kvm [1]: GICv3: no GICV resource entry
10475 11:54:30.535618 <6>[ 0.810194] kvm [1]: disabling GICv2 emulation
10476 11:54:30.542224 <6>[ 0.814885] kvm [1]: GIC system register CPU interface enabled
10477 11:54:30.545074 <6>[ 0.821050] kvm [1]: vgic interrupt IRQ18
10478 11:54:30.548882 <6>[ 0.825420] kvm [1]: VHE mode initialized successfully
10479 11:54:30.556458 <5>[ 0.831860] Initialise system trusted keyrings
10480 11:54:30.562801 <6>[ 0.836621] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10481 11:54:30.571413 <6>[ 0.846579] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10482 11:54:30.577813 <5>[ 0.852938] NFS: Registering the id_resolver key type
10483 11:54:30.581371 <5>[ 0.858239] Key type id_resolver registered
10484 11:54:30.588029 <5>[ 0.862655] Key type id_legacy registered
10485 11:54:30.594399 <6>[ 0.866934] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10486 11:54:30.601254 <6>[ 0.873856] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10487 11:54:30.607598 <6>[ 0.881613] 9p: Installing v9fs 9p2000 file system support
10488 11:54:30.643815 <5>[ 0.919179] Key type asymmetric registered
10489 11:54:30.647584 <5>[ 0.923509] Asymmetric key parser 'x509' registered
10490 11:54:30.657104 <6>[ 0.928652] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10491 11:54:30.660238 <6>[ 0.936265] io scheduler mq-deadline registered
10492 11:54:30.663505 <6>[ 0.941029] io scheduler kyber registered
10493 11:54:30.682729 <6>[ 0.958191] EINJ: ACPI disabled.
10494 11:54:30.715566 <4>[ 0.984295] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10495 11:54:30.725469 <4>[ 0.994986] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10496 11:54:30.740469 <6>[ 1.015893] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10497 11:54:30.748051 <6>[ 1.023893] printk: console [ttyS0] disabled
10498 11:54:30.776651 <6>[ 1.048540] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10499 11:54:30.782930 <6>[ 1.058018] printk: console [ttyS0] enabled
10500 11:54:30.785979 <6>[ 1.058018] printk: console [ttyS0] enabled
10501 11:54:30.792738 <6>[ 1.066911] printk: bootconsole [mtk8250] disabled
10502 11:54:30.796108 <6>[ 1.066911] printk: bootconsole [mtk8250] disabled
10503 11:54:30.802732 <6>[ 1.078097] SuperH (H)SCI(F) driver initialized
10504 11:54:30.805964 <6>[ 1.083386] msm_serial: driver initialized
10505 11:54:30.820221 <6>[ 1.092392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10506 11:54:30.830110 <6>[ 1.100939] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10507 11:54:30.836460 <6>[ 1.109481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10508 11:54:30.846834 <6>[ 1.118121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10509 11:54:30.856388 <6>[ 1.126830] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10510 11:54:30.863369 <6>[ 1.135544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10511 11:54:30.873005 <6>[ 1.144084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10512 11:54:30.879910 <6>[ 1.152894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10513 11:54:30.889484 <6>[ 1.161439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10514 11:54:30.901504 <6>[ 1.177008] loop: module loaded
10515 11:54:30.908081 <6>[ 1.183068] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10516 11:54:30.930821 <4>[ 1.206464] mtk-pmic-keys: Failed to locate of_node [id: -1]
10517 11:54:30.937573 <6>[ 1.213386] megasas: 07.719.03.00-rc1
10518 11:54:30.947167 <6>[ 1.222922] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10519 11:54:30.955069 <6>[ 1.230257] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10520 11:54:30.971288 <6>[ 1.246829] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10521 11:54:31.028697 <6>[ 1.296786] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10522 11:54:31.242739 <6>[ 1.517707] Freeing initrd memory: 17372K
10523 11:54:31.253451 <6>[ 1.528195] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10524 11:54:31.264056 <6>[ 1.539084] tun: Universal TUN/TAP device driver, 1.6
10525 11:54:31.267131 <6>[ 1.545139] thunder_xcv, ver 1.0
10526 11:54:31.270717 <6>[ 1.548643] thunder_bgx, ver 1.0
10527 11:54:31.273760 <6>[ 1.552138] nicpf, ver 1.0
10528 11:54:31.285151 <6>[ 1.556161] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10529 11:54:31.287663 <6>[ 1.563636] hns3: Copyright (c) 2017 Huawei Corporation.
10530 11:54:31.291621 <6>[ 1.569222] hclge is initializing
10531 11:54:31.297855 <6>[ 1.572801] e1000: Intel(R) PRO/1000 Network Driver
10532 11:54:31.304953 <6>[ 1.577930] e1000: Copyright (c) 1999-2006 Intel Corporation.
10533 11:54:31.307954 <6>[ 1.583942] e1000e: Intel(R) PRO/1000 Network Driver
10534 11:54:31.314239 <6>[ 1.589157] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10535 11:54:31.320993 <6>[ 1.595346] igb: Intel(R) Gigabit Ethernet Network Driver
10536 11:54:31.327717 <6>[ 1.600996] igb: Copyright (c) 2007-2014 Intel Corporation.
10537 11:54:31.334087 <6>[ 1.606832] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10538 11:54:31.341308 <6>[ 1.613349] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10539 11:54:31.344175 <6>[ 1.619812] sky2: driver version 1.30
10540 11:54:31.350723 <6>[ 1.624811] VFIO - User Level meta-driver version: 0.3
10541 11:54:31.357719 <6>[ 1.633080] usbcore: registered new interface driver usb-storage
10542 11:54:31.364541 <6>[ 1.639525] usbcore: registered new device driver onboard-usb-hub
10543 11:54:31.373423 <6>[ 1.648690] mt6397-rtc mt6359-rtc: registered as rtc0
10544 11:54:31.383935 <6>[ 1.654158] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:52:20 UTC (1700740340)
10545 11:54:31.386735 <6>[ 1.663737] i2c_dev: i2c /dev entries driver
10546 11:54:31.403791 <6>[ 1.675469] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10547 11:54:31.423936 <6>[ 1.698466] cpu cpu0: EM: created perf domain
10548 11:54:31.426551 <6>[ 1.703403] cpu cpu4: EM: created perf domain
10549 11:54:31.433526 <6>[ 1.708982] sdhci: Secure Digital Host Controller Interface driver
10550 11:54:31.440888 <6>[ 1.715414] sdhci: Copyright(c) Pierre Ossman
10551 11:54:31.447574 <6>[ 1.720370] Synopsys Designware Multimedia Card Interface Driver
10552 11:54:31.454215 <6>[ 1.727023] sdhci-pltfm: SDHCI platform and OF driver helper
10553 11:54:31.457728 <6>[ 1.727056] mmc0: CQHCI version 5.10
10554 11:54:31.464069 <6>[ 1.737366] ledtrig-cpu: registered to indicate activity on CPUs
10555 11:54:31.471238 <6>[ 1.744430] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10556 11:54:31.477932 <6>[ 1.751487] usbcore: registered new interface driver usbhid
10557 11:54:31.480867 <6>[ 1.757311] usbhid: USB HID core driver
10558 11:54:31.487302 <6>[ 1.761510] spi_master spi0: will run message pump with realtime priority
10559 11:54:31.534835 <6>[ 1.803285] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10560 11:54:31.554249 <6>[ 1.819519] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10561 11:54:31.557998 <6>[ 1.834371] mmc0: Command Queue Engine enabled
10562 11:54:31.564450 <6>[ 1.834412] cros-ec-spi spi0.0: Chrome EC device registered
10563 11:54:31.571342 <6>[ 1.839127] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10564 11:54:31.578540 <6>[ 1.852328] mmcblk0: mmc0:0001 DA4128 116 GiB
10565 11:54:31.588583 <6>[ 1.859260] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10566 11:54:31.594658 <6>[ 1.867536] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10567 11:54:31.598359 <6>[ 1.869690] NET: Registered PF_PACKET protocol family
10568 11:54:31.604825 <6>[ 1.875907] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10569 11:54:31.608867 <6>[ 1.879865] 9pnet: Installing 9P2000 support
10570 11:54:31.614948 <6>[ 1.885731] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10571 11:54:31.618316 <5>[ 1.889565] Key type dns_resolver registered
10572 11:54:31.624865 <6>[ 1.895479] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10573 11:54:31.631232 <6>[ 1.899709] registered taskstats version 1
10574 11:54:31.634719 <5>[ 1.910179] Loading compiled-in X.509 certificates
10575 11:54:31.664533 <4>[ 1.932981] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10576 11:54:31.674989 <4>[ 1.943718] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 11:54:31.681191 <3>[ 1.954265] debugfs: File 'uA_load' in directory '/' already present!
10578 11:54:31.688281 <3>[ 1.960971] debugfs: File 'min_uV' in directory '/' already present!
10579 11:54:31.695116 <3>[ 1.967625] debugfs: File 'max_uV' in directory '/' already present!
10580 11:54:31.701299 <3>[ 1.974236] debugfs: File 'constraint_flags' in directory '/' already present!
10581 11:54:31.712608 <3>[ 1.983887] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10582 11:54:31.722257 <6>[ 1.997320] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10583 11:54:31.729401 <6>[ 2.004122] xhci-mtk 11200000.usb: xHCI Host Controller
10584 11:54:31.735744 <6>[ 2.009627] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10585 11:54:31.746102 <6>[ 2.017484] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10586 11:54:31.752748 <6>[ 2.026902] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10587 11:54:31.759014 <6>[ 2.032967] xhci-mtk 11200000.usb: xHCI Host Controller
10588 11:54:31.765985 <6>[ 2.038441] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10589 11:54:31.772737 <6>[ 2.046086] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10590 11:54:31.779570 <6>[ 2.053744] hub 1-0:1.0: USB hub found
10591 11:54:31.782534 <6>[ 2.057751] hub 1-0:1.0: 1 port detected
10592 11:54:31.789674 <6>[ 2.062016] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10593 11:54:31.796300 <6>[ 2.070567] hub 2-0:1.0: USB hub found
10594 11:54:31.799379 <6>[ 2.074571] hub 2-0:1.0: 1 port detected
10595 11:54:31.807589 <6>[ 2.082643] mtk-msdc 11f70000.mmc: Got CD GPIO
10596 11:54:31.817891 <6>[ 2.089617] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10597 11:54:31.824516 <6>[ 2.097659] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10598 11:54:31.834087 <4>[ 2.105588] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10599 11:54:31.844628 <6>[ 2.115116] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10600 11:54:31.850830 <6>[ 2.123191] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10601 11:54:31.857320 <6>[ 2.131212] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10602 11:54:31.867453 <6>[ 2.139135] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10603 11:54:31.874423 <6>[ 2.146952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10604 11:54:31.884612 <6>[ 2.154771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10605 11:54:31.894174 <6>[ 2.165056] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10606 11:54:31.901078 <6>[ 2.173412] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10607 11:54:31.910796 <6>[ 2.181758] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10608 11:54:31.917473 <6>[ 2.190097] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10609 11:54:31.927367 <6>[ 2.198435] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10610 11:54:31.933954 <6>[ 2.206774] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10611 11:54:31.943990 <6>[ 2.215114] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10612 11:54:31.951128 <6>[ 2.223453] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10613 11:54:31.961268 <6>[ 2.231791] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10614 11:54:31.967449 <6>[ 2.240129] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10615 11:54:31.977746 <6>[ 2.248468] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10616 11:54:31.984545 <6>[ 2.256815] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10617 11:54:31.994412 <6>[ 2.265153] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10618 11:54:32.001062 <6>[ 2.273492] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10619 11:54:32.010749 <6>[ 2.281831] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10620 11:54:32.017166 <6>[ 2.290611] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10621 11:54:32.024239 <6>[ 2.297861] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10622 11:54:32.030752 <6>[ 2.304728] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10623 11:54:32.037559 <6>[ 2.311579] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10624 11:54:32.044020 <6>[ 2.318604] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10625 11:54:32.053957 <6>[ 2.325484] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10626 11:54:32.064370 <6>[ 2.334611] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10627 11:54:32.074263 <6>[ 2.343729] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10628 11:54:32.083584 <6>[ 2.353022] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10629 11:54:32.090686 <6>[ 2.362493] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10630 11:54:32.100408 <6>[ 2.371960] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10631 11:54:32.110519 <6>[ 2.381081] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10632 11:54:32.120432 <6>[ 2.390551] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10633 11:54:32.130533 <6>[ 2.399669] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10634 11:54:32.140660 <6>[ 2.408962] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10635 11:54:32.150232 <6>[ 2.419123] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10636 11:54:32.160342 <6>[ 2.430743] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10637 11:54:32.166205 <6>[ 2.440476] Trying to probe devices needed for running init ...
10638 11:54:32.187579 <6>[ 2.459423] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10639 11:54:32.216036 <6>[ 2.490830] hub 2-1:1.0: USB hub found
10640 11:54:32.219401 <6>[ 2.495324] hub 2-1:1.0: 3 ports detected
10641 11:54:32.227921 <6>[ 2.502904] hub 2-1:1.0: USB hub found
10642 11:54:32.230876 <6>[ 2.507274] hub 2-1:1.0: 3 ports detected
10643 11:54:32.342346 <6>[ 2.611158] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10644 11:54:32.493022 <6>[ 2.768929] hub 1-1:1.0: USB hub found
10645 11:54:32.496632 <6>[ 2.773448] hub 1-1:1.0: 4 ports detected
10646 11:54:32.507069 <6>[ 2.782371] hub 1-1:1.0: USB hub found
10647 11:54:32.509807 <6>[ 2.787092] hub 1-1:1.0: 4 ports detected
10648 11:54:32.579279 <6>[ 2.851430] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10649 11:54:32.831266 <6>[ 3.103169] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10650 11:54:32.963926 <6>[ 3.239152] hub 1-1.4:1.0: USB hub found
10651 11:54:32.967179 <6>[ 3.243834] hub 1-1.4:1.0: 2 ports detected
10652 11:54:32.977039 <6>[ 3.252673] hub 1-1.4:1.0: USB hub found
10653 11:54:32.980833 <6>[ 3.257284] hub 1-1.4:1.0: 2 ports detected
10654 11:54:33.278832 <6>[ 3.551170] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10655 11:54:33.471066 <6>[ 3.743171] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10656 11:54:44.456514 <6>[ 14.736263] ALSA device list:
10657 11:54:44.462676 <6>[ 14.739563] No soundcards found.
10658 11:54:44.471351 <6>[ 14.747610] Freeing unused kernel memory: 8384K
10659 11:54:44.474082 <6>[ 14.752610] Run /init as init process
10660 11:54:44.485995 Loading, please wait...
10661 11:54:44.506267 Starting version 247.3-7+deb11u2
10662 11:54:44.690144 <6>[ 14.963677] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10663 11:54:44.696801 <3>[ 14.968275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 11:54:44.703724 <6>[ 14.977114] remoteproc remoteproc0: scp is available
10665 11:54:44.710457 <3>[ 14.979485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 11:54:44.717019 <6>[ 14.985229] remoteproc remoteproc0: powering up scp
10667 11:54:44.723891 <3>[ 14.992871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 11:54:44.733675 <6>[ 14.998007] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10669 11:54:44.740407 <3>[ 15.006538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 11:54:44.747470 <6>[ 15.014564] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10671 11:54:44.753487 <3>[ 15.023981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 11:54:44.760245 <6>[ 15.025119] mc: Linux media interface: v0.10
10673 11:54:44.766736 <6>[ 15.025755] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10674 11:54:44.776735 <6>[ 15.025770] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10675 11:54:44.783109 <6>[ 15.025776] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10676 11:54:44.793543 <3>[ 15.027789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 11:54:44.799950 <3>[ 15.027863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 11:54:44.809510 <3>[ 15.027868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 11:54:44.816248 <6>[ 15.037391] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10680 11:54:44.822729 <4>[ 15.038735] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10681 11:54:44.829844 <4>[ 15.043444] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 11:54:44.839389 <3>[ 15.075824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 11:54:44.842933 <6>[ 15.078752] usbcore: registered new interface driver r8152
10684 11:54:44.849553 <6>[ 15.080701] videodev: Linux video capture interface: v2.00
10685 11:54:44.859511 <3>[ 15.132227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 11:54:44.866012 <3>[ 15.140367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 11:54:44.876254 <3>[ 15.148477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 11:54:44.882751 <4>[ 15.148493] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10689 11:54:44.889943 <4>[ 15.148493] Fallback method does not support PEC.
10690 11:54:44.895985 <6>[ 15.153723] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10691 11:54:44.902600 <6>[ 15.153728] pci_bus 0000:00: root bus resource [bus 00-ff]
10692 11:54:44.909289 <6>[ 15.153733] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10693 11:54:44.919245 <6>[ 15.153735] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10694 11:54:44.926094 <6>[ 15.153764] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10695 11:54:44.932761 <6>[ 15.153778] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10696 11:54:44.936228 <6>[ 15.153851] pci 0000:00:00.0: supports D1 D2
10697 11:54:44.942789 <6>[ 15.153853] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10698 11:54:44.949067 <6>[ 15.153990] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10699 11:54:44.959023 <6>[ 15.154030] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10700 11:54:44.966189 <6>[ 15.154041] remoteproc remoteproc0: remote processor scp is now up
10701 11:54:44.972364 <6>[ 15.154885] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10702 11:54:44.978958 <6>[ 15.154971] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10703 11:54:44.988983 <6>[ 15.154996] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10704 11:54:44.996147 <6>[ 15.155011] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10705 11:54:45.002832 <6>[ 15.155026] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10706 11:54:45.005879 <6>[ 15.155128] pci 0000:01:00.0: supports D1 D2
10707 11:54:45.012847 <6>[ 15.155130] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10708 11:54:45.022668 <3>[ 15.156752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 11:54:45.030056 <6>[ 15.167035] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10710 11:54:45.036592 <6>[ 15.167060] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10711 11:54:45.043778 <6>[ 15.167063] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10712 11:54:45.053212 <6>[ 15.167070] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10713 11:54:45.059988 <6>[ 15.167083] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10714 11:54:45.070204 <6>[ 15.167096] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10715 11:54:45.073235 <6>[ 15.167108] pci 0000:00:00.0: PCI bridge to [bus 01]
10716 11:54:45.083200 <6>[ 15.167114] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10717 11:54:45.089526 <6>[ 15.167259] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10718 11:54:45.096092 <6>[ 15.167283] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10719 11:54:45.103001 <6>[ 15.167790] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10720 11:54:45.106189 <6>[ 15.168235] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10721 11:54:45.116464 <6>[ 15.171438] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10722 11:54:45.122685 <3>[ 15.177320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 11:54:45.132763 <6>[ 15.185478] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10724 11:54:45.139600 <3>[ 15.190057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 11:54:45.149660 <6>[ 15.190397] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10726 11:54:45.159892 <4>[ 15.194574] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10727 11:54:45.166264 <4>[ 15.194584] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10728 11:54:45.176660 <6>[ 15.199080] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10729 11:54:45.186331 <6>[ 15.199361] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10730 11:54:45.193420 <5>[ 15.216229] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10731 11:54:45.203086 <3>[ 15.218257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 11:54:45.206129 <6>[ 15.225883] usbcore: registered new interface driver cdc_ether
10733 11:54:45.216387 <3>[ 15.232294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 11:54:45.223217 <5>[ 15.242360] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10735 11:54:45.229551 <3>[ 15.247345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 11:54:45.236203 <6>[ 15.248031] Bluetooth: Core ver 2.22
10737 11:54:45.239797 <6>[ 15.248212] NET: Registered PF_BLUETOOTH protocol family
10738 11:54:45.246056 <6>[ 15.248218] Bluetooth: HCI device and connection manager initialized
10739 11:54:45.253281 <6>[ 15.248247] Bluetooth: HCI socket layer initialized
10740 11:54:45.256495 <6>[ 15.248253] Bluetooth: L2CAP socket layer initialized
10741 11:54:45.262779 <6>[ 15.248273] Bluetooth: SCO socket layer initialized
10742 11:54:45.273004 <4>[ 15.256034] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10743 11:54:45.279896 <6>[ 15.263753] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10744 11:54:45.282764 <6>[ 15.263854] usbcore: registered new interface driver r8153_ecm
10745 11:54:45.289915 <6>[ 15.269318] cfg80211: failed to load regulatory.db
10746 11:54:45.302907 <6>[ 15.278619] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10747 11:54:45.306365 <6>[ 15.291045] r8152 2-1.3:1.0 eth0: v1.12.13
10748 11:54:45.312887 <6>[ 15.296021] usbcore: registered new interface driver uvcvideo
10749 11:54:45.319307 <6>[ 15.297269] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10750 11:54:45.326439 <3>[ 15.307864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10751 11:54:45.339177 <4>[ 15.312159] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10752 11:54:45.342658 <6>[ 15.312728] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10753 11:54:45.349410 <6>[ 15.312887] usbcore: registered new interface driver btusb
10754 11:54:45.355837 <6>[ 15.353472] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10755 11:54:45.362511 <3>[ 15.356058] Bluetooth: hci0: Failed to load firmware file (-2)
10756 11:54:45.369141 <6>[ 15.364069] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10757 11:54:45.375831 <3>[ 15.370383] Bluetooth: hci0: Failed to set up firmware (-2)
10758 11:54:45.382330 <6>[ 15.397799] mt7921e 0000:01:00.0: ASIC revision: 79610010
10759 11:54:45.392798 <4>[ 15.405861] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10760 11:54:45.399204 <3>[ 15.427145] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10761 11:54:45.412443 <4>[ 15.505900] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10762 11:54:45.415513 Begin: Loading essential drivers ... done.
10763 11:54:45.419115 Begin: Running /scripts/init-premount ... done.
10764 11:54:45.428969 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10765 11:54:45.435819 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10766 11:54:45.439153 Device /sys/class/net/enx00e04c787aaa found
10767 11:54:45.442368 done.
10768 11:54:45.481564 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10769 11:54:45.530655 <4>[ 15.800932] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 11:54:45.646108 <4>[ 15.916309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 11:54:45.762036 <4>[ 16.032174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 11:54:45.878105 <4>[ 16.148069] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 11:54:45.993487 <4>[ 16.263965] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 11:54:46.109716 <4>[ 16.379908] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 11:54:46.225386 <4>[ 16.495901] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 11:54:46.341807 <4>[ 16.611827] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:54:46.457628 <4>[ 16.727853] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 11:54:46.564916 <3>[ 16.841706] mt7921e 0000:01:00.0: hardware init failed
10779 11:54:46.630753 <6>[ 16.907424] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10780 11:54:46.877405 IP-Config: no response after 2 secs - giving up
10781 11:54:46.917796 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10782 11:54:46.920974 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10783 11:54:46.927714 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10784 11:54:46.934000 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10785 11:54:46.940698 host : mt8192-asurada-spherion-r0-cbg-0
10786 11:54:46.947211 domain : lava-rack
10787 11:54:46.950956 rootserver: 192.168.201.1 rootpath:
10788 11:54:46.953949 filename :
10789 11:54:47.076501 done.
10790 11:54:47.083013 Begin: Running /scripts/nfs-bottom ... done.
10791 11:54:47.101881 Begin: Running /scripts/init-bottom ... done.
10792 11:54:48.309264 <6>[ 18.586259] NET: Registered PF_INET6 protocol family
10793 11:54:48.316905 <6>[ 18.593861] Segment Routing with IPv6
10794 11:54:48.320113 <6>[ 18.597824] In-situ OAM (IOAM) with IPv6
10795 11:54:48.436155 <30>[ 18.693595] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10796 11:54:48.439985 <30>[ 18.718101] systemd[1]: Detected architecture arm64.
10797 11:54:48.461111
10798 11:54:48.464186 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10799 11:54:48.464625
10800 11:54:48.484627 <30>[ 18.761581] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10801 11:54:49.362889 <30>[ 19.637405] systemd[1]: Queued start job for default target Graphical Interface.
10802 11:54:49.392043 <30>[ 19.669876] systemd[1]: Created slice system-getty.slice.
10803 11:54:49.398867 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10804 11:54:49.415292 <30>[ 19.692847] systemd[1]: Created slice system-modprobe.slice.
10805 11:54:49.421494 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10806 11:54:49.439121 <30>[ 19.716624] systemd[1]: Created slice system-serial\x2dgetty.slice.
10807 11:54:49.448784 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10808 11:54:49.462808 <30>[ 19.740498] systemd[1]: Created slice User and Session Slice.
10809 11:54:49.469334 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10810 11:54:49.488898 <30>[ 19.763512] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10811 11:54:49.498735 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10812 11:54:49.516971 <30>[ 19.791444] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10813 11:54:49.523737 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10814 11:54:49.544227 <30>[ 19.815322] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10815 11:54:49.551060 <30>[ 19.827486] systemd[1]: Reached target Local Encrypted Volumes.
10816 11:54:49.557513 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10817 11:54:49.574339 <30>[ 19.851687] systemd[1]: Reached target Paths.
10818 11:54:49.577397 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10819 11:54:49.593718 <30>[ 19.871198] systemd[1]: Reached target Remote File Systems.
10820 11:54:49.600486 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10821 11:54:49.618304 <30>[ 19.895557] systemd[1]: Reached target Slices.
10822 11:54:49.625168 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10823 11:54:49.637902 <30>[ 19.915212] systemd[1]: Reached target Swap.
10824 11:54:49.641104 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10825 11:54:49.662167 <30>[ 19.935787] systemd[1]: Listening on initctl Compatibility Named Pipe.
10826 11:54:49.668391 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10827 11:54:49.675027 <30>[ 19.952330] systemd[1]: Listening on Journal Audit Socket.
10828 11:54:49.681686 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10829 11:54:49.699114 <30>[ 19.976805] systemd[1]: Listening on Journal Socket (/dev/log).
10830 11:54:49.706341 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10831 11:54:49.722467 <30>[ 19.999825] systemd[1]: Listening on Journal Socket.
10832 11:54:49.728784 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10833 11:54:49.746242 <30>[ 20.020894] systemd[1]: Listening on Network Service Netlink Socket.
10834 11:54:49.753041 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10835 11:54:49.768687 <30>[ 20.046103] systemd[1]: Listening on udev Control Socket.
10836 11:54:49.774774 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10837 11:54:49.790131 <30>[ 20.067749] systemd[1]: Listening on udev Kernel Socket.
10838 11:54:49.796591 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10839 11:54:49.837384 <30>[ 20.115207] systemd[1]: Mounting Huge Pages File System...
10840 11:54:49.843824 Mounting [0;1;39mHuge Pages File System[0m...
10841 11:54:49.861936 <30>[ 20.139490] systemd[1]: Mounting POSIX Message Queue File System...
10842 11:54:49.868406 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10843 11:54:49.890317 <30>[ 20.168132] systemd[1]: Mounting Kernel Debug File System...
10844 11:54:49.896759 Mounting [0;1;39mKernel Debug File System[0m...
10845 11:54:49.913227 <30>[ 20.187694] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10846 11:54:49.969785 <30>[ 20.243956] systemd[1]: Starting Create list of static device nodes for the current kernel...
10847 11:54:49.979586 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10848 11:54:49.998896 <30>[ 20.276382] systemd[1]: Starting Load Kernel Module configfs...
10849 11:54:50.005659 Starting [0;1;39mLoad Kernel Module configfs[0m...
10850 11:54:50.024912 <30>[ 20.302334] systemd[1]: Starting Load Kernel Module drm...
10851 11:54:50.031609 Starting [0;1;39mLoad Kernel Module drm[0m...
10852 11:54:50.049170 <30>[ 20.326492] systemd[1]: Starting Load Kernel Module fuse...
10853 11:54:50.055616 Starting [0;1;39mLoad Kernel Module fuse[0m...
10854 11:54:50.089697 <6>[ 20.366616] fuse: init (API version 7.37)
10855 11:54:50.098839 <30>[ 20.367345] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10856 11:54:50.126618 <30>[ 20.403697] systemd[1]: Starting Journal Service...
10857 11:54:50.129516 Starting [0;1;39mJournal Service[0m...
10858 11:54:50.153482 <30>[ 20.431072] systemd[1]: Starting Load Kernel Modules...
10859 11:54:50.160433 Starting [0;1;39mLoad Kernel Modules[0m...
10860 11:54:50.182950 <30>[ 20.456863] systemd[1]: Starting Remount Root and Kernel File Systems...
10861 11:54:50.189702 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10862 11:54:50.206882 <30>[ 20.484143] systemd[1]: Starting Coldplug All udev Devices...
10863 11:54:50.213549 Starting [0;1;39mColdplug All udev Devices[0m...
10864 11:54:50.230971 <30>[ 20.508183] systemd[1]: Mounted Huge Pages File System.
10865 11:54:50.237280 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10866 11:54:50.254621 <30>[ 20.532139] systemd[1]: Mounted POSIX Message Queue File System.
10867 11:54:50.261030 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10868 11:54:50.278161 <30>[ 20.555936] systemd[1]: Mounted Kernel Debug File System.
10869 11:54:50.284494 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10870 11:54:50.300802 <3>[ 20.575213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 11:54:50.311039 <30>[ 20.585285] systemd[1]: Finished Create list of static device nodes for the current kernel.
10872 11:54:50.321560 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10873 11:54:50.331114 <3>[ 20.604942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 11:54:50.338726 <30>[ 20.616149] systemd[1]: modprobe@configfs.service: Succeeded.
10875 11:54:50.345379 <30>[ 20.623096] systemd[1]: Finished Load Kernel Module configfs.
10876 11:54:50.357896 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10877 11:54:50.367933 <3>[ 20.641983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 11:54:50.374266 <30>[ 20.651867] systemd[1]: modprobe@drm.service: Succeeded.
10879 11:54:50.380838 <30>[ 20.657885] systemd[1]: Finished Load Kernel Module drm.
10880 11:54:50.387872 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10881 11:54:50.398752 <3>[ 20.672852] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:54:50.405361 <30>[ 20.683083] systemd[1]: modprobe@fuse.service: Succeeded.
10883 11:54:50.413058 <30>[ 20.690596] systemd[1]: Finished Load Kernel Module fuse.
10884 11:54:50.420181 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10885 11:54:50.431630 <3>[ 20.705731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 11:54:50.438513 <30>[ 20.716228] systemd[1]: Finished Load Kernel Modules.
10887 11:54:50.449858 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10888 11:54:50.463126 <3>[ 20.736716] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 11:54:50.474986 <30>[ 20.749084] systemd[1]: Finished Remount Root and Kernel File Systems.
10890 11:54:50.482100 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10891 11:54:50.493565 <3>[ 20.767689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 11:54:50.526733 <3>[ 20.800868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 11:54:50.533896 <30>[ 20.806447] systemd[1]: Mounting FUSE Control File System...
10894 11:54:50.540258 Mounting [0;1;39mFUSE Control File System[0m...
10895 11:54:50.562467 <30>[ 20.836639] systemd[1]: Mounting Kernel Configuration File System...
10896 11:54:50.569515 <3>[ 20.839517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:54:50.575921 Mounting [0;1;39mKernel Configuration File System[0m...
10898 11:54:50.598765 <30>[ 20.872769] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10899 11:54:50.608604 <3>[ 20.874776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:54:50.618806 <30>[ 20.882036] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10901 11:54:50.667500 <30>[ 20.944523] systemd[1]: Starting Load/Save Random Seed...
10902 11:54:50.687898 Starting [0;1;39mLoad/Save Random Seed<4>[ 20.953553] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10903 11:54:50.688351 [0m...
10904 11:54:50.698033 <3>[ 20.970709] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10905 11:54:50.705457 <30>[ 20.982564] systemd[1]: Starting Apply Kernel Variables...
10906 11:54:50.712072 Starting [0;1;39mApply Kernel Variables[0m...
10907 11:54:50.731248 <30>[ 21.008687] systemd[1]: Starting Create System Users...
10908 11:54:50.737834 Starting [0;1;39mCreate System Users[0m...
10909 11:54:50.752078 <30>[ 21.029681] systemd[1]: Started Journal Service.
10910 11:54:50.758772 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10911 11:54:50.782069 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10912 11:54:50.793954 See 'systemctl status systemd-udev-trigger.service' for details.
10913 11:54:50.811073 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10914 11:54:50.826164 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10915 11:54:50.842962 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10916 11:54:50.860234 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10917 11:54:50.880352 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10918 11:54:50.922424 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10919 11:54:50.944464 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10920 11:54:50.965868 <46>[ 21.240332] systemd-journald[303]: Received client request to flush runtime journal.
10921 11:54:52.072507 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10922 11:54:52.085986 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10923 11:54:52.102933 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10924 11:54:52.149259 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10925 11:54:52.389018 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10926 11:54:52.427130 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10927 11:54:52.480736 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10928 11:54:52.555873 Starting [0;1;39mNetwork Service[0m...
10929 11:54:52.638134 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10930 11:54:52.703006 Starting [0;1;39mNetwork Time Synchronization[0m...
10931 11:54:52.733154 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10932 11:54:52.869913 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10933 11:54:52.893825 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10934 11:54:52.942128 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10935 11:54:53.126357 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10936 11:54:53.170103 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10937 11:54:53.184238 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10938 11:54:53.231679 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10939 11:54:53.263771 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10940 11:54:53.278167 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10941 11:54:53.297936 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10942 11:54:53.350640 Starting [0;1;39mNetwork Name Resolution[0m...
10943 11:54:53.394684 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10944 11:54:53.413506 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10945 11:54:53.437024 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10946 11:54:53.453481 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10947 11:54:53.469561 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10948 11:54:53.507417 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10949 11:54:53.974203 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10950 11:54:54.242905 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10951 11:54:54.571435 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10952 11:54:54.589106 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10953 11:54:54.611406 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10954 11:54:54.629246 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10955 11:54:54.649143 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10956 11:54:54.702586 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10957 11:54:54.750076 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10958 11:54:54.949875 Starting [0;1;39mUser Login Management[0m...
10959 11:54:55.235056 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10960 11:54:55.249290 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10961 11:54:55.268481 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10962 11:54:55.309731 Starting [0;1;39mPermit User Sessions[0m...
10963 11:54:55.331851 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10964 11:54:55.348480 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10965 11:54:55.390234 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10966 11:54:55.430546 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10967 11:54:55.445322 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10968 11:54:55.461771 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10969 11:54:55.469005 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10970 11:54:55.485690 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10971 11:54:55.525762 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10972 11:54:55.583255 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10973 11:54:55.654699
10974 11:54:55.655171
10975 11:54:55.657671 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10976 11:54:55.658277
10977 11:54:55.661172 debian-bullseye-arm64 login: root (automatic login)
10978 11:54:55.661634
10979 11:54:55.661978
10980 11:54:55.972550 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
10981 11:54:55.973134
10982 11:54:55.979320 The programs included with the Debian GNU/Linux system are free software;
10983 11:54:55.985545 the exact distribution terms for each program are described in the
10984 11:54:55.988666 individual files in /usr/share/doc/*/copyright.
10985 11:54:55.989087
10986 11:54:55.995661 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10987 11:54:55.999013 permitted by applicable law.
10988 11:54:56.095025 Matched prompt #10: / #
10990 11:54:56.097125 Setting prompt string to ['/ #']
10991 11:54:56.097904 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10993 11:54:56.099900 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10994 11:54:56.100615 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10995 11:54:56.101290 Setting prompt string to ['/ #']
10996 11:54:56.101816 Forcing a shell prompt, looking for ['/ #']
10998 11:54:56.153087 / #
10999 11:54:56.153256 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11000 11:54:56.153369 Waiting using forced prompt support (timeout 00:02:30)
11001 11:54:56.158456
11002 11:54:56.158746 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11003 11:54:56.158835 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11005 11:54:56.259167 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq'
11006 11:54:56.264479 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066534/extract-nfsrootfs-rkiwpbsq'
11008 11:54:56.364988 / # export NFS_SERVER_IP='192.168.201.1'
11009 11:54:56.370327 export NFS_SERVER_IP='192.168.201.1'
11010 11:54:56.370629 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11011 11:54:56.370760 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11012 11:54:56.370885 end: 2 depthcharge-action (duration 00:01:24) [common]
11013 11:54:56.371011 start: 3 lava-test-retry (timeout 00:01:00) [common]
11014 11:54:56.371144 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11015 11:54:56.371255 Using namespace: common
11017 11:54:56.471585 / # #
11018 11:54:56.471770 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11019 11:54:56.476610 #
11020 11:54:56.476882 Using /lava-12066534
11022 11:54:56.577234 / # export SHELL=/bin/sh
11023 11:54:56.582489 export SHELL=/bin/sh
11025 11:54:56.683034 / # . /lava-12066534/environment
11026 11:54:56.688172 . /lava-12066534/environment
11028 11:54:56.794900 / # /lava-12066534/bin/lava-test-runner /lava-12066534/0
11029 11:54:56.795053 Test shell timeout: 10s (minimum of the action and connection timeout)
11030 11:54:56.800069 /lava-12066534/bin/lava-test-runner /lava-12066534/0
11031 11:54:57.043342 + export TESTRUN_ID=0_dmesg
11032 11:54:57.046934 + cd /lava-12066534/0/tests/0_dmesg
11033 11:54:57.049871 + cat uuid
11034 11:54:57.063047 + UUID=12066534_<8>[ 27.338359] <LAVA_SIGNAL_STARTRUN 0_dmesg 12066534_1.6.2.3.1>
11035 11:54:57.063136 1.6.2.3.1
11036 11:54:57.063204 + set +x
11037 11:54:57.063444 Received signal: <STARTRUN> 0_dmesg 12066534_1.6.2.3.1
11038 11:54:57.063534 Starting test lava.0_dmesg (12066534_1.6.2.3.1)
11039 11:54:57.063635 Skipping test definition patterns.
11040 11:54:57.069486 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11041 11:54:57.159196 <8>[ 27.434518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11042 11:54:57.159720 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11044 11:54:57.232216 <8>[ 27.507495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11045 11:54:57.232549 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11047 11:54:57.301510 <8>[ 27.576732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11048 11:54:57.301842 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11050 11:54:57.305440 + set +x
11051 11:54:57.308270 <8>[ 27.586350] <LAVA_SIGNAL_ENDRUN 0_dmesg 12066534_1.6.2.3.1>
11052 11:54:57.308549 Received signal: <ENDRUN> 0_dmesg 12066534_1.6.2.3.1
11053 11:54:57.308653 Ending use of test pattern.
11054 11:54:57.308748 Ending test lava.0_dmesg (12066534_1.6.2.3.1), duration 0.25
11056 11:54:57.314515 <LAVA_TEST_RUNNER EXIT>
11057 11:54:57.314804 ok: lava_test_shell seems to have completed
11058 11:54:57.314945 alert: pass
crit: pass
emerg: pass
11059 11:54:57.315060 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11060 11:54:57.315171 end: 3 lava-test-retry (duration 00:00:01) [common]
11061 11:54:57.315283 start: 4 lava-test-retry (timeout 00:01:00) [common]
11062 11:54:57.315392 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11063 11:54:57.315477 Using namespace: common
11065 11:54:57.415825 / # #
11066 11:54:57.415981 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11067 11:54:57.416134 Using /lava-12066534
11069 11:54:57.516472 export SHELL=/bin/sh
11070 11:54:57.516683 #
11072 11:54:57.617184 / # export SHELL=/bin/sh. /lava-12066534/environment
11073 11:54:57.617635
11075 11:54:57.718452 / # . /lava-12066534/environment/lava-12066534/bin/lava-test-runner /lava-12066534/1
11076 11:54:57.718595 Test shell timeout: 10s (minimum of the action and connection timeout)
11077 11:54:57.718747
11078 11:54:57.723679 / # /lava-12066534/bin/lava-test-runner /lava-12066534/1
11079 11:54:57.822115 + export TESTRUN_ID=1_bootrr
11080 11:54:57.825393 + cd /lava-12066534/1/tests/1_bootrr
11081 11:54:57.828670 + cat uuid
11082 11:54:57.835118 + <8>[ 28.112326] <LAVA_SIGNAL_STARTRUN 1_bootrr 12066534_1.6.2.3.5>
11083 11:54:57.835402 Received signal: <STARTRUN> 1_bootrr 12066534_1.6.2.3.5
11084 11:54:57.835481 Starting test lava.1_bootrr (12066534_1.6.2.3.5)
11085 11:54:57.835571 Skipping test definition patterns.
11086 11:54:57.838390 UUID=12066534_1.6.2.3.5
11087 11:54:57.838471 + set +x
11088 11:54:57.848877 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12066534/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11089 11:54:57.851381 + cd /opt/bootrr/libexec/bootrr
11090 11:54:57.854755 + sh helpers/bootrr-auto
11091 11:54:57.898656 /lava-12066534/1/../bin/lava-test-case
11092 11:54:57.921803 <8>[ 28.197368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11093 11:54:57.922073 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11095 11:54:57.953121 /lava-12066534/1/../bin/lava-test-case
11096 11:54:57.975392 <8>[ 28.250634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11097 11:54:57.975659 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11099 11:54:57.993159 /lava-12066534/1/../bin/lava-test-case
11100 11:54:58.015697 <8>[ 28.291277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11101 11:54:58.015953 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11103 11:54:58.057410 /lava-12066534/1/../bin/lava-test-case
11104 11:54:58.079476 <8>[ 28.354479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11105 11:54:58.079742 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11107 11:54:58.107360 /lava-12066534/1/../bin/lava-test-case
11108 11:54:58.128670 <8>[ 28.404125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11109 11:54:58.128959 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11111 11:54:58.161283 /lava-12066534/1/../bin/lava-test-case
11112 11:54:58.186292 <8>[ 28.461356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11113 11:54:58.186569 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11115 11:54:58.214666 /lava-12066534/1/../bin/lava-test-case
11116 11:54:58.239982 <8>[ 28.515313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11117 11:54:58.240276 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11119 11:54:58.266794 /lava-12066534/1/../bin/lava-test-case
11120 11:54:58.290686 <8>[ 28.566324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11121 11:54:58.290954 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11123 11:54:58.310073 /lava-12066534/1/../bin/lava-test-case
11124 11:54:58.328281 <8>[ 28.604023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11125 11:54:58.328549 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11127 11:54:58.359371 /lava-12066534/1/../bin/lava-test-case
11128 11:54:58.382113 <8>[ 28.657629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11129 11:54:58.382378 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11131 11:54:58.401357 /lava-12066534/1/../bin/lava-test-case
11132 11:54:58.427002 <8>[ 28.702101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11133 11:54:58.427288 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11135 11:54:58.458386 /lava-12066534/1/../bin/lava-test-case
11136 11:54:58.485757 <8>[ 28.761410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11137 11:54:58.486038 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11139 11:54:58.525327 /lava-12066534/1/../bin/lava-test-case
11140 11:54:58.546448 <8>[ 28.821775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11141 11:54:58.546732 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11143 11:54:58.574333 /lava-12066534/1/../bin/lava-test-case
11144 11:54:58.592685 <8>[ 28.867955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11145 11:54:58.592949 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11147 11:54:58.626165 /lava-12066534/1/../bin/lava-test-case
11148 11:54:58.649829 <8>[ 28.925226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11149 11:54:58.650113 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11151 11:54:58.668909 /lava-12066534/1/../bin/lava-test-case
11152 11:54:58.689773 <8>[ 28.965180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11153 11:54:58.690046 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11155 11:54:58.718258 /lava-12066534/1/../bin/lava-test-case
11156 11:54:58.739252 <8>[ 29.014529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11157 11:54:58.739533 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11159 11:54:58.758235 /lava-12066534/1/../bin/lava-test-case
11160 11:54:58.780781 <8>[ 29.055912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11161 11:54:58.781051 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11163 11:54:58.808312 /lava-12066534/1/../bin/lava-test-case
11164 11:54:58.833530 <8>[ 29.109259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11165 11:54:58.833821 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11167 11:54:58.858943 /lava-12066534/1/../bin/lava-test-case
11168 11:54:58.879364 <8>[ 29.154751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11169 11:54:58.879650 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11171 11:54:58.906388 /lava-12066534/1/../bin/lava-test-case
11172 11:54:58.929702 <8>[ 29.205159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11173 11:54:58.929966 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11175 11:54:58.948134 /lava-12066534/1/../bin/lava-test-case
11176 11:54:58.970223 <8>[ 29.245833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11177 11:54:58.970488 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11179 11:54:59.000406 /lava-12066534/1/../bin/lava-test-case
11180 11:54:59.027030 <8>[ 29.302498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11181 11:54:59.027308 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11183 11:54:59.045864 /lava-12066534/1/../bin/lava-test-case
11184 11:54:59.067754 <8>[ 29.343111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11185 11:54:59.068015 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11187 11:54:59.098330 /lava-12066534/1/../bin/lava-test-case
11188 11:54:59.126714 <8>[ 29.402003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11189 11:54:59.127001 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11191 11:54:59.155332 /lava-12066534/1/../bin/lava-test-case
11192 11:54:59.175282 <8>[ 29.450905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11193 11:54:59.175556 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11195 11:54:59.200863 /lava-12066534/1/../bin/lava-test-case
11196 11:54:59.220778 <8>[ 29.496417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11197 11:54:59.221041 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11199 11:54:59.247266 /lava-12066534/1/../bin/lava-test-case
11200 11:54:59.269557 <8>[ 29.544683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11201 11:54:59.269842 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11203 11:54:59.291716 /lava-12066534/1/../bin/lava-test-case
11204 11:54:59.311703 <8>[ 29.587140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11205 11:54:59.311958 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11207 11:54:59.342924 /lava-12066534/1/../bin/lava-test-case
11208 11:54:59.369444 <8>[ 29.645007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11209 11:54:59.369727 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11211 11:54:59.399280 /lava-12066534/1/../bin/lava-test-case
11212 11:54:59.426845 <8>[ 29.702519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11213 11:54:59.427205 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11215 11:54:59.458234 /lava-12066534/1/../bin/lava-test-case
11216 11:54:59.483167 <8>[ 29.758387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11217 11:54:59.483526 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11219 11:54:59.515090 /lava-12066534/1/../bin/lava-test-case
11220 11:54:59.537807 <8>[ 29.813540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11221 11:54:59.538083 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11223 11:54:59.556685 /lava-12066534/1/../bin/lava-test-case
11224 11:54:59.576999 <8>[ 29.852554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11225 11:54:59.577279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11227 11:54:59.607775 /lava-12066534/1/../bin/lava-test-case
11228 11:54:59.633656 <8>[ 29.908979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11229 11:54:59.633935 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11231 11:54:59.661411 /lava-12066534/1/../bin/lava-test-case
11232 11:54:59.682342 <8>[ 29.957893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11233 11:54:59.682617 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11235 11:54:59.700753 /lava-12066534/1/../bin/lava-test-case
11236 11:54:59.719805 <8>[ 29.995156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11237 11:54:59.720070 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11239 11:54:59.746372 /lava-12066534/1/../bin/lava-test-case
11240 11:54:59.766839 <8>[ 30.042464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11241 11:54:59.767105 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11243 11:54:59.784949 /lava-12066534/1/../bin/lava-test-case
11244 11:54:59.807574 <8>[ 30.083435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11245 11:54:59.807834 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11247 11:54:59.848437 /lava-12066534/1/../bin/lava-test-case
11248 11:54:59.870678 <8>[ 30.146078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11249 11:54:59.870953 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11251 11:54:59.890213 /lava-12066534/1/../bin/lava-test-case
11252 11:54:59.909156 <8>[ 30.184807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11253 11:54:59.909428 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11255 11:54:59.936501 /lava-12066534/1/../bin/lava-test-case
11256 11:54:59.957450 <8>[ 30.233136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11257 11:54:59.957726 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11259 11:54:59.976370 /lava-12066534/1/../bin/lava-test-case
11260 11:54:59.996816 <8>[ 30.272265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11261 11:54:59.997076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11263 11:55:00.025856 /lava-12066534/1/../bin/lava-test-case
11264 11:55:00.047068 <8>[ 30.322550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11265 11:55:00.047352 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11267 11:55:00.065444 /lava-12066534/1/../bin/lava-test-case
11268 11:55:00.089775 <8>[ 30.364835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11269 11:55:00.090060 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11271 11:55:00.122103 /lava-12066534/1/../bin/lava-test-case
11272 11:55:00.145134 <8>[ 30.420954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11273 11:55:00.145414 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11275 11:55:00.175099 /lava-12066534/1/../bin/lava-test-case
11276 11:55:00.206036 <8>[ 30.481386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11277 11:55:00.206838 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11279 11:55:00.240446 /lava-12066534/1/../bin/lava-test-case
11280 11:55:00.269447 <8>[ 30.545083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11281 11:55:00.269746 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11283 11:55:00.289799 /lava-12066534/1/../bin/lava-test-case
11284 11:55:00.316943 <8>[ 30.592189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11285 11:55:00.317265 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11287 11:55:00.345281 /lava-12066534/1/../bin/lava-test-case
11288 11:55:00.370265 <8>[ 30.645841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11289 11:55:00.370551 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11291 11:55:00.401127 /lava-12066534/1/../bin/lava-test-case
11292 11:55:00.421525 <8>[ 30.697039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11293 11:55:00.421900 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11295 11:55:00.442683 /lava-12066534/1/../bin/lava-test-case
11296 11:55:00.467426 <8>[ 30.742936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11297 11:55:00.467718 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11299 11:55:00.500292 /lava-12066534/1/../bin/lava-test-case
11300 11:55:00.525462 <8>[ 30.800856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11301 11:55:00.525742 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11303 11:55:00.546471 /lava-12066534/1/../bin/lava-test-case
11304 11:55:00.570183 <8>[ 30.845509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11305 11:55:00.571037 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11307 11:55:00.607543 /lava-12066534/1/../bin/lava-test-case
11308 11:55:00.641161 <8>[ 30.916103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11309 11:55:00.641973 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11311 11:55:00.675769 /lava-12066534/1/../bin/lava-test-case
11312 11:55:00.708709 <8>[ 30.983585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11313 11:55:00.709428 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11315 11:55:00.746095 /lava-12066534/1/../bin/lava-test-case
11316 11:55:00.778147 <8>[ 31.053296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11317 11:55:00.778963 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11319 11:55:00.819062 /lava-12066534/1/../bin/lava-test-case
11320 11:55:00.845230 <8>[ 31.120699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11321 11:55:00.845516 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11323 11:55:00.876114 /lava-12066534/1/../bin/lava-test-case
11324 11:55:00.906055 <8>[ 31.181327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11325 11:55:00.906716 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11327 11:55:00.929750 /lava-12066534/1/../bin/lava-test-case
11328 11:55:00.960874 <8>[ 31.236269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11329 11:55:00.961614 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11331 11:55:00.998043 /lava-12066534/1/../bin/lava-test-case
11332 11:55:01.029929 <8>[ 31.304901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11333 11:55:01.030635 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11335 11:55:01.067154 /lava-12066534/1/../bin/lava-test-case
11336 11:55:01.095186 <8>[ 31.370492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11337 11:55:01.095921 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11339 11:55:01.117293 /lava-12066534/1/../bin/lava-test-case
11340 11:55:01.151370 <8>[ 31.426459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11341 11:55:01.152310 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11343 11:55:01.190354 /lava-12066534/1/../bin/lava-test-case
11344 11:55:01.219624 <8>[ 31.494850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11345 11:55:01.220533 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11347 11:55:01.243838 /lava-12066534/1/../bin/lava-test-case
11348 11:55:01.272216 <8>[ 31.547563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11349 11:55:01.273021 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11351 11:55:01.305814 /lava-12066534/1/../bin/lava-test-case
11352 11:55:01.335522 <8>[ 31.610693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11353 11:55:01.336231 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11355 11:55:01.358245 /lava-12066534/1/../bin/lava-test-case
11356 11:55:01.385756 <8>[ 31.661182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11357 11:55:01.386452 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11359 11:55:01.420716 /lava-12066534/1/../bin/lava-test-case
11360 11:55:01.451805 <8>[ 31.727163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11361 11:55:01.452585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11363 11:55:01.483799 /lava-12066534/1/../bin/lava-test-case
11364 11:55:01.509455 <8>[ 31.784705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11365 11:55:01.509747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11367 11:55:01.547929 /lava-12066534/1/../bin/lava-test-case
11368 11:55:01.575538 <8>[ 31.850982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11369 11:55:01.575984 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11371 11:55:01.606456 /lava-12066534/1/../bin/lava-test-case
11372 11:55:01.630028 <8>[ 31.905993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11373 11:55:01.630304 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11375 11:55:01.660826 /lava-12066534/1/../bin/lava-test-case
11376 11:55:01.686250 <8>[ 31.962147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11377 11:55:01.686538 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11379 11:55:01.713911 /lava-12066534/1/../bin/lava-test-case
11380 11:55:01.737507 <8>[ 32.013266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11381 11:55:01.737827 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11383 11:55:01.768730 /lava-12066534/1/../bin/lava-test-case
11384 11:55:01.794131 <8>[ 32.069993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11385 11:55:01.794405 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11387 11:55:01.819041 /lava-12066534/1/../bin/lava-test-case
11388 11:55:01.848696 <8>[ 32.124203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11389 11:55:01.849012 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11391 11:55:01.886738 /lava-12066534/1/../bin/lava-test-case
11392 11:55:01.910416 <8>[ 32.186360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11393 11:55:01.910688 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11395 11:55:01.940772 /lava-12066534/1/../bin/lava-test-case
11396 11:55:01.964786 <8>[ 32.240346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11397 11:55:01.965065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11399 11:55:01.993833 /lava-12066534/1/../bin/lava-test-case
11400 11:55:02.020104 <8>[ 32.295948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11401 11:55:02.020379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11403 11:55:02.049297 /lava-12066534/1/../bin/lava-test-case
11404 11:55:02.078221 <8>[ 32.353693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11405 11:55:02.078906 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11407 11:55:02.114416 /lava-12066534/1/../bin/lava-test-case
11408 11:55:02.141418 <8>[ 32.416763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11409 11:55:02.142182 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11411 11:55:02.176448 /lava-12066534/1/../bin/lava-test-case
11412 11:55:02.206381 <8>[ 32.481409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11413 11:55:02.207078 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11415 11:55:02.246886 /lava-12066534/1/../bin/lava-test-case
11416 11:55:02.272930 <8>[ 32.548530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11417 11:55:02.273688 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11419 11:55:02.295272 /lava-12066534/1/../bin/lava-test-case
11420 11:55:02.319460 <8>[ 32.595414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11421 11:55:02.319732 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11423 11:55:02.348446 /lava-12066534/1/../bin/lava-test-case
11424 11:55:02.369696 <8>[ 32.645398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11425 11:55:02.370046 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11427 11:55:02.387261 /lava-12066534/1/../bin/lava-test-case
11428 11:55:02.412318 <8>[ 32.688224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11429 11:55:02.412703 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11431 11:55:02.440565 /lava-12066534/1/../bin/lava-test-case
11432 11:55:02.466034 <8>[ 32.741731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11433 11:55:02.466325 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11435 11:55:02.485243 /lava-12066534/1/../bin/lava-test-case
11436 11:55:02.507493 <8>[ 32.782755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11437 11:55:02.508184 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11439 11:55:02.547998 /lava-12066534/1/../bin/lava-test-case
11440 11:55:02.579644 <8>[ 32.855316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11441 11:55:02.579999 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11443 11:55:02.607109 /lava-12066534/1/../bin/lava-test-case
11444 11:55:02.634350 <8>[ 32.909838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11445 11:55:02.634722 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11447 11:55:02.666661 /lava-12066534/1/../bin/lava-test-case
11448 11:55:02.698962 <8>[ 32.974466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11449 11:55:02.699236 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11451 11:55:02.718784 /lava-12066534/1/../bin/lava-test-case
11452 11:55:02.744241 <8>[ 33.019907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11453 11:55:02.744526 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11455 11:55:02.778147 /lava-12066534/1/../bin/lava-test-case
11456 11:55:02.803985 <8>[ 33.079714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11457 11:55:02.804261 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11459 11:55:02.827047 /lava-12066534/1/../bin/lava-test-case
11460 11:55:02.851357 <8>[ 33.127024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11461 11:55:02.851635 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11463 11:55:02.882402 /lava-12066534/1/../bin/lava-test-case
11464 11:55:02.910942 <8>[ 33.186255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11465 11:55:02.911216 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11467 11:55:02.947088 /lava-12066534/1/../bin/lava-test-case
11468 11:55:02.972689 <8>[ 33.248446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11469 11:55:02.972976 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11471 11:55:02.993668 /lava-12066534/1/../bin/lava-test-case
11472 11:55:03.018323 <8>[ 33.294139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11473 11:55:03.018600 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11475 11:55:03.050493 /lava-12066534/1/../bin/lava-test-case
11476 11:55:03.076687 <8>[ 33.352437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11477 11:55:03.076960 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11479 11:55:03.098637 /lava-12066534/1/../bin/lava-test-case
11480 11:55:03.118737 <8>[ 33.394609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11481 11:55:03.119009 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11483 11:55:03.149921 /lava-12066534/1/../bin/lava-test-case
11484 11:55:03.173999 <8>[ 33.449587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11485 11:55:03.174285 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11487 11:55:03.193701 /lava-12066534/1/../bin/lava-test-case
11488 11:55:03.214731 <8>[ 33.490556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11489 11:55:03.214995 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11491 11:55:04.257433 /lava-12066534/1/../bin/lava-test-case
11492 11:55:04.284778 <8>[ 34.560805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11493 11:55:04.285053 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11495 11:55:04.304635 /lava-12066534/1/../bin/lava-test-case
11496 11:55:04.327273 <8>[ 34.603234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11497 11:55:04.327549 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11499 11:55:05.362320 /lava-12066534/1/../bin/lava-test-case
11500 11:55:05.391686 <8>[ 35.667659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11501 11:55:05.392430 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11503 11:55:05.413259 /lava-12066534/1/../bin/lava-test-case
11504 11:55:05.440263 <8>[ 35.716524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11505 11:55:05.440519 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11507 11:55:06.479031 /lava-12066534/1/../bin/lava-test-case
11508 11:55:06.505035 <8>[ 36.781532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11509 11:55:06.505343 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11511 11:55:06.524135 /lava-12066534/1/../bin/lava-test-case
11512 11:55:06.548775 <8>[ 36.824829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11513 11:55:06.549083 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11515 11:55:07.583991 /lava-12066534/1/../bin/lava-test-case
11516 11:55:07.611066 <8>[ 37.887546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11517 11:55:07.611376 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11519 11:55:07.628140 /lava-12066534/1/../bin/lava-test-case
11520 11:55:07.647608 <8>[ 37.924199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11521 11:55:07.647892 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11523 11:55:08.685906 /lava-12066534/1/../bin/lava-test-case
11524 11:55:08.707754 <8>[ 38.984490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11525 11:55:08.708031 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11527 11:55:08.724266 /lava-12066534/1/../bin/lava-test-case
11528 11:55:08.742464 <8>[ 39.018929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11529 11:55:08.742721 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11531 11:55:09.778332 /lava-12066534/1/../bin/lava-test-case
11532 11:55:09.807065 <8>[ 40.083286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11533 11:55:09.807379 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11535 11:55:09.828187 /lava-12066534/1/../bin/lava-test-case
11536 11:55:09.851206 <8>[ 40.127764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11537 11:55:09.851508 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11539 11:55:10.886153 /lava-12066534/1/../bin/lava-test-case
11540 11:55:10.911797 <8>[ 41.188013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11541 11:55:10.912079 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11543 11:55:10.929894 /lava-12066534/1/../bin/lava-test-case
11544 11:55:10.950519 <8>[ 41.227245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11545 11:55:10.950801 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11547 11:55:10.970057 /lava-12066534/1/../bin/lava-test-case
11548 11:55:10.990621 <8>[ 41.267359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11549 11:55:10.990922 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11551 11:55:12.029505 /lava-12066534/1/../bin/lava-test-case
11552 11:55:12.054077 <8>[ 42.330497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11553 11:55:12.054367 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11555 11:55:12.073820 /lava-12066534/1/../bin/lava-test-case
11556 11:55:12.094064 <8>[ 42.370426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11557 11:55:12.094324 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11559 11:55:12.118396 /lava-12066534/1/../bin/lava-test-case
11560 11:55:12.141042 <8>[ 42.418189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11561 11:55:12.141302 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11563 11:55:12.159455 /lava-12066534/1/../bin/lava-test-case
11564 11:55:12.181024 <8>[ 42.457864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11565 11:55:12.181294 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11567 11:55:12.207653 /lava-12066534/1/../bin/lava-test-case
11568 11:55:12.227988 <8>[ 42.505116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11569 11:55:12.228246 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11571 11:55:12.257908 /lava-12066534/1/../bin/lava-test-case
11572 11:55:12.282590 <8>[ 42.559629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11573 11:55:12.282855 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11575 11:55:12.311402 /lava-12066534/1/../bin/lava-test-case
11576 11:55:12.334065 <8>[ 42.610668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11577 11:55:12.334325 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11579 11:55:12.358904 /lava-12066534/1/../bin/lava-test-case
11580 11:55:12.378224 <8>[ 42.655138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11581 11:55:12.378486 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11583 11:55:12.406345 /lava-12066534/1/../bin/lava-test-case
11584 11:55:12.428941 <8>[ 42.705932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11585 11:55:12.429240 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11587 11:55:12.457271 /lava-12066534/1/../bin/lava-test-case
11588 11:55:12.481875 <8>[ 42.759103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11589 11:55:12.482140 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11591 11:55:12.502041 /lava-12066534/1/../bin/lava-test-case
11592 11:55:12.524390 <8>[ 42.801593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11593 11:55:12.524647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11595 11:55:12.554222 /lava-12066534/1/../bin/lava-test-case
11596 11:55:12.577103 <8>[ 42.854264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11597 11:55:12.577420 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11599 11:55:12.594763 /lava-12066534/1/../bin/lava-test-case
11600 11:55:12.617271 <8>[ 42.894335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11601 11:55:12.617530 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11603 11:55:12.648773 /lava-12066534/1/../bin/lava-test-case
11604 11:55:12.670293 <8>[ 42.947382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11605 11:55:12.670556 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11607 11:55:12.697818 /lava-12066534/1/../bin/lava-test-case
11608 11:55:12.720466 <8>[ 42.997454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11609 11:55:12.720730 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11611 11:55:12.750657 /lava-12066534/1/../bin/lava-test-case
11612 11:55:12.772367 <8>[ 43.049419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11613 11:55:12.772628 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11615 11:55:12.793171 /lava-12066534/1/../bin/lava-test-case
11616 11:55:12.814773 <8>[ 43.091980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11617 11:55:12.815031 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11619 11:55:12.846352 /lava-12066534/1/../bin/lava-test-case
11620 11:55:12.874024 <8>[ 43.151230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11621 11:55:12.874288 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11623 11:55:12.894627 /lava-12066534/1/../bin/lava-test-case
11624 11:55:12.917871 <8>[ 43.194758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11625 11:55:12.918129 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11627 11:55:12.945783 /lava-12066534/1/../bin/lava-test-case
11628 11:55:12.968520 <8>[ 43.245191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11629 11:55:12.968781 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11631 11:55:12.986917 /lava-12066534/1/../bin/lava-test-case
11632 11:55:13.009428 <8>[ 43.286510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11633 11:55:13.009717 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11635 11:55:14.052610 /lava-12066534/1/../bin/lava-test-case
11636 11:55:14.076921 <8>[ 44.354040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11637 11:55:14.077228 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11639 11:55:15.112391 /lava-12066534/1/../bin/lava-test-case
11640 11:55:15.139843 <8>[ 45.417019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11641 11:55:15.140119 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11643 11:55:15.157523 /lava-12066534/1/../bin/lava-test-case
11644 11:55:15.179571 <8>[ 45.456662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11645 11:55:15.179836 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11647 11:55:15.208633 /lava-12066534/1/../bin/lava-test-case
11648 11:55:15.233048 <8>[ 45.510379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11649 11:55:15.233312 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11651 11:55:15.253727 /lava-12066534/1/../bin/lava-test-case
11652 11:55:15.275426 <8>[ 45.552431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11653 11:55:15.275687 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11655 11:55:15.307698 /lava-12066534/1/../bin/lava-test-case
11656 11:55:15.330054 <8>[ 45.607017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11657 11:55:15.330316 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11659 11:55:15.349950 /lava-12066534/1/../bin/lava-test-case
11660 11:55:15.372429 <8>[ 45.649902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11661 11:55:15.372687 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11663 11:55:15.400789 /lava-12066534/1/../bin/lava-test-case
11664 11:55:15.423654 <8>[ 45.701201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11665 11:55:15.423916 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11667 11:55:15.449440 /lava-12066534/1/../bin/lava-test-case
11668 11:55:15.471573 <8>[ 45.749018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11669 11:55:15.471835 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11671 11:55:15.499309 /lava-12066534/1/../bin/lava-test-case
11672 11:55:15.521176 <8>[ 45.798315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11673 11:55:15.521434 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11675 11:55:15.541564 /lava-12066534/1/../bin/lava-test-case
11676 11:55:15.562080 <8>[ 45.839524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11677 11:55:15.562344 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11679 11:55:15.593239 /lava-12066534/1/../bin/lava-test-case
11680 11:55:15.616465 <8>[ 45.893852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11681 11:55:15.616726 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11683 11:55:15.634188 /lava-12066534/1/../bin/lava-test-case
11684 11:55:15.656843 <8>[ 45.933765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11685 11:55:15.657103 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11687 11:55:15.684914 /lava-12066534/1/../bin/lava-test-case
11688 11:55:15.707941 <8>[ 45.985270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11689 11:55:15.708251 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11691 11:55:15.727553 /lava-12066534/1/../bin/lava-test-case
11692 11:55:15.754536 <8>[ 46.031962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11693 11:55:15.754859 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11695 11:55:15.791967 /lava-12066534/1/../bin/lava-test-case
11696 11:55:15.816701 <8>[ 46.094016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11697 11:55:15.817016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11699 11:55:15.837572 /lava-12066534/1/../bin/lava-test-case
11700 11:55:15.862493 <8>[ 46.139504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11701 11:55:15.862805 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11703 11:55:15.875323 <6>[ 46.159132] vpu: disabling
11704 11:55:15.878337 <6>[ 46.162329] vproc2: disabling
11705 11:55:15.882000 <6>[ 46.165769] vproc1: disabling
11706 11:55:15.885406 <6>[ 46.169185] vaud18: disabling
11707 11:55:15.892123 <6>[ 46.172843] vsram_others: disabling
11708 11:55:15.895552 <6>[ 46.176934] va09: disabling
11709 11:55:15.898970 <6>[ 46.180217] vsram_md: disabling
11710 11:55:15.902436 <6>[ 46.183904] Vgpu: disabling
11711 11:55:15.920250 /lava-12066534/1/../bin/lava-test-case
11712 11:55:15.944700 <8>[ 46.221785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11713 11:55:15.945010 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11715 11:55:15.965004 /lava-12066534/1/../bin/lava-test-case
11716 11:55:15.989553 <8>[ 46.267120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11717 11:55:15.989914 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11719 11:55:16.021492 /lava-12066534/1/../bin/lava-test-case
11720 11:55:16.046826 <8>[ 46.323916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11721 11:55:16.047154 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11723 11:55:16.068141 /lava-12066534/1/../bin/lava-test-case
11724 11:55:16.092618 <8>[ 46.369784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11725 11:55:16.092945 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11727 11:55:16.139872 /lava-12066534/1/../bin/lava-test-case
11728 11:55:16.163929 <8>[ 46.441274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11729 11:55:16.164256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11731 11:55:17.192190 /lava-12066534/1/../bin/lava-test-case
11732 11:55:17.216396 <8>[ 47.493777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11733 11:55:17.216719 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11735 11:55:18.243992 /lava-12066534/1/../bin/lava-test-case
11736 11:55:18.268124 <8>[ 48.545639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11737 11:55:18.268460 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11738 11:55:18.268555 Bad test result: blocked
11739 11:55:18.286467 /lava-12066534/1/../bin/lava-test-case
11740 11:55:18.305256 <8>[ 48.582495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11741 11:55:18.305607 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11743 11:55:19.345398 /lava-12066534/1/../bin/lava-test-case
11744 11:55:19.374379 <8>[ 49.651951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11745 11:55:19.374778 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11747 11:55:19.391557 /lava-12066534/1/../bin/lava-test-case
11748 11:55:19.411283 <8>[ 49.689170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11749 11:55:19.411613 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11751 11:55:19.441012 /lava-12066534/1/../bin/lava-test-case
11752 11:55:19.465183 <8>[ 49.742563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11753 11:55:19.465512 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11755 11:55:19.490997 /lava-12066534/1/../bin/lava-test-case
11756 11:55:19.511680 <8>[ 49.789644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11757 11:55:19.512009 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11759 11:55:19.530218 /lava-12066534/1/../bin/lava-test-case
11760 11:55:19.554051 <8>[ 49.831796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11761 11:55:19.554380 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11763 11:55:19.585256 /lava-12066534/1/../bin/lava-test-case
11764 11:55:19.608448 <8>[ 49.886155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11765 11:55:19.608774 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11767 11:55:19.628559 /lava-12066534/1/../bin/lava-test-case
11768 11:55:19.651034 <8>[ 49.928325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11769 11:55:19.651364 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11771 11:55:20.696163 /lava-12066534/1/../bin/lava-test-case
11772 11:55:20.724772 <8>[ 51.002290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11773 11:55:20.725157 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11775 11:55:20.745719 /lava-12066534/1/../bin/lava-test-case
11776 11:55:20.770214 <8>[ 51.048024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11777 11:55:20.770572 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11779 11:55:21.804869 /lava-12066534/1/../bin/lava-test-case
11780 11:55:21.829956 <8>[ 52.107892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11781 11:55:21.830293 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11783 11:55:21.848933 /lava-12066534/1/../bin/lava-test-case
11784 11:55:21.873438 <8>[ 52.151615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11785 11:55:21.873792 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11787 11:55:22.911631 /lava-12066534/1/../bin/lava-test-case
11788 11:55:22.936241 <8>[ 53.214238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11789 11:55:22.936560 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11791 11:55:22.954432 /lava-12066534/1/../bin/lava-test-case
11792 11:55:22.977365 <8>[ 53.255426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11793 11:55:22.977757 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11795 11:55:24.016200 /lava-12066534/1/../bin/lava-test-case
11796 11:55:24.043616 <8>[ 54.322064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11797 11:55:24.043946 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11799 11:55:24.064533 /lava-12066534/1/../bin/lava-test-case
11800 11:55:24.089298 <8>[ 54.367420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11801 11:55:24.089641 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11803 11:55:24.122944 /lava-12066534/1/../bin/lava-test-case
11804 11:55:24.144613 <8>[ 54.422717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11805 11:55:24.144936 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11807 11:55:24.174737 /lava-12066534/1/../bin/lava-test-case
11808 11:55:24.199654 <8>[ 54.478186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11809 11:55:24.199983 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11811 11:55:24.221451 /lava-12066534/1/../bin/lava-test-case
11812 11:55:24.241571 <8>[ 54.519308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11813 11:55:24.241902 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11815 11:55:24.269239 /lava-12066534/1/../bin/lava-test-case
11816 11:55:24.295382 <8>[ 54.573717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11817 11:55:24.295715 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11819 11:55:24.320226 /lava-12066534/1/../bin/lava-test-case
11820 11:55:24.342011 <8>[ 54.620235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11821 11:55:24.342336 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11823 11:55:24.375570 /lava-12066534/1/../bin/lava-test-case
11824 11:55:24.398334 <8>[ 54.676363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11825 11:55:24.398650 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11827 11:55:24.419116 /lava-12066534/1/../bin/lava-test-case
11828 11:55:24.440893 <8>[ 54.719144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11829 11:55:24.441213 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11831 11:55:24.468681 /lava-12066534/1/../bin/lava-test-case
11832 11:55:24.489608 <8>[ 54.767891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11833 11:55:24.489987 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11835 11:55:24.495272 + set +x
11836 11:55:24.498710 Received signal: <ENDRUN> 1_bootrr 12066534_1.6.2.3.5
11837 11:55:24.498811 Ending use of test pattern.
11838 11:55:24.498892 Ending test lava.1_bootrr (12066534_1.6.2.3.5), duration 26.66
11840 11:55:24.501388 <8>[ 54.779689] <LAVA_SIGNAL_ENDRUN 1_bootrr 12066534_1.6.2.3.5>
11841 11:55:24.504926 <LAVA_TEST_RUNNER EXIT>
11842 11:55:24.505186 ok: lava_test_shell seems to have completed
11843 11:55:24.506536 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11844 11:55:24.506695 end: 4.1 lava-test-shell (duration 00:00:27) [common]
11845 11:55:24.506796 end: 4 lava-test-retry (duration 00:00:27) [common]
11846 11:55:24.506895 start: 5 finalize (timeout 00:07:40) [common]
11847 11:55:24.506999 start: 5.1 power-off (timeout 00:00:30) [common]
11848 11:55:24.507164 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11849 11:55:24.585477 >> Command sent successfully.
11850 11:55:24.588044 Returned 0 in 0 seconds
11851 11:55:24.688468 end: 5.1 power-off (duration 00:00:00) [common]
11853 11:55:24.688873 start: 5.2 read-feedback (timeout 00:07:40) [common]
11854 11:55:24.689156 Listened to connection for namespace 'common' for up to 1s
11855 11:55:25.689690 Finalising connection for namespace 'common'
11856 11:55:25.689869 Disconnecting from shell: Finalise
11857 11:55:25.689953 / #
11858 11:55:25.790302 end: 5.2 read-feedback (duration 00:00:01) [common]
11859 11:55:25.790482 end: 5 finalize (duration 00:00:01) [common]
11860 11:55:25.790599 Cleaning after the job
11861 11:55:25.790710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/ramdisk
11862 11:55:25.793254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/kernel
11863 11:55:25.805918 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/dtb
11864 11:55:25.806120 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/nfsrootfs
11865 11:55:25.880639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066534/tftp-deploy-01176oom/modules
11866 11:55:25.888263 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066534
11867 11:55:26.265118 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066534
11868 11:55:26.265303 Job finished correctly