Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 37
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:51:15.296465 lava-dispatcher, installed at version: 2023.10
2 11:51:15.296664 start: 0 validate
3 11:51:15.296790 Start time: 2023-11-23 11:51:15.296783+00:00 (UTC)
4 11:51:15.296908 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:51:15.297043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:51:15.565573 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:51:15.566309 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:51:33.334510 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:51:33.335283 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:51:33.604157 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:51:33.604873 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:51:34.132468 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:51:34.133209 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:51:37.139995 validate duration: 21.84
16 11:51:37.140261 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:51:37.140360 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:51:37.140451 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:51:37.140569 Not decompressing ramdisk as can be used compressed.
20 11:51:37.140653 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:51:37.140723 saving as /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/ramdisk/initrd.cpio.gz
22 11:51:37.140790 total size: 4665395 (4 MB)
23 11:51:37.405389 progress 0 % (0 MB)
24 11:51:37.406919 progress 5 % (0 MB)
25 11:51:37.408283 progress 10 % (0 MB)
26 11:51:37.409513 progress 15 % (0 MB)
27 11:51:37.410865 progress 20 % (0 MB)
28 11:51:37.412182 progress 25 % (1 MB)
29 11:51:37.413487 progress 30 % (1 MB)
30 11:51:37.414809 progress 35 % (1 MB)
31 11:51:37.416034 progress 40 % (1 MB)
32 11:51:37.417511 progress 45 % (2 MB)
33 11:51:37.418839 progress 50 % (2 MB)
34 11:51:37.420140 progress 55 % (2 MB)
35 11:51:37.421458 progress 60 % (2 MB)
36 11:51:37.422945 progress 65 % (2 MB)
37 11:51:37.424188 progress 70 % (3 MB)
38 11:51:37.425496 progress 75 % (3 MB)
39 11:51:37.426811 progress 80 % (3 MB)
40 11:51:37.428275 progress 85 % (3 MB)
41 11:51:37.429594 progress 90 % (4 MB)
42 11:51:37.430887 progress 95 % (4 MB)
43 11:51:37.432204 progress 100 % (4 MB)
44 11:51:37.432360 4 MB downloaded in 0.29 s (15.26 MB/s)
45 11:51:37.432523 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:51:37.432757 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:51:37.432862 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:51:37.432978 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:51:37.433131 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:51:37.433202 saving as /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/kernel/Image
52 11:51:37.433268 total size: 49107456 (46 MB)
53 11:51:37.433329 No compression specified
54 11:51:37.434468 progress 0 % (0 MB)
55 11:51:37.447619 progress 5 % (2 MB)
56 11:51:37.461272 progress 10 % (4 MB)
57 11:51:37.474614 progress 15 % (7 MB)
58 11:51:37.487845 progress 20 % (9 MB)
59 11:51:37.501013 progress 25 % (11 MB)
60 11:51:37.514162 progress 30 % (14 MB)
61 11:51:37.527337 progress 35 % (16 MB)
62 11:51:37.540600 progress 40 % (18 MB)
63 11:51:37.554054 progress 45 % (21 MB)
64 11:51:37.567294 progress 50 % (23 MB)
65 11:51:37.580764 progress 55 % (25 MB)
66 11:51:37.593977 progress 60 % (28 MB)
67 11:51:37.607151 progress 65 % (30 MB)
68 11:51:37.620281 progress 70 % (32 MB)
69 11:51:37.633432 progress 75 % (35 MB)
70 11:51:37.646812 progress 80 % (37 MB)
71 11:51:37.660133 progress 85 % (39 MB)
72 11:51:37.673461 progress 90 % (42 MB)
73 11:51:37.686732 progress 95 % (44 MB)
74 11:51:37.699812 progress 100 % (46 MB)
75 11:51:37.700066 46 MB downloaded in 0.27 s (175.54 MB/s)
76 11:51:37.700225 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:51:37.700465 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:51:37.700554 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:51:37.700642 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:51:37.700776 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:51:37.700846 saving as /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/dtb/mt8192-asurada-spherion-r0.dtb
83 11:51:37.700908 total size: 47278 (0 MB)
84 11:51:37.700969 No compression specified
85 11:51:37.702358 progress 69 % (0 MB)
86 11:51:37.702677 progress 100 % (0 MB)
87 11:51:37.702833 0 MB downloaded in 0.00 s (23.44 MB/s)
88 11:51:37.702958 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:51:37.703197 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:51:37.703320 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:51:37.703428 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:51:37.703542 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:51:37.703611 saving as /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/nfsrootfs/full.rootfs.tar
95 11:51:37.703674 total size: 200813988 (191 MB)
96 11:51:37.703737 Using unxz to decompress xz
97 11:51:37.707536 progress 0 % (0 MB)
98 11:51:38.244977 progress 5 % (9 MB)
99 11:51:38.754125 progress 10 % (19 MB)
100 11:51:39.347598 progress 15 % (28 MB)
101 11:51:39.719534 progress 20 % (38 MB)
102 11:51:40.047228 progress 25 % (47 MB)
103 11:51:40.639222 progress 30 % (57 MB)
104 11:51:41.201425 progress 35 % (67 MB)
105 11:51:41.817484 progress 40 % (76 MB)
106 11:51:42.384058 progress 45 % (86 MB)
107 11:51:42.985314 progress 50 % (95 MB)
108 11:51:43.612601 progress 55 % (105 MB)
109 11:51:44.275647 progress 60 % (114 MB)
110 11:51:44.402772 progress 65 % (124 MB)
111 11:51:44.546461 progress 70 % (134 MB)
112 11:51:44.649196 progress 75 % (143 MB)
113 11:51:44.720939 progress 80 % (153 MB)
114 11:51:44.789212 progress 85 % (162 MB)
115 11:51:44.889354 progress 90 % (172 MB)
116 11:51:45.163504 progress 95 % (181 MB)
117 11:51:45.740288 progress 100 % (191 MB)
118 11:51:45.745780 191 MB downloaded in 8.04 s (23.81 MB/s)
119 11:51:45.746165 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:51:45.746599 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:51:45.746723 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:51:45.746850 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:51:45.747034 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:51:45.747141 saving as /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/modules/modules.tar
126 11:51:45.747235 total size: 8621364 (8 MB)
127 11:51:45.747331 Using unxz to decompress xz
128 11:51:46.007607 progress 0 % (0 MB)
129 11:51:46.028639 progress 5 % (0 MB)
130 11:51:46.052187 progress 10 % (0 MB)
131 11:51:46.077078 progress 15 % (1 MB)
132 11:51:46.100742 progress 20 % (1 MB)
133 11:51:46.124926 progress 25 % (2 MB)
134 11:51:46.150715 progress 30 % (2 MB)
135 11:51:46.177539 progress 35 % (2 MB)
136 11:51:46.201220 progress 40 % (3 MB)
137 11:51:46.225533 progress 45 % (3 MB)
138 11:51:46.250858 progress 50 % (4 MB)
139 11:51:46.275610 progress 55 % (4 MB)
140 11:51:46.300795 progress 60 % (4 MB)
141 11:51:46.328123 progress 65 % (5 MB)
142 11:51:46.353025 progress 70 % (5 MB)
143 11:51:46.377135 progress 75 % (6 MB)
144 11:51:46.403516 progress 80 % (6 MB)
145 11:51:46.428797 progress 85 % (7 MB)
146 11:51:46.453734 progress 90 % (7 MB)
147 11:51:46.483578 progress 95 % (7 MB)
148 11:51:46.512819 progress 100 % (8 MB)
149 11:51:46.517545 8 MB downloaded in 0.77 s (10.67 MB/s)
150 11:51:46.517858 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:51:46.518235 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:51:46.518367 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:51:46.518513 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:51:49.744413 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4
156 11:51:49.744646 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:51:49.744788 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:51:49.745016 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq
159 11:51:49.745191 makedir: /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin
160 11:51:49.745329 makedir: /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/tests
161 11:51:49.745468 makedir: /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/results
162 11:51:49.745622 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-add-keys
163 11:51:49.745826 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-add-sources
164 11:51:49.746008 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-background-process-start
165 11:51:49.746160 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-background-process-stop
166 11:51:49.746286 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-common-functions
167 11:51:49.746415 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-echo-ipv4
168 11:51:49.746575 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-install-packages
169 11:51:49.746695 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-installed-packages
170 11:51:49.746813 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-os-build
171 11:51:49.746933 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-probe-channel
172 11:51:49.747052 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-probe-ip
173 11:51:49.747170 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-target-ip
174 11:51:49.747287 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-target-mac
175 11:51:49.747411 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-target-storage
176 11:51:49.747533 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-case
177 11:51:49.747653 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-event
178 11:51:49.747770 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-feedback
179 11:51:49.747888 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-raise
180 11:51:49.748005 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-reference
181 11:51:49.748128 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-runner
182 11:51:49.748246 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-set
183 11:51:49.748365 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-test-shell
184 11:51:49.748486 Updating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-add-keys (debian)
185 11:51:49.748638 Updating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-add-sources (debian)
186 11:51:49.748773 Updating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-install-packages (debian)
187 11:51:49.748906 Updating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-installed-packages (debian)
188 11:51:49.749037 Updating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/bin/lava-os-build (debian)
189 11:51:49.749151 Creating /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/environment
190 11:51:49.749243 LAVA metadata
191 11:51:49.749315 - LAVA_JOB_ID=12066530
192 11:51:49.749378 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:51:49.749482 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:51:49.749559 skipped lava-vland-overlay
195 11:51:49.749634 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:51:49.749714 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:51:49.749774 skipped lava-multinode-overlay
198 11:51:49.749846 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:51:49.749923 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:51:49.749997 Loading test definitions
201 11:51:49.750084 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:51:49.750156 Using /lava-12066530 at stage 0
203 11:51:49.750660 uuid=12066530_1.6.2.3.1 testdef=None
204 11:51:49.750751 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:51:49.750836 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:51:49.751275 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:51:49.751494 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:51:49.752031 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:51:49.752267 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:51:49.752829 runner path: /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/0/tests/0_timesync-off test_uuid 12066530_1.6.2.3.1
213 11:51:49.752979 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:51:49.753202 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:51:49.753274 Using /lava-12066530 at stage 0
217 11:51:49.753369 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:51:49.753448 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/0/tests/1_kselftest-dt'
219 11:52:05.449354 Running '/usr/bin/git checkout kernelci.org
220 11:52:05.594373 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 11:52:05.595223 uuid=12066530_1.6.2.3.5 testdef=None
222 11:52:05.595399 end: 1.6.2.3.5 git-repo-action (duration 00:00:16) [common]
224 11:52:05.595653 start: 1.6.2.3.6 test-overlay (timeout 00:09:32) [common]
225 11:52:05.596395 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:52:05.596629 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:32) [common]
228 11:52:05.597625 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:52:05.597859 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:32) [common]
231 11:52:05.598818 runner path: /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/0/tests/1_kselftest-dt test_uuid 12066530_1.6.2.3.5
232 11:52:05.598913 BOARD='mt8192-asurada-spherion-r0'
233 11:52:05.599031 BRANCH='cip-gitlab'
234 11:52:05.599132 SKIPFILE='/dev/null'
235 11:52:05.599223 SKIP_INSTALL='True'
236 11:52:05.599301 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:52:05.599365 TST_CASENAME=''
238 11:52:05.599422 TST_CMDFILES='dt'
239 11:52:05.599564 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:52:05.599769 Creating lava-test-runner.conf files
242 11:52:05.599835 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066530/lava-overlay-1p1iktyq/lava-12066530/0 for stage 0
243 11:52:05.599926 - 0_timesync-off
244 11:52:05.599993 - 1_kselftest-dt
245 11:52:05.600086 end: 1.6.2.3 test-definition (duration 00:00:16) [common]
246 11:52:05.600172 start: 1.6.2.4 compress-overlay (timeout 00:09:32) [common]
247 11:52:13.039654 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:52:13.039836 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:24) [common]
249 11:52:13.039926 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:52:13.040032 end: 1.6.2 lava-overlay (duration 00:00:23) [common]
251 11:52:13.040126 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:24) [common]
252 11:52:13.154638 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:52:13.154989 start: 1.6.4 extract-modules (timeout 00:09:24) [common]
254 11:52:13.155102 extracting modules file /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4
255 11:52:13.367842 extracting modules file /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066530/extract-overlay-ramdisk-3z4ywou5/ramdisk
256 11:52:13.572941 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:52:13.573117 start: 1.6.5 apply-overlay-tftp (timeout 00:09:24) [common]
258 11:52:13.573215 [common] Applying overlay to NFS
259 11:52:13.573284 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066530/compress-overlay-68jkubde/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4
260 11:52:14.477353 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:52:14.477522 start: 1.6.6 configure-preseed-file (timeout 00:09:23) [common]
262 11:52:14.477616 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:52:14.477704 start: 1.6.7 compress-ramdisk (timeout 00:09:23) [common]
264 11:52:14.477785 Building ramdisk /var/lib/lava/dispatcher/tmp/12066530/extract-overlay-ramdisk-3z4ywou5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066530/extract-overlay-ramdisk-3z4ywou5/ramdisk
265 11:52:14.783477 >> 119398 blocks
266 11:52:16.767226 rename /var/lib/lava/dispatcher/tmp/12066530/extract-overlay-ramdisk-3z4ywou5/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/ramdisk/ramdisk.cpio.gz
267 11:52:16.767662 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:52:16.767784 start: 1.6.8 prepare-kernel (timeout 00:09:20) [common]
269 11:52:16.767887 start: 1.6.8.1 prepare-fit (timeout 00:09:20) [common]
270 11:52:16.767996 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/kernel/Image'
271 11:52:29.628392 Returned 0 in 12 seconds
272 11:52:29.729009 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/kernel/image.itb
273 11:52:30.114507 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:52:30.114879 output: Created: Thu Nov 23 11:52:30 2023
275 11:52:30.114958 output: Image 0 (kernel-1)
276 11:52:30.115026 output: Description:
277 11:52:30.115106 output: Created: Thu Nov 23 11:52:30 2023
278 11:52:30.115171 output: Type: Kernel Image
279 11:52:30.115234 output: Compression: lzma compressed
280 11:52:30.115297 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
281 11:52:30.115374 output: Architecture: AArch64
282 11:52:30.115438 output: OS: Linux
283 11:52:30.115497 output: Load Address: 0x00000000
284 11:52:30.115557 output: Entry Point: 0x00000000
285 11:52:30.115627 output: Hash algo: crc32
286 11:52:30.115682 output: Hash value: e6d7c86f
287 11:52:30.115740 output: Image 1 (fdt-1)
288 11:52:30.115813 output: Description: mt8192-asurada-spherion-r0
289 11:52:30.115901 output: Created: Thu Nov 23 11:52:30 2023
290 11:52:30.115986 output: Type: Flat Device Tree
291 11:52:30.116079 output: Compression: uncompressed
292 11:52:30.116164 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:52:30.116249 output: Architecture: AArch64
294 11:52:30.116342 output: Hash algo: crc32
295 11:52:30.116426 output: Hash value: cc4352de
296 11:52:30.116511 output: Image 2 (ramdisk-1)
297 11:52:30.116604 output: Description: unavailable
298 11:52:30.116689 output: Created: Thu Nov 23 11:52:30 2023
299 11:52:30.116780 output: Type: RAMDisk Image
300 11:52:30.116866 output: Compression: Unknown Compression
301 11:52:30.116950 output: Data Size: 17799583 Bytes = 17382.41 KiB = 16.98 MiB
302 11:52:30.117042 output: Architecture: AArch64
303 11:52:30.117128 output: OS: Linux
304 11:52:30.117212 output: Load Address: unavailable
305 11:52:30.117304 output: Entry Point: unavailable
306 11:52:30.117389 output: Hash algo: crc32
307 11:52:30.117473 output: Hash value: 3be7e33c
308 11:52:30.117566 output: Default Configuration: 'conf-1'
309 11:52:30.117651 output: Configuration 0 (conf-1)
310 11:52:30.117735 output: Description: mt8192-asurada-spherion-r0
311 11:52:30.117827 output: Kernel: kernel-1
312 11:52:30.117911 output: Init Ramdisk: ramdisk-1
313 11:52:30.117995 output: FDT: fdt-1
314 11:52:30.118087 output: Loadables: kernel-1
315 11:52:30.118171 output:
316 11:52:30.118411 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:52:30.118549 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:52:30.118655 end: 1.6 prepare-tftp-overlay (duration 00:00:44) [common]
319 11:52:30.118757 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:07) [common]
320 11:52:30.118853 No LXC device requested
321 11:52:30.118934 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:52:30.119032 start: 1.8 deploy-device-env (timeout 00:09:07) [common]
323 11:52:30.119116 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:52:30.119185 Checking files for TFTP limit of 4294967296 bytes.
325 11:52:30.119704 end: 1 tftp-deploy (duration 00:00:53) [common]
326 11:52:30.119827 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:52:30.119927 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:52:30.120066 substitutions:
329 11:52:30.120138 - {DTB}: 12066530/tftp-deploy-2foalg4i/dtb/mt8192-asurada-spherion-r0.dtb
330 11:52:30.120204 - {INITRD}: 12066530/tftp-deploy-2foalg4i/ramdisk/ramdisk.cpio.gz
331 11:52:30.120269 - {KERNEL}: 12066530/tftp-deploy-2foalg4i/kernel/Image
332 11:52:30.120365 - {LAVA_MAC}: None
333 11:52:30.120454 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4
334 11:52:30.120551 - {NFS_SERVER_IP}: 192.168.201.1
335 11:52:30.120639 - {PRESEED_CONFIG}: None
336 11:52:30.120726 - {PRESEED_LOCAL}: None
337 11:52:30.120823 - {RAMDISK}: 12066530/tftp-deploy-2foalg4i/ramdisk/ramdisk.cpio.gz
338 11:52:30.120910 - {ROOT_PART}: None
339 11:52:30.120997 - {ROOT}: None
340 11:52:30.121093 - {SERVER_IP}: 192.168.201.1
341 11:52:30.121179 - {TEE}: None
342 11:52:30.121268 Parsed boot commands:
343 11:52:30.121358 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:52:30.121589 Parsed boot commands: tftpboot 192.168.201.1 12066530/tftp-deploy-2foalg4i/kernel/image.itb 12066530/tftp-deploy-2foalg4i/kernel/cmdline
345 11:52:30.121709 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:52:30.121835 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:52:30.121959 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:52:30.122086 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:52:30.122190 Not connected, no need to disconnect.
350 11:52:30.122306 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:52:30.122432 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:52:30.122540 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 11:52:30.126128 Setting prompt string to ['lava-test: # ']
354 11:52:30.126530 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:52:30.126675 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:52:30.126819 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:52:30.126939 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:52:30.127134 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 11:52:35.259408 >> Command sent successfully.
360 11:52:35.261807 Returned 0 in 5 seconds
361 11:52:35.362609 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:52:35.364361 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:52:35.365171 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:52:35.365885 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:52:35.366404 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:52:35.367030 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:52:35.367797 [Enter `^Ec?' for help]
369 11:52:35.540161
370 11:52:35.540302
371 11:52:35.540378 F0: 102B 0000
372 11:52:35.540444
373 11:52:35.540507 F3: 1001 0000 [0200]
374 11:52:35.540567
375 11:52:35.543847 F3: 1001 0000
376 11:52:35.543931
377 11:52:35.543998 F7: 102D 0000
378 11:52:35.544061
379 11:52:35.544120 F1: 0000 0000
380 11:52:35.547540
381 11:52:35.547624 V0: 0000 0000 [0001]
382 11:52:35.547691
383 11:52:35.547754 00: 0007 8000
384 11:52:35.547818
385 11:52:35.551417 01: 0000 0000
386 11:52:35.551502
387 11:52:35.551568 BP: 0C00 0209 [0000]
388 11:52:35.551630
389 11:52:35.551688 G0: 1182 0000
390 11:52:35.555113
391 11:52:35.555196 EC: 0000 0021 [4000]
392 11:52:35.555263
393 11:52:35.558511 S7: 0000 0000 [0000]
394 11:52:35.558594
395 11:52:35.558660 CC: 0000 0000 [0001]
396 11:52:35.558722
397 11:52:35.561754 T0: 0000 0040 [010F]
398 11:52:35.561873
399 11:52:35.561946 Jump to BL
400 11:52:35.562009
401 11:52:35.586879
402 11:52:35.586968
403 11:52:35.587034
404 11:52:35.594477 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:52:35.598112 ARM64: Exception handlers installed.
406 11:52:35.601771 ARM64: Testing exception
407 11:52:35.601858 ARM64: Done test exception
408 11:52:35.609779 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:52:35.620603 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:52:35.628153 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:52:35.637664 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:52:35.644141 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:52:35.654377 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:52:35.664564 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:52:35.671418 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:52:35.689345 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:52:35.692958 WDT: Last reset was cold boot
418 11:52:35.696439 SPI1(PAD0) initialized at 2873684 Hz
419 11:52:35.699796 SPI5(PAD0) initialized at 992727 Hz
420 11:52:35.703389 VBOOT: Loading verstage.
421 11:52:35.709969 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:52:35.713053 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:52:35.716462 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:52:35.719462 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:52:35.726964 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:52:35.733823 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:52:35.744546 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:52:35.744660
429 11:52:35.744764
430 11:52:35.754639 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:52:35.757886 ARM64: Exception handlers installed.
432 11:52:35.760983 ARM64: Testing exception
433 11:52:35.761096 ARM64: Done test exception
434 11:52:35.769359 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:52:35.771120 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:52:35.785577 Probing TPM: . done!
437 11:52:35.785693 TPM ready after 0 ms
438 11:52:35.792631 Connected to device vid:did:rid of 1ae0:0028:00
439 11:52:35.799932 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:52:35.855322 Initialized TPM device CR50 revision 0
441 11:52:35.867286 tlcl_send_startup: Startup return code is 0
442 11:52:35.867403 TPM: setup succeeded
443 11:52:35.878304 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:52:35.887443 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:52:35.897237 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:52:35.906854 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:52:35.910252 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:52:35.918475 in-header: 03 07 00 00 08 00 00 00
449 11:52:35.922030 in-data: aa e4 47 04 13 02 00 00
450 11:52:35.925811 Chrome EC: UHEPI supported
451 11:52:35.932751 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:52:35.936802 in-header: 03 ad 00 00 08 00 00 00
453 11:52:35.940504 in-data: 00 20 20 08 00 00 00 00
454 11:52:35.940583 Phase 1
455 11:52:35.944119 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:52:35.951591 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:52:35.955445 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:52:35.959035 Recovery requested (1009000e)
459 11:52:35.968237 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:52:35.973351 tlcl_extend: response is 0
461 11:52:35.983226 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:52:35.988912 tlcl_extend: response is 0
463 11:52:35.995779 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:52:36.015834 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:52:36.022505 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:52:36.022587
467 11:52:36.022654
468 11:52:36.032857 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:52:36.036176 ARM64: Exception handlers installed.
470 11:52:36.036280 ARM64: Testing exception
471 11:52:36.039852 ARM64: Done test exception
472 11:52:36.060896 pmic_efuse_setting: Set efuses in 11 msecs
473 11:52:36.064716 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:52:36.070905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:52:36.074738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:52:36.081333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:52:36.084703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:52:36.088029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:52:36.095598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:52:36.098818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:52:36.102786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:52:36.109950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:52:36.113831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:52:36.117615 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:52:36.121658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:52:36.128122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:52:36.131281 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:52:36.138097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:52:36.145120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:52:36.148703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:52:36.156245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:52:36.160141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:52:36.166987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:52:36.174062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:52:36.177467 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:52:36.184077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:52:36.187535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:52:36.194340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:52:36.200695 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:52:36.204590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:52:36.211050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:52:36.214241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:52:36.220845 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:52:36.224006 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:52:36.230841 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:52:36.234069 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:52:36.240739 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:52:36.244257 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:52:36.250811 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:52:36.254194 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:52:36.260800 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:52:36.264303 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:52:36.267521 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:52:36.274285 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:52:36.277639 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:52:36.281024 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:52:36.285017 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:52:36.291941 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:52:36.296159 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:52:36.299615 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:52:36.303048 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:52:36.306845 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:52:36.310323 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:52:36.314394 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:52:36.325898 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:52:36.333220 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:52:36.336800 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:52:36.344736 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:52:36.355744 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:52:36.358454 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:52:36.361611 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:52:36.368674 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:52:36.374848 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 11:52:36.378060 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:52:36.385434 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:52:36.388496 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:52:36.397929 [RTC]rtc_get_frequency_meter,154: input=15, output=771
538 11:52:36.407486 [RTC]rtc_get_frequency_meter,154: input=23, output=958
539 11:52:36.417652 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 11:52:36.427036 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 11:52:36.437167 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 11:52:36.440722 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 11:52:36.444000 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 11:52:36.450648 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 11:52:36.454055 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 11:52:36.457584 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 11:52:36.460667 ADC[4]: Raw value=902876 ID=7
548 11:52:36.463973 ADC[3]: Raw value=213179 ID=1
549 11:52:36.464060 RAM Code: 0x71
550 11:52:36.467409 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 11:52:36.474154 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 11:52:36.484245 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 11:52:36.490735 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:52:36.493815 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 11:52:36.497547 in-header: 03 07 00 00 08 00 00 00
556 11:52:36.500556 in-data: aa e4 47 04 13 02 00 00
557 11:52:36.500641 Chrome EC: UHEPI supported
558 11:52:36.507571 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 11:52:36.510727 in-header: 03 ed 00 00 08 00 00 00
560 11:52:36.513839 in-data: 80 20 60 08 00 00 00 00
561 11:52:36.517543 MRC: failed to locate region type 0.
562 11:52:36.524022 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 11:52:36.527286 DRAM-K: Running full calibration
564 11:52:36.534325 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 11:52:36.537538 header.status = 0x0
566 11:52:36.537624 header.version = 0x6 (expected: 0x6)
567 11:52:36.544165 header.size = 0xd00 (expected: 0xd00)
568 11:52:36.544258 header.flags = 0x0
569 11:52:36.550797 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 11:52:36.568037 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
571 11:52:36.574771 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 11:52:36.578098 dram_init: ddr_geometry: 2
573 11:52:36.581168 [EMI] MDL number = 2
574 11:52:36.581253 [EMI] Get MDL freq = 0
575 11:52:36.584439 dram_init: ddr_type: 0
576 11:52:36.584524 is_discrete_lpddr4: 1
577 11:52:36.587953 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 11:52:36.588039
579 11:52:36.588107
580 11:52:36.591160 [Bian_co] ETT version 0.0.0.1
581 11:52:36.598198 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 11:52:36.598309
583 11:52:36.601680 dramc_set_vcore_voltage set vcore to 650000
584 11:52:36.601765 Read voltage for 800, 4
585 11:52:36.604619 Vio18 = 0
586 11:52:36.604704 Vcore = 650000
587 11:52:36.604772 Vdram = 0
588 11:52:36.607985 Vddq = 0
589 11:52:36.608070 Vmddr = 0
590 11:52:36.611084 dram_init: config_dvfs: 1
591 11:52:36.614740 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 11:52:36.621249 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 11:52:36.624586 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 11:52:36.627841 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 11:52:36.631265 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 11:52:36.634938 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 11:52:36.638071 MEM_TYPE=3, freq_sel=18
598 11:52:36.641402 sv_algorithm_assistance_LP4_1600
599 11:52:36.644710 ============ PULL DRAM RESETB DOWN ============
600 11:52:36.648260 ========== PULL DRAM RESETB DOWN end =========
601 11:52:36.654821 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 11:52:36.658713 ===================================
603 11:52:36.658799 LPDDR4 DRAM CONFIGURATION
604 11:52:36.661662 ===================================
605 11:52:36.664867 EX_ROW_EN[0] = 0x0
606 11:52:36.668009 EX_ROW_EN[1] = 0x0
607 11:52:36.668095 LP4Y_EN = 0x0
608 11:52:36.671733 WORK_FSP = 0x0
609 11:52:36.671819 WL = 0x2
610 11:52:36.675104 RL = 0x2
611 11:52:36.675189 BL = 0x2
612 11:52:36.678321 RPST = 0x0
613 11:52:36.678432 RD_PRE = 0x0
614 11:52:36.681393 WR_PRE = 0x1
615 11:52:36.681478 WR_PST = 0x0
616 11:52:36.684538 DBI_WR = 0x0
617 11:52:36.684623 DBI_RD = 0x0
618 11:52:36.688102 OTF = 0x1
619 11:52:36.691553 ===================================
620 11:52:36.694693 ===================================
621 11:52:36.694778 ANA top config
622 11:52:36.697913 ===================================
623 11:52:36.701235 DLL_ASYNC_EN = 0
624 11:52:36.705114 ALL_SLAVE_EN = 1
625 11:52:36.708114 NEW_RANK_MODE = 1
626 11:52:36.708197 DLL_IDLE_MODE = 1
627 11:52:36.711192 LP45_APHY_COMB_EN = 1
628 11:52:36.714853 TX_ODT_DIS = 1
629 11:52:36.717932 NEW_8X_MODE = 1
630 11:52:36.721722 ===================================
631 11:52:36.724827 ===================================
632 11:52:36.728298 data_rate = 1600
633 11:52:36.728403 CKR = 1
634 11:52:36.731484 DQ_P2S_RATIO = 8
635 11:52:36.735262 ===================================
636 11:52:36.738055 CA_P2S_RATIO = 8
637 11:52:36.741697 DQ_CA_OPEN = 0
638 11:52:36.745444 DQ_SEMI_OPEN = 0
639 11:52:36.745519 CA_SEMI_OPEN = 0
640 11:52:36.748310 CA_FULL_RATE = 0
641 11:52:36.751699 DQ_CKDIV4_EN = 1
642 11:52:36.754976 CA_CKDIV4_EN = 1
643 11:52:36.758169 CA_PREDIV_EN = 0
644 11:52:36.761373 PH8_DLY = 0
645 11:52:36.761470 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 11:52:36.765099 DQ_AAMCK_DIV = 4
647 11:52:36.768402 CA_AAMCK_DIV = 4
648 11:52:36.771524 CA_ADMCK_DIV = 4
649 11:52:36.774951 DQ_TRACK_CA_EN = 0
650 11:52:36.778177 CA_PICK = 800
651 11:52:36.778279 CA_MCKIO = 800
652 11:52:36.781602 MCKIO_SEMI = 0
653 11:52:36.784890 PLL_FREQ = 3068
654 11:52:36.788593 DQ_UI_PI_RATIO = 32
655 11:52:36.791897 CA_UI_PI_RATIO = 0
656 11:52:36.794975 ===================================
657 11:52:36.798291 ===================================
658 11:52:36.801512 memory_type:LPDDR4
659 11:52:36.801587 GP_NUM : 10
660 11:52:36.804937 SRAM_EN : 1
661 11:52:36.805043 MD32_EN : 0
662 11:52:36.808848 ===================================
663 11:52:36.811914 [ANA_INIT] >>>>>>>>>>>>>>
664 11:52:36.815608 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 11:52:36.819204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:52:36.823040 ===================================
667 11:52:36.823122 data_rate = 1600,PCW = 0X7600
668 11:52:36.826565 ===================================
669 11:52:36.829725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 11:52:36.837346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 11:52:36.841140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 11:52:36.848306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 11:52:36.851510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 11:52:36.855299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 11:52:36.855374 [ANA_INIT] flow start
676 11:52:36.858874 [ANA_INIT] PLL >>>>>>>>
677 11:52:36.858945 [ANA_INIT] PLL <<<<<<<<
678 11:52:36.862520 [ANA_INIT] MIDPI >>>>>>>>
679 11:52:36.866164 [ANA_INIT] MIDPI <<<<<<<<
680 11:52:36.866244 [ANA_INIT] DLL >>>>>>>>
681 11:52:36.869621 [ANA_INIT] flow end
682 11:52:36.873223 ============ LP4 DIFF to SE enter ============
683 11:52:36.877642 ============ LP4 DIFF to SE exit ============
684 11:52:36.881093 [ANA_INIT] <<<<<<<<<<<<<
685 11:52:36.884844 [Flow] Enable top DCM control >>>>>
686 11:52:36.884943 [Flow] Enable top DCM control <<<<<
687 11:52:36.888400 Enable DLL master slave shuffle
688 11:52:36.895853 ==============================================================
689 11:52:36.895961 Gating Mode config
690 11:52:36.903440 ==============================================================
691 11:52:36.903550 Config description:
692 11:52:36.914438 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 11:52:36.922247 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 11:52:36.926208 SELPH_MODE 0: By rank 1: By Phase
695 11:52:36.929635 ==============================================================
696 11:52:36.933534 GAT_TRACK_EN = 1
697 11:52:36.937885 RX_GATING_MODE = 2
698 11:52:36.940721 RX_GATING_TRACK_MODE = 2
699 11:52:36.940803 SELPH_MODE = 1
700 11:52:36.944357 PICG_EARLY_EN = 1
701 11:52:36.948307 VALID_LAT_VALUE = 1
702 11:52:36.955641 ==============================================================
703 11:52:36.959660 Enter into Gating configuration >>>>
704 11:52:36.959749 Exit from Gating configuration <<<<
705 11:52:36.963198 Enter into DVFS_PRE_config >>>>>
706 11:52:36.974275 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 11:52:36.977952 Exit from DVFS_PRE_config <<<<<
708 11:52:36.981994 Enter into PICG configuration >>>>
709 11:52:36.985418 Exit from PICG configuration <<<<
710 11:52:36.985497 [RX_INPUT] configuration >>>>>
711 11:52:36.989389 [RX_INPUT] configuration <<<<<
712 11:52:36.996726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 11:52:37.000473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 11:52:37.007987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 11:52:37.011444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 11:52:37.019080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:52:37.026745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:52:37.030400 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 11:52:37.033817 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 11:52:37.037616 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 11:52:37.041001 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 11:52:37.045061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 11:52:37.048892 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 11:52:37.052832 ===================================
725 11:52:37.056434 LPDDR4 DRAM CONFIGURATION
726 11:52:37.060115 ===================================
727 11:52:37.060201 EX_ROW_EN[0] = 0x0
728 11:52:37.063722 EX_ROW_EN[1] = 0x0
729 11:52:37.063807 LP4Y_EN = 0x0
730 11:52:37.067396 WORK_FSP = 0x0
731 11:52:37.067483 WL = 0x2
732 11:52:37.071636 RL = 0x2
733 11:52:37.071721 BL = 0x2
734 11:52:37.074832 RPST = 0x0
735 11:52:37.074918 RD_PRE = 0x0
736 11:52:37.078516 WR_PRE = 0x1
737 11:52:37.078601 WR_PST = 0x0
738 11:52:37.078670 DBI_WR = 0x0
739 11:52:37.082646 DBI_RD = 0x0
740 11:52:37.082732 OTF = 0x1
741 11:52:37.086351 ===================================
742 11:52:37.089575 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 11:52:37.093906 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 11:52:37.101123 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 11:52:37.104866 ===================================
746 11:52:37.104952 LPDDR4 DRAM CONFIGURATION
747 11:52:37.108560 ===================================
748 11:52:37.112188 EX_ROW_EN[0] = 0x10
749 11:52:37.112274 EX_ROW_EN[1] = 0x0
750 11:52:37.115652 LP4Y_EN = 0x0
751 11:52:37.115738 WORK_FSP = 0x0
752 11:52:37.120003 WL = 0x2
753 11:52:37.120088 RL = 0x2
754 11:52:37.120156 BL = 0x2
755 11:52:37.123611 RPST = 0x0
756 11:52:37.123697 RD_PRE = 0x0
757 11:52:37.127305 WR_PRE = 0x1
758 11:52:37.127389 WR_PST = 0x0
759 11:52:37.131170 DBI_WR = 0x0
760 11:52:37.131254 DBI_RD = 0x0
761 11:52:37.135535 OTF = 0x1
762 11:52:37.135619 ===================================
763 11:52:37.142149 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 11:52:37.147022 nWR fixed to 40
765 11:52:37.150657 [ModeRegInit_LP4] CH0 RK0
766 11:52:37.150741 [ModeRegInit_LP4] CH0 RK1
767 11:52:37.154100 [ModeRegInit_LP4] CH1 RK0
768 11:52:37.154184 [ModeRegInit_LP4] CH1 RK1
769 11:52:37.157496 match AC timing 13
770 11:52:37.161368 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 11:52:37.164581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 11:52:37.171324 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 11:52:37.174806 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 11:52:37.177896 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 11:52:37.181382 [EMI DOE] emi_dcm 0
776 11:52:37.184442 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 11:52:37.184526 ==
778 11:52:37.187769 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:52:37.194371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:52:37.194498 ==
781 11:52:37.197858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:52:37.204557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:52:37.214488 [CA 0] Center 38 (7~69) winsize 63
784 11:52:37.217428 [CA 1] Center 38 (7~69) winsize 63
785 11:52:37.220829 [CA 2] Center 35 (5~66) winsize 62
786 11:52:37.224046 [CA 3] Center 35 (5~66) winsize 62
787 11:52:37.227473 [CA 4] Center 34 (4~65) winsize 62
788 11:52:37.230905 [CA 5] Center 33 (3~64) winsize 62
789 11:52:37.231020
790 11:52:37.234019 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 11:52:37.234123
792 11:52:37.237540 [CATrainingPosCal] consider 1 rank data
793 11:52:37.240795 u2DelayCellTimex100 = 270/100 ps
794 11:52:37.244080 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 11:52:37.247308 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 11:52:37.254374 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 11:52:37.257497 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 11:52:37.260865 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:52:37.264052 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:52:37.264155
801 11:52:37.267639 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:52:37.267716
803 11:52:37.270899 [CBTSetCACLKResult] CA Dly = 33
804 11:52:37.270977 CS Dly: 6 (0~37)
805 11:52:37.274267 ==
806 11:52:37.274342 Dram Type= 6, Freq= 0, CH_0, rank 1
807 11:52:37.280722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 11:52:37.280803 ==
809 11:52:37.284357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 11:52:37.290695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 11:52:37.300364 [CA 0] Center 38 (7~69) winsize 63
812 11:52:37.304120 [CA 1] Center 38 (7~69) winsize 63
813 11:52:37.307347 [CA 2] Center 36 (6~67) winsize 62
814 11:52:37.310472 [CA 3] Center 36 (5~67) winsize 63
815 11:52:37.313872 [CA 4] Center 35 (4~66) winsize 63
816 11:52:37.317283 [CA 5] Center 34 (4~65) winsize 62
817 11:52:37.317387
818 11:52:37.320540 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 11:52:37.320662
820 11:52:37.323577 [CATrainingPosCal] consider 2 rank data
821 11:52:37.327202 u2DelayCellTimex100 = 270/100 ps
822 11:52:37.330568 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 11:52:37.333924 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 11:52:37.340485 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 11:52:37.344187 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 11:52:37.347466 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 11:52:37.350535 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 11:52:37.350640
829 11:52:37.353997 CA PerBit enable=1, Macro0, CA PI delay=34
830 11:52:37.354099
831 11:52:37.357362 [CBTSetCACLKResult] CA Dly = 34
832 11:52:37.357467 CS Dly: 6 (0~38)
833 11:52:37.357561
834 11:52:37.360974 ----->DramcWriteLeveling(PI) begin...
835 11:52:37.361082 ==
836 11:52:37.364822 Dram Type= 6, Freq= 0, CH_0, rank 0
837 11:52:37.370870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 11:52:37.370974 ==
839 11:52:37.374277 Write leveling (Byte 0): 32 => 32
840 11:52:37.377607 Write leveling (Byte 1): 28 => 28
841 11:52:37.377684 DramcWriteLeveling(PI) end<-----
842 11:52:37.377752
843 11:52:37.381059 ==
844 11:52:37.384085 Dram Type= 6, Freq= 0, CH_0, rank 0
845 11:52:37.387924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 11:52:37.388002 ==
847 11:52:37.390800 [Gating] SW mode calibration
848 11:52:37.398152 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 11:52:37.401904 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 11:52:37.405575 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 11:52:37.409778 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 11:52:37.416075 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:52:37.419466 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:52:37.423460 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:52:37.429839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:52:37.433412 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:52:37.436592 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:52:37.439838 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:52:37.446925 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:52:37.450297 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:52:37.453282 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:52:37.460354 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:52:37.463185 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:52:37.466665 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:52:37.473771 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:52:37.477044 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 11:52:37.480529 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
868 11:52:37.486712 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
869 11:52:37.490323 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:52:37.493562 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:52:37.500273 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:52:37.503621 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:52:37.507024 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:52:37.513437 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:52:37.516760 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
876 11:52:37.520047 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
877 11:52:37.523433 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
878 11:52:37.530320 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:52:37.533595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:52:37.536797 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:52:37.543388 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:52:37.546727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:52:37.550064 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
884 11:52:37.556852 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
885 11:52:37.559920 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:52:37.563235 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:52:37.570219 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:52:37.573598 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:52:37.576700 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:52:37.583516 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:52:37.586958 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
892 11:52:37.590009 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
893 11:52:37.596898 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 11:52:37.600151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:52:37.603471 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:52:37.607159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:52:37.613714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:52:37.616784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:52:37.620375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 11:52:37.627074 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 11:52:37.630287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:52:37.633488 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:52:37.640352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:52:37.643918 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:52:37.646860 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:52:37.653897 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:52:37.657073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:52:37.660256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:52:37.667104 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:52:37.670549 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:52:37.673941 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:52:37.680438 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:52:37.683821 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:52:37.686900 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:52:37.690672 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 11:52:37.697105 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 11:52:37.700303 Total UI for P1: 0, mck2ui 16
918 11:52:37.703657 best dqsien dly found for B0: ( 0, 14, 4)
919 11:52:37.706961 Total UI for P1: 0, mck2ui 16
920 11:52:37.710266 best dqsien dly found for B1: ( 0, 14, 6)
921 11:52:37.713685 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
922 11:52:37.717180 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
923 11:52:37.717290
924 11:52:37.720427 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
925 11:52:37.723749 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 11:52:37.727248 [Gating] SW calibration Done
927 11:52:37.727332 ==
928 11:52:37.730379 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:52:37.733793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:52:37.733879 ==
931 11:52:37.737423 RX Vref Scan: 0
932 11:52:37.737509
933 11:52:37.737576 RX Vref 0 -> 0, step: 1
934 11:52:37.737638
935 11:52:37.740470 RX Delay -130 -> 252, step: 16
936 11:52:37.743606 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
937 11:52:37.750932 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 11:52:37.753728 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
939 11:52:37.757455 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
940 11:52:37.760512 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 11:52:37.763929 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 11:52:37.770818 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 11:52:37.773833 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 11:52:37.777850 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 11:52:37.780707 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
946 11:52:37.783794 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
947 11:52:37.790617 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 11:52:37.794172 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
949 11:52:37.797519 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 11:52:37.801255 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 11:52:37.804014 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
952 11:52:37.807672 ==
953 11:52:37.807757 Dram Type= 6, Freq= 0, CH_0, rank 0
954 11:52:37.813851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 11:52:37.813936 ==
956 11:52:37.814004 DQS Delay:
957 11:52:37.817454 DQS0 = 0, DQS1 = 0
958 11:52:37.817539 DQM Delay:
959 11:52:37.821124 DQM0 = 93, DQM1 = 82
960 11:52:37.821234 DQ Delay:
961 11:52:37.824093 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
962 11:52:37.827385 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
963 11:52:37.830553 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
964 11:52:37.833985 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
965 11:52:37.834079
966 11:52:37.834146
967 11:52:37.834208 ==
968 11:52:37.837380 Dram Type= 6, Freq= 0, CH_0, rank 0
969 11:52:37.840855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 11:52:37.840941 ==
971 11:52:37.841007
972 11:52:37.841069
973 11:52:37.843927 TX Vref Scan disable
974 11:52:37.847728 == TX Byte 0 ==
975 11:52:37.850904 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
976 11:52:37.854116 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
977 11:52:37.857477 == TX Byte 1 ==
978 11:52:37.860928 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
979 11:52:37.864470 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
980 11:52:37.864584 ==
981 11:52:37.867935 Dram Type= 6, Freq= 0, CH_0, rank 0
982 11:52:37.870999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 11:52:37.871084 ==
984 11:52:37.885731 TX Vref=22, minBit 8, minWin=26, winSum=442
985 11:52:37.888819 TX Vref=24, minBit 8, minWin=27, winSum=446
986 11:52:37.892329 TX Vref=26, minBit 8, minWin=27, winSum=449
987 11:52:37.895539 TX Vref=28, minBit 0, minWin=28, winSum=453
988 11:52:37.898943 TX Vref=30, minBit 8, minWin=27, winSum=454
989 11:52:37.902085 TX Vref=32, minBit 9, minWin=27, winSum=456
990 11:52:37.909020 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
991 11:52:37.909124
992 11:52:37.912204 Final TX Range 1 Vref 28
993 11:52:37.912283
994 11:52:37.912347 ==
995 11:52:37.915498 Dram Type= 6, Freq= 0, CH_0, rank 0
996 11:52:37.918880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 11:52:37.918987 ==
998 11:52:37.919081
999 11:52:37.922222
1000 11:52:37.922333 TX Vref Scan disable
1001 11:52:37.925480 == TX Byte 0 ==
1002 11:52:37.928840 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1003 11:52:37.932296 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1004 11:52:37.935901 == TX Byte 1 ==
1005 11:52:37.939142 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1006 11:52:37.942187 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1007 11:52:37.942271
1008 11:52:37.945842 [DATLAT]
1009 11:52:37.945926 Freq=800, CH0 RK0
1010 11:52:37.945993
1011 11:52:37.949366 DATLAT Default: 0xa
1012 11:52:37.949449 0, 0xFFFF, sum = 0
1013 11:52:37.952516 1, 0xFFFF, sum = 0
1014 11:52:37.952604 2, 0xFFFF, sum = 0
1015 11:52:37.955884 3, 0xFFFF, sum = 0
1016 11:52:37.955971 4, 0xFFFF, sum = 0
1017 11:52:37.959146 5, 0xFFFF, sum = 0
1018 11:52:37.959230 6, 0xFFFF, sum = 0
1019 11:52:37.962924 7, 0xFFFF, sum = 0
1020 11:52:37.963007 8, 0xFFFF, sum = 0
1021 11:52:37.965901 9, 0x0, sum = 1
1022 11:52:37.965986 10, 0x0, sum = 2
1023 11:52:37.969369 11, 0x0, sum = 3
1024 11:52:37.969453 12, 0x0, sum = 4
1025 11:52:37.972700 best_step = 10
1026 11:52:37.972785
1027 11:52:37.972850 ==
1028 11:52:37.975816 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 11:52:37.979483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 11:52:37.979566 ==
1031 11:52:37.982674 RX Vref Scan: 1
1032 11:52:37.982756
1033 11:52:37.982821 Set Vref Range= 32 -> 127
1034 11:52:37.982882
1035 11:52:37.986106 RX Vref 32 -> 127, step: 1
1036 11:52:37.986187
1037 11:52:37.989161 RX Delay -95 -> 252, step: 8
1038 11:52:37.989244
1039 11:52:37.992307 Set Vref, RX VrefLevel [Byte0]: 32
1040 11:52:37.996101 [Byte1]: 32
1041 11:52:37.996183
1042 11:52:37.999492 Set Vref, RX VrefLevel [Byte0]: 33
1043 11:52:38.002342 [Byte1]: 33
1044 11:52:38.006318
1045 11:52:38.006404 Set Vref, RX VrefLevel [Byte0]: 34
1046 11:52:38.009311 [Byte1]: 34
1047 11:52:38.013577
1048 11:52:38.013659 Set Vref, RX VrefLevel [Byte0]: 35
1049 11:52:38.016934 [Byte1]: 35
1050 11:52:38.021306
1051 11:52:38.021411 Set Vref, RX VrefLevel [Byte0]: 36
1052 11:52:38.024587 [Byte1]: 36
1053 11:52:38.028933
1054 11:52:38.029017 Set Vref, RX VrefLevel [Byte0]: 37
1055 11:52:38.031987 [Byte1]: 37
1056 11:52:38.036197
1057 11:52:38.036281 Set Vref, RX VrefLevel [Byte0]: 38
1058 11:52:38.039691 [Byte1]: 38
1059 11:52:38.045200
1060 11:52:38.045284 Set Vref, RX VrefLevel [Byte0]: 39
1061 11:52:38.047775 [Byte1]: 39
1062 11:52:38.051356
1063 11:52:38.051436 Set Vref, RX VrefLevel [Byte0]: 40
1064 11:52:38.054964 [Byte1]: 40
1065 11:52:38.059284
1066 11:52:38.059359 Set Vref, RX VrefLevel [Byte0]: 41
1067 11:52:38.062755 [Byte1]: 41
1068 11:52:38.067192
1069 11:52:38.067265 Set Vref, RX VrefLevel [Byte0]: 42
1070 11:52:38.070608 [Byte1]: 42
1071 11:52:38.074725
1072 11:52:38.074830 Set Vref, RX VrefLevel [Byte0]: 43
1073 11:52:38.077943 [Byte1]: 43
1074 11:52:38.082125
1075 11:52:38.082201 Set Vref, RX VrefLevel [Byte0]: 44
1076 11:52:38.085662 [Byte1]: 44
1077 11:52:38.089968
1078 11:52:38.090059 Set Vref, RX VrefLevel [Byte0]: 45
1079 11:52:38.093067 [Byte1]: 45
1080 11:52:38.097415
1081 11:52:38.097499 Set Vref, RX VrefLevel [Byte0]: 46
1082 11:52:38.100727 [Byte1]: 46
1083 11:52:38.104907
1084 11:52:38.104991 Set Vref, RX VrefLevel [Byte0]: 47
1085 11:52:38.107712 [Byte1]: 47
1086 11:52:38.112379
1087 11:52:38.112464 Set Vref, RX VrefLevel [Byte0]: 48
1088 11:52:38.115731 [Byte1]: 48
1089 11:52:38.119851
1090 11:52:38.119935 Set Vref, RX VrefLevel [Byte0]: 49
1091 11:52:38.123297 [Byte1]: 49
1092 11:52:38.127371
1093 11:52:38.127455 Set Vref, RX VrefLevel [Byte0]: 50
1094 11:52:38.130828 [Byte1]: 50
1095 11:52:38.134804
1096 11:52:38.134886 Set Vref, RX VrefLevel [Byte0]: 51
1097 11:52:38.138504 [Byte1]: 51
1098 11:52:38.142465
1099 11:52:38.142548 Set Vref, RX VrefLevel [Byte0]: 52
1100 11:52:38.146168 [Byte1]: 52
1101 11:52:38.150213
1102 11:52:38.150322 Set Vref, RX VrefLevel [Byte0]: 53
1103 11:52:38.153888 [Byte1]: 53
1104 11:52:38.158339
1105 11:52:38.158474 Set Vref, RX VrefLevel [Byte0]: 54
1106 11:52:38.161229 [Byte1]: 54
1107 11:52:38.165704
1108 11:52:38.165787 Set Vref, RX VrefLevel [Byte0]: 55
1109 11:52:38.168714 [Byte1]: 55
1110 11:52:38.172841
1111 11:52:38.172924 Set Vref, RX VrefLevel [Byte0]: 56
1112 11:52:38.176423 [Byte1]: 56
1113 11:52:38.181251
1114 11:52:38.181333 Set Vref, RX VrefLevel [Byte0]: 57
1115 11:52:38.184227 [Byte1]: 57
1116 11:52:38.188323
1117 11:52:38.188405 Set Vref, RX VrefLevel [Byte0]: 58
1118 11:52:38.191515 [Byte1]: 58
1119 11:52:38.195681
1120 11:52:38.195764 Set Vref, RX VrefLevel [Byte0]: 59
1121 11:52:38.199246 [Byte1]: 59
1122 11:52:38.203265
1123 11:52:38.203347 Set Vref, RX VrefLevel [Byte0]: 60
1124 11:52:38.206932 [Byte1]: 60
1125 11:52:38.210864
1126 11:52:38.210946 Set Vref, RX VrefLevel [Byte0]: 61
1127 11:52:38.214378 [Byte1]: 61
1128 11:52:38.218558
1129 11:52:38.218641 Set Vref, RX VrefLevel [Byte0]: 62
1130 11:52:38.222191 [Byte1]: 62
1131 11:52:38.226580
1132 11:52:38.226663 Set Vref, RX VrefLevel [Byte0]: 63
1133 11:52:38.229477 [Byte1]: 63
1134 11:52:38.233652
1135 11:52:38.233764 Set Vref, RX VrefLevel [Byte0]: 64
1136 11:52:38.237006 [Byte1]: 64
1137 11:52:38.241531
1138 11:52:38.241614 Set Vref, RX VrefLevel [Byte0]: 65
1139 11:52:38.244499 [Byte1]: 65
1140 11:52:38.248906
1141 11:52:38.248989 Set Vref, RX VrefLevel [Byte0]: 66
1142 11:52:38.252490 [Byte1]: 66
1143 11:52:38.256397
1144 11:52:38.256480 Set Vref, RX VrefLevel [Byte0]: 67
1145 11:52:38.259760 [Byte1]: 67
1146 11:52:38.264159
1147 11:52:38.264258 Set Vref, RX VrefLevel [Byte0]: 68
1148 11:52:38.267421 [Byte1]: 68
1149 11:52:38.271797
1150 11:52:38.271892 Set Vref, RX VrefLevel [Byte0]: 69
1151 11:52:38.275173 [Byte1]: 69
1152 11:52:38.279554
1153 11:52:38.279657 Set Vref, RX VrefLevel [Byte0]: 70
1154 11:52:38.282628 [Byte1]: 70
1155 11:52:38.286894
1156 11:52:38.286995 Set Vref, RX VrefLevel [Byte0]: 71
1157 11:52:38.290115 [Byte1]: 71
1158 11:52:38.294445
1159 11:52:38.294549 Set Vref, RX VrefLevel [Byte0]: 72
1160 11:52:38.297786 [Byte1]: 72
1161 11:52:38.302243
1162 11:52:38.302349 Set Vref, RX VrefLevel [Byte0]: 73
1163 11:52:38.305494 [Byte1]: 73
1164 11:52:38.309843
1165 11:52:38.309916 Set Vref, RX VrefLevel [Byte0]: 74
1166 11:52:38.313457 [Byte1]: 74
1167 11:52:38.317302
1168 11:52:38.317399 Set Vref, RX VrefLevel [Byte0]: 75
1169 11:52:38.320409 [Byte1]: 75
1170 11:52:38.324762
1171 11:52:38.324835 Set Vref, RX VrefLevel [Byte0]: 76
1172 11:52:38.328382 [Byte1]: 76
1173 11:52:38.332766
1174 11:52:38.332854 Set Vref, RX VrefLevel [Byte0]: 77
1175 11:52:38.335863 [Byte1]: 77
1176 11:52:38.340279
1177 11:52:38.340356 Set Vref, RX VrefLevel [Byte0]: 78
1178 11:52:38.343293 [Byte1]: 78
1179 11:52:38.347697
1180 11:52:38.347795 Set Vref, RX VrefLevel [Byte0]: 79
1181 11:52:38.350809 [Byte1]: 79
1182 11:52:38.355433
1183 11:52:38.355515 Final RX Vref Byte 0 = 62 to rank0
1184 11:52:38.358541 Final RX Vref Byte 1 = 53 to rank0
1185 11:52:38.361813 Final RX Vref Byte 0 = 62 to rank1
1186 11:52:38.365092 Final RX Vref Byte 1 = 53 to rank1==
1187 11:52:38.368990 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 11:52:38.375525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 11:52:38.375608 ==
1190 11:52:38.375674 DQS Delay:
1191 11:52:38.375733 DQS0 = 0, DQS1 = 0
1192 11:52:38.378816 DQM Delay:
1193 11:52:38.378898 DQM0 = 93, DQM1 = 81
1194 11:52:38.382125 DQ Delay:
1195 11:52:38.385257 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1196 11:52:38.388566 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1197 11:52:38.388648 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1198 11:52:38.395452 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1199 11:52:38.395534
1200 11:52:38.395599
1201 11:52:38.402119 [DQSOSCAuto] RK0, (LSB)MR18= 0x3934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1202 11:52:38.405617 CH0 RK0: MR19=606, MR18=3934
1203 11:52:38.412339 CH0_RK0: MR19=0x606, MR18=0x3934, DQSOSC=395, MR23=63, INC=94, DEC=63
1204 11:52:38.412421
1205 11:52:38.415543 ----->DramcWriteLeveling(PI) begin...
1206 11:52:38.415627 ==
1207 11:52:38.418626 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 11:52:38.422493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 11:52:38.422576 ==
1210 11:52:38.425632 Write leveling (Byte 0): 32 => 32
1211 11:52:38.428852 Write leveling (Byte 1): 27 => 27
1212 11:52:38.432231 DramcWriteLeveling(PI) end<-----
1213 11:52:38.432313
1214 11:52:38.432378 ==
1215 11:52:38.435518 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 11:52:38.438677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 11:52:38.438786 ==
1218 11:52:38.442285 [Gating] SW mode calibration
1219 11:52:38.449029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 11:52:38.455612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 11:52:38.459072 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 11:52:38.462298 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 11:52:38.509462 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1224 11:52:38.509578 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:52:38.509869 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:52:38.509964 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:52:38.510071 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:52:38.510179 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:52:38.510267 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:52:38.510375 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:52:38.510521 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:52:38.510675 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:52:38.513979 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:52:38.517588 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:52:38.520929 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:52:38.524102 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:52:38.530817 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:52:38.533901 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 11:52:38.537343 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1240 11:52:38.540762 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:52:38.547499 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:52:38.550783 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:52:38.554005 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:52:38.560526 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:52:38.564044 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:52:38.567443 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1247 11:52:38.574005 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1248 11:52:38.577552 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:52:38.580619 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:52:38.587713 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:52:38.590814 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:52:38.594053 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:52:38.600867 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1254 11:52:38.604294 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
1255 11:52:38.607592 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1256 11:52:38.614505 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:52:38.617816 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:52:38.620907 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:52:38.624500 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:52:38.630929 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:52:38.634366 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:52:38.637726 0 11 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1263 11:52:38.645014 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1264 11:52:38.648384 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:52:38.652259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:52:38.655830 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:52:38.659671 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:52:38.666094 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:52:38.669578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1270 11:52:38.673788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:52:38.677542 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 11:52:38.683757 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:52:38.687508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:52:38.690459 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:52:38.697259 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:52:38.700769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:52:38.704176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:52:38.710865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:52:38.714254 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:52:38.717435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:52:38.720954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:52:38.727612 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:52:38.730902 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:52:38.734158 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:52:38.740805 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:52:38.743818 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1287 11:52:38.747172 Total UI for P1: 0, mck2ui 16
1288 11:52:38.750524 best dqsien dly found for B0: ( 0, 14, 2)
1289 11:52:38.753791 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 11:52:38.757174 Total UI for P1: 0, mck2ui 16
1291 11:52:38.760753 best dqsien dly found for B1: ( 0, 14, 4)
1292 11:52:38.764125 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1293 11:52:38.767245 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1294 11:52:38.767327
1295 11:52:38.774003 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1296 11:52:38.777256 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1297 11:52:38.780585 [Gating] SW calibration Done
1298 11:52:38.780668 ==
1299 11:52:38.784051 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:52:38.787287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:52:38.787369 ==
1302 11:52:38.787433 RX Vref Scan: 0
1303 11:52:38.787492
1304 11:52:38.790807 RX Vref 0 -> 0, step: 1
1305 11:52:38.790888
1306 11:52:38.794140 RX Delay -130 -> 252, step: 16
1307 11:52:38.797279 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1308 11:52:38.800800 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1309 11:52:38.807550 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1310 11:52:38.810643 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1311 11:52:38.813991 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1312 11:52:38.817392 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1313 11:52:38.820874 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1314 11:52:38.824221 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1315 11:52:38.830852 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1316 11:52:38.833981 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1317 11:52:38.837563 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1318 11:52:38.840798 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1319 11:52:38.847616 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1320 11:52:38.850680 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1321 11:52:38.854278 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1322 11:52:38.857188 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1323 11:52:38.857271 ==
1324 11:52:38.860680 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 11:52:38.864245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 11:52:38.867744 ==
1327 11:52:38.867823 DQS Delay:
1328 11:52:38.867893 DQS0 = 0, DQS1 = 0
1329 11:52:38.870871 DQM Delay:
1330 11:52:38.870949 DQM0 = 89, DQM1 = 79
1331 11:52:38.874065 DQ Delay:
1332 11:52:38.874166 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1333 11:52:38.877322 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1334 11:52:38.880758 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1335 11:52:38.884863 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1336 11:52:38.887633
1337 11:52:38.887714
1338 11:52:38.887779 ==
1339 11:52:38.890705 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 11:52:38.894257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 11:52:38.894356 ==
1342 11:52:38.894441
1343 11:52:38.894501
1344 11:52:38.897298 TX Vref Scan disable
1345 11:52:38.897398 == TX Byte 0 ==
1346 11:52:38.904034 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1347 11:52:38.907684 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1348 11:52:38.907769 == TX Byte 1 ==
1349 11:52:38.914575 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1350 11:52:38.917338 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1351 11:52:38.917423 ==
1352 11:52:38.920919 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 11:52:38.924263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 11:52:38.924349 ==
1355 11:52:38.938472 TX Vref=22, minBit 3, minWin=27, winSum=446
1356 11:52:38.941479 TX Vref=24, minBit 3, minWin=27, winSum=446
1357 11:52:38.945059 TX Vref=26, minBit 8, minWin=27, winSum=452
1358 11:52:38.948352 TX Vref=28, minBit 8, minWin=28, winSum=456
1359 11:52:38.951617 TX Vref=30, minBit 10, minWin=27, winSum=456
1360 11:52:38.958266 TX Vref=32, minBit 4, minWin=28, winSum=457
1361 11:52:38.961586 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 32
1362 11:52:38.961668
1363 11:52:38.965382 Final TX Range 1 Vref 32
1364 11:52:38.965464
1365 11:52:38.965553 ==
1366 11:52:38.968365 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 11:52:38.971609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:52:38.971691 ==
1369 11:52:38.971756
1370 11:52:38.974943
1371 11:52:38.975024 TX Vref Scan disable
1372 11:52:38.978687 == TX Byte 0 ==
1373 11:52:38.981444 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1374 11:52:38.984889 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1375 11:52:38.988365 == TX Byte 1 ==
1376 11:52:38.991665 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1377 11:52:38.994966 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1378 11:52:38.998662
1379 11:52:38.998742 [DATLAT]
1380 11:52:38.998805 Freq=800, CH0 RK1
1381 11:52:38.998864
1382 11:52:39.001738 DATLAT Default: 0xa
1383 11:52:39.001818 0, 0xFFFF, sum = 0
1384 11:52:39.005275 1, 0xFFFF, sum = 0
1385 11:52:39.005357 2, 0xFFFF, sum = 0
1386 11:52:39.008500 3, 0xFFFF, sum = 0
1387 11:52:39.008582 4, 0xFFFF, sum = 0
1388 11:52:39.011684 5, 0xFFFF, sum = 0
1389 11:52:39.011766 6, 0xFFFF, sum = 0
1390 11:52:39.015509 7, 0xFFFF, sum = 0
1391 11:52:39.018564 8, 0xFFFF, sum = 0
1392 11:52:39.018645 9, 0x0, sum = 1
1393 11:52:39.018709 10, 0x0, sum = 2
1394 11:52:39.021734 11, 0x0, sum = 3
1395 11:52:39.021816 12, 0x0, sum = 4
1396 11:52:39.025223 best_step = 10
1397 11:52:39.025303
1398 11:52:39.025366 ==
1399 11:52:39.028466 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 11:52:39.031677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 11:52:39.031758 ==
1402 11:52:39.035261 RX Vref Scan: 0
1403 11:52:39.035341
1404 11:52:39.035407 RX Vref 0 -> 0, step: 1
1405 11:52:39.035467
1406 11:52:39.038712 RX Delay -79 -> 252, step: 8
1407 11:52:39.045264 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1408 11:52:39.048673 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1409 11:52:39.052245 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1410 11:52:39.055591 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1411 11:52:39.058792 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1412 11:52:39.065260 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1413 11:52:39.069020 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1414 11:52:39.072217 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 11:52:39.075377 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1416 11:52:39.078787 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1417 11:52:39.081887 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1418 11:52:39.088889 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1419 11:52:39.092162 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1420 11:52:39.095310 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1421 11:52:39.098977 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 11:52:39.105309 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1423 11:52:39.105390 ==
1424 11:52:39.108780 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 11:52:39.112165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:52:39.112246 ==
1427 11:52:39.112309 DQS Delay:
1428 11:52:39.115561 DQS0 = 0, DQS1 = 0
1429 11:52:39.115641 DQM Delay:
1430 11:52:39.118943 DQM0 = 90, DQM1 = 82
1431 11:52:39.119023 DQ Delay:
1432 11:52:39.122011 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1433 11:52:39.125481 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1434 11:52:39.128877 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1435 11:52:39.132354 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1436 11:52:39.132434
1437 11:52:39.132496
1438 11:52:39.138674 [DQSOSCAuto] RK1, (LSB)MR18= 0x401a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1439 11:52:39.142077 CH0 RK1: MR19=606, MR18=401A
1440 11:52:39.148976 CH0_RK1: MR19=0x606, MR18=0x401A, DQSOSC=393, MR23=63, INC=95, DEC=63
1441 11:52:39.152297 [RxdqsGatingPostProcess] freq 800
1442 11:52:39.156004 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 11:52:39.158812 Pre-setting of DQS Precalculation
1444 11:52:39.165752 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 11:52:39.165832 ==
1446 11:52:39.169109 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 11:52:39.172390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 11:52:39.172475 ==
1449 11:52:39.179436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 11:52:39.185802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 11:52:39.193518 [CA 0] Center 36 (6~67) winsize 62
1452 11:52:39.196972 [CA 1] Center 37 (6~68) winsize 63
1453 11:52:39.200383 [CA 2] Center 34 (4~65) winsize 62
1454 11:52:39.204100 [CA 3] Center 34 (4~65) winsize 62
1455 11:52:39.207175 [CA 4] Center 34 (4~65) winsize 62
1456 11:52:39.210260 [CA 5] Center 33 (3~64) winsize 62
1457 11:52:39.210340
1458 11:52:39.213617 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1459 11:52:39.213698
1460 11:52:39.217081 [CATrainingPosCal] consider 1 rank data
1461 11:52:39.220288 u2DelayCellTimex100 = 270/100 ps
1462 11:52:39.223704 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1463 11:52:39.227170 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1464 11:52:39.230189 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1465 11:52:39.236898 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1466 11:52:39.240410 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1467 11:52:39.243951 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1468 11:52:39.244033
1469 11:52:39.247139 CA PerBit enable=1, Macro0, CA PI delay=33
1470 11:52:39.247219
1471 11:52:39.250312 [CBTSetCACLKResult] CA Dly = 33
1472 11:52:39.250402 CS Dly: 5 (0~36)
1473 11:52:39.250480 ==
1474 11:52:39.253804 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 11:52:39.260528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 11:52:39.260608 ==
1477 11:52:39.263796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 11:52:39.270528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 11:52:39.279811 [CA 0] Center 37 (6~68) winsize 63
1480 11:52:39.282872 [CA 1] Center 37 (6~68) winsize 63
1481 11:52:39.286196 [CA 2] Center 35 (5~66) winsize 62
1482 11:52:39.289653 [CA 3] Center 34 (4~65) winsize 62
1483 11:52:39.293399 [CA 4] Center 34 (4~65) winsize 62
1484 11:52:39.296395 [CA 5] Center 34 (4~65) winsize 62
1485 11:52:39.296480
1486 11:52:39.299464 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1487 11:52:39.299549
1488 11:52:39.303134 [CATrainingPosCal] consider 2 rank data
1489 11:52:39.306374 u2DelayCellTimex100 = 270/100 ps
1490 11:52:39.309743 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 11:52:39.313606 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1492 11:52:39.317517 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1493 11:52:39.320946 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 11:52:39.325221 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 11:52:39.328980 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 11:52:39.329067
1497 11:52:39.332285 CA PerBit enable=1, Macro0, CA PI delay=34
1498 11:52:39.332369
1499 11:52:39.336330 [CBTSetCACLKResult] CA Dly = 34
1500 11:52:39.336416 CS Dly: 6 (0~38)
1501 11:52:39.339642
1502 11:52:39.339741 ----->DramcWriteLeveling(PI) begin...
1503 11:52:39.339826 ==
1504 11:52:39.343281 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 11:52:39.346983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 11:52:39.350279 ==
1507 11:52:39.350423 Write leveling (Byte 0): 24 => 24
1508 11:52:39.353825 Write leveling (Byte 1): 30 => 30
1509 11:52:39.357280 DramcWriteLeveling(PI) end<-----
1510 11:52:39.357363
1511 11:52:39.357429 ==
1512 11:52:39.360364 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 11:52:39.367640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 11:52:39.367724 ==
1515 11:52:39.367790 [Gating] SW mode calibration
1516 11:52:39.377617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 11:52:39.380915 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 11:52:39.384052 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 11:52:39.390821 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1520 11:52:39.394054 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:52:39.397415 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:52:39.403880 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:52:39.407382 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:52:39.410569 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:52:39.417531 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:52:39.420857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:52:39.424112 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:52:39.430594 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:52:39.433984 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:52:39.437358 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:52:39.444360 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:52:39.447848 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:52:39.451263 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:52:39.454320 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 11:52:39.460833 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 11:52:39.464404 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1537 11:52:39.467887 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:52:39.474547 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:52:39.477882 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:52:39.480788 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:52:39.487886 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:52:39.491089 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:52:39.494776 0 9 4 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
1544 11:52:39.501252 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1545 11:52:39.504431 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:52:39.508135 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:52:39.514970 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:52:39.518035 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:52:39.521190 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:52:39.524362 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1551 11:52:39.531101 0 10 4 | B1->B0 | 2f2f 2c2c | 1 0 | (1 1) (1 0)
1552 11:52:39.534362 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:52:39.537935 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:52:39.544378 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:52:39.548036 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:52:39.551683 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:52:39.558140 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:52:39.561356 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1559 11:52:39.564645 0 11 4 | B1->B0 | 3232 3535 | 0 1 | (0 0) (0 0)
1560 11:52:39.571384 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1561 11:52:39.574336 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:52:39.577961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:52:39.584652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:52:39.588249 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:52:39.591511 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:52:39.594940 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1567 11:52:39.601595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1568 11:52:39.604876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:52:39.608650 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:52:39.614709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:52:39.618524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:52:39.621763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:52:39.628108 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:52:39.631791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:52:39.635189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:52:39.642002 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:52:39.645055 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:52:39.648247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:52:39.654704 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:52:39.658155 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:52:39.661780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:52:39.668596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 11:52:39.671683 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 11:52:39.674865 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 11:52:39.678372 Total UI for P1: 0, mck2ui 16
1586 11:52:39.681752 best dqsien dly found for B0: ( 0, 14, 2)
1587 11:52:39.684856 Total UI for P1: 0, mck2ui 16
1588 11:52:39.688245 best dqsien dly found for B1: ( 0, 14, 2)
1589 11:52:39.691501 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1590 11:52:39.695039 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1591 11:52:39.695118
1592 11:52:39.698664 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1593 11:52:39.701598 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 11:52:39.704873 [Gating] SW calibration Done
1595 11:52:39.704974 ==
1596 11:52:39.708297 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:52:39.711771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:52:39.714904 ==
1599 11:52:39.715005 RX Vref Scan: 0
1600 11:52:39.715096
1601 11:52:39.718333 RX Vref 0 -> 0, step: 1
1602 11:52:39.718471
1603 11:52:39.721536 RX Delay -130 -> 252, step: 16
1604 11:52:39.725071 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1605 11:52:39.728259 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1606 11:52:39.731937 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 11:52:39.735186 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1608 11:52:39.741996 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1609 11:52:39.745286 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1610 11:52:39.748320 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1611 11:52:39.751744 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1612 11:52:39.755214 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1613 11:52:39.761715 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1614 11:52:39.765156 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1615 11:52:39.768850 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1616 11:52:39.772043 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1617 11:52:39.775350 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1618 11:52:39.781860 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1619 11:52:39.785538 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1620 11:52:39.785639 ==
1621 11:52:39.788455 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:52:39.791685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:52:39.791755 ==
1624 11:52:39.791853 DQS Delay:
1625 11:52:39.795347 DQS0 = 0, DQS1 = 0
1626 11:52:39.795417 DQM Delay:
1627 11:52:39.798367 DQM0 = 88, DQM1 = 81
1628 11:52:39.798490 DQ Delay:
1629 11:52:39.802094 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1630 11:52:39.805055 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1631 11:52:39.808614 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1632 11:52:39.812066 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1633 11:52:39.812147
1634 11:52:39.812213
1635 11:52:39.812271 ==
1636 11:52:39.815707 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:52:39.821859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:52:39.821966 ==
1639 11:52:39.822058
1640 11:52:39.822145
1641 11:52:39.822240 TX Vref Scan disable
1642 11:52:39.825440 == TX Byte 0 ==
1643 11:52:39.828489 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1644 11:52:39.834927 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1645 11:52:39.835037 == TX Byte 1 ==
1646 11:52:39.838611 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1647 11:52:39.841902 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1648 11:52:39.845299 ==
1649 11:52:39.848706 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 11:52:39.851642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 11:52:39.851745 ==
1652 11:52:39.865087 TX Vref=22, minBit 10, minWin=27, winSum=451
1653 11:52:39.867861 TX Vref=24, minBit 15, minWin=27, winSum=455
1654 11:52:39.871321 TX Vref=26, minBit 15, minWin=27, winSum=455
1655 11:52:39.874692 TX Vref=28, minBit 15, minWin=27, winSum=458
1656 11:52:39.878098 TX Vref=30, minBit 9, minWin=27, winSum=457
1657 11:52:39.884853 TX Vref=32, minBit 12, minWin=27, winSum=458
1658 11:52:39.888279 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1659 11:52:39.888376
1660 11:52:39.891590 Final TX Range 1 Vref 28
1661 11:52:39.891670
1662 11:52:39.891735 ==
1663 11:52:39.895067 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 11:52:39.899035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 11:52:39.899106 ==
1666 11:52:39.899166
1667 11:52:39.901843
1668 11:52:39.901939 TX Vref Scan disable
1669 11:52:39.905159 == TX Byte 0 ==
1670 11:52:39.908581 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1671 11:52:39.911802 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1672 11:52:39.915382 == TX Byte 1 ==
1673 11:52:39.918589 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1674 11:52:39.921970 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1675 11:52:39.925617
1676 11:52:39.925693 [DATLAT]
1677 11:52:39.925762 Freq=800, CH1 RK0
1678 11:52:39.925823
1679 11:52:39.928868 DATLAT Default: 0xa
1680 11:52:39.928936 0, 0xFFFF, sum = 0
1681 11:52:39.931918 1, 0xFFFF, sum = 0
1682 11:52:39.931987 2, 0xFFFF, sum = 0
1683 11:52:39.935240 3, 0xFFFF, sum = 0
1684 11:52:39.935326 4, 0xFFFF, sum = 0
1685 11:52:39.938908 5, 0xFFFF, sum = 0
1686 11:52:39.939006 6, 0xFFFF, sum = 0
1687 11:52:39.942125 7, 0xFFFF, sum = 0
1688 11:52:39.942210 8, 0xFFFF, sum = 0
1689 11:52:39.945574 9, 0x0, sum = 1
1690 11:52:39.945658 10, 0x0, sum = 2
1691 11:52:39.948837 11, 0x0, sum = 3
1692 11:52:39.948920 12, 0x0, sum = 4
1693 11:52:39.952380 best_step = 10
1694 11:52:39.952462
1695 11:52:39.952528 ==
1696 11:52:39.955496 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 11:52:39.958816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 11:52:39.958899 ==
1699 11:52:39.962343 RX Vref Scan: 1
1700 11:52:39.962456
1701 11:52:39.962523 Set Vref Range= 32 -> 127
1702 11:52:39.962584
1703 11:52:39.965603 RX Vref 32 -> 127, step: 1
1704 11:52:39.965703
1705 11:52:39.969132 RX Delay -95 -> 252, step: 8
1706 11:52:39.969217
1707 11:52:39.972198 Set Vref, RX VrefLevel [Byte0]: 32
1708 11:52:39.975629 [Byte1]: 32
1709 11:52:39.975729
1710 11:52:39.978833 Set Vref, RX VrefLevel [Byte0]: 33
1711 11:52:39.982066 [Byte1]: 33
1712 11:52:39.985383
1713 11:52:39.985472 Set Vref, RX VrefLevel [Byte0]: 34
1714 11:52:39.988790 [Byte1]: 34
1715 11:52:39.993178
1716 11:52:39.993259 Set Vref, RX VrefLevel [Byte0]: 35
1717 11:52:39.996240 [Byte1]: 35
1718 11:52:40.000734
1719 11:52:40.000817 Set Vref, RX VrefLevel [Byte0]: 36
1720 11:52:40.003778 [Byte1]: 36
1721 11:52:40.008309
1722 11:52:40.008391 Set Vref, RX VrefLevel [Byte0]: 37
1723 11:52:40.011440 [Byte1]: 37
1724 11:52:40.015968
1725 11:52:40.016050 Set Vref, RX VrefLevel [Byte0]: 38
1726 11:52:40.019157 [Byte1]: 38
1727 11:52:40.023580
1728 11:52:40.023707 Set Vref, RX VrefLevel [Byte0]: 39
1729 11:52:40.026800 [Byte1]: 39
1730 11:52:40.031034
1731 11:52:40.031117 Set Vref, RX VrefLevel [Byte0]: 40
1732 11:52:40.034500 [Byte1]: 40
1733 11:52:40.038805
1734 11:52:40.038887 Set Vref, RX VrefLevel [Byte0]: 41
1735 11:52:40.042068 [Byte1]: 41
1736 11:52:40.046899
1737 11:52:40.046982 Set Vref, RX VrefLevel [Byte0]: 42
1738 11:52:40.050018 [Byte1]: 42
1739 11:52:40.054100
1740 11:52:40.054240 Set Vref, RX VrefLevel [Byte0]: 43
1741 11:52:40.057282 [Byte1]: 43
1742 11:52:40.061584
1743 11:52:40.061697 Set Vref, RX VrefLevel [Byte0]: 44
1744 11:52:40.064969 [Byte1]: 44
1745 11:52:40.068930
1746 11:52:40.069012 Set Vref, RX VrefLevel [Byte0]: 45
1747 11:52:40.072204 [Byte1]: 45
1748 11:52:40.076625
1749 11:52:40.076707 Set Vref, RX VrefLevel [Byte0]: 46
1750 11:52:40.080102 [Byte1]: 46
1751 11:52:40.084175
1752 11:52:40.084257 Set Vref, RX VrefLevel [Byte0]: 47
1753 11:52:40.087483 [Byte1]: 47
1754 11:52:40.091970
1755 11:52:40.092059 Set Vref, RX VrefLevel [Byte0]: 48
1756 11:52:40.095189 [Byte1]: 48
1757 11:52:40.099497
1758 11:52:40.099579 Set Vref, RX VrefLevel [Byte0]: 49
1759 11:52:40.102697 [Byte1]: 49
1760 11:52:40.107741
1761 11:52:40.107823 Set Vref, RX VrefLevel [Byte0]: 50
1762 11:52:40.110904 [Byte1]: 50
1763 11:52:40.114691
1764 11:52:40.114772 Set Vref, RX VrefLevel [Byte0]: 51
1765 11:52:40.117880 [Byte1]: 51
1766 11:52:40.122459
1767 11:52:40.122541 Set Vref, RX VrefLevel [Byte0]: 52
1768 11:52:40.125526 [Byte1]: 52
1769 11:52:40.130025
1770 11:52:40.130107 Set Vref, RX VrefLevel [Byte0]: 53
1771 11:52:40.133077 [Byte1]: 53
1772 11:52:40.137509
1773 11:52:40.137591 Set Vref, RX VrefLevel [Byte0]: 54
1774 11:52:40.140950 [Byte1]: 54
1775 11:52:40.145065
1776 11:52:40.145148 Set Vref, RX VrefLevel [Byte0]: 55
1777 11:52:40.148422 [Byte1]: 55
1778 11:52:40.153010
1779 11:52:40.153092 Set Vref, RX VrefLevel [Byte0]: 56
1780 11:52:40.155883 [Byte1]: 56
1781 11:52:40.160074
1782 11:52:40.160165 Set Vref, RX VrefLevel [Byte0]: 57
1783 11:52:40.163543 [Byte1]: 57
1784 11:52:40.167898
1785 11:52:40.167979 Set Vref, RX VrefLevel [Byte0]: 58
1786 11:52:40.170972 [Byte1]: 58
1787 11:52:40.175308
1788 11:52:40.175393 Set Vref, RX VrefLevel [Byte0]: 59
1789 11:52:40.178551 [Byte1]: 59
1790 11:52:40.183095
1791 11:52:40.183167 Set Vref, RX VrefLevel [Byte0]: 60
1792 11:52:40.186259 [Byte1]: 60
1793 11:52:40.190768
1794 11:52:40.190850 Set Vref, RX VrefLevel [Byte0]: 61
1795 11:52:40.194082 [Byte1]: 61
1796 11:52:40.198180
1797 11:52:40.198262 Set Vref, RX VrefLevel [Byte0]: 62
1798 11:52:40.201678 [Byte1]: 62
1799 11:52:40.205772
1800 11:52:40.205853 Set Vref, RX VrefLevel [Byte0]: 63
1801 11:52:40.209288 [Byte1]: 63
1802 11:52:40.213359
1803 11:52:40.213441 Set Vref, RX VrefLevel [Byte0]: 64
1804 11:52:40.216749 [Byte1]: 64
1805 11:52:40.221637
1806 11:52:40.221722 Set Vref, RX VrefLevel [Byte0]: 65
1807 11:52:40.224382 [Byte1]: 65
1808 11:52:40.228562
1809 11:52:40.228644 Set Vref, RX VrefLevel [Byte0]: 66
1810 11:52:40.231972 [Byte1]: 66
1811 11:52:40.236448
1812 11:52:40.236531 Set Vref, RX VrefLevel [Byte0]: 67
1813 11:52:40.239478 [Byte1]: 67
1814 11:52:40.243873
1815 11:52:40.243955 Set Vref, RX VrefLevel [Byte0]: 68
1816 11:52:40.247421 [Byte1]: 68
1817 11:52:40.251568
1818 11:52:40.251650 Set Vref, RX VrefLevel [Byte0]: 69
1819 11:52:40.254627 [Byte1]: 69
1820 11:52:40.259427
1821 11:52:40.259508 Set Vref, RX VrefLevel [Byte0]: 70
1822 11:52:40.262268 [Byte1]: 70
1823 11:52:40.266927
1824 11:52:40.267009 Set Vref, RX VrefLevel [Byte0]: 71
1825 11:52:40.269819 [Byte1]: 71
1826 11:52:40.274442
1827 11:52:40.274524 Set Vref, RX VrefLevel [Byte0]: 72
1828 11:52:40.277360 [Byte1]: 72
1829 11:52:40.282047
1830 11:52:40.282129 Set Vref, RX VrefLevel [Byte0]: 73
1831 11:52:40.285001 [Byte1]: 73
1832 11:52:40.289218
1833 11:52:40.289300 Set Vref, RX VrefLevel [Byte0]: 74
1834 11:52:40.292972 [Byte1]: 74
1835 11:52:40.296937
1836 11:52:40.297019 Set Vref, RX VrefLevel [Byte0]: 75
1837 11:52:40.301085 [Byte1]: 75
1838 11:52:40.305012
1839 11:52:40.305094 Set Vref, RX VrefLevel [Byte0]: 76
1840 11:52:40.307726 [Byte1]: 76
1841 11:52:40.312172
1842 11:52:40.312254 Set Vref, RX VrefLevel [Byte0]: 77
1843 11:52:40.315469 [Byte1]: 77
1844 11:52:40.320133
1845 11:52:40.320215 Set Vref, RX VrefLevel [Byte0]: 78
1846 11:52:40.323215 [Byte1]: 78
1847 11:52:40.327147
1848 11:52:40.330963 Final RX Vref Byte 0 = 51 to rank0
1849 11:52:40.331045 Final RX Vref Byte 1 = 62 to rank0
1850 11:52:40.334002 Final RX Vref Byte 0 = 51 to rank1
1851 11:52:40.337594 Final RX Vref Byte 1 = 62 to rank1==
1852 11:52:40.340761 Dram Type= 6, Freq= 0, CH_1, rank 0
1853 11:52:40.347561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 11:52:40.347645 ==
1855 11:52:40.347710 DQS Delay:
1856 11:52:40.347769 DQS0 = 0, DQS1 = 0
1857 11:52:40.350707 DQM Delay:
1858 11:52:40.350790 DQM0 = 92, DQM1 = 82
1859 11:52:40.354169 DQ Delay:
1860 11:52:40.357433 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1861 11:52:40.360903 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1862 11:52:40.360985 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1863 11:52:40.367763 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1864 11:52:40.367845
1865 11:52:40.367910
1866 11:52:40.374363 [DQSOSCAuto] RK0, (LSB)MR18= 0x3351, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1867 11:52:40.377464 CH1 RK0: MR19=606, MR18=3351
1868 11:52:40.384362 CH1_RK0: MR19=0x606, MR18=0x3351, DQSOSC=389, MR23=63, INC=97, DEC=65
1869 11:52:40.384445
1870 11:52:40.387471 ----->DramcWriteLeveling(PI) begin...
1871 11:52:40.387555 ==
1872 11:52:40.391400 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 11:52:40.394205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 11:52:40.394287 ==
1875 11:52:40.397690 Write leveling (Byte 0): 26 => 26
1876 11:52:40.401071 Write leveling (Byte 1): 30 => 30
1877 11:52:40.404052 DramcWriteLeveling(PI) end<-----
1878 11:52:40.404133
1879 11:52:40.404198 ==
1880 11:52:40.407746 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 11:52:40.410915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 11:52:40.410997 ==
1883 11:52:40.414298 [Gating] SW mode calibration
1884 11:52:40.421083 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1885 11:52:40.427606 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1886 11:52:40.430745 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1887 11:52:40.434418 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1888 11:52:40.440898 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1889 11:52:40.444130 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:52:40.447847 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:52:40.454358 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:52:40.457712 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:52:40.460994 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:52:40.468192 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:52:40.470998 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:52:40.474406 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:52:40.477829 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:52:40.484646 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:52:40.488111 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:52:40.491101 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:52:40.497722 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:52:40.501118 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1903 11:52:40.504329 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1904 11:52:40.511088 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:52:40.514736 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:52:40.517951 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:52:40.524284 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:52:40.527680 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:52:40.531283 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:52:40.537418 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:52:40.541069 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:52:40.544493 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1913 11:52:40.551137 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:52:40.554277 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:52:40.557661 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:52:40.561526 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:52:40.567971 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:52:40.570933 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1919 11:52:40.574851 0 10 4 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (1 1)
1920 11:52:40.581421 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:52:40.584723 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:52:40.587759 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:52:40.594491 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:52:40.597626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:52:40.600978 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:52:40.607497 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:52:40.611267 0 11 4 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (0 0)
1928 11:52:40.614360 0 11 8 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
1929 11:52:40.621176 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:52:40.624183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:52:40.627659 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:52:40.634293 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:52:40.637521 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:52:40.640916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:52:40.647620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1936 11:52:40.650785 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1937 11:52:40.654608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:52:40.661582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:52:40.664455 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:52:40.667594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:52:40.670967 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:52:40.677533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:52:40.681169 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:52:40.684102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:52:40.690711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:52:40.694154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:52:40.697341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:52:40.704262 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:52:40.707497 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:52:40.710796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:52:40.717556 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1952 11:52:40.720995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1953 11:52:40.724287 Total UI for P1: 0, mck2ui 16
1954 11:52:40.727485 best dqsien dly found for B1: ( 0, 14, 4)
1955 11:52:40.731251 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 11:52:40.734217 Total UI for P1: 0, mck2ui 16
1957 11:52:40.737826 best dqsien dly found for B0: ( 0, 14, 6)
1958 11:52:40.740863 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1959 11:52:40.744590 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1960 11:52:40.744674
1961 11:52:40.747995 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1962 11:52:40.754579 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1963 11:52:40.754657 [Gating] SW calibration Done
1964 11:52:40.754726 ==
1965 11:52:40.757428 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 11:52:40.764321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 11:52:40.764396 ==
1968 11:52:40.764463 RX Vref Scan: 0
1969 11:52:40.764524
1970 11:52:40.767621 RX Vref 0 -> 0, step: 1
1971 11:52:40.767718
1972 11:52:40.771035 RX Delay -130 -> 252, step: 16
1973 11:52:40.774287 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1974 11:52:40.777585 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1975 11:52:40.780946 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1976 11:52:40.787413 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1977 11:52:40.790883 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1978 11:52:40.794410 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1979 11:52:40.797652 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1980 11:52:40.801250 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1981 11:52:40.804205 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1982 11:52:40.810974 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1983 11:52:40.814866 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1984 11:52:40.817782 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1985 11:52:40.821018 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1986 11:52:40.824484 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1987 11:52:40.831434 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1988 11:52:40.834706 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1989 11:52:40.834803 ==
1990 11:52:40.837628 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 11:52:40.841016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 11:52:40.841113 ==
1993 11:52:40.844591 DQS Delay:
1994 11:52:40.844698 DQS0 = 0, DQS1 = 0
1995 11:52:40.844788 DQM Delay:
1996 11:52:40.847785 DQM0 = 89, DQM1 = 82
1997 11:52:40.847855 DQ Delay:
1998 11:52:40.851056 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1999 11:52:40.854376 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
2000 11:52:40.857917 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
2001 11:52:40.861182 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
2002 11:52:40.861278
2003 11:52:40.861367
2004 11:52:40.861449 ==
2005 11:52:40.864919 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 11:52:40.871110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 11:52:40.871191 ==
2008 11:52:40.871253
2009 11:52:40.871311
2010 11:52:40.871372 TX Vref Scan disable
2011 11:52:40.874967 == TX Byte 0 ==
2012 11:52:40.878398 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2013 11:52:40.881192 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2014 11:52:40.884576 == TX Byte 1 ==
2015 11:52:40.888001 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2016 11:52:40.891374 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2017 11:52:40.894934 ==
2018 11:52:40.898060 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 11:52:40.901708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 11:52:40.901805 ==
2021 11:52:40.913902 TX Vref=22, minBit 12, minWin=27, winSum=452
2022 11:52:40.917498 TX Vref=24, minBit 13, minWin=27, winSum=455
2023 11:52:40.920590 TX Vref=26, minBit 13, minWin=27, winSum=459
2024 11:52:40.924332 TX Vref=28, minBit 8, minWin=28, winSum=459
2025 11:52:40.927272 TX Vref=30, minBit 8, minWin=28, winSum=459
2026 11:52:40.934712 TX Vref=32, minBit 8, minWin=28, winSum=457
2027 11:52:40.937574 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
2028 11:52:40.937658
2029 11:52:40.941012 Final TX Range 1 Vref 28
2030 11:52:40.941095
2031 11:52:40.941161 ==
2032 11:52:40.944064 Dram Type= 6, Freq= 0, CH_1, rank 1
2033 11:52:40.947697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2034 11:52:40.947781 ==
2035 11:52:40.947847
2036 11:52:40.950649
2037 11:52:40.950731 TX Vref Scan disable
2038 11:52:40.954212 == TX Byte 0 ==
2039 11:52:40.957590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2040 11:52:40.961000 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2041 11:52:40.964197 == TX Byte 1 ==
2042 11:52:40.967894 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2043 11:52:40.971025 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2044 11:52:40.971115
2045 11:52:40.974587 [DATLAT]
2046 11:52:40.974696 Freq=800, CH1 RK1
2047 11:52:40.974789
2048 11:52:40.977566 DATLAT Default: 0xa
2049 11:52:40.977648 0, 0xFFFF, sum = 0
2050 11:52:40.981012 1, 0xFFFF, sum = 0
2051 11:52:40.981096 2, 0xFFFF, sum = 0
2052 11:52:40.984511 3, 0xFFFF, sum = 0
2053 11:52:40.984595 4, 0xFFFF, sum = 0
2054 11:52:40.987328 5, 0xFFFF, sum = 0
2055 11:52:40.987412 6, 0xFFFF, sum = 0
2056 11:52:40.990610 7, 0xFFFF, sum = 0
2057 11:52:40.994327 8, 0xFFFF, sum = 0
2058 11:52:40.994458 9, 0x0, sum = 1
2059 11:52:40.994527 10, 0x0, sum = 2
2060 11:52:40.997721 11, 0x0, sum = 3
2061 11:52:40.997806 12, 0x0, sum = 4
2062 11:52:41.000768 best_step = 10
2063 11:52:41.000852
2064 11:52:41.000917 ==
2065 11:52:41.004797 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 11:52:41.007979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 11:52:41.008063 ==
2068 11:52:41.011257 RX Vref Scan: 0
2069 11:52:41.011341
2070 11:52:41.011407 RX Vref 0 -> 0, step: 1
2071 11:52:41.011469
2072 11:52:41.014504 RX Delay -95 -> 252, step: 8
2073 11:52:41.020835 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2074 11:52:41.024325 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2075 11:52:41.027702 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2076 11:52:41.030994 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2077 11:52:41.034419 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2078 11:52:41.041095 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2079 11:52:41.044198 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2080 11:52:41.047526 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2081 11:52:41.051353 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2082 11:52:41.054540 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2083 11:52:41.057794 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2084 11:52:41.064280 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2085 11:52:41.067695 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2086 11:52:41.071103 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2087 11:52:41.074560 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2088 11:52:41.081664 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2089 11:52:41.081749 ==
2090 11:52:41.084504 Dram Type= 6, Freq= 0, CH_1, rank 1
2091 11:52:41.087862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2092 11:52:41.087946 ==
2093 11:52:41.088029 DQS Delay:
2094 11:52:41.091290 DQS0 = 0, DQS1 = 0
2095 11:52:41.091375 DQM Delay:
2096 11:52:41.094621 DQM0 = 91, DQM1 = 84
2097 11:52:41.094705 DQ Delay:
2098 11:52:41.097814 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2099 11:52:41.101051 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2100 11:52:41.104473 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2101 11:52:41.108241 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2102 11:52:41.108325
2103 11:52:41.108391
2104 11:52:41.114817 [DQSOSCAuto] RK1, (LSB)MR18= 0x380d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2105 11:52:41.117793 CH1 RK1: MR19=606, MR18=380D
2106 11:52:41.124987 CH1_RK1: MR19=0x606, MR18=0x380D, DQSOSC=395, MR23=63, INC=94, DEC=63
2107 11:52:41.127863 [RxdqsGatingPostProcess] freq 800
2108 11:52:41.131124 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2109 11:52:41.134814 Pre-setting of DQS Precalculation
2110 11:52:41.141335 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2111 11:52:41.147845 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2112 11:52:41.154985 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2113 11:52:41.155070
2114 11:52:41.155135
2115 11:52:41.158063 [Calibration Summary] 1600 Mbps
2116 11:52:41.158147 CH 0, Rank 0
2117 11:52:41.161504 SW Impedance : PASS
2118 11:52:41.164574 DUTY Scan : NO K
2119 11:52:41.164646 ZQ Calibration : PASS
2120 11:52:41.168078 Jitter Meter : NO K
2121 11:52:41.171268 CBT Training : PASS
2122 11:52:41.171351 Write leveling : PASS
2123 11:52:41.174825 RX DQS gating : PASS
2124 11:52:41.178332 RX DQ/DQS(RDDQC) : PASS
2125 11:52:41.178450 TX DQ/DQS : PASS
2126 11:52:41.181880 RX DATLAT : PASS
2127 11:52:41.184918 RX DQ/DQS(Engine): PASS
2128 11:52:41.185000 TX OE : NO K
2129 11:52:41.185065 All Pass.
2130 11:52:41.188063
2131 11:52:41.188144 CH 0, Rank 1
2132 11:52:41.191553 SW Impedance : PASS
2133 11:52:41.191635 DUTY Scan : NO K
2134 11:52:41.195128 ZQ Calibration : PASS
2135 11:52:41.195210 Jitter Meter : NO K
2136 11:52:41.197984 CBT Training : PASS
2137 11:52:41.201533 Write leveling : PASS
2138 11:52:41.201615 RX DQS gating : PASS
2139 11:52:41.205156 RX DQ/DQS(RDDQC) : PASS
2140 11:52:41.207892 TX DQ/DQS : PASS
2141 11:52:41.207975 RX DATLAT : PASS
2142 11:52:41.211401 RX DQ/DQS(Engine): PASS
2143 11:52:41.214940 TX OE : NO K
2144 11:52:41.215022 All Pass.
2145 11:52:41.215087
2146 11:52:41.215147 CH 1, Rank 0
2147 11:52:41.218054 SW Impedance : PASS
2148 11:52:41.221794 DUTY Scan : NO K
2149 11:52:41.221895 ZQ Calibration : PASS
2150 11:52:41.225057 Jitter Meter : NO K
2151 11:52:41.228091 CBT Training : PASS
2152 11:52:41.228173 Write leveling : PASS
2153 11:52:41.231710 RX DQS gating : PASS
2154 11:52:41.235109 RX DQ/DQS(RDDQC) : PASS
2155 11:52:41.235191 TX DQ/DQS : PASS
2156 11:52:41.238056 RX DATLAT : PASS
2157 11:52:41.238138 RX DQ/DQS(Engine): PASS
2158 11:52:41.241623 TX OE : NO K
2159 11:52:41.241705 All Pass.
2160 11:52:41.241770
2161 11:52:41.245003 CH 1, Rank 1
2162 11:52:41.245081 SW Impedance : PASS
2163 11:52:41.248223 DUTY Scan : NO K
2164 11:52:41.251480 ZQ Calibration : PASS
2165 11:52:41.251563 Jitter Meter : NO K
2166 11:52:41.255002 CBT Training : PASS
2167 11:52:41.258146 Write leveling : PASS
2168 11:52:41.258228 RX DQS gating : PASS
2169 11:52:41.261798 RX DQ/DQS(RDDQC) : PASS
2170 11:52:41.265551 TX DQ/DQS : PASS
2171 11:52:41.265633 RX DATLAT : PASS
2172 11:52:41.268214 RX DQ/DQS(Engine): PASS
2173 11:52:41.271864 TX OE : NO K
2174 11:52:41.271946 All Pass.
2175 11:52:41.272011
2176 11:52:41.272071 DramC Write-DBI off
2177 11:52:41.275212 PER_BANK_REFRESH: Hybrid Mode
2178 11:52:41.278355 TX_TRACKING: ON
2179 11:52:41.282037 [GetDramInforAfterCalByMRR] Vendor 6.
2180 11:52:41.285200 [GetDramInforAfterCalByMRR] Revision 606.
2181 11:52:41.288798 [GetDramInforAfterCalByMRR] Revision 2 0.
2182 11:52:41.288880 MR0 0x3b3b
2183 11:52:41.288945 MR8 0x5151
2184 11:52:41.295182 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2185 11:52:41.295265
2186 11:52:41.295329 MR0 0x3b3b
2187 11:52:41.295389 MR8 0x5151
2188 11:52:41.298572 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2189 11:52:41.298654
2190 11:52:41.309090 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2191 11:52:41.311724 [FAST_K] Save calibration result to emmc
2192 11:52:41.315472 [FAST_K] Save calibration result to emmc
2193 11:52:41.318781 dram_init: config_dvfs: 1
2194 11:52:41.321974 dramc_set_vcore_voltage set vcore to 662500
2195 11:52:41.324977 Read voltage for 1200, 2
2196 11:52:41.325140 Vio18 = 0
2197 11:52:41.325212 Vcore = 662500
2198 11:52:41.328455 Vdram = 0
2199 11:52:41.328526 Vddq = 0
2200 11:52:41.328587 Vmddr = 0
2201 11:52:41.335405 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2202 11:52:41.338717 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2203 11:52:41.341942 MEM_TYPE=3, freq_sel=15
2204 11:52:41.345036 sv_algorithm_assistance_LP4_1600
2205 11:52:41.348876 ============ PULL DRAM RESETB DOWN ============
2206 11:52:41.352161 ========== PULL DRAM RESETB DOWN end =========
2207 11:52:41.358974 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2208 11:52:41.362004 ===================================
2209 11:52:41.362076 LPDDR4 DRAM CONFIGURATION
2210 11:52:41.365422 ===================================
2211 11:52:41.368680 EX_ROW_EN[0] = 0x0
2212 11:52:41.372392 EX_ROW_EN[1] = 0x0
2213 11:52:41.372464 LP4Y_EN = 0x0
2214 11:52:41.375337 WORK_FSP = 0x0
2215 11:52:41.375408 WL = 0x4
2216 11:52:41.378726 RL = 0x4
2217 11:52:41.378801 BL = 0x2
2218 11:52:41.382157 RPST = 0x0
2219 11:52:41.382231 RD_PRE = 0x0
2220 11:52:41.385380 WR_PRE = 0x1
2221 11:52:41.385451 WR_PST = 0x0
2222 11:52:41.388732 DBI_WR = 0x0
2223 11:52:41.388805 DBI_RD = 0x0
2224 11:52:41.391887 OTF = 0x1
2225 11:52:41.395248 ===================================
2226 11:52:41.398846 ===================================
2227 11:52:41.398917 ANA top config
2228 11:52:41.402240 ===================================
2229 11:52:41.405281 DLL_ASYNC_EN = 0
2230 11:52:41.408652 ALL_SLAVE_EN = 0
2231 11:52:41.412070 NEW_RANK_MODE = 1
2232 11:52:41.412141 DLL_IDLE_MODE = 1
2233 11:52:41.415664 LP45_APHY_COMB_EN = 1
2234 11:52:41.418833 TX_ODT_DIS = 1
2235 11:52:41.422200 NEW_8X_MODE = 1
2236 11:52:41.425129 ===================================
2237 11:52:41.428718 ===================================
2238 11:52:41.431886 data_rate = 2400
2239 11:52:41.431957 CKR = 1
2240 11:52:41.435246 DQ_P2S_RATIO = 8
2241 11:52:41.438543 ===================================
2242 11:52:41.442394 CA_P2S_RATIO = 8
2243 11:52:41.445516 DQ_CA_OPEN = 0
2244 11:52:41.448912 DQ_SEMI_OPEN = 0
2245 11:52:41.448996 CA_SEMI_OPEN = 0
2246 11:52:41.452041 CA_FULL_RATE = 0
2247 11:52:41.455349 DQ_CKDIV4_EN = 0
2248 11:52:41.458972 CA_CKDIV4_EN = 0
2249 11:52:41.462274 CA_PREDIV_EN = 0
2250 11:52:41.465451 PH8_DLY = 17
2251 11:52:41.465529 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2252 11:52:41.468969 DQ_AAMCK_DIV = 4
2253 11:52:41.472390 CA_AAMCK_DIV = 4
2254 11:52:41.475550 CA_ADMCK_DIV = 4
2255 11:52:41.478760 DQ_TRACK_CA_EN = 0
2256 11:52:41.482006 CA_PICK = 1200
2257 11:52:41.485443 CA_MCKIO = 1200
2258 11:52:41.485588 MCKIO_SEMI = 0
2259 11:52:41.489009 PLL_FREQ = 2366
2260 11:52:41.492251 DQ_UI_PI_RATIO = 32
2261 11:52:41.495427 CA_UI_PI_RATIO = 0
2262 11:52:41.498706 ===================================
2263 11:52:41.502396 ===================================
2264 11:52:41.505603 memory_type:LPDDR4
2265 11:52:41.505793 GP_NUM : 10
2266 11:52:41.508906 SRAM_EN : 1
2267 11:52:41.509152 MD32_EN : 0
2268 11:52:41.512580 ===================================
2269 11:52:41.515601 [ANA_INIT] >>>>>>>>>>>>>>
2270 11:52:41.518988 <<<<<< [CONFIGURE PHASE]: ANA_TX
2271 11:52:41.522578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2272 11:52:41.525819 ===================================
2273 11:52:41.529093 data_rate = 2400,PCW = 0X5b00
2274 11:52:41.532481 ===================================
2275 11:52:41.535860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2276 11:52:41.539508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 11:52:41.545765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 11:52:41.549393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2279 11:52:41.552576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2280 11:52:41.559502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2281 11:52:41.559954 [ANA_INIT] flow start
2282 11:52:41.562767 [ANA_INIT] PLL >>>>>>>>
2283 11:52:41.563169 [ANA_INIT] PLL <<<<<<<<
2284 11:52:41.566354 [ANA_INIT] MIDPI >>>>>>>>
2285 11:52:41.569964 [ANA_INIT] MIDPI <<<<<<<<
2286 11:52:41.572682 [ANA_INIT] DLL >>>>>>>>
2287 11:52:41.573081 [ANA_INIT] DLL <<<<<<<<
2288 11:52:41.576682 [ANA_INIT] flow end
2289 11:52:41.579445 ============ LP4 DIFF to SE enter ============
2290 11:52:41.582902 ============ LP4 DIFF to SE exit ============
2291 11:52:41.586030 [ANA_INIT] <<<<<<<<<<<<<
2292 11:52:41.589692 [Flow] Enable top DCM control >>>>>
2293 11:52:41.592836 [Flow] Enable top DCM control <<<<<
2294 11:52:41.596058 Enable DLL master slave shuffle
2295 11:52:41.602848 ==============================================================
2296 11:52:41.603271 Gating Mode config
2297 11:52:41.609361 ==============================================================
2298 11:52:41.609784 Config description:
2299 11:52:41.619848 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2300 11:52:41.626360 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2301 11:52:41.633136 SELPH_MODE 0: By rank 1: By Phase
2302 11:52:41.636220 ==============================================================
2303 11:52:41.639741 GAT_TRACK_EN = 1
2304 11:52:41.643106 RX_GATING_MODE = 2
2305 11:52:41.646141 RX_GATING_TRACK_MODE = 2
2306 11:52:41.649538 SELPH_MODE = 1
2307 11:52:41.653154 PICG_EARLY_EN = 1
2308 11:52:41.656612 VALID_LAT_VALUE = 1
2309 11:52:41.659641 ==============================================================
2310 11:52:41.663330 Enter into Gating configuration >>>>
2311 11:52:41.666422 Exit from Gating configuration <<<<
2312 11:52:41.669867 Enter into DVFS_PRE_config >>>>>
2313 11:52:41.682867 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2314 11:52:41.683292 Exit from DVFS_PRE_config <<<<<
2315 11:52:41.686250 Enter into PICG configuration >>>>
2316 11:52:41.689755 Exit from PICG configuration <<<<
2317 11:52:41.692916 [RX_INPUT] configuration >>>>>
2318 11:52:41.696734 [RX_INPUT] configuration <<<<<
2319 11:52:41.703039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2320 11:52:41.706486 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2321 11:52:41.713501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2322 11:52:41.720097 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2323 11:52:41.726815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 11:52:41.733090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 11:52:41.736601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2326 11:52:41.739751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2327 11:52:41.742984 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2328 11:52:41.749825 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2329 11:52:41.753281 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2330 11:52:41.756532 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 11:52:41.759927 ===================================
2332 11:52:41.763014 LPDDR4 DRAM CONFIGURATION
2333 11:52:41.766621 ===================================
2334 11:52:41.767044 EX_ROW_EN[0] = 0x0
2335 11:52:41.769917 EX_ROW_EN[1] = 0x0
2336 11:52:41.770339 LP4Y_EN = 0x0
2337 11:52:41.773108 WORK_FSP = 0x0
2338 11:52:41.773532 WL = 0x4
2339 11:52:41.776676 RL = 0x4
2340 11:52:41.777100 BL = 0x2
2341 11:52:41.779886 RPST = 0x0
2342 11:52:41.783664 RD_PRE = 0x0
2343 11:52:41.784088 WR_PRE = 0x1
2344 11:52:41.786549 WR_PST = 0x0
2345 11:52:41.786973 DBI_WR = 0x0
2346 11:52:41.789839 DBI_RD = 0x0
2347 11:52:41.790264 OTF = 0x1
2348 11:52:41.793129 ===================================
2349 11:52:41.796386 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2350 11:52:41.799690 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2351 11:52:41.806287 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2352 11:52:41.809601 ===================================
2353 11:52:41.813071 LPDDR4 DRAM CONFIGURATION
2354 11:52:41.816089 ===================================
2355 11:52:41.816172 EX_ROW_EN[0] = 0x10
2356 11:52:41.819656 EX_ROW_EN[1] = 0x0
2357 11:52:41.819738 LP4Y_EN = 0x0
2358 11:52:41.823085 WORK_FSP = 0x0
2359 11:52:41.823168 WL = 0x4
2360 11:52:41.826139 RL = 0x4
2361 11:52:41.826245 BL = 0x2
2362 11:52:41.829294 RPST = 0x0
2363 11:52:41.829375 RD_PRE = 0x0
2364 11:52:41.832624 WR_PRE = 0x1
2365 11:52:41.832705 WR_PST = 0x0
2366 11:52:41.836256 DBI_WR = 0x0
2367 11:52:41.836337 DBI_RD = 0x0
2368 11:52:41.839963 OTF = 0x1
2369 11:52:41.842815 ===================================
2370 11:52:41.849587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2371 11:52:41.849676 ==
2372 11:52:41.853053 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 11:52:41.856134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 11:52:41.856216 ==
2375 11:52:41.860062 [Duty_Offset_Calibration]
2376 11:52:41.860142 B0:2 B1:0 CA:1
2377 11:52:41.860205
2378 11:52:41.862685 [DutyScan_Calibration_Flow] k_type=0
2379 11:52:41.872831
2380 11:52:41.872912 ==CLK 0==
2381 11:52:41.875840 Final CLK duty delay cell = -4
2382 11:52:41.879141 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2383 11:52:41.882637 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2384 11:52:41.885923 [-4] AVG Duty = 4953%(X100)
2385 11:52:41.886029
2386 11:52:41.889304 CH0 CLK Duty spec in!! Max-Min= 156%
2387 11:52:41.892751 [DutyScan_Calibration_Flow] ====Done====
2388 11:52:41.892832
2389 11:52:41.895919 [DutyScan_Calibration_Flow] k_type=1
2390 11:52:41.911419
2391 11:52:41.911507 ==DQS 0 ==
2392 11:52:41.914921 Final DQS duty delay cell = 0
2393 11:52:41.918122 [0] MAX Duty = 5187%(X100), DQS PI = 30
2394 11:52:41.921365 [0] MIN Duty = 4938%(X100), DQS PI = 0
2395 11:52:41.921446 [0] AVG Duty = 5062%(X100)
2396 11:52:41.924558
2397 11:52:41.924638 ==DQS 1 ==
2398 11:52:41.928035 Final DQS duty delay cell = -4
2399 11:52:41.931330 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2400 11:52:41.934627 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2401 11:52:41.938174 [-4] AVG Duty = 5031%(X100)
2402 11:52:41.938280
2403 11:52:41.941459 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2404 11:52:41.941541
2405 11:52:41.944871 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2406 11:52:41.948157 [DutyScan_Calibration_Flow] ====Done====
2407 11:52:41.948264
2408 11:52:41.951628 [DutyScan_Calibration_Flow] k_type=3
2409 11:52:41.968671
2410 11:52:41.968751 ==DQM 0 ==
2411 11:52:41.971370 Final DQM duty delay cell = 0
2412 11:52:41.974860 [0] MAX Duty = 5062%(X100), DQS PI = 24
2413 11:52:41.978469 [0] MIN Duty = 4844%(X100), DQS PI = 2
2414 11:52:41.978553 [0] AVG Duty = 4953%(X100)
2415 11:52:41.978619
2416 11:52:41.982103 ==DQM 1 ==
2417 11:52:41.985139 Final DQM duty delay cell = 0
2418 11:52:41.988439 [0] MAX Duty = 5187%(X100), DQS PI = 48
2419 11:52:41.991665 [0] MIN Duty = 5000%(X100), DQS PI = 22
2420 11:52:41.991748 [0] AVG Duty = 5093%(X100)
2421 11:52:41.991813
2422 11:52:41.998149 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2423 11:52:41.998232
2424 11:52:42.001680 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2425 11:52:42.005229 [DutyScan_Calibration_Flow] ====Done====
2426 11:52:42.005340
2427 11:52:42.008369 [DutyScan_Calibration_Flow] k_type=2
2428 11:52:42.023952
2429 11:52:42.024059 ==DQ 0 ==
2430 11:52:42.027377 Final DQ duty delay cell = -4
2431 11:52:42.030497 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2432 11:52:42.033772 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2433 11:52:42.037168 [-4] AVG Duty = 4968%(X100)
2434 11:52:42.037287
2435 11:52:42.037384 ==DQ 1 ==
2436 11:52:42.040730 Final DQ duty delay cell = 0
2437 11:52:42.044368 [0] MAX Duty = 4938%(X100), DQS PI = 4
2438 11:52:42.047527 [0] MIN Duty = 4907%(X100), DQS PI = 0
2439 11:52:42.047638 [0] AVG Duty = 4922%(X100)
2440 11:52:42.047733
2441 11:52:42.051029 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2442 11:52:42.051106
2443 11:52:42.054058 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2444 11:52:42.061156 [DutyScan_Calibration_Flow] ====Done====
2445 11:52:42.061300 ==
2446 11:52:42.064597 Dram Type= 6, Freq= 0, CH_1, rank 0
2447 11:52:42.067715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 11:52:42.067839 ==
2449 11:52:42.071153 [Duty_Offset_Calibration]
2450 11:52:42.071263 B0:0 B1:-1 CA:2
2451 11:52:42.071358
2452 11:52:42.074353 [DutyScan_Calibration_Flow] k_type=0
2453 11:52:42.084075
2454 11:52:42.084185 ==CLK 0==
2455 11:52:42.087787 Final CLK duty delay cell = 0
2456 11:52:42.091283 [0] MAX Duty = 5156%(X100), DQS PI = 16
2457 11:52:42.094023 [0] MIN Duty = 4938%(X100), DQS PI = 44
2458 11:52:42.094123 [0] AVG Duty = 5047%(X100)
2459 11:52:42.097470
2460 11:52:42.100642 CH1 CLK Duty spec in!! Max-Min= 218%
2461 11:52:42.104551 [DutyScan_Calibration_Flow] ====Done====
2462 11:52:42.104647
2463 11:52:42.107496 [DutyScan_Calibration_Flow] k_type=1
2464 11:52:42.123688
2465 11:52:42.123777 ==DQS 0 ==
2466 11:52:42.126728 Final DQS duty delay cell = 0
2467 11:52:42.130355 [0] MAX Duty = 5093%(X100), DQS PI = 24
2468 11:52:42.133637 [0] MIN Duty = 4969%(X100), DQS PI = 0
2469 11:52:42.133740 [0] AVG Duty = 5031%(X100)
2470 11:52:42.136815
2471 11:52:42.136889 ==DQS 1 ==
2472 11:52:42.140155 Final DQS duty delay cell = 0
2473 11:52:42.143351 [0] MAX Duty = 5156%(X100), DQS PI = 0
2474 11:52:42.146531 [0] MIN Duty = 4844%(X100), DQS PI = 36
2475 11:52:42.146634 [0] AVG Duty = 5000%(X100)
2476 11:52:42.150074
2477 11:52:42.153292 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2478 11:52:42.153377
2479 11:52:42.156831 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2480 11:52:42.160084 [DutyScan_Calibration_Flow] ====Done====
2481 11:52:42.160169
2482 11:52:42.163495 [DutyScan_Calibration_Flow] k_type=3
2483 11:52:42.180657
2484 11:52:42.180742 ==DQM 0 ==
2485 11:52:42.183776 Final DQM duty delay cell = 4
2486 11:52:42.187457 [4] MAX Duty = 5093%(X100), DQS PI = 6
2487 11:52:42.191108 [4] MIN Duty = 4969%(X100), DQS PI = 28
2488 11:52:42.191193 [4] AVG Duty = 5031%(X100)
2489 11:52:42.193945
2490 11:52:42.194029 ==DQM 1 ==
2491 11:52:42.197209 Final DQM duty delay cell = 0
2492 11:52:42.200815 [0] MAX Duty = 5249%(X100), DQS PI = 0
2493 11:52:42.203942 [0] MIN Duty = 4875%(X100), DQS PI = 36
2494 11:52:42.204026 [0] AVG Duty = 5062%(X100)
2495 11:52:42.207574
2496 11:52:42.210801 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2497 11:52:42.210885
2498 11:52:42.214059 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2499 11:52:42.217381 [DutyScan_Calibration_Flow] ====Done====
2500 11:52:42.217465
2501 11:52:42.220865 [DutyScan_Calibration_Flow] k_type=2
2502 11:52:42.237283
2503 11:52:42.237367 ==DQ 0 ==
2504 11:52:42.240579 Final DQ duty delay cell = 0
2505 11:52:42.243846 [0] MAX Duty = 5062%(X100), DQS PI = 18
2506 11:52:42.247083 [0] MIN Duty = 4938%(X100), DQS PI = 46
2507 11:52:42.247183 [0] AVG Duty = 5000%(X100)
2508 11:52:42.247267
2509 11:52:42.250656 ==DQ 1 ==
2510 11:52:42.254269 Final DQ duty delay cell = 0
2511 11:52:42.257251 [0] MAX Duty = 5031%(X100), DQS PI = 2
2512 11:52:42.260581 [0] MIN Duty = 4813%(X100), DQS PI = 36
2513 11:52:42.260665 [0] AVG Duty = 4922%(X100)
2514 11:52:42.260748
2515 11:52:42.264084 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2516 11:52:42.264169
2517 11:52:42.267558 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2518 11:52:42.274169 [DutyScan_Calibration_Flow] ====Done====
2519 11:52:42.277254 nWR fixed to 30
2520 11:52:42.277340 [ModeRegInit_LP4] CH0 RK0
2521 11:52:42.280639 [ModeRegInit_LP4] CH0 RK1
2522 11:52:42.284212 [ModeRegInit_LP4] CH1 RK0
2523 11:52:42.284297 [ModeRegInit_LP4] CH1 RK1
2524 11:52:42.287274 match AC timing 7
2525 11:52:42.290870 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2526 11:52:42.294077 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2527 11:52:42.301234 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2528 11:52:42.304142 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2529 11:52:42.310595 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2530 11:52:42.310680 ==
2531 11:52:42.313895 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 11:52:42.317492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 11:52:42.317577 ==
2534 11:52:42.323999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 11:52:42.327577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2536 11:52:42.337189 [CA 0] Center 38 (7~69) winsize 63
2537 11:52:42.340389 [CA 1] Center 38 (8~69) winsize 62
2538 11:52:42.343664 [CA 2] Center 35 (5~66) winsize 62
2539 11:52:42.347215 [CA 3] Center 35 (4~66) winsize 63
2540 11:52:42.350818 [CA 4] Center 34 (4~65) winsize 62
2541 11:52:42.353664 [CA 5] Center 33 (3~63) winsize 61
2542 11:52:42.353747
2543 11:52:42.357029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 11:52:42.357112
2545 11:52:42.360479 [CATrainingPosCal] consider 1 rank data
2546 11:52:42.364146 u2DelayCellTimex100 = 270/100 ps
2547 11:52:42.366961 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2548 11:52:42.370340 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2549 11:52:42.377139 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 11:52:42.380475 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2551 11:52:42.383689 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2552 11:52:42.387246 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2553 11:52:42.387320
2554 11:52:42.390866 CA PerBit enable=1, Macro0, CA PI delay=33
2555 11:52:42.390937
2556 11:52:42.394196 [CBTSetCACLKResult] CA Dly = 33
2557 11:52:42.394310 CS Dly: 6 (0~37)
2558 11:52:42.394410 ==
2559 11:52:42.397051 Dram Type= 6, Freq= 0, CH_0, rank 1
2560 11:52:42.403669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 11:52:42.403782 ==
2562 11:52:42.407341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2563 11:52:42.413920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2564 11:52:42.422639 [CA 0] Center 39 (8~70) winsize 63
2565 11:52:42.426366 [CA 1] Center 38 (8~69) winsize 62
2566 11:52:42.429552 [CA 2] Center 35 (5~66) winsize 62
2567 11:52:42.432688 [CA 3] Center 35 (5~66) winsize 62
2568 11:52:42.436336 [CA 4] Center 34 (4~65) winsize 62
2569 11:52:42.439342 [CA 5] Center 34 (4~64) winsize 61
2570 11:52:42.439417
2571 11:52:42.443128 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2572 11:52:42.443239
2573 11:52:42.446299 [CATrainingPosCal] consider 2 rank data
2574 11:52:42.449780 u2DelayCellTimex100 = 270/100 ps
2575 11:52:42.452806 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2576 11:52:42.456153 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2577 11:52:42.459542 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2578 11:52:42.466520 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2579 11:52:42.469903 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2580 11:52:42.472802 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2581 11:52:42.472902
2582 11:52:42.476286 CA PerBit enable=1, Macro0, CA PI delay=33
2583 11:52:42.476397
2584 11:52:42.479737 [CBTSetCACLKResult] CA Dly = 33
2585 11:52:42.479810 CS Dly: 7 (0~39)
2586 11:52:42.479871
2587 11:52:42.483146 ----->DramcWriteLeveling(PI) begin...
2588 11:52:42.483258 ==
2589 11:52:42.486420 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 11:52:42.493359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 11:52:42.493459 ==
2592 11:52:42.496446 Write leveling (Byte 0): 36 => 36
2593 11:52:42.499907 Write leveling (Byte 1): 32 => 32
2594 11:52:42.499980 DramcWriteLeveling(PI) end<-----
2595 11:52:42.500042
2596 11:52:42.503233 ==
2597 11:52:42.503331 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 11:52:42.509914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 11:52:42.510013 ==
2600 11:52:42.513291 [Gating] SW mode calibration
2601 11:52:42.519782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2602 11:52:42.523108 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2603 11:52:42.529839 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2604 11:52:42.533640 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
2605 11:52:42.536603 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 11:52:42.543901 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:52:42.547172 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:52:42.549811 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:52:42.556555 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2610 11:52:42.560359 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2611 11:52:42.563508 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2612 11:52:42.566966 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 11:52:42.573364 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:52:42.576710 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:52:42.579949 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:52:42.586295 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:52:42.589910 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2618 11:52:42.593101 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2619 11:52:42.600096 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2620 11:52:42.603250 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 11:52:42.606780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:52:42.613480 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:52:42.616570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:52:42.620016 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:52:42.626434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:52:42.629939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2627 11:52:42.633431 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2628 11:52:42.640139 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:52:42.643535 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:52:42.646513 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:52:42.649959 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:52:42.656696 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:52:42.660102 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:52:42.663286 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:52:42.670400 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:52:42.673234 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:52:42.676726 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:52:42.683350 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:52:42.686655 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:52:42.690069 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:52:42.696606 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2642 11:52:42.699786 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2643 11:52:42.703532 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2644 11:52:42.706785 Total UI for P1: 0, mck2ui 16
2645 11:52:42.710234 best dqsien dly found for B0: ( 1, 3, 26)
2646 11:52:42.716610 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2647 11:52:42.716693 Total UI for P1: 0, mck2ui 16
2648 11:52:42.720327 best dqsien dly found for B1: ( 1, 4, 0)
2649 11:52:42.726760 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2650 11:52:42.730103 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2651 11:52:42.730186
2652 11:52:42.733515 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2653 11:52:42.736612 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2654 11:52:42.740158 [Gating] SW calibration Done
2655 11:52:42.740241 ==
2656 11:52:42.743544 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 11:52:42.746633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 11:52:42.746716 ==
2659 11:52:42.746782 RX Vref Scan: 0
2660 11:52:42.750162
2661 11:52:42.750245 RX Vref 0 -> 0, step: 1
2662 11:52:42.750310
2663 11:52:42.753187 RX Delay -40 -> 252, step: 8
2664 11:52:42.756997 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2665 11:52:42.760413 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2666 11:52:42.767103 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2667 11:52:42.770135 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2668 11:52:42.773364 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2669 11:52:42.776733 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2670 11:52:42.780046 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2671 11:52:42.787236 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2672 11:52:42.790358 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2673 11:52:42.793648 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2674 11:52:42.796858 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2675 11:52:42.800097 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2676 11:52:42.804160 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2677 11:52:42.810619 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2678 11:52:42.813915 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2679 11:52:42.817205 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2680 11:52:42.817290 ==
2681 11:52:42.820760 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 11:52:42.823796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 11:52:42.823894 ==
2684 11:52:42.826991 DQS Delay:
2685 11:52:42.827080 DQS0 = 0, DQS1 = 0
2686 11:52:42.830675 DQM Delay:
2687 11:52:42.830745 DQM0 = 122, DQM1 = 110
2688 11:52:42.833884 DQ Delay:
2689 11:52:42.837144 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2690 11:52:42.840548 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2691 11:52:42.843808 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2692 11:52:42.847157 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2693 11:52:42.847269
2694 11:52:42.847363
2695 11:52:42.847454 ==
2696 11:52:42.850551 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 11:52:42.854086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 11:52:42.854184 ==
2699 11:52:42.854275
2700 11:52:42.854364
2701 11:52:42.857123 TX Vref Scan disable
2702 11:52:42.860415 == TX Byte 0 ==
2703 11:52:42.863825 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2704 11:52:42.867222 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2705 11:52:42.870353 == TX Byte 1 ==
2706 11:52:42.873841 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2707 11:52:42.877422 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2708 11:52:42.877520 ==
2709 11:52:42.880443 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 11:52:42.883754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 11:52:42.887030 ==
2712 11:52:42.897259 TX Vref=22, minBit 0, minWin=23, winSum=405
2713 11:52:42.900439 TX Vref=24, minBit 0, minWin=25, winSum=413
2714 11:52:42.903732 TX Vref=26, minBit 1, minWin=25, winSum=418
2715 11:52:42.907147 TX Vref=28, minBit 4, minWin=26, winSum=424
2716 11:52:42.910309 TX Vref=30, minBit 5, minWin=25, winSum=424
2717 11:52:42.913701 TX Vref=32, minBit 3, minWin=26, winSum=424
2718 11:52:42.920729 [TxChooseVref] Worse bit 4, Min win 26, Win sum 424, Final Vref 28
2719 11:52:42.920805
2720 11:52:42.924055 Final TX Range 1 Vref 28
2721 11:52:42.924129
2722 11:52:42.924191 ==
2723 11:52:42.927118 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 11:52:42.930381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 11:52:42.930490 ==
2726 11:52:42.930557
2727 11:52:42.930615
2728 11:52:42.933740 TX Vref Scan disable
2729 11:52:42.937453 == TX Byte 0 ==
2730 11:52:42.940495 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2731 11:52:42.943782 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2732 11:52:42.947136 == TX Byte 1 ==
2733 11:52:42.950568 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2734 11:52:42.953877 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2735 11:52:42.953950
2736 11:52:42.957283 [DATLAT]
2737 11:52:42.957382 Freq=1200, CH0 RK0
2738 11:52:42.957472
2739 11:52:42.960589 DATLAT Default: 0xd
2740 11:52:42.960688 0, 0xFFFF, sum = 0
2741 11:52:42.963932 1, 0xFFFF, sum = 0
2742 11:52:42.964005 2, 0xFFFF, sum = 0
2743 11:52:42.967657 3, 0xFFFF, sum = 0
2744 11:52:42.967732 4, 0xFFFF, sum = 0
2745 11:52:42.971014 5, 0xFFFF, sum = 0
2746 11:52:42.971089 6, 0xFFFF, sum = 0
2747 11:52:42.973940 7, 0xFFFF, sum = 0
2748 11:52:42.974016 8, 0xFFFF, sum = 0
2749 11:52:42.977265 9, 0xFFFF, sum = 0
2750 11:52:42.977363 10, 0xFFFF, sum = 0
2751 11:52:42.980728 11, 0xFFFF, sum = 0
2752 11:52:42.980808 12, 0x0, sum = 1
2753 11:52:42.983975 13, 0x0, sum = 2
2754 11:52:42.984053 14, 0x0, sum = 3
2755 11:52:42.987557 15, 0x0, sum = 4
2756 11:52:42.987632 best_step = 13
2757 11:52:42.987694
2758 11:52:42.987752 ==
2759 11:52:42.990819 Dram Type= 6, Freq= 0, CH_0, rank 0
2760 11:52:42.997723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2761 11:52:42.997796 ==
2762 11:52:42.997863 RX Vref Scan: 1
2763 11:52:42.997921
2764 11:52:43.001007 Set Vref Range= 32 -> 127
2765 11:52:43.001105
2766 11:52:43.004337 RX Vref 32 -> 127, step: 1
2767 11:52:43.004433
2768 11:52:43.008042 RX Delay -13 -> 252, step: 4
2769 11:52:43.008116
2770 11:52:43.008181 Set Vref, RX VrefLevel [Byte0]: 32
2771 11:52:43.010980 [Byte1]: 32
2772 11:52:43.015178
2773 11:52:43.015276 Set Vref, RX VrefLevel [Byte0]: 33
2774 11:52:43.018609 [Byte1]: 33
2775 11:52:43.023234
2776 11:52:43.023340 Set Vref, RX VrefLevel [Byte0]: 34
2777 11:52:43.026511 [Byte1]: 34
2778 11:52:43.031130
2779 11:52:43.031211 Set Vref, RX VrefLevel [Byte0]: 35
2780 11:52:43.034368 [Byte1]: 35
2781 11:52:43.039022
2782 11:52:43.039127 Set Vref, RX VrefLevel [Byte0]: 36
2783 11:52:43.042479 [Byte1]: 36
2784 11:52:43.047246
2785 11:52:43.047323 Set Vref, RX VrefLevel [Byte0]: 37
2786 11:52:43.050274 [Byte1]: 37
2787 11:52:43.055408
2788 11:52:43.055484 Set Vref, RX VrefLevel [Byte0]: 38
2789 11:52:43.058140 [Byte1]: 38
2790 11:52:43.062946
2791 11:52:43.063030 Set Vref, RX VrefLevel [Byte0]: 39
2792 11:52:43.066032 [Byte1]: 39
2793 11:52:43.070795
2794 11:52:43.070868 Set Vref, RX VrefLevel [Byte0]: 40
2795 11:52:43.074147 [Byte1]: 40
2796 11:52:43.078727
2797 11:52:43.078838 Set Vref, RX VrefLevel [Byte0]: 41
2798 11:52:43.081682 [Byte1]: 41
2799 11:52:43.086518
2800 11:52:43.086627 Set Vref, RX VrefLevel [Byte0]: 42
2801 11:52:43.089643 [Byte1]: 42
2802 11:52:43.094428
2803 11:52:43.094547 Set Vref, RX VrefLevel [Byte0]: 43
2804 11:52:43.097868 [Byte1]: 43
2805 11:52:43.102126
2806 11:52:43.102234 Set Vref, RX VrefLevel [Byte0]: 44
2807 11:52:43.105594 [Byte1]: 44
2808 11:52:43.109962
2809 11:52:43.110038 Set Vref, RX VrefLevel [Byte0]: 45
2810 11:52:43.113547 [Byte1]: 45
2811 11:52:43.117950
2812 11:52:43.118050 Set Vref, RX VrefLevel [Byte0]: 46
2813 11:52:43.121165 [Byte1]: 46
2814 11:52:43.125795
2815 11:52:43.125866 Set Vref, RX VrefLevel [Byte0]: 47
2816 11:52:43.129443 [Byte1]: 47
2817 11:52:43.133923
2818 11:52:43.133997 Set Vref, RX VrefLevel [Byte0]: 48
2819 11:52:43.136967 [Byte1]: 48
2820 11:52:43.141617
2821 11:52:43.141716 Set Vref, RX VrefLevel [Byte0]: 49
2822 11:52:43.144758 [Byte1]: 49
2823 11:52:43.149578
2824 11:52:43.149657 Set Vref, RX VrefLevel [Byte0]: 50
2825 11:52:43.152935 [Byte1]: 50
2826 11:52:43.157473
2827 11:52:43.157548 Set Vref, RX VrefLevel [Byte0]: 51
2828 11:52:43.161035 [Byte1]: 51
2829 11:52:43.165293
2830 11:52:43.165394 Set Vref, RX VrefLevel [Byte0]: 52
2831 11:52:43.168689 [Byte1]: 52
2832 11:52:43.173327
2833 11:52:43.173404 Set Vref, RX VrefLevel [Byte0]: 53
2834 11:52:43.176491 [Byte1]: 53
2835 11:52:43.181279
2836 11:52:43.181362 Set Vref, RX VrefLevel [Byte0]: 54
2837 11:52:43.184292 [Byte1]: 54
2838 11:52:43.188852
2839 11:52:43.188975 Set Vref, RX VrefLevel [Byte0]: 55
2840 11:52:43.192206 [Byte1]: 55
2841 11:52:43.197397
2842 11:52:43.197520 Set Vref, RX VrefLevel [Byte0]: 56
2843 11:52:43.200466 [Byte1]: 56
2844 11:52:43.205122
2845 11:52:43.205252 Set Vref, RX VrefLevel [Byte0]: 57
2846 11:52:43.208003 [Byte1]: 57
2847 11:52:43.212696
2848 11:52:43.212875 Set Vref, RX VrefLevel [Byte0]: 58
2849 11:52:43.215997 [Byte1]: 58
2850 11:52:43.221077
2851 11:52:43.221298 Set Vref, RX VrefLevel [Byte0]: 59
2852 11:52:43.223867 [Byte1]: 59
2853 11:52:43.228963
2854 11:52:43.229322 Set Vref, RX VrefLevel [Byte0]: 60
2855 11:52:43.232441 [Byte1]: 60
2856 11:52:43.236651
2857 11:52:43.237037 Set Vref, RX VrefLevel [Byte0]: 61
2858 11:52:43.239947 [Byte1]: 61
2859 11:52:43.244364
2860 11:52:43.244764 Set Vref, RX VrefLevel [Byte0]: 62
2861 11:52:43.247857 [Byte1]: 62
2862 11:52:43.252568
2863 11:52:43.253076 Set Vref, RX VrefLevel [Byte0]: 63
2864 11:52:43.255967 [Byte1]: 63
2865 11:52:43.260372
2866 11:52:43.260941 Set Vref, RX VrefLevel [Byte0]: 64
2867 11:52:43.264045 [Byte1]: 64
2868 11:52:43.268491
2869 11:52:43.268950 Set Vref, RX VrefLevel [Byte0]: 65
2870 11:52:43.271607 [Byte1]: 65
2871 11:52:43.276109
2872 11:52:43.276547 Set Vref, RX VrefLevel [Byte0]: 66
2873 11:52:43.279550 [Byte1]: 66
2874 11:52:43.284214
2875 11:52:43.284663 Set Vref, RX VrefLevel [Byte0]: 67
2876 11:52:43.287317 [Byte1]: 67
2877 11:52:43.292091
2878 11:52:43.292531 Set Vref, RX VrefLevel [Byte0]: 68
2879 11:52:43.295130 [Byte1]: 68
2880 11:52:43.299902
2881 11:52:43.302861 Set Vref, RX VrefLevel [Byte0]: 69
2882 11:52:43.306580 [Byte1]: 69
2883 11:52:43.307009
2884 11:52:43.309647 Set Vref, RX VrefLevel [Byte0]: 70
2885 11:52:43.313018 [Byte1]: 70
2886 11:52:43.313447
2887 11:52:43.316272 Final RX Vref Byte 0 = 57 to rank0
2888 11:52:43.319507 Final RX Vref Byte 1 = 48 to rank0
2889 11:52:43.323288 Final RX Vref Byte 0 = 57 to rank1
2890 11:52:43.326511 Final RX Vref Byte 1 = 48 to rank1==
2891 11:52:43.329466 Dram Type= 6, Freq= 0, CH_0, rank 0
2892 11:52:43.333333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 11:52:43.333730 ==
2894 11:52:43.336656 DQS Delay:
2895 11:52:43.337046 DQS0 = 0, DQS1 = 0
2896 11:52:43.339866 DQM Delay:
2897 11:52:43.340346 DQM0 = 122, DQM1 = 109
2898 11:52:43.340783 DQ Delay:
2899 11:52:43.343175 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2900 11:52:43.349736 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2901 11:52:43.353309 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2902 11:52:43.356617 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =118
2903 11:52:43.357037
2904 11:52:43.357364
2905 11:52:43.363197 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2906 11:52:43.366534 CH0 RK0: MR19=404, MR18=E0B
2907 11:52:43.373023 CH0_RK0: MR19=0x404, MR18=0xE0B, DQSOSC=404, MR23=63, INC=40, DEC=26
2908 11:52:43.373443
2909 11:52:43.376231 ----->DramcWriteLeveling(PI) begin...
2910 11:52:43.376659 ==
2911 11:52:43.379717 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 11:52:43.383306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 11:52:43.383731 ==
2914 11:52:43.386722 Write leveling (Byte 0): 35 => 35
2915 11:52:43.390302 Write leveling (Byte 1): 31 => 31
2916 11:52:43.393576 DramcWriteLeveling(PI) end<-----
2917 11:52:43.394033
2918 11:52:43.394366 ==
2919 11:52:43.396565 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 11:52:43.400521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 11:52:43.400947 ==
2922 11:52:43.403600 [Gating] SW mode calibration
2923 11:52:43.409884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2924 11:52:43.416788 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2925 11:52:43.420304 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2926 11:52:43.423414 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 11:52:43.429975 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:52:43.433426 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:52:43.436756 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 11:52:43.443368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:52:43.446616 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2932 11:52:43.450257 0 15 28 | B1->B0 | 3030 2c2c | 0 0 | (1 0) (0 0)
2933 11:52:43.456710 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2934 11:52:43.460222 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 11:52:43.463945 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:52:43.470313 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:52:43.473709 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:52:43.476838 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:52:43.479999 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2940 11:52:43.486939 1 0 28 | B1->B0 | 3333 3a3a | 0 1 | (0 0) (1 1)
2941 11:52:43.490134 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:52:43.493535 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 11:52:43.500368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:52:43.504283 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:52:43.506834 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:52:43.513696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:52:43.516936 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:52:43.520317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2949 11:52:43.527177 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2950 11:52:43.530381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:52:43.533792 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:52:43.540599 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:52:43.543525 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:52:43.547008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:52:43.553940 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:52:43.557185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:52:43.560445 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:52:43.564013 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:52:43.570222 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:52:43.573707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:52:43.577018 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:52:43.583880 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:52:43.587086 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:52:43.590503 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2965 11:52:43.597349 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2966 11:52:43.597773 Total UI for P1: 0, mck2ui 16
2967 11:52:43.603624 best dqsien dly found for B1: ( 1, 3, 28)
2968 11:52:43.607272 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 11:52:43.610607 Total UI for P1: 0, mck2ui 16
2970 11:52:43.613766 best dqsien dly found for B0: ( 1, 3, 30)
2971 11:52:43.617109 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2972 11:52:43.620183 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2973 11:52:43.620592
2974 11:52:43.623657 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2975 11:52:43.627367 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2976 11:52:43.630335 [Gating] SW calibration Done
2977 11:52:43.630848 ==
2978 11:52:43.633721 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:52:43.638014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:52:43.638472 ==
2981 11:52:43.640501 RX Vref Scan: 0
2982 11:52:43.640917
2983 11:52:43.643813 RX Vref 0 -> 0, step: 1
2984 11:52:43.644231
2985 11:52:43.644564 RX Delay -40 -> 252, step: 8
2986 11:52:43.650526 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2987 11:52:43.654264 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2988 11:52:43.657200 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2989 11:52:43.660635 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2990 11:52:43.663783 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2991 11:52:43.670359 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2992 11:52:43.674075 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2993 11:52:43.677187 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2994 11:52:43.680468 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2995 11:52:43.683777 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2996 11:52:43.690657 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2997 11:52:43.693959 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2998 11:52:43.697375 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2999 11:52:43.700824 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3000 11:52:43.704119 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3001 11:52:43.710580 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
3002 11:52:43.711022 ==
3003 11:52:43.714083 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 11:52:43.717220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 11:52:43.717701 ==
3006 11:52:43.718072 DQS Delay:
3007 11:52:43.720778 DQS0 = 0, DQS1 = 0
3008 11:52:43.721211 DQM Delay:
3009 11:52:43.723979 DQM0 = 120, DQM1 = 108
3010 11:52:43.724412 DQ Delay:
3011 11:52:43.727201 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3012 11:52:43.730635 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3013 11:52:43.734102 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3014 11:52:43.737433 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3015 11:52:43.737862
3016 11:52:43.738285
3017 11:52:43.738714 ==
3018 11:52:43.741050 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 11:52:43.747135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 11:52:43.747571 ==
3021 11:52:43.748005
3022 11:52:43.748416
3023 11:52:43.748815 TX Vref Scan disable
3024 11:52:43.751029 == TX Byte 0 ==
3025 11:52:43.754336 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3026 11:52:43.757520 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3027 11:52:43.760813 == TX Byte 1 ==
3028 11:52:43.764246 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3029 11:52:43.767496 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3030 11:52:43.770854 ==
3031 11:52:43.774609 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 11:52:43.777514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 11:52:43.777947 ==
3034 11:52:43.789110 TX Vref=22, minBit 0, minWin=24, winSum=405
3035 11:52:43.792674 TX Vref=24, minBit 5, minWin=24, winSum=414
3036 11:52:43.795691 TX Vref=26, minBit 1, minWin=25, winSum=415
3037 11:52:43.799009 TX Vref=28, minBit 1, minWin=25, winSum=415
3038 11:52:43.802602 TX Vref=30, minBit 1, minWin=25, winSum=421
3039 11:52:43.809169 TX Vref=32, minBit 1, minWin=25, winSum=418
3040 11:52:43.812622 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 30
3041 11:52:43.813056
3042 11:52:43.815660 Final TX Range 1 Vref 30
3043 11:52:43.816093
3044 11:52:43.816518 ==
3045 11:52:43.819331 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 11:52:43.822553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 11:52:43.822986 ==
3048 11:52:43.823417
3049 11:52:43.826109
3050 11:52:43.826571 TX Vref Scan disable
3051 11:52:43.829232 == TX Byte 0 ==
3052 11:52:43.832753 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3053 11:52:43.835723 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3054 11:52:43.839251 == TX Byte 1 ==
3055 11:52:43.842738 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3056 11:52:43.845903 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3057 11:52:43.846309
3058 11:52:43.849189 [DATLAT]
3059 11:52:43.849603 Freq=1200, CH0 RK1
3060 11:52:43.849956
3061 11:52:43.852845 DATLAT Default: 0xd
3062 11:52:43.853305 0, 0xFFFF, sum = 0
3063 11:52:43.855916 1, 0xFFFF, sum = 0
3064 11:52:43.856378 2, 0xFFFF, sum = 0
3065 11:52:43.859442 3, 0xFFFF, sum = 0
3066 11:52:43.859942 4, 0xFFFF, sum = 0
3067 11:52:43.862649 5, 0xFFFF, sum = 0
3068 11:52:43.863119 6, 0xFFFF, sum = 0
3069 11:52:43.866451 7, 0xFFFF, sum = 0
3070 11:52:43.866918 8, 0xFFFF, sum = 0
3071 11:52:43.869510 9, 0xFFFF, sum = 0
3072 11:52:43.869970 10, 0xFFFF, sum = 0
3073 11:52:43.872864 11, 0xFFFF, sum = 0
3074 11:52:43.873327 12, 0x0, sum = 1
3075 11:52:43.875907 13, 0x0, sum = 2
3076 11:52:43.876376 14, 0x0, sum = 3
3077 11:52:43.879582 15, 0x0, sum = 4
3078 11:52:43.880040 best_step = 13
3079 11:52:43.880409
3080 11:52:43.880755 ==
3081 11:52:43.882986 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:52:43.889726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:52:43.890209 ==
3084 11:52:43.890616 RX Vref Scan: 0
3085 11:52:43.890967
3086 11:52:43.892852 RX Vref 0 -> 0, step: 1
3087 11:52:43.893299
3088 11:52:43.896169 RX Delay -21 -> 252, step: 4
3089 11:52:43.899552 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3090 11:52:43.902811 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3091 11:52:43.909427 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3092 11:52:43.912950 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3093 11:52:43.916383 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3094 11:52:43.919579 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3095 11:52:43.923025 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3096 11:52:43.926298 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3097 11:52:43.932919 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3098 11:52:43.936667 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3099 11:52:43.939834 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3100 11:52:43.943440 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3101 11:52:43.946443 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3102 11:52:43.952835 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3103 11:52:43.956264 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3104 11:52:43.959921 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3105 11:52:43.960394 ==
3106 11:52:43.963280 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 11:52:43.966445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 11:52:43.969460 ==
3109 11:52:43.969922 DQS Delay:
3110 11:52:43.970295 DQS0 = 0, DQS1 = 0
3111 11:52:43.973249 DQM Delay:
3112 11:52:43.973707 DQM0 = 119, DQM1 = 107
3113 11:52:43.976270 DQ Delay:
3114 11:52:43.979709 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =112
3115 11:52:43.983296 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3116 11:52:43.986760 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3117 11:52:43.989937 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3118 11:52:43.990429
3119 11:52:43.990804
3120 11:52:43.996512 [DQSOSCAuto] RK1, (LSB)MR18= 0xef6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3121 11:52:44.000017 CH0 RK1: MR19=403, MR18=EF6
3122 11:52:44.007140 CH0_RK1: MR19=0x403, MR18=0xEF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3123 11:52:44.010068 [RxdqsGatingPostProcess] freq 1200
3124 11:52:44.013462 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3125 11:52:44.016894 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 11:52:44.020550 best DQS1 dly(2T, 0.5T) = (0, 12)
3127 11:52:44.023366 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 11:52:44.026691 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3129 11:52:44.029994 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 11:52:44.033261 best DQS1 dly(2T, 0.5T) = (0, 11)
3131 11:52:44.036611 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 11:52:44.040318 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3133 11:52:44.043640 Pre-setting of DQS Precalculation
3134 11:52:44.046847 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3135 11:52:44.047269 ==
3136 11:52:44.050033 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 11:52:44.056643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 11:52:44.057111 ==
3139 11:52:44.060154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 11:52:44.066860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3141 11:52:44.075156 [CA 0] Center 37 (7~68) winsize 62
3142 11:52:44.078441 [CA 1] Center 37 (7~68) winsize 62
3143 11:52:44.081988 [CA 2] Center 35 (5~65) winsize 61
3144 11:52:44.085349 [CA 3] Center 34 (4~65) winsize 62
3145 11:52:44.088345 [CA 4] Center 34 (4~65) winsize 62
3146 11:52:44.091751 [CA 5] Center 33 (3~64) winsize 62
3147 11:52:44.092173
3148 11:52:44.095199 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3149 11:52:44.095624
3150 11:52:44.098320 [CATrainingPosCal] consider 1 rank data
3151 11:52:44.102125 u2DelayCellTimex100 = 270/100 ps
3152 11:52:44.105460 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 11:52:44.108687 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 11:52:44.112370 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3155 11:52:44.118346 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3156 11:52:44.121935 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3157 11:52:44.125520 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3158 11:52:44.126091
3159 11:52:44.128558 CA PerBit enable=1, Macro0, CA PI delay=33
3160 11:52:44.129198
3161 11:52:44.131938 [CBTSetCACLKResult] CA Dly = 33
3162 11:52:44.132521 CS Dly: 5 (0~36)
3163 11:52:44.132912 ==
3164 11:52:44.135255 Dram Type= 6, Freq= 0, CH_1, rank 1
3165 11:52:44.141742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 11:52:44.142418 ==
3167 11:52:44.145480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3168 11:52:44.151875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3169 11:52:44.160929 [CA 0] Center 38 (8~69) winsize 62
3170 11:52:44.164127 [CA 1] Center 38 (7~69) winsize 63
3171 11:52:44.167487 [CA 2] Center 35 (5~66) winsize 62
3172 11:52:44.170750 [CA 3] Center 35 (5~65) winsize 61
3173 11:52:44.174449 [CA 4] Center 34 (4~64) winsize 61
3174 11:52:44.177562 [CA 5] Center 34 (4~64) winsize 61
3175 11:52:44.177980
3176 11:52:44.180800 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3177 11:52:44.181222
3178 11:52:44.184132 [CATrainingPosCal] consider 2 rank data
3179 11:52:44.187479 u2DelayCellTimex100 = 270/100 ps
3180 11:52:44.190751 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3181 11:52:44.194074 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3182 11:52:44.197725 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3183 11:52:44.204530 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3184 11:52:44.207449 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3185 11:52:44.210974 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3186 11:52:44.211399
3187 11:52:44.214230 CA PerBit enable=1, Macro0, CA PI delay=34
3188 11:52:44.214688
3189 11:52:44.217807 [CBTSetCACLKResult] CA Dly = 34
3190 11:52:44.218227 CS Dly: 6 (0~39)
3191 11:52:44.218607
3192 11:52:44.220884 ----->DramcWriteLeveling(PI) begin...
3193 11:52:44.221310 ==
3194 11:52:44.224341 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 11:52:44.231264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 11:52:44.231691 ==
3197 11:52:44.234515 Write leveling (Byte 0): 24 => 24
3198 11:52:44.237619 Write leveling (Byte 1): 29 => 29
3199 11:52:44.238042 DramcWriteLeveling(PI) end<-----
3200 11:52:44.238376
3201 11:52:44.241016 ==
3202 11:52:44.244476 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 11:52:44.247668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 11:52:44.248158 ==
3205 11:52:44.251036 [Gating] SW mode calibration
3206 11:52:44.258036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3207 11:52:44.261050 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3208 11:52:44.267536 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 11:52:44.270816 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:52:44.273854 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:52:44.280869 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 11:52:44.283928 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:52:44.287508 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:52:44.293615 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
3215 11:52:44.297072 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3216 11:52:44.300523 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:52:44.307249 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:52:44.311169 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:52:44.313915 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:52:44.320951 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:52:44.323891 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3222 11:52:44.327145 1 0 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3223 11:52:44.330473 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:52:44.337124 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:52:44.340867 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:52:44.343921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:52:44.350861 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:52:44.353918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:52:44.357487 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3230 11:52:44.363910 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3231 11:52:44.367433 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3232 11:52:44.370974 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:52:44.377614 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:52:44.380614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:52:44.384423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:52:44.390799 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:52:44.394417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:52:44.397538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:52:44.400675 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:52:44.407345 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:52:44.410773 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:52:44.414451 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:52:44.420777 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:52:44.424602 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:52:44.427442 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3246 11:52:44.434110 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3247 11:52:44.437446 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 11:52:44.440977 Total UI for P1: 0, mck2ui 16
3249 11:52:44.444250 best dqsien dly found for B0: ( 1, 3, 22)
3250 11:52:44.447433 Total UI for P1: 0, mck2ui 16
3251 11:52:44.450945 best dqsien dly found for B1: ( 1, 3, 24)
3252 11:52:44.454249 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3253 11:52:44.457798 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3254 11:52:44.457883
3255 11:52:44.460812 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3256 11:52:44.464468 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3257 11:52:44.467450 [Gating] SW calibration Done
3258 11:52:44.467533 ==
3259 11:52:44.471007 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 11:52:44.474142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 11:52:44.474226 ==
3262 11:52:44.477490 RX Vref Scan: 0
3263 11:52:44.477573
3264 11:52:44.481212 RX Vref 0 -> 0, step: 1
3265 11:52:44.481296
3266 11:52:44.481362 RX Delay -40 -> 252, step: 8
3267 11:52:44.487571 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3268 11:52:44.490890 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3269 11:52:44.494492 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3270 11:52:44.497742 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3271 11:52:44.501581 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3272 11:52:44.507866 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3273 11:52:44.510919 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3274 11:52:44.514513 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3275 11:52:44.518200 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3276 11:52:44.521273 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3277 11:52:44.524917 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3278 11:52:44.531231 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3279 11:52:44.534530 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3280 11:52:44.537769 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3281 11:52:44.541126 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3282 11:52:44.547690 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3283 11:52:44.547773 ==
3284 11:52:44.551510 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 11:52:44.554580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 11:52:44.554681 ==
3287 11:52:44.554748 DQS Delay:
3288 11:52:44.557779 DQS0 = 0, DQS1 = 0
3289 11:52:44.557863 DQM Delay:
3290 11:52:44.561551 DQM0 = 120, DQM1 = 112
3291 11:52:44.561635 DQ Delay:
3292 11:52:44.564874 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3293 11:52:44.568036 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3294 11:52:44.571239 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3295 11:52:44.574694 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3296 11:52:44.574778
3297 11:52:44.574843
3298 11:52:44.574904 ==
3299 11:52:44.577976 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 11:52:44.584601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 11:52:44.584686 ==
3302 11:52:44.584752
3303 11:52:44.584814
3304 11:52:44.584872 TX Vref Scan disable
3305 11:52:44.588674 == TX Byte 0 ==
3306 11:52:44.591319 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3307 11:52:44.594966 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3308 11:52:44.598126 == TX Byte 1 ==
3309 11:52:44.601564 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3310 11:52:44.605285 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3311 11:52:44.608252 ==
3312 11:52:44.611581 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 11:52:44.614672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 11:52:44.614757 ==
3315 11:52:44.626051 TX Vref=22, minBit 11, minWin=24, winSum=406
3316 11:52:44.629970 TX Vref=24, minBit 3, minWin=25, winSum=410
3317 11:52:44.633100 TX Vref=26, minBit 8, minWin=25, winSum=415
3318 11:52:44.635914 TX Vref=28, minBit 10, minWin=25, winSum=417
3319 11:52:44.639653 TX Vref=30, minBit 9, minWin=25, winSum=424
3320 11:52:44.646249 TX Vref=32, minBit 9, minWin=25, winSum=422
3321 11:52:44.649693 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 30
3322 11:52:44.649778
3323 11:52:44.652659 Final TX Range 1 Vref 30
3324 11:52:44.652743
3325 11:52:44.652809 ==
3326 11:52:44.655922 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 11:52:44.659501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 11:52:44.659583 ==
3329 11:52:44.662680
3330 11:52:44.662754
3331 11:52:44.662816 TX Vref Scan disable
3332 11:52:44.665979 == TX Byte 0 ==
3333 11:52:44.669266 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3334 11:52:44.672574 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3335 11:52:44.676136 == TX Byte 1 ==
3336 11:52:44.679587 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3337 11:52:44.682587 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3338 11:52:44.686544
3339 11:52:44.686616 [DATLAT]
3340 11:52:44.686679 Freq=1200, CH1 RK0
3341 11:52:44.686738
3342 11:52:44.689734 DATLAT Default: 0xd
3343 11:52:44.689806 0, 0xFFFF, sum = 0
3344 11:52:44.692841 1, 0xFFFF, sum = 0
3345 11:52:44.692914 2, 0xFFFF, sum = 0
3346 11:52:44.696524 3, 0xFFFF, sum = 0
3347 11:52:44.696597 4, 0xFFFF, sum = 0
3348 11:52:44.699757 5, 0xFFFF, sum = 0
3349 11:52:44.699829 6, 0xFFFF, sum = 0
3350 11:52:44.703247 7, 0xFFFF, sum = 0
3351 11:52:44.706017 8, 0xFFFF, sum = 0
3352 11:52:44.706090 9, 0xFFFF, sum = 0
3353 11:52:44.710094 10, 0xFFFF, sum = 0
3354 11:52:44.710167 11, 0xFFFF, sum = 0
3355 11:52:44.712877 12, 0x0, sum = 1
3356 11:52:44.712956 13, 0x0, sum = 2
3357 11:52:44.716331 14, 0x0, sum = 3
3358 11:52:44.716404 15, 0x0, sum = 4
3359 11:52:44.716465 best_step = 13
3360 11:52:44.716530
3361 11:52:44.719665 ==
3362 11:52:44.719741 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 11:52:44.726187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 11:52:44.726278 ==
3365 11:52:44.726345 RX Vref Scan: 1
3366 11:52:44.726416
3367 11:52:44.729377 Set Vref Range= 32 -> 127
3368 11:52:44.729457
3369 11:52:44.732833 RX Vref 32 -> 127, step: 1
3370 11:52:44.732922
3371 11:52:44.736498 RX Delay -13 -> 252, step: 4
3372 11:52:44.736592
3373 11:52:44.739838 Set Vref, RX VrefLevel [Byte0]: 32
3374 11:52:44.742870 [Byte1]: 32
3375 11:52:44.742989
3376 11:52:44.746606 Set Vref, RX VrefLevel [Byte0]: 33
3377 11:52:44.749699 [Byte1]: 33
3378 11:52:44.749832
3379 11:52:44.752933 Set Vref, RX VrefLevel [Byte0]: 34
3380 11:52:44.756621 [Byte1]: 34
3381 11:52:44.760466
3382 11:52:44.760633 Set Vref, RX VrefLevel [Byte0]: 35
3383 11:52:44.763709 [Byte1]: 35
3384 11:52:44.768756
3385 11:52:44.768989 Set Vref, RX VrefLevel [Byte0]: 36
3386 11:52:44.771699 [Byte1]: 36
3387 11:52:44.776278
3388 11:52:44.776567 Set Vref, RX VrefLevel [Byte0]: 37
3389 11:52:44.779843 [Byte1]: 37
3390 11:52:44.784398
3391 11:52:44.784803 Set Vref, RX VrefLevel [Byte0]: 38
3392 11:52:44.787834 [Byte1]: 38
3393 11:52:44.792199
3394 11:52:44.792606 Set Vref, RX VrefLevel [Byte0]: 39
3395 11:52:44.795664 [Byte1]: 39
3396 11:52:44.799751
3397 11:52:44.799831 Set Vref, RX VrefLevel [Byte0]: 40
3398 11:52:44.803147 [Byte1]: 40
3399 11:52:44.807596
3400 11:52:44.807676 Set Vref, RX VrefLevel [Byte0]: 41
3401 11:52:44.811011 [Byte1]: 41
3402 11:52:44.815798
3403 11:52:44.815877 Set Vref, RX VrefLevel [Byte0]: 42
3404 11:52:44.818665 [Byte1]: 42
3405 11:52:44.823370
3406 11:52:44.823449 Set Vref, RX VrefLevel [Byte0]: 43
3407 11:52:44.826684 [Byte1]: 43
3408 11:52:44.831302
3409 11:52:44.831381 Set Vref, RX VrefLevel [Byte0]: 44
3410 11:52:44.834450 [Byte1]: 44
3411 11:52:44.839014
3412 11:52:44.839093 Set Vref, RX VrefLevel [Byte0]: 45
3413 11:52:44.842394 [Byte1]: 45
3414 11:52:44.846957
3415 11:52:44.847037 Set Vref, RX VrefLevel [Byte0]: 46
3416 11:52:44.850370 [Byte1]: 46
3417 11:52:44.855306
3418 11:52:44.855386 Set Vref, RX VrefLevel [Byte0]: 47
3419 11:52:44.858313 [Byte1]: 47
3420 11:52:44.862617
3421 11:52:44.862700 Set Vref, RX VrefLevel [Byte0]: 48
3422 11:52:44.865972 [Byte1]: 48
3423 11:52:44.870597
3424 11:52:44.870676 Set Vref, RX VrefLevel [Byte0]: 49
3425 11:52:44.874142 [Byte1]: 49
3426 11:52:44.878804
3427 11:52:44.878883 Set Vref, RX VrefLevel [Byte0]: 50
3428 11:52:44.882199 [Byte1]: 50
3429 11:52:44.886413
3430 11:52:44.886492 Set Vref, RX VrefLevel [Byte0]: 51
3431 11:52:44.889615 [Byte1]: 51
3432 11:52:44.894396
3433 11:52:44.894476 Set Vref, RX VrefLevel [Byte0]: 52
3434 11:52:44.897491 [Byte1]: 52
3435 11:52:44.902070
3436 11:52:44.902149 Set Vref, RX VrefLevel [Byte0]: 53
3437 11:52:44.905569 [Byte1]: 53
3438 11:52:44.910117
3439 11:52:44.910196 Set Vref, RX VrefLevel [Byte0]: 54
3440 11:52:44.913458 [Byte1]: 54
3441 11:52:44.918025
3442 11:52:44.918104 Set Vref, RX VrefLevel [Byte0]: 55
3443 11:52:44.921173 [Byte1]: 55
3444 11:52:44.925761
3445 11:52:44.925841 Set Vref, RX VrefLevel [Byte0]: 56
3446 11:52:44.929043 [Byte1]: 56
3447 11:52:44.933994
3448 11:52:44.934073 Set Vref, RX VrefLevel [Byte0]: 57
3449 11:52:44.936972 [Byte1]: 57
3450 11:52:44.941624
3451 11:52:44.941704 Set Vref, RX VrefLevel [Byte0]: 58
3452 11:52:44.945077 [Byte1]: 58
3453 11:52:44.949401
3454 11:52:44.949481 Set Vref, RX VrefLevel [Byte0]: 59
3455 11:52:44.952782 [Byte1]: 59
3456 11:52:44.957272
3457 11:52:44.957351 Set Vref, RX VrefLevel [Byte0]: 60
3458 11:52:44.960707 [Byte1]: 60
3459 11:52:44.965464
3460 11:52:44.965546 Set Vref, RX VrefLevel [Byte0]: 61
3461 11:52:44.968807 [Byte1]: 61
3462 11:52:44.973612
3463 11:52:44.973693 Set Vref, RX VrefLevel [Byte0]: 62
3464 11:52:44.976421 [Byte1]: 62
3465 11:52:44.981097
3466 11:52:44.981178 Set Vref, RX VrefLevel [Byte0]: 63
3467 11:52:44.987802 [Byte1]: 63
3468 11:52:44.987884
3469 11:52:44.991170 Set Vref, RX VrefLevel [Byte0]: 64
3470 11:52:44.994154 [Byte1]: 64
3471 11:52:44.994261
3472 11:52:44.997602 Set Vref, RX VrefLevel [Byte0]: 65
3473 11:52:45.000967 [Byte1]: 65
3474 11:52:45.004891
3475 11:52:45.004973 Set Vref, RX VrefLevel [Byte0]: 66
3476 11:52:45.007982 [Byte1]: 66
3477 11:52:45.012672
3478 11:52:45.012754 Set Vref, RX VrefLevel [Byte0]: 67
3479 11:52:45.016021 [Byte1]: 67
3480 11:52:45.020928
3481 11:52:45.021009 Set Vref, RX VrefLevel [Byte0]: 68
3482 11:52:45.023966 [Byte1]: 68
3483 11:52:45.028773
3484 11:52:45.028854 Final RX Vref Byte 0 = 51 to rank0
3485 11:52:45.031737 Final RX Vref Byte 1 = 55 to rank0
3486 11:52:45.035314 Final RX Vref Byte 0 = 51 to rank1
3487 11:52:45.038884 Final RX Vref Byte 1 = 55 to rank1==
3488 11:52:45.042173 Dram Type= 6, Freq= 0, CH_1, rank 0
3489 11:52:45.045248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 11:52:45.048689 ==
3491 11:52:45.048771 DQS Delay:
3492 11:52:45.048835 DQS0 = 0, DQS1 = 0
3493 11:52:45.052250 DQM Delay:
3494 11:52:45.052332 DQM0 = 119, DQM1 = 112
3495 11:52:45.055636 DQ Delay:
3496 11:52:45.058335 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3497 11:52:45.062059 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3498 11:52:45.065089 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3499 11:52:45.068651 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3500 11:52:45.068734
3501 11:52:45.068799
3502 11:52:45.075598 [DQSOSCAuto] RK0, (LSB)MR18= 0x418, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3503 11:52:45.079248 CH1 RK0: MR19=404, MR18=418
3504 11:52:45.085320 CH1_RK0: MR19=0x404, MR18=0x418, DQSOSC=400, MR23=63, INC=40, DEC=27
3505 11:52:45.085404
3506 11:52:45.088526 ----->DramcWriteLeveling(PI) begin...
3507 11:52:45.088611 ==
3508 11:52:45.091982 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 11:52:45.095245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 11:52:45.095330 ==
3511 11:52:45.098470 Write leveling (Byte 0): 26 => 26
3512 11:52:45.101950 Write leveling (Byte 1): 30 => 30
3513 11:52:45.105155 DramcWriteLeveling(PI) end<-----
3514 11:52:45.105239
3515 11:52:45.105305 ==
3516 11:52:45.108762 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 11:52:45.112445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 11:52:45.115420 ==
3519 11:52:45.115504 [Gating] SW mode calibration
3520 11:52:45.122234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3521 11:52:45.129013 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3522 11:52:45.132033 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 11:52:45.138828 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:52:45.142271 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:52:45.145711 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 11:52:45.152223 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 11:52:45.155467 0 15 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3528 11:52:45.158989 0 15 24 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 0)
3529 11:52:45.165724 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3530 11:52:45.168973 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:52:45.172140 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:52:45.175667 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:52:45.182231 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 11:52:45.185612 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 11:52:45.188751 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3536 11:52:45.195391 1 0 24 | B1->B0 | 4040 2e2e | 0 0 | (1 1) (0 0)
3537 11:52:45.198929 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:52:45.202244 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:52:45.208849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:52:45.211970 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:52:45.215458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:52:45.222505 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:52:45.225803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 11:52:45.229098 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3545 11:52:45.235656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:52:45.238830 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:52:45.242051 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:52:45.248532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:52:45.251753 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:52:45.255727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:52:45.261982 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:52:45.265179 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:52:45.268330 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:52:45.275240 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:52:45.278298 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:52:45.281503 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:52:45.288390 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:52:45.291541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:52:45.295000 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 11:52:45.301464 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3561 11:52:45.305017 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3562 11:52:45.308038 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 11:52:45.311462 Total UI for P1: 0, mck2ui 16
3564 11:52:45.315392 best dqsien dly found for B0: ( 1, 3, 26)
3565 11:52:45.317954 Total UI for P1: 0, mck2ui 16
3566 11:52:45.321429 best dqsien dly found for B1: ( 1, 3, 28)
3567 11:52:45.325091 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3568 11:52:45.328089 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3569 11:52:45.328172
3570 11:52:45.331511 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3571 11:52:45.338110 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3572 11:52:45.338194 [Gating] SW calibration Done
3573 11:52:45.338261 ==
3574 11:52:45.341458 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 11:52:45.347867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 11:52:45.347952 ==
3577 11:52:45.348018 RX Vref Scan: 0
3578 11:52:45.348079
3579 11:52:45.351082 RX Vref 0 -> 0, step: 1
3580 11:52:45.351165
3581 11:52:45.354888 RX Delay -40 -> 252, step: 8
3582 11:52:45.357926 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3583 11:52:45.361385 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3584 11:52:45.364929 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3585 11:52:45.371315 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3586 11:52:45.374357 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3587 11:52:45.378131 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3588 11:52:45.381224 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3589 11:52:45.384344 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3590 11:52:45.391261 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3591 11:52:45.394366 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3592 11:52:45.397698 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3593 11:52:45.401006 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3594 11:52:45.404423 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3595 11:52:45.411054 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3596 11:52:45.414480 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3597 11:52:45.417716 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3598 11:52:45.417800 ==
3599 11:52:45.421256 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:52:45.424829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:52:45.424916 ==
3602 11:52:45.427569 DQS Delay:
3603 11:52:45.427652 DQS0 = 0, DQS1 = 0
3604 11:52:45.430928 DQM Delay:
3605 11:52:45.431012 DQM0 = 120, DQM1 = 113
3606 11:52:45.431078 DQ Delay:
3607 11:52:45.437655 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3608 11:52:45.440951 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3609 11:52:45.444266 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3610 11:52:45.447604 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3611 11:52:45.447688
3612 11:52:45.447754
3613 11:52:45.447815 ==
3614 11:52:45.450956 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:52:45.454114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:52:45.454201 ==
3617 11:52:45.454267
3618 11:52:45.454331
3619 11:52:45.457533 TX Vref Scan disable
3620 11:52:45.461245 == TX Byte 0 ==
3621 11:52:45.464199 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 11:52:45.467718 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 11:52:45.470728 == TX Byte 1 ==
3624 11:52:45.474566 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3625 11:52:45.477774 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3626 11:52:45.477858 ==
3627 11:52:45.480694 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 11:52:45.484416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 11:52:45.487554 ==
3630 11:52:45.497970 TX Vref=22, minBit 1, minWin=25, winSum=418
3631 11:52:45.500886 TX Vref=24, minBit 1, minWin=25, winSum=424
3632 11:52:45.504442 TX Vref=26, minBit 1, minWin=26, winSum=426
3633 11:52:45.507929 TX Vref=28, minBit 3, minWin=26, winSum=429
3634 11:52:45.511460 TX Vref=30, minBit 9, minWin=26, winSum=432
3635 11:52:45.514371 TX Vref=32, minBit 1, minWin=26, winSum=432
3636 11:52:45.520951 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3637 11:52:45.521035
3638 11:52:45.524324 Final TX Range 1 Vref 30
3639 11:52:45.524408
3640 11:52:45.524474 ==
3641 11:52:45.527675 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 11:52:45.530922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 11:52:45.531032 ==
3644 11:52:45.531127
3645 11:52:45.534421
3646 11:52:45.534518 TX Vref Scan disable
3647 11:52:45.537836 == TX Byte 0 ==
3648 11:52:45.541114 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3649 11:52:45.544107 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3650 11:52:45.547661 == TX Byte 1 ==
3651 11:52:45.550763 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3652 11:52:45.554182 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3653 11:52:45.557371
3654 11:52:45.557472 [DATLAT]
3655 11:52:45.557542 Freq=1200, CH1 RK1
3656 11:52:45.557638
3657 11:52:45.561077 DATLAT Default: 0xd
3658 11:52:45.561178 0, 0xFFFF, sum = 0
3659 11:52:45.564045 1, 0xFFFF, sum = 0
3660 11:52:45.564146 2, 0xFFFF, sum = 0
3661 11:52:45.567467 3, 0xFFFF, sum = 0
3662 11:52:45.567541 4, 0xFFFF, sum = 0
3663 11:52:45.570724 5, 0xFFFF, sum = 0
3664 11:52:45.574082 6, 0xFFFF, sum = 0
3665 11:52:45.574191 7, 0xFFFF, sum = 0
3666 11:52:45.577316 8, 0xFFFF, sum = 0
3667 11:52:45.577430 9, 0xFFFF, sum = 0
3668 11:52:45.580773 10, 0xFFFF, sum = 0
3669 11:52:45.580847 11, 0xFFFF, sum = 0
3670 11:52:45.584207 12, 0x0, sum = 1
3671 11:52:45.584310 13, 0x0, sum = 2
3672 11:52:45.587508 14, 0x0, sum = 3
3673 11:52:45.587585 15, 0x0, sum = 4
3674 11:52:45.587654 best_step = 13
3675 11:52:45.587743
3676 11:52:45.591088 ==
3677 11:52:45.594301 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 11:52:45.597509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 11:52:45.597586 ==
3680 11:52:45.597652 RX Vref Scan: 0
3681 11:52:45.597713
3682 11:52:45.600981 RX Vref 0 -> 0, step: 1
3683 11:52:45.601081
3684 11:52:45.604060 RX Delay -13 -> 252, step: 4
3685 11:52:45.607511 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3686 11:52:45.614069 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3687 11:52:45.617338 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3688 11:52:45.620917 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3689 11:52:45.624519 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3690 11:52:45.627775 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3691 11:52:45.631045 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3692 11:52:45.637712 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3693 11:52:45.640627 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3694 11:52:45.644274 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3695 11:52:45.647217 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3696 11:52:45.651114 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3697 11:52:45.657664 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3698 11:52:45.660663 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3699 11:52:45.664255 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3700 11:52:45.667167 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3701 11:52:45.667242 ==
3702 11:52:45.670957 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 11:52:45.677449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 11:52:45.677527 ==
3705 11:52:45.677592 DQS Delay:
3706 11:52:45.681102 DQS0 = 0, DQS1 = 0
3707 11:52:45.681170 DQM Delay:
3708 11:52:45.684044 DQM0 = 119, DQM1 = 113
3709 11:52:45.684138 DQ Delay:
3710 11:52:45.687535 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3711 11:52:45.690642 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3712 11:52:45.693606 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3713 11:52:45.697545 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3714 11:52:45.697639
3715 11:52:45.697727
3716 11:52:45.707085 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3717 11:52:45.707190 CH1 RK1: MR19=403, MR18=7EC
3718 11:52:45.713666 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3719 11:52:45.717080 [RxdqsGatingPostProcess] freq 1200
3720 11:52:45.723605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3721 11:52:45.726862 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 11:52:45.730567 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 11:52:45.733699 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 11:52:45.737067 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 11:52:45.737170 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 11:52:45.740604 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 11:52:45.744064 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 11:52:45.747148 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 11:52:45.750351 Pre-setting of DQS Precalculation
3730 11:52:45.757144 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3731 11:52:45.763581 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3732 11:52:45.770330 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3733 11:52:45.770458
3734 11:52:45.770524
3735 11:52:45.774784 [Calibration Summary] 2400 Mbps
3736 11:52:45.774853 CH 0, Rank 0
3737 11:52:45.776949 SW Impedance : PASS
3738 11:52:45.780592 DUTY Scan : NO K
3739 11:52:45.780692 ZQ Calibration : PASS
3740 11:52:45.784013 Jitter Meter : NO K
3741 11:52:45.786833 CBT Training : PASS
3742 11:52:45.786903 Write leveling : PASS
3743 11:52:45.790354 RX DQS gating : PASS
3744 11:52:45.793706 RX DQ/DQS(RDDQC) : PASS
3745 11:52:45.793800 TX DQ/DQS : PASS
3746 11:52:45.796725 RX DATLAT : PASS
3747 11:52:45.800039 RX DQ/DQS(Engine): PASS
3748 11:52:45.800127 TX OE : NO K
3749 11:52:45.803461 All Pass.
3750 11:52:45.803558
3751 11:52:45.803648 CH 0, Rank 1
3752 11:52:45.806936 SW Impedance : PASS
3753 11:52:45.807008 DUTY Scan : NO K
3754 11:52:45.810088 ZQ Calibration : PASS
3755 11:52:45.813411 Jitter Meter : NO K
3756 11:52:45.813485 CBT Training : PASS
3757 11:52:45.816632 Write leveling : PASS
3758 11:52:45.816728 RX DQS gating : PASS
3759 11:52:45.820140 RX DQ/DQS(RDDQC) : PASS
3760 11:52:45.823714 TX DQ/DQS : PASS
3761 11:52:45.823790 RX DATLAT : PASS
3762 11:52:45.827010 RX DQ/DQS(Engine): PASS
3763 11:52:45.830343 TX OE : NO K
3764 11:52:45.830477 All Pass.
3765 11:52:45.830569
3766 11:52:45.830662 CH 1, Rank 0
3767 11:52:45.833367 SW Impedance : PASS
3768 11:52:45.836548 DUTY Scan : NO K
3769 11:52:45.836621 ZQ Calibration : PASS
3770 11:52:45.839821 Jitter Meter : NO K
3771 11:52:45.843492 CBT Training : PASS
3772 11:52:45.843594 Write leveling : PASS
3773 11:52:45.846630 RX DQS gating : PASS
3774 11:52:45.849803 RX DQ/DQS(RDDQC) : PASS
3775 11:52:45.849902 TX DQ/DQS : PASS
3776 11:52:45.853502 RX DATLAT : PASS
3777 11:52:45.856872 RX DQ/DQS(Engine): PASS
3778 11:52:45.856969 TX OE : NO K
3779 11:52:45.857063 All Pass.
3780 11:52:45.859716
3781 11:52:45.859816 CH 1, Rank 1
3782 11:52:45.863205 SW Impedance : PASS
3783 11:52:45.863302 DUTY Scan : NO K
3784 11:52:45.866657 ZQ Calibration : PASS
3785 11:52:45.866756 Jitter Meter : NO K
3786 11:52:45.870249 CBT Training : PASS
3787 11:52:45.873344 Write leveling : PASS
3788 11:52:45.873441 RX DQS gating : PASS
3789 11:52:45.876494 RX DQ/DQS(RDDQC) : PASS
3790 11:52:45.879771 TX DQ/DQS : PASS
3791 11:52:45.879841 RX DATLAT : PASS
3792 11:52:45.883240 RX DQ/DQS(Engine): PASS
3793 11:52:45.887128 TX OE : NO K
3794 11:52:45.887202 All Pass.
3795 11:52:45.887266
3796 11:52:45.889993 DramC Write-DBI off
3797 11:52:45.890087 PER_BANK_REFRESH: Hybrid Mode
3798 11:52:45.893451 TX_TRACKING: ON
3799 11:52:45.899888 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3800 11:52:45.906292 [FAST_K] Save calibration result to emmc
3801 11:52:45.909883 dramc_set_vcore_voltage set vcore to 650000
3802 11:52:45.909983 Read voltage for 600, 5
3803 11:52:45.913324 Vio18 = 0
3804 11:52:45.913421 Vcore = 650000
3805 11:52:45.913513 Vdram = 0
3806 11:52:45.916541 Vddq = 0
3807 11:52:45.916642 Vmddr = 0
3808 11:52:45.919577 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3809 11:52:45.926601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3810 11:52:45.929781 MEM_TYPE=3, freq_sel=19
3811 11:52:45.932860 sv_algorithm_assistance_LP4_1600
3812 11:52:45.936281 ============ PULL DRAM RESETB DOWN ============
3813 11:52:45.939468 ========== PULL DRAM RESETB DOWN end =========
3814 11:52:45.943082 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3815 11:52:45.946555 ===================================
3816 11:52:45.949780 LPDDR4 DRAM CONFIGURATION
3817 11:52:45.952971 ===================================
3818 11:52:45.956548 EX_ROW_EN[0] = 0x0
3819 11:52:45.956618 EX_ROW_EN[1] = 0x0
3820 11:52:45.959740 LP4Y_EN = 0x0
3821 11:52:45.959813 WORK_FSP = 0x0
3822 11:52:45.962961 WL = 0x2
3823 11:52:45.963035 RL = 0x2
3824 11:52:45.966096 BL = 0x2
3825 11:52:45.969768 RPST = 0x0
3826 11:52:45.969863 RD_PRE = 0x0
3827 11:52:45.973027 WR_PRE = 0x1
3828 11:52:45.973099 WR_PST = 0x0
3829 11:52:45.976177 DBI_WR = 0x0
3830 11:52:45.976277 DBI_RD = 0x0
3831 11:52:45.979908 OTF = 0x1
3832 11:52:45.982976 ===================================
3833 11:52:45.986317 ===================================
3834 11:52:45.986409 ANA top config
3835 11:52:45.989408 ===================================
3836 11:52:45.992880 DLL_ASYNC_EN = 0
3837 11:52:45.996320 ALL_SLAVE_EN = 1
3838 11:52:45.996390 NEW_RANK_MODE = 1
3839 11:52:45.999917 DLL_IDLE_MODE = 1
3840 11:52:46.002693 LP45_APHY_COMB_EN = 1
3841 11:52:46.005975 TX_ODT_DIS = 1
3842 11:52:46.006073 NEW_8X_MODE = 1
3843 11:52:46.009578 ===================================
3844 11:52:46.012592 ===================================
3845 11:52:46.016149 data_rate = 1200
3846 11:52:46.019802 CKR = 1
3847 11:52:46.022781 DQ_P2S_RATIO = 8
3848 11:52:46.026141 ===================================
3849 11:52:46.029460 CA_P2S_RATIO = 8
3850 11:52:46.032581 DQ_CA_OPEN = 0
3851 11:52:46.032655 DQ_SEMI_OPEN = 0
3852 11:52:46.036151 CA_SEMI_OPEN = 0
3853 11:52:46.039464 CA_FULL_RATE = 0
3854 11:52:46.042844 DQ_CKDIV4_EN = 1
3855 11:52:46.045969 CA_CKDIV4_EN = 1
3856 11:52:46.049590 CA_PREDIV_EN = 0
3857 11:52:46.049670 PH8_DLY = 0
3858 11:52:46.052643 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3859 11:52:46.055906 DQ_AAMCK_DIV = 4
3860 11:52:46.059830 CA_AAMCK_DIV = 4
3861 11:52:46.062865 CA_ADMCK_DIV = 4
3862 11:52:46.066206 DQ_TRACK_CA_EN = 0
3863 11:52:46.066278 CA_PICK = 600
3864 11:52:46.069270 CA_MCKIO = 600
3865 11:52:46.072638 MCKIO_SEMI = 0
3866 11:52:46.075901 PLL_FREQ = 2288
3867 11:52:46.079712 DQ_UI_PI_RATIO = 32
3868 11:52:46.082890 CA_UI_PI_RATIO = 0
3869 11:52:46.086206 ===================================
3870 11:52:46.089341 ===================================
3871 11:52:46.089437 memory_type:LPDDR4
3872 11:52:46.092767 GP_NUM : 10
3873 11:52:46.096387 SRAM_EN : 1
3874 11:52:46.096458 MD32_EN : 0
3875 11:52:46.099441 ===================================
3876 11:52:46.102724 [ANA_INIT] >>>>>>>>>>>>>>
3877 11:52:46.106399 <<<<<< [CONFIGURE PHASE]: ANA_TX
3878 11:52:46.109246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3879 11:52:46.113044 ===================================
3880 11:52:46.116120 data_rate = 1200,PCW = 0X5800
3881 11:52:46.119305 ===================================
3882 11:52:46.122802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3883 11:52:46.126006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 11:52:46.132545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3885 11:52:46.135820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3886 11:52:46.139239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3887 11:52:46.142539 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3888 11:52:46.146211 [ANA_INIT] flow start
3889 11:52:46.149040 [ANA_INIT] PLL >>>>>>>>
3890 11:52:46.149144 [ANA_INIT] PLL <<<<<<<<
3891 11:52:46.152737 [ANA_INIT] MIDPI >>>>>>>>
3892 11:52:46.156010 [ANA_INIT] MIDPI <<<<<<<<
3893 11:52:46.159120 [ANA_INIT] DLL >>>>>>>>
3894 11:52:46.159192 [ANA_INIT] flow end
3895 11:52:46.162486 ============ LP4 DIFF to SE enter ============
3896 11:52:46.169264 ============ LP4 DIFF to SE exit ============
3897 11:52:46.169378 [ANA_INIT] <<<<<<<<<<<<<
3898 11:52:46.172437 [Flow] Enable top DCM control >>>>>
3899 11:52:46.175809 [Flow] Enable top DCM control <<<<<
3900 11:52:46.179207 Enable DLL master slave shuffle
3901 11:52:46.185939 ==============================================================
3902 11:52:46.186022 Gating Mode config
3903 11:52:46.192205 ==============================================================
3904 11:52:46.195586 Config description:
3905 11:52:46.202563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3906 11:52:46.208856 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3907 11:52:46.215700 SELPH_MODE 0: By rank 1: By Phase
3908 11:52:46.222380 ==============================================================
3909 11:52:46.222498 GAT_TRACK_EN = 1
3910 11:52:46.225608 RX_GATING_MODE = 2
3911 11:52:46.229284 RX_GATING_TRACK_MODE = 2
3912 11:52:46.232348 SELPH_MODE = 1
3913 11:52:46.235702 PICG_EARLY_EN = 1
3914 11:52:46.238988 VALID_LAT_VALUE = 1
3915 11:52:46.245818 ==============================================================
3916 11:52:46.248780 Enter into Gating configuration >>>>
3917 11:52:46.252339 Exit from Gating configuration <<<<
3918 11:52:46.255537 Enter into DVFS_PRE_config >>>>>
3919 11:52:46.265445 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3920 11:52:46.268742 Exit from DVFS_PRE_config <<<<<
3921 11:52:46.272038 Enter into PICG configuration >>>>
3922 11:52:46.276058 Exit from PICG configuration <<<<
3923 11:52:46.278759 [RX_INPUT] configuration >>>>>
3924 11:52:46.278842 [RX_INPUT] configuration <<<<<
3925 11:52:46.285264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3926 11:52:46.291935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3927 11:52:46.295540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 11:52:46.302089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 11:52:46.309079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 11:52:46.315394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 11:52:46.318824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3932 11:52:46.322347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3933 11:52:46.328483 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3934 11:52:46.331817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3935 11:52:46.335132 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3936 11:52:46.341879 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 11:52:46.345304 ===================================
3938 11:52:46.345399 LPDDR4 DRAM CONFIGURATION
3939 11:52:46.348825 ===================================
3940 11:52:46.352015 EX_ROW_EN[0] = 0x0
3941 11:52:46.352099 EX_ROW_EN[1] = 0x0
3942 11:52:46.355580 LP4Y_EN = 0x0
3943 11:52:46.355664 WORK_FSP = 0x0
3944 11:52:46.358665 WL = 0x2
3945 11:52:46.361919 RL = 0x2
3946 11:52:46.362003 BL = 0x2
3947 11:52:46.365348 RPST = 0x0
3948 11:52:46.365439 RD_PRE = 0x0
3949 11:52:46.368562 WR_PRE = 0x1
3950 11:52:46.368646 WR_PST = 0x0
3951 11:52:46.371516 DBI_WR = 0x0
3952 11:52:46.371600 DBI_RD = 0x0
3953 11:52:46.374905 OTF = 0x1
3954 11:52:46.378060 ===================================
3955 11:52:46.381786 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3956 11:52:46.384888 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3957 11:52:46.391648 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3958 11:52:46.394980 ===================================
3959 11:52:46.395104 LPDDR4 DRAM CONFIGURATION
3960 11:52:46.397954 ===================================
3961 11:52:46.401438 EX_ROW_EN[0] = 0x10
3962 11:52:46.401524 EX_ROW_EN[1] = 0x0
3963 11:52:46.404665 LP4Y_EN = 0x0
3964 11:52:46.408209 WORK_FSP = 0x0
3965 11:52:46.408293 WL = 0x2
3966 11:52:46.411441 RL = 0x2
3967 11:52:46.411529 BL = 0x2
3968 11:52:46.414602 RPST = 0x0
3969 11:52:46.414686 RD_PRE = 0x0
3970 11:52:46.418230 WR_PRE = 0x1
3971 11:52:46.418339 WR_PST = 0x0
3972 11:52:46.421579 DBI_WR = 0x0
3973 11:52:46.421662 DBI_RD = 0x0
3974 11:52:46.424838 OTF = 0x1
3975 11:52:46.428084 ===================================
3976 11:52:46.434935 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3977 11:52:46.437856 nWR fixed to 30
3978 11:52:46.437940 [ModeRegInit_LP4] CH0 RK0
3979 11:52:46.441542 [ModeRegInit_LP4] CH0 RK1
3980 11:52:46.444322 [ModeRegInit_LP4] CH1 RK0
3981 11:52:46.444406 [ModeRegInit_LP4] CH1 RK1
3982 11:52:46.447756 match AC timing 17
3983 11:52:46.451173 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3984 11:52:46.454529 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3985 11:52:46.461158 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3986 11:52:46.464495 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3987 11:52:46.470861 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3988 11:52:46.470947 ==
3989 11:52:46.474680 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 11:52:46.477719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 11:52:46.477805 ==
3992 11:52:46.484368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 11:52:46.490997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3994 11:52:46.494099 [CA 0] Center 36 (5~67) winsize 63
3995 11:52:46.497423 [CA 1] Center 36 (6~67) winsize 62
3996 11:52:46.500920 [CA 2] Center 34 (4~65) winsize 62
3997 11:52:46.504136 [CA 3] Center 34 (3~65) winsize 63
3998 11:52:46.507439 [CA 4] Center 33 (3~64) winsize 62
3999 11:52:46.507523 [CA 5] Center 33 (2~64) winsize 63
4000 11:52:46.511021
4001 11:52:46.514052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4002 11:52:46.514156
4003 11:52:46.517285 [CATrainingPosCal] consider 1 rank data
4004 11:52:46.521183 u2DelayCellTimex100 = 270/100 ps
4005 11:52:46.524247 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4006 11:52:46.527261 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4007 11:52:46.530826 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4008 11:52:46.533793 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4009 11:52:46.537394 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 11:52:46.540701 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4011 11:52:46.540786
4012 11:52:46.544030 CA PerBit enable=1, Macro0, CA PI delay=33
4013 11:52:46.547665
4014 11:52:46.547759 [CBTSetCACLKResult] CA Dly = 33
4015 11:52:46.550766 CS Dly: 4 (0~35)
4016 11:52:46.550857 ==
4017 11:52:46.553823 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 11:52:46.557088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:52:46.557177 ==
4020 11:52:46.564177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4021 11:52:46.570554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4022 11:52:46.573727 [CA 0] Center 36 (6~67) winsize 62
4023 11:52:46.576815 [CA 1] Center 36 (6~67) winsize 62
4024 11:52:46.580368 [CA 2] Center 35 (5~66) winsize 62
4025 11:52:46.583746 [CA 3] Center 35 (4~66) winsize 63
4026 11:52:46.587275 [CA 4] Center 34 (3~65) winsize 63
4027 11:52:46.590114 [CA 5] Center 33 (3~64) winsize 62
4028 11:52:46.590198
4029 11:52:46.593724 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4030 11:52:46.593806
4031 11:52:46.596761 [CATrainingPosCal] consider 2 rank data
4032 11:52:46.600491 u2DelayCellTimex100 = 270/100 ps
4033 11:52:46.603466 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4034 11:52:46.607275 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4035 11:52:46.610167 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4036 11:52:46.613939 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4037 11:52:46.617078 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 11:52:46.620232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4039 11:52:46.623411
4040 11:52:46.626778 CA PerBit enable=1, Macro0, CA PI delay=33
4041 11:52:46.626861
4042 11:52:46.630324 [CBTSetCACLKResult] CA Dly = 33
4043 11:52:46.630413 CS Dly: 5 (0~37)
4044 11:52:46.630480
4045 11:52:46.633469 ----->DramcWriteLeveling(PI) begin...
4046 11:52:46.633554 ==
4047 11:52:46.636781 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 11:52:46.640354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 11:52:46.643614 ==
4050 11:52:46.643696 Write leveling (Byte 0): 35 => 35
4051 11:52:46.646871 Write leveling (Byte 1): 31 => 31
4052 11:52:46.650442 DramcWriteLeveling(PI) end<-----
4053 11:52:46.650525
4054 11:52:46.650589 ==
4055 11:52:46.653423 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 11:52:46.660261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 11:52:46.660344 ==
4058 11:52:46.660410 [Gating] SW mode calibration
4059 11:52:46.670299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4060 11:52:46.673207 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4061 11:52:46.676538 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 11:52:46.683195 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 11:52:46.686455 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 11:52:46.690024 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
4065 11:52:46.696583 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4066 11:52:46.699856 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:52:46.703118 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:52:46.709862 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:52:46.713208 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 11:52:46.717066 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 11:52:46.723211 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 11:52:46.727002 0 10 12 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
4073 11:52:46.729702 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4074 11:52:46.736552 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:52:46.740003 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:52:46.743275 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:52:46.749725 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:52:46.753126 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 11:52:46.756362 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 11:52:46.763272 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4081 11:52:46.766345 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4082 11:52:46.769850 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:52:46.776426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:52:46.780034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:52:46.782970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:52:46.789703 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:52:46.793102 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:52:46.796251 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:52:46.799576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:52:46.806418 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:52:46.810248 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:52:46.813390 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:52:46.819856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:52:46.823343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:52:46.826611 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 11:52:46.833270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4097 11:52:46.836311 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4098 11:52:46.839908 Total UI for P1: 0, mck2ui 16
4099 11:52:46.843378 best dqsien dly found for B0: ( 0, 13, 12)
4100 11:52:46.846839 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 11:52:46.849760 Total UI for P1: 0, mck2ui 16
4102 11:52:46.852894 best dqsien dly found for B1: ( 0, 13, 14)
4103 11:52:46.856170 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4104 11:52:46.859859 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4105 11:52:46.859942
4106 11:52:46.866687 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4107 11:52:46.870088 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4108 11:52:46.870172 [Gating] SW calibration Done
4109 11:52:46.872682 ==
4110 11:52:46.876480 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 11:52:46.879884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 11:52:46.879968 ==
4113 11:52:46.880035 RX Vref Scan: 0
4114 11:52:46.880097
4115 11:52:46.882837 RX Vref 0 -> 0, step: 1
4116 11:52:46.882920
4117 11:52:46.886223 RX Delay -230 -> 252, step: 16
4118 11:52:46.889537 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4119 11:52:46.892952 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4120 11:52:46.899803 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4121 11:52:46.902988 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4122 11:52:46.906513 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4123 11:52:46.909371 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4124 11:52:46.913104 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4125 11:52:46.919766 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4126 11:52:46.923029 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4127 11:52:46.926170 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4128 11:52:46.929815 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4129 11:52:46.936153 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4130 11:52:46.939504 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4131 11:52:46.942586 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4132 11:52:46.945941 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4133 11:52:46.952769 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4134 11:52:46.952851 ==
4135 11:52:46.956074 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:52:46.959340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:52:46.959440 ==
4138 11:52:46.959533 DQS Delay:
4139 11:52:46.962814 DQS0 = 0, DQS1 = 0
4140 11:52:46.962886 DQM Delay:
4141 11:52:46.966020 DQM0 = 50, DQM1 = 39
4142 11:52:46.966098 DQ Delay:
4143 11:52:46.969350 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4144 11:52:46.972694 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4145 11:52:46.976147 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4146 11:52:46.979198 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4147 11:52:46.979269
4148 11:52:46.979330
4149 11:52:46.979389 ==
4150 11:52:46.983018 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 11:52:46.986099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:52:46.986176 ==
4153 11:52:46.986243
4154 11:52:46.986303
4155 11:52:46.989268 TX Vref Scan disable
4156 11:52:46.992769 == TX Byte 0 ==
4157 11:52:46.996003 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4158 11:52:46.999422 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4159 11:52:47.003130 == TX Byte 1 ==
4160 11:52:47.006320 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4161 11:52:47.009480 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4162 11:52:47.009576 ==
4163 11:52:47.013044 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 11:52:47.019557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:52:47.019630 ==
4166 11:52:47.019693
4167 11:52:47.019750
4168 11:52:47.019813 TX Vref Scan disable
4169 11:52:47.023894 == TX Byte 0 ==
4170 11:52:47.026819 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4171 11:52:47.033504 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4172 11:52:47.033580 == TX Byte 1 ==
4173 11:52:47.037232 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4174 11:52:47.043553 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4175 11:52:47.043652
4176 11:52:47.043732 [DATLAT]
4177 11:52:47.043793 Freq=600, CH0 RK0
4178 11:52:47.043852
4179 11:52:47.046878 DATLAT Default: 0x9
4180 11:52:47.046962 0, 0xFFFF, sum = 0
4181 11:52:47.050330 1, 0xFFFF, sum = 0
4182 11:52:47.050434 2, 0xFFFF, sum = 0
4183 11:52:47.053989 3, 0xFFFF, sum = 0
4184 11:52:47.054073 4, 0xFFFF, sum = 0
4185 11:52:47.056786 5, 0xFFFF, sum = 0
4186 11:52:47.060367 6, 0xFFFF, sum = 0
4187 11:52:47.060451 7, 0xFFFF, sum = 0
4188 11:52:47.063879 8, 0x0, sum = 1
4189 11:52:47.063963 9, 0x0, sum = 2
4190 11:52:47.064030 10, 0x0, sum = 3
4191 11:52:47.066929 11, 0x0, sum = 4
4192 11:52:47.067013 best_step = 9
4193 11:52:47.067078
4194 11:52:47.067138 ==
4195 11:52:47.070204 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 11:52:47.076875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 11:52:47.076958 ==
4198 11:52:47.077024 RX Vref Scan: 1
4199 11:52:47.077085
4200 11:52:47.080316 RX Vref 0 -> 0, step: 1
4201 11:52:47.080398
4202 11:52:47.083458 RX Delay -179 -> 252, step: 8
4203 11:52:47.083540
4204 11:52:47.087097 Set Vref, RX VrefLevel [Byte0]: 57
4205 11:52:47.089884 [Byte1]: 48
4206 11:52:47.089967
4207 11:52:47.093399 Final RX Vref Byte 0 = 57 to rank0
4208 11:52:47.096809 Final RX Vref Byte 1 = 48 to rank0
4209 11:52:47.100248 Final RX Vref Byte 0 = 57 to rank1
4210 11:52:47.103282 Final RX Vref Byte 1 = 48 to rank1==
4211 11:52:47.106826 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 11:52:47.110663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 11:52:47.110745 ==
4214 11:52:47.113801 DQS Delay:
4215 11:52:47.113883 DQS0 = 0, DQS1 = 0
4216 11:52:47.113948 DQM Delay:
4217 11:52:47.116863 DQM0 = 48, DQM1 = 39
4218 11:52:47.116946 DQ Delay:
4219 11:52:47.119972 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4220 11:52:47.123800 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4221 11:52:47.126649 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4222 11:52:47.130259 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4223 11:52:47.130341
4224 11:52:47.130441
4225 11:52:47.139929 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4226 11:52:47.143385 CH0 RK0: MR19=808, MR18=5C56
4227 11:52:47.146627 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4228 11:52:47.146710
4229 11:52:47.149958 ----->DramcWriteLeveling(PI) begin...
4230 11:52:47.153155 ==
4231 11:52:47.156792 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 11:52:47.160040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 11:52:47.160123 ==
4234 11:52:47.163247 Write leveling (Byte 0): 33 => 33
4235 11:52:47.166873 Write leveling (Byte 1): 32 => 32
4236 11:52:47.169871 DramcWriteLeveling(PI) end<-----
4237 11:52:47.169953
4238 11:52:47.170017 ==
4239 11:52:47.173112 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 11:52:47.176637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 11:52:47.176720 ==
4242 11:52:47.180320 [Gating] SW mode calibration
4243 11:52:47.186482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4244 11:52:47.193150 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4245 11:52:47.196649 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 11:52:47.199680 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 11:52:47.203393 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4248 11:52:47.209805 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 0)
4249 11:52:47.213131 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4250 11:52:47.216716 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:52:47.223057 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:52:47.226408 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:52:47.229879 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 11:52:47.236358 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 11:52:47.239603 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 11:52:47.243237 0 10 12 | B1->B0 | 3131 3535 | 0 0 | (0 0) (0 0)
4257 11:52:47.249844 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4258 11:52:47.253062 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:52:47.256649 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:52:47.262952 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:52:47.266294 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 11:52:47.270123 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 11:52:47.276266 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 11:52:47.279490 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4265 11:52:47.282738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:52:47.289785 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:52:47.292715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:52:47.296014 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:52:47.302594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:52:47.306193 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:52:47.309144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:52:47.315900 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:52:47.319412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:52:47.322380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:52:47.329466 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:52:47.332585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:52:47.335803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 11:52:47.342571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:52:47.345530 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 11:52:47.349541 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 11:52:47.355710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 11:52:47.355792 Total UI for P1: 0, mck2ui 16
4283 11:52:47.359348 best dqsien dly found for B0: ( 0, 13, 14)
4284 11:52:47.362235 Total UI for P1: 0, mck2ui 16
4285 11:52:47.365918 best dqsien dly found for B1: ( 0, 13, 14)
4286 11:52:47.368930 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4287 11:52:47.375516 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4288 11:52:47.375598
4289 11:52:47.379391 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4290 11:52:47.382403 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4291 11:52:47.386010 [Gating] SW calibration Done
4292 11:52:47.386091 ==
4293 11:52:47.389155 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 11:52:47.392373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 11:52:47.392456 ==
4296 11:52:47.395510 RX Vref Scan: 0
4297 11:52:47.395592
4298 11:52:47.395656 RX Vref 0 -> 0, step: 1
4299 11:52:47.395717
4300 11:52:47.399243 RX Delay -230 -> 252, step: 16
4301 11:52:47.402254 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4302 11:52:47.409041 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4303 11:52:47.412109 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4304 11:52:47.415688 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4305 11:52:47.419154 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4306 11:52:47.422240 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4307 11:52:47.429431 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4308 11:52:47.432327 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4309 11:52:47.435554 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4310 11:52:47.439051 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4311 11:52:47.445668 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4312 11:52:47.448952 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4313 11:52:47.452188 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4314 11:52:47.455607 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4315 11:52:47.462264 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4316 11:52:47.465537 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4317 11:52:47.465620 ==
4318 11:52:47.468929 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 11:52:47.472000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 11:52:47.472084 ==
4321 11:52:47.472149 DQS Delay:
4322 11:52:47.475710 DQS0 = 0, DQS1 = 0
4323 11:52:47.475793 DQM Delay:
4324 11:52:47.479355 DQM0 = 48, DQM1 = 42
4325 11:52:47.479438 DQ Delay:
4326 11:52:47.482058 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4327 11:52:47.485207 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4328 11:52:47.488707 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4329 11:52:47.492309 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4330 11:52:47.492391
4331 11:52:47.492456
4332 11:52:47.492516 ==
4333 11:52:47.495301 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 11:52:47.498604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 11:52:47.502270 ==
4336 11:52:47.502352
4337 11:52:47.502453
4338 11:52:47.502513 TX Vref Scan disable
4339 11:52:47.505255 == TX Byte 0 ==
4340 11:52:47.508944 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4341 11:52:47.511941 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4342 11:52:47.515678 == TX Byte 1 ==
4343 11:52:47.518892 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4344 11:52:47.525327 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4345 11:52:47.525434 ==
4346 11:52:47.528771 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 11:52:47.531692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:52:47.531791 ==
4349 11:52:47.531889
4350 11:52:47.531977
4351 11:52:47.534995 TX Vref Scan disable
4352 11:52:47.535070 == TX Byte 0 ==
4353 11:52:47.541803 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4354 11:52:47.545456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4355 11:52:47.548708 == TX Byte 1 ==
4356 11:52:47.551652 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4357 11:52:47.554962 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4358 11:52:47.555044
4359 11:52:47.555109 [DATLAT]
4360 11:52:47.558348 Freq=600, CH0 RK1
4361 11:52:47.558466
4362 11:52:47.558530 DATLAT Default: 0x9
4363 11:52:47.561992 0, 0xFFFF, sum = 0
4364 11:52:47.562075 1, 0xFFFF, sum = 0
4365 11:52:47.565120 2, 0xFFFF, sum = 0
4366 11:52:47.568198 3, 0xFFFF, sum = 0
4367 11:52:47.568280 4, 0xFFFF, sum = 0
4368 11:52:47.571841 5, 0xFFFF, sum = 0
4369 11:52:47.571925 6, 0xFFFF, sum = 0
4370 11:52:47.574893 7, 0xFFFF, sum = 0
4371 11:52:47.574975 8, 0x0, sum = 1
4372 11:52:47.575040 9, 0x0, sum = 2
4373 11:52:47.578343 10, 0x0, sum = 3
4374 11:52:47.578463 11, 0x0, sum = 4
4375 11:52:47.581691 best_step = 9
4376 11:52:47.581771
4377 11:52:47.581838 ==
4378 11:52:47.584764 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 11:52:47.588830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 11:52:47.588911 ==
4381 11:52:47.591407 RX Vref Scan: 0
4382 11:52:47.591488
4383 11:52:47.591552 RX Vref 0 -> 0, step: 1
4384 11:52:47.591611
4385 11:52:47.594902 RX Delay -179 -> 252, step: 8
4386 11:52:47.602365 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4387 11:52:47.605662 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4388 11:52:47.608951 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4389 11:52:47.612160 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4390 11:52:47.615568 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4391 11:52:47.622550 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4392 11:52:47.626279 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4393 11:52:47.628829 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4394 11:52:47.632323 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4395 11:52:47.635507 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4396 11:52:47.642234 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4397 11:52:47.645784 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4398 11:52:47.649103 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4399 11:52:47.651984 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4400 11:52:47.659142 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4401 11:52:47.662592 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4402 11:52:47.662674 ==
4403 11:52:47.665445 Dram Type= 6, Freq= 0, CH_0, rank 1
4404 11:52:47.669123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:52:47.669205 ==
4406 11:52:47.672013 DQS Delay:
4407 11:52:47.672095 DQS0 = 0, DQS1 = 0
4408 11:52:47.672158 DQM Delay:
4409 11:52:47.675316 DQM0 = 47, DQM1 = 39
4410 11:52:47.675397 DQ Delay:
4411 11:52:47.679106 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4412 11:52:47.682288 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4413 11:52:47.685377 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4414 11:52:47.688638 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4415 11:52:47.688722
4416 11:52:47.688787
4417 11:52:47.698694 [DQSOSCAuto] RK1, (LSB)MR18= 0x6937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4418 11:52:47.698779 CH0 RK1: MR19=808, MR18=6937
4419 11:52:47.705775 CH0_RK1: MR19=0x808, MR18=0x6937, DQSOSC=390, MR23=63, INC=172, DEC=114
4420 11:52:47.708920 [RxdqsGatingPostProcess] freq 600
4421 11:52:47.715555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4422 11:52:47.718765 Pre-setting of DQS Precalculation
4423 11:52:47.722320 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4424 11:52:47.722442 ==
4425 11:52:47.725454 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 11:52:47.729017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 11:52:47.731956 ==
4428 11:52:47.735335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4429 11:52:47.742635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4430 11:52:47.745861 [CA 0] Center 35 (5~66) winsize 62
4431 11:52:47.748950 [CA 1] Center 35 (5~66) winsize 62
4432 11:52:47.752572 [CA 2] Center 34 (4~65) winsize 62
4433 11:52:47.755628 [CA 3] Center 33 (3~64) winsize 62
4434 11:52:47.758830 [CA 4] Center 34 (3~65) winsize 63
4435 11:52:47.762298 [CA 5] Center 33 (3~64) winsize 62
4436 11:52:47.762404
4437 11:52:47.765471 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4438 11:52:47.765555
4439 11:52:47.769001 [CATrainingPosCal] consider 1 rank data
4440 11:52:47.772363 u2DelayCellTimex100 = 270/100 ps
4441 11:52:47.776095 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4442 11:52:47.779368 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4443 11:52:47.782215 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 11:52:47.785380 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 11:52:47.792380 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4446 11:52:47.795262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4447 11:52:47.795346
4448 11:52:47.798694 CA PerBit enable=1, Macro0, CA PI delay=33
4449 11:52:47.798778
4450 11:52:47.802005 [CBTSetCACLKResult] CA Dly = 33
4451 11:52:47.802088 CS Dly: 3 (0~34)
4452 11:52:47.802155 ==
4453 11:52:47.805324 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 11:52:47.808820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:52:47.812135 ==
4456 11:52:47.815450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4457 11:52:47.822068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4458 11:52:47.825640 [CA 0] Center 35 (5~66) winsize 62
4459 11:52:47.828891 [CA 1] Center 35 (5~66) winsize 62
4460 11:52:47.832235 [CA 2] Center 34 (4~65) winsize 62
4461 11:52:47.835437 [CA 3] Center 34 (4~64) winsize 61
4462 11:52:47.838759 [CA 4] Center 34 (4~64) winsize 61
4463 11:52:47.842081 [CA 5] Center 34 (4~64) winsize 61
4464 11:52:47.842167
4465 11:52:47.845225 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4466 11:52:47.845301
4467 11:52:47.848568 [CATrainingPosCal] consider 2 rank data
4468 11:52:47.852420 u2DelayCellTimex100 = 270/100 ps
4469 11:52:47.855279 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4470 11:52:47.858726 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4471 11:52:47.861904 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4472 11:52:47.865416 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4473 11:52:47.872240 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4474 11:52:47.875511 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4475 11:52:47.875595
4476 11:52:47.878542 CA PerBit enable=1, Macro0, CA PI delay=34
4477 11:52:47.878616
4478 11:52:47.881836 [CBTSetCACLKResult] CA Dly = 34
4479 11:52:47.881913 CS Dly: 4 (0~37)
4480 11:52:47.881994
4481 11:52:47.885273 ----->DramcWriteLeveling(PI) begin...
4482 11:52:47.885356 ==
4483 11:52:47.888670 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 11:52:47.895340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 11:52:47.895417 ==
4486 11:52:47.898453 Write leveling (Byte 0): 31 => 31
4487 11:52:47.901989 Write leveling (Byte 1): 29 => 29
4488 11:52:47.902063 DramcWriteLeveling(PI) end<-----
4489 11:52:47.902143
4490 11:52:47.905265 ==
4491 11:52:47.905338 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 11:52:47.912028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 11:52:47.912109 ==
4494 11:52:47.915448 [Gating] SW mode calibration
4495 11:52:47.922127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4496 11:52:47.925334 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4497 11:52:47.932048 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 11:52:47.935303 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 11:52:47.938737 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4500 11:52:47.945295 0 9 12 | B1->B0 | 2c2c 2b2b | 0 1 | (0 1) (1 0)
4501 11:52:47.948468 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:52:47.952016 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:52:47.955481 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:52:47.962303 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 11:52:47.965625 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 11:52:47.968623 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 11:52:47.975393 0 10 8 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (1 1)
4508 11:52:47.979041 0 10 12 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
4509 11:52:47.982300 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:52:47.988807 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:52:47.992055 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:52:47.995324 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:52:48.002039 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:52:48.005232 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 11:52:48.008690 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 11:52:48.015022 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4517 11:52:48.018269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:52:48.021823 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:52:48.028426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:52:48.031590 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:52:48.034986 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:52:48.041770 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:52:48.044995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:52:48.048309 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:52:48.054867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:52:48.058301 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:52:48.061558 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:52:48.068241 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:52:48.071630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:52:48.074806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:52:48.081615 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 11:52:48.085297 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4533 11:52:48.088176 Total UI for P1: 0, mck2ui 16
4534 11:52:48.091621 best dqsien dly found for B0: ( 0, 13, 10)
4535 11:52:48.095182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 11:52:48.098152 Total UI for P1: 0, mck2ui 16
4537 11:52:48.101554 best dqsien dly found for B1: ( 0, 13, 12)
4538 11:52:48.104689 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4539 11:52:48.108621 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4540 11:52:48.108696
4541 11:52:48.111583 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4542 11:52:48.118561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4543 11:52:48.118636 [Gating] SW calibration Done
4544 11:52:48.118715 ==
4545 11:52:48.121473 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 11:52:48.128187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 11:52:48.128262 ==
4548 11:52:48.128349 RX Vref Scan: 0
4549 11:52:48.128422
4550 11:52:48.131748 RX Vref 0 -> 0, step: 1
4551 11:52:48.131826
4552 11:52:48.134646 RX Delay -230 -> 252, step: 16
4553 11:52:48.138171 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4554 11:52:48.141598 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4555 11:52:48.145046 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4556 11:52:48.151434 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4557 11:52:48.154880 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4558 11:52:48.158134 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4559 11:52:48.161491 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4560 11:52:48.165182 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4561 11:52:48.171529 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4562 11:52:48.175199 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4563 11:52:48.178960 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4564 11:52:48.181620 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4565 11:52:48.188352 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4566 11:52:48.191467 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4567 11:52:48.194976 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4568 11:52:48.198110 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4569 11:52:48.198192 ==
4570 11:52:48.201385 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 11:52:48.208001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:52:48.208080 ==
4573 11:52:48.208169 DQS Delay:
4574 11:52:48.211721 DQS0 = 0, DQS1 = 0
4575 11:52:48.211801 DQM Delay:
4576 11:52:48.211885 DQM0 = 50, DQM1 = 45
4577 11:52:48.215082 DQ Delay:
4578 11:52:48.218181 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4579 11:52:48.221834 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4580 11:52:48.225234 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4581 11:52:48.228233 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4582 11:52:48.228320
4583 11:52:48.228402
4584 11:52:48.228479 ==
4585 11:52:48.231831 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 11:52:48.234673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 11:52:48.234753 ==
4588 11:52:48.234839
4589 11:52:48.234916
4590 11:52:48.238154 TX Vref Scan disable
4591 11:52:48.241609 == TX Byte 0 ==
4592 11:52:48.244693 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4593 11:52:48.248155 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4594 11:52:48.251645 == TX Byte 1 ==
4595 11:52:48.255217 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4596 11:52:48.258651 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4597 11:52:48.258744 ==
4598 11:52:48.261860 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 11:52:48.264846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 11:52:48.264948 ==
4601 11:52:48.265039
4602 11:52:48.268214
4603 11:52:48.268322 TX Vref Scan disable
4604 11:52:48.272088 == TX Byte 0 ==
4605 11:52:48.275199 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4606 11:52:48.278291 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4607 11:52:48.281635 == TX Byte 1 ==
4608 11:52:48.285179 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4609 11:52:48.288918 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4610 11:52:48.291713
4611 11:52:48.291849 [DATLAT]
4612 11:52:48.291974 Freq=600, CH1 RK0
4613 11:52:48.292066
4614 11:52:48.294938 DATLAT Default: 0x9
4615 11:52:48.295016 0, 0xFFFF, sum = 0
4616 11:52:48.298021 1, 0xFFFF, sum = 0
4617 11:52:48.298136 2, 0xFFFF, sum = 0
4618 11:52:48.301681 3, 0xFFFF, sum = 0
4619 11:52:48.301758 4, 0xFFFF, sum = 0
4620 11:52:48.305009 5, 0xFFFF, sum = 0
4621 11:52:48.308315 6, 0xFFFF, sum = 0
4622 11:52:48.308390 7, 0xFFFF, sum = 0
4623 11:52:48.308475 8, 0x0, sum = 1
4624 11:52:48.311436 9, 0x0, sum = 2
4625 11:52:48.311509 10, 0x0, sum = 3
4626 11:52:48.314810 11, 0x0, sum = 4
4627 11:52:48.314882 best_step = 9
4628 11:52:48.314944
4629 11:52:48.315000 ==
4630 11:52:48.318142 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 11:52:48.324710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 11:52:48.324798 ==
4633 11:52:48.324881 RX Vref Scan: 1
4634 11:52:48.324958
4635 11:52:48.328348 RX Vref 0 -> 0, step: 1
4636 11:52:48.328423
4637 11:52:48.331529 RX Delay -163 -> 252, step: 8
4638 11:52:48.331602
4639 11:52:48.334979 Set Vref, RX VrefLevel [Byte0]: 51
4640 11:52:48.338076 [Byte1]: 55
4641 11:52:48.338155
4642 11:52:48.341560 Final RX Vref Byte 0 = 51 to rank0
4643 11:52:48.345053 Final RX Vref Byte 1 = 55 to rank0
4644 11:52:48.348262 Final RX Vref Byte 0 = 51 to rank1
4645 11:52:48.351351 Final RX Vref Byte 1 = 55 to rank1==
4646 11:52:48.354591 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 11:52:48.357979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 11:52:48.358097 ==
4649 11:52:48.361265 DQS Delay:
4650 11:52:48.361380 DQS0 = 0, DQS1 = 0
4651 11:52:48.361474 DQM Delay:
4652 11:52:48.364478 DQM0 = 49, DQM1 = 41
4653 11:52:48.364576 DQ Delay:
4654 11:52:48.368295 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4655 11:52:48.371550 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4656 11:52:48.374527 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4657 11:52:48.378115 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4658 11:52:48.378189
4659 11:52:48.378252
4660 11:52:48.387942 [DQSOSCAuto] RK0, (LSB)MR18= 0x5077, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4661 11:52:48.391281 CH1 RK0: MR19=808, MR18=5077
4662 11:52:48.394854 CH1_RK0: MR19=0x808, MR18=0x5077, DQSOSC=387, MR23=63, INC=175, DEC=116
4663 11:52:48.394927
4664 11:52:48.397853 ----->DramcWriteLeveling(PI) begin...
4665 11:52:48.401570 ==
4666 11:52:48.404925 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 11:52:48.407965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 11:52:48.408048 ==
4669 11:52:48.411039 Write leveling (Byte 0): 30 => 30
4670 11:52:48.414368 Write leveling (Byte 1): 30 => 30
4671 11:52:48.417787 DramcWriteLeveling(PI) end<-----
4672 11:52:48.417869
4673 11:52:48.417933 ==
4674 11:52:48.421461 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 11:52:48.424796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 11:52:48.424878 ==
4677 11:52:48.428255 [Gating] SW mode calibration
4678 11:52:48.434856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4679 11:52:48.437670 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4680 11:52:48.444671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 11:52:48.447935 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4682 11:52:48.451094 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4683 11:52:48.458001 0 9 12 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
4684 11:52:48.461064 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4685 11:52:48.464675 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:52:48.471383 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 11:52:48.474721 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 11:52:48.477577 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 11:52:48.484559 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 11:52:48.487593 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4691 11:52:48.491127 0 10 12 | B1->B0 | 3c3c 2828 | 0 0 | (0 0) (0 0)
4692 11:52:48.497738 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4693 11:52:48.501079 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:52:48.504048 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:52:48.511063 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 11:52:48.514281 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 11:52:48.517626 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:52:48.524163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 11:52:48.527539 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4700 11:52:48.531239 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:52:48.537248 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:52:48.540588 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:52:48.544337 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:52:48.550371 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:52:48.554224 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:52:48.557356 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:52:48.563997 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:52:48.567478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:52:48.570745 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:52:48.577455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:52:48.580626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:52:48.584162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:52:48.587511 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:52:48.593873 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 11:52:48.597408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4716 11:52:48.600965 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 11:52:48.603770 Total UI for P1: 0, mck2ui 16
4718 11:52:48.607474 best dqsien dly found for B0: ( 0, 13, 12)
4719 11:52:48.610634 Total UI for P1: 0, mck2ui 16
4720 11:52:48.613667 best dqsien dly found for B1: ( 0, 13, 12)
4721 11:52:48.617062 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4722 11:52:48.623860 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4723 11:52:48.623969
4724 11:52:48.627062 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4725 11:52:48.630514 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4726 11:52:48.633812 [Gating] SW calibration Done
4727 11:52:48.633894 ==
4728 11:52:48.637132 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 11:52:48.640565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 11:52:48.640661 ==
4731 11:52:48.640728 RX Vref Scan: 0
4732 11:52:48.643843
4733 11:52:48.643925 RX Vref 0 -> 0, step: 1
4734 11:52:48.643991
4735 11:52:48.647123 RX Delay -230 -> 252, step: 16
4736 11:52:48.650588 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4737 11:52:48.656962 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4738 11:52:48.660354 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4739 11:52:48.663878 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4740 11:52:48.666996 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4741 11:52:48.670113 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4742 11:52:48.677180 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4743 11:52:48.680418 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4744 11:52:48.683577 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4745 11:52:48.687582 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4746 11:52:48.690269 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4747 11:52:48.697112 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4748 11:52:48.700778 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4749 11:52:48.703695 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4750 11:52:48.706941 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4751 11:52:48.713577 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4752 11:52:48.713656 ==
4753 11:52:48.717397 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 11:52:48.720370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 11:52:48.720469 ==
4756 11:52:48.720558 DQS Delay:
4757 11:52:48.723393 DQS0 = 0, DQS1 = 0
4758 11:52:48.723463 DQM Delay:
4759 11:52:48.727224 DQM0 = 50, DQM1 = 46
4760 11:52:48.727294 DQ Delay:
4761 11:52:48.730268 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4762 11:52:48.733539 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4763 11:52:48.736731 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4764 11:52:48.740349 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4765 11:52:48.740424
4766 11:52:48.740489
4767 11:52:48.740549 ==
4768 11:52:48.743819 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 11:52:48.747034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 11:52:48.749931 ==
4771 11:52:48.750013
4772 11:52:48.750103
4773 11:52:48.750190 TX Vref Scan disable
4774 11:52:48.753501 == TX Byte 0 ==
4775 11:52:48.756526 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4776 11:52:48.759920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4777 11:52:48.763575 == TX Byte 1 ==
4778 11:52:48.766740 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4779 11:52:48.770310 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4780 11:52:48.773749 ==
4781 11:52:48.776643 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 11:52:48.780031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 11:52:48.780113 ==
4784 11:52:48.780178
4785 11:52:48.780238
4786 11:52:48.783270 TX Vref Scan disable
4787 11:52:48.783352 == TX Byte 0 ==
4788 11:52:48.789935 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4789 11:52:48.793690 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4790 11:52:48.793777 == TX Byte 1 ==
4791 11:52:48.799849 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4792 11:52:48.803171 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4793 11:52:48.803247
4794 11:52:48.803309 [DATLAT]
4795 11:52:48.806712 Freq=600, CH1 RK1
4796 11:52:48.806783
4797 11:52:48.806843 DATLAT Default: 0x9
4798 11:52:48.810123 0, 0xFFFF, sum = 0
4799 11:52:48.810204 1, 0xFFFF, sum = 0
4800 11:52:48.813967 2, 0xFFFF, sum = 0
4801 11:52:48.814038 3, 0xFFFF, sum = 0
4802 11:52:48.816743 4, 0xFFFF, sum = 0
4803 11:52:48.816814 5, 0xFFFF, sum = 0
4804 11:52:48.819866 6, 0xFFFF, sum = 0
4805 11:52:48.819937 7, 0xFFFF, sum = 0
4806 11:52:48.823228 8, 0x0, sum = 1
4807 11:52:48.823299 9, 0x0, sum = 2
4808 11:52:48.826923 10, 0x0, sum = 3
4809 11:52:48.826994 11, 0x0, sum = 4
4810 11:52:48.830032 best_step = 9
4811 11:52:48.830105
4812 11:52:48.830171 ==
4813 11:52:48.833216 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 11:52:48.836606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 11:52:48.836678 ==
4816 11:52:48.839917 RX Vref Scan: 0
4817 11:52:48.839987
4818 11:52:48.840047 RX Vref 0 -> 0, step: 1
4819 11:52:48.840142
4820 11:52:48.843316 RX Delay -163 -> 252, step: 8
4821 11:52:48.850208 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4822 11:52:48.853579 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4823 11:52:48.856695 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4824 11:52:48.860139 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4825 11:52:48.863758 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4826 11:52:48.870234 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4827 11:52:48.873654 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4828 11:52:48.876722 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4829 11:52:48.880128 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4830 11:52:48.886698 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4831 11:52:48.889974 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4832 11:52:48.893485 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4833 11:52:48.896672 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4834 11:52:48.900285 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4835 11:52:48.906394 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4836 11:52:48.909695 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4837 11:52:48.909791 ==
4838 11:52:48.913331 Dram Type= 6, Freq= 0, CH_1, rank 1
4839 11:52:48.916668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4840 11:52:48.916765 ==
4841 11:52:48.919982 DQS Delay:
4842 11:52:48.920083 DQS0 = 0, DQS1 = 0
4843 11:52:48.920172 DQM Delay:
4844 11:52:48.923049 DQM0 = 49, DQM1 = 44
4845 11:52:48.923119 DQ Delay:
4846 11:52:48.927096 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4847 11:52:48.929735 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4848 11:52:48.933396 DQ8 =32, DQ9 =32, DQ10 =40, DQ11 =40
4849 11:52:48.936783 DQ12 =56, DQ13 =48, DQ14 =48, DQ15 =56
4850 11:52:48.936880
4851 11:52:48.936969
4852 11:52:48.946636 [DQSOSCAuto] RK1, (LSB)MR18= 0x6126, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4853 11:52:48.949875 CH1 RK1: MR19=808, MR18=6126
4854 11:52:48.953449 CH1_RK1: MR19=0x808, MR18=0x6126, DQSOSC=391, MR23=63, INC=171, DEC=114
4855 11:52:48.956516 [RxdqsGatingPostProcess] freq 600
4856 11:52:48.963206 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4857 11:52:48.966620 Pre-setting of DQS Precalculation
4858 11:52:48.969879 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4859 11:52:48.979511 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4860 11:52:48.986159 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4861 11:52:48.986259
4862 11:52:48.986349
4863 11:52:48.989604 [Calibration Summary] 1200 Mbps
4864 11:52:48.989704 CH 0, Rank 0
4865 11:52:48.992985 SW Impedance : PASS
4866 11:52:48.993066 DUTY Scan : NO K
4867 11:52:48.996003 ZQ Calibration : PASS
4868 11:52:48.999583 Jitter Meter : NO K
4869 11:52:48.999680 CBT Training : PASS
4870 11:52:49.003106 Write leveling : PASS
4871 11:52:49.006187 RX DQS gating : PASS
4872 11:52:49.006284 RX DQ/DQS(RDDQC) : PASS
4873 11:52:49.009434 TX DQ/DQS : PASS
4874 11:52:49.009505 RX DATLAT : PASS
4875 11:52:49.013054 RX DQ/DQS(Engine): PASS
4876 11:52:49.015979 TX OE : NO K
4877 11:52:49.016050 All Pass.
4878 11:52:49.016119
4879 11:52:49.016178 CH 0, Rank 1
4880 11:52:49.019483 SW Impedance : PASS
4881 11:52:49.022945 DUTY Scan : NO K
4882 11:52:49.023045 ZQ Calibration : PASS
4883 11:52:49.026245 Jitter Meter : NO K
4884 11:52:49.029338 CBT Training : PASS
4885 11:52:49.029437 Write leveling : PASS
4886 11:52:49.032982 RX DQS gating : PASS
4887 11:52:49.036032 RX DQ/DQS(RDDQC) : PASS
4888 11:52:49.036117 TX DQ/DQS : PASS
4889 11:52:49.039571 RX DATLAT : PASS
4890 11:52:49.043069 RX DQ/DQS(Engine): PASS
4891 11:52:49.043160 TX OE : NO K
4892 11:52:49.043223 All Pass.
4893 11:52:49.046328
4894 11:52:49.046433 CH 1, Rank 0
4895 11:52:49.049731 SW Impedance : PASS
4896 11:52:49.049805 DUTY Scan : NO K
4897 11:52:49.052804 ZQ Calibration : PASS
4898 11:52:49.052876 Jitter Meter : NO K
4899 11:52:49.056166 CBT Training : PASS
4900 11:52:49.059854 Write leveling : PASS
4901 11:52:49.059951 RX DQS gating : PASS
4902 11:52:49.063120 RX DQ/DQS(RDDQC) : PASS
4903 11:52:49.066229 TX DQ/DQS : PASS
4904 11:52:49.066329 RX DATLAT : PASS
4905 11:52:49.069858 RX DQ/DQS(Engine): PASS
4906 11:52:49.073510 TX OE : NO K
4907 11:52:49.073614 All Pass.
4908 11:52:49.073703
4909 11:52:49.073796 CH 1, Rank 1
4910 11:52:49.076230 SW Impedance : PASS
4911 11:52:49.079298 DUTY Scan : NO K
4912 11:52:49.079371 ZQ Calibration : PASS
4913 11:52:49.082649 Jitter Meter : NO K
4914 11:52:49.086010 CBT Training : PASS
4915 11:52:49.086083 Write leveling : PASS
4916 11:52:49.089636 RX DQS gating : PASS
4917 11:52:49.092878 RX DQ/DQS(RDDQC) : PASS
4918 11:52:49.092963 TX DQ/DQS : PASS
4919 11:52:49.096438 RX DATLAT : PASS
4920 11:52:49.096523 RX DQ/DQS(Engine): PASS
4921 11:52:49.099433 TX OE : NO K
4922 11:52:49.099518 All Pass.
4923 11:52:49.099602
4924 11:52:49.102847 DramC Write-DBI off
4925 11:52:49.106122 PER_BANK_REFRESH: Hybrid Mode
4926 11:52:49.106207 TX_TRACKING: ON
4927 11:52:49.116063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4928 11:52:49.119183 [FAST_K] Save calibration result to emmc
4929 11:52:49.122590 dramc_set_vcore_voltage set vcore to 662500
4930 11:52:49.125765 Read voltage for 933, 3
4931 11:52:49.125849 Vio18 = 0
4932 11:52:49.129122 Vcore = 662500
4933 11:52:49.129206 Vdram = 0
4934 11:52:49.129289 Vddq = 0
4935 11:52:49.129367 Vmddr = 0
4936 11:52:49.135559 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4937 11:52:49.142267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4938 11:52:49.142352 MEM_TYPE=3, freq_sel=17
4939 11:52:49.145589 sv_algorithm_assistance_LP4_1600
4940 11:52:49.148761 ============ PULL DRAM RESETB DOWN ============
4941 11:52:49.156015 ========== PULL DRAM RESETB DOWN end =========
4942 11:52:49.159167 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4943 11:52:49.162091 ===================================
4944 11:52:49.165559 LPDDR4 DRAM CONFIGURATION
4945 11:52:49.168862 ===================================
4946 11:52:49.168946 EX_ROW_EN[0] = 0x0
4947 11:52:49.172295 EX_ROW_EN[1] = 0x0
4948 11:52:49.172379 LP4Y_EN = 0x0
4949 11:52:49.175821 WORK_FSP = 0x0
4950 11:52:49.175905 WL = 0x3
4951 11:52:49.179011 RL = 0x3
4952 11:52:49.182006 BL = 0x2
4953 11:52:49.182090 RPST = 0x0
4954 11:52:49.185345 RD_PRE = 0x0
4955 11:52:49.185430 WR_PRE = 0x1
4956 11:52:49.188762 WR_PST = 0x0
4957 11:52:49.188847 DBI_WR = 0x0
4958 11:52:49.191953 DBI_RD = 0x0
4959 11:52:49.192036 OTF = 0x1
4960 11:52:49.195483 ===================================
4961 11:52:49.199010 ===================================
4962 11:52:49.202045 ANA top config
4963 11:52:49.205414 ===================================
4964 11:52:49.205498 DLL_ASYNC_EN = 0
4965 11:52:49.208519 ALL_SLAVE_EN = 1
4966 11:52:49.211987 NEW_RANK_MODE = 1
4967 11:52:49.215472 DLL_IDLE_MODE = 1
4968 11:52:49.215556 LP45_APHY_COMB_EN = 1
4969 11:52:49.218732 TX_ODT_DIS = 1
4970 11:52:49.222207 NEW_8X_MODE = 1
4971 11:52:49.225165 ===================================
4972 11:52:49.228501 ===================================
4973 11:52:49.232077 data_rate = 1866
4974 11:52:49.235317 CKR = 1
4975 11:52:49.238811 DQ_P2S_RATIO = 8
4976 11:52:49.242090 ===================================
4977 11:52:49.242245 CA_P2S_RATIO = 8
4978 11:52:49.245096 DQ_CA_OPEN = 0
4979 11:52:49.248545 DQ_SEMI_OPEN = 0
4980 11:52:49.251505 CA_SEMI_OPEN = 0
4981 11:52:49.255230 CA_FULL_RATE = 0
4982 11:52:49.258332 DQ_CKDIV4_EN = 1
4983 11:52:49.258470 CA_CKDIV4_EN = 1
4984 11:52:49.261786 CA_PREDIV_EN = 0
4985 11:52:49.264915 PH8_DLY = 0
4986 11:52:49.268255 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4987 11:52:49.271549 DQ_AAMCK_DIV = 4
4988 11:52:49.274752 CA_AAMCK_DIV = 4
4989 11:52:49.274835 CA_ADMCK_DIV = 4
4990 11:52:49.278422 DQ_TRACK_CA_EN = 0
4991 11:52:49.281336 CA_PICK = 933
4992 11:52:49.285012 CA_MCKIO = 933
4993 11:52:49.287939 MCKIO_SEMI = 0
4994 11:52:49.291164 PLL_FREQ = 3732
4995 11:52:49.294701 DQ_UI_PI_RATIO = 32
4996 11:52:49.294784 CA_UI_PI_RATIO = 0
4997 11:52:49.298104 ===================================
4998 11:52:49.301262 ===================================
4999 11:52:49.304805 memory_type:LPDDR4
5000 11:52:49.307750 GP_NUM : 10
5001 11:52:49.307833 SRAM_EN : 1
5002 11:52:49.311317 MD32_EN : 0
5003 11:52:49.314752 ===================================
5004 11:52:49.318270 [ANA_INIT] >>>>>>>>>>>>>>
5005 11:52:49.320988 <<<<<< [CONFIGURE PHASE]: ANA_TX
5006 11:52:49.324301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:52:49.327671 ===================================
5008 11:52:49.327753 data_rate = 1866,PCW = 0X8f00
5009 11:52:49.331071 ===================================
5010 11:52:49.334563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5011 11:52:49.341122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 11:52:49.347877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5013 11:52:49.351130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5014 11:52:49.354099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5015 11:52:49.357819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5016 11:52:49.360932 [ANA_INIT] flow start
5017 11:52:49.361015 [ANA_INIT] PLL >>>>>>>>
5018 11:52:49.364306 [ANA_INIT] PLL <<<<<<<<
5019 11:52:49.367715 [ANA_INIT] MIDPI >>>>>>>>
5020 11:52:49.371327 [ANA_INIT] MIDPI <<<<<<<<
5021 11:52:49.371410 [ANA_INIT] DLL >>>>>>>>
5022 11:52:49.374331 [ANA_INIT] flow end
5023 11:52:49.377623 ============ LP4 DIFF to SE enter ============
5024 11:52:49.381099 ============ LP4 DIFF to SE exit ============
5025 11:52:49.384302 [ANA_INIT] <<<<<<<<<<<<<
5026 11:52:49.387633 [Flow] Enable top DCM control >>>>>
5027 11:52:49.390906 [Flow] Enable top DCM control <<<<<
5028 11:52:49.394551 Enable DLL master slave shuffle
5029 11:52:49.400724 ==============================================================
5030 11:52:49.400807 Gating Mode config
5031 11:52:49.407193 ==============================================================
5032 11:52:49.407275 Config description:
5033 11:52:49.417536 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5034 11:52:49.424034 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5035 11:52:49.430599 SELPH_MODE 0: By rank 1: By Phase
5036 11:52:49.433847 ==============================================================
5037 11:52:49.437405 GAT_TRACK_EN = 1
5038 11:52:49.440719 RX_GATING_MODE = 2
5039 11:52:49.444031 RX_GATING_TRACK_MODE = 2
5040 11:52:49.447281 SELPH_MODE = 1
5041 11:52:49.450691 PICG_EARLY_EN = 1
5042 11:52:49.454025 VALID_LAT_VALUE = 1
5043 11:52:49.460617 ==============================================================
5044 11:52:49.463976 Enter into Gating configuration >>>>
5045 11:52:49.464060 Exit from Gating configuration <<<<
5046 11:52:49.467351 Enter into DVFS_PRE_config >>>>>
5047 11:52:49.480707 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5048 11:52:49.484223 Exit from DVFS_PRE_config <<<<<
5049 11:52:49.487436 Enter into PICG configuration >>>>
5050 11:52:49.490780 Exit from PICG configuration <<<<
5051 11:52:49.490863 [RX_INPUT] configuration >>>>>
5052 11:52:49.493865 [RX_INPUT] configuration <<<<<
5053 11:52:49.500452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5054 11:52:49.503940 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5055 11:52:49.510324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 11:52:49.517274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 11:52:49.523518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5058 11:52:49.530228 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5059 11:52:49.533825 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5060 11:52:49.537024 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5061 11:52:49.540755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5062 11:52:49.547015 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5063 11:52:49.550637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5064 11:52:49.553793 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 11:52:49.556929 ===================================
5066 11:52:49.560495 LPDDR4 DRAM CONFIGURATION
5067 11:52:49.563916 ===================================
5068 11:52:49.567019 EX_ROW_EN[0] = 0x0
5069 11:52:49.567101 EX_ROW_EN[1] = 0x0
5070 11:52:49.570195 LP4Y_EN = 0x0
5071 11:52:49.570278 WORK_FSP = 0x0
5072 11:52:49.573801 WL = 0x3
5073 11:52:49.573915 RL = 0x3
5074 11:52:49.576938 BL = 0x2
5075 11:52:49.577021 RPST = 0x0
5076 11:52:49.580240 RD_PRE = 0x0
5077 11:52:49.580322 WR_PRE = 0x1
5078 11:52:49.584037 WR_PST = 0x0
5079 11:52:49.584120 DBI_WR = 0x0
5080 11:52:49.587036 DBI_RD = 0x0
5081 11:52:49.587118 OTF = 0x1
5082 11:52:49.590487 ===================================
5083 11:52:49.596831 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5084 11:52:49.600349 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5085 11:52:49.603858 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5086 11:52:49.606696 ===================================
5087 11:52:49.610181 LPDDR4 DRAM CONFIGURATION
5088 11:52:49.613672 ===================================
5089 11:52:49.617005 EX_ROW_EN[0] = 0x10
5090 11:52:49.617088 EX_ROW_EN[1] = 0x0
5091 11:52:49.620129 LP4Y_EN = 0x0
5092 11:52:49.620211 WORK_FSP = 0x0
5093 11:52:49.623634 WL = 0x3
5094 11:52:49.623716 RL = 0x3
5095 11:52:49.627164 BL = 0x2
5096 11:52:49.627246 RPST = 0x0
5097 11:52:49.630237 RD_PRE = 0x0
5098 11:52:49.630318 WR_PRE = 0x1
5099 11:52:49.633911 WR_PST = 0x0
5100 11:52:49.634021 DBI_WR = 0x0
5101 11:52:49.637277 DBI_RD = 0x0
5102 11:52:49.637359 OTF = 0x1
5103 11:52:49.640203 ===================================
5104 11:52:49.647260 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5105 11:52:49.651431 nWR fixed to 30
5106 11:52:49.654689 [ModeRegInit_LP4] CH0 RK0
5107 11:52:49.654771 [ModeRegInit_LP4] CH0 RK1
5108 11:52:49.658216 [ModeRegInit_LP4] CH1 RK0
5109 11:52:49.661246 [ModeRegInit_LP4] CH1 RK1
5110 11:52:49.661356 match AC timing 9
5111 11:52:49.667808 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5112 11:52:49.671075 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5113 11:52:49.674314 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5114 11:52:49.681187 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5115 11:52:49.684445 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5116 11:52:49.684527 ==
5117 11:52:49.687864 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 11:52:49.690928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 11:52:49.691011 ==
5120 11:52:49.697499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 11:52:49.704119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5122 11:52:49.707471 [CA 0] Center 38 (7~69) winsize 63
5123 11:52:49.710862 [CA 1] Center 38 (8~69) winsize 62
5124 11:52:49.713963 [CA 2] Center 35 (5~66) winsize 62
5125 11:52:49.717269 [CA 3] Center 34 (4~65) winsize 62
5126 11:52:49.720718 [CA 4] Center 34 (4~65) winsize 62
5127 11:52:49.724140 [CA 5] Center 33 (3~64) winsize 62
5128 11:52:49.724222
5129 11:52:49.727291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5130 11:52:49.727373
5131 11:52:49.730833 [CATrainingPosCal] consider 1 rank data
5132 11:52:49.733897 u2DelayCellTimex100 = 270/100 ps
5133 11:52:49.737587 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5134 11:52:49.740984 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5135 11:52:49.744097 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5136 11:52:49.747531 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5137 11:52:49.750770 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5138 11:52:49.757644 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5139 11:52:49.757727
5140 11:52:49.760810 CA PerBit enable=1, Macro0, CA PI delay=33
5141 11:52:49.760912
5142 11:52:49.764073 [CBTSetCACLKResult] CA Dly = 33
5143 11:52:49.764155 CS Dly: 7 (0~38)
5144 11:52:49.764220 ==
5145 11:52:49.767223 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 11:52:49.770679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:52:49.774029 ==
5148 11:52:49.777384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5149 11:52:49.784150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5150 11:52:49.787116 [CA 0] Center 38 (8~69) winsize 62
5151 11:52:49.790736 [CA 1] Center 38 (8~69) winsize 62
5152 11:52:49.793833 [CA 2] Center 36 (6~66) winsize 61
5153 11:52:49.797287 [CA 3] Center 35 (5~66) winsize 62
5154 11:52:49.800684 [CA 4] Center 34 (4~65) winsize 62
5155 11:52:49.804095 [CA 5] Center 34 (4~64) winsize 61
5156 11:52:49.804178
5157 11:52:49.807436 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5158 11:52:49.807524
5159 11:52:49.810345 [CATrainingPosCal] consider 2 rank data
5160 11:52:49.813968 u2DelayCellTimex100 = 270/100 ps
5161 11:52:49.817378 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5162 11:52:49.820740 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5163 11:52:49.823978 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5164 11:52:49.827790 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5165 11:52:49.833851 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5166 11:52:49.837043 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5167 11:52:49.837125
5168 11:52:49.840347 CA PerBit enable=1, Macro0, CA PI delay=34
5169 11:52:49.840429
5170 11:52:49.843965 [CBTSetCACLKResult] CA Dly = 34
5171 11:52:49.844054 CS Dly: 7 (0~39)
5172 11:52:49.844119
5173 11:52:49.847135 ----->DramcWriteLeveling(PI) begin...
5174 11:52:49.847218 ==
5175 11:52:49.850847 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 11:52:49.857164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 11:52:49.857249 ==
5178 11:52:49.860430 Write leveling (Byte 0): 33 => 33
5179 11:52:49.860513 Write leveling (Byte 1): 30 => 30
5180 11:52:49.863946 DramcWriteLeveling(PI) end<-----
5181 11:52:49.864029
5182 11:52:49.864093 ==
5183 11:52:49.867014 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 11:52:49.874108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 11:52:49.874191 ==
5186 11:52:49.877018 [Gating] SW mode calibration
5187 11:52:49.883808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5188 11:52:49.886965 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5189 11:52:49.893622 0 14 0 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
5190 11:52:49.896765 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 11:52:49.900297 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 11:52:49.907090 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 11:52:49.910381 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 11:52:49.913625 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 11:52:49.920022 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5196 11:52:49.923469 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5197 11:52:49.926822 0 15 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
5198 11:52:49.933521 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 11:52:49.937015 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 11:52:49.940245 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 11:52:49.946790 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 11:52:49.950348 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 11:52:49.953409 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5204 11:52:49.956890 0 15 28 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
5205 11:52:49.963223 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:52:49.966882 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:52:49.970467 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:52:49.976660 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:52:49.979969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:52:49.983480 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:52:49.989874 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5212 11:52:49.993393 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5213 11:52:49.996759 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:52:50.003196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:52:50.006593 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:52:50.009742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:52:50.016562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:52:50.019974 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:52:50.022933 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:52:50.029801 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:52:50.033146 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:52:50.036192 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:52:50.043146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:52:50.046282 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:52:50.049753 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:52:50.056002 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:52:50.059739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 11:52:50.063141 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5229 11:52:50.069503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 11:52:50.069635 Total UI for P1: 0, mck2ui 16
5231 11:52:50.076184 best dqsien dly found for B0: ( 1, 2, 26)
5232 11:52:50.076267 Total UI for P1: 0, mck2ui 16
5233 11:52:50.079503 best dqsien dly found for B1: ( 1, 2, 30)
5234 11:52:50.086816 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5235 11:52:50.089632 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5236 11:52:50.089714
5237 11:52:50.093091 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5238 11:52:50.095944 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5239 11:52:50.099216 [Gating] SW calibration Done
5240 11:52:50.099298 ==
5241 11:52:50.102547 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:52:50.106121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:52:50.106204 ==
5244 11:52:50.109621 RX Vref Scan: 0
5245 11:52:50.109703
5246 11:52:50.109768 RX Vref 0 -> 0, step: 1
5247 11:52:50.109827
5248 11:52:50.112521 RX Delay -80 -> 252, step: 8
5249 11:52:50.116119 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5250 11:52:50.122694 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5251 11:52:50.126061 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5252 11:52:50.129521 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5253 11:52:50.132620 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5254 11:52:50.135899 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5255 11:52:50.139015 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5256 11:52:50.145715 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5257 11:52:50.149168 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5258 11:52:50.152368 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5259 11:52:50.155986 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5260 11:52:50.159280 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5261 11:52:50.162441 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5262 11:52:50.169137 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5263 11:52:50.172469 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5264 11:52:50.175547 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5265 11:52:50.175629 ==
5266 11:52:50.178823 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 11:52:50.182644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 11:52:50.182728 ==
5269 11:52:50.186043 DQS Delay:
5270 11:52:50.186125 DQS0 = 0, DQS1 = 0
5271 11:52:50.186190 DQM Delay:
5272 11:52:50.189131 DQM0 = 105, DQM1 = 90
5273 11:52:50.189213 DQ Delay:
5274 11:52:50.192314 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5275 11:52:50.195625 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5276 11:52:50.199101 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5277 11:52:50.202389 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5278 11:52:50.202498
5279 11:52:50.202563
5280 11:52:50.205597 ==
5281 11:52:50.208827 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 11:52:50.212342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 11:52:50.212424 ==
5284 11:52:50.212489
5285 11:52:50.212549
5286 11:52:50.215756 TX Vref Scan disable
5287 11:52:50.215838 == TX Byte 0 ==
5288 11:52:50.218876 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5289 11:52:50.225468 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5290 11:52:50.225551 == TX Byte 1 ==
5291 11:52:50.232283 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5292 11:52:50.235478 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5293 11:52:50.235561 ==
5294 11:52:50.238732 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 11:52:50.242288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 11:52:50.242405 ==
5297 11:52:50.242510
5298 11:52:50.242573
5299 11:52:50.245739 TX Vref Scan disable
5300 11:52:50.248940 == TX Byte 0 ==
5301 11:52:50.252354 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5302 11:52:50.255367 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5303 11:52:50.258772 == TX Byte 1 ==
5304 11:52:50.262074 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5305 11:52:50.265518 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5306 11:52:50.265627
5307 11:52:50.268635 [DATLAT]
5308 11:52:50.268717 Freq=933, CH0 RK0
5309 11:52:50.268783
5310 11:52:50.272197 DATLAT Default: 0xd
5311 11:52:50.272280 0, 0xFFFF, sum = 0
5312 11:52:50.275570 1, 0xFFFF, sum = 0
5313 11:52:50.275671 2, 0xFFFF, sum = 0
5314 11:52:50.278545 3, 0xFFFF, sum = 0
5315 11:52:50.278655 4, 0xFFFF, sum = 0
5316 11:52:50.282250 5, 0xFFFF, sum = 0
5317 11:52:50.282334 6, 0xFFFF, sum = 0
5318 11:52:50.285221 7, 0xFFFF, sum = 0
5319 11:52:50.285305 8, 0xFFFF, sum = 0
5320 11:52:50.288782 9, 0xFFFF, sum = 0
5321 11:52:50.288874 10, 0x0, sum = 1
5322 11:52:50.292041 11, 0x0, sum = 2
5323 11:52:50.292124 12, 0x0, sum = 3
5324 11:52:50.295338 13, 0x0, sum = 4
5325 11:52:50.295448 best_step = 11
5326 11:52:50.295544
5327 11:52:50.295635 ==
5328 11:52:50.298416 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 11:52:50.302124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 11:52:50.305180 ==
5331 11:52:50.305270 RX Vref Scan: 1
5332 11:52:50.305336
5333 11:52:50.308291 RX Vref 0 -> 0, step: 1
5334 11:52:50.308373
5335 11:52:50.312038 RX Delay -53 -> 252, step: 4
5336 11:52:50.312120
5337 11:52:50.315309 Set Vref, RX VrefLevel [Byte0]: 57
5338 11:52:50.318557 [Byte1]: 48
5339 11:52:50.318666
5340 11:52:50.321551 Final RX Vref Byte 0 = 57 to rank0
5341 11:52:50.324794 Final RX Vref Byte 1 = 48 to rank0
5342 11:52:50.328435 Final RX Vref Byte 0 = 57 to rank1
5343 11:52:50.331962 Final RX Vref Byte 1 = 48 to rank1==
5344 11:52:50.334824 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 11:52:50.338698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 11:52:50.338780 ==
5347 11:52:50.341894 DQS Delay:
5348 11:52:50.341976 DQS0 = 0, DQS1 = 0
5349 11:52:50.342041 DQM Delay:
5350 11:52:50.345123 DQM0 = 107, DQM1 = 91
5351 11:52:50.345205 DQ Delay:
5352 11:52:50.348372 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5353 11:52:50.351799 DQ4 =106, DQ5 =100, DQ6 =114, DQ7 =114
5354 11:52:50.355238 DQ8 =84, DQ9 =76, DQ10 =92, DQ11 =90
5355 11:52:50.358286 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =100
5356 11:52:50.358369
5357 11:52:50.358468
5358 11:52:50.368289 [DQSOSCAuto] RK0, (LSB)MR18= 0x2925, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
5359 11:52:50.371871 CH0 RK0: MR19=505, MR18=2925
5360 11:52:50.378062 CH0_RK0: MR19=0x505, MR18=0x2925, DQSOSC=408, MR23=63, INC=65, DEC=43
5361 11:52:50.378144
5362 11:52:50.381622 ----->DramcWriteLeveling(PI) begin...
5363 11:52:50.381703 ==
5364 11:52:50.384483 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 11:52:50.388009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 11:52:50.388089 ==
5367 11:52:50.391250 Write leveling (Byte 0): 31 => 31
5368 11:52:50.394689 Write leveling (Byte 1): 31 => 31
5369 11:52:50.398073 DramcWriteLeveling(PI) end<-----
5370 11:52:50.398153
5371 11:52:50.398216 ==
5372 11:52:50.401298 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 11:52:50.404457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 11:52:50.404571 ==
5375 11:52:50.407842 [Gating] SW mode calibration
5376 11:52:50.414680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 11:52:50.420964 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 11:52:50.424202 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 11:52:50.427549 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 11:52:50.434779 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 11:52:50.438389 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 11:52:50.441127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:52:50.447951 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 11:52:50.450992 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 11:52:50.454361 0 14 28 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
5386 11:52:50.461412 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 11:52:50.464782 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 11:52:50.467872 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 11:52:50.474377 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 11:52:50.477950 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 11:52:50.481289 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 11:52:50.487621 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5393 11:52:50.490907 0 15 28 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
5394 11:52:50.494418 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 11:52:50.501238 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:52:50.504397 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:52:50.508107 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:52:50.511322 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:52:50.517814 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:52:50.520878 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 11:52:50.524298 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5402 11:52:50.530873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5403 11:52:50.534104 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:52:50.537406 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:52:50.544083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:52:50.547631 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:52:50.551227 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:52:50.557343 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:52:50.560964 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:52:50.564195 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:52:50.570973 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:52:50.574094 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:52:50.577206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:52:50.584024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 11:52:50.587407 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:52:50.590950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5417 11:52:50.597226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5418 11:52:50.600767 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 11:52:50.604028 Total UI for P1: 0, mck2ui 16
5420 11:52:50.607333 best dqsien dly found for B0: ( 1, 2, 26)
5421 11:52:50.610491 Total UI for P1: 0, mck2ui 16
5422 11:52:50.613819 best dqsien dly found for B1: ( 1, 2, 28)
5423 11:52:50.617174 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5424 11:52:50.620953 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5425 11:52:50.621036
5426 11:52:50.623795 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5427 11:52:50.627366 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5428 11:52:50.630836 [Gating] SW calibration Done
5429 11:52:50.630969 ==
5430 11:52:50.634138 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:52:50.637599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:52:50.640711 ==
5433 11:52:50.640824 RX Vref Scan: 0
5434 11:52:50.640912
5435 11:52:50.643976 RX Vref 0 -> 0, step: 1
5436 11:52:50.644133
5437 11:52:50.644232 RX Delay -80 -> 252, step: 8
5438 11:52:50.650508 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5439 11:52:50.653863 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5440 11:52:50.657519 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5441 11:52:50.660950 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5442 11:52:50.664019 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5443 11:52:50.667892 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5444 11:52:50.674142 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5445 11:52:50.677932 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5446 11:52:50.681025 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5447 11:52:50.684256 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5448 11:52:50.687500 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5449 11:52:50.694491 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5450 11:52:50.697976 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5451 11:52:50.701363 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5452 11:52:50.704451 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5453 11:52:50.707799 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5454 11:52:50.708226 ==
5455 11:52:50.710692 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:52:50.714629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:52:50.717550 ==
5458 11:52:50.717973 DQS Delay:
5459 11:52:50.718312 DQS0 = 0, DQS1 = 0
5460 11:52:50.721074 DQM Delay:
5461 11:52:50.721532 DQM0 = 104, DQM1 = 90
5462 11:52:50.724109 DQ Delay:
5463 11:52:50.727661 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5464 11:52:50.730826 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5465 11:52:50.734119 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5466 11:52:50.737798 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5467 11:52:50.738219
5468 11:52:50.738596
5469 11:52:50.738917 ==
5470 11:52:50.741320 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 11:52:50.744658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 11:52:50.745114 ==
5473 11:52:50.745483
5474 11:52:50.745802
5475 11:52:50.747514 TX Vref Scan disable
5476 11:52:50.747947 == TX Byte 0 ==
5477 11:52:50.754310 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5478 11:52:50.757535 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5479 11:52:50.757958 == TX Byte 1 ==
5480 11:52:50.764112 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5481 11:52:50.767213 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5482 11:52:50.767641 ==
5483 11:52:50.770691 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 11:52:50.774426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 11:52:50.774860 ==
5486 11:52:50.775202
5487 11:52:50.777361
5488 11:52:50.777813 TX Vref Scan disable
5489 11:52:50.780749 == TX Byte 0 ==
5490 11:52:50.784028 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5491 11:52:50.787516 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5492 11:52:50.790678 == TX Byte 1 ==
5493 11:52:50.793793 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5494 11:52:50.797725 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5495 11:52:50.798151
5496 11:52:50.800899 [DATLAT]
5497 11:52:50.801435 Freq=933, CH0 RK1
5498 11:52:50.801782
5499 11:52:50.803804 DATLAT Default: 0xb
5500 11:52:50.804228 0, 0xFFFF, sum = 0
5501 11:52:50.807125 1, 0xFFFF, sum = 0
5502 11:52:50.807637 2, 0xFFFF, sum = 0
5503 11:52:50.810535 3, 0xFFFF, sum = 0
5504 11:52:50.810965 4, 0xFFFF, sum = 0
5505 11:52:50.814119 5, 0xFFFF, sum = 0
5506 11:52:50.814572 6, 0xFFFF, sum = 0
5507 11:52:50.817414 7, 0xFFFF, sum = 0
5508 11:52:50.817844 8, 0xFFFF, sum = 0
5509 11:52:50.820564 9, 0xFFFF, sum = 0
5510 11:52:50.820995 10, 0x0, sum = 1
5511 11:52:50.823983 11, 0x0, sum = 2
5512 11:52:50.824414 12, 0x0, sum = 3
5513 11:52:50.827413 13, 0x0, sum = 4
5514 11:52:50.827846 best_step = 11
5515 11:52:50.828182
5516 11:52:50.828518 ==
5517 11:52:50.830370 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 11:52:50.837300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 11:52:50.837744 ==
5520 11:52:50.838083 RX Vref Scan: 0
5521 11:52:50.838447
5522 11:52:50.840313 RX Vref 0 -> 0, step: 1
5523 11:52:50.840777
5524 11:52:50.843893 RX Delay -53 -> 252, step: 4
5525 11:52:50.847196 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5526 11:52:50.854077 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5527 11:52:50.857150 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5528 11:52:50.860269 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5529 11:52:50.863529 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5530 11:52:50.866740 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5531 11:52:50.873583 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5532 11:52:50.876745 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5533 11:52:50.880121 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5534 11:52:50.883443 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5535 11:52:50.887057 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5536 11:52:50.889993 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5537 11:52:50.897101 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5538 11:52:50.900174 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5539 11:52:50.903333 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5540 11:52:50.906842 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5541 11:52:50.907318 ==
5542 11:52:50.910456 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 11:52:50.916937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 11:52:50.917343 ==
5545 11:52:50.917691 DQS Delay:
5546 11:52:50.918021 DQS0 = 0, DQS1 = 0
5547 11:52:50.920039 DQM Delay:
5548 11:52:50.920537 DQM0 = 104, DQM1 = 92
5549 11:52:50.923426 DQ Delay:
5550 11:52:50.926496 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5551 11:52:50.930042 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5552 11:52:50.933057 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5553 11:52:50.936666 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5554 11:52:50.937205
5555 11:52:50.937625
5556 11:52:50.943220 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5557 11:52:50.946644 CH0 RK1: MR19=505, MR18=2708
5558 11:52:50.952990 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5559 11:52:50.956288 [RxdqsGatingPostProcess] freq 933
5560 11:52:50.962992 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5561 11:52:50.963590 best DQS0 dly(2T, 0.5T) = (0, 10)
5562 11:52:50.966330 best DQS1 dly(2T, 0.5T) = (0, 10)
5563 11:52:50.969607 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5564 11:52:50.973185 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5565 11:52:50.976519 best DQS0 dly(2T, 0.5T) = (0, 10)
5566 11:52:50.979802 best DQS1 dly(2T, 0.5T) = (0, 10)
5567 11:52:50.982882 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5568 11:52:50.986213 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5569 11:52:50.989669 Pre-setting of DQS Precalculation
5570 11:52:50.992913 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5571 11:52:50.996239 ==
5572 11:52:50.999766 Dram Type= 6, Freq= 0, CH_1, rank 0
5573 11:52:51.003347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 11:52:51.003810 ==
5575 11:52:51.006425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 11:52:51.012909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5577 11:52:51.016548 [CA 0] Center 37 (7~68) winsize 62
5578 11:52:51.020192 [CA 1] Center 37 (7~68) winsize 62
5579 11:52:51.023429 [CA 2] Center 35 (5~66) winsize 62
5580 11:52:51.026702 [CA 3] Center 34 (4~65) winsize 62
5581 11:52:51.029979 [CA 4] Center 34 (4~65) winsize 62
5582 11:52:51.033326 [CA 5] Center 34 (4~65) winsize 62
5583 11:52:51.033822
5584 11:52:51.036634 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5585 11:52:51.037229
5586 11:52:51.039708 [CATrainingPosCal] consider 1 rank data
5587 11:52:51.043283 u2DelayCellTimex100 = 270/100 ps
5588 11:52:51.046499 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5589 11:52:51.050174 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5590 11:52:51.056551 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5591 11:52:51.059941 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5592 11:52:51.063322 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5593 11:52:51.066635 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5594 11:52:51.067101
5595 11:52:51.070047 CA PerBit enable=1, Macro0, CA PI delay=34
5596 11:52:51.070575
5597 11:52:51.073422 [CBTSetCACLKResult] CA Dly = 34
5598 11:52:51.073850 CS Dly: 6 (0~37)
5599 11:52:51.076543 ==
5600 11:52:51.076936 Dram Type= 6, Freq= 0, CH_1, rank 1
5601 11:52:51.083645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 11:52:51.084103 ==
5603 11:52:51.086511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5604 11:52:51.093281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5605 11:52:51.096669 [CA 0] Center 38 (8~68) winsize 61
5606 11:52:51.100725 [CA 1] Center 38 (8~69) winsize 62
5607 11:52:51.103297 [CA 2] Center 36 (6~66) winsize 61
5608 11:52:51.106436 [CA 3] Center 35 (6~65) winsize 60
5609 11:52:51.109739 [CA 4] Center 35 (5~65) winsize 61
5610 11:52:51.113202 [CA 5] Center 35 (5~65) winsize 61
5611 11:52:51.113730
5612 11:52:51.116635 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5613 11:52:51.117085
5614 11:52:51.119833 [CATrainingPosCal] consider 2 rank data
5615 11:52:51.123511 u2DelayCellTimex100 = 270/100 ps
5616 11:52:51.126512 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5617 11:52:51.130085 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5618 11:52:51.136944 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5619 11:52:51.139837 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5620 11:52:51.143613 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5621 11:52:51.146590 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5622 11:52:51.147033
5623 11:52:51.149921 CA PerBit enable=1, Macro0, CA PI delay=35
5624 11:52:51.150368
5625 11:52:51.153114 [CBTSetCACLKResult] CA Dly = 35
5626 11:52:51.153662 CS Dly: 7 (0~39)
5627 11:52:51.154096
5628 11:52:51.156343 ----->DramcWriteLeveling(PI) begin...
5629 11:52:51.160033 ==
5630 11:52:51.163249 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 11:52:51.166473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 11:52:51.166932 ==
5633 11:52:51.170041 Write leveling (Byte 0): 28 => 28
5634 11:52:51.173084 Write leveling (Byte 1): 29 => 29
5635 11:52:51.176576 DramcWriteLeveling(PI) end<-----
5636 11:52:51.177028
5637 11:52:51.177526 ==
5638 11:52:51.180072 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 11:52:51.183152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 11:52:51.183611 ==
5641 11:52:51.186365 [Gating] SW mode calibration
5642 11:52:51.192926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5643 11:52:51.199761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5644 11:52:51.203386 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 11:52:51.206846 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 11:52:51.209501 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 11:52:51.216302 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 11:52:51.219567 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:52:51.222718 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5650 11:52:51.229447 0 14 24 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 1)
5651 11:52:51.232749 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
5652 11:52:51.236155 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 11:52:51.242682 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 11:52:51.246212 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 11:52:51.249489 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 11:52:51.256771 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:52:51.260178 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:52:51.263026 0 15 24 | B1->B0 | 2828 2f2f | 0 0 | (1 1) (0 0)
5659 11:52:51.270031 0 15 28 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
5660 11:52:51.272972 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:52:51.276629 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:52:51.282939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:52:51.286424 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:52:51.289848 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:52:51.296029 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:52:51.299612 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5667 11:52:51.302678 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:52:51.309332 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:52:51.313054 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:52:51.316158 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:52:51.319980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:52:51.325981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:52:51.329256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:52:51.332800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:52:51.339330 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:52:51.342800 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:52:51.346108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:52:51.352867 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:52:51.356013 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:52:51.359112 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:52:51.365827 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:52:51.369491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5683 11:52:51.372559 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 11:52:51.375855 Total UI for P1: 0, mck2ui 16
5685 11:52:51.379416 best dqsien dly found for B0: ( 1, 2, 24)
5686 11:52:51.382640 Total UI for P1: 0, mck2ui 16
5687 11:52:51.385919 best dqsien dly found for B1: ( 1, 2, 24)
5688 11:52:51.389301 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5689 11:52:51.392176 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5690 11:52:51.395545
5691 11:52:51.399085 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5692 11:52:51.402340 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5693 11:52:51.405775 [Gating] SW calibration Done
5694 11:52:51.406173 ==
5695 11:52:51.409120 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 11:52:51.412512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 11:52:51.412960 ==
5698 11:52:51.413331 RX Vref Scan: 0
5699 11:52:51.413711
5700 11:52:51.415939 RX Vref 0 -> 0, step: 1
5701 11:52:51.416386
5702 11:52:51.419156 RX Delay -80 -> 252, step: 8
5703 11:52:51.422718 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5704 11:52:51.425870 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5705 11:52:51.432233 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5706 11:52:51.435623 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5707 11:52:51.438912 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5708 11:52:51.442097 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5709 11:52:51.445661 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5710 11:52:51.449034 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5711 11:52:51.452478 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5712 11:52:51.458430 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5713 11:52:51.461830 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5714 11:52:51.465253 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5715 11:52:51.468273 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5716 11:52:51.471914 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5717 11:52:51.478976 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5718 11:52:51.481980 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5719 11:52:51.482577 ==
5720 11:52:51.485473 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:52:51.488472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:52:51.489039 ==
5723 11:52:51.491735 DQS Delay:
5724 11:52:51.492189 DQS0 = 0, DQS1 = 0
5725 11:52:51.492647 DQM Delay:
5726 11:52:51.495237 DQM0 = 102, DQM1 = 95
5727 11:52:51.495687 DQ Delay:
5728 11:52:51.498286 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5729 11:52:51.501876 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5730 11:52:51.505215 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5731 11:52:51.508265 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5732 11:52:51.508717
5733 11:52:51.509089
5734 11:52:51.511623 ==
5735 11:52:51.512199 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 11:52:51.518217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 11:52:51.518737 ==
5738 11:52:51.519102
5739 11:52:51.519437
5740 11:52:51.521720 TX Vref Scan disable
5741 11:52:51.522316 == TX Byte 0 ==
5742 11:52:51.524908 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5743 11:52:51.531491 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5744 11:52:51.531953 == TX Byte 1 ==
5745 11:52:51.534911 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5746 11:52:51.541248 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5747 11:52:51.541706 ==
5748 11:52:51.544830 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 11:52:51.547913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 11:52:51.548490 ==
5751 11:52:51.548986
5752 11:52:51.549456
5753 11:52:51.551725 TX Vref Scan disable
5754 11:52:51.555260 == TX Byte 0 ==
5755 11:52:51.558154 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5756 11:52:51.561935 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5757 11:52:51.564871 == TX Byte 1 ==
5758 11:52:51.568058 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5759 11:52:51.571541 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5760 11:52:51.571986
5761 11:52:51.572486 [DATLAT]
5762 11:52:51.574647 Freq=933, CH1 RK0
5763 11:52:51.575214
5764 11:52:51.575699 DATLAT Default: 0xd
5765 11:52:51.578081 0, 0xFFFF, sum = 0
5766 11:52:51.581820 1, 0xFFFF, sum = 0
5767 11:52:51.582449 2, 0xFFFF, sum = 0
5768 11:52:51.584819 3, 0xFFFF, sum = 0
5769 11:52:51.585405 4, 0xFFFF, sum = 0
5770 11:52:51.588098 5, 0xFFFF, sum = 0
5771 11:52:51.588679 6, 0xFFFF, sum = 0
5772 11:52:51.591560 7, 0xFFFF, sum = 0
5773 11:52:51.592021 8, 0xFFFF, sum = 0
5774 11:52:51.595047 9, 0xFFFF, sum = 0
5775 11:52:51.595501 10, 0x0, sum = 1
5776 11:52:51.598321 11, 0x0, sum = 2
5777 11:52:51.598823 12, 0x0, sum = 3
5778 11:52:51.601446 13, 0x0, sum = 4
5779 11:52:51.601907 best_step = 11
5780 11:52:51.602267
5781 11:52:51.602672 ==
5782 11:52:51.604645 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 11:52:51.607925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 11:52:51.608513 ==
5785 11:52:51.611527 RX Vref Scan: 1
5786 11:52:51.612093
5787 11:52:51.614785 RX Vref 0 -> 0, step: 1
5788 11:52:51.615250
5789 11:52:51.615611 RX Delay -53 -> 252, step: 4
5790 11:52:51.615956
5791 11:52:51.618111 Set Vref, RX VrefLevel [Byte0]: 51
5792 11:52:51.621118 [Byte1]: 55
5793 11:52:51.625815
5794 11:52:51.626267 Final RX Vref Byte 0 = 51 to rank0
5795 11:52:51.629358 Final RX Vref Byte 1 = 55 to rank0
5796 11:52:51.632689 Final RX Vref Byte 0 = 51 to rank1
5797 11:52:51.636003 Final RX Vref Byte 1 = 55 to rank1==
5798 11:52:51.639751 Dram Type= 6, Freq= 0, CH_1, rank 0
5799 11:52:51.645878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:52:51.646444 ==
5801 11:52:51.646805 DQS Delay:
5802 11:52:51.647130 DQS0 = 0, DQS1 = 0
5803 11:52:51.649504 DQM Delay:
5804 11:52:51.649906 DQM0 = 104, DQM1 = 97
5805 11:52:51.652385 DQ Delay:
5806 11:52:51.655848 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5807 11:52:51.659092 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5808 11:52:51.662599 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5809 11:52:51.665942 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =104
5810 11:52:51.666534
5811 11:52:51.666927
5812 11:52:51.672731 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5813 11:52:51.675640 CH1 RK0: MR19=505, MR18=1A33
5814 11:52:51.682555 CH1_RK0: MR19=0x505, MR18=0x1A33, DQSOSC=405, MR23=63, INC=66, DEC=44
5815 11:52:51.683106
5816 11:52:51.685793 ----->DramcWriteLeveling(PI) begin...
5817 11:52:51.686210 ==
5818 11:52:51.688993 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 11:52:51.692717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 11:52:51.693175 ==
5821 11:52:51.696081 Write leveling (Byte 0): 27 => 27
5822 11:52:51.699275 Write leveling (Byte 1): 28 => 28
5823 11:52:51.702826 DramcWriteLeveling(PI) end<-----
5824 11:52:51.703268
5825 11:52:51.703621 ==
5826 11:52:51.705958 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 11:52:51.709227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 11:52:51.712436 ==
5829 11:52:51.712893 [Gating] SW mode calibration
5830 11:52:51.722477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5831 11:52:51.725745 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5832 11:52:51.729004 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 11:52:51.735791 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:52:51.739200 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 11:52:51.742750 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 11:52:51.748810 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 11:52:51.752208 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:52:51.755595 0 14 24 | B1->B0 | 2f2f 3131 | 1 0 | (1 1) (0 1)
5839 11:52:51.762019 0 14 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
5840 11:52:51.765378 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5841 11:52:51.768868 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 11:52:51.775055 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 11:52:51.778419 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 11:52:51.781691 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:52:51.788585 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:52:51.791615 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5847 11:52:51.794732 0 15 28 | B1->B0 | 4242 3737 | 0 0 | (0 0) (0 0)
5848 11:52:51.801859 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 11:52:51.805039 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:52:51.808585 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:52:51.814768 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:52:51.818126 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:52:51.821362 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5854 11:52:51.828056 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5855 11:52:51.831183 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5856 11:52:51.834496 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:52:51.841029 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:52:51.844678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:52:51.847762 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:52:51.854349 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:52:51.858035 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:52:51.861209 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:52:51.867653 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:52:51.871061 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:52:51.874182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:52:51.880720 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:52:51.884627 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:52:51.887226 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:52:51.894322 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:52:51.897305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5871 11:52:51.900921 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5872 11:52:51.904255 Total UI for P1: 0, mck2ui 16
5873 11:52:51.907386 best dqsien dly found for B1: ( 1, 2, 24)
5874 11:52:51.911082 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 11:52:51.914256 Total UI for P1: 0, mck2ui 16
5876 11:52:51.917425 best dqsien dly found for B0: ( 1, 2, 26)
5877 11:52:51.923651 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5878 11:52:51.926980 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5879 11:52:51.927062
5880 11:52:51.930424 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5881 11:52:51.933759 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5882 11:52:51.937164 [Gating] SW calibration Done
5883 11:52:51.937246 ==
5884 11:52:51.940464 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:52:51.944010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:52:51.944092 ==
5887 11:52:51.947117 RX Vref Scan: 0
5888 11:52:51.947199
5889 11:52:51.947265 RX Vref 0 -> 0, step: 1
5890 11:52:51.947325
5891 11:52:51.951546 RX Delay -80 -> 252, step: 8
5892 11:52:51.954061 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5893 11:52:51.960514 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5894 11:52:51.963465 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5895 11:52:51.966862 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5896 11:52:51.970340 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5897 11:52:51.973199 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5898 11:52:51.976843 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5899 11:52:51.983428 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5900 11:52:51.986808 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5901 11:52:51.989990 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5902 11:52:51.993244 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5903 11:52:51.996975 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5904 11:52:51.999982 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5905 11:52:52.006440 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5906 11:52:52.010089 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5907 11:52:52.013276 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5908 11:52:52.013358 ==
5909 11:52:52.016721 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:52:52.019827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:52:52.019909 ==
5912 11:52:52.022961 DQS Delay:
5913 11:52:52.023042 DQS0 = 0, DQS1 = 0
5914 11:52:52.026439 DQM Delay:
5915 11:52:52.026520 DQM0 = 102, DQM1 = 96
5916 11:52:52.026585 DQ Delay:
5917 11:52:52.029810 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5918 11:52:52.033025 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =99
5919 11:52:52.036275 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5920 11:52:52.039873 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5921 11:52:52.043142
5922 11:52:52.043223
5923 11:52:52.043288 ==
5924 11:52:52.046410 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 11:52:52.049975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 11:52:52.050057 ==
5927 11:52:52.050122
5928 11:52:52.050181
5929 11:52:52.052912 TX Vref Scan disable
5930 11:52:52.052994 == TX Byte 0 ==
5931 11:52:52.059512 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5932 11:52:52.062986 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5933 11:52:52.063069 == TX Byte 1 ==
5934 11:52:52.069619 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5935 11:52:52.072750 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5936 11:52:52.072833 ==
5937 11:52:52.076061 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 11:52:52.079898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 11:52:52.079980 ==
5940 11:52:52.080045
5941 11:52:52.080105
5942 11:52:52.082662 TX Vref Scan disable
5943 11:52:52.086202 == TX Byte 0 ==
5944 11:52:52.089865 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 11:52:52.092979 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 11:52:52.096212 == TX Byte 1 ==
5947 11:52:52.099342 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5948 11:52:52.102838 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5949 11:52:52.102920
5950 11:52:52.106094 [DATLAT]
5951 11:52:52.106176 Freq=933, CH1 RK1
5952 11:52:52.106241
5953 11:52:52.109561 DATLAT Default: 0xb
5954 11:52:52.109643 0, 0xFFFF, sum = 0
5955 11:52:52.113247 1, 0xFFFF, sum = 0
5956 11:52:52.113331 2, 0xFFFF, sum = 0
5957 11:52:52.116009 3, 0xFFFF, sum = 0
5958 11:52:52.116092 4, 0xFFFF, sum = 0
5959 11:52:52.119759 5, 0xFFFF, sum = 0
5960 11:52:52.119843 6, 0xFFFF, sum = 0
5961 11:52:52.122949 7, 0xFFFF, sum = 0
5962 11:52:52.123032 8, 0xFFFF, sum = 0
5963 11:52:52.126075 9, 0xFFFF, sum = 0
5964 11:52:52.126158 10, 0x0, sum = 1
5965 11:52:52.129835 11, 0x0, sum = 2
5966 11:52:52.129918 12, 0x0, sum = 3
5967 11:52:52.132695 13, 0x0, sum = 4
5968 11:52:52.132778 best_step = 11
5969 11:52:52.132842
5970 11:52:52.132901 ==
5971 11:52:52.136306 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 11:52:52.142725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 11:52:52.142808 ==
5974 11:52:52.142873 RX Vref Scan: 0
5975 11:52:52.142932
5976 11:52:52.146177 RX Vref 0 -> 0, step: 1
5977 11:52:52.146258
5978 11:52:52.149690 RX Delay -53 -> 252, step: 4
5979 11:52:52.152528 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5980 11:52:52.156171 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5981 11:52:52.162688 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5982 11:52:52.166188 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5983 11:52:52.169266 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5984 11:52:52.172699 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5985 11:52:52.176363 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5986 11:52:52.182693 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5987 11:52:52.186149 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5988 11:52:52.189396 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5989 11:52:52.192831 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5990 11:52:52.195940 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5991 11:52:52.199500 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5992 11:52:52.205817 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5993 11:52:52.209302 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5994 11:52:52.212453 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5995 11:52:52.212535 ==
5996 11:52:52.216071 Dram Type= 6, Freq= 0, CH_1, rank 1
5997 11:52:52.219380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5998 11:52:52.219463 ==
5999 11:52:52.222375 DQS Delay:
6000 11:52:52.222465 DQS0 = 0, DQS1 = 0
6001 11:52:52.225745 DQM Delay:
6002 11:52:52.225827 DQM0 = 105, DQM1 = 98
6003 11:52:52.229135 DQ Delay:
6004 11:52:52.232355 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
6005 11:52:52.235612 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
6006 11:52:52.238899 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
6007 11:52:52.242291 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
6008 11:52:52.242373
6009 11:52:52.242474
6010 11:52:52.249181 [DQSOSCAuto] RK1, (LSB)MR18= 0x2603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
6011 11:52:52.252702 CH1 RK1: MR19=505, MR18=2603
6012 11:52:52.259110 CH1_RK1: MR19=0x505, MR18=0x2603, DQSOSC=409, MR23=63, INC=64, DEC=43
6013 11:52:52.262325 [RxdqsGatingPostProcess] freq 933
6014 11:52:52.265780 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6015 11:52:52.269582 best DQS0 dly(2T, 0.5T) = (0, 10)
6016 11:52:52.272653 best DQS1 dly(2T, 0.5T) = (0, 10)
6017 11:52:52.276014 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6018 11:52:52.279044 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6019 11:52:52.282285 best DQS0 dly(2T, 0.5T) = (0, 10)
6020 11:52:52.285860 best DQS1 dly(2T, 0.5T) = (0, 10)
6021 11:52:52.289220 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6022 11:52:52.292328 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6023 11:52:52.295636 Pre-setting of DQS Precalculation
6024 11:52:52.299135 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6025 11:52:52.309222 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6026 11:52:52.316172 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6027 11:52:52.316255
6028 11:52:52.316319
6029 11:52:52.319433 [Calibration Summary] 1866 Mbps
6030 11:52:52.319515 CH 0, Rank 0
6031 11:52:52.322338 SW Impedance : PASS
6032 11:52:52.322463 DUTY Scan : NO K
6033 11:52:52.325708 ZQ Calibration : PASS
6034 11:52:52.329060 Jitter Meter : NO K
6035 11:52:52.329143 CBT Training : PASS
6036 11:52:52.332244 Write leveling : PASS
6037 11:52:52.335570 RX DQS gating : PASS
6038 11:52:52.335652 RX DQ/DQS(RDDQC) : PASS
6039 11:52:52.338871 TX DQ/DQS : PASS
6040 11:52:52.338978 RX DATLAT : PASS
6041 11:52:52.342222 RX DQ/DQS(Engine): PASS
6042 11:52:52.345459 TX OE : NO K
6043 11:52:52.345566 All Pass.
6044 11:52:52.345665
6045 11:52:52.349431 CH 0, Rank 1
6046 11:52:52.349539 SW Impedance : PASS
6047 11:52:52.352228 DUTY Scan : NO K
6048 11:52:52.352310 ZQ Calibration : PASS
6049 11:52:52.355869 Jitter Meter : NO K
6050 11:52:52.358879 CBT Training : PASS
6051 11:52:52.358961 Write leveling : PASS
6052 11:52:52.362352 RX DQS gating : PASS
6053 11:52:52.365375 RX DQ/DQS(RDDQC) : PASS
6054 11:52:52.365457 TX DQ/DQS : PASS
6055 11:52:52.368760 RX DATLAT : PASS
6056 11:52:52.372651 RX DQ/DQS(Engine): PASS
6057 11:52:52.372733 TX OE : NO K
6058 11:52:52.375624 All Pass.
6059 11:52:52.375705
6060 11:52:52.375770 CH 1, Rank 0
6061 11:52:52.379035 SW Impedance : PASS
6062 11:52:52.379117 DUTY Scan : NO K
6063 11:52:52.382136 ZQ Calibration : PASS
6064 11:52:52.385219 Jitter Meter : NO K
6065 11:52:52.385301 CBT Training : PASS
6066 11:52:52.388914 Write leveling : PASS
6067 11:52:52.392329 RX DQS gating : PASS
6068 11:52:52.392411 RX DQ/DQS(RDDQC) : PASS
6069 11:52:52.395661 TX DQ/DQS : PASS
6070 11:52:52.395743 RX DATLAT : PASS
6071 11:52:52.398763 RX DQ/DQS(Engine): PASS
6072 11:52:52.402123 TX OE : NO K
6073 11:52:52.402205 All Pass.
6074 11:52:52.402271
6075 11:52:52.402331 CH 1, Rank 1
6076 11:52:52.405395 SW Impedance : PASS
6077 11:52:52.409384 DUTY Scan : NO K
6078 11:52:52.409466 ZQ Calibration : PASS
6079 11:52:52.412339 Jitter Meter : NO K
6080 11:52:52.415530 CBT Training : PASS
6081 11:52:52.415612 Write leveling : PASS
6082 11:52:52.418956 RX DQS gating : PASS
6083 11:52:52.422005 RX DQ/DQS(RDDQC) : PASS
6084 11:52:52.422086 TX DQ/DQS : PASS
6085 11:52:52.425250 RX DATLAT : PASS
6086 11:52:52.428622 RX DQ/DQS(Engine): PASS
6087 11:52:52.428705 TX OE : NO K
6088 11:52:52.428770 All Pass.
6089 11:52:52.432045
6090 11:52:52.432127 DramC Write-DBI off
6091 11:52:52.435805 PER_BANK_REFRESH: Hybrid Mode
6092 11:52:52.435888 TX_TRACKING: ON
6093 11:52:52.445297 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6094 11:52:52.448789 [FAST_K] Save calibration result to emmc
6095 11:52:52.452625 dramc_set_vcore_voltage set vcore to 650000
6096 11:52:52.455764 Read voltage for 400, 6
6097 11:52:52.455847 Vio18 = 0
6098 11:52:52.458878 Vcore = 650000
6099 11:52:52.458960 Vdram = 0
6100 11:52:52.459026 Vddq = 0
6101 11:52:52.459085 Vmddr = 0
6102 11:52:52.465500 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6103 11:52:52.468874 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6104 11:52:52.472115 MEM_TYPE=3, freq_sel=20
6105 11:52:52.475540 sv_algorithm_assistance_LP4_800
6106 11:52:52.478987 ============ PULL DRAM RESETB DOWN ============
6107 11:52:52.485433 ========== PULL DRAM RESETB DOWN end =========
6108 11:52:52.489020 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6109 11:52:52.491823 ===================================
6110 11:52:52.495669 LPDDR4 DRAM CONFIGURATION
6111 11:52:52.498675 ===================================
6112 11:52:52.498759 EX_ROW_EN[0] = 0x0
6113 11:52:52.501819 EX_ROW_EN[1] = 0x0
6114 11:52:52.501903 LP4Y_EN = 0x0
6115 11:52:52.505534 WORK_FSP = 0x0
6116 11:52:52.505617 WL = 0x2
6117 11:52:52.508434 RL = 0x2
6118 11:52:52.508518 BL = 0x2
6119 11:52:52.511914 RPST = 0x0
6120 11:52:52.511997 RD_PRE = 0x0
6121 11:52:52.515046 WR_PRE = 0x1
6122 11:52:52.518414 WR_PST = 0x0
6123 11:52:52.518498 DBI_WR = 0x0
6124 11:52:52.522114 DBI_RD = 0x0
6125 11:52:52.522197 OTF = 0x1
6126 11:52:52.525105 ===================================
6127 11:52:52.528305 ===================================
6128 11:52:52.528389 ANA top config
6129 11:52:52.532435 ===================================
6130 11:52:52.535068 DLL_ASYNC_EN = 0
6131 11:52:52.538607 ALL_SLAVE_EN = 1
6132 11:52:52.541493 NEW_RANK_MODE = 1
6133 11:52:52.544867 DLL_IDLE_MODE = 1
6134 11:52:52.544972 LP45_APHY_COMB_EN = 1
6135 11:52:52.548150 TX_ODT_DIS = 1
6136 11:52:52.551438 NEW_8X_MODE = 1
6137 11:52:52.554770 ===================================
6138 11:52:52.558152 ===================================
6139 11:52:52.561482 data_rate = 800
6140 11:52:52.564808 CKR = 1
6141 11:52:52.568334 DQ_P2S_RATIO = 4
6142 11:52:52.568412 ===================================
6143 11:52:52.571650 CA_P2S_RATIO = 4
6144 11:52:52.574868 DQ_CA_OPEN = 0
6145 11:52:52.578061 DQ_SEMI_OPEN = 1
6146 11:52:52.581530 CA_SEMI_OPEN = 1
6147 11:52:52.584947 CA_FULL_RATE = 0
6148 11:52:52.585016 DQ_CKDIV4_EN = 0
6149 11:52:52.588199 CA_CKDIV4_EN = 1
6150 11:52:52.591407 CA_PREDIV_EN = 0
6151 11:52:52.594885 PH8_DLY = 0
6152 11:52:52.598247 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6153 11:52:52.601277 DQ_AAMCK_DIV = 0
6154 11:52:52.601348 CA_AAMCK_DIV = 0
6155 11:52:52.604954 CA_ADMCK_DIV = 4
6156 11:52:52.608123 DQ_TRACK_CA_EN = 0
6157 11:52:52.611442 CA_PICK = 800
6158 11:52:52.614742 CA_MCKIO = 400
6159 11:52:52.617786 MCKIO_SEMI = 400
6160 11:52:52.621340 PLL_FREQ = 3016
6161 11:52:52.624503 DQ_UI_PI_RATIO = 32
6162 11:52:52.624577 CA_UI_PI_RATIO = 32
6163 11:52:52.627797 ===================================
6164 11:52:52.631406 ===================================
6165 11:52:52.634971 memory_type:LPDDR4
6166 11:52:52.637960 GP_NUM : 10
6167 11:52:52.638039 SRAM_EN : 1
6168 11:52:52.641161 MD32_EN : 0
6169 11:52:52.644659 ===================================
6170 11:52:52.647862 [ANA_INIT] >>>>>>>>>>>>>>
6171 11:52:52.647938 <<<<<< [CONFIGURE PHASE]: ANA_TX
6172 11:52:52.654471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6173 11:52:52.658067 ===================================
6174 11:52:52.658184 data_rate = 800,PCW = 0X7400
6175 11:52:52.661328 ===================================
6176 11:52:52.664738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6177 11:52:52.671120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 11:52:52.681625 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 11:52:52.687527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6180 11:52:52.691059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6181 11:52:52.694277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6182 11:52:52.697879 [ANA_INIT] flow start
6183 11:52:52.697988 [ANA_INIT] PLL >>>>>>>>
6184 11:52:52.700979 [ANA_INIT] PLL <<<<<<<<
6185 11:52:52.704394 [ANA_INIT] MIDPI >>>>>>>>
6186 11:52:52.704496 [ANA_INIT] MIDPI <<<<<<<<
6187 11:52:52.707695 [ANA_INIT] DLL >>>>>>>>
6188 11:52:52.711247 [ANA_INIT] flow end
6189 11:52:52.714440 ============ LP4 DIFF to SE enter ============
6190 11:52:52.717451 ============ LP4 DIFF to SE exit ============
6191 11:52:52.721031 [ANA_INIT] <<<<<<<<<<<<<
6192 11:52:52.724335 [Flow] Enable top DCM control >>>>>
6193 11:52:52.727372 [Flow] Enable top DCM control <<<<<
6194 11:52:52.730980 Enable DLL master slave shuffle
6195 11:52:52.734303 ==============================================================
6196 11:52:52.737833 Gating Mode config
6197 11:52:52.741091 ==============================================================
6198 11:52:52.744289 Config description:
6199 11:52:52.754418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6200 11:52:52.760679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6201 11:52:52.764278 SELPH_MODE 0: By rank 1: By Phase
6202 11:52:52.770754 ==============================================================
6203 11:52:52.774301 GAT_TRACK_EN = 0
6204 11:52:52.777489 RX_GATING_MODE = 2
6205 11:52:52.780957 RX_GATING_TRACK_MODE = 2
6206 11:52:52.784115 SELPH_MODE = 1
6207 11:52:52.787708 PICG_EARLY_EN = 1
6208 11:52:52.787782 VALID_LAT_VALUE = 1
6209 11:52:52.794205 ==============================================================
6210 11:52:52.797591 Enter into Gating configuration >>>>
6211 11:52:52.800895 Exit from Gating configuration <<<<
6212 11:52:52.804575 Enter into DVFS_PRE_config >>>>>
6213 11:52:52.814390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6214 11:52:52.817645 Exit from DVFS_PRE_config <<<<<
6215 11:52:52.820785 Enter into PICG configuration >>>>
6216 11:52:52.824187 Exit from PICG configuration <<<<
6217 11:52:52.827695 [RX_INPUT] configuration >>>>>
6218 11:52:52.830977 [RX_INPUT] configuration <<<<<
6219 11:52:52.834302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6220 11:52:52.840798 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6221 11:52:52.847528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 11:52:52.854415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 11:52:52.861001 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 11:52:52.864100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 11:52:52.870766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6226 11:52:52.874271 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6227 11:52:52.877353 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6228 11:52:52.881312 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6229 11:52:52.887465 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6230 11:52:52.890823 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 11:52:52.893944 ===================================
6232 11:52:52.897520 LPDDR4 DRAM CONFIGURATION
6233 11:52:52.900522 ===================================
6234 11:52:52.900605 EX_ROW_EN[0] = 0x0
6235 11:52:52.904149 EX_ROW_EN[1] = 0x0
6236 11:52:52.904231 LP4Y_EN = 0x0
6237 11:52:52.907227 WORK_FSP = 0x0
6238 11:52:52.907309 WL = 0x2
6239 11:52:52.911008 RL = 0x2
6240 11:52:52.911091 BL = 0x2
6241 11:52:52.914256 RPST = 0x0
6242 11:52:52.914339 RD_PRE = 0x0
6243 11:52:52.917170 WR_PRE = 0x1
6244 11:52:52.917253 WR_PST = 0x0
6245 11:52:52.921163 DBI_WR = 0x0
6246 11:52:52.924184 DBI_RD = 0x0
6247 11:52:52.924275 OTF = 0x1
6248 11:52:52.927144 ===================================
6249 11:52:52.930459 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6250 11:52:52.933883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6251 11:52:52.940660 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6252 11:52:52.944133 ===================================
6253 11:52:52.947331 LPDDR4 DRAM CONFIGURATION
6254 11:52:52.950432 ===================================
6255 11:52:52.950554 EX_ROW_EN[0] = 0x10
6256 11:52:52.954045 EX_ROW_EN[1] = 0x0
6257 11:52:52.954128 LP4Y_EN = 0x0
6258 11:52:52.957244 WORK_FSP = 0x0
6259 11:52:52.957327 WL = 0x2
6260 11:52:52.960575 RL = 0x2
6261 11:52:52.960658 BL = 0x2
6262 11:52:52.963902 RPST = 0x0
6263 11:52:52.963985 RD_PRE = 0x0
6264 11:52:52.966939 WR_PRE = 0x1
6265 11:52:52.967028 WR_PST = 0x0
6266 11:52:52.970579 DBI_WR = 0x0
6267 11:52:52.970662 DBI_RD = 0x0
6268 11:52:52.973812 OTF = 0x1
6269 11:52:52.977506 ===================================
6270 11:52:52.984289 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6271 11:52:52.987303 nWR fixed to 30
6272 11:52:52.990930 [ModeRegInit_LP4] CH0 RK0
6273 11:52:52.991013 [ModeRegInit_LP4] CH0 RK1
6274 11:52:52.994010 [ModeRegInit_LP4] CH1 RK0
6275 11:52:52.997137 [ModeRegInit_LP4] CH1 RK1
6276 11:52:52.997219 match AC timing 19
6277 11:52:53.003862 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6278 11:52:53.007432 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6279 11:52:53.010482 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6280 11:52:53.017051 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6281 11:52:53.020546 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6282 11:52:53.020630 ==
6283 11:52:53.023747 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 11:52:53.027388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 11:52:53.027472 ==
6286 11:52:53.033885 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 11:52:53.040327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 11:52:53.043652 [CA 0] Center 36 (8~64) winsize 57
6289 11:52:53.047212 [CA 1] Center 36 (8~64) winsize 57
6290 11:52:53.047295 [CA 2] Center 36 (8~64) winsize 57
6291 11:52:53.050414 [CA 3] Center 36 (8~64) winsize 57
6292 11:52:53.053621 [CA 4] Center 36 (8~64) winsize 57
6293 11:52:53.057297 [CA 5] Center 36 (8~64) winsize 57
6294 11:52:53.057395
6295 11:52:53.060510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 11:52:53.060580
6297 11:52:53.067215 [CATrainingPosCal] consider 1 rank data
6298 11:52:53.067315 u2DelayCellTimex100 = 270/100 ps
6299 11:52:53.073645 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:52:53.077070 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:52:53.080329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:52:53.083584 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:52:53.086809 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:52:53.089994 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:52:53.090093
6306 11:52:53.093291 CA PerBit enable=1, Macro0, CA PI delay=36
6307 11:52:53.093390
6308 11:52:53.097084 [CBTSetCACLKResult] CA Dly = 36
6309 11:52:53.100078 CS Dly: 1 (0~32)
6310 11:52:53.100178 ==
6311 11:52:53.103567 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 11:52:53.106810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 11:52:53.106896 ==
6314 11:52:53.113307 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 11:52:53.116820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6316 11:52:53.120146 [CA 0] Center 36 (8~64) winsize 57
6317 11:52:53.123553 [CA 1] Center 36 (8~64) winsize 57
6318 11:52:53.126837 [CA 2] Center 36 (8~64) winsize 57
6319 11:52:53.129961 [CA 3] Center 36 (8~64) winsize 57
6320 11:52:53.133662 [CA 4] Center 36 (8~64) winsize 57
6321 11:52:53.136808 [CA 5] Center 36 (8~64) winsize 57
6322 11:52:53.136906
6323 11:52:53.140160 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6324 11:52:53.140235
6325 11:52:53.143162 [CATrainingPosCal] consider 2 rank data
6326 11:52:53.146705 u2DelayCellTimex100 = 270/100 ps
6327 11:52:53.150513 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:52:53.153345 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:52:53.156849 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:52:53.159817 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:52:53.166652 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:52:53.170039 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:52:53.170141
6334 11:52:53.173760 CA PerBit enable=1, Macro0, CA PI delay=36
6335 11:52:53.173835
6336 11:52:53.176784 [CBTSetCACLKResult] CA Dly = 36
6337 11:52:53.176869 CS Dly: 1 (0~32)
6338 11:52:53.176936
6339 11:52:53.179945 ----->DramcWriteLeveling(PI) begin...
6340 11:52:53.180015 ==
6341 11:52:53.183165 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:52:53.189748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:52:53.189830 ==
6344 11:52:53.193393 Write leveling (Byte 0): 40 => 8
6345 11:52:53.193476 Write leveling (Byte 1): 32 => 0
6346 11:52:53.196461 DramcWriteLeveling(PI) end<-----
6347 11:52:53.196557
6348 11:52:53.200173 ==
6349 11:52:53.200269 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 11:52:53.206414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 11:52:53.206525 ==
6352 11:52:53.210016 [Gating] SW mode calibration
6353 11:52:53.216681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6354 11:52:53.219842 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6355 11:52:53.226207 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 11:52:53.229704 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 11:52:53.232989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 11:52:53.239725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 11:52:53.243192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 11:52:53.246362 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 11:52:53.253004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 11:52:53.256312 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 11:52:53.259484 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 11:52:53.262931 Total UI for P1: 0, mck2ui 16
6365 11:52:53.266230 best dqsien dly found for B0: ( 0, 14, 24)
6366 11:52:53.270207 Total UI for P1: 0, mck2ui 16
6367 11:52:53.272871 best dqsien dly found for B1: ( 0, 14, 24)
6368 11:52:53.276524 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6369 11:52:53.279508 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6370 11:52:53.279588
6371 11:52:53.282971 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 11:52:53.289348 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 11:52:53.289454 [Gating] SW calibration Done
6374 11:52:53.292866 ==
6375 11:52:53.292968 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 11:52:53.299316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 11:52:53.299391 ==
6378 11:52:53.299462 RX Vref Scan: 0
6379 11:52:53.299552
6380 11:52:53.302652 RX Vref 0 -> 0, step: 1
6381 11:52:53.302725
6382 11:52:53.305946 RX Delay -410 -> 252, step: 16
6383 11:52:53.309666 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6384 11:52:53.312527 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6385 11:52:53.319248 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6386 11:52:53.322787 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6387 11:52:53.325986 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6388 11:52:53.329395 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6389 11:52:53.335940 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6390 11:52:53.339560 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6391 11:52:53.342605 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6392 11:52:53.345945 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6393 11:52:53.352540 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6394 11:52:53.355692 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6395 11:52:53.359298 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6396 11:52:53.362345 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6397 11:52:53.369355 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6398 11:52:53.372184 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6399 11:52:53.372294 ==
6400 11:52:53.375803 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 11:52:53.378906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 11:52:53.378983 ==
6403 11:52:53.382267 DQS Delay:
6404 11:52:53.382366 DQS0 = 19, DQS1 = 43
6405 11:52:53.385554 DQM Delay:
6406 11:52:53.385634 DQM0 = 5, DQM1 = 13
6407 11:52:53.385696 DQ Delay:
6408 11:52:53.388826 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6409 11:52:53.392245 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6410 11:52:53.395539 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6411 11:52:53.398916 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6412 11:52:53.398993
6413 11:52:53.399056
6414 11:52:53.399116 ==
6415 11:52:53.402259 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 11:52:53.406007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 11:52:53.409355 ==
6418 11:52:53.409456
6419 11:52:53.409545
6420 11:52:53.409640 TX Vref Scan disable
6421 11:52:53.412361 == TX Byte 0 ==
6422 11:52:53.415666 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6423 11:52:53.419031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6424 11:52:53.422285 == TX Byte 1 ==
6425 11:52:53.425878 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6426 11:52:53.429059 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6427 11:52:53.429142 ==
6428 11:52:53.432364 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 11:52:53.439331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 11:52:53.439414 ==
6431 11:52:53.439479
6432 11:52:53.439538
6433 11:52:53.439595 TX Vref Scan disable
6434 11:52:53.442293 == TX Byte 0 ==
6435 11:52:53.445705 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 11:52:53.449079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 11:52:53.452535 == TX Byte 1 ==
6438 11:52:53.456087 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 11:52:53.458780 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 11:52:53.458855
6441 11:52:53.462264 [DATLAT]
6442 11:52:53.462360 Freq=400, CH0 RK0
6443 11:52:53.462478
6444 11:52:53.465825 DATLAT Default: 0xf
6445 11:52:53.465928 0, 0xFFFF, sum = 0
6446 11:52:53.469059 1, 0xFFFF, sum = 0
6447 11:52:53.469162 2, 0xFFFF, sum = 0
6448 11:52:53.472243 3, 0xFFFF, sum = 0
6449 11:52:53.472347 4, 0xFFFF, sum = 0
6450 11:52:53.475617 5, 0xFFFF, sum = 0
6451 11:52:53.475691 6, 0xFFFF, sum = 0
6452 11:52:53.478944 7, 0xFFFF, sum = 0
6453 11:52:53.479016 8, 0xFFFF, sum = 0
6454 11:52:53.482501 9, 0xFFFF, sum = 0
6455 11:52:53.482576 10, 0xFFFF, sum = 0
6456 11:52:53.485795 11, 0xFFFF, sum = 0
6457 11:52:53.488848 12, 0xFFFF, sum = 0
6458 11:52:53.488932 13, 0x0, sum = 1
6459 11:52:53.488999 14, 0x0, sum = 2
6460 11:52:53.492992 15, 0x0, sum = 3
6461 11:52:53.493083 16, 0x0, sum = 4
6462 11:52:53.495875 best_step = 14
6463 11:52:53.495957
6464 11:52:53.496021 ==
6465 11:52:53.498910 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 11:52:53.502335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 11:52:53.502425 ==
6468 11:52:53.505411 RX Vref Scan: 1
6469 11:52:53.505493
6470 11:52:53.505557 RX Vref 0 -> 0, step: 1
6471 11:52:53.505617
6472 11:52:53.508874 RX Delay -327 -> 252, step: 8
6473 11:52:53.508989
6474 11:52:53.512290 Set Vref, RX VrefLevel [Byte0]: 57
6475 11:52:53.515753 [Byte1]: 48
6476 11:52:53.520193
6477 11:52:53.520298 Final RX Vref Byte 0 = 57 to rank0
6478 11:52:53.523700 Final RX Vref Byte 1 = 48 to rank0
6479 11:52:53.526881 Final RX Vref Byte 0 = 57 to rank1
6480 11:52:53.530882 Final RX Vref Byte 1 = 48 to rank1==
6481 11:52:53.533791 Dram Type= 6, Freq= 0, CH_0, rank 0
6482 11:52:53.540115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 11:52:53.540230 ==
6484 11:52:53.540326 DQS Delay:
6485 11:52:53.543811 DQS0 = 28, DQS1 = 48
6486 11:52:53.543882 DQM Delay:
6487 11:52:53.543942 DQM0 = 12, DQM1 = 16
6488 11:52:53.546801 DQ Delay:
6489 11:52:53.550351 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6490 11:52:53.550487 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6491 11:52:53.553668 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6492 11:52:53.557077 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6493 11:52:53.560091
6494 11:52:53.560162
6495 11:52:53.567098 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6496 11:52:53.570178 CH0 RK0: MR19=C0C, MR18=B1AA
6497 11:52:53.576704 CH0_RK0: MR19=0xC0C, MR18=0xB1AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6498 11:52:53.576788 ==
6499 11:52:53.580055 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 11:52:53.583592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:52:53.583676 ==
6502 11:52:53.586908 [Gating] SW mode calibration
6503 11:52:53.593482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6504 11:52:53.599945 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6505 11:52:53.603536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 11:52:53.607026 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 11:52:53.613624 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 11:52:53.616846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 11:52:53.620082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 11:52:53.623481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 11:52:53.629854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 11:52:53.633521 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:52:53.636874 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 11:52:53.640006 Total UI for P1: 0, mck2ui 16
6515 11:52:53.643427 best dqsien dly found for B0: ( 0, 14, 24)
6516 11:52:53.646697 Total UI for P1: 0, mck2ui 16
6517 11:52:53.649951 best dqsien dly found for B1: ( 0, 14, 24)
6518 11:52:53.653030 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6519 11:52:53.659708 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6520 11:52:53.659791
6521 11:52:53.663263 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 11:52:53.666812 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 11:52:53.669926 [Gating] SW calibration Done
6524 11:52:53.670008 ==
6525 11:52:53.673114 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 11:52:53.676589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 11:52:53.676672 ==
6528 11:52:53.679705 RX Vref Scan: 0
6529 11:52:53.679787
6530 11:52:53.679853 RX Vref 0 -> 0, step: 1
6531 11:52:53.679914
6532 11:52:53.683249 RX Delay -410 -> 252, step: 16
6533 11:52:53.686606 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6534 11:52:53.693076 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6535 11:52:53.696379 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6536 11:52:53.699804 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6537 11:52:53.703432 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6538 11:52:53.709759 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6539 11:52:53.713180 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6540 11:52:53.716535 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6541 11:52:53.719696 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6542 11:52:53.726022 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6543 11:52:53.729810 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6544 11:52:53.732740 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6545 11:52:53.736449 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6546 11:52:53.742925 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6547 11:52:53.746347 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6548 11:52:53.749311 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6549 11:52:53.749394 ==
6550 11:52:53.752893 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 11:52:53.759707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 11:52:53.759790 ==
6553 11:52:53.759856 DQS Delay:
6554 11:52:53.762799 DQS0 = 27, DQS1 = 35
6555 11:52:53.762882 DQM Delay:
6556 11:52:53.762947 DQM0 = 9, DQM1 = 9
6557 11:52:53.766140 DQ Delay:
6558 11:52:53.769465 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6559 11:52:53.769547 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6560 11:52:53.772691 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6561 11:52:53.775985 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6562 11:52:53.776067
6563 11:52:53.776132
6564 11:52:53.776192 ==
6565 11:52:53.780002 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 11:52:53.785996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 11:52:53.786094 ==
6568 11:52:53.786172
6569 11:52:53.786233
6570 11:52:53.786290 TX Vref Scan disable
6571 11:52:53.789341 == TX Byte 0 ==
6572 11:52:53.792769 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6573 11:52:53.796402 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6574 11:52:53.799707 == TX Byte 1 ==
6575 11:52:53.802710 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6576 11:52:53.806014 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6577 11:52:53.806096 ==
6578 11:52:53.809326 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 11:52:53.816175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 11:52:53.816259 ==
6581 11:52:53.816324
6582 11:52:53.816384
6583 11:52:53.816441 TX Vref Scan disable
6584 11:52:53.819762 == TX Byte 0 ==
6585 11:52:53.822987 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6586 11:52:53.826125 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6587 11:52:53.829360 == TX Byte 1 ==
6588 11:52:53.832596 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6589 11:52:53.835946 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6590 11:52:53.836029
6591 11:52:53.839221 [DATLAT]
6592 11:52:53.839303 Freq=400, CH0 RK1
6593 11:52:53.839368
6594 11:52:53.842507 DATLAT Default: 0xe
6595 11:52:53.842589 0, 0xFFFF, sum = 0
6596 11:52:53.845784 1, 0xFFFF, sum = 0
6597 11:52:53.845867 2, 0xFFFF, sum = 0
6598 11:52:53.849134 3, 0xFFFF, sum = 0
6599 11:52:53.849217 4, 0xFFFF, sum = 0
6600 11:52:53.852678 5, 0xFFFF, sum = 0
6601 11:52:53.852761 6, 0xFFFF, sum = 0
6602 11:52:53.855804 7, 0xFFFF, sum = 0
6603 11:52:53.859087 8, 0xFFFF, sum = 0
6604 11:52:53.859170 9, 0xFFFF, sum = 0
6605 11:52:53.862668 10, 0xFFFF, sum = 0
6606 11:52:53.862751 11, 0xFFFF, sum = 0
6607 11:52:53.865897 12, 0xFFFF, sum = 0
6608 11:52:53.865980 13, 0x0, sum = 1
6609 11:52:53.868876 14, 0x0, sum = 2
6610 11:52:53.868959 15, 0x0, sum = 3
6611 11:52:53.872645 16, 0x0, sum = 4
6612 11:52:53.872729 best_step = 14
6613 11:52:53.872794
6614 11:52:53.872852 ==
6615 11:52:53.875905 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 11:52:53.878921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 11:52:53.879005 ==
6618 11:52:53.882491 RX Vref Scan: 0
6619 11:52:53.882574
6620 11:52:53.885674 RX Vref 0 -> 0, step: 1
6621 11:52:53.885756
6622 11:52:53.885821 RX Delay -311 -> 252, step: 8
6623 11:52:53.894553 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6624 11:52:53.897570 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6625 11:52:53.900856 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6626 11:52:53.904229 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6627 11:52:53.910842 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6628 11:52:53.914232 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6629 11:52:53.917366 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6630 11:52:53.920884 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6631 11:52:53.927548 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6632 11:52:53.930851 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6633 11:52:53.934270 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6634 11:52:53.937213 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6635 11:52:53.944028 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6636 11:52:53.947275 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6637 11:52:53.950348 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6638 11:52:53.957082 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6639 11:52:53.957162 ==
6640 11:52:53.960918 Dram Type= 6, Freq= 0, CH_0, rank 1
6641 11:52:53.963673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 11:52:53.963748 ==
6643 11:52:53.963832 DQS Delay:
6644 11:52:53.967196 DQS0 = 28, DQS1 = 40
6645 11:52:53.967279 DQM Delay:
6646 11:52:53.970761 DQM0 = 11, DQM1 = 12
6647 11:52:53.970844 DQ Delay:
6648 11:52:53.974015 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6649 11:52:53.977362 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6650 11:52:53.980706 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6651 11:52:53.983854 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =16
6652 11:52:53.983936
6653 11:52:53.984002
6654 11:52:53.990732 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf74, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6655 11:52:53.993874 CH0 RK1: MR19=C0C, MR18=BF74
6656 11:52:54.000586 CH0_RK1: MR19=0xC0C, MR18=0xBF74, DQSOSC=386, MR23=63, INC=396, DEC=264
6657 11:52:54.003850 [RxdqsGatingPostProcess] freq 400
6658 11:52:54.010477 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6659 11:52:54.010564 best DQS0 dly(2T, 0.5T) = (0, 10)
6660 11:52:54.014288 best DQS1 dly(2T, 0.5T) = (0, 10)
6661 11:52:54.017419 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6662 11:52:54.020347 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6663 11:52:54.023595 best DQS0 dly(2T, 0.5T) = (0, 10)
6664 11:52:54.027121 best DQS1 dly(2T, 0.5T) = (0, 10)
6665 11:52:54.030241 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6666 11:52:54.033863 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6667 11:52:54.036976 Pre-setting of DQS Precalculation
6668 11:52:54.043779 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6669 11:52:54.043864 ==
6670 11:52:54.046925 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 11:52:54.050402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 11:52:54.050502 ==
6673 11:52:54.056937 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 11:52:54.060522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6675 11:52:54.063622 [CA 0] Center 36 (8~64) winsize 57
6676 11:52:54.066985 [CA 1] Center 36 (8~64) winsize 57
6677 11:52:54.070157 [CA 2] Center 36 (8~64) winsize 57
6678 11:52:54.073386 [CA 3] Center 36 (8~64) winsize 57
6679 11:52:54.076714 [CA 4] Center 36 (8~64) winsize 57
6680 11:52:54.080208 [CA 5] Center 36 (8~64) winsize 57
6681 11:52:54.080292
6682 11:52:54.083786 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6683 11:52:54.083870
6684 11:52:54.087114 [CATrainingPosCal] consider 1 rank data
6685 11:52:54.090369 u2DelayCellTimex100 = 270/100 ps
6686 11:52:54.093702 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:52:54.096819 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:52:54.100403 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:52:54.103285 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:52:54.110123 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:52:54.113287 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:52:54.113362
6693 11:52:54.116755 CA PerBit enable=1, Macro0, CA PI delay=36
6694 11:52:54.116829
6695 11:52:54.120028 [CBTSetCACLKResult] CA Dly = 36
6696 11:52:54.120105 CS Dly: 1 (0~32)
6697 11:52:54.120167 ==
6698 11:52:54.123393 Dram Type= 6, Freq= 0, CH_1, rank 1
6699 11:52:54.129997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 11:52:54.130079 ==
6701 11:52:54.133676 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 11:52:54.139889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6703 11:52:54.143168 [CA 0] Center 36 (8~64) winsize 57
6704 11:52:54.146840 [CA 1] Center 36 (8~64) winsize 57
6705 11:52:54.150267 [CA 2] Center 36 (8~64) winsize 57
6706 11:52:54.153689 [CA 3] Center 36 (8~64) winsize 57
6707 11:52:54.156618 [CA 4] Center 36 (8~64) winsize 57
6708 11:52:54.160169 [CA 5] Center 36 (8~64) winsize 57
6709 11:52:54.160253
6710 11:52:54.163896 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6711 11:52:54.163979
6712 11:52:54.166839 [CATrainingPosCal] consider 2 rank data
6713 11:52:54.170355 u2DelayCellTimex100 = 270/100 ps
6714 11:52:54.173503 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:52:54.176603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:52:54.180411 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:52:54.183196 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:52:54.186826 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:52:54.189980 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:52:54.190062
6721 11:52:54.193202 CA PerBit enable=1, Macro0, CA PI delay=36
6722 11:52:54.196698
6723 11:52:54.196781 [CBTSetCACLKResult] CA Dly = 36
6724 11:52:54.200089 CS Dly: 1 (0~32)
6725 11:52:54.200170
6726 11:52:54.203233 ----->DramcWriteLeveling(PI) begin...
6727 11:52:54.203307 ==
6728 11:52:54.206512 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:52:54.210200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:52:54.210283 ==
6731 11:52:54.213475 Write leveling (Byte 0): 40 => 8
6732 11:52:54.216557 Write leveling (Byte 1): 32 => 0
6733 11:52:54.220292 DramcWriteLeveling(PI) end<-----
6734 11:52:54.220373
6735 11:52:54.220438 ==
6736 11:52:54.223447 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 11:52:54.226747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 11:52:54.226830 ==
6739 11:52:54.229693 [Gating] SW mode calibration
6740 11:52:54.236635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6741 11:52:54.243032 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6742 11:52:54.246619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6743 11:52:54.253140 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6744 11:52:54.256402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 11:52:54.259891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 11:52:54.263518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 11:52:54.269935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 11:52:54.273503 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 11:52:54.276573 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 11:52:54.283451 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 11:52:54.286650 Total UI for P1: 0, mck2ui 16
6752 11:52:54.289987 best dqsien dly found for B0: ( 0, 14, 24)
6753 11:52:54.293300 Total UI for P1: 0, mck2ui 16
6754 11:52:54.296651 best dqsien dly found for B1: ( 0, 14, 24)
6755 11:52:54.299803 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6756 11:52:54.303540 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6757 11:52:54.303622
6758 11:52:54.306528 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 11:52:54.309948 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 11:52:54.312988 [Gating] SW calibration Done
6761 11:52:54.313070 ==
6762 11:52:54.316520 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 11:52:54.320058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 11:52:54.320141 ==
6765 11:52:54.323387 RX Vref Scan: 0
6766 11:52:54.323469
6767 11:52:54.323536 RX Vref 0 -> 0, step: 1
6768 11:52:54.326613
6769 11:52:54.326696 RX Delay -410 -> 252, step: 16
6770 11:52:54.333460 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6771 11:52:54.336769 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6772 11:52:54.339949 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6773 11:52:54.342963 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6774 11:52:54.350296 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6775 11:52:54.353322 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6776 11:52:54.356490 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6777 11:52:54.360066 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6778 11:52:54.366794 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6779 11:52:54.370007 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6780 11:52:54.372957 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6781 11:52:54.376142 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6782 11:52:54.383191 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6783 11:52:54.386360 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6784 11:52:54.389919 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6785 11:52:54.396339 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6786 11:52:54.396423 ==
6787 11:52:54.399562 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 11:52:54.402971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 11:52:54.403055 ==
6790 11:52:54.403139 DQS Delay:
6791 11:52:54.406768 DQS0 = 27, DQS1 = 43
6792 11:52:54.406851 DQM Delay:
6793 11:52:54.409436 DQM0 = 5, DQM1 = 15
6794 11:52:54.409520 DQ Delay:
6795 11:52:54.412689 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6796 11:52:54.416202 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6797 11:52:54.419389 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6798 11:52:54.422688 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6799 11:52:54.422772
6800 11:52:54.422838
6801 11:52:54.422899 ==
6802 11:52:54.425990 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 11:52:54.429611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 11:52:54.429695 ==
6805 11:52:54.429762
6806 11:52:54.429823
6807 11:52:54.432666 TX Vref Scan disable
6808 11:52:54.432750 == TX Byte 0 ==
6809 11:52:54.439367 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 11:52:54.442905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 11:52:54.442989 == TX Byte 1 ==
6812 11:52:54.449308 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6813 11:52:54.452564 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6814 11:52:54.452648 ==
6815 11:52:54.455833 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 11:52:54.459511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 11:52:54.459596 ==
6818 11:52:54.459663
6819 11:52:54.459725
6820 11:52:54.462639 TX Vref Scan disable
6821 11:52:54.462722 == TX Byte 0 ==
6822 11:52:54.469308 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 11:52:54.472661 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 11:52:54.472745 == TX Byte 1 ==
6825 11:52:54.479360 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6826 11:52:54.482654 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6827 11:52:54.482738
6828 11:52:54.482803 [DATLAT]
6829 11:52:54.486108 Freq=400, CH1 RK0
6830 11:52:54.486193
6831 11:52:54.486259 DATLAT Default: 0xf
6832 11:52:54.489472 0, 0xFFFF, sum = 0
6833 11:52:54.489558 1, 0xFFFF, sum = 0
6834 11:52:54.492660 2, 0xFFFF, sum = 0
6835 11:52:54.492745 3, 0xFFFF, sum = 0
6836 11:52:54.496406 4, 0xFFFF, sum = 0
6837 11:52:54.496491 5, 0xFFFF, sum = 0
6838 11:52:54.499859 6, 0xFFFF, sum = 0
6839 11:52:54.499944 7, 0xFFFF, sum = 0
6840 11:52:54.502742 8, 0xFFFF, sum = 0
6841 11:52:54.502828 9, 0xFFFF, sum = 0
6842 11:52:54.505990 10, 0xFFFF, sum = 0
6843 11:52:54.509611 11, 0xFFFF, sum = 0
6844 11:52:54.509695 12, 0xFFFF, sum = 0
6845 11:52:54.512794 13, 0x0, sum = 1
6846 11:52:54.512879 14, 0x0, sum = 2
6847 11:52:54.512946 15, 0x0, sum = 3
6848 11:52:54.516148 16, 0x0, sum = 4
6849 11:52:54.516234 best_step = 14
6850 11:52:54.516300
6851 11:52:54.519602 ==
6852 11:52:54.519686 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 11:52:54.526098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 11:52:54.526182 ==
6855 11:52:54.526249 RX Vref Scan: 1
6856 11:52:54.526311
6857 11:52:54.529181 RX Vref 0 -> 0, step: 1
6858 11:52:54.529265
6859 11:52:54.532830 RX Delay -327 -> 252, step: 8
6860 11:52:54.532914
6861 11:52:54.536238 Set Vref, RX VrefLevel [Byte0]: 51
6862 11:52:54.539393 [Byte1]: 55
6863 11:52:54.542879
6864 11:52:54.542989 Final RX Vref Byte 0 = 51 to rank0
6865 11:52:54.546458 Final RX Vref Byte 1 = 55 to rank0
6866 11:52:54.549379 Final RX Vref Byte 0 = 51 to rank1
6867 11:52:54.552915 Final RX Vref Byte 1 = 55 to rank1==
6868 11:52:54.556310 Dram Type= 6, Freq= 0, CH_1, rank 0
6869 11:52:54.563204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 11:52:54.563289 ==
6871 11:52:54.563356 DQS Delay:
6872 11:52:54.563418 DQS0 = 32, DQS1 = 40
6873 11:52:54.566168 DQM Delay:
6874 11:52:54.566251 DQM0 = 11, DQM1 = 12
6875 11:52:54.569591 DQ Delay:
6876 11:52:54.572658 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6877 11:52:54.572769 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6878 11:52:54.576042 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6879 11:52:54.579248 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6880 11:52:54.579351
6881 11:52:54.579451
6882 11:52:54.589500 [DQSOSCAuto] RK0, (LSB)MR18= 0x93ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6883 11:52:54.592996 CH1 RK0: MR19=C0C, MR18=93CE
6884 11:52:54.599254 CH1_RK0: MR19=0xC0C, MR18=0x93CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6885 11:52:54.599346 ==
6886 11:52:54.602582 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 11:52:54.606292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:52:54.606375 ==
6889 11:52:54.609333 [Gating] SW mode calibration
6890 11:52:54.616197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6891 11:52:54.619377 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6892 11:52:54.626019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6893 11:52:54.629343 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6894 11:52:54.632577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 11:52:54.639518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 11:52:54.642417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 11:52:54.646094 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 11:52:54.652842 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 11:52:54.655727 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 11:52:54.659191 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 11:52:54.662487 Total UI for P1: 0, mck2ui 16
6902 11:52:54.666206 best dqsien dly found for B0: ( 0, 14, 24)
6903 11:52:54.669304 Total UI for P1: 0, mck2ui 16
6904 11:52:54.672648 best dqsien dly found for B1: ( 0, 14, 24)
6905 11:52:54.675910 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6906 11:52:54.679015 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6907 11:52:54.679097
6908 11:52:54.685701 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 11:52:54.689159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 11:52:54.692389 [Gating] SW calibration Done
6911 11:52:54.692471 ==
6912 11:52:54.696022 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 11:52:54.698843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 11:52:54.698957 ==
6915 11:52:54.699051 RX Vref Scan: 0
6916 11:52:54.699141
6917 11:52:54.702455 RX Vref 0 -> 0, step: 1
6918 11:52:54.702562
6919 11:52:54.705477 RX Delay -410 -> 252, step: 16
6920 11:52:54.709406 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6921 11:52:54.715541 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6922 11:52:54.718886 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6923 11:52:54.722176 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6924 11:52:54.725507 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6925 11:52:54.732141 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6926 11:52:54.735573 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6927 11:52:54.738674 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6928 11:52:54.742076 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6929 11:52:54.748993 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6930 11:52:54.752144 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6931 11:52:54.755391 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6932 11:52:54.758965 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6933 11:52:54.765309 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6934 11:52:54.768669 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6935 11:52:54.772160 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6936 11:52:54.772238 ==
6937 11:52:54.775436 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 11:52:54.778926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 11:52:54.782249 ==
6940 11:52:54.782346 DQS Delay:
6941 11:52:54.782461 DQS0 = 35, DQS1 = 43
6942 11:52:54.785329 DQM Delay:
6943 11:52:54.785395 DQM0 = 17, DQM1 = 18
6944 11:52:54.788706 DQ Delay:
6945 11:52:54.792139 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6946 11:52:54.792214 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6947 11:52:54.795687 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6948 11:52:54.798868 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6949 11:52:54.798950
6950 11:52:54.802401
6951 11:52:54.802482 ==
6952 11:52:54.805410 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 11:52:54.808860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 11:52:54.808942 ==
6955 11:52:54.809008
6956 11:52:54.809068
6957 11:52:54.812315 TX Vref Scan disable
6958 11:52:54.812396 == TX Byte 0 ==
6959 11:52:54.815289 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6960 11:52:54.822295 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6961 11:52:54.822378 == TX Byte 1 ==
6962 11:52:54.825335 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6963 11:52:54.831972 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6964 11:52:54.832054 ==
6965 11:52:54.835383 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 11:52:54.838527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 11:52:54.838609 ==
6968 11:52:54.838674
6969 11:52:54.838734
6970 11:52:54.841861 TX Vref Scan disable
6971 11:52:54.841943 == TX Byte 0 ==
6972 11:52:54.844983 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6973 11:52:54.851660 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6974 11:52:54.851743 == TX Byte 1 ==
6975 11:52:54.855094 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6976 11:52:54.862033 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6977 11:52:54.862116
6978 11:52:54.862181 [DATLAT]
6979 11:52:54.862241 Freq=400, CH1 RK1
6980 11:52:54.862300
6981 11:52:54.865015 DATLAT Default: 0xe
6982 11:52:54.868792 0, 0xFFFF, sum = 0
6983 11:52:54.868875 1, 0xFFFF, sum = 0
6984 11:52:54.871505 2, 0xFFFF, sum = 0
6985 11:52:54.871588 3, 0xFFFF, sum = 0
6986 11:52:54.874927 4, 0xFFFF, sum = 0
6987 11:52:54.875010 5, 0xFFFF, sum = 0
6988 11:52:54.878490 6, 0xFFFF, sum = 0
6989 11:52:54.878573 7, 0xFFFF, sum = 0
6990 11:52:54.881545 8, 0xFFFF, sum = 0
6991 11:52:54.881628 9, 0xFFFF, sum = 0
6992 11:52:54.884983 10, 0xFFFF, sum = 0
6993 11:52:54.885066 11, 0xFFFF, sum = 0
6994 11:52:54.888349 12, 0xFFFF, sum = 0
6995 11:52:54.888433 13, 0x0, sum = 1
6996 11:52:54.891538 14, 0x0, sum = 2
6997 11:52:54.891621 15, 0x0, sum = 3
6998 11:52:54.894938 16, 0x0, sum = 4
6999 11:52:54.895022 best_step = 14
7000 11:52:54.895088
7001 11:52:54.895148 ==
7002 11:52:54.898264 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 11:52:54.904820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 11:52:54.904903 ==
7005 11:52:54.904969 RX Vref Scan: 0
7006 11:52:54.905029
7007 11:52:54.908377 RX Vref 0 -> 0, step: 1
7008 11:52:54.908459
7009 11:52:54.911316 RX Delay -327 -> 252, step: 8
7010 11:52:54.918334 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7011 11:52:54.921518 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7012 11:52:54.925042 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7013 11:52:54.928273 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7014 11:52:54.931483 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7015 11:52:54.938289 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7016 11:52:54.941540 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7017 11:52:54.944701 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7018 11:52:54.948214 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
7019 11:52:54.954712 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7020 11:52:54.957973 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7021 11:52:54.961341 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7022 11:52:54.968078 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7023 11:52:54.971483 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7024 11:52:54.974872 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7025 11:52:54.978249 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7026 11:52:54.978350 ==
7027 11:52:54.981587 Dram Type= 6, Freq= 0, CH_1, rank 1
7028 11:52:54.988095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 11:52:54.988177 ==
7030 11:52:54.988242 DQS Delay:
7031 11:52:54.991260 DQS0 = 32, DQS1 = 40
7032 11:52:54.991342 DQM Delay:
7033 11:52:54.991407 DQM0 = 12, DQM1 = 14
7034 11:52:54.994541 DQ Delay:
7035 11:52:54.998462 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7036 11:52:55.001296 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
7037 11:52:55.001379 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7038 11:52:55.004815 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7039 11:52:55.008062
7040 11:52:55.008144
7041 11:52:55.014652 [DQSOSCAuto] RK1, (LSB)MR18= 0xb058, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7042 11:52:55.017847 CH1 RK1: MR19=C0C, MR18=B058
7043 11:52:55.024727 CH1_RK1: MR19=0xC0C, MR18=0xB058, DQSOSC=387, MR23=63, INC=394, DEC=262
7044 11:52:55.027907 [RxdqsGatingPostProcess] freq 400
7045 11:52:55.031081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7046 11:52:55.034374 best DQS0 dly(2T, 0.5T) = (0, 10)
7047 11:52:55.037997 best DQS1 dly(2T, 0.5T) = (0, 10)
7048 11:52:55.041122 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7049 11:52:55.044465 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7050 11:52:55.047896 best DQS0 dly(2T, 0.5T) = (0, 10)
7051 11:52:55.051283 best DQS1 dly(2T, 0.5T) = (0, 10)
7052 11:52:55.054870 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7053 11:52:55.057753 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7054 11:52:55.061468 Pre-setting of DQS Precalculation
7055 11:52:55.064395 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7056 11:52:55.071179 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7057 11:52:55.081084 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7058 11:52:55.081167
7059 11:52:55.081232
7060 11:52:55.084233 [Calibration Summary] 800 Mbps
7061 11:52:55.084315 CH 0, Rank 0
7062 11:52:55.087546 SW Impedance : PASS
7063 11:52:55.087628 DUTY Scan : NO K
7064 11:52:55.090752 ZQ Calibration : PASS
7065 11:52:55.094395 Jitter Meter : NO K
7066 11:52:55.094491 CBT Training : PASS
7067 11:52:55.097904 Write leveling : PASS
7068 11:52:55.097986 RX DQS gating : PASS
7069 11:52:55.101056 RX DQ/DQS(RDDQC) : PASS
7070 11:52:55.104095 TX DQ/DQS : PASS
7071 11:52:55.104178 RX DATLAT : PASS
7072 11:52:55.107397 RX DQ/DQS(Engine): PASS
7073 11:52:55.110832 TX OE : NO K
7074 11:52:55.110914 All Pass.
7075 11:52:55.110979
7076 11:52:55.111039 CH 0, Rank 1
7077 11:52:55.114026 SW Impedance : PASS
7078 11:52:55.117218 DUTY Scan : NO K
7079 11:52:55.117300 ZQ Calibration : PASS
7080 11:52:55.121426 Jitter Meter : NO K
7081 11:52:55.123965 CBT Training : PASS
7082 11:52:55.124048 Write leveling : NO K
7083 11:52:55.127429 RX DQS gating : PASS
7084 11:52:55.130804 RX DQ/DQS(RDDQC) : PASS
7085 11:52:55.130887 TX DQ/DQS : PASS
7086 11:52:55.133763 RX DATLAT : PASS
7087 11:52:55.136998 RX DQ/DQS(Engine): PASS
7088 11:52:55.137080 TX OE : NO K
7089 11:52:55.140460 All Pass.
7090 11:52:55.140542
7091 11:52:55.140607 CH 1, Rank 0
7092 11:52:55.143827 SW Impedance : PASS
7093 11:52:55.143908 DUTY Scan : NO K
7094 11:52:55.147376 ZQ Calibration : PASS
7095 11:52:55.150507 Jitter Meter : NO K
7096 11:52:55.150589 CBT Training : PASS
7097 11:52:55.153668 Write leveling : PASS
7098 11:52:55.157171 RX DQS gating : PASS
7099 11:52:55.157278 RX DQ/DQS(RDDQC) : PASS
7100 11:52:55.160659 TX DQ/DQS : PASS
7101 11:52:55.160741 RX DATLAT : PASS
7102 11:52:55.163884 RX DQ/DQS(Engine): PASS
7103 11:52:55.167151 TX OE : NO K
7104 11:52:55.167233 All Pass.
7105 11:52:55.167298
7106 11:52:55.167378 CH 1, Rank 1
7107 11:52:55.170665 SW Impedance : PASS
7108 11:52:55.173476 DUTY Scan : NO K
7109 11:52:55.173559 ZQ Calibration : PASS
7110 11:52:55.176751 Jitter Meter : NO K
7111 11:52:55.180314 CBT Training : PASS
7112 11:52:55.180396 Write leveling : NO K
7113 11:52:55.183418 RX DQS gating : PASS
7114 11:52:55.186977 RX DQ/DQS(RDDQC) : PASS
7115 11:52:55.187059 TX DQ/DQS : PASS
7116 11:52:55.190372 RX DATLAT : PASS
7117 11:52:55.193597 RX DQ/DQS(Engine): PASS
7118 11:52:55.193679 TX OE : NO K
7119 11:52:55.196733 All Pass.
7120 11:52:55.196815
7121 11:52:55.196879 DramC Write-DBI off
7122 11:52:55.200136 PER_BANK_REFRESH: Hybrid Mode
7123 11:52:55.200218 TX_TRACKING: ON
7124 11:52:55.209968 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7125 11:52:55.213342 [FAST_K] Save calibration result to emmc
7126 11:52:55.216682 dramc_set_vcore_voltage set vcore to 725000
7127 11:52:55.220038 Read voltage for 1600, 0
7128 11:52:55.220138 Vio18 = 0
7129 11:52:55.223752 Vcore = 725000
7130 11:52:55.223826 Vdram = 0
7131 11:52:55.223887 Vddq = 0
7132 11:52:55.227092 Vmddr = 0
7133 11:52:55.230265 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7134 11:52:55.236541 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7135 11:52:55.236617 MEM_TYPE=3, freq_sel=13
7136 11:52:55.239933 sv_algorithm_assistance_LP4_3733
7137 11:52:55.243707 ============ PULL DRAM RESETB DOWN ============
7138 11:52:55.249847 ========== PULL DRAM RESETB DOWN end =========
7139 11:52:55.253217 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7140 11:52:55.256556 ===================================
7141 11:52:55.260211 LPDDR4 DRAM CONFIGURATION
7142 11:52:55.263377 ===================================
7143 11:52:55.263459 EX_ROW_EN[0] = 0x0
7144 11:52:55.266937 EX_ROW_EN[1] = 0x0
7145 11:52:55.270119 LP4Y_EN = 0x0
7146 11:52:55.270201 WORK_FSP = 0x1
7147 11:52:55.273419 WL = 0x5
7148 11:52:55.273502 RL = 0x5
7149 11:52:55.276908 BL = 0x2
7150 11:52:55.276990 RPST = 0x0
7151 11:52:55.280047 RD_PRE = 0x0
7152 11:52:55.280129 WR_PRE = 0x1
7153 11:52:55.283389 WR_PST = 0x1
7154 11:52:55.283471 DBI_WR = 0x0
7155 11:52:55.286586 DBI_RD = 0x0
7156 11:52:55.286668 OTF = 0x1
7157 11:52:55.290004 ===================================
7158 11:52:55.293321 ===================================
7159 11:52:55.296328 ANA top config
7160 11:52:55.299823 ===================================
7161 11:52:55.299905 DLL_ASYNC_EN = 0
7162 11:52:55.303258 ALL_SLAVE_EN = 0
7163 11:52:55.306377 NEW_RANK_MODE = 1
7164 11:52:55.309604 DLL_IDLE_MODE = 1
7165 11:52:55.313322 LP45_APHY_COMB_EN = 1
7166 11:52:55.313404 TX_ODT_DIS = 0
7167 11:52:55.316289 NEW_8X_MODE = 1
7168 11:52:55.319714 ===================================
7169 11:52:55.323203 ===================================
7170 11:52:55.326630 data_rate = 3200
7171 11:52:55.330167 CKR = 1
7172 11:52:55.333056 DQ_P2S_RATIO = 8
7173 11:52:55.336628 ===================================
7174 11:52:55.336710 CA_P2S_RATIO = 8
7175 11:52:55.339737 DQ_CA_OPEN = 0
7176 11:52:55.342999 DQ_SEMI_OPEN = 0
7177 11:52:55.346325 CA_SEMI_OPEN = 0
7178 11:52:55.350200 CA_FULL_RATE = 0
7179 11:52:55.353295 DQ_CKDIV4_EN = 0
7180 11:52:55.353379 CA_CKDIV4_EN = 0
7181 11:52:55.356418 CA_PREDIV_EN = 0
7182 11:52:55.359688 PH8_DLY = 12
7183 11:52:55.363028 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7184 11:52:55.366379 DQ_AAMCK_DIV = 4
7185 11:52:55.369705 CA_AAMCK_DIV = 4
7186 11:52:55.369787 CA_ADMCK_DIV = 4
7187 11:52:55.373528 DQ_TRACK_CA_EN = 0
7188 11:52:55.376308 CA_PICK = 1600
7189 11:52:55.379774 CA_MCKIO = 1600
7190 11:52:55.383200 MCKIO_SEMI = 0
7191 11:52:55.386394 PLL_FREQ = 3068
7192 11:52:55.389899 DQ_UI_PI_RATIO = 32
7193 11:52:55.390001 CA_UI_PI_RATIO = 0
7194 11:52:55.393214 ===================================
7195 11:52:55.396304 ===================================
7196 11:52:55.400016 memory_type:LPDDR4
7197 11:52:55.403446 GP_NUM : 10
7198 11:52:55.403555 SRAM_EN : 1
7199 11:52:55.407013 MD32_EN : 0
7200 11:52:55.410072 ===================================
7201 11:52:55.412833 [ANA_INIT] >>>>>>>>>>>>>>
7202 11:52:55.416704 <<<<<< [CONFIGURE PHASE]: ANA_TX
7203 11:52:55.419771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7204 11:52:55.423236 ===================================
7205 11:52:55.423344 data_rate = 3200,PCW = 0X7600
7206 11:52:55.426186 ===================================
7207 11:52:55.429638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7208 11:52:55.436454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 11:52:55.442802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 11:52:55.446209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7211 11:52:55.449409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7212 11:52:55.452999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7213 11:52:55.456259 [ANA_INIT] flow start
7214 11:52:55.456360 [ANA_INIT] PLL >>>>>>>>
7215 11:52:55.459726 [ANA_INIT] PLL <<<<<<<<
7216 11:52:55.463068 [ANA_INIT] MIDPI >>>>>>>>
7217 11:52:55.466101 [ANA_INIT] MIDPI <<<<<<<<
7218 11:52:55.466198 [ANA_INIT] DLL >>>>>>>>
7219 11:52:55.469457 [ANA_INIT] DLL <<<<<<<<
7220 11:52:55.469553 [ANA_INIT] flow end
7221 11:52:55.476464 ============ LP4 DIFF to SE enter ============
7222 11:52:55.479494 ============ LP4 DIFF to SE exit ============
7223 11:52:55.483140 [ANA_INIT] <<<<<<<<<<<<<
7224 11:52:55.485947 [Flow] Enable top DCM control >>>>>
7225 11:52:55.489607 [Flow] Enable top DCM control <<<<<
7226 11:52:55.492531 Enable DLL master slave shuffle
7227 11:52:55.496206 ==============================================================
7228 11:52:55.499268 Gating Mode config
7229 11:52:55.502979 ==============================================================
7230 11:52:55.505937 Config description:
7231 11:52:55.515825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7232 11:52:55.522533 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7233 11:52:55.525848 SELPH_MODE 0: By rank 1: By Phase
7234 11:52:55.532579 ==============================================================
7235 11:52:55.535668 GAT_TRACK_EN = 1
7236 11:52:55.539115 RX_GATING_MODE = 2
7237 11:52:55.542515 RX_GATING_TRACK_MODE = 2
7238 11:52:55.545721 SELPH_MODE = 1
7239 11:52:55.549171 PICG_EARLY_EN = 1
7240 11:52:55.549253 VALID_LAT_VALUE = 1
7241 11:52:55.556244 ==============================================================
7242 11:52:55.559273 Enter into Gating configuration >>>>
7243 11:52:55.562499 Exit from Gating configuration <<<<
7244 11:52:55.565996 Enter into DVFS_PRE_config >>>>>
7245 11:52:55.575840 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7246 11:52:55.579221 Exit from DVFS_PRE_config <<<<<
7247 11:52:55.582775 Enter into PICG configuration >>>>
7248 11:52:55.585828 Exit from PICG configuration <<<<
7249 11:52:55.589033 [RX_INPUT] configuration >>>>>
7250 11:52:55.592237 [RX_INPUT] configuration <<<<<
7251 11:52:55.595857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7252 11:52:55.602329 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7253 11:52:55.609322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 11:52:55.616051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 11:52:55.622330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 11:52:55.625812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 11:52:55.632275 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7258 11:52:55.635612 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7259 11:52:55.638954 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7260 11:52:55.642467 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7261 11:52:55.649138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7262 11:52:55.652518 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 11:52:55.655799 ===================================
7264 11:52:55.659184 LPDDR4 DRAM CONFIGURATION
7265 11:52:55.662306 ===================================
7266 11:52:55.662416 EX_ROW_EN[0] = 0x0
7267 11:52:55.665915 EX_ROW_EN[1] = 0x0
7268 11:52:55.665997 LP4Y_EN = 0x0
7269 11:52:55.668886 WORK_FSP = 0x1
7270 11:52:55.668999 WL = 0x5
7271 11:52:55.672474 RL = 0x5
7272 11:52:55.672557 BL = 0x2
7273 11:52:55.675745 RPST = 0x0
7274 11:52:55.675828 RD_PRE = 0x0
7275 11:52:55.678986 WR_PRE = 0x1
7276 11:52:55.682510 WR_PST = 0x1
7277 11:52:55.682593 DBI_WR = 0x0
7278 11:52:55.686116 DBI_RD = 0x0
7279 11:52:55.686199 OTF = 0x1
7280 11:52:55.688777 ===================================
7281 11:52:55.692599 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7282 11:52:55.695440 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7283 11:52:55.702002 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7284 11:52:55.705397 ===================================
7285 11:52:55.708813 LPDDR4 DRAM CONFIGURATION
7286 11:52:55.711980 ===================================
7287 11:52:55.712062 EX_ROW_EN[0] = 0x10
7288 11:52:55.715296 EX_ROW_EN[1] = 0x0
7289 11:52:55.715379 LP4Y_EN = 0x0
7290 11:52:55.718793 WORK_FSP = 0x1
7291 11:52:55.718875 WL = 0x5
7292 11:52:55.722029 RL = 0x5
7293 11:52:55.722112 BL = 0x2
7294 11:52:55.725836 RPST = 0x0
7295 11:52:55.725934 RD_PRE = 0x0
7296 11:52:55.728949 WR_PRE = 0x1
7297 11:52:55.729032 WR_PST = 0x1
7298 11:52:55.732148 DBI_WR = 0x0
7299 11:52:55.732230 DBI_RD = 0x0
7300 11:52:55.735529 OTF = 0x1
7301 11:52:55.738835 ===================================
7302 11:52:55.745371 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7303 11:52:55.745454 ==
7304 11:52:55.748623 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 11:52:55.751809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7306 11:52:55.751893 ==
7307 11:52:55.755310 [Duty_Offset_Calibration]
7308 11:52:55.755392 B0:2 B1:0 CA:1
7309 11:52:55.755457
7310 11:52:55.758653 [DutyScan_Calibration_Flow] k_type=0
7311 11:52:55.768847
7312 11:52:55.768930 ==CLK 0==
7313 11:52:55.772134 Final CLK duty delay cell = -4
7314 11:52:55.775355 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7315 11:52:55.778741 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7316 11:52:55.781917 [-4] AVG Duty = 4906%(X100)
7317 11:52:55.782000
7318 11:52:55.785487 CH0 CLK Duty spec in!! Max-Min= 187%
7319 11:52:55.788964 [DutyScan_Calibration_Flow] ====Done====
7320 11:52:55.789047
7321 11:52:55.792410 [DutyScan_Calibration_Flow] k_type=1
7322 11:52:55.808511
7323 11:52:55.808593 ==DQS 0 ==
7324 11:52:55.811724 Final DQS duty delay cell = 0
7325 11:52:55.814729 [0] MAX Duty = 5249%(X100), DQS PI = 32
7326 11:52:55.818325 [0] MIN Duty = 4969%(X100), DQS PI = 0
7327 11:52:55.821420 [0] AVG Duty = 5109%(X100)
7328 11:52:55.821503
7329 11:52:55.821569 ==DQS 1 ==
7330 11:52:55.824904 Final DQS duty delay cell = -4
7331 11:52:55.828213 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7332 11:52:55.831848 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7333 11:52:55.834866 [-4] AVG Duty = 5000%(X100)
7334 11:52:55.834968
7335 11:52:55.838272 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7336 11:52:55.838354
7337 11:52:55.841656 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7338 11:52:55.844937 [DutyScan_Calibration_Flow] ====Done====
7339 11:52:55.845019
7340 11:52:55.848360 [DutyScan_Calibration_Flow] k_type=3
7341 11:52:55.865887
7342 11:52:55.865970 ==DQM 0 ==
7343 11:52:55.869243 Final DQM duty delay cell = 0
7344 11:52:55.872609 [0] MAX Duty = 5124%(X100), DQS PI = 26
7345 11:52:55.875542 [0] MIN Duty = 4813%(X100), DQS PI = 50
7346 11:52:55.879062 [0] AVG Duty = 4968%(X100)
7347 11:52:55.879145
7348 11:52:55.879210 ==DQM 1 ==
7349 11:52:55.882376 Final DQM duty delay cell = 0
7350 11:52:55.885508 [0] MAX Duty = 5249%(X100), DQS PI = 28
7351 11:52:55.889425 [0] MIN Duty = 5000%(X100), DQS PI = 20
7352 11:52:55.892210 [0] AVG Duty = 5124%(X100)
7353 11:52:55.892286
7354 11:52:55.895735 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7355 11:52:55.895811
7356 11:52:55.899435 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7357 11:52:55.902216 [DutyScan_Calibration_Flow] ====Done====
7358 11:52:55.902290
7359 11:52:55.905523 [DutyScan_Calibration_Flow] k_type=2
7360 11:52:55.922855
7361 11:52:55.922937 ==DQ 0 ==
7362 11:52:55.926600 Final DQ duty delay cell = 0
7363 11:52:55.929772 [0] MAX Duty = 5124%(X100), DQS PI = 32
7364 11:52:55.932881 [0] MIN Duty = 5000%(X100), DQS PI = 16
7365 11:52:55.932956 [0] AVG Duty = 5062%(X100)
7366 11:52:55.936442
7367 11:52:55.936514 ==DQ 1 ==
7368 11:52:55.939766 Final DQ duty delay cell = 0
7369 11:52:55.943120 [0] MAX Duty = 4969%(X100), DQS PI = 42
7370 11:52:55.946012 [0] MIN Duty = 4875%(X100), DQS PI = 10
7371 11:52:55.946086 [0] AVG Duty = 4922%(X100)
7372 11:52:55.946147
7373 11:52:55.949438 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7374 11:52:55.953031
7375 11:52:55.956151 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7376 11:52:55.959802 [DutyScan_Calibration_Flow] ====Done====
7377 11:52:55.959881 ==
7378 11:52:55.962705 Dram Type= 6, Freq= 0, CH_1, rank 0
7379 11:52:55.966508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7380 11:52:55.966581 ==
7381 11:52:55.969699 [Duty_Offset_Calibration]
7382 11:52:55.969769 B0:0 B1:-1 CA:2
7383 11:52:55.969829
7384 11:52:55.972747 [DutyScan_Calibration_Flow] k_type=0
7385 11:52:55.983053
7386 11:52:55.983148 ==CLK 0==
7387 11:52:55.986587 Final CLK duty delay cell = 0
7388 11:52:55.989789 [0] MAX Duty = 5156%(X100), DQS PI = 40
7389 11:52:55.993843 [0] MIN Duty = 4906%(X100), DQS PI = 12
7390 11:52:55.993915 [0] AVG Duty = 5031%(X100)
7391 11:52:55.996808
7392 11:52:55.999730 CH1 CLK Duty spec in!! Max-Min= 250%
7393 11:52:56.003307 [DutyScan_Calibration_Flow] ====Done====
7394 11:52:56.003383
7395 11:52:56.006455 [DutyScan_Calibration_Flow] k_type=1
7396 11:52:56.022783
7397 11:52:56.022863 ==DQS 0 ==
7398 11:52:56.026456 Final DQS duty delay cell = 0
7399 11:52:56.029824 [0] MAX Duty = 5062%(X100), DQS PI = 8
7400 11:52:56.033008 [0] MIN Duty = 5000%(X100), DQS PI = 0
7401 11:52:56.033091 [0] AVG Duty = 5031%(X100)
7402 11:52:56.036058
7403 11:52:56.036131 ==DQS 1 ==
7404 11:52:56.039497 Final DQS duty delay cell = 0
7405 11:52:56.043089 [0] MAX Duty = 5187%(X100), DQS PI = 28
7406 11:52:56.046178 [0] MIN Duty = 4844%(X100), DQS PI = 0
7407 11:52:56.046249 [0] AVG Duty = 5015%(X100)
7408 11:52:56.049678
7409 11:52:56.052862 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7410 11:52:56.052931
7411 11:52:56.056194 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7412 11:52:56.059778 [DutyScan_Calibration_Flow] ====Done====
7413 11:52:56.059850
7414 11:52:56.062824 [DutyScan_Calibration_Flow] k_type=3
7415 11:52:56.080423
7416 11:52:56.080501 ==DQM 0 ==
7417 11:52:56.083644 Final DQM duty delay cell = 4
7418 11:52:56.086843 [4] MAX Duty = 5156%(X100), DQS PI = 26
7419 11:52:56.090292 [4] MIN Duty = 4969%(X100), DQS PI = 2
7420 11:52:56.093492 [4] AVG Duty = 5062%(X100)
7421 11:52:56.093571
7422 11:52:56.093633 ==DQM 1 ==
7423 11:52:56.096871 Final DQM duty delay cell = 0
7424 11:52:56.100158 [0] MAX Duty = 5312%(X100), DQS PI = 26
7425 11:52:56.103301 [0] MIN Duty = 4907%(X100), DQS PI = 2
7426 11:52:56.106815 [0] AVG Duty = 5109%(X100)
7427 11:52:56.106894
7428 11:52:56.110146 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7429 11:52:56.110213
7430 11:52:56.113485 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7431 11:52:56.116883 [DutyScan_Calibration_Flow] ====Done====
7432 11:52:56.116950
7433 11:52:56.120233 [DutyScan_Calibration_Flow] k_type=2
7434 11:52:56.136947
7435 11:52:56.137021 ==DQ 0 ==
7436 11:52:56.140726 Final DQ duty delay cell = 0
7437 11:52:56.143661 [0] MAX Duty = 5093%(X100), DQS PI = 22
7438 11:52:56.147005 [0] MIN Duty = 4969%(X100), DQS PI = 0
7439 11:52:56.147076 [0] AVG Duty = 5031%(X100)
7440 11:52:56.147136
7441 11:52:56.150300 ==DQ 1 ==
7442 11:52:56.153879 Final DQ duty delay cell = 0
7443 11:52:56.156892 [0] MAX Duty = 5094%(X100), DQS PI = 34
7444 11:52:56.160478 [0] MIN Duty = 4813%(X100), DQS PI = 2
7445 11:52:56.160551 [0] AVG Duty = 4953%(X100)
7446 11:52:56.160612
7447 11:52:56.163936 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7448 11:52:56.164004
7449 11:52:56.167060 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7450 11:52:56.173714 [DutyScan_Calibration_Flow] ====Done====
7451 11:52:56.176895 nWR fixed to 30
7452 11:52:56.176973 [ModeRegInit_LP4] CH0 RK0
7453 11:52:56.180387 [ModeRegInit_LP4] CH0 RK1
7454 11:52:56.183745 [ModeRegInit_LP4] CH1 RK0
7455 11:52:56.183816 [ModeRegInit_LP4] CH1 RK1
7456 11:52:56.186971 match AC timing 5
7457 11:52:56.190056 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7458 11:52:56.193436 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7459 11:52:56.200785 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7460 11:52:56.203646 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7461 11:52:56.210199 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7462 11:52:56.210273 [MiockJmeterHQA]
7463 11:52:56.210334
7464 11:52:56.213861 [DramcMiockJmeter] u1RxGatingPI = 0
7465 11:52:56.216810 0 : 4363, 4137
7466 11:52:56.216880 4 : 4252, 4027
7467 11:52:56.216941 8 : 4368, 4140
7468 11:52:56.220085 12 : 4258, 4029
7469 11:52:56.220160 16 : 4257, 4029
7470 11:52:56.223900 20 : 4363, 4137
7471 11:52:56.223975 24 : 4252, 4027
7472 11:52:56.226607 28 : 4253, 4027
7473 11:52:56.226675 32 : 4252, 4027
7474 11:52:56.230568 36 : 4255, 4029
7475 11:52:56.230642 40 : 4253, 4027
7476 11:52:56.230709 44 : 4252, 4027
7477 11:52:56.233840 48 : 4366, 4140
7478 11:52:56.233909 52 : 4253, 4027
7479 11:52:56.236700 56 : 4255, 4029
7480 11:52:56.236770 60 : 4252, 4027
7481 11:52:56.240250 64 : 4361, 4138
7482 11:52:56.240319 68 : 4250, 4027
7483 11:52:56.240378 72 : 4361, 4138
7484 11:52:56.243358 76 : 4250, 4027
7485 11:52:56.243434 80 : 4250, 4027
7486 11:52:56.246856 84 : 4250, 4027
7487 11:52:56.246931 88 : 4253, 3698
7488 11:52:56.249981 92 : 4360, 0
7489 11:52:56.250059 96 : 4250, 0
7490 11:52:56.250119 100 : 4253, 0
7491 11:52:56.253327 104 : 4361, 0
7492 11:52:56.253397 108 : 4361, 0
7493 11:52:56.256711 112 : 4363, 0
7494 11:52:56.256790 116 : 4250, 0
7495 11:52:56.256852 120 : 4250, 0
7496 11:52:56.259932 124 : 4250, 0
7497 11:52:56.260012 128 : 4252, 0
7498 11:52:56.260073 132 : 4250, 0
7499 11:52:56.263494 136 : 4250, 0
7500 11:52:56.263571 140 : 4252, 0
7501 11:52:56.266304 144 : 4361, 0
7502 11:52:56.266372 148 : 4250, 0
7503 11:52:56.266481 152 : 4250, 0
7504 11:52:56.270166 156 : 4250, 0
7505 11:52:56.270234 160 : 4361, 0
7506 11:52:56.273335 164 : 4361, 0
7507 11:52:56.273418 168 : 4250, 0
7508 11:52:56.273482 172 : 4360, 0
7509 11:52:56.276607 176 : 4250, 0
7510 11:52:56.276679 180 : 4250, 0
7511 11:52:56.279957 184 : 4249, 0
7512 11:52:56.280033 188 : 4250, 0
7513 11:52:56.280094 192 : 4252, 0
7514 11:52:56.283112 196 : 4250, 0
7515 11:52:56.283180 200 : 4250, 2
7516 11:52:56.286542 204 : 4253, 2264
7517 11:52:56.286611 208 : 4250, 4026
7518 11:52:56.286670 212 : 4250, 4027
7519 11:52:56.289881 216 : 4360, 4138
7520 11:52:56.289950 220 : 4250, 4027
7521 11:52:56.293182 224 : 4250, 4027
7522 11:52:56.293257 228 : 4360, 4138
7523 11:52:56.296479 232 : 4361, 4138
7524 11:52:56.296547 236 : 4250, 4027
7525 11:52:56.299737 240 : 4363, 4139
7526 11:52:56.299822 244 : 4360, 4138
7527 11:52:56.303114 248 : 4250, 4027
7528 11:52:56.303190 252 : 4253, 4030
7529 11:52:56.306843 256 : 4252, 4029
7530 11:52:56.306916 260 : 4250, 4027
7531 11:52:56.309719 264 : 4250, 4027
7532 11:52:56.309790 268 : 4249, 4027
7533 11:52:56.313108 272 : 4252, 4029
7534 11:52:56.313191 276 : 4250, 4027
7535 11:52:56.313257 280 : 4363, 4140
7536 11:52:56.316180 284 : 4361, 4138
7537 11:52:56.316263 288 : 4247, 4024
7538 11:52:56.319643 292 : 4363, 4140
7539 11:52:56.319726 296 : 4360, 4138
7540 11:52:56.323409 300 : 4250, 4027
7541 11:52:56.323492 304 : 4250, 4027
7542 11:52:56.326251 308 : 4252, 4029
7543 11:52:56.326334 312 : 4250, 3993
7544 11:52:56.329903 316 : 4250, 2320
7545 11:52:56.329986 320 : 4250, 10
7546 11:52:56.330052
7547 11:52:56.333171 MIOCK jitter meter ch=0
7548 11:52:56.333253
7549 11:52:56.336459 1T = (320-92) = 228 dly cells
7550 11:52:56.339947 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7551 11:52:56.340029 ==
7552 11:52:56.343104 Dram Type= 6, Freq= 0, CH_0, rank 0
7553 11:52:56.349779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 11:52:56.349862 ==
7555 11:52:56.352928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 11:52:56.359619 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 11:52:56.363148 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 11:52:56.369904 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 11:52:56.377475 [CA 0] Center 43 (13~73) winsize 61
7560 11:52:56.380442 [CA 1] Center 43 (13~73) winsize 61
7561 11:52:56.383998 [CA 2] Center 38 (8~68) winsize 61
7562 11:52:56.387020 [CA 3] Center 37 (8~67) winsize 60
7563 11:52:56.390461 [CA 4] Center 36 (6~67) winsize 62
7564 11:52:56.393896 [CA 5] Center 35 (5~65) winsize 61
7565 11:52:56.393978
7566 11:52:56.397284 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 11:52:56.397367
7568 11:52:56.401171 [CATrainingPosCal] consider 1 rank data
7569 11:52:56.404006 u2DelayCellTimex100 = 285/100 ps
7570 11:52:56.407381 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7571 11:52:56.413725 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7572 11:52:56.417477 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7573 11:52:56.420255 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7574 11:52:56.423709 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
7575 11:52:56.427270 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7576 11:52:56.427352
7577 11:52:56.430688 CA PerBit enable=1, Macro0, CA PI delay=35
7578 11:52:56.430771
7579 11:52:56.434226 [CBTSetCACLKResult] CA Dly = 35
7580 11:52:56.434308 CS Dly: 9 (0~40)
7581 11:52:56.440475 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 11:52:56.443950 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 11:52:56.444028 ==
7584 11:52:56.447336 Dram Type= 6, Freq= 0, CH_0, rank 1
7585 11:52:56.450523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 11:52:56.450611 ==
7587 11:52:56.457214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7588 11:52:56.460786 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7589 11:52:56.467130 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7590 11:52:56.470548 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7591 11:52:56.480525 [CA 0] Center 43 (13~73) winsize 61
7592 11:52:56.483793 [CA 1] Center 43 (13~73) winsize 61
7593 11:52:56.487148 [CA 2] Center 37 (8~67) winsize 60
7594 11:52:56.490720 [CA 3] Center 38 (9~67) winsize 59
7595 11:52:56.494005 [CA 4] Center 36 (6~67) winsize 62
7596 11:52:56.497153 [CA 5] Center 36 (6~66) winsize 61
7597 11:52:56.497259
7598 11:52:56.500252 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7599 11:52:56.500333
7600 11:52:56.503954 [CATrainingPosCal] consider 2 rank data
7601 11:52:56.507321 u2DelayCellTimex100 = 285/100 ps
7602 11:52:56.510299 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7603 11:52:56.517066 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7604 11:52:56.520565 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7605 11:52:56.523725 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7606 11:52:56.527289 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
7607 11:52:56.530511 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7608 11:52:56.530584
7609 11:52:56.533392 CA PerBit enable=1, Macro0, CA PI delay=35
7610 11:52:56.533466
7611 11:52:56.536857 [CBTSetCACLKResult] CA Dly = 35
7612 11:52:56.540125 CS Dly: 10 (0~42)
7613 11:52:56.543462 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7614 11:52:56.546701 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7615 11:52:56.546782
7616 11:52:56.549945 ----->DramcWriteLeveling(PI) begin...
7617 11:52:56.550018 ==
7618 11:52:56.553385 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 11:52:56.559986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 11:52:56.560064 ==
7621 11:52:56.563069 Write leveling (Byte 0): 36 => 36
7622 11:52:56.566502 Write leveling (Byte 1): 31 => 31
7623 11:52:56.566580 DramcWriteLeveling(PI) end<-----
7624 11:52:56.566642
7625 11:52:56.569665 ==
7626 11:52:56.573281 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 11:52:56.576491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 11:52:56.576572 ==
7629 11:52:56.580286 [Gating] SW mode calibration
7630 11:52:56.586712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7631 11:52:56.590051 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7632 11:52:56.596392 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 11:52:56.599955 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 11:52:56.603159 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7635 11:52:56.609364 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7636 11:52:56.612773 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7637 11:52:56.616127 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7638 11:52:56.622831 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 11:52:56.625929 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 11:52:56.629335 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 11:52:56.635872 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 11:52:56.639594 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
7643 11:52:56.642566 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7644 11:52:56.649302 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7645 11:52:56.652433 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7646 11:52:56.655664 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:52:56.662691 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 11:52:56.665857 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 11:52:56.669015 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 11:52:56.675554 1 6 8 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7651 11:52:56.678887 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7652 11:52:56.682620 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
7653 11:52:56.689001 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:52:56.691977 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 11:52:56.695690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 11:52:56.702259 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 11:52:56.705801 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 11:52:56.709005 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 11:52:56.715538 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7660 11:52:56.718941 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7661 11:52:56.722534 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7662 11:52:56.729359 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7663 11:52:56.732217 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:52:56.735315 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:52:56.739007 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:52:56.745399 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:52:56.748791 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:52:56.752116 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:52:56.758899 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:52:56.762210 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:52:56.765360 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:52:56.772212 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:52:56.775288 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 11:52:56.778882 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 11:52:56.785790 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7676 11:52:56.789107 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7677 11:52:56.792367 Total UI for P1: 0, mck2ui 16
7678 11:52:56.795305 best dqsien dly found for B0: ( 1, 9, 12)
7679 11:52:56.799038 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7680 11:52:56.805591 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 11:52:56.805674 Total UI for P1: 0, mck2ui 16
7682 11:52:56.808714 best dqsien dly found for B1: ( 1, 9, 20)
7683 11:52:56.815553 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7684 11:52:56.818582 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7685 11:52:56.818664
7686 11:52:56.821875 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7687 11:52:56.825694 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7688 11:52:56.828760 [Gating] SW calibration Done
7689 11:52:56.828843 ==
7690 11:52:56.832296 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 11:52:56.835470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 11:52:56.835553 ==
7693 11:52:56.838620 RX Vref Scan: 0
7694 11:52:56.838701
7695 11:52:56.838765 RX Vref 0 -> 0, step: 1
7696 11:52:56.838826
7697 11:52:56.842507 RX Delay 0 -> 252, step: 8
7698 11:52:56.845127 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7699 11:52:56.852094 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7700 11:52:56.855529 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7701 11:52:56.859025 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7702 11:52:56.862085 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7703 11:52:56.865120 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7704 11:52:56.868400 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7705 11:52:56.875230 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7706 11:52:56.878404 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7707 11:52:56.881848 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7708 11:52:56.885435 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7709 11:52:56.888699 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7710 11:52:56.895232 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7711 11:52:56.898721 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7712 11:52:56.902144 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7713 11:52:56.905213 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7714 11:52:56.905297 ==
7715 11:52:56.908371 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 11:52:56.915064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 11:52:56.915144 ==
7718 11:52:56.915211 DQS Delay:
7719 11:52:56.915276 DQS0 = 0, DQS1 = 0
7720 11:52:56.918884 DQM Delay:
7721 11:52:56.918955 DQM0 = 138, DQM1 = 127
7722 11:52:56.921899 DQ Delay:
7723 11:52:56.925128 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7724 11:52:56.928816 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7725 11:52:56.931673 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7726 11:52:56.935026 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7727 11:52:56.935096
7728 11:52:56.935157
7729 11:52:56.935216 ==
7730 11:52:56.938288 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 11:52:56.941899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 11:52:56.945419 ==
7733 11:52:56.945496
7734 11:52:56.945559
7735 11:52:56.945618 TX Vref Scan disable
7736 11:52:56.948458 == TX Byte 0 ==
7737 11:52:56.951986 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7738 11:52:56.955550 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7739 11:52:56.958332 == TX Byte 1 ==
7740 11:52:56.961535 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7741 11:52:56.964942 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7742 11:52:56.965014 ==
7743 11:52:56.968470 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:52:56.974765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:52:56.974843 ==
7746 11:52:56.988062
7747 11:52:56.991493 TX Vref early break, caculate TX vref
7748 11:52:56.994753 TX Vref=16, minBit 12, minWin=22, winSum=376
7749 11:52:56.997994 TX Vref=18, minBit 8, minWin=23, winSum=388
7750 11:52:57.001351 TX Vref=20, minBit 1, minWin=24, winSum=394
7751 11:52:57.004942 TX Vref=22, minBit 1, minWin=24, winSum=403
7752 11:52:57.008141 TX Vref=24, minBit 0, minWin=24, winSum=410
7753 11:52:57.015669 TX Vref=26, minBit 7, minWin=25, winSum=420
7754 11:52:57.017904 TX Vref=28, minBit 0, minWin=26, winSum=426
7755 11:52:57.021258 TX Vref=30, minBit 2, minWin=25, winSum=424
7756 11:52:57.025067 TX Vref=32, minBit 0, minWin=25, winSum=413
7757 11:52:57.028374 TX Vref=34, minBit 0, minWin=24, winSum=407
7758 11:52:57.031383 TX Vref=36, minBit 7, minWin=23, winSum=394
7759 11:52:57.038358 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
7760 11:52:57.038477
7761 11:52:57.041749 Final TX Range 0 Vref 28
7762 11:52:57.041821
7763 11:52:57.041882 ==
7764 11:52:57.044878 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 11:52:57.048042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 11:52:57.048118 ==
7767 11:52:57.048180
7768 11:52:57.048238
7769 11:52:57.051474 TX Vref Scan disable
7770 11:52:57.057956 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7771 11:52:57.058030 == TX Byte 0 ==
7772 11:52:57.061333 u2DelayCellOfst[0]=13 cells (4 PI)
7773 11:52:57.064846 u2DelayCellOfst[1]=17 cells (5 PI)
7774 11:52:57.068322 u2DelayCellOfst[2]=10 cells (3 PI)
7775 11:52:57.071179 u2DelayCellOfst[3]=13 cells (4 PI)
7776 11:52:57.074371 u2DelayCellOfst[4]=10 cells (3 PI)
7777 11:52:57.078225 u2DelayCellOfst[5]=0 cells (0 PI)
7778 11:52:57.081446 u2DelayCellOfst[6]=17 cells (5 PI)
7779 11:52:57.084742 u2DelayCellOfst[7]=13 cells (4 PI)
7780 11:52:57.087724 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7781 11:52:57.091079 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7782 11:52:57.094412 == TX Byte 1 ==
7783 11:52:57.097801 u2DelayCellOfst[8]=0 cells (0 PI)
7784 11:52:57.101491 u2DelayCellOfst[9]=0 cells (0 PI)
7785 11:52:57.101562 u2DelayCellOfst[10]=10 cells (3 PI)
7786 11:52:57.104438 u2DelayCellOfst[11]=3 cells (1 PI)
7787 11:52:57.107533 u2DelayCellOfst[12]=13 cells (4 PI)
7788 11:52:57.110791 u2DelayCellOfst[13]=13 cells (4 PI)
7789 11:52:57.114466 u2DelayCellOfst[14]=17 cells (5 PI)
7790 11:52:57.117777 u2DelayCellOfst[15]=10 cells (3 PI)
7791 11:52:57.124302 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7792 11:52:57.127722 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7793 11:52:57.127792 DramC Write-DBI on
7794 11:52:57.127852 ==
7795 11:52:57.131219 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 11:52:57.137840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 11:52:57.137916 ==
7798 11:52:57.137977
7799 11:52:57.138035
7800 11:52:57.138099 TX Vref Scan disable
7801 11:52:57.141883 == TX Byte 0 ==
7802 11:52:57.145553 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7803 11:52:57.148625 == TX Byte 1 ==
7804 11:52:57.151867 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7805 11:52:57.155162 DramC Write-DBI off
7806 11:52:57.155233
7807 11:52:57.155301 [DATLAT]
7808 11:52:57.155359 Freq=1600, CH0 RK0
7809 11:52:57.155415
7810 11:52:57.158590 DATLAT Default: 0xf
7811 11:52:57.158672 0, 0xFFFF, sum = 0
7812 11:52:57.161531 1, 0xFFFF, sum = 0
7813 11:52:57.161607 2, 0xFFFF, sum = 0
7814 11:52:57.165471 3, 0xFFFF, sum = 0
7815 11:52:57.168165 4, 0xFFFF, sum = 0
7816 11:52:57.168249 5, 0xFFFF, sum = 0
7817 11:52:57.172001 6, 0xFFFF, sum = 0
7818 11:52:57.172084 7, 0xFFFF, sum = 0
7819 11:52:57.175009 8, 0xFFFF, sum = 0
7820 11:52:57.175093 9, 0xFFFF, sum = 0
7821 11:52:57.178131 10, 0xFFFF, sum = 0
7822 11:52:57.178246 11, 0xFFFF, sum = 0
7823 11:52:57.181636 12, 0xFFFF, sum = 0
7824 11:52:57.181719 13, 0xFFFF, sum = 0
7825 11:52:57.185095 14, 0x0, sum = 1
7826 11:52:57.185180 15, 0x0, sum = 2
7827 11:52:57.188501 16, 0x0, sum = 3
7828 11:52:57.188584 17, 0x0, sum = 4
7829 11:52:57.191508 best_step = 15
7830 11:52:57.191590
7831 11:52:57.191657 ==
7832 11:52:57.194880 Dram Type= 6, Freq= 0, CH_0, rank 0
7833 11:52:57.198222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7834 11:52:57.198304 ==
7835 11:52:57.198372 RX Vref Scan: 1
7836 11:52:57.201862
7837 11:52:57.201944 Set Vref Range= 24 -> 127
7838 11:52:57.202009
7839 11:52:57.205371 RX Vref 24 -> 127, step: 1
7840 11:52:57.205453
7841 11:52:57.207999 RX Delay 19 -> 252, step: 4
7842 11:52:57.208081
7843 11:52:57.211795 Set Vref, RX VrefLevel [Byte0]: 24
7844 11:52:57.215048 [Byte1]: 24
7845 11:52:57.215135
7846 11:52:57.218153 Set Vref, RX VrefLevel [Byte0]: 25
7847 11:52:57.221643 [Byte1]: 25
7848 11:52:57.221727
7849 11:52:57.225009 Set Vref, RX VrefLevel [Byte0]: 26
7850 11:52:57.228274 [Byte1]: 26
7851 11:52:57.232601
7852 11:52:57.232685 Set Vref, RX VrefLevel [Byte0]: 27
7853 11:52:57.235800 [Byte1]: 27
7854 11:52:57.239605
7855 11:52:57.239714 Set Vref, RX VrefLevel [Byte0]: 28
7856 11:52:57.242968 [Byte1]: 28
7857 11:52:57.247237
7858 11:52:57.247318 Set Vref, RX VrefLevel [Byte0]: 29
7859 11:52:57.250234 [Byte1]: 29
7860 11:52:57.254719
7861 11:52:57.254801 Set Vref, RX VrefLevel [Byte0]: 30
7862 11:52:57.257807 [Byte1]: 30
7863 11:52:57.262047
7864 11:52:57.262128 Set Vref, RX VrefLevel [Byte0]: 31
7865 11:52:57.265809 [Byte1]: 31
7866 11:52:57.269814
7867 11:52:57.269899 Set Vref, RX VrefLevel [Byte0]: 32
7868 11:52:57.273186 [Byte1]: 32
7869 11:52:57.277847
7870 11:52:57.277932 Set Vref, RX VrefLevel [Byte0]: 33
7871 11:52:57.280944 [Byte1]: 33
7872 11:52:57.284855
7873 11:52:57.284939 Set Vref, RX VrefLevel [Byte0]: 34
7874 11:52:57.288509 [Byte1]: 34
7875 11:52:57.292430
7876 11:52:57.292514 Set Vref, RX VrefLevel [Byte0]: 35
7877 11:52:57.295998 [Byte1]: 35
7878 11:52:57.299947
7879 11:52:57.300031 Set Vref, RX VrefLevel [Byte0]: 36
7880 11:52:57.303391 [Byte1]: 36
7881 11:52:57.308130
7882 11:52:57.308214 Set Vref, RX VrefLevel [Byte0]: 37
7883 11:52:57.311061 [Byte1]: 37
7884 11:52:57.315418
7885 11:52:57.315526 Set Vref, RX VrefLevel [Byte0]: 38
7886 11:52:57.318963 [Byte1]: 38
7887 11:52:57.323047
7888 11:52:57.323128 Set Vref, RX VrefLevel [Byte0]: 39
7889 11:52:57.326059 [Byte1]: 39
7890 11:52:57.330865
7891 11:52:57.330946 Set Vref, RX VrefLevel [Byte0]: 40
7892 11:52:57.333791 [Byte1]: 40
7893 11:52:57.338246
7894 11:52:57.338328 Set Vref, RX VrefLevel [Byte0]: 41
7895 11:52:57.341185 [Byte1]: 41
7896 11:52:57.345735
7897 11:52:57.345815 Set Vref, RX VrefLevel [Byte0]: 42
7898 11:52:57.348991 [Byte1]: 42
7899 11:52:57.353240
7900 11:52:57.353322 Set Vref, RX VrefLevel [Byte0]: 43
7901 11:52:57.356364 [Byte1]: 43
7902 11:52:57.360688
7903 11:52:57.360770 Set Vref, RX VrefLevel [Byte0]: 44
7904 11:52:57.364088 [Byte1]: 44
7905 11:52:57.368549
7906 11:52:57.368631 Set Vref, RX VrefLevel [Byte0]: 45
7907 11:52:57.371678 [Byte1]: 45
7908 11:52:57.375893
7909 11:52:57.375975 Set Vref, RX VrefLevel [Byte0]: 46
7910 11:52:57.379415 [Byte1]: 46
7911 11:52:57.383326
7912 11:52:57.383411 Set Vref, RX VrefLevel [Byte0]: 47
7913 11:52:57.386710 [Byte1]: 47
7914 11:52:57.390946
7915 11:52:57.391055 Set Vref, RX VrefLevel [Byte0]: 48
7916 11:52:57.394316 [Byte1]: 48
7917 11:52:57.398501
7918 11:52:57.398584 Set Vref, RX VrefLevel [Byte0]: 49
7919 11:52:57.402269 [Byte1]: 49
7920 11:52:57.406483
7921 11:52:57.406565 Set Vref, RX VrefLevel [Byte0]: 50
7922 11:52:57.409308 [Byte1]: 50
7923 11:52:57.413526
7924 11:52:57.413608 Set Vref, RX VrefLevel [Byte0]: 51
7925 11:52:57.417316 [Byte1]: 51
7926 11:52:57.421411
7927 11:52:57.421493 Set Vref, RX VrefLevel [Byte0]: 52
7928 11:52:57.424658 [Byte1]: 52
7929 11:52:57.429075
7930 11:52:57.429157 Set Vref, RX VrefLevel [Byte0]: 53
7931 11:52:57.431984 [Byte1]: 53
7932 11:52:57.436322
7933 11:52:57.436404 Set Vref, RX VrefLevel [Byte0]: 54
7934 11:52:57.439749 [Byte1]: 54
7935 11:52:57.443868
7936 11:52:57.443950 Set Vref, RX VrefLevel [Byte0]: 55
7937 11:52:57.447236 [Byte1]: 55
7938 11:52:57.451933
7939 11:52:57.452015 Set Vref, RX VrefLevel [Byte0]: 56
7940 11:52:57.454628 [Byte1]: 56
7941 11:52:57.459369
7942 11:52:57.459451 Set Vref, RX VrefLevel [Byte0]: 57
7943 11:52:57.463143 [Byte1]: 57
7944 11:52:57.466848
7945 11:52:57.466931 Set Vref, RX VrefLevel [Byte0]: 58
7946 11:52:57.470247 [Byte1]: 58
7947 11:52:57.474284
7948 11:52:57.474372 Set Vref, RX VrefLevel [Byte0]: 59
7949 11:52:57.477762 [Byte1]: 59
7950 11:52:57.481635
7951 11:52:57.481744 Set Vref, RX VrefLevel [Byte0]: 60
7952 11:52:57.485118 [Byte1]: 60
7953 11:52:57.489503
7954 11:52:57.489603 Set Vref, RX VrefLevel [Byte0]: 61
7955 11:52:57.492927 [Byte1]: 61
7956 11:52:57.496785
7957 11:52:57.496887 Set Vref, RX VrefLevel [Byte0]: 62
7958 11:52:57.500537 [Byte1]: 62
7959 11:52:57.504737
7960 11:52:57.504814 Set Vref, RX VrefLevel [Byte0]: 63
7961 11:52:57.507774 [Byte1]: 63
7962 11:52:57.511984
7963 11:52:57.512056 Set Vref, RX VrefLevel [Byte0]: 64
7964 11:52:57.515392 [Byte1]: 64
7965 11:52:57.519777
7966 11:52:57.519852 Set Vref, RX VrefLevel [Byte0]: 65
7967 11:52:57.523068 [Byte1]: 65
7968 11:52:57.527154
7969 11:52:57.527239 Set Vref, RX VrefLevel [Byte0]: 66
7970 11:52:57.530502 [Byte1]: 66
7971 11:52:57.534804
7972 11:52:57.534885 Set Vref, RX VrefLevel [Byte0]: 67
7973 11:52:57.538046 [Byte1]: 67
7974 11:52:57.542298
7975 11:52:57.542439 Set Vref, RX VrefLevel [Byte0]: 68
7976 11:52:57.545863 [Byte1]: 68
7977 11:52:57.549905
7978 11:52:57.549987 Set Vref, RX VrefLevel [Byte0]: 69
7979 11:52:57.553461 [Byte1]: 69
7980 11:52:57.557818
7981 11:52:57.557893 Set Vref, RX VrefLevel [Byte0]: 70
7982 11:52:57.560729 [Byte1]: 70
7983 11:52:57.565171
7984 11:52:57.565253 Set Vref, RX VrefLevel [Byte0]: 71
7985 11:52:57.568237 [Byte1]: 71
7986 11:52:57.573087
7987 11:52:57.573159 Set Vref, RX VrefLevel [Byte0]: 72
7988 11:52:57.575949 [Byte1]: 72
7989 11:52:57.580455
7990 11:52:57.580538 Set Vref, RX VrefLevel [Byte0]: 73
7991 11:52:57.583832 [Byte1]: 73
7992 11:52:57.588045
7993 11:52:57.588127 Set Vref, RX VrefLevel [Byte0]: 74
7994 11:52:57.590962 [Byte1]: 74
7995 11:52:57.595802
7996 11:52:57.595883 Set Vref, RX VrefLevel [Byte0]: 75
7997 11:52:57.598946 [Byte1]: 75
7998 11:52:57.603013
7999 11:52:57.603095 Set Vref, RX VrefLevel [Byte0]: 76
8000 11:52:57.606213 [Byte1]: 76
8001 11:52:57.610859
8002 11:52:57.610941 Set Vref, RX VrefLevel [Byte0]: 77
8003 11:52:57.613813 [Byte1]: 77
8004 11:52:57.618308
8005 11:52:57.618412 Set Vref, RX VrefLevel [Byte0]: 78
8006 11:52:57.621995 [Byte1]: 78
8007 11:52:57.625909
8008 11:52:57.625991 Set Vref, RX VrefLevel [Byte0]: 79
8009 11:52:57.629006 [Byte1]: 79
8010 11:52:57.633631
8011 11:52:57.633712 Set Vref, RX VrefLevel [Byte0]: 80
8012 11:52:57.636951 [Byte1]: 80
8013 11:52:57.641041
8014 11:52:57.641123 Final RX Vref Byte 0 = 60 to rank0
8015 11:52:57.644234 Final RX Vref Byte 1 = 61 to rank0
8016 11:52:57.647675 Final RX Vref Byte 0 = 60 to rank1
8017 11:52:57.651077 Final RX Vref Byte 1 = 61 to rank1==
8018 11:52:57.653912 Dram Type= 6, Freq= 0, CH_0, rank 0
8019 11:52:57.660903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 11:52:57.660989 ==
8021 11:52:57.661073 DQS Delay:
8022 11:52:57.661155 DQS0 = 0, DQS1 = 0
8023 11:52:57.664065 DQM Delay:
8024 11:52:57.664152 DQM0 = 136, DQM1 = 124
8025 11:52:57.667638 DQ Delay:
8026 11:52:57.670768 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8027 11:52:57.674205 DQ4 =138, DQ5 =126, DQ6 =142, DQ7 =144
8028 11:52:57.677808 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8029 11:52:57.680623 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
8030 11:52:57.680708
8031 11:52:57.680791
8032 11:52:57.680869
8033 11:52:57.684289 [DramC_TX_OE_Calibration] TA2
8034 11:52:57.687312 Original DQ_B0 (3 6) =30, OEN = 27
8035 11:52:57.690952 Original DQ_B1 (3 6) =30, OEN = 27
8036 11:52:57.694110 24, 0x0, End_B0=24 End_B1=24
8037 11:52:57.694191 25, 0x0, End_B0=25 End_B1=25
8038 11:52:57.697400 26, 0x0, End_B0=26 End_B1=26
8039 11:52:57.701237 27, 0x0, End_B0=27 End_B1=27
8040 11:52:57.704071 28, 0x0, End_B0=28 End_B1=28
8041 11:52:57.704146 29, 0x0, End_B0=29 End_B1=29
8042 11:52:57.708006 30, 0x0, End_B0=30 End_B1=30
8043 11:52:57.710959 31, 0x4141, End_B0=30 End_B1=30
8044 11:52:57.714389 Byte0 end_step=30 best_step=27
8045 11:52:57.717270 Byte1 end_step=30 best_step=27
8046 11:52:57.720791 Byte0 TX OE(2T, 0.5T) = (3, 3)
8047 11:52:57.720865 Byte1 TX OE(2T, 0.5T) = (3, 3)
8048 11:52:57.720942
8049 11:52:57.723981
8050 11:52:57.730737 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8051 11:52:57.733933 CH0 RK0: MR19=303, MR18=201E
8052 11:52:57.740940 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8053 11:52:57.741048
8054 11:52:57.743811 ----->DramcWriteLeveling(PI) begin...
8055 11:52:57.743922 ==
8056 11:52:57.747173 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 11:52:57.750525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 11:52:57.750611 ==
8059 11:52:57.754102 Write leveling (Byte 0): 36 => 36
8060 11:52:57.757272 Write leveling (Byte 1): 29 => 29
8061 11:52:57.760732 DramcWriteLeveling(PI) end<-----
8062 11:52:57.760835
8063 11:52:57.760915 ==
8064 11:52:57.763984 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:52:57.767427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:52:57.767513 ==
8067 11:52:57.770492 [Gating] SW mode calibration
8068 11:52:57.777435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8069 11:52:57.783711 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8070 11:52:57.787515 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:52:57.790650 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:52:57.797191 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:52:57.800330 1 4 12 | B1->B0 | 2424 3232 | 1 0 | (0 0) (0 0)
8074 11:52:57.803798 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 11:52:57.810305 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 11:52:57.813660 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 11:52:57.817125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 11:52:57.823936 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 11:52:57.826852 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 11:52:57.830501 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 11:52:57.837065 1 5 12 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 1)
8082 11:52:57.840138 1 5 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8083 11:52:57.843594 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 11:52:57.850316 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 11:52:57.854078 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 11:52:57.857074 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 11:52:57.863470 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 11:52:57.866718 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8089 11:52:57.870255 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8090 11:52:57.877222 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 11:52:57.880190 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 11:52:57.883778 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 11:52:57.886713 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 11:52:57.893318 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 11:52:57.896672 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 11:52:57.900266 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8097 11:52:57.906794 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8098 11:52:57.910472 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:52:57.913422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8100 11:52:57.920194 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:52:57.923079 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:52:57.926695 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:52:57.933245 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:52:57.936640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:52:57.939608 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:52:57.946685 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:52:57.949728 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:52:57.952897 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:52:57.959603 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:52:57.963120 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:52:57.966204 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:52:57.972867 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:52:57.976481 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8114 11:52:57.979589 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8115 11:52:57.983036 Total UI for P1: 0, mck2ui 16
8116 11:52:57.986105 best dqsien dly found for B0: ( 1, 9, 12)
8117 11:52:57.993013 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 11:52:57.993096 Total UI for P1: 0, mck2ui 16
8119 11:52:57.999719 best dqsien dly found for B1: ( 1, 9, 14)
8120 11:52:58.003025 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8121 11:52:58.006322 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8122 11:52:58.006430
8123 11:52:58.009871 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8124 11:52:58.012602 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8125 11:52:58.016378 [Gating] SW calibration Done
8126 11:52:58.016461 ==
8127 11:52:58.019533 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 11:52:58.022714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 11:52:58.022831 ==
8130 11:52:58.025871 RX Vref Scan: 0
8131 11:52:58.025954
8132 11:52:58.026019 RX Vref 0 -> 0, step: 1
8133 11:52:58.026079
8134 11:52:58.029248 RX Delay 0 -> 252, step: 8
8135 11:52:58.033005 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8136 11:52:58.039382 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8137 11:52:58.042528 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8138 11:52:58.045862 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8139 11:52:58.049145 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8140 11:52:58.052714 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8141 11:52:58.059283 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8142 11:52:58.062549 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8143 11:52:58.065719 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8144 11:52:58.069077 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8145 11:52:58.072731 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8146 11:52:58.079254 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8147 11:52:58.082269 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8148 11:52:58.085714 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8149 11:52:58.089274 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8150 11:52:58.095623 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8151 11:52:58.095705 ==
8152 11:52:58.099026 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 11:52:58.102350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 11:52:58.102448 ==
8155 11:52:58.102514 DQS Delay:
8156 11:52:58.105801 DQS0 = 0, DQS1 = 0
8157 11:52:58.105883 DQM Delay:
8158 11:52:58.109162 DQM0 = 136, DQM1 = 125
8159 11:52:58.109261 DQ Delay:
8160 11:52:58.112232 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8161 11:52:58.115605 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8162 11:52:58.119215 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8163 11:52:58.122294 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8164 11:52:58.122424
8165 11:52:58.122505
8166 11:52:58.122565 ==
8167 11:52:58.125664 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 11:52:58.132535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 11:52:58.132619 ==
8170 11:52:58.132684
8171 11:52:58.132743
8172 11:52:58.132801 TX Vref Scan disable
8173 11:52:58.136683 == TX Byte 0 ==
8174 11:52:58.139433 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8175 11:52:58.145792 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8176 11:52:58.145875 == TX Byte 1 ==
8177 11:52:58.149341 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8178 11:52:58.152508 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8179 11:52:58.156023 ==
8180 11:52:58.159395 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 11:52:58.162414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 11:52:58.162538 ==
8183 11:52:58.175555
8184 11:52:58.178939 TX Vref early break, caculate TX vref
8185 11:52:58.182309 TX Vref=16, minBit 8, minWin=23, winSum=388
8186 11:52:58.185749 TX Vref=18, minBit 0, minWin=24, winSum=399
8187 11:52:58.188995 TX Vref=20, minBit 8, minWin=24, winSum=408
8188 11:52:58.192383 TX Vref=22, minBit 0, minWin=25, winSum=417
8189 11:52:58.195942 TX Vref=24, minBit 0, minWin=26, winSum=424
8190 11:52:58.202276 TX Vref=26, minBit 0, minWin=26, winSum=428
8191 11:52:58.205841 TX Vref=28, minBit 1, minWin=26, winSum=431
8192 11:52:58.209479 TX Vref=30, minBit 2, minWin=25, winSum=422
8193 11:52:58.212289 TX Vref=32, minBit 0, minWin=25, winSum=417
8194 11:52:58.216034 TX Vref=34, minBit 0, minWin=24, winSum=408
8195 11:52:58.222287 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
8196 11:52:58.222391
8197 11:52:58.225740 Final TX Range 0 Vref 28
8198 11:52:58.225823
8199 11:52:58.225888 ==
8200 11:52:58.229281 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 11:52:58.232554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 11:52:58.232641 ==
8203 11:52:58.232706
8204 11:52:58.232765
8205 11:52:58.235438 TX Vref Scan disable
8206 11:52:58.242289 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8207 11:52:58.242371 == TX Byte 0 ==
8208 11:52:58.245469 u2DelayCellOfst[0]=13 cells (4 PI)
8209 11:52:58.248952 u2DelayCellOfst[1]=20 cells (6 PI)
8210 11:52:58.252068 u2DelayCellOfst[2]=13 cells (4 PI)
8211 11:52:58.255548 u2DelayCellOfst[3]=13 cells (4 PI)
8212 11:52:58.259022 u2DelayCellOfst[4]=10 cells (3 PI)
8213 11:52:58.261934 u2DelayCellOfst[5]=0 cells (0 PI)
8214 11:52:58.265236 u2DelayCellOfst[6]=20 cells (6 PI)
8215 11:52:58.268647 u2DelayCellOfst[7]=20 cells (6 PI)
8216 11:52:58.272245 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8217 11:52:58.275650 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8218 11:52:58.275733 == TX Byte 1 ==
8219 11:52:58.278746 u2DelayCellOfst[8]=0 cells (0 PI)
8220 11:52:58.282337 u2DelayCellOfst[9]=0 cells (0 PI)
8221 11:52:58.285682 u2DelayCellOfst[10]=3 cells (1 PI)
8222 11:52:58.288650 u2DelayCellOfst[11]=0 cells (0 PI)
8223 11:52:58.292156 u2DelayCellOfst[12]=10 cells (3 PI)
8224 11:52:58.295719 u2DelayCellOfst[13]=10 cells (3 PI)
8225 11:52:58.298678 u2DelayCellOfst[14]=10 cells (3 PI)
8226 11:52:58.302368 u2DelayCellOfst[15]=6 cells (2 PI)
8227 11:52:58.305645 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8228 11:52:58.312094 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8229 11:52:58.312178 DramC Write-DBI on
8230 11:52:58.312254 ==
8231 11:52:58.315776 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 11:52:58.318715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 11:52:58.318799 ==
8234 11:52:58.322221
8235 11:52:58.322305
8236 11:52:58.322370 TX Vref Scan disable
8237 11:52:58.325559 == TX Byte 0 ==
8238 11:52:58.328506 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8239 11:52:58.332106 == TX Byte 1 ==
8240 11:52:58.335214 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8241 11:52:58.335299 DramC Write-DBI off
8242 11:52:58.338329
8243 11:52:58.338464 [DATLAT]
8244 11:52:58.338535 Freq=1600, CH0 RK1
8245 11:52:58.338599
8246 11:52:58.342264 DATLAT Default: 0xf
8247 11:52:58.342369 0, 0xFFFF, sum = 0
8248 11:52:58.344987 1, 0xFFFF, sum = 0
8249 11:52:58.345090 2, 0xFFFF, sum = 0
8250 11:52:58.348408 3, 0xFFFF, sum = 0
8251 11:52:58.351852 4, 0xFFFF, sum = 0
8252 11:52:58.351959 5, 0xFFFF, sum = 0
8253 11:52:58.354887 6, 0xFFFF, sum = 0
8254 11:52:58.354991 7, 0xFFFF, sum = 0
8255 11:52:58.358158 8, 0xFFFF, sum = 0
8256 11:52:58.358258 9, 0xFFFF, sum = 0
8257 11:52:58.361633 10, 0xFFFF, sum = 0
8258 11:52:58.361737 11, 0xFFFF, sum = 0
8259 11:52:58.364838 12, 0xFFFF, sum = 0
8260 11:52:58.364953 13, 0xFFFF, sum = 0
8261 11:52:58.368132 14, 0x0, sum = 1
8262 11:52:58.368235 15, 0x0, sum = 2
8263 11:52:58.371648 16, 0x0, sum = 3
8264 11:52:58.371749 17, 0x0, sum = 4
8265 11:52:58.374959 best_step = 15
8266 11:52:58.375062
8267 11:52:58.375153 ==
8268 11:52:58.378288 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 11:52:58.381706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 11:52:58.381817 ==
8271 11:52:58.384679 RX Vref Scan: 0
8272 11:52:58.384784
8273 11:52:58.384877 RX Vref 0 -> 0, step: 1
8274 11:52:58.384976
8275 11:52:58.388284 RX Delay 11 -> 252, step: 4
8276 11:52:58.391300 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8277 11:52:58.398596 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8278 11:52:58.401331 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8279 11:52:58.404758 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8280 11:52:58.408399 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8281 11:52:58.411354 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8282 11:52:58.417887 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8283 11:52:58.421375 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8284 11:52:58.424541 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8285 11:52:58.427821 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8286 11:52:58.431363 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8287 11:52:58.438030 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8288 11:52:58.441362 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8289 11:52:58.444721 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8290 11:52:58.448208 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8291 11:52:58.451242 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8292 11:52:58.454815 ==
8293 11:52:58.458089 Dram Type= 6, Freq= 0, CH_0, rank 1
8294 11:52:58.461553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 11:52:58.461630 ==
8296 11:52:58.461695 DQS Delay:
8297 11:52:58.464655 DQS0 = 0, DQS1 = 0
8298 11:52:58.464754 DQM Delay:
8299 11:52:58.468259 DQM0 = 132, DQM1 = 123
8300 11:52:58.468357 DQ Delay:
8301 11:52:58.471578 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8302 11:52:58.474888 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8303 11:52:58.477956 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8304 11:52:58.481679 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8305 11:52:58.481783
8306 11:52:58.481876
8307 11:52:58.481965
8308 11:52:58.484785 [DramC_TX_OE_Calibration] TA2
8309 11:52:58.487897 Original DQ_B0 (3 6) =30, OEN = 27
8310 11:52:58.491128 Original DQ_B1 (3 6) =30, OEN = 27
8311 11:52:58.494624 24, 0x0, End_B0=24 End_B1=24
8312 11:52:58.498044 25, 0x0, End_B0=25 End_B1=25
8313 11:52:58.498157 26, 0x0, End_B0=26 End_B1=26
8314 11:52:58.501096 27, 0x0, End_B0=27 End_B1=27
8315 11:52:58.504494 28, 0x0, End_B0=28 End_B1=28
8316 11:52:58.507728 29, 0x0, End_B0=29 End_B1=29
8317 11:52:58.511138 30, 0x0, End_B0=30 End_B1=30
8318 11:52:58.511255 31, 0x4545, End_B0=30 End_B1=30
8319 11:52:58.514646 Byte0 end_step=30 best_step=27
8320 11:52:58.517716 Byte1 end_step=30 best_step=27
8321 11:52:58.521281 Byte0 TX OE(2T, 0.5T) = (3, 3)
8322 11:52:58.524260 Byte1 TX OE(2T, 0.5T) = (3, 3)
8323 11:52:58.524370
8324 11:52:58.524464
8325 11:52:58.531132 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8326 11:52:58.534215 CH0 RK1: MR19=303, MR18=210D
8327 11:52:58.540955 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8328 11:52:58.544129 [RxdqsGatingPostProcess] freq 1600
8329 11:52:58.551030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8330 11:52:58.551108 best DQS0 dly(2T, 0.5T) = (1, 1)
8331 11:52:58.554241 best DQS1 dly(2T, 0.5T) = (1, 1)
8332 11:52:58.558145 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8333 11:52:58.560575 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8334 11:52:58.564280 best DQS0 dly(2T, 0.5T) = (1, 1)
8335 11:52:58.567425 best DQS1 dly(2T, 0.5T) = (1, 1)
8336 11:52:58.570809 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8337 11:52:58.574097 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8338 11:52:58.577280 Pre-setting of DQS Precalculation
8339 11:52:58.580557 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8340 11:52:58.580660 ==
8341 11:52:58.584283 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 11:52:58.590919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 11:52:58.591022 ==
8344 11:52:58.593803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 11:52:58.600420 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 11:52:58.603766 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 11:52:58.610437 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 11:52:58.618357 [CA 0] Center 40 (11~70) winsize 60
8349 11:52:58.621648 [CA 1] Center 41 (11~71) winsize 61
8350 11:52:58.624883 [CA 2] Center 37 (7~67) winsize 61
8351 11:52:58.628334 [CA 3] Center 36 (7~66) winsize 60
8352 11:52:58.631402 [CA 4] Center 37 (7~67) winsize 61
8353 11:52:58.634685 [CA 5] Center 36 (6~66) winsize 61
8354 11:52:58.634761
8355 11:52:58.638059 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8356 11:52:58.638156
8357 11:52:58.641408 [CATrainingPosCal] consider 1 rank data
8358 11:52:58.644738 u2DelayCellTimex100 = 285/100 ps
8359 11:52:58.648091 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8360 11:52:58.654625 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8361 11:52:58.658498 CA2 delay=37 (7~67),Diff = 1 PI (3 cell)
8362 11:52:58.661763 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8363 11:52:58.664787 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8364 11:52:58.667927 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8365 11:52:58.668026
8366 11:52:58.671470 CA PerBit enable=1, Macro0, CA PI delay=36
8367 11:52:58.671568
8368 11:52:58.674687 [CBTSetCACLKResult] CA Dly = 36
8369 11:52:58.674768 CS Dly: 8 (0~39)
8370 11:52:58.681547 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 11:52:58.684732 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 11:52:58.684832 ==
8373 11:52:58.688119 Dram Type= 6, Freq= 0, CH_1, rank 1
8374 11:52:58.691152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 11:52:58.691241 ==
8376 11:52:58.697980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8377 11:52:58.701283 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8378 11:52:58.708084 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8379 11:52:58.711201 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8380 11:52:58.721314 [CA 0] Center 42 (12~72) winsize 61
8381 11:52:58.724751 [CA 1] Center 41 (11~71) winsize 61
8382 11:52:58.728026 [CA 2] Center 37 (8~67) winsize 60
8383 11:52:58.731556 [CA 3] Center 37 (8~66) winsize 59
8384 11:52:58.734865 [CA 4] Center 37 (8~67) winsize 60
8385 11:52:58.737745 [CA 5] Center 36 (7~66) winsize 60
8386 11:52:58.737847
8387 11:52:58.741250 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8388 11:52:58.741347
8389 11:52:58.744512 [CATrainingPosCal] consider 2 rank data
8390 11:52:58.747776 u2DelayCellTimex100 = 285/100 ps
8391 11:52:58.751196 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8392 11:52:58.758063 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8393 11:52:58.761131 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8394 11:52:58.764443 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8395 11:52:58.768240 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8396 11:52:58.771159 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8397 11:52:58.771232
8398 11:52:58.774629 CA PerBit enable=1, Macro0, CA PI delay=36
8399 11:52:58.774728
8400 11:52:58.778029 [CBTSetCACLKResult] CA Dly = 36
8401 11:52:58.781175 CS Dly: 10 (0~43)
8402 11:52:58.784470 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8403 11:52:58.787812 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8404 11:52:58.787893
8405 11:52:58.791399 ----->DramcWriteLeveling(PI) begin...
8406 11:52:58.791473 ==
8407 11:52:58.794683 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 11:52:58.797744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 11:52:58.801066 ==
8410 11:52:58.801135 Write leveling (Byte 0): 24 => 24
8411 11:52:58.804441 Write leveling (Byte 1): 27 => 27
8412 11:52:58.807919 DramcWriteLeveling(PI) end<-----
8413 11:52:58.807992
8414 11:52:58.808053 ==
8415 11:52:58.811506 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 11:52:58.817873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 11:52:58.817957 ==
8418 11:52:58.818023 [Gating] SW mode calibration
8419 11:52:58.827677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8420 11:52:58.831172 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8421 11:52:58.834679 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:52:58.841076 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:52:58.844328 1 4 8 | B1->B0 | 2727 2c2c | 1 1 | (1 1) (1 1)
8424 11:52:58.848021 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 11:52:58.854374 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 11:52:58.857765 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 11:52:58.861077 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 11:52:58.868326 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 11:52:58.870943 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 11:52:58.874529 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8431 11:52:58.881059 1 5 8 | B1->B0 | 3131 2d2d | 1 0 | (1 0) (0 1)
8432 11:52:58.884385 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8433 11:52:58.887261 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 11:52:58.894244 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 11:52:58.897697 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 11:52:58.900961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 11:52:58.907588 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 11:52:58.910816 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 11:52:58.914088 1 6 8 | B1->B0 | 3f3f 4242 | 1 0 | (0 0) (0 0)
8440 11:52:58.920913 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 11:52:58.923973 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 11:52:58.927628 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 11:52:58.934226 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 11:52:58.937057 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 11:52:58.940847 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 11:52:58.947169 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 11:52:58.950798 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8448 11:52:58.953863 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8449 11:52:58.960550 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8450 11:52:58.963870 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:52:58.967241 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:52:58.973764 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:52:58.977409 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:52:58.980579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:52:58.986692 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:52:58.990347 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:52:58.993633 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:52:59.000272 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:52:59.003617 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:52:59.006928 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:52:59.010008 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:52:59.016630 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:52:59.020242 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8464 11:52:59.026622 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8465 11:52:59.026708 Total UI for P1: 0, mck2ui 16
8466 11:52:59.029918 best dqsien dly found for B0: ( 1, 9, 8)
8467 11:52:59.036275 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8468 11:52:59.039709 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 11:52:59.042940 Total UI for P1: 0, mck2ui 16
8470 11:52:59.046559 best dqsien dly found for B1: ( 1, 9, 12)
8471 11:52:59.049523 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8472 11:52:59.053109 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8473 11:52:59.053192
8474 11:52:59.056228 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8475 11:52:59.062797 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8476 11:52:59.062880 [Gating] SW calibration Done
8477 11:52:59.062945 ==
8478 11:52:59.066330 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 11:52:59.072917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 11:52:59.073000 ==
8481 11:52:59.073065 RX Vref Scan: 0
8482 11:52:59.073124
8483 11:52:59.076422 RX Vref 0 -> 0, step: 1
8484 11:52:59.076504
8485 11:52:59.079500 RX Delay 0 -> 252, step: 8
8486 11:52:59.082961 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8487 11:52:59.085863 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8488 11:52:59.089471 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8489 11:52:59.092757 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8490 11:52:59.099436 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8491 11:52:59.102706 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8492 11:52:59.105883 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8493 11:52:59.109377 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8494 11:52:59.112423 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8495 11:52:59.119492 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8496 11:52:59.122593 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8497 11:52:59.126307 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8498 11:52:59.129037 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8499 11:52:59.132480 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8500 11:52:59.139159 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8501 11:52:59.142146 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8502 11:52:59.142233 ==
8503 11:52:59.145735 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 11:52:59.149074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 11:52:59.149157 ==
8506 11:52:59.152202 DQS Delay:
8507 11:52:59.152283 DQS0 = 0, DQS1 = 0
8508 11:52:59.152348 DQM Delay:
8509 11:52:59.155787 DQM0 = 138, DQM1 = 130
8510 11:52:59.155871 DQ Delay:
8511 11:52:59.158919 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8512 11:52:59.162288 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8513 11:52:59.169088 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8514 11:52:59.172497 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8515 11:52:59.172581
8516 11:52:59.172664
8517 11:52:59.172742 ==
8518 11:52:59.175756 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 11:52:59.179081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 11:52:59.179166 ==
8521 11:52:59.179269
8522 11:52:59.179366
8523 11:52:59.182099 TX Vref Scan disable
8524 11:52:59.182210 == TX Byte 0 ==
8525 11:52:59.188800 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8526 11:52:59.192451 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8527 11:52:59.192536 == TX Byte 1 ==
8528 11:52:59.198730 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8529 11:52:59.202048 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8530 11:52:59.202133 ==
8531 11:52:59.205619 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 11:52:59.208686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 11:52:59.208771 ==
8534 11:52:59.223651
8535 11:52:59.226803 TX Vref early break, caculate TX vref
8536 11:52:59.230125 TX Vref=16, minBit 10, minWin=22, winSum=369
8537 11:52:59.233489 TX Vref=18, minBit 10, minWin=22, winSum=382
8538 11:52:59.236830 TX Vref=20, minBit 10, minWin=23, winSum=392
8539 11:52:59.240361 TX Vref=22, minBit 11, minWin=24, winSum=401
8540 11:52:59.247114 TX Vref=24, minBit 10, minWin=24, winSum=414
8541 11:52:59.250129 TX Vref=26, minBit 10, minWin=25, winSum=419
8542 11:52:59.253363 TX Vref=28, minBit 10, minWin=25, winSum=422
8543 11:52:59.256815 TX Vref=30, minBit 12, minWin=25, winSum=419
8544 11:52:59.260187 TX Vref=32, minBit 9, minWin=24, winSum=406
8545 11:52:59.263388 TX Vref=34, minBit 13, minWin=23, winSum=400
8546 11:52:59.270200 TX Vref=36, minBit 10, minWin=22, winSum=390
8547 11:52:59.273328 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 28
8548 11:52:59.276987
8549 11:52:59.277071 Final TX Range 0 Vref 28
8550 11:52:59.277156
8551 11:52:59.277235 ==
8552 11:52:59.279943 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 11:52:59.287062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 11:52:59.287147 ==
8555 11:52:59.287230
8556 11:52:59.287308
8557 11:52:59.287384 TX Vref Scan disable
8558 11:52:59.293838 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8559 11:52:59.293923 == TX Byte 0 ==
8560 11:52:59.297422 u2DelayCellOfst[0]=13 cells (4 PI)
8561 11:52:59.300355 u2DelayCellOfst[1]=10 cells (3 PI)
8562 11:52:59.303838 u2DelayCellOfst[2]=0 cells (0 PI)
8563 11:52:59.307222 u2DelayCellOfst[3]=3 cells (1 PI)
8564 11:52:59.310535 u2DelayCellOfst[4]=6 cells (2 PI)
8565 11:52:59.313995 u2DelayCellOfst[5]=17 cells (5 PI)
8566 11:52:59.317028 u2DelayCellOfst[6]=17 cells (5 PI)
8567 11:52:59.320625 u2DelayCellOfst[7]=3 cells (1 PI)
8568 11:52:59.323765 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8569 11:52:59.326950 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8570 11:52:59.330363 == TX Byte 1 ==
8571 11:52:59.333924 u2DelayCellOfst[8]=0 cells (0 PI)
8572 11:52:59.336834 u2DelayCellOfst[9]=3 cells (1 PI)
8573 11:52:59.340378 u2DelayCellOfst[10]=6 cells (2 PI)
8574 11:52:59.340462 u2DelayCellOfst[11]=3 cells (1 PI)
8575 11:52:59.343620 u2DelayCellOfst[12]=13 cells (4 PI)
8576 11:52:59.346977 u2DelayCellOfst[13]=17 cells (5 PI)
8577 11:52:59.350135 u2DelayCellOfst[14]=20 cells (6 PI)
8578 11:52:59.353395 u2DelayCellOfst[15]=17 cells (5 PI)
8579 11:52:59.359898 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8580 11:52:59.363288 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8581 11:52:59.363397 DramC Write-DBI on
8582 11:52:59.367113 ==
8583 11:52:59.367188 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 11:52:59.373205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 11:52:59.373289 ==
8586 11:52:59.373354
8587 11:52:59.373413
8588 11:52:59.376654 TX Vref Scan disable
8589 11:52:59.376737 == TX Byte 0 ==
8590 11:52:59.383254 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8591 11:52:59.383341 == TX Byte 1 ==
8592 11:52:59.386392 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8593 11:52:59.389860 DramC Write-DBI off
8594 11:52:59.389942
8595 11:52:59.390007 [DATLAT]
8596 11:52:59.393314 Freq=1600, CH1 RK0
8597 11:52:59.393396
8598 11:52:59.393461 DATLAT Default: 0xf
8599 11:52:59.396553 0, 0xFFFF, sum = 0
8600 11:52:59.396637 1, 0xFFFF, sum = 0
8601 11:52:59.399875 2, 0xFFFF, sum = 0
8602 11:52:59.399959 3, 0xFFFF, sum = 0
8603 11:52:59.403207 4, 0xFFFF, sum = 0
8604 11:52:59.403291 5, 0xFFFF, sum = 0
8605 11:52:59.406727 6, 0xFFFF, sum = 0
8606 11:52:59.406837 7, 0xFFFF, sum = 0
8607 11:52:59.410089 8, 0xFFFF, sum = 0
8608 11:52:59.410200 9, 0xFFFF, sum = 0
8609 11:52:59.413210 10, 0xFFFF, sum = 0
8610 11:52:59.413294 11, 0xFFFF, sum = 0
8611 11:52:59.416459 12, 0xFFFF, sum = 0
8612 11:52:59.420133 13, 0xFFFF, sum = 0
8613 11:52:59.420217 14, 0x0, sum = 1
8614 11:52:59.420294 15, 0x0, sum = 2
8615 11:52:59.423372 16, 0x0, sum = 3
8616 11:52:59.423456 17, 0x0, sum = 4
8617 11:52:59.426326 best_step = 15
8618 11:52:59.426455
8619 11:52:59.426552 ==
8620 11:52:59.429970 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 11:52:59.433228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 11:52:59.433311 ==
8623 11:52:59.436602 RX Vref Scan: 1
8624 11:52:59.436684
8625 11:52:59.439874 Set Vref Range= 24 -> 127
8626 11:52:59.439957
8627 11:52:59.440022 RX Vref 24 -> 127, step: 1
8628 11:52:59.440082
8629 11:52:59.443009 RX Delay 19 -> 252, step: 4
8630 11:52:59.443117
8631 11:52:59.446711 Set Vref, RX VrefLevel [Byte0]: 24
8632 11:52:59.450252 [Byte1]: 24
8633 11:52:59.450334
8634 11:52:59.453211 Set Vref, RX VrefLevel [Byte0]: 25
8635 11:52:59.456474 [Byte1]: 25
8636 11:52:59.460409
8637 11:52:59.460509 Set Vref, RX VrefLevel [Byte0]: 26
8638 11:52:59.463722 [Byte1]: 26
8639 11:52:59.468298
8640 11:52:59.468381 Set Vref, RX VrefLevel [Byte0]: 27
8641 11:52:59.471055 [Byte1]: 27
8642 11:52:59.475741
8643 11:52:59.475824 Set Vref, RX VrefLevel [Byte0]: 28
8644 11:52:59.479191 [Byte1]: 28
8645 11:52:59.483628
8646 11:52:59.483711 Set Vref, RX VrefLevel [Byte0]: 29
8647 11:52:59.486555 [Byte1]: 29
8648 11:52:59.490639
8649 11:52:59.490722 Set Vref, RX VrefLevel [Byte0]: 30
8650 11:52:59.493911 [Byte1]: 30
8651 11:52:59.498326
8652 11:52:59.498445 Set Vref, RX VrefLevel [Byte0]: 31
8653 11:52:59.501293 [Byte1]: 31
8654 11:52:59.505835
8655 11:52:59.505939 Set Vref, RX VrefLevel [Byte0]: 32
8656 11:52:59.508957 [Byte1]: 32
8657 11:52:59.513327
8658 11:52:59.513409 Set Vref, RX VrefLevel [Byte0]: 33
8659 11:52:59.516411 [Byte1]: 33
8660 11:52:59.521274
8661 11:52:59.521356 Set Vref, RX VrefLevel [Byte0]: 34
8662 11:52:59.523930 [Byte1]: 34
8663 11:52:59.528430
8664 11:52:59.528512 Set Vref, RX VrefLevel [Byte0]: 35
8665 11:52:59.531810 [Byte1]: 35
8666 11:52:59.536032
8667 11:52:59.536169 Set Vref, RX VrefLevel [Byte0]: 36
8668 11:52:59.539634 [Byte1]: 36
8669 11:52:59.543483
8670 11:52:59.543570 Set Vref, RX VrefLevel [Byte0]: 37
8671 11:52:59.546961 [Byte1]: 37
8672 11:52:59.550942
8673 11:52:59.551025 Set Vref, RX VrefLevel [Byte0]: 38
8674 11:52:59.554656 [Byte1]: 38
8675 11:52:59.559040
8676 11:52:59.559122 Set Vref, RX VrefLevel [Byte0]: 39
8677 11:52:59.561864 [Byte1]: 39
8678 11:52:59.566344
8679 11:52:59.566473 Set Vref, RX VrefLevel [Byte0]: 40
8680 11:52:59.569681 [Byte1]: 40
8681 11:52:59.573782
8682 11:52:59.573864 Set Vref, RX VrefLevel [Byte0]: 41
8683 11:52:59.577404 [Byte1]: 41
8684 11:52:59.581463
8685 11:52:59.584495 Set Vref, RX VrefLevel [Byte0]: 42
8686 11:52:59.584579 [Byte1]: 42
8687 11:52:59.588951
8688 11:52:59.589033 Set Vref, RX VrefLevel [Byte0]: 43
8689 11:52:59.592347 [Byte1]: 43
8690 11:52:59.596588
8691 11:52:59.596671 Set Vref, RX VrefLevel [Byte0]: 44
8692 11:52:59.599798 [Byte1]: 44
8693 11:52:59.604320
8694 11:52:59.604402 Set Vref, RX VrefLevel [Byte0]: 45
8695 11:52:59.607429 [Byte1]: 45
8696 11:52:59.611830
8697 11:52:59.611912 Set Vref, RX VrefLevel [Byte0]: 46
8698 11:52:59.615019 [Byte1]: 46
8699 11:52:59.619172
8700 11:52:59.619254 Set Vref, RX VrefLevel [Byte0]: 47
8701 11:52:59.622546 [Byte1]: 47
8702 11:52:59.626903
8703 11:52:59.626986 Set Vref, RX VrefLevel [Byte0]: 48
8704 11:52:59.630243 [Byte1]: 48
8705 11:52:59.634534
8706 11:52:59.634633 Set Vref, RX VrefLevel [Byte0]: 49
8707 11:52:59.637777 [Byte1]: 49
8708 11:52:59.642133
8709 11:52:59.642241 Set Vref, RX VrefLevel [Byte0]: 50
8710 11:52:59.645332 [Byte1]: 50
8711 11:52:59.649844
8712 11:52:59.649927 Set Vref, RX VrefLevel [Byte0]: 51
8713 11:52:59.652750 [Byte1]: 51
8714 11:52:59.656979
8715 11:52:59.657061 Set Vref, RX VrefLevel [Byte0]: 52
8716 11:52:59.660452 [Byte1]: 52
8717 11:52:59.664605
8718 11:52:59.664722 Set Vref, RX VrefLevel [Byte0]: 53
8719 11:52:59.668393 [Byte1]: 53
8720 11:52:59.672394
8721 11:52:59.672477 Set Vref, RX VrefLevel [Byte0]: 54
8722 11:52:59.675867 [Byte1]: 54
8723 11:52:59.679842
8724 11:52:59.679925 Set Vref, RX VrefLevel [Byte0]: 55
8725 11:52:59.683498 [Byte1]: 55
8726 11:52:59.687368
8727 11:52:59.687450 Set Vref, RX VrefLevel [Byte0]: 56
8728 11:52:59.690541 [Byte1]: 56
8729 11:52:59.695182
8730 11:52:59.695265 Set Vref, RX VrefLevel [Byte0]: 57
8731 11:52:59.698510 [Byte1]: 57
8732 11:52:59.702380
8733 11:52:59.702483 Set Vref, RX VrefLevel [Byte0]: 58
8734 11:52:59.706382 [Byte1]: 58
8735 11:52:59.710061
8736 11:52:59.710144 Set Vref, RX VrefLevel [Byte0]: 59
8737 11:52:59.716715 [Byte1]: 59
8738 11:52:59.716799
8739 11:52:59.720188 Set Vref, RX VrefLevel [Byte0]: 60
8740 11:52:59.723352 [Byte1]: 60
8741 11:52:59.723436
8742 11:52:59.726939 Set Vref, RX VrefLevel [Byte0]: 61
8743 11:52:59.729959 [Byte1]: 61
8744 11:52:59.730043
8745 11:52:59.733308 Set Vref, RX VrefLevel [Byte0]: 62
8746 11:52:59.736505 [Byte1]: 62
8747 11:52:59.740847
8748 11:52:59.740930 Set Vref, RX VrefLevel [Byte0]: 63
8749 11:52:59.743853 [Byte1]: 63
8750 11:52:59.747961
8751 11:52:59.748044 Set Vref, RX VrefLevel [Byte0]: 64
8752 11:52:59.751528 [Byte1]: 64
8753 11:52:59.755741
8754 11:52:59.755823 Set Vref, RX VrefLevel [Byte0]: 65
8755 11:52:59.759052 [Byte1]: 65
8756 11:52:59.763013
8757 11:52:59.763127 Set Vref, RX VrefLevel [Byte0]: 66
8758 11:52:59.766364 [Byte1]: 66
8759 11:52:59.770835
8760 11:52:59.770934 Set Vref, RX VrefLevel [Byte0]: 67
8761 11:52:59.774337 [Byte1]: 67
8762 11:52:59.778258
8763 11:52:59.778342 Set Vref, RX VrefLevel [Byte0]: 68
8764 11:52:59.781743 [Byte1]: 68
8765 11:52:59.786321
8766 11:52:59.786429 Set Vref, RX VrefLevel [Byte0]: 69
8767 11:52:59.789659 [Byte1]: 69
8768 11:52:59.793946
8769 11:52:59.794021 Set Vref, RX VrefLevel [Byte0]: 70
8770 11:52:59.796587 [Byte1]: 70
8771 11:52:59.800900
8772 11:52:59.800983 Set Vref, RX VrefLevel [Byte0]: 71
8773 11:52:59.804407 [Byte1]: 71
8774 11:52:59.808745
8775 11:52:59.808829 Set Vref, RX VrefLevel [Byte0]: 72
8776 11:52:59.811801 [Byte1]: 72
8777 11:52:59.816252
8778 11:52:59.816335 Set Vref, RX VrefLevel [Byte0]: 73
8779 11:52:59.819490 [Byte1]: 73
8780 11:52:59.823651
8781 11:52:59.823734 Set Vref, RX VrefLevel [Byte0]: 74
8782 11:52:59.827053 [Byte1]: 74
8783 11:52:59.831497
8784 11:52:59.831580 Set Vref, RX VrefLevel [Byte0]: 75
8785 11:52:59.834619 [Byte1]: 75
8786 11:52:59.838851
8787 11:52:59.838934 Set Vref, RX VrefLevel [Byte0]: 76
8788 11:52:59.842186 [Byte1]: 76
8789 11:52:59.846440
8790 11:52:59.846524 Final RX Vref Byte 0 = 53 to rank0
8791 11:52:59.849655 Final RX Vref Byte 1 = 62 to rank0
8792 11:52:59.853238 Final RX Vref Byte 0 = 53 to rank1
8793 11:52:59.856683 Final RX Vref Byte 1 = 62 to rank1==
8794 11:52:59.859706 Dram Type= 6, Freq= 0, CH_1, rank 0
8795 11:52:59.866261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 11:52:59.866346 ==
8797 11:52:59.866450 DQS Delay:
8798 11:52:59.866512 DQS0 = 0, DQS1 = 0
8799 11:52:59.869882 DQM Delay:
8800 11:52:59.869990 DQM0 = 134, DQM1 = 129
8801 11:52:59.873146 DQ Delay:
8802 11:52:59.876134 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8803 11:52:59.880163 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
8804 11:52:59.882970 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8805 11:52:59.886198 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8806 11:52:59.886282
8807 11:52:59.886348
8808 11:52:59.886451
8809 11:52:59.889620 [DramC_TX_OE_Calibration] TA2
8810 11:52:59.893509 Original DQ_B0 (3 6) =30, OEN = 27
8811 11:52:59.896373 Original DQ_B1 (3 6) =30, OEN = 27
8812 11:52:59.899475 24, 0x0, End_B0=24 End_B1=24
8813 11:52:59.899565 25, 0x0, End_B0=25 End_B1=25
8814 11:52:59.902813 26, 0x0, End_B0=26 End_B1=26
8815 11:52:59.906123 27, 0x0, End_B0=27 End_B1=27
8816 11:52:59.909492 28, 0x0, End_B0=28 End_B1=28
8817 11:52:59.912918 29, 0x0, End_B0=29 End_B1=29
8818 11:52:59.913004 30, 0x0, End_B0=30 End_B1=30
8819 11:52:59.916024 31, 0x4141, End_B0=30 End_B1=30
8820 11:52:59.919510 Byte0 end_step=30 best_step=27
8821 11:52:59.922681 Byte1 end_step=30 best_step=27
8822 11:52:59.926033 Byte0 TX OE(2T, 0.5T) = (3, 3)
8823 11:52:59.929212 Byte1 TX OE(2T, 0.5T) = (3, 3)
8824 11:52:59.929295
8825 11:52:59.929361
8826 11:52:59.936485 [DQSOSCAuto] RK0, (LSB)MR18= 0x1928, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
8827 11:52:59.939553 CH1 RK0: MR19=303, MR18=1928
8828 11:52:59.946267 CH1_RK0: MR19=0x303, MR18=0x1928, DQSOSC=389, MR23=63, INC=24, DEC=16
8829 11:52:59.946352
8830 11:52:59.949511 ----->DramcWriteLeveling(PI) begin...
8831 11:52:59.949595 ==
8832 11:52:59.952578 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 11:52:59.956333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 11:52:59.956417 ==
8835 11:52:59.959406 Write leveling (Byte 0): 25 => 25
8836 11:52:59.962568 Write leveling (Byte 1): 28 => 28
8837 11:52:59.966143 DramcWriteLeveling(PI) end<-----
8838 11:52:59.966226
8839 11:52:59.966292 ==
8840 11:52:59.969426 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 11:52:59.972681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 11:52:59.972766 ==
8843 11:52:59.976288 [Gating] SW mode calibration
8844 11:52:59.982592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8845 11:52:59.989542 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8846 11:52:59.993220 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:52:59.995985 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:53:00.002712 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8849 11:53:00.006228 1 4 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (0 0)
8850 11:53:00.009099 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 11:53:00.016315 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 11:53:00.019256 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 11:53:00.022886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 11:53:00.029329 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 11:53:00.032670 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 11:53:00.036074 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8857 11:53:00.043133 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8858 11:53:00.046380 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 11:53:00.049324 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 11:53:00.056104 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 11:53:00.059738 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 11:53:00.062890 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 11:53:00.069170 1 6 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8864 11:53:00.072759 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8865 11:53:00.076258 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 11:53:00.079359 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:53:00.085850 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 11:53:00.089401 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 11:53:00.093042 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 11:53:00.099326 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 11:53:00.102761 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 11:53:00.105962 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8873 11:53:00.112367 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8874 11:53:00.115781 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:53:00.119063 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:53:00.125777 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 11:53:00.129081 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 11:53:00.132284 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 11:53:00.139409 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 11:53:00.142139 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 11:53:00.145888 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 11:53:00.152270 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 11:53:00.155486 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 11:53:00.158788 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 11:53:00.165472 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 11:53:00.169021 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 11:53:00.172259 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 11:53:00.178742 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8889 11:53:00.182108 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8890 11:53:00.185460 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 11:53:00.188641 Total UI for P1: 0, mck2ui 16
8892 11:53:00.192028 best dqsien dly found for B0: ( 1, 9, 10)
8893 11:53:00.195243 Total UI for P1: 0, mck2ui 16
8894 11:53:00.198715 best dqsien dly found for B1: ( 1, 9, 10)
8895 11:53:00.202164 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8896 11:53:00.205534 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8897 11:53:00.205618
8898 11:53:00.208924 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8899 11:53:00.215359 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8900 11:53:00.215444 [Gating] SW calibration Done
8901 11:53:00.218646 ==
8902 11:53:00.221963 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 11:53:00.225404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 11:53:00.225488 ==
8905 11:53:00.225555 RX Vref Scan: 0
8906 11:53:00.225616
8907 11:53:00.228546 RX Vref 0 -> 0, step: 1
8908 11:53:00.228630
8909 11:53:00.232026 RX Delay 0 -> 252, step: 8
8910 11:53:00.235264 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8911 11:53:00.238423 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8912 11:53:00.241765 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8913 11:53:00.248272 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8914 11:53:00.252126 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8915 11:53:00.255472 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8916 11:53:00.258429 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8917 11:53:00.261786 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8918 11:53:00.268315 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8919 11:53:00.272052 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8920 11:53:00.275133 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8921 11:53:00.278737 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8922 11:53:00.281999 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8923 11:53:00.288479 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8924 11:53:00.291962 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8925 11:53:00.295298 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8926 11:53:00.295382 ==
8927 11:53:00.298360 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:53:00.301962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:53:00.302084 ==
8930 11:53:00.304821 DQS Delay:
8931 11:53:00.304905 DQS0 = 0, DQS1 = 0
8932 11:53:00.308180 DQM Delay:
8933 11:53:00.308263 DQM0 = 137, DQM1 = 132
8934 11:53:00.308330 DQ Delay:
8935 11:53:00.315035 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8936 11:53:00.317943 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8937 11:53:00.321622 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8938 11:53:00.325276 DQ12 =143, DQ13 =143, DQ14 =135, DQ15 =143
8939 11:53:00.325360
8940 11:53:00.325463
8941 11:53:00.325526 ==
8942 11:53:00.328419 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:53:00.331416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:53:00.331500 ==
8945 11:53:00.331567
8946 11:53:00.331629
8947 11:53:00.334969 TX Vref Scan disable
8948 11:53:00.338312 == TX Byte 0 ==
8949 11:53:00.341912 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8950 11:53:00.345371 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8951 11:53:00.348260 == TX Byte 1 ==
8952 11:53:00.351691 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8953 11:53:00.355019 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8954 11:53:00.355103 ==
8955 11:53:00.358204 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 11:53:00.361413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 11:53:00.365028 ==
8958 11:53:00.376043
8959 11:53:00.379242 TX Vref early break, caculate TX vref
8960 11:53:00.382715 TX Vref=16, minBit 9, minWin=21, winSum=384
8961 11:53:00.386173 TX Vref=18, minBit 9, minWin=22, winSum=392
8962 11:53:00.389261 TX Vref=20, minBit 10, minWin=23, winSum=398
8963 11:53:00.392730 TX Vref=22, minBit 9, minWin=23, winSum=407
8964 11:53:00.395856 TX Vref=24, minBit 9, minWin=24, winSum=416
8965 11:53:00.402391 TX Vref=26, minBit 9, minWin=25, winSum=422
8966 11:53:00.405826 TX Vref=28, minBit 8, minWin=25, winSum=422
8967 11:53:00.409208 TX Vref=30, minBit 8, minWin=25, winSum=414
8968 11:53:00.412349 TX Vref=32, minBit 10, minWin=24, winSum=406
8969 11:53:00.415847 TX Vref=34, minBit 8, minWin=23, winSum=399
8970 11:53:00.422674 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 26
8971 11:53:00.422758
8972 11:53:00.426026 Final TX Range 0 Vref 26
8973 11:53:00.426111
8974 11:53:00.426177 ==
8975 11:53:00.429246 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 11:53:00.432394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 11:53:00.432482 ==
8978 11:53:00.432549
8979 11:53:00.432610
8980 11:53:00.435662 TX Vref Scan disable
8981 11:53:00.442728 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8982 11:53:00.442813 == TX Byte 0 ==
8983 11:53:00.445529 u2DelayCellOfst[0]=17 cells (5 PI)
8984 11:53:00.449355 u2DelayCellOfst[1]=13 cells (4 PI)
8985 11:53:00.452256 u2DelayCellOfst[2]=0 cells (0 PI)
8986 11:53:00.455818 u2DelayCellOfst[3]=6 cells (2 PI)
8987 11:53:00.459448 u2DelayCellOfst[4]=10 cells (3 PI)
8988 11:53:00.462333 u2DelayCellOfst[5]=20 cells (6 PI)
8989 11:53:00.466121 u2DelayCellOfst[6]=20 cells (6 PI)
8990 11:53:00.466205 u2DelayCellOfst[7]=6 cells (2 PI)
8991 11:53:00.472578 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8992 11:53:00.475721 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8993 11:53:00.475805 == TX Byte 1 ==
8994 11:53:00.479058 u2DelayCellOfst[8]=0 cells (0 PI)
8995 11:53:00.482827 u2DelayCellOfst[9]=3 cells (1 PI)
8996 11:53:00.485777 u2DelayCellOfst[10]=6 cells (2 PI)
8997 11:53:00.489060 u2DelayCellOfst[11]=0 cells (0 PI)
8998 11:53:00.492464 u2DelayCellOfst[12]=10 cells (3 PI)
8999 11:53:00.496013 u2DelayCellOfst[13]=13 cells (4 PI)
9000 11:53:00.499201 u2DelayCellOfst[14]=17 cells (5 PI)
9001 11:53:00.502630 u2DelayCellOfst[15]=17 cells (5 PI)
9002 11:53:00.505564 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9003 11:53:00.512486 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9004 11:53:00.512571 DramC Write-DBI on
9005 11:53:00.512639 ==
9006 11:53:00.515730 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 11:53:00.518752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 11:53:00.518836 ==
9009 11:53:00.522044
9010 11:53:00.522127
9011 11:53:00.522194 TX Vref Scan disable
9012 11:53:00.525655 == TX Byte 0 ==
9013 11:53:00.528839 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9014 11:53:00.532272 == TX Byte 1 ==
9015 11:53:00.535382 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9016 11:53:00.535466 DramC Write-DBI off
9017 11:53:00.538740
9018 11:53:00.538824 [DATLAT]
9019 11:53:00.538890 Freq=1600, CH1 RK1
9020 11:53:00.538953
9021 11:53:00.541967 DATLAT Default: 0xf
9022 11:53:00.542051 0, 0xFFFF, sum = 0
9023 11:53:00.545227 1, 0xFFFF, sum = 0
9024 11:53:00.545312 2, 0xFFFF, sum = 0
9025 11:53:00.548600 3, 0xFFFF, sum = 0
9026 11:53:00.552142 4, 0xFFFF, sum = 0
9027 11:53:00.552227 5, 0xFFFF, sum = 0
9028 11:53:00.555686 6, 0xFFFF, sum = 0
9029 11:53:00.555772 7, 0xFFFF, sum = 0
9030 11:53:00.558917 8, 0xFFFF, sum = 0
9031 11:53:00.559003 9, 0xFFFF, sum = 0
9032 11:53:00.562206 10, 0xFFFF, sum = 0
9033 11:53:00.562308 11, 0xFFFF, sum = 0
9034 11:53:00.565521 12, 0xFFFF, sum = 0
9035 11:53:00.565613 13, 0xFFFF, sum = 0
9036 11:53:00.568899 14, 0x0, sum = 1
9037 11:53:00.568984 15, 0x0, sum = 2
9038 11:53:00.571929 16, 0x0, sum = 3
9039 11:53:00.572015 17, 0x0, sum = 4
9040 11:53:00.575615 best_step = 15
9041 11:53:00.575699
9042 11:53:00.575766 ==
9043 11:53:00.578813 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 11:53:00.582318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 11:53:00.582438 ==
9046 11:53:00.582506 RX Vref Scan: 0
9047 11:53:00.582569
9048 11:53:00.585410 RX Vref 0 -> 0, step: 1
9049 11:53:00.585494
9050 11:53:00.588581 RX Delay 19 -> 252, step: 4
9051 11:53:00.591817 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9052 11:53:00.595414 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9053 11:53:00.601701 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9054 11:53:00.605276 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9055 11:53:00.608504 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9056 11:53:00.612249 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9057 11:53:00.615237 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9058 11:53:00.621992 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9059 11:53:00.625054 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9060 11:53:00.628657 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9061 11:53:00.632269 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9062 11:53:00.635202 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9063 11:53:00.642106 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9064 11:53:00.645686 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9065 11:53:00.648623 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9066 11:53:00.651963 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9067 11:53:00.652065 ==
9068 11:53:00.655250 Dram Type= 6, Freq= 0, CH_1, rank 1
9069 11:53:00.658955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9070 11:53:00.662225 ==
9071 11:53:00.662335 DQS Delay:
9072 11:53:00.662466 DQS0 = 0, DQS1 = 0
9073 11:53:00.665638 DQM Delay:
9074 11:53:00.665734 DQM0 = 134, DQM1 = 130
9075 11:53:00.668681 DQ Delay:
9076 11:53:00.672168 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
9077 11:53:00.675284 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9078 11:53:00.678599 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9079 11:53:00.681777 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9080 11:53:00.681881
9081 11:53:00.681973
9082 11:53:00.682060
9083 11:53:00.685369 [DramC_TX_OE_Calibration] TA2
9084 11:53:00.688588 Original DQ_B0 (3 6) =30, OEN = 27
9085 11:53:00.692089 Original DQ_B1 (3 6) =30, OEN = 27
9086 11:53:00.695157 24, 0x0, End_B0=24 End_B1=24
9087 11:53:00.695238 25, 0x0, End_B0=25 End_B1=25
9088 11:53:00.698714 26, 0x0, End_B0=26 End_B1=26
9089 11:53:00.701681 27, 0x0, End_B0=27 End_B1=27
9090 11:53:00.705536 28, 0x0, End_B0=28 End_B1=28
9091 11:53:00.705614 29, 0x0, End_B0=29 End_B1=29
9092 11:53:00.708246 30, 0x0, End_B0=30 End_B1=30
9093 11:53:00.712032 31, 0x4141, End_B0=30 End_B1=30
9094 11:53:00.715446 Byte0 end_step=30 best_step=27
9095 11:53:00.718954 Byte1 end_step=30 best_step=27
9096 11:53:00.721968 Byte0 TX OE(2T, 0.5T) = (3, 3)
9097 11:53:00.722069 Byte1 TX OE(2T, 0.5T) = (3, 3)
9098 11:53:00.722159
9099 11:53:00.725394
9100 11:53:00.731721 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9101 11:53:00.734981 CH1 RK1: MR19=303, MR18=1D08
9102 11:53:00.741803 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9103 11:53:00.741882 [RxdqsGatingPostProcess] freq 1600
9104 11:53:00.748509 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9105 11:53:00.751497 best DQS0 dly(2T, 0.5T) = (1, 1)
9106 11:53:00.755232 best DQS1 dly(2T, 0.5T) = (1, 1)
9107 11:53:00.758392 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9108 11:53:00.761732 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9109 11:53:00.764932 best DQS0 dly(2T, 0.5T) = (1, 1)
9110 11:53:00.768487 best DQS1 dly(2T, 0.5T) = (1, 1)
9111 11:53:00.771725 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9112 11:53:00.775026 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9113 11:53:00.775110 Pre-setting of DQS Precalculation
9114 11:53:00.781841 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9115 11:53:00.788812 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9116 11:53:00.795427 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 11:53:00.795516
9118 11:53:00.795586
9119 11:53:00.798300 [Calibration Summary] 3200 Mbps
9120 11:53:00.801825 CH 0, Rank 0
9121 11:53:00.801910 SW Impedance : PASS
9122 11:53:00.804972 DUTY Scan : NO K
9123 11:53:00.808296 ZQ Calibration : PASS
9124 11:53:00.808373 Jitter Meter : NO K
9125 11:53:00.811856 CBT Training : PASS
9126 11:53:00.811928 Write leveling : PASS
9127 11:53:00.815112 RX DQS gating : PASS
9128 11:53:00.818346 RX DQ/DQS(RDDQC) : PASS
9129 11:53:00.818458 TX DQ/DQS : PASS
9130 11:53:00.821912 RX DATLAT : PASS
9131 11:53:00.824878 RX DQ/DQS(Engine): PASS
9132 11:53:00.824953 TX OE : PASS
9133 11:53:00.828410 All Pass.
9134 11:53:00.828490
9135 11:53:00.828557 CH 0, Rank 1
9136 11:53:00.831823 SW Impedance : PASS
9137 11:53:00.831904 DUTY Scan : NO K
9138 11:53:00.834883 ZQ Calibration : PASS
9139 11:53:00.838550 Jitter Meter : NO K
9140 11:53:00.838636 CBT Training : PASS
9141 11:53:00.841925 Write leveling : PASS
9142 11:53:00.844900 RX DQS gating : PASS
9143 11:53:00.844980 RX DQ/DQS(RDDQC) : PASS
9144 11:53:00.848152 TX DQ/DQS : PASS
9145 11:53:00.851517 RX DATLAT : PASS
9146 11:53:00.851639 RX DQ/DQS(Engine): PASS
9147 11:53:00.854930 TX OE : PASS
9148 11:53:00.855008 All Pass.
9149 11:53:00.855076
9150 11:53:00.858209 CH 1, Rank 0
9151 11:53:00.858281 SW Impedance : PASS
9152 11:53:00.861337 DUTY Scan : NO K
9153 11:53:00.861410 ZQ Calibration : PASS
9154 11:53:00.864913 Jitter Meter : NO K
9155 11:53:00.868072 CBT Training : PASS
9156 11:53:00.868146 Write leveling : PASS
9157 11:53:00.871685 RX DQS gating : PASS
9158 11:53:00.875149 RX DQ/DQS(RDDQC) : PASS
9159 11:53:00.875226 TX DQ/DQS : PASS
9160 11:53:00.878389 RX DATLAT : PASS
9161 11:53:00.881440 RX DQ/DQS(Engine): PASS
9162 11:53:00.881520 TX OE : PASS
9163 11:53:00.885169 All Pass.
9164 11:53:00.885254
9165 11:53:00.885321 CH 1, Rank 1
9166 11:53:00.888261 SW Impedance : PASS
9167 11:53:00.888335 DUTY Scan : NO K
9168 11:53:00.891388 ZQ Calibration : PASS
9169 11:53:00.894811 Jitter Meter : NO K
9170 11:53:00.894889 CBT Training : PASS
9171 11:53:00.898151 Write leveling : PASS
9172 11:53:00.901386 RX DQS gating : PASS
9173 11:53:00.901466 RX DQ/DQS(RDDQC) : PASS
9174 11:53:00.904546 TX DQ/DQS : PASS
9175 11:53:00.904624 RX DATLAT : PASS
9176 11:53:00.908147 RX DQ/DQS(Engine): PASS
9177 11:53:00.911475 TX OE : PASS
9178 11:53:00.911563 All Pass.
9179 11:53:00.911631
9180 11:53:00.914752 DramC Write-DBI on
9181 11:53:00.914823 PER_BANK_REFRESH: Hybrid Mode
9182 11:53:00.918135 TX_TRACKING: ON
9183 11:53:00.928249 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9184 11:53:00.934738 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9185 11:53:00.941256 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9186 11:53:00.944516 [FAST_K] Save calibration result to emmc
9187 11:53:00.948110 sync common calibartion params.
9188 11:53:00.951101 sync cbt_mode0:1, 1:1
9189 11:53:00.951176 dram_init: ddr_geometry: 2
9190 11:53:00.954778 dram_init: ddr_geometry: 2
9191 11:53:00.958010 dram_init: ddr_geometry: 2
9192 11:53:00.961089 0:dram_rank_size:100000000
9193 11:53:00.961169 1:dram_rank_size:100000000
9194 11:53:00.967939 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9195 11:53:00.971174 DFS_SHUFFLE_HW_MODE: ON
9196 11:53:00.974538 dramc_set_vcore_voltage set vcore to 725000
9197 11:53:00.974617 Read voltage for 1600, 0
9198 11:53:00.977897 Vio18 = 0
9199 11:53:00.977988 Vcore = 725000
9200 11:53:00.978057 Vdram = 0
9201 11:53:00.981216 Vddq = 0
9202 11:53:00.981294 Vmddr = 0
9203 11:53:00.984551 switch to 3200 Mbps bootup
9204 11:53:00.984624 [DramcRunTimeConfig]
9205 11:53:00.987956 PHYPLL
9206 11:53:00.988027 DPM_CONTROL_AFTERK: ON
9207 11:53:00.991295 PER_BANK_REFRESH: ON
9208 11:53:00.994312 REFRESH_OVERHEAD_REDUCTION: ON
9209 11:53:00.994405 CMD_PICG_NEW_MODE: OFF
9210 11:53:00.997815 XRTWTW_NEW_MODE: ON
9211 11:53:00.997884 XRTRTR_NEW_MODE: ON
9212 11:53:01.001185 TX_TRACKING: ON
9213 11:53:01.001261 RDSEL_TRACKING: OFF
9214 11:53:01.004289 DQS Precalculation for DVFS: ON
9215 11:53:01.007565 RX_TRACKING: OFF
9216 11:53:01.007639 HW_GATING DBG: ON
9217 11:53:01.011052 ZQCS_ENABLE_LP4: ON
9218 11:53:01.011123 RX_PICG_NEW_MODE: ON
9219 11:53:01.014319 TX_PICG_NEW_MODE: ON
9220 11:53:01.014419 ENABLE_RX_DCM_DPHY: ON
9221 11:53:01.017863 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9222 11:53:01.021129 DUMMY_READ_FOR_TRACKING: OFF
9223 11:53:01.024471 !!! SPM_CONTROL_AFTERK: OFF
9224 11:53:01.027629 !!! SPM could not control APHY
9225 11:53:01.027709 IMPEDANCE_TRACKING: ON
9226 11:53:01.031156 TEMP_SENSOR: ON
9227 11:53:01.031227 HW_SAVE_FOR_SR: OFF
9228 11:53:01.034258 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9229 11:53:01.037430 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9230 11:53:01.041145 Read ODT Tracking: ON
9231 11:53:01.044460 Refresh Rate DeBounce: ON
9232 11:53:01.044531 DFS_NO_QUEUE_FLUSH: ON
9233 11:53:01.048013 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9234 11:53:01.050693 ENABLE_DFS_RUNTIME_MRW: OFF
9235 11:53:01.054183 DDR_RESERVE_NEW_MODE: ON
9236 11:53:01.054255 MR_CBT_SWITCH_FREQ: ON
9237 11:53:01.057338 =========================
9238 11:53:01.076183 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9239 11:53:01.079342 dram_init: ddr_geometry: 2
9240 11:53:01.097781 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9241 11:53:01.100862 dram_init: dram init end (result: 0)
9242 11:53:01.107748 DRAM-K: Full calibration passed in 24568 msecs
9243 11:53:01.111162 MRC: failed to locate region type 0.
9244 11:53:01.111240 DRAM rank0 size:0x100000000,
9245 11:53:01.114870 DRAM rank1 size=0x100000000
9246 11:53:01.124471 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9247 11:53:01.131241 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9248 11:53:01.137911 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9249 11:53:01.144331 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9250 11:53:01.147750 DRAM rank0 size:0x100000000,
9251 11:53:01.151057 DRAM rank1 size=0x100000000
9252 11:53:01.151146 CBMEM:
9253 11:53:01.154205 IMD: root @ 0xfffff000 254 entries.
9254 11:53:01.157732 IMD: root @ 0xffffec00 62 entries.
9255 11:53:01.160725 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9256 11:53:01.164165 WARNING: RO_VPD is uninitialized or empty.
9257 11:53:01.170455 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9258 11:53:01.177712 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9259 11:53:01.190373 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9260 11:53:01.201868 BS: romstage times (exec / console): total (unknown) / 24055 ms
9261 11:53:01.201947
9262 11:53:01.202012
9263 11:53:01.212118 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9264 11:53:01.215367 ARM64: Exception handlers installed.
9265 11:53:01.218355 ARM64: Testing exception
9266 11:53:01.222003 ARM64: Done test exception
9267 11:53:01.222103 Enumerating buses...
9268 11:53:01.225079 Show all devs... Before device enumeration.
9269 11:53:01.228775 Root Device: enabled 1
9270 11:53:01.232016 CPU_CLUSTER: 0: enabled 1
9271 11:53:01.232092 CPU: 00: enabled 1
9272 11:53:01.235184 Compare with tree...
9273 11:53:01.235263 Root Device: enabled 1
9274 11:53:01.238482 CPU_CLUSTER: 0: enabled 1
9275 11:53:01.242248 CPU: 00: enabled 1
9276 11:53:01.242324 Root Device scanning...
9277 11:53:01.245133 scan_static_bus for Root Device
9278 11:53:01.248925 CPU_CLUSTER: 0 enabled
9279 11:53:01.251824 scan_static_bus for Root Device done
9280 11:53:01.255437 scan_bus: bus Root Device finished in 8 msecs
9281 11:53:01.255513 done
9282 11:53:01.262146 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9283 11:53:01.265720 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9284 11:53:01.271713 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9285 11:53:01.274840 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9286 11:53:01.278157 Allocating resources...
9287 11:53:01.281654 Reading resources...
9288 11:53:01.285052 Root Device read_resources bus 0 link: 0
9289 11:53:01.285132 DRAM rank0 size:0x100000000,
9290 11:53:01.288352 DRAM rank1 size=0x100000000
9291 11:53:01.291627 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9292 11:53:01.294969 CPU: 00 missing read_resources
9293 11:53:01.298328 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9294 11:53:01.305100 Root Device read_resources bus 0 link: 0 done
9295 11:53:01.305175 Done reading resources.
9296 11:53:01.311473 Show resources in subtree (Root Device)...After reading.
9297 11:53:01.315206 Root Device child on link 0 CPU_CLUSTER: 0
9298 11:53:01.318204 CPU_CLUSTER: 0 child on link 0 CPU: 00
9299 11:53:01.328450 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9300 11:53:01.328531 CPU: 00
9301 11:53:01.331201 Root Device assign_resources, bus 0 link: 0
9302 11:53:01.334768 CPU_CLUSTER: 0 missing set_resources
9303 11:53:01.341294 Root Device assign_resources, bus 0 link: 0 done
9304 11:53:01.341375 Done setting resources.
9305 11:53:01.348069 Show resources in subtree (Root Device)...After assigning values.
9306 11:53:01.351308 Root Device child on link 0 CPU_CLUSTER: 0
9307 11:53:01.354609 CPU_CLUSTER: 0 child on link 0 CPU: 00
9308 11:53:01.364219 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9309 11:53:01.364299 CPU: 00
9310 11:53:01.367808 Done allocating resources.
9311 11:53:01.370885 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9312 11:53:01.374341 Enabling resources...
9313 11:53:01.374455 done.
9314 11:53:01.381035 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9315 11:53:01.381121 Initializing devices...
9316 11:53:01.384271 Root Device init
9317 11:53:01.384355 init hardware done!
9318 11:53:01.387717 0x00000018: ctrlr->caps
9319 11:53:01.391058 52.000 MHz: ctrlr->f_max
9320 11:53:01.391151 0.400 MHz: ctrlr->f_min
9321 11:53:01.394648 0x40ff8080: ctrlr->voltages
9322 11:53:01.394732 sclk: 390625
9323 11:53:01.397645 Bus Width = 1
9324 11:53:01.397728 sclk: 390625
9325 11:53:01.400911 Bus Width = 1
9326 11:53:01.400994 Early init status = 3
9327 11:53:01.407578 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9328 11:53:01.410720 in-header: 03 fc 00 00 01 00 00 00
9329 11:53:01.410814 in-data: 00
9330 11:53:01.417141 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9331 11:53:01.420704 in-header: 03 fd 00 00 00 00 00 00
9332 11:53:01.424084 in-data:
9333 11:53:01.427083 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9334 11:53:01.431296 in-header: 03 fc 00 00 01 00 00 00
9335 11:53:01.434118 in-data: 00
9336 11:53:01.437295 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9337 11:53:01.442645 in-header: 03 fd 00 00 00 00 00 00
9338 11:53:01.446067 in-data:
9339 11:53:01.449350 [SSUSB] Setting up USB HOST controller...
9340 11:53:01.452711 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9341 11:53:01.456161 [SSUSB] phy power-on done.
9342 11:53:01.459264 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9343 11:53:01.465695 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9344 11:53:01.469186 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9345 11:53:01.475933 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9346 11:53:01.482477 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9347 11:53:01.488948 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9348 11:53:01.495680 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9349 11:53:01.502413 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9350 11:53:01.505686 SPM: binary array size = 0x9dc
9351 11:53:01.509372 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9352 11:53:01.515928 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9353 11:53:01.522346 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9354 11:53:01.525895 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9355 11:53:01.532156 configure_display: Starting display init
9356 11:53:01.566216 anx7625_power_on_init: Init interface.
9357 11:53:01.569432 anx7625_disable_pd_protocol: Disabled PD feature.
9358 11:53:01.572540 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9359 11:53:01.600187 anx7625_start_dp_work: Secure OCM version=00
9360 11:53:01.603610 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9361 11:53:01.618631 sp_tx_get_edid_block: EDID Block = 1
9362 11:53:01.721401 Extracted contents:
9363 11:53:01.724374 header: 00 ff ff ff ff ff ff 00
9364 11:53:01.727659 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9365 11:53:01.731390 version: 01 04
9366 11:53:01.734124 basic params: 95 1f 11 78 0a
9367 11:53:01.737845 chroma info: 76 90 94 55 54 90 27 21 50 54
9368 11:53:01.740658 established: 00 00 00
9369 11:53:01.747387 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9370 11:53:01.751033 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9371 11:53:01.757511 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 11:53:01.764212 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9373 11:53:01.771191 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9374 11:53:01.773859 extensions: 00
9375 11:53:01.773942 checksum: fb
9376 11:53:01.774008
9377 11:53:01.777380 Manufacturer: IVO Model 57d Serial Number 0
9378 11:53:01.780679 Made week 0 of 2020
9379 11:53:01.780764 EDID version: 1.4
9380 11:53:01.784032 Digital display
9381 11:53:01.787310 6 bits per primary color channel
9382 11:53:01.787396 DisplayPort interface
9383 11:53:01.790617 Maximum image size: 31 cm x 17 cm
9384 11:53:01.794132 Gamma: 220%
9385 11:53:01.794216 Check DPMS levels
9386 11:53:01.797221 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9387 11:53:01.800556 First detailed timing is preferred timing
9388 11:53:01.804174 Established timings supported:
9389 11:53:01.807147 Standard timings supported:
9390 11:53:01.810714 Detailed timings
9391 11:53:01.813861 Hex of detail: 383680a07038204018303c0035ae10000019
9392 11:53:01.817097 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9393 11:53:01.824009 0780 0798 07c8 0820 hborder 0
9394 11:53:01.827057 0438 043b 0447 0458 vborder 0
9395 11:53:01.830621 -hsync -vsync
9396 11:53:01.830704 Did detailed timing
9397 11:53:01.836930 Hex of detail: 000000000000000000000000000000000000
9398 11:53:01.837014 Manufacturer-specified data, tag 0
9399 11:53:01.843678 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9400 11:53:01.846891 ASCII string: InfoVision
9401 11:53:01.850226 Hex of detail: 000000fe00523134304e574635205248200a
9402 11:53:01.853637 ASCII string: R140NWF5 RH
9403 11:53:01.853721 Checksum
9404 11:53:01.853786 Checksum: 0xfb (valid)
9405 11:53:01.860577 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9406 11:53:01.863877 DSI data_rate: 832800000 bps
9407 11:53:01.866940 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9408 11:53:01.874097 anx7625_parse_edid: pixelclock(138800).
9409 11:53:01.877257 hactive(1920), hsync(48), hfp(24), hbp(88)
9410 11:53:01.880296 vactive(1080), vsync(12), vfp(3), vbp(17)
9411 11:53:01.883775 anx7625_dsi_config: config dsi.
9412 11:53:01.890178 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9413 11:53:01.903110 anx7625_dsi_config: success to config DSI
9414 11:53:01.906200 anx7625_dp_start: MIPI phy setup OK.
9415 11:53:01.909811 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9416 11:53:01.912946 mtk_ddp_mode_set invalid vrefresh 60
9417 11:53:01.916065 main_disp_path_setup
9418 11:53:01.916188 ovl_layer_smi_id_en
9419 11:53:01.920055 ovl_layer_smi_id_en
9420 11:53:01.920139 ccorr_config
9421 11:53:01.920205 aal_config
9422 11:53:01.922934 gamma_config
9423 11:53:01.923018 postmask_config
9424 11:53:01.926302 dither_config
9425 11:53:01.929646 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9426 11:53:01.935913 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9427 11:53:01.939588 Root Device init finished in 552 msecs
9428 11:53:01.942403 CPU_CLUSTER: 0 init
9429 11:53:01.949245 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9430 11:53:01.952827 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9431 11:53:01.955949 APU_MBOX 0x190000b0 = 0x10001
9432 11:53:01.959571 APU_MBOX 0x190001b0 = 0x10001
9433 11:53:01.962672 APU_MBOX 0x190005b0 = 0x10001
9434 11:53:01.966045 APU_MBOX 0x190006b0 = 0x10001
9435 11:53:01.969367 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9436 11:53:01.981815 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9437 11:53:01.994597 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9438 11:53:02.001231 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9439 11:53:02.012484 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9440 11:53:02.021903 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9441 11:53:02.025056 CPU_CLUSTER: 0 init finished in 81 msecs
9442 11:53:02.028416 Devices initialized
9443 11:53:02.031507 Show all devs... After init.
9444 11:53:02.031591 Root Device: enabled 1
9445 11:53:02.035190 CPU_CLUSTER: 0: enabled 1
9446 11:53:02.038563 CPU: 00: enabled 1
9447 11:53:02.041950 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9448 11:53:02.044926 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9449 11:53:02.048330 ELOG: NV offset 0x57f000 size 0x1000
9450 11:53:02.054683 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9451 11:53:02.061898 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9452 11:53:02.064837 ELOG: Event(17) added with size 13 at 2023-11-23 11:52:28 UTC
9453 11:53:02.068312 out: cmd=0x121: 03 db 21 01 00 00 00 00
9454 11:53:02.071871 in-header: 03 f5 00 00 2c 00 00 00
9455 11:53:02.085213 in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9456 11:53:02.092170 ELOG: Event(A1) added with size 10 at 2023-11-23 11:52:28 UTC
9457 11:53:02.098839 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9458 11:53:02.105287 ELOG: Event(A0) added with size 9 at 2023-11-23 11:52:28 UTC
9459 11:53:02.109027 elog_add_boot_reason: Logged dev mode boot
9460 11:53:02.112090 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9461 11:53:02.115372 Finalize devices...
9462 11:53:02.115473 Devices finalized
9463 11:53:02.122217 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9464 11:53:02.125270 Writing coreboot table at 0xffe64000
9465 11:53:02.129048 0. 000000000010a000-0000000000113fff: RAMSTAGE
9466 11:53:02.132069 1. 0000000040000000-00000000400fffff: RAM
9467 11:53:02.135391 2. 0000000040100000-000000004032afff: RAMSTAGE
9468 11:53:02.142308 3. 000000004032b000-00000000545fffff: RAM
9469 11:53:02.145206 4. 0000000054600000-000000005465ffff: BL31
9470 11:53:02.148775 5. 0000000054660000-00000000ffe63fff: RAM
9471 11:53:02.152051 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9472 11:53:02.158602 7. 0000000100000000-000000023fffffff: RAM
9473 11:53:02.158686 Passing 5 GPIOs to payload:
9474 11:53:02.165233 NAME | PORT | POLARITY | VALUE
9475 11:53:02.168636 EC in RW | 0x000000aa | low | undefined
9476 11:53:02.175294 EC interrupt | 0x00000005 | low | undefined
9477 11:53:02.178781 TPM interrupt | 0x000000ab | high | undefined
9478 11:53:02.182038 SD card detect | 0x00000011 | high | undefined
9479 11:53:02.188369 speaker enable | 0x00000093 | high | undefined
9480 11:53:02.191808 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9481 11:53:02.195085 in-header: 03 f9 00 00 02 00 00 00
9482 11:53:02.195169 in-data: 02 00
9483 11:53:02.198180 ADC[4]: Raw value=901032 ID=7
9484 11:53:02.201568 ADC[3]: Raw value=213179 ID=1
9485 11:53:02.201652 RAM Code: 0x71
9486 11:53:02.204763 ADC[6]: Raw value=74502 ID=0
9487 11:53:02.208517 ADC[5]: Raw value=212441 ID=1
9488 11:53:02.208601 SKU Code: 0x1
9489 11:53:02.215024 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f933
9490 11:53:02.218177 coreboot table: 964 bytes.
9491 11:53:02.221411 IMD ROOT 0. 0xfffff000 0x00001000
9492 11:53:02.225053 IMD SMALL 1. 0xffffe000 0x00001000
9493 11:53:02.228509 RO MCACHE 2. 0xffffc000 0x00001104
9494 11:53:02.231617 CONSOLE 3. 0xfff7c000 0x00080000
9495 11:53:02.234731 FMAP 4. 0xfff7b000 0x00000452
9496 11:53:02.238161 TIME STAMP 5. 0xfff7a000 0x00000910
9497 11:53:02.241465 VBOOT WORK 6. 0xfff66000 0x00014000
9498 11:53:02.244727 RAMOOPS 7. 0xffe66000 0x00100000
9499 11:53:02.248482 COREBOOT 8. 0xffe64000 0x00002000
9500 11:53:02.248567 IMD small region:
9501 11:53:02.251457 IMD ROOT 0. 0xffffec00 0x00000400
9502 11:53:02.255006 VPD 1. 0xffffeb80 0x0000006c
9503 11:53:02.258682 MMC STATUS 2. 0xffffeb60 0x00000004
9504 11:53:02.265261 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9505 11:53:02.265345 Probing TPM: done!
9506 11:53:02.271650 Connected to device vid:did:rid of 1ae0:0028:00
9507 11:53:02.278768 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9508 11:53:02.281989 Initialized TPM device CR50 revision 0
9509 11:53:02.285751 Checking cr50 for pending updates
9510 11:53:02.291292 Reading cr50 TPM mode
9511 11:53:02.300578 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9512 11:53:02.306702 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9513 11:53:02.346792 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9514 11:53:02.350280 Checking segment from ROM address 0x40100000
9515 11:53:02.353400 Checking segment from ROM address 0x4010001c
9516 11:53:02.360033 Loading segment from ROM address 0x40100000
9517 11:53:02.360117 code (compression=0)
9518 11:53:02.366950 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9519 11:53:02.376787 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9520 11:53:02.376873 it's not compressed!
9521 11:53:02.383649 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9522 11:53:02.386921 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9523 11:53:02.407302 Loading segment from ROM address 0x4010001c
9524 11:53:02.407386 Entry Point 0x80000000
9525 11:53:02.410988 Loaded segments
9526 11:53:02.413818 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9527 11:53:02.420713 Jumping to boot code at 0x80000000(0xffe64000)
9528 11:53:02.427293 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9529 11:53:02.433899 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9530 11:53:02.441666 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9531 11:53:02.445198 Checking segment from ROM address 0x40100000
9532 11:53:02.448337 Checking segment from ROM address 0x4010001c
9533 11:53:02.455349 Loading segment from ROM address 0x40100000
9534 11:53:02.455463 code (compression=1)
9535 11:53:02.461984 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9536 11:53:02.471604 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9537 11:53:02.471712 using LZMA
9538 11:53:02.480062 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9539 11:53:02.486591 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9540 11:53:02.490092 Loading segment from ROM address 0x4010001c
9541 11:53:02.490194 Entry Point 0x54601000
9542 11:53:02.493143 Loaded segments
9543 11:53:02.496576 NOTICE: MT8192 bl31_setup
9544 11:53:02.504085 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9545 11:53:02.507022 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9546 11:53:02.510676 WARNING: region 0:
9547 11:53:02.513933 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 11:53:02.514037 WARNING: region 1:
9549 11:53:02.520204 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9550 11:53:02.523840 WARNING: region 2:
9551 11:53:02.527447 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9552 11:53:02.530456 WARNING: region 3:
9553 11:53:02.533457 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9554 11:53:02.537211 WARNING: region 4:
9555 11:53:02.543613 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9556 11:53:02.543716 WARNING: region 5:
9557 11:53:02.547005 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 11:53:02.550191 WARNING: region 6:
9559 11:53:02.553682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 11:53:02.553793 WARNING: region 7:
9561 11:53:02.560221 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 11:53:02.566980 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9563 11:53:02.570319 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9564 11:53:02.573935 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9565 11:53:02.580312 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9566 11:53:02.583838 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9567 11:53:02.586952 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9568 11:53:02.593634 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9569 11:53:02.596920 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9570 11:53:02.600394 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9571 11:53:02.606771 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9572 11:53:02.610783 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9573 11:53:02.617017 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9574 11:53:02.620193 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9575 11:53:02.623909 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9576 11:53:02.630338 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9577 11:53:02.633681 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9578 11:53:02.636962 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9579 11:53:02.643584 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9580 11:53:02.646867 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9581 11:53:02.653339 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9582 11:53:02.656903 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9583 11:53:02.660124 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9584 11:53:02.667268 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9585 11:53:02.670256 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9586 11:53:02.677027 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9587 11:53:02.680439 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9588 11:53:02.683935 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9589 11:53:02.690623 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9590 11:53:02.693788 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9591 11:53:02.697086 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9592 11:53:02.703619 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9593 11:53:02.707232 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9594 11:53:02.710429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9595 11:53:02.717175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9596 11:53:02.720621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9597 11:53:02.723997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9598 11:53:02.726945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9599 11:53:02.733641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9600 11:53:02.736974 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9601 11:53:02.740396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9602 11:53:02.743740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9603 11:53:02.750631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9604 11:53:02.754159 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9605 11:53:02.757382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9606 11:53:02.760409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9607 11:53:02.767451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9608 11:53:02.770619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9609 11:53:02.773692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9610 11:53:02.780571 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9611 11:53:02.784157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9612 11:53:02.790644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9613 11:53:02.793798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9614 11:53:02.797307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9615 11:53:02.803948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9616 11:53:02.807194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9617 11:53:02.814045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9618 11:53:02.816965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9619 11:53:02.820412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9620 11:53:02.827414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9621 11:53:02.830415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9622 11:53:02.837271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9623 11:53:02.840623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9624 11:53:02.847312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9625 11:53:02.850318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9626 11:53:02.857195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9627 11:53:02.860740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9628 11:53:02.864004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9629 11:53:02.870650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9630 11:53:02.873997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9631 11:53:02.880685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9632 11:53:02.884601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9633 11:53:02.887393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9634 11:53:02.894072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9635 11:53:02.897263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9636 11:53:02.904185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9637 11:53:02.907363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9638 11:53:02.914120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9639 11:53:02.917577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9640 11:53:02.921029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9641 11:53:02.927846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9642 11:53:02.931189 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9643 11:53:02.937914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9644 11:53:02.940913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9645 11:53:02.947846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9646 11:53:02.950828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9647 11:53:02.954277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9648 11:53:02.961101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9649 11:53:02.964677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9650 11:53:02.971049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9651 11:53:02.974418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9652 11:53:02.981225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9653 11:53:02.984241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9654 11:53:02.987708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9655 11:53:02.994312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9656 11:53:02.997962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9657 11:53:03.004587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9658 11:53:03.008208 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9659 11:53:03.011081 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9660 11:53:03.014567 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9661 11:53:03.021164 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9662 11:53:03.024552 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9663 11:53:03.027729 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9664 11:53:03.034691 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9665 11:53:03.037822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9666 11:53:03.044413 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9667 11:53:03.047658 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9668 11:53:03.051565 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9669 11:53:03.058267 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9670 11:53:03.061293 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9671 11:53:03.067982 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9672 11:53:03.071457 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9673 11:53:03.074325 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9674 11:53:03.081372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9675 11:53:03.084755 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9676 11:53:03.091209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9677 11:53:03.094741 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9678 11:53:03.097796 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9679 11:53:03.101113 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9680 11:53:03.108446 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9681 11:53:03.111324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9682 11:53:03.115025 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9683 11:53:03.118103 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9684 11:53:03.124814 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9685 11:53:03.127835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9686 11:53:03.131233 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9687 11:53:03.138054 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9688 11:53:03.141637 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9689 11:53:03.147841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9690 11:53:03.151378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9691 11:53:03.154465 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9692 11:53:03.161187 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9693 11:53:03.164888 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9694 11:53:03.168037 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9695 11:53:03.174750 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9696 11:53:03.178588 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9697 11:53:03.184755 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9698 11:53:03.187815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9699 11:53:03.191361 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9700 11:53:03.198125 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9701 11:53:03.201557 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9702 11:53:03.204743 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9703 11:53:03.211772 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9704 11:53:03.214501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9705 11:53:03.221525 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9706 11:53:03.224728 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9707 11:53:03.228229 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9708 11:53:03.234613 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9709 11:53:03.237983 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9710 11:53:03.244927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9711 11:53:03.248127 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9712 11:53:03.251476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9713 11:53:03.258013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9714 11:53:03.261389 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9715 11:53:03.264766 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9716 11:53:03.271514 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9717 11:53:03.274929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9718 11:53:03.281428 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9719 11:53:03.284950 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9720 11:53:03.288379 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9721 11:53:03.294628 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9722 11:53:03.298341 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9723 11:53:03.304868 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9724 11:53:03.308327 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9725 11:53:03.311348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9726 11:53:03.317894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9727 11:53:03.321368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9728 11:53:03.325206 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9729 11:53:03.331521 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9730 11:53:03.334455 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9731 11:53:03.341506 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9732 11:53:03.344683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9733 11:53:03.347867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9734 11:53:03.354762 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9735 11:53:03.357980 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9736 11:53:03.364351 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9737 11:53:03.367864 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9738 11:53:03.371076 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9739 11:53:03.377504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9740 11:53:03.381162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9741 11:53:03.387704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9742 11:53:03.391390 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9743 11:53:03.394333 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9744 11:53:03.401221 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9745 11:53:03.404407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9746 11:53:03.411489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9747 11:53:03.414349 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9748 11:53:03.417957 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9749 11:53:03.424193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9750 11:53:03.427431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9751 11:53:03.434306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9752 11:53:03.437647 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9753 11:53:03.440623 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9754 11:53:03.447480 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9755 11:53:03.450553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9756 11:53:03.457490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9757 11:53:03.460805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9758 11:53:03.464160 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9759 11:53:03.471309 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9760 11:53:03.474294 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9761 11:53:03.480873 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9762 11:53:03.484421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9763 11:53:03.487579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9764 11:53:03.494078 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9765 11:53:03.497594 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9766 11:53:03.504268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9767 11:53:03.507619 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9768 11:53:03.514258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9769 11:53:03.517195 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9770 11:53:03.520727 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9771 11:53:03.527177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9772 11:53:03.530676 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9773 11:53:03.537074 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9774 11:53:03.540598 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9775 11:53:03.546990 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9776 11:53:03.550191 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9777 11:53:03.553504 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9778 11:53:03.560469 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9779 11:53:03.563745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9780 11:53:03.570293 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9781 11:53:03.573527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9782 11:53:03.579913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9783 11:53:03.583605 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9784 11:53:03.587138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9785 11:53:03.593470 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9786 11:53:03.596726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9787 11:53:03.603110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9788 11:53:03.606542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9789 11:53:03.609717 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9790 11:53:03.616305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9791 11:53:03.619818 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9792 11:53:03.622969 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9793 11:53:03.629874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9794 11:53:03.633103 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9795 11:53:03.636207 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9796 11:53:03.639675 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9797 11:53:03.646353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9798 11:53:03.649803 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9799 11:53:03.656541 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9800 11:53:03.659965 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9801 11:53:03.662596 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9802 11:53:03.669429 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9803 11:53:03.673151 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9804 11:53:03.676320 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9805 11:53:03.682883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9806 11:53:03.685968 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9807 11:53:03.689508 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9808 11:53:03.696265 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9809 11:53:03.699490 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9810 11:53:03.702843 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9811 11:53:03.709623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9812 11:53:03.712909 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9813 11:53:03.719775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9814 11:53:03.722365 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9815 11:53:03.726053 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9816 11:53:03.732345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9817 11:53:03.735815 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9818 11:53:03.742710 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9819 11:53:03.745554 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9820 11:53:03.748852 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9821 11:53:03.755511 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9822 11:53:03.759074 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9823 11:53:03.762463 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9824 11:53:03.768962 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9825 11:53:03.771926 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9826 11:53:03.775619 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9827 11:53:03.782344 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9828 11:53:03.785391 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9829 11:53:03.791891 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9830 11:53:03.795349 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9831 11:53:03.799046 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9832 11:53:03.801965 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9833 11:53:03.808401 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9834 11:53:03.812147 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9835 11:53:03.815275 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9836 11:53:03.818527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9837 11:53:03.825153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9838 11:53:03.828288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9839 11:53:03.831907 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9840 11:53:03.834942 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9841 11:53:03.841753 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9842 11:53:03.844884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9843 11:53:03.848810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9844 11:53:03.855015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9845 11:53:03.858329 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9846 11:53:03.861534 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9847 11:53:03.868037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9848 11:53:03.871360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9849 11:53:03.878009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9850 11:53:03.881616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9851 11:53:03.884490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9852 11:53:03.891329 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9853 11:53:03.894838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9854 11:53:03.901334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9855 11:53:03.904974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9856 11:53:03.911159 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9857 11:53:03.915027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9858 11:53:03.917978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9859 11:53:03.924538 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9860 11:53:03.927826 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9861 11:53:03.934424 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9862 11:53:03.937724 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9863 11:53:03.941058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9864 11:53:03.947794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9865 11:53:03.950812 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9866 11:53:03.957854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9867 11:53:03.960975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9868 11:53:03.964521 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9869 11:53:03.971147 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9870 11:53:03.974275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9871 11:53:03.981166 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9872 11:53:03.984598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9873 11:53:03.988155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9874 11:53:03.994707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9875 11:53:03.998092 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9876 11:53:04.004459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9877 11:53:04.007797 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9878 11:53:04.011013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9879 11:53:04.018061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9880 11:53:04.021420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9881 11:53:04.027642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9882 11:53:04.031199 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9883 11:53:04.034554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9884 11:53:04.041237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9885 11:53:04.044788 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9886 11:53:04.051638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9887 11:53:04.054603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9888 11:53:04.061071 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9889 11:53:04.064248 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9890 11:53:04.067750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9891 11:53:04.074341 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9892 11:53:04.077436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9893 11:53:04.080782 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9894 11:53:04.087735 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9895 11:53:04.091025 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9896 11:53:04.097839 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9897 11:53:04.100937 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9898 11:53:04.107623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9899 11:53:04.110795 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9900 11:53:04.114355 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9901 11:53:04.120660 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9902 11:53:04.124260 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9903 11:53:04.131072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9904 11:53:04.134022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9905 11:53:04.137323 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9906 11:53:04.144142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9907 11:53:04.147448 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9908 11:53:04.153871 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9909 11:53:04.157589 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9910 11:53:04.160729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9911 11:53:04.167208 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9912 11:53:04.171269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9913 11:53:04.177006 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9914 11:53:04.180538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9915 11:53:04.183863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9916 11:53:04.190229 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9917 11:53:04.193448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9918 11:53:04.200549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9919 11:53:04.203465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9920 11:53:04.210015 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9921 11:53:04.213505 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9922 11:53:04.220158 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9923 11:53:04.223264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9924 11:53:04.226480 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9925 11:53:04.233579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9926 11:53:04.237154 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9927 11:53:04.243458 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9928 11:53:04.246841 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9929 11:53:04.253211 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9930 11:53:04.256936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9931 11:53:04.259979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9932 11:53:04.266871 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9933 11:53:04.270195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9934 11:53:04.276461 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9935 11:53:04.279800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9936 11:53:04.286772 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9937 11:53:04.289657 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9938 11:53:04.296404 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9939 11:53:04.299847 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9940 11:53:04.303257 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9941 11:53:04.309698 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9942 11:53:04.313193 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9943 11:53:04.320039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9944 11:53:04.322929 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9945 11:53:04.329642 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9946 11:53:04.333045 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9947 11:53:04.336159 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9948 11:53:04.343001 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9949 11:53:04.346250 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9950 11:53:04.352711 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9951 11:53:04.356623 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9952 11:53:04.363139 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9953 11:53:04.366178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9954 11:53:04.373055 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9955 11:53:04.376086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9956 11:53:04.379986 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9957 11:53:04.385962 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9958 11:53:04.389385 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9959 11:53:04.396236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9960 11:53:04.399251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9961 11:53:04.406021 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9962 11:53:04.409267 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9963 11:53:04.412772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9964 11:53:04.419362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9965 11:53:04.422314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9966 11:53:04.428994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9967 11:53:04.432307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9968 11:53:04.439168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9969 11:53:04.442319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9970 11:53:04.449186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9971 11:53:04.452675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9972 11:53:04.458819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9973 11:53:04.462628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9974 11:53:04.465655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9975 11:53:04.472814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9976 11:53:04.475739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9977 11:53:04.482357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9978 11:53:04.485642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9979 11:53:04.492498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9980 11:53:04.495829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9981 11:53:04.502561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9982 11:53:04.505591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9983 11:53:04.512215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9984 11:53:04.515538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9985 11:53:04.522055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9986 11:53:04.525262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9987 11:53:04.532375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9988 11:53:04.535340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9989 11:53:04.542139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9990 11:53:04.545365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9991 11:53:04.551972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9992 11:53:04.555274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9993 11:53:04.562072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9994 11:53:04.565259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9995 11:53:04.571915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9996 11:53:04.575187 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9997 11:53:04.578841 INFO: [APUAPC] vio 0
9998 11:53:04.581800 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9999 11:53:04.588824 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10000 11:53:04.592001 INFO: [APUAPC] D0_APC_0: 0x400510
10001 11:53:04.592103 INFO: [APUAPC] D0_APC_1: 0x0
10002 11:53:04.595130 INFO: [APUAPC] D0_APC_2: 0x1540
10003 11:53:04.598559 INFO: [APUAPC] D0_APC_3: 0x0
10004 11:53:04.601565 INFO: [APUAPC] D1_APC_0: 0xffffffff
10005 11:53:04.605353 INFO: [APUAPC] D1_APC_1: 0xffffffff
10006 11:53:04.608758 INFO: [APUAPC] D1_APC_2: 0x3fffff
10007 11:53:04.611605 INFO: [APUAPC] D1_APC_3: 0x0
10008 11:53:04.614961 INFO: [APUAPC] D2_APC_0: 0xffffffff
10009 11:53:04.618199 INFO: [APUAPC] D2_APC_1: 0xffffffff
10010 11:53:04.621752 INFO: [APUAPC] D2_APC_2: 0x3fffff
10011 11:53:04.625186 INFO: [APUAPC] D2_APC_3: 0x0
10012 11:53:04.628084 INFO: [APUAPC] D3_APC_0: 0xffffffff
10013 11:53:04.631843 INFO: [APUAPC] D3_APC_1: 0xffffffff
10014 11:53:04.635007 INFO: [APUAPC] D3_APC_2: 0x3fffff
10015 11:53:04.638223 INFO: [APUAPC] D3_APC_3: 0x0
10016 11:53:04.641632 INFO: [APUAPC] D4_APC_0: 0xffffffff
10017 11:53:04.644969 INFO: [APUAPC] D4_APC_1: 0xffffffff
10018 11:53:04.648136 INFO: [APUAPC] D4_APC_2: 0x3fffff
10019 11:53:04.651768 INFO: [APUAPC] D4_APC_3: 0x0
10020 11:53:04.654841 INFO: [APUAPC] D5_APC_0: 0xffffffff
10021 11:53:04.658152 INFO: [APUAPC] D5_APC_1: 0xffffffff
10022 11:53:04.661357 INFO: [APUAPC] D5_APC_2: 0x3fffff
10023 11:53:04.664941 INFO: [APUAPC] D5_APC_3: 0x0
10024 11:53:04.668348 INFO: [APUAPC] D6_APC_0: 0xffffffff
10025 11:53:04.671268 INFO: [APUAPC] D6_APC_1: 0xffffffff
10026 11:53:04.674724 INFO: [APUAPC] D6_APC_2: 0x3fffff
10027 11:53:04.677838 INFO: [APUAPC] D6_APC_3: 0x0
10028 11:53:04.681326 INFO: [APUAPC] D7_APC_0: 0xffffffff
10029 11:53:04.684584 INFO: [APUAPC] D7_APC_1: 0xffffffff
10030 11:53:04.687830 INFO: [APUAPC] D7_APC_2: 0x3fffff
10031 11:53:04.691196 INFO: [APUAPC] D7_APC_3: 0x0
10032 11:53:04.694481 INFO: [APUAPC] D8_APC_0: 0xffffffff
10033 11:53:04.697922 INFO: [APUAPC] D8_APC_1: 0xffffffff
10034 11:53:04.701435 INFO: [APUAPC] D8_APC_2: 0x3fffff
10035 11:53:04.705023 INFO: [APUAPC] D8_APC_3: 0x0
10036 11:53:04.707569 INFO: [APUAPC] D9_APC_0: 0xffffffff
10037 11:53:04.711021 INFO: [APUAPC] D9_APC_1: 0xffffffff
10038 11:53:04.714619 INFO: [APUAPC] D9_APC_2: 0x3fffff
10039 11:53:04.717411 INFO: [APUAPC] D9_APC_3: 0x0
10040 11:53:04.720932 INFO: [APUAPC] D10_APC_0: 0xffffffff
10041 11:53:04.724449 INFO: [APUAPC] D10_APC_1: 0xffffffff
10042 11:53:04.727407 INFO: [APUAPC] D10_APC_2: 0x3fffff
10043 11:53:04.730686 INFO: [APUAPC] D10_APC_3: 0x0
10044 11:53:04.734434 INFO: [APUAPC] D11_APC_0: 0xffffffff
10045 11:53:04.737894 INFO: [APUAPC] D11_APC_1: 0xffffffff
10046 11:53:04.740749 INFO: [APUAPC] D11_APC_2: 0x3fffff
10047 11:53:04.744493 INFO: [APUAPC] D11_APC_3: 0x0
10048 11:53:04.747830 INFO: [APUAPC] D12_APC_0: 0xffffffff
10049 11:53:04.750614 INFO: [APUAPC] D12_APC_1: 0xffffffff
10050 11:53:04.753925 INFO: [APUAPC] D12_APC_2: 0x3fffff
10051 11:53:04.757458 INFO: [APUAPC] D12_APC_3: 0x0
10052 11:53:04.760607 INFO: [APUAPC] D13_APC_0: 0xffffffff
10053 11:53:04.763947 INFO: [APUAPC] D13_APC_1: 0xffffffff
10054 11:53:04.767415 INFO: [APUAPC] D13_APC_2: 0x3fffff
10055 11:53:04.770676 INFO: [APUAPC] D13_APC_3: 0x0
10056 11:53:04.774080 INFO: [APUAPC] D14_APC_0: 0xffffffff
10057 11:53:04.777809 INFO: [APUAPC] D14_APC_1: 0xffffffff
10058 11:53:04.781308 INFO: [APUAPC] D14_APC_2: 0x3fffff
10059 11:53:04.783972 INFO: [APUAPC] D14_APC_3: 0x0
10060 11:53:04.787240 INFO: [APUAPC] D15_APC_0: 0xffffffff
10061 11:53:04.790585 INFO: [APUAPC] D15_APC_1: 0xffffffff
10062 11:53:04.793988 INFO: [APUAPC] D15_APC_2: 0x3fffff
10063 11:53:04.797486 INFO: [APUAPC] D15_APC_3: 0x0
10064 11:53:04.800791 INFO: [APUAPC] APC_CON: 0x4
10065 11:53:04.800874 INFO: [NOCDAPC] D0_APC_0: 0x0
10066 11:53:04.803850 INFO: [NOCDAPC] D0_APC_1: 0x0
10067 11:53:04.807594 INFO: [NOCDAPC] D1_APC_0: 0x0
10068 11:53:04.811043 INFO: [NOCDAPC] D1_APC_1: 0xfff
10069 11:53:04.813742 INFO: [NOCDAPC] D2_APC_0: 0x0
10070 11:53:04.817320 INFO: [NOCDAPC] D2_APC_1: 0xfff
10071 11:53:04.820449 INFO: [NOCDAPC] D3_APC_0: 0x0
10072 11:53:04.824205 INFO: [NOCDAPC] D3_APC_1: 0xfff
10073 11:53:04.827430 INFO: [NOCDAPC] D4_APC_0: 0x0
10074 11:53:04.830313 INFO: [NOCDAPC] D4_APC_1: 0xfff
10075 11:53:04.830451 INFO: [NOCDAPC] D5_APC_0: 0x0
10076 11:53:04.833748 INFO: [NOCDAPC] D5_APC_1: 0xfff
10077 11:53:04.837303 INFO: [NOCDAPC] D6_APC_0: 0x0
10078 11:53:04.840537 INFO: [NOCDAPC] D6_APC_1: 0xfff
10079 11:53:04.843805 INFO: [NOCDAPC] D7_APC_0: 0x0
10080 11:53:04.847176 INFO: [NOCDAPC] D7_APC_1: 0xfff
10081 11:53:04.850555 INFO: [NOCDAPC] D8_APC_0: 0x0
10082 11:53:04.853981 INFO: [NOCDAPC] D8_APC_1: 0xfff
10083 11:53:04.857337 INFO: [NOCDAPC] D9_APC_0: 0x0
10084 11:53:04.860329 INFO: [NOCDAPC] D9_APC_1: 0xfff
10085 11:53:04.863753 INFO: [NOCDAPC] D10_APC_0: 0x0
10086 11:53:04.867235 INFO: [NOCDAPC] D10_APC_1: 0xfff
10087 11:53:04.867318 INFO: [NOCDAPC] D11_APC_0: 0x0
10088 11:53:04.870560 INFO: [NOCDAPC] D11_APC_1: 0xfff
10089 11:53:04.873835 INFO: [NOCDAPC] D12_APC_0: 0x0
10090 11:53:04.877035 INFO: [NOCDAPC] D12_APC_1: 0xfff
10091 11:53:04.880646 INFO: [NOCDAPC] D13_APC_0: 0x0
10092 11:53:04.883719 INFO: [NOCDAPC] D13_APC_1: 0xfff
10093 11:53:04.887284 INFO: [NOCDAPC] D14_APC_0: 0x0
10094 11:53:04.890541 INFO: [NOCDAPC] D14_APC_1: 0xfff
10095 11:53:04.893732 INFO: [NOCDAPC] D15_APC_0: 0x0
10096 11:53:04.896988 INFO: [NOCDAPC] D15_APC_1: 0xfff
10097 11:53:04.901108 INFO: [NOCDAPC] APC_CON: 0x4
10098 11:53:04.903683 INFO: [APUAPC] set_apusys_apc done
10099 11:53:04.907191 INFO: [DEVAPC] devapc_init done
10100 11:53:04.910478 INFO: GICv3 without legacy support detected.
10101 11:53:04.913649 INFO: ARM GICv3 driver initialized in EL3
10102 11:53:04.917105 INFO: Maximum SPI INTID supported: 639
10103 11:53:04.920298 INFO: BL31: Initializing runtime services
10104 11:53:04.926923 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10105 11:53:04.930142 INFO: SPM: enable CPC mode
10106 11:53:04.937063 INFO: mcdi ready for mcusys-off-idle and system suspend
10107 11:53:04.940429 INFO: BL31: Preparing for EL3 exit to normal world
10108 11:53:04.943416 INFO: Entry point address = 0x80000000
10109 11:53:04.946806 INFO: SPSR = 0x8
10110 11:53:04.951533
10111 11:53:04.951630
10112 11:53:04.951724
10113 11:53:04.954617 Starting depthcharge on Spherion...
10114 11:53:04.954717
10115 11:53:04.954813 Wipe memory regions:
10116 11:53:04.954901
10117 11:53:04.955691 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10118 11:53:04.955799 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10119 11:53:04.955884 Setting prompt string to ['asurada:']
10120 11:53:04.955992 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10121 11:53:04.958530 [0x00000040000000, 0x00000054600000)
10122 11:53:05.080232
10123 11:53:05.080403 [0x00000054660000, 0x00000080000000)
10124 11:53:05.340799
10125 11:53:05.340960 [0x000000821a7280, 0x000000ffe64000)
10126 11:53:06.085847
10127 11:53:06.086013 [0x00000100000000, 0x00000240000000)
10128 11:53:07.976276
10129 11:53:07.979408 Initializing XHCI USB controller at 0x11200000.
10130 11:53:09.019241
10131 11:53:09.022147 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10132 11:53:09.022227
10133 11:53:09.022291
10134 11:53:09.022393
10135 11:53:09.022703 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 11:53:09.123030 asurada: tftpboot 192.168.201.1 12066530/tftp-deploy-2foalg4i/kernel/image.itb 12066530/tftp-deploy-2foalg4i/kernel/cmdline
10138 11:53:09.123147 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10139 11:53:09.123230 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10140 11:53:09.127500 tftpboot 192.168.201.1 12066530/tftp-deploy-2foalg4i/kernel/image.itbtp-deploy-2foalg4i/kernel/cmdline
10141 11:53:09.127583
10142 11:53:09.127648 Waiting for link
10143 11:53:09.285706
10144 11:53:09.285854 R8152: Initializing
10145 11:53:09.285953
10146 11:53:09.289137 Version 9 (ocp_data = 6010)
10147 11:53:09.289242
10148 11:53:09.292195 R8152: Done initializing
10149 11:53:09.292272
10150 11:53:09.292341 Adding net device
10151 11:53:11.166612
10152 11:53:11.166759 done.
10153 11:53:11.166834
10154 11:53:11.166896 MAC: 00:e0:4c:72:2d:d6
10155 11:53:11.166956
10156 11:53:11.169734 Sending DHCP discover... done.
10157 11:53:11.169835
10158 11:53:21.624854 Waiting for reply... R8152: Bulk read error 0xffffffbf
10159 11:53:21.625014
10160 11:53:21.628416 Receive failed.
10161 11:53:21.628500
10162 11:53:21.628580 done.
10163 11:53:21.628672
10164 11:53:21.631509 Sending DHCP request... done.
10165 11:53:21.631589
10166 11:53:21.634806 Waiting for reply... done.
10167 11:53:21.634887
10168 11:53:21.634950 My ip is 192.168.201.21
10169 11:53:21.635009
10170 11:53:21.638447 The DHCP server ip is 192.168.201.1
10171 11:53:21.638528
10172 11:53:21.644702 TFTP server IP predefined by user: 192.168.201.1
10173 11:53:21.644810
10174 11:53:21.651972 Bootfile predefined by user: 12066530/tftp-deploy-2foalg4i/kernel/image.itb
10175 11:53:21.652082
10176 11:53:21.652174 Sending tftp read request... done.
10177 11:53:21.654855
10178 11:53:21.654969 Waiting for the transfer...
10179 11:53:21.655069
10180 11:53:21.921058 00000000 ################################################################
10181 11:53:21.921190
10182 11:53:22.198916 00080000 ################################################################
10183 11:53:22.199054
10184 11:53:22.448828 00100000 ################################################################
10185 11:53:22.449000
10186 11:53:22.726321 00180000 ################################################################
10187 11:53:22.726470
10188 11:53:23.011275 00200000 ################################################################
10189 11:53:23.011412
10190 11:53:23.302714 00280000 ################################################################
10191 11:53:23.302841
10192 11:53:23.597544 00300000 ################################################################
10193 11:53:23.597693
10194 11:53:23.890991 00380000 ################################################################
10195 11:53:23.891131
10196 11:53:24.185127 00400000 ################################################################
10197 11:53:24.185281
10198 11:53:24.446569 00480000 ################################################################
10199 11:53:24.446708
10200 11:53:24.695689 00500000 ################################################################
10201 11:53:24.695821
10202 11:53:24.944921 00580000 ################################################################
10203 11:53:24.945056
10204 11:53:25.205284 00600000 ################################################################
10205 11:53:25.205424
10206 11:53:25.494989 00680000 ################################################################
10207 11:53:25.495470
10208 11:53:25.873710 00700000 ################################################################
10209 11:53:25.874235
10210 11:53:26.252519 00780000 ################################################################
10211 11:53:26.253068
10212 11:53:26.578971 00800000 ################################################################
10213 11:53:26.579117
10214 11:53:26.870516 00880000 ################################################################
10215 11:53:26.870659
10216 11:53:27.167650 00900000 ################################################################
10217 11:53:27.167794
10218 11:53:27.464655 00980000 ################################################################
10219 11:53:27.464808
10220 11:53:27.764309 00a00000 ################################################################
10221 11:53:27.764462
10222 11:53:28.138751 00a80000 ################################################################
10223 11:53:28.139265
10224 11:53:28.479582 00b00000 ################################################################
10225 11:53:28.479728
10226 11:53:28.779202 00b80000 ################################################################
10227 11:53:28.779345
10228 11:53:29.078523 00c00000 ################################################################
10229 11:53:29.078662
10230 11:53:29.371695 00c80000 ################################################################
10231 11:53:29.371834
10232 11:53:29.652463 00d00000 ################################################################
10233 11:53:29.652604
10234 11:53:29.947728 00d80000 ################################################################
10235 11:53:29.947866
10236 11:53:30.254576 00e00000 ################################################################
10237 11:53:30.254777
10238 11:53:30.542232 00e80000 ################################################################
10239 11:53:30.542378
10240 11:53:30.838694 00f00000 ################################################################
10241 11:53:30.838832
10242 11:53:31.125764 00f80000 ################################################################
10243 11:53:31.125901
10244 11:53:31.412123 01000000 ################################################################
10245 11:53:31.412302
10246 11:53:31.695095 01080000 ################################################################
10247 11:53:31.695236
10248 11:53:31.989768 01100000 ################################################################
10249 11:53:31.989938
10250 11:53:32.286803 01180000 ################################################################
10251 11:53:32.286944
10252 11:53:32.567415 01200000 ################################################################
10253 11:53:32.567557
10254 11:53:32.851491 01280000 ################################################################
10255 11:53:32.851627
10256 11:53:33.132166 01300000 ################################################################
10257 11:53:33.132311
10258 11:53:33.421310 01380000 ################################################################
10259 11:53:33.421476
10260 11:53:33.706842 01400000 ################################################################
10261 11:53:33.707013
10262 11:53:33.981020 01480000 ################################################################
10263 11:53:33.981179
10264 11:53:34.276533 01500000 ################################################################
10265 11:53:34.276672
10266 11:53:34.563872 01580000 ################################################################
10267 11:53:34.564039
10268 11:53:34.850245 01600000 ################################################################
10269 11:53:34.850386
10270 11:53:35.204729 01680000 ################################################################
10271 11:53:35.205422
10272 11:53:35.495532 01700000 ################################################################
10273 11:53:35.495677
10274 11:53:35.779107 01780000 ################################################################
10275 11:53:35.779250
10276 11:53:36.076214 01800000 ################################################################
10277 11:53:36.076364
10278 11:53:36.367895 01880000 ################################################################
10279 11:53:36.368039
10280 11:53:36.659828 01900000 ################################################################
10281 11:53:36.659969
10282 11:53:36.954897 01980000 ################################################################
10283 11:53:36.955039
10284 11:53:37.249891 01a00000 ################################################################
10285 11:53:37.250032
10286 11:53:37.547558 01a80000 ################################################################
10287 11:53:37.547704
10288 11:53:37.829355 01b00000 ################################################################
10289 11:53:37.829502
10290 11:53:37.862747 01b80000 ######## done.
10291 11:53:37.862836
10292 11:53:37.866174 The bootfile was 28896078 bytes long.
10293 11:53:37.866663
10294 11:53:37.870018 Sending tftp read request... done.
10295 11:53:37.870493
10296 11:53:37.873112 Waiting for the transfer...
10297 11:53:37.873539
10298 11:53:37.873873 00000000 # done.
10299 11:53:37.874195
10300 11:53:37.882940 Command line loaded dynamically from TFTP file: 12066530/tftp-deploy-2foalg4i/kernel/cmdline
10301 11:53:37.883496
10302 11:53:37.903057 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10303 11:53:37.903633
10304 11:53:37.906259 Loading FIT.
10305 11:53:37.906768
10306 11:53:37.909694 Image ramdisk-1 has 17799583 bytes.
10307 11:53:37.910264
10308 11:53:37.910748 Image fdt-1 has 47278 bytes.
10309 11:53:37.913035
10310 11:53:37.913505 Image kernel-1 has 11047184 bytes.
10311 11:53:37.913880
10312 11:53:37.923074 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10313 11:53:37.923551
10314 11:53:37.939754 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10315 11:53:37.940364
10316 11:53:37.946935 Choosing best match conf-1 for compat google,spherion-rev2.
10317 11:53:37.950456
10318 11:53:37.955331 Connected to device vid:did:rid of 1ae0:0028:00
10319 11:53:37.963478
10320 11:53:37.966275 tpm_get_response: command 0x17b, return code 0x0
10321 11:53:37.966784
10322 11:53:37.970139 ec_init: CrosEC protocol v3 supported (256, 248)
10323 11:53:37.974946
10324 11:53:37.978633 tpm_cleanup: add release locality here.
10325 11:53:37.979206
10326 11:53:37.979581 Shutting down all USB controllers.
10327 11:53:37.979935
10328 11:53:37.981866 Removing current net device
10329 11:53:37.982260
10330 11:53:37.988272 Exiting depthcharge with code 4 at timestamp: 62397445
10331 11:53:37.988842
10332 11:53:37.991904 LZMA decompressing kernel-1 to 0x821a6718
10333 11:53:37.992486
10334 11:53:37.994879 LZMA decompressing kernel-1 to 0x40000000
10335 11:53:39.383282
10336 11:53:39.383850 jumping to kernel
10337 11:53:39.386022 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10338 11:53:39.386618 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10339 11:53:39.387041 Setting prompt string to ['Linux version [0-9]']
10340 11:53:39.387423 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10341 11:53:39.387801 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10342 11:53:39.466211
10343 11:53:39.469408 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10344 11:53:39.473066 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10345 11:53:39.473578 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10346 11:53:39.473976 Setting prompt string to []
10347 11:53:39.474421 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 11:53:39.474840 Using line separator: #'\n'#
10349 11:53:39.475179 No login prompt set.
10350 11:53:39.475518 Parsing kernel messages
10351 11:53:39.475826 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 11:53:39.476369 [login-action] Waiting for messages, (timeout 00:03:51)
10353 11:53:39.493095 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10354 11:53:39.496261 [ 0.000000] random: crng init done
10355 11:53:39.502686 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10356 11:53:39.506065 [ 0.000000] efi: UEFI not found.
10357 11:53:39.512812 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10358 11:53:39.519673 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10359 11:53:39.529483 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 11:53:39.539276 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 11:53:39.546369 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10362 11:53:39.549458 [ 0.000000] printk: bootconsole [mtk8250] enabled
10363 11:53:39.558461 [ 0.000000] NUMA: No NUMA configuration found
10364 11:53:39.564627 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10365 11:53:39.571506 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10366 11:53:39.572086 [ 0.000000] Zone ranges:
10367 11:53:39.578162 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10368 11:53:39.581577 [ 0.000000] DMA32 empty
10369 11:53:39.588393 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10370 11:53:39.591230 [ 0.000000] Movable zone start for each node
10371 11:53:39.594650 [ 0.000000] Early memory node ranges
10372 11:53:39.601767 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10373 11:53:39.608282 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10374 11:53:39.614633 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10375 11:53:39.621207 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10376 11:53:39.627827 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10377 11:53:39.634252 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10378 11:53:39.689724 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10379 11:53:39.696574 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10380 11:53:39.703069 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10381 11:53:39.706239 [ 0.000000] psci: probing for conduit method from DT.
10382 11:53:39.713406 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10383 11:53:39.716198 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10384 11:53:39.722959 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10385 11:53:39.726476 [ 0.000000] psci: SMC Calling Convention v1.2
10386 11:53:39.733330 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10387 11:53:39.736482 [ 0.000000] Detected VIPT I-cache on CPU0
10388 11:53:39.743031 [ 0.000000] CPU features: detected: GIC system register CPU interface
10389 11:53:39.749963 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10390 11:53:39.756270 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10391 11:53:39.762850 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10392 11:53:39.769493 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10393 11:53:39.776058 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10394 11:53:39.782752 [ 0.000000] alternatives: applying boot alternatives
10395 11:53:39.786035 [ 0.000000] Fallback order for Node 0: 0
10396 11:53:39.796213 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10397 11:53:39.796785 [ 0.000000] Policy zone: Normal
10398 11:53:39.819126 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10399 11:53:39.832863 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10400 11:53:39.842821 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10401 11:53:39.852510 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10402 11:53:39.859064 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10403 11:53:39.862547 <6>[ 0.000000] software IO TLB: area num 8.
10404 11:53:39.919091 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10405 11:53:40.067929 <6>[ 0.000000] Memory: 7952236K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400532K reserved, 32768K cma-reserved)
10406 11:53:40.074554 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10407 11:53:40.081487 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10408 11:53:40.084708 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10409 11:53:40.091335 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10410 11:53:40.098365 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10411 11:53:40.101153 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10412 11:53:40.111473 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10413 11:53:40.117914 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10414 11:53:40.121356 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10415 11:53:40.129059 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10416 11:53:40.132627 <6>[ 0.000000] GICv3: 608 SPIs implemented
10417 11:53:40.139151 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10418 11:53:40.142513 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10419 11:53:40.145910 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10420 11:53:40.156070 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10421 11:53:40.165575 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10422 11:53:40.178917 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10423 11:53:40.185967 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10424 11:53:40.194993 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10425 11:53:40.208417 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10426 11:53:40.214439 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10427 11:53:40.220860 <6>[ 0.009228] Console: colour dummy device 80x25
10428 11:53:40.231261 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10429 11:53:40.234317 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10430 11:53:40.241545 <6>[ 0.029270] LSM: Security Framework initializing
10431 11:53:40.247654 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 11:53:40.257754 <6>[ 0.042070] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 11:53:40.264234 <6>[ 0.051467] cblist_init_generic: Setting adjustable number of callback queues.
10434 11:53:40.270721 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 11:53:40.281101 <6>[ 0.065250] cblist_init_generic: Setting adjustable number of callback queues.
10436 11:53:40.284377 <6>[ 0.072677] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 11:53:40.291281 <6>[ 0.079076] rcu: Hierarchical SRCU implementation.
10438 11:53:40.297605 <6>[ 0.084121] rcu: Max phase no-delay instances is 1000.
10439 11:53:40.303984 <6>[ 0.091175] EFI services will not be available.
10440 11:53:40.307436 <6>[ 0.096127] smp: Bringing up secondary CPUs ...
10441 11:53:40.315403 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10442 11:53:40.321844 <6>[ 0.101243] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10443 11:53:40.328360 <6>[ 0.101273] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10444 11:53:40.331946 <6>[ 0.101610] Detected VIPT I-cache on CPU2
10445 11:53:40.338045 <6>[ 0.101662] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10446 11:53:40.347906 <6>[ 0.101678] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10447 11:53:40.351167 <6>[ 0.101935] Detected VIPT I-cache on CPU3
10448 11:53:40.357889 <6>[ 0.101981] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10449 11:53:40.364314 <6>[ 0.101994] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10450 11:53:40.367928 <6>[ 0.102298] CPU features: detected: Spectre-v4
10451 11:53:40.374749 <6>[ 0.102305] CPU features: detected: Spectre-BHB
10452 11:53:40.377582 <6>[ 0.102310] Detected PIPT I-cache on CPU4
10453 11:53:40.384522 <6>[ 0.102368] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10454 11:53:40.391051 <6>[ 0.102384] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10455 11:53:40.397892 <6>[ 0.102676] Detected PIPT I-cache on CPU5
10456 11:53:40.404759 <6>[ 0.102740] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10457 11:53:40.411036 <6>[ 0.102756] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10458 11:53:40.414220 <6>[ 0.103038] Detected PIPT I-cache on CPU6
10459 11:53:40.421406 <6>[ 0.103104] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10460 11:53:40.427906 <6>[ 0.103120] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10461 11:53:40.434414 <6>[ 0.103415] Detected PIPT I-cache on CPU7
10462 11:53:40.441234 <6>[ 0.103482] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10463 11:53:40.447576 <6>[ 0.103498] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10464 11:53:40.451155 <6>[ 0.103546] smp: Brought up 1 node, 8 CPUs
10465 11:53:40.457815 <6>[ 0.244854] SMP: Total of 8 processors activated.
10466 11:53:40.461238 <6>[ 0.249774] CPU features: detected: 32-bit EL0 Support
10467 11:53:40.470949 <6>[ 0.255137] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10468 11:53:40.477888 <6>[ 0.263992] CPU features: detected: Common not Private translations
10469 11:53:40.481186 <6>[ 0.270468] CPU features: detected: CRC32 instructions
10470 11:53:40.487965 <6>[ 0.275819] CPU features: detected: RCpc load-acquire (LDAPR)
10471 11:53:40.494216 <6>[ 0.281779] CPU features: detected: LSE atomic instructions
10472 11:53:40.501029 <6>[ 0.287596] CPU features: detected: Privileged Access Never
10473 11:53:40.504307 <6>[ 0.293375] CPU features: detected: RAS Extension Support
10474 11:53:40.511325 <6>[ 0.298984] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10475 11:53:40.517809 <6>[ 0.306248] CPU: All CPU(s) started at EL2
10476 11:53:40.524235 <6>[ 0.310591] alternatives: applying system-wide alternatives
10477 11:53:40.532417 <6>[ 0.321297] devtmpfs: initialized
10478 11:53:40.548458 <6>[ 0.330249] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10479 11:53:40.554809 <6>[ 0.340210] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10480 11:53:40.561336 <6>[ 0.348420] pinctrl core: initialized pinctrl subsystem
10481 11:53:40.564769 <6>[ 0.355216] DMI not present or invalid.
10482 11:53:40.571409 <6>[ 0.359629] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10483 11:53:40.581416 <6>[ 0.366517] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10484 11:53:40.587951 <6>[ 0.374103] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10485 11:53:40.598021 <6>[ 0.382309] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10486 11:53:40.601394 <6>[ 0.390553] audit: initializing netlink subsys (disabled)
10487 11:53:40.611489 <5>[ 0.396245] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10488 11:53:40.618051 <6>[ 0.396983] thermal_sys: Registered thermal governor 'step_wise'
10489 11:53:40.624340 <6>[ 0.404211] thermal_sys: Registered thermal governor 'power_allocator'
10490 11:53:40.628323 <6>[ 0.410467] cpuidle: using governor menu
10491 11:53:40.634256 <6>[ 0.421433] NET: Registered PF_QIPCRTR protocol family
10492 11:53:40.641196 <6>[ 0.426930] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10493 11:53:40.644481 <6>[ 0.434036] ASID allocator initialised with 32768 entries
10494 11:53:40.652013 <6>[ 0.440645] Serial: AMBA PL011 UART driver
10495 11:53:40.661321 <4>[ 0.449821] Trying to register duplicate clock ID: 134
10496 11:53:40.718226 <6>[ 0.509972] KASLR enabled
10497 11:53:40.732165 <6>[ 0.517706] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10498 11:53:40.739294 <6>[ 0.524716] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10499 11:53:40.745906 <6>[ 0.531205] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10500 11:53:40.752340 <6>[ 0.538210] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10501 11:53:40.759043 <6>[ 0.544699] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10502 11:53:40.765528 <6>[ 0.551701] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10503 11:53:40.772285 <6>[ 0.558188] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10504 11:53:40.778878 <6>[ 0.565193] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10505 11:53:40.782540 <6>[ 0.572708] ACPI: Interpreter disabled.
10506 11:53:40.790911 <6>[ 0.579204] iommu: Default domain type: Translated
10507 11:53:40.797942 <6>[ 0.584320] iommu: DMA domain TLB invalidation policy: strict mode
10508 11:53:40.800784 <5>[ 0.590978] SCSI subsystem initialized
10509 11:53:40.808249 <6>[ 0.595143] usbcore: registered new interface driver usbfs
10510 11:53:40.814574 <6>[ 0.600875] usbcore: registered new interface driver hub
10511 11:53:40.817378 <6>[ 0.606430] usbcore: registered new device driver usb
10512 11:53:40.824048 <6>[ 0.612580] pps_core: LinuxPPS API ver. 1 registered
10513 11:53:40.834216 <6>[ 0.617774] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10514 11:53:40.837405 <6>[ 0.627119] PTP clock support registered
10515 11:53:40.840587 <6>[ 0.631366] EDAC MC: Ver: 3.0.0
10516 11:53:40.848311 <6>[ 0.636576] FPGA manager framework
10517 11:53:40.854808 <6>[ 0.640257] Advanced Linux Sound Architecture Driver Initialized.
10518 11:53:40.857925 <6>[ 0.647033] vgaarb: loaded
10519 11:53:40.864817 <6>[ 0.650202] clocksource: Switched to clocksource arch_sys_counter
10520 11:53:40.867870 <5>[ 0.656642] VFS: Disk quotas dquot_6.6.0
10521 11:53:40.874783 <6>[ 0.660826] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10522 11:53:40.877790 <6>[ 0.668017] pnp: PnP ACPI: disabled
10523 11:53:40.885996 <6>[ 0.674670] NET: Registered PF_INET protocol family
10524 11:53:40.896257 <6>[ 0.680254] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10525 11:53:40.907304 <6>[ 0.692551] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10526 11:53:40.917503 <6>[ 0.701368] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10527 11:53:40.924065 <6>[ 0.709338] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10528 11:53:40.930679 <6>[ 0.718037] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10529 11:53:40.942675 <6>[ 0.727788] TCP: Hash tables configured (established 65536 bind 65536)
10530 11:53:40.949451 <6>[ 0.734644] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 11:53:40.956138 <6>[ 0.741843] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 11:53:40.962643 <6>[ 0.749543] NET: Registered PF_UNIX/PF_LOCAL protocol family
10533 11:53:40.969419 <6>[ 0.755716] RPC: Registered named UNIX socket transport module.
10534 11:53:40.972329 <6>[ 0.761870] RPC: Registered udp transport module.
10535 11:53:40.978821 <6>[ 0.766802] RPC: Registered tcp transport module.
10536 11:53:40.985844 <6>[ 0.771735] RPC: Registered tcp NFSv4.1 backchannel transport module.
10537 11:53:40.989205 <6>[ 0.778403] PCI: CLS 0 bytes, default 64
10538 11:53:40.992184 <6>[ 0.782801] Unpacking initramfs...
10539 11:53:41.017955 <6>[ 0.802296] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10540 11:53:41.027600 <6>[ 0.810948] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10541 11:53:41.030664 <6>[ 0.819826] kvm [1]: IPA Size Limit: 40 bits
10542 11:53:41.037386 <6>[ 0.824353] kvm [1]: GICv3: no GICV resource entry
10543 11:53:41.040410 <6>[ 0.829375] kvm [1]: disabling GICv2 emulation
10544 11:53:41.047391 <6>[ 0.834062] kvm [1]: GIC system register CPU interface enabled
10545 11:53:41.050896 <6>[ 0.840228] kvm [1]: vgic interrupt IRQ18
10546 11:53:41.057466 <6>[ 0.844582] kvm [1]: VHE mode initialized successfully
10547 11:53:41.063350 <5>[ 0.850998] Initialise system trusted keyrings
10548 11:53:41.070163 <6>[ 0.855821] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10549 11:53:41.077369 <6>[ 0.865831] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10550 11:53:41.084413 <5>[ 0.872308] NFS: Registering the id_resolver key type
10551 11:53:41.087487 <5>[ 0.877618] Key type id_resolver registered
10552 11:53:41.094436 <5>[ 0.882035] Key type id_legacy registered
10553 11:53:41.100574 <6>[ 0.886312] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10554 11:53:41.107033 <6>[ 0.893231] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10555 11:53:41.114129 <6>[ 0.900964] 9p: Installing v9fs 9p2000 file system support
10556 11:53:41.151289 <5>[ 0.939546] Key type asymmetric registered
10557 11:53:41.154656 <5>[ 0.943893] Asymmetric key parser 'x509' registered
10558 11:53:41.164900 <6>[ 0.949059] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10559 11:53:41.168006 <6>[ 0.956680] io scheduler mq-deadline registered
10560 11:53:41.171041 <6>[ 0.961444] io scheduler kyber registered
10561 11:53:41.190979 <6>[ 0.979131] EINJ: ACPI disabled.
10562 11:53:41.224426 <4>[ 1.005745] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 11:53:41.234319 <4>[ 1.016393] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 11:53:41.249048 <6>[ 1.037720] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10565 11:53:41.257267 <6>[ 1.045833] printk: console [ttyS0] disabled
10566 11:53:41.285753 <6>[ 1.070478] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10567 11:53:41.292334 <6>[ 1.079953] printk: console [ttyS0] enabled
10568 11:53:41.295833 <6>[ 1.079953] printk: console [ttyS0] enabled
10569 11:53:41.302194 <6>[ 1.088847] printk: bootconsole [mtk8250] disabled
10570 11:53:41.305462 <6>[ 1.088847] printk: bootconsole [mtk8250] disabled
10571 11:53:41.312805 <6>[ 1.100149] SuperH (H)SCI(F) driver initialized
10572 11:53:41.315348 <6>[ 1.105452] msm_serial: driver initialized
10573 11:53:41.329493 <6>[ 1.114587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10574 11:53:41.339906 <6>[ 1.123133] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10575 11:53:41.346640 <6>[ 1.131675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10576 11:53:41.356433 <6>[ 1.140306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10577 11:53:41.363278 <6>[ 1.149028] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10578 11:53:41.373426 <6>[ 1.157750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10579 11:53:41.383208 <6>[ 1.166292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10580 11:53:41.389740 <6>[ 1.175096] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10581 11:53:41.399476 <6>[ 1.183641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10582 11:53:41.411280 <6>[ 1.199445] loop: module loaded
10583 11:53:41.417615 <6>[ 1.205366] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10584 11:53:41.439960 <4>[ 1.228788] mtk-pmic-keys: Failed to locate of_node [id: -1]
10585 11:53:41.446991 <6>[ 1.235704] megasas: 07.719.03.00-rc1
10586 11:53:41.457277 <6>[ 1.245393] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10587 11:53:41.465658 <6>[ 1.253613] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10588 11:53:41.482122 <6>[ 1.270169] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10589 11:53:41.538610 <6>[ 1.320248] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10590 11:53:41.730272 <6>[ 1.518797] Freeing initrd memory: 17380K
10591 11:53:41.741177 <6>[ 1.529309] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10592 11:53:41.752017 <6>[ 1.540200] tun: Universal TUN/TAP device driver, 1.6
10593 11:53:41.755288 <6>[ 1.546299] thunder_xcv, ver 1.0
10594 11:53:41.758456 <6>[ 1.549793] thunder_bgx, ver 1.0
10595 11:53:41.761818 <6>[ 1.553289] nicpf, ver 1.0
10596 11:53:41.772186 <6>[ 1.557332] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10597 11:53:41.775959 <6>[ 1.564808] hns3: Copyright (c) 2017 Huawei Corporation.
10598 11:53:41.782045 <6>[ 1.570395] hclge is initializing
10599 11:53:41.785789 <6>[ 1.573972] e1000: Intel(R) PRO/1000 Network Driver
10600 11:53:41.792804 <6>[ 1.579101] e1000: Copyright (c) 1999-2006 Intel Corporation.
10601 11:53:41.795629 <6>[ 1.585117] e1000e: Intel(R) PRO/1000 Network Driver
10602 11:53:41.802832 <6>[ 1.590333] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10603 11:53:41.809135 <6>[ 1.596518] igb: Intel(R) Gigabit Ethernet Network Driver
10604 11:53:41.815550 <6>[ 1.602168] igb: Copyright (c) 2007-2014 Intel Corporation.
10605 11:53:41.822082 <6>[ 1.608004] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10606 11:53:41.828925 <6>[ 1.614521] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10607 11:53:41.832085 <6>[ 1.620992] sky2: driver version 1.30
10608 11:53:41.839307 <6>[ 1.626029] VFIO - User Level meta-driver version: 0.3
10609 11:53:41.846263 <6>[ 1.634374] usbcore: registered new interface driver usb-storage
10610 11:53:41.852865 <6>[ 1.640816] usbcore: registered new device driver onboard-usb-hub
10611 11:53:41.861885 <6>[ 1.650035] mt6397-rtc mt6359-rtc: registered as rtc0
10612 11:53:41.871933 <6>[ 1.655501] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:53:08 UTC (1700740388)
10613 11:53:41.875159 <6>[ 1.665086] i2c_dev: i2c /dev entries driver
10614 11:53:41.892102 <6>[ 1.676984] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10615 11:53:41.911834 <6>[ 1.699975] cpu cpu0: EM: created perf domain
10616 11:53:41.915195 <6>[ 1.704897] cpu cpu4: EM: created perf domain
10617 11:53:41.922130 <6>[ 1.710486] sdhci: Secure Digital Host Controller Interface driver
10618 11:53:41.928966 <6>[ 1.716914] sdhci: Copyright(c) Pierre Ossman
10619 11:53:41.935415 <6>[ 1.721876] Synopsys Designware Multimedia Card Interface Driver
10620 11:53:41.942486 <6>[ 1.728524] sdhci-pltfm: SDHCI platform and OF driver helper
10621 11:53:41.945714 <6>[ 1.728643] mmc0: CQHCI version 5.10
10622 11:53:41.952490 <6>[ 1.738619] ledtrig-cpu: registered to indicate activity on CPUs
10623 11:53:41.959220 <6>[ 1.745652] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10624 11:53:41.965974 <6>[ 1.752712] usbcore: registered new interface driver usbhid
10625 11:53:41.968607 <6>[ 1.758536] usbhid: USB HID core driver
10626 11:53:41.975501 <6>[ 1.762736] spi_master spi0: will run message pump with realtime priority
10627 11:53:42.019018 <6>[ 1.800500] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10628 11:53:42.034405 <6>[ 1.816668] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10629 11:53:42.041607 <6>[ 1.830321] mmc0: Command Queue Engine enabled
10630 11:53:42.048642 <6>[ 1.835104] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 11:53:42.051768 <6>[ 1.842358] mmcblk0: mmc0:0001 DA4128 116 GiB
10632 11:53:42.058666 <6>[ 1.847316] cros-ec-spi spi0.0: Chrome EC device registered
10633 11:53:42.066056 <6>[ 1.851103] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 11:53:42.073399 <6>[ 1.860914] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 11:53:42.079536 <6>[ 1.867149] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 11:53:42.085883 <6>[ 1.873102] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10637 11:53:42.104544 <6>[ 1.889459] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10638 11:53:42.111951 <6>[ 1.900065] NET: Registered PF_PACKET protocol family
10639 11:53:42.115187 <6>[ 1.905458] 9pnet: Installing 9P2000 support
10640 11:53:42.121710 <5>[ 1.910024] Key type dns_resolver registered
10641 11:53:42.125309 <6>[ 1.915025] registered taskstats version 1
10642 11:53:42.131562 <5>[ 1.919412] Loading compiled-in X.509 certificates
10643 11:53:42.162723 <4>[ 1.944293] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 11:53:42.173219 <4>[ 1.955073] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 11:53:42.179404 <3>[ 1.965615] debugfs: File 'uA_load' in directory '/' already present!
10646 11:53:42.186297 <3>[ 1.972316] debugfs: File 'min_uV' in directory '/' already present!
10647 11:53:42.192783 <3>[ 1.978925] debugfs: File 'max_uV' in directory '/' already present!
10648 11:53:42.199557 <3>[ 1.985531] debugfs: File 'constraint_flags' in directory '/' already present!
10649 11:53:42.210222 <3>[ 1.995372] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10650 11:53:42.223680 <6>[ 2.011817] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10651 11:53:42.230191 <6>[ 2.018608] xhci-mtk 11200000.usb: xHCI Host Controller
10652 11:53:42.236870 <6>[ 2.024099] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10653 11:53:42.247505 <6>[ 2.031936] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10654 11:53:42.253646 <6>[ 2.041341] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10655 11:53:42.260247 <6>[ 2.047403] xhci-mtk 11200000.usb: xHCI Host Controller
10656 11:53:42.266998 <6>[ 2.052886] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10657 11:53:42.273774 <6>[ 2.060541] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10658 11:53:42.280186 <6>[ 2.068167] hub 1-0:1.0: USB hub found
10659 11:53:42.283478 <6>[ 2.072180] hub 1-0:1.0: 1 port detected
10660 11:53:42.290085 <6>[ 2.076457] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10661 11:53:42.296981 <6>[ 2.084976] hub 2-0:1.0: USB hub found
10662 11:53:42.300329 <6>[ 2.088983] hub 2-0:1.0: 1 port detected
10663 11:53:42.307718 <6>[ 2.096124] mtk-msdc 11f70000.mmc: Got CD GPIO
10664 11:53:42.319055 <6>[ 2.104070] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10665 11:53:42.326126 <6>[ 2.112098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10666 11:53:42.335920 <4>[ 2.119997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10667 11:53:42.345730 <6>[ 2.129530] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10668 11:53:42.352519 <6>[ 2.137612] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10669 11:53:42.359283 <6>[ 2.145709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10670 11:53:42.369394 <6>[ 2.153636] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10671 11:53:42.376217 <6>[ 2.161456] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10672 11:53:42.385850 <6>[ 2.169274] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10673 11:53:42.395858 <6>[ 2.179758] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10674 11:53:42.402820 <6>[ 2.188119] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10675 11:53:42.413158 <6>[ 2.196458] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10676 11:53:42.419886 <6>[ 2.204797] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10677 11:53:42.429373 <6>[ 2.213136] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10678 11:53:42.436096 <6>[ 2.221478] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10679 11:53:42.446235 <6>[ 2.229830] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10680 11:53:42.453037 <6>[ 2.238171] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10681 11:53:42.463040 <6>[ 2.246509] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10682 11:53:42.469802 <6>[ 2.254853] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10683 11:53:42.479560 <6>[ 2.263192] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10684 11:53:42.485956 <6>[ 2.271531] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10685 11:53:42.496369 <6>[ 2.279870] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10686 11:53:42.502731 <6>[ 2.288207] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10687 11:53:42.512991 <6>[ 2.296546] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10688 11:53:42.519268 <6>[ 2.305284] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10689 11:53:42.526074 <6>[ 2.312453] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10690 11:53:42.533249 <6>[ 2.319202] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10691 11:53:42.539170 <6>[ 2.325965] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10692 11:53:42.545773 <6>[ 2.332911] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10693 11:53:42.555930 <6>[ 2.339768] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10694 11:53:42.565898 <6>[ 2.348893] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10695 11:53:42.572363 <6>[ 2.358013] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10696 11:53:42.582572 <6>[ 2.367312] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10697 11:53:42.592328 <6>[ 2.376783] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10698 11:53:42.602248 <6>[ 2.386251] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10699 11:53:42.612388 <6>[ 2.395371] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10700 11:53:42.621932 <6>[ 2.404840] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10701 11:53:42.628412 <6>[ 2.413958] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10702 11:53:42.642030 <6>[ 2.423252] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10703 11:53:42.651670 <6>[ 2.433412] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10704 11:53:42.658078 <6>[ 2.444888] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10705 11:53:42.666535 <6>[ 2.454702] Trying to probe devices needed for running init ...
10706 11:53:42.689661 <6>[ 2.474764] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10707 11:53:42.718085 <6>[ 2.506186] hub 2-1:1.0: USB hub found
10708 11:53:42.721348 <6>[ 2.510678] hub 2-1:1.0: 3 ports detected
10709 11:53:42.729810 <6>[ 2.518138] hub 2-1:1.0: USB hub found
10710 11:53:42.732904 <6>[ 2.522503] hub 2-1:1.0: 3 ports detected
10711 11:53:42.841455 <6>[ 2.626478] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10712 11:53:42.996529 <6>[ 2.784515] hub 1-1:1.0: USB hub found
10713 11:53:42.999720 <6>[ 2.789009] hub 1-1:1.0: 4 ports detected
10714 11:53:43.009435 <6>[ 2.797421] hub 1-1:1.0: USB hub found
10715 11:53:43.012373 <6>[ 2.801887] hub 1-1:1.0: 4 ports detected
10716 11:53:43.081725 <6>[ 2.866734] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10717 11:53:43.333310 <6>[ 3.118468] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10718 11:53:43.466934 <6>[ 3.254519] hub 1-1.4:1.0: USB hub found
10719 11:53:43.469438 <6>[ 3.259192] hub 1-1.4:1.0: 2 ports detected
10720 11:53:43.479849 <6>[ 3.267904] hub 1-1.4:1.0: USB hub found
10721 11:53:43.483152 <6>[ 3.272513] hub 1-1.4:1.0: 2 ports detected
10722 11:53:43.781807 <6>[ 3.566489] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10723 11:53:43.973350 <6>[ 3.758523] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10724 11:53:54.942422 <6>[ 14.735534] ALSA device list:
10725 11:53:54.948738 <6>[ 14.738829] No soundcards found.
10726 11:53:54.957062 <6>[ 14.746760] Freeing unused kernel memory: 8384K
10727 11:53:54.960634 <6>[ 14.751739] Run /init as init process
10728 11:53:54.971936 Loading, please wait...
10729 11:53:54.992990 Starting version 247.3-7+deb11u2
10730 11:53:55.205878 <6>[ 14.992347] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10731 11:53:55.221181 <6>[ 15.011087] remoteproc remoteproc0: scp is available
10732 11:53:55.227837 <6>[ 15.016626] remoteproc remoteproc0: powering up scp
10733 11:53:55.234579 <6>[ 15.021937] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10734 11:53:55.241249 <6>[ 15.030408] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10735 11:53:55.248076 <6>[ 15.031690] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10736 11:53:55.257812 <6>[ 15.043724] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10737 11:53:55.264390 <4>[ 15.050688] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10738 11:53:55.274541 <6>[ 15.052588] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10739 11:53:55.277668 <6>[ 15.063629] mc: Linux media interface: v0.10
10740 11:53:55.287698 <3>[ 15.070790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 11:53:55.294468 <4>[ 15.074445] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10742 11:53:55.301017 <3>[ 15.081229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 11:53:55.310994 <6>[ 15.095972] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10744 11:53:55.317070 <3>[ 15.096650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 11:53:55.326787 <3>[ 15.113364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:53:55.333442 <6>[ 15.113920] videodev: Linux video capture interface: v2.00
10747 11:53:55.340545 <3>[ 15.121599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 11:53:55.347120 <3>[ 15.121618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 11:53:55.356973 <3>[ 15.121627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 11:53:55.363941 <3>[ 15.121633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:53:55.373720 <3>[ 15.121891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:53:55.380590 <4>[ 15.124942] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10753 11:53:55.387169 <4>[ 15.124942] Fallback method does not support PEC.
10754 11:53:55.393950 <3>[ 15.141774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 11:53:55.403685 <3>[ 15.143852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 11:53:55.410501 <6>[ 15.163760] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10757 11:53:55.420397 <6>[ 15.163813] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10758 11:53:55.423618 <6>[ 15.163821] remoteproc remoteproc0: remote processor scp is now up
10759 11:53:55.433801 <3>[ 15.168033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 11:53:55.440194 <3>[ 15.168038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 11:53:55.450147 <3>[ 15.168094] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 11:53:55.460315 <6>[ 15.190239] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10763 11:53:55.466797 <3>[ 15.190447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:53:55.473450 <6>[ 15.195605] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10765 11:53:55.480317 <6>[ 15.195610] pci_bus 0000:00: root bus resource [bus 00-ff]
10766 11:53:55.487315 <6>[ 15.195613] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10767 11:53:55.497004 <6>[ 15.195616] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10768 11:53:55.503673 <6>[ 15.195644] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10769 11:53:55.510114 <6>[ 15.195657] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10770 11:53:55.516937 <6>[ 15.195723] pci 0000:00:00.0: supports D1 D2
10771 11:53:55.523797 <6>[ 15.195725] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10772 11:53:55.530437 <6>[ 15.196620] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10773 11:53:55.537003 <6>[ 15.196690] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10774 11:53:55.543516 <6>[ 15.196714] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10775 11:53:55.553429 <6>[ 15.196730] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10776 11:53:55.560062 <6>[ 15.196744] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10777 11:53:55.563469 <6>[ 15.196847] pci 0000:01:00.0: supports D1 D2
10778 11:53:55.569736 <6>[ 15.196848] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10779 11:53:55.577115 <6>[ 15.198937] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10780 11:53:55.587009 <6>[ 15.200206] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10781 11:53:55.597275 <3>[ 15.205557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 11:53:55.603653 <3>[ 15.205561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 11:53:55.613921 <3>[ 15.205564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 11:53:55.620038 <3>[ 15.205579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 11:53:55.627011 <6>[ 15.206315] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10786 11:53:55.633613 <6>[ 15.206335] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10787 11:53:55.643264 <6>[ 15.206338] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10788 11:53:55.650010 <6>[ 15.206349] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10789 11:53:55.660294 <6>[ 15.206362] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10790 11:53:55.666977 <6>[ 15.206375] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10791 11:53:55.673688 <6>[ 15.206388] pci 0000:00:00.0: PCI bridge to [bus 01]
10792 11:53:55.679782 <6>[ 15.206393] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10793 11:53:55.686923 <6>[ 15.206487] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10794 11:53:55.693292 <6>[ 15.206974] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10795 11:53:55.699590 <6>[ 15.207481] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10796 11:53:55.706230 <6>[ 15.215378] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10797 11:53:55.716208 <6>[ 15.217315] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10798 11:53:55.726371 <4>[ 15.236996] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10799 11:53:55.733134 <5>[ 15.239055] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10800 11:53:55.735840 <6>[ 15.245798] Bluetooth: Core ver 2.22
10801 11:53:55.742618 <5>[ 15.250144] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10802 11:53:55.752777 <4>[ 15.250204] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10803 11:53:55.759098 <6>[ 15.250210] cfg80211: failed to load regulatory.db
10804 11:53:55.766239 <4>[ 15.256178] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10805 11:53:55.772164 <6>[ 15.263187] NET: Registered PF_BLUETOOTH protocol family
10806 11:53:55.779359 <6>[ 15.271013] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10807 11:53:55.785684 <6>[ 15.271970] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10808 11:53:55.791890 <6>[ 15.276035] Bluetooth: HCI device and connection manager initialized
10809 11:53:55.802357 <3>[ 15.284208] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 11:53:55.808744 <6>[ 15.284229] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10811 11:53:55.822192 <6>[ 15.284894] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10812 11:53:55.828688 <6>[ 15.285111] usbcore: registered new interface driver uvcvideo
10813 11:53:55.832058 <6>[ 15.293556] Bluetooth: HCI socket layer initialized
10814 11:53:55.835339 <6>[ 15.322449] r8152 2-1.3:1.0 eth0: v1.12.13
10815 11:53:55.841849 <6>[ 15.326206] Bluetooth: L2CAP socket layer initialized
10816 11:53:55.848129 <6>[ 15.326239] Bluetooth: SCO socket layer initialized
10817 11:53:55.851699 <6>[ 15.332814] usbcore: registered new interface driver r8152
10818 11:53:55.858683 <6>[ 15.333536] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10819 11:53:55.865393 <6>[ 15.333627] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10820 11:53:55.871523 <6>[ 15.350387] mt7921e 0000:01:00.0: ASIC revision: 79610010
10821 11:53:55.878424 <6>[ 15.382799] usbcore: registered new interface driver cdc_ether
10822 11:53:55.884676 <6>[ 15.383038] usbcore: registered new interface driver btusb
10823 11:53:55.895131 <4>[ 15.406914] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 11:53:55.902301 <6>[ 15.422000] usbcore: registered new interface driver r8153_ecm
10825 11:53:55.904827 <3>[ 15.429890] Bluetooth: hci0: Failed to load firmware file (-2)
10826 11:53:55.911171 <6>[ 15.444257] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10827 11:53:55.917807 <3>[ 15.445887] Bluetooth: hci0: Failed to set up firmware (-2)
10828 11:53:55.928524 <4>[ 15.485160] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 11:53:55.941568 <4>[ 15.487600] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10830 11:53:55.951425 <4>[ 15.599757] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 11:53:55.954940 Begin: Loading essential drivers ... done.
10832 11:53:55.957868 Begin: Running /scripts/init-premount ... done.
10833 11:53:55.967838 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10834 11:53:55.974221 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10835 11:53:55.977761 Device /sys/class/net/enx00e04c722dd6 found
10836 11:53:55.981004 done.
10837 11:53:56.027897 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10838 11:53:56.069339 <4>[ 15.852467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 11:53:56.183837 <4>[ 15.967515] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 11:53:56.300074 <4>[ 16.083411] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 11:53:56.416179 <4>[ 16.199302] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10842 11:53:56.531965 <4>[ 16.315244] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 11:53:56.647482 <4>[ 16.431208] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 11:53:56.763196 <4>[ 16.547180] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 11:53:56.878842 <4>[ 16.663098] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10846 11:53:56.986489 <3>[ 16.777065] mt7921e 0000:01:00.0: hardware init failed
10847 11:53:57.179045 <6>[ 16.969682] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10848 11:53:57.364844 IP-Config: no response after 2 secs - giving up
10849 11:53:57.407539 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10850 11:53:57.410551 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10851 11:53:57.417126 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10852 11:53:57.426815 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10853 11:53:57.433545 host : mt8192-asurada-spherion-r0-cbg-1
10854 11:53:57.440186 domain : lava-rack
10855 11:53:57.443339 rootserver: 192.168.201.1 rootpath:
10856 11:53:57.443458 filename :
10857 11:53:57.495200 done.
10858 11:53:57.502055 Begin: Running /scripts/nfs-bottom ... done.
10859 11:53:57.523004 Begin: Running /scripts/init-bottom ... done.
10860 11:53:58.702239 <6>[ 18.492992] NET: Registered PF_INET6 protocol family
10861 11:53:58.709641 <6>[ 18.500466] Segment Routing with IPv6
10862 11:53:58.713273 <6>[ 18.504510] In-situ OAM (IOAM) with IPv6
10863 11:53:58.827601 <30>[ 18.598380] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10864 11:53:58.830889 <30>[ 18.622799] systemd[1]: Detected architecture arm64.
10865 11:53:58.852367
10866 11:53:58.856051 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10867 11:53:58.856141
10868 11:53:58.873685 <30>[ 18.664722] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10869 11:53:59.696313 <30>[ 19.483655] systemd[1]: Queued start job for default target Graphical Interface.
10870 11:53:59.729986 <30>[ 19.520902] systemd[1]: Created slice system-getty.slice.
10871 11:53:59.736530 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10872 11:53:59.752938 <30>[ 19.543971] systemd[1]: Created slice system-modprobe.slice.
10873 11:53:59.759692 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10874 11:53:59.777601 <30>[ 19.568555] systemd[1]: Created slice system-serial\x2dgetty.slice.
10875 11:53:59.788028 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10876 11:53:59.800498 <30>[ 19.591594] systemd[1]: Created slice User and Session Slice.
10877 11:53:59.807015 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10878 11:53:59.828300 <30>[ 19.615321] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10879 11:53:59.837800 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10880 11:53:59.855680 <30>[ 19.643254] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10881 11:53:59.862198 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10882 11:53:59.886351 <30>[ 19.670647] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10883 11:53:59.892814 <30>[ 19.682791] systemd[1]: Reached target Local Encrypted Volumes.
10884 11:53:59.899621 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10885 11:53:59.916238 <30>[ 19.707033] systemd[1]: Reached target Paths.
10886 11:53:59.922633 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10887 11:53:59.935523 <30>[ 19.726489] systemd[1]: Reached target Remote File Systems.
10888 11:53:59.942022 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10889 11:53:59.959913 <30>[ 19.750765] systemd[1]: Reached target Slices.
10890 11:53:59.966354 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10891 11:53:59.979835 <30>[ 19.770503] systemd[1]: Reached target Swap.
10892 11:53:59.983083 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10893 11:54:00.003366 <30>[ 19.790995] systemd[1]: Listening on initctl Compatibility Named Pipe.
10894 11:54:00.010088 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10895 11:54:00.016423 <30>[ 19.807029] systemd[1]: Listening on Journal Audit Socket.
10896 11:54:00.023360 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10897 11:54:00.041211 <30>[ 19.831695] systemd[1]: Listening on Journal Socket (/dev/log).
10898 11:54:00.047355 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10899 11:54:00.064668 <30>[ 19.855740] systemd[1]: Listening on Journal Socket.
10900 11:54:00.071239 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10901 11:54:00.088497 <30>[ 19.876120] systemd[1]: Listening on Network Service Netlink Socket.
10902 11:54:00.094987 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10903 11:54:00.110278 <30>[ 19.901088] systemd[1]: Listening on udev Control Socket.
10904 11:54:00.117006 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10905 11:54:00.131832 <30>[ 19.922936] systemd[1]: Listening on udev Kernel Socket.
10906 11:54:00.138562 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10907 11:54:00.199761 <30>[ 19.990695] systemd[1]: Mounting Huge Pages File System...
10908 11:54:00.206475 Mounting [0;1;39mHuge Pages File System[0m...
10909 11:54:00.224361 <30>[ 20.014824] systemd[1]: Mounting POSIX Message Queue File System...
10910 11:54:00.230584 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10911 11:54:00.251791 <30>[ 20.042771] systemd[1]: Mounting Kernel Debug File System...
10912 11:54:00.258978 Mounting [0;1;39mKernel Debug File System[0m...
10913 11:54:00.275559 <30>[ 20.062948] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10914 11:54:00.293831 <30>[ 20.081566] systemd[1]: Starting Create list of static device nodes for the current kernel...
10915 11:54:00.300366 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10916 11:54:00.318303 <30>[ 20.109459] systemd[1]: Starting Load Kernel Module configfs...
10917 11:54:00.324999 Starting [0;1;39mLoad Kernel Module configfs[0m...
10918 11:54:00.344534 <30>[ 20.135495] systemd[1]: Starting Load Kernel Module drm...
10919 11:54:00.351775 Starting [0;1;39mLoad Kernel Module drm[0m...
10920 11:54:00.368408 <30>[ 20.159160] systemd[1]: Starting Load Kernel Module fuse...
10921 11:54:00.374983 Starting [0;1;39mLoad Kernel Module fuse[0m...
10922 11:54:00.398704 <6>[ 20.189755] fuse: init (API version 7.37)
10923 11:54:00.408977 <30>[ 20.190585] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10924 11:54:00.418912 <30>[ 20.209843] systemd[1]: Starting Journal Service...
10925 11:54:00.422285 Starting [0;1;39mJournal Service[0m...
10926 11:54:00.447404 <30>[ 20.238517] systemd[1]: Starting Load Kernel Modules...
10927 11:54:00.454164 Starting [0;1;39mLoad Kernel Modules[0m...
10928 11:54:00.474970 <30>[ 20.262638] systemd[1]: Starting Remount Root and Kernel File Systems...
10929 11:54:00.481489 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10930 11:54:00.500494 <30>[ 20.291221] systemd[1]: Starting Coldplug All udev Devices...
10931 11:54:00.506766 Starting [0;1;39mColdplug All udev Devices[0m...
10932 11:54:00.524538 <30>[ 20.315536] systemd[1]: Mounted Huge Pages File System.
10933 11:54:00.531008 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10934 11:54:00.545516 <3>[ 20.333199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:54:00.552212 <30>[ 20.342959] systemd[1]: Mounted POSIX Message Queue File System.
10936 11:54:00.558798 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10937 11:54:00.576415 <30>[ 20.366815] systemd[1]: Mounted Kernel Debug File System.
10938 11:54:00.586590 <3>[ 20.372532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 11:54:00.589652 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10940 11:54:00.611879 <30>[ 20.399268] systemd[1]: Finished Create list of static device nodes for the current kernel.
10941 11:54:00.622314 [[0;32m OK [0m] Finished [0<3>[ 20.410355] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 11:54:00.628485 ;1;39mCreate list of st… nodes for the current kernel[0m.
10943 11:54:00.644858 <30>[ 20.435404] systemd[1]: modprobe@configfs.service: Succeeded.
10944 11:54:00.654893 <3>[ 20.440126] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 11:54:00.661444 <30>[ 20.442096] systemd[1]: Finished Load Kernel Module configfs.
10946 11:54:00.668321 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10947 11:54:00.682335 <3>[ 20.470074] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:54:00.689742 <30>[ 20.480693] systemd[1]: modprobe@drm.service: Succeeded.
10949 11:54:00.696488 <30>[ 20.487375] systemd[1]: Finished Load Kernel Module drm.
10950 11:54:00.703910 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10951 11:54:00.713625 <3>[ 20.500669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:54:00.720870 <30>[ 20.511872] systemd[1]: modprobe@fuse.service: Succeeded.
10953 11:54:00.727784 <30>[ 20.518782] systemd[1]: Finished Load Kernel Module fuse.
10954 11:54:00.735263 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10955 11:54:00.747133 <3>[ 20.534914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:54:00.755849 <30>[ 20.546539] systemd[1]: Finished Load Kernel Modules.
10957 11:54:00.761991 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10958 11:54:00.780337 <3>[ 20.568060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:54:00.786913 <30>[ 20.568534] systemd[1]: Finished Remount Root and Kernel File Systems.
10960 11:54:00.793536 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10961 11:54:00.813095 <3>[ 20.600613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:54:00.849863 <30>[ 20.640886] systemd[1]: Mounting FUSE Control File System...
10963 11:54:00.863352 Mountin<3>[ 20.648250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 11:54:00.866496 g [0;1;39mFUSE Control File System[0m...
10965 11:54:00.884084 <30>[ 20.674871] systemd[1]: Mounting Kernel Configuration File System...
10966 11:54:00.891398 Mounting [0;1;39mKernel Configuration File System[0m...
10967 11:54:00.915738 <30>[ 20.702864] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10968 11:54:00.925576 <30>[ 20.711941] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10969 11:54:00.964361 <30>[ 20.755297] systemd[1]: Starting Load/Save Random Seed...
10970 11:54:00.971000 Starting [0;1;39mLoad/Save Random Seed[0m...
10971 11:54:00.986696 <30>[ 20.777543] systemd[1]: Starting Apply Kernel Variables...
10972 11:54:01.003316 <4>[ 20.781073] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10973 11:54:01.010095 <3>[ 20.799051] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10974 11:54:01.016850 Starting [0;1;39mApply Kernel Variables[0m...
10975 11:54:01.036761 <30>[ 20.827711] systemd[1]: Starting Create System Users...
10976 11:54:01.043348 Starting [0;1;39mCreate System Users[0m...
10977 11:54:01.059046 <30>[ 20.850139] systemd[1]: Started Journal Service.
10978 11:54:01.065359 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10979 11:54:01.089128 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10980 11:54:01.103215 See 'systemctl status systemd-udev-trigger.service' for details.
10981 11:54:01.120555 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10982 11:54:01.136335 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10983 11:54:01.153405 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10984 11:54:01.169308 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10985 11:54:01.185455 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10986 11:54:01.220752 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10987 11:54:01.237683 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10988 11:54:01.267895 <46>[ 21.055698] systemd-journald[300]: Received client request to flush runtime journal.
10989 11:54:01.295984 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10990 11:54:01.313064 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10991 11:54:01.331878 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10992 11:54:01.376261 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10993 11:54:02.668133 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10994 11:54:02.712298 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10995 11:54:02.732001 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10996 11:54:02.770045 Starting [0;1;39mNetwork Service[0m...
10997 11:54:03.099464 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10998 11:54:03.120712 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10999 11:54:03.187435 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11000 11:54:03.404705 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11001 11:54:03.422759 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11002 11:54:03.460331 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11003 11:54:03.482778 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11004 11:54:03.510669 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11005 11:54:03.531688 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11006 11:54:03.560990 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11007 11:54:03.604306 Starting [0;1;39mNetwork Name Resolution[0m...
11008 11:54:03.625403 Starting [0;1;39mNetwork Time Synchronization[0m...
11009 11:54:03.643483 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11010 11:54:03.693051 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11011 11:54:03.822167 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11012 11:54:03.844824 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11013 11:54:03.866817 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11014 11:54:03.884176 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11015 11:54:03.900129 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11016 11:54:04.020475 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11017 11:54:04.058205 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11018 11:54:04.078539 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11019 11:54:04.097911 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11020 11:54:04.112639 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11021 11:54:04.381051 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11022 11:54:04.394969 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11023 11:54:04.411505 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11024 11:54:04.460126 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11025 11:54:04.887925 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11026 11:54:05.242005 Starting [0;1;39mUser Login Management[0m...
11027 11:54:05.345921 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11028 11:54:05.366254 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11029 11:54:05.383574 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11030 11:54:05.424633 Starting [0;1;39mPermit User Sessions[0m...
11031 11:54:05.507924 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11032 11:54:05.528475 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11033 11:54:05.579555 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11034 11:54:05.603236 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11035 11:54:05.623771 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11036 11:54:05.640459 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11037 11:54:05.657342 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11038 11:54:05.675804 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11039 11:54:05.728428 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11040 11:54:05.773640 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11041 11:54:05.885836
11042 11:54:05.885995
11043 11:54:05.889178 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11044 11:54:05.889275
11045 11:54:05.892605 debian-bullseye-arm64 login: root (automatic login)
11046 11:54:05.892699
11047 11:54:05.892795
11048 11:54:06.208415 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
11049 11:54:06.208571
11050 11:54:06.214796 The programs included with the Debian GNU/Linux system are free software;
11051 11:54:06.221279 the exact distribution terms for each program are described in the
11052 11:54:06.224595 individual files in /usr/share/doc/*/copyright.
11053 11:54:06.224728
11054 11:54:06.231269 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11055 11:54:06.234618 permitted by applicable law.
11056 11:54:07.020196 Matched prompt #10: / #
11058 11:54:07.020545 Setting prompt string to ['/ #']
11059 11:54:07.020661 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11061 11:54:07.020888 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11062 11:54:07.020995 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11063 11:54:07.021077 Setting prompt string to ['/ #']
11064 11:54:07.021173 Forcing a shell prompt, looking for ['/ #']
11066 11:54:07.071495 / #
11067 11:54:07.071687 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11068 11:54:07.071849 Waiting using forced prompt support (timeout 00:02:30)
11069 11:54:07.076745
11070 11:54:07.077041 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11071 11:54:07.077155 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11073 11:54:07.177640 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4'
11074 11:54:07.183340 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066530/extract-nfsrootfs-mktoc5x4'
11076 11:54:07.284000 / # export NFS_SERVER_IP='192.168.201.1'
11077 11:54:07.289499 export NFS_SERVER_IP='192.168.201.1'
11078 11:54:07.289836 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11079 11:54:07.289960 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11080 11:54:07.290066 end: 2 depthcharge-action (duration 00:01:37) [common]
11081 11:54:07.290199 start: 3 lava-test-retry (timeout 00:07:30) [common]
11082 11:54:07.290327 start: 3.1 lava-test-shell (timeout 00:07:30) [common]
11083 11:54:07.290498 Using namespace: common
11085 11:54:07.390923 / # #
11086 11:54:07.391126 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11087 11:54:07.396265 #
11088 11:54:07.396547 Using /lava-12066530
11090 11:54:07.496968 / # export SHELL=/bin/bash
11091 11:54:07.502607 export SHELL=/bin/bash
11093 11:54:07.603237 / # . /lava-12066530/environment
11094 11:54:07.608848 . /lava-12066530/environment
11096 11:54:07.714613 / # /lava-12066530/bin/lava-test-runner /lava-12066530/0
11097 11:54:07.714803 Test shell timeout: 10s (minimum of the action and connection timeout)
11098 11:54:07.719990 /lava-12066530/bin/lava-test-runner /lava-12066530/0
11099 11:54:07.965864 + export TESTRUN_ID=0_timesync-off
11100 11:54:07.968926 + TESTRUN_ID=0_timesync-off
11101 11:54:07.972590 + cd /lava-12066530/0/tests/0_timesync-off
11102 11:54:07.975827 ++ cat uuid
11103 11:54:07.978889 + UUID=12066530_1.6.2.3.1
11104 11:54:07.978976 + set +x
11105 11:54:07.985860 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12066530_1.6.2.3.1>
11106 11:54:07.986163 Received signal: <STARTRUN> 0_timesync-off 12066530_1.6.2.3.1
11107 11:54:07.986279 Starting test lava.0_timesync-off (12066530_1.6.2.3.1)
11108 11:54:07.986438 Skipping test definition patterns.
11109 11:54:07.988701 + systemctl stop systemd-timesyncd
11110 11:54:08.055859 + set +x
11111 11:54:08.059246 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12066530_1.6.2.3.1>
11112 11:54:08.059519 Received signal: <ENDRUN> 0_timesync-off 12066530_1.6.2.3.1
11113 11:54:08.059611 Ending use of test pattern.
11114 11:54:08.059677 Ending test lava.0_timesync-off (12066530_1.6.2.3.1), duration 0.07
11116 11:54:08.118447 + export TESTRUN_ID=1_kselftest-dt
11117 11:54:08.121867 + TESTRUN_ID=1_kselftest-dt
11118 11:54:08.125176 + cd /lava-12066530/0/tests/1_kselftest-dt
11119 11:54:08.128203 ++ cat uuid
11120 11:54:08.128294 + UUID=12066530_1.6.2.3.5
11121 11:54:08.131786 + set +x
11122 11:54:08.135224 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12066530_1.6.2.3.5>
11123 11:54:08.135487 Received signal: <STARTRUN> 1_kselftest-dt 12066530_1.6.2.3.5
11124 11:54:08.135559 Starting test lava.1_kselftest-dt (12066530_1.6.2.3.5)
11125 11:54:08.135642 Skipping test definition patterns.
11126 11:54:08.138790 + cd ./automated/linux/kselftest/
11127 11:54:08.167988 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11128 11:54:08.191570 INFO: install_deps skipped
11129 11:54:08.298170 --2023-11-23 11:53:33-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11130 11:54:08.304348 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11131 11:54:08.435070 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11132 11:54:08.567655 HTTP request sent, awaiting response... 200 OK
11133 11:54:08.571247 Length: 2962844 (2.8M) [application/octet-stream]
11134 11:54:08.574287 Saving to: 'kselftest.tar.xz'
11135 11:54:08.574376
11136 11:54:08.574463
11137 11:54:08.833543 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11138 11:54:09.099040 kselftest.tar.xz 1%[ ] 49.22K 187KB/s
11139 11:54:09.412398 kselftest.tar.xz 7%[> ] 218.91K 414KB/s
11140 11:54:09.688313 kselftest.tar.xz 27%[====> ] 808.57K 959KB/s
11141 11:54:09.814770 kselftest.tar.xz 68%[============> ] 1.93M 1.73MB/s
11142 11:54:09.821566 kselftest.tar.xz 100%[===================>] 2.83M 2.27MB/s in 1.2s
11143 11:54:09.821682
11144 11:54:10.078961 2023-11-23 11:53:35 (2.27 MB/s) - 'kselftest.tar.xz' saved [2962844/2962844]
11145 11:54:10.079115
11146 11:54:15.422894 skiplist:
11147 11:54:15.426342 ========================================
11148 11:54:15.429688 ========================================
11149 11:54:15.489182 ============== Tests to run ===============
11150 11:54:15.492303 ===========End Tests to run ===============
11151 11:54:15.498192 shardfile-dt fail
11152 11:54:15.520856 ./kselftest.sh: 131: cannot open /lava-12066530/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11153 11:54:15.524353 + ../../utils/send-to-lava.sh ./output/result.txt
11154 11:54:15.584046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11155 11:54:15.584193 + set +x
11156 11:54:15.584440 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11158 11:54:15.590016 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12066530_1.6.2.3.5>
11159 11:54:15.590103 <LAVA_TEST_RUNNER EXIT>
11160 11:54:15.590340 Received signal: <ENDRUN> 1_kselftest-dt 12066530_1.6.2.3.5
11161 11:54:15.590421 Ending use of test pattern.
11162 11:54:15.590526 Ending test lava.1_kselftest-dt (12066530_1.6.2.3.5), duration 7.45
11164 11:54:15.590750 ok: lava_test_shell seems to have completed
11165 11:54:15.590842 shardfile-dt: fail
11166 11:54:15.590929 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11167 11:54:15.591013 end: 3 lava-test-retry (duration 00:00:08) [common]
11168 11:54:15.591099 start: 4 finalize (timeout 00:07:22) [common]
11169 11:54:15.591190 start: 4.1 power-off (timeout 00:00:30) [common]
11170 11:54:15.591343 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11171 11:54:15.666236 >> Command sent successfully.
11172 11:54:15.668604 Returned 0 in 0 seconds
11173 11:54:15.769028 end: 4.1 power-off (duration 00:00:00) [common]
11175 11:54:15.769368 start: 4.2 read-feedback (timeout 00:07:21) [common]
11176 11:54:15.769629 Listened to connection for namespace 'common' for up to 1s
11177 11:54:15.769917 Listened to connection for namespace 'common' for up to 1s
11178 11:54:16.770539 Finalising connection for namespace 'common'
11179 11:54:16.770773 Disconnecting from shell: Finalise
11180 11:54:16.770855 / #
11181 11:54:16.871220 end: 4.2 read-feedback (duration 00:00:01) [common]
11182 11:54:16.871450 end: 4 finalize (duration 00:00:01) [common]
11183 11:54:16.871571 Cleaning after the job
11184 11:54:16.871677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/ramdisk
11185 11:54:16.874085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/kernel
11186 11:54:16.883890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/dtb
11187 11:54:16.884098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/nfsrootfs
11188 11:54:16.951235 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066530/tftp-deploy-2foalg4i/modules
11189 11:54:16.956781 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066530
11190 11:54:17.499943 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066530
11191 11:54:17.500130 Job finished correctly