Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 135
- Kernel Warnings: 23
- Boot result: PASS
- Errors: 0
1 11:58:25.528150 lava-dispatcher, installed at version: 2023.10
2 11:58:25.528423 start: 0 validate
3 11:58:25.528561 Start time: 2023-11-23 11:58:25.528553+00:00 (UTC)
4 11:58:25.528690 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:58:25.528825 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:58:25.795994 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:58:25.796171 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:58:26.061505 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:58:26.061753 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:58:26.318839 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:58:26.319022 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:58:26.586302 validate duration: 1.06
14 11:58:26.586591 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:58:26.586687 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:58:26.586771 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:58:26.586897 Not decompressing ramdisk as can be used compressed.
18 11:58:26.586983 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 11:58:26.587046 saving as /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/ramdisk/rootfs.cpio.gz
20 11:58:26.587108 total size: 84918747 (80 MB)
21 11:58:26.588233 progress 0 % (0 MB)
22 11:58:26.610446 progress 5 % (4 MB)
23 11:58:26.632683 progress 10 % (8 MB)
24 11:58:26.654436 progress 15 % (12 MB)
25 11:58:26.676687 progress 20 % (16 MB)
26 11:58:26.698614 progress 25 % (20 MB)
27 11:58:26.720806 progress 30 % (24 MB)
28 11:58:26.742873 progress 35 % (28 MB)
29 11:58:26.764709 progress 40 % (32 MB)
30 11:58:26.786894 progress 45 % (36 MB)
31 11:58:26.808681 progress 50 % (40 MB)
32 11:58:26.830851 progress 55 % (44 MB)
33 11:58:26.852565 progress 60 % (48 MB)
34 11:58:26.874554 progress 65 % (52 MB)
35 11:58:26.896813 progress 70 % (56 MB)
36 11:58:26.918597 progress 75 % (60 MB)
37 11:58:26.940703 progress 80 % (64 MB)
38 11:58:26.962531 progress 85 % (68 MB)
39 11:58:26.984774 progress 90 % (72 MB)
40 11:58:27.006893 progress 95 % (76 MB)
41 11:58:27.028441 progress 100 % (80 MB)
42 11:58:27.028690 80 MB downloaded in 0.44 s (183.40 MB/s)
43 11:58:27.028861 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:58:27.029103 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:58:27.029189 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:58:27.029273 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:58:27.029412 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:58:27.029483 saving as /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/kernel/Image
50 11:58:27.029543 total size: 49107456 (46 MB)
51 11:58:27.029662 No compression specified
52 11:58:27.030756 progress 0 % (0 MB)
53 11:58:27.043403 progress 5 % (2 MB)
54 11:58:27.056349 progress 10 % (4 MB)
55 11:58:27.069221 progress 15 % (7 MB)
56 11:58:27.082120 progress 20 % (9 MB)
57 11:58:27.095106 progress 25 % (11 MB)
58 11:58:27.108167 progress 30 % (14 MB)
59 11:58:27.120925 progress 35 % (16 MB)
60 11:58:27.133625 progress 40 % (18 MB)
61 11:58:27.146419 progress 45 % (21 MB)
62 11:58:27.159400 progress 50 % (23 MB)
63 11:58:27.172235 progress 55 % (25 MB)
64 11:58:27.185150 progress 60 % (28 MB)
65 11:58:27.198027 progress 65 % (30 MB)
66 11:58:27.211119 progress 70 % (32 MB)
67 11:58:27.223860 progress 75 % (35 MB)
68 11:58:27.236606 progress 80 % (37 MB)
69 11:58:27.249441 progress 85 % (39 MB)
70 11:58:27.262318 progress 90 % (42 MB)
71 11:58:27.274995 progress 95 % (44 MB)
72 11:58:27.287533 progress 100 % (46 MB)
73 11:58:27.287797 46 MB downloaded in 0.26 s (181.35 MB/s)
74 11:58:27.287958 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:58:27.288184 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:58:27.288274 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:58:27.288357 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:58:27.288494 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:58:27.288561 saving as /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/dtb/mt8192-asurada-spherion-r0.dtb
81 11:58:27.288619 total size: 47278 (0 MB)
82 11:58:27.288678 No compression specified
83 11:58:27.289835 progress 69 % (0 MB)
84 11:58:27.290109 progress 100 % (0 MB)
85 11:58:27.290261 0 MB downloaded in 0.00 s (27.50 MB/s)
86 11:58:27.290382 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:58:27.290597 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:58:27.290679 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:58:27.290760 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:58:27.290875 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:58:27.290944 saving as /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/modules/modules.tar
93 11:58:27.291002 total size: 8621364 (8 MB)
94 11:58:27.291078 Using unxz to decompress xz
95 11:58:27.295371 progress 0 % (0 MB)
96 11:58:27.316709 progress 5 % (0 MB)
97 11:58:27.340413 progress 10 % (0 MB)
98 11:58:27.364035 progress 15 % (1 MB)
99 11:58:27.387964 progress 20 % (1 MB)
100 11:58:27.412513 progress 25 % (2 MB)
101 11:58:27.439116 progress 30 % (2 MB)
102 11:58:27.467850 progress 35 % (2 MB)
103 11:58:27.491601 progress 40 % (3 MB)
104 11:58:27.516426 progress 45 % (3 MB)
105 11:58:27.542059 progress 50 % (4 MB)
106 11:58:27.566945 progress 55 % (4 MB)
107 11:58:27.592300 progress 60 % (4 MB)
108 11:58:27.620471 progress 65 % (5 MB)
109 11:58:27.645874 progress 70 % (5 MB)
110 11:58:27.669405 progress 75 % (6 MB)
111 11:58:27.697035 progress 80 % (6 MB)
112 11:58:27.723329 progress 85 % (7 MB)
113 11:58:27.748796 progress 90 % (7 MB)
114 11:58:27.778523 progress 95 % (7 MB)
115 11:58:27.809820 progress 100 % (8 MB)
116 11:58:27.814731 8 MB downloaded in 0.52 s (15.70 MB/s)
117 11:58:27.815004 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:58:27.815266 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:58:27.815360 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:58:27.815456 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:58:27.815535 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:58:27.815625 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:58:27.815854 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1
125 11:58:27.815988 makedir: /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin
126 11:58:27.816142 makedir: /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/tests
127 11:58:27.816300 makedir: /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/results
128 11:58:27.816437 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-add-keys
129 11:58:27.816609 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-add-sources
130 11:58:27.816764 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-background-process-start
131 11:58:27.816919 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-background-process-stop
132 11:58:27.817065 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-common-functions
133 11:58:27.817212 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-echo-ipv4
134 11:58:27.817386 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-install-packages
135 11:58:27.817559 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-installed-packages
136 11:58:27.817777 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-os-build
137 11:58:27.817948 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-probe-channel
138 11:58:27.818094 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-probe-ip
139 11:58:27.818240 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-target-ip
140 11:58:27.818386 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-target-mac
141 11:58:27.818534 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-target-storage
142 11:58:27.818713 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-case
143 11:58:27.818884 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-event
144 11:58:27.819029 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-feedback
145 11:58:27.819180 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-raise
146 11:58:27.819354 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-reference
147 11:58:27.819527 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-runner
148 11:58:27.819699 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-set
149 11:58:27.819874 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-test-shell
150 11:58:27.820053 Updating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-install-packages (oe)
151 11:58:27.820257 Updating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/bin/lava-installed-packages (oe)
152 11:58:27.820425 Creating /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/environment
153 11:58:27.820569 LAVA metadata
154 11:58:27.820677 - LAVA_JOB_ID=12066560
155 11:58:27.820780 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:58:27.820940 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:58:27.821039 skipped lava-vland-overlay
158 11:58:27.821166 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:58:27.821294 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:58:27.821394 skipped lava-multinode-overlay
161 11:58:27.821518 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:58:27.821692 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:58:27.821808 Loading test definitions
164 11:58:27.821947 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 11:58:27.822057 Using /lava-12066560 at stage 0
166 11:58:27.822209 Fetching tests from https://github.com/kernelci/kernelci-core
167 11:58:27.822329 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/0/tests/0_sleep'
168 11:58:28.605290 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/0/tests/0_sleep
169 11:58:28.606665 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 11:58:28.607075 uuid=12066560_1.5.2.3.1 testdef=None
171 11:58:28.607219 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 11:58:28.607543 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 11:58:28.608118 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 11:58:28.608346 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 11:58:28.609057 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 11:58:28.609293 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 11:58:28.610025 runner path: /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/0/tests/0_sleep test_uuid 12066560_1.5.2.3.1
181 11:58:28.610110 sleep_params='mem freeze'
182 11:58:28.610251 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 11:58:28.610461 Creating lava-test-runner.conf files
185 11:58:28.610524 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066560/lava-overlay-4iefrfe1/lava-12066560/0 for stage 0
186 11:58:28.610616 - 0_sleep
187 11:58:28.610718 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 11:58:28.610802 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 11:58:28.741467 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 11:58:28.741679 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 11:58:28.741771 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 11:58:28.741869 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 11:58:28.741958 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 11:58:31.217312 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 11:58:31.217776 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 11:58:31.217928 extracting modules file /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066560/extract-overlay-ramdisk-i6o71xto/ramdisk
197 11:58:31.451820 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 11:58:31.451991 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 11:58:31.452087 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066560/compress-overlay-q9zfseul/overlay-1.5.2.4.tar.gz to ramdisk
200 11:58:31.452162 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066560/compress-overlay-q9zfseul/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066560/extract-overlay-ramdisk-i6o71xto/ramdisk
201 11:58:31.549682 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 11:58:31.549871 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 11:58:31.549985 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 11:58:31.550104 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 11:58:31.550206 Building ramdisk /var/lib/lava/dispatcher/tmp/12066560/extract-overlay-ramdisk-i6o71xto/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066560/extract-overlay-ramdisk-i6o71xto/ramdisk
206 11:58:33.102616 >> 563549 blocks
207 11:58:43.025999 rename /var/lib/lava/dispatcher/tmp/12066560/extract-overlay-ramdisk-i6o71xto/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/ramdisk/ramdisk.cpio.gz
208 11:58:43.026490 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 11:58:43.026635 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 11:58:43.026757 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 11:58:43.026895 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/kernel/Image'
212 11:58:55.571894 Returned 0 in 12 seconds
213 11:58:55.672548 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/kernel/image.itb
214 11:58:57.031192 output: FIT description: Kernel Image image with one or more FDT blobs
215 11:58:57.031602 output: Created: Thu Nov 23 11:58:56 2023
216 11:58:57.031687 output: Image 0 (kernel-1)
217 11:58:57.031756 output: Description:
218 11:58:57.031819 output: Created: Thu Nov 23 11:58:56 2023
219 11:58:57.031882 output: Type: Kernel Image
220 11:58:57.031941 output: Compression: lzma compressed
221 11:58:57.031996 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
222 11:58:57.032051 output: Architecture: AArch64
223 11:58:57.032105 output: OS: Linux
224 11:58:57.032162 output: Load Address: 0x00000000
225 11:58:57.032214 output: Entry Point: 0x00000000
226 11:58:57.032273 output: Hash algo: crc32
227 11:58:57.032329 output: Hash value: e6d7c86f
228 11:58:57.032388 output: Image 1 (fdt-1)
229 11:58:57.032444 output: Description: mt8192-asurada-spherion-r0
230 11:58:57.032496 output: Created: Thu Nov 23 11:58:56 2023
231 11:58:57.032548 output: Type: Flat Device Tree
232 11:58:57.032599 output: Compression: uncompressed
233 11:58:57.032651 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 11:58:57.032703 output: Architecture: AArch64
235 11:58:57.032754 output: Hash algo: crc32
236 11:58:57.032805 output: Hash value: cc4352de
237 11:58:57.032856 output: Image 2 (ramdisk-1)
238 11:58:57.032907 output: Description: unavailable
239 11:58:57.032958 output: Created: Thu Nov 23 11:58:56 2023
240 11:58:57.033010 output: Type: RAMDisk Image
241 11:58:57.033064 output: Compression: Unknown Compression
242 11:58:57.033116 output: Data Size: 98333691 Bytes = 96029.00 KiB = 93.78 MiB
243 11:58:57.033168 output: Architecture: AArch64
244 11:58:57.033219 output: OS: Linux
245 11:58:57.033270 output: Load Address: unavailable
246 11:58:57.033321 output: Entry Point: unavailable
247 11:58:57.033371 output: Hash algo: crc32
248 11:58:57.033422 output: Hash value: a54d7d1e
249 11:58:57.033473 output: Default Configuration: 'conf-1'
250 11:58:57.033524 output: Configuration 0 (conf-1)
251 11:58:57.033585 output: Description: mt8192-asurada-spherion-r0
252 11:58:57.033640 output: Kernel: kernel-1
253 11:58:57.033691 output: Init Ramdisk: ramdisk-1
254 11:58:57.033743 output: FDT: fdt-1
255 11:58:57.033794 output: Loadables: kernel-1
256 11:58:57.033845 output:
257 11:58:57.034046 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 11:58:57.034137 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 11:58:57.034239 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 11:58:57.034331 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
261 11:58:57.034416 No LXC device requested
262 11:58:57.034493 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 11:58:57.034577 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
264 11:58:57.034653 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 11:58:57.034725 Checking files for TFTP limit of 4294967296 bytes.
266 11:58:57.035230 end: 1 tftp-deploy (duration 00:00:30) [common]
267 11:58:57.035335 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 11:58:57.035424 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 11:58:57.035553 substitutions:
270 11:58:57.035620 - {DTB}: 12066560/tftp-deploy-3c0cps04/dtb/mt8192-asurada-spherion-r0.dtb
271 11:58:57.035683 - {INITRD}: 12066560/tftp-deploy-3c0cps04/ramdisk/ramdisk.cpio.gz
272 11:58:57.035741 - {KERNEL}: 12066560/tftp-deploy-3c0cps04/kernel/Image
273 11:58:57.035797 - {LAVA_MAC}: None
274 11:58:57.035853 - {PRESEED_CONFIG}: None
275 11:58:57.035906 - {PRESEED_LOCAL}: None
276 11:58:57.035960 - {RAMDISK}: 12066560/tftp-deploy-3c0cps04/ramdisk/ramdisk.cpio.gz
277 11:58:57.036013 - {ROOT_PART}: None
278 11:58:57.036066 - {ROOT}: None
279 11:58:57.036118 - {SERVER_IP}: 192.168.201.1
280 11:58:57.036171 - {TEE}: None
281 11:58:57.036223 Parsed boot commands:
282 11:58:57.036277 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 11:58:57.036456 Parsed boot commands: tftpboot 192.168.201.1 12066560/tftp-deploy-3c0cps04/kernel/image.itb 12066560/tftp-deploy-3c0cps04/kernel/cmdline
284 11:58:57.036546 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 11:58:57.036631 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 11:58:57.036724 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 11:58:57.036811 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 11:58:57.036879 Not connected, no need to disconnect.
289 11:58:57.036951 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 11:58:57.037031 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 11:58:57.037094 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 11:58:57.041259 Setting prompt string to ['lava-test: # ']
293 11:58:57.041658 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 11:58:57.041771 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 11:58:57.041873 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 11:58:57.041961 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 11:58:57.042221 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 11:59:02.177850 >> Command sent successfully.
299 11:59:02.180392 Returned 0 in 5 seconds
300 11:59:02.280802 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 11:59:02.281117 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 11:59:02.281216 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 11:59:02.281307 Setting prompt string to 'Starting depthcharge on Spherion...'
305 11:59:02.281372 Changing prompt to 'Starting depthcharge on Spherion...'
306 11:59:02.281442 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 11:59:02.281751 [Enter `^Ec?' for help]
308 11:59:02.454675
309 11:59:02.454843
310 11:59:02.454948 F0: 102B 0000
311 11:59:02.455047
312 11:59:02.455114 F3: 1001 0000 [0200]
313 11:59:02.455173
314 11:59:02.458041 F3: 1001 0000
315 11:59:02.458157
316 11:59:02.458265 F7: 102D 0000
317 11:59:02.458347
318 11:59:02.460891 F1: 0000 0000
319 11:59:02.461032
320 11:59:02.461137 V0: 0000 0000 [0001]
321 11:59:02.461268
322 11:59:02.464640 00: 0007 8000
323 11:59:02.464755
324 11:59:02.464838 01: 0000 0000
325 11:59:02.464920
326 11:59:02.467762 BP: 0C00 0209 [0000]
327 11:59:02.467882
328 11:59:02.467995 G0: 1182 0000
329 11:59:02.468099
330 11:59:02.468204 EC: 0000 0021 [4000]
331 11:59:02.471657
332 11:59:02.471745 S7: 0000 0000 [0000]
333 11:59:02.471833
334 11:59:02.471916 CC: 0000 0000 [0001]
335 11:59:02.475035
336 11:59:02.475125 T0: 0000 0040 [010F]
337 11:59:02.475214
338 11:59:02.475296 Jump to BL
339 11:59:02.475377
340 11:59:02.501593
341 11:59:02.501720
342 11:59:02.501813
343 11:59:02.508479 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 11:59:02.512133 ARM64: Exception handlers installed.
345 11:59:02.515642 ARM64: Testing exception
346 11:59:02.518917 ARM64: Done test exception
347 11:59:02.525412 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 11:59:02.535568 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 11:59:02.542178 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 11:59:02.552741 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 11:59:02.559689 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 11:59:02.565772 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 11:59:02.577998 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 11:59:02.584869 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 11:59:02.604039 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 11:59:02.607745 WDT: Last reset was cold boot
357 11:59:02.610922 SPI1(PAD0) initialized at 2873684 Hz
358 11:59:02.614604 SPI5(PAD0) initialized at 992727 Hz
359 11:59:02.617505 VBOOT: Loading verstage.
360 11:59:02.624448 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 11:59:02.628720 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 11:59:02.631664 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 11:59:02.635285 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 11:59:02.642008 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 11:59:02.648258 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 11:59:02.659609 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 11:59:02.659698
368 11:59:02.659785
369 11:59:02.670139 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 11:59:02.673307 ARM64: Exception handlers installed.
371 11:59:02.673395 ARM64: Testing exception
372 11:59:02.677286 ARM64: Done test exception
373 11:59:02.679933 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 11:59:02.686579 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 11:59:02.700125 Probing TPM: . done!
376 11:59:02.700216 TPM ready after 0 ms
377 11:59:02.707128 Connected to device vid:did:rid of 1ae0:0028:00
378 11:59:02.714137 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 11:59:02.773599 Initialized TPM device CR50 revision 0
380 11:59:02.785297 tlcl_send_startup: Startup return code is 0
381 11:59:02.785420 TPM: setup succeeded
382 11:59:02.796430 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 11:59:02.805473 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 11:59:02.817619 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 11:59:02.828059 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 11:59:02.831417 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 11:59:02.834962 in-header: 03 07 00 00 08 00 00 00
388 11:59:02.839555 in-data: aa e4 47 04 13 02 00 00
389 11:59:02.839652 Chrome EC: UHEPI supported
390 11:59:02.846130 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 11:59:02.849854 in-header: 03 95 00 00 08 00 00 00
392 11:59:02.854059 in-data: 18 20 20 08 00 00 00 00
393 11:59:02.854146 Phase 1
394 11:59:02.857912 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 11:59:02.865136 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 11:59:02.868840 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 11:59:02.872377 Recovery requested (1009000e)
398 11:59:02.883784 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 11:59:02.887619 tlcl_extend: response is 0
400 11:59:02.899342 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 11:59:02.902967 tlcl_extend: response is 0
402 11:59:02.910162 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 11:59:02.929301 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 11:59:02.935927 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 11:59:02.936016
406 11:59:02.936081
407 11:59:02.945936 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 11:59:02.949198 ARM64: Exception handlers installed.
409 11:59:02.952555 ARM64: Testing exception
410 11:59:02.952637 ARM64: Done test exception
411 11:59:02.975000 pmic_efuse_setting: Set efuses in 11 msecs
412 11:59:02.978565 pmwrap_interface_init: Select PMIF_VLD_RDY
413 11:59:02.985104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 11:59:02.988248 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 11:59:02.995563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 11:59:02.998936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 11:59:03.002655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 11:59:03.010453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 11:59:03.013544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 11:59:03.017887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 11:59:03.021415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 11:59:03.029193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 11:59:03.032557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 11:59:03.036911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 11:59:03.040142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 11:59:03.047461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 11:59:03.054692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 11:59:03.058419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 11:59:03.065932 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 11:59:03.069469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 11:59:03.076466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 11:59:03.080417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 11:59:03.088412 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 11:59:03.092356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 11:59:03.099199 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 11:59:03.103235 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 11:59:03.106951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 11:59:03.114572 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 11:59:03.117737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 11:59:03.125633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 11:59:03.129350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 11:59:03.132937 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 11:59:03.140394 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 11:59:03.143442 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 11:59:03.147131 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 11:59:03.154695 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 11:59:03.158393 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 11:59:03.165802 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 11:59:03.169113 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 11:59:03.172762 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 11:59:03.176463 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 11:59:03.183799 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 11:59:03.187909 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 11:59:03.191196 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 11:59:03.195039 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 11:59:03.198343 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 11:59:03.206617 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 11:59:03.210128 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 11:59:03.214150 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 11:59:03.217607 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 11:59:03.221614 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 11:59:03.224883 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 11:59:03.228665 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 11:59:03.236320 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 11:59:03.247296 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 11:59:03.250974 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 11:59:03.257758 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 11:59:03.269011 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 11:59:03.272988 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 11:59:03.276736 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 11:59:03.280274 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 11:59:03.288060 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
473 11:59:03.291865 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 11:59:03.300649 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 11:59:03.303306 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 11:59:03.312241 [RTC]rtc_get_frequency_meter,154: input=15, output=759
477 11:59:03.321839 [RTC]rtc_get_frequency_meter,154: input=23, output=942
478 11:59:03.331481 [RTC]rtc_get_frequency_meter,154: input=19, output=851
479 11:59:03.341123 [RTC]rtc_get_frequency_meter,154: input=17, output=803
480 11:59:03.351034 [RTC]rtc_get_frequency_meter,154: input=16, output=783
481 11:59:03.360136 [RTC]rtc_get_frequency_meter,154: input=16, output=783
482 11:59:03.369757 [RTC]rtc_get_frequency_meter,154: input=17, output=805
483 11:59:03.372808 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 11:59:03.380500 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 11:59:03.384361 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 11:59:03.387936 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 11:59:03.391579 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 11:59:03.395311 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 11:59:03.399501 ADC[4]: Raw value=906203 ID=7
490 11:59:03.402546 ADC[3]: Raw value=213441 ID=1
491 11:59:03.402632 RAM Code: 0x71
492 11:59:03.406567 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 11:59:03.414433 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 11:59:03.421698 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 11:59:03.428834 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 11:59:03.432375 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 11:59:03.435947 in-header: 03 07 00 00 08 00 00 00
498 11:59:03.439445 in-data: aa e4 47 04 13 02 00 00
499 11:59:03.439537 Chrome EC: UHEPI supported
500 11:59:03.446918 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 11:59:03.450779 in-header: 03 95 00 00 08 00 00 00
502 11:59:03.454312 in-data: 18 20 20 08 00 00 00 00
503 11:59:03.458355 MRC: failed to locate region type 0.
504 11:59:03.465338 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 11:59:03.465430 DRAM-K: Running full calibration
506 11:59:03.472846 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 11:59:03.476625 header.status = 0x0
508 11:59:03.480411 header.version = 0x6 (expected: 0x6)
509 11:59:03.480505 header.size = 0xd00 (expected: 0xd00)
510 11:59:03.484245 header.flags = 0x0
511 11:59:03.488449 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 11:59:03.508688 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
513 11:59:03.515795 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 11:59:03.515895 dram_init: ddr_geometry: 2
515 11:59:03.519787 [EMI] MDL number = 2
516 11:59:03.519873 [EMI] Get MDL freq = 0
517 11:59:03.524107 dram_init: ddr_type: 0
518 11:59:03.524192 is_discrete_lpddr4: 1
519 11:59:03.527112 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 11:59:03.527197
521 11:59:03.527264
522 11:59:03.530815 [Bian_co] ETT version 0.0.0.1
523 11:59:03.534928 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 11:59:03.535014
525 11:59:03.538961 dramc_set_vcore_voltage set vcore to 650000
526 11:59:03.542722 Read voltage for 800, 4
527 11:59:03.542806 Vio18 = 0
528 11:59:03.546430 Vcore = 650000
529 11:59:03.546513 Vdram = 0
530 11:59:03.546580 Vddq = 0
531 11:59:03.546641 Vmddr = 0
532 11:59:03.550075 dram_init: config_dvfs: 1
533 11:59:03.553897 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 11:59:03.561037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 11:59:03.565418 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 11:59:03.568137 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 11:59:03.572181 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 11:59:03.576203 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 11:59:03.576292 MEM_TYPE=3, freq_sel=18
540 11:59:03.579990 sv_algorithm_assistance_LP4_1600
541 11:59:03.586316 ============ PULL DRAM RESETB DOWN ============
542 11:59:03.589419 ========== PULL DRAM RESETB DOWN end =========
543 11:59:03.592673 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 11:59:03.596357 ===================================
545 11:59:03.599785 LPDDR4 DRAM CONFIGURATION
546 11:59:03.603648 ===================================
547 11:59:03.603732 EX_ROW_EN[0] = 0x0
548 11:59:03.607257 EX_ROW_EN[1] = 0x0
549 11:59:03.607340 LP4Y_EN = 0x0
550 11:59:03.611250 WORK_FSP = 0x0
551 11:59:03.611335 WL = 0x2
552 11:59:03.614638 RL = 0x2
553 11:59:03.614720 BL = 0x2
554 11:59:03.618315 RPST = 0x0
555 11:59:03.618397 RD_PRE = 0x0
556 11:59:03.621885 WR_PRE = 0x1
557 11:59:03.621967 WR_PST = 0x0
558 11:59:03.625538 DBI_WR = 0x0
559 11:59:03.625673 DBI_RD = 0x0
560 11:59:03.628736 OTF = 0x1
561 11:59:03.631675 ===================================
562 11:59:03.635259 ===================================
563 11:59:03.635341 ANA top config
564 11:59:03.638935 ===================================
565 11:59:03.641760 DLL_ASYNC_EN = 0
566 11:59:03.641842 ALL_SLAVE_EN = 1
567 11:59:03.645607 NEW_RANK_MODE = 1
568 11:59:03.648716 DLL_IDLE_MODE = 1
569 11:59:03.651754 LP45_APHY_COMB_EN = 1
570 11:59:03.655313 TX_ODT_DIS = 1
571 11:59:03.655396 NEW_8X_MODE = 1
572 11:59:03.659651 ===================================
573 11:59:03.662549 ===================================
574 11:59:03.666205 data_rate = 1600
575 11:59:03.669472 CKR = 1
576 11:59:03.672761 DQ_P2S_RATIO = 8
577 11:59:03.675665 ===================================
578 11:59:03.675748 CA_P2S_RATIO = 8
579 11:59:03.679083 DQ_CA_OPEN = 0
580 11:59:03.682487 DQ_SEMI_OPEN = 0
581 11:59:03.685928 CA_SEMI_OPEN = 0
582 11:59:03.689697 CA_FULL_RATE = 0
583 11:59:03.692599 DQ_CKDIV4_EN = 1
584 11:59:03.692681 CA_CKDIV4_EN = 1
585 11:59:03.696419 CA_PREDIV_EN = 0
586 11:59:03.699412 PH8_DLY = 0
587 11:59:03.703097 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 11:59:03.706025 DQ_AAMCK_DIV = 4
589 11:59:03.709803 CA_AAMCK_DIV = 4
590 11:59:03.709885 CA_ADMCK_DIV = 4
591 11:59:03.712976 DQ_TRACK_CA_EN = 0
592 11:59:03.716798 CA_PICK = 800
593 11:59:03.719403 CA_MCKIO = 800
594 11:59:03.724113 MCKIO_SEMI = 0
595 11:59:03.724198 PLL_FREQ = 3068
596 11:59:03.727214 DQ_UI_PI_RATIO = 32
597 11:59:03.730538 CA_UI_PI_RATIO = 0
598 11:59:03.734339 ===================================
599 11:59:03.738524 ===================================
600 11:59:03.738635 memory_type:LPDDR4
601 11:59:03.742076 GP_NUM : 10
602 11:59:03.742188 SRAM_EN : 1
603 11:59:03.745843 MD32_EN : 0
604 11:59:03.749337 ===================================
605 11:59:03.753055 [ANA_INIT] >>>>>>>>>>>>>>
606 11:59:03.753141 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 11:59:03.756822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 11:59:03.760226 ===================================
609 11:59:03.763229 data_rate = 1600,PCW = 0X7600
610 11:59:03.766809 ===================================
611 11:59:03.770430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 11:59:03.776731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 11:59:03.780029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 11:59:03.787198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 11:59:03.789976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 11:59:03.793369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 11:59:03.793451 [ANA_INIT] flow start
618 11:59:03.796865 [ANA_INIT] PLL >>>>>>>>
619 11:59:03.799951 [ANA_INIT] PLL <<<<<<<<
620 11:59:03.803573 [ANA_INIT] MIDPI >>>>>>>>
621 11:59:03.803655 [ANA_INIT] MIDPI <<<<<<<<
622 11:59:03.806588 [ANA_INIT] DLL >>>>>>>>
623 11:59:03.810296 [ANA_INIT] flow end
624 11:59:03.813263 ============ LP4 DIFF to SE enter ============
625 11:59:03.816686 ============ LP4 DIFF to SE exit ============
626 11:59:03.819856 [ANA_INIT] <<<<<<<<<<<<<
627 11:59:03.823441 [Flow] Enable top DCM control >>>>>
628 11:59:03.826609 [Flow] Enable top DCM control <<<<<
629 11:59:03.830288 Enable DLL master slave shuffle
630 11:59:03.833718 ==============================================================
631 11:59:03.836667 Gating Mode config
632 11:59:03.840334 ==============================================================
633 11:59:03.843389 Config description:
634 11:59:03.853244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 11:59:03.860172 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 11:59:03.863690 SELPH_MODE 0: By rank 1: By Phase
637 11:59:03.870162 ==============================================================
638 11:59:03.873757 GAT_TRACK_EN = 1
639 11:59:03.876847 RX_GATING_MODE = 2
640 11:59:03.880296 RX_GATING_TRACK_MODE = 2
641 11:59:03.883833 SELPH_MODE = 1
642 11:59:03.883918 PICG_EARLY_EN = 1
643 11:59:03.886951 VALID_LAT_VALUE = 1
644 11:59:03.893832 ==============================================================
645 11:59:03.896526 Enter into Gating configuration >>>>
646 11:59:03.900124 Exit from Gating configuration <<<<
647 11:59:03.903664 Enter into DVFS_PRE_config >>>>>
648 11:59:03.913501 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 11:59:03.917147 Exit from DVFS_PRE_config <<<<<
650 11:59:03.920130 Enter into PICG configuration >>>>
651 11:59:03.923595 Exit from PICG configuration <<<<
652 11:59:03.926741 [RX_INPUT] configuration >>>>>
653 11:59:03.930438 [RX_INPUT] configuration <<<<<
654 11:59:03.933538 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 11:59:03.940442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 11:59:03.946822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 11:59:03.953343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 11:59:03.956863 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 11:59:03.963357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 11:59:03.966819 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 11:59:03.973786 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 11:59:03.977124 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 11:59:03.980059 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 11:59:03.983304 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 11:59:03.990260 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 11:59:03.993434 ===================================
667 11:59:03.993520 LPDDR4 DRAM CONFIGURATION
668 11:59:03.997153 ===================================
669 11:59:04.000207 EX_ROW_EN[0] = 0x0
670 11:59:04.003729 EX_ROW_EN[1] = 0x0
671 11:59:04.003813 LP4Y_EN = 0x0
672 11:59:04.007182 WORK_FSP = 0x0
673 11:59:04.007266 WL = 0x2
674 11:59:04.010568 RL = 0x2
675 11:59:04.010653 BL = 0x2
676 11:59:04.013563 RPST = 0x0
677 11:59:04.013687 RD_PRE = 0x0
678 11:59:04.017274 WR_PRE = 0x1
679 11:59:04.017357 WR_PST = 0x0
680 11:59:04.020328 DBI_WR = 0x0
681 11:59:04.020412 DBI_RD = 0x0
682 11:59:04.023740 OTF = 0x1
683 11:59:04.027336 ===================================
684 11:59:04.030458 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 11:59:04.033720 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 11:59:04.041018 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 11:59:04.041104 ===================================
688 11:59:04.043825 LPDDR4 DRAM CONFIGURATION
689 11:59:04.047392 ===================================
690 11:59:04.050692 EX_ROW_EN[0] = 0x10
691 11:59:04.050777 EX_ROW_EN[1] = 0x0
692 11:59:04.053813 LP4Y_EN = 0x0
693 11:59:04.053897 WORK_FSP = 0x0
694 11:59:04.057344 WL = 0x2
695 11:59:04.057430 RL = 0x2
696 11:59:04.060475 BL = 0x2
697 11:59:04.060559 RPST = 0x0
698 11:59:04.064300 RD_PRE = 0x0
699 11:59:04.067306 WR_PRE = 0x1
700 11:59:04.067389 WR_PST = 0x0
701 11:59:04.070338 DBI_WR = 0x0
702 11:59:04.070423 DBI_RD = 0x0
703 11:59:04.073886 OTF = 0x1
704 11:59:04.077170 ===================================
705 11:59:04.080424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 11:59:04.086076 nWR fixed to 40
707 11:59:04.089381 [ModeRegInit_LP4] CH0 RK0
708 11:59:04.089465 [ModeRegInit_LP4] CH0 RK1
709 11:59:04.092574 [ModeRegInit_LP4] CH1 RK0
710 11:59:04.095870 [ModeRegInit_LP4] CH1 RK1
711 11:59:04.095954 match AC timing 13
712 11:59:04.102390 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 11:59:04.105711 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 11:59:04.109211 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 11:59:04.115660 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 11:59:04.119086 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 11:59:04.119170 [EMI DOE] emi_dcm 0
718 11:59:04.125539 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 11:59:04.125678 ==
720 11:59:04.129301 Dram Type= 6, Freq= 0, CH_0, rank 0
721 11:59:04.132314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 11:59:04.132398 ==
723 11:59:04.139057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 11:59:04.145512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 11:59:04.153212 [CA 0] Center 36 (6~67) winsize 62
726 11:59:04.156592 [CA 1] Center 36 (6~67) winsize 62
727 11:59:04.159640 [CA 2] Center 34 (4~65) winsize 62
728 11:59:04.163374 [CA 3] Center 33 (3~64) winsize 62
729 11:59:04.166442 [CA 4] Center 33 (2~64) winsize 63
730 11:59:04.170229 [CA 5] Center 32 (2~62) winsize 61
731 11:59:04.170313
732 11:59:04.173251 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 11:59:04.173335
734 11:59:04.176896 [CATrainingPosCal] consider 1 rank data
735 11:59:04.179810 u2DelayCellTimex100 = 270/100 ps
736 11:59:04.183603 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 11:59:04.186661 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 11:59:04.193224 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 11:59:04.196777 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 11:59:04.200032 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
741 11:59:04.203617 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
742 11:59:04.203700
743 11:59:04.206660 CA PerBit enable=1, Macro0, CA PI delay=32
744 11:59:04.206743
745 11:59:04.209835 [CBTSetCACLKResult] CA Dly = 32
746 11:59:04.209918 CS Dly: 4 (0~35)
747 11:59:04.209984 ==
748 11:59:04.213292 Dram Type= 6, Freq= 0, CH_0, rank 1
749 11:59:04.219906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 11:59:04.219990 ==
751 11:59:04.223499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 11:59:04.230116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 11:59:04.239352 [CA 0] Center 36 (6~67) winsize 62
754 11:59:04.243045 [CA 1] Center 36 (6~67) winsize 62
755 11:59:04.246662 [CA 2] Center 34 (4~65) winsize 62
756 11:59:04.249336 [CA 3] Center 33 (3~64) winsize 62
757 11:59:04.253041 [CA 4] Center 32 (2~63) winsize 62
758 11:59:04.256248 [CA 5] Center 32 (2~63) winsize 62
759 11:59:04.256330
760 11:59:04.259650 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 11:59:04.259734
762 11:59:04.263002 [CATrainingPosCal] consider 2 rank data
763 11:59:04.266315 u2DelayCellTimex100 = 270/100 ps
764 11:59:04.269556 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 11:59:04.272859 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 11:59:04.279775 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 11:59:04.282725 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 11:59:04.286271 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
769 11:59:04.289423 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
770 11:59:04.289507
771 11:59:04.292984 CA PerBit enable=1, Macro0, CA PI delay=32
772 11:59:04.293067
773 11:59:04.296246 [CBTSetCACLKResult] CA Dly = 32
774 11:59:04.296329 CS Dly: 5 (0~37)
775 11:59:04.296396
776 11:59:04.299845 ----->DramcWriteLeveling(PI) begin...
777 11:59:04.302861 ==
778 11:59:04.302961 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:59:04.307095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:59:04.310440 ==
781 11:59:04.310532 Write leveling (Byte 0): 33 => 33
782 11:59:04.314113 Write leveling (Byte 1): 31 => 31
783 11:59:04.318214 DramcWriteLeveling(PI) end<-----
784 11:59:04.318298
785 11:59:04.318364 ==
786 11:59:04.321205 Dram Type= 6, Freq= 0, CH_0, rank 0
787 11:59:04.324641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 11:59:04.324734 ==
789 11:59:04.328162 [Gating] SW mode calibration
790 11:59:04.335492 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 11:59:04.341738 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 11:59:04.345439 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 11:59:04.348465 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 11:59:04.354983 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
795 11:59:04.358521 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 11:59:04.362005 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:59:04.368503 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:59:04.372185 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:59:04.375611 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:59:04.382130 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:59:04.385209 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:59:04.388659 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:59:04.392057 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:59:04.399027 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:59:04.402857 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:59:04.405705 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:59:04.412199 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:59:04.415728 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:59:04.419283 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
810 11:59:04.425885 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 11:59:04.429147 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:59:04.432522 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:59:04.439156 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:59:04.442105 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:59:04.445630 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:59:04.448878 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:59:04.455466 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:59:04.459285 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
819 11:59:04.463039 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
820 11:59:04.469287 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 11:59:04.472569 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 11:59:04.476323 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 11:59:04.482738 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 11:59:04.486119 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 11:59:04.489352 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
826 11:59:04.495840 0 10 8 | B1->B0 | 3131 2525 | 1 0 | (1 1) (0 0)
827 11:59:04.499272 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:59:04.502459 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:59:04.510142 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:59:04.513048 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:59:04.515971 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:59:04.523052 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:59:04.525952 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:59:04.529351 0 11 8 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
835 11:59:04.532761 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
836 11:59:04.539615 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 11:59:04.542949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 11:59:04.545986 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 11:59:04.552945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 11:59:04.556590 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 11:59:04.559444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 11:59:04.566490 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 11:59:04.569680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:59:04.573476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:59:04.580132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:59:04.582870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:59:04.586918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:59:04.593245 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:59:04.596190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:59:04.600197 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:59:04.606362 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:59:04.609700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 11:59:04.612914 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:59:04.616580 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:59:04.623540 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:59:04.626516 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:59:04.630182 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 11:59:04.636595 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 11:59:04.640178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 11:59:04.643269 Total UI for P1: 0, mck2ui 16
861 11:59:04.646466 best dqsien dly found for B0: ( 0, 14, 6)
862 11:59:04.649561 Total UI for P1: 0, mck2ui 16
863 11:59:04.653295 best dqsien dly found for B1: ( 0, 14, 8)
864 11:59:04.656875 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 11:59:04.660661 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 11:59:04.660834
867 11:59:04.663749 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 11:59:04.667348 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 11:59:04.670436 [Gating] SW calibration Done
870 11:59:04.670561 ==
871 11:59:04.673931 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:59:04.676912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 11:59:04.677024 ==
874 11:59:04.680587 RX Vref Scan: 0
875 11:59:04.680683
876 11:59:04.680755 RX Vref 0 -> 0, step: 1
877 11:59:04.680822
878 11:59:04.684163 RX Delay -130 -> 252, step: 16
879 11:59:04.687144 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 11:59:04.693976 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 11:59:04.697102 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 11:59:04.701045 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 11:59:04.704179 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 11:59:04.707576 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 11:59:04.713733 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
886 11:59:04.717544 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
887 11:59:04.720556 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 11:59:04.724285 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
889 11:59:04.727258 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 11:59:04.734183 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 11:59:04.737016 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 11:59:04.740681 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 11:59:04.744009 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 11:59:04.747145 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 11:59:04.750518 ==
896 11:59:04.750601 Dram Type= 6, Freq= 0, CH_0, rank 0
897 11:59:04.757153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 11:59:04.757237 ==
899 11:59:04.757303 DQS Delay:
900 11:59:04.760401 DQS0 = 0, DQS1 = 0
901 11:59:04.760483 DQM Delay:
902 11:59:04.764135 DQM0 = 93, DQM1 = 84
903 11:59:04.764216 DQ Delay:
904 11:59:04.767390 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
905 11:59:04.770899 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
906 11:59:04.774506 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
907 11:59:04.777345 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
908 11:59:04.777454
909 11:59:04.777546
910 11:59:04.777667 ==
911 11:59:04.780884 Dram Type= 6, Freq= 0, CH_0, rank 0
912 11:59:04.783840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 11:59:04.783922 ==
914 11:59:04.783987
915 11:59:04.784046
916 11:59:04.787589 TX Vref Scan disable
917 11:59:04.790562 == TX Byte 0 ==
918 11:59:04.794351 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
919 11:59:04.797322 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
920 11:59:04.797430 == TX Byte 1 ==
921 11:59:04.804032 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
922 11:59:04.807562 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
923 11:59:04.807644 ==
924 11:59:04.811032 Dram Type= 6, Freq= 0, CH_0, rank 0
925 11:59:04.814201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 11:59:04.814284 ==
927 11:59:04.828377 TX Vref=22, minBit 8, minWin=27, winSum=448
928 11:59:04.831723 TX Vref=24, minBit 10, minWin=27, winSum=450
929 11:59:04.835222 TX Vref=26, minBit 0, minWin=28, winSum=455
930 11:59:04.838909 TX Vref=28, minBit 5, minWin=28, winSum=456
931 11:59:04.841889 TX Vref=30, minBit 2, minWin=28, winSum=457
932 11:59:04.845154 TX Vref=32, minBit 0, minWin=28, winSum=456
933 11:59:04.852108 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
934 11:59:04.852191
935 11:59:04.855104 Final TX Range 1 Vref 30
936 11:59:04.855187
937 11:59:04.855252 ==
938 11:59:04.858461 Dram Type= 6, Freq= 0, CH_0, rank 0
939 11:59:04.861519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 11:59:04.861649 ==
941 11:59:04.864851
942 11:59:04.864943
943 11:59:04.865012 TX Vref Scan disable
944 11:59:04.868131 == TX Byte 0 ==
945 11:59:04.871694 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
946 11:59:04.875117 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
947 11:59:04.878688 == TX Byte 1 ==
948 11:59:04.882202 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 11:59:04.885125 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 11:59:04.885235
951 11:59:04.888683 [DATLAT]
952 11:59:04.888764 Freq=800, CH0 RK0
953 11:59:04.888838
954 11:59:04.891658 DATLAT Default: 0xa
955 11:59:04.891739 0, 0xFFFF, sum = 0
956 11:59:04.895608 1, 0xFFFF, sum = 0
957 11:59:04.895694 2, 0xFFFF, sum = 0
958 11:59:04.898767 3, 0xFFFF, sum = 0
959 11:59:04.898857 4, 0xFFFF, sum = 0
960 11:59:04.901809 5, 0xFFFF, sum = 0
961 11:59:04.901892 6, 0xFFFF, sum = 0
962 11:59:04.905146 7, 0xFFFF, sum = 0
963 11:59:04.908685 8, 0xFFFF, sum = 0
964 11:59:04.908768 9, 0x0, sum = 1
965 11:59:04.908833 10, 0x0, sum = 2
966 11:59:04.911929 11, 0x0, sum = 3
967 11:59:04.912011 12, 0x0, sum = 4
968 11:59:04.914839 best_step = 10
969 11:59:04.914920
970 11:59:04.914985 ==
971 11:59:04.918292 Dram Type= 6, Freq= 0, CH_0, rank 0
972 11:59:04.921493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 11:59:04.921582 ==
974 11:59:04.925067 RX Vref Scan: 1
975 11:59:04.925148
976 11:59:04.925211 Set Vref Range= 32 -> 127
977 11:59:04.925323
978 11:59:04.928677 RX Vref 32 -> 127, step: 1
979 11:59:04.928758
980 11:59:04.931563 RX Delay -79 -> 252, step: 8
981 11:59:04.931655
982 11:59:04.935295 Set Vref, RX VrefLevel [Byte0]: 32
983 11:59:04.938303 [Byte1]: 32
984 11:59:04.938385
985 11:59:04.941880 Set Vref, RX VrefLevel [Byte0]: 33
986 11:59:04.945445 [Byte1]: 33
987 11:59:04.948291
988 11:59:04.948399 Set Vref, RX VrefLevel [Byte0]: 34
989 11:59:04.952220 [Byte1]: 34
990 11:59:04.956651
991 11:59:04.956734 Set Vref, RX VrefLevel [Byte0]: 35
992 11:59:04.959207 [Byte1]: 35
993 11:59:04.963940
994 11:59:04.964018 Set Vref, RX VrefLevel [Byte0]: 36
995 11:59:04.967466 [Byte1]: 36
996 11:59:04.971648
997 11:59:04.971756 Set Vref, RX VrefLevel [Byte0]: 37
998 11:59:04.974813 [Byte1]: 37
999 11:59:04.979023
1000 11:59:04.979105 Set Vref, RX VrefLevel [Byte0]: 38
1001 11:59:04.982534 [Byte1]: 38
1002 11:59:04.986668
1003 11:59:04.986749 Set Vref, RX VrefLevel [Byte0]: 39
1004 11:59:04.990077 [Byte1]: 39
1005 11:59:04.994154
1006 11:59:04.994238 Set Vref, RX VrefLevel [Byte0]: 40
1007 11:59:04.997706 [Byte1]: 40
1008 11:59:05.001289
1009 11:59:05.004960 Set Vref, RX VrefLevel [Byte0]: 41
1010 11:59:05.005055 [Byte1]: 41
1011 11:59:05.009289
1012 11:59:05.009403 Set Vref, RX VrefLevel [Byte0]: 42
1013 11:59:05.012367 [Byte1]: 42
1014 11:59:05.016487
1015 11:59:05.016625 Set Vref, RX VrefLevel [Byte0]: 43
1016 11:59:05.020478 [Byte1]: 43
1017 11:59:05.023831
1018 11:59:05.023919 Set Vref, RX VrefLevel [Byte0]: 44
1019 11:59:05.027603 [Byte1]: 44
1020 11:59:05.031810
1021 11:59:05.031905 Set Vref, RX VrefLevel [Byte0]: 45
1022 11:59:05.034833 [Byte1]: 45
1023 11:59:05.039304
1024 11:59:05.039466 Set Vref, RX VrefLevel [Byte0]: 46
1025 11:59:05.042849 [Byte1]: 46
1026 11:59:05.047082
1027 11:59:05.047247 Set Vref, RX VrefLevel [Byte0]: 47
1028 11:59:05.050364 [Byte1]: 47
1029 11:59:05.054605
1030 11:59:05.054785 Set Vref, RX VrefLevel [Byte0]: 48
1031 11:59:05.057894 [Byte1]: 48
1032 11:59:05.062080
1033 11:59:05.062236 Set Vref, RX VrefLevel [Byte0]: 49
1034 11:59:05.065648 [Byte1]: 49
1035 11:59:05.069907
1036 11:59:05.070117 Set Vref, RX VrefLevel [Byte0]: 50
1037 11:59:05.072688 [Byte1]: 50
1038 11:59:05.076998
1039 11:59:05.077148 Set Vref, RX VrefLevel [Byte0]: 51
1040 11:59:05.080700 [Byte1]: 51
1041 11:59:05.084712
1042 11:59:05.084959 Set Vref, RX VrefLevel [Byte0]: 52
1043 11:59:05.088196 [Byte1]: 52
1044 11:59:05.092617
1045 11:59:05.093005 Set Vref, RX VrefLevel [Byte0]: 53
1046 11:59:05.095991 [Byte1]: 53
1047 11:59:05.100197
1048 11:59:05.100674 Set Vref, RX VrefLevel [Byte0]: 54
1049 11:59:05.103483 [Byte1]: 54
1050 11:59:05.107483
1051 11:59:05.108022 Set Vref, RX VrefLevel [Byte0]: 55
1052 11:59:05.110938 [Byte1]: 55
1053 11:59:05.115381
1054 11:59:05.115889 Set Vref, RX VrefLevel [Byte0]: 56
1055 11:59:05.118351 [Byte1]: 56
1056 11:59:05.122548
1057 11:59:05.122962 Set Vref, RX VrefLevel [Byte0]: 57
1058 11:59:05.125746 [Byte1]: 57
1059 11:59:05.130589
1060 11:59:05.130996 Set Vref, RX VrefLevel [Byte0]: 58
1061 11:59:05.133707 [Byte1]: 58
1062 11:59:05.138081
1063 11:59:05.138586 Set Vref, RX VrefLevel [Byte0]: 59
1064 11:59:05.141234 [Byte1]: 59
1065 11:59:05.145173
1066 11:59:05.145622 Set Vref, RX VrefLevel [Byte0]: 60
1067 11:59:05.148566 [Byte1]: 60
1068 11:59:05.152864
1069 11:59:05.153410 Set Vref, RX VrefLevel [Byte0]: 61
1070 11:59:05.156109 [Byte1]: 61
1071 11:59:05.160734
1072 11:59:05.161143 Set Vref, RX VrefLevel [Byte0]: 62
1073 11:59:05.164056 [Byte1]: 62
1074 11:59:05.167898
1075 11:59:05.168386 Set Vref, RX VrefLevel [Byte0]: 63
1076 11:59:05.171763 [Byte1]: 63
1077 11:59:05.175847
1078 11:59:05.176254 Set Vref, RX VrefLevel [Byte0]: 64
1079 11:59:05.178701 [Byte1]: 64
1080 11:59:05.183092
1081 11:59:05.183479 Set Vref, RX VrefLevel [Byte0]: 65
1082 11:59:05.186428 [Byte1]: 65
1083 11:59:05.190568
1084 11:59:05.190940 Set Vref, RX VrefLevel [Byte0]: 66
1085 11:59:05.193827 [Byte1]: 66
1086 11:59:05.198317
1087 11:59:05.198688 Set Vref, RX VrefLevel [Byte0]: 67
1088 11:59:05.201792 [Byte1]: 67
1089 11:59:05.205802
1090 11:59:05.206177 Set Vref, RX VrefLevel [Byte0]: 68
1091 11:59:05.209061 [Byte1]: 68
1092 11:59:05.213234
1093 11:59:05.213633 Set Vref, RX VrefLevel [Byte0]: 69
1094 11:59:05.216785 [Byte1]: 69
1095 11:59:05.220568
1096 11:59:05.220943 Set Vref, RX VrefLevel [Byte0]: 70
1097 11:59:05.224543 [Byte1]: 70
1098 11:59:05.228145
1099 11:59:05.228597 Set Vref, RX VrefLevel [Byte0]: 71
1100 11:59:05.231666 [Byte1]: 71
1101 11:59:05.235908
1102 11:59:05.236397 Set Vref, RX VrefLevel [Byte0]: 72
1103 11:59:05.239141 [Byte1]: 72
1104 11:59:05.243681
1105 11:59:05.244051 Set Vref, RX VrefLevel [Byte0]: 73
1106 11:59:05.246798 [Byte1]: 73
1107 11:59:05.250884
1108 11:59:05.251304 Set Vref, RX VrefLevel [Byte0]: 74
1109 11:59:05.254125 [Byte1]: 74
1110 11:59:05.258569
1111 11:59:05.259036 Set Vref, RX VrefLevel [Byte0]: 75
1112 11:59:05.261652 [Byte1]: 75
1113 11:59:05.266183
1114 11:59:05.266539 Set Vref, RX VrefLevel [Byte0]: 76
1115 11:59:05.269233 [Byte1]: 76
1116 11:59:05.273770
1117 11:59:05.274157 Set Vref, RX VrefLevel [Byte0]: 77
1118 11:59:05.277203 [Byte1]: 77
1119 11:59:05.280884
1120 11:59:05.281257 Set Vref, RX VrefLevel [Byte0]: 78
1121 11:59:05.284630 [Byte1]: 78
1122 11:59:05.288734
1123 11:59:05.289207 Set Vref, RX VrefLevel [Byte0]: 79
1124 11:59:05.291809 [Byte1]: 79
1125 11:59:05.296326
1126 11:59:05.296830 Final RX Vref Byte 0 = 53 to rank0
1127 11:59:05.299622 Final RX Vref Byte 1 = 53 to rank0
1128 11:59:05.303420 Final RX Vref Byte 0 = 53 to rank1
1129 11:59:05.306279 Final RX Vref Byte 1 = 53 to rank1==
1130 11:59:05.310245 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 11:59:05.316594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 11:59:05.317073 ==
1133 11:59:05.317374 DQS Delay:
1134 11:59:05.317699 DQS0 = 0, DQS1 = 0
1135 11:59:05.319564 DQM Delay:
1136 11:59:05.319935 DQM0 = 91, DQM1 = 85
1137 11:59:05.323686 DQ Delay:
1138 11:59:05.326456 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1139 11:59:05.329644 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1140 11:59:05.330064 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1141 11:59:05.336320 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1142 11:59:05.336800
1143 11:59:05.337099
1144 11:59:05.342822 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1145 11:59:05.346262 CH0 RK0: MR19=606, MR18=4B41
1146 11:59:05.353639 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1147 11:59:05.354115
1148 11:59:05.356125 ----->DramcWriteLeveling(PI) begin...
1149 11:59:05.356533 ==
1150 11:59:05.359691 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 11:59:05.363313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 11:59:05.363925 ==
1153 11:59:05.366392 Write leveling (Byte 0): 31 => 31
1154 11:59:05.369516 Write leveling (Byte 1): 28 => 28
1155 11:59:05.372782 DramcWriteLeveling(PI) end<-----
1156 11:59:05.373159
1157 11:59:05.373657 ==
1158 11:59:05.417236 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 11:59:05.418169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 11:59:05.418531 ==
1161 11:59:05.418839 [Gating] SW mode calibration
1162 11:59:05.419134 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 11:59:05.419421 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 11:59:05.419698 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 11:59:05.420031 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 11:59:05.420321 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1167 11:59:05.420592 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:59:05.420859 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:59:05.461320 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:59:05.461909 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:59:05.462253 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:59:05.462559 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:59:05.463201 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:59:05.463520 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:59:05.463810 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:59:05.464091 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:59:05.464367 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:59:05.464636 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:59:05.503244 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:59:05.503784 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:59:05.504120 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:59:05.504425 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1183 11:59:05.504716 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:59:05.505333 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:59:05.505683 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:59:05.505971 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:59:05.506248 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:59:05.508133 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:59:05.511337 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:59:05.514931 0 9 8 | B1->B0 | 2b2b 2727 | 1 0 | (1 1) (0 0)
1191 11:59:05.517743 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 11:59:05.521255 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 11:59:05.528157 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 11:59:05.531907 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 11:59:05.534653 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 11:59:05.541662 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 11:59:05.545726 0 10 4 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
1198 11:59:05.548920 0 10 8 | B1->B0 | 2525 2525 | 0 0 | (1 0) (0 0)
1199 11:59:05.552407 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1200 11:59:05.560136 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:59:05.563433 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:59:05.566764 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:59:05.569813 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:59:05.577690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:59:05.580943 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1206 11:59:05.584385 0 11 8 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
1207 11:59:05.587598 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:59:05.594267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 11:59:05.597698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 11:59:05.600881 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 11:59:05.607619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 11:59:05.610972 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 11:59:05.614386 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 11:59:05.620502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1215 11:59:05.624450 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1216 11:59:05.627513 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:59:05.634209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:59:05.637615 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:59:05.641010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:59:05.647084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:59:05.650767 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:59:05.654120 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:59:05.657536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:59:05.664278 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 11:59:05.668027 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 11:59:05.670935 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 11:59:05.677657 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 11:59:05.680545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 11:59:05.684149 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 11:59:05.691015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1231 11:59:05.694367 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 11:59:05.697666 Total UI for P1: 0, mck2ui 16
1233 11:59:05.700836 best dqsien dly found for B0: ( 0, 14, 8)
1234 11:59:05.704157 Total UI for P1: 0, mck2ui 16
1235 11:59:05.708540 best dqsien dly found for B1: ( 0, 14, 8)
1236 11:59:05.710679 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1237 11:59:05.714506 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1238 11:59:05.715032
1239 11:59:05.718203 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1240 11:59:05.720776 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1241 11:59:05.724576 [Gating] SW calibration Done
1242 11:59:05.725099 ==
1243 11:59:05.727706 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 11:59:05.731156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 11:59:05.731576 ==
1246 11:59:05.734610 RX Vref Scan: 0
1247 11:59:05.735025
1248 11:59:05.737770 RX Vref 0 -> 0, step: 1
1249 11:59:05.738287
1250 11:59:05.738624 RX Delay -130 -> 252, step: 16
1251 11:59:05.744351 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1252 11:59:05.747625 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1253 11:59:05.750867 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1254 11:59:05.754352 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1255 11:59:05.757975 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1256 11:59:05.764360 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1257 11:59:05.768257 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1258 11:59:05.770709 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1259 11:59:05.774553 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1260 11:59:05.777677 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1261 11:59:05.785046 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1262 11:59:05.788162 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1263 11:59:05.790477 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1264 11:59:05.794339 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1265 11:59:05.797626 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1266 11:59:05.804480 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1267 11:59:05.805000 ==
1268 11:59:05.807805 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 11:59:05.810926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 11:59:05.811498 ==
1271 11:59:05.811845 DQS Delay:
1272 11:59:05.814229 DQS0 = 0, DQS1 = 0
1273 11:59:05.814650 DQM Delay:
1274 11:59:05.817611 DQM0 = 94, DQM1 = 84
1275 11:59:05.818140 DQ Delay:
1276 11:59:05.821114 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1277 11:59:05.824633 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =101
1278 11:59:05.827921 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1279 11:59:05.831250 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1280 11:59:05.831671
1281 11:59:05.832003
1282 11:59:05.832308 ==
1283 11:59:05.834273 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 11:59:05.837753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 11:59:05.838282 ==
1286 11:59:05.841145
1287 11:59:05.841708
1288 11:59:05.842057 TX Vref Scan disable
1289 11:59:05.844502 == TX Byte 0 ==
1290 11:59:05.847518 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1291 11:59:05.850925 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1292 11:59:05.854390 == TX Byte 1 ==
1293 11:59:05.857803 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1294 11:59:05.861406 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1295 11:59:05.862086 ==
1296 11:59:05.864749 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 11:59:05.871546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 11:59:05.872070 ==
1299 11:59:05.883452 TX Vref=22, minBit 9, minWin=27, winSum=449
1300 11:59:05.886336 TX Vref=24, minBit 8, minWin=27, winSum=450
1301 11:59:05.890115 TX Vref=26, minBit 1, minWin=28, winSum=455
1302 11:59:05.893113 TX Vref=28, minBit 5, minWin=28, winSum=459
1303 11:59:05.896712 TX Vref=30, minBit 8, minWin=28, winSum=460
1304 11:59:05.899957 TX Vref=32, minBit 7, minWin=28, winSum=458
1305 11:59:05.906523 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1306 11:59:05.907043
1307 11:59:05.910237 Final TX Range 1 Vref 30
1308 11:59:05.910757
1309 11:59:05.911087 ==
1310 11:59:05.913931 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 11:59:05.916642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 11:59:05.917172 ==
1313 11:59:05.917502
1314 11:59:05.919983
1315 11:59:05.920514 TX Vref Scan disable
1316 11:59:05.923216 == TX Byte 0 ==
1317 11:59:05.927232 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1318 11:59:05.930074 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1319 11:59:05.933097 == TX Byte 1 ==
1320 11:59:05.936764 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1321 11:59:05.939663 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1322 11:59:05.943399
1323 11:59:05.943810 [DATLAT]
1324 11:59:05.944136 Freq=800, CH0 RK1
1325 11:59:05.944443
1326 11:59:05.946390 DATLAT Default: 0xa
1327 11:59:05.946799 0, 0xFFFF, sum = 0
1328 11:59:05.950193 1, 0xFFFF, sum = 0
1329 11:59:05.950612 2, 0xFFFF, sum = 0
1330 11:59:05.953128 3, 0xFFFF, sum = 0
1331 11:59:05.953548 4, 0xFFFF, sum = 0
1332 11:59:05.956982 5, 0xFFFF, sum = 0
1333 11:59:05.957504 6, 0xFFFF, sum = 0
1334 11:59:05.960109 7, 0xFFFF, sum = 0
1335 11:59:05.960621 8, 0xFFFF, sum = 0
1336 11:59:05.963541 9, 0x0, sum = 1
1337 11:59:05.964052 10, 0x0, sum = 2
1338 11:59:05.967184 11, 0x0, sum = 3
1339 11:59:05.967723 12, 0x0, sum = 4
1340 11:59:05.970115 best_step = 10
1341 11:59:05.970526
1342 11:59:05.970860 ==
1343 11:59:05.973842 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 11:59:05.976658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 11:59:05.977077 ==
1346 11:59:05.980207 RX Vref Scan: 0
1347 11:59:05.980718
1348 11:59:05.981043 RX Vref 0 -> 0, step: 1
1349 11:59:05.981474
1350 11:59:05.983956 RX Delay -95 -> 252, step: 8
1351 11:59:05.989879 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1352 11:59:05.993469 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1353 11:59:05.997104 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1354 11:59:05.999912 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1355 11:59:06.003833 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1356 11:59:06.010214 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1357 11:59:06.013876 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1358 11:59:06.016989 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1359 11:59:06.020084 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1360 11:59:06.023474 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1361 11:59:06.030437 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1362 11:59:06.033678 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1363 11:59:06.036972 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1364 11:59:06.040558 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1365 11:59:06.043754 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1366 11:59:06.050605 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1367 11:59:06.051104 ==
1368 11:59:06.053572 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 11:59:06.057504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 11:59:06.058061 ==
1371 11:59:06.058400 DQS Delay:
1372 11:59:06.060205 DQS0 = 0, DQS1 = 0
1373 11:59:06.060620 DQM Delay:
1374 11:59:06.064068 DQM0 = 92, DQM1 = 83
1375 11:59:06.064578 DQ Delay:
1376 11:59:06.066940 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1377 11:59:06.070673 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1378 11:59:06.074145 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1379 11:59:06.077484 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1380 11:59:06.077949
1381 11:59:06.078279
1382 11:59:06.084114 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1383 11:59:06.087034 CH0 RK1: MR19=606, MR18=3F10
1384 11:59:06.093675 CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63
1385 11:59:06.097655 [RxdqsGatingPostProcess] freq 800
1386 11:59:06.100470 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1387 11:59:06.103990 Pre-setting of DQS Precalculation
1388 11:59:06.110771 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1389 11:59:06.111296 ==
1390 11:59:06.114074 Dram Type= 6, Freq= 0, CH_1, rank 0
1391 11:59:06.118014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 11:59:06.118532 ==
1393 11:59:06.124073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 11:59:06.131184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 11:59:06.138632 [CA 0] Center 36 (6~67) winsize 62
1396 11:59:06.141772 [CA 1] Center 36 (6~67) winsize 62
1397 11:59:06.145070 [CA 2] Center 34 (4~65) winsize 62
1398 11:59:06.148139 [CA 3] Center 34 (4~65) winsize 62
1399 11:59:06.151698 [CA 4] Center 34 (4~65) winsize 62
1400 11:59:06.154950 [CA 5] Center 34 (4~64) winsize 61
1401 11:59:06.155371
1402 11:59:06.159007 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1403 11:59:06.159520
1404 11:59:06.162196 [CATrainingPosCal] consider 1 rank data
1405 11:59:06.165363 u2DelayCellTimex100 = 270/100 ps
1406 11:59:06.168955 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1407 11:59:06.171862 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 11:59:06.175330 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 11:59:06.182324 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 11:59:06.185453 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 11:59:06.188597 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1412 11:59:06.189106
1413 11:59:06.192313 CA PerBit enable=1, Macro0, CA PI delay=34
1414 11:59:06.192890
1415 11:59:06.194919 [CBTSetCACLKResult] CA Dly = 34
1416 11:59:06.195354 CS Dly: 5 (0~36)
1417 11:59:06.195684 ==
1418 11:59:06.198238 Dram Type= 6, Freq= 0, CH_1, rank 1
1419 11:59:06.205254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 11:59:06.205805 ==
1421 11:59:06.208659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 11:59:06.215840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 11:59:06.224993 [CA 0] Center 36 (6~67) winsize 62
1424 11:59:06.228271 [CA 1] Center 37 (6~68) winsize 63
1425 11:59:06.232093 [CA 2] Center 35 (5~66) winsize 62
1426 11:59:06.236903 [CA 3] Center 34 (4~65) winsize 62
1427 11:59:06.239590 [CA 4] Center 35 (5~66) winsize 62
1428 11:59:06.240005 [CA 5] Center 35 (5~65) winsize 61
1429 11:59:06.243902
1430 11:59:06.244317 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1431 11:59:06.247489
1432 11:59:06.247957 [CATrainingPosCal] consider 2 rank data
1433 11:59:06.250887 u2DelayCellTimex100 = 270/100 ps
1434 11:59:06.254246 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 11:59:06.260615 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 11:59:06.264461 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1437 11:59:06.267768 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 11:59:06.270894 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1439 11:59:06.274270 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
1440 11:59:06.274805
1441 11:59:06.277693 CA PerBit enable=1, Macro0, CA PI delay=34
1442 11:59:06.278156
1443 11:59:06.281225 [CBTSetCACLKResult] CA Dly = 34
1444 11:59:06.281797 CS Dly: 6 (0~38)
1445 11:59:06.284036
1446 11:59:06.287923 ----->DramcWriteLeveling(PI) begin...
1447 11:59:06.288453 ==
1448 11:59:06.291062 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 11:59:06.294258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 11:59:06.294813 ==
1451 11:59:06.297071 Write leveling (Byte 0): 27 => 27
1452 11:59:06.300225 Write leveling (Byte 1): 27 => 27
1453 11:59:06.304547 DramcWriteLeveling(PI) end<-----
1454 11:59:06.305066
1455 11:59:06.305402 ==
1456 11:59:06.307325 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 11:59:06.310699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 11:59:06.311120 ==
1459 11:59:06.313601 [Gating] SW mode calibration
1460 11:59:06.320658 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1461 11:59:06.327799 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1462 11:59:06.330775 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1463 11:59:06.334171 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1464 11:59:06.340848 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:59:06.344024 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:59:06.347404 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:59:06.350658 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:59:06.357770 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:59:06.360946 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:59:06.364441 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:59:06.370538 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:59:06.373781 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:59:06.377478 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:59:06.383801 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:59:06.387571 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:59:06.391091 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:59:06.397094 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:59:06.400757 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1479 11:59:06.404213 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1480 11:59:06.411247 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:59:06.414304 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:59:06.417568 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:59:06.424024 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:59:06.427551 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:59:06.431078 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:59:06.437552 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:59:06.440625 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1488 11:59:06.443936 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1489 11:59:06.447484 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 11:59:06.454491 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 11:59:06.457604 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 11:59:06.460972 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 11:59:06.467921 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 11:59:06.471112 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 11:59:06.474538 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 0)
1496 11:59:06.481227 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1497 11:59:06.484040 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:59:06.487507 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:59:06.494814 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:59:06.497759 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:59:06.501675 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:59:06.504594 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:59:06.511513 0 11 4 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
1504 11:59:06.514516 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1505 11:59:06.518113 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 11:59:06.524673 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 11:59:06.528088 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 11:59:06.531169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 11:59:06.538212 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 11:59:06.541644 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 11:59:06.544814 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1512 11:59:06.550972 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:59:06.554708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:59:06.557929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:59:06.564784 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:59:06.567591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:59:06.571290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:59:06.578225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:59:06.581060 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:59:06.584447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:59:06.588301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:59:06.594700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 11:59:06.597893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 11:59:06.601205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 11:59:06.608630 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 11:59:06.611466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 11:59:06.614509 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1528 11:59:06.618076 Total UI for P1: 0, mck2ui 16
1529 11:59:06.621374 best dqsien dly found for B1: ( 0, 14, 2)
1530 11:59:06.628655 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 11:59:06.629209 Total UI for P1: 0, mck2ui 16
1532 11:59:06.634730 best dqsien dly found for B0: ( 0, 14, 4)
1533 11:59:06.638439 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1534 11:59:06.641526 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1535 11:59:06.641983
1536 11:59:06.644687 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1537 11:59:06.648676 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1538 11:59:06.651785 [Gating] SW calibration Done
1539 11:59:06.652311 ==
1540 11:59:06.654626 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 11:59:06.658218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 11:59:06.658641 ==
1543 11:59:06.661649 RX Vref Scan: 0
1544 11:59:06.662068
1545 11:59:06.662398 RX Vref 0 -> 0, step: 1
1546 11:59:06.662704
1547 11:59:06.664905 RX Delay -130 -> 252, step: 16
1548 11:59:06.668611 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1549 11:59:06.672122 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1550 11:59:06.678126 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1551 11:59:06.681785 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1552 11:59:06.685143 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1553 11:59:06.688625 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1554 11:59:06.692107 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1555 11:59:06.698240 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1556 11:59:06.701425 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1557 11:59:06.705494 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1558 11:59:06.708548 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1559 11:59:06.711629 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1560 11:59:06.718411 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1561 11:59:06.722169 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1562 11:59:06.725402 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1563 11:59:06.728658 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1564 11:59:06.729077 ==
1565 11:59:06.732098 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 11:59:06.735491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 11:59:06.738368 ==
1568 11:59:06.738785 DQS Delay:
1569 11:59:06.739178 DQS0 = 0, DQS1 = 0
1570 11:59:06.742464 DQM Delay:
1571 11:59:06.742970 DQM0 = 94, DQM1 = 91
1572 11:59:06.745333 DQ Delay:
1573 11:59:06.748509 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1574 11:59:06.752150 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1575 11:59:06.755070 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1576 11:59:06.758497 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1577 11:59:06.759008
1578 11:59:06.759337
1579 11:59:06.759639 ==
1580 11:59:06.762131 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 11:59:06.764860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 11:59:06.765275 ==
1583 11:59:06.765628
1584 11:59:06.765939
1585 11:59:06.768654 TX Vref Scan disable
1586 11:59:06.772009 == TX Byte 0 ==
1587 11:59:06.775675 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1588 11:59:06.778817 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1589 11:59:06.779325 == TX Byte 1 ==
1590 11:59:06.785303 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1591 11:59:06.789080 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1592 11:59:06.789499 ==
1593 11:59:06.792933 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:59:06.796093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:59:06.796542 ==
1596 11:59:06.809166 TX Vref=22, minBit 1, minWin=26, winSum=437
1597 11:59:06.812803 TX Vref=24, minBit 0, minWin=27, winSum=441
1598 11:59:06.816417 TX Vref=26, minBit 0, minWin=27, winSum=444
1599 11:59:06.819499 TX Vref=28, minBit 2, minWin=27, winSum=451
1600 11:59:06.822384 TX Vref=30, minBit 1, minWin=27, winSum=450
1601 11:59:06.825796 TX Vref=32, minBit 1, minWin=27, winSum=447
1602 11:59:06.832129 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1603 11:59:06.832552
1604 11:59:06.836133 Final TX Range 1 Vref 28
1605 11:59:06.836667
1606 11:59:06.837044 ==
1607 11:59:06.838892 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 11:59:06.842662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 11:59:06.843183 ==
1610 11:59:06.843516
1611 11:59:06.845888
1612 11:59:06.846333 TX Vref Scan disable
1613 11:59:06.848792 == TX Byte 0 ==
1614 11:59:06.852820 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1615 11:59:06.855864 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1616 11:59:06.859586 == TX Byte 1 ==
1617 11:59:06.862255 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1618 11:59:06.866118 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1619 11:59:06.866532
1620 11:59:06.869336 [DATLAT]
1621 11:59:06.869898 Freq=800, CH1 RK0
1622 11:59:06.870237
1623 11:59:06.872907 DATLAT Default: 0xa
1624 11:59:06.873320 0, 0xFFFF, sum = 0
1625 11:59:06.875994 1, 0xFFFF, sum = 0
1626 11:59:06.876413 2, 0xFFFF, sum = 0
1627 11:59:06.879024 3, 0xFFFF, sum = 0
1628 11:59:06.879443 4, 0xFFFF, sum = 0
1629 11:59:06.882172 5, 0xFFFF, sum = 0
1630 11:59:06.882593 6, 0xFFFF, sum = 0
1631 11:59:06.886067 7, 0xFFFF, sum = 0
1632 11:59:06.886484 8, 0xFFFF, sum = 0
1633 11:59:06.889096 9, 0x0, sum = 1
1634 11:59:06.889513 10, 0x0, sum = 2
1635 11:59:06.892822 11, 0x0, sum = 3
1636 11:59:06.893241 12, 0x0, sum = 4
1637 11:59:06.896046 best_step = 10
1638 11:59:06.896455
1639 11:59:06.896777 ==
1640 11:59:06.899358 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:59:06.903028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:59:06.903539 ==
1643 11:59:06.905534 RX Vref Scan: 1
1644 11:59:06.905987
1645 11:59:06.906326 Set Vref Range= 32 -> 127
1646 11:59:06.906629
1647 11:59:06.909457 RX Vref 32 -> 127, step: 1
1648 11:59:06.910023
1649 11:59:06.912401 RX Delay -79 -> 252, step: 8
1650 11:59:06.912813
1651 11:59:06.916013 Set Vref, RX VrefLevel [Byte0]: 32
1652 11:59:06.919393 [Byte1]: 32
1653 11:59:06.919905
1654 11:59:06.922941 Set Vref, RX VrefLevel [Byte0]: 33
1655 11:59:06.925472 [Byte1]: 33
1656 11:59:06.929124
1657 11:59:06.929534 Set Vref, RX VrefLevel [Byte0]: 34
1658 11:59:06.932661 [Byte1]: 34
1659 11:59:06.937089
1660 11:59:06.937626 Set Vref, RX VrefLevel [Byte0]: 35
1661 11:59:06.939981 [Byte1]: 35
1662 11:59:06.944973
1663 11:59:06.945477 Set Vref, RX VrefLevel [Byte0]: 36
1664 11:59:06.948185 [Byte1]: 36
1665 11:59:06.952003
1666 11:59:06.952582 Set Vref, RX VrefLevel [Byte0]: 37
1667 11:59:06.955000 [Byte1]: 37
1668 11:59:06.959326
1669 11:59:06.959847 Set Vref, RX VrefLevel [Byte0]: 38
1670 11:59:06.962600 [Byte1]: 38
1671 11:59:06.967134
1672 11:59:06.967658 Set Vref, RX VrefLevel [Byte0]: 39
1673 11:59:06.970407 [Byte1]: 39
1674 11:59:06.974701
1675 11:59:06.975122 Set Vref, RX VrefLevel [Byte0]: 40
1676 11:59:06.978033 [Byte1]: 40
1677 11:59:06.982053
1678 11:59:06.982570 Set Vref, RX VrefLevel [Byte0]: 41
1679 11:59:06.985334 [Byte1]: 41
1680 11:59:06.989564
1681 11:59:06.990140 Set Vref, RX VrefLevel [Byte0]: 42
1682 11:59:06.993201 [Byte1]: 42
1683 11:59:06.997428
1684 11:59:06.998004 Set Vref, RX VrefLevel [Byte0]: 43
1685 11:59:07.000570 [Byte1]: 43
1686 11:59:07.005119
1687 11:59:07.005681 Set Vref, RX VrefLevel [Byte0]: 44
1688 11:59:07.007911 [Byte1]: 44
1689 11:59:07.019610
1690 11:59:07.019704 Set Vref, RX VrefLevel [Byte0]: 45
1691 11:59:07.019772 [Byte1]: 45
1692 11:59:07.019833
1693 11:59:07.019889 Set Vref, RX VrefLevel [Byte0]: 46
1694 11:59:07.022632 [Byte1]: 46
1695 11:59:07.027410
1696 11:59:07.027575 Set Vref, RX VrefLevel [Byte0]: 47
1697 11:59:07.030252 [Byte1]: 47
1698 11:59:07.034506
1699 11:59:07.034659 Set Vref, RX VrefLevel [Byte0]: 48
1700 11:59:07.037917 [Byte1]: 48
1701 11:59:07.041938
1702 11:59:07.042132 Set Vref, RX VrefLevel [Byte0]: 49
1703 11:59:07.045423 [Byte1]: 49
1704 11:59:07.049797
1705 11:59:07.049982 Set Vref, RX VrefLevel [Byte0]: 50
1706 11:59:07.053178 [Byte1]: 50
1707 11:59:07.057754
1708 11:59:07.057973 Set Vref, RX VrefLevel [Byte0]: 51
1709 11:59:07.060864 [Byte1]: 51
1710 11:59:07.065569
1711 11:59:07.065951 Set Vref, RX VrefLevel [Byte0]: 52
1712 11:59:07.068118 [Byte1]: 52
1713 11:59:07.072523
1714 11:59:07.072917 Set Vref, RX VrefLevel [Byte0]: 53
1715 11:59:07.076105 [Byte1]: 53
1716 11:59:07.080528
1717 11:59:07.081088 Set Vref, RX VrefLevel [Byte0]: 54
1718 11:59:07.083150 [Byte1]: 54
1719 11:59:07.087723
1720 11:59:07.088139 Set Vref, RX VrefLevel [Byte0]: 55
1721 11:59:07.091159 [Byte1]: 55
1722 11:59:07.095578
1723 11:59:07.096096 Set Vref, RX VrefLevel [Byte0]: 56
1724 11:59:07.098564 [Byte1]: 56
1725 11:59:07.102865
1726 11:59:07.103371 Set Vref, RX VrefLevel [Byte0]: 57
1727 11:59:07.105970 [Byte1]: 57
1728 11:59:07.110700
1729 11:59:07.111219 Set Vref, RX VrefLevel [Byte0]: 58
1730 11:59:07.113770 [Byte1]: 58
1731 11:59:07.118093
1732 11:59:07.121186 Set Vref, RX VrefLevel [Byte0]: 59
1733 11:59:07.124610 [Byte1]: 59
1734 11:59:07.125134
1735 11:59:07.127922 Set Vref, RX VrefLevel [Byte0]: 60
1736 11:59:07.131128 [Byte1]: 60
1737 11:59:07.131551
1738 11:59:07.134151 Set Vref, RX VrefLevel [Byte0]: 61
1739 11:59:07.138499 [Byte1]: 61
1740 11:59:07.139014
1741 11:59:07.141061 Set Vref, RX VrefLevel [Byte0]: 62
1742 11:59:07.144308 [Byte1]: 62
1743 11:59:07.148381
1744 11:59:07.148901 Set Vref, RX VrefLevel [Byte0]: 63
1745 11:59:07.151256 [Byte1]: 63
1746 11:59:07.155566
1747 11:59:07.155978 Set Vref, RX VrefLevel [Byte0]: 64
1748 11:59:07.158944 [Byte1]: 64
1749 11:59:07.163453
1750 11:59:07.163969 Set Vref, RX VrefLevel [Byte0]: 65
1751 11:59:07.166319 [Byte1]: 65
1752 11:59:07.170656
1753 11:59:07.171175 Set Vref, RX VrefLevel [Byte0]: 66
1754 11:59:07.173775 [Byte1]: 66
1755 11:59:07.178074
1756 11:59:07.178593 Set Vref, RX VrefLevel [Byte0]: 67
1757 11:59:07.181217 [Byte1]: 67
1758 11:59:07.185854
1759 11:59:07.186391 Set Vref, RX VrefLevel [Byte0]: 68
1760 11:59:07.189198 [Byte1]: 68
1761 11:59:07.193501
1762 11:59:07.194094 Set Vref, RX VrefLevel [Byte0]: 69
1763 11:59:07.196746 [Byte1]: 69
1764 11:59:07.200536
1765 11:59:07.200955 Set Vref, RX VrefLevel [Byte0]: 70
1766 11:59:07.204117 [Byte1]: 70
1767 11:59:07.208736
1768 11:59:07.209256 Set Vref, RX VrefLevel [Byte0]: 71
1769 11:59:07.211805 [Byte1]: 71
1770 11:59:07.216378
1771 11:59:07.216897 Set Vref, RX VrefLevel [Byte0]: 72
1772 11:59:07.219408 [Byte1]: 72
1773 11:59:07.223496
1774 11:59:07.224015 Final RX Vref Byte 0 = 59 to rank0
1775 11:59:07.227012 Final RX Vref Byte 1 = 58 to rank0
1776 11:59:07.230379 Final RX Vref Byte 0 = 59 to rank1
1777 11:59:07.233815 Final RX Vref Byte 1 = 58 to rank1==
1778 11:59:07.237397 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 11:59:07.240278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 11:59:07.244226 ==
1781 11:59:07.244737 DQS Delay:
1782 11:59:07.245065 DQS0 = 0, DQS1 = 0
1783 11:59:07.247093 DQM Delay:
1784 11:59:07.247508 DQM0 = 95, DQM1 = 89
1785 11:59:07.250430 DQ Delay:
1786 11:59:07.253696 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1787 11:59:07.254203 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =96
1788 11:59:07.257332 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1789 11:59:07.264175 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1790 11:59:07.264693
1791 11:59:07.265022
1792 11:59:07.270494 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1793 11:59:07.273739 CH1 RK0: MR19=606, MR18=2B47
1794 11:59:07.280399 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1795 11:59:07.280912
1796 11:59:07.283573 ----->DramcWriteLeveling(PI) begin...
1797 11:59:07.284179 ==
1798 11:59:07.286758 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 11:59:07.290201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 11:59:07.290616 ==
1801 11:59:07.293346 Write leveling (Byte 0): 27 => 27
1802 11:59:07.296700 Write leveling (Byte 1): 29 => 29
1803 11:59:07.300176 DramcWriteLeveling(PI) end<-----
1804 11:59:07.300587
1805 11:59:07.300947 ==
1806 11:59:07.303290 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 11:59:07.307419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 11:59:07.307939 ==
1809 11:59:07.310525 [Gating] SW mode calibration
1810 11:59:07.317198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 11:59:07.323719 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 11:59:07.326707 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 11:59:07.330099 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1814 11:59:07.337454 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1815 11:59:07.340096 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:59:07.344183 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:59:07.350498 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:59:07.353564 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:59:07.356920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:59:07.363712 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:59:07.367165 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:59:07.370532 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:59:07.377326 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:59:07.380451 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:59:07.384523 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:59:07.387550 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:59:07.394500 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:59:07.397409 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1829 11:59:07.400443 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1830 11:59:07.407278 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:59:07.410494 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:59:07.414178 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:59:07.420936 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:59:07.424086 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:59:07.427877 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:59:07.434019 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:59:07.437383 0 9 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
1838 11:59:07.440440 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1839 11:59:07.447250 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:59:07.450416 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:59:07.454112 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:59:07.457193 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:59:07.463910 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:59:07.466942 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 11:59:07.470917 0 10 4 | B1->B0 | 2b2b 3131 | 1 0 | (1 0) (0 1)
1846 11:59:07.477291 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:59:07.480499 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:59:07.484203 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:59:07.490795 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:59:07.493750 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:59:07.496852 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:59:07.503883 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1853 11:59:07.506850 0 11 4 | B1->B0 | 3f3f 2f2f | 0 0 | (0 0) (0 0)
1854 11:59:07.510873 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1855 11:59:07.517379 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:59:07.520749 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:59:07.524138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:59:07.530609 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:59:07.533573 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 11:59:07.537663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:59:07.544088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1862 11:59:07.547653 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:59:07.550272 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:59:07.557318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:59:07.560765 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:59:07.564194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:59:07.567533 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:59:07.573688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:59:07.577110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:59:07.580161 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:59:07.586894 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:59:07.590249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:59:07.593476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:59:07.600497 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:59:07.604040 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:59:07.607105 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:59:07.613977 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1878 11:59:07.616838 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 11:59:07.620629 Total UI for P1: 0, mck2ui 16
1880 11:59:07.623781 best dqsien dly found for B0: ( 0, 14, 4)
1881 11:59:07.626882 Total UI for P1: 0, mck2ui 16
1882 11:59:07.630192 best dqsien dly found for B1: ( 0, 14, 4)
1883 11:59:07.633568 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1884 11:59:07.636725 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1885 11:59:07.637137
1886 11:59:07.640666 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1887 11:59:07.643679 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 11:59:07.646899 [Gating] SW calibration Done
1889 11:59:07.647310 ==
1890 11:59:07.650087 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 11:59:07.653975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 11:59:07.654389 ==
1893 11:59:07.657027 RX Vref Scan: 0
1894 11:59:07.657442
1895 11:59:07.660324 RX Vref 0 -> 0, step: 1
1896 11:59:07.660734
1897 11:59:07.661055 RX Delay -130 -> 252, step: 16
1898 11:59:07.667005 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1899 11:59:07.670440 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1900 11:59:07.673869 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1901 11:59:07.677194 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1902 11:59:07.680535 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1903 11:59:07.687114 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1904 11:59:07.690311 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1905 11:59:07.693987 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1906 11:59:07.697188 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1907 11:59:07.700476 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1908 11:59:07.707038 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1909 11:59:07.710289 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1910 11:59:07.713622 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1911 11:59:07.717249 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1912 11:59:07.720124 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1913 11:59:07.727083 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1914 11:59:07.727498 ==
1915 11:59:07.730904 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 11:59:07.733543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 11:59:07.733993 ==
1918 11:59:07.734326 DQS Delay:
1919 11:59:07.737278 DQS0 = 0, DQS1 = 0
1920 11:59:07.737723 DQM Delay:
1921 11:59:07.740598 DQM0 = 94, DQM1 = 90
1922 11:59:07.741128 DQ Delay:
1923 11:59:07.743660 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1924 11:59:07.746741 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1925 11:59:07.750352 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1926 11:59:07.753505 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1927 11:59:07.753946
1928 11:59:07.754267
1929 11:59:07.754564 ==
1930 11:59:07.757197 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 11:59:07.760707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 11:59:07.763621 ==
1933 11:59:07.764129
1934 11:59:07.764452
1935 11:59:07.764749 TX Vref Scan disable
1936 11:59:07.767164 == TX Byte 0 ==
1937 11:59:07.770523 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 11:59:07.774169 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 11:59:07.776762 == TX Byte 1 ==
1940 11:59:07.779803 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 11:59:07.783342 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 11:59:07.786413 ==
1943 11:59:07.789997 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 11:59:07.793285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 11:59:07.793735 ==
1946 11:59:07.805812 TX Vref=22, minBit 1, minWin=26, winSum=442
1947 11:59:07.809365 TX Vref=24, minBit 0, minWin=27, winSum=447
1948 11:59:07.812715 TX Vref=26, minBit 2, minWin=27, winSum=449
1949 11:59:07.815848 TX Vref=28, minBit 2, minWin=27, winSum=451
1950 11:59:07.819871 TX Vref=30, minBit 2, minWin=27, winSum=451
1951 11:59:07.822453 TX Vref=32, minBit 2, minWin=27, winSum=451
1952 11:59:07.829458 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1953 11:59:07.830012
1954 11:59:07.832839 Final TX Range 1 Vref 28
1955 11:59:07.833286
1956 11:59:07.833667 ==
1957 11:59:07.836161 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 11:59:07.839582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 11:59:07.840149 ==
1960 11:59:07.840494
1961 11:59:07.840803
1962 11:59:07.842673 TX Vref Scan disable
1963 11:59:07.846037 == TX Byte 0 ==
1964 11:59:07.849629 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1965 11:59:07.852688 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1966 11:59:07.855963 == TX Byte 1 ==
1967 11:59:07.859443 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 11:59:07.862757 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 11:59:07.863267
1970 11:59:07.866403 [DATLAT]
1971 11:59:07.866931 Freq=800, CH1 RK1
1972 11:59:07.867348
1973 11:59:07.869672 DATLAT Default: 0xa
1974 11:59:07.870186 0, 0xFFFF, sum = 0
1975 11:59:07.872820 1, 0xFFFF, sum = 0
1976 11:59:07.873338 2, 0xFFFF, sum = 0
1977 11:59:07.876543 3, 0xFFFF, sum = 0
1978 11:59:07.877059 4, 0xFFFF, sum = 0
1979 11:59:07.879730 5, 0xFFFF, sum = 0
1980 11:59:07.880307 6, 0xFFFF, sum = 0
1981 11:59:07.882553 7, 0xFFFF, sum = 0
1982 11:59:07.882974 8, 0xFFFF, sum = 0
1983 11:59:07.886366 9, 0x0, sum = 1
1984 11:59:07.886911 10, 0x0, sum = 2
1985 11:59:07.889039 11, 0x0, sum = 3
1986 11:59:07.889532 12, 0x0, sum = 4
1987 11:59:07.892610 best_step = 10
1988 11:59:07.893039
1989 11:59:07.893477 ==
1990 11:59:07.895679 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 11:59:07.899347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 11:59:07.899785 ==
1993 11:59:07.902813 RX Vref Scan: 0
1994 11:59:07.903243
1995 11:59:07.903685 RX Vref 0 -> 0, step: 1
1996 11:59:07.904104
1997 11:59:07.905706 RX Delay -63 -> 252, step: 8
1998 11:59:07.912875 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1999 11:59:07.916347 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2000 11:59:07.919443 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2001 11:59:07.922996 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2002 11:59:07.926273 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2003 11:59:07.929470 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2004 11:59:07.935716 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2005 11:59:07.939240 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2006 11:59:07.942560 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2007 11:59:07.946144 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2008 11:59:07.949156 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2009 11:59:07.953012 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2010 11:59:07.959668 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2011 11:59:07.962672 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2012 11:59:07.966141 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2013 11:59:07.969700 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2014 11:59:07.970117 ==
2015 11:59:07.972911 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 11:59:07.979888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 11:59:07.980304 ==
2018 11:59:07.980632 DQS Delay:
2019 11:59:07.980936 DQS0 = 0, DQS1 = 0
2020 11:59:07.982764 DQM Delay:
2021 11:59:07.983177 DQM0 = 97, DQM1 = 90
2022 11:59:07.986318 DQ Delay:
2023 11:59:07.989078 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2024 11:59:07.992662 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2025 11:59:07.996264 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2026 11:59:07.999481 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2027 11:59:07.999893
2028 11:59:08.000216
2029 11:59:08.006203 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2030 11:59:08.009220 CH1 RK1: MR19=606, MR18=440E
2031 11:59:08.016513 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2032 11:59:08.019844 [RxdqsGatingPostProcess] freq 800
2033 11:59:08.022728 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 11:59:08.026598 Pre-setting of DQS Precalculation
2035 11:59:08.032878 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 11:59:08.039867 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 11:59:08.046046 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 11:59:08.046464
2039 11:59:08.046788
2040 11:59:08.049468 [Calibration Summary] 1600 Mbps
2041 11:59:08.049963 CH 0, Rank 0
2042 11:59:08.053200 SW Impedance : PASS
2043 11:59:08.056174 DUTY Scan : NO K
2044 11:59:08.056612 ZQ Calibration : PASS
2045 11:59:08.059987 Jitter Meter : NO K
2046 11:59:08.060415 CBT Training : PASS
2047 11:59:08.063060 Write leveling : PASS
2048 11:59:08.066776 RX DQS gating : PASS
2049 11:59:08.067190 RX DQ/DQS(RDDQC) : PASS
2050 11:59:08.069892 TX DQ/DQS : PASS
2051 11:59:08.073135 RX DATLAT : PASS
2052 11:59:08.073655 RX DQ/DQS(Engine): PASS
2053 11:59:08.076142 TX OE : NO K
2054 11:59:08.076726 All Pass.
2055 11:59:08.077242
2056 11:59:08.079441 CH 0, Rank 1
2057 11:59:08.080038 SW Impedance : PASS
2058 11:59:08.082970 DUTY Scan : NO K
2059 11:59:08.086136 ZQ Calibration : PASS
2060 11:59:08.086640 Jitter Meter : NO K
2061 11:59:08.089706 CBT Training : PASS
2062 11:59:08.093167 Write leveling : PASS
2063 11:59:08.093735 RX DQS gating : PASS
2064 11:59:08.096408 RX DQ/DQS(RDDQC) : PASS
2065 11:59:08.099809 TX DQ/DQS : PASS
2066 11:59:08.100227 RX DATLAT : PASS
2067 11:59:08.102716 RX DQ/DQS(Engine): PASS
2068 11:59:08.103108 TX OE : NO K
2069 11:59:08.106281 All Pass.
2070 11:59:08.106661
2071 11:59:08.107007 CH 1, Rank 0
2072 11:59:08.109501 SW Impedance : PASS
2073 11:59:08.109836 DUTY Scan : NO K
2074 11:59:08.112578 ZQ Calibration : PASS
2075 11:59:08.115965 Jitter Meter : NO K
2076 11:59:08.116260 CBT Training : PASS
2077 11:59:08.119824 Write leveling : PASS
2078 11:59:08.122536 RX DQS gating : PASS
2079 11:59:08.122828 RX DQ/DQS(RDDQC) : PASS
2080 11:59:08.126302 TX DQ/DQS : PASS
2081 11:59:08.129919 RX DATLAT : PASS
2082 11:59:08.130212 RX DQ/DQS(Engine): PASS
2083 11:59:08.132694 TX OE : NO K
2084 11:59:08.133004 All Pass.
2085 11:59:08.133240
2086 11:59:08.135794 CH 1, Rank 1
2087 11:59:08.136088 SW Impedance : PASS
2088 11:59:08.139638 DUTY Scan : NO K
2089 11:59:08.142956 ZQ Calibration : PASS
2090 11:59:08.143339 Jitter Meter : NO K
2091 11:59:08.146403 CBT Training : PASS
2092 11:59:08.149362 Write leveling : PASS
2093 11:59:08.149686 RX DQS gating : PASS
2094 11:59:08.153171 RX DQ/DQS(RDDQC) : PASS
2095 11:59:08.153464 TX DQ/DQS : PASS
2096 11:59:08.156042 RX DATLAT : PASS
2097 11:59:08.159727 RX DQ/DQS(Engine): PASS
2098 11:59:08.160021 TX OE : NO K
2099 11:59:08.162633 All Pass.
2100 11:59:08.162924
2101 11:59:08.163258 DramC Write-DBI off
2102 11:59:08.166288 PER_BANK_REFRESH: Hybrid Mode
2103 11:59:08.169358 TX_TRACKING: ON
2104 11:59:08.173018 [GetDramInforAfterCalByMRR] Vendor 6.
2105 11:59:08.176357 [GetDramInforAfterCalByMRR] Revision 606.
2106 11:59:08.179411 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 11:59:08.179705 MR0 0x3b3b
2108 11:59:08.179937 MR8 0x5151
2109 11:59:08.182772 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 11:59:08.186663
2111 11:59:08.186953 MR0 0x3b3b
2112 11:59:08.187182 MR8 0x5151
2113 11:59:08.189659 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 11:59:08.189955
2115 11:59:08.199954 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 11:59:08.202981 [FAST_K] Save calibration result to emmc
2117 11:59:08.206273 [FAST_K] Save calibration result to emmc
2118 11:59:08.209952 dram_init: config_dvfs: 1
2119 11:59:08.213416 dramc_set_vcore_voltage set vcore to 662500
2120 11:59:08.216514 Read voltage for 1200, 2
2121 11:59:08.217022 Vio18 = 0
2122 11:59:08.217352 Vcore = 662500
2123 11:59:08.220114 Vdram = 0
2124 11:59:08.220642 Vddq = 0
2125 11:59:08.220982 Vmddr = 0
2126 11:59:08.226502 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 11:59:08.230303 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 11:59:08.233380 MEM_TYPE=3, freq_sel=15
2129 11:59:08.236385 sv_algorithm_assistance_LP4_1600
2130 11:59:08.239738 ============ PULL DRAM RESETB DOWN ============
2131 11:59:08.243985 ========== PULL DRAM RESETB DOWN end =========
2132 11:59:08.249947 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 11:59:08.253698 ===================================
2134 11:59:08.254116 LPDDR4 DRAM CONFIGURATION
2135 11:59:08.257163 ===================================
2136 11:59:08.260475 EX_ROW_EN[0] = 0x0
2137 11:59:08.260985 EX_ROW_EN[1] = 0x0
2138 11:59:08.264159 LP4Y_EN = 0x0
2139 11:59:08.264667 WORK_FSP = 0x0
2140 11:59:08.266844 WL = 0x4
2141 11:59:08.270025 RL = 0x4
2142 11:59:08.270444 BL = 0x2
2143 11:59:08.273433 RPST = 0x0
2144 11:59:08.273847 RD_PRE = 0x0
2145 11:59:08.277006 WR_PRE = 0x1
2146 11:59:08.277512 WR_PST = 0x0
2147 11:59:08.280575 DBI_WR = 0x0
2148 11:59:08.281118 DBI_RD = 0x0
2149 11:59:08.283991 OTF = 0x1
2150 11:59:08.287239 ===================================
2151 11:59:08.290697 ===================================
2152 11:59:08.291117 ANA top config
2153 11:59:08.294032 ===================================
2154 11:59:08.297295 DLL_ASYNC_EN = 0
2155 11:59:08.300383 ALL_SLAVE_EN = 0
2156 11:59:08.300903 NEW_RANK_MODE = 1
2157 11:59:08.304159 DLL_IDLE_MODE = 1
2158 11:59:08.307255 LP45_APHY_COMB_EN = 1
2159 11:59:08.310672 TX_ODT_DIS = 1
2160 11:59:08.311176 NEW_8X_MODE = 1
2161 11:59:08.314305 ===================================
2162 11:59:08.317019 ===================================
2163 11:59:08.320729 data_rate = 2400
2164 11:59:08.323800 CKR = 1
2165 11:59:08.327360 DQ_P2S_RATIO = 8
2166 11:59:08.330536 ===================================
2167 11:59:08.333882 CA_P2S_RATIO = 8
2168 11:59:08.336806 DQ_CA_OPEN = 0
2169 11:59:08.337226 DQ_SEMI_OPEN = 0
2170 11:59:08.340176 CA_SEMI_OPEN = 0
2171 11:59:08.344247 CA_FULL_RATE = 0
2172 11:59:08.347251 DQ_CKDIV4_EN = 0
2173 11:59:08.350786 CA_CKDIV4_EN = 0
2174 11:59:08.353893 CA_PREDIV_EN = 0
2175 11:59:08.354312 PH8_DLY = 17
2176 11:59:08.357291 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 11:59:08.360340 DQ_AAMCK_DIV = 4
2178 11:59:08.363995 CA_AAMCK_DIV = 4
2179 11:59:08.367366 CA_ADMCK_DIV = 4
2180 11:59:08.367901 DQ_TRACK_CA_EN = 0
2181 11:59:08.370844 CA_PICK = 1200
2182 11:59:08.373829 CA_MCKIO = 1200
2183 11:59:08.377169 MCKIO_SEMI = 0
2184 11:59:08.380298 PLL_FREQ = 2366
2185 11:59:08.383531 DQ_UI_PI_RATIO = 32
2186 11:59:08.386991 CA_UI_PI_RATIO = 0
2187 11:59:08.390693 ===================================
2188 11:59:08.393943 ===================================
2189 11:59:08.394356 memory_type:LPDDR4
2190 11:59:08.397028 GP_NUM : 10
2191 11:59:08.400585 SRAM_EN : 1
2192 11:59:08.400995 MD32_EN : 0
2193 11:59:08.404409 ===================================
2194 11:59:08.407836 [ANA_INIT] >>>>>>>>>>>>>>
2195 11:59:08.410383 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 11:59:08.414316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 11:59:08.417446 ===================================
2198 11:59:08.421265 data_rate = 2400,PCW = 0X5b00
2199 11:59:08.423874 ===================================
2200 11:59:08.427355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 11:59:08.430851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 11:59:08.437553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 11:59:08.440608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 11:59:08.444289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 11:59:08.447757 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 11:59:08.450711 [ANA_INIT] flow start
2207 11:59:08.453825 [ANA_INIT] PLL >>>>>>>>
2208 11:59:08.454364 [ANA_INIT] PLL <<<<<<<<
2209 11:59:08.457445 [ANA_INIT] MIDPI >>>>>>>>
2210 11:59:08.460479 [ANA_INIT] MIDPI <<<<<<<<
2211 11:59:08.460889 [ANA_INIT] DLL >>>>>>>>
2212 11:59:08.464150 [ANA_INIT] DLL <<<<<<<<
2213 11:59:08.467432 [ANA_INIT] flow end
2214 11:59:08.470518 ============ LP4 DIFF to SE enter ============
2215 11:59:08.473642 ============ LP4 DIFF to SE exit ============
2216 11:59:08.477430 [ANA_INIT] <<<<<<<<<<<<<
2217 11:59:08.480498 [Flow] Enable top DCM control >>>>>
2218 11:59:08.483472 [Flow] Enable top DCM control <<<<<
2219 11:59:08.486985 Enable DLL master slave shuffle
2220 11:59:08.490529 ==============================================================
2221 11:59:08.493845 Gating Mode config
2222 11:59:08.500259 ==============================================================
2223 11:59:08.500380 Config description:
2224 11:59:08.510201 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 11:59:08.517228 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 11:59:08.520734 SELPH_MODE 0: By rank 1: By Phase
2227 11:59:08.527156 ==============================================================
2228 11:59:08.530310 GAT_TRACK_EN = 1
2229 11:59:08.533979 RX_GATING_MODE = 2
2230 11:59:08.537197 RX_GATING_TRACK_MODE = 2
2231 11:59:08.540605 SELPH_MODE = 1
2232 11:59:08.544088 PICG_EARLY_EN = 1
2233 11:59:08.547111 VALID_LAT_VALUE = 1
2234 11:59:08.550814 ==============================================================
2235 11:59:08.553829 Enter into Gating configuration >>>>
2236 11:59:08.557686 Exit from Gating configuration <<<<
2237 11:59:08.560900 Enter into DVFS_PRE_config >>>>>
2238 11:59:08.570952 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 11:59:08.573902 Exit from DVFS_PRE_config <<<<<
2240 11:59:08.577108 Enter into PICG configuration >>>>
2241 11:59:08.580700 Exit from PICG configuration <<<<
2242 11:59:08.583974 [RX_INPUT] configuration >>>>>
2243 11:59:08.587178 [RX_INPUT] configuration <<<<<
2244 11:59:08.590981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 11:59:08.597395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 11:59:08.604065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 11:59:08.610817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 11:59:08.617449 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 11:59:08.620725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 11:59:08.627701 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 11:59:08.630650 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 11:59:08.634158 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 11:59:08.637530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 11:59:08.644052 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 11:59:08.647382 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 11:59:08.650761 ===================================
2257 11:59:08.654093 LPDDR4 DRAM CONFIGURATION
2258 11:59:08.657675 ===================================
2259 11:59:08.658092 EX_ROW_EN[0] = 0x0
2260 11:59:08.660678 EX_ROW_EN[1] = 0x0
2261 11:59:08.661087 LP4Y_EN = 0x0
2262 11:59:08.664312 WORK_FSP = 0x0
2263 11:59:08.664727 WL = 0x4
2264 11:59:08.667741 RL = 0x4
2265 11:59:08.668157 BL = 0x2
2266 11:59:08.671022 RPST = 0x0
2267 11:59:08.671654 RD_PRE = 0x0
2268 11:59:08.674131 WR_PRE = 0x1
2269 11:59:08.674541 WR_PST = 0x0
2270 11:59:08.677668 DBI_WR = 0x0
2271 11:59:08.678082 DBI_RD = 0x0
2272 11:59:08.680846 OTF = 0x1
2273 11:59:08.684456 ===================================
2274 11:59:08.687638 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 11:59:08.691086 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 11:59:08.697781 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 11:59:08.701016 ===================================
2278 11:59:08.701435 LPDDR4 DRAM CONFIGURATION
2279 11:59:08.703964 ===================================
2280 11:59:08.707599 EX_ROW_EN[0] = 0x10
2281 11:59:08.710689 EX_ROW_EN[1] = 0x0
2282 11:59:08.711105 LP4Y_EN = 0x0
2283 11:59:08.713935 WORK_FSP = 0x0
2284 11:59:08.714348 WL = 0x4
2285 11:59:08.717893 RL = 0x4
2286 11:59:08.718313 BL = 0x2
2287 11:59:08.720676 RPST = 0x0
2288 11:59:08.721091 RD_PRE = 0x0
2289 11:59:08.724823 WR_PRE = 0x1
2290 11:59:08.725237 WR_PST = 0x0
2291 11:59:08.727607 DBI_WR = 0x0
2292 11:59:08.728019 DBI_RD = 0x0
2293 11:59:08.731319 OTF = 0x1
2294 11:59:08.734049 ===================================
2295 11:59:08.740919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 11:59:08.741334 ==
2297 11:59:08.744059 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 11:59:08.747772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 11:59:08.748185 ==
2300 11:59:08.750841 [Duty_Offset_Calibration]
2301 11:59:08.751249 B0:2 B1:1 CA:1
2302 11:59:08.751571
2303 11:59:08.754647 [DutyScan_Calibration_Flow] k_type=0
2304 11:59:08.764464
2305 11:59:08.764875 ==CLK 0==
2306 11:59:08.767814 Final CLK duty delay cell = 0
2307 11:59:08.771333 [0] MAX Duty = 5187%(X100), DQS PI = 24
2308 11:59:08.774349 [0] MIN Duty = 4875%(X100), DQS PI = 0
2309 11:59:08.774761 [0] AVG Duty = 5031%(X100)
2310 11:59:08.775086
2311 11:59:08.777790 CH0 CLK Duty spec in!! Max-Min= 312%
2312 11:59:08.784503 [DutyScan_Calibration_Flow] ====Done====
2313 11:59:08.784914
2314 11:59:08.787627 [DutyScan_Calibration_Flow] k_type=1
2315 11:59:08.802920
2316 11:59:08.803114 ==DQS 0 ==
2317 11:59:08.805829 Final DQS duty delay cell = -4
2318 11:59:08.808963 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2319 11:59:08.812528 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2320 11:59:08.815564 [-4] AVG Duty = 4937%(X100)
2321 11:59:08.815675
2322 11:59:08.815762 ==DQS 1 ==
2323 11:59:08.819059 Final DQS duty delay cell = 0
2324 11:59:08.822509 [0] MAX Duty = 5156%(X100), DQS PI = 12
2325 11:59:08.825647 [0] MIN Duty = 5031%(X100), DQS PI = 32
2326 11:59:08.829278 [0] AVG Duty = 5093%(X100)
2327 11:59:08.829369
2328 11:59:08.832367 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2329 11:59:08.832449
2330 11:59:08.835634 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2331 11:59:08.839320 [DutyScan_Calibration_Flow] ====Done====
2332 11:59:08.839401
2333 11:59:08.842445 [DutyScan_Calibration_Flow] k_type=3
2334 11:59:08.859734
2335 11:59:08.859980 ==DQM 0 ==
2336 11:59:08.863077 Final DQM duty delay cell = 0
2337 11:59:08.866246 [0] MAX Duty = 5156%(X100), DQS PI = 30
2338 11:59:08.870019 [0] MIN Duty = 4906%(X100), DQS PI = 58
2339 11:59:08.870432 [0] AVG Duty = 5031%(X100)
2340 11:59:08.873175
2341 11:59:08.873610 ==DQM 1 ==
2342 11:59:08.876708 Final DQM duty delay cell = 0
2343 11:59:08.879726 [0] MAX Duty = 5093%(X100), DQS PI = 0
2344 11:59:08.883351 [0] MIN Duty = 5031%(X100), DQS PI = 16
2345 11:59:08.883761 [0] AVG Duty = 5062%(X100)
2346 11:59:08.886241
2347 11:59:08.890213 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2348 11:59:08.890647
2349 11:59:08.893253 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2350 11:59:08.896349 [DutyScan_Calibration_Flow] ====Done====
2351 11:59:08.896757
2352 11:59:08.899929 [DutyScan_Calibration_Flow] k_type=2
2353 11:59:08.916397
2354 11:59:08.916883 ==DQ 0 ==
2355 11:59:08.919369 Final DQ duty delay cell = 0
2356 11:59:08.922758 [0] MAX Duty = 5031%(X100), DQS PI = 24
2357 11:59:08.926164 [0] MIN Duty = 4906%(X100), DQS PI = 0
2358 11:59:08.926581 [0] AVG Duty = 4968%(X100)
2359 11:59:08.926912
2360 11:59:08.929087 ==DQ 1 ==
2361 11:59:08.932451 Final DQ duty delay cell = 0
2362 11:59:08.935705 [0] MAX Duty = 5093%(X100), DQS PI = 24
2363 11:59:08.939695 [0] MIN Duty = 4907%(X100), DQS PI = 36
2364 11:59:08.940113 [0] AVG Duty = 5000%(X100)
2365 11:59:08.940442
2366 11:59:08.942767 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2367 11:59:08.946276
2368 11:59:08.949468 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2369 11:59:08.952907 [DutyScan_Calibration_Flow] ====Done====
2370 11:59:08.953320 ==
2371 11:59:08.956333 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 11:59:08.959443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 11:59:08.959860 ==
2374 11:59:08.962550 [Duty_Offset_Calibration]
2375 11:59:08.962964 B0:1 B1:0 CA:0
2376 11:59:08.963292
2377 11:59:08.965733 [DutyScan_Calibration_Flow] k_type=0
2378 11:59:08.975180
2379 11:59:08.975593 ==CLK 0==
2380 11:59:08.979093 Final CLK duty delay cell = -4
2381 11:59:08.981965 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2382 11:59:08.985711 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2383 11:59:08.988586 [-4] AVG Duty = 4969%(X100)
2384 11:59:08.989001
2385 11:59:08.992385 CH1 CLK Duty spec in!! Max-Min= 124%
2386 11:59:08.995264 [DutyScan_Calibration_Flow] ====Done====
2387 11:59:08.995681
2388 11:59:08.998820 [DutyScan_Calibration_Flow] k_type=1
2389 11:59:09.014996
2390 11:59:09.015260 ==DQS 0 ==
2391 11:59:09.017896 Final DQS duty delay cell = 0
2392 11:59:09.021420 [0] MAX Duty = 5094%(X100), DQS PI = 28
2393 11:59:09.025072 [0] MIN Duty = 4875%(X100), DQS PI = 0
2394 11:59:09.025241 [0] AVG Duty = 4984%(X100)
2395 11:59:09.028140
2396 11:59:09.028290 ==DQS 1 ==
2397 11:59:09.031193 Final DQS duty delay cell = 0
2398 11:59:09.034378 [0] MAX Duty = 5156%(X100), DQS PI = 18
2399 11:59:09.037765 [0] MIN Duty = 4969%(X100), DQS PI = 10
2400 11:59:09.041486 [0] AVG Duty = 5062%(X100)
2401 11:59:09.041604
2402 11:59:09.044757 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2403 11:59:09.044861
2404 11:59:09.047983 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2405 11:59:09.051547 [DutyScan_Calibration_Flow] ====Done====
2406 11:59:09.051645
2407 11:59:09.054679 [DutyScan_Calibration_Flow] k_type=3
2408 11:59:09.071426
2409 11:59:09.071572 ==DQM 0 ==
2410 11:59:09.075203 Final DQM duty delay cell = 0
2411 11:59:09.078048 [0] MAX Duty = 5156%(X100), DQS PI = 6
2412 11:59:09.081253 [0] MIN Duty = 5031%(X100), DQS PI = 46
2413 11:59:09.081334 [0] AVG Duty = 5093%(X100)
2414 11:59:09.084882
2415 11:59:09.084963 ==DQM 1 ==
2416 11:59:09.088088 Final DQM duty delay cell = 0
2417 11:59:09.091118 [0] MAX Duty = 5031%(X100), DQS PI = 16
2418 11:59:09.094691 [0] MIN Duty = 4907%(X100), DQS PI = 36
2419 11:59:09.094774 [0] AVG Duty = 4969%(X100)
2420 11:59:09.098276
2421 11:59:09.101310 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2422 11:59:09.101391
2423 11:59:09.104939 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2424 11:59:09.107824 [DutyScan_Calibration_Flow] ====Done====
2425 11:59:09.107905
2426 11:59:09.111293 [DutyScan_Calibration_Flow] k_type=2
2427 11:59:09.126956
2428 11:59:09.127084 ==DQ 0 ==
2429 11:59:09.130231 Final DQ duty delay cell = -4
2430 11:59:09.134198 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2431 11:59:09.136962 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2432 11:59:09.140504 [-4] AVG Duty = 4984%(X100)
2433 11:59:09.140611
2434 11:59:09.140692 ==DQ 1 ==
2435 11:59:09.143477 Final DQ duty delay cell = 0
2436 11:59:09.146893 [0] MAX Duty = 5125%(X100), DQS PI = 20
2437 11:59:09.150237 [0] MIN Duty = 4969%(X100), DQS PI = 12
2438 11:59:09.150350 [0] AVG Duty = 5047%(X100)
2439 11:59:09.153714
2440 11:59:09.156982 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2441 11:59:09.157082
2442 11:59:09.160048 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2443 11:59:09.163525 [DutyScan_Calibration_Flow] ====Done====
2444 11:59:09.166899 nWR fixed to 30
2445 11:59:09.167002 [ModeRegInit_LP4] CH0 RK0
2446 11:59:09.170388 [ModeRegInit_LP4] CH0 RK1
2447 11:59:09.173740 [ModeRegInit_LP4] CH1 RK0
2448 11:59:09.176982 [ModeRegInit_LP4] CH1 RK1
2449 11:59:09.177102 match AC timing 7
2450 11:59:09.180352 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 11:59:09.187345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 11:59:09.190416 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 11:59:09.197125 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 11:59:09.200370 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 11:59:09.200549 ==
2456 11:59:09.203858 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 11:59:09.206935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 11:59:09.207128 ==
2459 11:59:09.214013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 11:59:09.220372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2461 11:59:09.227354 [CA 0] Center 39 (8~70) winsize 63
2462 11:59:09.230567 [CA 1] Center 39 (8~70) winsize 63
2463 11:59:09.233687 [CA 2] Center 35 (5~66) winsize 62
2464 11:59:09.237421 [CA 3] Center 34 (4~65) winsize 62
2465 11:59:09.240560 [CA 4] Center 33 (3~64) winsize 62
2466 11:59:09.244399 [CA 5] Center 32 (3~62) winsize 60
2467 11:59:09.244492
2468 11:59:09.247458 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2469 11:59:09.247540
2470 11:59:09.250808 [CATrainingPosCal] consider 1 rank data
2471 11:59:09.253935 u2DelayCellTimex100 = 270/100 ps
2472 11:59:09.257679 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2473 11:59:09.260790 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2474 11:59:09.267833 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2475 11:59:09.270931 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2476 11:59:09.274149 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2477 11:59:09.277884 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2478 11:59:09.278120
2479 11:59:09.281148 CA PerBit enable=1, Macro0, CA PI delay=32
2480 11:59:09.281474
2481 11:59:09.284308 [CBTSetCACLKResult] CA Dly = 32
2482 11:59:09.284615 CS Dly: 6 (0~37)
2483 11:59:09.284807 ==
2484 11:59:09.287327 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 11:59:09.294415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 11:59:09.294750 ==
2487 11:59:09.297526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 11:59:09.304132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2489 11:59:09.313165 [CA 0] Center 38 (8~69) winsize 62
2490 11:59:09.316737 [CA 1] Center 38 (8~69) winsize 62
2491 11:59:09.320273 [CA 2] Center 35 (4~66) winsize 63
2492 11:59:09.323273 [CA 3] Center 34 (4~65) winsize 62
2493 11:59:09.327311 [CA 4] Center 33 (3~63) winsize 61
2494 11:59:09.330104 [CA 5] Center 32 (3~62) winsize 60
2495 11:59:09.330527
2496 11:59:09.333542 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 11:59:09.334002
2498 11:59:09.336917 [CATrainingPosCal] consider 2 rank data
2499 11:59:09.339937 u2DelayCellTimex100 = 270/100 ps
2500 11:59:09.343159 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2501 11:59:09.346697 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2502 11:59:09.349875 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2503 11:59:09.356574 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2504 11:59:09.359936 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2505 11:59:09.363122 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2506 11:59:09.363212
2507 11:59:09.366718 CA PerBit enable=1, Macro0, CA PI delay=32
2508 11:59:09.366800
2509 11:59:09.369928 [CBTSetCACLKResult] CA Dly = 32
2510 11:59:09.370009 CS Dly: 6 (0~38)
2511 11:59:09.370074
2512 11:59:09.372875 ----->DramcWriteLeveling(PI) begin...
2513 11:59:09.372957 ==
2514 11:59:09.376845 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 11:59:09.383666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 11:59:09.384084 ==
2517 11:59:09.387274 Write leveling (Byte 0): 33 => 33
2518 11:59:09.390518 Write leveling (Byte 1): 30 => 30
2519 11:59:09.390931 DramcWriteLeveling(PI) end<-----
2520 11:59:09.393573
2521 11:59:09.394024 ==
2522 11:59:09.396744 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 11:59:09.400357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 11:59:09.400771 ==
2525 11:59:09.403723 [Gating] SW mode calibration
2526 11:59:09.410046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 11:59:09.413449 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 11:59:09.420369 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2529 11:59:09.423788 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2530 11:59:09.427393 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:59:09.433683 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:59:09.436822 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:59:09.440589 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:59:09.446998 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2535 11:59:09.450653 0 15 28 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
2536 11:59:09.453901 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2537 11:59:09.457130 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:59:09.464060 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:59:09.466992 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:59:09.470793 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:59:09.476953 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:59:09.480092 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2543 11:59:09.483683 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2544 11:59:09.490208 1 1 0 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
2545 11:59:09.494079 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:59:09.496980 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:59:09.503996 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:59:09.506992 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:59:09.510777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:59:09.517720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 11:59:09.520656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 11:59:09.523665 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 11:59:09.530677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:59:09.534233 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:59:09.537068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:59:09.544210 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:59:09.547485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:59:09.551236 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:59:09.553825 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:59:09.560892 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:59:09.564184 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:59:09.567902 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:59:09.574440 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:59:09.577709 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:59:09.581042 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:59:09.587768 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 11:59:09.590567 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 11:59:09.594196 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 11:59:09.597300 Total UI for P1: 0, mck2ui 16
2570 11:59:09.601414 best dqsien dly found for B0: ( 1, 3, 26)
2571 11:59:09.607660 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 11:59:09.608182 Total UI for P1: 0, mck2ui 16
2573 11:59:09.610986 best dqsien dly found for B1: ( 1, 4, 0)
2574 11:59:09.617633 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2575 11:59:09.621081 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 11:59:09.621641
2577 11:59:09.625047 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2578 11:59:09.628004 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 11:59:09.630888 [Gating] SW calibration Done
2580 11:59:09.631306 ==
2581 11:59:09.634579 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 11:59:09.637426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 11:59:09.637937 ==
2584 11:59:09.638305 RX Vref Scan: 0
2585 11:59:09.640914
2586 11:59:09.641330 RX Vref 0 -> 0, step: 1
2587 11:59:09.641706
2588 11:59:09.644583 RX Delay -40 -> 252, step: 8
2589 11:59:09.647958 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2590 11:59:09.651078 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2591 11:59:09.657530 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 11:59:09.660716 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2593 11:59:09.664077 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2594 11:59:09.667887 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2595 11:59:09.670559 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2596 11:59:09.677549 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2597 11:59:09.681034 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2598 11:59:09.684244 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2599 11:59:09.687367 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2600 11:59:09.690812 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2601 11:59:09.697540 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2602 11:59:09.700929 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2603 11:59:09.704236 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2604 11:59:09.707794 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2605 11:59:09.708316 ==
2606 11:59:09.710945 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 11:59:09.717643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 11:59:09.718064 ==
2609 11:59:09.718392 DQS Delay:
2610 11:59:09.718693 DQS0 = 0, DQS1 = 0
2611 11:59:09.720725 DQM Delay:
2612 11:59:09.721184 DQM0 = 121, DQM1 = 114
2613 11:59:09.724973 DQ Delay:
2614 11:59:09.727840 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2615 11:59:09.731470 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2616 11:59:09.734563 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2617 11:59:09.737782 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2618 11:59:09.738194
2619 11:59:09.738520
2620 11:59:09.738821 ==
2621 11:59:09.741424 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:59:09.744443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:59:09.744956 ==
2624 11:59:09.745288
2625 11:59:09.748137
2626 11:59:09.748722 TX Vref Scan disable
2627 11:59:09.750748 == TX Byte 0 ==
2628 11:59:09.754529 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2629 11:59:09.757656 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2630 11:59:09.761094 == TX Byte 1 ==
2631 11:59:09.764545 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2632 11:59:09.767749 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2633 11:59:09.768258 ==
2634 11:59:09.770656 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 11:59:09.777993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 11:59:09.778505 ==
2637 11:59:09.788360 TX Vref=22, minBit 1, minWin=24, winSum=403
2638 11:59:09.791453 TX Vref=24, minBit 0, minWin=24, winSum=409
2639 11:59:09.794781 TX Vref=26, minBit 0, minWin=26, winSum=419
2640 11:59:09.797881 TX Vref=28, minBit 0, minWin=26, winSum=423
2641 11:59:09.801858 TX Vref=30, minBit 0, minWin=26, winSum=424
2642 11:59:09.808232 TX Vref=32, minBit 12, minWin=25, winSum=422
2643 11:59:09.812067 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2644 11:59:09.812593
2645 11:59:09.814536 Final TX Range 1 Vref 30
2646 11:59:09.814951
2647 11:59:09.815274 ==
2648 11:59:09.817978 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:59:09.821487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:59:09.822083 ==
2651 11:59:09.822424
2652 11:59:09.825225
2653 11:59:09.825775 TX Vref Scan disable
2654 11:59:09.828171 == TX Byte 0 ==
2655 11:59:09.831548 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 11:59:09.834618 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 11:59:09.838182 == TX Byte 1 ==
2658 11:59:09.841655 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2659 11:59:09.844809 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2660 11:59:09.848036
2661 11:59:09.848547 [DATLAT]
2662 11:59:09.848879 Freq=1200, CH0 RK0
2663 11:59:09.849187
2664 11:59:09.851357 DATLAT Default: 0xd
2665 11:59:09.851772 0, 0xFFFF, sum = 0
2666 11:59:09.854796 1, 0xFFFF, sum = 0
2667 11:59:09.855275 2, 0xFFFF, sum = 0
2668 11:59:09.857956 3, 0xFFFF, sum = 0
2669 11:59:09.858556 4, 0xFFFF, sum = 0
2670 11:59:09.861190 5, 0xFFFF, sum = 0
2671 11:59:09.861633 6, 0xFFFF, sum = 0
2672 11:59:09.864623 7, 0xFFFF, sum = 0
2673 11:59:09.868510 8, 0xFFFF, sum = 0
2674 11:59:09.869066 9, 0xFFFF, sum = 0
2675 11:59:09.871273 10, 0xFFFF, sum = 0
2676 11:59:09.871737 11, 0xFFFF, sum = 0
2677 11:59:09.874565 12, 0x0, sum = 1
2678 11:59:09.875073 13, 0x0, sum = 2
2679 11:59:09.878164 14, 0x0, sum = 3
2680 11:59:09.878583 15, 0x0, sum = 4
2681 11:59:09.878917 best_step = 13
2682 11:59:09.879220
2683 11:59:09.881256 ==
2684 11:59:09.884634 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:59:09.888438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:59:09.888951 ==
2687 11:59:09.889284 RX Vref Scan: 1
2688 11:59:09.889623
2689 11:59:09.891335 Set Vref Range= 32 -> 127
2690 11:59:09.891747
2691 11:59:09.894447 RX Vref 32 -> 127, step: 1
2692 11:59:09.894861
2693 11:59:09.898053 RX Delay -13 -> 252, step: 4
2694 11:59:09.898500
2695 11:59:09.901487 Set Vref, RX VrefLevel [Byte0]: 32
2696 11:59:09.904589 [Byte1]: 32
2697 11:59:09.905002
2698 11:59:09.908378 Set Vref, RX VrefLevel [Byte0]: 33
2699 11:59:09.911332 [Byte1]: 33
2700 11:59:09.911840
2701 11:59:09.914980 Set Vref, RX VrefLevel [Byte0]: 34
2702 11:59:09.918029 [Byte1]: 34
2703 11:59:09.922152
2704 11:59:09.922561 Set Vref, RX VrefLevel [Byte0]: 35
2705 11:59:09.925354 [Byte1]: 35
2706 11:59:09.929914
2707 11:59:09.930430 Set Vref, RX VrefLevel [Byte0]: 36
2708 11:59:09.933645 [Byte1]: 36
2709 11:59:09.938293
2710 11:59:09.938705 Set Vref, RX VrefLevel [Byte0]: 37
2711 11:59:09.940951 [Byte1]: 37
2712 11:59:09.946201
2713 11:59:09.946614 Set Vref, RX VrefLevel [Byte0]: 38
2714 11:59:09.949432 [Byte1]: 38
2715 11:59:09.953615
2716 11:59:09.954038 Set Vref, RX VrefLevel [Byte0]: 39
2717 11:59:09.957118 [Byte1]: 39
2718 11:59:09.961418
2719 11:59:09.962052 Set Vref, RX VrefLevel [Byte0]: 40
2720 11:59:09.964966 [Byte1]: 40
2721 11:59:09.969727
2722 11:59:09.970247 Set Vref, RX VrefLevel [Byte0]: 41
2723 11:59:09.972907 [Byte1]: 41
2724 11:59:09.977670
2725 11:59:09.978227 Set Vref, RX VrefLevel [Byte0]: 42
2726 11:59:09.980418 [Byte1]: 42
2727 11:59:09.985691
2728 11:59:09.986209 Set Vref, RX VrefLevel [Byte0]: 43
2729 11:59:09.988661 [Byte1]: 43
2730 11:59:09.993173
2731 11:59:09.993721 Set Vref, RX VrefLevel [Byte0]: 44
2732 11:59:09.997085 [Byte1]: 44
2733 11:59:10.001302
2734 11:59:10.001929 Set Vref, RX VrefLevel [Byte0]: 45
2735 11:59:10.004514 [Byte1]: 45
2736 11:59:10.009150
2737 11:59:10.009749 Set Vref, RX VrefLevel [Byte0]: 46
2738 11:59:10.012656 [Byte1]: 46
2739 11:59:10.017268
2740 11:59:10.017751 Set Vref, RX VrefLevel [Byte0]: 47
2741 11:59:10.020376 [Byte1]: 47
2742 11:59:10.025164
2743 11:59:10.025771 Set Vref, RX VrefLevel [Byte0]: 48
2744 11:59:10.027881 [Byte1]: 48
2745 11:59:10.032855
2746 11:59:10.033417 Set Vref, RX VrefLevel [Byte0]: 49
2747 11:59:10.036084 [Byte1]: 49
2748 11:59:10.040830
2749 11:59:10.041498 Set Vref, RX VrefLevel [Byte0]: 50
2750 11:59:10.043821 [Byte1]: 50
2751 11:59:10.048463
2752 11:59:10.049024 Set Vref, RX VrefLevel [Byte0]: 51
2753 11:59:10.051631 [Byte1]: 51
2754 11:59:10.056267
2755 11:59:10.056878 Set Vref, RX VrefLevel [Byte0]: 52
2756 11:59:10.059575 [Byte1]: 52
2757 11:59:10.064086
2758 11:59:10.064509 Set Vref, RX VrefLevel [Byte0]: 53
2759 11:59:10.067465 [Byte1]: 53
2760 11:59:10.072018
2761 11:59:10.072462 Set Vref, RX VrefLevel [Byte0]: 54
2762 11:59:10.075205 [Byte1]: 54
2763 11:59:10.080117
2764 11:59:10.080697 Set Vref, RX VrefLevel [Byte0]: 55
2765 11:59:10.086055 [Byte1]: 55
2766 11:59:10.086592
2767 11:59:10.089718 Set Vref, RX VrefLevel [Byte0]: 56
2768 11:59:10.092745 [Byte1]: 56
2769 11:59:10.093214
2770 11:59:10.096297 Set Vref, RX VrefLevel [Byte0]: 57
2771 11:59:10.099959 [Byte1]: 57
2772 11:59:10.103520
2773 11:59:10.103934 Set Vref, RX VrefLevel [Byte0]: 58
2774 11:59:10.106719 [Byte1]: 58
2775 11:59:10.112156
2776 11:59:10.112664 Set Vref, RX VrefLevel [Byte0]: 59
2777 11:59:10.115076 [Byte1]: 59
2778 11:59:10.119504
2779 11:59:10.120200 Set Vref, RX VrefLevel [Byte0]: 60
2780 11:59:10.122970 [Byte1]: 60
2781 11:59:10.127009
2782 11:59:10.127427 Set Vref, RX VrefLevel [Byte0]: 61
2783 11:59:10.130753 [Byte1]: 61
2784 11:59:10.135063
2785 11:59:10.135477 Set Vref, RX VrefLevel [Byte0]: 62
2786 11:59:10.138602 [Byte1]: 62
2787 11:59:10.143101
2788 11:59:10.143532 Set Vref, RX VrefLevel [Byte0]: 63
2789 11:59:10.146012 [Byte1]: 63
2790 11:59:10.150646
2791 11:59:10.151056 Set Vref, RX VrefLevel [Byte0]: 64
2792 11:59:10.154393 [Byte1]: 64
2793 11:59:10.158539
2794 11:59:10.158946 Set Vref, RX VrefLevel [Byte0]: 65
2795 11:59:10.161808 [Byte1]: 65
2796 11:59:10.166938
2797 11:59:10.167358 Set Vref, RX VrefLevel [Byte0]: 66
2798 11:59:10.169843 [Byte1]: 66
2799 11:59:10.174725
2800 11:59:10.175167 Set Vref, RX VrefLevel [Byte0]: 67
2801 11:59:10.178066 [Byte1]: 67
2802 11:59:10.182593
2803 11:59:10.183037 Set Vref, RX VrefLevel [Byte0]: 68
2804 11:59:10.185768 [Byte1]: 68
2805 11:59:10.190451
2806 11:59:10.190870 Set Vref, RX VrefLevel [Byte0]: 69
2807 11:59:10.193510 [Byte1]: 69
2808 11:59:10.198521
2809 11:59:10.198957 Final RX Vref Byte 0 = 53 to rank0
2810 11:59:10.201826 Final RX Vref Byte 1 = 50 to rank0
2811 11:59:10.204628 Final RX Vref Byte 0 = 53 to rank1
2812 11:59:10.207986 Final RX Vref Byte 1 = 50 to rank1==
2813 11:59:10.211793 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 11:59:10.215130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 11:59:10.218671 ==
2816 11:59:10.219088 DQS Delay:
2817 11:59:10.219414 DQS0 = 0, DQS1 = 0
2818 11:59:10.221413 DQM Delay:
2819 11:59:10.221888 DQM0 = 120, DQM1 = 112
2820 11:59:10.224933 DQ Delay:
2821 11:59:10.228635 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2822 11:59:10.231766 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2823 11:59:10.235063 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2824 11:59:10.238303 DQ12 =120, DQ13 =116, DQ14 =124, DQ15 =122
2825 11:59:10.238819
2826 11:59:10.239150
2827 11:59:10.244881 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2828 11:59:10.248667 CH0 RK0: MR19=404, MR18=150F
2829 11:59:10.255354 CH0_RK0: MR19=0x404, MR18=0x150F, DQSOSC=401, MR23=63, INC=40, DEC=27
2830 11:59:10.255810
2831 11:59:10.258424 ----->DramcWriteLeveling(PI) begin...
2832 11:59:10.258839 ==
2833 11:59:10.261657 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 11:59:10.265768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 11:59:10.266294 ==
2836 11:59:10.268445 Write leveling (Byte 0): 32 => 32
2837 11:59:10.271865 Write leveling (Byte 1): 29 => 29
2838 11:59:10.275376 DramcWriteLeveling(PI) end<-----
2839 11:59:10.275926
2840 11:59:10.276377 ==
2841 11:59:10.278681 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 11:59:10.281963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 11:59:10.285128 ==
2844 11:59:10.285535 [Gating] SW mode calibration
2845 11:59:10.295773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 11:59:10.298559 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 11:59:10.301659 0 15 0 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (1 0)
2848 11:59:10.308792 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 11:59:10.312452 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 11:59:10.315411 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 11:59:10.321974 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 11:59:10.325225 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 11:59:10.328658 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:59:10.335208 0 15 28 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 1)
2855 11:59:10.338779 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
2856 11:59:10.341803 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 11:59:10.348367 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 11:59:10.352323 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 11:59:10.355282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 11:59:10.358946 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 11:59:10.365942 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:59:10.368853 1 0 28 | B1->B0 | 3e3e 3f3f | 0 1 | (1 1) (0 0)
2863 11:59:10.371891 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2864 11:59:10.378895 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 11:59:10.382013 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 11:59:10.385668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 11:59:10.391902 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 11:59:10.395593 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 11:59:10.398501 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:59:10.404960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2871 11:59:10.408586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2872 11:59:10.411678 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:59:10.419083 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:59:10.422253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:59:10.425293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:59:10.432169 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:59:10.435169 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:59:10.438864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:59:10.442116 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:59:10.448820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:59:10.452628 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:59:10.455566 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:59:10.462466 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:59:10.466093 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:59:10.469397 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:59:10.475870 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2887 11:59:10.478825 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 11:59:10.482570 Total UI for P1: 0, mck2ui 16
2889 11:59:10.485951 best dqsien dly found for B0: ( 1, 3, 28)
2890 11:59:10.488789 Total UI for P1: 0, mck2ui 16
2891 11:59:10.492258 best dqsien dly found for B1: ( 1, 3, 28)
2892 11:59:10.495387 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2893 11:59:10.498858 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2894 11:59:10.499403
2895 11:59:10.502235 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 11:59:10.505933 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2897 11:59:10.509266 [Gating] SW calibration Done
2898 11:59:10.509705 ==
2899 11:59:10.512658 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 11:59:10.515743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 11:59:10.516157 ==
2902 11:59:10.519048 RX Vref Scan: 0
2903 11:59:10.519488
2904 11:59:10.522976 RX Vref 0 -> 0, step: 1
2905 11:59:10.523384
2906 11:59:10.523761 RX Delay -40 -> 252, step: 8
2907 11:59:10.529289 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2908 11:59:10.532800 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2909 11:59:10.536313 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2910 11:59:10.539417 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2911 11:59:10.542889 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2912 11:59:10.548985 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2913 11:59:10.552901 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2914 11:59:10.556199 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2915 11:59:10.559465 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2916 11:59:10.563241 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2917 11:59:10.565905 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2918 11:59:10.572888 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2919 11:59:10.576266 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2920 11:59:10.579191 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2921 11:59:10.582984 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2922 11:59:10.586194 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2923 11:59:10.589348 ==
2924 11:59:10.592977 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 11:59:10.595765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 11:59:10.595957 ==
2927 11:59:10.596110 DQS Delay:
2928 11:59:10.599556 DQS0 = 0, DQS1 = 0
2929 11:59:10.599743 DQM Delay:
2930 11:59:10.602681 DQM0 = 122, DQM1 = 112
2931 11:59:10.602861 DQ Delay:
2932 11:59:10.606060 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2933 11:59:10.609330 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2934 11:59:10.612748 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2935 11:59:10.615744 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2936 11:59:10.615960
2937 11:59:10.616168
2938 11:59:10.616381 ==
2939 11:59:10.619296 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 11:59:10.625745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 11:59:10.625998 ==
2942 11:59:10.626208
2943 11:59:10.626425
2944 11:59:10.626645 TX Vref Scan disable
2945 11:59:10.629969 == TX Byte 0 ==
2946 11:59:10.632750 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2947 11:59:10.635930 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2948 11:59:10.639713 == TX Byte 1 ==
2949 11:59:10.642757 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2950 11:59:10.646210 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2951 11:59:10.649881 ==
2952 11:59:10.652900 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 11:59:10.656463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 11:59:10.656564 ==
2955 11:59:10.667913 TX Vref=22, minBit 1, minWin=25, winSum=410
2956 11:59:10.670827 TX Vref=24, minBit 3, minWin=25, winSum=414
2957 11:59:10.675083 TX Vref=26, minBit 3, minWin=25, winSum=419
2958 11:59:10.677649 TX Vref=28, minBit 3, minWin=25, winSum=422
2959 11:59:10.680814 TX Vref=30, minBit 12, minWin=25, winSum=426
2960 11:59:10.687894 TX Vref=32, minBit 13, minWin=25, winSum=421
2961 11:59:10.691182 [TxChooseVref] Worse bit 12, Min win 25, Win sum 426, Final Vref 30
2962 11:59:10.691484
2963 11:59:10.694043 Final TX Range 1 Vref 30
2964 11:59:10.694281
2965 11:59:10.694470 ==
2966 11:59:10.697693 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 11:59:10.701172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 11:59:10.701752 ==
2969 11:59:10.704487
2970 11:59:10.704957
2971 11:59:10.705486 TX Vref Scan disable
2972 11:59:10.707765 == TX Byte 0 ==
2973 11:59:10.710947 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2974 11:59:10.714337 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2975 11:59:10.717817 == TX Byte 1 ==
2976 11:59:10.720953 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2977 11:59:10.724503 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2978 11:59:10.724888
2979 11:59:10.727845 [DATLAT]
2980 11:59:10.728227 Freq=1200, CH0 RK1
2981 11:59:10.728653
2982 11:59:10.731197 DATLAT Default: 0xd
2983 11:59:10.731581 0, 0xFFFF, sum = 0
2984 11:59:10.734287 1, 0xFFFF, sum = 0
2985 11:59:10.734680 2, 0xFFFF, sum = 0
2986 11:59:10.737820 3, 0xFFFF, sum = 0
2987 11:59:10.738383 4, 0xFFFF, sum = 0
2988 11:59:10.741407 5, 0xFFFF, sum = 0
2989 11:59:10.741978 6, 0xFFFF, sum = 0
2990 11:59:10.744666 7, 0xFFFF, sum = 0
2991 11:59:10.745143 8, 0xFFFF, sum = 0
2992 11:59:10.748098 9, 0xFFFF, sum = 0
2993 11:59:10.751202 10, 0xFFFF, sum = 0
2994 11:59:10.751754 11, 0xFFFF, sum = 0
2995 11:59:10.755004 12, 0x0, sum = 1
2996 11:59:10.755544 13, 0x0, sum = 2
2997 11:59:10.755928 14, 0x0, sum = 3
2998 11:59:10.758077 15, 0x0, sum = 4
2999 11:59:10.758601 best_step = 13
3000 11:59:10.759055
3001 11:59:10.761707 ==
3002 11:59:10.764582 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 11:59:10.768008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 11:59:10.768460 ==
3005 11:59:10.768984 RX Vref Scan: 0
3006 11:59:10.769482
3007 11:59:10.771189 RX Vref 0 -> 0, step: 1
3008 11:59:10.771738
3009 11:59:10.774893 RX Delay -13 -> 252, step: 4
3010 11:59:10.778033 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3011 11:59:10.781802 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3012 11:59:10.787829 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3013 11:59:10.791489 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3014 11:59:10.794690 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3015 11:59:10.797841 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3016 11:59:10.801682 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3017 11:59:10.808019 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3018 11:59:10.811267 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3019 11:59:10.814842 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3020 11:59:10.818320 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3021 11:59:10.821346 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3022 11:59:10.828267 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3023 11:59:10.831388 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3024 11:59:10.835258 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3025 11:59:10.838136 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3026 11:59:10.838790 ==
3027 11:59:10.841803 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 11:59:10.848341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 11:59:10.848929 ==
3030 11:59:10.849370 DQS Delay:
3031 11:59:10.849897 DQS0 = 0, DQS1 = 0
3032 11:59:10.851578 DQM Delay:
3033 11:59:10.852069 DQM0 = 121, DQM1 = 110
3034 11:59:10.855088 DQ Delay:
3035 11:59:10.857888 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3036 11:59:10.861452 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3037 11:59:10.865086 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3038 11:59:10.867897 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3039 11:59:10.868480
3040 11:59:10.869035
3041 11:59:10.874852 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3042 11:59:10.878170 CH0 RK1: MR19=403, MR18=10F1
3043 11:59:10.884917 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3044 11:59:10.888432 [RxdqsGatingPostProcess] freq 1200
3045 11:59:10.894826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 11:59:10.898181 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 11:59:10.898609 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 11:59:10.901323 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 11:59:10.904735 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 11:59:10.907959 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 11:59:10.911819 best DQS1 dly(2T, 0.5T) = (0, 11)
3052 11:59:10.914966 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 11:59:10.918128 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3054 11:59:10.921398 Pre-setting of DQS Precalculation
3055 11:59:10.928242 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 11:59:10.928661 ==
3057 11:59:10.931597 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 11:59:10.934752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 11:59:10.935171 ==
3060 11:59:10.941988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 11:59:10.945112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3062 11:59:10.954066 [CA 0] Center 37 (7~68) winsize 62
3063 11:59:10.957415 [CA 1] Center 37 (7~68) winsize 62
3064 11:59:10.960963 [CA 2] Center 35 (5~65) winsize 61
3065 11:59:10.964180 [CA 3] Center 34 (4~64) winsize 61
3066 11:59:10.967829 [CA 4] Center 34 (4~64) winsize 61
3067 11:59:10.970685 [CA 5] Center 33 (3~63) winsize 61
3068 11:59:10.971127
3069 11:59:10.974458 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3070 11:59:10.974889
3071 11:59:10.977888 [CATrainingPosCal] consider 1 rank data
3072 11:59:10.981676 u2DelayCellTimex100 = 270/100 ps
3073 11:59:10.984898 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 11:59:10.987651 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 11:59:10.994230 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3076 11:59:10.997452 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3077 11:59:11.000717 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 11:59:11.004203 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3079 11:59:11.004502
3080 11:59:11.007381 CA PerBit enable=1, Macro0, CA PI delay=33
3081 11:59:11.007602
3082 11:59:11.010645 [CBTSetCACLKResult] CA Dly = 33
3083 11:59:11.010877 CS Dly: 7 (0~38)
3084 11:59:11.011110 ==
3085 11:59:11.014271 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 11:59:11.020948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 11:59:11.021176 ==
3088 11:59:11.023966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 11:59:11.031036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3090 11:59:11.039990 [CA 0] Center 37 (7~68) winsize 62
3091 11:59:11.043300 [CA 1] Center 37 (7~68) winsize 62
3092 11:59:11.046461 [CA 2] Center 35 (5~65) winsize 61
3093 11:59:11.049815 [CA 3] Center 34 (4~65) winsize 62
3094 11:59:11.052804 [CA 4] Center 34 (4~65) winsize 62
3095 11:59:11.056009 [CA 5] Center 34 (4~64) winsize 61
3096 11:59:11.056090
3097 11:59:11.059892 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3098 11:59:11.059972
3099 11:59:11.063010 [CATrainingPosCal] consider 2 rank data
3100 11:59:11.066167 u2DelayCellTimex100 = 270/100 ps
3101 11:59:11.069496 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 11:59:11.073050 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 11:59:11.079619 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3104 11:59:11.083007 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 11:59:11.086390 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 11:59:11.090016 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3107 11:59:11.090121
3108 11:59:11.093206 CA PerBit enable=1, Macro0, CA PI delay=33
3109 11:59:11.093301
3110 11:59:11.096485 [CBTSetCACLKResult] CA Dly = 33
3111 11:59:11.096594 CS Dly: 8 (0~41)
3112 11:59:11.096716
3113 11:59:11.100230 ----->DramcWriteLeveling(PI) begin...
3114 11:59:11.100383 ==
3115 11:59:11.103417 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 11:59:11.109857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 11:59:11.109981 ==
3118 11:59:11.113305 Write leveling (Byte 0): 25 => 25
3119 11:59:11.117259 Write leveling (Byte 1): 29 => 29
3120 11:59:11.117498 DramcWriteLeveling(PI) end<-----
3121 11:59:11.117672
3122 11:59:11.120171 ==
3123 11:59:11.123338 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 11:59:11.127128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 11:59:11.127429 ==
3126 11:59:11.129911 [Gating] SW mode calibration
3127 11:59:11.137136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 11:59:11.140172 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 11:59:11.147335 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3130 11:59:11.150263 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 11:59:11.154097 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 11:59:11.160601 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 11:59:11.163498 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 11:59:11.167627 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 11:59:11.173948 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
3136 11:59:11.177543 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3137 11:59:11.180840 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:59:11.187365 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 11:59:11.190459 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 11:59:11.193653 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 11:59:11.197514 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 11:59:11.203666 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3143 11:59:11.207581 1 0 24 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
3144 11:59:11.210581 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:59:11.216966 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 11:59:11.220198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:59:11.223784 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 11:59:11.230781 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 11:59:11.233967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 11:59:11.237688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 11:59:11.243898 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3152 11:59:11.247139 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 11:59:11.250912 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:59:11.257573 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:59:11.260565 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:59:11.263942 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:59:11.267187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:59:11.274116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:59:11.277281 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:59:11.280882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:59:11.287203 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:59:11.290742 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:59:11.294152 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:59:11.300706 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:59:11.304212 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:59:11.307393 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:59:11.314353 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3168 11:59:11.317542 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 11:59:11.320996 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 11:59:11.324193 Total UI for P1: 0, mck2ui 16
3171 11:59:11.327256 best dqsien dly found for B0: ( 1, 3, 26)
3172 11:59:11.330843 Total UI for P1: 0, mck2ui 16
3173 11:59:11.334358 best dqsien dly found for B1: ( 1, 3, 26)
3174 11:59:11.337330 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3175 11:59:11.340939 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3176 11:59:11.341370
3177 11:59:11.344158 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3178 11:59:11.350988 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3179 11:59:11.351406 [Gating] SW calibration Done
3180 11:59:11.351737 ==
3181 11:59:11.354191 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 11:59:11.361196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 11:59:11.361663 ==
3184 11:59:11.362007 RX Vref Scan: 0
3185 11:59:11.362318
3186 11:59:11.364374 RX Vref 0 -> 0, step: 1
3187 11:59:11.364892
3188 11:59:11.367472 RX Delay -40 -> 252, step: 8
3189 11:59:11.371365 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3190 11:59:11.374395 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3191 11:59:11.377746 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3192 11:59:11.381550 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3193 11:59:11.387922 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3194 11:59:11.391590 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3195 11:59:11.394557 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3196 11:59:11.398118 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3197 11:59:11.401046 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3198 11:59:11.408109 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3199 11:59:11.411725 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3200 11:59:11.414349 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3201 11:59:11.417826 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3202 11:59:11.421181 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3203 11:59:11.427767 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3204 11:59:11.431108 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3205 11:59:11.431528 ==
3206 11:59:11.434842 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 11:59:11.437688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 11:59:11.438140 ==
3209 11:59:11.440928 DQS Delay:
3210 11:59:11.441339 DQS0 = 0, DQS1 = 0
3211 11:59:11.441716 DQM Delay:
3212 11:59:11.445006 DQM0 = 121, DQM1 = 117
3213 11:59:11.445546 DQ Delay:
3214 11:59:11.448113 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3215 11:59:11.451124 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3216 11:59:11.454613 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3217 11:59:11.461636 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =127
3218 11:59:11.462053
3219 11:59:11.462381
3220 11:59:11.462683 ==
3221 11:59:11.464608 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:59:11.467768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 11:59:11.468152 ==
3224 11:59:11.468470
3225 11:59:11.468768
3226 11:59:11.471520 TX Vref Scan disable
3227 11:59:11.471931 == TX Byte 0 ==
3228 11:59:11.477800 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3229 11:59:11.481666 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3230 11:59:11.482127 == TX Byte 1 ==
3231 11:59:11.488032 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3232 11:59:11.491061 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3233 11:59:11.491475 ==
3234 11:59:11.494885 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 11:59:11.498223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 11:59:11.498651 ==
3237 11:59:11.510838 TX Vref=22, minBit 12, minWin=24, winSum=411
3238 11:59:11.513998 TX Vref=24, minBit 9, minWin=24, winSum=415
3239 11:59:11.517238 TX Vref=26, minBit 1, minWin=26, winSum=426
3240 11:59:11.521112 TX Vref=28, minBit 1, minWin=26, winSum=427
3241 11:59:11.523842 TX Vref=30, minBit 2, minWin=26, winSum=430
3242 11:59:11.527589 TX Vref=32, minBit 9, minWin=26, winSum=434
3243 11:59:11.533657 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3244 11:59:11.534122
3245 11:59:11.537061 Final TX Range 1 Vref 32
3246 11:59:11.537472
3247 11:59:11.537847 ==
3248 11:59:11.540421 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 11:59:11.544163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 11:59:11.544584 ==
3251 11:59:11.544911
3252 11:59:11.545217
3253 11:59:11.547286 TX Vref Scan disable
3254 11:59:11.550939 == TX Byte 0 ==
3255 11:59:11.554366 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3256 11:59:11.557714 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3257 11:59:11.560979 == TX Byte 1 ==
3258 11:59:11.564152 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3259 11:59:11.567125 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3260 11:59:11.567595
3261 11:59:11.570678 [DATLAT]
3262 11:59:11.571116 Freq=1200, CH1 RK0
3263 11:59:11.571493
3264 11:59:11.573900 DATLAT Default: 0xd
3265 11:59:11.574516 0, 0xFFFF, sum = 0
3266 11:59:11.577311 1, 0xFFFF, sum = 0
3267 11:59:11.577768 2, 0xFFFF, sum = 0
3268 11:59:11.580580 3, 0xFFFF, sum = 0
3269 11:59:11.581002 4, 0xFFFF, sum = 0
3270 11:59:11.584095 5, 0xFFFF, sum = 0
3271 11:59:11.584520 6, 0xFFFF, sum = 0
3272 11:59:11.587777 7, 0xFFFF, sum = 0
3273 11:59:11.588198 8, 0xFFFF, sum = 0
3274 11:59:11.590981 9, 0xFFFF, sum = 0
3275 11:59:11.591405 10, 0xFFFF, sum = 0
3276 11:59:11.593931 11, 0xFFFF, sum = 0
3277 11:59:11.594355 12, 0x0, sum = 1
3278 11:59:11.597859 13, 0x0, sum = 2
3279 11:59:11.598520 14, 0x0, sum = 3
3280 11:59:11.601017 15, 0x0, sum = 4
3281 11:59:11.601444 best_step = 13
3282 11:59:11.601816
3283 11:59:11.602131 ==
3284 11:59:11.604545 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 11:59:11.611267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 11:59:11.611783 ==
3287 11:59:11.612120 RX Vref Scan: 1
3288 11:59:11.612431
3289 11:59:11.614129 Set Vref Range= 32 -> 127
3290 11:59:11.614546
3291 11:59:11.617469 RX Vref 32 -> 127, step: 1
3292 11:59:11.618031
3293 11:59:11.618371 RX Delay -5 -> 252, step: 4
3294 11:59:11.621481
3295 11:59:11.622047 Set Vref, RX VrefLevel [Byte0]: 32
3296 11:59:11.624504 [Byte1]: 32
3297 11:59:11.628915
3298 11:59:11.629331 Set Vref, RX VrefLevel [Byte0]: 33
3299 11:59:11.632330 [Byte1]: 33
3300 11:59:11.636785
3301 11:59:11.637195 Set Vref, RX VrefLevel [Byte0]: 34
3302 11:59:11.639948 [Byte1]: 34
3303 11:59:11.644588
3304 11:59:11.644997 Set Vref, RX VrefLevel [Byte0]: 35
3305 11:59:11.647755 [Byte1]: 35
3306 11:59:11.652504
3307 11:59:11.652914 Set Vref, RX VrefLevel [Byte0]: 36
3308 11:59:11.655701 [Byte1]: 36
3309 11:59:11.660560
3310 11:59:11.661063 Set Vref, RX VrefLevel [Byte0]: 37
3311 11:59:11.663561 [Byte1]: 37
3312 11:59:11.668221
3313 11:59:11.668806 Set Vref, RX VrefLevel [Byte0]: 38
3314 11:59:11.671449 [Byte1]: 38
3315 11:59:11.675914
3316 11:59:11.676329 Set Vref, RX VrefLevel [Byte0]: 39
3317 11:59:11.679564 [Byte1]: 39
3318 11:59:11.683612
3319 11:59:11.684021 Set Vref, RX VrefLevel [Byte0]: 40
3320 11:59:11.687134 [Byte1]: 40
3321 11:59:11.691438
3322 11:59:11.691937 Set Vref, RX VrefLevel [Byte0]: 41
3323 11:59:11.694591 [Byte1]: 41
3324 11:59:11.699805
3325 11:59:11.700218 Set Vref, RX VrefLevel [Byte0]: 42
3326 11:59:11.703203 [Byte1]: 42
3327 11:59:11.707124
3328 11:59:11.707638 Set Vref, RX VrefLevel [Byte0]: 43
3329 11:59:11.710381 [Byte1]: 43
3330 11:59:11.715349
3331 11:59:11.715796 Set Vref, RX VrefLevel [Byte0]: 44
3332 11:59:11.718624 [Byte1]: 44
3333 11:59:11.723295
3334 11:59:11.723705 Set Vref, RX VrefLevel [Byte0]: 45
3335 11:59:11.726329 [Byte1]: 45
3336 11:59:11.731134
3337 11:59:11.731639 Set Vref, RX VrefLevel [Byte0]: 46
3338 11:59:11.734267 [Byte1]: 46
3339 11:59:11.738829
3340 11:59:11.739361 Set Vref, RX VrefLevel [Byte0]: 47
3341 11:59:11.741886 [Byte1]: 47
3342 11:59:11.746839
3343 11:59:11.747409 Set Vref, RX VrefLevel [Byte0]: 48
3344 11:59:11.749838 [Byte1]: 48
3345 11:59:11.754612
3346 11:59:11.755153 Set Vref, RX VrefLevel [Byte0]: 49
3347 11:59:11.758004 [Byte1]: 49
3348 11:59:11.762152
3349 11:59:11.762663 Set Vref, RX VrefLevel [Byte0]: 50
3350 11:59:11.765786 [Byte1]: 50
3351 11:59:11.770096
3352 11:59:11.770564 Set Vref, RX VrefLevel [Byte0]: 51
3353 11:59:11.773572 [Byte1]: 51
3354 11:59:11.778096
3355 11:59:11.778655 Set Vref, RX VrefLevel [Byte0]: 52
3356 11:59:11.781982 [Byte1]: 52
3357 11:59:11.786205
3358 11:59:11.786756 Set Vref, RX VrefLevel [Byte0]: 53
3359 11:59:11.789302 [Byte1]: 53
3360 11:59:11.794295
3361 11:59:11.794854 Set Vref, RX VrefLevel [Byte0]: 54
3362 11:59:11.797470 [Byte1]: 54
3363 11:59:11.802021
3364 11:59:11.802580 Set Vref, RX VrefLevel [Byte0]: 55
3365 11:59:11.805357 [Byte1]: 55
3366 11:59:11.809673
3367 11:59:11.810234 Set Vref, RX VrefLevel [Byte0]: 56
3368 11:59:11.812717 [Byte1]: 56
3369 11:59:11.817396
3370 11:59:11.818050 Set Vref, RX VrefLevel [Byte0]: 57
3371 11:59:11.820663 [Byte1]: 57
3372 11:59:11.825562
3373 11:59:11.826200 Set Vref, RX VrefLevel [Byte0]: 58
3374 11:59:11.828618 [Byte1]: 58
3375 11:59:11.833034
3376 11:59:11.833618 Set Vref, RX VrefLevel [Byte0]: 59
3377 11:59:11.836337 [Byte1]: 59
3378 11:59:11.840576
3379 11:59:11.841029 Set Vref, RX VrefLevel [Byte0]: 60
3380 11:59:11.844340 [Byte1]: 60
3381 11:59:11.848931
3382 11:59:11.849487 Set Vref, RX VrefLevel [Byte0]: 61
3383 11:59:11.852312 [Byte1]: 61
3384 11:59:11.856624
3385 11:59:11.857087 Set Vref, RX VrefLevel [Byte0]: 62
3386 11:59:11.859629 [Byte1]: 62
3387 11:59:11.864535
3388 11:59:11.865091 Set Vref, RX VrefLevel [Byte0]: 63
3389 11:59:11.867937 [Byte1]: 63
3390 11:59:11.872091
3391 11:59:11.872640 Set Vref, RX VrefLevel [Byte0]: 64
3392 11:59:11.876082 [Byte1]: 64
3393 11:59:11.880405
3394 11:59:11.880958 Set Vref, RX VrefLevel [Byte0]: 65
3395 11:59:11.883356 [Byte1]: 65
3396 11:59:11.887760
3397 11:59:11.888219 Set Vref, RX VrefLevel [Byte0]: 66
3398 11:59:11.891061 [Byte1]: 66
3399 11:59:11.896211
3400 11:59:11.896764 Set Vref, RX VrefLevel [Byte0]: 67
3401 11:59:11.899199 [Byte1]: 67
3402 11:59:11.903442
3403 11:59:11.904139 Set Vref, RX VrefLevel [Byte0]: 68
3404 11:59:11.906974 [Byte1]: 68
3405 11:59:11.911480
3406 11:59:11.911939 Set Vref, RX VrefLevel [Byte0]: 69
3407 11:59:11.914871 [Byte1]: 69
3408 11:59:11.919253
3409 11:59:11.919804 Final RX Vref Byte 0 = 56 to rank0
3410 11:59:11.922560 Final RX Vref Byte 1 = 53 to rank0
3411 11:59:11.926067 Final RX Vref Byte 0 = 56 to rank1
3412 11:59:11.929143 Final RX Vref Byte 1 = 53 to rank1==
3413 11:59:11.932381 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 11:59:11.938914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 11:59:11.939385 ==
3416 11:59:11.939754 DQS Delay:
3417 11:59:11.940090 DQS0 = 0, DQS1 = 0
3418 11:59:11.942684 DQM Delay:
3419 11:59:11.943192 DQM0 = 120, DQM1 = 117
3420 11:59:11.945538 DQ Delay:
3421 11:59:11.949179 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3422 11:59:11.952558 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3423 11:59:11.955982 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3424 11:59:11.959407 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3425 11:59:11.959900
3426 11:59:11.960243
3427 11:59:11.965716 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3428 11:59:11.968812 CH1 RK0: MR19=304, MR18=FF12
3429 11:59:11.975600 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3430 11:59:11.976116
3431 11:59:11.979162 ----->DramcWriteLeveling(PI) begin...
3432 11:59:11.979587 ==
3433 11:59:11.982641 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 11:59:11.985517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 11:59:11.988834 ==
3436 11:59:11.989249 Write leveling (Byte 0): 25 => 25
3437 11:59:11.993071 Write leveling (Byte 1): 28 => 28
3438 11:59:11.995641 DramcWriteLeveling(PI) end<-----
3439 11:59:11.996120
3440 11:59:11.996450 ==
3441 11:59:11.999273 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 11:59:12.005657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 11:59:12.006159 ==
3444 11:59:12.006511 [Gating] SW mode calibration
3445 11:59:12.015849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 11:59:12.019052 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 11:59:12.022831 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:59:12.029095 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:59:12.032437 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 11:59:12.035289 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 11:59:12.041948 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 11:59:12.045558 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3453 11:59:12.048409 0 15 24 | B1->B0 | 2b2b 3434 | 1 1 | (1 0) (1 0)
3454 11:59:12.055802 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 11:59:12.058798 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 11:59:12.062141 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:59:12.068697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 11:59:12.072015 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 11:59:12.075699 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 11:59:12.082349 1 0 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3461 11:59:12.085870 1 0 24 | B1->B0 | 4242 2a2a | 0 0 | (0 0) (0 0)
3462 11:59:12.088679 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:59:12.095199 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:59:12.099081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:59:12.102231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:59:12.108875 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 11:59:12.112112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 11:59:12.115891 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 11:59:12.122625 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3470 11:59:12.125931 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:59:12.128694 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3472 11:59:12.131938 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:59:12.138779 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:59:12.142029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:59:12.145462 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:59:12.152008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:59:12.155438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:59:12.159117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:59:12.165174 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:59:12.169036 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:59:12.172285 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:59:12.178846 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:59:12.182189 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:59:12.185343 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3485 11:59:12.192016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3486 11:59:12.195562 Total UI for P1: 0, mck2ui 16
3487 11:59:12.198834 best dqsien dly found for B1: ( 1, 3, 20)
3488 11:59:12.202531 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3489 11:59:12.205120 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 11:59:12.208879 Total UI for P1: 0, mck2ui 16
3491 11:59:12.211668 best dqsien dly found for B0: ( 1, 3, 26)
3492 11:59:12.215349 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3493 11:59:12.218590 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3494 11:59:12.219112
3495 11:59:12.225020 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3496 11:59:12.228310 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3497 11:59:12.232032 [Gating] SW calibration Done
3498 11:59:12.232464 ==
3499 11:59:12.235077 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 11:59:12.238648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 11:59:12.239112 ==
3502 11:59:12.239449 RX Vref Scan: 0
3503 11:59:12.239802
3504 11:59:12.241542 RX Vref 0 -> 0, step: 1
3505 11:59:12.241951
3506 11:59:12.245430 RX Delay -40 -> 252, step: 8
3507 11:59:12.248595 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3508 11:59:12.251548 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3509 11:59:12.258707 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3510 11:59:12.261563 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3511 11:59:12.265106 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3512 11:59:12.268222 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3513 11:59:12.271842 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3514 11:59:12.274972 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3515 11:59:12.281657 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3516 11:59:12.284769 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3517 11:59:12.288471 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3518 11:59:12.291562 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3519 11:59:12.298467 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3520 11:59:12.301865 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3521 11:59:12.305376 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3522 11:59:12.308338 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3523 11:59:12.308760 ==
3524 11:59:12.311246 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 11:59:12.318006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 11:59:12.318441 ==
3527 11:59:12.318768 DQS Delay:
3528 11:59:12.319127 DQS0 = 0, DQS1 = 0
3529 11:59:12.321156 DQM Delay:
3530 11:59:12.321567 DQM0 = 120, DQM1 = 117
3531 11:59:12.324463 DQ Delay:
3532 11:59:12.327636 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3533 11:59:12.331066 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3534 11:59:12.334906 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3535 11:59:12.337760 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3536 11:59:12.338182
3537 11:59:12.338512
3538 11:59:12.338831 ==
3539 11:59:12.340980 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:59:12.344566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:59:12.347955 ==
3542 11:59:12.348394
3543 11:59:12.348719
3544 11:59:12.349035 TX Vref Scan disable
3545 11:59:12.351215 == TX Byte 0 ==
3546 11:59:12.354776 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3547 11:59:12.357623 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3548 11:59:12.361388 == TX Byte 1 ==
3549 11:59:12.364857 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 11:59:12.367607 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 11:59:12.368024 ==
3552 11:59:12.371519 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 11:59:12.377914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 11:59:12.378328 ==
3555 11:59:12.388840 TX Vref=22, minBit 9, minWin=25, winSum=422
3556 11:59:12.392475 TX Vref=24, minBit 10, minWin=25, winSum=423
3557 11:59:12.395649 TX Vref=26, minBit 1, minWin=26, winSum=425
3558 11:59:12.398561 TX Vref=28, minBit 8, minWin=26, winSum=431
3559 11:59:12.401906 TX Vref=30, minBit 2, minWin=26, winSum=435
3560 11:59:12.408642 TX Vref=32, minBit 10, minWin=26, winSum=433
3561 11:59:12.411899 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 30
3562 11:59:12.412332
3563 11:59:12.415657 Final TX Range 1 Vref 30
3564 11:59:12.416173
3565 11:59:12.416648 ==
3566 11:59:12.418823 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 11:59:12.422009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 11:59:12.422427 ==
3569 11:59:12.424887
3570 11:59:12.425424
3571 11:59:12.425859 TX Vref Scan disable
3572 11:59:12.428189 == TX Byte 0 ==
3573 11:59:12.432066 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3574 11:59:12.435480 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3575 11:59:12.438666 == TX Byte 1 ==
3576 11:59:12.442180 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 11:59:12.445242 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 11:59:12.448701
3579 11:59:12.449138 [DATLAT]
3580 11:59:12.449608 Freq=1200, CH1 RK1
3581 11:59:12.450082
3582 11:59:12.452060 DATLAT Default: 0xd
3583 11:59:12.452481 0, 0xFFFF, sum = 0
3584 11:59:12.454963 1, 0xFFFF, sum = 0
3585 11:59:12.455382 2, 0xFFFF, sum = 0
3586 11:59:12.458523 3, 0xFFFF, sum = 0
3587 11:59:12.461989 4, 0xFFFF, sum = 0
3588 11:59:12.462566 5, 0xFFFF, sum = 0
3589 11:59:12.464751 6, 0xFFFF, sum = 0
3590 11:59:12.465259 7, 0xFFFF, sum = 0
3591 11:59:12.468160 8, 0xFFFF, sum = 0
3592 11:59:12.468726 9, 0xFFFF, sum = 0
3593 11:59:12.471432 10, 0xFFFF, sum = 0
3594 11:59:12.472022 11, 0xFFFF, sum = 0
3595 11:59:12.475390 12, 0x0, sum = 1
3596 11:59:12.475809 13, 0x0, sum = 2
3597 11:59:12.478254 14, 0x0, sum = 3
3598 11:59:12.478641 15, 0x0, sum = 4
3599 11:59:12.481648 best_step = 13
3600 11:59:12.482210
3601 11:59:12.482737 ==
3602 11:59:12.484700 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 11:59:12.488332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 11:59:12.488726 ==
3605 11:59:12.488988 RX Vref Scan: 0
3606 11:59:12.489204
3607 11:59:12.491402 RX Vref 0 -> 0, step: 1
3608 11:59:12.491625
3609 11:59:12.494461 RX Delay -5 -> 252, step: 4
3610 11:59:12.498118 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3611 11:59:12.504566 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3612 11:59:12.508402 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3613 11:59:12.511114 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3614 11:59:12.514537 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3615 11:59:12.517912 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3616 11:59:12.524861 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3617 11:59:12.527761 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3618 11:59:12.531287 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3619 11:59:12.535092 iDelay=195, Bit 9, Center 110 (51 ~ 170) 120
3620 11:59:12.537759 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3621 11:59:12.544464 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3622 11:59:12.547910 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3623 11:59:12.550984 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3624 11:59:12.554723 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3625 11:59:12.557731 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3626 11:59:12.561639 ==
3627 11:59:12.564685 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 11:59:12.568258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 11:59:12.568676 ==
3630 11:59:12.569000 DQS Delay:
3631 11:59:12.571430 DQS0 = 0, DQS1 = 0
3632 11:59:12.571840 DQM Delay:
3633 11:59:12.574489 DQM0 = 120, DQM1 = 118
3634 11:59:12.574900 DQ Delay:
3635 11:59:12.577656 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3636 11:59:12.581053 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3637 11:59:12.584126 DQ8 =106, DQ9 =110, DQ10 =118, DQ11 =112
3638 11:59:12.587923 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3639 11:59:12.588465
3640 11:59:12.588800
3641 11:59:12.597674 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3642 11:59:12.600974 CH1 RK1: MR19=403, MR18=11EE
3643 11:59:12.607537 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3644 11:59:12.608059 [RxdqsGatingPostProcess] freq 1200
3645 11:59:12.614281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 11:59:12.617559 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 11:59:12.621306 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 11:59:12.624403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 11:59:12.627560 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 11:59:12.631144 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 11:59:12.634031 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 11:59:12.637946 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 11:59:12.640899 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 11:59:12.643783 Pre-setting of DQS Precalculation
3655 11:59:12.647466 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 11:59:12.654205 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 11:59:12.664057 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 11:59:12.664614
3659 11:59:12.664973
3660 11:59:12.665306 [Calibration Summary] 2400 Mbps
3661 11:59:12.667867 CH 0, Rank 0
3662 11:59:12.668495 SW Impedance : PASS
3663 11:59:12.670169 DUTY Scan : NO K
3664 11:59:12.674055 ZQ Calibration : PASS
3665 11:59:12.674607 Jitter Meter : NO K
3666 11:59:12.677228 CBT Training : PASS
3667 11:59:12.681023 Write leveling : PASS
3668 11:59:12.681619 RX DQS gating : PASS
3669 11:59:12.683882 RX DQ/DQS(RDDQC) : PASS
3670 11:59:12.686639 TX DQ/DQS : PASS
3671 11:59:12.687103 RX DATLAT : PASS
3672 11:59:12.690114 RX DQ/DQS(Engine): PASS
3673 11:59:12.693715 TX OE : NO K
3674 11:59:12.694222 All Pass.
3675 11:59:12.694588
3676 11:59:12.694926 CH 0, Rank 1
3677 11:59:12.697353 SW Impedance : PASS
3678 11:59:12.700614 DUTY Scan : NO K
3679 11:59:12.701162 ZQ Calibration : PASS
3680 11:59:12.703394 Jitter Meter : NO K
3681 11:59:12.706831 CBT Training : PASS
3682 11:59:12.707416 Write leveling : PASS
3683 11:59:12.710254 RX DQS gating : PASS
3684 11:59:12.713564 RX DQ/DQS(RDDQC) : PASS
3685 11:59:12.714070 TX DQ/DQS : PASS
3686 11:59:12.717298 RX DATLAT : PASS
3687 11:59:12.720410 RX DQ/DQS(Engine): PASS
3688 11:59:12.720956 TX OE : NO K
3689 11:59:12.723748 All Pass.
3690 11:59:12.724299
3691 11:59:12.724661 CH 1, Rank 0
3692 11:59:12.726427 SW Impedance : PASS
3693 11:59:12.726888 DUTY Scan : NO K
3694 11:59:12.730044 ZQ Calibration : PASS
3695 11:59:12.733276 Jitter Meter : NO K
3696 11:59:12.733768 CBT Training : PASS
3697 11:59:12.736647 Write leveling : PASS
3698 11:59:12.737222 RX DQS gating : PASS
3699 11:59:12.740126 RX DQ/DQS(RDDQC) : PASS
3700 11:59:12.742821 TX DQ/DQS : PASS
3701 11:59:12.743244 RX DATLAT : PASS
3702 11:59:12.746375 RX DQ/DQS(Engine): PASS
3703 11:59:12.749655 TX OE : NO K
3704 11:59:12.750072 All Pass.
3705 11:59:12.750405
3706 11:59:12.750709 CH 1, Rank 1
3707 11:59:12.753466 SW Impedance : PASS
3708 11:59:12.756521 DUTY Scan : NO K
3709 11:59:12.756970 ZQ Calibration : PASS
3710 11:59:12.759640 Jitter Meter : NO K
3711 11:59:12.763047 CBT Training : PASS
3712 11:59:12.763558 Write leveling : PASS
3713 11:59:12.766907 RX DQS gating : PASS
3714 11:59:12.769428 RX DQ/DQS(RDDQC) : PASS
3715 11:59:12.770043 TX DQ/DQS : PASS
3716 11:59:12.773057 RX DATLAT : PASS
3717 11:59:12.776771 RX DQ/DQS(Engine): PASS
3718 11:59:12.777282 TX OE : NO K
3719 11:59:12.777661 All Pass.
3720 11:59:12.779795
3721 11:59:12.780314 DramC Write-DBI off
3722 11:59:12.783317 PER_BANK_REFRESH: Hybrid Mode
3723 11:59:12.783825 TX_TRACKING: ON
3724 11:59:12.793458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 11:59:12.796230 [FAST_K] Save calibration result to emmc
3726 11:59:12.799759 dramc_set_vcore_voltage set vcore to 650000
3727 11:59:12.803210 Read voltage for 600, 5
3728 11:59:12.803757 Vio18 = 0
3729 11:59:12.806211 Vcore = 650000
3730 11:59:12.806666 Vdram = 0
3731 11:59:12.807025 Vddq = 0
3732 11:59:12.807358 Vmddr = 0
3733 11:59:12.812949 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 11:59:12.819895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 11:59:12.820450 MEM_TYPE=3, freq_sel=19
3736 11:59:12.823089 sv_algorithm_assistance_LP4_1600
3737 11:59:12.826060 ============ PULL DRAM RESETB DOWN ============
3738 11:59:12.833533 ========== PULL DRAM RESETB DOWN end =========
3739 11:59:12.836873 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 11:59:12.839516 ===================================
3741 11:59:12.842658 LPDDR4 DRAM CONFIGURATION
3742 11:59:12.846237 ===================================
3743 11:59:12.846694 EX_ROW_EN[0] = 0x0
3744 11:59:12.849886 EX_ROW_EN[1] = 0x0
3745 11:59:12.850432 LP4Y_EN = 0x0
3746 11:59:12.853267 WORK_FSP = 0x0
3747 11:59:12.853865 WL = 0x2
3748 11:59:12.856295 RL = 0x2
3749 11:59:12.856884 BL = 0x2
3750 11:59:12.860130 RPST = 0x0
3751 11:59:12.863219 RD_PRE = 0x0
3752 11:59:12.863770 WR_PRE = 0x1
3753 11:59:12.866453 WR_PST = 0x0
3754 11:59:12.867002 DBI_WR = 0x0
3755 11:59:12.869340 DBI_RD = 0x0
3756 11:59:12.869958 OTF = 0x1
3757 11:59:12.872858 ===================================
3758 11:59:12.876201 ===================================
3759 11:59:12.879742 ANA top config
3760 11:59:12.882774 ===================================
3761 11:59:12.883326 DLL_ASYNC_EN = 0
3762 11:59:12.885780 ALL_SLAVE_EN = 1
3763 11:59:12.888992 NEW_RANK_MODE = 1
3764 11:59:12.893020 DLL_IDLE_MODE = 1
3765 11:59:12.893571 LP45_APHY_COMB_EN = 1
3766 11:59:12.896421 TX_ODT_DIS = 1
3767 11:59:12.899303 NEW_8X_MODE = 1
3768 11:59:12.902608 ===================================
3769 11:59:12.906527 ===================================
3770 11:59:12.909687 data_rate = 1200
3771 11:59:12.913279 CKR = 1
3772 11:59:12.913797 DQ_P2S_RATIO = 8
3773 11:59:12.915621 ===================================
3774 11:59:12.919317 CA_P2S_RATIO = 8
3775 11:59:12.922374 DQ_CA_OPEN = 0
3776 11:59:12.925743 DQ_SEMI_OPEN = 0
3777 11:59:12.929432 CA_SEMI_OPEN = 0
3778 11:59:12.933104 CA_FULL_RATE = 0
3779 11:59:12.933716 DQ_CKDIV4_EN = 1
3780 11:59:12.935832 CA_CKDIV4_EN = 1
3781 11:59:12.939384 CA_PREDIV_EN = 0
3782 11:59:12.942368 PH8_DLY = 0
3783 11:59:12.946001 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 11:59:12.949284 DQ_AAMCK_DIV = 4
3785 11:59:12.949785 CA_AAMCK_DIV = 4
3786 11:59:12.952548 CA_ADMCK_DIV = 4
3787 11:59:12.955831 DQ_TRACK_CA_EN = 0
3788 11:59:12.959017 CA_PICK = 600
3789 11:59:12.962494 CA_MCKIO = 600
3790 11:59:12.966048 MCKIO_SEMI = 0
3791 11:59:12.969370 PLL_FREQ = 2288
3792 11:59:12.969963 DQ_UI_PI_RATIO = 32
3793 11:59:12.972442 CA_UI_PI_RATIO = 0
3794 11:59:12.976177 ===================================
3795 11:59:12.979127 ===================================
3796 11:59:12.982312 memory_type:LPDDR4
3797 11:59:12.986178 GP_NUM : 10
3798 11:59:12.986731 SRAM_EN : 1
3799 11:59:12.988909 MD32_EN : 0
3800 11:59:12.992397 ===================================
3801 11:59:12.995982 [ANA_INIT] >>>>>>>>>>>>>>
3802 11:59:12.996536 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 11:59:12.998719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 11:59:13.002308 ===================================
3805 11:59:13.005543 data_rate = 1200,PCW = 0X5800
3806 11:59:13.009308 ===================================
3807 11:59:13.012243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 11:59:13.019555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 11:59:13.025306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 11:59:13.028771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 11:59:13.032431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 11:59:13.035533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 11:59:13.038749 [ANA_INIT] flow start
3814 11:59:13.039219 [ANA_INIT] PLL >>>>>>>>
3815 11:59:13.042314 [ANA_INIT] PLL <<<<<<<<
3816 11:59:13.045130 [ANA_INIT] MIDPI >>>>>>>>
3817 11:59:13.045663 [ANA_INIT] MIDPI <<<<<<<<
3818 11:59:13.048631 [ANA_INIT] DLL >>>>>>>>
3819 11:59:13.052349 [ANA_INIT] flow end
3820 11:59:13.055387 ============ LP4 DIFF to SE enter ============
3821 11:59:13.058367 ============ LP4 DIFF to SE exit ============
3822 11:59:13.062181 [ANA_INIT] <<<<<<<<<<<<<
3823 11:59:13.065233 [Flow] Enable top DCM control >>>>>
3824 11:59:13.068692 [Flow] Enable top DCM control <<<<<
3825 11:59:13.072028 Enable DLL master slave shuffle
3826 11:59:13.075627 ==============================================================
3827 11:59:13.078537 Gating Mode config
3828 11:59:13.085573 ==============================================================
3829 11:59:13.086172 Config description:
3830 11:59:13.095376 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 11:59:13.102492 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 11:59:13.108543 SELPH_MODE 0: By rank 1: By Phase
3833 11:59:13.111732 ==============================================================
3834 11:59:13.114910 GAT_TRACK_EN = 1
3835 11:59:13.119176 RX_GATING_MODE = 2
3836 11:59:13.121794 RX_GATING_TRACK_MODE = 2
3837 11:59:13.125056 SELPH_MODE = 1
3838 11:59:13.128662 PICG_EARLY_EN = 1
3839 11:59:13.132188 VALID_LAT_VALUE = 1
3840 11:59:13.135084 ==============================================================
3841 11:59:13.138514 Enter into Gating configuration >>>>
3842 11:59:13.141422 Exit from Gating configuration <<<<
3843 11:59:13.144763 Enter into DVFS_PRE_config >>>>>
3844 11:59:13.158257 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 11:59:13.161724 Exit from DVFS_PRE_config <<<<<
3846 11:59:13.162197 Enter into PICG configuration >>>>
3847 11:59:13.164988 Exit from PICG configuration <<<<
3848 11:59:13.168734 [RX_INPUT] configuration >>>>>
3849 11:59:13.171502 [RX_INPUT] configuration <<<<<
3850 11:59:13.178382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 11:59:13.181571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 11:59:13.188315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 11:59:13.195244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 11:59:13.201531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 11:59:13.207951 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 11:59:13.211073 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 11:59:13.214653 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 11:59:13.217660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 11:59:13.224858 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 11:59:13.228187 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 11:59:13.231521 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 11:59:13.234316 ===================================
3863 11:59:13.237958 LPDDR4 DRAM CONFIGURATION
3864 11:59:13.241343 ===================================
3865 11:59:13.244217 EX_ROW_EN[0] = 0x0
3866 11:59:13.244675 EX_ROW_EN[1] = 0x0
3867 11:59:13.248185 LP4Y_EN = 0x0
3868 11:59:13.248640 WORK_FSP = 0x0
3869 11:59:13.251819 WL = 0x2
3870 11:59:13.252369 RL = 0x2
3871 11:59:13.254320 BL = 0x2
3872 11:59:13.254774 RPST = 0x0
3873 11:59:13.258318 RD_PRE = 0x0
3874 11:59:13.258873 WR_PRE = 0x1
3875 11:59:13.261161 WR_PST = 0x0
3876 11:59:13.261633 DBI_WR = 0x0
3877 11:59:13.264987 DBI_RD = 0x0
3878 11:59:13.265697 OTF = 0x1
3879 11:59:13.267730 ===================================
3880 11:59:13.270937 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 11:59:13.277957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 11:59:13.281332 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 11:59:13.284958 ===================================
3884 11:59:13.287644 LPDDR4 DRAM CONFIGURATION
3885 11:59:13.291568 ===================================
3886 11:59:13.292141 EX_ROW_EN[0] = 0x10
3887 11:59:13.294996 EX_ROW_EN[1] = 0x0
3888 11:59:13.297719 LP4Y_EN = 0x0
3889 11:59:13.298284 WORK_FSP = 0x0
3890 11:59:13.301148 WL = 0x2
3891 11:59:13.301826 RL = 0x2
3892 11:59:13.304219 BL = 0x2
3893 11:59:13.304777 RPST = 0x0
3894 11:59:13.308018 RD_PRE = 0x0
3895 11:59:13.308587 WR_PRE = 0x1
3896 11:59:13.310654 WR_PST = 0x0
3897 11:59:13.311293 DBI_WR = 0x0
3898 11:59:13.313794 DBI_RD = 0x0
3899 11:59:13.314418 OTF = 0x1
3900 11:59:13.317302 ===================================
3901 11:59:13.323820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 11:59:13.328678 nWR fixed to 30
3903 11:59:13.331939 [ModeRegInit_LP4] CH0 RK0
3904 11:59:13.332482 [ModeRegInit_LP4] CH0 RK1
3905 11:59:13.335269 [ModeRegInit_LP4] CH1 RK0
3906 11:59:13.338264 [ModeRegInit_LP4] CH1 RK1
3907 11:59:13.338681 match AC timing 17
3908 11:59:13.345149 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 11:59:13.348542 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 11:59:13.351697 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 11:59:13.358665 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 11:59:13.362257 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 11:59:13.362804 ==
3914 11:59:13.365294 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 11:59:13.368246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 11:59:13.368704 ==
3917 11:59:13.375231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 11:59:13.382297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3919 11:59:13.385126 [CA 0] Center 35 (5~66) winsize 62
3920 11:59:13.388843 [CA 1] Center 35 (5~66) winsize 62
3921 11:59:13.391890 [CA 2] Center 33 (3~64) winsize 62
3922 11:59:13.395633 [CA 3] Center 33 (2~64) winsize 63
3923 11:59:13.398573 [CA 4] Center 33 (2~64) winsize 63
3924 11:59:13.402194 [CA 5] Center 32 (1~63) winsize 63
3925 11:59:13.402648
3926 11:59:13.405255 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3927 11:59:13.405798
3928 11:59:13.408808 [CATrainingPosCal] consider 1 rank data
3929 11:59:13.412279 u2DelayCellTimex100 = 270/100 ps
3930 11:59:13.415156 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3931 11:59:13.418292 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3932 11:59:13.421884 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3933 11:59:13.424919 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3934 11:59:13.428992 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3935 11:59:13.431806 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
3936 11:59:13.432426
3937 11:59:13.438803 CA PerBit enable=1, Macro0, CA PI delay=32
3938 11:59:13.439352
3939 11:59:13.441423 [CBTSetCACLKResult] CA Dly = 32
3940 11:59:13.441917 CS Dly: 4 (0~35)
3941 11:59:13.442280 ==
3942 11:59:13.445038 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 11:59:13.448268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 11:59:13.448789 ==
3945 11:59:13.455008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 11:59:13.461674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 11:59:13.464810 [CA 0] Center 35 (5~66) winsize 62
3948 11:59:13.468925 [CA 1] Center 35 (5~66) winsize 62
3949 11:59:13.471437 [CA 2] Center 33 (3~64) winsize 62
3950 11:59:13.474601 [CA 3] Center 33 (3~64) winsize 62
3951 11:59:13.477893 [CA 4] Center 32 (2~63) winsize 62
3952 11:59:13.482076 [CA 5] Center 32 (2~63) winsize 62
3953 11:59:13.482626
3954 11:59:13.485057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 11:59:13.485654
3956 11:59:13.487970 [CATrainingPosCal] consider 2 rank data
3957 11:59:13.491552 u2DelayCellTimex100 = 270/100 ps
3958 11:59:13.494601 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3959 11:59:13.498001 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3960 11:59:13.501357 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3961 11:59:13.505146 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3962 11:59:13.507931 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3963 11:59:13.514684 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3964 11:59:13.515163
3965 11:59:13.517755 CA PerBit enable=1, Macro0, CA PI delay=32
3966 11:59:13.518219
3967 11:59:13.521181 [CBTSetCACLKResult] CA Dly = 32
3968 11:59:13.521694 CS Dly: 4 (0~36)
3969 11:59:13.522072
3970 11:59:13.524811 ----->DramcWriteLeveling(PI) begin...
3971 11:59:13.525234 ==
3972 11:59:13.527511 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 11:59:13.534296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 11:59:13.534814 ==
3975 11:59:13.538062 Write leveling (Byte 0): 34 => 34
3976 11:59:13.538481 Write leveling (Byte 1): 32 => 32
3977 11:59:13.541112 DramcWriteLeveling(PI) end<-----
3978 11:59:13.541530
3979 11:59:13.541910 ==
3980 11:59:13.544658 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 11:59:13.551098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 11:59:13.551567 ==
3983 11:59:13.554361 [Gating] SW mode calibration
3984 11:59:13.561450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 11:59:13.564476 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 11:59:13.571194 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 11:59:13.574489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 11:59:13.577714 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 11:59:13.584777 0 9 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 1)
3990 11:59:13.587942 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
3991 11:59:13.590945 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 11:59:13.594588 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:59:13.600857 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:59:13.604066 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 11:59:13.607714 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 11:59:13.614172 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3997 11:59:13.617443 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3998 11:59:13.620909 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3999 11:59:13.627423 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:59:13.630914 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:59:13.634195 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:59:13.640831 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:59:13.644092 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 11:59:13.647230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 11:59:13.653933 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 11:59:13.657149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4007 11:59:13.660988 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:59:13.667402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:59:13.670527 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:59:13.674272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:59:13.680602 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:59:13.684258 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:59:13.687225 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:59:13.694040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:59:13.697461 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:59:13.700744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:59:13.706761 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:59:13.710641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:59:13.713831 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:59:13.720795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:59:13.724084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4022 11:59:13.727176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4023 11:59:13.731073 Total UI for P1: 0, mck2ui 16
4024 11:59:13.733777 best dqsien dly found for B0: ( 0, 13, 12)
4025 11:59:13.736958 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 11:59:13.740361 Total UI for P1: 0, mck2ui 16
4027 11:59:13.743335 best dqsien dly found for B1: ( 0, 13, 18)
4028 11:59:13.750270 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4029 11:59:13.753681 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4030 11:59:13.754126
4031 11:59:13.756948 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4032 11:59:13.760181 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4033 11:59:13.763927 [Gating] SW calibration Done
4034 11:59:13.764353 ==
4035 11:59:13.766686 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 11:59:13.770166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 11:59:13.770700 ==
4038 11:59:13.773655 RX Vref Scan: 0
4039 11:59:13.774065
4040 11:59:13.774389 RX Vref 0 -> 0, step: 1
4041 11:59:13.774691
4042 11:59:13.776775 RX Delay -230 -> 252, step: 16
4043 11:59:13.780668 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4044 11:59:13.787332 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4045 11:59:13.790255 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4046 11:59:13.793567 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4047 11:59:13.797254 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4048 11:59:13.800517 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4049 11:59:13.806984 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4050 11:59:13.810321 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4051 11:59:13.813790 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4052 11:59:13.816775 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4053 11:59:13.820871 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4054 11:59:13.827423 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4055 11:59:13.830313 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4056 11:59:13.834348 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4057 11:59:13.837162 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4058 11:59:13.843662 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4059 11:59:13.844198 ==
4060 11:59:13.846832 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 11:59:13.850363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 11:59:13.850819 ==
4063 11:59:13.851175 DQS Delay:
4064 11:59:13.854318 DQS0 = 0, DQS1 = 0
4065 11:59:13.854877 DQM Delay:
4066 11:59:13.857475 DQM0 = 54, DQM1 = 46
4067 11:59:13.858063 DQ Delay:
4068 11:59:13.860931 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4069 11:59:13.863617 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4070 11:59:13.867214 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4071 11:59:13.870948 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4072 11:59:13.871514
4073 11:59:13.871878
4074 11:59:13.872209 ==
4075 11:59:13.873500 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 11:59:13.877059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 11:59:13.880456 ==
4078 11:59:13.880957
4079 11:59:13.881315
4080 11:59:13.881679 TX Vref Scan disable
4081 11:59:13.883824 == TX Byte 0 ==
4082 11:59:13.886822 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4083 11:59:13.890568 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4084 11:59:13.893766 == TX Byte 1 ==
4085 11:59:13.896584 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4086 11:59:13.900353 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4087 11:59:13.903650 ==
4088 11:59:13.904198 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 11:59:13.910412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 11:59:13.910964 ==
4091 11:59:13.911322
4092 11:59:13.911651
4093 11:59:13.913138 TX Vref Scan disable
4094 11:59:13.913845 == TX Byte 0 ==
4095 11:59:13.920324 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4096 11:59:13.923539 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4097 11:59:13.923950 == TX Byte 1 ==
4098 11:59:13.930074 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4099 11:59:13.933233 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4100 11:59:13.933857
4101 11:59:13.934325 [DATLAT]
4102 11:59:13.936528 Freq=600, CH0 RK0
4103 11:59:13.937060
4104 11:59:13.937625 DATLAT Default: 0x9
4105 11:59:13.939689 0, 0xFFFF, sum = 0
4106 11:59:13.940222 1, 0xFFFF, sum = 0
4107 11:59:13.943395 2, 0xFFFF, sum = 0
4108 11:59:13.943810 3, 0xFFFF, sum = 0
4109 11:59:13.946579 4, 0xFFFF, sum = 0
4110 11:59:13.946993 5, 0xFFFF, sum = 0
4111 11:59:13.950074 6, 0xFFFF, sum = 0
4112 11:59:13.950492 7, 0xFFFF, sum = 0
4113 11:59:13.953543 8, 0x0, sum = 1
4114 11:59:13.954000 9, 0x0, sum = 2
4115 11:59:13.956888 10, 0x0, sum = 3
4116 11:59:13.957302 11, 0x0, sum = 4
4117 11:59:13.959923 best_step = 9
4118 11:59:13.960346
4119 11:59:13.960666 ==
4120 11:59:13.963410 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:59:13.966919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:59:13.967657 ==
4123 11:59:13.970028 RX Vref Scan: 1
4124 11:59:13.970558
4125 11:59:13.970952 RX Vref 0 -> 0, step: 1
4126 11:59:13.971420
4127 11:59:13.973212 RX Delay -163 -> 252, step: 8
4128 11:59:13.973707
4129 11:59:13.976430 Set Vref, RX VrefLevel [Byte0]: 53
4130 11:59:13.979490 [Byte1]: 50
4131 11:59:13.983442
4132 11:59:13.983849 Final RX Vref Byte 0 = 53 to rank0
4133 11:59:13.986826 Final RX Vref Byte 1 = 50 to rank0
4134 11:59:13.990647 Final RX Vref Byte 0 = 53 to rank1
4135 11:59:13.993207 Final RX Vref Byte 1 = 50 to rank1==
4136 11:59:13.996809 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 11:59:14.003769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 11:59:14.004373 ==
4139 11:59:14.004885 DQS Delay:
4140 11:59:14.005259 DQS0 = 0, DQS1 = 0
4141 11:59:14.007024 DQM Delay:
4142 11:59:14.007575 DQM0 = 53, DQM1 = 46
4143 11:59:14.009800 DQ Delay:
4144 11:59:14.013078 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4145 11:59:14.016423 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4146 11:59:14.019948 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4147 11:59:14.022898 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4148 11:59:14.023510
4149 11:59:14.024092
4150 11:59:14.030214 [DQSOSCAuto] RK0, (LSB)MR18= 0x7265, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4151 11:59:14.033352 CH0 RK0: MR19=808, MR18=7265
4152 11:59:14.040160 CH0_RK0: MR19=0x808, MR18=0x7265, DQSOSC=388, MR23=63, INC=174, DEC=116
4153 11:59:14.040772
4154 11:59:14.043188 ----->DramcWriteLeveling(PI) begin...
4155 11:59:14.043724 ==
4156 11:59:14.046393 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 11:59:14.049864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 11:59:14.050404 ==
4159 11:59:14.053003 Write leveling (Byte 0): 35 => 35
4160 11:59:14.056866 Write leveling (Byte 1): 31 => 31
4161 11:59:14.059979 DramcWriteLeveling(PI) end<-----
4162 11:59:14.060386
4163 11:59:14.060704 ==
4164 11:59:14.063117 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 11:59:14.066760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 11:59:14.067175 ==
4167 11:59:14.069873 [Gating] SW mode calibration
4168 11:59:14.076277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4169 11:59:14.083620 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4170 11:59:14.086715 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 11:59:14.090072 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 11:59:14.096324 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 11:59:14.099909 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4174 11:59:14.103004 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (1 1) (1 0)
4175 11:59:14.109432 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:59:14.112918 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 11:59:14.116450 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 11:59:14.122794 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 11:59:14.126769 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 11:59:14.129501 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 11:59:14.136206 0 10 12 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4182 11:59:14.139562 0 10 16 | B1->B0 | 4040 4545 | 0 1 | (0 0) (0 0)
4183 11:59:14.143136 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:59:14.149459 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:59:14.152740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:59:14.156227 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 11:59:14.163095 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 11:59:14.166221 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 11:59:14.169814 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4190 11:59:14.176026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4191 11:59:14.179055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:59:14.182800 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:59:14.189448 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:59:14.192473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:59:14.196238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:59:14.202740 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:59:14.205932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:59:14.209293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:59:14.212852 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:59:14.219866 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:59:14.222933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:59:14.225910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:59:14.232822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:59:14.236185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 11:59:14.239179 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4206 11:59:14.245815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 11:59:14.248948 Total UI for P1: 0, mck2ui 16
4208 11:59:14.252672 best dqsien dly found for B0: ( 0, 13, 12)
4209 11:59:14.255910 Total UI for P1: 0, mck2ui 16
4210 11:59:14.259364 best dqsien dly found for B1: ( 0, 13, 14)
4211 11:59:14.262543 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4212 11:59:14.266149 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4213 11:59:14.266539
4214 11:59:14.269156 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4215 11:59:14.272398 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4216 11:59:14.275561 [Gating] SW calibration Done
4217 11:59:14.276118 ==
4218 11:59:14.279342 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 11:59:14.282692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 11:59:14.283116 ==
4221 11:59:14.285984 RX Vref Scan: 0
4222 11:59:14.286389
4223 11:59:14.288836 RX Vref 0 -> 0, step: 1
4224 11:59:14.289431
4225 11:59:14.289897 RX Delay -230 -> 252, step: 16
4226 11:59:14.295799 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4227 11:59:14.298815 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4228 11:59:14.302625 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4229 11:59:14.305615 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4230 11:59:14.311882 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4231 11:59:14.315491 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4232 11:59:14.318342 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4233 11:59:14.321728 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4234 11:59:14.325355 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4235 11:59:14.332001 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4236 11:59:14.334951 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4237 11:59:14.338667 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4238 11:59:14.341801 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4239 11:59:14.348409 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4240 11:59:14.351821 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4241 11:59:14.355450 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4242 11:59:14.355530 ==
4243 11:59:14.358225 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 11:59:14.361690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 11:59:14.361771 ==
4246 11:59:14.365269 DQS Delay:
4247 11:59:14.365349 DQS0 = 0, DQS1 = 0
4248 11:59:14.368465 DQM Delay:
4249 11:59:14.368545 DQM0 = 53, DQM1 = 42
4250 11:59:14.368608 DQ Delay:
4251 11:59:14.371711 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4252 11:59:14.375587 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4253 11:59:14.378291 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4254 11:59:14.381544 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4255 11:59:14.381661
4256 11:59:14.381724
4257 11:59:14.385082 ==
4258 11:59:14.388579 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:59:14.391763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:59:14.391846 ==
4261 11:59:14.391930
4262 11:59:14.392009
4263 11:59:14.394733 TX Vref Scan disable
4264 11:59:14.394815 == TX Byte 0 ==
4265 11:59:14.401400 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4266 11:59:14.404958 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4267 11:59:14.405041 == TX Byte 1 ==
4268 11:59:14.411543 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 11:59:14.415164 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 11:59:14.415248 ==
4271 11:59:14.418079 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 11:59:14.421421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 11:59:14.421505 ==
4274 11:59:14.421640
4275 11:59:14.421720
4276 11:59:14.424607 TX Vref Scan disable
4277 11:59:14.428067 == TX Byte 0 ==
4278 11:59:14.431258 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4279 11:59:14.434707 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4280 11:59:14.438100 == TX Byte 1 ==
4281 11:59:14.441181 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 11:59:14.444859 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 11:59:14.444941
4284 11:59:14.448023 [DATLAT]
4285 11:59:14.448132 Freq=600, CH0 RK1
4286 11:59:14.448218
4287 11:59:14.451178 DATLAT Default: 0x9
4288 11:59:14.451260 0, 0xFFFF, sum = 0
4289 11:59:14.454899 1, 0xFFFF, sum = 0
4290 11:59:14.454983 2, 0xFFFF, sum = 0
4291 11:59:14.457900 3, 0xFFFF, sum = 0
4292 11:59:14.457984 4, 0xFFFF, sum = 0
4293 11:59:14.461279 5, 0xFFFF, sum = 0
4294 11:59:14.461362 6, 0xFFFF, sum = 0
4295 11:59:14.464423 7, 0xFFFF, sum = 0
4296 11:59:14.464506 8, 0x0, sum = 1
4297 11:59:14.467594 9, 0x0, sum = 2
4298 11:59:14.467677 10, 0x0, sum = 3
4299 11:59:14.471292 11, 0x0, sum = 4
4300 11:59:14.471396 best_step = 9
4301 11:59:14.471484
4302 11:59:14.471567 ==
4303 11:59:14.474407 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:59:14.481295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:59:14.481400 ==
4306 11:59:14.481490 RX Vref Scan: 0
4307 11:59:14.481590
4308 11:59:14.484563 RX Vref 0 -> 0, step: 1
4309 11:59:14.484642
4310 11:59:14.488068 RX Delay -179 -> 252, step: 8
4311 11:59:14.491285 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4312 11:59:14.494480 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4313 11:59:14.500790 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4314 11:59:14.504537 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4315 11:59:14.507697 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4316 11:59:14.510743 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4317 11:59:14.514124 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4318 11:59:14.521148 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4319 11:59:14.524043 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4320 11:59:14.527889 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4321 11:59:14.530744 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4322 11:59:14.537875 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4323 11:59:14.540817 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4324 11:59:14.543912 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4325 11:59:14.547491 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4326 11:59:14.550580 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4327 11:59:14.553898 ==
4328 11:59:14.553977 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 11:59:14.560894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 11:59:14.560973 ==
4331 11:59:14.561035 DQS Delay:
4332 11:59:14.563991 DQS0 = 0, DQS1 = 0
4333 11:59:14.564070 DQM Delay:
4334 11:59:14.567628 DQM0 = 53, DQM1 = 46
4335 11:59:14.567707 DQ Delay:
4336 11:59:14.570723 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4337 11:59:14.574465 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4338 11:59:14.577522 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4339 11:59:14.580648 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4340 11:59:14.580731
4341 11:59:14.580792
4342 11:59:14.587595 [DQSOSCAuto] RK1, (LSB)MR18= 0x6121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4343 11:59:14.590906 CH0 RK1: MR19=808, MR18=6121
4344 11:59:14.597508 CH0_RK1: MR19=0x808, MR18=0x6121, DQSOSC=391, MR23=63, INC=171, DEC=114
4345 11:59:14.600916 [RxdqsGatingPostProcess] freq 600
4346 11:59:14.604405 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4347 11:59:14.607118 Pre-setting of DQS Precalculation
4348 11:59:14.614563 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4349 11:59:14.614645 ==
4350 11:59:14.617052 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 11:59:14.620551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 11:59:14.620636 ==
4353 11:59:14.627000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 11:59:14.634166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4355 11:59:14.637163 [CA 0] Center 35 (5~66) winsize 62
4356 11:59:14.640482 [CA 1] Center 35 (5~66) winsize 62
4357 11:59:14.644123 [CA 2] Center 34 (4~65) winsize 62
4358 11:59:14.647562 [CA 3] Center 34 (4~65) winsize 62
4359 11:59:14.650497 [CA 4] Center 34 (4~65) winsize 62
4360 11:59:14.653806 [CA 5] Center 33 (3~64) winsize 62
4361 11:59:14.653888
4362 11:59:14.657081 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4363 11:59:14.657164
4364 11:59:14.661137 [CATrainingPosCal] consider 1 rank data
4365 11:59:14.663910 u2DelayCellTimex100 = 270/100 ps
4366 11:59:14.667337 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 11:59:14.670575 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4368 11:59:14.673594 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4369 11:59:14.677385 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4370 11:59:14.680402 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 11:59:14.683444 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4372 11:59:14.683527
4373 11:59:14.690364 CA PerBit enable=1, Macro0, CA PI delay=33
4374 11:59:14.690447
4375 11:59:14.690530 [CBTSetCACLKResult] CA Dly = 33
4376 11:59:14.693509 CS Dly: 6 (0~37)
4377 11:59:14.693618 ==
4378 11:59:14.696891 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 11:59:14.700018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 11:59:14.700100 ==
4381 11:59:14.706748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 11:59:14.713697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4383 11:59:14.717193 [CA 0] Center 36 (5~67) winsize 63
4384 11:59:14.720145 [CA 1] Center 36 (5~67) winsize 63
4385 11:59:14.723315 [CA 2] Center 34 (4~65) winsize 62
4386 11:59:14.726602 [CA 3] Center 34 (4~65) winsize 62
4387 11:59:14.730194 [CA 4] Center 34 (4~65) winsize 62
4388 11:59:14.733329 [CA 5] Center 34 (4~65) winsize 62
4389 11:59:14.733410
4390 11:59:14.736783 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4391 11:59:14.736865
4392 11:59:14.739801 [CATrainingPosCal] consider 2 rank data
4393 11:59:14.743508 u2DelayCellTimex100 = 270/100 ps
4394 11:59:14.746911 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4395 11:59:14.749721 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4396 11:59:14.753296 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 11:59:14.756727 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 11:59:14.759996 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 11:59:14.763227 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4400 11:59:14.766133
4401 11:59:14.769985 CA PerBit enable=1, Macro0, CA PI delay=34
4402 11:59:14.770065
4403 11:59:14.773073 [CBTSetCACLKResult] CA Dly = 34
4404 11:59:14.773153 CS Dly: 6 (0~37)
4405 11:59:14.773217
4406 11:59:14.776219 ----->DramcWriteLeveling(PI) begin...
4407 11:59:14.776303 ==
4408 11:59:14.779595 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 11:59:14.782642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 11:59:14.786588 ==
4411 11:59:14.786668 Write leveling (Byte 0): 30 => 30
4412 11:59:14.789700 Write leveling (Byte 1): 30 => 30
4413 11:59:14.792825 DramcWriteLeveling(PI) end<-----
4414 11:59:14.792905
4415 11:59:14.792968 ==
4416 11:59:14.796576 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 11:59:14.802916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 11:59:14.802999 ==
4419 11:59:14.803063 [Gating] SW mode calibration
4420 11:59:14.812914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4421 11:59:14.816492 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4422 11:59:14.822818 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 11:59:14.826521 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 11:59:14.829545 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 11:59:14.832609 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (1 1) (1 1)
4426 11:59:14.839432 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:59:14.843193 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 11:59:14.846211 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 11:59:14.852757 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 11:59:14.855977 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 11:59:14.859436 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 11:59:14.866185 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 11:59:14.869444 0 10 12 | B1->B0 | 3737 3939 | 1 0 | (0 0) (0 0)
4434 11:59:14.872870 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:59:14.879094 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:59:14.882809 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:59:14.885772 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:59:14.892860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 11:59:14.896132 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 11:59:14.899188 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4441 11:59:14.906225 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4442 11:59:14.909371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4443 11:59:14.912307 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:59:14.919105 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:59:14.922630 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:59:14.926088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:59:14.932649 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:59:14.935923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:59:14.939409 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:59:14.946054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:59:14.949057 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:59:14.952424 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:59:14.955614 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:59:14.962292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 11:59:14.965837 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 11:59:14.969391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:59:14.975797 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4458 11:59:14.978898 Total UI for P1: 0, mck2ui 16
4459 11:59:14.982438 best dqsien dly found for B1: ( 0, 13, 10)
4460 11:59:14.985422 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 11:59:14.988868 Total UI for P1: 0, mck2ui 16
4462 11:59:14.992295 best dqsien dly found for B0: ( 0, 13, 12)
4463 11:59:14.995520 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4464 11:59:14.999041 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4465 11:59:14.999121
4466 11:59:15.002372 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4467 11:59:15.009156 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4468 11:59:15.009236 [Gating] SW calibration Done
4469 11:59:15.009300 ==
4470 11:59:15.012275 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 11:59:15.019230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 11:59:15.019311 ==
4473 11:59:15.019374 RX Vref Scan: 0
4474 11:59:15.019433
4475 11:59:15.021998 RX Vref 0 -> 0, step: 1
4476 11:59:15.022080
4477 11:59:15.025414 RX Delay -230 -> 252, step: 16
4478 11:59:15.028682 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4479 11:59:15.032177 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4480 11:59:15.035483 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4481 11:59:15.042152 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4482 11:59:15.045165 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4483 11:59:15.048926 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4484 11:59:15.051772 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4485 11:59:15.058710 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4486 11:59:15.061939 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4487 11:59:15.065111 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4488 11:59:15.068521 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4489 11:59:15.075395 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4490 11:59:15.078409 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4491 11:59:15.081651 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4492 11:59:15.085351 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4493 11:59:15.088852 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4494 11:59:15.091854 ==
4495 11:59:15.091938 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 11:59:15.098608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 11:59:15.098690 ==
4498 11:59:15.098774 DQS Delay:
4499 11:59:15.102343 DQS0 = 0, DQS1 = 0
4500 11:59:15.102424 DQM Delay:
4501 11:59:15.102517 DQM0 = 50, DQM1 = 46
4502 11:59:15.105256 DQ Delay:
4503 11:59:15.108762 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4504 11:59:15.112114 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4505 11:59:15.115709 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4506 11:59:15.118829 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4507 11:59:15.118911
4508 11:59:15.118994
4509 11:59:15.119072 ==
4510 11:59:15.122003 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 11:59:15.125049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 11:59:15.125162 ==
4513 11:59:15.125262
4514 11:59:15.125358
4515 11:59:15.128789 TX Vref Scan disable
4516 11:59:15.131896 == TX Byte 0 ==
4517 11:59:15.135339 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 11:59:15.138420 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 11:59:15.141699 == TX Byte 1 ==
4520 11:59:15.145341 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 11:59:15.148497 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 11:59:15.148602 ==
4523 11:59:15.151864 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 11:59:15.155245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 11:59:15.158024 ==
4526 11:59:15.158104
4527 11:59:15.158165
4528 11:59:15.158222 TX Vref Scan disable
4529 11:59:15.162439 == TX Byte 0 ==
4530 11:59:15.165661 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4531 11:59:15.172578 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4532 11:59:15.172661 == TX Byte 1 ==
4533 11:59:15.175985 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 11:59:15.182170 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 11:59:15.182252
4536 11:59:15.182315 [DATLAT]
4537 11:59:15.182374 Freq=600, CH1 RK0
4538 11:59:15.182431
4539 11:59:15.185720 DATLAT Default: 0x9
4540 11:59:15.185801 0, 0xFFFF, sum = 0
4541 11:59:15.189138 1, 0xFFFF, sum = 0
4542 11:59:15.189219 2, 0xFFFF, sum = 0
4543 11:59:15.192144 3, 0xFFFF, sum = 0
4544 11:59:15.195775 4, 0xFFFF, sum = 0
4545 11:59:15.195857 5, 0xFFFF, sum = 0
4546 11:59:15.198813 6, 0xFFFF, sum = 0
4547 11:59:15.198895 7, 0xFFFF, sum = 0
4548 11:59:15.201885 8, 0x0, sum = 1
4549 11:59:15.201967 9, 0x0, sum = 2
4550 11:59:15.202031 10, 0x0, sum = 3
4551 11:59:15.205304 11, 0x0, sum = 4
4552 11:59:15.205385 best_step = 9
4553 11:59:15.205448
4554 11:59:15.205507 ==
4555 11:59:15.208854 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:59:15.215302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:59:15.215382 ==
4558 11:59:15.215445 RX Vref Scan: 1
4559 11:59:15.215503
4560 11:59:15.218817 RX Vref 0 -> 0, step: 1
4561 11:59:15.218896
4562 11:59:15.221889 RX Delay -163 -> 252, step: 8
4563 11:59:15.221971
4564 11:59:15.225117 Set Vref, RX VrefLevel [Byte0]: 56
4565 11:59:15.228952 [Byte1]: 53
4566 11:59:15.229032
4567 11:59:15.232182 Final RX Vref Byte 0 = 56 to rank0
4568 11:59:15.235391 Final RX Vref Byte 1 = 53 to rank0
4569 11:59:15.238945 Final RX Vref Byte 0 = 56 to rank1
4570 11:59:15.242054 Final RX Vref Byte 1 = 53 to rank1==
4571 11:59:15.245014 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 11:59:15.248812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 11:59:15.248892 ==
4574 11:59:15.251676 DQS Delay:
4575 11:59:15.251756 DQS0 = 0, DQS1 = 0
4576 11:59:15.251822 DQM Delay:
4577 11:59:15.255086 DQM0 = 48, DQM1 = 45
4578 11:59:15.255166 DQ Delay:
4579 11:59:15.258565 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4580 11:59:15.262129 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4581 11:59:15.265589 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4582 11:59:15.268781 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4583 11:59:15.268866
4584 11:59:15.268930
4585 11:59:15.278565 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4586 11:59:15.281865 CH1 RK0: MR19=808, MR18=456A
4587 11:59:15.285214 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4588 11:59:15.285319
4589 11:59:15.288427 ----->DramcWriteLeveling(PI) begin...
4590 11:59:15.291636 ==
4591 11:59:15.295679 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 11:59:15.298245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 11:59:15.298352 ==
4594 11:59:15.301545 Write leveling (Byte 0): 29 => 29
4595 11:59:15.304830 Write leveling (Byte 1): 30 => 30
4596 11:59:15.308376 DramcWriteLeveling(PI) end<-----
4597 11:59:15.308458
4598 11:59:15.308541 ==
4599 11:59:15.311605 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 11:59:15.315505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 11:59:15.315587 ==
4602 11:59:15.318461 [Gating] SW mode calibration
4603 11:59:15.325237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 11:59:15.331519 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 11:59:15.335066 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 11:59:15.338532 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 11:59:15.344652 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4608 11:59:15.348154 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (0 1)
4609 11:59:15.351447 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 11:59:15.355110 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 11:59:15.361476 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 11:59:15.364725 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 11:59:15.368248 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 11:59:15.374720 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 11:59:15.378259 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4616 11:59:15.381399 0 10 12 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (1 1)
4617 11:59:15.388138 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:59:15.391287 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 11:59:15.394922 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 11:59:15.401561 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 11:59:15.404539 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 11:59:15.408117 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 11:59:15.414699 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 11:59:15.418263 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:59:15.421482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:59:15.428287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:59:15.431235 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:59:15.434830 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:59:15.441098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:59:15.444653 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:59:15.448220 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:59:15.454541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:59:15.458056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:59:15.461489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:59:15.467523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:59:15.471325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:59:15.474634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:59:15.481307 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:59:15.484253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4640 11:59:15.487406 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 11:59:15.491060 Total UI for P1: 0, mck2ui 16
4642 11:59:15.494199 best dqsien dly found for B0: ( 0, 13, 10)
4643 11:59:15.497479 Total UI for P1: 0, mck2ui 16
4644 11:59:15.500997 best dqsien dly found for B1: ( 0, 13, 8)
4645 11:59:15.504404 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4646 11:59:15.507272 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4647 11:59:15.507351
4648 11:59:15.510769 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4649 11:59:15.517482 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4650 11:59:15.517564 [Gating] SW calibration Done
4651 11:59:15.517668 ==
4652 11:59:15.521185 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 11:59:15.527420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 11:59:15.527503 ==
4655 11:59:15.527568 RX Vref Scan: 0
4656 11:59:15.527628
4657 11:59:15.531092 RX Vref 0 -> 0, step: 1
4658 11:59:15.531172
4659 11:59:15.534180 RX Delay -230 -> 252, step: 16
4660 11:59:15.537242 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4661 11:59:15.540772 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4662 11:59:15.547418 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4663 11:59:15.550833 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4664 11:59:15.553590 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4665 11:59:15.557198 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4666 11:59:15.560207 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4667 11:59:15.567164 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4668 11:59:15.570272 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4669 11:59:15.573777 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4670 11:59:15.577041 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4671 11:59:15.583669 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4672 11:59:15.587040 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4673 11:59:15.590490 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4674 11:59:15.593482 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4675 11:59:15.600388 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4676 11:59:15.600469 ==
4677 11:59:15.603506 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 11:59:15.607289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 11:59:15.607372 ==
4680 11:59:15.607455 DQS Delay:
4681 11:59:15.610315 DQS0 = 0, DQS1 = 0
4682 11:59:15.610397 DQM Delay:
4683 11:59:15.613495 DQM0 = 49, DQM1 = 48
4684 11:59:15.613640 DQ Delay:
4685 11:59:15.617225 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4686 11:59:15.620305 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4687 11:59:15.623952 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4688 11:59:15.627305 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4689 11:59:15.627389
4690 11:59:15.627472
4691 11:59:15.627550 ==
4692 11:59:15.630557 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 11:59:15.633378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 11:59:15.633485 ==
4695 11:59:15.633609
4696 11:59:15.633703
4697 11:59:15.636786 TX Vref Scan disable
4698 11:59:15.639934 == TX Byte 0 ==
4699 11:59:15.643440 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4700 11:59:15.646614 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4701 11:59:15.650379 == TX Byte 1 ==
4702 11:59:15.653303 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 11:59:15.656875 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 11:59:15.656957 ==
4705 11:59:15.660287 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 11:59:15.666560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 11:59:15.666641 ==
4708 11:59:15.666705
4709 11:59:15.666763
4710 11:59:15.666818 TX Vref Scan disable
4711 11:59:15.671383 == TX Byte 0 ==
4712 11:59:15.674269 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 11:59:15.677806 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 11:59:15.680976 == TX Byte 1 ==
4715 11:59:15.684251 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 11:59:15.690899 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 11:59:15.690980
4718 11:59:15.691042 [DATLAT]
4719 11:59:15.691101 Freq=600, CH1 RK1
4720 11:59:15.691158
4721 11:59:15.694344 DATLAT Default: 0x9
4722 11:59:15.694424 0, 0xFFFF, sum = 0
4723 11:59:15.697894 1, 0xFFFF, sum = 0
4724 11:59:15.697975 2, 0xFFFF, sum = 0
4725 11:59:15.701075 3, 0xFFFF, sum = 0
4726 11:59:15.701156 4, 0xFFFF, sum = 0
4727 11:59:15.704425 5, 0xFFFF, sum = 0
4728 11:59:15.707953 6, 0xFFFF, sum = 0
4729 11:59:15.708035 7, 0xFFFF, sum = 0
4730 11:59:15.708100 8, 0x0, sum = 1
4731 11:59:15.711032 9, 0x0, sum = 2
4732 11:59:15.711113 10, 0x0, sum = 3
4733 11:59:15.714157 11, 0x0, sum = 4
4734 11:59:15.714238 best_step = 9
4735 11:59:15.714300
4736 11:59:15.714359 ==
4737 11:59:15.717662 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 11:59:15.724121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 11:59:15.724206 ==
4740 11:59:15.724270 RX Vref Scan: 0
4741 11:59:15.724329
4742 11:59:15.727470 RX Vref 0 -> 0, step: 1
4743 11:59:15.727550
4744 11:59:15.730840 RX Delay -163 -> 252, step: 8
4745 11:59:15.733968 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4746 11:59:15.740943 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4747 11:59:15.744026 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4748 11:59:15.747674 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4749 11:59:15.750875 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4750 11:59:15.754157 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4751 11:59:15.760607 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4752 11:59:15.764175 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4753 11:59:15.767069 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4754 11:59:15.770942 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4755 11:59:15.774135 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4756 11:59:15.781385 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4757 11:59:15.784165 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4758 11:59:15.787701 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4759 11:59:15.790793 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4760 11:59:15.793996 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4761 11:59:15.797288 ==
4762 11:59:15.800782 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 11:59:15.804385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 11:59:15.804485 ==
4765 11:59:15.804579 DQS Delay:
4766 11:59:15.807521 DQS0 = 0, DQS1 = 0
4767 11:59:15.807619 DQM Delay:
4768 11:59:15.810766 DQM0 = 48, DQM1 = 45
4769 11:59:15.810870 DQ Delay:
4770 11:59:15.813726 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4771 11:59:15.817693 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4772 11:59:15.820445 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4773 11:59:15.823652 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4774 11:59:15.823757
4775 11:59:15.823854
4776 11:59:15.830473 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4777 11:59:15.833675 CH1 RK1: MR19=808, MR18=6D24
4778 11:59:15.840503 CH1_RK1: MR19=0x808, MR18=0x6D24, DQSOSC=389, MR23=63, INC=173, DEC=115
4779 11:59:15.843577 [RxdqsGatingPostProcess] freq 600
4780 11:59:15.850004 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 11:59:15.853967 Pre-setting of DQS Precalculation
4782 11:59:15.856711 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 11:59:15.863357 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 11:59:15.870311 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 11:59:15.870415
4786 11:59:15.870505
4787 11:59:15.873415 [Calibration Summary] 1200 Mbps
4788 11:59:15.876750 CH 0, Rank 0
4789 11:59:15.876850 SW Impedance : PASS
4790 11:59:15.879737 DUTY Scan : NO K
4791 11:59:15.883214 ZQ Calibration : PASS
4792 11:59:15.883316 Jitter Meter : NO K
4793 11:59:15.886737 CBT Training : PASS
4794 11:59:15.890059 Write leveling : PASS
4795 11:59:15.890134 RX DQS gating : PASS
4796 11:59:15.893503 RX DQ/DQS(RDDQC) : PASS
4797 11:59:15.896512 TX DQ/DQS : PASS
4798 11:59:15.896592 RX DATLAT : PASS
4799 11:59:15.899790 RX DQ/DQS(Engine): PASS
4800 11:59:15.899870 TX OE : NO K
4801 11:59:15.903288 All Pass.
4802 11:59:15.903367
4803 11:59:15.903429 CH 0, Rank 1
4804 11:59:15.906387 SW Impedance : PASS
4805 11:59:15.906466 DUTY Scan : NO K
4806 11:59:15.909793 ZQ Calibration : PASS
4807 11:59:15.913766 Jitter Meter : NO K
4808 11:59:15.913845 CBT Training : PASS
4809 11:59:15.916631 Write leveling : PASS
4810 11:59:15.919735 RX DQS gating : PASS
4811 11:59:15.919814 RX DQ/DQS(RDDQC) : PASS
4812 11:59:15.923241 TX DQ/DQS : PASS
4813 11:59:15.926326 RX DATLAT : PASS
4814 11:59:15.926407 RX DQ/DQS(Engine): PASS
4815 11:59:15.930338 TX OE : NO K
4816 11:59:15.930418 All Pass.
4817 11:59:15.930480
4818 11:59:15.933336 CH 1, Rank 0
4819 11:59:15.933415 SW Impedance : PASS
4820 11:59:15.936282 DUTY Scan : NO K
4821 11:59:15.940100 ZQ Calibration : PASS
4822 11:59:15.940180 Jitter Meter : NO K
4823 11:59:15.943315 CBT Training : PASS
4824 11:59:15.943394 Write leveling : PASS
4825 11:59:15.946435 RX DQS gating : PASS
4826 11:59:15.949634 RX DQ/DQS(RDDQC) : PASS
4827 11:59:15.949714 TX DQ/DQS : PASS
4828 11:59:15.953567 RX DATLAT : PASS
4829 11:59:15.956593 RX DQ/DQS(Engine): PASS
4830 11:59:15.956672 TX OE : NO K
4831 11:59:15.959692 All Pass.
4832 11:59:15.959772
4833 11:59:15.959835 CH 1, Rank 1
4834 11:59:15.963409 SW Impedance : PASS
4835 11:59:15.963488 DUTY Scan : NO K
4836 11:59:15.966540 ZQ Calibration : PASS
4837 11:59:15.969412 Jitter Meter : NO K
4838 11:59:15.969491 CBT Training : PASS
4839 11:59:15.972798 Write leveling : PASS
4840 11:59:15.976440 RX DQS gating : PASS
4841 11:59:15.976519 RX DQ/DQS(RDDQC) : PASS
4842 11:59:15.979782 TX DQ/DQS : PASS
4843 11:59:15.983057 RX DATLAT : PASS
4844 11:59:15.983136 RX DQ/DQS(Engine): PASS
4845 11:59:15.986371 TX OE : NO K
4846 11:59:15.986451 All Pass.
4847 11:59:15.986513
4848 11:59:15.989514 DramC Write-DBI off
4849 11:59:15.992957 PER_BANK_REFRESH: Hybrid Mode
4850 11:59:15.993037 TX_TRACKING: ON
4851 11:59:16.002736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 11:59:16.006536 [FAST_K] Save calibration result to emmc
4853 11:59:16.009567 dramc_set_vcore_voltage set vcore to 662500
4854 11:59:16.013227 Read voltage for 933, 3
4855 11:59:16.013306 Vio18 = 0
4856 11:59:16.013369 Vcore = 662500
4857 11:59:16.016192 Vdram = 0
4858 11:59:16.016271 Vddq = 0
4859 11:59:16.016333 Vmddr = 0
4860 11:59:16.022572 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 11:59:16.026256 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 11:59:16.029530 MEM_TYPE=3, freq_sel=17
4863 11:59:16.032577 sv_algorithm_assistance_LP4_1600
4864 11:59:16.036296 ============ PULL DRAM RESETB DOWN ============
4865 11:59:16.039316 ========== PULL DRAM RESETB DOWN end =========
4866 11:59:16.046180 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 11:59:16.049295 ===================================
4868 11:59:16.049407 LPDDR4 DRAM CONFIGURATION
4869 11:59:16.053110 ===================================
4870 11:59:16.056255 EX_ROW_EN[0] = 0x0
4871 11:59:16.059673 EX_ROW_EN[1] = 0x0
4872 11:59:16.059752 LP4Y_EN = 0x0
4873 11:59:16.062825 WORK_FSP = 0x0
4874 11:59:16.062904 WL = 0x3
4875 11:59:16.065868 RL = 0x3
4876 11:59:16.065947 BL = 0x2
4877 11:59:16.069799 RPST = 0x0
4878 11:59:16.069879 RD_PRE = 0x0
4879 11:59:16.072786 WR_PRE = 0x1
4880 11:59:16.072864 WR_PST = 0x0
4881 11:59:16.075903 DBI_WR = 0x0
4882 11:59:16.075982 DBI_RD = 0x0
4883 11:59:16.079702 OTF = 0x1
4884 11:59:16.082558 ===================================
4885 11:59:16.085781 ===================================
4886 11:59:16.085861 ANA top config
4887 11:59:16.089156 ===================================
4888 11:59:16.092478 DLL_ASYNC_EN = 0
4889 11:59:16.095756 ALL_SLAVE_EN = 1
4890 11:59:16.099150 NEW_RANK_MODE = 1
4891 11:59:16.099232 DLL_IDLE_MODE = 1
4892 11:59:16.102427 LP45_APHY_COMB_EN = 1
4893 11:59:16.105903 TX_ODT_DIS = 1
4894 11:59:16.109190 NEW_8X_MODE = 1
4895 11:59:16.112584 ===================================
4896 11:59:16.115535 ===================================
4897 11:59:16.118826 data_rate = 1866
4898 11:59:16.118895 CKR = 1
4899 11:59:16.122638 DQ_P2S_RATIO = 8
4900 11:59:16.125983 ===================================
4901 11:59:16.129315 CA_P2S_RATIO = 8
4902 11:59:16.132561 DQ_CA_OPEN = 0
4903 11:59:16.135797 DQ_SEMI_OPEN = 0
4904 11:59:16.135876 CA_SEMI_OPEN = 0
4905 11:59:16.139176 CA_FULL_RATE = 0
4906 11:59:16.142312 DQ_CKDIV4_EN = 1
4907 11:59:16.145980 CA_CKDIV4_EN = 1
4908 11:59:16.149236 CA_PREDIV_EN = 0
4909 11:59:16.152199 PH8_DLY = 0
4910 11:59:16.152279 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 11:59:16.155973 DQ_AAMCK_DIV = 4
4912 11:59:16.159206 CA_AAMCK_DIV = 4
4913 11:59:16.162604 CA_ADMCK_DIV = 4
4914 11:59:16.165892 DQ_TRACK_CA_EN = 0
4915 11:59:16.168884 CA_PICK = 933
4916 11:59:16.172228 CA_MCKIO = 933
4917 11:59:16.172308 MCKIO_SEMI = 0
4918 11:59:16.175316 PLL_FREQ = 3732
4919 11:59:16.178547 DQ_UI_PI_RATIO = 32
4920 11:59:16.182238 CA_UI_PI_RATIO = 0
4921 11:59:16.185468 ===================================
4922 11:59:16.189128 ===================================
4923 11:59:16.192221 memory_type:LPDDR4
4924 11:59:16.192300 GP_NUM : 10
4925 11:59:16.195496 SRAM_EN : 1
4926 11:59:16.198838 MD32_EN : 0
4927 11:59:16.201834 ===================================
4928 11:59:16.201914 [ANA_INIT] >>>>>>>>>>>>>>
4929 11:59:16.205587 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 11:59:16.208523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 11:59:16.212168 ===================================
4932 11:59:16.215420 data_rate = 1866,PCW = 0X8f00
4933 11:59:16.218786 ===================================
4934 11:59:16.221946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 11:59:16.228419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 11:59:16.232267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 11:59:16.238394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 11:59:16.241585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 11:59:16.245483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 11:59:16.245563 [ANA_INIT] flow start
4941 11:59:16.248039 [ANA_INIT] PLL >>>>>>>>
4942 11:59:16.251463 [ANA_INIT] PLL <<<<<<<<
4943 11:59:16.255142 [ANA_INIT] MIDPI >>>>>>>>
4944 11:59:16.255224 [ANA_INIT] MIDPI <<<<<<<<
4945 11:59:16.258390 [ANA_INIT] DLL >>>>>>>>
4946 11:59:16.261497 [ANA_INIT] flow end
4947 11:59:16.264806 ============ LP4 DIFF to SE enter ============
4948 11:59:16.268525 ============ LP4 DIFF to SE exit ============
4949 11:59:16.271499 [ANA_INIT] <<<<<<<<<<<<<
4950 11:59:16.274656 [Flow] Enable top DCM control >>>>>
4951 11:59:16.278256 [Flow] Enable top DCM control <<<<<
4952 11:59:16.281315 Enable DLL master slave shuffle
4953 11:59:16.285124 ==============================================================
4954 11:59:16.288254 Gating Mode config
4955 11:59:16.291338 ==============================================================
4956 11:59:16.295127 Config description:
4957 11:59:16.304586 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 11:59:16.311148 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 11:59:16.315026 SELPH_MODE 0: By rank 1: By Phase
4960 11:59:16.321500 ==============================================================
4961 11:59:16.324740 GAT_TRACK_EN = 1
4962 11:59:16.328047 RX_GATING_MODE = 2
4963 11:59:16.331032 RX_GATING_TRACK_MODE = 2
4964 11:59:16.334708 SELPH_MODE = 1
4965 11:59:16.337739 PICG_EARLY_EN = 1
4966 11:59:16.337819 VALID_LAT_VALUE = 1
4967 11:59:16.344450 ==============================================================
4968 11:59:16.347955 Enter into Gating configuration >>>>
4969 11:59:16.351172 Exit from Gating configuration <<<<
4970 11:59:16.354869 Enter into DVFS_PRE_config >>>>>
4971 11:59:16.364350 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 11:59:16.368197 Exit from DVFS_PRE_config <<<<<
4973 11:59:16.371428 Enter into PICG configuration >>>>
4974 11:59:16.374588 Exit from PICG configuration <<<<
4975 11:59:16.377504 [RX_INPUT] configuration >>>>>
4976 11:59:16.381227 [RX_INPUT] configuration <<<<<
4977 11:59:16.387572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 11:59:16.391318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 11:59:16.397556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 11:59:16.404521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 11:59:16.411296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 11:59:16.417491 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 11:59:16.420675 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 11:59:16.424328 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 11:59:16.427400 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 11:59:16.434029 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 11:59:16.437532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 11:59:16.440722 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 11:59:16.444188 ===================================
4990 11:59:16.447476 LPDDR4 DRAM CONFIGURATION
4991 11:59:16.450499 ===================================
4992 11:59:16.450609 EX_ROW_EN[0] = 0x0
4993 11:59:16.454159 EX_ROW_EN[1] = 0x0
4994 11:59:16.454239 LP4Y_EN = 0x0
4995 11:59:16.457559 WORK_FSP = 0x0
4996 11:59:16.457678 WL = 0x3
4997 11:59:16.460825 RL = 0x3
4998 11:59:16.460904 BL = 0x2
4999 11:59:16.464383 RPST = 0x0
5000 11:59:16.464463 RD_PRE = 0x0
5001 11:59:16.467561 WR_PRE = 0x1
5002 11:59:16.467639 WR_PST = 0x0
5003 11:59:16.471154 DBI_WR = 0x0
5004 11:59:16.474599 DBI_RD = 0x0
5005 11:59:16.474679 OTF = 0x1
5006 11:59:16.477929 ===================================
5007 11:59:16.481164 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 11:59:16.484552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 11:59:16.491247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 11:59:16.494395 ===================================
5011 11:59:16.497568 LPDDR4 DRAM CONFIGURATION
5012 11:59:16.500768 ===================================
5013 11:59:16.500847 EX_ROW_EN[0] = 0x10
5014 11:59:16.504558 EX_ROW_EN[1] = 0x0
5015 11:59:16.504637 LP4Y_EN = 0x0
5016 11:59:16.507609 WORK_FSP = 0x0
5017 11:59:16.507689 WL = 0x3
5018 11:59:16.510643 RL = 0x3
5019 11:59:16.510748 BL = 0x2
5020 11:59:16.514046 RPST = 0x0
5021 11:59:16.514157 RD_PRE = 0x0
5022 11:59:16.517800 WR_PRE = 0x1
5023 11:59:16.517897 WR_PST = 0x0
5024 11:59:16.520629 DBI_WR = 0x0
5025 11:59:16.520723 DBI_RD = 0x0
5026 11:59:16.524142 OTF = 0x1
5027 11:59:16.527637 ===================================
5028 11:59:16.534118 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 11:59:16.537072 nWR fixed to 30
5030 11:59:16.540722 [ModeRegInit_LP4] CH0 RK0
5031 11:59:16.540819 [ModeRegInit_LP4] CH0 RK1
5032 11:59:16.544125 [ModeRegInit_LP4] CH1 RK0
5033 11:59:16.547415 [ModeRegInit_LP4] CH1 RK1
5034 11:59:16.547516 match AC timing 9
5035 11:59:16.554092 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 11:59:16.557600 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 11:59:16.560724 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 11:59:16.567551 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 11:59:16.570982 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 11:59:16.571078 ==
5041 11:59:16.573864 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 11:59:16.577286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 11:59:16.577355 ==
5044 11:59:16.583714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 11:59:16.590447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5046 11:59:16.594407 [CA 0] Center 37 (6~68) winsize 63
5047 11:59:16.597191 [CA 1] Center 37 (6~68) winsize 63
5048 11:59:16.600209 [CA 2] Center 34 (4~65) winsize 62
5049 11:59:16.603889 [CA 3] Center 34 (3~65) winsize 63
5050 11:59:16.607036 [CA 4] Center 33 (3~64) winsize 62
5051 11:59:16.610179 [CA 5] Center 32 (2~62) winsize 61
5052 11:59:16.610261
5053 11:59:16.613765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5054 11:59:16.613846
5055 11:59:16.616803 [CATrainingPosCal] consider 1 rank data
5056 11:59:16.620094 u2DelayCellTimex100 = 270/100 ps
5057 11:59:16.623711 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5058 11:59:16.626818 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5059 11:59:16.630409 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5060 11:59:16.633676 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5061 11:59:16.637048 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5062 11:59:16.640488 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5063 11:59:16.640586
5064 11:59:16.647118 CA PerBit enable=1, Macro0, CA PI delay=32
5065 11:59:16.647217
5066 11:59:16.650213 [CBTSetCACLKResult] CA Dly = 32
5067 11:59:16.650306 CS Dly: 5 (0~36)
5068 11:59:16.650394 ==
5069 11:59:16.653793 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 11:59:16.657361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 11:59:16.657433 ==
5072 11:59:16.664248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 11:59:16.670274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5074 11:59:16.673840 [CA 0] Center 37 (7~68) winsize 62
5075 11:59:16.677259 [CA 1] Center 37 (7~68) winsize 62
5076 11:59:16.680140 [CA 2] Center 34 (4~65) winsize 62
5077 11:59:16.683973 [CA 3] Center 33 (3~64) winsize 62
5078 11:59:16.687164 [CA 4] Center 32 (2~63) winsize 62
5079 11:59:16.690093 [CA 5] Center 32 (2~62) winsize 61
5080 11:59:16.690175
5081 11:59:16.693961 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5082 11:59:16.694030
5083 11:59:16.696953 [CATrainingPosCal] consider 2 rank data
5084 11:59:16.700487 u2DelayCellTimex100 = 270/100 ps
5085 11:59:16.703585 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5086 11:59:16.706788 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5087 11:59:16.709756 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5088 11:59:16.713144 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5089 11:59:16.716922 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5090 11:59:16.723169 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5091 11:59:16.723247
5092 11:59:16.726937 CA PerBit enable=1, Macro0, CA PI delay=32
5093 11:59:16.727014
5094 11:59:16.730120 [CBTSetCACLKResult] CA Dly = 32
5095 11:59:16.730194 CS Dly: 6 (0~38)
5096 11:59:16.730255
5097 11:59:16.733038 ----->DramcWriteLeveling(PI) begin...
5098 11:59:16.733142 ==
5099 11:59:16.736347 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 11:59:16.743380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 11:59:16.743455 ==
5102 11:59:16.746460 Write leveling (Byte 0): 34 => 34
5103 11:59:16.746535 Write leveling (Byte 1): 27 => 27
5104 11:59:16.749842 DramcWriteLeveling(PI) end<-----
5105 11:59:16.749939
5106 11:59:16.750064 ==
5107 11:59:16.753433 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 11:59:16.759785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 11:59:16.759860 ==
5110 11:59:16.763088 [Gating] SW mode calibration
5111 11:59:16.770131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 11:59:16.772965 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 11:59:16.779993 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
5114 11:59:16.783005 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:59:16.786048 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 11:59:16.793180 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 11:59:16.796444 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 11:59:16.799405 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 11:59:16.806449 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5120 11:59:16.809984 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
5121 11:59:16.813168 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5122 11:59:16.819480 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:59:16.823328 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 11:59:16.826743 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 11:59:16.829537 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 11:59:16.836353 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 11:59:16.839431 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5128 11:59:16.842629 0 15 28 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
5129 11:59:16.849760 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5130 11:59:16.852573 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:59:16.856041 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:59:16.863238 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:59:16.866107 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 11:59:16.869219 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 11:59:16.875834 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5136 11:59:16.879683 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5137 11:59:16.882620 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 11:59:16.889485 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:59:16.892771 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:59:16.896203 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:59:16.902778 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:59:16.905913 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:59:16.909524 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:59:16.915966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:59:16.919657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:59:16.922799 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:59:16.929543 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:59:16.932623 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:59:16.935873 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 11:59:16.939461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 11:59:16.945743 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 11:59:16.949511 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 11:59:16.952877 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5154 11:59:16.956544 Total UI for P1: 0, mck2ui 16
5155 11:59:16.959505 best dqsien dly found for B0: ( 1, 2, 26)
5156 11:59:16.966314 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 11:59:16.969489 Total UI for P1: 0, mck2ui 16
5158 11:59:16.972496 best dqsien dly found for B1: ( 1, 3, 0)
5159 11:59:16.975800 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5160 11:59:16.979435 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5161 11:59:16.979515
5162 11:59:16.982336 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5163 11:59:16.986009 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5164 11:59:16.989072 [Gating] SW calibration Done
5165 11:59:16.989172 ==
5166 11:59:16.992194 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 11:59:16.995844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 11:59:16.995945 ==
5169 11:59:16.999192 RX Vref Scan: 0
5170 11:59:16.999260
5171 11:59:16.999318 RX Vref 0 -> 0, step: 1
5172 11:59:16.999386
5173 11:59:17.002428 RX Delay -80 -> 252, step: 8
5174 11:59:17.009266 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5175 11:59:17.012973 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5176 11:59:17.015899 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5177 11:59:17.019289 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5178 11:59:17.022281 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5179 11:59:17.025878 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5180 11:59:17.032087 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5181 11:59:17.035575 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5182 11:59:17.038766 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5183 11:59:17.042450 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5184 11:59:17.045699 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5185 11:59:17.049071 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5186 11:59:17.055533 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5187 11:59:17.058484 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5188 11:59:17.062342 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5189 11:59:17.065520 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5190 11:59:17.065641 ==
5191 11:59:17.068616 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 11:59:17.072183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 11:59:17.075858 ==
5194 11:59:17.075939 DQS Delay:
5195 11:59:17.076004 DQS0 = 0, DQS1 = 0
5196 11:59:17.078661 DQM Delay:
5197 11:59:17.078742 DQM0 = 104, DQM1 = 96
5198 11:59:17.081836 DQ Delay:
5199 11:59:17.085431 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5200 11:59:17.088643 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5201 11:59:17.092248 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5202 11:59:17.095375 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5203 11:59:17.095456
5204 11:59:17.095520
5205 11:59:17.095579 ==
5206 11:59:17.098580 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 11:59:17.102367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 11:59:17.102449 ==
5209 11:59:17.102512
5210 11:59:17.102571
5211 11:59:17.105503 TX Vref Scan disable
5212 11:59:17.105609 == TX Byte 0 ==
5213 11:59:17.111895 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5214 11:59:17.115468 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5215 11:59:17.118881 == TX Byte 1 ==
5216 11:59:17.121871 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5217 11:59:17.125947 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5218 11:59:17.126031 ==
5219 11:59:17.128963 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 11:59:17.131716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 11:59:17.131815 ==
5222 11:59:17.134948
5223 11:59:17.135029
5224 11:59:17.135092 TX Vref Scan disable
5225 11:59:17.138760 == TX Byte 0 ==
5226 11:59:17.142491 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5227 11:59:17.145396 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5228 11:59:17.148486 == TX Byte 1 ==
5229 11:59:17.152344 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5230 11:59:17.155398 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5231 11:59:17.158479
5232 11:59:17.158603 [DATLAT]
5233 11:59:17.158751 Freq=933, CH0 RK0
5234 11:59:17.158814
5235 11:59:17.162204 DATLAT Default: 0xd
5236 11:59:17.162309 0, 0xFFFF, sum = 0
5237 11:59:17.165099 1, 0xFFFF, sum = 0
5238 11:59:17.165195 2, 0xFFFF, sum = 0
5239 11:59:17.168851 3, 0xFFFF, sum = 0
5240 11:59:17.172129 4, 0xFFFF, sum = 0
5241 11:59:17.172210 5, 0xFFFF, sum = 0
5242 11:59:17.175256 6, 0xFFFF, sum = 0
5243 11:59:17.175337 7, 0xFFFF, sum = 0
5244 11:59:17.178889 8, 0xFFFF, sum = 0
5245 11:59:17.178970 9, 0xFFFF, sum = 0
5246 11:59:17.181814 10, 0x0, sum = 1
5247 11:59:17.181895 11, 0x0, sum = 2
5248 11:59:17.185546 12, 0x0, sum = 3
5249 11:59:17.185659 13, 0x0, sum = 4
5250 11:59:17.185736 best_step = 11
5251 11:59:17.185794
5252 11:59:17.188382 ==
5253 11:59:17.191983 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 11:59:17.195035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 11:59:17.195116 ==
5256 11:59:17.195179 RX Vref Scan: 1
5257 11:59:17.195236
5258 11:59:17.198811 RX Vref 0 -> 0, step: 1
5259 11:59:17.198907
5260 11:59:17.202073 RX Delay -45 -> 252, step: 4
5261 11:59:17.202177
5262 11:59:17.205094 Set Vref, RX VrefLevel [Byte0]: 53
5263 11:59:17.208216 [Byte1]: 50
5264 11:59:17.208295
5265 11:59:17.211485 Final RX Vref Byte 0 = 53 to rank0
5266 11:59:17.215186 Final RX Vref Byte 1 = 50 to rank0
5267 11:59:17.218449 Final RX Vref Byte 0 = 53 to rank1
5268 11:59:17.221593 Final RX Vref Byte 1 = 50 to rank1==
5269 11:59:17.224745 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 11:59:17.228340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 11:59:17.231962 ==
5272 11:59:17.232045 DQS Delay:
5273 11:59:17.232108 DQS0 = 0, DQS1 = 0
5274 11:59:17.235125 DQM Delay:
5275 11:59:17.235204 DQM0 = 104, DQM1 = 95
5276 11:59:17.238706 DQ Delay:
5277 11:59:17.241458 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5278 11:59:17.245002 DQ4 =104, DQ5 =94, DQ6 =112, DQ7 =112
5279 11:59:17.248103 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =90
5280 11:59:17.251268 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5281 11:59:17.251342
5282 11:59:17.251403
5283 11:59:17.258236 [DQSOSCAuto] RK0, (LSB)MR18= 0x3128, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5284 11:59:17.261234 CH0 RK0: MR19=505, MR18=3128
5285 11:59:17.268504 CH0_RK0: MR19=0x505, MR18=0x3128, DQSOSC=406, MR23=63, INC=65, DEC=43
5286 11:59:17.268583
5287 11:59:17.271270 ----->DramcWriteLeveling(PI) begin...
5288 11:59:17.271343 ==
5289 11:59:17.274487 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 11:59:17.277807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 11:59:17.277884 ==
5292 11:59:17.281683 Write leveling (Byte 0): 31 => 31
5293 11:59:17.284943 Write leveling (Byte 1): 31 => 31
5294 11:59:17.288046 DramcWriteLeveling(PI) end<-----
5295 11:59:17.288128
5296 11:59:17.288192 ==
5297 11:59:17.291173 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 11:59:17.294231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 11:59:17.297681 ==
5300 11:59:17.297768 [Gating] SW mode calibration
5301 11:59:17.307838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5302 11:59:17.311098 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5303 11:59:17.314058 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5304 11:59:17.321283 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 11:59:17.324339 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 11:59:17.327527 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 11:59:17.334399 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 11:59:17.337802 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 11:59:17.341038 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5310 11:59:17.347924 0 14 28 | B1->B0 | 2b2b 2929 | 1 0 | (0 0) (0 1)
5311 11:59:17.350984 0 15 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 0)
5312 11:59:17.355026 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:59:17.360888 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:59:17.364101 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 11:59:17.368057 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 11:59:17.374364 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 11:59:17.377624 0 15 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5318 11:59:17.381163 0 15 28 | B1->B0 | 3d3d 3636 | 0 0 | (0 0) (0 0)
5319 11:59:17.384110 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5320 11:59:17.391306 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 11:59:17.394130 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:59:17.397752 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 11:59:17.404048 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 11:59:17.407423 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 11:59:17.410973 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 11:59:17.417615 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5327 11:59:17.420759 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5328 11:59:17.423959 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:59:17.430819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:59:17.434500 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:59:17.437877 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:59:17.444452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:59:17.447546 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:59:17.450630 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:59:17.457190 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:59:17.460538 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:59:17.463919 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:59:17.471026 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 11:59:17.474205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 11:59:17.477190 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 11:59:17.483771 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5342 11:59:17.487256 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5343 11:59:17.490525 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5344 11:59:17.497326 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 11:59:17.497407 Total UI for P1: 0, mck2ui 16
5346 11:59:17.503853 best dqsien dly found for B0: ( 1, 2, 28)
5347 11:59:17.503935 Total UI for P1: 0, mck2ui 16
5348 11:59:17.507662 best dqsien dly found for B1: ( 1, 2, 30)
5349 11:59:17.513899 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5350 11:59:17.517346 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5351 11:59:17.517426
5352 11:59:17.520978 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5353 11:59:17.523936 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5354 11:59:17.526928 [Gating] SW calibration Done
5355 11:59:17.527113 ==
5356 11:59:17.530676 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 11:59:17.533805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 11:59:17.533886 ==
5359 11:59:17.536944 RX Vref Scan: 0
5360 11:59:17.537023
5361 11:59:17.537085 RX Vref 0 -> 0, step: 1
5362 11:59:17.537144
5363 11:59:17.540712 RX Delay -80 -> 252, step: 8
5364 11:59:17.543804 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5365 11:59:17.550443 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5366 11:59:17.553534 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5367 11:59:17.557398 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5368 11:59:17.560655 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5369 11:59:17.563848 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5370 11:59:17.566744 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5371 11:59:17.573601 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5372 11:59:17.577000 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5373 11:59:17.580118 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5374 11:59:17.583301 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5375 11:59:17.586713 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5376 11:59:17.590540 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5377 11:59:17.593486 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5378 11:59:17.600180 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5379 11:59:17.603374 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5380 11:59:17.603455 ==
5381 11:59:17.606797 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 11:59:17.610603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 11:59:17.610685 ==
5384 11:59:17.613173 DQS Delay:
5385 11:59:17.613253 DQS0 = 0, DQS1 = 0
5386 11:59:17.613317 DQM Delay:
5387 11:59:17.616615 DQM0 = 104, DQM1 = 94
5388 11:59:17.616695 DQ Delay:
5389 11:59:17.620282 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5390 11:59:17.623377 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5391 11:59:17.626534 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5392 11:59:17.630042 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5393 11:59:17.630123
5394 11:59:17.630186
5395 11:59:17.633143 ==
5396 11:59:17.633255 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:59:17.639687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:59:17.639769 ==
5399 11:59:17.639833
5400 11:59:17.639892
5401 11:59:17.643561 TX Vref Scan disable
5402 11:59:17.643642 == TX Byte 0 ==
5403 11:59:17.646641 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5404 11:59:17.653244 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5405 11:59:17.653345 == TX Byte 1 ==
5406 11:59:17.656462 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5407 11:59:17.663269 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5408 11:59:17.663350 ==
5409 11:59:17.666358 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 11:59:17.670048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 11:59:17.670136 ==
5412 11:59:17.670200
5413 11:59:17.670258
5414 11:59:17.673157 TX Vref Scan disable
5415 11:59:17.676266 == TX Byte 0 ==
5416 11:59:17.679358 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5417 11:59:17.682951 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5418 11:59:17.686730 == TX Byte 1 ==
5419 11:59:17.689905 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5420 11:59:17.692932 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5421 11:59:17.693013
5422 11:59:17.696134 [DATLAT]
5423 11:59:17.696215 Freq=933, CH0 RK1
5424 11:59:17.696279
5425 11:59:17.699496 DATLAT Default: 0xb
5426 11:59:17.699577 0, 0xFFFF, sum = 0
5427 11:59:17.702560 1, 0xFFFF, sum = 0
5428 11:59:17.702641 2, 0xFFFF, sum = 0
5429 11:59:17.706277 3, 0xFFFF, sum = 0
5430 11:59:17.706357 4, 0xFFFF, sum = 0
5431 11:59:17.709508 5, 0xFFFF, sum = 0
5432 11:59:17.709655 6, 0xFFFF, sum = 0
5433 11:59:17.712569 7, 0xFFFF, sum = 0
5434 11:59:17.712650 8, 0xFFFF, sum = 0
5435 11:59:17.715789 9, 0xFFFF, sum = 0
5436 11:59:17.715877 10, 0x0, sum = 1
5437 11:59:17.719593 11, 0x0, sum = 2
5438 11:59:17.719690 12, 0x0, sum = 3
5439 11:59:17.723171 13, 0x0, sum = 4
5440 11:59:17.723254 best_step = 11
5441 11:59:17.723318
5442 11:59:17.723376 ==
5443 11:59:17.726045 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 11:59:17.729153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 11:59:17.732811 ==
5446 11:59:17.732892 RX Vref Scan: 0
5447 11:59:17.732956
5448 11:59:17.735965 RX Vref 0 -> 0, step: 1
5449 11:59:17.736046
5450 11:59:17.739129 RX Delay -45 -> 252, step: 4
5451 11:59:17.742607 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5452 11:59:17.745504 iDelay=195, Bit 1, Center 106 (19 ~ 194) 176
5453 11:59:17.752557 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5454 11:59:17.755971 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5455 11:59:17.758965 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5456 11:59:17.762105 iDelay=195, Bit 5, Center 98 (11 ~ 186) 176
5457 11:59:17.766172 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5458 11:59:17.772239 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5459 11:59:17.775624 iDelay=195, Bit 8, Center 86 (3 ~ 170) 168
5460 11:59:17.779342 iDelay=195, Bit 9, Center 84 (-1 ~ 170) 172
5461 11:59:17.782828 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5462 11:59:17.786048 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5463 11:59:17.789385 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5464 11:59:17.795479 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5465 11:59:17.799214 iDelay=195, Bit 14, Center 106 (23 ~ 190) 168
5466 11:59:17.802415 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5467 11:59:17.802496 ==
5468 11:59:17.805955 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 11:59:17.809294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 11:59:17.809375 ==
5471 11:59:17.812004 DQS Delay:
5472 11:59:17.812084 DQS0 = 0, DQS1 = 0
5473 11:59:17.815782 DQM Delay:
5474 11:59:17.815862 DQM0 = 104, DQM1 = 94
5475 11:59:17.815925 DQ Delay:
5476 11:59:17.818834 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5477 11:59:17.822073 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5478 11:59:17.825761 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =88
5479 11:59:17.832404 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =102
5480 11:59:17.832487
5481 11:59:17.832553
5482 11:59:17.839188 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5483 11:59:17.842091 CH0 RK1: MR19=505, MR18=2B03
5484 11:59:17.848863 CH0_RK1: MR19=0x505, MR18=0x2B03, DQSOSC=408, MR23=63, INC=65, DEC=43
5485 11:59:17.852489 [RxdqsGatingPostProcess] freq 933
5486 11:59:17.855602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5487 11:59:17.858529 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 11:59:17.862334 best DQS1 dly(2T, 0.5T) = (0, 11)
5489 11:59:17.865381 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 11:59:17.868868 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5491 11:59:17.872597 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 11:59:17.875613 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 11:59:17.878440 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 11:59:17.882108 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 11:59:17.885323 Pre-setting of DQS Precalculation
5496 11:59:17.889143 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5497 11:59:17.889225 ==
5498 11:59:17.891791 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 11:59:17.898619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 11:59:17.898702 ==
5501 11:59:17.901691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5502 11:59:17.908455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5503 11:59:17.912186 [CA 0] Center 36 (6~67) winsize 62
5504 11:59:17.915151 [CA 1] Center 36 (6~67) winsize 62
5505 11:59:17.918373 [CA 2] Center 34 (4~65) winsize 62
5506 11:59:17.921846 [CA 3] Center 34 (4~64) winsize 61
5507 11:59:17.925182 [CA 4] Center 34 (4~64) winsize 61
5508 11:59:17.928329 [CA 5] Center 33 (3~64) winsize 62
5509 11:59:17.928433
5510 11:59:17.932482 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5511 11:59:17.932591
5512 11:59:17.935392 [CATrainingPosCal] consider 1 rank data
5513 11:59:17.938706 u2DelayCellTimex100 = 270/100 ps
5514 11:59:17.942113 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5515 11:59:17.945207 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 11:59:17.948849 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5517 11:59:17.955104 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5518 11:59:17.958413 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 11:59:17.962047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5520 11:59:17.962146
5521 11:59:17.965095 CA PerBit enable=1, Macro0, CA PI delay=33
5522 11:59:17.965168
5523 11:59:17.968669 [CBTSetCACLKResult] CA Dly = 33
5524 11:59:17.968768 CS Dly: 7 (0~38)
5525 11:59:17.968856 ==
5526 11:59:17.971750 Dram Type= 6, Freq= 0, CH_1, rank 1
5527 11:59:17.978239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 11:59:17.978315 ==
5529 11:59:17.981803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5530 11:59:17.988414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5531 11:59:17.991628 [CA 0] Center 36 (6~67) winsize 62
5532 11:59:17.994778 [CA 1] Center 37 (7~68) winsize 62
5533 11:59:17.998494 [CA 2] Center 35 (5~65) winsize 61
5534 11:59:18.001561 [CA 3] Center 34 (4~65) winsize 62
5535 11:59:18.005253 [CA 4] Center 34 (4~65) winsize 62
5536 11:59:18.008161 [CA 5] Center 33 (3~64) winsize 62
5537 11:59:18.008261
5538 11:59:18.012131 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5539 11:59:18.012232
5540 11:59:18.015232 [CATrainingPosCal] consider 2 rank data
5541 11:59:18.018445 u2DelayCellTimex100 = 270/100 ps
5542 11:59:18.022269 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 11:59:18.025507 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5544 11:59:18.028372 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5545 11:59:18.035173 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 11:59:18.038520 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 11:59:18.041612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5548 11:59:18.041702
5549 11:59:18.044736 CA PerBit enable=1, Macro0, CA PI delay=33
5550 11:59:18.044813
5551 11:59:18.048458 [CBTSetCACLKResult] CA Dly = 33
5552 11:59:18.048576 CS Dly: 8 (0~40)
5553 11:59:18.048666
5554 11:59:18.051886 ----->DramcWriteLeveling(PI) begin...
5555 11:59:18.051985 ==
5556 11:59:18.055299 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 11:59:18.061736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 11:59:18.061823 ==
5559 11:59:18.064737 Write leveling (Byte 0): 25 => 25
5560 11:59:18.068500 Write leveling (Byte 1): 26 => 26
5561 11:59:18.071964 DramcWriteLeveling(PI) end<-----
5562 11:59:18.072044
5563 11:59:18.072108 ==
5564 11:59:18.074766 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 11:59:18.077893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 11:59:18.077975 ==
5567 11:59:18.081625 [Gating] SW mode calibration
5568 11:59:18.088529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5569 11:59:18.094425 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5570 11:59:18.097995 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:59:18.101212 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 11:59:18.104790 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 11:59:18.111363 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 11:59:18.114458 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 11:59:18.118119 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 11:59:18.125264 0 14 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
5577 11:59:18.127801 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5578 11:59:18.131235 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:59:18.137933 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 11:59:18.140985 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 11:59:18.144443 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 11:59:18.151241 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 11:59:18.154236 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 11:59:18.157385 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5585 11:59:18.164237 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5586 11:59:18.167683 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:59:18.170806 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 11:59:18.177732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 11:59:18.181076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 11:59:18.184436 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 11:59:18.190662 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 11:59:18.194414 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5593 11:59:18.197326 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5594 11:59:18.204440 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:59:18.207457 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:59:18.210740 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:59:18.217488 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:59:18.220332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:59:18.223854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:59:18.230446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:59:18.233902 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:59:18.237372 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:59:18.243880 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 11:59:18.247208 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 11:59:18.250174 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 11:59:18.257344 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 11:59:18.260239 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 11:59:18.263466 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5609 11:59:18.270240 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 11:59:18.270320 Total UI for P1: 0, mck2ui 16
5611 11:59:18.273982 best dqsien dly found for B0: ( 1, 2, 24)
5612 11:59:18.277439 Total UI for P1: 0, mck2ui 16
5613 11:59:18.280469 best dqsien dly found for B1: ( 1, 2, 24)
5614 11:59:18.283623 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5615 11:59:18.290085 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5616 11:59:18.290160
5617 11:59:18.293656 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5618 11:59:18.297011 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5619 11:59:18.300058 [Gating] SW calibration Done
5620 11:59:18.300133 ==
5621 11:59:18.303762 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 11:59:18.307038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 11:59:18.307118 ==
5624 11:59:18.310345 RX Vref Scan: 0
5625 11:59:18.310424
5626 11:59:18.310491 RX Vref 0 -> 0, step: 1
5627 11:59:18.310565
5628 11:59:18.313200 RX Delay -80 -> 252, step: 8
5629 11:59:18.316666 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5630 11:59:18.320019 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5631 11:59:18.326637 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5632 11:59:18.330121 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5633 11:59:18.333286 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5634 11:59:18.337055 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5635 11:59:18.340182 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5636 11:59:18.343284 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5637 11:59:18.349869 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5638 11:59:18.353352 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5639 11:59:18.356541 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5640 11:59:18.360246 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5641 11:59:18.363497 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5642 11:59:18.370097 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5643 11:59:18.373535 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5644 11:59:18.376944 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5645 11:59:18.377030 ==
5646 11:59:18.379791 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 11:59:18.382878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 11:59:18.382976 ==
5649 11:59:18.386382 DQS Delay:
5650 11:59:18.386455 DQS0 = 0, DQS1 = 0
5651 11:59:18.389687 DQM Delay:
5652 11:59:18.389766 DQM0 = 102, DQM1 = 98
5653 11:59:18.389829 DQ Delay:
5654 11:59:18.393601 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5655 11:59:18.396940 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5656 11:59:18.400057 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5657 11:59:18.403205 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5658 11:59:18.406910
5659 11:59:18.407015
5660 11:59:18.407106 ==
5661 11:59:18.409862 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 11:59:18.413475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 11:59:18.413569 ==
5664 11:59:18.413686
5665 11:59:18.413743
5666 11:59:18.416545 TX Vref Scan disable
5667 11:59:18.416631 == TX Byte 0 ==
5668 11:59:18.423006 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 11:59:18.426700 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 11:59:18.426773 == TX Byte 1 ==
5671 11:59:18.433397 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 11:59:18.436387 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 11:59:18.436467 ==
5674 11:59:18.439582 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 11:59:18.443396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 11:59:18.443476 ==
5677 11:59:18.443539
5678 11:59:18.443597
5679 11:59:18.446467 TX Vref Scan disable
5680 11:59:18.450285 == TX Byte 0 ==
5681 11:59:18.452902 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 11:59:18.456455 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 11:59:18.459496 == TX Byte 1 ==
5684 11:59:18.463155 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5685 11:59:18.466492 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5686 11:59:18.466572
5687 11:59:18.469725 [DATLAT]
5688 11:59:18.469804 Freq=933, CH1 RK0
5689 11:59:18.469867
5690 11:59:18.473071 DATLAT Default: 0xd
5691 11:59:18.473180 0, 0xFFFF, sum = 0
5692 11:59:18.476124 1, 0xFFFF, sum = 0
5693 11:59:18.476205 2, 0xFFFF, sum = 0
5694 11:59:18.479637 3, 0xFFFF, sum = 0
5695 11:59:18.479745 4, 0xFFFF, sum = 0
5696 11:59:18.483056 5, 0xFFFF, sum = 0
5697 11:59:18.483137 6, 0xFFFF, sum = 0
5698 11:59:18.486232 7, 0xFFFF, sum = 0
5699 11:59:18.486312 8, 0xFFFF, sum = 0
5700 11:59:18.489860 9, 0xFFFF, sum = 0
5701 11:59:18.489945 10, 0x0, sum = 1
5702 11:59:18.493103 11, 0x0, sum = 2
5703 11:59:18.493182 12, 0x0, sum = 3
5704 11:59:18.496309 13, 0x0, sum = 4
5705 11:59:18.496416 best_step = 11
5706 11:59:18.496508
5707 11:59:18.496593 ==
5708 11:59:18.499426 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 11:59:18.502910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 11:59:18.506420 ==
5711 11:59:18.506500 RX Vref Scan: 1
5712 11:59:18.506563
5713 11:59:18.509440 RX Vref 0 -> 0, step: 1
5714 11:59:18.509519
5715 11:59:18.513183 RX Delay -45 -> 252, step: 4
5716 11:59:18.513262
5717 11:59:18.516322 Set Vref, RX VrefLevel [Byte0]: 56
5718 11:59:18.519298 [Byte1]: 53
5719 11:59:18.519377
5720 11:59:18.522900 Final RX Vref Byte 0 = 56 to rank0
5721 11:59:18.525804 Final RX Vref Byte 1 = 53 to rank0
5722 11:59:18.529418 Final RX Vref Byte 0 = 56 to rank1
5723 11:59:18.532408 Final RX Vref Byte 1 = 53 to rank1==
5724 11:59:18.536035 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 11:59:18.539021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 11:59:18.539123 ==
5727 11:59:18.542893 DQS Delay:
5728 11:59:18.542989 DQS0 = 0, DQS1 = 0
5729 11:59:18.543076 DQM Delay:
5730 11:59:18.546216 DQM0 = 103, DQM1 = 99
5731 11:59:18.546319 DQ Delay:
5732 11:59:18.549165 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5733 11:59:18.552563 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5734 11:59:18.555870 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5735 11:59:18.559142 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5736 11:59:18.562374
5737 11:59:18.562447
5738 11:59:18.568940 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5739 11:59:18.572640 CH1 RK0: MR19=505, MR18=162E
5740 11:59:18.579515 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5741 11:59:18.579616
5742 11:59:18.582659 ----->DramcWriteLeveling(PI) begin...
5743 11:59:18.582756 ==
5744 11:59:18.585894 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 11:59:18.588886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 11:59:18.588955 ==
5747 11:59:18.592494 Write leveling (Byte 0): 25 => 25
5748 11:59:18.595908 Write leveling (Byte 1): 27 => 27
5749 11:59:18.599365 DramcWriteLeveling(PI) end<-----
5750 11:59:18.599466
5751 11:59:18.599555 ==
5752 11:59:18.602251 Dram Type= 6, Freq= 0, CH_1, rank 1
5753 11:59:18.605991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 11:59:18.606066 ==
5755 11:59:18.609035 [Gating] SW mode calibration
5756 11:59:18.615590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5757 11:59:18.622205 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5758 11:59:18.625317 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:59:18.629039 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 11:59:18.635278 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 11:59:18.638992 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 11:59:18.642057 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 11:59:18.648606 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 11:59:18.652132 0 14 24 | B1->B0 | 2b2b 3131 | 0 0 | (0 1) (0 0)
5765 11:59:18.655941 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
5766 11:59:18.662269 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:59:18.665438 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 11:59:18.668786 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 11:59:18.675791 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 11:59:18.678782 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 11:59:18.681975 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5772 11:59:18.688824 0 15 24 | B1->B0 | 3b3b 2a2a | 0 0 | (0 0) (0 0)
5773 11:59:18.692282 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5774 11:59:18.695622 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:59:18.702090 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:59:18.705760 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 11:59:18.708702 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 11:59:18.715695 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 11:59:18.718776 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 11:59:18.721703 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5781 11:59:18.728301 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5782 11:59:18.731894 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:59:18.734927 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:59:18.742149 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:59:18.745131 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:59:18.748232 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:59:18.751987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:59:18.758409 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:59:18.761561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:59:18.765481 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:59:18.771833 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:59:18.774739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 11:59:18.778125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 11:59:18.785121 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 11:59:18.788456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 11:59:18.791349 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5797 11:59:18.798341 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 11:59:18.801527 Total UI for P1: 0, mck2ui 16
5799 11:59:18.804677 best dqsien dly found for B0: ( 1, 2, 24)
5800 11:59:18.804758 Total UI for P1: 0, mck2ui 16
5801 11:59:18.811488 best dqsien dly found for B1: ( 1, 2, 24)
5802 11:59:18.814761 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5803 11:59:18.818319 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5804 11:59:18.818408
5805 11:59:18.821813 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5806 11:59:18.824511 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5807 11:59:18.828317 [Gating] SW calibration Done
5808 11:59:18.828400 ==
5809 11:59:18.831398 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 11:59:18.834860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 11:59:18.834942 ==
5812 11:59:18.838093 RX Vref Scan: 0
5813 11:59:18.838173
5814 11:59:18.838236 RX Vref 0 -> 0, step: 1
5815 11:59:18.838296
5816 11:59:18.841278 RX Delay -80 -> 252, step: 8
5817 11:59:18.848123 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5818 11:59:18.851863 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5819 11:59:18.854593 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5820 11:59:18.857946 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5821 11:59:18.861053 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5822 11:59:18.864763 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5823 11:59:18.871377 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5824 11:59:18.874696 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5825 11:59:18.877989 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5826 11:59:18.881234 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5827 11:59:18.884890 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5828 11:59:18.887824 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5829 11:59:18.894424 iDelay=208, Bit 12, Center 111 (16 ~ 207) 192
5830 11:59:18.898073 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5831 11:59:18.901302 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5832 11:59:18.904551 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5833 11:59:18.904632 ==
5834 11:59:18.908105 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 11:59:18.911265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 11:59:18.914447 ==
5837 11:59:18.914527 DQS Delay:
5838 11:59:18.914591 DQS0 = 0, DQS1 = 0
5839 11:59:18.918210 DQM Delay:
5840 11:59:18.918291 DQM0 = 102, DQM1 = 99
5841 11:59:18.921219 DQ Delay:
5842 11:59:18.924352 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5843 11:59:18.928226 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5844 11:59:18.931228 DQ8 =87, DQ9 =91, DQ10 =103, DQ11 =91
5845 11:59:18.934671 DQ12 =111, DQ13 =107, DQ14 =99, DQ15 =107
5846 11:59:18.934752
5847 11:59:18.934816
5848 11:59:18.934874 ==
5849 11:59:18.937488 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 11:59:18.940771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 11:59:18.940871 ==
5852 11:59:18.940936
5853 11:59:18.940996
5854 11:59:18.944385 TX Vref Scan disable
5855 11:59:18.944466 == TX Byte 0 ==
5856 11:59:18.951164 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 11:59:18.954434 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 11:59:18.957877 == TX Byte 1 ==
5859 11:59:18.960758 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5860 11:59:18.963953 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5861 11:59:18.964034 ==
5862 11:59:18.967888 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 11:59:18.970879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 11:59:18.970960 ==
5865 11:59:18.971024
5866 11:59:18.973968
5867 11:59:18.974048 TX Vref Scan disable
5868 11:59:18.977727 == TX Byte 0 ==
5869 11:59:18.980882 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5870 11:59:18.984114 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5871 11:59:18.987675 == TX Byte 1 ==
5872 11:59:18.991549 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 11:59:18.994110 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 11:59:18.994191
5875 11:59:18.997764 [DATLAT]
5876 11:59:18.997844 Freq=933, CH1 RK1
5877 11:59:18.997909
5878 11:59:19.001249 DATLAT Default: 0xb
5879 11:59:19.001330 0, 0xFFFF, sum = 0
5880 11:59:19.004258 1, 0xFFFF, sum = 0
5881 11:59:19.004340 2, 0xFFFF, sum = 0
5882 11:59:19.007579 3, 0xFFFF, sum = 0
5883 11:59:19.007660 4, 0xFFFF, sum = 0
5884 11:59:19.010808 5, 0xFFFF, sum = 0
5885 11:59:19.010890 6, 0xFFFF, sum = 0
5886 11:59:19.013937 7, 0xFFFF, sum = 0
5887 11:59:19.017562 8, 0xFFFF, sum = 0
5888 11:59:19.017655 9, 0xFFFF, sum = 0
5889 11:59:19.017720 10, 0x0, sum = 1
5890 11:59:19.020883 11, 0x0, sum = 2
5891 11:59:19.020965 12, 0x0, sum = 3
5892 11:59:19.023840 13, 0x0, sum = 4
5893 11:59:19.023922 best_step = 11
5894 11:59:19.023985
5895 11:59:19.024044 ==
5896 11:59:19.027667 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 11:59:19.033787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 11:59:19.033869 ==
5899 11:59:19.033933 RX Vref Scan: 0
5900 11:59:19.033992
5901 11:59:19.037097 RX Vref 0 -> 0, step: 1
5902 11:59:19.037177
5903 11:59:19.040582 RX Delay -45 -> 252, step: 4
5904 11:59:19.044084 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5905 11:59:19.050507 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5906 11:59:19.054056 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5907 11:59:19.057562 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5908 11:59:19.060699 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5909 11:59:19.063817 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5910 11:59:19.070494 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5911 11:59:19.074117 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5912 11:59:19.077131 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5913 11:59:19.080875 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5914 11:59:19.084166 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5915 11:59:19.087130 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5916 11:59:19.094092 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5917 11:59:19.096902 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5918 11:59:19.101069 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5919 11:59:19.103830 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5920 11:59:19.103911 ==
5921 11:59:19.107412 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 11:59:19.113552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 11:59:19.113661 ==
5924 11:59:19.113725 DQS Delay:
5925 11:59:19.113785 DQS0 = 0, DQS1 = 0
5926 11:59:19.117478 DQM Delay:
5927 11:59:19.117619 DQM0 = 105, DQM1 = 100
5928 11:59:19.120361 DQ Delay:
5929 11:59:19.124188 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5930 11:59:19.127327 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5931 11:59:19.130299 DQ8 =90, DQ9 =88, DQ10 =102, DQ11 =92
5932 11:59:19.133980 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5933 11:59:19.134062
5934 11:59:19.134126
5935 11:59:19.140421 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5936 11:59:19.143565 CH1 RK1: MR19=505, MR18=2C00
5937 11:59:19.150825 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5938 11:59:19.153694 [RxdqsGatingPostProcess] freq 933
5939 11:59:19.160522 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 11:59:19.163838 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 11:59:19.163919 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 11:59:19.167132 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 11:59:19.170214 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 11:59:19.173396 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 11:59:19.177209 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 11:59:19.180566 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 11:59:19.183846 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 11:59:19.186627 Pre-setting of DQS Precalculation
5949 11:59:19.193480 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 11:59:19.200392 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 11:59:19.207013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 11:59:19.207094
5953 11:59:19.207159
5954 11:59:19.209905 [Calibration Summary] 1866 Mbps
5955 11:59:19.209986 CH 0, Rank 0
5956 11:59:19.213665 SW Impedance : PASS
5957 11:59:19.217027 DUTY Scan : NO K
5958 11:59:19.217108 ZQ Calibration : PASS
5959 11:59:19.220126 Jitter Meter : NO K
5960 11:59:19.223278 CBT Training : PASS
5961 11:59:19.223359 Write leveling : PASS
5962 11:59:19.226649 RX DQS gating : PASS
5963 11:59:19.226730 RX DQ/DQS(RDDQC) : PASS
5964 11:59:19.230172 TX DQ/DQS : PASS
5965 11:59:19.233785 RX DATLAT : PASS
5966 11:59:19.233865 RX DQ/DQS(Engine): PASS
5967 11:59:19.236701 TX OE : NO K
5968 11:59:19.236781 All Pass.
5969 11:59:19.236845
5970 11:59:19.240415 CH 0, Rank 1
5971 11:59:19.240496 SW Impedance : PASS
5972 11:59:19.243373 DUTY Scan : NO K
5973 11:59:19.246566 ZQ Calibration : PASS
5974 11:59:19.246647 Jitter Meter : NO K
5975 11:59:19.250409 CBT Training : PASS
5976 11:59:19.253472 Write leveling : PASS
5977 11:59:19.253587 RX DQS gating : PASS
5978 11:59:19.256674 RX DQ/DQS(RDDQC) : PASS
5979 11:59:19.260364 TX DQ/DQS : PASS
5980 11:59:19.260444 RX DATLAT : PASS
5981 11:59:19.263246 RX DQ/DQS(Engine): PASS
5982 11:59:19.266935 TX OE : NO K
5983 11:59:19.267016 All Pass.
5984 11:59:19.267080
5985 11:59:19.267140 CH 1, Rank 0
5986 11:59:19.270065 SW Impedance : PASS
5987 11:59:19.273029 DUTY Scan : NO K
5988 11:59:19.273110 ZQ Calibration : PASS
5989 11:59:19.277045 Jitter Meter : NO K
5990 11:59:19.277125 CBT Training : PASS
5991 11:59:19.280024 Write leveling : PASS
5992 11:59:19.283035 RX DQS gating : PASS
5993 11:59:19.283115 RX DQ/DQS(RDDQC) : PASS
5994 11:59:19.286816 TX DQ/DQS : PASS
5995 11:59:19.290298 RX DATLAT : PASS
5996 11:59:19.290379 RX DQ/DQS(Engine): PASS
5997 11:59:19.293461 TX OE : NO K
5998 11:59:19.293568 All Pass.
5999 11:59:19.293674
6000 11:59:19.296941 CH 1, Rank 1
6001 11:59:19.297048 SW Impedance : PASS
6002 11:59:19.299811 DUTY Scan : NO K
6003 11:59:19.303098 ZQ Calibration : PASS
6004 11:59:19.303179 Jitter Meter : NO K
6005 11:59:19.306660 CBT Training : PASS
6006 11:59:19.310230 Write leveling : PASS
6007 11:59:19.310311 RX DQS gating : PASS
6008 11:59:19.313366 RX DQ/DQS(RDDQC) : PASS
6009 11:59:19.316339 TX DQ/DQS : PASS
6010 11:59:19.316419 RX DATLAT : PASS
6011 11:59:19.319641 RX DQ/DQS(Engine): PASS
6012 11:59:19.319721 TX OE : NO K
6013 11:59:19.323228 All Pass.
6014 11:59:19.323309
6015 11:59:19.323403 DramC Write-DBI off
6016 11:59:19.326267 PER_BANK_REFRESH: Hybrid Mode
6017 11:59:19.330291 TX_TRACKING: ON
6018 11:59:19.336373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 11:59:19.340057 [FAST_K] Save calibration result to emmc
6020 11:59:19.344015 dramc_set_vcore_voltage set vcore to 650000
6021 11:59:19.346713 Read voltage for 400, 6
6022 11:59:19.346794 Vio18 = 0
6023 11:59:19.350073 Vcore = 650000
6024 11:59:19.350154 Vdram = 0
6025 11:59:19.350218 Vddq = 0
6026 11:59:19.353373 Vmddr = 0
6027 11:59:19.357005 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 11:59:19.363554 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 11:59:19.363635 MEM_TYPE=3, freq_sel=20
6030 11:59:19.366720 sv_algorithm_assistance_LP4_800
6031 11:59:19.373479 ============ PULL DRAM RESETB DOWN ============
6032 11:59:19.376738 ========== PULL DRAM RESETB DOWN end =========
6033 11:59:19.380549 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 11:59:19.383311 ===================================
6035 11:59:19.386391 LPDDR4 DRAM CONFIGURATION
6036 11:59:19.389969 ===================================
6037 11:59:19.390051 EX_ROW_EN[0] = 0x0
6038 11:59:19.393424 EX_ROW_EN[1] = 0x0
6039 11:59:19.396426 LP4Y_EN = 0x0
6040 11:59:19.396507 WORK_FSP = 0x0
6041 11:59:19.400137 WL = 0x2
6042 11:59:19.400218 RL = 0x2
6043 11:59:19.403036 BL = 0x2
6044 11:59:19.403120 RPST = 0x0
6045 11:59:19.406635 RD_PRE = 0x0
6046 11:59:19.406716 WR_PRE = 0x1
6047 11:59:19.409997 WR_PST = 0x0
6048 11:59:19.410077 DBI_WR = 0x0
6049 11:59:19.413350 DBI_RD = 0x0
6050 11:59:19.413431 OTF = 0x1
6051 11:59:19.416555 ===================================
6052 11:59:19.420431 ===================================
6053 11:59:19.423114 ANA top config
6054 11:59:19.426471 ===================================
6055 11:59:19.426553 DLL_ASYNC_EN = 0
6056 11:59:19.430102 ALL_SLAVE_EN = 1
6057 11:59:19.433228 NEW_RANK_MODE = 1
6058 11:59:19.437010 DLL_IDLE_MODE = 1
6059 11:59:19.440358 LP45_APHY_COMB_EN = 1
6060 11:59:19.440439 TX_ODT_DIS = 1
6061 11:59:19.443177 NEW_8X_MODE = 1
6062 11:59:19.447044 ===================================
6063 11:59:19.450159 ===================================
6064 11:59:19.453292 data_rate = 800
6065 11:59:19.456794 CKR = 1
6066 11:59:19.460307 DQ_P2S_RATIO = 4
6067 11:59:19.463308 ===================================
6068 11:59:19.463389 CA_P2S_RATIO = 4
6069 11:59:19.466447 DQ_CA_OPEN = 0
6070 11:59:19.469928 DQ_SEMI_OPEN = 1
6071 11:59:19.473422 CA_SEMI_OPEN = 1
6072 11:59:19.477091 CA_FULL_RATE = 0
6073 11:59:19.480163 DQ_CKDIV4_EN = 0
6074 11:59:19.480244 CA_CKDIV4_EN = 1
6075 11:59:19.483257 CA_PREDIV_EN = 0
6076 11:59:19.486475 PH8_DLY = 0
6077 11:59:19.490150 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 11:59:19.493234 DQ_AAMCK_DIV = 0
6079 11:59:19.496884 CA_AAMCK_DIV = 0
6080 11:59:19.496965 CA_ADMCK_DIV = 4
6081 11:59:19.500232 DQ_TRACK_CA_EN = 0
6082 11:59:19.503448 CA_PICK = 800
6083 11:59:19.506402 CA_MCKIO = 400
6084 11:59:19.509779 MCKIO_SEMI = 400
6085 11:59:19.513243 PLL_FREQ = 3016
6086 11:59:19.516740 DQ_UI_PI_RATIO = 32
6087 11:59:19.516821 CA_UI_PI_RATIO = 32
6088 11:59:19.519898 ===================================
6089 11:59:19.523373 ===================================
6090 11:59:19.526859 memory_type:LPDDR4
6091 11:59:19.530189 GP_NUM : 10
6092 11:59:19.530272 SRAM_EN : 1
6093 11:59:19.533694 MD32_EN : 0
6094 11:59:19.536274 ===================================
6095 11:59:19.539981 [ANA_INIT] >>>>>>>>>>>>>>
6096 11:59:19.542934 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 11:59:19.546817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 11:59:19.550050 ===================================
6099 11:59:19.550132 data_rate = 800,PCW = 0X7400
6100 11:59:19.553174 ===================================
6101 11:59:19.556418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 11:59:19.563158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 11:59:19.573500 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 11:59:19.579952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 11:59:19.582876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 11:59:19.586109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 11:59:19.589479 [ANA_INIT] flow start
6108 11:59:19.589618 [ANA_INIT] PLL >>>>>>>>
6109 11:59:19.593324 [ANA_INIT] PLL <<<<<<<<
6110 11:59:19.596062 [ANA_INIT] MIDPI >>>>>>>>
6111 11:59:19.596158 [ANA_INIT] MIDPI <<<<<<<<
6112 11:59:19.599320 [ANA_INIT] DLL >>>>>>>>
6113 11:59:19.602983 [ANA_INIT] flow end
6114 11:59:19.605972 ============ LP4 DIFF to SE enter ============
6115 11:59:19.609723 ============ LP4 DIFF to SE exit ============
6116 11:59:19.613087 [ANA_INIT] <<<<<<<<<<<<<
6117 11:59:19.616242 [Flow] Enable top DCM control >>>>>
6118 11:59:19.619649 [Flow] Enable top DCM control <<<<<
6119 11:59:19.623078 Enable DLL master slave shuffle
6120 11:59:19.626299 ==============================================================
6121 11:59:19.629409 Gating Mode config
6122 11:59:19.636217 ==============================================================
6123 11:59:19.636297 Config description:
6124 11:59:19.645768 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 11:59:19.652619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 11:59:19.655631 SELPH_MODE 0: By rank 1: By Phase
6127 11:59:19.662572 ==============================================================
6128 11:59:19.665835 GAT_TRACK_EN = 0
6129 11:59:19.668898 RX_GATING_MODE = 2
6130 11:59:19.672426 RX_GATING_TRACK_MODE = 2
6131 11:59:19.675384 SELPH_MODE = 1
6132 11:59:19.679193 PICG_EARLY_EN = 1
6133 11:59:19.682424 VALID_LAT_VALUE = 1
6134 11:59:19.685845 ==============================================================
6135 11:59:19.689231 Enter into Gating configuration >>>>
6136 11:59:19.692541 Exit from Gating configuration <<<<
6137 11:59:19.695635 Enter into DVFS_PRE_config >>>>>
6138 11:59:19.708780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 11:59:19.708894 Exit from DVFS_PRE_config <<<<<
6140 11:59:19.712138 Enter into PICG configuration >>>>
6141 11:59:19.715442 Exit from PICG configuration <<<<
6142 11:59:19.719091 [RX_INPUT] configuration >>>>>
6143 11:59:19.722235 [RX_INPUT] configuration <<<<<
6144 11:59:19.728775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 11:59:19.732409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 11:59:19.738671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 11:59:19.745230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 11:59:19.752317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 11:59:19.759144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 11:59:19.762785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 11:59:19.765357 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 11:59:19.768832 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 11:59:19.775164 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 11:59:19.778905 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 11:59:19.782114 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 11:59:19.785162 ===================================
6157 11:59:19.788328 LPDDR4 DRAM CONFIGURATION
6158 11:59:19.791608 ===================================
6159 11:59:19.795278 EX_ROW_EN[0] = 0x0
6160 11:59:19.795362 EX_ROW_EN[1] = 0x0
6161 11:59:19.798584 LP4Y_EN = 0x0
6162 11:59:19.798664 WORK_FSP = 0x0
6163 11:59:19.802224 WL = 0x2
6164 11:59:19.802305 RL = 0x2
6165 11:59:19.805093 BL = 0x2
6166 11:59:19.805174 RPST = 0x0
6167 11:59:19.808250 RD_PRE = 0x0
6168 11:59:19.808330 WR_PRE = 0x1
6169 11:59:19.811997 WR_PST = 0x0
6170 11:59:19.812079 DBI_WR = 0x0
6171 11:59:19.815082 DBI_RD = 0x0
6172 11:59:19.815162 OTF = 0x1
6173 11:59:19.818565 ===================================
6174 11:59:19.821497 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 11:59:19.828466 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 11:59:19.831855 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 11:59:19.835087 ===================================
6178 11:59:19.838266 LPDDR4 DRAM CONFIGURATION
6179 11:59:19.841557 ===================================
6180 11:59:19.841676 EX_ROW_EN[0] = 0x10
6181 11:59:19.844933 EX_ROW_EN[1] = 0x0
6182 11:59:19.848162 LP4Y_EN = 0x0
6183 11:59:19.848242 WORK_FSP = 0x0
6184 11:59:19.851840 WL = 0x2
6185 11:59:19.851951 RL = 0x2
6186 11:59:19.855055 BL = 0x2
6187 11:59:19.855135 RPST = 0x0
6188 11:59:19.858636 RD_PRE = 0x0
6189 11:59:19.858716 WR_PRE = 0x1
6190 11:59:19.861540 WR_PST = 0x0
6191 11:59:19.861647 DBI_WR = 0x0
6192 11:59:19.865065 DBI_RD = 0x0
6193 11:59:19.865145 OTF = 0x1
6194 11:59:19.868464 ===================================
6195 11:59:19.874948 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 11:59:19.879134 nWR fixed to 30
6197 11:59:19.882331 [ModeRegInit_LP4] CH0 RK0
6198 11:59:19.882412 [ModeRegInit_LP4] CH0 RK1
6199 11:59:19.885389 [ModeRegInit_LP4] CH1 RK0
6200 11:59:19.889159 [ModeRegInit_LP4] CH1 RK1
6201 11:59:19.889241 match AC timing 19
6202 11:59:19.895937 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 11:59:19.899179 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 11:59:19.902219 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 11:59:19.909186 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 11:59:19.912206 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 11:59:19.912288 ==
6208 11:59:19.916176 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 11:59:19.918759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 11:59:19.918840 ==
6211 11:59:19.925534 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 11:59:19.932450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6213 11:59:19.935684 [CA 0] Center 36 (8~64) winsize 57
6214 11:59:19.939021 [CA 1] Center 36 (8~64) winsize 57
6215 11:59:19.942158 [CA 2] Center 36 (8~64) winsize 57
6216 11:59:19.942241 [CA 3] Center 36 (8~64) winsize 57
6217 11:59:19.945378 [CA 4] Center 36 (8~64) winsize 57
6218 11:59:19.948882 [CA 5] Center 36 (8~64) winsize 57
6219 11:59:19.948957
6220 11:59:19.955379 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6221 11:59:19.955484
6222 11:59:19.958845 [CATrainingPosCal] consider 1 rank data
6223 11:59:19.962243 u2DelayCellTimex100 = 270/100 ps
6224 11:59:19.965429 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:59:19.968764 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:59:19.972093 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:59:19.975216 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:59:19.978867 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 11:59:19.982110 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 11:59:19.982194
6231 11:59:19.985283 CA PerBit enable=1, Macro0, CA PI delay=36
6232 11:59:19.985389
6233 11:59:19.988701 [CBTSetCACLKResult] CA Dly = 36
6234 11:59:19.991966 CS Dly: 1 (0~32)
6235 11:59:19.992047 ==
6236 11:59:19.995591 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 11:59:19.998927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 11:59:19.999010 ==
6239 11:59:20.005304 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 11:59:20.008478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 11:59:20.011776 [CA 0] Center 36 (8~64) winsize 57
6242 11:59:20.015544 [CA 1] Center 36 (8~64) winsize 57
6243 11:59:20.018527 [CA 2] Center 36 (8~64) winsize 57
6244 11:59:20.022104 [CA 3] Center 36 (8~64) winsize 57
6245 11:59:20.025106 [CA 4] Center 36 (8~64) winsize 57
6246 11:59:20.028712 [CA 5] Center 36 (8~64) winsize 57
6247 11:59:20.028814
6248 11:59:20.032029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 11:59:20.032107
6250 11:59:20.035198 [CATrainingPosCal] consider 2 rank data
6251 11:59:20.038419 u2DelayCellTimex100 = 270/100 ps
6252 11:59:20.042043 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:59:20.045010 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:59:20.048919 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:59:20.055280 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:59:20.058495 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 11:59:20.062077 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 11:59:20.062159
6259 11:59:20.065324 CA PerBit enable=1, Macro0, CA PI delay=36
6260 11:59:20.065405
6261 11:59:20.068502 [CBTSetCACLKResult] CA Dly = 36
6262 11:59:20.068583 CS Dly: 1 (0~32)
6263 11:59:20.068647
6264 11:59:20.071712 ----->DramcWriteLeveling(PI) begin...
6265 11:59:20.071808 ==
6266 11:59:20.075435 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 11:59:20.082023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 11:59:20.082108 ==
6269 11:59:20.085154 Write leveling (Byte 0): 40 => 8
6270 11:59:20.088711 Write leveling (Byte 1): 40 => 8
6271 11:59:20.088793 DramcWriteLeveling(PI) end<-----
6272 11:59:20.088972
6273 11:59:20.092056 ==
6274 11:59:20.094922 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 11:59:20.098389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 11:59:20.098496 ==
6277 11:59:20.101357 [Gating] SW mode calibration
6278 11:59:20.108157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 11:59:20.111395 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 11:59:20.118318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 11:59:20.121207 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 11:59:20.125221 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 11:59:20.131724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 11:59:20.135086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 11:59:20.138133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 11:59:20.144601 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 11:59:20.147878 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 11:59:20.151418 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 11:59:20.154804 Total UI for P1: 0, mck2ui 16
6290 11:59:20.157732 best dqsien dly found for B0: ( 0, 14, 24)
6291 11:59:20.161247 Total UI for P1: 0, mck2ui 16
6292 11:59:20.164689 best dqsien dly found for B1: ( 0, 14, 24)
6293 11:59:20.167815 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 11:59:20.171163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 11:59:20.171247
6296 11:59:20.178026 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 11:59:20.180937 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 11:59:20.184274 [Gating] SW calibration Done
6299 11:59:20.184351 ==
6300 11:59:20.188169 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 11:59:20.191442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 11:59:20.191570 ==
6303 11:59:20.191675 RX Vref Scan: 0
6304 11:59:20.191766
6305 11:59:20.194414 RX Vref 0 -> 0, step: 1
6306 11:59:20.194520
6307 11:59:20.197744 RX Delay -410 -> 252, step: 16
6308 11:59:20.200919 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6309 11:59:20.207798 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6310 11:59:20.210868 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6311 11:59:20.214464 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6312 11:59:20.217340 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6313 11:59:20.224164 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6314 11:59:20.227393 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6315 11:59:20.230635 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6316 11:59:20.234157 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6317 11:59:20.237833 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6318 11:59:20.244373 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6319 11:59:20.247931 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6320 11:59:20.250854 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6321 11:59:20.257698 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6322 11:59:20.260939 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6323 11:59:20.264237 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6324 11:59:20.264319 ==
6325 11:59:20.267171 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 11:59:20.270610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 11:59:20.274122 ==
6328 11:59:20.274202 DQS Delay:
6329 11:59:20.274266 DQS0 = 27, DQS1 = 35
6330 11:59:20.277778 DQM Delay:
6331 11:59:20.277857 DQM0 = 10, DQM1 = 11
6332 11:59:20.280626 DQ Delay:
6333 11:59:20.280706 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6334 11:59:20.283928 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6335 11:59:20.287434 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6336 11:59:20.290650 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6337 11:59:20.290755
6338 11:59:20.290845
6339 11:59:20.290934 ==
6340 11:59:20.293876 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 11:59:20.300814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 11:59:20.300905 ==
6343 11:59:20.300970
6344 11:59:20.301029
6345 11:59:20.301085 TX Vref Scan disable
6346 11:59:20.303844 == TX Byte 0 ==
6347 11:59:20.307691 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 11:59:20.310685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 11:59:20.313879 == TX Byte 1 ==
6350 11:59:20.317210 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 11:59:20.320647 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 11:59:20.323807 ==
6353 11:59:20.323912 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 11:59:20.330565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 11:59:20.330687 ==
6356 11:59:20.330779
6357 11:59:20.330866
6358 11:59:20.330951 TX Vref Scan disable
6359 11:59:20.334134 == TX Byte 0 ==
6360 11:59:20.337745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 11:59:20.340782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 11:59:20.343863 == TX Byte 1 ==
6363 11:59:20.347242 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 11:59:20.351119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 11:59:20.351200
6366 11:59:20.354057 [DATLAT]
6367 11:59:20.354137 Freq=400, CH0 RK0
6368 11:59:20.354202
6369 11:59:20.357372 DATLAT Default: 0xf
6370 11:59:20.357477 0, 0xFFFF, sum = 0
6371 11:59:20.360658 1, 0xFFFF, sum = 0
6372 11:59:20.360788 2, 0xFFFF, sum = 0
6373 11:59:20.364408 3, 0xFFFF, sum = 0
6374 11:59:20.364507 4, 0xFFFF, sum = 0
6375 11:59:20.367513 5, 0xFFFF, sum = 0
6376 11:59:20.367595 6, 0xFFFF, sum = 0
6377 11:59:20.370687 7, 0xFFFF, sum = 0
6378 11:59:20.370769 8, 0xFFFF, sum = 0
6379 11:59:20.374287 9, 0xFFFF, sum = 0
6380 11:59:20.377189 10, 0xFFFF, sum = 0
6381 11:59:20.377313 11, 0xFFFF, sum = 0
6382 11:59:20.380830 12, 0xFFFF, sum = 0
6383 11:59:20.380913 13, 0x0, sum = 1
6384 11:59:20.384202 14, 0x0, sum = 2
6385 11:59:20.384287 15, 0x0, sum = 3
6386 11:59:20.384354 16, 0x0, sum = 4
6387 11:59:20.387159 best_step = 14
6388 11:59:20.387243
6389 11:59:20.387309 ==
6390 11:59:20.390498 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 11:59:20.393873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 11:59:20.393955 ==
6393 11:59:20.397450 RX Vref Scan: 1
6394 11:59:20.397556
6395 11:59:20.397687 RX Vref 0 -> 0, step: 1
6396 11:59:20.400729
6397 11:59:20.400809 RX Delay -311 -> 252, step: 8
6398 11:59:20.400873
6399 11:59:20.404309 Set Vref, RX VrefLevel [Byte0]: 53
6400 11:59:20.407386 [Byte1]: 50
6401 11:59:20.412343
6402 11:59:20.412423 Final RX Vref Byte 0 = 53 to rank0
6403 11:59:20.415501 Final RX Vref Byte 1 = 50 to rank0
6404 11:59:20.418542 Final RX Vref Byte 0 = 53 to rank1
6405 11:59:20.422388 Final RX Vref Byte 1 = 50 to rank1==
6406 11:59:20.425493 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 11:59:20.432205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 11:59:20.432320 ==
6409 11:59:20.432399 DQS Delay:
6410 11:59:20.435227 DQS0 = 24, DQS1 = 32
6411 11:59:20.435309 DQM Delay:
6412 11:59:20.435372 DQM0 = 8, DQM1 = 10
6413 11:59:20.438939 DQ Delay:
6414 11:59:20.442188 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6415 11:59:20.442269 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6416 11:59:20.445536 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6417 11:59:20.448668 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6418 11:59:20.448749
6419 11:59:20.448812
6420 11:59:20.458628 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6421 11:59:20.462150 CH0 RK0: MR19=C0C, MR18=CBB7
6422 11:59:20.468706 CH0_RK0: MR19=0xC0C, MR18=0xCBB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6423 11:59:20.468789 ==
6424 11:59:20.471729 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 11:59:20.475213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 11:59:20.475296 ==
6427 11:59:20.478421 [Gating] SW mode calibration
6428 11:59:20.485371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 11:59:20.488971 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 11:59:20.495206 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 11:59:20.498753 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 11:59:20.501794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 11:59:20.508770 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 11:59:20.511787 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 11:59:20.515035 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 11:59:20.522155 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 11:59:20.524938 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 11:59:20.529069 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 11:59:20.531879 Total UI for P1: 0, mck2ui 16
6440 11:59:20.535465 best dqsien dly found for B0: ( 0, 14, 24)
6441 11:59:20.538542 Total UI for P1: 0, mck2ui 16
6442 11:59:20.542340 best dqsien dly found for B1: ( 0, 14, 24)
6443 11:59:20.545290 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 11:59:20.548486 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 11:59:20.548567
6446 11:59:20.555034 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 11:59:20.558600 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 11:59:20.561935 [Gating] SW calibration Done
6449 11:59:20.562017 ==
6450 11:59:20.565048 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 11:59:20.568461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 11:59:20.568542 ==
6453 11:59:20.568607 RX Vref Scan: 0
6454 11:59:20.568666
6455 11:59:20.571736 RX Vref 0 -> 0, step: 1
6456 11:59:20.571816
6457 11:59:20.574697 RX Delay -410 -> 252, step: 16
6458 11:59:20.578329 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6459 11:59:20.584924 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6460 11:59:20.588165 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6461 11:59:20.591280 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6462 11:59:20.594754 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6463 11:59:20.601731 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6464 11:59:20.605085 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6465 11:59:20.607857 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6466 11:59:20.611353 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6467 11:59:20.617856 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6468 11:59:20.621084 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6469 11:59:20.624486 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6470 11:59:20.627646 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6471 11:59:20.634482 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6472 11:59:20.637970 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6473 11:59:20.641165 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6474 11:59:20.641266 ==
6475 11:59:20.644824 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 11:59:20.648059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 11:59:20.651212 ==
6478 11:59:20.651318 DQS Delay:
6479 11:59:20.651408 DQS0 = 19, DQS1 = 35
6480 11:59:20.654965 DQM Delay:
6481 11:59:20.655075 DQM0 = 5, DQM1 = 12
6482 11:59:20.658062 DQ Delay:
6483 11:59:20.658161 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6484 11:59:20.661742 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6485 11:59:20.664742 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6486 11:59:20.667759 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6487 11:59:20.667857
6488 11:59:20.667945
6489 11:59:20.668031 ==
6490 11:59:20.671587 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 11:59:20.677785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 11:59:20.677867 ==
6493 11:59:20.677931
6494 11:59:20.677990
6495 11:59:20.678047 TX Vref Scan disable
6496 11:59:20.681387 == TX Byte 0 ==
6497 11:59:20.684252 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6498 11:59:20.688091 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6499 11:59:20.691676 == TX Byte 1 ==
6500 11:59:20.694327 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6501 11:59:20.697719 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6502 11:59:20.697814 ==
6503 11:59:20.701336 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 11:59:20.707868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 11:59:20.707976 ==
6506 11:59:20.708068
6507 11:59:20.708154
6508 11:59:20.708238 TX Vref Scan disable
6509 11:59:20.711419 == TX Byte 0 ==
6510 11:59:20.714330 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6511 11:59:20.717862 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6512 11:59:20.721263 == TX Byte 1 ==
6513 11:59:20.724530 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6514 11:59:20.727965 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6515 11:59:20.728072
6516 11:59:20.731038 [DATLAT]
6517 11:59:20.731121 Freq=400, CH0 RK1
6518 11:59:20.731185
6519 11:59:20.734779 DATLAT Default: 0xe
6520 11:59:20.734859 0, 0xFFFF, sum = 0
6521 11:59:20.737850 1, 0xFFFF, sum = 0
6522 11:59:20.737932 2, 0xFFFF, sum = 0
6523 11:59:20.740661 3, 0xFFFF, sum = 0
6524 11:59:20.740769 4, 0xFFFF, sum = 0
6525 11:59:20.744199 5, 0xFFFF, sum = 0
6526 11:59:20.744316 6, 0xFFFF, sum = 0
6527 11:59:20.747355 7, 0xFFFF, sum = 0
6528 11:59:20.747464 8, 0xFFFF, sum = 0
6529 11:59:20.751124 9, 0xFFFF, sum = 0
6530 11:59:20.754189 10, 0xFFFF, sum = 0
6531 11:59:20.754271 11, 0xFFFF, sum = 0
6532 11:59:20.757433 12, 0xFFFF, sum = 0
6533 11:59:20.757542 13, 0x0, sum = 1
6534 11:59:20.760512 14, 0x0, sum = 2
6535 11:59:20.760621 15, 0x0, sum = 3
6536 11:59:20.764322 16, 0x0, sum = 4
6537 11:59:20.764430 best_step = 14
6538 11:59:20.764522
6539 11:59:20.764609 ==
6540 11:59:20.767403 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 11:59:20.770700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 11:59:20.770782 ==
6543 11:59:20.774273 RX Vref Scan: 0
6544 11:59:20.774353
6545 11:59:20.777227 RX Vref 0 -> 0, step: 1
6546 11:59:20.777309
6547 11:59:20.777373 RX Delay -311 -> 252, step: 8
6548 11:59:20.785855 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6549 11:59:20.789461 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6550 11:59:20.792508 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6551 11:59:20.795630 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6552 11:59:20.802922 iDelay=217, Bit 4, Center -8 (-231 ~ 216) 448
6553 11:59:20.805999 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6554 11:59:20.809162 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6555 11:59:20.812428 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6556 11:59:20.819034 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6557 11:59:20.822176 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6558 11:59:20.825804 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6559 11:59:20.829424 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6560 11:59:20.835759 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6561 11:59:20.838843 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6562 11:59:20.842113 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6563 11:59:20.849061 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6564 11:59:20.849143 ==
6565 11:59:20.852145 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 11:59:20.855853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 11:59:20.855935 ==
6568 11:59:20.855999 DQS Delay:
6569 11:59:20.859184 DQS0 = 24, DQS1 = 32
6570 11:59:20.859265 DQM Delay:
6571 11:59:20.862175 DQM0 = 9, DQM1 = 9
6572 11:59:20.862257 DQ Delay:
6573 11:59:20.865916 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6574 11:59:20.869029 DQ4 =16, DQ5 =0, DQ6 =12, DQ7 =16
6575 11:59:20.872193 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6576 11:59:20.875380 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6577 11:59:20.875461
6578 11:59:20.875525
6579 11:59:20.882065 [DQSOSCAuto] RK1, (LSB)MR18= 0xb858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6580 11:59:20.885486 CH0 RK1: MR19=C0C, MR18=B858
6581 11:59:20.892082 CH0_RK1: MR19=0xC0C, MR18=0xB858, DQSOSC=386, MR23=63, INC=396, DEC=264
6582 11:59:20.895780 [RxdqsGatingPostProcess] freq 400
6583 11:59:20.898743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 11:59:20.902345 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 11:59:20.905925 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 11:59:20.909036 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 11:59:20.912050 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 11:59:20.915710 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 11:59:20.918991 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 11:59:20.922322 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 11:59:20.925521 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 11:59:20.928593 Pre-setting of DQS Precalculation
6593 11:59:20.932336 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 11:59:20.932448 ==
6595 11:59:20.935348 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 11:59:20.942208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 11:59:20.942389 ==
6598 11:59:20.945517 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 11:59:20.952310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6600 11:59:20.955543 [CA 0] Center 36 (8~64) winsize 57
6601 11:59:20.958554 [CA 1] Center 36 (8~64) winsize 57
6602 11:59:20.962211 [CA 2] Center 36 (8~64) winsize 57
6603 11:59:20.965282 [CA 3] Center 36 (8~64) winsize 57
6604 11:59:20.968576 [CA 4] Center 36 (8~64) winsize 57
6605 11:59:20.971546 [CA 5] Center 36 (8~64) winsize 57
6606 11:59:20.971652
6607 11:59:20.975513 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6608 11:59:20.975594
6609 11:59:20.978675 [CATrainingPosCal] consider 1 rank data
6610 11:59:20.981564 u2DelayCellTimex100 = 270/100 ps
6611 11:59:20.985573 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:59:20.988332 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:59:20.991837 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:59:20.995325 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:59:20.998583 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 11:59:21.005289 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 11:59:21.005372
6618 11:59:21.008300 CA PerBit enable=1, Macro0, CA PI delay=36
6619 11:59:21.008382
6620 11:59:21.011823 [CBTSetCACLKResult] CA Dly = 36
6621 11:59:21.011905 CS Dly: 1 (0~32)
6622 11:59:21.011969 ==
6623 11:59:21.014931 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 11:59:21.018426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 11:59:21.022064 ==
6626 11:59:21.025382 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 11:59:21.031501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6628 11:59:21.034682 [CA 0] Center 36 (8~64) winsize 57
6629 11:59:21.038793 [CA 1] Center 36 (8~64) winsize 57
6630 11:59:21.041376 [CA 2] Center 36 (8~64) winsize 57
6631 11:59:21.045068 [CA 3] Center 36 (8~64) winsize 57
6632 11:59:21.048183 [CA 4] Center 36 (8~64) winsize 57
6633 11:59:21.051328 [CA 5] Center 36 (8~64) winsize 57
6634 11:59:21.051445
6635 11:59:21.054872 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6636 11:59:21.054954
6637 11:59:21.058521 [CATrainingPosCal] consider 2 rank data
6638 11:59:21.062001 u2DelayCellTimex100 = 270/100 ps
6639 11:59:21.065099 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:59:21.067949 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:59:21.071397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:59:21.074942 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:59:21.078145 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 11:59:21.081301 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 11:59:21.081382
6646 11:59:21.084958 CA PerBit enable=1, Macro0, CA PI delay=36
6647 11:59:21.085067
6648 11:59:21.088013 [CBTSetCACLKResult] CA Dly = 36
6649 11:59:21.091060 CS Dly: 1 (0~32)
6650 11:59:21.091165
6651 11:59:21.094896 ----->DramcWriteLeveling(PI) begin...
6652 11:59:21.094995 ==
6653 11:59:21.097893 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 11:59:21.101553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 11:59:21.101671 ==
6656 11:59:21.104423 Write leveling (Byte 0): 40 => 8
6657 11:59:21.107762 Write leveling (Byte 1): 40 => 8
6658 11:59:21.111283 DramcWriteLeveling(PI) end<-----
6659 11:59:21.111363
6660 11:59:21.111426 ==
6661 11:59:21.114380 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 11:59:21.117964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 11:59:21.118045 ==
6664 11:59:21.121243 [Gating] SW mode calibration
6665 11:59:21.128155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 11:59:21.134477 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 11:59:21.137565 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 11:59:21.144650 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 11:59:21.148022 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 11:59:21.151213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 11:59:21.154689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 11:59:21.161086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 11:59:21.164673 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 11:59:21.167779 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 11:59:21.174933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 11:59:21.178129 Total UI for P1: 0, mck2ui 16
6677 11:59:21.181743 best dqsien dly found for B0: ( 0, 14, 24)
6678 11:59:21.184262 Total UI for P1: 0, mck2ui 16
6679 11:59:21.187889 best dqsien dly found for B1: ( 0, 14, 24)
6680 11:59:21.191634 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 11:59:21.194804 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 11:59:21.194885
6683 11:59:21.198526 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 11:59:21.201208 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 11:59:21.204585 [Gating] SW calibration Done
6686 11:59:21.204668 ==
6687 11:59:21.207447 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 11:59:21.211291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 11:59:21.211373 ==
6690 11:59:21.214143 RX Vref Scan: 0
6691 11:59:21.214216
6692 11:59:21.214276 RX Vref 0 -> 0, step: 1
6693 11:59:21.217656
6694 11:59:21.217724 RX Delay -410 -> 252, step: 16
6695 11:59:21.224085 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6696 11:59:21.227456 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6697 11:59:21.230972 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6698 11:59:21.234183 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6699 11:59:21.241300 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6700 11:59:21.244111 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6701 11:59:21.247875 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6702 11:59:21.251292 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6703 11:59:21.257294 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6704 11:59:21.260726 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6705 11:59:21.264451 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6706 11:59:21.267511 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6707 11:59:21.274027 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6708 11:59:21.277534 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6709 11:59:21.281104 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6710 11:59:21.284031 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6711 11:59:21.287609 ==
6712 11:59:21.290917 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 11:59:21.294222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 11:59:21.294304 ==
6715 11:59:21.294368 DQS Delay:
6716 11:59:21.297447 DQS0 = 35, DQS1 = 35
6717 11:59:21.297528 DQM Delay:
6718 11:59:21.300750 DQM0 = 18, DQM1 = 14
6719 11:59:21.300831 DQ Delay:
6720 11:59:21.304356 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6721 11:59:21.307426 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6722 11:59:21.310589 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6723 11:59:21.313757 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6724 11:59:21.313837
6725 11:59:21.313901
6726 11:59:21.313960 ==
6727 11:59:21.317502 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 11:59:21.320429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 11:59:21.320510 ==
6730 11:59:21.320574
6731 11:59:21.320633
6732 11:59:21.324242 TX Vref Scan disable
6733 11:59:21.327304 == TX Byte 0 ==
6734 11:59:21.330473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 11:59:21.333999 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 11:59:21.334081 == TX Byte 1 ==
6737 11:59:21.340522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 11:59:21.344032 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 11:59:21.344113 ==
6740 11:59:21.347222 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 11:59:21.350366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 11:59:21.350448 ==
6743 11:59:21.350512
6744 11:59:21.350571
6745 11:59:21.353475 TX Vref Scan disable
6746 11:59:21.357068 == TX Byte 0 ==
6747 11:59:21.360317 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 11:59:21.363941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 11:59:21.367201 == TX Byte 1 ==
6750 11:59:21.370317 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 11:59:21.374013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 11:59:21.374094
6753 11:59:21.374158 [DATLAT]
6754 11:59:21.377357 Freq=400, CH1 RK0
6755 11:59:21.377438
6756 11:59:21.377502 DATLAT Default: 0xf
6757 11:59:21.380462 0, 0xFFFF, sum = 0
6758 11:59:21.380545 1, 0xFFFF, sum = 0
6759 11:59:21.383930 2, 0xFFFF, sum = 0
6760 11:59:21.384011 3, 0xFFFF, sum = 0
6761 11:59:21.387048 4, 0xFFFF, sum = 0
6762 11:59:21.387130 5, 0xFFFF, sum = 0
6763 11:59:21.390274 6, 0xFFFF, sum = 0
6764 11:59:21.390355 7, 0xFFFF, sum = 0
6765 11:59:21.393842 8, 0xFFFF, sum = 0
6766 11:59:21.396877 9, 0xFFFF, sum = 0
6767 11:59:21.396959 10, 0xFFFF, sum = 0
6768 11:59:21.400496 11, 0xFFFF, sum = 0
6769 11:59:21.400577 12, 0xFFFF, sum = 0
6770 11:59:21.403815 13, 0x0, sum = 1
6771 11:59:21.403897 14, 0x0, sum = 2
6772 11:59:21.407068 15, 0x0, sum = 3
6773 11:59:21.407150 16, 0x0, sum = 4
6774 11:59:21.407215 best_step = 14
6775 11:59:21.407275
6776 11:59:21.410137 ==
6777 11:59:21.413477 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 11:59:21.417332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 11:59:21.417414 ==
6780 11:59:21.417477 RX Vref Scan: 1
6781 11:59:21.417537
6782 11:59:21.420640 RX Vref 0 -> 0, step: 1
6783 11:59:21.420721
6784 11:59:21.423708 RX Delay -311 -> 252, step: 8
6785 11:59:21.423789
6786 11:59:21.427153 Set Vref, RX VrefLevel [Byte0]: 56
6787 11:59:21.430161 [Byte1]: 53
6788 11:59:21.433852
6789 11:59:21.433934 Final RX Vref Byte 0 = 56 to rank0
6790 11:59:21.437014 Final RX Vref Byte 1 = 53 to rank0
6791 11:59:21.440843 Final RX Vref Byte 0 = 56 to rank1
6792 11:59:21.443918 Final RX Vref Byte 1 = 53 to rank1==
6793 11:59:21.447280 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 11:59:21.453769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 11:59:21.453851 ==
6796 11:59:21.453915 DQS Delay:
6797 11:59:21.457225 DQS0 = 24, DQS1 = 32
6798 11:59:21.457307 DQM Delay:
6799 11:59:21.457371 DQM0 = 6, DQM1 = 10
6800 11:59:21.460405 DQ Delay:
6801 11:59:21.463582 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6802 11:59:21.463663 DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4
6803 11:59:21.466893 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6804 11:59:21.470483 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6805 11:59:21.470565
6806 11:59:21.470629
6807 11:59:21.480574 [DQSOSCAuto] RK0, (LSB)MR18= 0x94ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6808 11:59:21.483590 CH1 RK0: MR19=C0C, MR18=94CE
6809 11:59:21.490186 CH1_RK0: MR19=0xC0C, MR18=0x94CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6810 11:59:21.490268 ==
6811 11:59:21.493891 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 11:59:21.497116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 11:59:21.497223 ==
6814 11:59:21.500247 [Gating] SW mode calibration
6815 11:59:21.507116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 11:59:21.510454 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 11:59:21.516786 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 11:59:21.520367 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 11:59:21.523433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 11:59:21.530087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 11:59:21.533431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 11:59:21.536519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 11:59:21.543045 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 11:59:21.546811 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 11:59:21.549697 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 11:59:21.553800 Total UI for P1: 0, mck2ui 16
6827 11:59:21.556675 best dqsien dly found for B0: ( 0, 14, 24)
6828 11:59:21.560044 Total UI for P1: 0, mck2ui 16
6829 11:59:21.563518 best dqsien dly found for B1: ( 0, 14, 24)
6830 11:59:21.566535 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 11:59:21.569833 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 11:59:21.573103
6833 11:59:21.576563 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 11:59:21.579649 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 11:59:21.583338 [Gating] SW calibration Done
6836 11:59:21.583428 ==
6837 11:59:21.586558 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 11:59:21.589703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 11:59:21.589821 ==
6840 11:59:21.589915 RX Vref Scan: 0
6841 11:59:21.593304
6842 11:59:21.593405 RX Vref 0 -> 0, step: 1
6843 11:59:21.593491
6844 11:59:21.596454 RX Delay -410 -> 252, step: 16
6845 11:59:21.599500 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6846 11:59:21.606396 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6847 11:59:21.609777 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6848 11:59:21.613393 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6849 11:59:21.616452 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6850 11:59:21.623187 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6851 11:59:21.626224 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6852 11:59:21.629659 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6853 11:59:21.633120 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6854 11:59:21.636804 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6855 11:59:21.643146 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6856 11:59:21.646426 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6857 11:59:21.649813 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6858 11:59:21.656393 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6859 11:59:21.659962 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6860 11:59:21.663217 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6861 11:59:21.663299 ==
6862 11:59:21.666409 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 11:59:21.669909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 11:59:21.672899 ==
6865 11:59:21.673005 DQS Delay:
6866 11:59:21.673096 DQS0 = 27, DQS1 = 35
6867 11:59:21.676422 DQM Delay:
6868 11:59:21.676503 DQM0 = 12, DQM1 = 14
6869 11:59:21.679623 DQ Delay:
6870 11:59:21.679703 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6871 11:59:21.683027 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6872 11:59:21.686338 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6873 11:59:21.689497 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6874 11:59:21.689637
6875 11:59:21.689703
6876 11:59:21.692620 ==
6877 11:59:21.692730 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 11:59:21.699535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 11:59:21.699617 ==
6880 11:59:21.699681
6881 11:59:21.699740
6882 11:59:21.702678 TX Vref Scan disable
6883 11:59:21.702759 == TX Byte 0 ==
6884 11:59:21.705866 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6885 11:59:21.709006 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6886 11:59:21.713119 == TX Byte 1 ==
6887 11:59:21.715885 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6888 11:59:21.719463 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6889 11:59:21.722517 ==
6890 11:59:21.725605 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 11:59:21.729345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 11:59:21.729452 ==
6893 11:59:21.729544
6894 11:59:21.729640
6895 11:59:21.732579 TX Vref Scan disable
6896 11:59:21.732697 == TX Byte 0 ==
6897 11:59:21.735468 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6898 11:59:21.742232 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6899 11:59:21.742355 == TX Byte 1 ==
6900 11:59:21.745610 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6901 11:59:21.752247 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6902 11:59:21.752351
6903 11:59:21.752440 [DATLAT]
6904 11:59:21.752526 Freq=400, CH1 RK1
6905 11:59:21.752610
6906 11:59:21.755660 DATLAT Default: 0xe
6907 11:59:21.755766 0, 0xFFFF, sum = 0
6908 11:59:21.759045 1, 0xFFFF, sum = 0
6909 11:59:21.759146 2, 0xFFFF, sum = 0
6910 11:59:21.762042 3, 0xFFFF, sum = 0
6911 11:59:21.765737 4, 0xFFFF, sum = 0
6912 11:59:21.765820 5, 0xFFFF, sum = 0
6913 11:59:21.768799 6, 0xFFFF, sum = 0
6914 11:59:21.768883 7, 0xFFFF, sum = 0
6915 11:59:21.772015 8, 0xFFFF, sum = 0
6916 11:59:21.772097 9, 0xFFFF, sum = 0
6917 11:59:21.776073 10, 0xFFFF, sum = 0
6918 11:59:21.776187 11, 0xFFFF, sum = 0
6919 11:59:21.778855 12, 0xFFFF, sum = 0
6920 11:59:21.778939 13, 0x0, sum = 1
6921 11:59:21.782415 14, 0x0, sum = 2
6922 11:59:21.782524 15, 0x0, sum = 3
6923 11:59:21.786066 16, 0x0, sum = 4
6924 11:59:21.786151 best_step = 14
6925 11:59:21.786216
6926 11:59:21.786277 ==
6927 11:59:21.789030 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 11:59:21.793077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 11:59:21.795396 ==
6930 11:59:21.795481 RX Vref Scan: 0
6931 11:59:21.795545
6932 11:59:21.798522 RX Vref 0 -> 0, step: 1
6933 11:59:21.798621
6934 11:59:21.801894 RX Delay -311 -> 252, step: 8
6935 11:59:21.805232 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6936 11:59:21.812281 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6937 11:59:21.815379 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6938 11:59:21.818829 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6939 11:59:21.821836 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6940 11:59:21.828380 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6941 11:59:21.832165 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6942 11:59:21.835117 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6943 11:59:21.838691 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6944 11:59:21.844994 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6945 11:59:21.848228 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6946 11:59:21.851560 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6947 11:59:21.854810 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6948 11:59:21.861793 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6949 11:59:21.864887 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6950 11:59:21.868407 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6951 11:59:21.868489 ==
6952 11:59:21.871368 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 11:59:21.878276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 11:59:21.878360 ==
6955 11:59:21.878425 DQS Delay:
6956 11:59:21.881384 DQS0 = 28, DQS1 = 36
6957 11:59:21.881465 DQM Delay:
6958 11:59:21.881529 DQM0 = 11, DQM1 = 14
6959 11:59:21.884848 DQ Delay:
6960 11:59:21.887840 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6961 11:59:21.891591 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6962 11:59:21.891673 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6963 11:59:21.894769 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6964 11:59:21.894850
6965 11:59:21.898271
6966 11:59:21.904830 [DQSOSCAuto] RK1, (LSB)MR18= 0xc354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6967 11:59:21.908009 CH1 RK1: MR19=C0C, MR18=C354
6968 11:59:21.914757 CH1_RK1: MR19=0xC0C, MR18=0xC354, DQSOSC=385, MR23=63, INC=398, DEC=265
6969 11:59:21.918236 [RxdqsGatingPostProcess] freq 400
6970 11:59:21.921730 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 11:59:21.924899 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 11:59:21.927893 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 11:59:21.931575 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 11:59:21.934584 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 11:59:21.938256 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 11:59:21.941275 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 11:59:21.944916 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 11:59:21.948063 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 11:59:21.951802 Pre-setting of DQS Precalculation
6980 11:59:21.955026 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 11:59:21.961533 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 11:59:21.968096 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 11:59:21.971563
6984 11:59:21.971664
6985 11:59:21.971744 [Calibration Summary] 800 Mbps
6986 11:59:21.974526 CH 0, Rank 0
6987 11:59:21.974607 SW Impedance : PASS
6988 11:59:21.978033 DUTY Scan : NO K
6989 11:59:21.981426 ZQ Calibration : PASS
6990 11:59:21.981508 Jitter Meter : NO K
6991 11:59:21.985000 CBT Training : PASS
6992 11:59:21.988296 Write leveling : PASS
6993 11:59:21.988378 RX DQS gating : PASS
6994 11:59:21.991441 RX DQ/DQS(RDDQC) : PASS
6995 11:59:21.994658 TX DQ/DQS : PASS
6996 11:59:21.994740 RX DATLAT : PASS
6997 11:59:21.998620 RX DQ/DQS(Engine): PASS
6998 11:59:22.001476 TX OE : NO K
6999 11:59:22.001573 All Pass.
7000 11:59:22.001665
7001 11:59:22.001727 CH 0, Rank 1
7002 11:59:22.005114 SW Impedance : PASS
7003 11:59:22.008354 DUTY Scan : NO K
7004 11:59:22.008435 ZQ Calibration : PASS
7005 11:59:22.011647 Jitter Meter : NO K
7006 11:59:22.011728 CBT Training : PASS
7007 11:59:22.014773 Write leveling : NO K
7008 11:59:22.018085 RX DQS gating : PASS
7009 11:59:22.018166 RX DQ/DQS(RDDQC) : PASS
7010 11:59:22.021257 TX DQ/DQS : PASS
7011 11:59:22.024437 RX DATLAT : PASS
7012 11:59:22.024518 RX DQ/DQS(Engine): PASS
7013 11:59:22.028044 TX OE : NO K
7014 11:59:22.028125 All Pass.
7015 11:59:22.028189
7016 11:59:22.031466 CH 1, Rank 0
7017 11:59:22.031547 SW Impedance : PASS
7018 11:59:22.034411 DUTY Scan : NO K
7019 11:59:22.038257 ZQ Calibration : PASS
7020 11:59:22.038338 Jitter Meter : NO K
7021 11:59:22.041476 CBT Training : PASS
7022 11:59:22.044993 Write leveling : PASS
7023 11:59:22.045075 RX DQS gating : PASS
7024 11:59:22.047855 RX DQ/DQS(RDDQC) : PASS
7025 11:59:22.051198 TX DQ/DQS : PASS
7026 11:59:22.051279 RX DATLAT : PASS
7027 11:59:22.054684 RX DQ/DQS(Engine): PASS
7028 11:59:22.057890 TX OE : NO K
7029 11:59:22.057989 All Pass.
7030 11:59:22.058068
7031 11:59:22.058132 CH 1, Rank 1
7032 11:59:22.061307 SW Impedance : PASS
7033 11:59:22.061429 DUTY Scan : NO K
7034 11:59:22.065017 ZQ Calibration : PASS
7035 11:59:22.068115 Jitter Meter : NO K
7036 11:59:22.068196 CBT Training : PASS
7037 11:59:22.071236 Write leveling : NO K
7038 11:59:22.074832 RX DQS gating : PASS
7039 11:59:22.074913 RX DQ/DQS(RDDQC) : PASS
7040 11:59:22.077780 TX DQ/DQS : PASS
7041 11:59:22.081261 RX DATLAT : PASS
7042 11:59:22.081343 RX DQ/DQS(Engine): PASS
7043 11:59:22.084412 TX OE : NO K
7044 11:59:22.084493 All Pass.
7045 11:59:22.084557
7046 11:59:22.087904 DramC Write-DBI off
7047 11:59:22.091132 PER_BANK_REFRESH: Hybrid Mode
7048 11:59:22.091214 TX_TRACKING: ON
7049 11:59:22.101404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 11:59:22.104431 [FAST_K] Save calibration result to emmc
7051 11:59:22.108183 dramc_set_vcore_voltage set vcore to 725000
7052 11:59:22.111205 Read voltage for 1600, 0
7053 11:59:22.111299 Vio18 = 0
7054 11:59:22.111363 Vcore = 725000
7055 11:59:22.114742 Vdram = 0
7056 11:59:22.114823 Vddq = 0
7057 11:59:22.114887 Vmddr = 0
7058 11:59:22.121176 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 11:59:22.124828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 11:59:22.128149 MEM_TYPE=3, freq_sel=13
7061 11:59:22.130857 sv_algorithm_assistance_LP4_3733
7062 11:59:22.134335 ============ PULL DRAM RESETB DOWN ============
7063 11:59:22.138357 ========== PULL DRAM RESETB DOWN end =========
7064 11:59:22.144354 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 11:59:22.148026 ===================================
7066 11:59:22.148107 LPDDR4 DRAM CONFIGURATION
7067 11:59:22.151571 ===================================
7068 11:59:22.155067 EX_ROW_EN[0] = 0x0
7069 11:59:22.157996 EX_ROW_EN[1] = 0x0
7070 11:59:22.158103 LP4Y_EN = 0x0
7071 11:59:22.161367 WORK_FSP = 0x1
7072 11:59:22.161493 WL = 0x5
7073 11:59:22.164223 RL = 0x5
7074 11:59:22.164328 BL = 0x2
7075 11:59:22.167736 RPST = 0x0
7076 11:59:22.167841 RD_PRE = 0x0
7077 11:59:22.171021 WR_PRE = 0x1
7078 11:59:22.171117 WR_PST = 0x1
7079 11:59:22.174590 DBI_WR = 0x0
7080 11:59:22.174665 DBI_RD = 0x0
7081 11:59:22.177940 OTF = 0x1
7082 11:59:22.181308 ===================================
7083 11:59:22.184179 ===================================
7084 11:59:22.184279 ANA top config
7085 11:59:22.187514 ===================================
7086 11:59:22.191133 DLL_ASYNC_EN = 0
7087 11:59:22.194060 ALL_SLAVE_EN = 0
7088 11:59:22.197637 NEW_RANK_MODE = 1
7089 11:59:22.197749 DLL_IDLE_MODE = 1
7090 11:59:22.200689 LP45_APHY_COMB_EN = 1
7091 11:59:22.204079 TX_ODT_DIS = 0
7092 11:59:22.207403 NEW_8X_MODE = 1
7093 11:59:22.210695 ===================================
7094 11:59:22.214400 ===================================
7095 11:59:22.217771 data_rate = 3200
7096 11:59:22.217875 CKR = 1
7097 11:59:22.220593 DQ_P2S_RATIO = 8
7098 11:59:22.224501 ===================================
7099 11:59:22.227374 CA_P2S_RATIO = 8
7100 11:59:22.230525 DQ_CA_OPEN = 0
7101 11:59:22.234201 DQ_SEMI_OPEN = 0
7102 11:59:22.237377 CA_SEMI_OPEN = 0
7103 11:59:22.237484 CA_FULL_RATE = 0
7104 11:59:22.240456 DQ_CKDIV4_EN = 0
7105 11:59:22.244501 CA_CKDIV4_EN = 0
7106 11:59:22.247332 CA_PREDIV_EN = 0
7107 11:59:22.250347 PH8_DLY = 12
7108 11:59:22.254079 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 11:59:22.254160 DQ_AAMCK_DIV = 4
7110 11:59:22.257416 CA_AAMCK_DIV = 4
7111 11:59:22.260921 CA_ADMCK_DIV = 4
7112 11:59:22.264291 DQ_TRACK_CA_EN = 0
7113 11:59:22.267498 CA_PICK = 1600
7114 11:59:22.270879 CA_MCKIO = 1600
7115 11:59:22.274083 MCKIO_SEMI = 0
7116 11:59:22.274165 PLL_FREQ = 3068
7117 11:59:22.277216 DQ_UI_PI_RATIO = 32
7118 11:59:22.280357 CA_UI_PI_RATIO = 0
7119 11:59:22.283930 ===================================
7120 11:59:22.287120 ===================================
7121 11:59:22.290645 memory_type:LPDDR4
7122 11:59:22.290727 GP_NUM : 10
7123 11:59:22.293930 SRAM_EN : 1
7124 11:59:22.297093 MD32_EN : 0
7125 11:59:22.300699 ===================================
7126 11:59:22.300781 [ANA_INIT] >>>>>>>>>>>>>>
7127 11:59:22.304166 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 11:59:22.307249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 11:59:22.310741 ===================================
7130 11:59:22.314465 data_rate = 3200,PCW = 0X7600
7131 11:59:22.317206 ===================================
7132 11:59:22.320741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 11:59:22.327112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 11:59:22.330306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 11:59:22.337155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 11:59:22.340317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 11:59:22.343494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 11:59:22.343577 [ANA_INIT] flow start
7139 11:59:22.347398 [ANA_INIT] PLL >>>>>>>>
7140 11:59:22.350271 [ANA_INIT] PLL <<<<<<<<
7141 11:59:22.353973 [ANA_INIT] MIDPI >>>>>>>>
7142 11:59:22.354055 [ANA_INIT] MIDPI <<<<<<<<
7143 11:59:22.357173 [ANA_INIT] DLL >>>>>>>>
7144 11:59:22.360233 [ANA_INIT] DLL <<<<<<<<
7145 11:59:22.360341 [ANA_INIT] flow end
7146 11:59:22.363412 ============ LP4 DIFF to SE enter ============
7147 11:59:22.370587 ============ LP4 DIFF to SE exit ============
7148 11:59:22.370670 [ANA_INIT] <<<<<<<<<<<<<
7149 11:59:22.373608 [Flow] Enable top DCM control >>>>>
7150 11:59:22.376783 [Flow] Enable top DCM control <<<<<
7151 11:59:22.380080 Enable DLL master slave shuffle
7152 11:59:22.387202 ==============================================================
7153 11:59:22.387288 Gating Mode config
7154 11:59:22.393283 ==============================================================
7155 11:59:22.396857 Config description:
7156 11:59:22.406674 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 11:59:22.413269 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 11:59:22.416892 SELPH_MODE 0: By rank 1: By Phase
7159 11:59:22.423566 ==============================================================
7160 11:59:22.426832 GAT_TRACK_EN = 1
7161 11:59:22.430066 RX_GATING_MODE = 2
7162 11:59:22.430177 RX_GATING_TRACK_MODE = 2
7163 11:59:22.433858 SELPH_MODE = 1
7164 11:59:24.931070 PICG_EARLY_EN = 1
7165 11:59:24.931359 VALID_LAT_VALUE = 1
7166 11:59:24.931486 ==============================================================
7167 11:59:24.931584 Enter into Gating configuration >>>>
7168 11:59:24.931682 Exit from Gating configuration <<<<
7169 11:59:24.931778 Enter into DVFS_PRE_config >>>>>
7170 11:59:24.931878 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 11:59:24.931980 Exit from DVFS_PRE_config <<<<<
7172 11:59:24.932074 Enter into PICG configuration >>>>
7173 11:59:24.932172 Exit from PICG configuration <<<<
7174 11:59:24.932266 [RX_INPUT] configuration >>>>>
7175 11:59:24.932360 [RX_INPUT] configuration <<<<<
7176 11:59:24.932454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 11:59:24.932548 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 11:59:24.932646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 11:59:24.932710 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 11:59:24.932786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 11:59:24.932856 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 11:59:24.932962 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 11:59:24.933054 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 11:59:24.933184 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 11:59:24.933279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 11:59:24.933374 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 11:59:24.933465 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 11:59:24.933554 ===================================
7189 11:59:24.933684 LPDDR4 DRAM CONFIGURATION
7190 11:59:24.933768 ===================================
7191 11:59:24.933852 EX_ROW_EN[0] = 0x0
7192 11:59:24.933934 EX_ROW_EN[1] = 0x0
7193 11:59:24.934015 LP4Y_EN = 0x0
7194 11:59:24.934099 WORK_FSP = 0x1
7195 11:59:24.934183 WL = 0x5
7196 11:59:24.934263 RL = 0x5
7197 11:59:24.934346 BL = 0x2
7198 11:59:24.934429 RPST = 0x0
7199 11:59:24.934512 RD_PRE = 0x0
7200 11:59:24.934592 WR_PRE = 0x1
7201 11:59:24.934675 WR_PST = 0x1
7202 11:59:24.934758 DBI_WR = 0x0
7203 11:59:24.934838 DBI_RD = 0x0
7204 11:59:24.934918 OTF = 0x1
7205 11:59:24.935003 ===================================
7206 11:59:24.935092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 11:59:24.935225 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 11:59:24.935315 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 11:59:24.935401 ===================================
7210 11:59:24.935481 LPDDR4 DRAM CONFIGURATION
7211 11:59:24.935566 ===================================
7212 11:59:24.935650 EX_ROW_EN[0] = 0x10
7213 11:59:24.935732 EX_ROW_EN[1] = 0x0
7214 11:59:24.935817 LP4Y_EN = 0x0
7215 11:59:24.935900 WORK_FSP = 0x1
7216 11:59:24.935984 WL = 0x5
7217 11:59:24.936099 RL = 0x5
7218 11:59:24.936198 BL = 0x2
7219 11:59:24.936293 RPST = 0x0
7220 11:59:24.936397 RD_PRE = 0x0
7221 11:59:24.936493 WR_PRE = 0x1
7222 11:59:24.936583 WR_PST = 0x1
7223 11:59:24.936670 DBI_WR = 0x0
7224 11:59:24.936754 DBI_RD = 0x0
7225 11:59:24.936813 OTF = 0x1
7226 11:59:24.936904 ===================================
7227 11:59:24.936993 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 11:59:24.937097 ==
7229 11:59:24.937179 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 11:59:24.937260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 11:59:24.937345 ==
7232 11:59:24.937429 [Duty_Offset_Calibration]
7233 11:59:24.937509 B0:2 B1:1 CA:1
7234 11:59:24.937615
7235 11:59:24.937688 [DutyScan_Calibration_Flow] k_type=0
7236 11:59:24.937742
7237 11:59:24.937794 ==CLK 0==
7238 11:59:24.937845 Final CLK duty delay cell = 0
7239 11:59:24.937902 [0] MAX Duty = 5187%(X100), DQS PI = 22
7240 11:59:24.937956 [0] MIN Duty = 4876%(X100), DQS PI = 48
7241 11:59:24.938025 [0] AVG Duty = 5031%(X100)
7242 11:59:24.938107
7243 11:59:24.938188 CH0 CLK Duty spec in!! Max-Min= 311%
7244 11:59:24.938272 [DutyScan_Calibration_Flow] ====Done====
7245 11:59:24.938354
7246 11:59:24.938434 [DutyScan_Calibration_Flow] k_type=1
7247 11:59:24.938517
7248 11:59:24.938599 ==DQS 0 ==
7249 11:59:24.938681 Final DQS duty delay cell = -4
7250 11:59:24.938763 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7251 11:59:24.938847 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7252 11:59:24.938930 [-4] AVG Duty = 4891%(X100)
7253 11:59:24.939010
7254 11:59:24.939090 ==DQS 1 ==
7255 11:59:24.939207 Final DQS duty delay cell = 0
7256 11:59:24.939290 [0] MAX Duty = 5187%(X100), DQS PI = 4
7257 11:59:24.939371 [0] MIN Duty = 5062%(X100), DQS PI = 32
7258 11:59:24.939455 [0] AVG Duty = 5124%(X100)
7259 11:59:24.939537
7260 11:59:24.939617 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7261 11:59:24.939699
7262 11:59:24.939782 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7263 11:59:24.939865 [DutyScan_Calibration_Flow] ====Done====
7264 11:59:24.939945
7265 11:59:24.940028 [DutyScan_Calibration_Flow] k_type=3
7266 11:59:24.940110
7267 11:59:24.940190 ==DQM 0 ==
7268 11:59:24.940270 Final DQM duty delay cell = 0
7269 11:59:24.940355 [0] MAX Duty = 5187%(X100), DQS PI = 26
7270 11:59:24.940438 [0] MIN Duty = 4907%(X100), DQS PI = 56
7271 11:59:24.940518 [0] AVG Duty = 5047%(X100)
7272 11:59:24.940601
7273 11:59:24.940684 ==DQM 1 ==
7274 11:59:24.940764 Final DQM duty delay cell = 0
7275 11:59:24.940845 [0] MAX Duty = 5187%(X100), DQS PI = 4
7276 11:59:24.940908 [0] MIN Duty = 5031%(X100), DQS PI = 50
7277 11:59:24.940968 [0] AVG Duty = 5109%(X100)
7278 11:59:24.941049
7279 11:59:24.941129 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7280 11:59:24.941212
7281 11:59:24.941295 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7282 11:59:24.941376 [DutyScan_Calibration_Flow] ====Done====
7283 11:59:24.941457
7284 11:59:24.941540 [DutyScan_Calibration_Flow] k_type=2
7285 11:59:24.941650
7286 11:59:24.941703 ==DQ 0 ==
7287 11:59:24.941764 Final DQ duty delay cell = 0
7288 11:59:24.941849 [0] MAX Duty = 5062%(X100), DQS PI = 24
7289 11:59:24.941931 [0] MIN Duty = 4907%(X100), DQS PI = 0
7290 11:59:24.942013 [0] AVG Duty = 4984%(X100)
7291 11:59:24.942098
7292 11:59:24.942178 ==DQ 1 ==
7293 11:59:24.942258 Final DQ duty delay cell = 0
7294 11:59:24.942342 [0] MAX Duty = 5156%(X100), DQS PI = 22
7295 11:59:24.942425 [0] MIN Duty = 4938%(X100), DQS PI = 34
7296 11:59:24.942506 [0] AVG Duty = 5047%(X100)
7297 11:59:24.942587
7298 11:59:24.942670 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7299 11:59:24.942750
7300 11:59:24.943047 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7301 11:59:24.943226 [DutyScan_Calibration_Flow] ====Done====
7302 11:59:24.943326 ==
7303 11:59:24.943407 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 11:59:24.943491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 11:59:24.943574 ==
7306 11:59:24.943655 [Duty_Offset_Calibration]
7307 11:59:24.943734 B0:1 B1:0 CA:0
7308 11:59:24.943817
7309 11:59:24.943899 [DutyScan_Calibration_Flow] k_type=0
7310 11:59:24.943979
7311 11:59:24.944060 ==CLK 0==
7312 11:59:24.944141 Final CLK duty delay cell = -4
7313 11:59:24.944225 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7314 11:59:24.944306 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7315 11:59:24.944389 [-4] AVG Duty = 4922%(X100)
7316 11:59:24.944471
7317 11:59:24.944550 CH1 CLK Duty spec in!! Max-Min= 156%
7318 11:59:24.944631 [DutyScan_Calibration_Flow] ====Done====
7319 11:59:24.944690
7320 11:59:24.944745 [DutyScan_Calibration_Flow] k_type=1
7321 11:59:24.944797
7322 11:59:24.944848 ==DQS 0 ==
7323 11:59:24.944899 Final DQS duty delay cell = 0
7324 11:59:24.944958 [0] MAX Duty = 5094%(X100), DQS PI = 16
7325 11:59:24.945042 [0] MIN Duty = 4875%(X100), DQS PI = 0
7326 11:59:24.945175 [0] AVG Duty = 4984%(X100)
7327 11:59:24.945276
7328 11:59:24.945358 ==DQS 1 ==
7329 11:59:24.945438 Final DQS duty delay cell = -4
7330 11:59:24.945518 [-4] MAX Duty = 4969%(X100), DQS PI = 16
7331 11:59:24.945640 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7332 11:59:24.945722 [-4] AVG Duty = 4859%(X100)
7333 11:59:24.945802
7334 11:59:24.945868 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7335 11:59:24.945924
7336 11:59:24.945976 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7337 11:59:24.946027 [DutyScan_Calibration_Flow] ====Done====
7338 11:59:24.946078
7339 11:59:24.946134 [DutyScan_Calibration_Flow] k_type=3
7340 11:59:24.946216
7341 11:59:24.946296 ==DQM 0 ==
7342 11:59:24.946377 Final DQM duty delay cell = 0
7343 11:59:24.946462 [0] MAX Duty = 5218%(X100), DQS PI = 18
7344 11:59:24.946545 [0] MIN Duty = 4969%(X100), DQS PI = 48
7345 11:59:24.946625 [0] AVG Duty = 5093%(X100)
7346 11:59:24.946704
7347 11:59:24.946786 ==DQM 1 ==
7348 11:59:24.946869 Final DQM duty delay cell = 0
7349 11:59:24.946949 [0] MAX Duty = 5093%(X100), DQS PI = 16
7350 11:59:24.947032 [0] MIN Duty = 4907%(X100), DQS PI = 34
7351 11:59:24.947115 [0] AVG Duty = 5000%(X100)
7352 11:59:24.947194
7353 11:59:24.947276 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7354 11:59:24.947358
7355 11:59:24.947438 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7356 11:59:24.947518 [DutyScan_Calibration_Flow] ====Done====
7357 11:59:24.947601
7358 11:59:24.947682 [DutyScan_Calibration_Flow] k_type=2
7359 11:59:24.947761
7360 11:59:24.947842 ==DQ 0 ==
7361 11:59:24.947925 Final DQ duty delay cell = -4
7362 11:59:24.948006 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7363 11:59:24.948089 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7364 11:59:24.948171 [-4] AVG Duty = 4968%(X100)
7365 11:59:24.948251
7366 11:59:24.948333 ==DQ 1 ==
7367 11:59:24.948415 Final DQ duty delay cell = 0
7368 11:59:24.948496 [0] MAX Duty = 5093%(X100), DQS PI = 16
7369 11:59:24.948579 [0] MIN Duty = 4938%(X100), DQS PI = 8
7370 11:59:24.948637 [0] AVG Duty = 5015%(X100)
7371 11:59:24.948688
7372 11:59:24.948739 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7373 11:59:24.948796
7374 11:59:24.948879 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7375 11:59:24.948959 [DutyScan_Calibration_Flow] ====Done====
7376 11:59:24.949041 nWR fixed to 30
7377 11:59:24.949124 [ModeRegInit_LP4] CH0 RK0
7378 11:59:24.949204 [ModeRegInit_LP4] CH0 RK1
7379 11:59:24.949284 [ModeRegInit_LP4] CH1 RK0
7380 11:59:24.949366 [ModeRegInit_LP4] CH1 RK1
7381 11:59:24.949449 match AC timing 5
7382 11:59:24.949529 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 11:59:24.949647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 11:59:24.949703 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 11:59:24.949786 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 11:59:24.949867 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 11:59:24.949949 [MiockJmeterHQA]
7388 11:59:24.950030
7389 11:59:24.950110 [DramcMiockJmeter] u1RxGatingPI = 0
7390 11:59:24.950190 0 : 4252, 4027
7391 11:59:24.950275 4 : 4367, 4140
7392 11:59:24.950359 8 : 4257, 4029
7393 11:59:24.950441 12 : 4254, 4029
7394 11:59:24.950525 16 : 4252, 4027
7395 11:59:24.950610 20 : 4255, 4029
7396 11:59:24.950692 24 : 4254, 4029
7397 11:59:24.950773 28 : 4364, 4137
7398 11:59:24.950859 32 : 4252, 4027
7399 11:59:24.950942 36 : 4363, 4138
7400 11:59:24.951023 40 : 4252, 4027
7401 11:59:24.951109 44 : 4252, 4027
7402 11:59:24.951191 48 : 4252, 4027
7403 11:59:24.951273 52 : 4365, 4140
7404 11:59:24.951357 56 : 4255, 4029
7405 11:59:24.951441 60 : 4363, 4137
7406 11:59:24.951523 64 : 4250, 4027
7407 11:59:24.951606 68 : 4250, 4027
7408 11:59:24.951690 72 : 4250, 4027
7409 11:59:24.951772 76 : 4252, 4030
7410 11:59:24.951853 80 : 4250, 4027
7411 11:59:24.951937 84 : 4360, 4137
7412 11:59:24.952021 88 : 4361, 68
7413 11:59:24.952103 92 : 4250, 0
7414 11:59:24.952187 96 : 4252, 0
7415 11:59:24.952271 100 : 4360, 0
7416 11:59:24.952353 104 : 4250, 0
7417 11:59:24.952434 108 : 4252, 0
7418 11:59:24.952519 112 : 4250, 0
7419 11:59:24.952603 116 : 4250, 0
7420 11:59:24.952684 120 : 4252, 0
7421 11:59:24.952769 124 : 4250, 0
7422 11:59:24.952853 128 : 4360, 0
7423 11:59:24.952935 132 : 4249, 0
7424 11:59:24.953020 136 : 4360, 0
7425 11:59:24.953104 140 : 4250, 0
7426 11:59:24.953186 144 : 4361, 0
7427 11:59:24.953267 148 : 4250, 0
7428 11:59:24.953352 152 : 4250, 0
7429 11:59:24.953437 156 : 4249, 0
7430 11:59:24.953519 160 : 4250, 0
7431 11:59:24.953608 164 : 4250, 0
7432 11:59:24.953666 168 : 4249, 0
7433 11:59:24.953720 172 : 4252, 0
7434 11:59:24.953773 176 : 4250, 0
7435 11:59:24.953826 180 : 4250, 0
7436 11:59:24.953886 184 : 4250, 0
7437 11:59:24.953947 188 : 4250, 0
7438 11:59:24.954034 192 : 4361, 0
7439 11:59:24.954116 196 : 4361, 0
7440 11:59:24.954200 200 : 4250, 0
7441 11:59:24.954283 204 : 4250, 1241
7442 11:59:24.954367 208 : 4250, 3918
7443 11:59:24.954450 212 : 4250, 4027
7444 11:59:24.954531 216 : 4250, 4027
7445 11:59:24.954616 220 : 4361, 4138
7446 11:59:24.954702 224 : 4361, 4138
7447 11:59:24.954784 228 : 4250, 4027
7448 11:59:24.954869 232 : 4361, 4137
7449 11:59:24.954954 236 : 4361, 4137
7450 11:59:24.955036 240 : 4250, 4027
7451 11:59:24.955118 244 : 4250, 4027
7452 11:59:24.955203 248 : 4250, 4027
7453 11:59:24.955287 252 : 4250, 4027
7454 11:59:24.955369 256 : 4250, 4027
7455 11:59:24.955455 260 : 4250, 4027
7456 11:59:24.955539 264 : 4250, 4027
7457 11:59:24.955621 268 : 4249, 4027
7458 11:59:24.955705 272 : 4361, 4137
7459 11:59:24.955790 276 : 4361, 4138
7460 11:59:24.955876 280 : 4247, 4025
7461 11:59:24.955960 284 : 4360, 4138
7462 11:59:24.956045 288 : 4250, 4027
7463 11:59:24.956127 292 : 4252, 4027
7464 11:59:24.956208 296 : 4250, 4027
7465 11:59:24.956293 300 : 4252, 4029
7466 11:59:24.956378 304 : 4250, 4027
7467 11:59:24.956462 308 : 4250, 3933
7468 11:59:24.956543 312 : 4250, 1995
7469 11:59:24.956627
7470 11:59:24.956684 MIOCK jitter meter ch=0
7471 11:59:24.956736
7472 11:59:24.956787 1T = (312-88) = 224 dly cells
7473 11:59:24.956840 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7474 11:59:24.956898 ==
7475 11:59:24.956962 Dram Type= 6, Freq= 0, CH_0, rank 0
7476 11:59:24.957045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7477 11:59:24.957125 ==
7478 11:59:24.957209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7479 11:59:24.957323 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7480 11:59:24.957403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7481 11:59:24.957687 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7482 11:59:24.957779 [CA 0] Center 43 (12~74) winsize 63
7483 11:59:24.957862 [CA 1] Center 43 (12~74) winsize 63
7484 11:59:24.957942 [CA 2] Center 38 (9~68) winsize 60
7485 11:59:24.958026 [CA 3] Center 38 (8~68) winsize 61
7486 11:59:24.958110 [CA 4] Center 37 (7~67) winsize 61
7487 11:59:24.958191 [CA 5] Center 36 (7~65) winsize 59
7488 11:59:24.958275
7489 11:59:24.958356 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7490 11:59:24.958436
7491 11:59:24.958519 [CATrainingPosCal] consider 1 rank data
7492 11:59:24.958602 u2DelayCellTimex100 = 290/100 ps
7493 11:59:24.958683 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7494 11:59:24.958766 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7495 11:59:24.958849 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7496 11:59:24.958930 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7497 11:59:24.959010 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7498 11:59:24.959094 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7499 11:59:24.959175
7500 11:59:24.959255 CA PerBit enable=1, Macro0, CA PI delay=36
7501 11:59:24.959338
7502 11:59:24.959420 [CBTSetCACLKResult] CA Dly = 36
7503 11:59:24.959503 CS Dly: 9 (0~40)
7504 11:59:24.959583 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7505 11:59:24.959668 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7506 11:59:24.959750 ==
7507 11:59:24.959830 Dram Type= 6, Freq= 0, CH_0, rank 1
7508 11:59:24.959916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 11:59:24.959996 ==
7510 11:59:24.960077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 11:59:24.960161 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 11:59:24.960244 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 11:59:24.960327 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 11:59:24.960411 [CA 0] Center 42 (12~73) winsize 62
7515 11:59:24.960494 [CA 1] Center 42 (12~73) winsize 62
7516 11:59:24.960574 [CA 2] Center 38 (8~68) winsize 61
7517 11:59:24.960654 [CA 3] Center 37 (8~67) winsize 60
7518 11:59:24.960718 [CA 4] Center 36 (6~66) winsize 61
7519 11:59:24.960773 [CA 5] Center 35 (5~65) winsize 61
7520 11:59:24.960829
7521 11:59:24.960909 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 11:59:24.960991
7523 11:59:24.961073 [CATrainingPosCal] consider 2 rank data
7524 11:59:24.961153 u2DelayCellTimex100 = 290/100 ps
7525 11:59:24.961233 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7526 11:59:24.961318 CA1 delay=42 (12~73),Diff = 6 PI (20 cell)
7527 11:59:24.961400 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7528 11:59:24.961481 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7529 11:59:24.961564 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 11:59:24.961638 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7531 11:59:24.961690
7532 11:59:24.961741 CA PerBit enable=1, Macro0, CA PI delay=36
7533 11:59:24.961793
7534 11:59:24.961850 [CBTSetCACLKResult] CA Dly = 36
7535 11:59:24.961905 CS Dly: 10 (0~42)
7536 11:59:24.961963 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 11:59:24.962049 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 11:59:24.962203
7539 11:59:24.962286 ----->DramcWriteLeveling(PI) begin...
7540 11:59:24.962373 ==
7541 11:59:24.962459 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 11:59:24.962540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 11:59:24.962631 ==
7544 11:59:24.962720 Write leveling (Byte 0): 36 => 36
7545 11:59:24.962806 Write leveling (Byte 1): 29 => 29
7546 11:59:24.962891 DramcWriteLeveling(PI) end<-----
7547 11:59:24.962970
7548 11:59:24.963053 ==
7549 11:59:24.963134 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 11:59:24.963216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 11:59:24.963302 ==
7552 11:59:24.963387 [Gating] SW mode calibration
7553 11:59:24.963473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7554 11:59:24.963555 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7555 11:59:24.963635 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7556 11:59:24.963720 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 11:59:24.963807 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7558 11:59:24.963888 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7559 11:59:24.963971 1 4 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7560 11:59:24.964055 1 4 20 | B1->B0 | 3333 3838 | 1 0 | (1 1) (1 1)
7561 11:59:24.964153 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7562 11:59:24.964277 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7563 11:59:24.964361 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7564 11:59:24.964441 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7565 11:59:24.964524 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7566 11:59:24.964612 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
7567 11:59:24.964694 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7568 11:59:24.964774 1 5 20 | B1->B0 | 2424 2c2c | 1 1 | (1 0) (0 0)
7569 11:59:24.964901 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7570 11:59:24.965010 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7571 11:59:24.965098 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7572 11:59:24.965215 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7573 11:59:24.965325 1 6 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7574 11:59:24.965425 1 6 12 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
7575 11:59:24.965511 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7576 11:59:24.965614 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7577 11:59:24.965698 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7578 11:59:24.965782 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 11:59:24.965844 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 11:59:24.965896 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 11:59:24.965969 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 11:59:24.966052 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 11:59:24.966132 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7584 11:59:24.966219 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:59:24.966303 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7586 11:59:24.966387 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:59:24.966664 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:59:24.966752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:59:24.966809 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:59:24.966868 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:59:24.966924 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:59:24.966977 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:59:24.967029 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:59:24.967081 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:59:24.967137 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:59:24.967190 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:59:24.967273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 11:59:24.967353 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 11:59:24.967436 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7600 11:59:24.967519 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 11:59:24.967600 Total UI for P1: 0, mck2ui 16
7602 11:59:24.967680 best dqsien dly found for B0: ( 1, 9, 12)
7603 11:59:24.967766 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 11:59:24.967847 Total UI for P1: 0, mck2ui 16
7605 11:59:24.967928 best dqsien dly found for B1: ( 1, 9, 20)
7606 11:59:24.968012 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7607 11:59:24.968095 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7608 11:59:24.968174
7609 11:59:24.968255 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7610 11:59:24.968339 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7611 11:59:24.968421 [Gating] SW calibration Done
7612 11:59:24.968500 ==
7613 11:59:24.968583 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 11:59:24.968667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 11:59:24.968748 ==
7616 11:59:24.968827 RX Vref Scan: 0
7617 11:59:24.968910
7618 11:59:24.968992 RX Vref 0 -> 0, step: 1
7619 11:59:24.969071
7620 11:59:24.969153 RX Delay 0 -> 252, step: 8
7621 11:59:24.969239 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7622 11:59:24.969320 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7623 11:59:24.969404 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7624 11:59:24.969487 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7625 11:59:24.969568 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7626 11:59:24.969701 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7627 11:59:24.969784 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7628 11:59:24.969864 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7629 11:59:24.969947 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7630 11:59:24.970029 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7631 11:59:24.970110 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7632 11:59:24.970190 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7633 11:59:24.970274 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7634 11:59:24.970357 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7635 11:59:24.970439 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7636 11:59:24.970522 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7637 11:59:24.970604 ==
7638 11:59:24.970687 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 11:59:24.970767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 11:59:24.970850 ==
7641 11:59:24.970933 DQS Delay:
7642 11:59:24.971013 DQS0 = 0, DQS1 = 0
7643 11:59:24.971092 DQM Delay:
7644 11:59:24.971174 DQM0 = 137, DQM1 = 129
7645 11:59:24.971260 DQ Delay:
7646 11:59:24.971341 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7647 11:59:24.971423 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7648 11:59:24.971506 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7649 11:59:24.971588 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7650 11:59:24.971670
7651 11:59:24.971753
7652 11:59:24.971832 ==
7653 11:59:24.971911 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 11:59:24.972001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 11:59:24.972087 ==
7656 11:59:24.972167
7657 11:59:24.972249
7658 11:59:24.972329 TX Vref Scan disable
7659 11:59:24.972411 == TX Byte 0 ==
7660 11:59:24.972491 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7661 11:59:24.972575 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7662 11:59:24.972656 == TX Byte 1 ==
7663 11:59:24.972737 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7664 11:59:24.972820 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7665 11:59:24.972898 ==
7666 11:59:24.972958 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 11:59:24.973013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 11:59:24.973067 ==
7669 11:59:24.973122
7670 11:59:24.973173 TX Vref early break, caculate TX vref
7671 11:59:24.973230 TX Vref=16, minBit 0, minWin=22, winSum=375
7672 11:59:24.973287 TX Vref=18, minBit 4, minWin=23, winSum=387
7673 11:59:24.973341 TX Vref=20, minBit 0, minWin=24, winSum=401
7674 11:59:24.973392 TX Vref=22, minBit 7, minWin=24, winSum=408
7675 11:59:24.973444 TX Vref=24, minBit 0, minWin=25, winSum=415
7676 11:59:24.973505 TX Vref=26, minBit 1, minWin=25, winSum=422
7677 11:59:24.973609 TX Vref=28, minBit 6, minWin=25, winSum=425
7678 11:59:24.973706 TX Vref=30, minBit 4, minWin=24, winSum=413
7679 11:59:24.973787 TX Vref=32, minBit 1, minWin=24, winSum=406
7680 11:59:24.973842 TX Vref=34, minBit 1, minWin=23, winSum=392
7681 11:59:24.973898 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 28
7682 11:59:24.973951
7683 11:59:24.974009 Final TX Range 0 Vref 28
7684 11:59:24.974077
7685 11:59:24.974159 ==
7686 11:59:24.974242 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 11:59:24.974324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 11:59:24.974407 ==
7689 11:59:24.974487
7690 11:59:24.974565
7691 11:59:24.974648 TX Vref Scan disable
7692 11:59:24.974706 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7693 11:59:24.974785 == TX Byte 0 ==
7694 11:59:24.974865 u2DelayCellOfst[0]=10 cells (3 PI)
7695 11:59:24.974924 u2DelayCellOfst[1]=16 cells (5 PI)
7696 11:59:24.974980 u2DelayCellOfst[2]=13 cells (4 PI)
7697 11:59:24.975032 u2DelayCellOfst[3]=10 cells (3 PI)
7698 11:59:24.975083 u2DelayCellOfst[4]=6 cells (2 PI)
7699 11:59:24.975134 u2DelayCellOfst[5]=0 cells (0 PI)
7700 11:59:24.975190 u2DelayCellOfst[6]=16 cells (5 PI)
7701 11:59:24.975242 u2DelayCellOfst[7]=13 cells (4 PI)
7702 11:59:24.975298 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7703 11:59:24.975355 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7704 11:59:24.975408 == TX Byte 1 ==
7705 11:59:24.975462 u2DelayCellOfst[8]=0 cells (0 PI)
7706 11:59:24.975547 u2DelayCellOfst[9]=0 cells (0 PI)
7707 11:59:24.975627 u2DelayCellOfst[10]=6 cells (2 PI)
7708 11:59:24.975908 u2DelayCellOfst[11]=3 cells (1 PI)
7709 11:59:24.975993 u2DelayCellOfst[12]=10 cells (3 PI)
7710 11:59:24.976078 u2DelayCellOfst[13]=10 cells (3 PI)
7711 11:59:24.976146 u2DelayCellOfst[14]=13 cells (4 PI)
7712 11:59:24.976199 u2DelayCellOfst[15]=10 cells (3 PI)
7713 11:59:24.976251 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7714 11:59:24.976302 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7715 11:59:24.976377 DramC Write-DBI on
7716 11:59:24.976459 ==
7717 11:59:24.976542 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 11:59:24.976624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 11:59:24.976707 ==
7720 11:59:24.976787
7721 11:59:24.976866
7722 11:59:24.976952 TX Vref Scan disable
7723 11:59:24.977037 == TX Byte 0 ==
7724 11:59:24.977119 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7725 11:59:24.977199 == TX Byte 1 ==
7726 11:59:24.977283 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7727 11:59:24.977365 DramC Write-DBI off
7728 11:59:24.977444
7729 11:59:24.977525 [DATLAT]
7730 11:59:24.977646 Freq=1600, CH0 RK0
7731 11:59:24.977700
7732 11:59:24.977752 DATLAT Default: 0xf
7733 11:59:24.977810 0, 0xFFFF, sum = 0
7734 11:59:24.977866 1, 0xFFFF, sum = 0
7735 11:59:24.977919 2, 0xFFFF, sum = 0
7736 11:59:24.977972 3, 0xFFFF, sum = 0
7737 11:59:24.978061 4, 0xFFFF, sum = 0
7738 11:59:24.978147 5, 0xFFFF, sum = 0
7739 11:59:24.978230 6, 0xFFFF, sum = 0
7740 11:59:24.978314 7, 0xFFFF, sum = 0
7741 11:59:24.978398 8, 0xFFFF, sum = 0
7742 11:59:24.978480 9, 0xFFFF, sum = 0
7743 11:59:24.978564 10, 0xFFFF, sum = 0
7744 11:59:24.978646 11, 0xFFFF, sum = 0
7745 11:59:24.978706 12, 0xFFFF, sum = 0
7746 11:59:24.978789 13, 0xFFFF, sum = 0
7747 11:59:24.978867 14, 0x0, sum = 1
7748 11:59:24.978925 15, 0x0, sum = 2
7749 11:59:24.978985 16, 0x0, sum = 3
7750 11:59:24.979067 17, 0x0, sum = 4
7751 11:59:24.979136 best_step = 15
7752 11:59:24.979189
7753 11:59:24.979270 ==
7754 11:59:24.979337 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 11:59:24.979394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 11:59:24.979449 ==
7757 11:59:24.979530 RX Vref Scan: 1
7758 11:59:24.979609
7759 11:59:24.979687 Set Vref Range= 24 -> 127
7760 11:59:24.979745
7761 11:59:24.979800 RX Vref 24 -> 127, step: 1
7762 11:59:24.979852
7763 11:59:24.979903 RX Delay 19 -> 252, step: 4
7764 11:59:24.979986
7765 11:59:24.980067 Set Vref, RX VrefLevel [Byte0]: 24
7766 11:59:24.980149 [Byte1]: 24
7767 11:59:24.980230
7768 11:59:24.980313 Set Vref, RX VrefLevel [Byte0]: 25
7769 11:59:24.980392 [Byte1]: 25
7770 11:59:24.980475
7771 11:59:24.980557 Set Vref, RX VrefLevel [Byte0]: 26
7772 11:59:24.980637 [Byte1]: 26
7773 11:59:24.980716
7774 11:59:24.980802 Set Vref, RX VrefLevel [Byte0]: 27
7775 11:59:24.980886 [Byte1]: 27
7776 11:59:24.980969
7777 11:59:24.981053 Set Vref, RX VrefLevel [Byte0]: 28
7778 11:59:24.981136 [Byte1]: 28
7779 11:59:24.981217
7780 11:59:24.981296 Set Vref, RX VrefLevel [Byte0]: 29
7781 11:59:24.981386 [Byte1]: 29
7782 11:59:24.981469
7783 11:59:24.981549 Set Vref, RX VrefLevel [Byte0]: 30
7784 11:59:24.981668 [Byte1]: 30
7785 11:59:24.981749
7786 11:59:24.981824 Set Vref, RX VrefLevel [Byte0]: 31
7787 11:59:24.981878 [Byte1]: 31
7788 11:59:24.981929
7789 11:59:24.981981 Set Vref, RX VrefLevel [Byte0]: 32
7790 11:59:24.982038 [Byte1]: 32
7791 11:59:24.982089
7792 11:59:24.982140 Set Vref, RX VrefLevel [Byte0]: 33
7793 11:59:24.982197 [Byte1]: 33
7794 11:59:24.982253
7795 11:59:24.982304 Set Vref, RX VrefLevel [Byte0]: 34
7796 11:59:24.982355 [Byte1]: 34
7797 11:59:24.982405
7798 11:59:24.982463 Set Vref, RX VrefLevel [Byte0]: 35
7799 11:59:24.982519 [Byte1]: 35
7800 11:59:24.982571
7801 11:59:24.982622 Set Vref, RX VrefLevel [Byte0]: 36
7802 11:59:24.982673 [Byte1]: 36
7803 11:59:24.982730
7804 11:59:24.982785 Set Vref, RX VrefLevel [Byte0]: 37
7805 11:59:24.982838 [Byte1]: 37
7806 11:59:24.982889
7807 11:59:24.982939 Set Vref, RX VrefLevel [Byte0]: 38
7808 11:59:24.982993 [Byte1]: 38
7809 11:59:24.983053
7810 11:59:24.983111 Set Vref, RX VrefLevel [Byte0]: 39
7811 11:59:24.983163 [Byte1]: 39
7812 11:59:24.983214
7813 11:59:24.983270 Set Vref, RX VrefLevel [Byte0]: 40
7814 11:59:24.983326 [Byte1]: 40
7815 11:59:24.983378
7816 11:59:24.983428 Set Vref, RX VrefLevel [Byte0]: 41
7817 11:59:24.983479 [Byte1]: 41
7818 11:59:24.983538
7819 11:59:24.983592 Set Vref, RX VrefLevel [Byte0]: 42
7820 11:59:24.983644 [Byte1]: 42
7821 11:59:24.983695
7822 11:59:24.983746 Set Vref, RX VrefLevel [Byte0]: 43
7823 11:59:24.983808 [Byte1]: 43
7824 11:59:24.983866
7825 11:59:24.983918 Set Vref, RX VrefLevel [Byte0]: 44
7826 11:59:24.983970 [Byte1]: 44
7827 11:59:24.984021
7828 11:59:24.984076 Set Vref, RX VrefLevel [Byte0]: 45
7829 11:59:24.984128 [Byte1]: 45
7830 11:59:24.984183
7831 11:59:24.984235 Set Vref, RX VrefLevel [Byte0]: 46
7832 11:59:24.984287 [Byte1]: 46
7833 11:59:24.984338
7834 11:59:24.984395 Set Vref, RX VrefLevel [Byte0]: 47
7835 11:59:24.984453 [Byte1]: 47
7836 11:59:24.984505
7837 11:59:24.984555 Set Vref, RX VrefLevel [Byte0]: 48
7838 11:59:24.984606 [Byte1]: 48
7839 11:59:24.984664
7840 11:59:24.984720 Set Vref, RX VrefLevel [Byte0]: 49
7841 11:59:24.984801 [Byte1]: 49
7842 11:59:24.984880
7843 11:59:24.984963 Set Vref, RX VrefLevel [Byte0]: 50
7844 11:59:24.985048 [Byte1]: 50
7845 11:59:24.985128
7846 11:59:24.985212 Set Vref, RX VrefLevel [Byte0]: 51
7847 11:59:24.985294 [Byte1]: 51
7848 11:59:24.985374
7849 11:59:24.985453 Set Vref, RX VrefLevel [Byte0]: 52
7850 11:59:24.985540 [Byte1]: 52
7851 11:59:24.985658
7852 11:59:24.985711 Set Vref, RX VrefLevel [Byte0]: 53
7853 11:59:24.985763 [Byte1]: 53
7854 11:59:24.985821
7855 11:59:24.985876 Set Vref, RX VrefLevel [Byte0]: 54
7856 11:59:24.985929 [Byte1]: 54
7857 11:59:24.985980
7858 11:59:24.986031 Set Vref, RX VrefLevel [Byte0]: 55
7859 11:59:24.986086 [Byte1]: 55
7860 11:59:24.986138
7861 11:59:24.986194 Set Vref, RX VrefLevel [Byte0]: 56
7862 11:59:24.986245 [Byte1]: 56
7863 11:59:24.986297
7864 11:59:24.986347 Set Vref, RX VrefLevel [Byte0]: 57
7865 11:59:24.986407 [Byte1]: 57
7866 11:59:24.986463
7867 11:59:24.986514 Set Vref, RX VrefLevel [Byte0]: 58
7868 11:59:24.986565 [Byte1]: 58
7869 11:59:24.986616
7870 11:59:24.986673 Set Vref, RX VrefLevel [Byte0]: 59
7871 11:59:24.986727 [Byte1]: 59
7872 11:59:24.986779
7873 11:59:24.986829 Set Vref, RX VrefLevel [Byte0]: 60
7874 11:59:24.986881 [Byte1]: 60
7875 11:59:24.986936
7876 11:59:24.986992 Set Vref, RX VrefLevel [Byte0]: 61
7877 11:59:24.987044 [Byte1]: 61
7878 11:59:24.987095
7879 11:59:24.987341 Set Vref, RX VrefLevel [Byte0]: 62
7880 11:59:24.987408 [Byte1]: 62
7881 11:59:24.987474
7882 11:59:24.987586 Set Vref, RX VrefLevel [Byte0]: 63
7883 11:59:24.987667 [Byte1]: 63
7884 11:59:24.987728
7885 11:59:24.987790 Set Vref, RX VrefLevel [Byte0]: 64
7886 11:59:24.987871 [Byte1]: 64
7887 11:59:24.987950
7888 11:59:24.988017 Set Vref, RX VrefLevel [Byte0]: 65
7889 11:59:24.988073 [Byte1]: 65
7890 11:59:24.988125
7891 11:59:24.988176 Set Vref, RX VrefLevel [Byte0]: 66
7892 11:59:24.988227 [Byte1]: 66
7893 11:59:24.988285
7894 11:59:24.988340 Set Vref, RX VrefLevel [Byte0]: 67
7895 11:59:24.988393 [Byte1]: 67
7896 11:59:24.988444
7897 11:59:24.988495 Set Vref, RX VrefLevel [Byte0]: 68
7898 11:59:24.988553 [Byte1]: 68
7899 11:59:24.988625
7900 11:59:24.988705 Set Vref, RX VrefLevel [Byte0]: 69
7901 11:59:24.988787 [Byte1]: 69
7902 11:59:24.988871
7903 11:59:24.988951 Set Vref, RX VrefLevel [Byte0]: 70
7904 11:59:24.989030 [Byte1]: 70
7905 11:59:24.989114
7906 11:59:24.989196 Set Vref, RX VrefLevel [Byte0]: 71
7907 11:59:24.989276 [Byte1]: 71
7908 11:59:24.989358
7909 11:59:24.989440 Set Vref, RX VrefLevel [Byte0]: 72
7910 11:59:24.989521 [Byte1]: 72
7911 11:59:24.989638
7912 11:59:24.989696 Set Vref, RX VrefLevel [Byte0]: 73
7913 11:59:24.989749 [Byte1]: 73
7914 11:59:24.989800
7915 11:59:24.989852 Set Vref, RX VrefLevel [Byte0]: 74
7916 11:59:24.989911 [Byte1]: 74
7917 11:59:24.989969
7918 11:59:24.990021 Final RX Vref Byte 0 = 56 to rank0
7919 11:59:24.990073 Final RX Vref Byte 1 = 60 to rank0
7920 11:59:24.990124 Final RX Vref Byte 0 = 56 to rank1
7921 11:59:24.990184 Final RX Vref Byte 1 = 60 to rank1==
7922 11:59:24.990237 Dram Type= 6, Freq= 0, CH_0, rank 0
7923 11:59:24.990289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7924 11:59:24.990341 ==
7925 11:59:24.990403 DQS Delay:
7926 11:59:24.990462 DQS0 = 0, DQS1 = 0
7927 11:59:24.990516 DQM Delay:
7928 11:59:24.990567 DQM0 = 133, DQM1 = 127
7929 11:59:24.990619 DQ Delay:
7930 11:59:24.990676 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7931 11:59:24.990733 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7932 11:59:24.990784 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7933 11:59:24.990836 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7934 11:59:24.990886
7935 11:59:24.990944
7936 11:59:24.990998
7937 11:59:24.991050 [DramC_TX_OE_Calibration] TA2
7938 11:59:24.991101 Original DQ_B0 (3 6) =30, OEN = 27
7939 11:59:24.991153 Original DQ_B1 (3 6) =30, OEN = 27
7940 11:59:24.991208 24, 0x0, End_B0=24 End_B1=24
7941 11:59:24.991262 25, 0x0, End_B0=25 End_B1=25
7942 11:59:24.991319 26, 0x0, End_B0=26 End_B1=26
7943 11:59:24.991372 27, 0x0, End_B0=27 End_B1=27
7944 11:59:24.991424 28, 0x0, End_B0=28 End_B1=28
7945 11:59:24.991475 29, 0x0, End_B0=29 End_B1=29
7946 11:59:24.991532 30, 0x0, End_B0=30 End_B1=30
7947 11:59:24.991589 31, 0x4141, End_B0=30 End_B1=30
7948 11:59:24.991642 Byte0 end_step=30 best_step=27
7949 11:59:24.991694 Byte1 end_step=30 best_step=27
7950 11:59:24.991745 Byte0 TX OE(2T, 0.5T) = (3, 3)
7951 11:59:24.991802 Byte1 TX OE(2T, 0.5T) = (3, 3)
7952 11:59:24.991858
7953 11:59:24.991909
7954 11:59:24.991959 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7955 11:59:24.992012 CH0 RK0: MR19=303, MR18=241F
7956 11:59:24.992072 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7957 11:59:25.095854
7958 11:59:25.095988 ----->DramcWriteLeveling(PI) begin...
7959 11:59:25.096085 ==
7960 11:59:25.096174 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 11:59:25.096273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 11:59:25.096360 ==
7963 11:59:25.096446 Write leveling (Byte 0): 36 => 36
7964 11:59:25.096541 Write leveling (Byte 1): 29 => 29
7965 11:59:25.096626 DramcWriteLeveling(PI) end<-----
7966 11:59:25.096715
7967 11:59:25.096802 ==
7968 11:59:25.096885 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 11:59:25.096976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 11:59:25.097062 ==
7971 11:59:25.097144 [Gating] SW mode calibration
7972 11:59:25.097235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7973 11:59:25.097322 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7974 11:59:25.097403 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 11:59:25.097497 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7976 11:59:25.097587 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7977 11:59:25.097676 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7978 11:59:25.097752 1 4 16 | B1->B0 | 3030 3636 | 0 1 | (0 0) (1 1)
7979 11:59:25.097806 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7980 11:59:25.097859 1 4 24 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7981 11:59:25.097911 1 4 28 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7982 11:59:25.097984 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7983 11:59:25.098041 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7984 11:59:25.098093 1 5 8 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7985 11:59:25.098146 1 5 12 | B1->B0 | 3434 3535 | 1 1 | (1 0) (1 0)
7986 11:59:25.098206 1 5 16 | B1->B0 | 2e2e 2928 | 1 1 | (1 0) (0 0)
7987 11:59:25.098287 1 5 20 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7988 11:59:25.098368 1 5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7989 11:59:25.098451 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7990 11:59:25.098533 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7991 11:59:25.098615 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7992 11:59:25.098696 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7993 11:59:25.098771 1 6 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7994 11:59:25.098824 1 6 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7995 11:59:25.098877 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 11:59:25.098929 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 11:59:25.099004 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7998 11:59:25.099059 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 11:59:25.099111 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 11:59:25.099163 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 11:59:25.099226 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8002 11:59:25.099501 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8003 11:59:25.099563 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:59:25.099616 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:59:25.099669 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:59:25.099732 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:59:25.099796 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:59:25.099848 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:59:25.099900 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:59:25.099953 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:59:25.100033 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:59:25.100115 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:59:25.100196 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:59:25.100290 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:59:25.100371 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 11:59:25.100452 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 11:59:25.100545 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8018 11:59:25.100627 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8019 11:59:25.100707 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 11:59:25.100800 Total UI for P1: 0, mck2ui 16
8021 11:59:25.100882 best dqsien dly found for B0: ( 1, 9, 14)
8022 11:59:25.100963 Total UI for P1: 0, mck2ui 16
8023 11:59:25.101072 best dqsien dly found for B1: ( 1, 9, 14)
8024 11:59:25.101160 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8025 11:59:25.101255 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8026 11:59:25.101345
8027 11:59:25.101431 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8028 11:59:25.101529 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8029 11:59:25.101617 [Gating] SW calibration Done
8030 11:59:25.101675 ==
8031 11:59:25.101730 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 11:59:25.101813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 11:59:25.101871 ==
8034 11:59:25.101928 RX Vref Scan: 0
8035 11:59:25.101984
8036 11:59:25.102065 RX Vref 0 -> 0, step: 1
8037 11:59:25.102123
8038 11:59:25.102178 RX Delay 0 -> 252, step: 8
8039 11:59:25.102234 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8040 11:59:25.102317 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8041 11:59:25.102375 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8042 11:59:25.102431 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8043 11:59:25.102487 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8044 11:59:25.102569 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8045 11:59:25.102627 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8046 11:59:25.102683 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8047 11:59:25.102738 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8048 11:59:25.102837 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8049 11:59:25.102925 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8050 11:59:25.103016 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8051 11:59:25.103087 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8052 11:59:25.103145 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8053 11:59:25.103201 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8054 11:59:25.103257 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8055 11:59:25.103312 ==
8056 11:59:25.103368 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 11:59:25.103424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 11:59:25.103480 ==
8059 11:59:25.103535 DQS Delay:
8060 11:59:25.103590 DQS0 = 0, DQS1 = 0
8061 11:59:25.103645 DQM Delay:
8062 11:59:25.103700 DQM0 = 137, DQM1 = 128
8063 11:59:25.103759 DQ Delay:
8064 11:59:25.103820 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8065 11:59:25.103883 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8066 11:59:25.103940 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8067 11:59:25.104019 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8068 11:59:25.104085
8069 11:59:25.104154
8070 11:59:25.104244 ==
8071 11:59:25.104337 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 11:59:25.104432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 11:59:25.104522 ==
8074 11:59:25.104608
8075 11:59:25.104707
8076 11:59:25.104795 TX Vref Scan disable
8077 11:59:25.104888 == TX Byte 0 ==
8078 11:59:25.104982 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8079 11:59:25.105069 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8080 11:59:25.105168 == TX Byte 1 ==
8081 11:59:25.105257 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8082 11:59:25.105343 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8083 11:59:25.105443 ==
8084 11:59:25.105530 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 11:59:25.105630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 11:59:25.105695 ==
8087 11:59:25.105751
8088 11:59:25.105807 TX Vref early break, caculate TX vref
8089 11:59:25.105876 TX Vref=16, minBit 1, minWin=23, winSum=381
8090 11:59:25.105944 TX Vref=18, minBit 1, minWin=23, winSum=393
8091 11:59:25.106001 TX Vref=20, minBit 0, minWin=24, winSum=406
8092 11:59:25.106057 TX Vref=22, minBit 3, minWin=24, winSum=410
8093 11:59:25.106119 TX Vref=24, minBit 1, minWin=24, winSum=417
8094 11:59:25.106191 TX Vref=26, minBit 1, minWin=25, winSum=425
8095 11:59:25.106248 TX Vref=28, minBit 3, minWin=24, winSum=421
8096 11:59:25.106305 TX Vref=30, minBit 4, minWin=24, winSum=416
8097 11:59:25.106360 TX Vref=32, minBit 7, minWin=24, winSum=410
8098 11:59:25.106440 TX Vref=34, minBit 2, minWin=24, winSum=399
8099 11:59:25.106498 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8100 11:59:25.106554
8101 11:59:25.106614 Final TX Range 0 Vref 26
8102 11:59:25.106702
8103 11:59:25.106788 ==
8104 11:59:25.106879 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 11:59:25.106975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 11:59:25.107062 ==
8107 11:59:25.107160
8108 11:59:25.107249
8109 11:59:25.107334 TX Vref Scan disable
8110 11:59:25.107434 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8111 11:59:25.107522 == TX Byte 0 ==
8112 11:59:25.107608 u2DelayCellOfst[0]=10 cells (3 PI)
8113 11:59:25.107708 u2DelayCellOfst[1]=13 cells (4 PI)
8114 11:59:25.107795 u2DelayCellOfst[2]=10 cells (3 PI)
8115 11:59:25.107889 u2DelayCellOfst[3]=10 cells (3 PI)
8116 11:59:25.107983 u2DelayCellOfst[4]=6 cells (2 PI)
8117 11:59:25.108069 u2DelayCellOfst[5]=0 cells (0 PI)
8118 11:59:25.108184 u2DelayCellOfst[6]=13 cells (4 PI)
8119 11:59:25.108274 u2DelayCellOfst[7]=13 cells (4 PI)
8120 11:59:25.108361 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8121 11:59:25.111028 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8122 11:59:25.113985 == TX Byte 1 ==
8123 11:59:25.114096 u2DelayCellOfst[8]=0 cells (0 PI)
8124 11:59:25.117113 u2DelayCellOfst[9]=0 cells (0 PI)
8125 11:59:25.120831 u2DelayCellOfst[10]=3 cells (1 PI)
8126 11:59:25.123928 u2DelayCellOfst[11]=0 cells (0 PI)
8127 11:59:25.127159 u2DelayCellOfst[12]=6 cells (2 PI)
8128 11:59:25.130717 u2DelayCellOfst[13]=6 cells (2 PI)
8129 11:59:25.133674 u2DelayCellOfst[14]=10 cells (3 PI)
8130 11:59:25.137437 u2DelayCellOfst[15]=6 cells (2 PI)
8131 11:59:25.140603 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8132 11:59:25.147022 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8133 11:59:25.147125 DramC Write-DBI on
8134 11:59:25.147214 ==
8135 11:59:25.150438 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 11:59:25.153827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 11:59:25.153903 ==
8138 11:59:25.157017
8139 11:59:25.157110
8140 11:59:25.157206 TX Vref Scan disable
8141 11:59:25.160154 == TX Byte 0 ==
8142 11:59:25.163662 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8143 11:59:25.167275 == TX Byte 1 ==
8144 11:59:25.170689 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8145 11:59:25.173747 DramC Write-DBI off
8146 11:59:25.173820
8147 11:59:25.173882 [DATLAT]
8148 11:59:25.173939 Freq=1600, CH0 RK1
8149 11:59:25.173995
8150 11:59:25.176802 DATLAT Default: 0xf
8151 11:59:25.176866 0, 0xFFFF, sum = 0
8152 11:59:25.180386 1, 0xFFFF, sum = 0
8153 11:59:25.183611 2, 0xFFFF, sum = 0
8154 11:59:25.183712 3, 0xFFFF, sum = 0
8155 11:59:25.187087 4, 0xFFFF, sum = 0
8156 11:59:25.187170 5, 0xFFFF, sum = 0
8157 11:59:25.190644 6, 0xFFFF, sum = 0
8158 11:59:25.190741 7, 0xFFFF, sum = 0
8159 11:59:25.193953 8, 0xFFFF, sum = 0
8160 11:59:25.194054 9, 0xFFFF, sum = 0
8161 11:59:25.196600 10, 0xFFFF, sum = 0
8162 11:59:25.196708 11, 0xFFFF, sum = 0
8163 11:59:25.200350 12, 0xFFFF, sum = 0
8164 11:59:25.200453 13, 0xFFFF, sum = 0
8165 11:59:25.203415 14, 0x0, sum = 1
8166 11:59:25.203510 15, 0x0, sum = 2
8167 11:59:25.206718 16, 0x0, sum = 3
8168 11:59:25.206823 17, 0x0, sum = 4
8169 11:59:25.210470 best_step = 15
8170 11:59:25.210563
8171 11:59:25.210658 ==
8172 11:59:25.213371 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 11:59:25.216487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 11:59:25.216561 ==
8175 11:59:25.219892 RX Vref Scan: 0
8176 11:59:25.219997
8177 11:59:25.220095 RX Vref 0 -> 0, step: 1
8178 11:59:25.220183
8179 11:59:25.223646 RX Delay 19 -> 252, step: 4
8180 11:59:25.226817 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8181 11:59:25.233134 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8182 11:59:25.236726 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8183 11:59:25.240012 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8184 11:59:25.242931 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8185 11:59:25.246333 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8186 11:59:25.252883 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8187 11:59:25.256567 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8188 11:59:25.259751 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8189 11:59:25.262848 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8190 11:59:25.266228 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8191 11:59:25.273071 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8192 11:59:25.276178 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8193 11:59:25.279949 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8194 11:59:25.282723 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8195 11:59:25.289821 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8196 11:59:25.289926 ==
8197 11:59:25.292619 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 11:59:25.296257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 11:59:25.296358 ==
8200 11:59:25.296422 DQS Delay:
8201 11:59:25.299146 DQS0 = 0, DQS1 = 0
8202 11:59:25.299222 DQM Delay:
8203 11:59:25.302693 DQM0 = 134, DQM1 = 127
8204 11:59:25.302762 DQ Delay:
8205 11:59:25.306218 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =132
8206 11:59:25.309192 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8207 11:59:25.313062 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8208 11:59:25.316248 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8209 11:59:25.316344
8210 11:59:25.316474
8211 11:59:25.319210
8212 11:59:25.319306 [DramC_TX_OE_Calibration] TA2
8213 11:59:25.322844 Original DQ_B0 (3 6) =30, OEN = 27
8214 11:59:25.325841 Original DQ_B1 (3 6) =30, OEN = 27
8215 11:59:25.329069 24, 0x0, End_B0=24 End_B1=24
8216 11:59:25.332925 25, 0x0, End_B0=25 End_B1=25
8217 11:59:25.335995 26, 0x0, End_B0=26 End_B1=26
8218 11:59:25.336098 27, 0x0, End_B0=27 End_B1=27
8219 11:59:25.338981 28, 0x0, End_B0=28 End_B1=28
8220 11:59:25.342822 29, 0x0, End_B0=29 End_B1=29
8221 11:59:25.345897 30, 0x0, End_B0=30 End_B1=30
8222 11:59:25.349444 31, 0x4141, End_B0=30 End_B1=30
8223 11:59:25.349554 Byte0 end_step=30 best_step=27
8224 11:59:25.352561 Byte1 end_step=30 best_step=27
8225 11:59:25.355985 Byte0 TX OE(2T, 0.5T) = (3, 3)
8226 11:59:25.359490 Byte1 TX OE(2T, 0.5T) = (3, 3)
8227 11:59:25.359595
8228 11:59:25.359689
8229 11:59:25.366105 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8230 11:59:25.369045 CH0 RK1: MR19=303, MR18=1F08
8231 11:59:25.376107 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8232 11:59:25.379233 [RxdqsGatingPostProcess] freq 1600
8233 11:59:25.386070 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8234 11:59:25.389025 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 11:59:25.389143 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 11:59:25.392078 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 11:59:25.395952 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 11:59:25.399043 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 11:59:25.402184 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 11:59:25.406072 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 11:59:25.409174 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 11:59:25.412578 Pre-setting of DQS Precalculation
8243 11:59:25.415647 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8244 11:59:25.415747 ==
8245 11:59:25.419545 Dram Type= 6, Freq= 0, CH_1, rank 0
8246 11:59:25.425794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 11:59:25.425894 ==
8248 11:59:25.428982 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8249 11:59:25.435428 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8250 11:59:25.438998 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8251 11:59:25.445550 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8252 11:59:25.453547 [CA 0] Center 42 (12~72) winsize 61
8253 11:59:25.457167 [CA 1] Center 42 (13~72) winsize 60
8254 11:59:25.460145 [CA 2] Center 39 (10~68) winsize 59
8255 11:59:25.463682 [CA 3] Center 38 (10~67) winsize 58
8256 11:59:25.467043 [CA 4] Center 38 (9~68) winsize 60
8257 11:59:25.470025 [CA 5] Center 37 (8~67) winsize 60
8258 11:59:25.470105
8259 11:59:25.473555 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8260 11:59:25.473685
8261 11:59:25.477361 [CATrainingPosCal] consider 1 rank data
8262 11:59:25.480321 u2DelayCellTimex100 = 290/100 ps
8263 11:59:25.483375 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8264 11:59:25.490166 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8265 11:59:25.493367 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8266 11:59:25.497069 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8267 11:59:25.500141 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8268 11:59:25.503357 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8269 11:59:25.503438
8270 11:59:25.507152 CA PerBit enable=1, Macro0, CA PI delay=37
8271 11:59:25.507233
8272 11:59:25.510543 [CBTSetCACLKResult] CA Dly = 37
8273 11:59:25.513323 CS Dly: 10 (0~41)
8274 11:59:25.516832 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8275 11:59:25.520306 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8276 11:59:25.520387 ==
8277 11:59:25.523511 Dram Type= 6, Freq= 0, CH_1, rank 1
8278 11:59:25.527051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 11:59:25.529866 ==
8280 11:59:25.533755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 11:59:25.536968 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 11:59:25.543796 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 11:59:25.546513 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 11:59:25.557108 [CA 0] Center 42 (12~72) winsize 61
8285 11:59:25.560768 [CA 1] Center 42 (12~72) winsize 61
8286 11:59:25.563710 [CA 2] Center 38 (9~68) winsize 60
8287 11:59:25.566964 [CA 3] Center 38 (8~68) winsize 61
8288 11:59:25.570382 [CA 4] Center 38 (8~68) winsize 61
8289 11:59:25.573734 [CA 5] Center 37 (8~67) winsize 60
8290 11:59:25.573815
8291 11:59:25.577404 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 11:59:25.577486
8293 11:59:25.580336 [CATrainingPosCal] consider 2 rank data
8294 11:59:25.583817 u2DelayCellTimex100 = 290/100 ps
8295 11:59:25.586945 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8296 11:59:25.593864 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8297 11:59:25.596786 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8298 11:59:25.600540 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8299 11:59:25.603942 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8300 11:59:25.607025 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8301 11:59:25.607107
8302 11:59:25.610165 CA PerBit enable=1, Macro0, CA PI delay=37
8303 11:59:25.610246
8304 11:59:25.613761 [CBTSetCACLKResult] CA Dly = 37
8305 11:59:25.616968 CS Dly: 11 (0~44)
8306 11:59:25.620128 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 11:59:25.623245 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 11:59:25.623325
8309 11:59:25.626968 ----->DramcWriteLeveling(PI) begin...
8310 11:59:25.627050 ==
8311 11:59:25.629939 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 11:59:25.636661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 11:59:25.636742 ==
8314 11:59:25.639764 Write leveling (Byte 0): 26 => 26
8315 11:59:25.642837 Write leveling (Byte 1): 28 => 28
8316 11:59:25.642917 DramcWriteLeveling(PI) end<-----
8317 11:59:25.642980
8318 11:59:25.646576 ==
8319 11:59:25.649400 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 11:59:25.653619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 11:59:25.653713 ==
8322 11:59:25.656256 [Gating] SW mode calibration
8323 11:59:25.663065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8324 11:59:25.666400 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8325 11:59:25.672888 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 11:59:25.676046 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 11:59:25.679341 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8328 11:59:25.686361 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8329 11:59:25.689453 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 11:59:25.692882 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 11:59:25.699827 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 11:59:25.702784 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 11:59:25.705987 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 11:59:25.713224 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 11:59:25.716486 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (0 0) (0 0)
8336 11:59:25.719468 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8337 11:59:25.726126 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 11:59:25.729473 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 11:59:25.732607 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 11:59:25.738734 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 11:59:25.742390 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 11:59:25.745537 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 11:59:25.751909 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
8344 11:59:25.755651 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8345 11:59:25.758801 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 11:59:25.765489 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 11:59:25.768848 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 11:59:25.771526 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 11:59:25.778523 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 11:59:25.781724 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 11:59:25.785208 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 11:59:25.791676 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8353 11:59:25.795254 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:59:25.798173 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:59:25.805271 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:59:25.808055 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:59:25.811701 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:59:25.818777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:59:25.821949 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:59:25.825138 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:59:25.831859 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:59:25.834701 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:59:25.837852 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:59:25.844407 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:59:25.848062 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:59:25.851246 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 11:59:25.857696 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8368 11:59:25.861283 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8369 11:59:25.864422 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 11:59:25.868151 Total UI for P1: 0, mck2ui 16
8371 11:59:25.871316 best dqsien dly found for B0: ( 1, 9, 10)
8372 11:59:25.874261 Total UI for P1: 0, mck2ui 16
8373 11:59:25.877847 best dqsien dly found for B1: ( 1, 9, 10)
8374 11:59:25.881392 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8375 11:59:25.884323 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8376 11:59:25.884420
8377 11:59:25.887821 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8378 11:59:25.894288 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8379 11:59:25.894369 [Gating] SW calibration Done
8380 11:59:25.898112 ==
8381 11:59:25.898196 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 11:59:25.904583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 11:59:25.904690 ==
8384 11:59:25.904785 RX Vref Scan: 0
8385 11:59:25.904871
8386 11:59:25.907458 RX Vref 0 -> 0, step: 1
8387 11:59:25.907539
8388 11:59:25.911624 RX Delay 0 -> 252, step: 8
8389 11:59:25.914213 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8390 11:59:25.917551 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8391 11:59:25.920875 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8392 11:59:25.924312 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8393 11:59:25.931017 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8394 11:59:25.934474 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8395 11:59:25.938031 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8396 11:59:25.940983 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8397 11:59:25.944514 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8398 11:59:25.951233 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8399 11:59:25.954323 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8400 11:59:25.958103 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8401 11:59:25.961183 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8402 11:59:25.964308 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8403 11:59:25.971304 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8404 11:59:25.974585 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8405 11:59:25.974667 ==
8406 11:59:25.977737 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 11:59:25.980877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 11:59:25.980996 ==
8409 11:59:25.984621 DQS Delay:
8410 11:59:25.984738 DQS0 = 0, DQS1 = 0
8411 11:59:25.984802 DQM Delay:
8412 11:59:25.987889 DQM0 = 136, DQM1 = 133
8413 11:59:25.987971 DQ Delay:
8414 11:59:25.990876 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8415 11:59:25.994311 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8416 11:59:26.000660 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8417 11:59:26.004696 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =147
8418 11:59:26.004777
8419 11:59:26.004841
8420 11:59:26.004900 ==
8421 11:59:26.007785 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 11:59:26.010837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 11:59:26.010919 ==
8424 11:59:26.010982
8425 11:59:26.011041
8426 11:59:26.014636 TX Vref Scan disable
8427 11:59:26.014717 == TX Byte 0 ==
8428 11:59:26.021255 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 11:59:26.024426 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 11:59:26.024507 == TX Byte 1 ==
8431 11:59:26.030725 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8432 11:59:26.034126 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8433 11:59:26.034207 ==
8434 11:59:26.037667 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 11:59:26.040626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 11:59:26.040729 ==
8437 11:59:26.054482
8438 11:59:26.057783 TX Vref early break, caculate TX vref
8439 11:59:26.061242 TX Vref=16, minBit 0, minWin=22, winSum=372
8440 11:59:26.064659 TX Vref=18, minBit 1, minWin=23, winSum=380
8441 11:59:26.067712 TX Vref=20, minBit 0, minWin=24, winSum=389
8442 11:59:26.071161 TX Vref=22, minBit 0, minWin=24, winSum=401
8443 11:59:26.075019 TX Vref=24, minBit 1, minWin=25, winSum=410
8444 11:59:26.081131 TX Vref=26, minBit 0, minWin=25, winSum=416
8445 11:59:26.084416 TX Vref=28, minBit 2, minWin=25, winSum=423
8446 11:59:26.088142 TX Vref=30, minBit 0, minWin=25, winSum=420
8447 11:59:26.091309 TX Vref=32, minBit 6, minWin=24, winSum=412
8448 11:59:26.094559 TX Vref=34, minBit 0, minWin=24, winSum=396
8449 11:59:26.101104 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
8450 11:59:26.101189
8451 11:59:26.104507 Final TX Range 0 Vref 28
8452 11:59:26.104583
8453 11:59:26.104645 ==
8454 11:59:26.107807 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 11:59:26.111244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 11:59:26.111318 ==
8457 11:59:26.111385
8458 11:59:26.111452
8459 11:59:26.114347 TX Vref Scan disable
8460 11:59:26.121412 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8461 11:59:26.121494 == TX Byte 0 ==
8462 11:59:26.124448 u2DelayCellOfst[0]=20 cells (6 PI)
8463 11:59:26.127544 u2DelayCellOfst[1]=13 cells (4 PI)
8464 11:59:26.131233 u2DelayCellOfst[2]=0 cells (0 PI)
8465 11:59:26.134221 u2DelayCellOfst[3]=10 cells (3 PI)
8466 11:59:26.137547 u2DelayCellOfst[4]=10 cells (3 PI)
8467 11:59:26.141116 u2DelayCellOfst[5]=20 cells (6 PI)
8468 11:59:26.144384 u2DelayCellOfst[6]=20 cells (6 PI)
8469 11:59:26.147381 u2DelayCellOfst[7]=10 cells (3 PI)
8470 11:59:26.150845 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8471 11:59:26.154609 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8472 11:59:26.154692 == TX Byte 1 ==
8473 11:59:26.157764 u2DelayCellOfst[8]=0 cells (0 PI)
8474 11:59:26.161021 u2DelayCellOfst[9]=3 cells (1 PI)
8475 11:59:26.164467 u2DelayCellOfst[10]=13 cells (4 PI)
8476 11:59:26.167262 u2DelayCellOfst[11]=6 cells (2 PI)
8477 11:59:26.171194 u2DelayCellOfst[12]=16 cells (5 PI)
8478 11:59:26.174136 u2DelayCellOfst[13]=16 cells (5 PI)
8479 11:59:26.177502 u2DelayCellOfst[14]=20 cells (6 PI)
8480 11:59:26.181064 u2DelayCellOfst[15]=20 cells (6 PI)
8481 11:59:26.184388 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8482 11:59:26.190694 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8483 11:59:26.190783 DramC Write-DBI on
8484 11:59:26.190848 ==
8485 11:59:26.193978 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 11:59:26.197272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 11:59:26.200599 ==
8488 11:59:26.200681
8489 11:59:26.200745
8490 11:59:26.200817 TX Vref Scan disable
8491 11:59:26.204080 == TX Byte 0 ==
8492 11:59:26.207656 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8493 11:59:26.210697 == TX Byte 1 ==
8494 11:59:26.214179 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8495 11:59:26.217570 DramC Write-DBI off
8496 11:59:26.217723
8497 11:59:26.217803 [DATLAT]
8498 11:59:26.217896 Freq=1600, CH1 RK0
8499 11:59:26.217996
8500 11:59:26.221036 DATLAT Default: 0xf
8501 11:59:26.221154 0, 0xFFFF, sum = 0
8502 11:59:26.223835 1, 0xFFFF, sum = 0
8503 11:59:26.223909 2, 0xFFFF, sum = 0
8504 11:59:26.227695 3, 0xFFFF, sum = 0
8505 11:59:26.231046 4, 0xFFFF, sum = 0
8506 11:59:26.231129 5, 0xFFFF, sum = 0
8507 11:59:26.234172 6, 0xFFFF, sum = 0
8508 11:59:26.234254 7, 0xFFFF, sum = 0
8509 11:59:26.237327 8, 0xFFFF, sum = 0
8510 11:59:26.237462 9, 0xFFFF, sum = 0
8511 11:59:26.241365 10, 0xFFFF, sum = 0
8512 11:59:26.241450 11, 0xFFFF, sum = 0
8513 11:59:26.244289 12, 0xFFFF, sum = 0
8514 11:59:26.244371 13, 0xFFFF, sum = 0
8515 11:59:26.247305 14, 0x0, sum = 1
8516 11:59:26.247387 15, 0x0, sum = 2
8517 11:59:26.250511 16, 0x0, sum = 3
8518 11:59:26.250593 17, 0x0, sum = 4
8519 11:59:26.254048 best_step = 15
8520 11:59:26.254128
8521 11:59:26.254191 ==
8522 11:59:26.257832 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 11:59:26.260901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 11:59:26.261008 ==
8525 11:59:26.261115 RX Vref Scan: 1
8526 11:59:26.261175
8527 11:59:26.264263 Set Vref Range= 24 -> 127
8528 11:59:26.264344
8529 11:59:26.267254 RX Vref 24 -> 127, step: 1
8530 11:59:26.267335
8531 11:59:26.270677 RX Delay 27 -> 252, step: 4
8532 11:59:26.270757
8533 11:59:26.273916 Set Vref, RX VrefLevel [Byte0]: 24
8534 11:59:26.277283 [Byte1]: 24
8535 11:59:26.277364
8536 11:59:26.280568 Set Vref, RX VrefLevel [Byte0]: 25
8537 11:59:26.283782 [Byte1]: 25
8538 11:59:26.283862
8539 11:59:26.287301 Set Vref, RX VrefLevel [Byte0]: 26
8540 11:59:26.290586 [Byte1]: 26
8541 11:59:26.294157
8542 11:59:26.294238 Set Vref, RX VrefLevel [Byte0]: 27
8543 11:59:26.297763 [Byte1]: 27
8544 11:59:26.301624
8545 11:59:26.301718 Set Vref, RX VrefLevel [Byte0]: 28
8546 11:59:26.305411 [Byte1]: 28
8547 11:59:26.309337
8548 11:59:26.309419 Set Vref, RX VrefLevel [Byte0]: 29
8549 11:59:26.312599 [Byte1]: 29
8550 11:59:26.317079
8551 11:59:26.317160 Set Vref, RX VrefLevel [Byte0]: 30
8552 11:59:26.320069 [Byte1]: 30
8553 11:59:26.324159
8554 11:59:26.324239 Set Vref, RX VrefLevel [Byte0]: 31
8555 11:59:26.327682 [Byte1]: 31
8556 11:59:26.331851
8557 11:59:26.331932 Set Vref, RX VrefLevel [Byte0]: 32
8558 11:59:26.335239 [Byte1]: 32
8559 11:59:26.339365
8560 11:59:26.339447 Set Vref, RX VrefLevel [Byte0]: 33
8561 11:59:26.342702 [Byte1]: 33
8562 11:59:26.347146
8563 11:59:26.347227 Set Vref, RX VrefLevel [Byte0]: 34
8564 11:59:26.350502 [Byte1]: 34
8565 11:59:26.354739
8566 11:59:26.354835 Set Vref, RX VrefLevel [Byte0]: 35
8567 11:59:26.357848 [Byte1]: 35
8568 11:59:26.362299
8569 11:59:26.362381 Set Vref, RX VrefLevel [Byte0]: 36
8570 11:59:26.365014 [Byte1]: 36
8571 11:59:26.369926
8572 11:59:26.370007 Set Vref, RX VrefLevel [Byte0]: 37
8573 11:59:26.372822 [Byte1]: 37
8574 11:59:26.377463
8575 11:59:26.377543 Set Vref, RX VrefLevel [Byte0]: 38
8576 11:59:26.380403 [Byte1]: 38
8577 11:59:26.384703
8578 11:59:26.384783 Set Vref, RX VrefLevel [Byte0]: 39
8579 11:59:26.387940 [Byte1]: 39
8580 11:59:26.392106
8581 11:59:26.392186 Set Vref, RX VrefLevel [Byte0]: 40
8582 11:59:26.395714 [Byte1]: 40
8583 11:59:26.400004
8584 11:59:26.400085 Set Vref, RX VrefLevel [Byte0]: 41
8585 11:59:26.403421 [Byte1]: 41
8586 11:59:26.407695
8587 11:59:26.407776 Set Vref, RX VrefLevel [Byte0]: 42
8588 11:59:26.410856 [Byte1]: 42
8589 11:59:26.414539
8590 11:59:26.414619 Set Vref, RX VrefLevel [Byte0]: 43
8591 11:59:26.418262 [Byte1]: 43
8592 11:59:26.422546
8593 11:59:26.422627 Set Vref, RX VrefLevel [Byte0]: 44
8594 11:59:26.425497 [Byte1]: 44
8595 11:59:26.429724
8596 11:59:26.429804 Set Vref, RX VrefLevel [Byte0]: 45
8597 11:59:26.433360 [Byte1]: 45
8598 11:59:26.437481
8599 11:59:26.437612 Set Vref, RX VrefLevel [Byte0]: 46
8600 11:59:26.440969 [Byte1]: 46
8601 11:59:26.445126
8602 11:59:26.445208 Set Vref, RX VrefLevel [Byte0]: 47
8603 11:59:26.448361 [Byte1]: 47
8604 11:59:26.452436
8605 11:59:26.452518 Set Vref, RX VrefLevel [Byte0]: 48
8606 11:59:26.455817 [Byte1]: 48
8607 11:59:26.460034
8608 11:59:26.460115 Set Vref, RX VrefLevel [Byte0]: 49
8609 11:59:26.463236 [Byte1]: 49
8610 11:59:26.467584
8611 11:59:26.467664 Set Vref, RX VrefLevel [Byte0]: 50
8612 11:59:26.470991 [Byte1]: 50
8613 11:59:26.475202
8614 11:59:26.475283 Set Vref, RX VrefLevel [Byte0]: 51
8615 11:59:26.478535 [Byte1]: 51
8616 11:59:26.482915
8617 11:59:26.482995 Set Vref, RX VrefLevel [Byte0]: 52
8618 11:59:26.485859 [Byte1]: 52
8619 11:59:26.490190
8620 11:59:26.490270 Set Vref, RX VrefLevel [Byte0]: 53
8621 11:59:26.493386 [Byte1]: 53
8622 11:59:26.497458
8623 11:59:26.497539 Set Vref, RX VrefLevel [Byte0]: 54
8624 11:59:26.501056 [Byte1]: 54
8625 11:59:26.505163
8626 11:59:26.505244 Set Vref, RX VrefLevel [Byte0]: 55
8627 11:59:26.508274 [Byte1]: 55
8628 11:59:26.512584
8629 11:59:26.512665 Set Vref, RX VrefLevel [Byte0]: 56
8630 11:59:26.515713 [Byte1]: 56
8631 11:59:26.520045
8632 11:59:26.520126 Set Vref, RX VrefLevel [Byte0]: 57
8633 11:59:26.523762 [Byte1]: 57
8634 11:59:26.527732
8635 11:59:26.527813 Set Vref, RX VrefLevel [Byte0]: 58
8636 11:59:26.531459 [Byte1]: 58
8637 11:59:26.535160
8638 11:59:26.535241 Set Vref, RX VrefLevel [Byte0]: 59
8639 11:59:26.538821 [Byte1]: 59
8640 11:59:26.542743
8641 11:59:26.542824 Set Vref, RX VrefLevel [Byte0]: 60
8642 11:59:26.546343 [Byte1]: 60
8643 11:59:26.550264
8644 11:59:26.550344 Set Vref, RX VrefLevel [Byte0]: 61
8645 11:59:26.553725 [Byte1]: 61
8646 11:59:26.557863
8647 11:59:26.557944 Set Vref, RX VrefLevel [Byte0]: 62
8648 11:59:26.561612 [Byte1]: 62
8649 11:59:26.565299
8650 11:59:26.565380 Set Vref, RX VrefLevel [Byte0]: 63
8651 11:59:26.568603 [Byte1]: 63
8652 11:59:26.573076
8653 11:59:26.573168 Set Vref, RX VrefLevel [Byte0]: 64
8654 11:59:26.576498 [Byte1]: 64
8655 11:59:26.580582
8656 11:59:26.580663 Set Vref, RX VrefLevel [Byte0]: 65
8657 11:59:26.583754 [Byte1]: 65
8658 11:59:26.588067
8659 11:59:26.588148 Set Vref, RX VrefLevel [Byte0]: 66
8660 11:59:26.591477 [Byte1]: 66
8661 11:59:26.595456
8662 11:59:26.595535 Set Vref, RX VrefLevel [Byte0]: 67
8663 11:59:26.598611 [Byte1]: 67
8664 11:59:26.603121
8665 11:59:26.603220 Set Vref, RX VrefLevel [Byte0]: 68
8666 11:59:26.606414 [Byte1]: 68
8667 11:59:26.610619
8668 11:59:26.610690 Set Vref, RX VrefLevel [Byte0]: 69
8669 11:59:26.614154 [Byte1]: 69
8670 11:59:26.617957
8671 11:59:26.618075 Set Vref, RX VrefLevel [Byte0]: 70
8672 11:59:26.621709 [Byte1]: 70
8673 11:59:26.625440
8674 11:59:26.625536 Set Vref, RX VrefLevel [Byte0]: 71
8675 11:59:26.629197 [Byte1]: 71
8676 11:59:26.632956
8677 11:59:26.633039 Set Vref, RX VrefLevel [Byte0]: 72
8678 11:59:26.636810 [Byte1]: 72
8679 11:59:26.641123
8680 11:59:26.641228 Set Vref, RX VrefLevel [Byte0]: 73
8681 11:59:26.644251 [Byte1]: 73
8682 11:59:26.648231
8683 11:59:26.648327 Set Vref, RX VrefLevel [Byte0]: 74
8684 11:59:26.651940 [Byte1]: 74
8685 11:59:26.656026
8686 11:59:26.656123 Set Vref, RX VrefLevel [Byte0]: 75
8687 11:59:26.659324 [Byte1]: 75
8688 11:59:26.663238
8689 11:59:26.663315 Final RX Vref Byte 0 = 57 to rank0
8690 11:59:26.666754 Final RX Vref Byte 1 = 57 to rank0
8691 11:59:26.670122 Final RX Vref Byte 0 = 57 to rank1
8692 11:59:26.673280 Final RX Vref Byte 1 = 57 to rank1==
8693 11:59:26.676734 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 11:59:26.683350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 11:59:26.683433 ==
8696 11:59:26.683497 DQS Delay:
8697 11:59:26.683556 DQS0 = 0, DQS1 = 0
8698 11:59:26.686492 DQM Delay:
8699 11:59:26.686573 DQM0 = 134, DQM1 = 131
8700 11:59:26.689773 DQ Delay:
8701 11:59:26.693008 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8702 11:59:26.696344 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8703 11:59:26.700469 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8704 11:59:26.703116 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8705 11:59:26.703197
8706 11:59:26.703261
8707 11:59:26.703320
8708 11:59:26.706475 [DramC_TX_OE_Calibration] TA2
8709 11:59:26.709585 Original DQ_B0 (3 6) =30, OEN = 27
8710 11:59:26.713467 Original DQ_B1 (3 6) =30, OEN = 27
8711 11:59:26.716399 24, 0x0, End_B0=24 End_B1=24
8712 11:59:26.716482 25, 0x0, End_B0=25 End_B1=25
8713 11:59:26.719788 26, 0x0, End_B0=26 End_B1=26
8714 11:59:26.723134 27, 0x0, End_B0=27 End_B1=27
8715 11:59:26.726589 28, 0x0, End_B0=28 End_B1=28
8716 11:59:26.726672 29, 0x0, End_B0=29 End_B1=29
8717 11:59:26.729741 30, 0x0, End_B0=30 End_B1=30
8718 11:59:26.732913 31, 0x4141, End_B0=30 End_B1=30
8719 11:59:26.736801 Byte0 end_step=30 best_step=27
8720 11:59:26.739842 Byte1 end_step=30 best_step=27
8721 11:59:26.743079 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 11:59:26.743160 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 11:59:26.746288
8724 11:59:26.746369
8725 11:59:26.753271 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8726 11:59:26.756426 CH1 RK0: MR19=303, MR18=1826
8727 11:59:26.763300 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8728 11:59:26.763381
8729 11:59:26.766456 ----->DramcWriteLeveling(PI) begin...
8730 11:59:26.766538 ==
8731 11:59:26.769435 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 11:59:26.773126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 11:59:26.773208 ==
8734 11:59:26.776575 Write leveling (Byte 0): 25 => 25
8735 11:59:26.779741 Write leveling (Byte 1): 29 => 29
8736 11:59:26.782774 DramcWriteLeveling(PI) end<-----
8737 11:59:26.782854
8738 11:59:26.782940 ==
8739 11:59:26.786277 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 11:59:26.789289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 11:59:26.789385 ==
8742 11:59:26.793148 [Gating] SW mode calibration
8743 11:59:26.799683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 11:59:26.806543 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 11:59:26.809268 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 11:59:26.812759 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 11:59:26.819470 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8748 11:59:26.823215 1 4 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
8749 11:59:26.825803 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 11:59:26.832638 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 11:59:26.835803 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 11:59:26.839566 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 11:59:26.845840 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 11:59:26.849128 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8755 11:59:26.852735 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
8756 11:59:26.859125 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
8757 11:59:26.862222 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 11:59:26.865923 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 11:59:26.872840 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 11:59:26.876042 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 11:59:26.879140 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 11:59:26.885752 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8763 11:59:26.888946 1 6 8 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
8764 11:59:26.892490 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8765 11:59:26.899027 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 11:59:26.902245 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 11:59:26.905463 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 11:59:26.912284 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 11:59:26.915562 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 11:59:26.919165 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 11:59:26.925224 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8772 11:59:26.928810 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8773 11:59:26.932329 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8774 11:59:26.938701 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:59:26.941733 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 11:59:26.945060 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 11:59:26.951938 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 11:59:26.955060 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:59:26.958537 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:59:26.962392 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:59:26.968562 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:59:26.972607 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:59:26.975677 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:59:26.982133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:59:26.985313 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:59:26.988892 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8787 11:59:26.995457 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8788 11:59:26.998984 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8789 11:59:27.001817 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 11:59:27.005345 Total UI for P1: 0, mck2ui 16
8791 11:59:27.008697 best dqsien dly found for B0: ( 1, 9, 12)
8792 11:59:27.012201 Total UI for P1: 0, mck2ui 16
8793 11:59:27.015211 best dqsien dly found for B1: ( 1, 9, 8)
8794 11:59:27.018462 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8795 11:59:27.021694 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8796 11:59:27.021808
8797 11:59:27.028800 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8798 11:59:27.032317 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8799 11:59:27.032399 [Gating] SW calibration Done
8800 11:59:27.035013 ==
8801 11:59:27.038803 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 11:59:27.042142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 11:59:27.042227 ==
8804 11:59:27.042292 RX Vref Scan: 0
8805 11:59:27.042352
8806 11:59:27.045088 RX Vref 0 -> 0, step: 1
8807 11:59:27.045169
8808 11:59:27.048857 RX Delay 0 -> 252, step: 8
8809 11:59:27.052370 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8810 11:59:27.054988 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8811 11:59:27.058457 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8812 11:59:27.064995 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8813 11:59:27.068537 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8814 11:59:27.071906 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8815 11:59:27.075546 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8816 11:59:27.078384 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8817 11:59:27.085349 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8818 11:59:27.088514 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8819 11:59:27.092342 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8820 11:59:27.095330 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8821 11:59:27.098613 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8822 11:59:27.104780 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8823 11:59:27.108559 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8824 11:59:27.111674 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8825 11:59:27.111756 ==
8826 11:59:27.115260 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 11:59:27.117990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 11:59:27.121572 ==
8829 11:59:27.121675 DQS Delay:
8830 11:59:27.121739 DQS0 = 0, DQS1 = 0
8831 11:59:27.124851 DQM Delay:
8832 11:59:27.124931 DQM0 = 136, DQM1 = 133
8833 11:59:27.128182 DQ Delay:
8834 11:59:27.131304 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8835 11:59:27.135051 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8836 11:59:27.138090 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8837 11:59:27.141959 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8838 11:59:27.142042
8839 11:59:27.142105
8840 11:59:27.142184 ==
8841 11:59:27.144833 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 11:59:27.148078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 11:59:27.148160 ==
8844 11:59:27.148223
8845 11:59:27.151304
8846 11:59:27.151385 TX Vref Scan disable
8847 11:59:27.154896 == TX Byte 0 ==
8848 11:59:27.157768 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8849 11:59:27.161505 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8850 11:59:27.164783 == TX Byte 1 ==
8851 11:59:27.167725 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8852 11:59:27.171260 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8853 11:59:27.171341 ==
8854 11:59:27.174626 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 11:59:27.181000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 11:59:27.181083 ==
8857 11:59:27.194019
8858 11:59:27.197663 TX Vref early break, caculate TX vref
8859 11:59:27.200864 TX Vref=16, minBit 0, minWin=23, winSum=380
8860 11:59:27.204071 TX Vref=18, minBit 0, minWin=24, winSum=391
8861 11:59:27.207100 TX Vref=20, minBit 0, minWin=23, winSum=396
8862 11:59:27.211156 TX Vref=22, minBit 0, minWin=24, winSum=407
8863 11:59:27.214430 TX Vref=24, minBit 0, minWin=25, winSum=418
8864 11:59:27.221025 TX Vref=26, minBit 0, minWin=25, winSum=421
8865 11:59:27.224517 TX Vref=28, minBit 0, minWin=25, winSum=422
8866 11:59:27.227387 TX Vref=30, minBit 1, minWin=25, winSum=419
8867 11:59:27.230518 TX Vref=32, minBit 0, minWin=25, winSum=412
8868 11:59:27.234167 TX Vref=34, minBit 0, minWin=24, winSum=403
8869 11:59:27.237132 TX Vref=36, minBit 6, minWin=23, winSum=389
8870 11:59:27.244425 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8871 11:59:27.244512
8872 11:59:27.247708 Final TX Range 0 Vref 28
8873 11:59:27.247789
8874 11:59:27.247853 ==
8875 11:59:27.250870 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 11:59:27.254059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 11:59:27.254141 ==
8878 11:59:27.254234
8879 11:59:27.254322
8880 11:59:27.257320 TX Vref Scan disable
8881 11:59:27.263775 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8882 11:59:27.263857 == TX Byte 0 ==
8883 11:59:27.267297 u2DelayCellOfst[0]=16 cells (5 PI)
8884 11:59:27.270452 u2DelayCellOfst[1]=13 cells (4 PI)
8885 11:59:27.274098 u2DelayCellOfst[2]=0 cells (0 PI)
8886 11:59:27.277250 u2DelayCellOfst[3]=6 cells (2 PI)
8887 11:59:27.280407 u2DelayCellOfst[4]=10 cells (3 PI)
8888 11:59:27.284001 u2DelayCellOfst[5]=16 cells (5 PI)
8889 11:59:27.287475 u2DelayCellOfst[6]=20 cells (6 PI)
8890 11:59:27.290796 u2DelayCellOfst[7]=6 cells (2 PI)
8891 11:59:27.294158 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8892 11:59:27.297164 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 11:59:27.300636 == TX Byte 1 ==
8894 11:59:27.300717 u2DelayCellOfst[8]=0 cells (0 PI)
8895 11:59:27.303739 u2DelayCellOfst[9]=3 cells (1 PI)
8896 11:59:27.306962 u2DelayCellOfst[10]=10 cells (3 PI)
8897 11:59:27.310360 u2DelayCellOfst[11]=6 cells (2 PI)
8898 11:59:27.314064 u2DelayCellOfst[12]=13 cells (4 PI)
8899 11:59:27.316908 u2DelayCellOfst[13]=16 cells (5 PI)
8900 11:59:27.320182 u2DelayCellOfst[14]=16 cells (5 PI)
8901 11:59:27.323796 u2DelayCellOfst[15]=20 cells (6 PI)
8902 11:59:27.326728 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 11:59:27.333602 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8904 11:59:27.333725 DramC Write-DBI on
8905 11:59:27.333821 ==
8906 11:59:27.336814 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 11:59:27.343676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 11:59:27.343759 ==
8909 11:59:27.343823
8910 11:59:27.343882
8911 11:59:27.343938 TX Vref Scan disable
8912 11:59:27.347307 == TX Byte 0 ==
8913 11:59:27.350345 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8914 11:59:27.353662 == TX Byte 1 ==
8915 11:59:27.357244 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 11:59:27.360199 DramC Write-DBI off
8917 11:59:27.360300
8918 11:59:27.360410 [DATLAT]
8919 11:59:27.360499 Freq=1600, CH1 RK1
8920 11:59:27.360598
8921 11:59:27.363998 DATLAT Default: 0xf
8922 11:59:27.364113 0, 0xFFFF, sum = 0
8923 11:59:27.367080 1, 0xFFFF, sum = 0
8924 11:59:27.370260 2, 0xFFFF, sum = 0
8925 11:59:27.370335 3, 0xFFFF, sum = 0
8926 11:59:27.373709 4, 0xFFFF, sum = 0
8927 11:59:27.373787 5, 0xFFFF, sum = 0
8928 11:59:27.377692 6, 0xFFFF, sum = 0
8929 11:59:27.377769 7, 0xFFFF, sum = 0
8930 11:59:27.380357 8, 0xFFFF, sum = 0
8931 11:59:27.380433 9, 0xFFFF, sum = 0
8932 11:59:27.383621 10, 0xFFFF, sum = 0
8933 11:59:27.383695 11, 0xFFFF, sum = 0
8934 11:59:27.387053 12, 0xFFFF, sum = 0
8935 11:59:27.387134 13, 0xFFFF, sum = 0
8936 11:59:27.390178 14, 0x0, sum = 1
8937 11:59:27.390254 15, 0x0, sum = 2
8938 11:59:27.393965 16, 0x0, sum = 3
8939 11:59:27.394037 17, 0x0, sum = 4
8940 11:59:27.396853 best_step = 15
8941 11:59:27.396923
8942 11:59:27.396982 ==
8943 11:59:27.400213 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 11:59:27.403599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 11:59:27.403680 ==
8946 11:59:27.407085 RX Vref Scan: 0
8947 11:59:27.407157
8948 11:59:27.407218 RX Vref 0 -> 0, step: 1
8949 11:59:27.407275
8950 11:59:27.410502 RX Delay 19 -> 252, step: 4
8951 11:59:27.413499 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8952 11:59:27.420458 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8953 11:59:27.423718 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8954 11:59:27.426856 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8955 11:59:27.430635 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8956 11:59:27.433919 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8957 11:59:27.437377 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8958 11:59:27.443717 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8959 11:59:27.446828 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8960 11:59:27.450464 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8961 11:59:27.453469 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8962 11:59:27.457228 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8963 11:59:27.463739 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8964 11:59:27.467170 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8965 11:59:27.470253 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8966 11:59:27.474128 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8967 11:59:27.474202 ==
8968 11:59:27.477169 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 11:59:27.483408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 11:59:27.483485 ==
8971 11:59:27.483547 DQS Delay:
8972 11:59:27.486859 DQS0 = 0, DQS1 = 0
8973 11:59:27.486934 DQM Delay:
8974 11:59:27.486996 DQM0 = 133, DQM1 = 130
8975 11:59:27.490460 DQ Delay:
8976 11:59:27.493813 DQ0 =138, DQ1 =128, DQ2 =120, DQ3 =130
8977 11:59:27.496820 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8978 11:59:27.500619 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8979 11:59:27.503694 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8980 11:59:27.503767
8981 11:59:27.503827
8982 11:59:27.503893
8983 11:59:27.507478 [DramC_TX_OE_Calibration] TA2
8984 11:59:27.510188 Original DQ_B0 (3 6) =30, OEN = 27
8985 11:59:27.513588 Original DQ_B1 (3 6) =30, OEN = 27
8986 11:59:27.517451 24, 0x0, End_B0=24 End_B1=24
8987 11:59:27.517552 25, 0x0, End_B0=25 End_B1=25
8988 11:59:27.520310 26, 0x0, End_B0=26 End_B1=26
8989 11:59:27.523794 27, 0x0, End_B0=27 End_B1=27
8990 11:59:27.526895 28, 0x0, End_B0=28 End_B1=28
8991 11:59:27.530698 29, 0x0, End_B0=29 End_B1=29
8992 11:59:27.530778 30, 0x0, End_B0=30 End_B1=30
8993 11:59:27.533873 31, 0x4141, End_B0=30 End_B1=30
8994 11:59:27.537119 Byte0 end_step=30 best_step=27
8995 11:59:27.540076 Byte1 end_step=30 best_step=27
8996 11:59:27.543779 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 11:59:27.543854 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 11:59:27.547324
8999 11:59:27.547399
9000 11:59:27.554165 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9001 11:59:27.557140 CH1 RK1: MR19=303, MR18=2409
9002 11:59:27.563620 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9003 11:59:27.567087 [RxdqsGatingPostProcess] freq 1600
9004 11:59:27.570238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 11:59:27.574046 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 11:59:27.577269 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 11:59:27.580393 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 11:59:27.583672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 11:59:27.586673 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 11:59:27.590317 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 11:59:27.593625 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 11:59:27.597304 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 11:59:27.600391 Pre-setting of DQS Precalculation
9014 11:59:27.603407 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 11:59:27.610641 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 11:59:27.616797 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 11:59:27.616878
9018 11:59:27.616941
9019 11:59:27.620166 [Calibration Summary] 3200 Mbps
9020 11:59:27.623506 CH 0, Rank 0
9021 11:59:27.623586 SW Impedance : PASS
9022 11:59:27.626909 DUTY Scan : NO K
9023 11:59:27.630364 ZQ Calibration : PASS
9024 11:59:27.630463 Jitter Meter : NO K
9025 11:59:27.633554 CBT Training : PASS
9026 11:59:27.636769 Write leveling : PASS
9027 11:59:27.636849 RX DQS gating : PASS
9028 11:59:27.639893 RX DQ/DQS(RDDQC) : PASS
9029 11:59:27.643630 TX DQ/DQS : PASS
9030 11:59:27.643715 RX DATLAT : PASS
9031 11:59:27.646629 RX DQ/DQS(Engine): PASS
9032 11:59:27.646712 TX OE : PASS
9033 11:59:27.650451 All Pass.
9034 11:59:27.650534
9035 11:59:27.650598 CH 0, Rank 1
9036 11:59:27.653751 SW Impedance : PASS
9037 11:59:27.653833 DUTY Scan : NO K
9038 11:59:27.656822 ZQ Calibration : PASS
9039 11:59:27.660318 Jitter Meter : NO K
9040 11:59:27.660399 CBT Training : PASS
9041 11:59:27.663270 Write leveling : PASS
9042 11:59:27.666527 RX DQS gating : PASS
9043 11:59:27.666608 RX DQ/DQS(RDDQC) : PASS
9044 11:59:27.670373 TX DQ/DQS : PASS
9045 11:59:27.673447 RX DATLAT : PASS
9046 11:59:27.673528 RX DQ/DQS(Engine): PASS
9047 11:59:27.676498 TX OE : PASS
9048 11:59:27.676578 All Pass.
9049 11:59:27.676642
9050 11:59:27.680234 CH 1, Rank 0
9051 11:59:27.680315 SW Impedance : PASS
9052 11:59:27.683120 DUTY Scan : NO K
9053 11:59:27.686779 ZQ Calibration : PASS
9054 11:59:27.686878 Jitter Meter : NO K
9055 11:59:27.689823 CBT Training : PASS
9056 11:59:27.693458 Write leveling : PASS
9057 11:59:27.693539 RX DQS gating : PASS
9058 11:59:27.696576 RX DQ/DQS(RDDQC) : PASS
9059 11:59:27.696656 TX DQ/DQS : PASS
9060 11:59:27.700240 RX DATLAT : PASS
9061 11:59:27.703620 RX DQ/DQS(Engine): PASS
9062 11:59:27.703701 TX OE : PASS
9063 11:59:27.707017 All Pass.
9064 11:59:27.707097
9065 11:59:27.707160 CH 1, Rank 1
9066 11:59:27.710213 SW Impedance : PASS
9067 11:59:27.710294 DUTY Scan : NO K
9068 11:59:27.713152 ZQ Calibration : PASS
9069 11:59:27.716680 Jitter Meter : NO K
9070 11:59:27.716760 CBT Training : PASS
9071 11:59:27.719982 Write leveling : PASS
9072 11:59:27.723512 RX DQS gating : PASS
9073 11:59:27.723593 RX DQ/DQS(RDDQC) : PASS
9074 11:59:27.726468 TX DQ/DQS : PASS
9075 11:59:27.730240 RX DATLAT : PASS
9076 11:59:27.730321 RX DQ/DQS(Engine): PASS
9077 11:59:27.733216 TX OE : PASS
9078 11:59:27.733297 All Pass.
9079 11:59:27.733360
9080 11:59:27.736614 DramC Write-DBI on
9081 11:59:27.740203 PER_BANK_REFRESH: Hybrid Mode
9082 11:59:27.740285 TX_TRACKING: ON
9083 11:59:27.750245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 11:59:27.756528 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 11:59:27.763338 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 11:59:27.766382 [FAST_K] Save calibration result to emmc
9087 11:59:27.769771 sync common calibartion params.
9088 11:59:27.773195 sync cbt_mode0:1, 1:1
9089 11:59:27.776378 dram_init: ddr_geometry: 2
9090 11:59:27.776459 dram_init: ddr_geometry: 2
9091 11:59:27.779680 dram_init: ddr_geometry: 2
9092 11:59:27.783201 0:dram_rank_size:100000000
9093 11:59:27.783312 1:dram_rank_size:100000000
9094 11:59:27.789831 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 11:59:27.792827 DFS_SHUFFLE_HW_MODE: ON
9096 11:59:27.796394 dramc_set_vcore_voltage set vcore to 725000
9097 11:59:27.799553 Read voltage for 1600, 0
9098 11:59:27.799634 Vio18 = 0
9099 11:59:27.799697 Vcore = 725000
9100 11:59:27.803276 Vdram = 0
9101 11:59:27.803384 Vddq = 0
9102 11:59:27.803476 Vmddr = 0
9103 11:59:27.806379 switch to 3200 Mbps bootup
9104 11:59:27.806460 [DramcRunTimeConfig]
9105 11:59:27.809806 PHYPLL
9106 11:59:27.809887 DPM_CONTROL_AFTERK: ON
9107 11:59:27.813374 PER_BANK_REFRESH: ON
9108 11:59:27.816449 REFRESH_OVERHEAD_REDUCTION: ON
9109 11:59:27.816529 CMD_PICG_NEW_MODE: OFF
9110 11:59:27.819522 XRTWTW_NEW_MODE: ON
9111 11:59:27.819602 XRTRTR_NEW_MODE: ON
9112 11:59:27.822746 TX_TRACKING: ON
9113 11:59:27.822854 RDSEL_TRACKING: OFF
9114 11:59:27.826254 DQS Precalculation for DVFS: ON
9115 11:59:27.830069 RX_TRACKING: OFF
9116 11:59:27.830176 HW_GATING DBG: ON
9117 11:59:27.832725 ZQCS_ENABLE_LP4: ON
9118 11:59:27.832806 RX_PICG_NEW_MODE: ON
9119 11:59:27.836200 TX_PICG_NEW_MODE: ON
9120 11:59:27.836281 ENABLE_RX_DCM_DPHY: ON
9121 11:59:27.839655 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 11:59:27.842921 DUMMY_READ_FOR_TRACKING: OFF
9123 11:59:27.846273 !!! SPM_CONTROL_AFTERK: OFF
9124 11:59:27.849446 !!! SPM could not control APHY
9125 11:59:27.849528 IMPEDANCE_TRACKING: ON
9126 11:59:27.852735 TEMP_SENSOR: ON
9127 11:59:27.852816 HW_SAVE_FOR_SR: OFF
9128 11:59:27.856482 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 11:59:27.859603 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 11:59:27.862615 Read ODT Tracking: ON
9131 11:59:27.866040 Refresh Rate DeBounce: ON
9132 11:59:27.866147 DFS_NO_QUEUE_FLUSH: ON
9133 11:59:27.869572 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 11:59:27.872856 ENABLE_DFS_RUNTIME_MRW: OFF
9135 11:59:27.875955 DDR_RESERVE_NEW_MODE: ON
9136 11:59:27.876036 MR_CBT_SWITCH_FREQ: ON
9137 11:59:27.879775 =========================
9138 11:59:27.898388 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 11:59:27.901692 dram_init: ddr_geometry: 2
9140 11:59:27.919959 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 11:59:27.923637 dram_init: dram init end (result: 0)
9142 11:59:27.930095 DRAM-K: Full calibration passed in 24450 msecs
9143 11:59:27.933446 MRC: failed to locate region type 0.
9144 11:59:27.933554 DRAM rank0 size:0x100000000,
9145 11:59:27.936365 DRAM rank1 size=0x100000000
9146 11:59:27.946803 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 11:59:27.953359 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 11:59:27.959760 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 11:59:27.966773 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 11:59:27.969815 DRAM rank0 size:0x100000000,
9151 11:59:27.973472 DRAM rank1 size=0x100000000
9152 11:59:27.973553 CBMEM:
9153 11:59:27.976687 IMD: root @ 0xfffff000 254 entries.
9154 11:59:27.979810 IMD: root @ 0xffffec00 62 entries.
9155 11:59:27.983465 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 11:59:27.986621 WARNING: RO_VPD is uninitialized or empty.
9157 11:59:27.993252 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 11:59:27.999958 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 11:59:28.012422 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9160 11:59:28.023901 BS: romstage times (exec / console): total (unknown) / 23983 ms
9161 11:59:28.023984
9162 11:59:28.024047
9163 11:59:28.033903 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 11:59:28.037513 ARM64: Exception handlers installed.
9165 11:59:28.040800 ARM64: Testing exception
9166 11:59:28.043845 ARM64: Done test exception
9167 11:59:28.043926 Enumerating buses...
9168 11:59:28.047691 Show all devs... Before device enumeration.
9169 11:59:28.050344 Root Device: enabled 1
9170 11:59:28.054086 CPU_CLUSTER: 0: enabled 1
9171 11:59:28.054167 CPU: 00: enabled 1
9172 11:59:28.057236 Compare with tree...
9173 11:59:28.057316 Root Device: enabled 1
9174 11:59:28.060270 CPU_CLUSTER: 0: enabled 1
9175 11:59:28.063910 CPU: 00: enabled 1
9176 11:59:28.063991 Root Device scanning...
9177 11:59:28.066867 scan_static_bus for Root Device
9178 11:59:28.070708 CPU_CLUSTER: 0 enabled
9179 11:59:28.074068 scan_static_bus for Root Device done
9180 11:59:28.077199 scan_bus: bus Root Device finished in 8 msecs
9181 11:59:28.077297 done
9182 11:59:28.083494 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 11:59:28.087285 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 11:59:28.093932 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 11:59:28.097081 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 11:59:28.100315 Allocating resources...
9187 11:59:28.103400 Reading resources...
9188 11:59:28.107292 Root Device read_resources bus 0 link: 0
9189 11:59:28.107373 DRAM rank0 size:0x100000000,
9190 11:59:28.110047 DRAM rank1 size=0x100000000
9191 11:59:28.113573 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 11:59:28.117081 CPU: 00 missing read_resources
9193 11:59:28.123726 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 11:59:28.126954 Root Device read_resources bus 0 link: 0 done
9195 11:59:28.127036 Done reading resources.
9196 11:59:28.133282 Show resources in subtree (Root Device)...After reading.
9197 11:59:28.136515 Root Device child on link 0 CPU_CLUSTER: 0
9198 11:59:28.140095 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 11:59:28.150033 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 11:59:28.150156 CPU: 00
9201 11:59:28.153511 Root Device assign_resources, bus 0 link: 0
9202 11:59:28.156591 CPU_CLUSTER: 0 missing set_resources
9203 11:59:28.163316 Root Device assign_resources, bus 0 link: 0 done
9204 11:59:28.163399 Done setting resources.
9205 11:59:28.170104 Show resources in subtree (Root Device)...After assigning values.
9206 11:59:28.173256 Root Device child on link 0 CPU_CLUSTER: 0
9207 11:59:28.176872 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 11:59:28.186882 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 11:59:28.186967 CPU: 00
9210 11:59:28.190119 Done allocating resources.
9211 11:59:28.193353 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 11:59:28.196621 Enabling resources...
9213 11:59:28.196702 done.
9214 11:59:28.203017 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 11:59:28.203100 Initializing devices...
9216 11:59:28.206643 Root Device init
9217 11:59:28.206724 init hardware done!
9218 11:59:28.209789 0x00000018: ctrlr->caps
9219 11:59:28.213013 52.000 MHz: ctrlr->f_max
9220 11:59:28.213096 0.400 MHz: ctrlr->f_min
9221 11:59:28.217068 0x40ff8080: ctrlr->voltages
9222 11:59:28.217150 sclk: 390625
9223 11:59:28.219830 Bus Width = 1
9224 11:59:28.219910 sclk: 390625
9225 11:59:28.223197 Bus Width = 1
9226 11:59:28.223278 Early init status = 3
9227 11:59:28.229440 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 11:59:28.233446 in-header: 03 fc 00 00 01 00 00 00
9229 11:59:28.233549 in-data: 00
9230 11:59:28.239784 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 11:59:28.242831 in-header: 03 fd 00 00 00 00 00 00
9232 11:59:28.246426 in-data:
9233 11:59:28.249572 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 11:59:28.253028 in-header: 03 fc 00 00 01 00 00 00
9235 11:59:28.256385 in-data: 00
9236 11:59:28.259222 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 11:59:28.264158 in-header: 03 fd 00 00 00 00 00 00
9238 11:59:28.267460 in-data:
9239 11:59:28.270475 [SSUSB] Setting up USB HOST controller...
9240 11:59:28.273900 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 11:59:28.277339 [SSUSB] phy power-on done.
9242 11:59:28.280436 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 11:59:28.287231 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 11:59:28.290695 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 11:59:28.297419 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 11:59:28.303820 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 11:59:28.310782 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 11:59:28.317030 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 11:59:28.323759 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 11:59:28.327376 SPM: binary array size = 0x9dc
9251 11:59:28.330020 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 11:59:28.336694 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 11:59:28.343568 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 11:59:28.346776 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 11:59:28.353201 configure_display: Starting display init
9256 11:59:28.387030 anx7625_power_on_init: Init interface.
9257 11:59:28.390695 anx7625_disable_pd_protocol: Disabled PD feature.
9258 11:59:28.393836 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 11:59:28.422195 anx7625_start_dp_work: Secure OCM version=00
9260 11:59:28.425382 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 11:59:28.439580 sp_tx_get_edid_block: EDID Block = 1
9262 11:59:28.542372 Extracted contents:
9263 11:59:28.545702 header: 00 ff ff ff ff ff ff 00
9264 11:59:28.549051 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 11:59:28.552417 version: 01 04
9266 11:59:28.555622 basic params: 95 1f 11 78 0a
9267 11:59:28.558761 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 11:59:28.562583 established: 00 00 00
9269 11:59:28.568799 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 11:59:28.572443 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 11:59:28.578600 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 11:59:28.585116 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 11:59:28.591722 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 11:59:28.595251 extensions: 00
9275 11:59:28.595333 checksum: fb
9276 11:59:28.595397
9277 11:59:28.598937 Manufacturer: IVO Model 57d Serial Number 0
9278 11:59:28.602322 Made week 0 of 2020
9279 11:59:28.602403 EDID version: 1.4
9280 11:59:28.605456 Digital display
9281 11:59:28.608757 6 bits per primary color channel
9282 11:59:28.608842 DisplayPort interface
9283 11:59:28.612032 Maximum image size: 31 cm x 17 cm
9284 11:59:28.615453 Gamma: 220%
9285 11:59:28.615535 Check DPMS levels
9286 11:59:28.618536 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 11:59:28.622233 First detailed timing is preferred timing
9288 11:59:28.625535 Established timings supported:
9289 11:59:28.628481 Standard timings supported:
9290 11:59:28.632036 Detailed timings
9291 11:59:28.635089 Hex of detail: 383680a07038204018303c0035ae10000019
9292 11:59:28.638810 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 11:59:28.645067 0780 0798 07c8 0820 hborder 0
9294 11:59:28.648257 0438 043b 0447 0458 vborder 0
9295 11:59:28.652130 -hsync -vsync
9296 11:59:28.652235 Did detailed timing
9297 11:59:28.655155 Hex of detail: 000000000000000000000000000000000000
9298 11:59:28.658759 Manufacturer-specified data, tag 0
9299 11:59:28.665440 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 11:59:28.668692 ASCII string: InfoVision
9301 11:59:28.671569 Hex of detail: 000000fe00523134304e574635205248200a
9302 11:59:28.675310 ASCII string: R140NWF5 RH
9303 11:59:28.675407 Checksum
9304 11:59:28.678305 Checksum: 0xfb (valid)
9305 11:59:28.682008 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 11:59:28.684841 DSI data_rate: 832800000 bps
9307 11:59:28.688316 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 11:59:28.695061 anx7625_parse_edid: pixelclock(138800).
9309 11:59:28.698097 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 11:59:28.701810 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 11:59:28.704838 anx7625_dsi_config: config dsi.
9312 11:59:28.711488 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 11:59:28.724506 anx7625_dsi_config: success to config DSI
9314 11:59:28.728210 anx7625_dp_start: MIPI phy setup OK.
9315 11:59:28.731210 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 11:59:28.734465 mtk_ddp_mode_set invalid vrefresh 60
9317 11:59:28.738240 main_disp_path_setup
9318 11:59:28.738321 ovl_layer_smi_id_en
9319 11:59:28.741106 ovl_layer_smi_id_en
9320 11:59:28.741185 ccorr_config
9321 11:59:28.741248 aal_config
9322 11:59:28.744282 gamma_config
9323 11:59:28.744363 postmask_config
9324 11:59:28.747562 dither_config
9325 11:59:28.751193 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 11:59:28.757811 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 11:59:28.761408 Root Device init finished in 551 msecs
9328 11:59:28.761516 CPU_CLUSTER: 0 init
9329 11:59:28.770701 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 11:59:28.774030 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 11:59:28.777499 APU_MBOX 0x190000b0 = 0x10001
9332 11:59:28.781121 APU_MBOX 0x190001b0 = 0x10001
9333 11:59:28.784146 APU_MBOX 0x190005b0 = 0x10001
9334 11:59:28.787874 APU_MBOX 0x190006b0 = 0x10001
9335 11:59:28.791039 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 11:59:28.803718 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9337 11:59:28.815514 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 11:59:28.822544 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 11:59:28.834447 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9340 11:59:28.842897 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 11:59:28.846927 CPU_CLUSTER: 0 init finished in 81 msecs
9342 11:59:28.849741 Devices initialized
9343 11:59:28.853541 Show all devs... After init.
9344 11:59:28.853689 Root Device: enabled 1
9345 11:59:28.856694 CPU_CLUSTER: 0: enabled 1
9346 11:59:28.860181 CPU: 00: enabled 1
9347 11:59:28.863159 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9348 11:59:28.866326 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 11:59:28.869840 ELOG: NV offset 0x57f000 size 0x1000
9350 11:59:28.876228 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9351 11:59:28.882804 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 11:59:28.886320 ELOG: Event(17) added with size 13 at 2023-11-23 11:57:17 UTC
9353 11:59:28.889796 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 11:59:28.893762 in-header: 03 e6 00 00 2c 00 00 00
9355 11:59:28.906838 in-data: 79 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 11:59:28.913080 ELOG: Event(A1) added with size 10 at 2023-11-23 11:57:17 UTC
9357 11:59:28.920007 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9358 11:59:28.926460 ELOG: Event(A0) added with size 9 at 2023-11-23 11:57:17 UTC
9359 11:59:28.930077 elog_add_boot_reason: Logged dev mode boot
9360 11:59:28.933831 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 11:59:28.936623 Finalize devices...
9362 11:59:28.936698 Devices finalized
9363 11:59:28.943356 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 11:59:28.946870 Writing coreboot table at 0xffe64000
9365 11:59:28.949742 0. 000000000010a000-0000000000113fff: RAMSTAGE
9366 11:59:28.953514 1. 0000000040000000-00000000400fffff: RAM
9367 11:59:28.956351 2. 0000000040100000-000000004032afff: RAMSTAGE
9368 11:59:28.963504 3. 000000004032b000-00000000545fffff: RAM
9369 11:59:28.966461 4. 0000000054600000-000000005465ffff: BL31
9370 11:59:28.969689 5. 0000000054660000-00000000ffe63fff: RAM
9371 11:59:28.976212 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9372 11:59:28.980049 7. 0000000100000000-000000023fffffff: RAM
9373 11:59:28.980131 Passing 5 GPIOs to payload:
9374 11:59:28.986754 NAME | PORT | POLARITY | VALUE
9375 11:59:28.990180 EC in RW | 0x000000aa | low | undefined
9376 11:59:28.996843 EC interrupt | 0x00000005 | low | undefined
9377 11:59:29.000472 TPM interrupt | 0x000000ab | high | undefined
9378 11:59:29.003824 SD card detect | 0x00000011 | high | undefined
9379 11:59:29.010288 speaker enable | 0x00000093 | high | undefined
9380 11:59:29.013619 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9381 11:59:29.017004 in-header: 03 f9 00 00 02 00 00 00
9382 11:59:29.017814 in-data: 02 00
9383 11:59:29.020290 ADC[4]: Raw value=905096 ID=7
9384 11:59:29.023643 ADC[3]: Raw value=213441 ID=1
9385 11:59:29.024193 RAM Code: 0x71
9386 11:59:29.026459 ADC[6]: Raw value=75701 ID=0
9387 11:59:29.030456 ADC[5]: Raw value=212703 ID=1
9388 11:59:29.031007 SKU Code: 0x1
9389 11:59:29.036380 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b2c3
9390 11:59:29.040105 coreboot table: 964 bytes.
9391 11:59:29.043064 IMD ROOT 0. 0xfffff000 0x00001000
9392 11:59:29.047057 IMD SMALL 1. 0xffffe000 0x00001000
9393 11:59:29.049713 RO MCACHE 2. 0xffffc000 0x00001104
9394 11:59:29.053561 CONSOLE 3. 0xfff7c000 0x00080000
9395 11:59:29.056819 FMAP 4. 0xfff7b000 0x00000452
9396 11:59:29.059633 TIME STAMP 5. 0xfff7a000 0x00000910
9397 11:59:29.063238 VBOOT WORK 6. 0xfff66000 0x00014000
9398 11:59:29.066432 RAMOOPS 7. 0xffe66000 0x00100000
9399 11:59:29.069557 COREBOOT 8. 0xffe64000 0x00002000
9400 11:59:29.070058 IMD small region:
9401 11:59:29.073079 IMD ROOT 0. 0xffffec00 0x00000400
9402 11:59:29.076075 VPD 1. 0xffffeb80 0x0000006c
9403 11:59:29.079753 MMC STATUS 2. 0xffffeb60 0x00000004
9404 11:59:29.086328 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9405 11:59:29.089865 Probing TPM: done!
9406 11:59:29.092931 Connected to device vid:did:rid of 1ae0:0028:00
9407 11:59:29.103148 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9408 11:59:29.106554 Initialized TPM device CR50 revision 0
9409 11:59:29.110268 Checking cr50 for pending updates
9410 11:59:29.113759 Reading cr50 TPM mode
9411 11:59:29.122239 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9412 11:59:29.128821 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9413 11:59:29.168880 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9414 11:59:29.171860 Checking segment from ROM address 0x40100000
9415 11:59:29.175384 Checking segment from ROM address 0x4010001c
9416 11:59:29.182150 Loading segment from ROM address 0x40100000
9417 11:59:29.182869 code (compression=0)
9418 11:59:29.192195 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9419 11:59:29.198721 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9420 11:59:29.199323 it's not compressed!
9421 11:59:29.205297 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9422 11:59:29.208483 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9423 11:59:29.228905 Loading segment from ROM address 0x4010001c
9424 11:59:29.229472 Entry Point 0x80000000
9425 11:59:29.231887 Loaded segments
9426 11:59:29.235052 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9427 11:59:29.242151 Jumping to boot code at 0x80000000(0xffe64000)
9428 11:59:29.248473 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9429 11:59:29.255373 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9430 11:59:29.263193 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9431 11:59:29.266593 Checking segment from ROM address 0x40100000
9432 11:59:29.269856 Checking segment from ROM address 0x4010001c
9433 11:59:29.276908 Loading segment from ROM address 0x40100000
9434 11:59:29.277007 code (compression=1)
9435 11:59:29.283088 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9436 11:59:29.293215 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9437 11:59:29.293362 using LZMA
9438 11:59:29.302094 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9439 11:59:29.308569 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9440 11:59:29.311424 Loading segment from ROM address 0x4010001c
9441 11:59:29.311713 Entry Point 0x54601000
9442 11:59:29.315224 Loaded segments
9443 11:59:29.318261 NOTICE: MT8192 bl31_setup
9444 11:59:29.325338 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9445 11:59:29.328566 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9446 11:59:29.332027 WARNING: region 0:
9447 11:59:29.335348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 11:59:29.335672 WARNING: region 1:
9449 11:59:29.342203 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9450 11:59:29.345225 WARNING: region 2:
9451 11:59:29.348932 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9452 11:59:29.352284 WARNING: region 3:
9453 11:59:29.355266 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 11:59:29.358659 WARNING: region 4:
9455 11:59:29.365391 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 11:59:29.365474 WARNING: region 5:
9457 11:59:29.368096 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 11:59:29.372004 WARNING: region 6:
9459 11:59:29.375076 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 11:59:29.375156 WARNING: region 7:
9461 11:59:29.381881 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 11:59:29.388241 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9463 11:59:29.391854 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9464 11:59:29.395084 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9465 11:59:29.401507 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9466 11:59:29.405049 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9467 11:59:29.408454 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9468 11:59:29.415106 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9469 11:59:29.418483 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9470 11:59:29.425882 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9471 11:59:29.428720 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9472 11:59:29.432278 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9473 11:59:29.438426 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9474 11:59:29.442412 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9475 11:59:29.445517 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9476 11:59:29.452173 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9477 11:59:29.455106 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9478 11:59:29.458920 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9479 11:59:29.465242 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9480 11:59:29.468913 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9481 11:59:29.475405 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9482 11:59:29.478759 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9483 11:59:29.482186 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9484 11:59:29.489226 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9485 11:59:29.492314 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9486 11:59:29.496076 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9487 11:59:29.502637 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9488 11:59:29.505760 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9489 11:59:29.512776 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9490 11:59:29.516486 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9491 11:59:29.519393 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9492 11:59:29.526729 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9493 11:59:29.529561 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9494 11:59:29.532652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9495 11:59:29.539252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9496 11:59:29.542682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9497 11:59:29.546191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9498 11:59:29.549142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9499 11:59:29.556108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9500 11:59:29.560146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9501 11:59:29.562881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9502 11:59:29.565896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9503 11:59:29.572784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9504 11:59:29.576567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9505 11:59:29.580048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9506 11:59:29.582972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9507 11:59:29.589383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9508 11:59:29.593336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9509 11:59:29.596566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9510 11:59:29.602940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9511 11:59:29.606014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9512 11:59:29.609458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9513 11:59:29.616256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9514 11:59:29.619331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9515 11:59:29.626112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9516 11:59:29.629501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9517 11:59:29.633141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9518 11:59:29.639149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9519 11:59:29.643053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9520 11:59:29.650178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9521 11:59:29.652676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9522 11:59:29.659193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9523 11:59:29.662770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9524 11:59:29.669487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9525 11:59:29.672478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9526 11:59:29.676562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9527 11:59:29.682585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9528 11:59:29.685922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9529 11:59:29.692675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9530 11:59:29.696152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9531 11:59:29.702740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9532 11:59:29.705934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9533 11:59:29.708901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9534 11:59:29.715786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9535 11:59:29.719360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9536 11:59:29.725673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9537 11:59:29.729028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9538 11:59:29.735471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9539 11:59:29.739105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9540 11:59:29.745641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9541 11:59:29.749041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9542 11:59:29.752885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9543 11:59:29.758945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9544 11:59:29.762515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9545 11:59:29.769157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9546 11:59:29.772352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9547 11:59:29.779027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9548 11:59:29.782789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9549 11:59:29.785708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9550 11:59:29.792200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9551 11:59:29.795954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9552 11:59:29.803061 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9553 11:59:29.806113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9554 11:59:29.812900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9555 11:59:29.815976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9556 11:59:29.819137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9557 11:59:29.825837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9558 11:59:29.829684 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9559 11:59:29.832965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9560 11:59:29.839179 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9561 11:59:29.843128 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9562 11:59:29.846377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9563 11:59:29.849244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9564 11:59:29.855935 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9565 11:59:29.859461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9566 11:59:29.865890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9567 11:59:29.869427 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9568 11:59:29.872942 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9569 11:59:29.879333 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9570 11:59:29.882507 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9571 11:59:29.889219 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9572 11:59:29.892798 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9573 11:59:29.896258 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9574 11:59:29.902873 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9575 11:59:29.906110 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9576 11:59:29.912535 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9577 11:59:29.916676 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9578 11:59:29.919725 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9579 11:59:29.926185 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9580 11:59:29.930143 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9581 11:59:29.933059 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9582 11:59:29.936516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9583 11:59:29.943384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9584 11:59:29.946384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9585 11:59:29.949650 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9586 11:59:29.953410 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9587 11:59:29.959687 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9588 11:59:29.962937 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9589 11:59:29.969867 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9590 11:59:29.972610 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9591 11:59:29.976632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9592 11:59:29.983331 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9593 11:59:29.986254 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9594 11:59:29.992396 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9595 11:59:29.995910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9596 11:59:29.999249 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9597 11:59:30.006070 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9598 11:59:30.009398 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9599 11:59:30.012678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9600 11:59:30.019817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9601 11:59:30.022654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9602 11:59:30.029697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9603 11:59:30.032780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9604 11:59:30.036492 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9605 11:59:30.043011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9606 11:59:30.046365 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9607 11:59:30.052699 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9608 11:59:30.056260 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9609 11:59:30.059347 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9610 11:59:30.066301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9611 11:59:30.069356 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9612 11:59:30.073564 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9613 11:59:30.079741 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9614 11:59:30.083046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9615 11:59:30.090024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9616 11:59:30.092937 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9617 11:59:30.096232 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9618 11:59:30.103046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9619 11:59:30.107091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9620 11:59:30.109488 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9621 11:59:30.116220 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9622 11:59:30.119245 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9623 11:59:30.126085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9624 11:59:30.129648 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9625 11:59:30.132857 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9626 11:59:30.139722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9627 11:59:30.142834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9628 11:59:30.149319 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9629 11:59:30.152549 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9630 11:59:30.155885 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9631 11:59:30.162981 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9632 11:59:30.166350 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9633 11:59:30.172666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9634 11:59:30.176322 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9635 11:59:30.179245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9636 11:59:30.185960 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9637 11:59:30.188996 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9638 11:59:30.195748 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9639 11:59:30.198647 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9640 11:59:30.202058 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9641 11:59:30.208999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9642 11:59:30.212526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9643 11:59:30.218965 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9644 11:59:30.221862 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9645 11:59:30.225520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9646 11:59:30.232104 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9647 11:59:30.235541 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9648 11:59:30.238677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9649 11:59:30.244990 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9650 11:59:30.248457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9651 11:59:30.255321 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9652 11:59:30.258552 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9653 11:59:30.265252 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9654 11:59:30.268360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9655 11:59:30.271620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9656 11:59:30.278844 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9657 11:59:30.281885 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9658 11:59:30.288573 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9659 11:59:30.292522 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9660 11:59:30.295791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9661 11:59:30.301838 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9662 11:59:30.305561 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9663 11:59:30.312352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9664 11:59:30.315508 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9665 11:59:30.322026 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9666 11:59:30.325066 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9667 11:59:30.328803 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9668 11:59:30.334877 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9669 11:59:30.338497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9670 11:59:30.344672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9671 11:59:30.348161 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9672 11:59:30.354940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9673 11:59:30.358235 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9674 11:59:30.361252 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9675 11:59:30.367861 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9676 11:59:30.371274 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9677 11:59:30.377876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9678 11:59:30.381373 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9679 11:59:30.384610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9680 11:59:30.391651 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9681 11:59:30.394513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9682 11:59:30.401518 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9683 11:59:30.404530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9684 11:59:30.411706 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9685 11:59:30.414421 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9686 11:59:30.418408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9687 11:59:30.424498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9688 11:59:30.428043 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9689 11:59:30.434737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9690 11:59:30.438229 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9691 11:59:30.441226 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9692 11:59:30.444596 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9693 11:59:30.451250 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9694 11:59:30.455016 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9695 11:59:30.457708 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9696 11:59:30.461213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9697 11:59:30.467811 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9698 11:59:30.471635 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9699 11:59:30.477747 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9700 11:59:30.481243 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9701 11:59:30.484389 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9702 11:59:30.490868 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9703 11:59:30.494385 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9704 11:59:30.500973 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9705 11:59:30.504412 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9706 11:59:30.507626 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9707 11:59:30.514491 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9708 11:59:30.518009 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9709 11:59:30.521090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9710 11:59:30.527790 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9711 11:59:30.531293 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9712 11:59:30.534315 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9713 11:59:30.540475 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9714 11:59:30.543637 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9715 11:59:30.547166 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9716 11:59:30.553915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9717 11:59:30.557485 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9718 11:59:30.563594 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9719 11:59:30.567053 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9720 11:59:30.570720 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9721 11:59:30.577272 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9722 11:59:30.580326 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9723 11:59:30.583867 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9724 11:59:30.590577 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9725 11:59:30.593573 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9726 11:59:30.597181 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9727 11:59:30.603852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9728 11:59:30.607246 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9729 11:59:30.614330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9730 11:59:30.617158 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9731 11:59:30.620281 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9732 11:59:30.623990 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9733 11:59:30.626947 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9734 11:59:30.633702 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9735 11:59:30.637085 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9736 11:59:30.640245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9737 11:59:30.644023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9738 11:59:30.650349 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9739 11:59:30.654017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9740 11:59:30.657073 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9741 11:59:30.660230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9742 11:59:30.666896 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9743 11:59:30.670463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9744 11:59:30.674060 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9745 11:59:30.680547 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9746 11:59:30.683943 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9747 11:59:30.690694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9748 11:59:30.693666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9749 11:59:30.700242 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9750 11:59:30.703639 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9751 11:59:30.707038 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9752 11:59:30.714000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9753 11:59:30.717131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9754 11:59:30.723828 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9755 11:59:30.726920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9756 11:59:30.730658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9757 11:59:30.737397 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9758 11:59:30.740781 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9759 11:59:30.747223 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9760 11:59:30.750376 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9761 11:59:30.754023 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9762 11:59:30.760224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9763 11:59:30.763691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9764 11:59:30.770121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9765 11:59:30.773624 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9766 11:59:30.780065 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9767 11:59:30.783288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9768 11:59:30.786916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9769 11:59:30.793475 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9770 11:59:30.797028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9771 11:59:30.803599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9772 11:59:30.806874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9773 11:59:30.810400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9774 11:59:30.816964 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9775 11:59:30.820112 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9776 11:59:30.826653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9777 11:59:30.830561 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9778 11:59:30.833414 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9779 11:59:30.840060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9780 11:59:30.844200 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9781 11:59:30.850076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9782 11:59:30.853467 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9783 11:59:30.857011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9784 11:59:30.863387 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9785 11:59:30.867223 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9786 11:59:30.873637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9787 11:59:30.876698 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9788 11:59:30.879930 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9789 11:59:30.886611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9790 11:59:30.889941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9791 11:59:30.896530 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9792 11:59:30.899671 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9793 11:59:30.903533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9794 11:59:30.910127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9795 11:59:30.912853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9796 11:59:30.920318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9797 11:59:30.923224 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9798 11:59:30.929560 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9799 11:59:30.933120 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9800 11:59:30.936394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9801 11:59:30.942839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9802 11:59:30.945839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9803 11:59:30.952932 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9804 11:59:30.956223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9805 11:59:30.959800 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9806 11:59:30.965980 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9807 11:59:30.969688 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9808 11:59:30.976174 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9809 11:59:30.979675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9810 11:59:30.982879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9811 11:59:30.989913 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9812 11:59:30.992688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9813 11:59:30.999436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9814 11:59:31.002576 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9815 11:59:31.005966 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9816 11:59:31.012638 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9817 11:59:31.015715 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9818 11:59:31.022546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9819 11:59:31.025992 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9820 11:59:31.032476 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9821 11:59:31.035830 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9822 11:59:31.042335 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9823 11:59:31.045765 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9824 11:59:31.049195 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9825 11:59:31.056463 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9826 11:59:31.059167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9827 11:59:31.066229 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9828 11:59:31.069180 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9829 11:59:31.075332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9830 11:59:31.078939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9831 11:59:31.082574 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9832 11:59:31.089020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9833 11:59:31.093045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9834 11:59:31.099446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9835 11:59:31.102222 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9836 11:59:31.106156 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9837 11:59:31.112395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9838 11:59:31.115995 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9839 11:59:31.122470 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9840 11:59:31.125918 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9841 11:59:31.132281 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9842 11:59:31.135846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9843 11:59:31.139270 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9844 11:59:31.145540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9845 11:59:31.149168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9846 11:59:31.155460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9847 11:59:31.159121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9848 11:59:31.165397 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9849 11:59:31.168671 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9850 11:59:31.175941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9851 11:59:31.178629 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9852 11:59:31.182134 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9853 11:59:31.188591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9854 11:59:31.191825 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9855 11:59:31.198891 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9856 11:59:31.202008 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9857 11:59:31.208897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9858 11:59:31.211963 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9859 11:59:31.215208 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9860 11:59:31.222005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9861 11:59:31.225102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9862 11:59:31.231661 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9863 11:59:31.234787 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9864 11:59:31.241735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9865 11:59:31.244659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9866 11:59:31.248269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9867 11:59:31.255087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9868 11:59:31.258375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9869 11:59:31.264641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9870 11:59:31.267986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9871 11:59:31.274401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9872 11:59:31.278362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9873 11:59:31.284680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9874 11:59:31.288672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9875 11:59:31.295485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9876 11:59:31.298142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9877 11:59:31.305263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9878 11:59:31.308454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9879 11:59:31.314903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9880 11:59:31.318102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9881 11:59:31.324594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9882 11:59:31.328656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9883 11:59:31.334495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9884 11:59:31.337515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9885 11:59:31.344290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9886 11:59:31.348232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9887 11:59:31.354449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9888 11:59:31.357512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9889 11:59:31.364611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9890 11:59:31.368014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9891 11:59:31.374479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9892 11:59:31.377965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9893 11:59:31.384498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9894 11:59:31.387625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9895 11:59:31.394285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9896 11:59:31.397603 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9897 11:59:31.397711 INFO: [APUAPC] vio 0
9898 11:59:31.405250 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9899 11:59:31.408361 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9900 11:59:31.411414 INFO: [APUAPC] D0_APC_0: 0x400510
9901 11:59:31.415196 INFO: [APUAPC] D0_APC_1: 0x0
9902 11:59:31.418602 INFO: [APUAPC] D0_APC_2: 0x1540
9903 11:59:31.421458 INFO: [APUAPC] D0_APC_3: 0x0
9904 11:59:31.424802 INFO: [APUAPC] D1_APC_0: 0xffffffff
9905 11:59:31.428451 INFO: [APUAPC] D1_APC_1: 0xffffffff
9906 11:59:31.431526 INFO: [APUAPC] D1_APC_2: 0x3fffff
9907 11:59:31.435409 INFO: [APUAPC] D1_APC_3: 0x0
9908 11:59:31.438903 INFO: [APUAPC] D2_APC_0: 0xffffffff
9909 11:59:31.441535 INFO: [APUAPC] D2_APC_1: 0xffffffff
9910 11:59:31.445140 INFO: [APUAPC] D2_APC_2: 0x3fffff
9911 11:59:31.448483 INFO: [APUAPC] D2_APC_3: 0x0
9912 11:59:31.451321 INFO: [APUAPC] D3_APC_0: 0xffffffff
9913 11:59:31.455214 INFO: [APUAPC] D3_APC_1: 0xffffffff
9914 11:59:31.458379 INFO: [APUAPC] D3_APC_2: 0x3fffff
9915 11:59:31.458490 INFO: [APUAPC] D3_APC_3: 0x0
9916 11:59:31.464840 INFO: [APUAPC] D4_APC_0: 0xffffffff
9917 11:59:31.468164 INFO: [APUAPC] D4_APC_1: 0xffffffff
9918 11:59:31.471686 INFO: [APUAPC] D4_APC_2: 0x3fffff
9919 11:59:31.471840 INFO: [APUAPC] D4_APC_3: 0x0
9920 11:59:31.475294 INFO: [APUAPC] D5_APC_0: 0xffffffff
9921 11:59:31.478217 INFO: [APUAPC] D5_APC_1: 0xffffffff
9922 11:59:31.481866 INFO: [APUAPC] D5_APC_2: 0x3fffff
9923 11:59:31.484876 INFO: [APUAPC] D5_APC_3: 0x0
9924 11:59:31.488483 INFO: [APUAPC] D6_APC_0: 0xffffffff
9925 11:59:31.491945 INFO: [APUAPC] D6_APC_1: 0xffffffff
9926 11:59:31.494883 INFO: [APUAPC] D6_APC_2: 0x3fffff
9927 11:59:31.498372 INFO: [APUAPC] D6_APC_3: 0x0
9928 11:59:31.501511 INFO: [APUAPC] D7_APC_0: 0xffffffff
9929 11:59:31.505005 INFO: [APUAPC] D7_APC_1: 0xffffffff
9930 11:59:31.508349 INFO: [APUAPC] D7_APC_2: 0x3fffff
9931 11:59:31.511523 INFO: [APUAPC] D7_APC_3: 0x0
9932 11:59:31.515059 INFO: [APUAPC] D8_APC_0: 0xffffffff
9933 11:59:31.518112 INFO: [APUAPC] D8_APC_1: 0xffffffff
9934 11:59:31.521715 INFO: [APUAPC] D8_APC_2: 0x3fffff
9935 11:59:31.525359 INFO: [APUAPC] D8_APC_3: 0x0
9936 11:59:31.528186 INFO: [APUAPC] D9_APC_0: 0xffffffff
9937 11:59:31.531276 INFO: [APUAPC] D9_APC_1: 0xffffffff
9938 11:59:31.535018 INFO: [APUAPC] D9_APC_2: 0x3fffff
9939 11:59:31.538174 INFO: [APUAPC] D9_APC_3: 0x0
9940 11:59:31.541930 INFO: [APUAPC] D10_APC_0: 0xffffffff
9941 11:59:31.545118 INFO: [APUAPC] D10_APC_1: 0xffffffff
9942 11:59:31.548017 INFO: [APUAPC] D10_APC_2: 0x3fffff
9943 11:59:31.551738 INFO: [APUAPC] D10_APC_3: 0x0
9944 11:59:31.555203 INFO: [APUAPC] D11_APC_0: 0xffffffff
9945 11:59:31.558289 INFO: [APUAPC] D11_APC_1: 0xffffffff
9946 11:59:31.561399 INFO: [APUAPC] D11_APC_2: 0x3fffff
9947 11:59:31.565260 INFO: [APUAPC] D11_APC_3: 0x0
9948 11:59:31.568162 INFO: [APUAPC] D12_APC_0: 0xffffffff
9949 11:59:31.571847 INFO: [APUAPC] D12_APC_1: 0xffffffff
9950 11:59:31.574870 INFO: [APUAPC] D12_APC_2: 0x3fffff
9951 11:59:31.578185 INFO: [APUAPC] D12_APC_3: 0x0
9952 11:59:31.581630 INFO: [APUAPC] D13_APC_0: 0xffffffff
9953 11:59:31.585219 INFO: [APUAPC] D13_APC_1: 0xffffffff
9954 11:59:31.588287 INFO: [APUAPC] D13_APC_2: 0x3fffff
9955 11:59:31.591764 INFO: [APUAPC] D13_APC_3: 0x0
9956 11:59:31.595185 INFO: [APUAPC] D14_APC_0: 0xffffffff
9957 11:59:31.598519 INFO: [APUAPC] D14_APC_1: 0xffffffff
9958 11:59:31.601340 INFO: [APUAPC] D14_APC_2: 0x3fffff
9959 11:59:31.605142 INFO: [APUAPC] D14_APC_3: 0x0
9960 11:59:31.608223 INFO: [APUAPC] D15_APC_0: 0xffffffff
9961 11:59:31.611532 INFO: [APUAPC] D15_APC_1: 0xffffffff
9962 11:59:31.615151 INFO: [APUAPC] D15_APC_2: 0x3fffff
9963 11:59:31.618074 INFO: [APUAPC] D15_APC_3: 0x0
9964 11:59:31.621445 INFO: [APUAPC] APC_CON: 0x4
9965 11:59:31.624720 INFO: [NOCDAPC] D0_APC_0: 0x0
9966 11:59:31.628497 INFO: [NOCDAPC] D0_APC_1: 0x0
9967 11:59:31.628817 INFO: [NOCDAPC] D1_APC_0: 0x0
9968 11:59:31.631656 INFO: [NOCDAPC] D1_APC_1: 0xfff
9969 11:59:31.634697 INFO: [NOCDAPC] D2_APC_0: 0x0
9970 11:59:31.638214 INFO: [NOCDAPC] D2_APC_1: 0xfff
9971 11:59:31.641495 INFO: [NOCDAPC] D3_APC_0: 0x0
9972 11:59:31.645293 INFO: [NOCDAPC] D3_APC_1: 0xfff
9973 11:59:31.648640 INFO: [NOCDAPC] D4_APC_0: 0x0
9974 11:59:31.651755 INFO: [NOCDAPC] D4_APC_1: 0xfff
9975 11:59:31.655302 INFO: [NOCDAPC] D5_APC_0: 0x0
9976 11:59:31.658675 INFO: [NOCDAPC] D5_APC_1: 0xfff
9977 11:59:31.658915 INFO: [NOCDAPC] D6_APC_0: 0x0
9978 11:59:31.661408 INFO: [NOCDAPC] D6_APC_1: 0xfff
9979 11:59:31.664846 INFO: [NOCDAPC] D7_APC_0: 0x0
9980 11:59:31.668379 INFO: [NOCDAPC] D7_APC_1: 0xfff
9981 11:59:31.671388 INFO: [NOCDAPC] D8_APC_0: 0x0
9982 11:59:31.674801 INFO: [NOCDAPC] D8_APC_1: 0xfff
9983 11:59:31.677976 INFO: [NOCDAPC] D9_APC_0: 0x0
9984 11:59:31.681166 INFO: [NOCDAPC] D9_APC_1: 0xfff
9985 11:59:31.684862 INFO: [NOCDAPC] D10_APC_0: 0x0
9986 11:59:31.688291 INFO: [NOCDAPC] D10_APC_1: 0xfff
9987 11:59:31.691301 INFO: [NOCDAPC] D11_APC_0: 0x0
9988 11:59:31.694662 INFO: [NOCDAPC] D11_APC_1: 0xfff
9989 11:59:31.694980 INFO: [NOCDAPC] D12_APC_0: 0x0
9990 11:59:31.698231 INFO: [NOCDAPC] D12_APC_1: 0xfff
9991 11:59:31.701612 INFO: [NOCDAPC] D13_APC_0: 0x0
9992 11:59:31.704682 INFO: [NOCDAPC] D13_APC_1: 0xfff
9993 11:59:31.708220 INFO: [NOCDAPC] D14_APC_0: 0x0
9994 11:59:31.711654 INFO: [NOCDAPC] D14_APC_1: 0xfff
9995 11:59:31.715001 INFO: [NOCDAPC] D15_APC_0: 0x0
9996 11:59:31.718220 INFO: [NOCDAPC] D15_APC_1: 0xfff
9997 11:59:31.722337 INFO: [NOCDAPC] APC_CON: 0x4
9998 11:59:31.725356 INFO: [APUAPC] set_apusys_apc done
9999 11:59:31.728138 INFO: [DEVAPC] devapc_init done
10000 11:59:31.731864 INFO: GICv3 without legacy support detected.
10001 11:59:31.735210 INFO: ARM GICv3 driver initialized in EL3
10002 11:59:31.738652 INFO: Maximum SPI INTID supported: 639
10003 11:59:31.745718 INFO: BL31: Initializing runtime services
10004 11:59:31.748512 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10005 11:59:31.751463 INFO: SPM: enable CPC mode
10006 11:59:31.758387 INFO: mcdi ready for mcusys-off-idle and system suspend
10007 11:59:31.761645 INFO: BL31: Preparing for EL3 exit to normal world
10008 11:59:31.764792 INFO: Entry point address = 0x80000000
10009 11:59:31.767965 INFO: SPSR = 0x8
10010 11:59:31.773285
10011 11:59:31.773525
10012 11:59:31.773787
10013 11:59:31.776554 Starting depthcharge on Spherion...
10014 11:59:31.776778
10015 11:59:31.776996 Wipe memory regions:
10016 11:59:31.777167
10017 11:59:31.778497 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10018 11:59:31.778766 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10019 11:59:31.779032 Setting prompt string to ['asurada:']
10020 11:59:31.779245 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10021 11:59:31.780094 [0x00000040000000, 0x00000054600000)
10022 11:59:31.902716
10023 11:59:31.903221 [0x00000054660000, 0x00000080000000)
10024 11:59:32.162911
10025 11:59:32.163097 [0x000000821a7280, 0x000000ffe64000)
10026 11:59:32.907332
10027 11:59:32.907463 [0x00000100000000, 0x00000240000000)
10028 11:59:34.798542
10029 11:59:34.801629 Initializing XHCI USB controller at 0x11200000.
10030 11:59:35.839460
10031 11:59:35.842079 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10032 11:59:35.842185
10033 11:59:35.842250
10034 11:59:35.842318
10035 11:59:35.842611 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 11:59:35.943106 asurada: tftpboot 192.168.201.1 12066560/tftp-deploy-3c0cps04/kernel/image.itb 12066560/tftp-deploy-3c0cps04/kernel/cmdline
10038 11:59:35.943323 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 11:59:35.943473 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10040 11:59:35.947616 tftpboot 192.168.201.1 12066560/tftp-deploy-3c0cps04/kernel/image.itp-deploy-3c0cps04/kernel/cmdline
10041 11:59:35.947818
10042 11:59:35.947931 Waiting for link
10043 11:59:36.108229
10044 11:59:36.108383 R8152: Initializing
10045 11:59:36.108448
10046 11:59:36.111364 Version 9 (ocp_data = 6010)
10047 11:59:36.111445
10048 11:59:36.114415 R8152: Done initializing
10049 11:59:36.114497
10050 11:59:36.114561 Adding net device
10051 11:59:38.061145
10052 11:59:38.061697 done.
10053 11:59:38.062095
10054 11:59:38.062420 MAC: 00:e0:4c:78:7a:aa
10055 11:59:38.062813
10056 11:59:38.064159 Sending DHCP discover... done.
10057 11:59:38.064580
10058 11:59:38.067147 Waiting for reply... done.
10059 11:59:38.067685
10060 11:59:38.070884 Sending DHCP request... done.
10061 11:59:38.071305
10062 11:59:38.076973 Waiting for reply... done.
10063 11:59:38.077395
10064 11:59:38.077791 My ip is 192.168.201.12
10065 11:59:38.078112
10066 11:59:38.080645 The DHCP server ip is 192.168.201.1
10067 11:59:38.081065
10068 11:59:38.086874 TFTP server IP predefined by user: 192.168.201.1
10069 11:59:38.087298
10070 11:59:38.093695 Bootfile predefined by user: 12066560/tftp-deploy-3c0cps04/kernel/image.itb
10071 11:59:38.094168
10072 11:59:38.094503 Sending tftp read request... done.
10073 11:59:38.096761
10074 11:59:38.103153 Waiting for the transfer...
10075 11:59:38.103612
10076 11:59:38.458700 00000000 ################################################################
10077 11:59:38.458847
10078 11:59:38.708694 00080000 ################################################################
10079 11:59:38.708852
10080 11:59:38.958234 00100000 ################################################################
10081 11:59:38.958377
10082 11:59:39.210634 00180000 ################################################################
10083 11:59:39.210767
10084 11:59:39.477670 00200000 ################################################################
10085 11:59:39.477815
10086 11:59:39.735351 00280000 ################################################################
10087 11:59:39.735492
10088 11:59:39.986611 00300000 ################################################################
10089 11:59:39.986751
10090 11:59:40.243714 00380000 ################################################################
10091 11:59:40.243869
10092 11:59:40.506986 00400000 ################################################################
10093 11:59:40.507147
10094 11:59:40.769779 00480000 ################################################################
10095 11:59:40.769912
10096 11:59:41.029448 00500000 ################################################################
10097 11:59:41.029585
10098 11:59:41.286711 00580000 ################################################################
10099 11:59:41.286848
10100 11:59:41.569804 00600000 ################################################################
10101 11:59:41.569947
10102 11:59:41.843813 00680000 ################################################################
10103 11:59:41.843972
10104 11:59:42.112173 00700000 ################################################################
10105 11:59:42.112310
10106 11:59:42.365615 00780000 ################################################################
10107 11:59:42.365765
10108 11:59:42.634798 00800000 ################################################################
10109 11:59:42.634942
10110 11:59:42.908209 00880000 ################################################################
10111 11:59:42.908371
10112 11:59:43.182827 00900000 ################################################################
10113 11:59:43.182997
10114 11:59:43.469453 00980000 ################################################################
10115 11:59:43.469623
10116 11:59:43.764270 00a00000 ################################################################
10117 11:59:43.764417
10118 11:59:44.113739 00a80000 ################################################################
10119 11:59:44.114233
10120 11:59:44.527413 00b00000 ################################################################
10121 11:59:44.527913
10122 11:59:44.955031 00b80000 ################################################################
10123 11:59:44.955523
10124 11:59:45.330061 00c00000 ################################################################
10125 11:59:45.330227
10126 11:59:45.631347 00c80000 ################################################################
10127 11:59:45.631489
10128 11:59:45.928231 00d00000 ################################################################
10129 11:59:45.928372
10130 11:59:46.230460 00d80000 ################################################################
10131 11:59:46.230599
10132 11:59:46.558730 00e00000 ################################################################
10133 11:59:46.558875
10134 11:59:46.840786 00e80000 ################################################################
10135 11:59:46.840931
10136 11:59:47.135010 00f00000 ################################################################
10137 11:59:47.135155
10138 11:59:47.528547 00f80000 ################################################################
10139 11:59:47.529068
10140 11:59:47.859539 01000000 ################################################################
10141 11:59:47.859696
10142 11:59:48.118683 01080000 ################################################################
10143 11:59:48.118814
10144 11:59:48.379072 01100000 ################################################################
10145 11:59:48.379201
10146 11:59:48.637133 01180000 ################################################################
10147 11:59:48.637289
10148 11:59:48.896299 01200000 ################################################################
10149 11:59:48.896465
10150 11:59:49.172372 01280000 ################################################################
10151 11:59:49.172530
10152 11:59:49.459113 01300000 ################################################################
10153 11:59:49.459255
10154 11:59:49.758231 01380000 ################################################################
10155 11:59:49.758369
10156 11:59:50.041432 01400000 ################################################################
10157 11:59:50.041604
10158 11:59:50.337097 01480000 ################################################################
10159 11:59:50.337234
10160 11:59:50.611393 01500000 ################################################################
10161 11:59:50.611559
10162 11:59:50.889882 01580000 ################################################################
10163 11:59:50.890064
10164 11:59:51.148431 01600000 ################################################################
10165 11:59:51.148569
10166 11:59:51.430846 01680000 ################################################################
10167 11:59:51.430987
10168 11:59:51.726780 01700000 ################################################################
10169 11:59:51.726929
10170 11:59:51.999847 01780000 ################################################################
10171 11:59:52.000017
10172 11:59:52.287555 01800000 ################################################################
10173 11:59:52.287695
10174 11:59:52.578616 01880000 ################################################################
10175 11:59:52.578740
10176 11:59:52.867592 01900000 ################################################################
10177 11:59:52.867743
10178 11:59:53.147998 01980000 ################################################################
10179 11:59:53.148157
10180 11:59:53.419049 01a00000 ################################################################
10181 11:59:53.419211
10182 11:59:53.680702 01a80000 ################################################################
10183 11:59:53.680836
10184 11:59:53.932105 01b00000 ################################################################
10185 11:59:53.932259
10186 11:59:54.187111 01b80000 ################################################################
10187 11:59:54.187245
10188 11:59:54.444911 01c00000 ################################################################
10189 11:59:54.445078
10190 11:59:54.698564 01c80000 ################################################################
10191 11:59:54.698730
10192 11:59:54.959261 01d00000 ################################################################
10193 11:59:54.959382
10194 11:59:55.229775 01d80000 ################################################################
10195 11:59:55.229905
10196 11:59:55.484085 01e00000 ################################################################
10197 11:59:55.484243
10198 11:59:55.732916 01e80000 ################################################################
10199 11:59:55.733081
10200 11:59:55.986472 01f00000 ################################################################
10201 11:59:55.986599
10202 11:59:56.237369 01f80000 ################################################################
10203 11:59:56.237523
10204 11:59:56.491714 02000000 ################################################################
10205 11:59:56.491879
10206 11:59:56.744283 02080000 ################################################################
10207 11:59:56.744437
10208 11:59:56.990549 02100000 ################################################################
10209 11:59:56.990688
10210 11:59:57.243653 02180000 ################################################################
10211 11:59:57.243814
10212 11:59:57.491370 02200000 ################################################################
10213 11:59:57.491498
10214 11:59:57.738902 02280000 ################################################################
10215 11:59:57.739062
10216 11:59:57.985971 02300000 ################################################################
10217 11:59:57.986110
10218 11:59:58.234362 02380000 ################################################################
10219 11:59:58.234533
10220 11:59:58.484844 02400000 ################################################################
10221 11:59:58.484979
10222 11:59:58.732262 02480000 ################################################################
10223 11:59:58.732401
10224 11:59:58.986728 02500000 ################################################################
10225 11:59:58.986862
10226 11:59:59.247823 02580000 ################################################################
10227 11:59:59.247951
10228 11:59:59.528157 02600000 ################################################################
10229 11:59:59.528315
10230 11:59:59.783348 02680000 ################################################################
10231 11:59:59.783478
10232 12:00:00.037099 02700000 ################################################################
10233 12:00:00.037229
10234 12:00:00.297055 02780000 ################################################################
10235 12:00:00.297188
10236 12:00:00.560330 02800000 ################################################################
10237 12:00:00.560488
10238 12:00:00.832223 02880000 ################################################################
10239 12:00:00.832353
10240 12:00:01.127649 02900000 ################################################################
10241 12:00:01.127780
10242 12:00:01.396277 02980000 ################################################################
10243 12:00:01.396438
10244 12:00:01.650603 02a00000 ################################################################
10245 12:00:01.650758
10246 12:00:01.911896 02a80000 ################################################################
10247 12:00:01.912028
10248 12:00:02.163452 02b00000 ################################################################
10249 12:00:02.163609
10250 12:00:02.426560 02b80000 ################################################################
10251 12:00:02.426697
10252 12:00:02.710492 02c00000 ################################################################
10253 12:00:02.710653
10254 12:00:02.981778 02c80000 ################################################################
10255 12:00:02.981902
10256 12:00:03.266263 02d00000 ################################################################
10257 12:00:03.266393
10258 12:00:03.542818 02d80000 ################################################################
10259 12:00:03.542946
10260 12:00:03.823269 02e00000 ################################################################
10261 12:00:03.823417
10262 12:00:04.092002 02e80000 ################################################################
10263 12:00:04.092151
10264 12:00:04.371045 02f00000 ################################################################
10265 12:00:04.371180
10266 12:00:04.642415 02f80000 ################################################################
10267 12:00:04.642559
10268 12:00:04.932670 03000000 ################################################################
10269 12:00:04.932817
10270 12:00:05.180841 03080000 ################################################################
10271 12:00:05.180987
10272 12:00:05.439138 03100000 ################################################################
10273 12:00:05.439270
10274 12:00:05.701038 03180000 ################################################################
10275 12:00:05.701198
10276 12:00:05.945230 03200000 ################################################################
10277 12:00:05.945365
10278 12:00:06.224394 03280000 ################################################################
10279 12:00:06.224530
10280 12:00:06.495390 03300000 ################################################################
10281 12:00:06.495529
10282 12:00:06.769922 03380000 ################################################################
10283 12:00:06.770081
10284 12:00:07.035164 03400000 ################################################################
10285 12:00:07.035334
10286 12:00:07.290348 03480000 ################################################################
10287 12:00:07.290485
10288 12:00:07.545448 03500000 ################################################################
10289 12:00:07.545606
10290 12:00:07.808730 03580000 ################################################################
10291 12:00:07.808879
10292 12:00:08.059457 03600000 ################################################################
10293 12:00:08.059615
10294 12:00:08.326688 03680000 ################################################################
10295 12:00:08.326845
10296 12:00:08.591756 03700000 ################################################################
10297 12:00:08.591889
10298 12:00:08.845454 03780000 ################################################################
10299 12:00:08.845622
10300 12:00:09.102376 03800000 ################################################################
10301 12:00:09.102526
10302 12:00:09.357746 03880000 ################################################################
10303 12:00:09.357877
10304 12:00:09.607385 03900000 ################################################################
10305 12:00:09.607517
10306 12:00:09.860349 03980000 ################################################################
10307 12:00:09.860506
10308 12:00:10.120532 03a00000 ################################################################
10309 12:00:10.120692
10310 12:00:10.373092 03a80000 ################################################################
10311 12:00:10.373232
10312 12:00:10.633095 03b00000 ################################################################
10313 12:00:10.633226
10314 12:00:10.904731 03b80000 ################################################################
10315 12:00:10.904865
10316 12:00:11.176233 03c00000 ################################################################
10317 12:00:11.176381
10318 12:00:11.431738 03c80000 ################################################################
10319 12:00:11.431900
10320 12:00:11.699587 03d00000 ################################################################
10321 12:00:11.699715
10322 12:00:11.946061 03d80000 ################################################################
10323 12:00:11.946192
10324 12:00:12.197955 03e00000 ################################################################
10325 12:00:12.198089
10326 12:00:12.447278 03e80000 ################################################################
10327 12:00:12.447413
10328 12:00:12.695648 03f00000 ################################################################
10329 12:00:12.695779
10330 12:00:12.954776 03f80000 ################################################################
10331 12:00:12.954938
10332 12:00:13.227433 04000000 ################################################################
10333 12:00:13.227564
10334 12:00:13.499187 04080000 ################################################################
10335 12:00:13.499343
10336 12:00:13.750185 04100000 ################################################################
10337 12:00:13.750323
10338 12:00:14.021532 04180000 ################################################################
10339 12:00:14.021741
10340 12:00:14.273107 04200000 ################################################################
10341 12:00:14.273265
10342 12:00:14.526331 04280000 ################################################################
10343 12:00:14.526489
10344 12:00:14.786286 04300000 ################################################################
10345 12:00:14.786427
10346 12:00:15.069091 04380000 ################################################################
10347 12:00:15.069242
10348 12:00:15.320690 04400000 ################################################################
10349 12:00:15.320851
10350 12:00:15.571812 04480000 ################################################################
10351 12:00:15.571977
10352 12:00:15.822463 04500000 ################################################################
10353 12:00:15.822598
10354 12:00:16.083926 04580000 ################################################################
10355 12:00:16.084075
10356 12:00:16.362934 04600000 ################################################################
10357 12:00:16.363060
10358 12:00:16.618757 04680000 ################################################################
10359 12:00:16.618884
10360 12:00:16.876492 04700000 ################################################################
10361 12:00:16.876648
10362 12:00:17.127189 04780000 ################################################################
10363 12:00:17.127318
10364 12:00:17.389707 04800000 ################################################################
10365 12:00:17.389839
10366 12:00:17.644189 04880000 ################################################################
10367 12:00:17.644345
10368 12:00:17.895772 04900000 ################################################################
10369 12:00:17.895903
10370 12:00:18.144911 04980000 ################################################################
10371 12:00:18.145038
10372 12:00:18.402704 04a00000 ################################################################
10373 12:00:18.402830
10374 12:00:18.654912 04a80000 ################################################################
10375 12:00:18.655040
10376 12:00:18.926660 04b00000 ################################################################
10377 12:00:18.926825
10378 12:00:19.178366 04b80000 ################################################################
10379 12:00:19.178504
10380 12:00:19.438553 04c00000 ################################################################
10381 12:00:19.438696
10382 12:00:19.688795 04c80000 ################################################################
10383 12:00:19.688924
10384 12:00:19.960719 04d00000 ################################################################
10385 12:00:19.960845
10386 12:00:20.239099 04d80000 ################################################################
10387 12:00:20.239226
10388 12:00:20.493345 04e00000 ################################################################
10389 12:00:20.493491
10390 12:00:20.746650 04e80000 ################################################################
10391 12:00:20.746813
10392 12:00:21.002585 04f00000 ################################################################
10393 12:00:21.002721
10394 12:00:21.264262 04f80000 ################################################################
10395 12:00:21.264419
10396 12:00:21.516119 05000000 ################################################################
10397 12:00:21.516260
10398 12:00:21.768852 05080000 ################################################################
10399 12:00:21.769010
10400 12:00:22.052097 05100000 ################################################################
10401 12:00:22.052255
10402 12:00:22.325878 05180000 ################################################################
10403 12:00:22.326017
10404 12:00:22.608827 05200000 ################################################################
10405 12:00:22.608958
10406 12:00:22.873986 05280000 ################################################################
10407 12:00:22.874256
10408 12:00:23.130605 05300000 ################################################################
10409 12:00:23.130777
10410 12:00:23.384246 05380000 ################################################################
10411 12:00:23.384370
10412 12:00:23.638249 05400000 ################################################################
10413 12:00:23.638376
10414 12:00:23.889520 05480000 ################################################################
10415 12:00:23.889685
10416 12:00:24.157851 05500000 ################################################################
10417 12:00:24.158007
10418 12:00:24.408407 05580000 ################################################################
10419 12:00:24.408541
10420 12:00:24.661278 05600000 ################################################################
10421 12:00:24.661410
10422 12:00:24.914082 05680000 ################################################################
10423 12:00:24.914219
10424 12:00:25.171955 05700000 ################################################################
10425 12:00:25.172161
10426 12:00:25.422155 05780000 ################################################################
10427 12:00:25.422281
10428 12:00:25.673297 05800000 ################################################################
10429 12:00:25.673456
10430 12:00:25.924766 05880000 ################################################################
10431 12:00:25.924926
10432 12:00:26.174283 05900000 ################################################################
10433 12:00:26.174416
10434 12:00:26.452037 05980000 ################################################################
10435 12:00:26.452172
10436 12:00:26.707385 05a00000 ################################################################
10437 12:00:26.707513
10438 12:00:26.967573 05a80000 ################################################################
10439 12:00:26.967728
10440 12:00:27.227201 05b00000 ################################################################
10441 12:00:27.227377
10442 12:00:27.482915 05b80000 ################################################################
10443 12:00:27.483075
10444 12:00:27.738160 05c00000 ################################################################
10445 12:00:27.738346
10446 12:00:27.987921 05c80000 ################################################################
10447 12:00:27.988054
10448 12:00:28.242651 05d00000 ################################################################
10449 12:00:28.242785
10450 12:00:28.493439 05d80000 ################################################################
10451 12:00:28.493570
10452 12:00:28.746947 05e00000 ################################################################
10453 12:00:28.747078
10454 12:00:28.998090 05e80000 ################################################################
10455 12:00:28.998222
10456 12:00:29.250037 05f00000 ################################################################
10457 12:00:29.250181
10458 12:00:29.505099 05f80000 ################################################################
10459 12:00:29.505238
10460 12:00:29.790098 06000000 ################################################################
10461 12:00:29.790224
10462 12:00:30.068111 06080000 ################################################################
10463 12:00:30.068268
10464 12:00:30.328904 06100000 ################################################################
10465 12:00:30.329035
10466 12:00:30.581999 06180000 ################################################################
10467 12:00:30.582142
10468 12:00:30.832055 06200000 ################################################################
10469 12:00:30.832197
10470 12:00:31.107938 06280000 ################################################################
10471 12:00:31.108095
10472 12:00:31.357640 06300000 ################################################################
10473 12:00:31.357804
10474 12:00:31.616376 06380000 ################################################################
10475 12:00:31.616531
10476 12:00:31.869824 06400000 ################################################################
10477 12:00:31.869961
10478 12:00:32.125846 06480000 ################################################################
10479 12:00:32.125976
10480 12:00:32.378631 06500000 ################################################################
10481 12:00:32.378762
10482 12:00:32.634893 06580000 ################################################################
10483 12:00:32.635062
10484 12:00:32.896764 06600000 ################################################################
10485 12:00:32.896902
10486 12:00:33.147670 06680000 ################################################################
10487 12:00:33.147803
10488 12:00:33.412367 06700000 ################################################################
10489 12:00:33.412523
10490 12:00:33.679167 06780000 ################################################################
10491 12:00:33.679296
10492 12:00:33.873168 06800000 ############################################### done.
10493 12:00:33.873302
10494 12:00:33.876356 The bootfile was 109430186 bytes long.
10495 12:00:33.876447
10496 12:00:33.879794 Sending tftp read request... done.
10497 12:00:33.879890
10498 12:00:33.882912 Waiting for the transfer...
10499 12:00:33.883084
10500 12:00:33.883170 00000000 # done.
10501 12:00:33.883251
10502 12:00:33.893255 Command line loaded dynamically from TFTP file: 12066560/tftp-deploy-3c0cps04/kernel/cmdline
10503 12:00:33.893443
10504 12:00:33.906210 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10505 12:00:33.906465
10506 12:00:33.906610 Loading FIT.
10507 12:00:33.906736
10508 12:00:33.909651 Image ramdisk-1 has 98333691 bytes.
10509 12:00:33.909916
10510 12:00:33.913082 Image fdt-1 has 47278 bytes.
10511 12:00:33.913346
10512 12:00:33.916266 Image kernel-1 has 11047184 bytes.
10513 12:00:33.916562
10514 12:00:33.923081 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10515 12:00:33.923427
10516 12:00:33.942978 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10517 12:00:33.943656
10518 12:00:33.945961 Choosing best match conf-1 for compat google,spherion-rev2.
10519 12:00:33.951271
10520 12:00:33.956024 Connected to device vid:did:rid of 1ae0:0028:00
10521 12:00:33.963948
10522 12:00:33.967222 tpm_get_response: command 0x17b, return code 0x0
10523 12:00:33.967639
10524 12:00:33.970854 ec_init: CrosEC protocol v3 supported (256, 248)
10525 12:00:33.975051
10526 12:00:33.978251 tpm_cleanup: add release locality here.
10527 12:00:33.978668
10528 12:00:33.978992 Shutting down all USB controllers.
10529 12:00:33.980995
10530 12:00:33.981536 Removing current net device
10531 12:00:33.981965
10532 12:00:33.987897 Exiting depthcharge with code 4 at timestamp: 91482143
10533 12:00:33.988410
10534 12:00:33.991478 LZMA decompressing kernel-1 to 0x821a6718
10535 12:00:33.991893
10536 12:00:33.994330 LZMA decompressing kernel-1 to 0x40000000
10537 12:00:35.383246
10538 12:00:35.383527 jumping to kernel
10539 12:00:35.384727 end: 2.2.4 bootloader-commands (duration 00:01:04) [common]
10540 12:00:35.384994 start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10541 12:00:35.385202 Setting prompt string to ['Linux version [0-9]']
10542 12:00:35.385383 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10543 12:00:35.385565 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10544 12:00:35.465411
10545 12:00:35.468587 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10546 12:00:35.472022 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10547 12:00:35.472280 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10548 12:00:35.472473 Setting prompt string to []
10549 12:00:35.472680 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10550 12:00:35.472872 Using line separator: #'\n'#
10551 12:00:35.473036 No login prompt set.
10552 12:00:35.473205 Parsing kernel messages
10553 12:00:35.473356 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10554 12:00:35.473662 [login-action] Waiting for messages, (timeout 00:03:22)
10555 12:00:35.491758 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10556 12:00:35.495212 [ 0.000000] random: crng init done
10557 12:00:35.501707 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10558 12:00:35.501930 [ 0.000000] efi: UEFI not found.
10559 12:00:35.512009 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10560 12:00:35.518352 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10561 12:00:35.528498 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10562 12:00:35.537958 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10563 12:00:35.544660 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10564 12:00:35.548173 [ 0.000000] printk: bootconsole [mtk8250] enabled
10565 12:00:35.556832 [ 0.000000] NUMA: No NUMA configuration found
10566 12:00:35.563223 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10567 12:00:35.569974 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10568 12:00:35.570058 [ 0.000000] Zone ranges:
10569 12:00:35.576706 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10570 12:00:35.580072 [ 0.000000] DMA32 empty
10571 12:00:35.586342 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10572 12:00:35.589615 [ 0.000000] Movable zone start for each node
10573 12:00:35.593292 [ 0.000000] Early memory node ranges
10574 12:00:35.599740 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10575 12:00:35.606663 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10576 12:00:35.613235 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10577 12:00:35.620230 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10578 12:00:35.626456 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10579 12:00:35.633352 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10580 12:00:35.689306 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10581 12:00:35.696083 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10582 12:00:35.702631 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10583 12:00:35.706090 [ 0.000000] psci: probing for conduit method from DT.
10584 12:00:35.712825 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10585 12:00:35.715813 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10586 12:00:35.723033 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10587 12:00:35.725839 [ 0.000000] psci: SMC Calling Convention v1.2
10588 12:00:35.732589 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10589 12:00:35.735721 [ 0.000000] Detected VIPT I-cache on CPU0
10590 12:00:35.742154 [ 0.000000] CPU features: detected: GIC system register CPU interface
10591 12:00:35.749059 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10592 12:00:35.755940 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10593 12:00:35.762558 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10594 12:00:35.769087 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10595 12:00:35.775669 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10596 12:00:35.782423 [ 0.000000] alternatives: applying boot alternatives
10597 12:00:35.785507 [ 0.000000] Fallback order for Node 0: 0
10598 12:00:35.792428 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10599 12:00:35.796001 [ 0.000000] Policy zone: Normal
10600 12:00:35.812496 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10601 12:00:35.822650 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10602 12:00:35.833364 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10603 12:00:35.843681 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10604 12:00:35.850344 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10605 12:00:35.853301 <6>[ 0.000000] software IO TLB: area num 8.
10606 12:00:35.910174 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10607 12:00:36.058975 <6>[ 0.000000] Memory: 7873588K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 479180K reserved, 32768K cma-reserved)
10608 12:00:36.065568 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10609 12:00:36.072292 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10610 12:00:36.075481 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10611 12:00:36.082302 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10612 12:00:36.089197 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10613 12:00:36.092193 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10614 12:00:36.101915 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10615 12:00:36.108952 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10616 12:00:36.115722 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10617 12:00:36.122243 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10618 12:00:36.125429 <6>[ 0.000000] GICv3: 608 SPIs implemented
10619 12:00:36.129041 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10620 12:00:36.135741 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10621 12:00:36.139208 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10622 12:00:36.145159 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10623 12:00:36.158512 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10624 12:00:36.168871 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10625 12:00:36.178379 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10626 12:00:36.185564 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10627 12:00:36.198231 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10628 12:00:36.204983 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10629 12:00:36.212008 <6>[ 0.009180] Console: colour dummy device 80x25
10630 12:00:36.221503 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10631 12:00:36.225482 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10632 12:00:36.231618 <6>[ 0.029221] LSM: Security Framework initializing
10633 12:00:36.238538 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10634 12:00:36.248093 <6>[ 0.041971] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10635 12:00:36.255248 <6>[ 0.051350] cblist_init_generic: Setting adjustable number of callback queues.
10636 12:00:36.261398 <6>[ 0.058792] cblist_init_generic: Setting shift to 3 and lim to 1.
10637 12:00:36.271532 <6>[ 0.065131] cblist_init_generic: Setting adjustable number of callback queues.
10638 12:00:36.275252 <6>[ 0.072558] cblist_init_generic: Setting shift to 3 and lim to 1.
10639 12:00:36.281556 <6>[ 0.078959] rcu: Hierarchical SRCU implementation.
10640 12:00:36.288556 <6>[ 0.083974] rcu: Max phase no-delay instances is 1000.
10641 12:00:36.294773 <6>[ 0.090995] EFI services will not be available.
10642 12:00:36.298102 <6>[ 0.095949] smp: Bringing up secondary CPUs ...
10643 12:00:36.305627 <6>[ 0.101025] Detected VIPT I-cache on CPU1
10644 12:00:36.312458 <6>[ 0.101094] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10645 12:00:36.319028 <6>[ 0.101125] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10646 12:00:36.322457 <6>[ 0.101455] Detected VIPT I-cache on CPU2
10647 12:00:36.329057 <6>[ 0.101500] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10648 12:00:36.336031 <6>[ 0.101516] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10649 12:00:36.342540 <6>[ 0.101765] Detected VIPT I-cache on CPU3
10650 12:00:36.349527 <6>[ 0.101807] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10651 12:00:36.355946 <6>[ 0.101821] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10652 12:00:36.359158 <6>[ 0.102127] CPU features: detected: Spectre-v4
10653 12:00:36.365550 <6>[ 0.102134] CPU features: detected: Spectre-BHB
10654 12:00:36.369050 <6>[ 0.102139] Detected PIPT I-cache on CPU4
10655 12:00:36.376076 <6>[ 0.102195] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10656 12:00:36.382342 <6>[ 0.102211] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10657 12:00:36.389570 <6>[ 0.102506] Detected PIPT I-cache on CPU5
10658 12:00:36.395338 <6>[ 0.102568] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10659 12:00:36.402621 <6>[ 0.102584] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10660 12:00:36.405822 <6>[ 0.102864] Detected PIPT I-cache on CPU6
10661 12:00:36.412282 <6>[ 0.102927] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10662 12:00:36.418819 <6>[ 0.102943] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10663 12:00:36.425748 <6>[ 0.103237] Detected PIPT I-cache on CPU7
10664 12:00:36.431998 <6>[ 0.103303] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10665 12:00:36.438839 <6>[ 0.103319] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10666 12:00:36.442152 <6>[ 0.103365] smp: Brought up 1 node, 8 CPUs
10667 12:00:36.449148 <6>[ 0.244832] SMP: Total of 8 processors activated.
10668 12:00:36.452859 <6>[ 0.249752] CPU features: detected: 32-bit EL0 Support
10669 12:00:36.462595 <6>[ 0.255116] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10670 12:00:36.468831 <6>[ 0.263916] CPU features: detected: Common not Private translations
10671 12:00:36.472273 <6>[ 0.270392] CPU features: detected: CRC32 instructions
10672 12:00:36.478844 <6>[ 0.275743] CPU features: detected: RCpc load-acquire (LDAPR)
10673 12:00:36.485421 <6>[ 0.281702] CPU features: detected: LSE atomic instructions
10674 12:00:36.492425 <6>[ 0.287484] CPU features: detected: Privileged Access Never
10675 12:00:36.495578 <6>[ 0.293263] CPU features: detected: RAS Extension Support
10676 12:00:36.505631 <6>[ 0.298872] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10677 12:00:36.508611 <6>[ 0.306134] CPU: All CPU(s) started at EL2
10678 12:00:36.515276 <6>[ 0.310450] alternatives: applying system-wide alternatives
10679 12:00:36.523579 <6>[ 0.321145] devtmpfs: initialized
10680 12:00:36.539229 <6>[ 0.330145] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10681 12:00:36.545859 <6>[ 0.340112] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10682 12:00:36.552218 <6>[ 0.348283] pinctrl core: initialized pinctrl subsystem
10683 12:00:36.555797 <6>[ 0.354953] DMI not present or invalid.
10684 12:00:36.562472 <6>[ 0.359370] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10685 12:00:36.572046 <6>[ 0.366251] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10686 12:00:36.579078 <6>[ 0.373835] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10687 12:00:36.588455 <6>[ 0.382060] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10688 12:00:36.592657 <6>[ 0.390303] audit: initializing netlink subsys (disabled)
10689 12:00:36.602158 <5>[ 0.395996] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10690 12:00:36.608385 <6>[ 0.396700] thermal_sys: Registered thermal governor 'step_wise'
10691 12:00:36.615117 <6>[ 0.403967] thermal_sys: Registered thermal governor 'power_allocator'
10692 12:00:36.618612 <6>[ 0.410224] cpuidle: using governor menu
10693 12:00:36.625418 <6>[ 0.421188] NET: Registered PF_QIPCRTR protocol family
10694 12:00:36.631866 <6>[ 0.426671] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10695 12:00:36.638429 <6>[ 0.433781] ASID allocator initialised with 32768 entries
10696 12:00:36.641536 <6>[ 0.440355] Serial: AMBA PL011 UART driver
10697 12:00:36.651672 <4>[ 0.449145] Trying to register duplicate clock ID: 134
10698 12:00:36.708176 <6>[ 0.508671] KASLR enabled
10699 12:00:36.722604 <6>[ 0.516388] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10700 12:00:36.729121 <6>[ 0.523404] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10701 12:00:36.735576 <6>[ 0.529894] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10702 12:00:36.742050 <6>[ 0.536901] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10703 12:00:36.748596 <6>[ 0.543391] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10704 12:00:36.755555 <6>[ 0.550397] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10705 12:00:36.762216 <6>[ 0.556890] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10706 12:00:36.768804 <6>[ 0.563900] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10707 12:00:36.772301 <6>[ 0.571305] ACPI: Interpreter disabled.
10708 12:00:36.779954 <6>[ 0.577728] iommu: Default domain type: Translated
10709 12:00:36.786883 <6>[ 0.582846] iommu: DMA domain TLB invalidation policy: strict mode
10710 12:00:36.790130 <5>[ 0.589499] SCSI subsystem initialized
10711 12:00:36.796860 <6>[ 0.593664] usbcore: registered new interface driver usbfs
10712 12:00:36.803420 <6>[ 0.599397] usbcore: registered new interface driver hub
10713 12:00:36.806650 <6>[ 0.604949] usbcore: registered new device driver usb
10714 12:00:36.813306 <6>[ 0.611052] pps_core: LinuxPPS API ver. 1 registered
10715 12:00:36.823576 <6>[ 0.616246] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10716 12:00:36.826971 <6>[ 0.625599] PTP clock support registered
10717 12:00:36.830327 <6>[ 0.629845] EDAC MC: Ver: 3.0.0
10718 12:00:36.837537 <6>[ 0.635006] FPGA manager framework
10719 12:00:36.844108 <6>[ 0.638688] Advanced Linux Sound Architecture Driver Initialized.
10720 12:00:36.847550 <6>[ 0.645459] vgaarb: loaded
10721 12:00:36.854135 <6>[ 0.648636] clocksource: Switched to clocksource arch_sys_counter
10722 12:00:36.857391 <5>[ 0.655068] VFS: Disk quotas dquot_6.6.0
10723 12:00:36.863969 <6>[ 0.659252] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10724 12:00:36.867216 <6>[ 0.666441] pnp: PnP ACPI: disabled
10725 12:00:36.875765 <6>[ 0.673071] NET: Registered PF_INET protocol family
10726 12:00:36.885325 <6>[ 0.678660] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10727 12:00:36.896843 <6>[ 0.690978] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10728 12:00:36.907010 <6>[ 0.699796] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10729 12:00:36.913285 <6>[ 0.707767] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10730 12:00:36.920480 <6>[ 0.716472] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10731 12:00:36.932148 <6>[ 0.726218] TCP: Hash tables configured (established 65536 bind 65536)
10732 12:00:36.938833 <6>[ 0.733079] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10733 12:00:36.945806 <6>[ 0.740282] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10734 12:00:36.952032 <6>[ 0.747979] NET: Registered PF_UNIX/PF_LOCAL protocol family
10735 12:00:36.958607 <6>[ 0.754156] RPC: Registered named UNIX socket transport module.
10736 12:00:36.962177 <6>[ 0.760311] RPC: Registered udp transport module.
10737 12:00:36.968870 <6>[ 0.765244] RPC: Registered tcp transport module.
10738 12:00:36.975524 <6>[ 0.770177] RPC: Registered tcp NFSv4.1 backchannel transport module.
10739 12:00:36.978601 <6>[ 0.776848] PCI: CLS 0 bytes, default 64
10740 12:00:36.982070 <6>[ 0.781244] Unpacking initramfs...
10741 12:00:36.999294 <6>[ 0.793251] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10742 12:00:37.009194 <6>[ 0.801915] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10743 12:00:37.012581 <6>[ 0.810772] kvm [1]: IPA Size Limit: 40 bits
10744 12:00:37.019012 <6>[ 0.815300] kvm [1]: GICv3: no GICV resource entry
10745 12:00:37.022087 <6>[ 0.820322] kvm [1]: disabling GICv2 emulation
10746 12:00:37.028957 <6>[ 0.825013] kvm [1]: GIC system register CPU interface enabled
10747 12:00:37.032388 <6>[ 0.831178] kvm [1]: vgic interrupt IRQ18
10748 12:00:37.039007 <6>[ 0.835563] kvm [1]: VHE mode initialized successfully
10749 12:00:37.045704 <5>[ 0.842007] Initialise system trusted keyrings
10750 12:00:37.051715 <6>[ 0.846775] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10751 12:00:37.059098 <6>[ 0.856760] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10752 12:00:37.066094 <5>[ 0.863142] NFS: Registering the id_resolver key type
10753 12:00:37.069054 <5>[ 0.868447] Key type id_resolver registered
10754 12:00:37.075605 <5>[ 0.872863] Key type id_legacy registered
10755 12:00:37.082403 <6>[ 0.877153] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10756 12:00:37.089354 <6>[ 0.884079] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10757 12:00:37.095722 <6>[ 0.891801] 9p: Installing v9fs 9p2000 file system support
10758 12:00:37.131386 <5>[ 0.929244] Key type asymmetric registered
10759 12:00:37.134759 <5>[ 0.933581] Asymmetric key parser 'x509' registered
10760 12:00:37.144773 <6>[ 0.938721] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10761 12:00:37.147999 <6>[ 0.946338] io scheduler mq-deadline registered
10762 12:00:37.151378 <6>[ 0.951117] io scheduler kyber registered
10763 12:00:37.170439 <6>[ 0.968214] EINJ: ACPI disabled.
10764 12:00:37.203087 <4>[ 0.993969] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10765 12:00:37.212930 <4>[ 1.004616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10766 12:00:37.227535 <6>[ 1.025354] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10767 12:00:37.235354 <6>[ 1.033330] printk: console [ttyS0] disabled
10768 12:00:37.263490 <6>[ 1.057977] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10769 12:00:37.270196 <6>[ 1.067452] printk: console [ttyS0] enabled
10770 12:00:37.273683 <6>[ 1.067452] printk: console [ttyS0] enabled
10771 12:00:37.280114 <6>[ 1.076346] printk: bootconsole [mtk8250] disabled
10772 12:00:37.283441 <6>[ 1.076346] printk: bootconsole [mtk8250] disabled
10773 12:00:37.290048 <6>[ 1.087597] SuperH (H)SCI(F) driver initialized
10774 12:00:37.293362 <6>[ 1.092904] msm_serial: driver initialized
10775 12:00:37.307848 <6>[ 1.101856] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10776 12:00:37.317468 <6>[ 1.110405] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10777 12:00:37.323943 <6>[ 1.118947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10778 12:00:37.333900 <6>[ 1.127576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10779 12:00:37.340526 <6>[ 1.136282] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10780 12:00:37.350830 <6>[ 1.145002] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10781 12:00:37.360639 <6>[ 1.153542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10782 12:00:37.367443 <6>[ 1.162344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10783 12:00:37.377190 <6>[ 1.170888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10784 12:00:37.389121 <6>[ 1.186502] loop: module loaded
10785 12:00:37.395669 <6>[ 1.192267] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10786 12:00:37.417782 <4>[ 1.215585] mtk-pmic-keys: Failed to locate of_node [id: -1]
10787 12:00:37.424672 <6>[ 1.222456] megasas: 07.719.03.00-rc1
10788 12:00:37.434086 <6>[ 1.231971] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10789 12:00:37.442692 <6>[ 1.240012] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10790 12:00:37.459179 <6>[ 1.256621] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10791 12:00:37.516049 <6>[ 1.306753] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10792 12:00:41.008927 <6>[ 4.806618] Freeing initrd memory: 96028K
10793 12:00:41.019540 <6>[ 4.817087] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10794 12:00:41.030688 <6>[ 4.827995] tun: Universal TUN/TAP device driver, 1.6
10795 12:00:41.034236 <6>[ 4.834062] thunder_xcv, ver 1.0
10796 12:00:41.036835 <6>[ 4.837565] thunder_bgx, ver 1.0
10797 12:00:41.040362 <6>[ 4.841060] nicpf, ver 1.0
10798 12:00:41.051130 <6>[ 4.845074] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10799 12:00:41.054107 <6>[ 4.852550] hns3: Copyright (c) 2017 Huawei Corporation.
10800 12:00:41.061198 <6>[ 4.858140] hclge is initializing
10801 12:00:41.064518 <6>[ 4.861720] e1000: Intel(R) PRO/1000 Network Driver
10802 12:00:41.070639 <6>[ 4.866849] e1000: Copyright (c) 1999-2006 Intel Corporation.
10803 12:00:41.074121 <6>[ 4.872860] e1000e: Intel(R) PRO/1000 Network Driver
10804 12:00:41.080982 <6>[ 4.878075] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10805 12:00:41.087168 <6>[ 4.884259] igb: Intel(R) Gigabit Ethernet Network Driver
10806 12:00:41.094019 <6>[ 4.889909] igb: Copyright (c) 2007-2014 Intel Corporation.
10807 12:00:41.100507 <6>[ 4.895745] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10808 12:00:41.107284 <6>[ 4.902263] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10809 12:00:41.110202 <6>[ 4.908736] sky2: driver version 1.30
10810 12:00:41.117001 <6>[ 4.913736] VFIO - User Level meta-driver version: 0.3
10811 12:00:41.124329 <6>[ 4.921987] usbcore: registered new interface driver usb-storage
10812 12:00:41.130914 <6>[ 4.928426] usbcore: registered new device driver onboard-usb-hub
10813 12:00:41.140471 <6>[ 4.937602] mt6397-rtc mt6359-rtc: registered as rtc0
10814 12:00:41.150572 <6>[ 4.943091] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:58:29 UTC (1700740709)
10815 12:00:41.153323 <6>[ 4.952724] i2c_dev: i2c /dev entries driver
10816 12:00:41.170411 <6>[ 4.964403] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10817 12:00:41.191187 <6>[ 4.988419] cpu cpu0: EM: created perf domain
10818 12:00:41.194452 <6>[ 4.993358] cpu cpu4: EM: created perf domain
10819 12:00:41.201340 <6>[ 4.998912] sdhci: Secure Digital Host Controller Interface driver
10820 12:00:41.207892 <6>[ 5.005344] sdhci: Copyright(c) Pierre Ossman
10821 12:00:41.214560 <6>[ 5.010299] Synopsys Designware Multimedia Card Interface Driver
10822 12:00:41.221360 <6>[ 5.016944] sdhci-pltfm: SDHCI platform and OF driver helper
10823 12:00:41.224401 <6>[ 5.016980] mmc0: CQHCI version 5.10
10824 12:00:41.231189 <6>[ 5.026920] ledtrig-cpu: registered to indicate activity on CPUs
10825 12:00:41.238094 <6>[ 5.033885] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10826 12:00:41.244736 <6>[ 5.040951] usbcore: registered new interface driver usbhid
10827 12:00:41.247660 <6>[ 5.046775] usbhid: USB HID core driver
10828 12:00:41.254411 <6>[ 5.050988] spi_master spi0: will run message pump with realtime priority
10829 12:00:41.298659 <6>[ 5.089753] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10830 12:00:41.317541 <6>[ 5.104890] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10831 12:00:41.324966 <6>[ 5.119707] cros-ec-spi spi0.0: Chrome EC device registered
10832 12:00:41.328105 <6>[ 5.125770] mmc0: Command Queue Engine enabled
10833 12:00:41.334954 <6>[ 5.130535] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10834 12:00:41.341602 <6>[ 5.138163] mmcblk0: mmc0:0001 DA4128 116 GiB
10835 12:00:41.350224 <6>[ 5.148045] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10836 12:00:41.358302 <6>[ 5.155949] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10837 12:00:41.368444 <6>[ 5.161358] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10838 12:00:41.374603 <6>[ 5.162177] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10839 12:00:41.378294 <6>[ 5.171986] NET: Registered PF_PACKET protocol family
10840 12:00:41.384945 <6>[ 5.176541] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10841 12:00:41.388264 <6>[ 5.181280] 9pnet: Installing 9P2000 support
10842 12:00:41.395048 <5>[ 5.192285] Key type dns_resolver registered
10843 12:00:41.398136 <6>[ 5.197252] registered taskstats version 1
10844 12:00:41.404262 <5>[ 5.201637] Loading compiled-in X.509 certificates
10845 12:00:41.434837 <4>[ 5.225652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10846 12:00:41.445441 <4>[ 5.236590] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10847 12:00:41.451228 <3>[ 5.247145] debugfs: File 'uA_load' in directory '/' already present!
10848 12:00:41.457533 <3>[ 5.253908] debugfs: File 'min_uV' in directory '/' already present!
10849 12:00:41.464555 <3>[ 5.260650] debugfs: File 'max_uV' in directory '/' already present!
10850 12:00:41.470686 <3>[ 5.267259] debugfs: File 'constraint_flags' in directory '/' already present!
10851 12:00:41.482497 <3>[ 5.276858] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10852 12:00:41.491823 <6>[ 5.289424] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10853 12:00:41.498656 <6>[ 5.296139] xhci-mtk 11200000.usb: xHCI Host Controller
10854 12:00:41.505273 <6>[ 5.301629] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10855 12:00:41.515395 <6>[ 5.309454] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10856 12:00:41.521756 <6>[ 5.318865] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10857 12:00:41.528916 <6>[ 5.324933] xhci-mtk 11200000.usb: xHCI Host Controller
10858 12:00:41.535325 <6>[ 5.330408] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10859 12:00:41.542255 <6>[ 5.338051] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10860 12:00:41.548246 <6>[ 5.345684] hub 1-0:1.0: USB hub found
10861 12:00:41.551949 <6>[ 5.349694] hub 1-0:1.0: 1 port detected
10862 12:00:41.558150 <6>[ 5.353952] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10863 12:00:41.565244 <6>[ 5.362481] hub 2-0:1.0: USB hub found
10864 12:00:41.568588 <6>[ 5.366484] hub 2-0:1.0: 1 port detected
10865 12:00:41.575693 <6>[ 5.373445] mtk-msdc 11f70000.mmc: Got CD GPIO
10866 12:00:41.586818 <6>[ 5.380668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10867 12:00:41.593291 <6>[ 5.388681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10868 12:00:41.602774 <4>[ 5.396576] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10869 12:00:41.613022 <6>[ 5.406100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10870 12:00:41.619415 <6>[ 5.414175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10871 12:00:41.625866 <6>[ 5.422323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10872 12:00:41.636195 <6>[ 5.430259] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10873 12:00:41.642818 <6>[ 5.438136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10874 12:00:41.652853 <6>[ 5.445959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10875 12:00:41.663056 <6>[ 5.456463] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10876 12:00:41.670072 <6>[ 5.464825] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10877 12:00:41.679578 <6>[ 5.473243] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10878 12:00:41.685870 <6>[ 5.481591] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10879 12:00:41.695888 <6>[ 5.489950] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10880 12:00:41.702244 <6>[ 5.498289] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10881 12:00:41.712435 <6>[ 5.506639] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10882 12:00:41.722658 <6>[ 5.514982] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10883 12:00:41.729672 <6>[ 5.523338] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10884 12:00:41.739220 <6>[ 5.531677] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10885 12:00:41.745455 <6>[ 5.540025] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10886 12:00:41.755259 <6>[ 5.548364] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10887 12:00:41.762216 <6>[ 5.556703] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10888 12:00:41.772568 <6>[ 5.565041] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10889 12:00:41.778741 <6>[ 5.573380] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10890 12:00:41.785384 <6>[ 5.582003] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10891 12:00:41.792255 <6>[ 5.589158] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10892 12:00:41.798536 <6>[ 5.595942] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10893 12:00:41.805890 <6>[ 5.602703] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10894 12:00:41.815311 <6>[ 5.609631] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10895 12:00:41.821910 <6>[ 5.616477] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10896 12:00:41.831970 <6>[ 5.625624] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10897 12:00:41.842032 <6>[ 5.634746] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10898 12:00:41.852044 <6>[ 5.644039] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10899 12:00:41.861773 <6>[ 5.653559] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10900 12:00:41.868630 <6>[ 5.663035] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10901 12:00:41.878352 <6>[ 5.672156] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10902 12:00:41.889100 <6>[ 5.681623] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10903 12:00:41.898545 <6>[ 5.690742] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10904 12:00:41.908553 <6>[ 5.700037] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10905 12:00:41.918101 <6>[ 5.710196] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10906 12:00:41.928339 <6>[ 5.722244] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10907 12:00:41.958548 <6>[ 5.753022] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10908 12:00:41.988766 <6>[ 5.785766] hub 2-1:1.0: USB hub found
10909 12:00:41.991386 <6>[ 5.790337] hub 2-1:1.0: 3 ports detected
10910 12:00:42.001173 <6>[ 5.798801] hub 2-1:1.0: USB hub found
10911 12:00:42.004480 <6>[ 5.803294] hub 2-1:1.0: 3 ports detected
10912 12:00:42.110278 <6>[ 5.904845] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10913 12:00:42.265223 <6>[ 6.062520] hub 1-1:1.0: USB hub found
10914 12:00:42.268071 <6>[ 6.066976] hub 1-1:1.0: 4 ports detected
10915 12:00:42.276684 <6>[ 6.074500] hub 1-1:1.0: USB hub found
10916 12:00:42.280037 <6>[ 6.078973] hub 1-1:1.0: 4 ports detected
10917 12:00:42.346302 <6>[ 6.141035] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10918 12:00:42.602143 <6>[ 6.396948] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10919 12:00:42.735040 <6>[ 6.532816] hub 1-1.4:1.0: USB hub found
10920 12:00:42.738270 <6>[ 6.537480] hub 1-1.4:1.0: 2 ports detected
10921 12:00:42.747800 <6>[ 6.545757] hub 1-1.4:1.0: USB hub found
10922 12:00:42.751237 <6>[ 6.550270] hub 1-1.4:1.0: 2 ports detected
10923 12:00:43.046454 <6>[ 6.840947] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10924 12:00:43.238858 <6>[ 7.032948] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10925 12:00:54.228143 <6>[ 18.029908] ALSA device list:
10926 12:00:54.234494 <6>[ 18.033200] No soundcards found.
10927 12:00:54.242426 <6>[ 18.041172] Freeing unused kernel memory: 8384K
10928 12:00:54.245190 <6>[ 18.046157] Run /init as init process
10929 12:00:54.293740 <6>[ 18.093095] NET: Registered PF_INET6 protocol family
10930 12:00:54.300633 <6>[ 18.099428] Segment Routing with IPv6
10931 12:00:54.303936 <6>[ 18.103377] In-situ OAM (IOAM) with IPv6
10932 12:00:54.338488 <30>[ 18.117444] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10933 12:00:54.341718 <30>[ 18.141365] systemd[1]: Detected architecture arm64.
10934 12:00:54.342346
10935 12:00:54.348374 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10936 12:00:54.348934
10937 12:00:54.362307 <30>[ 18.160954] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10938 12:00:54.523129 <30>[ 18.319261] systemd[1]: Queued start job for default target Graphical Interface.
10939 12:00:54.570970 <30>[ 18.369627] systemd[1]: Created slice system-getty.slice.
10940 12:00:54.577643 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10941 12:00:54.594190 <30>[ 18.393426] systemd[1]: Created slice system-modprobe.slice.
10942 12:00:54.601202 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10943 12:00:54.619413 <30>[ 18.417928] systemd[1]: Created slice system-serial\x2dgetty.slice.
10944 12:00:54.628576 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10945 12:00:54.642103 <30>[ 18.441350] systemd[1]: Created slice User and Session Slice.
10946 12:00:54.649095 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10947 12:00:54.670071 <30>[ 18.465599] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10948 12:00:54.676371 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10949 12:00:54.697950 <30>[ 18.493639] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10950 12:00:54.704619 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10951 12:00:54.728995 <30>[ 18.521426] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10952 12:00:54.735820 <30>[ 18.533689] systemd[1]: Reached target Local Encrypted Volumes.
10953 12:00:54.742680 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10954 12:00:54.758237 <30>[ 18.557440] systemd[1]: Reached target Paths.
10955 12:00:54.761905 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10956 12:00:54.778095 <30>[ 18.576927] systemd[1]: Reached target Remote File Systems.
10957 12:00:54.784476 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10958 12:00:54.797821 <30>[ 18.596884] systemd[1]: Reached target Slices.
10959 12:00:54.801664 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10960 12:00:54.817952 <30>[ 18.616932] systemd[1]: Reached target Swap.
10961 12:00:54.821625 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10962 12:00:54.841750 <30>[ 18.637376] systemd[1]: Listening on initctl Compatibility Named Pipe.
10963 12:00:54.847975 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10964 12:00:54.863619 <30>[ 18.662356] systemd[1]: Listening on Journal Audit Socket.
10965 12:00:54.870428 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10966 12:00:54.886694 <30>[ 18.686072] systemd[1]: Listening on Journal Socket (/dev/log).
10967 12:00:54.894143 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10968 12:00:54.911116 <30>[ 18.710123] systemd[1]: Listening on Journal Socket.
10969 12:00:54.918210 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10970 12:00:54.930285 <30>[ 18.729488] systemd[1]: Listening on udev Control Socket.
10971 12:00:54.937632 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10972 12:00:54.955076 <30>[ 18.753968] systemd[1]: Listening on udev Kernel Socket.
10973 12:00:54.961474 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10974 12:00:55.014847 <30>[ 18.813186] systemd[1]: Mounting Huge Pages File System...
10975 12:00:55.020733 Mounting [0;1;39mHuge Pages File System[0m...
10976 12:00:55.037155 <30>[ 18.836153] systemd[1]: Mounting POSIX Message Queue File System...
10977 12:00:55.043839 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10978 12:00:55.061676 <30>[ 18.860257] systemd[1]: Mounting Kernel Debug File System...
10979 12:00:55.067989 Mounting [0;1;39mKernel Debug File System[0m...
10980 12:00:55.085303 <30>[ 18.881099] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10981 12:00:55.098220 <30>[ 18.893985] systemd[1]: Starting Create list of static device nodes for the current kernel...
10982 12:00:55.104812 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10983 12:00:55.142166 <30>[ 18.941229] systemd[1]: Starting Load Kernel Module configfs...
10984 12:00:55.149007 Starting [0;1;39mLoad Kernel Module configfs[0m...
10985 12:00:55.166177 <30>[ 18.964800] systemd[1]: Starting Load Kernel Module drm...
10986 12:00:55.172268 Starting [0;1;39mLoad Kernel Module drm[0m...
10987 12:00:55.189038 <30>[ 18.985049] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10988 12:00:55.203781 <30>[ 19.002791] systemd[1]: Starting Journal Service...
10989 12:00:55.207126 Starting [0;1;39mJournal Service[0m...
10990 12:00:55.224992 <30>[ 19.023790] systemd[1]: Starting Load Kernel Modules...
10991 12:00:55.231541 Starting [0;1;39mLoad Kernel Modules[0m...
10992 12:00:55.251832 <30>[ 19.047661] systemd[1]: Starting Remount Root and Kernel File Systems...
10993 12:00:55.259027 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10994 12:00:55.276821 <30>[ 19.075857] systemd[1]: Starting Coldplug All udev Devices...
10995 12:00:55.283254 Starting [0;1;39mColdplug All udev Devices[0m...
10996 12:00:55.301358 <30>[ 19.100455] systemd[1]: Started Journal Service.
10997 12:00:55.308018 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10998 12:00:55.324972 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10999 12:00:55.342777 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11000 12:00:55.359025 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11001 12:00:55.378334 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11002 12:00:55.396311 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11003 12:00:55.415598 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11004 12:00:55.431679 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11005 12:00:55.452119 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11006 12:00:55.466469 See 'systemctl status systemd-remount-fs.service' for details.
11007 12:00:55.510951 Mounting [0;1;39mKernel Configuration File System[0m...
11008 12:00:55.528423 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11009 12:00:55.545968 <46>[ 19.341369] systemd-journald[174]: Received client request to flush runtime journal.
11010 12:00:55.555320 Starting [0;1;39mLoad/Save Random Seed[0m...
11011 12:00:55.574969 Starting [0;1;39mApply Kernel Variables[0m...
11012 12:00:55.595489 Starting [0;1;39mCreate System Users[0m...
11013 12:00:55.613524 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11014 12:00:55.630287 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11015 12:00:55.650654 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11016 12:00:55.663611 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11017 12:00:55.680046 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11018 12:00:55.700082 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11019 12:00:55.758697 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11020 12:00:55.781057 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11021 12:00:55.794496 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11022 12:00:55.813887 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11023 12:00:55.854426 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11024 12:00:55.882320 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11025 12:00:55.908939 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11026 12:00:55.927706 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11027 12:00:55.977976 Starting [0;1;39mNetwork Time Synchronization[0m...
11028 12:00:56.003288 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11029 12:00:56.061248 <6>[ 19.857019] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11030 12:00:56.071774 [[0;32m OK [<6>[ 19.866106] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11031 12:00:56.081321 0m] Finished [0;1;39mUpdate UTM<6>[ 19.877907] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11032 12:00:56.084861 P about System Boot/Shutdown[0m.
11033 12:00:56.106963 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11034 12:00:56.118450 <6>[ 19.914059] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11035 12:00:56.121387 <6>[ 19.922165] mc: Linux media interface: v0.10
11036 12:00:56.128155 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11037 12:00:56.134941 <6>[ 19.933613] remoteproc remoteproc0: scp is available
11038 12:00:56.141570 <6>[ 19.938965] remoteproc remoteproc0: powering up scp
11039 12:00:56.148221 <6>[ 19.944101] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11040 12:00:56.154819 <4>[ 19.949706] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11041 12:00:56.161931 <6>[ 19.952654] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11042 12:00:56.168654 <6>[ 19.953261] videodev: Linux video capture interface: v2.00
11043 12:00:56.174953 <4>[ 19.969577] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11044 12:00:56.181703 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11045 12:00:56.198517 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11046 12:00:56.211606 <6>[ 20.007235] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11047 12:00:56.218232 <3>[ 20.007299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 12:00:56.225025 <6>[ 20.014371] pci_bus 0000:00: root bus resource [bus 00-ff]
11049 12:00:56.231197 <3>[ 20.022425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11050 12:00:56.238146 <6>[ 20.024493] usbcore: registered new interface driver r8152
11051 12:00:56.244392 <6>[ 20.028052] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11052 12:00:56.254470 <6>[ 20.028059] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11053 12:00:56.261346 <6>[ 20.028108] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11054 12:00:56.268119 <3>[ 20.036319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11055 12:00:56.278342 <6>[ 20.042104] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11056 12:00:56.285158 <6>[ 20.043390] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11057 12:00:56.291749 <3>[ 20.049270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11058 12:00:56.298410 <6>[ 20.059669] pci 0000:00:00.0: supports D1 D2
11059 12:00:56.305360 <3>[ 20.065489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11060 12:00:56.315512 <4>[ 20.069482] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11061 12:00:56.318642 <4>[ 20.069482] Fallback method does not support PEC.
11062 12:00:56.325226 <6>[ 20.073501] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11063 12:00:56.335410 <6>[ 20.074821] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11064 12:00:56.342126 <3>[ 20.080982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11065 12:00:56.351985 <3>[ 20.080991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 12:00:56.358273 <3>[ 20.080997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11067 12:00:56.368474 <3>[ 20.083045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 12:00:56.371296 <6>[ 20.088808] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11069 12:00:56.381243 <6>[ 20.096687] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11070 12:00:56.388011 <3>[ 20.097162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 12:00:56.397991 <6>[ 20.101414] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11072 12:00:56.405048 <6>[ 20.101692] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11073 12:00:56.414511 <3>[ 20.109473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11074 12:00:56.421778 <6>[ 20.109613] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11075 12:00:56.428275 <6>[ 20.109639] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11076 12:00:56.437795 <6>[ 20.109658] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11077 12:00:56.441042 <6>[ 20.109787] pci 0000:01:00.0: supports D1 D2
11078 12:00:56.447539 <6>[ 20.109791] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11079 12:00:56.455225 <6>[ 20.120861] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11080 12:00:56.462236 <6>[ 20.120922] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11081 12:00:56.472520 <6>[ 20.120930] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11082 12:00:56.479595 <6>[ 20.120944] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11083 12:00:56.486430 <6>[ 20.120960] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11084 12:00:56.496755 <6>[ 20.120977] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11085 12:00:56.500199 <6>[ 20.120994] pci 0000:00:00.0: PCI bridge to [bus 01]
11086 12:00:56.506893 <6>[ 20.121003] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11087 12:00:56.513931 <6>[ 20.121390] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11088 12:00:56.523904 <6>[ 20.121785] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11089 12:00:56.530597 <6>[ 20.123142] remoteproc remoteproc0: remote processor scp is now up
11090 12:00:56.540694 <6>[ 20.125205] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11091 12:00:56.547264 <3>[ 20.130071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11092 12:00:56.558097 <3>[ 20.130850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11093 12:00:56.564786 <3>[ 20.149108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 12:00:56.571875 <6>[ 20.149181] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11095 12:00:56.575612 <6>[ 20.152907] Bluetooth: Core ver 2.22
11096 12:00:56.582043 <6>[ 20.152974] NET: Registered PF_BLUETOOTH protocol family
11097 12:00:56.588764 <6>[ 20.152977] Bluetooth: HCI device and connection manager initialized
11098 12:00:56.591997 <6>[ 20.152998] Bluetooth: HCI socket layer initialized
11099 12:00:56.598610 <6>[ 20.153004] Bluetooth: L2CAP socket layer initialized
11100 12:00:56.605283 <6>[ 20.153016] Bluetooth: SCO socket layer initialized
11101 12:00:56.608658 <6>[ 20.168677] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11102 12:00:56.618773 <3>[ 20.171022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11103 12:00:56.625671 <4>[ 20.171801] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11104 12:00:56.636017 <4>[ 20.171812] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11105 12:00:56.642467 <6>[ 20.177728] usbcore: registered new interface driver cdc_ether
11106 12:00:56.648994 <3>[ 20.184027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11107 12:00:56.659071 <3>[ 20.184039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11108 12:00:56.665928 <6>[ 20.185650] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11109 12:00:56.672769 <6>[ 20.187972] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11110 12:00:56.679127 <6>[ 20.192290] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11111 12:00:56.688763 <3>[ 20.200628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11112 12:00:56.696298 <3>[ 20.200708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11113 12:00:56.702463 <6>[ 20.210263] usbcore: registered new interface driver r8153_ecm
11114 12:00:56.709184 <6>[ 20.218614] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11115 12:00:56.712100 <6>[ 20.225198] r8152 2-1.3:1.0 eth0: v1.12.13
11116 12:00:56.719607 <6>[ 20.233928] usbcore: registered new interface driver btusb
11117 12:00:56.729966 <4>[ 20.234375] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11118 12:00:56.736770 <3>[ 20.234385] Bluetooth: hci0: Failed to load firmware file (-2)
11119 12:00:56.739842 <3>[ 20.234388] Bluetooth: hci0: Failed to set up firmware (-2)
11120 12:00:56.750523 <4>[ 20.234392] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11121 12:00:56.757265 <6>[ 20.235399] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11122 12:00:56.771073 <6>[ 20.242216] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11123 12:00:56.777682 <6>[ 20.242785] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11124 12:00:56.784442 <3>[ 20.271867] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
11125 12:00:56.790932 <6>[ 20.275141] usbcore: registered new interface driver uvcvideo
11126 12:00:56.801451 <3>[ 20.290337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11127 12:00:56.808655 <5>[ 20.302966] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11128 12:00:56.815447 <3>[ 20.330316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 12:00:56.825455 <3>[ 20.365473] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11130 12:00:56.836091 <3>[ 20.366199] power_supply sbs-5-000b: driver failed to report `energy_full_design' property: -6
11131 12:00:56.839679 <5>[ 20.370121] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11132 12:00:56.849827 <3>[ 20.395761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11133 12:00:56.860757 <4>[ 20.397507] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11134 12:00:56.866976 <3>[ 20.424012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11135 12:00:56.873944 <6>[ 20.431093] cfg80211: failed to load regulatory.db
11136 12:00:56.881290 <6>[ 20.504842] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11137 12:00:56.887371 <3>[ 20.527032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11138 12:00:56.894350 <6>[ 20.534042] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11139 12:00:56.904275 <3>[ 20.561213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11140 12:00:56.910794 <6>[ 20.580794] mt7921e 0000:01:00.0: ASIC revision: 79610010
11141 12:00:56.917426 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11142 12:00:56.961482 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11143 12:00:56.986212 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11144 12:00:57.016331 <4>[ 20.808807] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11145 12:00:57.134361 <4>[ 20.926652] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11146 12:00:57.140777 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11147 12:00:57.153738 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11148 12:00:57.173156 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11149 12:00:57.189096 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11150 12:00:57.205755 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11151 12:00:57.225506 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11152 12:00:57.250541 [[0;32m OK [0m] Reached target [0;1;39mSock<4>[ 21.043276] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11153 12:00:57.251086 ets[0m.
11154 12:00:57.267307 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11155 12:00:57.286230 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11156 12:00:57.326100 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11157 12:00:57.365237 Starting [0;1;39mUser Login Management[0m...
11158 12:00:57.378208 <4>[ 21.170039] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11159 12:00:57.391066 Starting [0;1;39mPermit User Sessions[0m...
11160 12:00:57.411250 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11161 12:00:57.428251 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11162 12:00:57.439740 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11163 12:00:57.455793 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11164 12:00:57.502296 <4>[ 21.295140] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11165 12:00:57.516381 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11166 12:00:57.559737 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11167 12:00:57.578978 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11168 12:00:57.594185 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11169 12:00:57.624362 [[0;32m OK [0m] Reached targ<4>[ 21.415706] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11170 12:00:57.627254 et [0;1;39mGraphical Interface[0m.
11171 12:00:57.671501 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11172 12:00:57.710155 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11173 12:00:57.745915 <4>[ 21.538548] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11174 12:00:57.746459
11175 12:00:57.746880
11176 12:00:57.748907 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11177 12:00:57.752532
11178 12:00:57.756024 debian-bullseye-arm64 login: root (automatic login)
11179 12:00:57.756572
11180 12:00:57.756930
11181 12:00:57.782403 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
11182 12:00:57.782958
11183 12:00:57.789033 The programs included with the Debian GNU/Linux system are free software;
11184 12:00:57.795943 the exact distribution terms for each program are described in the
11185 12:00:57.798779 individual files in /usr/share/doc/*/copyright.
11186 12:00:57.799262
11187 12:00:57.805162 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11188 12:00:57.809526 permitted by applicable law.
11189 12:00:57.811144 Matched prompt #10: / #
11191 12:00:57.812298 Setting prompt string to ['/ #']
11192 12:00:57.812765 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11194 12:00:57.813909 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11195 12:00:57.814391 start: 2.2.6 expect-shell-connection (timeout 00:02:59) [common]
11196 12:00:57.814771 Setting prompt string to ['/ #']
11197 12:00:57.815106 Forcing a shell prompt, looking for ['/ #']
11199 12:00:57.865898 / #
11200 12:00:57.866561 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11201 12:00:57.867033 Waiting using forced prompt support (timeout 00:02:30)
11202 12:00:57.867549 <4>[ 21.659693] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11203 12:00:57.872201
11204 12:00:57.914688 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11205 12:00:57.915346 start: 2.2.7 export-device-env (timeout 00:02:59) [common]
11206 12:00:57.915869 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11207 12:00:57.916362 end: 2.2 depthcharge-retry (duration 00:02:01) [common]
11208 12:00:57.916865 end: 2 depthcharge-action (duration 00:02:01) [common]
11209 12:00:57.917363 start: 3 lava-test-retry (timeout 00:05:00) [common]
11210 12:00:57.917906 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11211 12:00:57.918327 Using namespace: common
11213 12:00:58.019521 / # #
11214 12:00:58.020178 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11215 12:00:58.020796 #<4>[ 21.779566] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11216 12:00:58.026196
11217 12:00:58.027092 Using /lava-12066560
11219 12:00:58.128395 / # export SHELL=/bin/sh
11220 12:00:58.129220 export SHELL=/bin/sh<4>[ 21.899160] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11221 12:00:58.134740
11223 12:00:58.236569 / # . /lava-12066560/environment
11224 12:00:58.237369 . /lava-12066560/environment<3>[ 22.016922] mt7921e 0000:01:00.0: hardware init failed
11225 12:00:58.242928
11227 12:00:58.344720 / # /lava-12066560/bin/lava-test-runner /lava-12066560/0
11228 12:00:58.345375 Test shell timeout: 10s (minimum of the action and connection timeout)
11229 12:00:58.351191 /lava-12066560/bin/lava-test-runner /lava-12066560/0
11230 12:00:58.373973 + export TESTRUN_ID=0_sleep
11231 12:00:58.377404 + cd /lava-12066560/0/tests/0_sleep
11232 12:00:58.380603 + cat uuid
11233 12:00:58.381159 + UUID=12066560_1.5.2.3.1
11234 12:00:58.381689 + set +x
11235 12:00:58.387666 <LAVA_SIGNAL_STARTRUN 0_sleep 12066560_1.5.2.3.1>
11236 12:00:58.388509 Received signal: <STARTRUN> 0_sleep 12066560_1.5.2.3.1
11237 12:00:58.388921 Starting test lava.0_sleep (12066560_1.5.2.3.1)
11238 12:00:58.389370 Skipping test definition patterns.
11239 12:00:58.390072 + ./config/lava/sleep/sleep.sh mem freeze
11240 12:00:58.393457 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11242 12:00:58.396707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11243 12:00:58.400096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11244 12:00:58.400849 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11246 12:00:58.403230 rtcwake: assuming RTC uses UTC ...
11247 12:00:58.410283 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:58:52 2023
11248 12:00:58.413342 <6>[ 22.214343] PM: suspend entry (deep)
11249 12:00:58.419985 <6>[ 22.218480] Filesystems sync: 0.000 seconds
11250 12:00:58.423618 <6>[ 22.224976] Freezing user space processes
11251 12:00:58.434820 <6>[ 22.231129] Freezing user space processes completed (elapsed 0.001 seconds)
11252 12:00:58.438301 <6>[ 22.238371] OOM killer disabled.
11253 12:00:58.441423 <6>[ 22.241871] Freezing remaining freezable tasks
11254 12:00:58.451802 <6>[ 22.247857] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11255 12:00:58.458372 <6>[ 22.255529] printk: Suspending console(s) (use no_console_suspend to debug)
11256 12:01:01.846744 <3>[ 25.420941] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11257 12:01:01.856576 <3>[ 25.420972] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11258 12:01:01.866738 <3>[ 25.421022] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11259 12:01:01.873193 <3>[ 25.421059] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11260 12:01:01.879936 <3>[ 25.421354] PM: Some devices failed to suspend, or early wake event detected
11261 12:01:01.886864 <4>[ 25.435819] typec port0-partner: PM: parent port0 should not be sleeping
11262 12:01:01.893708 <6>[ 25.693293] OOM killer enabled.
11263 12:01:01.896758 <6>[ 25.696706] Restarting tasks ... done.
11264 12:01:01.903733 <5>[ 25.702872] random: crng reseeded on system resumption
11265 12:01:01.907202 <6>[ 25.709547] PM: suspend exit
11266 12:01:01.909965 rtcwake: write error
11267 12:01:01.917079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11268 12:01:01.917973 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11270 12:01:01.920562 rtcwake: assuming RTC uses UTC ...
11271 12:01:01.927101 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:58:56 2023
11272 12:01:01.939738 <6>[ 25.739506] PM: suspend entry (deep)
11273 12:01:01.943327 <6>[ 25.743427] Filesystems sync: 0.000 seconds
11274 12:01:01.946557 <6>[ 25.748458] Freezing user space processes
11275 12:01:01.958186 <6>[ 25.754547] Freezing user space processes completed (elapsed 0.001 seconds)
11276 12:01:01.961087 <6>[ 25.761780] OOM killer disabled.
11277 12:01:01.964813 <6>[ 25.765263] Freezing remaining freezable tasks
11278 12:01:01.975103 <6>[ 25.771343] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11279 12:01:01.981217 <6>[ 25.779028] printk: Suspending console(s) (use no_console_suspend to debug)
11280 12:01:05.438876 <3>[ 29.005104] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11281 12:01:05.448949 <3>[ 29.005212] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11282 12:01:05.459569 <3>[ 29.005257] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11283 12:01:05.465638 <3>[ 29.005297] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11284 12:01:05.472470 <3>[ 29.005538] PM: Some devices failed to suspend, or early wake event detected
11285 12:01:05.476186 <6>[ 29.278911] OOM killer enabled.
11286 12:01:05.484510 <6>[ 29.282321] Restarting tasks ... done.
11287 12:01:05.487906 <5>[ 29.288380] random: crng reseeded on system resumption
11288 12:01:05.490751 <6>[ 29.294543] PM: suspend exit
11289 12:01:05.494315 rtcwake: write error
11290 12:01:05.502867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11291 12:01:05.503843 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11293 12:01:05.506123 rtcwake: assuming RTC uses UTC ...
11294 12:01:05.512418 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:58:59 2023
11295 12:01:05.526100 <6>[ 29.325970] PM: suspend entry (deep)
11296 12:01:05.529216 <6>[ 29.329880] Filesystems sync: 0.000 seconds
11297 12:01:05.532405 <6>[ 29.334918] Freezing user space processes
11298 12:01:05.544381 <6>[ 29.340830] Freezing user space processes completed (elapsed 0.001 seconds)
11299 12:01:05.547682 <6>[ 29.348048] OOM killer disabled.
11300 12:01:05.551033 <6>[ 29.351526] Freezing remaining freezable tasks
11301 12:01:05.560589 <6>[ 29.357497] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11302 12:01:05.567240 <6>[ 29.365151] printk: Suspending console(s) (use no_console_suspend to debug)
11303 12:01:09.013817 <3>[ 32.588938] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11304 12:01:09.023718 <3>[ 32.588968] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11305 12:01:09.033885 <3>[ 32.589012] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11306 12:01:09.040454 <3>[ 32.589052] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11307 12:01:09.047181 <3>[ 32.589338] PM: Some devices failed to suspend, or early wake event detected
11308 12:01:09.050357 <6>[ 32.854706] OOM killer enabled.
11309 12:01:09.059562 <6>[ 32.858117] Restarting tasks ... done.
11310 12:01:09.062649 <5>[ 32.864377] random: crng reseeded on system resumption
11311 12:01:09.068486 <6>[ 32.873014] PM: suspend exit
11312 12:01:09.072270 rtcwake: write error
11313 12:01:09.079392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11314 12:01:09.079657 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11316 12:01:09.083047 rtcwake: assuming RTC uses UTC ...
11317 12:01:09.089442 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:03 2023
11318 12:01:09.102407 <6>[ 32.903161] PM: suspend entry (deep)
11319 12:01:09.105573 <6>[ 32.907058] Filesystems sync: 0.000 seconds
11320 12:01:09.109054 <6>[ 32.912092] Freezing user space processes
11321 12:01:09.120230 <6>[ 32.918092] Freezing user space processes completed (elapsed 0.001 seconds)
11322 12:01:09.123781 <6>[ 32.925345] OOM killer disabled.
11323 12:01:09.126739 <6>[ 32.928833] Freezing remaining freezable tasks
11324 12:01:09.137323 <6>[ 32.934946] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11325 12:01:09.143765 <6>[ 32.942620] printk: Suspending console(s) (use no_console_suspend to debug)
11326 12:01:12.601757 <3>[ 36.172947] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11327 12:01:12.611998 <3>[ 36.172978] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11328 12:01:12.621285 <3>[ 36.173020] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11329 12:01:12.628626 <3>[ 36.173060] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11330 12:01:12.635082 <3>[ 36.173370] PM: Some devices failed to suspend, or early wake event detected
11331 12:01:12.641488 <6>[ 36.442947] OOM killer enabled.
11332 12:01:12.644911 <6>[ 36.446360] Restarting tasks ... done.
11333 12:01:12.652166 <5>[ 36.453919] random: crng reseeded on system resumption
11334 12:01:12.656247 <6>[ 36.460516] PM: suspend exit
11335 12:01:12.659023 rtcwake: write error
11336 12:01:12.666966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11337 12:01:12.667232 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11339 12:01:12.670476 rtcwake: assuming RTC uses UTC ...
11340 12:01:12.677084 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:06 2023
11341 12:01:12.689491 <6>[ 36.491154] PM: suspend entry (deep)
11342 12:01:12.692890 <6>[ 36.495043] Filesystems sync: 0.000 seconds
11343 12:01:12.696476 <6>[ 36.500123] Freezing user space processes
11344 12:01:12.708124 <6>[ 36.506139] Freezing user space processes completed (elapsed 0.001 seconds)
11345 12:01:12.711750 <6>[ 36.513368] OOM killer disabled.
11346 12:01:12.715043 <6>[ 36.516853] Freezing remaining freezable tasks
11347 12:01:12.724649 <6>[ 36.522892] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11348 12:01:12.731273 <6>[ 36.530565] printk: Suspending console(s) (use no_console_suspend to debug)
11349 12:01:16.189136 <3>[ 39.757007] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11350 12:01:16.199033 <3>[ 39.757047] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11351 12:01:16.209003 <3>[ 39.757094] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11352 12:01:16.215553 <3>[ 39.757148] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11353 12:01:16.225228 <3>[ 39.757466] PM: Some devices failed to suspend, or early wake event detected
11354 12:01:16.228504 <6>[ 40.030792] OOM killer enabled.
11355 12:01:16.231828 <6>[ 40.034203] Restarting tasks ... done.
11356 12:01:16.240273 <5>[ 40.041713] random: crng reseeded on system resumption
11357 12:01:16.243111 <6>[ 40.047966] PM: suspend exit
11358 12:01:16.246338 rtcwake: write error
11359 12:01:16.254255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11360 12:01:16.254518 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11362 12:01:16.257234 rtcwake: assuming RTC uses UTC ...
11363 12:01:16.263628 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:10 2023
11364 12:01:16.276538 <6>[ 40.078469] PM: suspend entry (deep)
11365 12:01:16.280188 <6>[ 40.082367] Filesystems sync: 0.000 seconds
11366 12:01:16.283085 <6>[ 40.087446] Freezing user space processes
11367 12:01:16.294978 <6>[ 40.093311] Freezing user space processes completed (elapsed 0.001 seconds)
11368 12:01:16.298336 <6>[ 40.100534] OOM killer disabled.
11369 12:01:16.301481 <6>[ 40.104012] Freezing remaining freezable tasks
11370 12:01:16.311400 <6>[ 40.110163] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11371 12:01:16.318189 <6>[ 40.117838] printk: Suspending console(s) (use no_console_suspend to debug)
11372 12:01:19.769023 <3>[ 43.340945] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11373 12:01:19.779036 <3>[ 43.340978] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11374 12:01:19.788645 <3>[ 43.341021] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11375 12:01:19.795373 <3>[ 43.341066] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11376 12:01:19.805506 <3>[ 43.341263] PM: Some devices failed to suspend, or early wake event detected
11377 12:01:19.808690 <6>[ 43.611064] OOM killer enabled.
11378 12:01:19.811992 <6>[ 43.614474] Restarting tasks ... done.
11379 12:01:19.819786 <5>[ 43.621952] random: crng reseeded on system resumption
11380 12:01:19.824164 <6>[ 43.629628] PM: suspend exit
11381 12:01:19.827314 rtcwake: write error
11382 12:01:19.835921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11383 12:01:19.836684 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11385 12:01:19.839302 rtcwake: assuming RTC uses UTC ...
11386 12:01:19.845693 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:14 2023
11387 12:01:19.858485 <6>[ 43.660544] PM: suspend entry (deep)
11388 12:01:19.861769 <6>[ 43.664426] Filesystems sync: 0.000 seconds
11389 12:01:19.864953 <6>[ 43.669475] Freezing user space processes
11390 12:01:19.876921 <6>[ 43.675487] Freezing user space processes completed (elapsed 0.001 seconds)
11391 12:01:19.879978 <6>[ 43.682721] OOM killer disabled.
11392 12:01:19.883355 <6>[ 43.686204] Freezing remaining freezable tasks
11393 12:01:19.893592 <6>[ 43.692267] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11394 12:01:19.899878 <6>[ 43.699943] printk: Suspending console(s) (use no_console_suspend to debug)
11395 12:01:23.352060 <3>[ 46.925003] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11396 12:01:23.362021 <3>[ 46.925040] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11397 12:01:23.372143 <3>[ 46.925084] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11398 12:01:23.378566 <3>[ 46.925126] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11399 12:01:23.385557 <3>[ 46.925331] PM: Some devices failed to suspend, or early wake event detected
11400 12:01:23.388994 <6>[ 47.194896] OOM killer enabled.
11401 12:01:23.397339 <6>[ 47.198308] Restarting tasks ... done.
11402 12:01:23.404340 <5>[ 47.205633] random: crng reseeded on system resumption
11403 12:01:23.407780 <6>[ 47.211988] PM: suspend exit
11404 12:01:23.410922 rtcwake: write error
11405 12:01:23.417390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11406 12:01:23.417634 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11408 12:01:23.420685 rtcwake: assuming RTC uses UTC ...
11409 12:01:23.427570 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:17 2023
11410 12:01:23.440094 <6>[ 47.242693] PM: suspend entry (deep)
11411 12:01:23.443648 <6>[ 47.246586] Filesystems sync: 0.000 seconds
11412 12:01:23.447166 <6>[ 47.251662] Freezing user space processes
11413 12:01:23.458424 <6>[ 47.257530] Freezing user space processes completed (elapsed 0.001 seconds)
11414 12:01:23.461564 <6>[ 47.264761] OOM killer disabled.
11415 12:01:23.465212 <6>[ 47.268238] Freezing remaining freezable tasks
11416 12:01:23.474800 <6>[ 47.274288] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11417 12:01:23.481525 <6>[ 47.281966] printk: Suspending console(s) (use no_console_suspend to debug)
11418 12:01:26.928851 <6>[ 48.205094] vpu: disabling
11419 12:01:26.932126 <6>[ 48.205259] vproc2: disabling
11420 12:01:26.935196 <6>[ 48.205313] vproc1: disabling
11421 12:01:26.938672 <6>[ 48.205367] vaud18: disabling
11422 12:01:26.941618 <6>[ 48.205610] vsram_others: disabling
11423 12:01:26.944858 <6>[ 48.205804] va09: disabling
11424 12:01:26.948495 <6>[ 48.205880] vsram_md: disabling
11425 12:01:26.952119 <6>[ 48.206007] Vgpu: disabling
11426 12:01:26.958888 <3>[ 50.508966] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11427 12:01:26.968133 <3>[ 50.509006] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11428 12:01:26.979027 <3>[ 50.509054] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11429 12:01:26.985425 <3>[ 50.509097] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11430 12:01:26.991669 <3>[ 50.509393] PM: Some devices failed to suspend, or early wake event detected
11431 12:01:26.995529 <6>[ 50.800742] OOM killer enabled.
11432 12:01:27.002872 <6>[ 50.804140] Restarting tasks ... done.
11433 12:01:27.009886 <5>[ 50.811101] random: crng reseeded on system resumption
11434 12:01:27.012795 <6>[ 50.817542] PM: suspend exit
11435 12:01:27.012875 rtcwake: write error
11436 12:01:27.021855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11437 12:01:27.022115 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11439 12:01:27.025286 rtcwake: assuming RTC uses UTC ...
11440 12:01:27.032391 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:21 2023
11441 12:01:27.044552 <6>[ 50.847711] PM: suspend entry (deep)
11442 12:01:27.048207 <6>[ 50.851604] Filesystems sync: 0.000 seconds
11443 12:01:27.051039 <6>[ 50.856637] Freezing user space processes
11444 12:01:27.062691 <6>[ 50.862561] Freezing user space processes completed (elapsed 0.001 seconds)
11445 12:01:27.066539 <6>[ 50.869796] OOM killer disabled.
11446 12:01:27.069505 <6>[ 50.873278] Freezing remaining freezable tasks
11447 12:01:27.079898 <6>[ 50.879291] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11448 12:01:27.086260 <6>[ 50.886959] printk: Suspending console(s) (use no_console_suspend to debug)
11449 12:01:30.519916 <3>[ 54.092948] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11450 12:01:30.529783 <3>[ 54.092981] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11451 12:01:30.540058 <3>[ 54.093023] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11452 12:01:30.545983 <3>[ 54.093064] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11453 12:01:30.552577 <3>[ 54.093311] PM: Some devices failed to suspend, or early wake event detected
11454 12:01:30.559351 <6>[ 54.363067] OOM killer enabled.
11455 12:01:30.562756 <6>[ 54.366479] Restarting tasks ... done.
11456 12:01:30.570491 <5>[ 54.373916] random: crng reseeded on system resumption
11457 12:01:30.574004 <6>[ 54.380257] PM: suspend exit
11458 12:01:30.577163 rtcwake: write error
11459 12:01:30.584486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11460 12:01:30.584748 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11462 12:01:30.588148 rtcwake: assuming RTC uses UTC ...
11463 12:01:30.594699 rtcwake: wakeup from "mem" using rtc0 at Thu Nov 23 11:59:24 2023
11464 12:01:30.607157 <6>[ 54.410861] PM: suspend entry (deep)
11465 12:01:30.610596 <6>[ 54.414751] Filesystems sync: 0.000 seconds
11466 12:01:30.614024 <6>[ 54.419807] Freezing user space processes
11467 12:01:30.625809 <6>[ 54.425663] Freezing user space processes completed (elapsed 0.001 seconds)
11468 12:01:30.628969 <6>[ 54.432881] OOM killer disabled.
11469 12:01:30.632282 <6>[ 54.436358] Freezing remaining freezable tasks
11470 12:01:30.642158 <6>[ 54.442240] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11471 12:01:30.648930 <6>[ 54.449894] printk: Suspending console(s) (use no_console_suspend to debug)
11472 12:01:34.107180 <3>[ 57.676979] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11473 12:01:34.116873 <3>[ 57.677011] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11474 12:01:34.127403 <3>[ 57.677054] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11475 12:01:34.133493 <3>[ 57.677095] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11476 12:01:34.140759 <3>[ 57.677380] PM: Some devices failed to suspend, or early wake event detected
11477 12:01:34.143992 <6>[ 57.950794] OOM killer enabled.
11478 12:01:34.151977 <6>[ 57.954205] Restarting tasks ... done.
11479 12:01:34.158843 <5>[ 57.961648] random: crng reseeded on system resumption
11480 12:01:34.162045 <6>[ 57.969410] PM: suspend exit
11481 12:01:34.165342 rtcwake: write error
11482 12:01:34.173707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11483 12:01:34.174000 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11485 12:01:34.176975 rtcwake: assuming RTC uses UTC ...
11486 12:01:34.183429 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:28 2023
11487 12:01:34.197449 <6>[ 58.001464] PM: suspend entry (s2idle)
11488 12:01:34.201138 <6>[ 58.005536] Filesystems sync: 0.000 seconds
11489 12:01:34.207508 <6>[ 58.010599] Freezing user space processes
11490 12:01:34.214176 <6>[ 58.016522] Freezing user space processes completed (elapsed 0.001 seconds)
11491 12:01:34.217999 <6>[ 58.023753] OOM killer disabled.
11492 12:01:34.224302 <6>[ 58.027234] Freezing remaining freezable tasks
11493 12:01:34.230926 <6>[ 58.033209] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11494 12:01:34.237423 <6>[ 58.040861] printk: Suspending console(s) (use no_console_suspend to debug)
11495 12:01:37.686883 <3>[ 61.260945] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11496 12:01:37.697124 <3>[ 61.260977] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11497 12:01:37.707508 <3>[ 61.261021] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11498 12:01:37.713892 <3>[ 61.261061] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11499 12:01:37.720320 <3>[ 61.261375] PM: Some devices failed to suspend, or early wake event detected
11500 12:01:37.723708 <6>[ 61.530967] OOM killer enabled.
11501 12:01:37.731966 <6>[ 61.534385] Restarting tasks ... done.
11502 12:01:37.738441 <5>[ 61.541854] random: crng reseeded on system resumption
11503 12:01:37.741761 <6>[ 61.549311] PM: suspend exit
11504 12:01:37.744986 rtcwake: write error
11505 12:01:37.753373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11506 12:01:37.753677 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11508 12:01:37.756305 rtcwake: assuming RTC uses UTC ...
11509 12:01:37.763356 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:31 2023
11510 12:01:37.776034 <6>[ 61.580318] PM: suspend entry (s2idle)
11511 12:01:37.779696 <6>[ 61.584375] Filesystems sync: 0.000 seconds
11512 12:01:37.782562 <6>[ 61.589423] Freezing user space processes
11513 12:01:37.794133 <6>[ 61.595341] Freezing user space processes completed (elapsed 0.001 seconds)
11514 12:01:37.798005 <6>[ 61.602574] OOM killer disabled.
11515 12:01:37.801264 <6>[ 61.606056] Freezing remaining freezable tasks
11516 12:01:37.811445 <6>[ 61.612069] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11517 12:01:37.817476 <6>[ 61.619744] printk: Suspending console(s) (use no_console_suspend to debug)
11518 12:01:41.274435 <3>[ 64.845013] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11519 12:01:41.284626 <3>[ 64.845063] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11520 12:01:41.294747 <3>[ 64.845116] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11521 12:01:41.301040 <3>[ 64.845167] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11522 12:01:41.307640 <3>[ 64.845440] PM: Some devices failed to suspend, or early wake event detected
11523 12:01:41.311041 <6>[ 65.118953] OOM killer enabled.
11524 12:01:41.319715 <6>[ 65.122370] Restarting tasks ... done.
11525 12:01:41.326611 <5>[ 65.130224] random: crng reseeded on system resumption
11526 12:01:41.329937 <6>[ 65.136699] PM: suspend exit
11527 12:01:41.333130 rtcwake: write error
11528 12:01:41.339950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11529 12:01:41.340225 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11531 12:01:41.343194 rtcwake: assuming RTC uses UTC ...
11532 12:01:41.349564 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:35 2023
11533 12:01:41.362369 <6>[ 65.167172] PM: suspend entry (s2idle)
11534 12:01:41.366096 <6>[ 65.171241] Filesystems sync: 0.000 seconds
11535 12:01:41.369339 <6>[ 65.176259] Freezing user space processes
11536 12:01:41.380796 <6>[ 65.182296] Freezing user space processes completed (elapsed 0.001 seconds)
11537 12:01:41.384083 <6>[ 65.189536] OOM killer disabled.
11538 12:01:41.387827 <6>[ 65.193027] Freezing remaining freezable tasks
11539 12:01:41.397520 <6>[ 65.199132] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11540 12:01:41.404460 <6>[ 65.206805] printk: Suspending console(s) (use no_console_suspend to debug)
11541 12:01:44.853920 <3>[ 68.428935] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11542 12:01:44.863783 <3>[ 68.428966] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11543 12:01:44.873761 <3>[ 68.429009] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11544 12:01:44.880796 <3>[ 68.429054] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11545 12:01:44.887256 <3>[ 68.429246] PM: Some devices failed to suspend, or early wake event detected
11546 12:01:44.893887 <6>[ 68.698710] OOM killer enabled.
11547 12:01:44.896765 <6>[ 68.702121] Restarting tasks ... done.
11548 12:01:44.904019 <5>[ 68.709324] random: crng reseeded on system resumption
11549 12:01:44.907809 <6>[ 68.716070] PM: suspend exit
11550 12:01:44.911208 rtcwake: write error
11551 12:01:44.918565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11552 12:01:44.918829 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11554 12:01:44.921875 rtcwake: assuming RTC uses UTC ...
11555 12:01:44.928497 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:39 2023
11556 12:01:44.941549 <6>[ 68.746453] PM: suspend entry (s2idle)
11557 12:01:44.945051 <6>[ 68.750517] Filesystems sync: 0.000 seconds
11558 12:01:44.951265 <6>[ 68.755539] Freezing user space processes
11559 12:01:44.958171 <6>[ 68.761347] Freezing user space processes completed (elapsed 0.001 seconds)
11560 12:01:44.961410 <6>[ 68.768565] OOM killer disabled.
11561 12:01:44.968249 <6>[ 68.772045] Freezing remaining freezable tasks
11562 12:01:44.974517 <6>[ 68.778073] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11563 12:01:44.981463 <6>[ 68.785742] printk: Suspending console(s) (use no_console_suspend to debug)
11564 12:01:48.442513 <3>[ 72.012943] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11565 12:01:48.452666 <3>[ 72.012974] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11566 12:01:48.462044 <3>[ 72.013018] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11567 12:01:48.468928 <3>[ 72.013060] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11568 12:01:48.475280 <3>[ 72.013373] PM: Some devices failed to suspend, or early wake event detected
11569 12:01:48.478570 <6>[ 72.286949] OOM killer enabled.
11570 12:01:48.486768 <6>[ 72.290360] Restarting tasks ... done.
11571 12:01:48.493864 <5>[ 72.297422] random: crng reseeded on system resumption
11572 12:01:48.498126 <6>[ 72.304669] PM: suspend exit
11573 12:01:48.501312 rtcwake: write error
11574 12:01:48.507219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11575 12:01:48.508083 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11577 12:01:48.510868 rtcwake: assuming RTC uses UTC ...
11578 12:01:48.517069 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:42 2023
11579 12:01:48.529764 <6>[ 72.334527] PM: suspend entry (s2idle)
11580 12:01:48.533343 <6>[ 72.338598] Filesystems sync: 0.000 seconds
11581 12:01:48.540067 <6>[ 72.343654] Freezing user space processes
11582 12:01:48.546626 <6>[ 72.349459] Freezing user space processes completed (elapsed 0.001 seconds)
11583 12:01:48.550170 <6>[ 72.356680] OOM killer disabled.
11584 12:01:48.556193 <6>[ 72.360156] Freezing remaining freezable tasks
11585 12:01:48.562917 <6>[ 72.366166] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11586 12:01:48.569235 <6>[ 72.373835] printk: Suspending console(s) (use no_console_suspend to debug)
11587 12:01:52.021651 <3>[ 75.596964] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11588 12:01:52.031403 <3>[ 75.597002] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11589 12:01:52.041555 <3>[ 75.597051] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11590 12:01:52.047788 <3>[ 75.597102] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11591 12:01:52.055028 <3>[ 75.597386] PM: Some devices failed to suspend, or early wake event detected
11592 12:01:52.058078 <6>[ 75.866722] OOM killer enabled.
11593 12:01:52.066248 <6>[ 75.870134] Restarting tasks ... done.
11594 12:01:52.072997 <5>[ 75.877525] random: crng reseeded on system resumption
11595 12:01:52.076207 <6>[ 75.883768] PM: suspend exit
11596 12:01:52.079826 rtcwake: write error
11597 12:01:52.086215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11598 12:01:52.087044 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11600 12:01:52.089875 rtcwake: assuming RTC uses UTC ...
11601 12:01:52.096493 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:46 2023
11602 12:01:52.108585 <6>[ 75.914160] PM: suspend entry (s2idle)
11603 12:01:52.111751 <6>[ 75.918224] Filesystems sync: 0.000 seconds
11604 12:01:52.115537 <6>[ 75.923280] Freezing user space processes
11605 12:01:52.126787 <6>[ 75.928789] Freezing user space processes completed (elapsed 0.001 seconds)
11606 12:01:52.129779 <6>[ 75.936006] OOM killer disabled.
11607 12:01:52.132826 <6>[ 75.939486] Freezing remaining freezable tasks
11608 12:01:52.143564 <6>[ 75.945416] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11609 12:01:52.149747 <6>[ 75.953067] printk: Suspending console(s) (use no_console_suspend to debug)
11610 12:01:55.608693 <3>[ 79.180941] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11611 12:01:55.619446 <3>[ 79.180973] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11612 12:01:55.629127 <3>[ 79.181016] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11613 12:01:55.635367 <3>[ 79.181056] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11614 12:01:55.642214 <3>[ 79.181353] PM: Some devices failed to suspend, or early wake event detected
11615 12:01:55.645731 <6>[ 79.454972] OOM killer enabled.
11616 12:01:55.653616 <6>[ 79.458384] Restarting tasks ... done.
11617 12:01:55.660452 <5>[ 79.465571] random: crng reseeded on system resumption
11618 12:01:55.663974 <6>[ 79.472310] PM: suspend exit
11619 12:01:55.666866 rtcwake: write error
11620 12:01:55.673955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11621 12:01:55.674220 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11623 12:01:55.676609 rtcwake: assuming RTC uses UTC ...
11624 12:01:55.683265 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:49 2023
11625 12:01:55.696214 <6>[ 79.502331] PM: suspend entry (s2idle)
11626 12:01:55.699200 <6>[ 79.506394] Filesystems sync: 0.000 seconds
11627 12:01:55.702488 <6>[ 79.511440] Freezing user space processes
11628 12:01:55.714015 <6>[ 79.517276] Freezing user space processes completed (elapsed 0.001 seconds)
11629 12:01:55.718039 <6>[ 79.524495] OOM killer disabled.
11630 12:01:55.721313 <6>[ 79.527977] Freezing remaining freezable tasks
11631 12:01:55.731376 <6>[ 79.534116] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11632 12:01:55.737653 <6>[ 79.541786] printk: Suspending console(s) (use no_console_suspend to debug)
11633 12:01:59.188154 <3>[ 82.764936] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11634 12:01:59.198356 <3>[ 82.764966] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11635 12:01:59.208418 <3>[ 82.765010] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11636 12:01:59.215559 <3>[ 82.765051] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11637 12:01:59.221962 <3>[ 82.765292] PM: Some devices failed to suspend, or early wake event detected
11638 12:01:59.224901 <6>[ 83.034955] OOM killer enabled.
11639 12:01:59.235854 <6>[ 83.038367] Restarting tasks ... done.
11640 12:01:59.242080 <5>[ 83.047171] random: crng reseeded on system resumption
11641 12:01:59.246072 <6>[ 83.054597] PM: suspend exit
11642 12:01:59.249093 rtcwake: write error
11643 12:01:59.255807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11644 12:01:59.256073 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11646 12:01:59.258496 rtcwake: assuming RTC uses UTC ...
11647 12:01:59.265368 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:53 2023
11648 12:01:59.278278 <6>[ 83.084827] PM: suspend entry (s2idle)
11649 12:01:59.281473 <6>[ 83.088909] Filesystems sync: 0.000 seconds
11650 12:01:59.288421 <6>[ 83.093997] Freezing user space processes
11651 12:01:59.294579 <6>[ 83.099896] Freezing user space processes completed (elapsed 0.001 seconds)
11652 12:01:59.298224 <6>[ 83.107131] OOM killer disabled.
11653 12:01:59.305013 <6>[ 83.110613] Freezing remaining freezable tasks
11654 12:01:59.311833 <6>[ 83.116644] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11655 12:01:59.321141 <6>[ 83.124305] printk: Suspending console(s) (use no_console_suspend to debug)
11656 12:02:02.776246 <3>[ 86.348933] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11657 12:02:02.785776 <3>[ 86.348964] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11658 12:02:02.795835 <3>[ 86.349008] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11659 12:02:02.802675 <3>[ 86.349049] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11660 12:02:02.809457 <3>[ 86.349339] PM: Some devices failed to suspend, or early wake event detected
11661 12:02:02.812303 <6>[ 86.622960] OOM killer enabled.
11662 12:02:02.820958 <6>[ 86.626373] Restarting tasks ... done.
11663 12:02:02.827606 <5>[ 86.633888] random: crng reseeded on system resumption
11664 12:02:02.831056 <6>[ 86.640133] PM: suspend exit
11665 12:02:02.834946 rtcwake: write error
11666 12:02:02.841135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11667 12:02:02.841425 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11669 12:02:02.844555 rtcwake: assuming RTC uses UTC ...
11670 12:02:02.851271 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 11:59:57 2023
11671 12:02:02.863168 <6>[ 86.670515] PM: suspend entry (s2idle)
11672 12:02:02.866875 <6>[ 86.674581] Filesystems sync: 0.000 seconds
11673 12:02:02.873345 <6>[ 86.679637] Freezing user space processes
11674 12:02:02.879953 <6>[ 86.685449] Freezing user space processes completed (elapsed 0.001 seconds)
11675 12:02:02.883756 <6>[ 86.692666] OOM killer disabled.
11676 12:02:02.889765 <6>[ 86.696141] Freezing remaining freezable tasks
11677 12:02:02.896616 <6>[ 86.702163] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11678 12:02:02.903562 <6>[ 86.709829] printk: Suspending console(s) (use no_console_suspend to debug)
11679 12:02:06.360000 <3>[ 89.932966] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11680 12:02:06.369378 <3>[ 89.933007] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11681 12:02:06.379934 <3>[ 89.933056] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11682 12:02:06.386517 <3>[ 89.933107] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11683 12:02:06.393383 <3>[ 89.933520] PM: Some devices failed to suspend, or early wake event detected
11684 12:02:06.396361 <6>[ 90.206972] OOM killer enabled.
11685 12:02:06.404519 <6>[ 90.210385] Restarting tasks ... done.
11686 12:02:06.407684 <5>[ 90.216255] random: crng reseeded on system resumption
11687 12:02:06.411560 <6>[ 90.222525] PM: suspend exit
11688 12:02:06.414909 rtcwake: write error
11689 12:02:06.422481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11690 12:02:06.422741 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11692 12:02:06.426159 rtcwake: assuming RTC uses UTC ...
11693 12:02:06.432303 rtcwake: wakeup from "freeze" using rtc0 at Thu Nov 23 12:00:00 2023
11694 12:02:06.445309 <6>[ 90.252693] PM: suspend entry (s2idle)
11695 12:02:06.448816 <6>[ 90.256790] Filesystems sync: 0.000 seconds
11696 12:02:06.451952 <6>[ 90.261823] Freezing user space processes
11697 12:02:06.463450 <6>[ 90.267711] Freezing user space processes completed (elapsed 0.001 seconds)
11698 12:02:06.466957 <6>[ 90.274947] OOM killer disabled.
11699 12:02:06.469871 <6>[ 90.278431] Freezing remaining freezable tasks
11700 12:02:06.480107 <6>[ 90.284452] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11701 12:02:06.486914 <6>[ 90.292123] printk: Suspending console(s) (use no_console_suspend to debug)
11702 12:02:09.943930 <3>[ 93.517001] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11703 12:02:09.953839 <3>[ 93.517033] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11704 12:02:09.963569 <3>[ 93.517075] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11705 12:02:09.970351 <3>[ 93.517115] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11706 12:02:09.980363 <3>[ 93.517419] PM: Some devices failed to suspend, or early wake event detected
11707 12:02:09.983213 <6>[ 93.791050] OOM killer enabled.
11708 12:02:09.987154 <6>[ 93.794466] Restarting tasks ... done.
11709 12:02:09.993422 <5>[ 93.800353] random: crng reseeded on system resumption
11710 12:02:09.996617 <6>[ 93.807144] PM: suspend exit
11711 12:02:10.000112 rtcwake: write error
11712 12:02:10.007798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11713 12:02:10.008342 + set +x
11714 12:02:10.009002 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11716 12:02:10.014297 <LAVA_SIGNAL_ENDRUN 0_sleep 12066560_1.5.2.3.1>
11717 12:02:10.014784 <LAVA_TEST_RUNNER EXIT>
11718 12:02:10.015419 Received signal: <ENDRUN> 0_sleep 12066560_1.5.2.3.1
11719 12:02:10.015846 Ending use of test pattern.
11720 12:02:10.016191 Ending test lava.0_sleep (12066560_1.5.2.3.1), duration 71.63
11722 12:02:10.017414 ok: lava_test_shell seems to have completed
11723 12:02:10.018488 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11724 12:02:10.018976 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11725 12:02:10.019442 end: 3 lava-test-retry (duration 00:01:12) [common]
11726 12:02:10.019914 start: 4 finalize (timeout 00:06:17) [common]
11727 12:02:10.020392 start: 4.1 power-off (timeout 00:00:30) [common]
11728 12:02:10.021200 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11729 12:02:10.146155 >> Command sent successfully.
11730 12:02:10.158265 Returned 0 in 0 seconds
11731 12:02:10.259665 end: 4.1 power-off (duration 00:00:00) [common]
11733 12:02:10.261513 start: 4.2 read-feedback (timeout 00:06:16) [common]
11734 12:02:10.263093 Listened to connection for namespace 'common' for up to 1s
11735 12:02:11.263507 Finalising connection for namespace 'common'
11736 12:02:11.264160 Disconnecting from shell: Finalise
11737 12:02:11.264570 / #
11738 12:02:11.365534 end: 4.2 read-feedback (duration 00:00:01) [common]
11739 12:02:11.366283 end: 4 finalize (duration 00:00:01) [common]
11740 12:02:11.366891 Cleaning after the job
11741 12:02:11.367405 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/ramdisk
11742 12:02:11.412603 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/kernel
11743 12:02:11.441239 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/dtb
11744 12:02:11.441459 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066560/tftp-deploy-3c0cps04/modules
11745 12:02:11.448746 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066560
11746 12:02:11.619164 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066560
11747 12:02:11.619343 Job finished correctly