Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 21
- Boot result: FAIL
- Errors: 3
1 11:56:50.991233 lava-dispatcher, installed at version: 2023.10
2 11:56:50.991434 start: 0 validate
3 11:56:50.991564 Start time: 2023-11-23 11:56:50.991557+00:00 (UTC)
4 11:56:50.991682 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:56:50.991813 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:56:51.264198 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:56:51.265005 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:56:51.534371 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:56:51.535176 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:56:51.807516 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:56:51.808287 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:56:52.076478 validate duration: 1.08
14 11:56:52.077845 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:56:52.078379 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:56:52.078868 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:56:52.079545 Not decompressing ramdisk as can be used compressed.
18 11:56:52.080050 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 11:56:52.080411 saving as /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/ramdisk/rootfs.cpio.gz
20 11:56:52.080836 total size: 26246609 (25 MB)
21 11:56:52.086461 progress 0 % (0 MB)
22 11:56:52.115649 progress 5 % (1 MB)
23 11:56:52.128143 progress 10 % (2 MB)
24 11:56:52.137299 progress 15 % (3 MB)
25 11:56:52.145000 progress 20 % (5 MB)
26 11:56:52.151850 progress 25 % (6 MB)
27 11:56:52.158678 progress 30 % (7 MB)
28 11:56:52.165313 progress 35 % (8 MB)
29 11:56:52.171993 progress 40 % (10 MB)
30 11:56:52.178810 progress 45 % (11 MB)
31 11:56:52.185811 progress 50 % (12 MB)
32 11:56:52.192625 progress 55 % (13 MB)
33 11:56:52.199271 progress 60 % (15 MB)
34 11:56:52.205967 progress 65 % (16 MB)
35 11:56:52.212653 progress 70 % (17 MB)
36 11:56:52.219505 progress 75 % (18 MB)
37 11:56:52.226229 progress 80 % (20 MB)
38 11:56:52.232987 progress 85 % (21 MB)
39 11:56:52.239599 progress 90 % (22 MB)
40 11:56:52.246253 progress 95 % (23 MB)
41 11:56:52.252896 progress 100 % (25 MB)
42 11:56:52.253144 25 MB downloaded in 0.17 s (145.25 MB/s)
43 11:56:52.253340 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:56:52.253575 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:56:52.253660 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:56:52.253742 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:56:52.253880 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:56:52.253950 saving as /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/kernel/Image
50 11:56:52.254008 total size: 49107456 (46 MB)
51 11:56:52.254096 No compression specified
52 11:56:52.255272 progress 0 % (0 MB)
53 11:56:52.267776 progress 5 % (2 MB)
54 11:56:52.280312 progress 10 % (4 MB)
55 11:56:52.293146 progress 15 % (7 MB)
56 11:56:52.305685 progress 20 % (9 MB)
57 11:56:52.318280 progress 25 % (11 MB)
58 11:56:52.330793 progress 30 % (14 MB)
59 11:56:52.343256 progress 35 % (16 MB)
60 11:56:52.355985 progress 40 % (18 MB)
61 11:56:52.368718 progress 45 % (21 MB)
62 11:56:52.381450 progress 50 % (23 MB)
63 11:56:52.394250 progress 55 % (25 MB)
64 11:56:52.406822 progress 60 % (28 MB)
65 11:56:52.419531 progress 65 % (30 MB)
66 11:56:52.432183 progress 70 % (32 MB)
67 11:56:52.444625 progress 75 % (35 MB)
68 11:56:52.457248 progress 80 % (37 MB)
69 11:56:52.469836 progress 85 % (39 MB)
70 11:56:52.482648 progress 90 % (42 MB)
71 11:56:52.495343 progress 95 % (44 MB)
72 11:56:52.507706 progress 100 % (46 MB)
73 11:56:52.507912 46 MB downloaded in 0.25 s (184.45 MB/s)
74 11:56:52.508059 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:56:52.508292 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:56:52.508379 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:56:52.508470 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:56:52.508673 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:56:52.508754 saving as /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/dtb/mt8192-asurada-spherion-r0.dtb
81 11:56:52.508814 total size: 47278 (0 MB)
82 11:56:52.508874 No compression specified
83 11:56:52.510002 progress 69 % (0 MB)
84 11:56:52.510275 progress 100 % (0 MB)
85 11:56:52.510427 0 MB downloaded in 0.00 s (27.98 MB/s)
86 11:56:52.510546 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:56:52.510763 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:56:52.510847 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:56:52.510928 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:56:52.511042 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:56:52.511111 saving as /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/modules/modules.tar
93 11:56:52.511171 total size: 8621364 (8 MB)
94 11:56:52.511237 Using unxz to decompress xz
95 11:56:52.515527 progress 0 % (0 MB)
96 11:56:52.536375 progress 5 % (0 MB)
97 11:56:52.559596 progress 10 % (0 MB)
98 11:56:52.582751 progress 15 % (1 MB)
99 11:56:52.606476 progress 20 % (1 MB)
100 11:56:52.630292 progress 25 % (2 MB)
101 11:56:52.655314 progress 30 % (2 MB)
102 11:56:52.680675 progress 35 % (2 MB)
103 11:56:52.703882 progress 40 % (3 MB)
104 11:56:52.727836 progress 45 % (3 MB)
105 11:56:52.752295 progress 50 % (4 MB)
106 11:56:52.775690 progress 55 % (4 MB)
107 11:56:52.800182 progress 60 % (4 MB)
108 11:56:52.827518 progress 65 % (5 MB)
109 11:56:52.851755 progress 70 % (5 MB)
110 11:56:52.874177 progress 75 % (6 MB)
111 11:56:52.900519 progress 80 % (6 MB)
112 11:56:52.926247 progress 85 % (7 MB)
113 11:56:52.950956 progress 90 % (7 MB)
114 11:56:52.979749 progress 95 % (7 MB)
115 11:56:53.009191 progress 100 % (8 MB)
116 11:56:53.013833 8 MB downloaded in 0.50 s (16.36 MB/s)
117 11:56:53.014076 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:56:53.014331 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:56:53.014424 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:56:53.014538 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:56:53.014641 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:56:53.014736 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:56:53.015076 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2
125 11:56:53.015213 makedir: /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin
126 11:56:53.015342 makedir: /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/tests
127 11:56:53.015456 makedir: /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/results
128 11:56:53.015624 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-add-keys
129 11:56:53.015790 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-add-sources
130 11:56:53.015960 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-background-process-start
131 11:56:53.016124 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-background-process-stop
132 11:56:53.016251 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-common-functions
133 11:56:53.016377 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-echo-ipv4
134 11:56:53.016533 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-install-packages
135 11:56:53.016690 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-installed-packages
136 11:56:53.016815 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-os-build
137 11:56:53.016940 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-probe-channel
138 11:56:53.017064 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-probe-ip
139 11:56:53.017188 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-target-ip
140 11:56:53.017312 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-target-mac
141 11:56:53.017530 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-target-storage
142 11:56:53.017662 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-case
143 11:56:53.017790 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-event
144 11:56:53.017918 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-feedback
145 11:56:53.018044 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-raise
146 11:56:53.018171 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-reference
147 11:56:53.018297 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-runner
148 11:56:53.018422 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-set
149 11:56:53.018550 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-test-shell
150 11:56:53.018679 Updating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-install-packages (oe)
151 11:56:53.018831 Updating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/bin/lava-installed-packages (oe)
152 11:56:53.018954 Creating /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/environment
153 11:56:53.019054 LAVA metadata
154 11:56:53.019127 - LAVA_JOB_ID=12066571
155 11:56:53.019192 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:56:53.019293 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:56:53.019361 skipped lava-vland-overlay
158 11:56:53.019435 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:56:53.019547 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:56:53.019666 skipped lava-multinode-overlay
161 11:56:53.019751 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:56:53.019838 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:56:53.019915 Loading test definitions
164 11:56:53.020006 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:56:53.020080 Using /lava-12066571 at stage 0
166 11:56:53.020387 uuid=12066571_1.5.2.3.1 testdef=None
167 11:56:53.020475 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:56:53.020616 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:56:53.021135 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:56:53.021362 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:56:53.021994 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:56:53.022223 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:56:53.022825 runner path: /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/0/tests/0_v4l2-compliance-uvc test_uuid 12066571_1.5.2.3.1
176 11:56:53.022986 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:56:53.023189 Creating lava-test-runner.conf files
179 11:56:53.023252 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066571/lava-overlay-g3jmuxt2/lava-12066571/0 for stage 0
180 11:56:53.023341 - 0_v4l2-compliance-uvc
181 11:56:53.023437 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:56:53.023523 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:56:53.030289 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:56:53.030396 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:56:53.030480 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:56:53.030563 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:56:53.030652 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:56:53.734990 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:56:53.735371 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:56:53.735484 extracting modules file /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066571/extract-overlay-ramdisk-iorwxi9y/ramdisk
191 11:56:53.966323 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:56:53.966485 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:56:53.966585 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066571/compress-overlay-5d7_8wqo/overlay-1.5.2.4.tar.gz to ramdisk
194 11:56:53.966661 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066571/compress-overlay-5d7_8wqo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066571/extract-overlay-ramdisk-iorwxi9y/ramdisk
195 11:56:53.973409 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:56:53.973524 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:56:53.973615 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:56:53.973705 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:56:53.973786 Building ramdisk /var/lib/lava/dispatcher/tmp/12066571/extract-overlay-ramdisk-iorwxi9y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066571/extract-overlay-ramdisk-iorwxi9y/ramdisk
200 11:56:54.604627 >> 228427 blocks
201 11:56:58.413535 rename /var/lib/lava/dispatcher/tmp/12066571/extract-overlay-ramdisk-iorwxi9y/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/ramdisk/ramdisk.cpio.gz
202 11:56:58.413974 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 11:56:58.414099 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 11:56:58.414270 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 11:56:58.414386 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/kernel/Image'
206 11:57:10.298341 Returned 0 in 11 seconds
207 11:57:10.399418 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/kernel/image.itb
208 11:57:11.041629 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:57:11.042010 output: Created: Thu Nov 23 11:57:10 2023
210 11:57:11.042088 output: Image 0 (kernel-1)
211 11:57:11.042154 output: Description:
212 11:57:11.042218 output: Created: Thu Nov 23 11:57:10 2023
213 11:57:11.042281 output: Type: Kernel Image
214 11:57:11.042340 output: Compression: lzma compressed
215 11:57:11.042397 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
216 11:57:11.042450 output: Architecture: AArch64
217 11:57:11.042503 output: OS: Linux
218 11:57:11.042558 output: Load Address: 0x00000000
219 11:57:11.042612 output: Entry Point: 0x00000000
220 11:57:11.042666 output: Hash algo: crc32
221 11:57:11.042717 output: Hash value: e6d7c86f
222 11:57:11.042773 output: Image 1 (fdt-1)
223 11:57:11.042826 output: Description: mt8192-asurada-spherion-r0
224 11:57:11.042877 output: Created: Thu Nov 23 11:57:10 2023
225 11:57:11.042928 output: Type: Flat Device Tree
226 11:57:11.042979 output: Compression: uncompressed
227 11:57:11.043049 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:57:11.043113 output: Architecture: AArch64
229 11:57:11.043163 output: Hash algo: crc32
230 11:57:11.043214 output: Hash value: cc4352de
231 11:57:11.043265 output: Image 2 (ramdisk-1)
232 11:57:11.043316 output: Description: unavailable
233 11:57:11.043367 output: Created: Thu Nov 23 11:57:10 2023
234 11:57:11.043418 output: Type: RAMDisk Image
235 11:57:11.043469 output: Compression: Unknown Compression
236 11:57:11.043519 output: Data Size: 39374523 Bytes = 38451.68 KiB = 37.55 MiB
237 11:57:11.043570 output: Architecture: AArch64
238 11:57:11.043621 output: OS: Linux
239 11:57:11.043671 output: Load Address: unavailable
240 11:57:11.043722 output: Entry Point: unavailable
241 11:57:11.043772 output: Hash algo: crc32
242 11:57:11.043822 output: Hash value: b4309809
243 11:57:11.043873 output: Default Configuration: 'conf-1'
244 11:57:11.043923 output: Configuration 0 (conf-1)
245 11:57:11.043974 output: Description: mt8192-asurada-spherion-r0
246 11:57:11.044025 output: Kernel: kernel-1
247 11:57:11.044076 output: Init Ramdisk: ramdisk-1
248 11:57:11.044127 output: FDT: fdt-1
249 11:57:11.044177 output: Loadables: kernel-1
250 11:57:11.044227 output:
251 11:57:11.044423 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:57:11.044555 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:57:11.044675 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 11:57:11.044768 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 11:57:11.044843 No LXC device requested
256 11:57:11.044922 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:57:11.045006 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 11:57:11.045082 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:57:11.045148 Checking files for TFTP limit of 4294967296 bytes.
260 11:57:11.045633 end: 1 tftp-deploy (duration 00:00:19) [common]
261 11:57:11.045735 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:57:11.045822 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:57:11.045942 substitutions:
264 11:57:11.046005 - {DTB}: 12066571/tftp-deploy-hke564pf/dtb/mt8192-asurada-spherion-r0.dtb
265 11:57:11.046069 - {INITRD}: 12066571/tftp-deploy-hke564pf/ramdisk/ramdisk.cpio.gz
266 11:57:11.046125 - {KERNEL}: 12066571/tftp-deploy-hke564pf/kernel/Image
267 11:57:11.046181 - {LAVA_MAC}: None
268 11:57:11.046234 - {PRESEED_CONFIG}: None
269 11:57:11.046287 - {PRESEED_LOCAL}: None
270 11:57:11.046339 - {RAMDISK}: 12066571/tftp-deploy-hke564pf/ramdisk/ramdisk.cpio.gz
271 11:57:11.046392 - {ROOT_PART}: None
272 11:57:11.046443 - {ROOT}: None
273 11:57:11.046495 - {SERVER_IP}: 192.168.201.1
274 11:57:11.046547 - {TEE}: None
275 11:57:11.046599 Parsed boot commands:
276 11:57:11.046650 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:57:11.046830 Parsed boot commands: tftpboot 192.168.201.1 12066571/tftp-deploy-hke564pf/kernel/image.itb 12066571/tftp-deploy-hke564pf/kernel/cmdline
278 11:57:11.046916 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:57:11.047006 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:57:11.047101 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:57:11.047281 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:57:11.047351 Not connected, no need to disconnect.
283 11:57:11.047421 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:57:11.047499 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:57:11.047561 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:57:11.051631 Setting prompt string to ['lava-test: # ']
287 11:57:11.052044 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:57:11.052153 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:57:11.052251 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:57:11.052341 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:57:11.052579 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 11:57:16.199567 >> Command sent successfully.
293 11:57:16.211169 Returned 0 in 5 seconds
294 11:57:16.312491 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:57:16.314322 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:57:16.315094 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:57:16.315577 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:57:16.315955 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:57:16.316335 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:57:16.317817 [Enter `^Ec?' for help]
302 11:57:16.482870
303 11:57:16.483473
304 11:57:16.483939 F0: 102B 0000
305 11:57:16.484623
306 11:57:16.485071 F3: 1001 0000 [0200]
307 11:57:16.485419
308 11:57:16.486370 F3: 1001 0000
309 11:57:16.487077
310 11:57:16.487495 F7: 102D 0000
311 11:57:16.487843
312 11:57:16.489682 F1: 0000 0000
313 11:57:16.490244
314 11:57:16.490629 V0: 0000 0000 [0001]
315 11:57:16.490975
316 11:57:16.492589 00: 0007 8000
317 11:57:16.493060
318 11:57:16.493428 01: 0000 0000
319 11:57:16.493778
320 11:57:16.495988 BP: 0C00 0209 [0000]
321 11:57:16.496450
322 11:57:16.496877 G0: 1182 0000
323 11:57:16.497223
324 11:57:16.497550 EC: 0000 0021 [4000]
325 11:57:16.499728
326 11:57:16.500192 S7: 0000 0000 [0000]
327 11:57:16.500612
328 11:57:16.503019 CC: 0000 0000 [0001]
329 11:57:16.503478
330 11:57:16.503840 T0: 0000 0040 [010F]
331 11:57:16.504179
332 11:57:16.504502 Jump to BL
333 11:57:16.504878
334 11:57:16.529527
335 11:57:16.530081
336 11:57:16.530450
337 11:57:16.536658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:57:16.540320 ARM64: Exception handlers installed.
339 11:57:16.544058 ARM64: Testing exception
340 11:57:16.547247 ARM64: Done test exception
341 11:57:16.553900 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:57:16.563995 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:57:16.571432 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:57:16.581012 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:57:16.587532 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:57:16.594426 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:57:16.606380 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:57:16.613244 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:57:16.632682 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:57:16.635913 WDT: Last reset was cold boot
351 11:57:16.639359 SPI1(PAD0) initialized at 2873684 Hz
352 11:57:16.642487 SPI5(PAD0) initialized at 992727 Hz
353 11:57:16.645832 VBOOT: Loading verstage.
354 11:57:16.652672 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:57:16.655832 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:57:16.658735 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:57:16.662204 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:57:16.669820 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:57:16.676309 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:57:16.687134 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:57:16.687703
362 11:57:16.688382
363 11:57:16.697021 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:57:16.700922 ARM64: Exception handlers installed.
365 11:57:16.703638 ARM64: Testing exception
366 11:57:16.704099 ARM64: Done test exception
367 11:57:16.710527 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:57:16.714031 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:57:16.728090 Probing TPM: . done!
370 11:57:16.728706 TPM ready after 0 ms
371 11:57:16.735737 Connected to device vid:did:rid of 1ae0:0028:00
372 11:57:16.742634 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 11:57:16.791239 Initialized TPM device CR50 revision 0
374 11:57:16.794791 tlcl_send_startup: Startup return code is 0
375 11:57:16.802180 TPM: setup succeeded
376 11:57:16.815105 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:57:16.824123 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:57:16.833568 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:57:16.842987 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:57:16.846078 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:57:16.849210 in-header: 03 07 00 00 08 00 00 00
382 11:57:16.852668 in-data: aa e4 47 04 13 02 00 00
383 11:57:16.855795 Chrome EC: UHEPI supported
384 11:57:16.862499 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:57:16.866091 in-header: 03 95 00 00 08 00 00 00
386 11:57:16.869656 in-data: 18 20 20 08 00 00 00 00
387 11:57:16.870220 Phase 1
388 11:57:16.873091 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:57:16.880502 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:57:16.887232 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:57:16.887835 Recovery requested (1009000e)
392 11:57:16.897267 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:57:16.903122 tlcl_extend: response is 0
394 11:57:16.912368 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:57:16.918035 tlcl_extend: response is 0
396 11:57:16.924769 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:57:16.945078 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:57:16.952997 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:57:16.953619
400 11:57:16.954014
401 11:57:16.959719 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:57:16.963091 ARM64: Exception handlers installed.
403 11:57:16.966876 ARM64: Testing exception
404 11:57:16.969922 ARM64: Done test exception
405 11:57:16.990192 pmic_efuse_setting: Set efuses in 11 msecs
406 11:57:16.993705 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:57:17.000023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:57:17.003726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:57:17.010182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:57:17.013678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:57:17.020604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:57:17.023428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:57:17.027160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:57:17.033561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:57:17.037225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:57:17.043814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:57:17.047247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:57:17.050499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:57:17.056956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:57:17.063854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:57:17.067061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:57:17.074461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:57:17.078290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:57:17.085056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:57:17.092220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:57:17.096117 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:57:17.103739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:57:17.107799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:57:17.114996 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:57:17.118927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:57:17.122080 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:57:17.129280 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:57:17.132966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:57:17.141051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:57:17.144366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:57:17.148158 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:57:17.155472 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:57:17.159222 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:57:17.162861 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:57:17.170135 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:57:17.174085 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:57:17.181012 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:57:17.184878 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:57:17.188547 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:57:17.192061 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:57:17.199290 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:57:17.202971 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:57:17.206551 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:57:17.210394 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:57:17.213889 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:57:17.221197 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:57:17.224475 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:57:17.228684 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:57:17.231783 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:57:17.235564 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:57:17.242744 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:57:17.246244 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:57:17.253859 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:57:17.261272 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:57:17.264415 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:57:17.275617 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:57:17.283271 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:57:17.286596 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:57:17.290675 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:57:17.297224 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:57:17.304296 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:57:17.307506 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:57:17.315190 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:57:17.318883 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:57:17.327557 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 11:57:17.337105 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 11:57:17.346555 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 11:57:17.356480 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 11:57:17.365622 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 11:57:17.375193 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 11:57:17.385193 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 11:57:17.388680 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:57:17.395334 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:57:17.399182 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:57:17.402753 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:57:17.406735 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:57:17.410437 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:57:17.414049 ADC[4]: Raw value=670432 ID=5
484 11:57:17.417991 ADC[3]: Raw value=212917 ID=1
485 11:57:17.418554 RAM Code: 0x51
486 11:57:17.421222 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:57:17.428307 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:57:17.435664 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:57:17.439747 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:57:17.443100 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:57:17.447308 in-header: 03 07 00 00 08 00 00 00
492 11:57:17.451051 in-data: aa e4 47 04 13 02 00 00
493 11:57:17.454713 Chrome EC: UHEPI supported
494 11:57:17.461675 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:57:17.465389 in-header: 03 95 00 00 08 00 00 00
496 11:57:17.469410 in-data: 18 20 20 08 00 00 00 00
497 11:57:17.469936 MRC: failed to locate region type 0.
498 11:57:17.476678 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:57:17.480094 DRAM-K: Running full calibration
500 11:57:17.487605 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:57:17.488033 header.status = 0x0
502 11:57:17.491575 header.version = 0x6 (expected: 0x6)
503 11:57:17.495088 header.size = 0xd00 (expected: 0xd00)
504 11:57:17.495506 header.flags = 0x0
505 11:57:17.501967 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:57:17.520295 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:57:17.527355 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:57:17.530973 dram_init: ddr_geometry: 0
509 11:57:17.531684 [EMI] MDL number = 0
510 11:57:17.535056 [EMI] Get MDL freq = 0
511 11:57:17.535572 dram_init: ddr_type: 0
512 11:57:17.538570 is_discrete_lpddr4: 1
513 11:57:17.542327 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:57:17.542840
515 11:57:17.543177
516 11:57:17.546036 [Bian_co] ETT version 0.0.0.1
517 11:57:17.549695 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:57:17.550115
519 11:57:17.553554 dramc_set_vcore_voltage set vcore to 650000
520 11:57:17.554069 Read voltage for 800, 4
521 11:57:17.556857 Vio18 = 0
522 11:57:17.557274 Vcore = 650000
523 11:57:17.557606 Vdram = 0
524 11:57:17.560481 Vddq = 0
525 11:57:17.560950 Vmddr = 0
526 11:57:17.564340 dram_init: config_dvfs: 1
527 11:57:17.568034 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:57:17.571486 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:57:17.575162 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:57:17.578703 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:57:17.582325 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:57:17.589685 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:57:17.590212 MEM_TYPE=3, freq_sel=18
534 11:57:17.593123 sv_algorithm_assistance_LP4_1600
535 11:57:17.597299 ============ PULL DRAM RESETB DOWN ============
536 11:57:17.600355 ========== PULL DRAM RESETB DOWN end =========
537 11:57:17.607674 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:57:17.608097 ===================================
539 11:57:17.611479 LPDDR4 DRAM CONFIGURATION
540 11:57:17.615057 ===================================
541 11:57:17.618824 EX_ROW_EN[0] = 0x0
542 11:57:17.619358 EX_ROW_EN[1] = 0x0
543 11:57:17.622674 LP4Y_EN = 0x0
544 11:57:17.623208 WORK_FSP = 0x0
545 11:57:17.626478 WL = 0x2
546 11:57:17.626897 RL = 0x2
547 11:57:17.627226 BL = 0x2
548 11:57:17.629737 RPST = 0x0
549 11:57:17.630156 RD_PRE = 0x0
550 11:57:17.633512 WR_PRE = 0x1
551 11:57:17.634037 WR_PST = 0x0
552 11:57:17.637618 DBI_WR = 0x0
553 11:57:17.638145 DBI_RD = 0x0
554 11:57:17.640618 OTF = 0x1
555 11:57:17.644626 ===================================
556 11:57:17.645150 ===================================
557 11:57:17.648189 ANA top config
558 11:57:17.651652 ===================================
559 11:57:17.652070 DLL_ASYNC_EN = 0
560 11:57:17.655592 ALL_SLAVE_EN = 1
561 11:57:17.659512 NEW_RANK_MODE = 1
562 11:57:17.663098 DLL_IDLE_MODE = 1
563 11:57:17.663627 LP45_APHY_COMB_EN = 1
564 11:57:17.666466 TX_ODT_DIS = 1
565 11:57:17.669903 NEW_8X_MODE = 1
566 11:57:17.673329 ===================================
567 11:57:17.676693 ===================================
568 11:57:17.679988 data_rate = 1600
569 11:57:17.680531 CKR = 1
570 11:57:17.683418 DQ_P2S_RATIO = 8
571 11:57:17.686626 ===================================
572 11:57:17.690262 CA_P2S_RATIO = 8
573 11:57:17.693742 DQ_CA_OPEN = 0
574 11:57:17.696981 DQ_SEMI_OPEN = 0
575 11:57:17.697401 CA_SEMI_OPEN = 0
576 11:57:17.700336 CA_FULL_RATE = 0
577 11:57:17.704217 DQ_CKDIV4_EN = 1
578 11:57:17.707773 CA_CKDIV4_EN = 1
579 11:57:17.708191 CA_PREDIV_EN = 0
580 11:57:17.710996 PH8_DLY = 0
581 11:57:17.714553 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:57:17.718185 DQ_AAMCK_DIV = 4
583 11:57:17.721105 CA_AAMCK_DIV = 4
584 11:57:17.724549 CA_ADMCK_DIV = 4
585 11:57:17.725099 DQ_TRACK_CA_EN = 0
586 11:57:17.727807 CA_PICK = 800
587 11:57:17.731730 CA_MCKIO = 800
588 11:57:17.735291 MCKIO_SEMI = 0
589 11:57:17.738570 PLL_FREQ = 3068
590 11:57:17.738992 DQ_UI_PI_RATIO = 32
591 11:57:17.742279 CA_UI_PI_RATIO = 0
592 11:57:17.745365 ===================================
593 11:57:17.748430 ===================================
594 11:57:17.752438 memory_type:LPDDR4
595 11:57:17.753019 GP_NUM : 10
596 11:57:17.756322 SRAM_EN : 1
597 11:57:17.759855 MD32_EN : 0
598 11:57:17.760396 ===================================
599 11:57:17.763529 [ANA_INIT] >>>>>>>>>>>>>>
600 11:57:17.766994 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:57:17.770858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:57:17.774730 ===================================
603 11:57:17.775268 data_rate = 1600,PCW = 0X7600
604 11:57:17.778763 ===================================
605 11:57:17.781885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:57:17.789086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:57:17.792748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:57:17.799244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:57:17.802673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:57:17.806052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:57:17.806614 [ANA_INIT] flow start
612 11:57:17.809260 [ANA_INIT] PLL >>>>>>>>
613 11:57:17.812833 [ANA_INIT] PLL <<<<<<<<
614 11:57:17.815840 [ANA_INIT] MIDPI >>>>>>>>
615 11:57:17.816303 [ANA_INIT] MIDPI <<<<<<<<
616 11:57:17.819474 [ANA_INIT] DLL >>>>>>>>
617 11:57:17.820165 [ANA_INIT] flow end
618 11:57:17.825774 ============ LP4 DIFF to SE enter ============
619 11:57:17.829249 ============ LP4 DIFF to SE exit ============
620 11:57:17.832742 [ANA_INIT] <<<<<<<<<<<<<
621 11:57:17.836171 [Flow] Enable top DCM control >>>>>
622 11:57:17.839372 [Flow] Enable top DCM control <<<<<
623 11:57:17.842643 Enable DLL master slave shuffle
624 11:57:17.846152 ==============================================================
625 11:57:17.849249 Gating Mode config
626 11:57:17.852707 ==============================================================
627 11:57:17.855888 Config description:
628 11:57:17.866002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:57:17.872668 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:57:17.876187 SELPH_MODE 0: By rank 1: By Phase
631 11:57:17.882804 ==============================================================
632 11:57:17.886026 GAT_TRACK_EN = 1
633 11:57:17.889112 RX_GATING_MODE = 2
634 11:57:17.892892 RX_GATING_TRACK_MODE = 2
635 11:57:17.895864 SELPH_MODE = 1
636 11:57:17.896338 PICG_EARLY_EN = 1
637 11:57:17.899445 VALID_LAT_VALUE = 1
638 11:57:17.906271 ==============================================================
639 11:57:17.909371 Enter into Gating configuration >>>>
640 11:57:17.912742 Exit from Gating configuration <<<<
641 11:57:17.916204 Enter into DVFS_PRE_config >>>>>
642 11:57:17.925882 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:57:17.929239 Exit from DVFS_PRE_config <<<<<
644 11:57:17.932903 Enter into PICG configuration >>>>
645 11:57:17.935994 Exit from PICG configuration <<<<
646 11:57:17.939473 [RX_INPUT] configuration >>>>>
647 11:57:17.942853 [RX_INPUT] configuration <<<<<
648 11:57:17.946015 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:57:17.952887 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:57:17.959501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:57:17.965486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:57:17.972844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:57:17.975964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:57:17.982461 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:57:17.985614 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:57:17.989116 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:57:17.992608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:57:17.995611 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:57:18.002797 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:57:18.005640 ===================================
661 11:57:18.009089 LPDDR4 DRAM CONFIGURATION
662 11:57:18.012701 ===================================
663 11:57:18.013258 EX_ROW_EN[0] = 0x0
664 11:57:18.015832 EX_ROW_EN[1] = 0x0
665 11:57:18.016391 LP4Y_EN = 0x0
666 11:57:18.019262 WORK_FSP = 0x0
667 11:57:18.019823 WL = 0x2
668 11:57:18.022697 RL = 0x2
669 11:57:18.023259 BL = 0x2
670 11:57:18.025629 RPST = 0x0
671 11:57:18.026141 RD_PRE = 0x0
672 11:57:18.029469 WR_PRE = 0x1
673 11:57:18.030039 WR_PST = 0x0
674 11:57:18.032480 DBI_WR = 0x0
675 11:57:18.033094 DBI_RD = 0x0
676 11:57:18.035802 OTF = 0x1
677 11:57:18.039174 ===================================
678 11:57:18.042665 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:57:18.046008 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:57:18.052483 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:57:18.055808 ===================================
682 11:57:18.056368 LPDDR4 DRAM CONFIGURATION
683 11:57:18.059006 ===================================
684 11:57:18.062383 EX_ROW_EN[0] = 0x10
685 11:57:18.065629 EX_ROW_EN[1] = 0x0
686 11:57:18.066218 LP4Y_EN = 0x0
687 11:57:18.069357 WORK_FSP = 0x0
688 11:57:18.069927 WL = 0x2
689 11:57:18.072407 RL = 0x2
690 11:57:18.073014 BL = 0x2
691 11:57:18.075945 RPST = 0x0
692 11:57:18.076543 RD_PRE = 0x0
693 11:57:18.079115 WR_PRE = 0x1
694 11:57:18.079680 WR_PST = 0x0
695 11:57:18.082664 DBI_WR = 0x0
696 11:57:18.083229 DBI_RD = 0x0
697 11:57:18.085593 OTF = 0x1
698 11:57:18.089304 ===================================
699 11:57:18.095829 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:57:18.098803 nWR fixed to 40
701 11:57:18.099280 [ModeRegInit_LP4] CH0 RK0
702 11:57:18.102017 [ModeRegInit_LP4] CH0 RK1
703 11:57:18.106056 [ModeRegInit_LP4] CH1 RK0
704 11:57:18.109221 [ModeRegInit_LP4] CH1 RK1
705 11:57:18.109787 match AC timing 12
706 11:57:18.112500 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:57:18.119071 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:57:18.122224 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:57:18.125632 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:57:18.132629 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:57:18.133191 [EMI DOE] emi_dcm 0
712 11:57:18.139069 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:57:18.139627 ==
714 11:57:18.142667 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:57:18.145539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:57:18.146146 ==
717 11:57:18.152299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:57:18.155675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:57:18.165996 [CA 0] Center 37 (7~68) winsize 62
720 11:57:18.169080 [CA 1] Center 37 (7~68) winsize 62
721 11:57:18.171970 [CA 2] Center 35 (5~66) winsize 62
722 11:57:18.175477 [CA 3] Center 35 (4~66) winsize 63
723 11:57:18.179340 [CA 4] Center 34 (4~65) winsize 62
724 11:57:18.182030 [CA 5] Center 34 (4~64) winsize 61
725 11:57:18.182507
726 11:57:18.185349 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:57:18.185821
728 11:57:18.188948 [CATrainingPosCal] consider 1 rank data
729 11:57:18.192495 u2DelayCellTimex100 = 270/100 ps
730 11:57:18.195750 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 11:57:18.198715 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 11:57:18.205586 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 11:57:18.209392 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 11:57:18.212730 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 11:57:18.215768 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 11:57:18.216367
737 11:57:18.219414 CA PerBit enable=1, Macro0, CA PI delay=34
738 11:57:18.219976
739 11:57:18.222143 [CBTSetCACLKResult] CA Dly = 34
740 11:57:18.222614 CS Dly: 5 (0~36)
741 11:57:18.222991 ==
742 11:57:18.225768 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:57:18.232425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:57:18.233029 ==
745 11:57:18.235666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:57:18.242400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:57:18.251411 [CA 0] Center 37 (6~68) winsize 63
748 11:57:18.254992 [CA 1] Center 37 (6~68) winsize 63
749 11:57:18.258034 [CA 2] Center 35 (4~66) winsize 63
750 11:57:18.261308 [CA 3] Center 34 (4~65) winsize 62
751 11:57:18.265058 [CA 4] Center 33 (3~64) winsize 62
752 11:57:18.268179 [CA 5] Center 33 (3~64) winsize 62
753 11:57:18.268785
754 11:57:18.271548 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:57:18.272112
756 11:57:18.274876 [CATrainingPosCal] consider 2 rank data
757 11:57:18.277935 u2DelayCellTimex100 = 270/100 ps
758 11:57:18.281266 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 11:57:18.284690 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 11:57:18.291426 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 11:57:18.294804 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 11:57:18.297972 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 11:57:18.301216 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 11:57:18.301690
765 11:57:18.304384 CA PerBit enable=1, Macro0, CA PI delay=34
766 11:57:18.304894
767 11:57:18.308446 [CBTSetCACLKResult] CA Dly = 34
768 11:57:18.309080 CS Dly: 6 (0~38)
769 11:57:18.309464
770 11:57:18.311364 ----->DramcWriteLeveling(PI) begin...
771 11:57:18.314778 ==
772 11:57:18.315341 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:57:18.321520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:57:18.322120 ==
775 11:57:18.324499 Write leveling (Byte 0): 27 => 27
776 11:57:18.327938 Write leveling (Byte 1): 27 => 27
777 11:57:18.332018 DramcWriteLeveling(PI) end<-----
778 11:57:18.332656
779 11:57:18.333047 ==
780 11:57:18.335645 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:57:18.339298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:57:18.339879 ==
783 11:57:18.340260 [Gating] SW mode calibration
784 11:57:18.346793 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:57:18.353469 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:57:18.357113 0 6 0 | B1->B0 | 3333 3333 | 1 0 | (1 0) (0 1)
787 11:57:18.360563 0 6 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
788 11:57:18.367201 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:57:18.370705 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:57:18.374048 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:57:18.380743 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:57:18.384013 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:57:18.386987 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:57:18.394137 0 7 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
795 11:57:18.397179 0 7 4 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
796 11:57:18.400467 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:57:18.403792 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:57:18.410351 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:57:18.413860 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:57:18.417239 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:57:18.423680 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:57:18.427222 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 11:57:18.430485 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:57:18.437358 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:57:18.440672 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:57:18.443709 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:57:18.450727 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:57:18.454127 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:57:18.457112 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:57:18.463736 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:57:18.467272 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:57:18.470606 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:57:18.477492 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:57:18.480692 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:57:18.483616 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:57:18.490222 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:57:18.493541 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
818 11:57:18.496745 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
819 11:57:18.500060 Total UI for P1: 0, mck2ui 16
820 11:57:18.503795 best dqsien dly found for B1: ( 0, 9, 28)
821 11:57:18.510122 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
822 11:57:18.510544 Total UI for P1: 0, mck2ui 16
823 11:57:18.513447 best dqsien dly found for B0: ( 0, 10, 0)
824 11:57:18.516906 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 11:57:18.523851 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
826 11:57:18.524430
827 11:57:18.526848 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 11:57:18.530186 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
829 11:57:18.533685 [Gating] SW calibration Done
830 11:57:18.534208 ==
831 11:57:18.537026 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:57:18.540753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:57:18.541278 ==
834 11:57:18.543843 RX Vref Scan: 0
835 11:57:18.544364
836 11:57:18.544751 RX Vref 0 -> 0, step: 1
837 11:57:18.545064
838 11:57:18.547068 RX Delay -130 -> 252, step: 16
839 11:57:18.550505 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 11:57:18.556945 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:57:18.560389 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 11:57:18.563716 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:57:18.566863 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
844 11:57:18.570226 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:57:18.573526 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 11:57:18.580324 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 11:57:18.583766 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
848 11:57:18.587041 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 11:57:18.590618 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:57:18.593693 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:57:18.600169 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 11:57:18.603591 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 11:57:18.606997 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:57:18.610500 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:57:18.611065 ==
856 11:57:18.613302 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:57:18.620165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:57:18.620763 ==
859 11:57:18.621147 DQS Delay:
860 11:57:18.623479 DQS0 = 0, DQS1 = 0
861 11:57:18.623940 DQM Delay:
862 11:57:18.624307 DQM0 = 81, DQM1 = 75
863 11:57:18.626718 DQ Delay:
864 11:57:18.630246 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 11:57:18.633500 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
866 11:57:18.636815 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
867 11:57:18.640234 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 11:57:18.640835
869 11:57:18.641214
870 11:57:18.641562 ==
871 11:57:18.643914 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:57:18.647135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:57:18.647698 ==
874 11:57:18.648078
875 11:57:18.648427
876 11:57:18.650017 TX Vref Scan disable
877 11:57:18.650482 == TX Byte 0 ==
878 11:57:18.657116 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 11:57:18.660323 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 11:57:18.660938 == TX Byte 1 ==
881 11:57:18.667004 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 11:57:18.670258 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 11:57:18.670823 ==
884 11:57:18.673889 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:57:18.676965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:57:18.677533 ==
887 11:57:18.691222 TX Vref=22, minBit 2, minWin=27, winSum=442
888 11:57:18.693867 TX Vref=24, minBit 2, minWin=27, winSum=440
889 11:57:18.697406 TX Vref=26, minBit 0, minWin=27, winSum=445
890 11:57:18.700580 TX Vref=28, minBit 0, minWin=28, winSum=451
891 11:57:18.704204 TX Vref=30, minBit 0, minWin=28, winSum=450
892 11:57:18.707383 TX Vref=32, minBit 1, minWin=27, winSum=450
893 11:57:18.713811 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
894 11:57:18.714367
895 11:57:18.717112 Final TX Range 1 Vref 28
896 11:57:18.717585
897 11:57:18.717959 ==
898 11:57:18.720347 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:57:18.723792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:57:18.724266 ==
901 11:57:18.724688
902 11:57:18.727435
903 11:57:18.727904 TX Vref Scan disable
904 11:57:18.731207 == TX Byte 0 ==
905 11:57:18.734446 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 11:57:18.737915 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 11:57:18.741462 == TX Byte 1 ==
908 11:57:18.744394 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
909 11:57:18.748128 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
910 11:57:18.748743
911 11:57:18.751605 [DATLAT]
912 11:57:18.752166 Freq=800, CH0 RK0
913 11:57:18.752586
914 11:57:18.755131 DATLAT Default: 0xa
915 11:57:18.755692 0, 0xFFFF, sum = 0
916 11:57:18.757744 1, 0xFFFF, sum = 0
917 11:57:18.758229 2, 0xFFFF, sum = 0
918 11:57:18.761580 3, 0xFFFF, sum = 0
919 11:57:18.762170 4, 0xFFFF, sum = 0
920 11:57:18.764575 5, 0xFFFF, sum = 0
921 11:57:18.765043 6, 0xFFFF, sum = 0
922 11:57:18.768198 7, 0xFFFF, sum = 0
923 11:57:18.768823 8, 0x0, sum = 1
924 11:57:18.771314 9, 0x0, sum = 2
925 11:57:18.771883 10, 0x0, sum = 3
926 11:57:18.774824 11, 0x0, sum = 4
927 11:57:18.775399 best_step = 9
928 11:57:18.775769
929 11:57:18.776111 ==
930 11:57:18.777966 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:57:18.781093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:57:18.781560 ==
933 11:57:18.784888 RX Vref Scan: 1
934 11:57:18.785449
935 11:57:18.788321 Set Vref Range= 32 -> 127
936 11:57:18.788946
937 11:57:18.789321 RX Vref 32 -> 127, step: 1
938 11:57:18.789662
939 11:57:18.791487 RX Delay -111 -> 252, step: 8
940 11:57:18.792051
941 11:57:18.794601 Set Vref, RX VrefLevel [Byte0]: 32
942 11:57:18.797883 [Byte1]: 32
943 11:57:18.801730
944 11:57:18.802282 Set Vref, RX VrefLevel [Byte0]: 33
945 11:57:18.804634 [Byte1]: 33
946 11:57:18.809395
947 11:57:18.809948 Set Vref, RX VrefLevel [Byte0]: 34
948 11:57:18.812610 [Byte1]: 34
949 11:57:18.816906
950 11:57:18.817464 Set Vref, RX VrefLevel [Byte0]: 35
951 11:57:18.820214 [Byte1]: 35
952 11:57:18.824611
953 11:57:18.825164 Set Vref, RX VrefLevel [Byte0]: 36
954 11:57:18.827324 [Byte1]: 36
955 11:57:18.832170
956 11:57:18.832794 Set Vref, RX VrefLevel [Byte0]: 37
957 11:57:18.835644 [Byte1]: 37
958 11:57:18.839724
959 11:57:18.840290 Set Vref, RX VrefLevel [Byte0]: 38
960 11:57:18.842730 [Byte1]: 38
961 11:57:18.847428
962 11:57:18.847999 Set Vref, RX VrefLevel [Byte0]: 39
963 11:57:18.850645 [Byte1]: 39
964 11:57:18.854978
965 11:57:18.855541 Set Vref, RX VrefLevel [Byte0]: 40
966 11:57:18.858333 [Byte1]: 40
967 11:57:18.862617
968 11:57:18.863177 Set Vref, RX VrefLevel [Byte0]: 41
969 11:57:18.865763 [Byte1]: 41
970 11:57:18.870482
971 11:57:18.871041 Set Vref, RX VrefLevel [Byte0]: 42
972 11:57:18.873423 [Byte1]: 42
973 11:57:18.877621
974 11:57:18.881207 Set Vref, RX VrefLevel [Byte0]: 43
975 11:57:18.884437 [Byte1]: 43
976 11:57:18.885170
977 11:57:18.887416 Set Vref, RX VrefLevel [Byte0]: 44
978 11:57:18.890894 [Byte1]: 44
979 11:57:18.891464
980 11:57:18.894470 Set Vref, RX VrefLevel [Byte0]: 45
981 11:57:18.897544 [Byte1]: 45
982 11:57:18.900971
983 11:57:18.901647 Set Vref, RX VrefLevel [Byte0]: 46
984 11:57:18.903876 [Byte1]: 46
985 11:57:18.908545
986 11:57:18.909122 Set Vref, RX VrefLevel [Byte0]: 47
987 11:57:18.912094 [Byte1]: 47
988 11:57:18.916027
989 11:57:18.916640 Set Vref, RX VrefLevel [Byte0]: 48
990 11:57:18.919622 [Byte1]: 48
991 11:57:18.923870
992 11:57:18.924432 Set Vref, RX VrefLevel [Byte0]: 49
993 11:57:18.926705 [Byte1]: 49
994 11:57:18.931703
995 11:57:18.932257 Set Vref, RX VrefLevel [Byte0]: 50
996 11:57:18.934539 [Byte1]: 50
997 11:57:18.939087
998 11:57:18.939551 Set Vref, RX VrefLevel [Byte0]: 51
999 11:57:18.942363 [Byte1]: 51
1000 11:57:18.946822
1001 11:57:18.947390 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:57:18.949756 [Byte1]: 52
1003 11:57:18.954291
1004 11:57:18.954907 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:57:18.957831 [Byte1]: 53
1006 11:57:18.961949
1007 11:57:18.962504 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:57:18.965515 [Byte1]: 54
1009 11:57:18.969478
1010 11:57:18.970050 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:57:18.972963 [Byte1]: 55
1012 11:57:18.977357
1013 11:57:18.977936 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:57:18.980716 [Byte1]: 56
1015 11:57:18.984978
1016 11:57:18.985533 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:57:18.988661 [Byte1]: 57
1018 11:57:18.992979
1019 11:57:18.993541 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:57:18.996393 [Byte1]: 58
1021 11:57:19.000844
1022 11:57:19.001376 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:57:19.003732 [Byte1]: 59
1024 11:57:19.008156
1025 11:57:19.008780 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:57:19.011326 [Byte1]: 60
1027 11:57:19.016210
1028 11:57:19.016791 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:57:19.019211 [Byte1]: 61
1030 11:57:19.023320
1031 11:57:19.023772 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:57:19.026715 [Byte1]: 62
1033 11:57:19.031103
1034 11:57:19.031647 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:57:19.034291 [Byte1]: 63
1036 11:57:19.038438
1037 11:57:19.038987 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:57:19.041408 [Byte1]: 64
1039 11:57:19.046327
1040 11:57:19.046881 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:57:19.049367 [Byte1]: 65
1042 11:57:19.053552
1043 11:57:19.054100 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:57:19.057387 [Byte1]: 66
1045 11:57:19.061318
1046 11:57:19.061772 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:57:19.064977 [Byte1]: 67
1048 11:57:19.069130
1049 11:57:19.069585 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:57:19.072252 [Byte1]: 68
1051 11:57:19.076599
1052 11:57:19.077143 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:57:19.079989 [Byte1]: 69
1054 11:57:19.084140
1055 11:57:19.084735 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:57:19.087327 [Byte1]: 70
1057 11:57:19.091995
1058 11:57:19.092444 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:57:19.095557 [Byte1]: 71
1060 11:57:19.099630
1061 11:57:19.100193 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:57:19.102686 [Byte1]: 72
1063 11:57:19.107096
1064 11:57:19.107647 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:57:19.110466 [Byte1]: 73
1066 11:57:19.114739
1067 11:57:19.115191 Set Vref, RX VrefLevel [Byte0]: 74
1068 11:57:19.117967 [Byte1]: 74
1069 11:57:19.122375
1070 11:57:19.122823 Final RX Vref Byte 0 = 54 to rank0
1071 11:57:19.125574 Final RX Vref Byte 1 = 54 to rank0
1072 11:57:19.129030 Final RX Vref Byte 0 = 54 to rank1
1073 11:57:19.132909 Final RX Vref Byte 1 = 54 to rank1==
1074 11:57:19.135916 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 11:57:19.142363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 11:57:19.142916 ==
1077 11:57:19.143279 DQS Delay:
1078 11:57:19.145296 DQS0 = 0, DQS1 = 0
1079 11:57:19.145749 DQM Delay:
1080 11:57:19.146107 DQM0 = 83, DQM1 = 73
1081 11:57:19.148932 DQ Delay:
1082 11:57:19.152074 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 11:57:19.155525 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 11:57:19.159035 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1085 11:57:19.162118 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1086 11:57:19.162621
1087 11:57:19.163020
1088 11:57:19.168811 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1089 11:57:19.172136 CH0 RK0: MR19=606, MR18=3A3A
1090 11:57:19.178996 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1091 11:57:19.179574
1092 11:57:19.181930 ----->DramcWriteLeveling(PI) begin...
1093 11:57:19.182415 ==
1094 11:57:19.185119 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 11:57:19.188903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 11:57:19.189356 ==
1097 11:57:19.192250 Write leveling (Byte 0): 29 => 29
1098 11:57:19.195493 Write leveling (Byte 1): 28 => 28
1099 11:57:19.198583 DramcWriteLeveling(PI) end<-----
1100 11:57:19.199127
1101 11:57:19.199632 ==
1102 11:57:19.201923 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 11:57:19.205210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 11:57:19.205670 ==
1105 11:57:19.208451 [Gating] SW mode calibration
1106 11:57:19.215401 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 11:57:19.221946 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 11:57:19.225358 0 6 0 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 0)
1109 11:57:19.228744 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 11:57:19.235563 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 11:57:19.239310 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 11:57:19.241995 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 11:57:19.248881 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 11:57:19.252237 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 11:57:19.255715 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 11:57:19.262421 0 7 0 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (0 0)
1117 11:57:19.265352 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1118 11:57:19.269083 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 11:57:19.275487 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 11:57:19.279098 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 11:57:19.282751 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 11:57:19.288866 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 11:57:19.292634 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 11:57:19.295601 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1125 11:57:19.298843 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1126 11:57:19.305398 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 11:57:19.308820 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 11:57:19.312227 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 11:57:19.319244 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:57:19.322249 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:57:19.325316 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:57:19.332101 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:57:19.335431 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:57:19.339064 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:57:19.345719 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:57:19.349068 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:57:19.352360 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 11:57:19.359217 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 11:57:19.362193 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 11:57:19.365428 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1141 11:57:19.372951 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1142 11:57:19.373509 Total UI for P1: 0, mck2ui 16
1143 11:57:19.378694 best dqsien dly found for B0: ( 0, 10, 0)
1144 11:57:19.379230 Total UI for P1: 0, mck2ui 16
1145 11:57:19.382220 best dqsien dly found for B1: ( 0, 10, 2)
1146 11:57:19.388727 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1147 11:57:19.392624 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1148 11:57:19.393168
1149 11:57:19.395744 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1150 11:57:19.399025 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1151 11:57:19.402219 [Gating] SW calibration Done
1152 11:57:19.402677 ==
1153 11:57:19.405348 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 11:57:19.450107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1155 11:57:19.450797 ==
1156 11:57:19.451252 RX Vref Scan: 0
1157 11:57:19.451699
1158 11:57:19.452407 RX Vref 0 -> 0, step: 1
1159 11:57:19.452845
1160 11:57:19.453180 RX Delay -130 -> 252, step: 16
1161 11:57:19.453508 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1162 11:57:19.453830 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1163 11:57:19.454148 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1164 11:57:19.454460 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1165 11:57:19.454770 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1166 11:57:19.455086 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1167 11:57:19.455396 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1168 11:57:19.455703 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1169 11:57:19.486722 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1170 11:57:19.487467 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1171 11:57:19.487868 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1172 11:57:19.488644 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1173 11:57:19.489019 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1174 11:57:19.489358 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1175 11:57:19.489679 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1176 11:57:19.489995 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1177 11:57:19.490308 ==
1178 11:57:19.490621 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 11:57:19.491298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 11:57:19.491693 ==
1181 11:57:19.492013 DQS Delay:
1182 11:57:19.494139 DQS0 = 0, DQS1 = 0
1183 11:57:19.494602 DQM Delay:
1184 11:57:19.494966 DQM0 = 84, DQM1 = 74
1185 11:57:19.495305 DQ Delay:
1186 11:57:19.497462 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1187 11:57:19.500982 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1188 11:57:19.504277 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1189 11:57:19.507483 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1190 11:57:19.507950
1191 11:57:19.508314
1192 11:57:19.508706 ==
1193 11:57:19.511061 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 11:57:19.514297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1195 11:57:19.514844 ==
1196 11:57:19.517371
1197 11:57:19.517829
1198 11:57:19.518190 TX Vref Scan disable
1199 11:57:19.520629 == TX Byte 0 ==
1200 11:57:19.524265 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1201 11:57:19.527427 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1202 11:57:19.530859 == TX Byte 1 ==
1203 11:57:19.534339 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1204 11:57:19.537772 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1205 11:57:19.538508 ==
1206 11:57:19.540882 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 11:57:19.547969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1208 11:57:19.548565 ==
1209 11:57:19.559773 TX Vref=22, minBit 0, minWin=27, winSum=442
1210 11:57:19.562602 TX Vref=24, minBit 0, minWin=27, winSum=449
1211 11:57:19.566091 TX Vref=26, minBit 2, minWin=28, winSum=455
1212 11:57:19.569280 TX Vref=28, minBit 14, minWin=27, winSum=455
1213 11:57:19.572852 TX Vref=30, minBit 2, minWin=28, winSum=459
1214 11:57:19.576373 TX Vref=32, minBit 2, minWin=28, winSum=456
1215 11:57:19.583937 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1216 11:57:19.584503
1217 11:57:19.587512 Final TX Range 1 Vref 30
1218 11:57:19.588074
1219 11:57:19.588441 ==
1220 11:57:19.591184 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 11:57:19.594424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 11:57:19.594985 ==
1223 11:57:19.595352
1224 11:57:19.595725
1225 11:57:19.597875 TX Vref Scan disable
1226 11:57:19.598435 == TX Byte 0 ==
1227 11:57:19.604372 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1228 11:57:19.608087 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1229 11:57:19.608601 == TX Byte 1 ==
1230 11:57:19.614830 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1231 11:57:19.618398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1232 11:57:19.618951
1233 11:57:19.619315 [DATLAT]
1234 11:57:19.621822 Freq=800, CH0 RK1
1235 11:57:19.622373
1236 11:57:19.622745 DATLAT Default: 0x9
1237 11:57:19.624801 0, 0xFFFF, sum = 0
1238 11:57:19.625262 1, 0xFFFF, sum = 0
1239 11:57:19.628276 2, 0xFFFF, sum = 0
1240 11:57:19.629085 3, 0xFFFF, sum = 0
1241 11:57:19.631734 4, 0xFFFF, sum = 0
1242 11:57:19.632195 5, 0xFFFF, sum = 0
1243 11:57:19.635130 6, 0xFFFF, sum = 0
1244 11:57:19.635591 7, 0xFFFF, sum = 0
1245 11:57:19.638348 8, 0x0, sum = 1
1246 11:57:19.638956 9, 0x0, sum = 2
1247 11:57:19.641840 10, 0x0, sum = 3
1248 11:57:19.642401 11, 0x0, sum = 4
1249 11:57:19.645428 best_step = 9
1250 11:57:19.645977
1251 11:57:19.646344 ==
1252 11:57:19.648323 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 11:57:19.651950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1254 11:57:19.652501 ==
1255 11:57:19.652932 RX Vref Scan: 0
1256 11:57:19.653274
1257 11:57:19.654771 RX Vref 0 -> 0, step: 1
1258 11:57:19.655278
1259 11:57:19.658529 RX Delay -111 -> 252, step: 8
1260 11:57:19.661718 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1261 11:57:19.668477 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1262 11:57:19.671740 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1263 11:57:19.675460 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1264 11:57:19.678652 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1265 11:57:19.681608 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1266 11:57:19.688427 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1267 11:57:19.691988 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1268 11:57:19.695201 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1269 11:57:19.698303 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1270 11:57:19.701823 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1271 11:57:19.708439 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1272 11:57:19.711787 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1273 11:57:19.715217 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1274 11:57:19.718305 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1275 11:57:19.721803 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1276 11:57:19.725418 ==
1277 11:57:19.725984 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 11:57:19.731753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 11:57:19.732296 ==
1280 11:57:19.732729 DQS Delay:
1281 11:57:19.735649 DQS0 = 0, DQS1 = 0
1282 11:57:19.736103 DQM Delay:
1283 11:57:19.738468 DQM0 = 86, DQM1 = 74
1284 11:57:19.738925 DQ Delay:
1285 11:57:19.741893 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1286 11:57:19.745404 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1287 11:57:19.748300 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1288 11:57:19.751974 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1289 11:57:19.752577
1290 11:57:19.752951
1291 11:57:19.758721 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1292 11:57:19.762292 CH0 RK1: MR19=606, MR18=4040
1293 11:57:19.768264 CH0_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1294 11:57:19.771650 [RxdqsGatingPostProcess] freq 800
1295 11:57:19.774965 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1296 11:57:19.778256 Pre-setting of DQS Precalculation
1297 11:57:19.785111 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1298 11:57:19.785565 ==
1299 11:57:19.788234 Dram Type= 6, Freq= 0, CH_1, rank 0
1300 11:57:19.792113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1301 11:57:19.792422 ==
1302 11:57:19.798413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1303 11:57:19.801641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1304 11:57:19.812031 [CA 0] Center 36 (6~67) winsize 62
1305 11:57:19.815521 [CA 1] Center 36 (6~67) winsize 62
1306 11:57:19.818791 [CA 2] Center 34 (4~65) winsize 62
1307 11:57:19.821869 [CA 3] Center 34 (4~65) winsize 62
1308 11:57:19.824982 [CA 4] Center 33 (3~64) winsize 62
1309 11:57:19.828663 [CA 5] Center 33 (3~64) winsize 62
1310 11:57:19.829332
1311 11:57:19.832144 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1312 11:57:19.832733
1313 11:57:19.835539 [CATrainingPosCal] consider 1 rank data
1314 11:57:19.838890 u2DelayCellTimex100 = 270/100 ps
1315 11:57:19.842593 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1316 11:57:19.845353 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1317 11:57:19.852261 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 11:57:19.855284 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 11:57:19.858645 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1320 11:57:19.862386 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 11:57:19.862844
1322 11:57:19.865325 CA PerBit enable=1, Macro0, CA PI delay=33
1323 11:57:19.865782
1324 11:57:19.868844 [CBTSetCACLKResult] CA Dly = 33
1325 11:57:19.869383 CS Dly: 4 (0~35)
1326 11:57:19.869747 ==
1327 11:57:19.871879 Dram Type= 6, Freq= 0, CH_1, rank 1
1328 11:57:19.878869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1329 11:57:19.879420 ==
1330 11:57:19.882145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1331 11:57:19.888893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1332 11:57:19.897995 [CA 0] Center 36 (6~67) winsize 62
1333 11:57:19.900979 [CA 1] Center 36 (5~67) winsize 63
1334 11:57:19.904337 [CA 2] Center 34 (4~65) winsize 62
1335 11:57:19.907570 [CA 3] Center 34 (4~65) winsize 62
1336 11:57:19.910753 [CA 4] Center 33 (3~64) winsize 62
1337 11:57:19.914524 [CA 5] Center 33 (3~64) winsize 62
1338 11:57:19.915058
1339 11:57:19.917823 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1340 11:57:19.918276
1341 11:57:19.920910 [CATrainingPosCal] consider 2 rank data
1342 11:57:19.924673 u2DelayCellTimex100 = 270/100 ps
1343 11:57:19.928388 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1344 11:57:19.931004 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1345 11:57:19.938384 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1346 11:57:19.941142 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 11:57:19.944616 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1348 11:57:19.947988 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 11:57:19.948579
1350 11:57:19.951153 CA PerBit enable=1, Macro0, CA PI delay=33
1351 11:57:19.951613
1352 11:57:19.954883 [CBTSetCACLKResult] CA Dly = 33
1353 11:57:19.955471 CS Dly: 4 (0~35)
1354 11:57:19.955844
1355 11:57:19.958174 ----->DramcWriteLeveling(PI) begin...
1356 11:57:19.958724 ==
1357 11:57:19.961386 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 11:57:19.967993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 11:57:19.968611 ==
1360 11:57:19.971141 Write leveling (Byte 0): 25 => 25
1361 11:57:19.974617 Write leveling (Byte 1): 26 => 26
1362 11:57:19.975178 DramcWriteLeveling(PI) end<-----
1363 11:57:19.977817
1364 11:57:19.978353 ==
1365 11:57:19.981613 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 11:57:19.984967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 11:57:19.985527 ==
1368 11:57:19.988408 [Gating] SW mode calibration
1369 11:57:19.994895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1370 11:57:19.998151 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1371 11:57:20.004676 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1372 11:57:20.008017 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1373 11:57:20.011620 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 11:57:20.018185 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 11:57:20.021662 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 11:57:20.025026 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 11:57:20.031183 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 11:57:20.034686 0 6 28 | B1->B0 | 2424 2e2e | 0 0 | (1 1) (0 0)
1379 11:57:20.038202 0 7 0 | B1->B0 | 3636 4343 | 0 1 | (0 0) (0 0)
1380 11:57:20.044651 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1381 11:57:20.047884 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 11:57:20.051637 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 11:57:20.054894 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 11:57:20.061402 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 11:57:20.064560 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 11:57:20.068325 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 11:57:20.074673 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1388 11:57:20.078270 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 11:57:20.081392 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 11:57:20.087774 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 11:57:20.091569 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:57:20.094837 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:57:20.101459 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:57:20.104995 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:57:20.108016 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:57:20.114547 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:57:20.118315 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:57:20.121452 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:57:20.128082 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:57:20.131276 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 11:57:20.134805 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 11:57:20.141281 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1403 11:57:20.144857 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1404 11:57:20.147841 Total UI for P1: 0, mck2ui 16
1405 11:57:20.151705 best dqsien dly found for B0: ( 0, 9, 28)
1406 11:57:20.154671 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1407 11:57:20.158328 Total UI for P1: 0, mck2ui 16
1408 11:57:20.161434 best dqsien dly found for B1: ( 0, 10, 0)
1409 11:57:20.165007 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1410 11:57:20.167990 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1411 11:57:20.168615
1412 11:57:20.171230 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1413 11:57:20.177984 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1414 11:57:20.178533 [Gating] SW calibration Done
1415 11:57:20.178904 ==
1416 11:57:20.181416 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 11:57:20.188095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1418 11:57:20.188724 ==
1419 11:57:20.189101 RX Vref Scan: 0
1420 11:57:20.189442
1421 11:57:20.191429 RX Vref 0 -> 0, step: 1
1422 11:57:20.191917
1423 11:57:20.194504 RX Delay -130 -> 252, step: 16
1424 11:57:20.198213 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1425 11:57:20.201404 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1426 11:57:20.204657 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1427 11:57:20.211123 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1428 11:57:20.214805 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1429 11:57:20.218168 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1430 11:57:20.221368 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1431 11:57:20.225024 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1432 11:57:20.227708 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1433 11:57:20.234731 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1434 11:57:20.238904 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1435 11:57:20.241788 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1436 11:57:20.245132 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1437 11:57:20.248869 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1438 11:57:20.252815 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1439 11:57:20.259287 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1440 11:57:20.259844 ==
1441 11:57:20.263208 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 11:57:20.266683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1443 11:57:20.267231 ==
1444 11:57:20.267597 DQS Delay:
1445 11:57:20.270514 DQS0 = 0, DQS1 = 0
1446 11:57:20.271062 DQM Delay:
1447 11:57:20.271479 DQM0 = 81, DQM1 = 70
1448 11:57:20.274254 DQ Delay:
1449 11:57:20.274713 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1450 11:57:20.277438 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1451 11:57:20.281257 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1452 11:57:20.284158 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1453 11:57:20.284662
1454 11:57:20.285030
1455 11:57:20.287963 ==
1456 11:57:20.288550 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 11:57:20.294347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1458 11:57:20.294899 ==
1459 11:57:20.295268
1460 11:57:20.295604
1461 11:57:20.297903 TX Vref Scan disable
1462 11:57:20.298453 == TX Byte 0 ==
1463 11:57:20.300855 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 11:57:20.307928 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 11:57:20.308467 == TX Byte 1 ==
1466 11:57:20.310613 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1467 11:57:20.317578 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1468 11:57:20.318128 ==
1469 11:57:20.321117 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 11:57:20.324345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1471 11:57:20.324963 ==
1472 11:57:20.337583 TX Vref=22, minBit 8, minWin=27, winSum=444
1473 11:57:20.340440 TX Vref=24, minBit 10, minWin=27, winSum=448
1474 11:57:20.344187 TX Vref=26, minBit 0, minWin=28, winSum=455
1475 11:57:20.347188 TX Vref=28, minBit 0, minWin=28, winSum=454
1476 11:57:20.350777 TX Vref=30, minBit 2, minWin=28, winSum=456
1477 11:57:20.357307 TX Vref=32, minBit 3, minWin=28, winSum=454
1478 11:57:20.360978 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1479 11:57:20.361533
1480 11:57:20.363985 Final TX Range 1 Vref 30
1481 11:57:20.364583
1482 11:57:20.364961 ==
1483 11:57:20.367119 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 11:57:20.370115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 11:57:20.370574 ==
1486 11:57:20.373788
1487 11:57:20.374339
1488 11:57:20.374701 TX Vref Scan disable
1489 11:57:20.377091 == TX Byte 0 ==
1490 11:57:20.380545 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1491 11:57:20.387031 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1492 11:57:20.387580 == TX Byte 1 ==
1493 11:57:20.390551 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1494 11:57:20.393754 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1495 11:57:20.397239
1496 11:57:20.397691 [DATLAT]
1497 11:57:20.398053 Freq=800, CH1 RK0
1498 11:57:20.398393
1499 11:57:20.400622 DATLAT Default: 0xa
1500 11:57:20.401080 0, 0xFFFF, sum = 0
1501 11:57:20.404489 1, 0xFFFF, sum = 0
1502 11:57:20.405090 2, 0xFFFF, sum = 0
1503 11:57:20.407346 3, 0xFFFF, sum = 0
1504 11:57:20.407861 4, 0xFFFF, sum = 0
1505 11:57:20.410234 5, 0xFFFF, sum = 0
1506 11:57:20.410857 6, 0xFFFF, sum = 0
1507 11:57:20.413689 7, 0xFFFF, sum = 0
1508 11:57:20.414153 8, 0x0, sum = 1
1509 11:57:20.417249 9, 0x0, sum = 2
1510 11:57:20.417708 10, 0x0, sum = 3
1511 11:57:20.420599 11, 0x0, sum = 4
1512 11:57:20.421148 best_step = 9
1513 11:57:20.421511
1514 11:57:20.421845 ==
1515 11:57:20.423752 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 11:57:20.430448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1517 11:57:20.431070 ==
1518 11:57:20.431522 RX Vref Scan: 1
1519 11:57:20.431872
1520 11:57:20.434030 Set Vref Range= 32 -> 127
1521 11:57:20.434581
1522 11:57:20.437057 RX Vref 32 -> 127, step: 1
1523 11:57:20.437515
1524 11:57:20.437876 RX Delay -111 -> 252, step: 8
1525 11:57:20.440324
1526 11:57:20.440817 Set Vref, RX VrefLevel [Byte0]: 32
1527 11:57:20.444177 [Byte1]: 32
1528 11:57:20.448120
1529 11:57:20.448730 Set Vref, RX VrefLevel [Byte0]: 33
1530 11:57:20.451450 [Byte1]: 33
1531 11:57:20.455711
1532 11:57:20.456250 Set Vref, RX VrefLevel [Byte0]: 34
1533 11:57:20.459205 [Byte1]: 34
1534 11:57:20.463639
1535 11:57:20.464214 Set Vref, RX VrefLevel [Byte0]: 35
1536 11:57:20.466958 [Byte1]: 35
1537 11:57:20.470808
1538 11:57:20.471278 Set Vref, RX VrefLevel [Byte0]: 36
1539 11:57:20.474402 [Byte1]: 36
1540 11:57:20.478642
1541 11:57:20.479205 Set Vref, RX VrefLevel [Byte0]: 37
1542 11:57:20.482441 [Byte1]: 37
1543 11:57:20.486422
1544 11:57:20.486984 Set Vref, RX VrefLevel [Byte0]: 38
1545 11:57:20.489531 [Byte1]: 38
1546 11:57:20.494094
1547 11:57:20.494658 Set Vref, RX VrefLevel [Byte0]: 39
1548 11:57:20.497092 [Byte1]: 39
1549 11:57:20.501603
1550 11:57:20.502071 Set Vref, RX VrefLevel [Byte0]: 40
1551 11:57:20.505439 [Byte1]: 40
1552 11:57:20.509159
1553 11:57:20.509723 Set Vref, RX VrefLevel [Byte0]: 41
1554 11:57:20.512761 [Byte1]: 41
1555 11:57:20.516922
1556 11:57:20.517492 Set Vref, RX VrefLevel [Byte0]: 42
1557 11:57:20.520111 [Byte1]: 42
1558 11:57:20.524799
1559 11:57:20.525384 Set Vref, RX VrefLevel [Byte0]: 43
1560 11:57:20.527615 [Byte1]: 43
1561 11:57:20.532380
1562 11:57:20.532883 Set Vref, RX VrefLevel [Byte0]: 44
1563 11:57:20.535573 [Byte1]: 44
1564 11:57:20.539999
1565 11:57:20.540610 Set Vref, RX VrefLevel [Byte0]: 45
1566 11:57:20.546468 [Byte1]: 45
1567 11:57:20.547034
1568 11:57:20.549952 Set Vref, RX VrefLevel [Byte0]: 46
1569 11:57:20.553412 [Byte1]: 46
1570 11:57:20.553977
1571 11:57:20.556350 Set Vref, RX VrefLevel [Byte0]: 47
1572 11:57:20.559813 [Byte1]: 47
1573 11:57:20.560393
1574 11:57:20.563092 Set Vref, RX VrefLevel [Byte0]: 48
1575 11:57:20.566582 [Byte1]: 48
1576 11:57:20.570524
1577 11:57:20.571090 Set Vref, RX VrefLevel [Byte0]: 49
1578 11:57:20.573691 [Byte1]: 49
1579 11:57:20.578143
1580 11:57:20.578702 Set Vref, RX VrefLevel [Byte0]: 50
1581 11:57:20.581936 [Byte1]: 50
1582 11:57:20.585940
1583 11:57:20.586508 Set Vref, RX VrefLevel [Byte0]: 51
1584 11:57:20.589095 [Byte1]: 51
1585 11:57:20.593498
1586 11:57:20.593966 Set Vref, RX VrefLevel [Byte0]: 52
1587 11:57:20.596736 [Byte1]: 52
1588 11:57:20.601247
1589 11:57:20.601795 Set Vref, RX VrefLevel [Byte0]: 53
1590 11:57:20.604383 [Byte1]: 53
1591 11:57:20.608603
1592 11:57:20.609162 Set Vref, RX VrefLevel [Byte0]: 54
1593 11:57:20.611865 [Byte1]: 54
1594 11:57:20.616127
1595 11:57:20.616641 Set Vref, RX VrefLevel [Byte0]: 55
1596 11:57:20.619655 [Byte1]: 55
1597 11:57:20.623962
1598 11:57:20.624583 Set Vref, RX VrefLevel [Byte0]: 56
1599 11:57:20.627480 [Byte1]: 56
1600 11:57:20.631929
1601 11:57:20.632401 Set Vref, RX VrefLevel [Byte0]: 57
1602 11:57:20.634898 [Byte1]: 57
1603 11:57:20.639457
1604 11:57:20.640019 Set Vref, RX VrefLevel [Byte0]: 58
1605 11:57:20.645993 [Byte1]: 58
1606 11:57:20.646557
1607 11:57:20.649324 Set Vref, RX VrefLevel [Byte0]: 59
1608 11:57:20.652716 [Byte1]: 59
1609 11:57:20.653274
1610 11:57:20.655649 Set Vref, RX VrefLevel [Byte0]: 60
1611 11:57:20.659094 [Byte1]: 60
1612 11:57:20.662547
1613 11:57:20.663139 Set Vref, RX VrefLevel [Byte0]: 61
1614 11:57:20.665746 [Byte1]: 61
1615 11:57:20.670444
1616 11:57:20.671007 Set Vref, RX VrefLevel [Byte0]: 62
1617 11:57:20.673179 [Byte1]: 62
1618 11:57:20.677483
1619 11:57:20.678051 Set Vref, RX VrefLevel [Byte0]: 63
1620 11:57:20.681206 [Byte1]: 63
1621 11:57:20.685142
1622 11:57:20.685704 Set Vref, RX VrefLevel [Byte0]: 64
1623 11:57:20.688698 [Byte1]: 64
1624 11:57:20.692934
1625 11:57:20.693498 Set Vref, RX VrefLevel [Byte0]: 65
1626 11:57:20.695885 [Byte1]: 65
1627 11:57:20.700168
1628 11:57:20.700678 Set Vref, RX VrefLevel [Byte0]: 66
1629 11:57:20.703716 [Byte1]: 66
1630 11:57:20.708212
1631 11:57:20.708826 Set Vref, RX VrefLevel [Byte0]: 67
1632 11:57:20.711471 [Byte1]: 67
1633 11:57:20.715845
1634 11:57:20.716425 Set Vref, RX VrefLevel [Byte0]: 68
1635 11:57:20.719134 [Byte1]: 68
1636 11:57:20.723612
1637 11:57:20.724184 Set Vref, RX VrefLevel [Byte0]: 69
1638 11:57:20.726450 [Byte1]: 69
1639 11:57:20.731300
1640 11:57:20.731837 Set Vref, RX VrefLevel [Byte0]: 70
1641 11:57:20.734587 [Byte1]: 70
1642 11:57:20.738981
1643 11:57:20.739528 Set Vref, RX VrefLevel [Byte0]: 71
1644 11:57:20.742415 [Byte1]: 71
1645 11:57:20.746540
1646 11:57:20.747124 Set Vref, RX VrefLevel [Byte0]: 72
1647 11:57:20.749443 [Byte1]: 72
1648 11:57:20.754381
1649 11:57:20.754927 Set Vref, RX VrefLevel [Byte0]: 73
1650 11:57:20.757093 [Byte1]: 73
1651 11:57:20.761513
1652 11:57:20.762062 Set Vref, RX VrefLevel [Byte0]: 74
1653 11:57:20.765374 [Byte1]: 74
1654 11:57:20.769506
1655 11:57:20.770049 Set Vref, RX VrefLevel [Byte0]: 75
1656 11:57:20.772620 [Byte1]: 75
1657 11:57:20.777244
1658 11:57:20.777794 Final RX Vref Byte 0 = 59 to rank0
1659 11:57:20.780590 Final RX Vref Byte 1 = 53 to rank0
1660 11:57:20.783457 Final RX Vref Byte 0 = 59 to rank1
1661 11:57:20.787010 Final RX Vref Byte 1 = 53 to rank1==
1662 11:57:20.790400 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 11:57:20.796769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1664 11:57:20.797321 ==
1665 11:57:20.797689 DQS Delay:
1666 11:57:20.798030 DQS0 = 0, DQS1 = 0
1667 11:57:20.800199 DQM Delay:
1668 11:57:20.800693 DQM0 = 79, DQM1 = 72
1669 11:57:20.803626 DQ Delay:
1670 11:57:20.807019 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1671 11:57:20.810406 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1672 11:57:20.810961 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1673 11:57:20.817123 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1674 11:57:20.817669
1675 11:57:20.818033
1676 11:57:20.824711 [DQSOSCAuto] RK0, (LSB)MR18= 0x5555, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1677 11:57:20.827467 CH1 RK0: MR19=606, MR18=5555
1678 11:57:20.830815 CH1_RK0: MR19=0x606, MR18=0x5555, DQSOSC=388, MR23=63, INC=98, DEC=65
1679 11:57:20.831338
1680 11:57:20.838075 ----->DramcWriteLeveling(PI) begin...
1681 11:57:20.838536 ==
1682 11:57:20.840968 Dram Type= 6, Freq= 0, CH_1, rank 1
1683 11:57:20.844260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1684 11:57:20.844863 ==
1685 11:57:20.847782 Write leveling (Byte 0): 26 => 26
1686 11:57:20.851273 Write leveling (Byte 1): 26 => 26
1687 11:57:20.854399 DramcWriteLeveling(PI) end<-----
1688 11:57:20.854916
1689 11:57:20.855283 ==
1690 11:57:20.857460 Dram Type= 6, Freq= 0, CH_1, rank 1
1691 11:57:20.861317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1692 11:57:20.861882 ==
1693 11:57:20.864255 [Gating] SW mode calibration
1694 11:57:20.870837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1695 11:57:20.877587 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1696 11:57:20.881167 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1697 11:57:20.883950 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 11:57:20.887573 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 11:57:20.894364 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 11:57:20.897251 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 11:57:20.901188 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 11:57:20.907614 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 11:57:20.910861 0 6 28 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
1704 11:57:20.913932 0 7 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1705 11:57:20.920784 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 11:57:20.924356 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 11:57:20.927274 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 11:57:20.934086 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 11:57:20.937370 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 11:57:20.940855 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 11:57:20.947646 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1712 11:57:20.950800 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1713 11:57:20.953799 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 11:57:20.960493 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 11:57:20.963985 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 11:57:20.967494 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 11:57:20.974028 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 11:57:20.977153 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:57:20.980662 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:57:20.987218 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:57:20.990644 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 11:57:20.993962 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 11:57:20.997127 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 11:57:21.004013 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 11:57:21.007718 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 11:57:21.010672 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 11:57:21.016990 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1728 11:57:21.020684 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 11:57:21.023745 Total UI for P1: 0, mck2ui 16
1730 11:57:21.027036 best dqsien dly found for B0: ( 0, 9, 28)
1731 11:57:21.030368 Total UI for P1: 0, mck2ui 16
1732 11:57:21.033730 best dqsien dly found for B1: ( 0, 9, 30)
1733 11:57:21.036981 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1734 11:57:21.040325 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1735 11:57:21.040848
1736 11:57:21.043672 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1737 11:57:21.047307 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1738 11:57:21.050459 [Gating] SW calibration Done
1739 11:57:21.050979 ==
1740 11:57:21.053848 Dram Type= 6, Freq= 0, CH_1, rank 1
1741 11:57:21.060237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 11:57:21.060698 ==
1743 11:57:21.061037 RX Vref Scan: 0
1744 11:57:21.061345
1745 11:57:21.064036 RX Vref 0 -> 0, step: 1
1746 11:57:21.064450
1747 11:57:21.067320 RX Delay -130 -> 252, step: 16
1748 11:57:21.070371 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1749 11:57:21.074022 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1750 11:57:21.077056 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1751 11:57:21.080196 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1752 11:57:21.086928 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1753 11:57:21.090535 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1754 11:57:21.093605 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1755 11:57:21.097233 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1756 11:57:21.100788 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1757 11:57:21.107411 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1758 11:57:21.110435 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1759 11:57:21.113749 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1760 11:57:21.117313 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1761 11:57:21.120678 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1762 11:57:21.127275 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1763 11:57:21.130713 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1764 11:57:21.131292 ==
1765 11:57:21.133772 Dram Type= 6, Freq= 0, CH_1, rank 1
1766 11:57:21.137324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1767 11:57:21.137889 ==
1768 11:57:21.140656 DQS Delay:
1769 11:57:21.141217 DQS0 = 0, DQS1 = 0
1770 11:57:21.141587 DQM Delay:
1771 11:57:21.144124 DQM0 = 84, DQM1 = 73
1772 11:57:21.144765 DQ Delay:
1773 11:57:21.147415 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1774 11:57:21.150416 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1775 11:57:21.154278 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1776 11:57:21.157181 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1777 11:57:21.157643
1778 11:57:21.158008
1779 11:57:21.158351 ==
1780 11:57:21.160368 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 11:57:21.167332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1782 11:57:21.167897 ==
1783 11:57:21.168267
1784 11:57:21.168662
1785 11:57:21.168999 TX Vref Scan disable
1786 11:57:21.170324 == TX Byte 0 ==
1787 11:57:21.173832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1788 11:57:21.180665 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1789 11:57:21.181229 == TX Byte 1 ==
1790 11:57:21.183675 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1791 11:57:21.190530 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1792 11:57:21.191096 ==
1793 11:57:21.193700 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 11:57:21.196867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1795 11:57:21.197330 ==
1796 11:57:21.209492 TX Vref=22, minBit 8, minWin=27, winSum=447
1797 11:57:21.212976 TX Vref=24, minBit 8, minWin=27, winSum=452
1798 11:57:21.215646 TX Vref=26, minBit 0, minWin=28, winSum=454
1799 11:57:21.219370 TX Vref=28, minBit 0, minWin=28, winSum=457
1800 11:57:21.222747 TX Vref=30, minBit 0, minWin=28, winSum=456
1801 11:57:21.229501 TX Vref=32, minBit 0, minWin=28, winSum=454
1802 11:57:21.232354 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1803 11:57:21.232848
1804 11:57:21.235507 Final TX Range 1 Vref 28
1805 11:57:21.235916
1806 11:57:21.236259 ==
1807 11:57:21.239145 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 11:57:21.242832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1809 11:57:21.243389 ==
1810 11:57:21.246359
1811 11:57:21.246908
1812 11:57:21.247266 TX Vref Scan disable
1813 11:57:21.249084 == TX Byte 0 ==
1814 11:57:21.252618 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1815 11:57:21.256019 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1816 11:57:21.259588 == TX Byte 1 ==
1817 11:57:21.262565 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1818 11:57:21.265882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1819 11:57:21.269488
1820 11:57:21.270037 [DATLAT]
1821 11:57:21.270397 Freq=800, CH1 RK1
1822 11:57:21.270737
1823 11:57:21.272483 DATLAT Default: 0x9
1824 11:57:21.272970 0, 0xFFFF, sum = 0
1825 11:57:21.276350 1, 0xFFFF, sum = 0
1826 11:57:21.276955 2, 0xFFFF, sum = 0
1827 11:57:21.279266 3, 0xFFFF, sum = 0
1828 11:57:21.279849 4, 0xFFFF, sum = 0
1829 11:57:21.282541 5, 0xFFFF, sum = 0
1830 11:57:21.285866 6, 0xFFFF, sum = 0
1831 11:57:21.286424 7, 0xFFFF, sum = 0
1832 11:57:21.286789 8, 0x0, sum = 1
1833 11:57:21.289234 9, 0x0, sum = 2
1834 11:57:21.289816 10, 0x0, sum = 3
1835 11:57:21.292381 11, 0x0, sum = 4
1836 11:57:21.292895 best_step = 9
1837 11:57:21.293260
1838 11:57:21.293610 ==
1839 11:57:21.295677 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 11:57:21.302396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 11:57:21.302919 ==
1842 11:57:21.303276 RX Vref Scan: 0
1843 11:57:21.303613
1844 11:57:21.305737 RX Vref 0 -> 0, step: 1
1845 11:57:21.306187
1846 11:57:21.309019 RX Delay -111 -> 252, step: 8
1847 11:57:21.312483 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1848 11:57:21.316070 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1849 11:57:21.322341 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1850 11:57:21.326217 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1851 11:57:21.328997 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1852 11:57:21.332254 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1853 11:57:21.335951 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1854 11:57:21.342312 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1855 11:57:21.345790 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1856 11:57:21.349570 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1857 11:57:21.352354 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1858 11:57:21.355753 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1859 11:57:21.362745 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1860 11:57:21.366157 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1861 11:57:21.369460 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1862 11:57:21.372842 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1863 11:57:21.373497 ==
1864 11:57:21.375965 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 11:57:21.379258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1866 11:57:21.382696 ==
1867 11:57:21.383354 DQS Delay:
1868 11:57:21.383734 DQS0 = 0, DQS1 = 0
1869 11:57:21.385556 DQM Delay:
1870 11:57:21.386077 DQM0 = 82, DQM1 = 72
1871 11:57:21.389228 DQ Delay:
1872 11:57:21.392780 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1873 11:57:21.393311 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1874 11:57:21.396013 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1875 11:57:21.399120 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1876 11:57:21.402462
1877 11:57:21.403195
1878 11:57:21.409115 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1879 11:57:21.412294 CH1 RK1: MR19=606, MR18=3636
1880 11:57:21.419185 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1881 11:57:21.422454 [RxdqsGatingPostProcess] freq 800
1882 11:57:21.425723 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1883 11:57:21.428817 Pre-setting of DQS Precalculation
1884 11:57:21.432189 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1885 11:57:21.442540 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1886 11:57:21.448867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1887 11:57:21.449432
1888 11:57:21.449844
1889 11:57:21.452415 [Calibration Summary] 1600 Mbps
1890 11:57:21.453005 CH 0, Rank 0
1891 11:57:21.455819 SW Impedance : PASS
1892 11:57:21.456365 DUTY Scan : NO K
1893 11:57:21.459008 ZQ Calibration : PASS
1894 11:57:21.462540 Jitter Meter : NO K
1895 11:57:21.463089 CBT Training : PASS
1896 11:57:21.465910 Write leveling : PASS
1897 11:57:21.469151 RX DQS gating : PASS
1898 11:57:21.469701 RX DQ/DQS(RDDQC) : PASS
1899 11:57:21.472141 TX DQ/DQS : PASS
1900 11:57:21.475491 RX DATLAT : PASS
1901 11:57:21.476198 RX DQ/DQS(Engine): PASS
1902 11:57:21.479122 TX OE : NO K
1903 11:57:21.479804 All Pass.
1904 11:57:21.480177
1905 11:57:21.482280 CH 0, Rank 1
1906 11:57:21.483003 SW Impedance : PASS
1907 11:57:21.485603 DUTY Scan : NO K
1908 11:57:21.488695 ZQ Calibration : PASS
1909 11:57:21.489161 Jitter Meter : NO K
1910 11:57:21.492180 CBT Training : PASS
1911 11:57:21.495768 Write leveling : PASS
1912 11:57:21.496324 RX DQS gating : PASS
1913 11:57:21.498697 RX DQ/DQS(RDDQC) : PASS
1914 11:57:21.499152 TX DQ/DQS : PASS
1915 11:57:21.502837 RX DATLAT : PASS
1916 11:57:21.505948 RX DQ/DQS(Engine): PASS
1917 11:57:21.506509 TX OE : NO K
1918 11:57:21.508884 All Pass.
1919 11:57:21.509343
1920 11:57:21.509705 CH 1, Rank 0
1921 11:57:21.512494 SW Impedance : PASS
1922 11:57:21.513091 DUTY Scan : NO K
1923 11:57:21.515701 ZQ Calibration : PASS
1924 11:57:21.519253 Jitter Meter : NO K
1925 11:57:21.519832 CBT Training : PASS
1926 11:57:21.522380 Write leveling : PASS
1927 11:57:21.525794 RX DQS gating : PASS
1928 11:57:21.526256 RX DQ/DQS(RDDQC) : PASS
1929 11:57:21.528913 TX DQ/DQS : PASS
1930 11:57:21.532193 RX DATLAT : PASS
1931 11:57:21.532821 RX DQ/DQS(Engine): PASS
1932 11:57:21.535911 TX OE : NO K
1933 11:57:21.536478 All Pass.
1934 11:57:21.536909
1935 11:57:21.539438 CH 1, Rank 1
1936 11:57:21.539996 SW Impedance : PASS
1937 11:57:21.542792 DUTY Scan : NO K
1938 11:57:21.543353 ZQ Calibration : PASS
1939 11:57:21.545379 Jitter Meter : NO K
1940 11:57:21.549052 CBT Training : PASS
1941 11:57:21.549615 Write leveling : PASS
1942 11:57:21.552602 RX DQS gating : PASS
1943 11:57:21.555850 RX DQ/DQS(RDDQC) : PASS
1944 11:57:21.556407 TX DQ/DQS : PASS
1945 11:57:21.559048 RX DATLAT : PASS
1946 11:57:21.562393 RX DQ/DQS(Engine): PASS
1947 11:57:21.562963 TX OE : NO K
1948 11:57:21.565640 All Pass.
1949 11:57:21.566098
1950 11:57:21.566463 DramC Write-DBI off
1951 11:57:21.569285 PER_BANK_REFRESH: Hybrid Mode
1952 11:57:21.569847 TX_TRACKING: ON
1953 11:57:21.572598 [GetDramInforAfterCalByMRR] Vendor 6.
1954 11:57:21.579175 [GetDramInforAfterCalByMRR] Revision 606.
1955 11:57:21.582191 [GetDramInforAfterCalByMRR] Revision 2 0.
1956 11:57:21.582749 MR0 0x3939
1957 11:57:21.583122 MR8 0x1111
1958 11:57:21.585246 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1959 11:57:21.585708
1960 11:57:21.588950 MR0 0x3939
1961 11:57:21.589507 MR8 0x1111
1962 11:57:21.592379 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1963 11:57:21.592990
1964 11:57:21.602468 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1965 11:57:21.605843 [FAST_K] Save calibration result to emmc
1966 11:57:21.608910 [FAST_K] Save calibration result to emmc
1967 11:57:21.612468 dram_init: config_dvfs: 1
1968 11:57:21.615735 dramc_set_vcore_voltage set vcore to 662500
1969 11:57:21.618738 Read voltage for 1200, 2
1970 11:57:21.619204 Vio18 = 0
1971 11:57:21.619571 Vcore = 662500
1972 11:57:21.622135 Vdram = 0
1973 11:57:21.622594 Vddq = 0
1974 11:57:21.622955 Vmddr = 0
1975 11:57:21.628976 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1976 11:57:21.632024 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1977 11:57:21.635268 MEM_TYPE=3, freq_sel=15
1978 11:57:21.639197 sv_algorithm_assistance_LP4_1600
1979 11:57:21.642144 ============ PULL DRAM RESETB DOWN ============
1980 11:57:21.645691 ========== PULL DRAM RESETB DOWN end =========
1981 11:57:21.652667 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1982 11:57:21.655776 ===================================
1983 11:57:21.656337 LPDDR4 DRAM CONFIGURATION
1984 11:57:21.659106 ===================================
1985 11:57:21.662271 EX_ROW_EN[0] = 0x0
1986 11:57:21.665434 EX_ROW_EN[1] = 0x0
1987 11:57:21.665904 LP4Y_EN = 0x0
1988 11:57:21.669325 WORK_FSP = 0x0
1989 11:57:21.669888 WL = 0x4
1990 11:57:21.672372 RL = 0x4
1991 11:57:21.672975 BL = 0x2
1992 11:57:21.675577 RPST = 0x0
1993 11:57:21.676134 RD_PRE = 0x0
1994 11:57:21.679283 WR_PRE = 0x1
1995 11:57:21.679836 WR_PST = 0x0
1996 11:57:21.682272 DBI_WR = 0x0
1997 11:57:21.682834 DBI_RD = 0x0
1998 11:57:21.685374 OTF = 0x1
1999 11:57:21.688904 ===================================
2000 11:57:21.692223 ===================================
2001 11:57:21.692856 ANA top config
2002 11:57:21.695187 ===================================
2003 11:57:21.698885 DLL_ASYNC_EN = 0
2004 11:57:21.702050 ALL_SLAVE_EN = 0
2005 11:57:21.702515 NEW_RANK_MODE = 1
2006 11:57:21.705218 DLL_IDLE_MODE = 1
2007 11:57:21.709137 LP45_APHY_COMB_EN = 1
2008 11:57:21.712455 TX_ODT_DIS = 1
2009 11:57:21.715788 NEW_8X_MODE = 1
2010 11:57:21.718492 ===================================
2011 11:57:21.722209 ===================================
2012 11:57:21.722773 data_rate = 2400
2013 11:57:21.725437 CKR = 1
2014 11:57:21.728536 DQ_P2S_RATIO = 8
2015 11:57:21.732131 ===================================
2016 11:57:21.735340 CA_P2S_RATIO = 8
2017 11:57:21.738872 DQ_CA_OPEN = 0
2018 11:57:21.742179 DQ_SEMI_OPEN = 0
2019 11:57:21.742640 CA_SEMI_OPEN = 0
2020 11:57:21.745403 CA_FULL_RATE = 0
2021 11:57:21.748942 DQ_CKDIV4_EN = 0
2022 11:57:21.752619 CA_CKDIV4_EN = 0
2023 11:57:21.755671 CA_PREDIV_EN = 0
2024 11:57:21.758832 PH8_DLY = 17
2025 11:57:21.759396 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2026 11:57:21.762009 DQ_AAMCK_DIV = 4
2027 11:57:21.765508 CA_AAMCK_DIV = 4
2028 11:57:21.769323 CA_ADMCK_DIV = 4
2029 11:57:21.772661 DQ_TRACK_CA_EN = 0
2030 11:57:21.775680 CA_PICK = 1200
2031 11:57:21.776241 CA_MCKIO = 1200
2032 11:57:21.779226 MCKIO_SEMI = 0
2033 11:57:21.782460 PLL_FREQ = 2366
2034 11:57:21.785492 DQ_UI_PI_RATIO = 32
2035 11:57:21.789121 CA_UI_PI_RATIO = 0
2036 11:57:21.792309 ===================================
2037 11:57:21.795365 ===================================
2038 11:57:21.799234 memory_type:LPDDR4
2039 11:57:21.799814 GP_NUM : 10
2040 11:57:21.802237 SRAM_EN : 1
2041 11:57:21.802798 MD32_EN : 0
2042 11:57:21.805281 ===================================
2043 11:57:21.809204 [ANA_INIT] >>>>>>>>>>>>>>
2044 11:57:21.812032 <<<<<< [CONFIGURE PHASE]: ANA_TX
2045 11:57:21.815955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2046 11:57:21.818828 ===================================
2047 11:57:21.822420 data_rate = 2400,PCW = 0X5b00
2048 11:57:21.825524 ===================================
2049 11:57:21.828583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2050 11:57:21.835221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2051 11:57:21.838903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2052 11:57:21.845266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2053 11:57:21.848492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2054 11:57:21.851946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2055 11:57:21.852546 [ANA_INIT] flow start
2056 11:57:21.855551 [ANA_INIT] PLL >>>>>>>>
2057 11:57:21.858919 [ANA_INIT] PLL <<<<<<<<
2058 11:57:21.859478 [ANA_INIT] MIDPI >>>>>>>>
2059 11:57:21.862131 [ANA_INIT] MIDPI <<<<<<<<
2060 11:57:21.865173 [ANA_INIT] DLL >>>>>>>>
2061 11:57:21.865634 [ANA_INIT] DLL <<<<<<<<
2062 11:57:21.868836 [ANA_INIT] flow end
2063 11:57:21.872213 ============ LP4 DIFF to SE enter ============
2064 11:57:21.875721 ============ LP4 DIFF to SE exit ============
2065 11:57:21.878980 [ANA_INIT] <<<<<<<<<<<<<
2066 11:57:21.882000 [Flow] Enable top DCM control >>>>>
2067 11:57:21.885398 [Flow] Enable top DCM control <<<<<
2068 11:57:21.888775 Enable DLL master slave shuffle
2069 11:57:21.895730 ==============================================================
2070 11:57:21.896290 Gating Mode config
2071 11:57:21.901807 ==============================================================
2072 11:57:21.902368 Config description:
2073 11:57:21.911895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2074 11:57:21.918580 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2075 11:57:21.925081 SELPH_MODE 0: By rank 1: By Phase
2076 11:57:21.928448 ==============================================================
2077 11:57:21.931961 GAT_TRACK_EN = 1
2078 11:57:21.935478 RX_GATING_MODE = 2
2079 11:57:21.939007 RX_GATING_TRACK_MODE = 2
2080 11:57:21.941796 SELPH_MODE = 1
2081 11:57:21.945074 PICG_EARLY_EN = 1
2082 11:57:21.948662 VALID_LAT_VALUE = 1
2083 11:57:21.955169 ==============================================================
2084 11:57:21.958445 Enter into Gating configuration >>>>
2085 11:57:21.961798 Exit from Gating configuration <<<<
2086 11:57:21.962374 Enter into DVFS_PRE_config >>>>>
2087 11:57:21.974994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2088 11:57:21.978488 Exit from DVFS_PRE_config <<<<<
2089 11:57:21.982077 Enter into PICG configuration >>>>
2090 11:57:21.985227 Exit from PICG configuration <<<<
2091 11:57:21.985787 [RX_INPUT] configuration >>>>>
2092 11:57:21.988606 [RX_INPUT] configuration <<<<<
2093 11:57:21.995172 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2094 11:57:21.998036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2095 11:57:22.005411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 11:57:22.011999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 11:57:22.018177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2098 11:57:22.024950 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2099 11:57:22.028316 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2100 11:57:22.031363 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2101 11:57:22.038467 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2102 11:57:22.041549 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2103 11:57:22.044764 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2104 11:57:22.048132 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2105 11:57:22.051568 ===================================
2106 11:57:22.054941 LPDDR4 DRAM CONFIGURATION
2107 11:57:22.058367 ===================================
2108 11:57:22.061606 EX_ROW_EN[0] = 0x0
2109 11:57:22.062071 EX_ROW_EN[1] = 0x0
2110 11:57:22.064937 LP4Y_EN = 0x0
2111 11:57:22.065471 WORK_FSP = 0x0
2112 11:57:22.068155 WL = 0x4
2113 11:57:22.068653 RL = 0x4
2114 11:57:22.071539 BL = 0x2
2115 11:57:22.071998 RPST = 0x0
2116 11:57:22.074820 RD_PRE = 0x0
2117 11:57:22.075281 WR_PRE = 0x1
2118 11:57:22.078363 WR_PST = 0x0
2119 11:57:22.079061 DBI_WR = 0x0
2120 11:57:22.081763 DBI_RD = 0x0
2121 11:57:22.082312 OTF = 0x1
2122 11:57:22.085050 ===================================
2123 11:57:22.088592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2124 11:57:22.095085 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2125 11:57:22.098421 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 11:57:22.101824 ===================================
2127 11:57:22.105066 LPDDR4 DRAM CONFIGURATION
2128 11:57:22.108427 ===================================
2129 11:57:22.109032 EX_ROW_EN[0] = 0x10
2130 11:57:22.111624 EX_ROW_EN[1] = 0x0
2131 11:57:22.114969 LP4Y_EN = 0x0
2132 11:57:22.115512 WORK_FSP = 0x0
2133 11:57:22.118425 WL = 0x4
2134 11:57:22.118884 RL = 0x4
2135 11:57:22.121725 BL = 0x2
2136 11:57:22.122187 RPST = 0x0
2137 11:57:22.125127 RD_PRE = 0x0
2138 11:57:22.125589 WR_PRE = 0x1
2139 11:57:22.128454 WR_PST = 0x0
2140 11:57:22.128946 DBI_WR = 0x0
2141 11:57:22.131863 DBI_RD = 0x0
2142 11:57:22.132318 OTF = 0x1
2143 11:57:22.134986 ===================================
2144 11:57:22.142124 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2145 11:57:22.142541 ==
2146 11:57:22.145291 Dram Type= 6, Freq= 0, CH_0, rank 0
2147 11:57:22.148679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2148 11:57:22.149172 ==
2149 11:57:22.151789 [Duty_Offset_Calibration]
2150 11:57:22.155156 B0:0 B1:2 CA:1
2151 11:57:22.155572
2152 11:57:22.158402 [DutyScan_Calibration_Flow] k_type=0
2153 11:57:22.166777
2154 11:57:22.167293 ==CLK 0==
2155 11:57:22.170056 Final CLK duty delay cell = 0
2156 11:57:22.173418 [0] MAX Duty = 5093%(X100), DQS PI = 12
2157 11:57:22.176663 [0] MIN Duty = 4938%(X100), DQS PI = 52
2158 11:57:22.177194 [0] AVG Duty = 5015%(X100)
2159 11:57:22.179828
2160 11:57:22.180262 CH0 CLK Duty spec in!! Max-Min= 155%
2161 11:57:22.186606 [DutyScan_Calibration_Flow] ====Done====
2162 11:57:22.187114
2163 11:57:22.190133 [DutyScan_Calibration_Flow] k_type=1
2164 11:57:22.205697
2165 11:57:22.206230 ==DQS 0 ==
2166 11:57:22.209076 Final DQS duty delay cell = 0
2167 11:57:22.212316 [0] MAX Duty = 5125%(X100), DQS PI = 30
2168 11:57:22.215919 [0] MIN Duty = 5031%(X100), DQS PI = 4
2169 11:57:22.216382 [0] AVG Duty = 5078%(X100)
2170 11:57:22.219342
2171 11:57:22.219915 ==DQS 1 ==
2172 11:57:22.222472 Final DQS duty delay cell = 0
2173 11:57:22.225799 [0] MAX Duty = 5062%(X100), DQS PI = 58
2174 11:57:22.229356 [0] MIN Duty = 4906%(X100), DQS PI = 16
2175 11:57:22.229825 [0] AVG Duty = 4984%(X100)
2176 11:57:22.232702
2177 11:57:22.235895 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2178 11:57:22.236383
2179 11:57:22.239495 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2180 11:57:22.242693 [DutyScan_Calibration_Flow] ====Done====
2181 11:57:22.243110
2182 11:57:22.245566 [DutyScan_Calibration_Flow] k_type=3
2183 11:57:22.262959
2184 11:57:22.263475 ==DQM 0 ==
2185 11:57:22.266579 Final DQM duty delay cell = 0
2186 11:57:22.269424 [0] MAX Duty = 5124%(X100), DQS PI = 20
2187 11:57:22.272904 [0] MIN Duty = 4969%(X100), DQS PI = 40
2188 11:57:22.276187 [0] AVG Duty = 5046%(X100)
2189 11:57:22.276629
2190 11:57:22.276953 ==DQM 1 ==
2191 11:57:22.279684 Final DQM duty delay cell = 4
2192 11:57:22.283105 [4] MAX Duty = 5187%(X100), DQS PI = 56
2193 11:57:22.286433 [4] MIN Duty = 5000%(X100), DQS PI = 16
2194 11:57:22.289429 [4] AVG Duty = 5093%(X100)
2195 11:57:22.289899
2196 11:57:22.292901 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2197 11:57:22.293357
2198 11:57:22.296221 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2199 11:57:22.299944 [DutyScan_Calibration_Flow] ====Done====
2200 11:57:22.300470
2201 11:57:22.302990 [DutyScan_Calibration_Flow] k_type=2
2202 11:57:22.318159
2203 11:57:22.318705 ==DQ 0 ==
2204 11:57:22.321402 Final DQ duty delay cell = -4
2205 11:57:22.324739 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2206 11:57:22.328069 [-4] MIN Duty = 4813%(X100), DQS PI = 44
2207 11:57:22.331503 [-4] AVG Duty = 4937%(X100)
2208 11:57:22.332054
2209 11:57:22.332415 ==DQ 1 ==
2210 11:57:22.334526 Final DQ duty delay cell = -4
2211 11:57:22.337694 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2212 11:57:22.341331 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2213 11:57:22.344836 [-4] AVG Duty = 4969%(X100)
2214 11:57:22.345383
2215 11:57:22.348123 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2216 11:57:22.348714
2217 11:57:22.351421 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2218 11:57:22.354681 [DutyScan_Calibration_Flow] ====Done====
2219 11:57:22.355234 ==
2220 11:57:22.358267 Dram Type= 6, Freq= 0, CH_1, rank 0
2221 11:57:22.361236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2222 11:57:22.361784 ==
2223 11:57:22.364943 [Duty_Offset_Calibration]
2224 11:57:22.365617 B0:0 B1:5 CA:-5
2225 11:57:22.366126
2226 11:57:22.368009 [DutyScan_Calibration_Flow] k_type=0
2227 11:57:22.379123
2228 11:57:22.379687 ==CLK 0==
2229 11:57:22.382144 Final CLK duty delay cell = 0
2230 11:57:22.385254 [0] MAX Duty = 5094%(X100), DQS PI = 24
2231 11:57:22.388680 [0] MIN Duty = 4907%(X100), DQS PI = 44
2232 11:57:22.389136 [0] AVG Duty = 5000%(X100)
2233 11:57:22.392380
2234 11:57:22.392978 CH1 CLK Duty spec in!! Max-Min= 187%
2235 11:57:22.399042 [DutyScan_Calibration_Flow] ====Done====
2236 11:57:22.399744
2237 11:57:22.401958 [DutyScan_Calibration_Flow] k_type=1
2238 11:57:22.417290
2239 11:57:22.417841 ==DQS 0 ==
2240 11:57:22.420472 Final DQS duty delay cell = 0
2241 11:57:22.423711 [0] MAX Duty = 5125%(X100), DQS PI = 16
2242 11:57:22.427560 [0] MIN Duty = 4875%(X100), DQS PI = 40
2243 11:57:22.430556 [0] AVG Duty = 5000%(X100)
2244 11:57:22.431110
2245 11:57:22.431471 ==DQS 1 ==
2246 11:57:22.433580 Final DQS duty delay cell = -4
2247 11:57:22.437127 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2248 11:57:22.440488 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2249 11:57:22.443841 [-4] AVG Duty = 4953%(X100)
2250 11:57:22.444391
2251 11:57:22.447230 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2252 11:57:22.447780
2253 11:57:22.450505 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2254 11:57:22.453672 [DutyScan_Calibration_Flow] ====Done====
2255 11:57:22.454124
2256 11:57:22.456897 [DutyScan_Calibration_Flow] k_type=3
2257 11:57:22.472673
2258 11:57:22.473221 ==DQM 0 ==
2259 11:57:22.475886 Final DQM duty delay cell = -4
2260 11:57:22.479030 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2261 11:57:22.482555 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2262 11:57:22.485790 [-4] AVG Duty = 4969%(X100)
2263 11:57:22.486343
2264 11:57:22.486699 ==DQM 1 ==
2265 11:57:22.489044 Final DQM duty delay cell = -4
2266 11:57:22.492263 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2267 11:57:22.495968 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2268 11:57:22.499082 [-4] AVG Duty = 5000%(X100)
2269 11:57:22.499629
2270 11:57:22.502145 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2271 11:57:22.502694
2272 11:57:22.505395 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2273 11:57:22.509129 [DutyScan_Calibration_Flow] ====Done====
2274 11:57:22.509677
2275 11:57:22.512305 [DutyScan_Calibration_Flow] k_type=2
2276 11:57:22.529520
2277 11:57:22.530068 ==DQ 0 ==
2278 11:57:22.533280 Final DQ duty delay cell = 0
2279 11:57:22.536289 [0] MAX Duty = 5062%(X100), DQS PI = 0
2280 11:57:22.539876 [0] MIN Duty = 4969%(X100), DQS PI = 44
2281 11:57:22.540423 [0] AVG Duty = 5015%(X100)
2282 11:57:22.540850
2283 11:57:22.542988 ==DQ 1 ==
2284 11:57:22.546353 Final DQ duty delay cell = 0
2285 11:57:22.550144 [0] MAX Duty = 5031%(X100), DQS PI = 8
2286 11:57:22.553228 [0] MIN Duty = 4907%(X100), DQS PI = 0
2287 11:57:22.553779 [0] AVG Duty = 4969%(X100)
2288 11:57:22.554139
2289 11:57:22.556245 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2290 11:57:22.556839
2291 11:57:22.559919 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2292 11:57:22.562953 [DutyScan_Calibration_Flow] ====Done====
2293 11:57:22.568311 nWR fixed to 30
2294 11:57:22.571814 [ModeRegInit_LP4] CH0 RK0
2295 11:57:22.572258 [ModeRegInit_LP4] CH0 RK1
2296 11:57:22.574980 [ModeRegInit_LP4] CH1 RK0
2297 11:57:22.578447 [ModeRegInit_LP4] CH1 RK1
2298 11:57:22.578926 match AC timing 6
2299 11:57:22.585211 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2300 11:57:22.588643 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2301 11:57:22.591765 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2302 11:57:22.598404 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2303 11:57:22.601544 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2304 11:57:22.601992 ==
2305 11:57:22.604985 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 11:57:22.608498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2307 11:57:22.609042 ==
2308 11:57:22.614958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2309 11:57:22.621487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2310 11:57:22.629004 [CA 0] Center 39 (9~70) winsize 62
2311 11:57:22.632122 [CA 1] Center 39 (8~70) winsize 63
2312 11:57:22.635480 [CA 2] Center 36 (5~67) winsize 63
2313 11:57:22.639025 [CA 3] Center 35 (4~66) winsize 63
2314 11:57:22.642414 [CA 4] Center 34 (3~65) winsize 63
2315 11:57:22.645762 [CA 5] Center 33 (3~64) winsize 62
2316 11:57:22.646270
2317 11:57:22.648981 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2318 11:57:22.649385
2319 11:57:22.652635 [CATrainingPosCal] consider 1 rank data
2320 11:57:22.655794 u2DelayCellTimex100 = 270/100 ps
2321 11:57:22.659325 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2322 11:57:22.662448 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2323 11:57:22.669069 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2324 11:57:22.672361 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2325 11:57:22.676001 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2326 11:57:22.678983 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2327 11:57:22.679392
2328 11:57:22.682419 CA PerBit enable=1, Macro0, CA PI delay=33
2329 11:57:22.682927
2330 11:57:22.685812 [CBTSetCACLKResult] CA Dly = 33
2331 11:57:22.686316 CS Dly: 7 (0~38)
2332 11:57:22.688959 ==
2333 11:57:22.689389 Dram Type= 6, Freq= 0, CH_0, rank 1
2334 11:57:22.695713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2335 11:57:22.696218 ==
2336 11:57:22.699251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2337 11:57:22.705698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2338 11:57:22.714638 [CA 0] Center 39 (8~70) winsize 63
2339 11:57:22.718149 [CA 1] Center 38 (8~69) winsize 62
2340 11:57:22.721076 [CA 2] Center 35 (5~66) winsize 62
2341 11:57:22.724259 [CA 3] Center 35 (4~66) winsize 63
2342 11:57:22.727883 [CA 4] Center 33 (3~64) winsize 62
2343 11:57:22.731629 [CA 5] Center 34 (3~65) winsize 63
2344 11:57:22.732130
2345 11:57:22.734885 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2346 11:57:22.735454
2347 11:57:22.737679 [CATrainingPosCal] consider 2 rank data
2348 11:57:22.741270 u2DelayCellTimex100 = 270/100 ps
2349 11:57:22.744803 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2350 11:57:22.747710 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2351 11:57:22.754701 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2352 11:57:22.758013 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2353 11:57:22.761463 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2354 11:57:22.764746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2355 11:57:22.765295
2356 11:57:22.768015 CA PerBit enable=1, Macro0, CA PI delay=33
2357 11:57:22.768623
2358 11:57:22.770871 [CBTSetCACLKResult] CA Dly = 33
2359 11:57:22.771328 CS Dly: 7 (0~39)
2360 11:57:22.771688
2361 11:57:22.774574 ----->DramcWriteLeveling(PI) begin...
2362 11:57:22.778054 ==
2363 11:57:22.781237 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 11:57:22.784661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2365 11:57:22.785226 ==
2366 11:57:22.787778 Write leveling (Byte 0): 28 => 28
2367 11:57:22.791464 Write leveling (Byte 1): 26 => 26
2368 11:57:22.794265 DramcWriteLeveling(PI) end<-----
2369 11:57:22.794722
2370 11:57:22.795082 ==
2371 11:57:22.797761 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 11:57:22.801256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2373 11:57:22.801718 ==
2374 11:57:22.804910 [Gating] SW mode calibration
2375 11:57:22.811103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2376 11:57:22.814637 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2377 11:57:22.821150 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 11:57:22.824755 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 11:57:22.827663 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 11:57:22.834415 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 11:57:22.837876 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2382 11:57:22.841239 0 11 20 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (0 0)
2383 11:57:22.848055 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 11:57:22.851308 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 11:57:22.854728 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 11:57:22.861364 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 11:57:22.865028 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 11:57:22.867823 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 11:57:22.874665 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2390 11:57:22.877745 0 12 20 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)
2391 11:57:22.881233 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 11:57:22.887898 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 11:57:22.891772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 11:57:22.894766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 11:57:22.901141 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 11:57:22.904695 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 11:57:22.907628 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2398 11:57:22.911439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2399 11:57:22.917926 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 11:57:22.921152 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 11:57:22.924565 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 11:57:22.931388 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 11:57:22.934614 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 11:57:22.937634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 11:57:22.944263 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:57:22.947647 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:57:22.951273 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:57:22.957968 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 11:57:22.961032 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 11:57:22.964713 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 11:57:22.971223 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 11:57:22.974409 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 11:57:22.977791 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 11:57:22.984581 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2415 11:57:22.985134 Total UI for P1: 0, mck2ui 16
2416 11:57:22.988055 best dqsien dly found for B0: ( 0, 15, 18)
2417 11:57:22.994389 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2418 11:57:22.997674 Total UI for P1: 0, mck2ui 16
2419 11:57:23.001144 best dqsien dly found for B1: ( 0, 15, 20)
2420 11:57:23.004583 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2421 11:57:23.007866 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2422 11:57:23.008424
2423 11:57:23.011162 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2424 11:57:23.014518 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2425 11:57:23.018079 [Gating] SW calibration Done
2426 11:57:23.018639 ==
2427 11:57:23.021437 Dram Type= 6, Freq= 0, CH_0, rank 0
2428 11:57:23.024229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2429 11:57:23.024838 ==
2430 11:57:23.027800 RX Vref Scan: 0
2431 11:57:23.028259
2432 11:57:23.030948 RX Vref 0 -> 0, step: 1
2433 11:57:23.031536
2434 11:57:23.031911 RX Delay -40 -> 252, step: 8
2435 11:57:23.037564 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2436 11:57:23.041508 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2437 11:57:23.044180 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2438 11:57:23.047865 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2439 11:57:23.051429 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2440 11:57:23.057906 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2441 11:57:23.061191 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2442 11:57:23.064635 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2443 11:57:23.067639 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2444 11:57:23.070957 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2445 11:57:23.077695 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2446 11:57:23.081068 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2447 11:57:23.084461 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2448 11:57:23.087766 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2449 11:57:23.090991 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2450 11:57:23.097625 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2451 11:57:23.098176 ==
2452 11:57:23.101061 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 11:57:23.104650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2454 11:57:23.105206 ==
2455 11:57:23.105573 DQS Delay:
2456 11:57:23.107922 DQS0 = 0, DQS1 = 0
2457 11:57:23.108568 DQM Delay:
2458 11:57:23.110904 DQM0 = 115, DQM1 = 106
2459 11:57:23.111361 DQ Delay:
2460 11:57:23.114422 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2461 11:57:23.117934 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2462 11:57:23.120882 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2463 11:57:23.124589 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2464 11:57:23.125162
2465 11:57:23.125527
2466 11:57:23.125863 ==
2467 11:57:23.127647 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 11:57:23.134148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2469 11:57:23.134899 ==
2470 11:57:23.135343
2471 11:57:23.135926
2472 11:57:23.136289 TX Vref Scan disable
2473 11:57:23.137822 == TX Byte 0 ==
2474 11:57:23.141098 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2475 11:57:23.148081 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2476 11:57:23.148694 == TX Byte 1 ==
2477 11:57:23.151362 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2478 11:57:23.157982 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2479 11:57:23.158545 ==
2480 11:57:23.161136 Dram Type= 6, Freq= 0, CH_0, rank 0
2481 11:57:23.164938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2482 11:57:23.165494 ==
2483 11:57:23.176243 TX Vref=22, minBit 9, minWin=24, winSum=412
2484 11:57:23.179330 TX Vref=24, minBit 10, minWin=25, winSum=421
2485 11:57:23.182708 TX Vref=26, minBit 10, minWin=24, winSum=431
2486 11:57:23.185953 TX Vref=28, minBit 10, minWin=26, winSum=435
2487 11:57:23.189388 TX Vref=30, minBit 9, minWin=26, winSum=433
2488 11:57:23.196004 TX Vref=32, minBit 8, minWin=26, winSum=433
2489 11:57:23.199296 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2490 11:57:23.199856
2491 11:57:23.202523 Final TX Range 1 Vref 28
2492 11:57:23.203075
2493 11:57:23.203436 ==
2494 11:57:23.206138 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 11:57:23.209482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2496 11:57:23.212719 ==
2497 11:57:23.213340
2498 11:57:23.213707
2499 11:57:23.214044 TX Vref Scan disable
2500 11:57:23.215628 == TX Byte 0 ==
2501 11:57:23.219147 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2502 11:57:23.225901 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2503 11:57:23.226463 == TX Byte 1 ==
2504 11:57:23.229255 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2505 11:57:23.235910 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2506 11:57:23.236472
2507 11:57:23.236896 [DATLAT]
2508 11:57:23.237238 Freq=1200, CH0 RK0
2509 11:57:23.237564
2510 11:57:23.239249 DATLAT Default: 0xd
2511 11:57:23.239700 0, 0xFFFF, sum = 0
2512 11:57:23.242467 1, 0xFFFF, sum = 0
2513 11:57:23.243019 2, 0xFFFF, sum = 0
2514 11:57:23.245922 3, 0xFFFF, sum = 0
2515 11:57:23.249184 4, 0xFFFF, sum = 0
2516 11:57:23.249642 5, 0xFFFF, sum = 0
2517 11:57:23.252262 6, 0xFFFF, sum = 0
2518 11:57:23.252772 7, 0xFFFF, sum = 0
2519 11:57:23.255587 8, 0xFFFF, sum = 0
2520 11:57:23.256042 9, 0xFFFF, sum = 0
2521 11:57:23.259345 10, 0xFFFF, sum = 0
2522 11:57:23.259903 11, 0x0, sum = 1
2523 11:57:23.262813 12, 0x0, sum = 2
2524 11:57:23.263374 13, 0x0, sum = 3
2525 11:57:23.265845 14, 0x0, sum = 4
2526 11:57:23.266403 best_step = 12
2527 11:57:23.266769
2528 11:57:23.267101 ==
2529 11:57:23.269129 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 11:57:23.272632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 11:57:23.273192 ==
2532 11:57:23.275830 RX Vref Scan: 1
2533 11:57:23.276383
2534 11:57:23.279113 Set Vref Range= 32 -> 127
2535 11:57:23.279562
2536 11:57:23.279917 RX Vref 32 -> 127, step: 1
2537 11:57:23.280251
2538 11:57:23.282385 RX Delay -21 -> 252, step: 4
2539 11:57:23.282834
2540 11:57:23.285648 Set Vref, RX VrefLevel [Byte0]: 32
2541 11:57:23.289178 [Byte1]: 32
2542 11:57:23.292491
2543 11:57:23.292977 Set Vref, RX VrefLevel [Byte0]: 33
2544 11:57:23.295768 [Byte1]: 33
2545 11:57:23.300993
2546 11:57:23.301541 Set Vref, RX VrefLevel [Byte0]: 34
2547 11:57:23.303968 [Byte1]: 34
2548 11:57:23.308424
2549 11:57:23.308912 Set Vref, RX VrefLevel [Byte0]: 35
2550 11:57:23.311646 [Byte1]: 35
2551 11:57:23.316440
2552 11:57:23.317034 Set Vref, RX VrefLevel [Byte0]: 36
2553 11:57:23.319771 [Byte1]: 36
2554 11:57:23.324446
2555 11:57:23.325043 Set Vref, RX VrefLevel [Byte0]: 37
2556 11:57:23.327528 [Byte1]: 37
2557 11:57:23.332229
2558 11:57:23.332844 Set Vref, RX VrefLevel [Byte0]: 38
2559 11:57:23.335368 [Byte1]: 38
2560 11:57:23.340077
2561 11:57:23.340557 Set Vref, RX VrefLevel [Byte0]: 39
2562 11:57:23.343791 [Byte1]: 39
2563 11:57:23.348257
2564 11:57:23.348887 Set Vref, RX VrefLevel [Byte0]: 40
2565 11:57:23.354579 [Byte1]: 40
2566 11:57:23.355127
2567 11:57:23.358025 Set Vref, RX VrefLevel [Byte0]: 41
2568 11:57:23.361430 [Byte1]: 41
2569 11:57:23.361976
2570 11:57:23.364326 Set Vref, RX VrefLevel [Byte0]: 42
2571 11:57:23.368003 [Byte1]: 42
2572 11:57:23.371917
2573 11:57:23.372440 Set Vref, RX VrefLevel [Byte0]: 43
2574 11:57:23.375056 [Byte1]: 43
2575 11:57:23.379806
2576 11:57:23.380266 Set Vref, RX VrefLevel [Byte0]: 44
2577 11:57:23.383089 [Byte1]: 44
2578 11:57:23.388016
2579 11:57:23.388611 Set Vref, RX VrefLevel [Byte0]: 45
2580 11:57:23.391120 [Byte1]: 45
2581 11:57:23.395696
2582 11:57:23.396263 Set Vref, RX VrefLevel [Byte0]: 46
2583 11:57:23.398977 [Byte1]: 46
2584 11:57:23.403484
2585 11:57:23.404036 Set Vref, RX VrefLevel [Byte0]: 47
2586 11:57:23.406962 [Byte1]: 47
2587 11:57:23.411624
2588 11:57:23.412169 Set Vref, RX VrefLevel [Byte0]: 48
2589 11:57:23.414916 [Byte1]: 48
2590 11:57:23.419762
2591 11:57:23.420311 Set Vref, RX VrefLevel [Byte0]: 49
2592 11:57:23.422927 [Byte1]: 49
2593 11:57:23.427457
2594 11:57:23.428003 Set Vref, RX VrefLevel [Byte0]: 50
2595 11:57:23.430790 [Byte1]: 50
2596 11:57:23.435286
2597 11:57:23.435858 Set Vref, RX VrefLevel [Byte0]: 51
2598 11:57:23.438436 [Byte1]: 51
2599 11:57:23.443382
2600 11:57:23.443932 Set Vref, RX VrefLevel [Byte0]: 52
2601 11:57:23.446892 [Byte1]: 52
2602 11:57:23.451343
2603 11:57:23.451895 Set Vref, RX VrefLevel [Byte0]: 53
2604 11:57:23.454206 [Byte1]: 53
2605 11:57:23.459427
2606 11:57:23.459975 Set Vref, RX VrefLevel [Byte0]: 54
2607 11:57:23.462201 [Byte1]: 54
2608 11:57:23.466972
2609 11:57:23.467521 Set Vref, RX VrefLevel [Byte0]: 55
2610 11:57:23.470062 [Byte1]: 55
2611 11:57:23.475081
2612 11:57:23.475624 Set Vref, RX VrefLevel [Byte0]: 56
2613 11:57:23.477826 [Byte1]: 56
2614 11:57:23.482791
2615 11:57:23.483336 Set Vref, RX VrefLevel [Byte0]: 57
2616 11:57:23.485999 [Byte1]: 57
2617 11:57:23.490638
2618 11:57:23.491187 Set Vref, RX VrefLevel [Byte0]: 58
2619 11:57:23.494355 [Byte1]: 58
2620 11:57:23.498711
2621 11:57:23.499259 Set Vref, RX VrefLevel [Byte0]: 59
2622 11:57:23.502025 [Byte1]: 59
2623 11:57:23.506559
2624 11:57:23.507114 Set Vref, RX VrefLevel [Byte0]: 60
2625 11:57:23.509917 [Byte1]: 60
2626 11:57:23.514415
2627 11:57:23.514963 Set Vref, RX VrefLevel [Byte0]: 61
2628 11:57:23.517922 [Byte1]: 61
2629 11:57:23.522550
2630 11:57:23.523089 Set Vref, RX VrefLevel [Byte0]: 62
2631 11:57:23.525969 [Byte1]: 62
2632 11:57:23.530228
2633 11:57:23.531038 Set Vref, RX VrefLevel [Byte0]: 63
2634 11:57:23.533535 [Byte1]: 63
2635 11:57:23.538376
2636 11:57:23.538842 Set Vref, RX VrefLevel [Byte0]: 64
2637 11:57:23.541569 [Byte1]: 64
2638 11:57:23.546221
2639 11:57:23.546785 Set Vref, RX VrefLevel [Byte0]: 65
2640 11:57:23.549533 [Byte1]: 65
2641 11:57:23.554675
2642 11:57:23.555224 Set Vref, RX VrefLevel [Byte0]: 66
2643 11:57:23.557254 [Byte1]: 66
2644 11:57:23.562104
2645 11:57:23.562690 Final RX Vref Byte 0 = 50 to rank0
2646 11:57:23.565081 Final RX Vref Byte 1 = 48 to rank0
2647 11:57:23.568910 Final RX Vref Byte 0 = 50 to rank1
2648 11:57:23.572318 Final RX Vref Byte 1 = 48 to rank1==
2649 11:57:23.575669 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 11:57:23.582063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2651 11:57:23.582618 ==
2652 11:57:23.582979 DQS Delay:
2653 11:57:23.583312 DQS0 = 0, DQS1 = 0
2654 11:57:23.585192 DQM Delay:
2655 11:57:23.585641 DQM0 = 114, DQM1 = 105
2656 11:57:23.588794 DQ Delay:
2657 11:57:23.592206 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2658 11:57:23.595588 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2659 11:57:23.598618 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2660 11:57:23.601888 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2661 11:57:23.602438
2662 11:57:23.602798
2663 11:57:23.608970 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2664 11:57:23.612178 CH0 RK0: MR19=404, MR18=606
2665 11:57:23.619234 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2666 11:57:23.619793
2667 11:57:23.621762 ----->DramcWriteLeveling(PI) begin...
2668 11:57:23.622238 ==
2669 11:57:23.625382 Dram Type= 6, Freq= 0, CH_0, rank 1
2670 11:57:23.628897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2671 11:57:23.629449 ==
2672 11:57:23.632049 Write leveling (Byte 0): 28 => 28
2673 11:57:23.635319 Write leveling (Byte 1): 24 => 24
2674 11:57:23.638396 DramcWriteLeveling(PI) end<-----
2675 11:57:23.638856
2676 11:57:23.639216 ==
2677 11:57:23.641878 Dram Type= 6, Freq= 0, CH_0, rank 1
2678 11:57:23.645809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2679 11:57:23.648721 ==
2680 11:57:23.649263 [Gating] SW mode calibration
2681 11:57:23.658586 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2682 11:57:23.662017 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2683 11:57:23.665175 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 11:57:23.671888 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2685 11:57:23.674993 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2686 11:57:23.678396 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2687 11:57:23.685105 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2688 11:57:23.688145 0 11 20 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
2689 11:57:23.691874 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 11:57:23.698230 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 11:57:23.701382 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 11:57:23.704993 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 11:57:23.711668 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 11:57:23.714914 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2695 11:57:23.718680 0 12 16 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2696 11:57:23.725045 0 12 20 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2697 11:57:23.728209 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 11:57:23.731611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 11:57:23.738025 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 11:57:23.741337 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 11:57:23.744991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 11:57:23.751587 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2703 11:57:23.755162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2704 11:57:23.758069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2705 11:57:23.761354 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 11:57:23.768076 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 11:57:23.771757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 11:57:23.774899 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 11:57:23.781608 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 11:57:23.785190 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 11:57:23.788042 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 11:57:23.795300 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 11:57:23.798139 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 11:57:23.801452 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 11:57:23.808240 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 11:57:23.811574 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 11:57:23.815114 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 11:57:23.821463 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 11:57:23.824780 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2720 11:57:23.828067 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2721 11:57:23.834892 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2722 11:57:23.835443 Total UI for P1: 0, mck2ui 16
2723 11:57:23.841213 best dqsien dly found for B0: ( 0, 15, 18)
2724 11:57:23.841666 Total UI for P1: 0, mck2ui 16
2725 11:57:23.844976 best dqsien dly found for B1: ( 0, 15, 18)
2726 11:57:23.851336 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2727 11:57:23.854861 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2728 11:57:23.855405
2729 11:57:23.858100 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2730 11:57:23.861242 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2731 11:57:23.864778 [Gating] SW calibration Done
2732 11:57:23.865323 ==
2733 11:57:23.868204 Dram Type= 6, Freq= 0, CH_0, rank 1
2734 11:57:23.871577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2735 11:57:23.872140 ==
2736 11:57:23.875020 RX Vref Scan: 0
2737 11:57:23.875565
2738 11:57:23.875926 RX Vref 0 -> 0, step: 1
2739 11:57:23.876261
2740 11:57:23.878100 RX Delay -40 -> 252, step: 8
2741 11:57:23.881459 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2742 11:57:23.888383 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2743 11:57:23.891301 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2744 11:57:23.894891 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2745 11:57:23.897909 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2746 11:57:23.901000 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2747 11:57:23.908200 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2748 11:57:23.911468 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2749 11:57:23.914297 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2750 11:57:23.917665 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2751 11:57:23.921227 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2752 11:57:23.924610 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2753 11:57:23.931476 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2754 11:57:23.934534 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2755 11:57:23.937667 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2756 11:57:23.941233 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2757 11:57:23.941747 ==
2758 11:57:23.944630 Dram Type= 6, Freq= 0, CH_0, rank 1
2759 11:57:23.951786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2760 11:57:23.952382 ==
2761 11:57:23.952833 DQS Delay:
2762 11:57:23.955026 DQS0 = 0, DQS1 = 0
2763 11:57:23.955580 DQM Delay:
2764 11:57:23.955944 DQM0 = 115, DQM1 = 106
2765 11:57:23.958062 DQ Delay:
2766 11:57:23.961068 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111
2767 11:57:23.964775 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2768 11:57:23.968073 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2769 11:57:23.971507 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2770 11:57:23.972083
2771 11:57:23.972444
2772 11:57:23.972828 ==
2773 11:57:23.974712 Dram Type= 6, Freq= 0, CH_0, rank 1
2774 11:57:23.978049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2775 11:57:23.978690 ==
2776 11:57:23.981446
2777 11:57:23.981997
2778 11:57:23.982359 TX Vref Scan disable
2779 11:57:23.984388 == TX Byte 0 ==
2780 11:57:23.987921 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2781 11:57:23.991107 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2782 11:57:23.994761 == TX Byte 1 ==
2783 11:57:23.998158 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2784 11:57:24.001032 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2785 11:57:24.001495 ==
2786 11:57:24.004597 Dram Type= 6, Freq= 0, CH_0, rank 1
2787 11:57:24.011212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2788 11:57:24.011772 ==
2789 11:57:24.022361 TX Vref=22, minBit 8, minWin=25, winSum=418
2790 11:57:24.025564 TX Vref=24, minBit 8, minWin=25, winSum=425
2791 11:57:24.028716 TX Vref=26, minBit 1, minWin=26, winSum=427
2792 11:57:24.031852 TX Vref=28, minBit 8, minWin=26, winSum=430
2793 11:57:24.035371 TX Vref=30, minBit 8, minWin=26, winSum=435
2794 11:57:24.038738 TX Vref=32, minBit 8, minWin=25, winSum=435
2795 11:57:24.045264 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2796 11:57:24.045808
2797 11:57:24.048841 Final TX Range 1 Vref 30
2798 11:57:24.049299
2799 11:57:24.049661 ==
2800 11:57:24.052248 Dram Type= 6, Freq= 0, CH_0, rank 1
2801 11:57:24.055569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2802 11:57:24.056132 ==
2803 11:57:24.056498
2804 11:57:24.059151
2805 11:57:24.059874 TX Vref Scan disable
2806 11:57:24.062203 == TX Byte 0 ==
2807 11:57:24.065373 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2808 11:57:24.068431 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2809 11:57:24.072018 == TX Byte 1 ==
2810 11:57:24.075402 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2811 11:57:24.079075 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2812 11:57:24.079636
2813 11:57:24.082056 [DATLAT]
2814 11:57:24.082511 Freq=1200, CH0 RK1
2815 11:57:24.082930
2816 11:57:24.085478 DATLAT Default: 0xc
2817 11:57:24.086042 0, 0xFFFF, sum = 0
2818 11:57:24.088775 1, 0xFFFF, sum = 0
2819 11:57:24.089342 2, 0xFFFF, sum = 0
2820 11:57:24.092008 3, 0xFFFF, sum = 0
2821 11:57:24.092613 4, 0xFFFF, sum = 0
2822 11:57:24.095930 5, 0xFFFF, sum = 0
2823 11:57:24.096493 6, 0xFFFF, sum = 0
2824 11:57:24.098667 7, 0xFFFF, sum = 0
2825 11:57:24.102431 8, 0xFFFF, sum = 0
2826 11:57:24.102999 9, 0xFFFF, sum = 0
2827 11:57:24.105000 10, 0xFFFF, sum = 0
2828 11:57:24.105464 11, 0x0, sum = 1
2829 11:57:24.108711 12, 0x0, sum = 2
2830 11:57:24.109275 13, 0x0, sum = 3
2831 11:57:24.109649 14, 0x0, sum = 4
2832 11:57:24.111904 best_step = 12
2833 11:57:24.112355
2834 11:57:24.112773 ==
2835 11:57:24.115672 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 11:57:24.118624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2837 11:57:24.119101 ==
2838 11:57:24.122127 RX Vref Scan: 0
2839 11:57:24.122685
2840 11:57:24.123051 RX Vref 0 -> 0, step: 1
2841 11:57:24.123470
2842 11:57:24.125037 RX Delay -21 -> 252, step: 4
2843 11:57:24.132747 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2844 11:57:24.135802 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2845 11:57:24.138768 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2846 11:57:24.142494 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2847 11:57:24.145573 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2848 11:57:24.152701 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2849 11:57:24.156015 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2850 11:57:24.158935 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2851 11:57:24.162267 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2852 11:57:24.165682 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2853 11:57:24.172402 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2854 11:57:24.175650 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2855 11:57:24.179029 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2856 11:57:24.182122 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2857 11:57:24.185528 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2858 11:57:24.192271 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2859 11:57:24.192868 ==
2860 11:57:24.195837 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 11:57:24.198910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2862 11:57:24.199468 ==
2863 11:57:24.199835 DQS Delay:
2864 11:57:24.202275 DQS0 = 0, DQS1 = 0
2865 11:57:24.202826 DQM Delay:
2866 11:57:24.205458 DQM0 = 114, DQM1 = 106
2867 11:57:24.206008 DQ Delay:
2868 11:57:24.209320 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2869 11:57:24.212425 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2870 11:57:24.215908 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2871 11:57:24.219042 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =114
2872 11:57:24.219600
2873 11:57:24.219962
2874 11:57:24.229142 [DQSOSCAuto] RK1, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2875 11:57:24.232116 CH0 RK1: MR19=404, MR18=1313
2876 11:57:24.235667 CH0_RK1: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
2877 11:57:24.238569 [RxdqsGatingPostProcess] freq 1200
2878 11:57:24.245777 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2879 11:57:24.248960 Pre-setting of DQS Precalculation
2880 11:57:24.251901 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2881 11:57:24.255101 ==
2882 11:57:24.255555 Dram Type= 6, Freq= 0, CH_1, rank 0
2883 11:57:24.261939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2884 11:57:24.262446 ==
2885 11:57:24.265264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2886 11:57:24.271757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2887 11:57:24.281024 [CA 0] Center 37 (7~68) winsize 62
2888 11:57:24.284344 [CA 1] Center 37 (7~68) winsize 62
2889 11:57:24.287727 [CA 2] Center 34 (4~65) winsize 62
2890 11:57:24.291110 [CA 3] Center 33 (3~64) winsize 62
2891 11:57:24.294394 [CA 4] Center 32 (2~63) winsize 62
2892 11:57:24.297874 [CA 5] Center 32 (2~63) winsize 62
2893 11:57:24.298424
2894 11:57:24.301136 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2895 11:57:24.301688
2896 11:57:24.304188 [CATrainingPosCal] consider 1 rank data
2897 11:57:24.307702 u2DelayCellTimex100 = 270/100 ps
2898 11:57:24.310889 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2899 11:57:24.314386 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2900 11:57:24.320927 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2901 11:57:24.324309 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2902 11:57:24.327551 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2903 11:57:24.331046 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2904 11:57:24.331599
2905 11:57:24.333912 CA PerBit enable=1, Macro0, CA PI delay=32
2906 11:57:24.334364
2907 11:57:24.337458 [CBTSetCACLKResult] CA Dly = 32
2908 11:57:24.338117 CS Dly: 6 (0~37)
2909 11:57:24.340891 ==
2910 11:57:24.341346 Dram Type= 6, Freq= 0, CH_1, rank 1
2911 11:57:24.347481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2912 11:57:24.348030 ==
2913 11:57:24.351203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2914 11:57:24.357306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2915 11:57:24.366243 [CA 0] Center 37 (6~68) winsize 63
2916 11:57:24.369715 [CA 1] Center 37 (7~68) winsize 62
2917 11:57:24.372730 [CA 2] Center 33 (3~64) winsize 62
2918 11:57:24.376183 [CA 3] Center 33 (3~64) winsize 62
2919 11:57:24.379400 [CA 4] Center 32 (2~63) winsize 62
2920 11:57:24.382805 [CA 5] Center 32 (1~63) winsize 63
2921 11:57:24.383317
2922 11:57:24.386284 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2923 11:57:24.386735
2924 11:57:24.389543 [CATrainingPosCal] consider 2 rank data
2925 11:57:24.392983 u2DelayCellTimex100 = 270/100 ps
2926 11:57:24.396230 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2927 11:57:24.399516 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2928 11:57:24.403027 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2929 11:57:24.409425 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2930 11:57:24.413033 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2931 11:57:24.416047 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2932 11:57:24.416637
2933 11:57:24.419675 CA PerBit enable=1, Macro0, CA PI delay=32
2934 11:57:24.420164
2935 11:57:24.422843 [CBTSetCACLKResult] CA Dly = 32
2936 11:57:24.423291 CS Dly: 6 (0~38)
2937 11:57:24.423654
2938 11:57:24.426029 ----->DramcWriteLeveling(PI) begin...
2939 11:57:24.426508 ==
2940 11:57:24.429368 Dram Type= 6, Freq= 0, CH_1, rank 0
2941 11:57:24.436610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2942 11:57:24.437065 ==
2943 11:57:24.439542 Write leveling (Byte 0): 22 => 22
2944 11:57:24.443080 Write leveling (Byte 1): 22 => 22
2945 11:57:24.443494 DramcWriteLeveling(PI) end<-----
2946 11:57:24.446136
2947 11:57:24.446552 ==
2948 11:57:24.449552 Dram Type= 6, Freq= 0, CH_1, rank 0
2949 11:57:24.452832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2950 11:57:24.453246 ==
2951 11:57:24.456898 [Gating] SW mode calibration
2952 11:57:24.463190 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2953 11:57:24.466669 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2954 11:57:24.472861 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 11:57:24.476192 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 11:57:24.479890 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 11:57:24.486573 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 11:57:24.489841 0 11 16 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (0 1)
2959 11:57:24.493367 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2960 11:57:24.499905 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 11:57:24.503238 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 11:57:24.506439 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 11:57:24.513016 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 11:57:24.516390 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 11:57:24.519493 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2966 11:57:24.526232 0 12 16 | B1->B0 | 3232 3d3d | 0 0 | (1 1) (0 0)
2967 11:57:24.529446 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 11:57:24.532998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 11:57:24.539369 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:57:24.543117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:57:24.546199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:57:24.549459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 11:57:24.556445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 11:57:24.559675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2975 11:57:24.563189 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2976 11:57:24.569442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:57:24.573076 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:57:24.576100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:57:24.582988 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:57:24.586271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:57:24.589471 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:57:24.596489 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:57:24.599643 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:57:24.603342 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:57:24.609661 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:57:24.613544 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:57:24.616381 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:57:24.622895 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 11:57:24.626490 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2990 11:57:24.629724 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2991 11:57:24.633218 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2992 11:57:24.636534 Total UI for P1: 0, mck2ui 16
2993 11:57:24.639427 best dqsien dly found for B0: ( 0, 15, 14)
2994 11:57:24.646100 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 11:57:24.649288 Total UI for P1: 0, mck2ui 16
2996 11:57:24.652958 best dqsien dly found for B1: ( 0, 15, 20)
2997 11:57:24.656457 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2998 11:57:24.659766 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2999 11:57:24.660316
3000 11:57:24.663238 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3001 11:57:24.666562 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3002 11:57:24.669733 [Gating] SW calibration Done
3003 11:57:24.670282 ==
3004 11:57:24.673535 Dram Type= 6, Freq= 0, CH_1, rank 0
3005 11:57:24.676361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3006 11:57:24.676852 ==
3007 11:57:24.679538 RX Vref Scan: 0
3008 11:57:24.679989
3009 11:57:24.680346 RX Vref 0 -> 0, step: 1
3010 11:57:24.683323
3011 11:57:24.683871 RX Delay -40 -> 252, step: 8
3012 11:57:24.690200 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3013 11:57:24.693220 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3014 11:57:24.696543 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3015 11:57:24.700085 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3016 11:57:24.702856 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3017 11:57:24.706481 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3018 11:57:24.712910 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3019 11:57:24.716540 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3020 11:57:24.719856 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
3021 11:57:24.723156 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3022 11:57:24.726548 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3023 11:57:24.733146 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3024 11:57:24.736355 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3025 11:57:24.739435 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3026 11:57:24.742874 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3027 11:57:24.746088 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3028 11:57:24.749575 ==
3029 11:57:24.752770 Dram Type= 6, Freq= 0, CH_1, rank 0
3030 11:57:24.756252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3031 11:57:24.756856 ==
3032 11:57:24.757223 DQS Delay:
3033 11:57:24.759530 DQS0 = 0, DQS1 = 0
3034 11:57:24.759981 DQM Delay:
3035 11:57:24.763263 DQM0 = 115, DQM1 = 108
3036 11:57:24.763831 DQ Delay:
3037 11:57:24.766203 DQ0 =115, DQ1 =111, DQ2 =107, DQ3 =115
3038 11:57:24.769394 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3039 11:57:24.772971 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3040 11:57:24.776448 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3041 11:57:24.777043
3042 11:57:24.777406
3043 11:57:24.777741 ==
3044 11:57:24.779401 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 11:57:24.786230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3046 11:57:24.786781 ==
3047 11:57:24.787149
3048 11:57:24.787481
3049 11:57:24.787802 TX Vref Scan disable
3050 11:57:24.789419 == TX Byte 0 ==
3051 11:57:24.793068 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3052 11:57:24.799745 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3053 11:57:24.800314 == TX Byte 1 ==
3054 11:57:24.803273 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3055 11:57:24.809588 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3056 11:57:24.810139 ==
3057 11:57:24.813227 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 11:57:24.816233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3059 11:57:24.816835 ==
3060 11:57:24.827329 TX Vref=22, minBit 8, minWin=25, winSum=416
3061 11:57:24.830826 TX Vref=24, minBit 11, minWin=25, winSum=424
3062 11:57:24.834035 TX Vref=26, minBit 1, minWin=26, winSum=429
3063 11:57:24.837048 TX Vref=28, minBit 1, minWin=26, winSum=433
3064 11:57:24.840395 TX Vref=30, minBit 8, minWin=26, winSum=434
3065 11:57:24.847468 TX Vref=32, minBit 8, minWin=26, winSum=430
3066 11:57:24.850883 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3067 11:57:24.851480
3068 11:57:24.853687 Final TX Range 1 Vref 30
3069 11:57:24.854140
3070 11:57:24.854498 ==
3071 11:57:24.857499 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 11:57:24.860307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3073 11:57:24.860816 ==
3074 11:57:24.863692
3075 11:57:24.864239
3076 11:57:24.864659 TX Vref Scan disable
3077 11:57:24.867135 == TX Byte 0 ==
3078 11:57:24.870519 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3079 11:57:24.874022 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3080 11:57:24.877078 == TX Byte 1 ==
3081 11:57:24.880825 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3082 11:57:24.883934 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3083 11:57:24.884388
3084 11:57:24.887372 [DATLAT]
3085 11:57:24.887934 Freq=1200, CH1 RK0
3086 11:57:24.888295
3087 11:57:24.890672 DATLAT Default: 0xd
3088 11:57:24.891238 0, 0xFFFF, sum = 0
3089 11:57:24.893952 1, 0xFFFF, sum = 0
3090 11:57:24.894505 2, 0xFFFF, sum = 0
3091 11:57:24.897111 3, 0xFFFF, sum = 0
3092 11:57:24.897568 4, 0xFFFF, sum = 0
3093 11:57:24.900412 5, 0xFFFF, sum = 0
3094 11:57:24.900903 6, 0xFFFF, sum = 0
3095 11:57:24.904175 7, 0xFFFF, sum = 0
3096 11:57:24.904807 8, 0xFFFF, sum = 0
3097 11:57:24.907130 9, 0xFFFF, sum = 0
3098 11:57:24.910644 10, 0xFFFF, sum = 0
3099 11:57:24.911285 11, 0x0, sum = 1
3100 11:57:24.911666 12, 0x0, sum = 2
3101 11:57:24.913719 13, 0x0, sum = 3
3102 11:57:24.914236 14, 0x0, sum = 4
3103 11:57:24.917372 best_step = 12
3104 11:57:24.917941
3105 11:57:24.918307 ==
3106 11:57:24.920967 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 11:57:24.924125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 11:57:24.924729 ==
3109 11:57:24.927302 RX Vref Scan: 1
3110 11:57:24.927853
3111 11:57:24.928220 Set Vref Range= 32 -> 127
3112 11:57:24.930824
3113 11:57:24.931367 RX Vref 32 -> 127, step: 1
3114 11:57:24.931730
3115 11:57:24.934060 RX Delay -29 -> 252, step: 4
3116 11:57:24.934609
3117 11:57:24.937471 Set Vref, RX VrefLevel [Byte0]: 32
3118 11:57:24.940064 [Byte1]: 32
3119 11:57:24.943523
3120 11:57:24.944029 Set Vref, RX VrefLevel [Byte0]: 33
3121 11:57:24.947040 [Byte1]: 33
3122 11:57:24.951563
3123 11:57:24.952127 Set Vref, RX VrefLevel [Byte0]: 34
3124 11:57:24.955078 [Byte1]: 34
3125 11:57:24.959801
3126 11:57:24.960342 Set Vref, RX VrefLevel [Byte0]: 35
3127 11:57:24.962873 [Byte1]: 35
3128 11:57:24.967795
3129 11:57:24.968370 Set Vref, RX VrefLevel [Byte0]: 36
3130 11:57:24.970619 [Byte1]: 36
3131 11:57:24.975416
3132 11:57:24.975866 Set Vref, RX VrefLevel [Byte0]: 37
3133 11:57:24.978987 [Byte1]: 37
3134 11:57:24.983344
3135 11:57:24.983795 Set Vref, RX VrefLevel [Byte0]: 38
3136 11:57:24.986914 [Byte1]: 38
3137 11:57:24.991398
3138 11:57:24.991936 Set Vref, RX VrefLevel [Byte0]: 39
3139 11:57:24.994827 [Byte1]: 39
3140 11:57:24.999770
3141 11:57:25.000320 Set Vref, RX VrefLevel [Byte0]: 40
3142 11:57:25.002642 [Byte1]: 40
3143 11:57:25.007575
3144 11:57:25.008123 Set Vref, RX VrefLevel [Byte0]: 41
3145 11:57:25.010492 [Byte1]: 41
3146 11:57:25.015594
3147 11:57:25.016151 Set Vref, RX VrefLevel [Byte0]: 42
3148 11:57:25.018726 [Byte1]: 42
3149 11:57:25.023262
3150 11:57:25.023803 Set Vref, RX VrefLevel [Byte0]: 43
3151 11:57:25.026591 [Byte1]: 43
3152 11:57:25.031411
3153 11:57:25.031993 Set Vref, RX VrefLevel [Byte0]: 44
3154 11:57:25.034514 [Byte1]: 44
3155 11:57:25.039113
3156 11:57:25.039652 Set Vref, RX VrefLevel [Byte0]: 45
3157 11:57:25.042099 [Byte1]: 45
3158 11:57:25.046955
3159 11:57:25.047507 Set Vref, RX VrefLevel [Byte0]: 46
3160 11:57:25.050192 [Byte1]: 46
3161 11:57:25.055333
3162 11:57:25.055909 Set Vref, RX VrefLevel [Byte0]: 47
3163 11:57:25.058351 [Byte1]: 47
3164 11:57:25.062868
3165 11:57:25.063407 Set Vref, RX VrefLevel [Byte0]: 48
3166 11:57:25.066147 [Byte1]: 48
3167 11:57:25.070913
3168 11:57:25.071380 Set Vref, RX VrefLevel [Byte0]: 49
3169 11:57:25.074717 [Byte1]: 49
3170 11:57:25.079255
3171 11:57:25.079814 Set Vref, RX VrefLevel [Byte0]: 50
3172 11:57:25.082003 [Byte1]: 50
3173 11:57:25.087008
3174 11:57:25.087540 Set Vref, RX VrefLevel [Byte0]: 51
3175 11:57:25.090168 [Byte1]: 51
3176 11:57:25.094756
3177 11:57:25.095212 Set Vref, RX VrefLevel [Byte0]: 52
3178 11:57:25.098256 [Byte1]: 52
3179 11:57:25.102920
3180 11:57:25.103368 Set Vref, RX VrefLevel [Byte0]: 53
3181 11:57:25.106146 [Byte1]: 53
3182 11:57:25.111170
3183 11:57:25.111732 Set Vref, RX VrefLevel [Byte0]: 54
3184 11:57:25.114161 [Byte1]: 54
3185 11:57:25.118738
3186 11:57:25.119260 Set Vref, RX VrefLevel [Byte0]: 55
3187 11:57:25.122074 [Byte1]: 55
3188 11:57:25.126904
3189 11:57:25.127423 Set Vref, RX VrefLevel [Byte0]: 56
3190 11:57:25.129984 [Byte1]: 56
3191 11:57:25.134684
3192 11:57:25.135242 Set Vref, RX VrefLevel [Byte0]: 57
3193 11:57:25.137999 [Byte1]: 57
3194 11:57:25.142345
3195 11:57:25.142802 Set Vref, RX VrefLevel [Byte0]: 58
3196 11:57:25.145855 [Byte1]: 58
3197 11:57:25.150739
3198 11:57:25.151277 Set Vref, RX VrefLevel [Byte0]: 59
3199 11:57:25.153635 [Byte1]: 59
3200 11:57:25.158435
3201 11:57:25.158887 Set Vref, RX VrefLevel [Byte0]: 60
3202 11:57:25.162165 [Byte1]: 60
3203 11:57:25.166576
3204 11:57:25.167028 Set Vref, RX VrefLevel [Byte0]: 61
3205 11:57:25.170012 [Byte1]: 61
3206 11:57:25.174529
3207 11:57:25.175092 Set Vref, RX VrefLevel [Byte0]: 62
3208 11:57:25.178111 [Byte1]: 62
3209 11:57:25.182290
3210 11:57:25.182743 Set Vref, RX VrefLevel [Byte0]: 63
3211 11:57:25.185402 [Byte1]: 63
3212 11:57:25.190249
3213 11:57:25.190769 Set Vref, RX VrefLevel [Byte0]: 64
3214 11:57:25.193315 [Byte1]: 64
3215 11:57:25.198391
3216 11:57:25.198914 Set Vref, RX VrefLevel [Byte0]: 65
3217 11:57:25.201356 [Byte1]: 65
3218 11:57:25.206124
3219 11:57:25.206581 Set Vref, RX VrefLevel [Byte0]: 66
3220 11:57:25.209475 [Byte1]: 66
3221 11:57:25.214575
3222 11:57:25.215135 Set Vref, RX VrefLevel [Byte0]: 67
3223 11:57:25.217286 [Byte1]: 67
3224 11:57:25.222142
3225 11:57:25.222691 Set Vref, RX VrefLevel [Byte0]: 68
3226 11:57:25.225403 [Byte1]: 68
3227 11:57:25.229897
3228 11:57:25.230348 Set Vref, RX VrefLevel [Byte0]: 69
3229 11:57:25.233468 [Byte1]: 69
3230 11:57:25.238100
3231 11:57:25.238648 Set Vref, RX VrefLevel [Byte0]: 70
3232 11:57:25.241244 [Byte1]: 70
3233 11:57:25.246048
3234 11:57:25.246605 Final RX Vref Byte 0 = 56 to rank0
3235 11:57:25.249176 Final RX Vref Byte 1 = 54 to rank0
3236 11:57:25.252664 Final RX Vref Byte 0 = 56 to rank1
3237 11:57:25.256071 Final RX Vref Byte 1 = 54 to rank1==
3238 11:57:25.259120 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:57:25.265831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3240 11:57:25.266407 ==
3241 11:57:25.266777 DQS Delay:
3242 11:57:25.267114 DQS0 = 0, DQS1 = 0
3243 11:57:25.269099 DQM Delay:
3244 11:57:25.269554 DQM0 = 115, DQM1 = 106
3245 11:57:25.272678 DQ Delay:
3246 11:57:25.275819 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3247 11:57:25.279321 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3248 11:57:25.282331 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3249 11:57:25.286230 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =116
3250 11:57:25.286785
3251 11:57:25.287150
3252 11:57:25.292843 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3253 11:57:25.295721 CH1 RK0: MR19=404, MR18=1B1B
3254 11:57:25.302471 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3255 11:57:25.303101
3256 11:57:25.306533 ----->DramcWriteLeveling(PI) begin...
3257 11:57:25.307162 ==
3258 11:57:25.309241 Dram Type= 6, Freq= 0, CH_1, rank 1
3259 11:57:25.312409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3260 11:57:25.312922 ==
3261 11:57:25.316175 Write leveling (Byte 0): 19 => 19
3262 11:57:25.319442 Write leveling (Byte 1): 21 => 21
3263 11:57:25.322752 DramcWriteLeveling(PI) end<-----
3264 11:57:25.323306
3265 11:57:25.323676 ==
3266 11:57:25.326082 Dram Type= 6, Freq= 0, CH_1, rank 1
3267 11:57:25.332976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3268 11:57:25.333536 ==
3269 11:57:25.333909 [Gating] SW mode calibration
3270 11:57:25.342490 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3271 11:57:25.346108 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3272 11:57:25.349488 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3273 11:57:25.356109 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3274 11:57:25.359871 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3275 11:57:25.362571 0 11 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
3276 11:57:25.369205 0 11 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3277 11:57:25.372500 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 11:57:25.375894 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 11:57:25.382817 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 11:57:25.385883 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 11:57:25.388945 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 11:57:25.396085 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3283 11:57:25.398927 0 12 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3284 11:57:25.402164 0 12 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
3285 11:57:25.409056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 11:57:25.412332 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 11:57:25.416039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 11:57:25.422374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 11:57:25.425804 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 11:57:25.429263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 11:57:25.435821 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3292 11:57:25.438959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3293 11:57:25.442383 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3294 11:57:25.448879 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 11:57:25.452278 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 11:57:25.455539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 11:57:25.458848 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 11:57:25.465550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 11:57:25.468558 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 11:57:25.471922 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 11:57:25.478771 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 11:57:25.482211 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 11:57:25.485521 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 11:57:25.491842 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 11:57:25.495525 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 11:57:25.498877 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 11:57:25.505673 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3308 11:57:25.508648 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3309 11:57:25.511985 Total UI for P1: 0, mck2ui 16
3310 11:57:25.515343 best dqsien dly found for B0: ( 0, 15, 12)
3311 11:57:25.518875 Total UI for P1: 0, mck2ui 16
3312 11:57:25.522104 best dqsien dly found for B1: ( 0, 15, 14)
3313 11:57:25.525342 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3314 11:57:25.528556 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3315 11:57:25.529020
3316 11:57:25.532571 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3317 11:57:25.535866 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3318 11:57:25.539080 [Gating] SW calibration Done
3319 11:57:25.539640 ==
3320 11:57:25.542057 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 11:57:25.545223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 11:57:25.548953 ==
3323 11:57:25.549510 RX Vref Scan: 0
3324 11:57:25.549871
3325 11:57:25.552121 RX Vref 0 -> 0, step: 1
3326 11:57:25.552741
3327 11:57:25.555749 RX Delay -40 -> 252, step: 8
3328 11:57:25.558972 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3329 11:57:25.562197 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3330 11:57:25.565856 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3331 11:57:25.568987 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3332 11:57:25.575454 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3333 11:57:25.578719 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3334 11:57:25.581948 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3335 11:57:25.585418 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3336 11:57:25.588819 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3337 11:57:25.592143 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3338 11:57:25.598926 iDelay=208, Bit 10, Center 103 (24 ~ 183) 160
3339 11:57:25.602250 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3340 11:57:25.606099 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3341 11:57:25.608714 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3342 11:57:25.615366 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3343 11:57:25.618629 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3344 11:57:25.619192 ==
3345 11:57:25.621923 Dram Type= 6, Freq= 0, CH_1, rank 1
3346 11:57:25.625402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3347 11:57:25.625966 ==
3348 11:57:25.626349 DQS Delay:
3349 11:57:25.628446 DQS0 = 0, DQS1 = 0
3350 11:57:25.628951 DQM Delay:
3351 11:57:25.632013 DQM0 = 116, DQM1 = 106
3352 11:57:25.632655 DQ Delay:
3353 11:57:25.635275 DQ0 =119, DQ1 =115, DQ2 =99, DQ3 =115
3354 11:57:25.639119 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3355 11:57:25.641609 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3356 11:57:25.645004 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3357 11:57:25.645526
3358 11:57:25.648324
3359 11:57:25.648831 ==
3360 11:57:25.651950 Dram Type= 6, Freq= 0, CH_1, rank 1
3361 11:57:25.655433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3362 11:57:25.655989 ==
3363 11:57:25.656357
3364 11:57:25.656772
3365 11:57:25.658734 TX Vref Scan disable
3366 11:57:25.659287 == TX Byte 0 ==
3367 11:57:25.661866 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3368 11:57:25.669456 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3369 11:57:25.670016 == TX Byte 1 ==
3370 11:57:25.672025 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3371 11:57:25.678516 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3372 11:57:25.679084 ==
3373 11:57:25.681683 Dram Type= 6, Freq= 0, CH_1, rank 1
3374 11:57:25.685067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3375 11:57:25.685724 ==
3376 11:57:25.697247 TX Vref=22, minBit 0, minWin=26, winSum=424
3377 11:57:25.700782 TX Vref=24, minBit 9, minWin=25, winSum=427
3378 11:57:25.703691 TX Vref=26, minBit 2, minWin=26, winSum=429
3379 11:57:25.707420 TX Vref=28, minBit 2, minWin=26, winSum=428
3380 11:57:25.710327 TX Vref=30, minBit 11, minWin=25, winSum=436
3381 11:57:25.717313 TX Vref=32, minBit 9, minWin=26, winSum=434
3382 11:57:25.720783 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3383 11:57:25.721332
3384 11:57:25.723747 Final TX Range 1 Vref 32
3385 11:57:25.724321
3386 11:57:25.724761 ==
3387 11:57:25.727081 Dram Type= 6, Freq= 0, CH_1, rank 1
3388 11:57:25.730361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3389 11:57:25.731108 ==
3390 11:57:25.731790
3391 11:57:25.733796
3392 11:57:25.734411 TX Vref Scan disable
3393 11:57:25.736874 == TX Byte 0 ==
3394 11:57:25.740400 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3395 11:57:25.743870 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3396 11:57:25.747162 == TX Byte 1 ==
3397 11:57:25.750551 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3398 11:57:25.753803 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3399 11:57:25.754374
3400 11:57:25.756737 [DATLAT]
3401 11:57:25.757212 Freq=1200, CH1 RK1
3402 11:57:25.757678
3403 11:57:25.760136 DATLAT Default: 0xc
3404 11:57:25.760475 0, 0xFFFF, sum = 0
3405 11:57:25.763638 1, 0xFFFF, sum = 0
3406 11:57:25.764021 2, 0xFFFF, sum = 0
3407 11:57:25.766785 3, 0xFFFF, sum = 0
3408 11:57:25.767026 4, 0xFFFF, sum = 0
3409 11:57:25.769952 5, 0xFFFF, sum = 0
3410 11:57:25.770146 6, 0xFFFF, sum = 0
3411 11:57:25.773473 7, 0xFFFF, sum = 0
3412 11:57:25.773671 8, 0xFFFF, sum = 0
3413 11:57:25.776740 9, 0xFFFF, sum = 0
3414 11:57:25.780033 10, 0xFFFF, sum = 0
3415 11:57:25.780179 11, 0x0, sum = 1
3416 11:57:25.780315 12, 0x0, sum = 2
3417 11:57:25.783239 13, 0x0, sum = 3
3418 11:57:25.783387 14, 0x0, sum = 4
3419 11:57:25.786800 best_step = 12
3420 11:57:25.786941
3421 11:57:25.787074 ==
3422 11:57:25.790156 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 11:57:25.793566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3424 11:57:25.793687 ==
3425 11:57:25.796894 RX Vref Scan: 0
3426 11:57:25.797016
3427 11:57:25.797109 RX Vref 0 -> 0, step: 1
3428 11:57:25.797195
3429 11:57:25.800416 RX Delay -21 -> 252, step: 4
3430 11:57:25.806811 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3431 11:57:25.810220 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3432 11:57:25.813271 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3433 11:57:25.816684 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3434 11:57:25.820163 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3435 11:57:25.826736 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3436 11:57:25.830091 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3437 11:57:25.833496 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3438 11:57:25.836975 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3439 11:57:25.840159 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3440 11:57:25.846860 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3441 11:57:25.850001 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3442 11:57:25.853496 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3443 11:57:25.856757 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3444 11:57:25.860089 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3445 11:57:25.866616 iDelay=199, Bit 15, Center 112 (43 ~ 182) 140
3446 11:57:25.866771 ==
3447 11:57:25.870141 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 11:57:25.873480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3449 11:57:25.873668 ==
3450 11:57:25.873836 DQS Delay:
3451 11:57:25.876602 DQS0 = 0, DQS1 = 0
3452 11:57:25.876747 DQM Delay:
3453 11:57:25.879774 DQM0 = 115, DQM1 = 105
3454 11:57:25.879922 DQ Delay:
3455 11:57:25.883500 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3456 11:57:25.886866 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3457 11:57:25.890093 DQ8 =88, DQ9 =94, DQ10 =110, DQ11 =98
3458 11:57:25.893704 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =112
3459 11:57:25.893886
3460 11:57:25.894062
3461 11:57:25.903625 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3462 11:57:25.906947 CH1 RK1: MR19=404, MR18=A0A
3463 11:57:25.910150 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3464 11:57:25.913487 [RxdqsGatingPostProcess] freq 1200
3465 11:57:25.924738 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3466 11:57:25.924891 Pre-setting of DQS Precalculation
3467 11:57:25.926858 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3468 11:57:25.936759 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3469 11:57:25.943425 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3470 11:57:25.943628
3471 11:57:25.943770
3472 11:57:25.946869 [Calibration Summary] 2400 Mbps
3473 11:57:25.947082 CH 0, Rank 0
3474 11:57:25.950490 SW Impedance : PASS
3475 11:57:25.950731 DUTY Scan : NO K
3476 11:57:25.953756 ZQ Calibration : PASS
3477 11:57:25.956859 Jitter Meter : NO K
3478 11:57:25.957070 CBT Training : PASS
3479 11:57:25.960607 Write leveling : PASS
3480 11:57:25.960890 RX DQS gating : PASS
3481 11:57:25.964380 RX DQ/DQS(RDDQC) : PASS
3482 11:57:25.967143 TX DQ/DQS : PASS
3483 11:57:25.967403 RX DATLAT : PASS
3484 11:57:25.970850 RX DQ/DQS(Engine): PASS
3485 11:57:25.973917 TX OE : NO K
3486 11:57:25.974391 All Pass.
3487 11:57:25.974789
3488 11:57:25.975145 CH 0, Rank 1
3489 11:57:25.977234 SW Impedance : PASS
3490 11:57:25.980745 DUTY Scan : NO K
3491 11:57:25.981244 ZQ Calibration : PASS
3492 11:57:25.983941 Jitter Meter : NO K
3493 11:57:25.987555 CBT Training : PASS
3494 11:57:25.988180 Write leveling : PASS
3495 11:57:25.990395 RX DQS gating : PASS
3496 11:57:25.993833 RX DQ/DQS(RDDQC) : PASS
3497 11:57:25.994305 TX DQ/DQS : PASS
3498 11:57:25.997222 RX DATLAT : PASS
3499 11:57:26.000444 RX DQ/DQS(Engine): PASS
3500 11:57:26.001077 TX OE : NO K
3501 11:57:26.003992 All Pass.
3502 11:57:26.004448
3503 11:57:26.004859 CH 1, Rank 0
3504 11:57:26.007028 SW Impedance : PASS
3505 11:57:26.007486 DUTY Scan : NO K
3506 11:57:26.010462 ZQ Calibration : PASS
3507 11:57:26.013793 Jitter Meter : NO K
3508 11:57:26.014346 CBT Training : PASS
3509 11:57:26.017195 Write leveling : PASS
3510 11:57:26.017745 RX DQS gating : PASS
3511 11:57:26.020399 RX DQ/DQS(RDDQC) : PASS
3512 11:57:26.024037 TX DQ/DQS : PASS
3513 11:57:26.024633 RX DATLAT : PASS
3514 11:57:26.026991 RX DQ/DQS(Engine): PASS
3515 11:57:26.030854 TX OE : NO K
3516 11:57:26.031407 All Pass.
3517 11:57:26.031776
3518 11:57:26.032131 CH 1, Rank 1
3519 11:57:26.033575 SW Impedance : PASS
3520 11:57:26.037153 DUTY Scan : NO K
3521 11:57:26.037706 ZQ Calibration : PASS
3522 11:57:26.040299 Jitter Meter : NO K
3523 11:57:26.043714 CBT Training : PASS
3524 11:57:26.044228 Write leveling : PASS
3525 11:57:26.047183 RX DQS gating : PASS
3526 11:57:26.050637 RX DQ/DQS(RDDQC) : PASS
3527 11:57:26.051207 TX DQ/DQS : PASS
3528 11:57:26.054024 RX DATLAT : PASS
3529 11:57:26.057014 RX DQ/DQS(Engine): PASS
3530 11:57:26.057660 TX OE : NO K
3531 11:57:26.058147 All Pass.
3532 11:57:26.058601
3533 11:57:26.060365 DramC Write-DBI off
3534 11:57:26.063924 PER_BANK_REFRESH: Hybrid Mode
3535 11:57:26.064486 TX_TRACKING: ON
3536 11:57:26.073837 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3537 11:57:26.076932 [FAST_K] Save calibration result to emmc
3538 11:57:26.080464 dramc_set_vcore_voltage set vcore to 650000
3539 11:57:26.083960 Read voltage for 600, 5
3540 11:57:26.084606 Vio18 = 0
3541 11:57:26.087192 Vcore = 650000
3542 11:57:26.087831 Vdram = 0
3543 11:57:26.088320 Vddq = 0
3544 11:57:26.088844 Vmddr = 0
3545 11:57:26.094133 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3546 11:57:26.097290 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3547 11:57:26.100682 MEM_TYPE=3, freq_sel=19
3548 11:57:26.103767 sv_algorithm_assistance_LP4_1600
3549 11:57:26.107366 ============ PULL DRAM RESETB DOWN ============
3550 11:57:26.110715 ========== PULL DRAM RESETB DOWN end =========
3551 11:57:26.117665 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3552 11:57:26.120652 ===================================
3553 11:57:26.124386 LPDDR4 DRAM CONFIGURATION
3554 11:57:26.127361 ===================================
3555 11:57:26.127925 EX_ROW_EN[0] = 0x0
3556 11:57:26.130517 EX_ROW_EN[1] = 0x0
3557 11:57:26.131085 LP4Y_EN = 0x0
3558 11:57:26.134013 WORK_FSP = 0x0
3559 11:57:26.134491 WL = 0x2
3560 11:57:26.137271 RL = 0x2
3561 11:57:26.137835 BL = 0x2
3562 11:57:26.140213 RPST = 0x0
3563 11:57:26.140731 RD_PRE = 0x0
3564 11:57:26.143524 WR_PRE = 0x1
3565 11:57:26.144021 WR_PST = 0x0
3566 11:57:26.146946 DBI_WR = 0x0
3567 11:57:26.147406 DBI_RD = 0x0
3568 11:57:26.150567 OTF = 0x1
3569 11:57:26.154120 ===================================
3570 11:57:26.156778 ===================================
3571 11:57:26.157239 ANA top config
3572 11:57:26.160340 ===================================
3573 11:57:26.163712 DLL_ASYNC_EN = 0
3574 11:57:26.166992 ALL_SLAVE_EN = 1
3575 11:57:26.169985 NEW_RANK_MODE = 1
3576 11:57:26.173310 DLL_IDLE_MODE = 1
3577 11:57:26.173770 LP45_APHY_COMB_EN = 1
3578 11:57:26.176567 TX_ODT_DIS = 1
3579 11:57:26.180292 NEW_8X_MODE = 1
3580 11:57:26.183280 ===================================
3581 11:57:26.186870 ===================================
3582 11:57:26.190113 data_rate = 1200
3583 11:57:26.193406 CKR = 1
3584 11:57:26.193868 DQ_P2S_RATIO = 8
3585 11:57:26.196701 ===================================
3586 11:57:26.200298 CA_P2S_RATIO = 8
3587 11:57:26.203259 DQ_CA_OPEN = 0
3588 11:57:26.206893 DQ_SEMI_OPEN = 0
3589 11:57:26.209747 CA_SEMI_OPEN = 0
3590 11:57:26.213275 CA_FULL_RATE = 0
3591 11:57:26.213746 DQ_CKDIV4_EN = 1
3592 11:57:26.216555 CA_CKDIV4_EN = 1
3593 11:57:26.219798 CA_PREDIV_EN = 0
3594 11:57:26.223092 PH8_DLY = 0
3595 11:57:26.226567 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3596 11:57:26.229825 DQ_AAMCK_DIV = 4
3597 11:57:26.230392 CA_AAMCK_DIV = 4
3598 11:57:26.233194 CA_ADMCK_DIV = 4
3599 11:57:26.236467 DQ_TRACK_CA_EN = 0
3600 11:57:26.239606 CA_PICK = 600
3601 11:57:26.242730 CA_MCKIO = 600
3602 11:57:26.246235 MCKIO_SEMI = 0
3603 11:57:26.249861 PLL_FREQ = 2288
3604 11:57:26.250427 DQ_UI_PI_RATIO = 32
3605 11:57:26.252632 CA_UI_PI_RATIO = 0
3606 11:57:26.256220 ===================================
3607 11:57:26.259622 ===================================
3608 11:57:26.263070 memory_type:LPDDR4
3609 11:57:26.266593 GP_NUM : 10
3610 11:57:26.267339 SRAM_EN : 1
3611 11:57:26.269912 MD32_EN : 0
3612 11:57:26.273080 ===================================
3613 11:57:26.276135 [ANA_INIT] >>>>>>>>>>>>>>
3614 11:57:26.276734 <<<<<< [CONFIGURE PHASE]: ANA_TX
3615 11:57:26.279473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3616 11:57:26.282815 ===================================
3617 11:57:26.286231 data_rate = 1200,PCW = 0X5800
3618 11:57:26.289891 ===================================
3619 11:57:26.293116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3620 11:57:26.299642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3621 11:57:26.305742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3622 11:57:26.309340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3623 11:57:26.312882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3624 11:57:26.315905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3625 11:57:26.319915 [ANA_INIT] flow start
3626 11:57:26.320555 [ANA_INIT] PLL >>>>>>>>
3627 11:57:26.322622 [ANA_INIT] PLL <<<<<<<<
3628 11:57:26.326090 [ANA_INIT] MIDPI >>>>>>>>
3629 11:57:26.328907 [ANA_INIT] MIDPI <<<<<<<<
3630 11:57:26.329392 [ANA_INIT] DLL >>>>>>>>
3631 11:57:26.332143 [ANA_INIT] flow end
3632 11:57:26.335755 ============ LP4 DIFF to SE enter ============
3633 11:57:26.338847 ============ LP4 DIFF to SE exit ============
3634 11:57:26.342074 [ANA_INIT] <<<<<<<<<<<<<
3635 11:57:26.345546 [Flow] Enable top DCM control >>>>>
3636 11:57:26.348643 [Flow] Enable top DCM control <<<<<
3637 11:57:26.352046 Enable DLL master slave shuffle
3638 11:57:26.358814 ==============================================================
3639 11:57:26.359370 Gating Mode config
3640 11:57:26.365431 ==============================================================
3641 11:57:26.365971 Config description:
3642 11:57:26.375321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3643 11:57:26.382053 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3644 11:57:26.388557 SELPH_MODE 0: By rank 1: By Phase
3645 11:57:26.391928 ==============================================================
3646 11:57:26.395320 GAT_TRACK_EN = 1
3647 11:57:26.398655 RX_GATING_MODE = 2
3648 11:57:26.401957 RX_GATING_TRACK_MODE = 2
3649 11:57:26.405003 SELPH_MODE = 1
3650 11:57:26.408182 PICG_EARLY_EN = 1
3651 11:57:26.411954 VALID_LAT_VALUE = 1
3652 11:57:26.418838 ==============================================================
3653 11:57:26.421892 Enter into Gating configuration >>>>
3654 11:57:26.425186 Exit from Gating configuration <<<<
3655 11:57:26.425737 Enter into DVFS_PRE_config >>>>>
3656 11:57:26.438474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3657 11:57:26.441845 Exit from DVFS_PRE_config <<<<<
3658 11:57:26.444667 Enter into PICG configuration >>>>
3659 11:57:26.448048 Exit from PICG configuration <<<<
3660 11:57:26.448556 [RX_INPUT] configuration >>>>>
3661 11:57:26.451390 [RX_INPUT] configuration <<<<<
3662 11:57:26.458045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3663 11:57:26.464760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3664 11:57:26.468179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3665 11:57:26.474911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3666 11:57:26.481765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3667 11:57:26.488059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3668 11:57:26.491451 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3669 11:57:26.494760 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3670 11:57:26.501282 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3671 11:57:26.504886 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3672 11:57:26.508017 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3673 11:57:26.511356 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3674 11:57:26.514816 ===================================
3675 11:57:26.517942 LPDDR4 DRAM CONFIGURATION
3676 11:57:26.521286 ===================================
3677 11:57:26.524746 EX_ROW_EN[0] = 0x0
3678 11:57:26.525294 EX_ROW_EN[1] = 0x0
3679 11:57:26.528118 LP4Y_EN = 0x0
3680 11:57:26.528720 WORK_FSP = 0x0
3681 11:57:26.531091 WL = 0x2
3682 11:57:26.531546 RL = 0x2
3683 11:57:26.534507 BL = 0x2
3684 11:57:26.535055 RPST = 0x0
3685 11:57:26.537740 RD_PRE = 0x0
3686 11:57:26.538192 WR_PRE = 0x1
3687 11:57:26.540990 WR_PST = 0x0
3688 11:57:26.544386 DBI_WR = 0x0
3689 11:57:26.545107 DBI_RD = 0x0
3690 11:57:26.547512 OTF = 0x1
3691 11:57:26.550954 ===================================
3692 11:57:26.554520 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3693 11:57:26.557506 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3694 11:57:26.560993 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3695 11:57:26.564229 ===================================
3696 11:57:26.567586 LPDDR4 DRAM CONFIGURATION
3697 11:57:26.570660 ===================================
3698 11:57:26.574129 EX_ROW_EN[0] = 0x10
3699 11:57:26.574607 EX_ROW_EN[1] = 0x0
3700 11:57:26.577238 LP4Y_EN = 0x0
3701 11:57:26.577710 WORK_FSP = 0x0
3702 11:57:26.580723 WL = 0x2
3703 11:57:26.581303 RL = 0x2
3704 11:57:26.583910 BL = 0x2
3705 11:57:26.584364 RPST = 0x0
3706 11:57:26.587577 RD_PRE = 0x0
3707 11:57:26.588135 WR_PRE = 0x1
3708 11:57:26.590510 WR_PST = 0x0
3709 11:57:26.594043 DBI_WR = 0x0
3710 11:57:26.594500 DBI_RD = 0x0
3711 11:57:26.597125 OTF = 0x1
3712 11:57:26.600432 ===================================
3713 11:57:26.603709 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3714 11:57:26.609333 nWR fixed to 30
3715 11:57:26.612675 [ModeRegInit_LP4] CH0 RK0
3716 11:57:26.613228 [ModeRegInit_LP4] CH0 RK1
3717 11:57:26.615619 [ModeRegInit_LP4] CH1 RK0
3718 11:57:26.618875 [ModeRegInit_LP4] CH1 RK1
3719 11:57:26.619334 match AC timing 16
3720 11:57:26.625947 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3721 11:57:26.628971 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3722 11:57:26.632405 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3723 11:57:26.638841 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3724 11:57:26.642272 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3725 11:57:26.642748 ==
3726 11:57:26.645183 Dram Type= 6, Freq= 0, CH_0, rank 0
3727 11:57:26.648485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3728 11:57:26.649189 ==
3729 11:57:26.655548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3730 11:57:26.662130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3731 11:57:26.665150 [CA 0] Center 35 (5~66) winsize 62
3732 11:57:26.668924 [CA 1] Center 35 (5~66) winsize 62
3733 11:57:26.671983 [CA 2] Center 34 (4~65) winsize 62
3734 11:57:26.675037 [CA 3] Center 34 (4~65) winsize 62
3735 11:57:26.678469 [CA 4] Center 33 (3~64) winsize 62
3736 11:57:26.681657 [CA 5] Center 33 (3~64) winsize 62
3737 11:57:26.682119
3738 11:57:26.685159 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3739 11:57:26.685659
3740 11:57:26.688432 [CATrainingPosCal] consider 1 rank data
3741 11:57:26.691905 u2DelayCellTimex100 = 270/100 ps
3742 11:57:26.695244 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3743 11:57:26.698535 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3744 11:57:26.701757 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3745 11:57:26.705155 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3746 11:57:26.711399 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3747 11:57:26.715128 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3748 11:57:26.715682
3749 11:57:26.718581 CA PerBit enable=1, Macro0, CA PI delay=33
3750 11:57:26.719133
3751 11:57:26.721284 [CBTSetCACLKResult] CA Dly = 33
3752 11:57:26.721740 CS Dly: 5 (0~36)
3753 11:57:26.722103 ==
3754 11:57:26.724563 Dram Type= 6, Freq= 0, CH_0, rank 1
3755 11:57:26.731613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3756 11:57:26.732171 ==
3757 11:57:26.734826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3758 11:57:26.741427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3759 11:57:26.744627 [CA 0] Center 35 (5~66) winsize 62
3760 11:57:26.747811 [CA 1] Center 35 (5~66) winsize 62
3761 11:57:26.751402 [CA 2] Center 34 (4~65) winsize 62
3762 11:57:26.754802 [CA 3] Center 34 (4~65) winsize 62
3763 11:57:26.757898 [CA 4] Center 33 (3~64) winsize 62
3764 11:57:26.761214 [CA 5] Center 33 (3~64) winsize 62
3765 11:57:26.761765
3766 11:57:26.764611 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3767 11:57:26.765164
3768 11:57:26.767881 [CATrainingPosCal] consider 2 rank data
3769 11:57:26.771589 u2DelayCellTimex100 = 270/100 ps
3770 11:57:26.774988 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3771 11:57:26.777961 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3772 11:57:26.784637 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3773 11:57:26.787560 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3774 11:57:26.791159 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3775 11:57:26.794384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3776 11:57:26.794933
3777 11:57:26.797699 CA PerBit enable=1, Macro0, CA PI delay=33
3778 11:57:26.798247
3779 11:57:26.801172 [CBTSetCACLKResult] CA Dly = 33
3780 11:57:26.801719 CS Dly: 5 (0~36)
3781 11:57:26.802084
3782 11:57:26.804756 ----->DramcWriteLeveling(PI) begin...
3783 11:57:26.807894 ==
3784 11:57:26.810888 Dram Type= 6, Freq= 0, CH_0, rank 0
3785 11:57:26.814343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3786 11:57:26.814904 ==
3787 11:57:26.817755 Write leveling (Byte 0): 31 => 31
3788 11:57:26.820863 Write leveling (Byte 1): 30 => 30
3789 11:57:26.824391 DramcWriteLeveling(PI) end<-----
3790 11:57:26.824971
3791 11:57:26.825336 ==
3792 11:57:26.827524 Dram Type= 6, Freq= 0, CH_0, rank 0
3793 11:57:26.830850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3794 11:57:26.831402 ==
3795 11:57:26.834110 [Gating] SW mode calibration
3796 11:57:26.840563 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3797 11:57:26.847163 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3798 11:57:26.850572 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3799 11:57:26.854227 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3800 11:57:26.860335 0 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3801 11:57:26.863975 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3802 11:57:26.867220 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 11:57:26.873405 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 11:57:26.877123 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 11:57:26.880312 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 11:57:26.886686 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 11:57:26.889988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 11:57:26.893895 0 6 8 | B1->B0 | 3030 3838 | 0 0 | (1 1) (0 0)
3809 11:57:26.897410 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3810 11:57:26.903833 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 11:57:26.906652 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 11:57:26.910279 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 11:57:26.917126 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 11:57:26.920403 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 11:57:26.923524 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 11:57:26.929945 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3817 11:57:26.933240 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 11:57:26.936577 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 11:57:26.943222 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 11:57:26.946327 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 11:57:26.950057 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 11:57:26.956691 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 11:57:26.959852 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 11:57:26.963410 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 11:57:26.969828 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 11:57:26.973126 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 11:57:26.976746 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 11:57:26.983290 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 11:57:26.986397 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 11:57:26.990016 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 11:57:26.996442 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 11:57:26.999747 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3833 11:57:27.003122 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3834 11:57:27.006215 Total UI for P1: 0, mck2ui 16
3835 11:57:27.009527 best dqsien dly found for B0: ( 0, 9, 8)
3836 11:57:27.013129 Total UI for P1: 0, mck2ui 16
3837 11:57:27.016383 best dqsien dly found for B1: ( 0, 9, 8)
3838 11:57:27.019615 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3839 11:57:27.023123 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3840 11:57:27.023693
3841 11:57:27.026512 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3842 11:57:27.033369 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3843 11:57:27.033925 [Gating] SW calibration Done
3844 11:57:27.034291 ==
3845 11:57:27.036359 Dram Type= 6, Freq= 0, CH_0, rank 0
3846 11:57:27.042663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3847 11:57:27.043324 ==
3848 11:57:27.043699 RX Vref Scan: 0
3849 11:57:27.044140
3850 11:57:27.045937 RX Vref 0 -> 0, step: 1
3851 11:57:27.046408
3852 11:57:27.049367 RX Delay -230 -> 252, step: 16
3853 11:57:27.052852 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3854 11:57:27.056599 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3855 11:57:27.063120 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3856 11:57:27.066185 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3857 11:57:27.069250 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3858 11:57:27.072708 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3859 11:57:27.076161 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3860 11:57:27.082747 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3861 11:57:27.085893 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3862 11:57:27.089485 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3863 11:57:27.092997 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3864 11:57:27.099175 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3865 11:57:27.102429 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3866 11:57:27.105823 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3867 11:57:27.109218 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3868 11:57:27.115853 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3869 11:57:27.116430 ==
3870 11:57:27.119132 Dram Type= 6, Freq= 0, CH_0, rank 0
3871 11:57:27.122427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3872 11:57:27.122885 ==
3873 11:57:27.123250 DQS Delay:
3874 11:57:27.125815 DQS0 = 0, DQS1 = 0
3875 11:57:27.126267 DQM Delay:
3876 11:57:27.129261 DQM0 = 38, DQM1 = 33
3877 11:57:27.129716 DQ Delay:
3878 11:57:27.132399 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3879 11:57:27.135749 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3880 11:57:27.139409 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3881 11:57:27.142283 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3882 11:57:27.142737
3883 11:57:27.143148
3884 11:57:27.143554 ==
3885 11:57:27.145584 Dram Type= 6, Freq= 0, CH_0, rank 0
3886 11:57:27.149107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3887 11:57:27.149565 ==
3888 11:57:27.149923
3889 11:57:27.151814
3890 11:57:27.152263 TX Vref Scan disable
3891 11:57:27.155591 == TX Byte 0 ==
3892 11:57:27.158873 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3893 11:57:27.162321 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3894 11:57:27.165178 == TX Byte 1 ==
3895 11:57:27.168965 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3896 11:57:27.172055 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3897 11:57:27.172661 ==
3898 11:57:27.175375 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 11:57:27.181801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3900 11:57:27.182341 ==
3901 11:57:27.182754
3902 11:57:27.183132
3903 11:57:27.183455 TX Vref Scan disable
3904 11:57:27.186228 == TX Byte 0 ==
3905 11:57:27.189975 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3906 11:57:27.196678 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3907 11:57:27.197235 == TX Byte 1 ==
3908 11:57:27.199868 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3909 11:57:27.206374 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3910 11:57:27.206927
3911 11:57:27.207290 [DATLAT]
3912 11:57:27.207623 Freq=600, CH0 RK0
3913 11:57:27.207947
3914 11:57:27.209815 DATLAT Default: 0x9
3915 11:57:27.210364 0, 0xFFFF, sum = 0
3916 11:57:27.212827 1, 0xFFFF, sum = 0
3917 11:57:27.213288 2, 0xFFFF, sum = 0
3918 11:57:27.216143 3, 0xFFFF, sum = 0
3919 11:57:27.219946 4, 0xFFFF, sum = 0
3920 11:57:27.220502 5, 0xFFFF, sum = 0
3921 11:57:27.223135 6, 0xFFFF, sum = 0
3922 11:57:27.223698 7, 0x0, sum = 1
3923 11:57:27.224068 8, 0x0, sum = 2
3924 11:57:27.226199 9, 0x0, sum = 3
3925 11:57:27.226758 10, 0x0, sum = 4
3926 11:57:27.229796 best_step = 8
3927 11:57:27.230346
3928 11:57:27.230712 ==
3929 11:57:27.233059 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 11:57:27.236661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3931 11:57:27.237218 ==
3932 11:57:27.239622 RX Vref Scan: 1
3933 11:57:27.240188
3934 11:57:27.240585 RX Vref 0 -> 0, step: 1
3935 11:57:27.240930
3936 11:57:27.242746 RX Delay -195 -> 252, step: 8
3937 11:57:27.243198
3938 11:57:27.245955 Set Vref, RX VrefLevel [Byte0]: 50
3939 11:57:27.249422 [Byte1]: 48
3940 11:57:27.253217
3941 11:57:27.253764 Final RX Vref Byte 0 = 50 to rank0
3942 11:57:27.256624 Final RX Vref Byte 1 = 48 to rank0
3943 11:57:27.260464 Final RX Vref Byte 0 = 50 to rank1
3944 11:57:27.263685 Final RX Vref Byte 1 = 48 to rank1==
3945 11:57:27.267167 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 11:57:27.273789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3947 11:57:27.274340 ==
3948 11:57:27.274705 DQS Delay:
3949 11:57:27.275043 DQS0 = 0, DQS1 = 0
3950 11:57:27.276702 DQM Delay:
3951 11:57:27.277157 DQM0 = 39, DQM1 = 30
3952 11:57:27.280153 DQ Delay:
3953 11:57:27.283743 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3954 11:57:27.284297 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3955 11:57:27.286748 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3956 11:57:27.289943 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3957 11:57:27.293335
3958 11:57:27.293782
3959 11:57:27.300316 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3960 11:57:27.303447 CH0 RK0: MR19=808, MR18=5E5E
3961 11:57:27.310544 CH0_RK0: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
3962 11:57:27.311106
3963 11:57:27.313486 ----->DramcWriteLeveling(PI) begin...
3964 11:57:27.314008 ==
3965 11:57:27.317146 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 11:57:27.320343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3967 11:57:27.320938 ==
3968 11:57:27.323699 Write leveling (Byte 0): 31 => 31
3969 11:57:27.326594 Write leveling (Byte 1): 30 => 30
3970 11:57:27.330294 DramcWriteLeveling(PI) end<-----
3971 11:57:27.330861
3972 11:57:27.331229 ==
3973 11:57:27.333338 Dram Type= 6, Freq= 0, CH_0, rank 1
3974 11:57:27.337094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3975 11:57:27.337645 ==
3976 11:57:27.340003 [Gating] SW mode calibration
3977 11:57:27.346494 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 11:57:27.353113 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3979 11:57:27.356489 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 11:57:27.360043 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 11:57:27.366453 0 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (0 0)
3982 11:57:27.369720 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3983 11:57:27.373141 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:57:27.379840 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 11:57:27.383184 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:57:27.386583 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 11:57:27.393067 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 11:57:27.396232 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:57:27.399948 0 6 8 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
3990 11:57:27.406319 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3991 11:57:27.409868 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:57:27.413087 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:57:27.419574 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:57:27.422955 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:57:27.426207 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:57:27.433000 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:57:27.436062 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3998 11:57:27.439777 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:57:27.445779 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:57:27.449101 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:57:27.452895 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:57:27.459506 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:57:27.462732 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:57:27.465990 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:57:27.472664 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:57:27.476041 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:57:27.479215 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:57:27.485803 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:57:27.489022 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:57:27.492248 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:57:27.499264 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:57:27.502205 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:57:27.505567 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:57:27.511963 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:57:27.512490 Total UI for P1: 0, mck2ui 16
4016 11:57:27.518709 best dqsien dly found for B0: ( 0, 9, 10)
4017 11:57:27.519238 Total UI for P1: 0, mck2ui 16
4018 11:57:27.521902 best dqsien dly found for B1: ( 0, 9, 10)
4019 11:57:27.528369 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4020 11:57:27.531805 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4021 11:57:27.532347
4022 11:57:27.535093 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4023 11:57:27.538453 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4024 11:57:27.541716 [Gating] SW calibration Done
4025 11:57:27.542268 ==
4026 11:57:27.544987 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 11:57:27.548323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4028 11:57:27.548825 ==
4029 11:57:27.551972 RX Vref Scan: 0
4030 11:57:27.552557
4031 11:57:27.552938 RX Vref 0 -> 0, step: 1
4032 11:57:27.553277
4033 11:57:27.554874 RX Delay -230 -> 252, step: 16
4034 11:57:27.561899 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4035 11:57:27.564961 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4036 11:57:27.568558 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4037 11:57:27.571736 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4038 11:57:27.574728 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4039 11:57:27.581464 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4040 11:57:27.584830 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4041 11:57:27.588444 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4042 11:57:27.591391 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4043 11:57:27.598238 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4044 11:57:27.601141 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4045 11:57:27.604995 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4046 11:57:27.608172 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4047 11:57:27.614865 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4048 11:57:27.618065 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4049 11:57:27.621052 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4050 11:57:27.621515 ==
4051 11:57:27.624590 Dram Type= 6, Freq= 0, CH_0, rank 1
4052 11:57:27.628096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4053 11:57:27.628689 ==
4054 11:57:27.630888 DQS Delay:
4055 11:57:27.631344 DQS0 = 0, DQS1 = 0
4056 11:57:27.634268 DQM Delay:
4057 11:57:27.634748 DQM0 = 40, DQM1 = 32
4058 11:57:27.635120 DQ Delay:
4059 11:57:27.637944 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4060 11:57:27.641182 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4061 11:57:27.644404 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4062 11:57:27.648109 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4063 11:57:27.648608
4064 11:57:27.648979
4065 11:57:27.651643 ==
4066 11:57:27.654742 Dram Type= 6, Freq= 0, CH_0, rank 1
4067 11:57:27.658118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4068 11:57:27.658686 ==
4069 11:57:27.659171
4070 11:57:27.659618
4071 11:57:27.661164 TX Vref Scan disable
4072 11:57:27.661630 == TX Byte 0 ==
4073 11:57:27.667784 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4074 11:57:27.670900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4075 11:57:27.671371 == TX Byte 1 ==
4076 11:57:27.677675 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4077 11:57:27.680973 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4078 11:57:27.681443 ==
4079 11:57:27.684188 Dram Type= 6, Freq= 0, CH_0, rank 1
4080 11:57:27.687593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4081 11:57:27.688067 ==
4082 11:57:27.688741
4083 11:57:27.689442
4084 11:57:27.690744 TX Vref Scan disable
4085 11:57:27.694046 == TX Byte 0 ==
4086 11:57:27.697585 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4087 11:57:27.700456 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4088 11:57:27.704036 == TX Byte 1 ==
4089 11:57:27.707338 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4090 11:57:27.710482 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4091 11:57:27.710942
4092 11:57:27.714057 [DATLAT]
4093 11:57:27.714514 Freq=600, CH0 RK1
4094 11:57:27.714876
4095 11:57:27.717163 DATLAT Default: 0x8
4096 11:57:27.717649 0, 0xFFFF, sum = 0
4097 11:57:27.720739 1, 0xFFFF, sum = 0
4098 11:57:27.721213 2, 0xFFFF, sum = 0
4099 11:57:27.723892 3, 0xFFFF, sum = 0
4100 11:57:27.724365 4, 0xFFFF, sum = 0
4101 11:57:27.727078 5, 0xFFFF, sum = 0
4102 11:57:27.727551 6, 0xFFFF, sum = 0
4103 11:57:27.730664 7, 0x0, sum = 1
4104 11:57:27.731133 8, 0x0, sum = 2
4105 11:57:27.733754 9, 0x0, sum = 3
4106 11:57:27.734227 10, 0x0, sum = 4
4107 11:57:27.737159 best_step = 8
4108 11:57:27.737624
4109 11:57:27.738100 ==
4110 11:57:27.740652 Dram Type= 6, Freq= 0, CH_0, rank 1
4111 11:57:27.743861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4112 11:57:27.744405 ==
4113 11:57:27.747182 RX Vref Scan: 0
4114 11:57:27.747632
4115 11:57:27.748100 RX Vref 0 -> 0, step: 1
4116 11:57:27.748448
4117 11:57:27.750302 RX Delay -179 -> 252, step: 8
4118 11:57:27.757068 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4119 11:57:27.760604 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4120 11:57:27.764133 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4121 11:57:27.767540 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4122 11:57:27.773968 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4123 11:57:27.777153 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4124 11:57:27.780271 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4125 11:57:27.783976 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4126 11:57:27.787304 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4127 11:57:27.793754 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4128 11:57:27.797006 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4129 11:57:27.800330 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4130 11:57:27.803829 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4131 11:57:27.810349 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4132 11:57:27.813724 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4133 11:57:27.816935 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4134 11:57:27.817483 ==
4135 11:57:27.820200 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 11:57:27.826657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4137 11:57:27.827206 ==
4138 11:57:27.827591 DQS Delay:
4139 11:57:27.827933 DQS0 = 0, DQS1 = 0
4140 11:57:27.830187 DQM Delay:
4141 11:57:27.830640 DQM0 = 42, DQM1 = 33
4142 11:57:27.833274 DQ Delay:
4143 11:57:27.836560 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4144 11:57:27.839899 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =52
4145 11:57:27.843217 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4146 11:57:27.846400 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4147 11:57:27.846861
4148 11:57:27.847326
4149 11:57:27.853162 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4150 11:57:27.856262 CH0 RK1: MR19=808, MR18=6363
4151 11:57:27.863483 CH0_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4152 11:57:27.866207 [RxdqsGatingPostProcess] freq 600
4153 11:57:27.869415 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4154 11:57:27.872933 Pre-setting of DQS Precalculation
4155 11:57:27.879676 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4156 11:57:27.880236 ==
4157 11:57:27.882823 Dram Type= 6, Freq= 0, CH_1, rank 0
4158 11:57:27.886612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4159 11:57:27.887170 ==
4160 11:57:27.892811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4161 11:57:27.899366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4162 11:57:27.903035 [CA 0] Center 35 (5~66) winsize 62
4163 11:57:27.906508 [CA 1] Center 35 (5~66) winsize 62
4164 11:57:27.909220 [CA 2] Center 33 (3~64) winsize 62
4165 11:57:27.912758 [CA 3] Center 33 (3~64) winsize 62
4166 11:57:27.915993 [CA 4] Center 33 (2~64) winsize 63
4167 11:57:27.919306 [CA 5] Center 33 (2~64) winsize 63
4168 11:57:27.919857
4169 11:57:27.922844 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4170 11:57:27.923410
4171 11:57:27.925661 [CATrainingPosCal] consider 1 rank data
4172 11:57:27.929264 u2DelayCellTimex100 = 270/100 ps
4173 11:57:27.932599 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4174 11:57:27.936002 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4175 11:57:27.938889 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4176 11:57:27.942464 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4177 11:57:27.945666 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4178 11:57:27.949009 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4179 11:57:27.949465
4180 11:57:27.952592 CA PerBit enable=1, Macro0, CA PI delay=33
4181 11:57:27.955612
4182 11:57:27.956196 [CBTSetCACLKResult] CA Dly = 33
4183 11:57:27.959065 CS Dly: 4 (0~35)
4184 11:57:27.959612 ==
4185 11:57:27.962199 Dram Type= 6, Freq= 0, CH_1, rank 1
4186 11:57:27.965748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4187 11:57:27.966304 ==
4188 11:57:27.972380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4189 11:57:27.978795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4190 11:57:27.982200 [CA 0] Center 35 (5~66) winsize 62
4191 11:57:27.985261 [CA 1] Center 34 (4~65) winsize 62
4192 11:57:27.988777 [CA 2] Center 33 (3~64) winsize 62
4193 11:57:27.992156 [CA 3] Center 33 (3~64) winsize 62
4194 11:57:27.995277 [CA 4] Center 32 (2~63) winsize 62
4195 11:57:27.998983 [CA 5] Center 32 (2~63) winsize 62
4196 11:57:27.999546
4197 11:57:28.002259 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4198 11:57:28.002826
4199 11:57:28.005332 [CATrainingPosCal] consider 2 rank data
4200 11:57:28.008721 u2DelayCellTimex100 = 270/100 ps
4201 11:57:28.011857 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4202 11:57:28.015305 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4203 11:57:28.018637 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4204 11:57:28.021790 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4205 11:57:28.025417 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4206 11:57:28.031884 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4207 11:57:28.032459
4208 11:57:28.035289 CA PerBit enable=1, Macro0, CA PI delay=32
4209 11:57:28.035749
4210 11:57:28.038698 [CBTSetCACLKResult] CA Dly = 32
4211 11:57:28.039259 CS Dly: 4 (0~36)
4212 11:57:28.039628
4213 11:57:28.042065 ----->DramcWriteLeveling(PI) begin...
4214 11:57:28.042545 ==
4215 11:57:28.045125 Dram Type= 6, Freq= 0, CH_1, rank 0
4216 11:57:28.048127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4217 11:57:28.051785 ==
4218 11:57:28.052303 Write leveling (Byte 0): 29 => 29
4219 11:57:28.055381 Write leveling (Byte 1): 28 => 28
4220 11:57:28.058231 DramcWriteLeveling(PI) end<-----
4221 11:57:28.058696
4222 11:57:28.059060 ==
4223 11:57:28.061750 Dram Type= 6, Freq= 0, CH_1, rank 0
4224 11:57:28.068700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4225 11:57:28.069262 ==
4226 11:57:28.069637 [Gating] SW mode calibration
4227 11:57:28.078232 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 11:57:28.081726 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4229 11:57:28.088240 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 11:57:28.091525 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4231 11:57:28.095066 0 5 8 | B1->B0 | 2f2f 2a2a | 0 0 | (1 1) (1 1)
4232 11:57:28.101421 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 11:57:28.105045 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 11:57:28.107909 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:57:28.111345 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 11:57:28.118121 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 11:57:28.121459 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:57:28.124654 0 6 4 | B1->B0 | 2424 2e2e | 1 0 | (0 0) (0 0)
4239 11:57:28.131145 0 6 8 | B1->B0 | 3534 4040 | 1 0 | (0 0) (0 0)
4240 11:57:28.134199 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 11:57:28.137885 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 11:57:28.144488 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:57:28.147698 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:57:28.151351 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 11:57:28.157383 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:57:28.160940 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:57:28.164376 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:57:28.171050 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:57:28.174574 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:57:28.177808 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:57:28.184639 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:57:28.188176 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:57:28.191371 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:57:28.197764 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:57:28.201180 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:57:28.204318 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:57:28.210776 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:57:28.214027 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:57:28.217444 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:57:28.223985 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:57:28.227764 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:57:28.230795 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:57:28.237397 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4264 11:57:28.237950 Total UI for P1: 0, mck2ui 16
4265 11:57:28.243861 best dqsien dly found for B0: ( 0, 9, 6)
4266 11:57:28.247069 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 11:57:28.250680 Total UI for P1: 0, mck2ui 16
4268 11:57:28.253809 best dqsien dly found for B1: ( 0, 9, 8)
4269 11:57:28.256997 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4270 11:57:28.260274 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4271 11:57:28.260788
4272 11:57:28.263762 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4273 11:57:28.267217 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4274 11:57:28.270494 [Gating] SW calibration Done
4275 11:57:28.271022 ==
4276 11:57:28.273654 Dram Type= 6, Freq= 0, CH_1, rank 0
4277 11:57:28.276741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4278 11:57:28.277205 ==
4279 11:57:28.280356 RX Vref Scan: 0
4280 11:57:28.280858
4281 11:57:28.283722 RX Vref 0 -> 0, step: 1
4282 11:57:28.284260
4283 11:57:28.284695 RX Delay -230 -> 252, step: 16
4284 11:57:28.290151 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4285 11:57:28.293696 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4286 11:57:28.296764 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4287 11:57:28.300291 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4288 11:57:28.306826 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4289 11:57:28.310019 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4290 11:57:28.313485 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4291 11:57:28.317083 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4292 11:57:28.320003 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4293 11:57:28.326747 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4294 11:57:28.329907 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4295 11:57:28.333328 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4296 11:57:28.336925 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4297 11:57:28.343046 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4298 11:57:28.346767 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4299 11:57:28.349651 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4300 11:57:28.349890 ==
4301 11:57:28.353028 Dram Type= 6, Freq= 0, CH_1, rank 0
4302 11:57:28.359556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4303 11:57:28.359854 ==
4304 11:57:28.360043 DQS Delay:
4305 11:57:28.360220 DQS0 = 0, DQS1 = 0
4306 11:57:28.363026 DQM Delay:
4307 11:57:28.363356 DQM0 = 39, DQM1 = 32
4308 11:57:28.366157 DQ Delay:
4309 11:57:28.369863 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4310 11:57:28.370100 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4311 11:57:28.372740 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4312 11:57:28.379611 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4313 11:57:28.379914
4314 11:57:28.380104
4315 11:57:28.380279 ==
4316 11:57:28.383064 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 11:57:28.385956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4318 11:57:28.386213 ==
4319 11:57:28.386402
4320 11:57:28.386576
4321 11:57:28.389397 TX Vref Scan disable
4322 11:57:28.389634 == TX Byte 0 ==
4323 11:57:28.396424 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 11:57:28.400114 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 11:57:28.400640 == TX Byte 1 ==
4326 11:57:28.406335 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4327 11:57:28.409949 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4328 11:57:28.410406 ==
4329 11:57:28.413164 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 11:57:28.416526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 11:57:28.417097 ==
4332 11:57:28.417463
4333 11:57:28.417802
4334 11:57:28.419771 TX Vref Scan disable
4335 11:57:28.423145 == TX Byte 0 ==
4336 11:57:28.426156 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4337 11:57:28.432952 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4338 11:57:28.433512 == TX Byte 1 ==
4339 11:57:28.436163 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4340 11:57:28.442911 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4341 11:57:28.443471
4342 11:57:28.443835 [DATLAT]
4343 11:57:28.444171 Freq=600, CH1 RK0
4344 11:57:28.444496
4345 11:57:28.446048 DATLAT Default: 0x9
4346 11:57:28.446503 0, 0xFFFF, sum = 0
4347 11:57:28.449493 1, 0xFFFF, sum = 0
4348 11:57:28.452806 2, 0xFFFF, sum = 0
4349 11:57:28.453352 3, 0xFFFF, sum = 0
4350 11:57:28.456016 4, 0xFFFF, sum = 0
4351 11:57:28.456469 5, 0xFFFF, sum = 0
4352 11:57:28.459608 6, 0xFFFF, sum = 0
4353 11:57:28.460096 7, 0x0, sum = 1
4354 11:57:28.460710 8, 0x0, sum = 2
4355 11:57:28.462694 9, 0x0, sum = 3
4356 11:57:28.463277 10, 0x0, sum = 4
4357 11:57:28.465859 best_step = 8
4358 11:57:28.466306
4359 11:57:28.466666 ==
4360 11:57:28.468998 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 11:57:28.472893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 11:57:28.473441 ==
4363 11:57:28.476078 RX Vref Scan: 1
4364 11:57:28.476667
4365 11:57:28.477039 RX Vref 0 -> 0, step: 1
4366 11:57:28.477378
4367 11:57:28.479172 RX Delay -195 -> 252, step: 8
4368 11:57:28.479623
4369 11:57:28.482742 Set Vref, RX VrefLevel [Byte0]: 56
4370 11:57:28.485771 [Byte1]: 54
4371 11:57:28.489776
4372 11:57:28.490320 Final RX Vref Byte 0 = 56 to rank0
4373 11:57:28.493031 Final RX Vref Byte 1 = 54 to rank0
4374 11:57:28.496543 Final RX Vref Byte 0 = 56 to rank1
4375 11:57:28.500472 Final RX Vref Byte 1 = 54 to rank1==
4376 11:57:28.503347 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 11:57:28.510018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4378 11:57:28.510576 ==
4379 11:57:28.510941 DQS Delay:
4380 11:57:28.511275 DQS0 = 0, DQS1 = 0
4381 11:57:28.513300 DQM Delay:
4382 11:57:28.513756 DQM0 = 38, DQM1 = 29
4383 11:57:28.516596 DQ Delay:
4384 11:57:28.520235 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4385 11:57:28.523178 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4386 11:57:28.526764 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =20
4387 11:57:28.529530 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =36
4388 11:57:28.529989
4389 11:57:28.530351
4390 11:57:28.536155 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c7c, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4391 11:57:28.539608 CH1 RK0: MR19=808, MR18=7C7C
4392 11:57:28.545850 CH1_RK0: MR19=0x808, MR18=0x7C7C, DQSOSC=386, MR23=63, INC=176, DEC=117
4393 11:57:28.546511
4394 11:57:28.549234 ----->DramcWriteLeveling(PI) begin...
4395 11:57:28.549714 ==
4396 11:57:28.552992 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 11:57:28.556364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 11:57:28.556984 ==
4399 11:57:28.559529 Write leveling (Byte 0): 28 => 28
4400 11:57:28.562683 Write leveling (Byte 1): 28 => 28
4401 11:57:28.566002 DramcWriteLeveling(PI) end<-----
4402 11:57:28.566462
4403 11:57:28.566825 ==
4404 11:57:28.569220 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 11:57:28.572836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 11:57:28.573413 ==
4407 11:57:28.575933 [Gating] SW mode calibration
4408 11:57:28.582693 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 11:57:28.589564 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4410 11:57:28.592569 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 11:57:28.599525 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
4412 11:57:28.602589 0 5 8 | B1->B0 | 3030 2424 | 1 0 | (0 0) (0 0)
4413 11:57:28.605609 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 11:57:28.612746 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:57:28.615837 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:57:28.619178 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:57:28.625828 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:57:28.628825 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:57:28.632210 0 6 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
4420 11:57:28.638879 0 6 8 | B1->B0 | 3736 4646 | 1 0 | (0 0) (0 0)
4421 11:57:28.642210 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:57:28.645323 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:57:28.652236 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:57:28.655092 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:57:28.658890 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:57:28.665125 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:57:28.668754 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:57:28.671847 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4429 11:57:28.678596 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:57:28.681865 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:57:28.685215 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:57:28.691953 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:57:28.695322 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:57:28.698353 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:57:28.704993 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:57:28.707979 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:57:28.711814 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:57:28.715092 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:57:28.721767 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:57:28.724995 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:57:28.728030 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:57:28.734627 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:57:28.738416 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:57:28.741430 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4445 11:57:28.744462 Total UI for P1: 0, mck2ui 16
4446 11:57:28.747839 best dqsien dly found for B0: ( 0, 9, 6)
4447 11:57:28.754804 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 11:57:28.755378 Total UI for P1: 0, mck2ui 16
4449 11:57:28.761218 best dqsien dly found for B1: ( 0, 9, 8)
4450 11:57:28.764432 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4451 11:57:28.767868 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4452 11:57:28.768339
4453 11:57:28.771533 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4454 11:57:28.774768 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4455 11:57:28.777976 [Gating] SW calibration Done
4456 11:57:28.778554 ==
4457 11:57:28.781183 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 11:57:28.785056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4459 11:57:28.785639 ==
4460 11:57:28.787710 RX Vref Scan: 0
4461 11:57:28.788186
4462 11:57:28.788772 RX Vref 0 -> 0, step: 1
4463 11:57:28.789240
4464 11:57:28.790985 RX Delay -230 -> 252, step: 16
4465 11:57:28.798100 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4466 11:57:28.801169 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4467 11:57:28.804319 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4468 11:57:28.807624 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 11:57:28.810887 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 11:57:28.817673 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4471 11:57:28.821225 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4472 11:57:28.823831 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4473 11:57:28.827393 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4474 11:57:28.834310 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4475 11:57:28.837425 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4476 11:57:28.840598 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4477 11:57:28.844133 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4478 11:57:28.850636 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4479 11:57:28.853836 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4480 11:57:28.857044 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 11:57:28.857499 ==
4482 11:57:28.860646 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 11:57:28.863765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4484 11:57:28.867083 ==
4485 11:57:28.867630 DQS Delay:
4486 11:57:28.867990 DQS0 = 0, DQS1 = 0
4487 11:57:28.870578 DQM Delay:
4488 11:57:28.871149 DQM0 = 40, DQM1 = 32
4489 11:57:28.873457 DQ Delay:
4490 11:57:28.873906 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4491 11:57:28.877169 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4492 11:57:28.880395 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4493 11:57:28.884418 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4494 11:57:28.885019
4495 11:57:28.886961
4496 11:57:28.887513 ==
4497 11:57:28.890021 Dram Type= 6, Freq= 0, CH_1, rank 1
4498 11:57:28.893459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4499 11:57:28.893918 ==
4500 11:57:28.894277
4501 11:57:28.894609
4502 11:57:28.896714 TX Vref Scan disable
4503 11:57:28.897166 == TX Byte 0 ==
4504 11:57:28.903877 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4505 11:57:28.907021 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4506 11:57:28.907567 == TX Byte 1 ==
4507 11:57:28.913459 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4508 11:57:28.917069 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4509 11:57:28.917619 ==
4510 11:57:28.920219 Dram Type= 6, Freq= 0, CH_1, rank 1
4511 11:57:28.923567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4512 11:57:28.924115 ==
4513 11:57:28.924476
4514 11:57:28.924847
4515 11:57:28.926757 TX Vref Scan disable
4516 11:57:28.930270 == TX Byte 0 ==
4517 11:57:28.933320 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4518 11:57:28.936560 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4519 11:57:28.939760 == TX Byte 1 ==
4520 11:57:28.943284 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 11:57:28.946496 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 11:57:28.947072
4523 11:57:28.949801 [DATLAT]
4524 11:57:28.950256 Freq=600, CH1 RK1
4525 11:57:28.950623
4526 11:57:28.953083 DATLAT Default: 0x8
4527 11:57:28.953593 0, 0xFFFF, sum = 0
4528 11:57:28.956677 1, 0xFFFF, sum = 0
4529 11:57:28.957243 2, 0xFFFF, sum = 0
4530 11:57:28.960072 3, 0xFFFF, sum = 0
4531 11:57:28.960683 4, 0xFFFF, sum = 0
4532 11:57:28.963318 5, 0xFFFF, sum = 0
4533 11:57:28.963799 6, 0xFFFF, sum = 0
4534 11:57:28.966429 7, 0x0, sum = 1
4535 11:57:28.967007 8, 0x0, sum = 2
4536 11:57:28.969663 9, 0x0, sum = 3
4537 11:57:28.970146 10, 0x0, sum = 4
4538 11:57:28.973055 best_step = 8
4539 11:57:28.973529
4540 11:57:28.974011 ==
4541 11:57:28.976555 Dram Type= 6, Freq= 0, CH_1, rank 1
4542 11:57:28.979625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4543 11:57:28.980106 ==
4544 11:57:28.983183 RX Vref Scan: 0
4545 11:57:28.983748
4546 11:57:28.984238 RX Vref 0 -> 0, step: 1
4547 11:57:28.984797
4548 11:57:28.986126 RX Delay -195 -> 252, step: 8
4549 11:57:28.993105 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4550 11:57:28.996419 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4551 11:57:28.999894 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4552 11:57:29.003106 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4553 11:57:29.009725 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4554 11:57:29.013355 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4555 11:57:29.016632 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4556 11:57:29.020239 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4557 11:57:29.023509 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4558 11:57:29.030067 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4559 11:57:29.033322 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4560 11:57:29.036796 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4561 11:57:29.040036 iDelay=205, Bit 12, Center 40 (-123 ~ 204) 328
4562 11:57:29.046129 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4563 11:57:29.049320 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4564 11:57:29.053317 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4565 11:57:29.053847 ==
4566 11:57:29.056575 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 11:57:29.063137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 11:57:29.063659 ==
4569 11:57:29.064108 DQS Delay:
4570 11:57:29.064642 DQS0 = 0, DQS1 = 0
4571 11:57:29.066072 DQM Delay:
4572 11:57:29.066500 DQM0 = 37, DQM1 = 29
4573 11:57:29.069362 DQ Delay:
4574 11:57:29.072499 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4575 11:57:29.076324 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4576 11:57:29.079305 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4577 11:57:29.082548 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4578 11:57:29.082983
4579 11:57:29.083420
4580 11:57:29.089127 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4581 11:57:29.092311 CH1 RK1: MR19=808, MR18=5454
4582 11:57:29.099332 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4583 11:57:29.102690 [RxdqsGatingPostProcess] freq 600
4584 11:57:29.105913 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4585 11:57:29.109248 Pre-setting of DQS Precalculation
4586 11:57:29.115939 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4587 11:57:29.122315 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4588 11:57:29.129255 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4589 11:57:29.129788
4590 11:57:29.130233
4591 11:57:29.132345 [Calibration Summary] 1200 Mbps
4592 11:57:29.132933 CH 0, Rank 0
4593 11:57:29.135603 SW Impedance : PASS
4594 11:57:29.139135 DUTY Scan : NO K
4595 11:57:29.139611 ZQ Calibration : PASS
4596 11:57:29.142538 Jitter Meter : NO K
4597 11:57:29.145632 CBT Training : PASS
4598 11:57:29.146204 Write leveling : PASS
4599 11:57:29.149146 RX DQS gating : PASS
4600 11:57:29.152078 RX DQ/DQS(RDDQC) : PASS
4601 11:57:29.152586 TX DQ/DQS : PASS
4602 11:57:29.155747 RX DATLAT : PASS
4603 11:57:29.156315 RX DQ/DQS(Engine): PASS
4604 11:57:29.159243 TX OE : NO K
4605 11:57:29.159815 All Pass.
4606 11:57:29.160306
4607 11:57:29.161949 CH 0, Rank 1
4608 11:57:29.162380 SW Impedance : PASS
4609 11:57:29.165268 DUTY Scan : NO K
4610 11:57:29.168935 ZQ Calibration : PASS
4611 11:57:29.169396 Jitter Meter : NO K
4612 11:57:29.172440 CBT Training : PASS
4613 11:57:29.175479 Write leveling : PASS
4614 11:57:29.176030 RX DQS gating : PASS
4615 11:57:29.179191 RX DQ/DQS(RDDQC) : PASS
4616 11:57:29.182165 TX DQ/DQS : PASS
4617 11:57:29.182729 RX DATLAT : PASS
4618 11:57:29.185853 RX DQ/DQS(Engine): PASS
4619 11:57:29.188847 TX OE : NO K
4620 11:57:29.189427 All Pass.
4621 11:57:29.189799
4622 11:57:29.190137 CH 1, Rank 0
4623 11:57:29.191955 SW Impedance : PASS
4624 11:57:29.195463 DUTY Scan : NO K
4625 11:57:29.196017 ZQ Calibration : PASS
4626 11:57:29.198714 Jitter Meter : NO K
4627 11:57:29.201871 CBT Training : PASS
4628 11:57:29.202428 Write leveling : PASS
4629 11:57:29.205485 RX DQS gating : PASS
4630 11:57:29.208446 RX DQ/DQS(RDDQC) : PASS
4631 11:57:29.208963 TX DQ/DQS : PASS
4632 11:57:29.212047 RX DATLAT : PASS
4633 11:57:29.215359 RX DQ/DQS(Engine): PASS
4634 11:57:29.215941 TX OE : NO K
4635 11:57:29.216438 All Pass.
4636 11:57:29.218570
4637 11:57:29.219141 CH 1, Rank 1
4638 11:57:29.222004 SW Impedance : PASS
4639 11:57:29.222573 DUTY Scan : NO K
4640 11:57:29.225291 ZQ Calibration : PASS
4641 11:57:29.225860 Jitter Meter : NO K
4642 11:57:29.228655 CBT Training : PASS
4643 11:57:29.231824 Write leveling : PASS
4644 11:57:29.232392 RX DQS gating : PASS
4645 11:57:29.235162 RX DQ/DQS(RDDQC) : PASS
4646 11:57:29.238436 TX DQ/DQS : PASS
4647 11:57:29.239008 RX DATLAT : PASS
4648 11:57:29.241744 RX DQ/DQS(Engine): PASS
4649 11:57:29.244854 TX OE : NO K
4650 11:57:29.245333 All Pass.
4651 11:57:29.245821
4652 11:57:29.248243 DramC Write-DBI off
4653 11:57:29.248806 PER_BANK_REFRESH: Hybrid Mode
4654 11:57:29.251396 TX_TRACKING: ON
4655 11:57:29.261443 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4656 11:57:29.264363 [FAST_K] Save calibration result to emmc
4657 11:57:29.268173 dramc_set_vcore_voltage set vcore to 662500
4658 11:57:29.268803 Read voltage for 933, 3
4659 11:57:29.271184 Vio18 = 0
4660 11:57:29.271653 Vcore = 662500
4661 11:57:29.272134 Vdram = 0
4662 11:57:29.274571 Vddq = 0
4663 11:57:29.275042 Vmddr = 0
4664 11:57:29.277996 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4665 11:57:29.284681 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4666 11:57:29.288009 MEM_TYPE=3, freq_sel=17
4667 11:57:29.291096 sv_algorithm_assistance_LP4_1600
4668 11:57:29.294389 ============ PULL DRAM RESETB DOWN ============
4669 11:57:29.297958 ========== PULL DRAM RESETB DOWN end =========
4670 11:57:29.304851 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4671 11:57:29.308113 ===================================
4672 11:57:29.308723 LPDDR4 DRAM CONFIGURATION
4673 11:57:29.311393 ===================================
4674 11:57:29.314339 EX_ROW_EN[0] = 0x0
4675 11:57:29.314916 EX_ROW_EN[1] = 0x0
4676 11:57:29.317760 LP4Y_EN = 0x0
4677 11:57:29.321137 WORK_FSP = 0x0
4678 11:57:29.321718 WL = 0x3
4679 11:57:29.324116 RL = 0x3
4680 11:57:29.324674 BL = 0x2
4681 11:57:29.327953 RPST = 0x0
4682 11:57:29.328604 RD_PRE = 0x0
4683 11:57:29.331383 WR_PRE = 0x1
4684 11:57:29.331948 WR_PST = 0x0
4685 11:57:29.334130 DBI_WR = 0x0
4686 11:57:29.334703 DBI_RD = 0x0
4687 11:57:29.337877 OTF = 0x1
4688 11:57:29.341028 ===================================
4689 11:57:29.344289 ===================================
4690 11:57:29.344918 ANA top config
4691 11:57:29.347362 ===================================
4692 11:57:29.350794 DLL_ASYNC_EN = 0
4693 11:57:29.354168 ALL_SLAVE_EN = 1
4694 11:57:29.354724 NEW_RANK_MODE = 1
4695 11:57:29.357399 DLL_IDLE_MODE = 1
4696 11:57:29.360616 LP45_APHY_COMB_EN = 1
4697 11:57:29.363896 TX_ODT_DIS = 1
4698 11:57:29.367416 NEW_8X_MODE = 1
4699 11:57:29.370572 ===================================
4700 11:57:29.373829 ===================================
4701 11:57:29.377254 data_rate = 1866
4702 11:57:29.377806 CKR = 1
4703 11:57:29.380468 DQ_P2S_RATIO = 8
4704 11:57:29.384047 ===================================
4705 11:57:29.387240 CA_P2S_RATIO = 8
4706 11:57:29.390764 DQ_CA_OPEN = 0
4707 11:57:29.393522 DQ_SEMI_OPEN = 0
4708 11:57:29.393983 CA_SEMI_OPEN = 0
4709 11:57:29.397008 CA_FULL_RATE = 0
4710 11:57:29.400258 DQ_CKDIV4_EN = 1
4711 11:57:29.403688 CA_CKDIV4_EN = 1
4712 11:57:29.407285 CA_PREDIV_EN = 0
4713 11:57:29.410116 PH8_DLY = 0
4714 11:57:29.413867 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4715 11:57:29.414418 DQ_AAMCK_DIV = 4
4716 11:57:29.416718 CA_AAMCK_DIV = 4
4717 11:57:29.420241 CA_ADMCK_DIV = 4
4718 11:57:29.423482 DQ_TRACK_CA_EN = 0
4719 11:57:29.426813 CA_PICK = 933
4720 11:57:29.430355 CA_MCKIO = 933
4721 11:57:29.430910 MCKIO_SEMI = 0
4722 11:57:29.433259 PLL_FREQ = 3732
4723 11:57:29.436673 DQ_UI_PI_RATIO = 32
4724 11:57:29.440163 CA_UI_PI_RATIO = 0
4725 11:57:29.443240 ===================================
4726 11:57:29.446861 ===================================
4727 11:57:29.449681 memory_type:LPDDR4
4728 11:57:29.450142 GP_NUM : 10
4729 11:57:29.453351 SRAM_EN : 1
4730 11:57:29.456779 MD32_EN : 0
4731 11:57:29.459848 ===================================
4732 11:57:29.460431 [ANA_INIT] >>>>>>>>>>>>>>
4733 11:57:29.463022 <<<<<< [CONFIGURE PHASE]: ANA_TX
4734 11:57:29.466594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4735 11:57:29.470180 ===================================
4736 11:57:29.472987 data_rate = 1866,PCW = 0X8f00
4737 11:57:29.476544 ===================================
4738 11:57:29.480012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4739 11:57:29.486410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4740 11:57:29.489222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4741 11:57:29.496148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4742 11:57:29.499763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4743 11:57:29.503168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4744 11:57:29.506163 [ANA_INIT] flow start
4745 11:57:29.506718 [ANA_INIT] PLL >>>>>>>>
4746 11:57:29.509258 [ANA_INIT] PLL <<<<<<<<
4747 11:57:29.512532 [ANA_INIT] MIDPI >>>>>>>>
4748 11:57:29.512995 [ANA_INIT] MIDPI <<<<<<<<
4749 11:57:29.516402 [ANA_INIT] DLL >>>>>>>>
4750 11:57:29.519417 [ANA_INIT] flow end
4751 11:57:29.522871 ============ LP4 DIFF to SE enter ============
4752 11:57:29.526438 ============ LP4 DIFF to SE exit ============
4753 11:57:29.529039 [ANA_INIT] <<<<<<<<<<<<<
4754 11:57:29.532428 [Flow] Enable top DCM control >>>>>
4755 11:57:29.535925 [Flow] Enable top DCM control <<<<<
4756 11:57:29.538969 Enable DLL master slave shuffle
4757 11:57:29.542568 ==============================================================
4758 11:57:29.546010 Gating Mode config
4759 11:57:29.552333 ==============================================================
4760 11:57:29.552829 Config description:
4761 11:57:29.562563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4762 11:57:29.569182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4763 11:57:29.572360 SELPH_MODE 0: By rank 1: By Phase
4764 11:57:29.579286 ==============================================================
4765 11:57:29.582371 GAT_TRACK_EN = 1
4766 11:57:29.585595 RX_GATING_MODE = 2
4767 11:57:29.588727 RX_GATING_TRACK_MODE = 2
4768 11:57:29.592348 SELPH_MODE = 1
4769 11:57:29.595516 PICG_EARLY_EN = 1
4770 11:57:29.598909 VALID_LAT_VALUE = 1
4771 11:57:29.602235 ==============================================================
4772 11:57:29.605530 Enter into Gating configuration >>>>
4773 11:57:29.608876 Exit from Gating configuration <<<<
4774 11:57:29.611904 Enter into DVFS_PRE_config >>>>>
4775 11:57:29.625151 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4776 11:57:29.625719 Exit from DVFS_PRE_config <<<<<
4777 11:57:29.628593 Enter into PICG configuration >>>>
4778 11:57:29.631975 Exit from PICG configuration <<<<
4779 11:57:29.635241 [RX_INPUT] configuration >>>>>
4780 11:57:29.638543 [RX_INPUT] configuration <<<<<
4781 11:57:29.645370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4782 11:57:29.648746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4783 11:57:29.655171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4784 11:57:29.662084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4785 11:57:29.668400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4786 11:57:29.675313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4787 11:57:29.678500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4788 11:57:29.681799 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4789 11:57:29.685268 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4790 11:57:29.691944 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4791 11:57:29.695032 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4792 11:57:29.698266 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4793 11:57:29.701548 ===================================
4794 11:57:29.705141 LPDDR4 DRAM CONFIGURATION
4795 11:57:29.708421 ===================================
4796 11:57:29.711701 EX_ROW_EN[0] = 0x0
4797 11:57:29.712262 EX_ROW_EN[1] = 0x0
4798 11:57:29.715066 LP4Y_EN = 0x0
4799 11:57:29.715629 WORK_FSP = 0x0
4800 11:57:29.718514 WL = 0x3
4801 11:57:29.719068 RL = 0x3
4802 11:57:29.721349 BL = 0x2
4803 11:57:29.721811 RPST = 0x0
4804 11:57:29.725002 RD_PRE = 0x0
4805 11:57:29.725564 WR_PRE = 0x1
4806 11:57:29.728456 WR_PST = 0x0
4807 11:57:29.728951 DBI_WR = 0x0
4808 11:57:29.731606 DBI_RD = 0x0
4809 11:57:29.732165 OTF = 0x1
4810 11:57:29.734553 ===================================
4811 11:57:29.737992 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4812 11:57:29.744726 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4813 11:57:29.748117 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4814 11:57:29.751093 ===================================
4815 11:57:29.754862 LPDDR4 DRAM CONFIGURATION
4816 11:57:29.757842 ===================================
4817 11:57:29.758409 EX_ROW_EN[0] = 0x10
4818 11:57:29.760989 EX_ROW_EN[1] = 0x0
4819 11:57:29.764651 LP4Y_EN = 0x0
4820 11:57:29.765204 WORK_FSP = 0x0
4821 11:57:29.767801 WL = 0x3
4822 11:57:29.768259 RL = 0x3
4823 11:57:29.771166 BL = 0x2
4824 11:57:29.771622 RPST = 0x0
4825 11:57:29.774333 RD_PRE = 0x0
4826 11:57:29.774947 WR_PRE = 0x1
4827 11:57:29.777444 WR_PST = 0x0
4828 11:57:29.777900 DBI_WR = 0x0
4829 11:57:29.780993 DBI_RD = 0x0
4830 11:57:29.781449 OTF = 0x1
4831 11:57:29.784182 ===================================
4832 11:57:29.790777 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4833 11:57:29.795400 nWR fixed to 30
4834 11:57:29.798730 [ModeRegInit_LP4] CH0 RK0
4835 11:57:29.799291 [ModeRegInit_LP4] CH0 RK1
4836 11:57:29.802314 [ModeRegInit_LP4] CH1 RK0
4837 11:57:29.805702 [ModeRegInit_LP4] CH1 RK1
4838 11:57:29.806269 match AC timing 8
4839 11:57:29.812045 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4840 11:57:29.815394 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4841 11:57:29.818956 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4842 11:57:29.825335 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4843 11:57:29.828477 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4844 11:57:29.829079 ==
4845 11:57:29.831650 Dram Type= 6, Freq= 0, CH_0, rank 0
4846 11:57:29.835287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4847 11:57:29.835857 ==
4848 11:57:29.841633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4849 11:57:29.848056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4850 11:57:29.851648 [CA 0] Center 38 (8~69) winsize 62
4851 11:57:29.855217 [CA 1] Center 38 (8~69) winsize 62
4852 11:57:29.858221 [CA 2] Center 36 (5~67) winsize 63
4853 11:57:29.861699 [CA 3] Center 36 (5~67) winsize 63
4854 11:57:29.864796 [CA 4] Center 34 (4~65) winsize 62
4855 11:57:29.867952 [CA 5] Center 34 (4~64) winsize 61
4856 11:57:29.868410
4857 11:57:29.871348 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4858 11:57:29.871808
4859 11:57:29.874899 [CATrainingPosCal] consider 1 rank data
4860 11:57:29.877943 u2DelayCellTimex100 = 270/100 ps
4861 11:57:29.881412 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 11:57:29.884626 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4863 11:57:29.888015 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4864 11:57:29.891504 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4865 11:57:29.894837 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4866 11:57:29.901138 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4867 11:57:29.901604
4868 11:57:29.904430 CA PerBit enable=1, Macro0, CA PI delay=34
4869 11:57:29.905020
4870 11:57:29.908044 [CBTSetCACLKResult] CA Dly = 34
4871 11:57:29.908646 CS Dly: 7 (0~38)
4872 11:57:29.909023 ==
4873 11:57:29.911296 Dram Type= 6, Freq= 0, CH_0, rank 1
4874 11:57:29.914506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4875 11:57:29.918022 ==
4876 11:57:29.921588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4877 11:57:29.927851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4878 11:57:29.931142 [CA 0] Center 38 (8~69) winsize 62
4879 11:57:29.934650 [CA 1] Center 38 (7~69) winsize 63
4880 11:57:29.937739 [CA 2] Center 36 (6~67) winsize 62
4881 11:57:29.940951 [CA 3] Center 35 (5~66) winsize 62
4882 11:57:29.944084 [CA 4] Center 34 (4~65) winsize 62
4883 11:57:29.947768 [CA 5] Center 34 (4~65) winsize 62
4884 11:57:29.948342
4885 11:57:29.950836 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4886 11:57:29.951363
4887 11:57:29.954149 [CATrainingPosCal] consider 2 rank data
4888 11:57:29.957482 u2DelayCellTimex100 = 270/100 ps
4889 11:57:29.960773 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 11:57:29.964209 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4891 11:57:29.967808 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4892 11:57:29.973958 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4893 11:57:29.977300 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4894 11:57:29.980460 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4895 11:57:29.980947
4896 11:57:29.983844 CA PerBit enable=1, Macro0, CA PI delay=34
4897 11:57:29.984300
4898 11:57:29.987426 [CBTSetCACLKResult] CA Dly = 34
4899 11:57:29.987974 CS Dly: 7 (0~39)
4900 11:57:29.988438
4901 11:57:29.990750 ----->DramcWriteLeveling(PI) begin...
4902 11:57:29.994071 ==
4903 11:57:29.994627 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 11:57:30.000597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 11:57:30.001171 ==
4906 11:57:30.003756 Write leveling (Byte 0): 27 => 27
4907 11:57:30.007434 Write leveling (Byte 1): 27 => 27
4908 11:57:30.010928 DramcWriteLeveling(PI) end<-----
4909 11:57:30.011511
4910 11:57:30.011913 ==
4911 11:57:30.014160 Dram Type= 6, Freq= 0, CH_0, rank 0
4912 11:57:30.017285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4913 11:57:30.017837 ==
4914 11:57:30.020853 [Gating] SW mode calibration
4915 11:57:30.027241 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4916 11:57:30.031115 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4917 11:57:30.037121 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 11:57:30.040483 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 11:57:30.043671 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 11:57:30.050286 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 11:57:30.053232 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 11:57:30.056813 0 10 20 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4923 11:57:30.063817 0 10 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (1 0)
4924 11:57:30.066766 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 11:57:30.070590 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 11:57:30.076840 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 11:57:30.080116 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 11:57:30.083568 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 11:57:30.090184 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 11:57:30.093261 0 11 20 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
4931 11:57:30.096838 0 11 24 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
4932 11:57:30.103478 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 11:57:30.106549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 11:57:30.110132 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 11:57:30.116989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 11:57:30.120185 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 11:57:30.123418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4938 11:57:30.129972 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4939 11:57:30.133282 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4940 11:57:30.136720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 11:57:30.143258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 11:57:30.146783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 11:57:30.149448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 11:57:30.156196 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 11:57:30.159783 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 11:57:30.163011 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 11:57:30.169548 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 11:57:30.172953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 11:57:30.176109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 11:57:30.182786 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 11:57:30.186361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 11:57:30.189893 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 11:57:30.196592 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4954 11:57:30.199776 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4955 11:57:30.202864 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4956 11:57:30.206229 Total UI for P1: 0, mck2ui 16
4957 11:57:30.209571 best dqsien dly found for B0: ( 0, 14, 18)
4958 11:57:30.212599 Total UI for P1: 0, mck2ui 16
4959 11:57:30.215996 best dqsien dly found for B1: ( 0, 14, 18)
4960 11:57:30.219372 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4961 11:57:30.222693 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
4962 11:57:30.223247
4963 11:57:30.225841 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4964 11:57:30.232934 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
4965 11:57:30.233488 [Gating] SW calibration Done
4966 11:57:30.233853 ==
4967 11:57:30.236040 Dram Type= 6, Freq= 0, CH_0, rank 0
4968 11:57:30.242633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4969 11:57:30.243187 ==
4970 11:57:30.243549 RX Vref Scan: 0
4971 11:57:30.243882
4972 11:57:30.245938 RX Vref 0 -> 0, step: 1
4973 11:57:30.246495
4974 11:57:30.249043 RX Delay -80 -> 252, step: 8
4975 11:57:30.252548 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4976 11:57:30.256082 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4977 11:57:30.259292 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4978 11:57:30.265538 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4979 11:57:30.268864 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4980 11:57:30.272116 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4981 11:57:30.275755 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4982 11:57:30.279032 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4983 11:57:30.282258 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4984 11:57:30.288852 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4985 11:57:30.292316 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4986 11:57:30.295536 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4987 11:57:30.298986 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
4988 11:57:30.301855 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4989 11:57:30.308692 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4990 11:57:30.312230 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4991 11:57:30.312843 ==
4992 11:57:30.315074 Dram Type= 6, Freq= 0, CH_0, rank 0
4993 11:57:30.318356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4994 11:57:30.318908 ==
4995 11:57:30.321926 DQS Delay:
4996 11:57:30.322473 DQS0 = 0, DQS1 = 0
4997 11:57:30.322836 DQM Delay:
4998 11:57:30.325430 DQM0 = 95, DQM1 = 83
4999 11:57:30.326000 DQ Delay:
5000 11:57:30.328385 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5001 11:57:30.332030 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5002 11:57:30.334972 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5003 11:57:30.337976 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5004 11:57:30.338429
5005 11:57:30.338785
5006 11:57:30.339115 ==
5007 11:57:30.341811 Dram Type= 6, Freq= 0, CH_0, rank 0
5008 11:57:30.351493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5009 11:57:30.352204 ==
5010 11:57:30.352772
5011 11:57:30.353260
5012 11:57:30.353764 TX Vref Scan disable
5013 11:57:30.354313 == TX Byte 0 ==
5014 11:57:30.355348 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5015 11:57:30.362311 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5016 11:57:30.362865 == TX Byte 1 ==
5017 11:57:30.365471 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5018 11:57:30.371847 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5019 11:57:30.372386 ==
5020 11:57:30.375612 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 11:57:30.378607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5022 11:57:30.379154 ==
5023 11:57:30.379515
5024 11:57:30.379848
5025 11:57:30.381849 TX Vref Scan disable
5026 11:57:30.382389 == TX Byte 0 ==
5027 11:57:30.388679 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5028 11:57:30.391945 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5029 11:57:30.392562 == TX Byte 1 ==
5030 11:57:30.398341 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5031 11:57:30.401786 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5032 11:57:30.402239
5033 11:57:30.402593 [DATLAT]
5034 11:57:30.404980 Freq=933, CH0 RK0
5035 11:57:30.405429
5036 11:57:30.405784 DATLAT Default: 0xd
5037 11:57:30.408486 0, 0xFFFF, sum = 0
5038 11:57:30.408986 1, 0xFFFF, sum = 0
5039 11:57:30.411579 2, 0xFFFF, sum = 0
5040 11:57:30.412109 3, 0xFFFF, sum = 0
5041 11:57:30.414970 4, 0xFFFF, sum = 0
5042 11:57:30.418306 5, 0xFFFF, sum = 0
5043 11:57:30.418932 6, 0xFFFF, sum = 0
5044 11:57:30.421519 7, 0xFFFF, sum = 0
5045 11:57:30.421977 8, 0xFFFF, sum = 0
5046 11:57:30.425018 9, 0xFFFF, sum = 0
5047 11:57:30.425575 10, 0x0, sum = 1
5048 11:57:30.428192 11, 0x0, sum = 2
5049 11:57:30.428674 12, 0x0, sum = 3
5050 11:57:30.429040 13, 0x0, sum = 4
5051 11:57:30.431361 best_step = 11
5052 11:57:30.431810
5053 11:57:30.432170 ==
5054 11:57:30.435026 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 11:57:30.438396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5056 11:57:30.438947 ==
5057 11:57:30.441607 RX Vref Scan: 1
5058 11:57:30.442155
5059 11:57:30.444903 RX Vref 0 -> 0, step: 1
5060 11:57:30.445451
5061 11:57:30.445810 RX Delay -69 -> 252, step: 4
5062 11:57:30.446141
5063 11:57:30.448174 Set Vref, RX VrefLevel [Byte0]: 50
5064 11:57:30.451163 [Byte1]: 48
5065 11:57:30.456107
5066 11:57:30.456707 Final RX Vref Byte 0 = 50 to rank0
5067 11:57:30.459235 Final RX Vref Byte 1 = 48 to rank0
5068 11:57:30.462613 Final RX Vref Byte 0 = 50 to rank1
5069 11:57:30.466074 Final RX Vref Byte 1 = 48 to rank1==
5070 11:57:30.469172 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 11:57:30.476141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 11:57:30.476752 ==
5073 11:57:30.477123 DQS Delay:
5074 11:57:30.477458 DQS0 = 0, DQS1 = 0
5075 11:57:30.479321 DQM Delay:
5076 11:57:30.479879 DQM0 = 96, DQM1 = 86
5077 11:57:30.482836 DQ Delay:
5078 11:57:30.486016 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5079 11:57:30.489015 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =104
5080 11:57:30.492731 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =78
5081 11:57:30.495755 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =96
5082 11:57:30.496208
5083 11:57:30.496614
5084 11:57:30.502464 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5085 11:57:30.505757 CH0 RK0: MR19=505, MR18=2424
5086 11:57:30.512293 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5087 11:57:30.512931
5088 11:57:30.515669 ----->DramcWriteLeveling(PI) begin...
5089 11:57:30.516222 ==
5090 11:57:30.519253 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 11:57:30.522546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5092 11:57:30.523118 ==
5093 11:57:30.525735 Write leveling (Byte 0): 27 => 27
5094 11:57:30.528904 Write leveling (Byte 1): 28 => 28
5095 11:57:30.532724 DramcWriteLeveling(PI) end<-----
5096 11:57:30.533278
5097 11:57:30.533643 ==
5098 11:57:30.535344 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 11:57:30.539110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5100 11:57:30.539676 ==
5101 11:57:30.542273 [Gating] SW mode calibration
5102 11:57:30.548821 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 11:57:30.555140 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5104 11:57:30.558706 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:57:30.565083 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:57:30.568830 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:57:30.572083 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 11:57:30.578586 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5109 11:57:30.582281 0 10 20 | B1->B0 | 3131 2f2f | 0 1 | (0 1) (1 0)
5110 11:57:30.585089 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:57:30.591880 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:57:30.595288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:57:30.598749 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:57:30.605419 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:57:30.608371 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 11:57:30.612124 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5117 11:57:30.618504 0 11 20 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
5118 11:57:30.621834 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5119 11:57:30.625435 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:57:30.628215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:57:30.634825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:57:30.638216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:57:30.641510 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 11:57:30.648263 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:57:30.651165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5126 11:57:30.654542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:57:30.661102 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:57:30.664400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:57:30.668226 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:57:30.674305 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:57:30.677557 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:57:30.681197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:57:30.688048 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:57:30.691022 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:57:30.694246 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:57:30.701053 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:57:30.704248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:57:30.707355 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:57:30.714242 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:57:30.717643 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:57:30.720851 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 11:57:30.727761 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5143 11:57:30.731001 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 11:57:30.734084 Total UI for P1: 0, mck2ui 16
5145 11:57:30.737619 best dqsien dly found for B0: ( 0, 14, 22)
5146 11:57:30.740848 Total UI for P1: 0, mck2ui 16
5147 11:57:30.744116 best dqsien dly found for B1: ( 0, 14, 22)
5148 11:57:30.747374 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5149 11:57:30.751019 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5150 11:57:30.751473
5151 11:57:30.753935 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5152 11:57:30.757414 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5153 11:57:30.760838 [Gating] SW calibration Done
5154 11:57:30.761379 ==
5155 11:57:30.764044 Dram Type= 6, Freq= 0, CH_0, rank 1
5156 11:57:30.770590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5157 11:57:30.771111 ==
5158 11:57:30.771479 RX Vref Scan: 0
5159 11:57:30.771884
5160 11:57:30.774185 RX Vref 0 -> 0, step: 1
5161 11:57:30.774733
5162 11:57:30.777280 RX Delay -80 -> 252, step: 8
5163 11:57:30.780922 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5164 11:57:30.783611 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5165 11:57:30.787362 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5166 11:57:30.790375 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5167 11:57:30.793598 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5168 11:57:30.800586 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5169 11:57:30.803901 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5170 11:57:30.807356 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5171 11:57:30.810683 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5172 11:57:30.813867 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5173 11:57:30.820283 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5174 11:57:30.823847 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5175 11:57:30.826929 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5176 11:57:30.830280 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5177 11:57:30.833600 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5178 11:57:30.836683 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5179 11:57:30.839904 ==
5180 11:57:30.843986 Dram Type= 6, Freq= 0, CH_0, rank 1
5181 11:57:30.847019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5182 11:57:30.847574 ==
5183 11:57:30.847939 DQS Delay:
5184 11:57:30.849693 DQS0 = 0, DQS1 = 0
5185 11:57:30.850144 DQM Delay:
5186 11:57:30.853262 DQM0 = 97, DQM1 = 88
5187 11:57:30.853715 DQ Delay:
5188 11:57:30.856670 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5189 11:57:30.859897 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5190 11:57:30.863702 DQ8 =75, DQ9 =71, DQ10 =91, DQ11 =79
5191 11:57:30.866614 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5192 11:57:30.867172
5193 11:57:30.867529
5194 11:57:30.867859 ==
5195 11:57:30.869640 Dram Type= 6, Freq= 0, CH_0, rank 1
5196 11:57:30.873148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5197 11:57:30.873611 ==
5198 11:57:30.873974
5199 11:57:30.874311
5200 11:57:30.876219 TX Vref Scan disable
5201 11:57:30.879536 == TX Byte 0 ==
5202 11:57:30.882705 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5203 11:57:30.886431 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5204 11:57:30.889471 == TX Byte 1 ==
5205 11:57:30.892822 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5206 11:57:30.896645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5207 11:57:30.897193 ==
5208 11:57:30.899708 Dram Type= 6, Freq= 0, CH_0, rank 1
5209 11:57:30.906161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5210 11:57:30.906713 ==
5211 11:57:30.907079
5212 11:57:30.907413
5213 11:57:30.907734 TX Vref Scan disable
5214 11:57:30.910271 == TX Byte 0 ==
5215 11:57:30.913366 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5216 11:57:30.920095 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5217 11:57:30.920689 == TX Byte 1 ==
5218 11:57:30.923816 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5219 11:57:30.929863 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5220 11:57:30.930415
5221 11:57:30.930781 [DATLAT]
5222 11:57:30.931116 Freq=933, CH0 RK1
5223 11:57:30.931441
5224 11:57:30.933232 DATLAT Default: 0xb
5225 11:57:30.933685 0, 0xFFFF, sum = 0
5226 11:57:30.936424 1, 0xFFFF, sum = 0
5227 11:57:30.940072 2, 0xFFFF, sum = 0
5228 11:57:30.940678 3, 0xFFFF, sum = 0
5229 11:57:30.943121 4, 0xFFFF, sum = 0
5230 11:57:30.943595 5, 0xFFFF, sum = 0
5231 11:57:30.946839 6, 0xFFFF, sum = 0
5232 11:57:30.947399 7, 0xFFFF, sum = 0
5233 11:57:30.949804 8, 0xFFFF, sum = 0
5234 11:57:30.950260 9, 0xFFFF, sum = 0
5235 11:57:30.952992 10, 0x0, sum = 1
5236 11:57:30.953452 11, 0x0, sum = 2
5237 11:57:30.956558 12, 0x0, sum = 3
5238 11:57:30.957020 13, 0x0, sum = 4
5239 11:57:30.957386 best_step = 11
5240 11:57:30.959994
5241 11:57:30.960601 ==
5242 11:57:30.963140 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 11:57:30.966206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 11:57:30.966659 ==
5245 11:57:30.967018 RX Vref Scan: 0
5246 11:57:30.967350
5247 11:57:30.969863 RX Vref 0 -> 0, step: 1
5248 11:57:30.970467
5249 11:57:30.972804 RX Delay -69 -> 252, step: 4
5250 11:57:30.979920 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5251 11:57:30.983299 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5252 11:57:30.986376 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5253 11:57:30.989542 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5254 11:57:30.992771 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5255 11:57:30.995968 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5256 11:57:31.003460 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5257 11:57:31.006035 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5258 11:57:31.009523 iDelay=203, Bit 8, Center 78 (-9 ~ 166) 176
5259 11:57:31.012578 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5260 11:57:31.016170 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5261 11:57:31.022687 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5262 11:57:31.026246 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5263 11:57:31.029504 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5264 11:57:31.032675 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5265 11:57:31.035891 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5266 11:57:31.036367 ==
5267 11:57:31.039572 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 11:57:31.046198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5269 11:57:31.046761 ==
5270 11:57:31.047129 DQS Delay:
5271 11:57:31.047464 DQS0 = 0, DQS1 = 0
5272 11:57:31.049452 DQM Delay:
5273 11:57:31.049903 DQM0 = 97, DQM1 = 86
5274 11:57:31.052385 DQ Delay:
5275 11:57:31.055728 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5276 11:57:31.059566 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5277 11:57:31.062654 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5278 11:57:31.065688 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5279 11:57:31.066304
5280 11:57:31.066673
5281 11:57:31.072321 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5282 11:57:31.075529 CH0 RK1: MR19=505, MR18=2929
5283 11:57:31.082490 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5284 11:57:31.085609 [RxdqsGatingPostProcess] freq 933
5285 11:57:31.089007 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5286 11:57:31.092406 Pre-setting of DQS Precalculation
5287 11:57:31.098961 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5288 11:57:31.099420 ==
5289 11:57:31.102165 Dram Type= 6, Freq= 0, CH_1, rank 0
5290 11:57:31.105400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 11:57:31.105858 ==
5292 11:57:31.111921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5293 11:57:31.118524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5294 11:57:31.121792 [CA 0] Center 37 (6~68) winsize 63
5295 11:57:31.125179 [CA 1] Center 37 (6~68) winsize 63
5296 11:57:31.128755 [CA 2] Center 34 (4~65) winsize 62
5297 11:57:31.132120 [CA 3] Center 34 (4~65) winsize 62
5298 11:57:31.135587 [CA 4] Center 33 (2~64) winsize 63
5299 11:57:31.138983 [CA 5] Center 33 (3~64) winsize 62
5300 11:57:31.139525
5301 11:57:31.142080 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5302 11:57:31.142779
5303 11:57:31.145126 [CATrainingPosCal] consider 1 rank data
5304 11:57:31.148689 u2DelayCellTimex100 = 270/100 ps
5305 11:57:31.151819 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5306 11:57:31.155112 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5307 11:57:31.158932 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5308 11:57:31.161898 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5309 11:57:31.165054 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5310 11:57:31.168755 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5311 11:57:31.169303
5312 11:57:31.171633 CA PerBit enable=1, Macro0, CA PI delay=33
5313 11:57:31.172155
5314 11:57:31.175103 [CBTSetCACLKResult] CA Dly = 33
5315 11:57:31.178467 CS Dly: 5 (0~36)
5316 11:57:31.178915 ==
5317 11:57:31.182009 Dram Type= 6, Freq= 0, CH_1, rank 1
5318 11:57:31.185113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5319 11:57:31.185601 ==
5320 11:57:31.191855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5321 11:57:31.198323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5322 11:57:31.201816 [CA 0] Center 37 (6~68) winsize 63
5323 11:57:31.205145 [CA 1] Center 37 (6~68) winsize 63
5324 11:57:31.208563 [CA 2] Center 34 (4~65) winsize 62
5325 11:57:31.211858 [CA 3] Center 34 (4~65) winsize 62
5326 11:57:31.214797 [CA 4] Center 32 (2~63) winsize 62
5327 11:57:31.218095 [CA 5] Center 32 (2~63) winsize 62
5328 11:57:31.218647
5329 11:57:31.221598 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5330 11:57:31.222146
5331 11:57:31.225087 [CATrainingPosCal] consider 2 rank data
5332 11:57:31.228217 u2DelayCellTimex100 = 270/100 ps
5333 11:57:31.231444 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5334 11:57:31.235322 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5335 11:57:31.238159 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5336 11:57:31.241093 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5337 11:57:31.244736 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5338 11:57:31.248082 CA5 delay=33 (3~63),Diff = 1 PI (6 cell)
5339 11:57:31.251215
5340 11:57:31.254489 CA PerBit enable=1, Macro0, CA PI delay=32
5341 11:57:31.255022
5342 11:57:31.257918 [CBTSetCACLKResult] CA Dly = 32
5343 11:57:31.258465 CS Dly: 5 (0~37)
5344 11:57:31.258821
5345 11:57:31.261411 ----->DramcWriteLeveling(PI) begin...
5346 11:57:31.261994 ==
5347 11:57:31.264576 Dram Type= 6, Freq= 0, CH_1, rank 0
5348 11:57:31.268086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5349 11:57:31.271635 ==
5350 11:57:31.272175 Write leveling (Byte 0): 23 => 23
5351 11:57:31.274570 Write leveling (Byte 1): 23 => 23
5352 11:57:31.278312 DramcWriteLeveling(PI) end<-----
5353 11:57:31.278867
5354 11:57:31.279239 ==
5355 11:57:31.281268 Dram Type= 6, Freq= 0, CH_1, rank 0
5356 11:57:31.288000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5357 11:57:31.288617 ==
5358 11:57:31.289001 [Gating] SW mode calibration
5359 11:57:31.297787 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 11:57:31.301147 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5361 11:57:31.304341 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 11:57:31.311050 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 11:57:31.314234 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 11:57:31.317721 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 11:57:31.324496 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5366 11:57:31.327523 0 10 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
5367 11:57:31.330870 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5368 11:57:31.337475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 11:57:31.340667 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 11:57:31.344348 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 11:57:31.350657 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 11:57:31.353901 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 11:57:31.357376 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5374 11:57:31.364106 0 11 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5375 11:57:31.367322 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5376 11:57:31.370746 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 11:57:31.377056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 11:57:31.380314 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 11:57:31.383851 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 11:57:31.390436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 11:57:31.393659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5382 11:57:31.397040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5383 11:57:31.403855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:57:31.406888 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:57:31.410303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:57:31.416944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:57:31.420073 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:57:31.423590 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:57:31.430123 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:57:31.433478 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:57:31.436467 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:57:31.443434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:57:31.447277 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:57:31.450238 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:57:31.456663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:57:31.460143 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:57:31.463645 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 11:57:31.470030 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5399 11:57:31.470752 Total UI for P1: 0, mck2ui 16
5400 11:57:31.473472 best dqsien dly found for B0: ( 0, 14, 16)
5401 11:57:31.480150 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5402 11:57:31.483367 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 11:57:31.486619 Total UI for P1: 0, mck2ui 16
5404 11:57:31.490019 best dqsien dly found for B1: ( 0, 14, 22)
5405 11:57:31.493223 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5406 11:57:31.496554 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5407 11:57:31.497015
5408 11:57:31.500051 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5409 11:57:31.506372 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5410 11:57:31.506899 [Gating] SW calibration Done
5411 11:57:31.509943 ==
5412 11:57:31.510502 Dram Type= 6, Freq= 0, CH_1, rank 0
5413 11:57:31.516668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5414 11:57:31.517235 ==
5415 11:57:31.517608 RX Vref Scan: 0
5416 11:57:31.517948
5417 11:57:31.520012 RX Vref 0 -> 0, step: 1
5418 11:57:31.520470
5419 11:57:31.523332 RX Delay -80 -> 252, step: 8
5420 11:57:31.526505 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5421 11:57:31.529884 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5422 11:57:31.533150 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5423 11:57:31.539622 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5424 11:57:31.543337 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5425 11:57:31.546319 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5426 11:57:31.549842 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5427 11:57:31.552997 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5428 11:57:31.556273 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5429 11:57:31.562863 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5430 11:57:31.566276 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5431 11:57:31.569357 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5432 11:57:31.573079 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5433 11:57:31.576180 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5434 11:57:31.582992 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5435 11:57:31.586260 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5436 11:57:31.586814 ==
5437 11:57:31.589259 Dram Type= 6, Freq= 0, CH_1, rank 0
5438 11:57:31.593062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5439 11:57:31.593705 ==
5440 11:57:31.594081 DQS Delay:
5441 11:57:31.596024 DQS0 = 0, DQS1 = 0
5442 11:57:31.596585 DQM Delay:
5443 11:57:31.599284 DQM0 = 93, DQM1 = 87
5444 11:57:31.599804 DQ Delay:
5445 11:57:31.602858 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5446 11:57:31.605870 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5447 11:57:31.609250 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5448 11:57:31.612688 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5449 11:57:31.613203
5450 11:57:31.613565
5451 11:57:31.613898 ==
5452 11:57:31.616493 Dram Type= 6, Freq= 0, CH_1, rank 0
5453 11:57:31.619114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5454 11:57:31.622829 ==
5455 11:57:31.623398
5456 11:57:31.623765
5457 11:57:31.624100 TX Vref Scan disable
5458 11:57:31.626119 == TX Byte 0 ==
5459 11:57:31.629455 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5460 11:57:31.632367 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5461 11:57:31.636021 == TX Byte 1 ==
5462 11:57:31.639367 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5463 11:57:31.642676 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5464 11:57:31.645939 ==
5465 11:57:31.648985 Dram Type= 6, Freq= 0, CH_1, rank 0
5466 11:57:31.652283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5467 11:57:31.652875 ==
5468 11:57:31.653306
5469 11:57:31.653649
5470 11:57:31.655671 TX Vref Scan disable
5471 11:57:31.656201 == TX Byte 0 ==
5472 11:57:31.662293 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5473 11:57:31.666064 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5474 11:57:31.666622 == TX Byte 1 ==
5475 11:57:31.672288 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5476 11:57:31.675342 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5477 11:57:31.675795
5478 11:57:31.676153 [DATLAT]
5479 11:57:31.678647 Freq=933, CH1 RK0
5480 11:57:31.679117
5481 11:57:31.679474 DATLAT Default: 0xd
5482 11:57:31.682316 0, 0xFFFF, sum = 0
5483 11:57:31.682873 1, 0xFFFF, sum = 0
5484 11:57:31.685359 2, 0xFFFF, sum = 0
5485 11:57:31.685816 3, 0xFFFF, sum = 0
5486 11:57:31.688859 4, 0xFFFF, sum = 0
5487 11:57:31.689558 5, 0xFFFF, sum = 0
5488 11:57:31.692036 6, 0xFFFF, sum = 0
5489 11:57:31.692491 7, 0xFFFF, sum = 0
5490 11:57:31.695403 8, 0xFFFF, sum = 0
5491 11:57:31.698717 9, 0xFFFF, sum = 0
5492 11:57:31.699191 10, 0x0, sum = 1
5493 11:57:31.699554 11, 0x0, sum = 2
5494 11:57:31.701928 12, 0x0, sum = 3
5495 11:57:31.702385 13, 0x0, sum = 4
5496 11:57:31.705226 best_step = 11
5497 11:57:31.705674
5498 11:57:31.706059 ==
5499 11:57:31.708501 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 11:57:31.711814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 11:57:31.712263 ==
5502 11:57:31.715096 RX Vref Scan: 1
5503 11:57:31.715545
5504 11:57:31.715899 RX Vref 0 -> 0, step: 1
5505 11:57:31.718654
5506 11:57:31.719209 RX Delay -69 -> 252, step: 4
5507 11:57:31.719575
5508 11:57:31.721729 Set Vref, RX VrefLevel [Byte0]: 56
5509 11:57:31.725063 [Byte1]: 54
5510 11:57:31.729591
5511 11:57:31.730041 Final RX Vref Byte 0 = 56 to rank0
5512 11:57:31.732769 Final RX Vref Byte 1 = 54 to rank0
5513 11:57:31.736657 Final RX Vref Byte 0 = 56 to rank1
5514 11:57:31.739685 Final RX Vref Byte 1 = 54 to rank1==
5515 11:57:31.743118 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 11:57:31.749855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 11:57:31.750400 ==
5518 11:57:31.750763 DQS Delay:
5519 11:57:31.751094 DQS0 = 0, DQS1 = 0
5520 11:57:31.752789 DQM Delay:
5521 11:57:31.753242 DQM0 = 94, DQM1 = 89
5522 11:57:31.756261 DQ Delay:
5523 11:57:31.759867 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5524 11:57:31.762847 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5525 11:57:31.766536 DQ8 =74, DQ9 =80, DQ10 =90, DQ11 =80
5526 11:57:31.769568 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =98
5527 11:57:31.770110
5528 11:57:31.770472
5529 11:57:31.776186 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5530 11:57:31.779613 CH1 RK0: MR19=505, MR18=3737
5531 11:57:31.786336 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5532 11:57:31.786889
5533 11:57:31.789100 ----->DramcWriteLeveling(PI) begin...
5534 11:57:31.789610 ==
5535 11:57:31.792560 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 11:57:31.796107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5537 11:57:31.796703 ==
5538 11:57:31.799520 Write leveling (Byte 0): 23 => 23
5539 11:57:31.802592 Write leveling (Byte 1): 23 => 23
5540 11:57:31.805954 DramcWriteLeveling(PI) end<-----
5541 11:57:31.806574
5542 11:57:31.806948 ==
5543 11:57:31.809121 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 11:57:31.812259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5545 11:57:31.812767 ==
5546 11:57:31.815767 [Gating] SW mode calibration
5547 11:57:31.822569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 11:57:31.829300 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5549 11:57:31.832996 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 11:57:31.839080 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 11:57:31.842822 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 11:57:31.845828 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5553 11:57:31.852265 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
5554 11:57:31.855621 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5555 11:57:31.858818 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 11:57:31.865697 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 11:57:31.868911 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 11:57:31.872492 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 11:57:31.878645 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 11:57:31.882087 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5561 11:57:31.885260 0 11 16 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
5562 11:57:31.892116 0 11 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5563 11:57:31.895507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 11:57:31.898536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 11:57:31.905276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 11:57:31.908475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 11:57:31.912340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 11:57:31.918309 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 11:57:31.921516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5570 11:57:31.925064 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5571 11:57:31.928434 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 11:57:31.935152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 11:57:31.938629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:57:31.941552 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:57:31.948329 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 11:57:31.951927 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 11:57:31.954892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 11:57:31.961516 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 11:57:31.965051 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 11:57:31.968602 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 11:57:31.975024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:57:31.977906 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:57:31.981337 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:57:31.988213 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:57:31.991187 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5586 11:57:31.994960 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5587 11:57:31.997990 Total UI for P1: 0, mck2ui 16
5588 11:57:32.001317 best dqsien dly found for B0: ( 0, 14, 16)
5589 11:57:32.007952 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 11:57:32.008545 Total UI for P1: 0, mck2ui 16
5591 11:57:32.014370 best dqsien dly found for B1: ( 0, 14, 20)
5592 11:57:32.018158 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5593 11:57:32.021242 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5594 11:57:32.021793
5595 11:57:32.024658 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5596 11:57:32.028029 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5597 11:57:32.031323 [Gating] SW calibration Done
5598 11:57:32.031873 ==
5599 11:57:32.034533 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 11:57:32.037585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5601 11:57:32.038137 ==
5602 11:57:32.041046 RX Vref Scan: 0
5603 11:57:32.041497
5604 11:57:32.044095 RX Vref 0 -> 0, step: 1
5605 11:57:32.044697
5606 11:57:32.045092 RX Delay -80 -> 252, step: 8
5607 11:57:32.050832 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5608 11:57:32.053913 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5609 11:57:32.057550 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5610 11:57:32.060928 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5611 11:57:32.064293 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5612 11:57:32.067528 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5613 11:57:32.074110 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5614 11:57:32.077130 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5615 11:57:32.080296 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5616 11:57:32.084374 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5617 11:57:32.087090 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5618 11:57:32.094098 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5619 11:57:32.097080 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5620 11:57:32.100478 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5621 11:57:32.103853 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5622 11:57:32.107381 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5623 11:57:32.108013 ==
5624 11:57:32.110736 Dram Type= 6, Freq= 0, CH_1, rank 1
5625 11:57:32.117371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5626 11:57:32.117954 ==
5627 11:57:32.118326 DQS Delay:
5628 11:57:32.118666 DQS0 = 0, DQS1 = 0
5629 11:57:32.120614 DQM Delay:
5630 11:57:32.121064 DQM0 = 96, DQM1 = 89
5631 11:57:32.123912 DQ Delay:
5632 11:57:32.127402 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5633 11:57:32.130707 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5634 11:57:32.131257 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5635 11:57:32.137158 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5636 11:57:32.137705
5637 11:57:32.138064
5638 11:57:32.138397 ==
5639 11:57:32.140404 Dram Type= 6, Freq= 0, CH_1, rank 1
5640 11:57:32.143897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5641 11:57:32.144441 ==
5642 11:57:32.144864
5643 11:57:32.145198
5644 11:57:32.147340 TX Vref Scan disable
5645 11:57:32.148007 == TX Byte 0 ==
5646 11:57:32.153724 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5647 11:57:32.157054 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5648 11:57:32.157510 == TX Byte 1 ==
5649 11:57:32.163549 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5650 11:57:32.166938 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5651 11:57:32.167392 ==
5652 11:57:32.170350 Dram Type= 6, Freq= 0, CH_1, rank 1
5653 11:57:32.173524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5654 11:57:32.173979 ==
5655 11:57:32.174336
5656 11:57:32.174668
5657 11:57:32.176772 TX Vref Scan disable
5658 11:57:32.180070 == TX Byte 0 ==
5659 11:57:32.183318 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5660 11:57:32.187014 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5661 11:57:32.190191 == TX Byte 1 ==
5662 11:57:32.193375 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5663 11:57:32.197192 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5664 11:57:32.197743
5665 11:57:32.199938 [DATLAT]
5666 11:57:32.200388 Freq=933, CH1 RK1
5667 11:57:32.200788
5668 11:57:32.203245 DATLAT Default: 0xb
5669 11:57:32.203695 0, 0xFFFF, sum = 0
5670 11:57:32.206619 1, 0xFFFF, sum = 0
5671 11:57:32.207174 2, 0xFFFF, sum = 0
5672 11:57:32.209940 3, 0xFFFF, sum = 0
5673 11:57:32.210397 4, 0xFFFF, sum = 0
5674 11:57:32.213357 5, 0xFFFF, sum = 0
5675 11:57:32.213966 6, 0xFFFF, sum = 0
5676 11:57:32.216483 7, 0xFFFF, sum = 0
5677 11:57:32.216985 8, 0xFFFF, sum = 0
5678 11:57:32.219795 9, 0xFFFF, sum = 0
5679 11:57:32.220251 10, 0x0, sum = 1
5680 11:57:32.223098 11, 0x0, sum = 2
5681 11:57:32.223644 12, 0x0, sum = 3
5682 11:57:32.226443 13, 0x0, sum = 4
5683 11:57:32.226971 best_step = 11
5684 11:57:32.227332
5685 11:57:32.227667 ==
5686 11:57:32.229759 Dram Type= 6, Freq= 0, CH_1, rank 1
5687 11:57:32.236424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5688 11:57:32.237007 ==
5689 11:57:32.237373 RX Vref Scan: 0
5690 11:57:32.237708
5691 11:57:32.239771 RX Vref 0 -> 0, step: 1
5692 11:57:32.240218
5693 11:57:32.242960 RX Delay -69 -> 252, step: 4
5694 11:57:32.246176 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5695 11:57:32.252998 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5696 11:57:32.256285 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5697 11:57:32.259587 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5698 11:57:32.263012 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5699 11:57:32.266214 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5700 11:57:32.269764 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5701 11:57:32.276041 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5702 11:57:32.279589 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5703 11:57:32.282751 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5704 11:57:32.286158 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5705 11:57:32.289562 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5706 11:57:32.296092 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5707 11:57:32.299599 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5708 11:57:32.302972 iDelay=203, Bit 14, Center 96 (-1 ~ 194) 196
5709 11:57:32.306045 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5710 11:57:32.306499 ==
5711 11:57:32.309077 Dram Type= 6, Freq= 0, CH_1, rank 1
5712 11:57:32.312662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5713 11:57:32.316219 ==
5714 11:57:32.316792 DQS Delay:
5715 11:57:32.317161 DQS0 = 0, DQS1 = 0
5716 11:57:32.319161 DQM Delay:
5717 11:57:32.319609 DQM0 = 96, DQM1 = 88
5718 11:57:32.322304 DQ Delay:
5719 11:57:32.322789 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5720 11:57:32.325604 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5721 11:57:32.329150 DQ8 =76, DQ9 =78, DQ10 =88, DQ11 =80
5722 11:57:32.335564 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =94
5723 11:57:32.336077
5724 11:57:32.336433
5725 11:57:32.342165 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5726 11:57:32.345465 CH1 RK1: MR19=505, MR18=2525
5727 11:57:32.352422 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5728 11:57:32.355416 [RxdqsGatingPostProcess] freq 933
5729 11:57:32.358712 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5730 11:57:32.362050 Pre-setting of DQS Precalculation
5731 11:57:32.368604 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5732 11:57:32.375272 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5733 11:57:32.381621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5734 11:57:32.382137
5735 11:57:32.382499
5736 11:57:32.385161 [Calibration Summary] 1866 Mbps
5737 11:57:32.385618 CH 0, Rank 0
5738 11:57:32.388414 SW Impedance : PASS
5739 11:57:32.391972 DUTY Scan : NO K
5740 11:57:32.392421 ZQ Calibration : PASS
5741 11:57:32.395176 Jitter Meter : NO K
5742 11:57:32.398627 CBT Training : PASS
5743 11:57:32.399084 Write leveling : PASS
5744 11:57:32.401554 RX DQS gating : PASS
5745 11:57:32.405271 RX DQ/DQS(RDDQC) : PASS
5746 11:57:32.405958 TX DQ/DQS : PASS
5747 11:57:32.408324 RX DATLAT : PASS
5748 11:57:32.411566 RX DQ/DQS(Engine): PASS
5749 11:57:32.412021 TX OE : NO K
5750 11:57:32.414925 All Pass.
5751 11:57:32.415387
5752 11:57:32.415743 CH 0, Rank 1
5753 11:57:32.418638 SW Impedance : PASS
5754 11:57:32.419160 DUTY Scan : NO K
5755 11:57:32.421548 ZQ Calibration : PASS
5756 11:57:32.424981 Jitter Meter : NO K
5757 11:57:32.425432 CBT Training : PASS
5758 11:57:32.428196 Write leveling : PASS
5759 11:57:32.428761 RX DQS gating : PASS
5760 11:57:32.431677 RX DQ/DQS(RDDQC) : PASS
5761 11:57:32.434870 TX DQ/DQS : PASS
5762 11:57:32.435421 RX DATLAT : PASS
5763 11:57:32.438473 RX DQ/DQS(Engine): PASS
5764 11:57:32.441581 TX OE : NO K
5765 11:57:32.442031 All Pass.
5766 11:57:32.442388
5767 11:57:32.442721 CH 1, Rank 0
5768 11:57:32.445051 SW Impedance : PASS
5769 11:57:32.448329 DUTY Scan : NO K
5770 11:57:32.448937 ZQ Calibration : PASS
5771 11:57:32.451474 Jitter Meter : NO K
5772 11:57:32.454676 CBT Training : PASS
5773 11:57:32.455265 Write leveling : PASS
5774 11:57:32.457930 RX DQS gating : PASS
5775 11:57:32.461775 RX DQ/DQS(RDDQC) : PASS
5776 11:57:32.462323 TX DQ/DQS : PASS
5777 11:57:32.464807 RX DATLAT : PASS
5778 11:57:32.468283 RX DQ/DQS(Engine): PASS
5779 11:57:32.468876 TX OE : NO K
5780 11:57:32.471345 All Pass.
5781 11:57:32.471945
5782 11:57:32.472314 CH 1, Rank 1
5783 11:57:32.474393 SW Impedance : PASS
5784 11:57:32.474844 DUTY Scan : NO K
5785 11:57:32.477956 ZQ Calibration : PASS
5786 11:57:32.481111 Jitter Meter : NO K
5787 11:57:32.481723 CBT Training : PASS
5788 11:57:32.484477 Write leveling : PASS
5789 11:57:32.485093 RX DQS gating : PASS
5790 11:57:32.487828 RX DQ/DQS(RDDQC) : PASS
5791 11:57:32.491416 TX DQ/DQS : PASS
5792 11:57:32.492145 RX DATLAT : PASS
5793 11:57:32.494289 RX DQ/DQS(Engine): PASS
5794 11:57:32.497888 TX OE : NO K
5795 11:57:32.498370 All Pass.
5796 11:57:32.498733
5797 11:57:32.500942 DramC Write-DBI off
5798 11:57:32.501566 PER_BANK_REFRESH: Hybrid Mode
5799 11:57:32.504340 TX_TRACKING: ON
5800 11:57:32.514739 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5801 11:57:32.517629 [FAST_K] Save calibration result to emmc
5802 11:57:32.520983 dramc_set_vcore_voltage set vcore to 650000
5803 11:57:32.521560 Read voltage for 400, 6
5804 11:57:32.524261 Vio18 = 0
5805 11:57:32.524894 Vcore = 650000
5806 11:57:32.525265 Vdram = 0
5807 11:57:32.527581 Vddq = 0
5808 11:57:32.528260 Vmddr = 0
5809 11:57:32.531358 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5810 11:57:32.537551 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5811 11:57:32.540822 MEM_TYPE=3, freq_sel=20
5812 11:57:32.544323 sv_algorithm_assistance_LP4_800
5813 11:57:32.547785 ============ PULL DRAM RESETB DOWN ============
5814 11:57:32.551332 ========== PULL DRAM RESETB DOWN end =========
5815 11:57:32.557441 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5816 11:57:32.560759 ===================================
5817 11:57:32.561215 LPDDR4 DRAM CONFIGURATION
5818 11:57:32.564460 ===================================
5819 11:57:32.567453 EX_ROW_EN[0] = 0x0
5820 11:57:32.568002 EX_ROW_EN[1] = 0x0
5821 11:57:32.570621 LP4Y_EN = 0x0
5822 11:57:32.571073 WORK_FSP = 0x0
5823 11:57:32.574592 WL = 0x2
5824 11:57:32.577323 RL = 0x2
5825 11:57:32.577775 BL = 0x2
5826 11:57:32.580895 RPST = 0x0
5827 11:57:32.581455 RD_PRE = 0x0
5828 11:57:32.584136 WR_PRE = 0x1
5829 11:57:32.584632 WR_PST = 0x0
5830 11:57:32.587338 DBI_WR = 0x0
5831 11:57:32.587880 DBI_RD = 0x0
5832 11:57:32.590916 OTF = 0x1
5833 11:57:32.594051 ===================================
5834 11:57:32.597476 ===================================
5835 11:57:32.598126 ANA top config
5836 11:57:32.601052 ===================================
5837 11:57:32.604102 DLL_ASYNC_EN = 0
5838 11:57:32.607356 ALL_SLAVE_EN = 1
5839 11:57:32.607882 NEW_RANK_MODE = 1
5840 11:57:32.610828 DLL_IDLE_MODE = 1
5841 11:57:32.614042 LP45_APHY_COMB_EN = 1
5842 11:57:32.617301 TX_ODT_DIS = 1
5843 11:57:32.617936 NEW_8X_MODE = 1
5844 11:57:32.620816 ===================================
5845 11:57:32.624020 ===================================
5846 11:57:32.627421 data_rate = 800
5847 11:57:32.630674 CKR = 1
5848 11:57:32.634102 DQ_P2S_RATIO = 4
5849 11:57:32.637288 ===================================
5850 11:57:32.640545 CA_P2S_RATIO = 4
5851 11:57:32.644205 DQ_CA_OPEN = 0
5852 11:57:32.644818 DQ_SEMI_OPEN = 1
5853 11:57:32.647531 CA_SEMI_OPEN = 1
5854 11:57:32.650846 CA_FULL_RATE = 0
5855 11:57:32.654085 DQ_CKDIV4_EN = 0
5856 11:57:32.657011 CA_CKDIV4_EN = 1
5857 11:57:32.660781 CA_PREDIV_EN = 0
5858 11:57:32.661331 PH8_DLY = 0
5859 11:57:32.663860 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5860 11:57:32.667218 DQ_AAMCK_DIV = 0
5861 11:57:32.670668 CA_AAMCK_DIV = 0
5862 11:57:32.673450 CA_ADMCK_DIV = 4
5863 11:57:32.677372 DQ_TRACK_CA_EN = 0
5864 11:57:32.680600 CA_PICK = 800
5865 11:57:32.681166 CA_MCKIO = 400
5866 11:57:32.683460 MCKIO_SEMI = 400
5867 11:57:32.686632 PLL_FREQ = 3016
5868 11:57:32.690263 DQ_UI_PI_RATIO = 32
5869 11:57:32.693330 CA_UI_PI_RATIO = 32
5870 11:57:32.697273 ===================================
5871 11:57:32.700614 ===================================
5872 11:57:32.703761 memory_type:LPDDR4
5873 11:57:32.704213 GP_NUM : 10
5874 11:57:32.706560 SRAM_EN : 1
5875 11:57:32.709980 MD32_EN : 0
5876 11:57:32.713251 ===================================
5877 11:57:32.713704 [ANA_INIT] >>>>>>>>>>>>>>
5878 11:57:32.717337 <<<<<< [CONFIGURE PHASE]: ANA_TX
5879 11:57:32.720436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5880 11:57:32.723155 ===================================
5881 11:57:32.726964 data_rate = 800,PCW = 0X7400
5882 11:57:32.729973 ===================================
5883 11:57:32.733318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5884 11:57:32.739975 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5885 11:57:32.749625 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5886 11:57:32.756168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5887 11:57:32.759387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5888 11:57:32.762781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5889 11:57:32.763336 [ANA_INIT] flow start
5890 11:57:32.765975 [ANA_INIT] PLL >>>>>>>>
5891 11:57:32.769353 [ANA_INIT] PLL <<<<<<<<
5892 11:57:32.769804 [ANA_INIT] MIDPI >>>>>>>>
5893 11:57:32.772701 [ANA_INIT] MIDPI <<<<<<<<
5894 11:57:32.776200 [ANA_INIT] DLL >>>>>>>>
5895 11:57:32.776794 [ANA_INIT] flow end
5896 11:57:32.782560 ============ LP4 DIFF to SE enter ============
5897 11:57:32.785994 ============ LP4 DIFF to SE exit ============
5898 11:57:32.786635 [ANA_INIT] <<<<<<<<<<<<<
5899 11:57:32.789501 [Flow] Enable top DCM control >>>>>
5900 11:57:32.792476 [Flow] Enable top DCM control <<<<<
5901 11:57:32.796210 Enable DLL master slave shuffle
5902 11:57:32.802741 ==============================================================
5903 11:57:32.806097 Gating Mode config
5904 11:57:32.809344 ==============================================================
5905 11:57:32.812654 Config description:
5906 11:57:32.822515 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5907 11:57:32.829092 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5908 11:57:32.832495 SELPH_MODE 0: By rank 1: By Phase
5909 11:57:32.839057 ==============================================================
5910 11:57:32.842008 GAT_TRACK_EN = 0
5911 11:57:32.845536 RX_GATING_MODE = 2
5912 11:57:32.848979 RX_GATING_TRACK_MODE = 2
5913 11:57:32.852444 SELPH_MODE = 1
5914 11:57:32.853028 PICG_EARLY_EN = 1
5915 11:57:32.855367 VALID_LAT_VALUE = 1
5916 11:57:32.862510 ==============================================================
5917 11:57:32.865449 Enter into Gating configuration >>>>
5918 11:57:32.868950 Exit from Gating configuration <<<<
5919 11:57:32.872175 Enter into DVFS_PRE_config >>>>>
5920 11:57:32.881953 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5921 11:57:32.885135 Exit from DVFS_PRE_config <<<<<
5922 11:57:32.888397 Enter into PICG configuration >>>>
5923 11:57:32.892257 Exit from PICG configuration <<<<
5924 11:57:32.895498 [RX_INPUT] configuration >>>>>
5925 11:57:32.898615 [RX_INPUT] configuration <<<<<
5926 11:57:32.901982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5927 11:57:32.908476 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5928 11:57:32.914983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5929 11:57:32.921294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5930 11:57:32.928354 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5931 11:57:32.934926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5932 11:57:32.938210 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5933 11:57:32.941130 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5934 11:57:32.944914 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5935 11:57:32.951548 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5936 11:57:32.954414 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5937 11:57:32.957946 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5938 11:57:32.961297 ===================================
5939 11:57:32.964916 LPDDR4 DRAM CONFIGURATION
5940 11:57:32.968331 ===================================
5941 11:57:32.968929 EX_ROW_EN[0] = 0x0
5942 11:57:32.971490 EX_ROW_EN[1] = 0x0
5943 11:57:32.972035 LP4Y_EN = 0x0
5944 11:57:32.975114 WORK_FSP = 0x0
5945 11:57:32.975661 WL = 0x2
5946 11:57:32.978144 RL = 0x2
5947 11:57:32.978698 BL = 0x2
5948 11:57:32.981137 RPST = 0x0
5949 11:57:32.984543 RD_PRE = 0x0
5950 11:57:32.985001 WR_PRE = 0x1
5951 11:57:32.987931 WR_PST = 0x0
5952 11:57:32.988381 DBI_WR = 0x0
5953 11:57:32.991580 DBI_RD = 0x0
5954 11:57:32.992126 OTF = 0x1
5955 11:57:32.994861 ===================================
5956 11:57:32.998053 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5957 11:57:33.004488 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5958 11:57:33.007809 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5959 11:57:33.010935 ===================================
5960 11:57:33.014830 LPDDR4 DRAM CONFIGURATION
5961 11:57:33.017661 ===================================
5962 11:57:33.018118 EX_ROW_EN[0] = 0x10
5963 11:57:33.021103 EX_ROW_EN[1] = 0x0
5964 11:57:33.021650 LP4Y_EN = 0x0
5965 11:57:33.024388 WORK_FSP = 0x0
5966 11:57:33.025097 WL = 0x2
5967 11:57:33.027950 RL = 0x2
5968 11:57:33.028402 BL = 0x2
5969 11:57:33.031120 RPST = 0x0
5970 11:57:33.031668 RD_PRE = 0x0
5971 11:57:33.034566 WR_PRE = 0x1
5972 11:57:33.038122 WR_PST = 0x0
5973 11:57:33.038670 DBI_WR = 0x0
5974 11:57:33.041000 DBI_RD = 0x0
5975 11:57:33.041557 OTF = 0x1
5976 11:57:33.044073 ===================================
5977 11:57:33.051148 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5978 11:57:33.054554 nWR fixed to 30
5979 11:57:33.057672 [ModeRegInit_LP4] CH0 RK0
5980 11:57:33.058134 [ModeRegInit_LP4] CH0 RK1
5981 11:57:33.061121 [ModeRegInit_LP4] CH1 RK0
5982 11:57:33.064667 [ModeRegInit_LP4] CH1 RK1
5983 11:57:33.065220 match AC timing 18
5984 11:57:33.071346 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5985 11:57:33.074476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5986 11:57:33.078183 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5987 11:57:33.084776 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5988 11:57:33.087829 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5989 11:57:33.088396 ==
5990 11:57:33.091313 Dram Type= 6, Freq= 0, CH_0, rank 0
5991 11:57:33.094488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5992 11:57:33.094969 ==
5993 11:57:33.101275 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5994 11:57:33.108044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5995 11:57:33.111066 [CA 0] Center 36 (8~64) winsize 57
5996 11:57:33.114406 [CA 1] Center 36 (8~64) winsize 57
5997 11:57:33.117374 [CA 2] Center 36 (8~64) winsize 57
5998 11:57:33.121125 [CA 3] Center 36 (8~64) winsize 57
5999 11:57:33.121701 [CA 4] Center 36 (8~64) winsize 57
6000 11:57:33.124128 [CA 5] Center 36 (8~64) winsize 57
6001 11:57:33.124650
6002 11:57:33.130646 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6003 11:57:33.131114
6004 11:57:33.134288 [CATrainingPosCal] consider 1 rank data
6005 11:57:33.137295 u2DelayCellTimex100 = 270/100 ps
6006 11:57:33.140495 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 11:57:33.144033 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 11:57:33.147126 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 11:57:33.150523 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 11:57:33.153718 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 11:57:33.157129 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 11:57:33.157603
6013 11:57:33.160489 CA PerBit enable=1, Macro0, CA PI delay=36
6014 11:57:33.161007
6015 11:57:33.164059 [CBTSetCACLKResult] CA Dly = 36
6016 11:57:33.167877 CS Dly: 1 (0~32)
6017 11:57:33.168446 ==
6018 11:57:33.170370 Dram Type= 6, Freq= 0, CH_0, rank 1
6019 11:57:33.174086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6020 11:57:33.174678 ==
6021 11:57:33.180735 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6022 11:57:33.186899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6023 11:57:33.187455 [CA 0] Center 36 (8~64) winsize 57
6024 11:57:33.190446 [CA 1] Center 36 (8~64) winsize 57
6025 11:57:33.193860 [CA 2] Center 36 (8~64) winsize 57
6026 11:57:33.196941 [CA 3] Center 36 (8~64) winsize 57
6027 11:57:33.200447 [CA 4] Center 36 (8~64) winsize 57
6028 11:57:33.203800 [CA 5] Center 36 (8~64) winsize 57
6029 11:57:33.204489
6030 11:57:33.207012 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6031 11:57:33.207584
6032 11:57:33.210256 [CATrainingPosCal] consider 2 rank data
6033 11:57:33.213287 u2DelayCellTimex100 = 270/100 ps
6034 11:57:33.217280 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 11:57:33.223307 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 11:57:33.227143 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 11:57:33.229841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 11:57:33.233534 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 11:57:33.236864 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 11:57:33.237412
6041 11:57:33.239818 CA PerBit enable=1, Macro0, CA PI delay=36
6042 11:57:33.240276
6043 11:57:33.243108 [CBTSetCACLKResult] CA Dly = 36
6044 11:57:33.243642 CS Dly: 1 (0~32)
6045 11:57:33.246650
6046 11:57:33.250306 ----->DramcWriteLeveling(PI) begin...
6047 11:57:33.250862 ==
6048 11:57:33.253415 Dram Type= 6, Freq= 0, CH_0, rank 0
6049 11:57:33.256484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6050 11:57:33.256962 ==
6051 11:57:33.259898 Write leveling (Byte 0): 32 => 0
6052 11:57:33.263365 Write leveling (Byte 1): 32 => 0
6053 11:57:33.266823 DramcWriteLeveling(PI) end<-----
6054 11:57:33.267388
6055 11:57:33.267752 ==
6056 11:57:33.269877 Dram Type= 6, Freq= 0, CH_0, rank 0
6057 11:57:33.273425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6058 11:57:33.273978 ==
6059 11:57:33.276560 [Gating] SW mode calibration
6060 11:57:33.283140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6061 11:57:33.286449 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6062 11:57:33.293037 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6063 11:57:33.296602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6064 11:57:33.299934 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6065 11:57:33.306643 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6066 11:57:33.309581 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6067 11:57:33.313079 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6068 11:57:33.319479 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6069 11:57:33.323006 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6070 11:57:33.327081 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6071 11:57:33.329475 Total UI for P1: 0, mck2ui 16
6072 11:57:33.333320 best dqsien dly found for B0: ( 0, 10, 16)
6073 11:57:33.336598 Total UI for P1: 0, mck2ui 16
6074 11:57:33.339675 best dqsien dly found for B1: ( 0, 10, 24)
6075 11:57:33.342765 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6076 11:57:33.349582 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6077 11:57:33.350137
6078 11:57:33.353213 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6079 11:57:33.356064 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6080 11:57:33.359614 [Gating] SW calibration Done
6081 11:57:33.360174 ==
6082 11:57:33.362900 Dram Type= 6, Freq= 0, CH_0, rank 0
6083 11:57:33.366169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6084 11:57:33.366723 ==
6085 11:57:33.369493 RX Vref Scan: 0
6086 11:57:33.370043
6087 11:57:33.370414 RX Vref 0 -> 0, step: 1
6088 11:57:33.370757
6089 11:57:33.372974 RX Delay -410 -> 252, step: 16
6090 11:57:33.376304 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6091 11:57:33.382734 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6092 11:57:33.385973 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6093 11:57:33.389131 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6094 11:57:33.392896 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6095 11:57:33.399363 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6096 11:57:33.402816 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6097 11:57:33.405785 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6098 11:57:33.409440 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6099 11:57:33.415839 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6100 11:57:33.418994 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6101 11:57:33.422496 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6102 11:57:33.429308 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6103 11:57:33.432355 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6104 11:57:33.435837 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6105 11:57:33.439502 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6106 11:57:33.440219 ==
6107 11:57:33.442349 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 11:57:33.449211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 11:57:33.449761 ==
6110 11:57:33.450133 DQS Delay:
6111 11:57:33.452424 DQS0 = 51, DQS1 = 59
6112 11:57:33.453033 DQM Delay:
6113 11:57:33.455446 DQM0 = 12, DQM1 = 16
6114 11:57:33.455905 DQ Delay:
6115 11:57:33.458747 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6116 11:57:33.461912 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6117 11:57:33.462373 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6118 11:57:33.469126 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6119 11:57:33.469692
6120 11:57:33.470060
6121 11:57:33.470402 ==
6122 11:57:33.472052 Dram Type= 6, Freq= 0, CH_0, rank 0
6123 11:57:33.475685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6124 11:57:33.476250 ==
6125 11:57:33.476676
6126 11:57:33.477023
6127 11:57:33.478754 TX Vref Scan disable
6128 11:57:33.479313 == TX Byte 0 ==
6129 11:57:33.485256 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 11:57:33.488687 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 11:57:33.489150 == TX Byte 1 ==
6132 11:57:33.495434 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 11:57:33.498696 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 11:57:33.499261 ==
6135 11:57:33.501817 Dram Type= 6, Freq= 0, CH_0, rank 0
6136 11:57:33.505468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6137 11:57:33.506031 ==
6138 11:57:33.506400
6139 11:57:33.506738
6140 11:57:33.508534 TX Vref Scan disable
6141 11:57:33.508994 == TX Byte 0 ==
6142 11:57:33.515071 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 11:57:33.518289 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 11:57:33.518773 == TX Byte 1 ==
6145 11:57:33.525246 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6146 11:57:33.528703 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6147 11:57:33.529251
6148 11:57:33.529619 [DATLAT]
6149 11:57:33.532051 Freq=400, CH0 RK0
6150 11:57:33.532643
6151 11:57:33.533010 DATLAT Default: 0xf
6152 11:57:33.535268 0, 0xFFFF, sum = 0
6153 11:57:33.535822 1, 0xFFFF, sum = 0
6154 11:57:33.538416 2, 0xFFFF, sum = 0
6155 11:57:33.538880 3, 0xFFFF, sum = 0
6156 11:57:33.541533 4, 0xFFFF, sum = 0
6157 11:57:33.541999 5, 0xFFFF, sum = 0
6158 11:57:33.545262 6, 0xFFFF, sum = 0
6159 11:57:33.545747 7, 0xFFFF, sum = 0
6160 11:57:33.548707 8, 0xFFFF, sum = 0
6161 11:57:33.552448 9, 0xFFFF, sum = 0
6162 11:57:33.553053 10, 0xFFFF, sum = 0
6163 11:57:33.554927 11, 0xFFFF, sum = 0
6164 11:57:33.555390 12, 0x0, sum = 1
6165 11:57:33.558402 13, 0x0, sum = 2
6166 11:57:33.558870 14, 0x0, sum = 3
6167 11:57:33.559241 15, 0x0, sum = 4
6168 11:57:33.561797 best_step = 13
6169 11:57:33.562253
6170 11:57:33.562613 ==
6171 11:57:33.564860 Dram Type= 6, Freq= 0, CH_0, rank 0
6172 11:57:33.568446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6173 11:57:33.569079 ==
6174 11:57:33.571831 RX Vref Scan: 1
6175 11:57:33.572376
6176 11:57:33.575202 RX Vref 0 -> 0, step: 1
6177 11:57:33.575749
6178 11:57:33.576115 RX Delay -359 -> 252, step: 8
6179 11:57:33.576457
6180 11:57:33.578769 Set Vref, RX VrefLevel [Byte0]: 50
6181 11:57:33.581450 [Byte1]: 48
6182 11:57:33.587141
6183 11:57:33.587974 Final RX Vref Byte 0 = 50 to rank0
6184 11:57:33.590573 Final RX Vref Byte 1 = 48 to rank0
6185 11:57:33.593588 Final RX Vref Byte 0 = 50 to rank1
6186 11:57:33.597150 Final RX Vref Byte 1 = 48 to rank1==
6187 11:57:33.600209 Dram Type= 6, Freq= 0, CH_0, rank 0
6188 11:57:33.607047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6189 11:57:33.607651 ==
6190 11:57:33.608201 DQS Delay:
6191 11:57:33.610260 DQS0 = 52, DQS1 = 68
6192 11:57:33.610809 DQM Delay:
6193 11:57:33.611177 DQM0 = 9, DQM1 = 16
6194 11:57:33.613372 DQ Delay:
6195 11:57:33.617496 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6196 11:57:33.618045 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6197 11:57:33.620314 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6198 11:57:33.623462 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6199 11:57:33.624010
6200 11:57:33.624383
6201 11:57:33.633309 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6202 11:57:33.636810 CH0 RK0: MR19=C0C, MR18=B1B1
6203 11:57:33.643202 CH0_RK0: MR19=0xC0C, MR18=0xB1B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6204 11:57:33.643759 ==
6205 11:57:33.646901 Dram Type= 6, Freq= 0, CH_0, rank 1
6206 11:57:33.650051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6207 11:57:33.650604 ==
6208 11:57:33.653452 [Gating] SW mode calibration
6209 11:57:33.659925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6210 11:57:33.666563 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6211 11:57:33.669595 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6212 11:57:33.672897 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6213 11:57:33.679675 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6214 11:57:33.683040 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6215 11:57:33.686327 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6216 11:57:33.689393 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6217 11:57:33.695964 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6218 11:57:33.699881 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6219 11:57:33.703051 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6220 11:57:33.706229 Total UI for P1: 0, mck2ui 16
6221 11:57:33.709370 best dqsien dly found for B0: ( 0, 10, 16)
6222 11:57:33.712940 Total UI for P1: 0, mck2ui 16
6223 11:57:33.716428 best dqsien dly found for B1: ( 0, 10, 16)
6224 11:57:33.719041 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6225 11:57:33.726188 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6226 11:57:33.726748
6227 11:57:33.729495 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6228 11:57:33.732421 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6229 11:57:33.736008 [Gating] SW calibration Done
6230 11:57:33.736466 ==
6231 11:57:33.739342 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 11:57:33.742713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6233 11:57:33.743280 ==
6234 11:57:33.745748 RX Vref Scan: 0
6235 11:57:33.746205
6236 11:57:33.746570 RX Vref 0 -> 0, step: 1
6237 11:57:33.746910
6238 11:57:33.749472 RX Delay -410 -> 252, step: 16
6239 11:57:33.752709 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6240 11:57:33.759438 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6241 11:57:33.762300 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6242 11:57:33.765731 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6243 11:57:33.769374 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6244 11:57:33.775753 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6245 11:57:33.779225 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6246 11:57:33.782374 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6247 11:57:33.785466 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6248 11:57:33.792381 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6249 11:57:33.795653 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6250 11:57:33.799028 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6251 11:57:33.805479 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6252 11:57:33.809037 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6253 11:57:33.811925 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6254 11:57:33.815585 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6255 11:57:33.816162 ==
6256 11:57:33.818739 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 11:57:33.825645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 11:57:33.826213 ==
6259 11:57:33.826584 DQS Delay:
6260 11:57:33.828947 DQS0 = 43, DQS1 = 59
6261 11:57:33.829505 DQM Delay:
6262 11:57:33.829874 DQM0 = 6, DQM1 = 15
6263 11:57:33.832225 DQ Delay:
6264 11:57:33.835771 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6265 11:57:33.836328 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6266 11:57:33.839000 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6267 11:57:33.842423 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6268 11:57:33.842986
6269 11:57:33.845310
6270 11:57:33.845769 ==
6271 11:57:33.849011 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 11:57:33.852383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6273 11:57:33.852985 ==
6274 11:57:33.853363
6275 11:57:33.853702
6276 11:57:33.855155 TX Vref Scan disable
6277 11:57:33.855621 == TX Byte 0 ==
6278 11:57:33.858511 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6279 11:57:33.865453 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6280 11:57:33.866005 == TX Byte 1 ==
6281 11:57:33.868816 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6282 11:57:33.875996 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6283 11:57:33.876592 ==
6284 11:57:33.878706 Dram Type= 6, Freq= 0, CH_0, rank 1
6285 11:57:33.882399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6286 11:57:33.882955 ==
6287 11:57:33.883325
6288 11:57:33.883662
6289 11:57:33.885097 TX Vref Scan disable
6290 11:57:33.885557 == TX Byte 0 ==
6291 11:57:33.888725 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6292 11:57:33.894807 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6293 11:57:33.895268 == TX Byte 1 ==
6294 11:57:33.898364 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6295 11:57:33.905039 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6296 11:57:33.905507
6297 11:57:33.905875 [DATLAT]
6298 11:57:33.906215 Freq=400, CH0 RK1
6299 11:57:33.908180
6300 11:57:33.908678 DATLAT Default: 0xd
6301 11:57:33.911759 0, 0xFFFF, sum = 0
6302 11:57:33.912221 1, 0xFFFF, sum = 0
6303 11:57:33.914817 2, 0xFFFF, sum = 0
6304 11:57:33.915281 3, 0xFFFF, sum = 0
6305 11:57:33.918051 4, 0xFFFF, sum = 0
6306 11:57:33.918514 5, 0xFFFF, sum = 0
6307 11:57:33.921634 6, 0xFFFF, sum = 0
6308 11:57:33.922201 7, 0xFFFF, sum = 0
6309 11:57:33.924955 8, 0xFFFF, sum = 0
6310 11:57:33.925502 9, 0xFFFF, sum = 0
6311 11:57:33.928352 10, 0xFFFF, sum = 0
6312 11:57:33.929026 11, 0xFFFF, sum = 0
6313 11:57:33.931902 12, 0x0, sum = 1
6314 11:57:33.932463 13, 0x0, sum = 2
6315 11:57:33.934745 14, 0x0, sum = 3
6316 11:57:33.935206 15, 0x0, sum = 4
6317 11:57:33.938263 best_step = 13
6318 11:57:33.938807
6319 11:57:33.939337 ==
6320 11:57:33.941768 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 11:57:33.944851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6322 11:57:33.945317 ==
6323 11:57:33.948263 RX Vref Scan: 0
6324 11:57:33.948844
6325 11:57:33.949211 RX Vref 0 -> 0, step: 1
6326 11:57:33.949552
6327 11:57:33.951415 RX Delay -359 -> 252, step: 8
6328 11:57:33.958960 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6329 11:57:33.962537 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6330 11:57:33.966146 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6331 11:57:33.969230 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6332 11:57:33.975709 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6333 11:57:33.978914 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6334 11:57:33.983033 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6335 11:57:33.985852 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6336 11:57:33.992214 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6337 11:57:33.995744 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6338 11:57:33.999390 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6339 11:57:34.006154 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6340 11:57:34.008915 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6341 11:57:34.012498 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6342 11:57:34.015848 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6343 11:57:34.022404 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6344 11:57:34.022954 ==
6345 11:57:34.026212 Dram Type= 6, Freq= 0, CH_0, rank 1
6346 11:57:34.028987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6347 11:57:34.029539 ==
6348 11:57:34.029901 DQS Delay:
6349 11:57:34.032024 DQS0 = 52, DQS1 = 64
6350 11:57:34.032479 DQM Delay:
6351 11:57:34.035572 DQM0 = 10, DQM1 = 13
6352 11:57:34.036122 DQ Delay:
6353 11:57:34.038988 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6354 11:57:34.041887 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6355 11:57:34.045223 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6356 11:57:34.048626 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6357 11:57:34.049185
6358 11:57:34.049554
6359 11:57:34.055553 [DQSOSCAuto] RK1, (LSB)MR18= 0xc3c3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6360 11:57:34.058543 CH0 RK1: MR19=C0C, MR18=C3C3
6361 11:57:34.065131 CH0_RK1: MR19=0xC0C, MR18=0xC3C3, DQSOSC=385, MR23=63, INC=398, DEC=265
6362 11:57:34.068657 [RxdqsGatingPostProcess] freq 400
6363 11:57:34.075252 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6364 11:57:34.078548 Pre-setting of DQS Precalculation
6365 11:57:34.081851 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6366 11:57:34.082403 ==
6367 11:57:34.085135 Dram Type= 6, Freq= 0, CH_1, rank 0
6368 11:57:34.088393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6369 11:57:34.088997 ==
6370 11:57:34.094882 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6371 11:57:34.101812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6372 11:57:34.104933 [CA 0] Center 36 (8~64) winsize 57
6373 11:57:34.108277 [CA 1] Center 36 (8~64) winsize 57
6374 11:57:34.111840 [CA 2] Center 36 (8~64) winsize 57
6375 11:57:34.115195 [CA 3] Center 36 (8~64) winsize 57
6376 11:57:34.118355 [CA 4] Center 36 (8~64) winsize 57
6377 11:57:34.118909 [CA 5] Center 36 (8~64) winsize 57
6378 11:57:34.121355
6379 11:57:34.124809 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6380 11:57:34.125365
6381 11:57:34.128082 [CATrainingPosCal] consider 1 rank data
6382 11:57:34.131517 u2DelayCellTimex100 = 270/100 ps
6383 11:57:34.135125 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 11:57:34.138108 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 11:57:34.141182 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 11:57:34.144989 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 11:57:34.148071 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 11:57:34.151064 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 11:57:34.151524
6390 11:57:34.154742 CA PerBit enable=1, Macro0, CA PI delay=36
6391 11:57:34.155303
6392 11:57:34.157777 [CBTSetCACLKResult] CA Dly = 36
6393 11:57:34.161076 CS Dly: 1 (0~32)
6394 11:57:34.161550 ==
6395 11:57:34.164295 Dram Type= 6, Freq= 0, CH_1, rank 1
6396 11:57:34.167852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6397 11:57:34.168418 ==
6398 11:57:34.174437 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6399 11:57:34.181367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6400 11:57:34.184656 [CA 0] Center 36 (8~64) winsize 57
6401 11:57:34.185215 [CA 1] Center 36 (8~64) winsize 57
6402 11:57:34.188056 [CA 2] Center 36 (8~64) winsize 57
6403 11:57:34.191146 [CA 3] Center 36 (8~64) winsize 57
6404 11:57:34.194330 [CA 4] Center 36 (8~64) winsize 57
6405 11:57:34.197537 [CA 5] Center 36 (8~64) winsize 57
6406 11:57:34.197998
6407 11:57:34.200918 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6408 11:57:34.201443
6409 11:57:34.207852 [CATrainingPosCal] consider 2 rank data
6410 11:57:34.208410 u2DelayCellTimex100 = 270/100 ps
6411 11:57:34.214587 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 11:57:34.217566 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 11:57:34.220599 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 11:57:34.224304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 11:57:34.227364 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 11:57:34.231137 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 11:57:34.231696
6418 11:57:34.234339 CA PerBit enable=1, Macro0, CA PI delay=36
6419 11:57:34.234891
6420 11:57:34.237411 [CBTSetCACLKResult] CA Dly = 36
6421 11:57:34.241134 CS Dly: 1 (0~32)
6422 11:57:34.241683
6423 11:57:34.244199 ----->DramcWriteLeveling(PI) begin...
6424 11:57:34.244845 ==
6425 11:57:34.247676 Dram Type= 6, Freq= 0, CH_1, rank 0
6426 11:57:34.250800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6427 11:57:34.251354 ==
6428 11:57:34.254203 Write leveling (Byte 0): 32 => 0
6429 11:57:34.257672 Write leveling (Byte 1): 32 => 0
6430 11:57:34.260733 DramcWriteLeveling(PI) end<-----
6431 11:57:34.261194
6432 11:57:34.261563 ==
6433 11:57:34.264200 Dram Type= 6, Freq= 0, CH_1, rank 0
6434 11:57:34.267702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6435 11:57:34.268250 ==
6436 11:57:34.270771 [Gating] SW mode calibration
6437 11:57:34.277673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6438 11:57:34.283909 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6439 11:57:34.287078 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 11:57:34.290237 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 11:57:34.297062 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 11:57:34.300417 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 11:57:34.303829 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 11:57:34.310437 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 11:57:34.313885 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 11:57:34.317077 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6447 11:57:34.320325 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 11:57:34.323924 Total UI for P1: 0, mck2ui 16
6449 11:57:34.327579 best dqsien dly found for B0: ( 0, 10, 16)
6450 11:57:34.330638 Total UI for P1: 0, mck2ui 16
6451 11:57:34.333641 best dqsien dly found for B1: ( 0, 10, 16)
6452 11:57:34.336926 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6453 11:57:34.343681 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6454 11:57:34.344236
6455 11:57:34.346961 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6456 11:57:34.350412 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6457 11:57:34.353348 [Gating] SW calibration Done
6458 11:57:34.353802 ==
6459 11:57:34.357208 Dram Type= 6, Freq= 0, CH_1, rank 0
6460 11:57:34.360765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6461 11:57:34.361339 ==
6462 11:57:34.363512 RX Vref Scan: 0
6463 11:57:34.363958
6464 11:57:34.364314 RX Vref 0 -> 0, step: 1
6465 11:57:34.364702
6466 11:57:34.367240 RX Delay -410 -> 252, step: 16
6467 11:57:34.370228 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6468 11:57:34.376916 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6469 11:57:34.379990 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6470 11:57:34.383538 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6471 11:57:34.386989 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6472 11:57:34.393527 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6473 11:57:34.397078 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6474 11:57:34.399709 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6475 11:57:34.403229 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6476 11:57:34.410122 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6477 11:57:34.413183 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6478 11:57:34.416879 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6479 11:57:34.423476 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6480 11:57:34.426398 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6481 11:57:34.429981 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6482 11:57:34.433184 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6483 11:57:34.433740 ==
6484 11:57:34.436550 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 11:57:34.443537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 11:57:34.444093 ==
6487 11:57:34.444456 DQS Delay:
6488 11:57:34.446657 DQS0 = 43, DQS1 = 59
6489 11:57:34.447215 DQM Delay:
6490 11:57:34.449951 DQM0 = 6, DQM1 = 15
6491 11:57:34.450519 DQ Delay:
6492 11:57:34.453051 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6493 11:57:34.456457 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6494 11:57:34.457037 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6495 11:57:34.459683 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6496 11:57:34.463013
6497 11:57:34.463464
6498 11:57:34.463839 ==
6499 11:57:34.466944 Dram Type= 6, Freq= 0, CH_1, rank 0
6500 11:57:34.469752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6501 11:57:34.470307 ==
6502 11:57:34.470667
6503 11:57:34.470999
6504 11:57:34.473429 TX Vref Scan disable
6505 11:57:34.473976 == TX Byte 0 ==
6506 11:57:34.476501 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 11:57:34.483280 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 11:57:34.483833 == TX Byte 1 ==
6509 11:57:34.486469 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 11:57:34.493082 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 11:57:34.493839 ==
6512 11:57:34.496481 Dram Type= 6, Freq= 0, CH_1, rank 0
6513 11:57:34.499842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6514 11:57:34.500431 ==
6515 11:57:34.500975
6516 11:57:34.501438
6517 11:57:34.502901 TX Vref Scan disable
6518 11:57:34.503379 == TX Byte 0 ==
6519 11:57:34.509767 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 11:57:34.512931 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 11:57:34.513410 == TX Byte 1 ==
6522 11:57:34.519580 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6523 11:57:34.522846 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6524 11:57:34.523425
6525 11:57:34.523918 [DATLAT]
6526 11:57:34.526197 Freq=400, CH1 RK0
6527 11:57:34.526778
6528 11:57:34.527270 DATLAT Default: 0xf
6529 11:57:34.529337 0, 0xFFFF, sum = 0
6530 11:57:34.529836 1, 0xFFFF, sum = 0
6531 11:57:34.532904 2, 0xFFFF, sum = 0
6532 11:57:34.533486 3, 0xFFFF, sum = 0
6533 11:57:34.536229 4, 0xFFFF, sum = 0
6534 11:57:34.536759 5, 0xFFFF, sum = 0
6535 11:57:34.539656 6, 0xFFFF, sum = 0
6536 11:57:34.540237 7, 0xFFFF, sum = 0
6537 11:57:34.543200 8, 0xFFFF, sum = 0
6538 11:57:34.546071 9, 0xFFFF, sum = 0
6539 11:57:34.546573 10, 0xFFFF, sum = 0
6540 11:57:34.549401 11, 0xFFFF, sum = 0
6541 11:57:34.549986 12, 0x0, sum = 1
6542 11:57:34.552606 13, 0x0, sum = 2
6543 11:57:34.553063 14, 0x0, sum = 3
6544 11:57:34.553423 15, 0x0, sum = 4
6545 11:57:34.556001 best_step = 13
6546 11:57:34.556451
6547 11:57:34.556850 ==
6548 11:57:34.559336 Dram Type= 6, Freq= 0, CH_1, rank 0
6549 11:57:34.562666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6550 11:57:34.563119 ==
6551 11:57:34.566395 RX Vref Scan: 1
6552 11:57:34.566942
6553 11:57:34.567302 RX Vref 0 -> 0, step: 1
6554 11:57:34.569222
6555 11:57:34.569669 RX Delay -359 -> 252, step: 8
6556 11:57:34.570027
6557 11:57:34.572777 Set Vref, RX VrefLevel [Byte0]: 56
6558 11:57:34.576252 [Byte1]: 54
6559 11:57:34.581182
6560 11:57:34.581727 Final RX Vref Byte 0 = 56 to rank0
6561 11:57:34.584405 Final RX Vref Byte 1 = 54 to rank0
6562 11:57:34.587964 Final RX Vref Byte 0 = 56 to rank1
6563 11:57:34.591255 Final RX Vref Byte 1 = 54 to rank1==
6564 11:57:34.594275 Dram Type= 6, Freq= 0, CH_1, rank 0
6565 11:57:34.600810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6566 11:57:34.601350 ==
6567 11:57:34.601712 DQS Delay:
6568 11:57:34.604481 DQS0 = 48, DQS1 = 64
6569 11:57:34.604969 DQM Delay:
6570 11:57:34.605328 DQM0 = 7, DQM1 = 16
6571 11:57:34.607304 DQ Delay:
6572 11:57:34.610794 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6573 11:57:34.611343 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6574 11:57:34.614471 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6575 11:57:34.617355 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6576 11:57:34.617806
6577 11:57:34.618160
6578 11:57:34.627381 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e1, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6579 11:57:34.630754 CH1 RK0: MR19=C0C, MR18=E1E1
6580 11:57:34.637642 CH1_RK0: MR19=0xC0C, MR18=0xE1E1, DQSOSC=382, MR23=63, INC=404, DEC=269
6581 11:57:34.638196 ==
6582 11:57:34.640995 Dram Type= 6, Freq= 0, CH_1, rank 1
6583 11:57:34.644308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6584 11:57:34.644893 ==
6585 11:57:34.647558 [Gating] SW mode calibration
6586 11:57:34.654121 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6587 11:57:34.657254 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6588 11:57:34.664199 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6589 11:57:34.667980 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6590 11:57:34.670692 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6591 11:57:34.677360 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6592 11:57:34.680623 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6593 11:57:34.684284 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6594 11:57:34.690555 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6595 11:57:34.693827 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6596 11:57:34.697072 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6597 11:57:34.700728 Total UI for P1: 0, mck2ui 16
6598 11:57:34.703720 best dqsien dly found for B0: ( 0, 10, 16)
6599 11:57:34.707071 Total UI for P1: 0, mck2ui 16
6600 11:57:34.710453 best dqsien dly found for B1: ( 0, 10, 16)
6601 11:57:34.713577 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6602 11:57:34.717152 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6603 11:57:34.720149
6604 11:57:34.723835 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6605 11:57:34.727174 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6606 11:57:34.730433 [Gating] SW calibration Done
6607 11:57:34.731017 ==
6608 11:57:34.733646 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 11:57:34.736794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6610 11:57:34.737258 ==
6611 11:57:34.740395 RX Vref Scan: 0
6612 11:57:34.741003
6613 11:57:34.741374 RX Vref 0 -> 0, step: 1
6614 11:57:34.741717
6615 11:57:34.743618 RX Delay -410 -> 252, step: 16
6616 11:57:34.747341 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6617 11:57:34.753624 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6618 11:57:34.756950 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6619 11:57:34.760158 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6620 11:57:34.763101 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6621 11:57:34.769692 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6622 11:57:34.773452 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6623 11:57:34.776629 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6624 11:57:34.779966 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6625 11:57:34.786659 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6626 11:57:34.789813 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6627 11:57:34.792990 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6628 11:57:34.800129 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6629 11:57:34.802800 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6630 11:57:34.806597 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6631 11:57:34.809616 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6632 11:57:34.810077 ==
6633 11:57:34.812854 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 11:57:34.819697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 11:57:34.820257 ==
6636 11:57:34.820673 DQS Delay:
6637 11:57:34.823358 DQS0 = 43, DQS1 = 59
6638 11:57:34.823932 DQM Delay:
6639 11:57:34.826687 DQM0 = 9, DQM1 = 17
6640 11:57:34.827270 DQ Delay:
6641 11:57:34.829741 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6642 11:57:34.833229 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6643 11:57:34.833682 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6644 11:57:34.839831 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6645 11:57:34.840376
6646 11:57:34.840782
6647 11:57:34.841122 ==
6648 11:57:34.842929 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 11:57:34.846025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6650 11:57:34.846537 ==
6651 11:57:34.846924
6652 11:57:34.847259
6653 11:57:34.849247 TX Vref Scan disable
6654 11:57:34.849878 == TX Byte 0 ==
6655 11:57:34.852783 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6656 11:57:34.859568 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6657 11:57:34.860267 == TX Byte 1 ==
6658 11:57:34.862490 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6659 11:57:34.869185 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6660 11:57:34.869640 ==
6661 11:57:34.872758 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 11:57:34.876190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6663 11:57:34.876765 ==
6664 11:57:34.877133
6665 11:57:34.877466
6666 11:57:34.879021 TX Vref Scan disable
6667 11:57:34.879474 == TX Byte 0 ==
6668 11:57:34.885597 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6669 11:57:34.889034 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6670 11:57:34.889508 == TX Byte 1 ==
6671 11:57:34.892570 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6672 11:57:34.899133 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6673 11:57:34.899680
6674 11:57:34.900051 [DATLAT]
6675 11:57:34.902643 Freq=400, CH1 RK1
6676 11:57:34.903222
6677 11:57:34.903596 DATLAT Default: 0xd
6678 11:57:34.905590 0, 0xFFFF, sum = 0
6679 11:57:34.906155 1, 0xFFFF, sum = 0
6680 11:57:34.908857 2, 0xFFFF, sum = 0
6681 11:57:34.909317 3, 0xFFFF, sum = 0
6682 11:57:34.912136 4, 0xFFFF, sum = 0
6683 11:57:34.912638 5, 0xFFFF, sum = 0
6684 11:57:34.915728 6, 0xFFFF, sum = 0
6685 11:57:34.916291 7, 0xFFFF, sum = 0
6686 11:57:34.918946 8, 0xFFFF, sum = 0
6687 11:57:34.919514 9, 0xFFFF, sum = 0
6688 11:57:34.922156 10, 0xFFFF, sum = 0
6689 11:57:34.922621 11, 0xFFFF, sum = 0
6690 11:57:34.925839 12, 0x0, sum = 1
6691 11:57:34.926410 13, 0x0, sum = 2
6692 11:57:34.928875 14, 0x0, sum = 3
6693 11:57:34.929337 15, 0x0, sum = 4
6694 11:57:34.932616 best_step = 13
6695 11:57:34.933171
6696 11:57:34.933537 ==
6697 11:57:34.935893 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 11:57:34.939423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6699 11:57:34.939990 ==
6700 11:57:34.942042 RX Vref Scan: 0
6701 11:57:34.942498
6702 11:57:34.942858 RX Vref 0 -> 0, step: 1
6703 11:57:34.943259
6704 11:57:34.945631 RX Delay -359 -> 252, step: 8
6705 11:57:34.953653 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6706 11:57:34.957085 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6707 11:57:34.959974 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6708 11:57:34.967200 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6709 11:57:34.969696 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6710 11:57:34.973293 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6711 11:57:34.976636 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6712 11:57:34.980295 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6713 11:57:34.986803 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6714 11:57:34.989694 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6715 11:57:34.993359 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6716 11:57:35.000062 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6717 11:57:35.003189 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
6718 11:57:35.006476 iDelay=217, Bit 13, Center -36 (-287 ~ 216) 504
6719 11:57:35.010044 iDelay=217, Bit 14, Center -40 (-295 ~ 216) 512
6720 11:57:35.016479 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6721 11:57:35.016996 ==
6722 11:57:35.020056 Dram Type= 6, Freq= 0, CH_1, rank 1
6723 11:57:35.023797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6724 11:57:35.024344 ==
6725 11:57:35.024790 DQS Delay:
6726 11:57:35.026695 DQS0 = 48, DQS1 = 60
6727 11:57:35.027241 DQM Delay:
6728 11:57:35.029881 DQM0 = 9, DQM1 = 13
6729 11:57:35.030427 DQ Delay:
6730 11:57:35.033010 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6731 11:57:35.036873 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6732 11:57:35.039940 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6733 11:57:35.043227 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6734 11:57:35.043773
6735 11:57:35.044137
6736 11:57:35.049855 [DQSOSCAuto] RK1, (LSB)MR18= 0xafaf, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6737 11:57:35.053044 CH1 RK1: MR19=C0C, MR18=AFAF
6738 11:57:35.059315 CH1_RK1: MR19=0xC0C, MR18=0xAFAF, DQSOSC=388, MR23=63, INC=392, DEC=261
6739 11:57:35.062765 [RxdqsGatingPostProcess] freq 400
6740 11:57:35.069485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6741 11:57:35.070038 Pre-setting of DQS Precalculation
6742 11:57:35.076142 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6743 11:57:35.082858 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6744 11:57:35.089582 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6745 11:57:35.090129
6746 11:57:35.090492
6747 11:57:35.092697 [Calibration Summary] 800 Mbps
6748 11:57:35.095891 CH 0, Rank 0
6749 11:57:35.096681 SW Impedance : PASS
6750 11:57:35.099334 DUTY Scan : NO K
6751 11:57:35.102767 ZQ Calibration : PASS
6752 11:57:35.103340 Jitter Meter : NO K
6753 11:57:35.105905 CBT Training : PASS
6754 11:57:35.109201 Write leveling : PASS
6755 11:57:35.109655 RX DQS gating : PASS
6756 11:57:35.112216 RX DQ/DQS(RDDQC) : PASS
6757 11:57:35.112722 TX DQ/DQS : PASS
6758 11:57:35.115788 RX DATLAT : PASS
6759 11:57:35.118955 RX DQ/DQS(Engine): PASS
6760 11:57:35.119503 TX OE : NO K
6761 11:57:35.122016 All Pass.
6762 11:57:35.122566
6763 11:57:35.122933 CH 0, Rank 1
6764 11:57:35.125788 SW Impedance : PASS
6765 11:57:35.126334 DUTY Scan : NO K
6766 11:57:35.128728 ZQ Calibration : PASS
6767 11:57:35.132476 Jitter Meter : NO K
6768 11:57:35.133076 CBT Training : PASS
6769 11:57:35.135952 Write leveling : NO K
6770 11:57:35.138721 RX DQS gating : PASS
6771 11:57:35.139266 RX DQ/DQS(RDDQC) : PASS
6772 11:57:35.142160 TX DQ/DQS : PASS
6773 11:57:35.145374 RX DATLAT : PASS
6774 11:57:35.145831 RX DQ/DQS(Engine): PASS
6775 11:57:35.148887 TX OE : NO K
6776 11:57:35.149436 All Pass.
6777 11:57:35.149800
6778 11:57:35.152495 CH 1, Rank 0
6779 11:57:35.153094 SW Impedance : PASS
6780 11:57:35.155752 DUTY Scan : NO K
6781 11:57:35.158612 ZQ Calibration : PASS
6782 11:57:35.159070 Jitter Meter : NO K
6783 11:57:35.161827 CBT Training : PASS
6784 11:57:35.165452 Write leveling : PASS
6785 11:57:35.165909 RX DQS gating : PASS
6786 11:57:35.169052 RX DQ/DQS(RDDQC) : PASS
6787 11:57:35.169604 TX DQ/DQS : PASS
6788 11:57:35.172278 RX DATLAT : PASS
6789 11:57:35.175361 RX DQ/DQS(Engine): PASS
6790 11:57:35.175912 TX OE : NO K
6791 11:57:35.178400 All Pass.
6792 11:57:35.178945
6793 11:57:35.179305 CH 1, Rank 1
6794 11:57:35.181858 SW Impedance : PASS
6795 11:57:35.182405 DUTY Scan : NO K
6796 11:57:35.185074 ZQ Calibration : PASS
6797 11:57:35.188472 Jitter Meter : NO K
6798 11:57:35.189073 CBT Training : PASS
6799 11:57:35.191719 Write leveling : NO K
6800 11:57:35.195196 RX DQS gating : PASS
6801 11:57:35.195750 RX DQ/DQS(RDDQC) : PASS
6802 11:57:35.198307 TX DQ/DQS : PASS
6803 11:57:35.201541 RX DATLAT : PASS
6804 11:57:35.201999 RX DQ/DQS(Engine): PASS
6805 11:57:35.205219 TX OE : NO K
6806 11:57:35.205778 All Pass.
6807 11:57:35.206153
6808 11:57:35.208552 DramC Write-DBI off
6809 11:57:35.211575 PER_BANK_REFRESH: Hybrid Mode
6810 11:57:35.212131 TX_TRACKING: ON
6811 11:57:35.221424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6812 11:57:35.224586 [FAST_K] Save calibration result to emmc
6813 11:57:35.228206 dramc_set_vcore_voltage set vcore to 725000
6814 11:57:35.231452 Read voltage for 1600, 0
6815 11:57:35.232008 Vio18 = 0
6816 11:57:35.232376 Vcore = 725000
6817 11:57:35.235018 Vdram = 0
6818 11:57:35.235584 Vddq = 0
6819 11:57:35.235953 Vmddr = 0
6820 11:57:35.241394 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6821 11:57:35.244488 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6822 11:57:35.247873 MEM_TYPE=3, freq_sel=13
6823 11:57:35.251170 sv_algorithm_assistance_LP4_3733
6824 11:57:35.254515 ============ PULL DRAM RESETB DOWN ============
6825 11:57:35.261260 ========== PULL DRAM RESETB DOWN end =========
6826 11:57:35.264573 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6827 11:57:35.267444 ===================================
6828 11:57:35.271283 LPDDR4 DRAM CONFIGURATION
6829 11:57:35.274401 ===================================
6830 11:57:35.274865 EX_ROW_EN[0] = 0x0
6831 11:57:35.277762 EX_ROW_EN[1] = 0x0
6832 11:57:35.278321 LP4Y_EN = 0x0
6833 11:57:35.281470 WORK_FSP = 0x1
6834 11:57:35.282027 WL = 0x5
6835 11:57:35.284279 RL = 0x5
6836 11:57:35.284763 BL = 0x2
6837 11:57:35.287890 RPST = 0x0
6838 11:57:35.288344 RD_PRE = 0x0
6839 11:57:35.291159 WR_PRE = 0x1
6840 11:57:35.294496 WR_PST = 0x1
6841 11:57:35.295071 DBI_WR = 0x0
6842 11:57:35.297623 DBI_RD = 0x0
6843 11:57:35.298180 OTF = 0x1
6844 11:57:35.300723 ===================================
6845 11:57:35.304261 ===================================
6846 11:57:35.304882 ANA top config
6847 11:57:35.307478 ===================================
6848 11:57:35.310811 DLL_ASYNC_EN = 0
6849 11:57:35.313842 ALL_SLAVE_EN = 0
6850 11:57:35.317023 NEW_RANK_MODE = 1
6851 11:57:35.320585 DLL_IDLE_MODE = 1
6852 11:57:35.321043 LP45_APHY_COMB_EN = 1
6853 11:57:35.323830 TX_ODT_DIS = 0
6854 11:57:35.327256 NEW_8X_MODE = 1
6855 11:57:35.330423 ===================================
6856 11:57:35.333824 ===================================
6857 11:57:35.337446 data_rate = 3200
6858 11:57:35.340307 CKR = 1
6859 11:57:35.343648 DQ_P2S_RATIO = 8
6860 11:57:35.347205 ===================================
6861 11:57:35.347744 CA_P2S_RATIO = 8
6862 11:57:35.350431 DQ_CA_OPEN = 0
6863 11:57:35.353750 DQ_SEMI_OPEN = 0
6864 11:57:35.356889 CA_SEMI_OPEN = 0
6865 11:57:35.360252 CA_FULL_RATE = 0
6866 11:57:35.363484 DQ_CKDIV4_EN = 0
6867 11:57:35.364035 CA_CKDIV4_EN = 0
6868 11:57:35.366957 CA_PREDIV_EN = 0
6869 11:57:35.369901 PH8_DLY = 12
6870 11:57:35.373211 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6871 11:57:35.376814 DQ_AAMCK_DIV = 4
6872 11:57:35.380311 CA_AAMCK_DIV = 4
6873 11:57:35.380900 CA_ADMCK_DIV = 4
6874 11:57:35.383598 DQ_TRACK_CA_EN = 0
6875 11:57:35.386759 CA_PICK = 1600
6876 11:57:35.390194 CA_MCKIO = 1600
6877 11:57:35.393584 MCKIO_SEMI = 0
6878 11:57:35.396621 PLL_FREQ = 3068
6879 11:57:35.399819 DQ_UI_PI_RATIO = 32
6880 11:57:35.400277 CA_UI_PI_RATIO = 0
6881 11:57:35.403078 ===================================
6882 11:57:35.406992 ===================================
6883 11:57:35.409518 memory_type:LPDDR4
6884 11:57:35.412725 GP_NUM : 10
6885 11:57:35.416134 SRAM_EN : 1
6886 11:57:35.416640 MD32_EN : 0
6887 11:57:35.419407 ===================================
6888 11:57:35.422937 [ANA_INIT] >>>>>>>>>>>>>>
6889 11:57:35.426324 <<<<<< [CONFIGURE PHASE]: ANA_TX
6890 11:57:35.429588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6891 11:57:35.432680 ===================================
6892 11:57:35.435943 data_rate = 3200,PCW = 0X7600
6893 11:57:35.439685 ===================================
6894 11:57:35.442871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6895 11:57:35.445965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6896 11:57:35.452434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6897 11:57:35.455622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6898 11:57:35.459106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6899 11:57:35.462714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6900 11:57:35.465846 [ANA_INIT] flow start
6901 11:57:35.469068 [ANA_INIT] PLL >>>>>>>>
6902 11:57:35.469521 [ANA_INIT] PLL <<<<<<<<
6903 11:57:35.472847 [ANA_INIT] MIDPI >>>>>>>>
6904 11:57:35.475579 [ANA_INIT] MIDPI <<<<<<<<
6905 11:57:35.479164 [ANA_INIT] DLL >>>>>>>>
6906 11:57:35.479714 [ANA_INIT] DLL <<<<<<<<
6907 11:57:35.482347 [ANA_INIT] flow end
6908 11:57:35.485370 ============ LP4 DIFF to SE enter ============
6909 11:57:35.489311 ============ LP4 DIFF to SE exit ============
6910 11:57:35.492071 [ANA_INIT] <<<<<<<<<<<<<
6911 11:57:35.495916 [Flow] Enable top DCM control >>>>>
6912 11:57:35.498771 [Flow] Enable top DCM control <<<<<
6913 11:57:35.502662 Enable DLL master slave shuffle
6914 11:57:35.508543 ==============================================================
6915 11:57:35.509006 Gating Mode config
6916 11:57:35.515799 ==============================================================
6917 11:57:35.516363 Config description:
6918 11:57:35.525219 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6919 11:57:35.532010 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6920 11:57:35.538510 SELPH_MODE 0: By rank 1: By Phase
6921 11:57:35.542122 ==============================================================
6922 11:57:35.545020 GAT_TRACK_EN = 1
6923 11:57:35.548455 RX_GATING_MODE = 2
6924 11:57:35.551784 RX_GATING_TRACK_MODE = 2
6925 11:57:35.555019 SELPH_MODE = 1
6926 11:57:35.558597 PICG_EARLY_EN = 1
6927 11:57:35.561448 VALID_LAT_VALUE = 1
6928 11:57:35.568251 ==============================================================
6929 11:57:35.571593 Enter into Gating configuration >>>>
6930 11:57:35.574809 Exit from Gating configuration <<<<
6931 11:57:35.578059 Enter into DVFS_PRE_config >>>>>
6932 11:57:35.588218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6933 11:57:35.591460 Exit from DVFS_PRE_config <<<<<
6934 11:57:35.594523 Enter into PICG configuration >>>>
6935 11:57:35.598225 Exit from PICG configuration <<<<
6936 11:57:35.601246 [RX_INPUT] configuration >>>>>
6937 11:57:35.601711 [RX_INPUT] configuration <<<<<
6938 11:57:35.607893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6939 11:57:35.615186 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6940 11:57:35.617806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6941 11:57:35.624474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6942 11:57:35.630986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6943 11:57:35.637702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6944 11:57:35.640641 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6945 11:57:35.644128 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6946 11:57:35.650747 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6947 11:57:35.654313 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6948 11:57:35.657431 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6949 11:57:35.664287 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6950 11:57:35.667670 ===================================
6951 11:57:35.668133 LPDDR4 DRAM CONFIGURATION
6952 11:57:35.670829 ===================================
6953 11:57:35.673965 EX_ROW_EN[0] = 0x0
6954 11:57:35.674518 EX_ROW_EN[1] = 0x0
6955 11:57:35.677302 LP4Y_EN = 0x0
6956 11:57:35.680864 WORK_FSP = 0x1
6957 11:57:35.681431 WL = 0x5
6958 11:57:35.683980 RL = 0x5
6959 11:57:35.684497 BL = 0x2
6960 11:57:35.687278 RPST = 0x0
6961 11:57:35.687837 RD_PRE = 0x0
6962 11:57:35.690537 WR_PRE = 0x1
6963 11:57:35.691086 WR_PST = 0x1
6964 11:57:35.694240 DBI_WR = 0x0
6965 11:57:35.694783 DBI_RD = 0x0
6966 11:57:35.697394 OTF = 0x1
6967 11:57:35.700221 ===================================
6968 11:57:35.703746 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6969 11:57:35.707123 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6970 11:57:35.713568 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6971 11:57:35.717245 ===================================
6972 11:57:35.717794 LPDDR4 DRAM CONFIGURATION
6973 11:57:35.720062 ===================================
6974 11:57:35.723434 EX_ROW_EN[0] = 0x10
6975 11:57:35.723987 EX_ROW_EN[1] = 0x0
6976 11:57:35.727102 LP4Y_EN = 0x0
6977 11:57:35.730103 WORK_FSP = 0x1
6978 11:57:35.730651 WL = 0x5
6979 11:57:35.733288 RL = 0x5
6980 11:57:35.733745 BL = 0x2
6981 11:57:35.736915 RPST = 0x0
6982 11:57:35.737368 RD_PRE = 0x0
6983 11:57:35.740047 WR_PRE = 0x1
6984 11:57:35.740499 WR_PST = 0x1
6985 11:57:35.743709 DBI_WR = 0x0
6986 11:57:35.744255 DBI_RD = 0x0
6987 11:57:35.746714 OTF = 0x1
6988 11:57:35.749866 ===================================
6989 11:57:35.756917 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6990 11:57:35.757481 ==
6991 11:57:35.760269 Dram Type= 6, Freq= 0, CH_0, rank 0
6992 11:57:35.763157 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6993 11:57:35.763630 ==
6994 11:57:35.766667 [Duty_Offset_Calibration]
6995 11:57:35.767137 B0:0 B1:2 CA:1
6996 11:57:35.767502
6997 11:57:35.770142 [DutyScan_Calibration_Flow] k_type=0
6998 11:57:35.780243
6999 11:57:35.780850 ==CLK 0==
7000 11:57:35.783662 Final CLK duty delay cell = 0
7001 11:57:35.786642 [0] MAX Duty = 5187%(X100), DQS PI = 24
7002 11:57:35.790104 [0] MIN Duty = 4938%(X100), DQS PI = 54
7003 11:57:35.793148 [0] AVG Duty = 5062%(X100)
7004 11:57:35.793608
7005 11:57:35.796681 CH0 CLK Duty spec in!! Max-Min= 249%
7006 11:57:35.799809 [DutyScan_Calibration_Flow] ====Done====
7007 11:57:35.800414
7008 11:57:35.803209 [DutyScan_Calibration_Flow] k_type=1
7009 11:57:35.820473
7010 11:57:35.821095 ==DQS 0 ==
7011 11:57:35.823577 Final DQS duty delay cell = 0
7012 11:57:35.826822 [0] MAX Duty = 5156%(X100), DQS PI = 34
7013 11:57:35.829939 [0] MIN Duty = 5031%(X100), DQS PI = 8
7014 11:57:35.830401 [0] AVG Duty = 5093%(X100)
7015 11:57:35.833508
7016 11:57:35.834068 ==DQS 1 ==
7017 11:57:35.836499 Final DQS duty delay cell = 0
7018 11:57:35.840315 [0] MAX Duty = 5031%(X100), DQS PI = 2
7019 11:57:35.843717 [0] MIN Duty = 4876%(X100), DQS PI = 16
7020 11:57:35.847264 [0] AVG Duty = 4953%(X100)
7021 11:57:35.847820
7022 11:57:35.850053 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7023 11:57:35.850511
7024 11:57:35.853487 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7025 11:57:35.856783 [DutyScan_Calibration_Flow] ====Done====
7026 11:57:35.857337
7027 11:57:35.860217 [DutyScan_Calibration_Flow] k_type=3
7028 11:57:35.877496
7029 11:57:35.878054 ==DQM 0 ==
7030 11:57:35.880589 Final DQM duty delay cell = 0
7031 11:57:35.884058 [0] MAX Duty = 5187%(X100), DQS PI = 22
7032 11:57:35.887264 [0] MIN Duty = 4907%(X100), DQS PI = 42
7033 11:57:35.890919 [0] AVG Duty = 5047%(X100)
7034 11:57:35.891477
7035 11:57:35.891863 ==DQM 1 ==
7036 11:57:35.894249 Final DQM duty delay cell = 0
7037 11:57:35.897055 [0] MAX Duty = 5031%(X100), DQS PI = 50
7038 11:57:35.900724 [0] MIN Duty = 4782%(X100), DQS PI = 14
7039 11:57:35.904031 [0] AVG Duty = 4906%(X100)
7040 11:57:35.904495
7041 11:57:35.906724 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7042 11:57:35.907177
7043 11:57:35.910437 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7044 11:57:35.913463 [DutyScan_Calibration_Flow] ====Done====
7045 11:57:35.913925
7046 11:57:35.916722 [DutyScan_Calibration_Flow] k_type=2
7047 11:57:35.933607
7048 11:57:35.934156 ==DQ 0 ==
7049 11:57:35.937804 Final DQ duty delay cell = 0
7050 11:57:35.940248 [0] MAX Duty = 5218%(X100), DQS PI = 18
7051 11:57:35.943436 [0] MIN Duty = 4938%(X100), DQS PI = 56
7052 11:57:35.943892 [0] AVG Duty = 5078%(X100)
7053 11:57:35.946949
7054 11:57:35.947503 ==DQ 1 ==
7055 11:57:35.950417 Final DQ duty delay cell = -4
7056 11:57:35.953770 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7057 11:57:35.957049 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7058 11:57:35.960296 [-4] AVG Duty = 4953%(X100)
7059 11:57:35.960891
7060 11:57:35.963395 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7061 11:57:35.963852
7062 11:57:35.966946 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7063 11:57:35.970023 [DutyScan_Calibration_Flow] ====Done====
7064 11:57:35.970494 ==
7065 11:57:35.973228 Dram Type= 6, Freq= 0, CH_1, rank 0
7066 11:57:35.976747 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7067 11:57:35.977300 ==
7068 11:57:35.980323 [Duty_Offset_Calibration]
7069 11:57:35.980930 B0:0 B1:4 CA:-5
7070 11:57:35.981296
7071 11:57:35.983279 [DutyScan_Calibration_Flow] k_type=0
7072 11:57:35.994253
7073 11:57:35.994808 ==CLK 0==
7074 11:57:35.997941 Final CLK duty delay cell = 0
7075 11:57:36.001197 [0] MAX Duty = 5156%(X100), DQS PI = 20
7076 11:57:36.004183 [0] MIN Duty = 4906%(X100), DQS PI = 50
7077 11:57:36.007460 [0] AVG Duty = 5031%(X100)
7078 11:57:36.008010
7079 11:57:36.010652 CH1 CLK Duty spec in!! Max-Min= 250%
7080 11:57:36.014267 [DutyScan_Calibration_Flow] ====Done====
7081 11:57:36.014856
7082 11:57:36.017396 [DutyScan_Calibration_Flow] k_type=1
7083 11:57:36.033264
7084 11:57:36.033825 ==DQS 0 ==
7085 11:57:36.036649 Final DQS duty delay cell = 0
7086 11:57:36.039864 [0] MAX Duty = 5187%(X100), DQS PI = 20
7087 11:57:36.043359 [0] MIN Duty = 4876%(X100), DQS PI = 42
7088 11:57:36.046265 [0] AVG Duty = 5031%(X100)
7089 11:57:36.046721
7090 11:57:36.047086 ==DQS 1 ==
7091 11:57:36.049769 Final DQS duty delay cell = -4
7092 11:57:36.053519 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7093 11:57:36.056420 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7094 11:57:36.059862 [-4] AVG Duty = 4937%(X100)
7095 11:57:36.060415
7096 11:57:36.062638 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7097 11:57:36.063097
7098 11:57:36.066186 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7099 11:57:36.069508 [DutyScan_Calibration_Flow] ====Done====
7100 11:57:36.070064
7101 11:57:36.072965 [DutyScan_Calibration_Flow] k_type=3
7102 11:57:36.088884
7103 11:57:36.089453 ==DQM 0 ==
7104 11:57:36.092551 Final DQM duty delay cell = -4
7105 11:57:36.095994 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7106 11:57:36.099204 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7107 11:57:36.102142 [-4] AVG Duty = 4922%(X100)
7108 11:57:36.102618
7109 11:57:36.102987 ==DQM 1 ==
7110 11:57:36.105273 Final DQM duty delay cell = -4
7111 11:57:36.108605 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7112 11:57:36.112015 [-4] MIN Duty = 4876%(X100), DQS PI = 38
7113 11:57:36.115370 [-4] AVG Duty = 4969%(X100)
7114 11:57:36.115923
7115 11:57:36.118924 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7116 11:57:36.119510
7117 11:57:36.122241 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7118 11:57:36.125377 [DutyScan_Calibration_Flow] ====Done====
7119 11:57:36.125867
7120 11:57:36.128604 [DutyScan_Calibration_Flow] k_type=2
7121 11:57:36.146532
7122 11:57:36.147079 ==DQ 0 ==
7123 11:57:36.149686 Final DQ duty delay cell = 0
7124 11:57:36.153254 [0] MAX Duty = 5093%(X100), DQS PI = 16
7125 11:57:36.156777 [0] MIN Duty = 4938%(X100), DQS PI = 48
7126 11:57:36.157335 [0] AVG Duty = 5015%(X100)
7127 11:57:36.160064
7128 11:57:36.160673 ==DQ 1 ==
7129 11:57:36.163013 Final DQ duty delay cell = 0
7130 11:57:36.166339 [0] MAX Duty = 5031%(X100), DQS PI = 2
7131 11:57:36.169939 [0] MIN Duty = 4876%(X100), DQS PI = 28
7132 11:57:36.170493 [0] AVG Duty = 4953%(X100)
7133 11:57:36.170860
7134 11:57:36.173213 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7135 11:57:36.176871
7136 11:57:36.177428 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7137 11:57:36.183287 [DutyScan_Calibration_Flow] ====Done====
7138 11:57:36.186538 nWR fixed to 30
7139 11:57:36.187091 [ModeRegInit_LP4] CH0 RK0
7140 11:57:36.189652 [ModeRegInit_LP4] CH0 RK1
7141 11:57:36.193136 [ModeRegInit_LP4] CH1 RK0
7142 11:57:36.193693 [ModeRegInit_LP4] CH1 RK1
7143 11:57:36.196434 match AC timing 4
7144 11:57:36.199654 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7145 11:57:36.206184 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7146 11:57:36.209781 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7147 11:57:36.216925 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7148 11:57:36.220102 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7149 11:57:36.220700 [MiockJmeterHQA]
7150 11:57:36.221072
7151 11:57:36.222786 [DramcMiockJmeter] u1RxGatingPI = 0
7152 11:57:36.226274 0 : 4255, 4027
7153 11:57:36.226845 4 : 4257, 4029
7154 11:57:36.227341 8 : 4363, 4137
7155 11:57:36.229979 12 : 4257, 4029
7156 11:57:36.230573 16 : 4252, 4027
7157 11:57:36.232934 20 : 4363, 4138
7158 11:57:36.233414 24 : 4252, 4026
7159 11:57:36.236368 28 : 4252, 4027
7160 11:57:36.236975 32 : 4253, 4027
7161 11:57:36.239534 36 : 4255, 4029
7162 11:57:36.240120 40 : 4252, 4027
7163 11:57:36.240662 44 : 4252, 4027
7164 11:57:36.242794 48 : 4365, 4140
7165 11:57:36.243362 52 : 4252, 4026
7166 11:57:36.246140 56 : 4255, 4029
7167 11:57:36.246754 60 : 4250, 4027
7168 11:57:36.249700 64 : 4361, 4137
7169 11:57:36.250270 68 : 4250, 4026
7170 11:57:36.252732 72 : 4361, 4137
7171 11:57:36.253299 76 : 4250, 4026
7172 11:57:36.253793 80 : 4250, 4027
7173 11:57:36.255976 84 : 4249, 4027
7174 11:57:36.256451 88 : 4253, 4029
7175 11:57:36.259795 92 : 4361, 4137
7176 11:57:36.260359 96 : 4250, 4027
7177 11:57:36.262426 100 : 4360, 2544
7178 11:57:36.262918 104 : 4361, 0
7179 11:57:36.263407 108 : 4249, 0
7180 11:57:36.266060 112 : 4363, 0
7181 11:57:36.266536 116 : 4363, 0
7182 11:57:36.269368 120 : 4363, 0
7183 11:57:36.269845 124 : 4250, 0
7184 11:57:36.270329 128 : 4249, 0
7185 11:57:36.272672 132 : 4361, 0
7186 11:57:36.273239 136 : 4250, 0
7187 11:57:36.275842 140 : 4250, 0
7188 11:57:36.276407 144 : 4250, 0
7189 11:57:36.276945 148 : 4252, 0
7190 11:57:36.279177 152 : 4250, 0
7191 11:57:36.279738 156 : 4250, 0
7192 11:57:36.282372 160 : 4252, 0
7193 11:57:36.282850 164 : 4250, 0
7194 11:57:36.283437 168 : 4360, 0
7195 11:57:36.285837 172 : 4361, 0
7196 11:57:36.286460 176 : 4250, 0
7197 11:57:36.286951 180 : 4250, 0
7198 11:57:36.288868 184 : 4250, 0
7199 11:57:36.289347 188 : 4253, 0
7200 11:57:36.292460 192 : 4250, 0
7201 11:57:36.293080 196 : 4250, 0
7202 11:57:36.293573 200 : 4253, 0
7203 11:57:36.295523 204 : 4360, 0
7204 11:57:36.296001 208 : 4250, 0
7205 11:57:36.298745 212 : 4250, 0
7206 11:57:36.299223 216 : 4250, 0
7207 11:57:36.299709 220 : 4360, 244
7208 11:57:36.302222 224 : 4250, 3874
7209 11:57:36.302787 228 : 4250, 4026
7210 11:57:36.305514 232 : 4250, 4027
7211 11:57:36.305992 236 : 4250, 4027
7212 11:57:36.308728 240 : 4250, 4027
7213 11:57:36.309192 244 : 4253, 4029
7214 11:57:36.312079 248 : 4250, 4027
7215 11:57:36.312583 252 : 4360, 4138
7216 11:57:36.315446 256 : 4360, 4137
7217 11:57:36.315908 260 : 4250, 4026
7218 11:57:36.319065 264 : 4363, 4139
7219 11:57:36.319622 268 : 4250, 4027
7220 11:57:36.322067 272 : 4250, 4027
7221 11:57:36.322535 276 : 4252, 4026
7222 11:57:36.322951 280 : 4252, 4029
7223 11:57:36.325488 284 : 4250, 4027
7224 11:57:36.325955 288 : 4250, 4027
7225 11:57:36.329019 292 : 4250, 4027
7226 11:57:36.329483 296 : 4253, 4029
7227 11:57:36.332437 300 : 4250, 4027
7228 11:57:36.333110 304 : 4360, 4138
7229 11:57:36.335581 308 : 4361, 4137
7230 11:57:36.336130 312 : 4250, 4026
7231 11:57:36.338930 316 : 4363, 4139
7232 11:57:36.339478 320 : 4250, 4027
7233 11:57:36.342320 324 : 4249, 4027
7234 11:57:36.342895 328 : 4250, 4027
7235 11:57:36.345376 332 : 4252, 4029
7236 11:57:36.345837 336 : 4250, 3984
7237 11:57:36.346206 340 : 4250, 2263
7238 11:57:36.348620 344 : 4250, 2
7239 11:57:36.349099
7240 11:57:36.351991 MIOCK jitter meter ch=0
7241 11:57:36.352585
7242 11:57:36.352964 1T = (344-104) = 240 dly cells
7243 11:57:36.359027 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7244 11:57:36.359638 ==
7245 11:57:36.361972 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 11:57:36.365434 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7247 11:57:36.368575 ==
7248 11:57:36.372299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7249 11:57:36.375543 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7250 11:57:36.381806 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7251 11:57:36.388439 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7252 11:57:36.395225 [CA 0] Center 42 (12~73) winsize 62
7253 11:57:36.398607 [CA 1] Center 42 (12~73) winsize 62
7254 11:57:36.401585 [CA 2] Center 39 (9~69) winsize 61
7255 11:57:36.404913 [CA 3] Center 38 (9~68) winsize 60
7256 11:57:36.408579 [CA 4] Center 37 (7~67) winsize 61
7257 11:57:36.411877 [CA 5] Center 36 (6~66) winsize 61
7258 11:57:36.412427
7259 11:57:36.414940 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7260 11:57:36.415394
7261 11:57:36.418378 [CATrainingPosCal] consider 1 rank data
7262 11:57:36.421322 u2DelayCellTimex100 = 271/100 ps
7263 11:57:36.427981 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7264 11:57:36.431537 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7265 11:57:36.434863 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7266 11:57:36.438008 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7267 11:57:36.441501 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7268 11:57:36.445080 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7269 11:57:36.445665
7270 11:57:36.448196 CA PerBit enable=1, Macro0, CA PI delay=36
7271 11:57:36.448799
7272 11:57:36.451227 [CBTSetCACLKResult] CA Dly = 36
7273 11:57:36.454490 CS Dly: 10 (0~41)
7274 11:57:36.458137 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7275 11:57:36.461506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7276 11:57:36.462052 ==
7277 11:57:36.464755 Dram Type= 6, Freq= 0, CH_0, rank 1
7278 11:57:36.471275 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7279 11:57:36.471850 ==
7280 11:57:36.474659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7281 11:57:36.478000 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7282 11:57:36.484674 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7283 11:57:36.491065 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7284 11:57:36.497792 [CA 0] Center 42 (12~73) winsize 62
7285 11:57:36.500871 [CA 1] Center 41 (11~72) winsize 62
7286 11:57:36.504387 [CA 2] Center 38 (8~68) winsize 61
7287 11:57:36.507688 [CA 3] Center 37 (7~67) winsize 61
7288 11:57:36.511284 [CA 4] Center 35 (5~65) winsize 61
7289 11:57:36.514288 [CA 5] Center 35 (5~66) winsize 62
7290 11:57:36.514748
7291 11:57:36.517804 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7292 11:57:36.518263
7293 11:57:36.520967 [CATrainingPosCal] consider 2 rank data
7294 11:57:36.523974 u2DelayCellTimex100 = 271/100 ps
7295 11:57:36.530850 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7296 11:57:36.534018 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7297 11:57:36.537250 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7298 11:57:36.540433 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7299 11:57:36.544441 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7300 11:57:36.547710 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7301 11:57:36.548255
7302 11:57:36.550889 CA PerBit enable=1, Macro0, CA PI delay=36
7303 11:57:36.551433
7304 11:57:36.553724 [CBTSetCACLKResult] CA Dly = 36
7305 11:57:36.557130 CS Dly: 11 (0~43)
7306 11:57:36.561070 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7307 11:57:36.564072 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7308 11:57:36.564565
7309 11:57:36.566899 ----->DramcWriteLeveling(PI) begin...
7310 11:57:36.567359 ==
7311 11:57:36.570663 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 11:57:36.577118 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7313 11:57:36.577654 ==
7314 11:57:36.580308 Write leveling (Byte 0): 30 => 30
7315 11:57:36.580811 Write leveling (Byte 1): 26 => 26
7316 11:57:36.584225 DramcWriteLeveling(PI) end<-----
7317 11:57:36.584842
7318 11:57:36.587367 ==
7319 11:57:36.587949 Dram Type= 6, Freq= 0, CH_0, rank 0
7320 11:57:36.593490 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7321 11:57:36.594025 ==
7322 11:57:36.597167 [Gating] SW mode calibration
7323 11:57:36.603779 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7324 11:57:36.607060 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7325 11:57:36.613821 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7326 11:57:36.616945 0 12 4 | B1->B0 | 2323 3333 | 0 0 | (1 1) (1 1)
7327 11:57:36.620592 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 11:57:36.627226 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 11:57:36.630481 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 11:57:36.634048 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7331 11:57:36.640478 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 11:57:36.643562 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7333 11:57:36.647011 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7334 11:57:36.653844 0 13 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7335 11:57:36.656833 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7336 11:57:36.660791 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 11:57:36.666718 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 11:57:36.670241 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 11:57:36.673446 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 11:57:36.676889 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 11:57:36.683812 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7342 11:57:36.687110 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7343 11:57:36.690257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 11:57:36.697009 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 11:57:36.700153 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 11:57:36.703406 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 11:57:36.709776 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 11:57:36.713402 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7349 11:57:36.716374 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7350 11:57:36.723297 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7351 11:57:36.726167 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 11:57:36.729642 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 11:57:36.736486 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 11:57:36.739905 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 11:57:36.743069 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 11:57:36.749782 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 11:57:36.752973 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 11:57:36.756554 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 11:57:36.763099 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 11:57:36.766204 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 11:57:36.769296 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 11:57:36.776377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 11:57:36.779662 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 11:57:36.782983 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7365 11:57:36.789407 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7366 11:57:36.792924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7367 11:57:36.796564 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7368 11:57:36.799982 Total UI for P1: 0, mck2ui 16
7369 11:57:36.802891 best dqsien dly found for B0: ( 1, 1, 0)
7370 11:57:36.805946 Total UI for P1: 0, mck2ui 16
7371 11:57:36.809506 best dqsien dly found for B1: ( 1, 1, 2)
7372 11:57:36.813134 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7373 11:57:36.816211 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7374 11:57:36.816862
7375 11:57:36.819735 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7376 11:57:36.822814 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7377 11:57:36.825912 [Gating] SW calibration Done
7378 11:57:36.826374 ==
7379 11:57:36.829939 Dram Type= 6, Freq= 0, CH_0, rank 0
7380 11:57:36.836375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7381 11:57:36.837059 ==
7382 11:57:36.837434 RX Vref Scan: 0
7383 11:57:36.837779
7384 11:57:36.839539 RX Vref 0 -> 0, step: 1
7385 11:57:36.840115
7386 11:57:36.843051 RX Delay 0 -> 252, step: 8
7387 11:57:36.845905 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7388 11:57:36.849786 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7389 11:57:36.852244 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7390 11:57:36.856089 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7391 11:57:36.862351 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7392 11:57:36.865586 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7393 11:57:36.868571 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7394 11:57:36.872444 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7395 11:57:36.878811 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7396 11:57:36.882219 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7397 11:57:36.885505 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7398 11:57:36.889117 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7399 11:57:36.892197 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7400 11:57:36.898712 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7401 11:57:36.901990 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7402 11:57:36.905252 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7403 11:57:36.905716 ==
7404 11:57:36.908576 Dram Type= 6, Freq= 0, CH_0, rank 0
7405 11:57:36.911701 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7406 11:57:36.912157 ==
7407 11:57:36.915314 DQS Delay:
7408 11:57:36.915862 DQS0 = 0, DQS1 = 0
7409 11:57:36.918535 DQM Delay:
7410 11:57:36.918990 DQM0 = 129, DQM1 = 123
7411 11:57:36.922274 DQ Delay:
7412 11:57:36.925012 DQ0 =123, DQ1 =131, DQ2 =127, DQ3 =127
7413 11:57:36.928606 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7414 11:57:36.931808 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7415 11:57:36.935191 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7416 11:57:36.935749
7417 11:57:36.936113
7418 11:57:36.936451 ==
7419 11:57:36.938333 Dram Type= 6, Freq= 0, CH_0, rank 0
7420 11:57:36.941907 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7421 11:57:36.942464 ==
7422 11:57:36.942835
7423 11:57:36.943170
7424 11:57:36.945038 TX Vref Scan disable
7425 11:57:36.948729 == TX Byte 0 ==
7426 11:57:36.951705 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7427 11:57:36.954902 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7428 11:57:36.958056 == TX Byte 1 ==
7429 11:57:36.961814 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7430 11:57:36.964721 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7431 11:57:36.965180 ==
7432 11:57:36.968033 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 11:57:36.974700 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 11:57:36.975268 ==
7435 11:57:36.986692
7436 11:57:36.989695 TX Vref early break, caculate TX vref
7437 11:57:36.993057 TX Vref=16, minBit 8, minWin=21, winSum=374
7438 11:57:36.996611 TX Vref=18, minBit 9, minWin=22, winSum=380
7439 11:57:36.999748 TX Vref=20, minBit 8, minWin=22, winSum=385
7440 11:57:37.003114 TX Vref=22, minBit 8, minWin=23, winSum=397
7441 11:57:37.006388 TX Vref=24, minBit 8, minWin=24, winSum=405
7442 11:57:37.013227 TX Vref=26, minBit 8, minWin=25, winSum=415
7443 11:57:37.016560 TX Vref=28, minBit 8, minWin=24, winSum=410
7444 11:57:37.019889 TX Vref=30, minBit 8, minWin=24, winSum=407
7445 11:57:37.023141 TX Vref=32, minBit 3, minWin=24, winSum=398
7446 11:57:37.026369 TX Vref=34, minBit 3, minWin=23, winSum=387
7447 11:57:37.033464 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 26
7448 11:57:37.034016
7449 11:57:37.036390 Final TX Range 0 Vref 26
7450 11:57:37.036982
7451 11:57:37.037347 ==
7452 11:57:37.040158 Dram Type= 6, Freq= 0, CH_0, rank 0
7453 11:57:37.043077 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7454 11:57:37.043632 ==
7455 11:57:37.043997
7456 11:57:37.044332
7457 11:57:37.046582 TX Vref Scan disable
7458 11:57:37.053127 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7459 11:57:37.053679 == TX Byte 0 ==
7460 11:57:37.056656 u2DelayCellOfst[0]=14 cells (4 PI)
7461 11:57:37.059898 u2DelayCellOfst[1]=21 cells (6 PI)
7462 11:57:37.062821 u2DelayCellOfst[2]=18 cells (5 PI)
7463 11:57:37.066267 u2DelayCellOfst[3]=14 cells (4 PI)
7464 11:57:37.069395 u2DelayCellOfst[4]=10 cells (3 PI)
7465 11:57:37.072999 u2DelayCellOfst[5]=0 cells (0 PI)
7466 11:57:37.076185 u2DelayCellOfst[6]=21 cells (6 PI)
7467 11:57:37.079435 u2DelayCellOfst[7]=21 cells (6 PI)
7468 11:57:37.082957 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7469 11:57:37.086122 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7470 11:57:37.089263 == TX Byte 1 ==
7471 11:57:37.089715 u2DelayCellOfst[8]=3 cells (1 PI)
7472 11:57:37.093014 u2DelayCellOfst[9]=0 cells (0 PI)
7473 11:57:37.096237 u2DelayCellOfst[10]=10 cells (3 PI)
7474 11:57:37.099652 u2DelayCellOfst[11]=7 cells (2 PI)
7475 11:57:37.102662 u2DelayCellOfst[12]=14 cells (4 PI)
7476 11:57:37.106232 u2DelayCellOfst[13]=14 cells (4 PI)
7477 11:57:37.109389 u2DelayCellOfst[14]=18 cells (5 PI)
7478 11:57:37.113110 u2DelayCellOfst[15]=18 cells (5 PI)
7479 11:57:37.116227 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7480 11:57:37.122905 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7481 11:57:37.123472 DramC Write-DBI on
7482 11:57:37.123957 ==
7483 11:57:37.126188 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 11:57:37.129588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7485 11:57:37.130157 ==
7486 11:57:37.132458
7487 11:57:37.132968
7488 11:57:37.133447 TX Vref Scan disable
7489 11:57:37.136463 == TX Byte 0 ==
7490 11:57:37.139100 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7491 11:57:37.142815 == TX Byte 1 ==
7492 11:57:37.146224 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7493 11:57:37.149013 DramC Write-DBI off
7494 11:57:37.149481
7495 11:57:37.149955 [DATLAT]
7496 11:57:37.150403 Freq=1600, CH0 RK0
7497 11:57:37.150841
7498 11:57:37.152480 DATLAT Default: 0xf
7499 11:57:37.153025 0, 0xFFFF, sum = 0
7500 11:57:37.155913 1, 0xFFFF, sum = 0
7501 11:57:37.159266 2, 0xFFFF, sum = 0
7502 11:57:37.159839 3, 0xFFFF, sum = 0
7503 11:57:37.162674 4, 0xFFFF, sum = 0
7504 11:57:37.163240 5, 0xFFFF, sum = 0
7505 11:57:37.165741 6, 0xFFFF, sum = 0
7506 11:57:37.166216 7, 0xFFFF, sum = 0
7507 11:57:37.168844 8, 0xFFFF, sum = 0
7508 11:57:37.169342 9, 0xFFFF, sum = 0
7509 11:57:37.172260 10, 0xFFFF, sum = 0
7510 11:57:37.172850 11, 0xFFFF, sum = 0
7511 11:57:37.175761 12, 0xFFF, sum = 0
7512 11:57:37.176446 13, 0x0, sum = 1
7513 11:57:37.179012 14, 0x0, sum = 2
7514 11:57:37.179569 15, 0x0, sum = 3
7515 11:57:37.182317 16, 0x0, sum = 4
7516 11:57:37.182875 best_step = 14
7517 11:57:37.183245
7518 11:57:37.183583 ==
7519 11:57:37.185577 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 11:57:37.189362 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7521 11:57:37.192639 ==
7522 11:57:37.193192 RX Vref Scan: 1
7523 11:57:37.193569
7524 11:57:37.195368 Set Vref Range= 24 -> 127
7525 11:57:37.195830
7526 11:57:37.198888 RX Vref 24 -> 127, step: 1
7527 11:57:37.199440
7528 11:57:37.199808 RX Delay 11 -> 252, step: 4
7529 11:57:37.200152
7530 11:57:37.202320 Set Vref, RX VrefLevel [Byte0]: 24
7531 11:57:37.205398 [Byte1]: 24
7532 11:57:37.209117
7533 11:57:37.209575 Set Vref, RX VrefLevel [Byte0]: 25
7534 11:57:37.212591 [Byte1]: 25
7535 11:57:37.216718
7536 11:57:37.217176 Set Vref, RX VrefLevel [Byte0]: 26
7537 11:57:37.220060 [Byte1]: 26
7538 11:57:37.224900
7539 11:57:37.225461 Set Vref, RX VrefLevel [Byte0]: 27
7540 11:57:37.228153 [Byte1]: 27
7541 11:57:37.232438
7542 11:57:37.233072 Set Vref, RX VrefLevel [Byte0]: 28
7543 11:57:37.235755 [Byte1]: 28
7544 11:57:37.239725
7545 11:57:37.240275 Set Vref, RX VrefLevel [Byte0]: 29
7546 11:57:37.243355 [Byte1]: 29
7547 11:57:37.247463
7548 11:57:37.248010 Set Vref, RX VrefLevel [Byte0]: 30
7549 11:57:37.250908 [Byte1]: 30
7550 11:57:37.254999
7551 11:57:37.255554 Set Vref, RX VrefLevel [Byte0]: 31
7552 11:57:37.258406 [Byte1]: 31
7553 11:57:37.262839
7554 11:57:37.263378 Set Vref, RX VrefLevel [Byte0]: 32
7555 11:57:37.265588 [Byte1]: 32
7556 11:57:37.270105
7557 11:57:37.270723 Set Vref, RX VrefLevel [Byte0]: 33
7558 11:57:37.273412 [Byte1]: 33
7559 11:57:37.277784
7560 11:57:37.278331 Set Vref, RX VrefLevel [Byte0]: 34
7561 11:57:37.280989 [Byte1]: 34
7562 11:57:37.285439
7563 11:57:37.285981 Set Vref, RX VrefLevel [Byte0]: 35
7564 11:57:37.288668 [Byte1]: 35
7565 11:57:37.293169
7566 11:57:37.293711 Set Vref, RX VrefLevel [Byte0]: 36
7567 11:57:37.296392 [Byte1]: 36
7568 11:57:37.301154
7569 11:57:37.301700 Set Vref, RX VrefLevel [Byte0]: 37
7570 11:57:37.304332 [Byte1]: 37
7571 11:57:37.308114
7572 11:57:37.308878 Set Vref, RX VrefLevel [Byte0]: 38
7573 11:57:37.311711 [Byte1]: 38
7574 11:57:37.315932
7575 11:57:37.316477 Set Vref, RX VrefLevel [Byte0]: 39
7576 11:57:37.318960 [Byte1]: 39
7577 11:57:37.323555
7578 11:57:37.324117 Set Vref, RX VrefLevel [Byte0]: 40
7579 11:57:37.326654 [Byte1]: 40
7580 11:57:37.330972
7581 11:57:37.331511 Set Vref, RX VrefLevel [Byte0]: 41
7582 11:57:37.334227 [Byte1]: 41
7583 11:57:37.338507
7584 11:57:37.338970 Set Vref, RX VrefLevel [Byte0]: 42
7585 11:57:37.342006 [Byte1]: 42
7586 11:57:37.346577
7587 11:57:37.347121 Set Vref, RX VrefLevel [Byte0]: 43
7588 11:57:37.349595 [Byte1]: 43
7589 11:57:37.353746
7590 11:57:37.354293 Set Vref, RX VrefLevel [Byte0]: 44
7591 11:57:37.357407 [Byte1]: 44
7592 11:57:37.361892
7593 11:57:37.362436 Set Vref, RX VrefLevel [Byte0]: 45
7594 11:57:37.364902 [Byte1]: 45
7595 11:57:37.369172
7596 11:57:37.369725 Set Vref, RX VrefLevel [Byte0]: 46
7597 11:57:37.372714 [Byte1]: 46
7598 11:57:37.377073
7599 11:57:37.377624 Set Vref, RX VrefLevel [Byte0]: 47
7600 11:57:37.379836 [Byte1]: 47
7601 11:57:37.384587
7602 11:57:37.385136 Set Vref, RX VrefLevel [Byte0]: 48
7603 11:57:37.387755 [Byte1]: 48
7604 11:57:37.391919
7605 11:57:37.392379 Set Vref, RX VrefLevel [Byte0]: 49
7606 11:57:37.395345 [Byte1]: 49
7607 11:57:37.399816
7608 11:57:37.400367 Set Vref, RX VrefLevel [Byte0]: 50
7609 11:57:37.403041 [Byte1]: 50
7610 11:57:37.407350
7611 11:57:37.407897 Set Vref, RX VrefLevel [Byte0]: 51
7612 11:57:37.410423 [Byte1]: 51
7613 11:57:37.414804
7614 11:57:37.415353 Set Vref, RX VrefLevel [Byte0]: 52
7615 11:57:37.418581 [Byte1]: 52
7616 11:57:37.422325
7617 11:57:37.422886 Set Vref, RX VrefLevel [Byte0]: 53
7618 11:57:37.425934 [Byte1]: 53
7619 11:57:37.429942
7620 11:57:37.430405 Set Vref, RX VrefLevel [Byte0]: 54
7621 11:57:37.433722 [Byte1]: 54
7622 11:57:37.437728
7623 11:57:37.438280 Set Vref, RX VrefLevel [Byte0]: 55
7624 11:57:37.440794 [Byte1]: 55
7625 11:57:37.445464
7626 11:57:37.446011 Set Vref, RX VrefLevel [Byte0]: 56
7627 11:57:37.448665 [Byte1]: 56
7628 11:57:37.453019
7629 11:57:37.453566 Set Vref, RX VrefLevel [Byte0]: 57
7630 11:57:37.455999 [Byte1]: 57
7631 11:57:37.460588
7632 11:57:37.461138 Set Vref, RX VrefLevel [Byte0]: 58
7633 11:57:37.463785 [Byte1]: 58
7634 11:57:37.467977
7635 11:57:37.468562 Set Vref, RX VrefLevel [Byte0]: 59
7636 11:57:37.471574 [Byte1]: 59
7637 11:57:37.475743
7638 11:57:37.476294 Set Vref, RX VrefLevel [Byte0]: 60
7639 11:57:37.479164 [Byte1]: 60
7640 11:57:37.483536
7641 11:57:37.484095 Set Vref, RX VrefLevel [Byte0]: 61
7642 11:57:37.486711 [Byte1]: 61
7643 11:57:37.490936
7644 11:57:37.491486 Set Vref, RX VrefLevel [Byte0]: 62
7645 11:57:37.494502 [Byte1]: 62
7646 11:57:37.498766
7647 11:57:37.499319 Set Vref, RX VrefLevel [Byte0]: 63
7648 11:57:37.501957 [Byte1]: 63
7649 11:57:37.506198
7650 11:57:37.506748 Set Vref, RX VrefLevel [Byte0]: 64
7651 11:57:37.509547 [Byte1]: 64
7652 11:57:37.513734
7653 11:57:37.514287 Set Vref, RX VrefLevel [Byte0]: 65
7654 11:57:37.517030 [Byte1]: 65
7655 11:57:37.521487
7656 11:57:37.522035 Set Vref, RX VrefLevel [Byte0]: 66
7657 11:57:37.524432 [Byte1]: 66
7658 11:57:37.528878
7659 11:57:37.529338 Set Vref, RX VrefLevel [Byte0]: 67
7660 11:57:37.532219 [Byte1]: 67
7661 11:57:37.536733
7662 11:57:37.537288 Set Vref, RX VrefLevel [Byte0]: 68
7663 11:57:37.539939 [Byte1]: 68
7664 11:57:37.544952
7665 11:57:37.545499 Set Vref, RX VrefLevel [Byte0]: 69
7666 11:57:37.547925 [Byte1]: 69
7667 11:57:37.551839
7668 11:57:37.552383 Set Vref, RX VrefLevel [Byte0]: 70
7669 11:57:37.555316 [Byte1]: 70
7670 11:57:37.559589
7671 11:57:37.560136 Set Vref, RX VrefLevel [Byte0]: 71
7672 11:57:37.562775 [Byte1]: 71
7673 11:57:37.566946
7674 11:57:37.567406 Final RX Vref Byte 0 = 54 to rank0
7675 11:57:37.570172 Final RX Vref Byte 1 = 54 to rank0
7676 11:57:37.573393 Final RX Vref Byte 0 = 54 to rank1
7677 11:57:37.577387 Final RX Vref Byte 1 = 54 to rank1==
7678 11:57:37.580079 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 11:57:37.587004 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7680 11:57:37.587566 ==
7681 11:57:37.587937 DQS Delay:
7682 11:57:37.588278 DQS0 = 0, DQS1 = 0
7683 11:57:37.590454 DQM Delay:
7684 11:57:37.590940 DQM0 = 126, DQM1 = 120
7685 11:57:37.593576 DQ Delay:
7686 11:57:37.596972 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7687 11:57:37.600188 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7688 11:57:37.603810 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7689 11:57:37.607033 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7690 11:57:37.607587
7691 11:57:37.607952
7692 11:57:37.608289
7693 11:57:37.610142 [DramC_TX_OE_Calibration] TA2
7694 11:57:37.613717 Original DQ_B0 (3 6) =30, OEN = 27
7695 11:57:37.616581 Original DQ_B1 (3 6) =30, OEN = 27
7696 11:57:37.620123 24, 0x0, End_B0=24 End_B1=24
7697 11:57:37.620737 25, 0x0, End_B0=25 End_B1=25
7698 11:57:37.623603 26, 0x0, End_B0=26 End_B1=26
7699 11:57:37.626746 27, 0x0, End_B0=27 End_B1=27
7700 11:57:37.630322 28, 0x0, End_B0=28 End_B1=28
7701 11:57:37.633413 29, 0x0, End_B0=29 End_B1=29
7702 11:57:37.633885 30, 0x0, End_B0=30 End_B1=30
7703 11:57:37.636666 31, 0x4141, End_B0=30 End_B1=30
7704 11:57:37.639837 Byte0 end_step=30 best_step=27
7705 11:57:37.643568 Byte1 end_step=30 best_step=27
7706 11:57:37.646757 Byte0 TX OE(2T, 0.5T) = (3, 3)
7707 11:57:37.649877 Byte1 TX OE(2T, 0.5T) = (3, 3)
7708 11:57:37.650663
7709 11:57:37.651155
7710 11:57:37.656654 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7711 11:57:37.659554 CH0 RK0: MR19=303, MR18=1D1D
7712 11:57:37.666177 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7713 11:57:37.666720
7714 11:57:37.669558 ----->DramcWriteLeveling(PI) begin...
7715 11:57:37.670102 ==
7716 11:57:37.673091 Dram Type= 6, Freq= 0, CH_0, rank 1
7717 11:57:37.676251 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7718 11:57:37.676753 ==
7719 11:57:37.679723 Write leveling (Byte 0): 29 => 29
7720 11:57:37.683085 Write leveling (Byte 1): 24 => 24
7721 11:57:37.686468 DramcWriteLeveling(PI) end<-----
7722 11:57:37.687019
7723 11:57:37.687386 ==
7724 11:57:37.689421 Dram Type= 6, Freq= 0, CH_0, rank 1
7725 11:57:37.692639 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7726 11:57:37.693107 ==
7727 11:57:37.696303 [Gating] SW mode calibration
7728 11:57:37.702850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7729 11:57:37.709568 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7730 11:57:37.712729 0 12 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7731 11:57:37.719526 0 12 4 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
7732 11:57:37.722712 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 11:57:37.725832 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 11:57:37.733252 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 11:57:37.736066 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7736 11:57:37.739859 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7737 11:57:37.742706 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7738 11:57:37.749393 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7739 11:57:37.753027 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7740 11:57:37.755830 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 11:57:37.762825 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 11:57:37.765778 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 11:57:37.769129 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 11:57:37.776067 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 11:57:37.779396 0 13 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7746 11:57:37.782739 0 14 0 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7747 11:57:37.789129 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7748 11:57:37.792359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 11:57:37.795753 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 11:57:37.802536 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 11:57:37.805458 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 11:57:37.809041 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7753 11:57:37.815284 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 11:57:37.818583 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7755 11:57:37.822201 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7756 11:57:37.828671 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7757 11:57:37.831948 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 11:57:37.835367 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 11:57:37.842141 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 11:57:37.845238 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 11:57:37.848847 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 11:57:37.855082 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 11:57:37.858847 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 11:57:37.862084 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 11:57:37.868322 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 11:57:37.871503 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 11:57:37.875128 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 11:57:37.881826 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 11:57:37.885464 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7770 11:57:37.888764 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7771 11:57:37.895131 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7772 11:57:37.898272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7773 11:57:37.901884 Total UI for P1: 0, mck2ui 16
7774 11:57:37.905448 best dqsien dly found for B0: ( 1, 1, 0)
7775 11:57:37.908571 Total UI for P1: 0, mck2ui 16
7776 11:57:37.911975 best dqsien dly found for B1: ( 1, 1, 2)
7777 11:57:37.915344 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7778 11:57:37.918510 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7779 11:57:37.919063
7780 11:57:37.921890 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7781 11:57:37.925122 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7782 11:57:37.928083 [Gating] SW calibration Done
7783 11:57:37.928708 ==
7784 11:57:37.931716 Dram Type= 6, Freq= 0, CH_0, rank 1
7785 11:57:37.934953 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7786 11:57:37.935578 ==
7787 11:57:37.938345 RX Vref Scan: 0
7788 11:57:37.938892
7789 11:57:37.939257 RX Vref 0 -> 0, step: 1
7790 11:57:37.941694
7791 11:57:37.942408 RX Delay 0 -> 252, step: 8
7792 11:57:37.948292 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7793 11:57:37.951871 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7794 11:57:37.954819 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7795 11:57:37.958225 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7796 11:57:37.961366 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7797 11:57:37.965206 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7798 11:57:37.971085 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7799 11:57:37.974842 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7800 11:57:37.978277 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7801 11:57:37.981249 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7802 11:57:37.987918 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7803 11:57:37.991412 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7804 11:57:37.994859 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7805 11:57:37.998209 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7806 11:57:38.001498 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7807 11:57:38.007936 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7808 11:57:38.008489 ==
7809 11:57:38.011312 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 11:57:38.014624 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 11:57:38.015181 ==
7812 11:57:38.015549 DQS Delay:
7813 11:57:38.018265 DQS0 = 0, DQS1 = 0
7814 11:57:38.018717 DQM Delay:
7815 11:57:38.021283 DQM0 = 130, DQM1 = 124
7816 11:57:38.021736 DQ Delay:
7817 11:57:38.024464 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7818 11:57:38.027838 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7819 11:57:38.031194 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7820 11:57:38.034498 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7821 11:57:38.034952
7822 11:57:38.035306
7823 11:57:38.037777 ==
7824 11:57:38.040895 Dram Type= 6, Freq= 0, CH_0, rank 1
7825 11:57:38.044641 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7826 11:57:38.045195 ==
7827 11:57:38.045564
7828 11:57:38.045905
7829 11:57:38.047513 TX Vref Scan disable
7830 11:57:38.048074 == TX Byte 0 ==
7831 11:57:38.050961 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7832 11:57:38.057739 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7833 11:57:38.058297 == TX Byte 1 ==
7834 11:57:38.061192 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7835 11:57:38.067427 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7836 11:57:38.067882 ==
7837 11:57:38.070669 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 11:57:38.074213 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 11:57:38.074770 ==
7840 11:57:38.087842
7841 11:57:38.090952 TX Vref early break, caculate TX vref
7842 11:57:38.094503 TX Vref=16, minBit 9, minWin=22, winSum=376
7843 11:57:38.097648 TX Vref=18, minBit 9, minWin=23, winSum=388
7844 11:57:38.100830 TX Vref=20, minBit 8, minWin=23, winSum=396
7845 11:57:38.104197 TX Vref=22, minBit 1, minWin=24, winSum=401
7846 11:57:38.107626 TX Vref=24, minBit 0, minWin=25, winSum=408
7847 11:57:38.113994 TX Vref=26, minBit 0, minWin=25, winSum=413
7848 11:57:38.117060 TX Vref=28, minBit 1, minWin=25, winSum=415
7849 11:57:38.120590 TX Vref=30, minBit 8, minWin=24, winSum=412
7850 11:57:38.124175 TX Vref=32, minBit 7, minWin=24, winSum=403
7851 11:57:38.127595 TX Vref=34, minBit 8, minWin=23, winSum=391
7852 11:57:38.133987 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
7853 11:57:38.134444
7854 11:57:38.136971 Final TX Range 0 Vref 28
7855 11:57:38.137424
7856 11:57:38.137784 ==
7857 11:57:38.141077 Dram Type= 6, Freq= 0, CH_0, rank 1
7858 11:57:38.144142 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7859 11:57:38.144783 ==
7860 11:57:38.145167
7861 11:57:38.145501
7862 11:57:38.147360 TX Vref Scan disable
7863 11:57:38.154447 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7864 11:57:38.155004 == TX Byte 0 ==
7865 11:57:38.156974 u2DelayCellOfst[0]=14 cells (4 PI)
7866 11:57:38.160443 u2DelayCellOfst[1]=18 cells (5 PI)
7867 11:57:38.163565 u2DelayCellOfst[2]=14 cells (4 PI)
7868 11:57:38.166791 u2DelayCellOfst[3]=14 cells (4 PI)
7869 11:57:38.170226 u2DelayCellOfst[4]=10 cells (3 PI)
7870 11:57:38.173427 u2DelayCellOfst[5]=0 cells (0 PI)
7871 11:57:38.177022 u2DelayCellOfst[6]=21 cells (6 PI)
7872 11:57:38.180103 u2DelayCellOfst[7]=18 cells (5 PI)
7873 11:57:38.183760 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7874 11:57:38.187108 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7875 11:57:38.190427 == TX Byte 1 ==
7876 11:57:38.193762 u2DelayCellOfst[8]=3 cells (1 PI)
7877 11:57:38.194305 u2DelayCellOfst[9]=0 cells (0 PI)
7878 11:57:38.196644 u2DelayCellOfst[10]=10 cells (3 PI)
7879 11:57:38.200029 u2DelayCellOfst[11]=3 cells (1 PI)
7880 11:57:38.203465 u2DelayCellOfst[12]=14 cells (4 PI)
7881 11:57:38.207084 u2DelayCellOfst[13]=18 cells (5 PI)
7882 11:57:38.209876 u2DelayCellOfst[14]=18 cells (5 PI)
7883 11:57:38.213371 u2DelayCellOfst[15]=18 cells (5 PI)
7884 11:57:38.216637 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7885 11:57:38.223437 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7886 11:57:38.223995 DramC Write-DBI on
7887 11:57:38.224364 ==
7888 11:57:38.226924 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 11:57:38.233366 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 11:57:38.233834 ==
7891 11:57:38.234203
7892 11:57:38.234541
7893 11:57:38.234868 TX Vref Scan disable
7894 11:57:38.237173 == TX Byte 0 ==
7895 11:57:38.240669 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7896 11:57:38.244069 == TX Byte 1 ==
7897 11:57:38.247216 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7898 11:57:38.250586 DramC Write-DBI off
7899 11:57:38.251139
7900 11:57:38.251506 [DATLAT]
7901 11:57:38.251848 Freq=1600, CH0 RK1
7902 11:57:38.252179
7903 11:57:38.254050 DATLAT Default: 0xe
7904 11:57:38.254604 0, 0xFFFF, sum = 0
7905 11:57:38.256949 1, 0xFFFF, sum = 0
7906 11:57:38.260684 2, 0xFFFF, sum = 0
7907 11:57:38.261157 3, 0xFFFF, sum = 0
7908 11:57:38.264286 4, 0xFFFF, sum = 0
7909 11:57:38.264930 5, 0xFFFF, sum = 0
7910 11:57:38.267116 6, 0xFFFF, sum = 0
7911 11:57:38.267606 7, 0xFFFF, sum = 0
7912 11:57:38.270881 8, 0xFFFF, sum = 0
7913 11:57:38.271529 9, 0xFFFF, sum = 0
7914 11:57:38.273874 10, 0xFFFF, sum = 0
7915 11:57:38.274432 11, 0xFFFF, sum = 0
7916 11:57:38.277173 12, 0x8FFF, sum = 0
7917 11:57:38.277633 13, 0x0, sum = 1
7918 11:57:38.280585 14, 0x0, sum = 2
7919 11:57:38.281139 15, 0x0, sum = 3
7920 11:57:38.283859 16, 0x0, sum = 4
7921 11:57:38.284419 best_step = 14
7922 11:57:38.284830
7923 11:57:38.285168 ==
7924 11:57:38.287130 Dram Type= 6, Freq= 0, CH_0, rank 1
7925 11:57:38.290409 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7926 11:57:38.293875 ==
7927 11:57:38.294428 RX Vref Scan: 0
7928 11:57:38.294792
7929 11:57:38.296906 RX Vref 0 -> 0, step: 1
7930 11:57:38.297358
7931 11:57:38.297716 RX Delay 11 -> 252, step: 4
7932 11:57:38.304822 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7933 11:57:38.308377 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7934 11:57:38.310980 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7935 11:57:38.314254 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7936 11:57:38.317643 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116
7937 11:57:38.324345 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7938 11:57:38.328096 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7939 11:57:38.331057 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7940 11:57:38.334426 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7941 11:57:38.338003 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7942 11:57:38.344781 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7943 11:57:38.347924 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7944 11:57:38.350850 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7945 11:57:38.354315 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7946 11:57:38.360932 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7947 11:57:38.364176 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7948 11:57:38.364755 ==
7949 11:57:38.366985 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 11:57:38.371118 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7951 11:57:38.371755 ==
7952 11:57:38.372130 DQS Delay:
7953 11:57:38.373909 DQS0 = 0, DQS1 = 0
7954 11:57:38.374362 DQM Delay:
7955 11:57:38.377181 DQM0 = 128, DQM1 = 120
7956 11:57:38.377632 DQ Delay:
7957 11:57:38.380655 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7958 11:57:38.384181 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
7959 11:57:38.387508 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7960 11:57:38.393774 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7961 11:57:38.394329
7962 11:57:38.394701
7963 11:57:38.395037
7964 11:57:38.397573 [DramC_TX_OE_Calibration] TA2
7965 11:57:38.398027 Original DQ_B0 (3 6) =30, OEN = 27
7966 11:57:38.400551 Original DQ_B1 (3 6) =30, OEN = 27
7967 11:57:38.403886 24, 0x0, End_B0=24 End_B1=24
7968 11:57:38.407360 25, 0x0, End_B0=25 End_B1=25
7969 11:57:38.410460 26, 0x0, End_B0=26 End_B1=26
7970 11:57:38.414042 27, 0x0, End_B0=27 End_B1=27
7971 11:57:38.414545 28, 0x0, End_B0=28 End_B1=28
7972 11:57:38.416900 29, 0x0, End_B0=29 End_B1=29
7973 11:57:38.420474 30, 0x0, End_B0=30 End_B1=30
7974 11:57:38.423558 31, 0x4141, End_B0=30 End_B1=30
7975 11:57:38.427321 Byte0 end_step=30 best_step=27
7976 11:57:38.427878 Byte1 end_step=30 best_step=27
7977 11:57:38.430115 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 11:57:38.433674 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 11:57:38.434228
7980 11:57:38.434586
7981 11:57:38.443742 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7982 11:57:38.444300 CH0 RK1: MR19=303, MR18=2121
7983 11:57:38.450377 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7984 11:57:38.453493 [RxdqsGatingPostProcess] freq 1600
7985 11:57:38.459802 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7986 11:57:38.463379 Pre-setting of DQS Precalculation
7987 11:57:38.466434 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7988 11:57:38.466993 ==
7989 11:57:38.469744 Dram Type= 6, Freq= 0, CH_1, rank 0
7990 11:57:38.476740 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7991 11:57:38.477294 ==
7992 11:57:38.479943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7993 11:57:38.486683 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7994 11:57:38.489871 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7995 11:57:38.496722 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7996 11:57:38.503640 [CA 0] Center 40 (10~71) winsize 62
7997 11:57:38.506515 [CA 1] Center 40 (10~70) winsize 61
7998 11:57:38.509817 [CA 2] Center 36 (6~66) winsize 61
7999 11:57:38.513441 [CA 3] Center 35 (6~65) winsize 60
8000 11:57:38.516402 [CA 4] Center 33 (3~63) winsize 61
8001 11:57:38.519865 [CA 5] Center 33 (4~63) winsize 60
8002 11:57:38.520417
8003 11:57:38.523078 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8004 11:57:38.523631
8005 11:57:38.526679 [CATrainingPosCal] consider 1 rank data
8006 11:57:38.529646 u2DelayCellTimex100 = 271/100 ps
8007 11:57:38.536124 CA0 delay=40 (10~71),Diff = 7 PI (25 cell)
8008 11:57:38.539746 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8009 11:57:38.542794 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8010 11:57:38.546500 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8011 11:57:38.549398 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8012 11:57:38.553074 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8013 11:57:38.553632
8014 11:57:38.556035 CA PerBit enable=1, Macro0, CA PI delay=33
8015 11:57:38.556630
8016 11:57:38.559630 [CBTSetCACLKResult] CA Dly = 33
8017 11:57:38.562421 CS Dly: 9 (0~40)
8018 11:57:38.565700 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8019 11:57:38.569315 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8020 11:57:38.569772 ==
8021 11:57:38.572626 Dram Type= 6, Freq= 0, CH_1, rank 1
8022 11:57:38.579372 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8023 11:57:38.579923 ==
8024 11:57:38.583078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8025 11:57:38.589343 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8026 11:57:38.592676 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8027 11:57:38.599124 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8028 11:57:38.606235 [CA 0] Center 40 (10~70) winsize 61
8029 11:57:38.608902 [CA 1] Center 39 (9~70) winsize 62
8030 11:57:38.612613 [CA 2] Center 35 (6~65) winsize 60
8031 11:57:38.615180 [CA 3] Center 35 (6~64) winsize 59
8032 11:57:38.618888 [CA 4] Center 33 (3~63) winsize 61
8033 11:57:38.621883 [CA 5] Center 33 (4~63) winsize 60
8034 11:57:38.622335
8035 11:57:38.625439 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8036 11:57:38.626110
8037 11:57:38.628625 [CATrainingPosCal] consider 2 rank data
8038 11:57:38.631713 u2DelayCellTimex100 = 271/100 ps
8039 11:57:38.635053 CA0 delay=40 (10~70),Diff = 7 PI (25 cell)
8040 11:57:38.641863 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8041 11:57:38.645111 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8042 11:57:38.648217 CA3 delay=35 (6~64),Diff = 2 PI (7 cell)
8043 11:57:38.651639 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8044 11:57:38.655011 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8045 11:57:38.655464
8046 11:57:38.658489 CA PerBit enable=1, Macro0, CA PI delay=33
8047 11:57:38.659048
8048 11:57:38.661972 [CBTSetCACLKResult] CA Dly = 33
8049 11:57:38.665248 CS Dly: 10 (0~42)
8050 11:57:38.668173 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8051 11:57:38.671302 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8052 11:57:38.671759
8053 11:57:38.675127 ----->DramcWriteLeveling(PI) begin...
8054 11:57:38.675682 ==
8055 11:57:38.678306 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 11:57:38.685215 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 11:57:38.685772 ==
8058 11:57:38.688070 Write leveling (Byte 0): 21 => 21
8059 11:57:38.691362 Write leveling (Byte 1): 21 => 21
8060 11:57:38.691817 DramcWriteLeveling(PI) end<-----
8061 11:57:38.692357
8062 11:57:38.694993 ==
8063 11:57:38.698116 Dram Type= 6, Freq= 0, CH_1, rank 0
8064 11:57:38.701456 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8065 11:57:38.702011 ==
8066 11:57:38.704718 [Gating] SW mode calibration
8067 11:57:38.711364 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8068 11:57:38.715099 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8069 11:57:38.721126 0 12 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8070 11:57:38.724479 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 11:57:38.728159 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 11:57:38.734562 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 11:57:38.737956 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 11:57:38.740898 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 11:57:38.748217 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8076 11:57:38.751354 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8077 11:57:38.754655 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8078 11:57:38.760982 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8079 11:57:38.764434 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 11:57:38.767377 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 11:57:38.774277 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 11:57:38.777532 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 11:57:38.780868 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8084 11:57:38.787640 0 13 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8085 11:57:38.791036 0 14 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
8086 11:57:38.794547 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 11:57:38.800897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 11:57:38.804054 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 11:57:38.807750 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 11:57:38.813916 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 11:57:38.817138 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 11:57:38.820284 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 11:57:38.827122 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8094 11:57:38.830198 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 11:57:38.833613 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 11:57:38.840444 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:57:38.843429 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:57:38.846993 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:57:38.853473 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:57:38.856929 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:57:38.859917 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:57:38.866651 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:57:38.870263 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:57:38.873550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:57:38.880218 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:57:38.883411 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:57:38.886624 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 11:57:38.892917 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8109 11:57:38.896608 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 11:57:38.899782 Total UI for P1: 0, mck2ui 16
8111 11:57:38.903102 best dqsien dly found for B0: ( 1, 0, 26)
8112 11:57:38.906475 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 11:57:38.909676 Total UI for P1: 0, mck2ui 16
8114 11:57:38.912834 best dqsien dly found for B1: ( 1, 0, 30)
8115 11:57:38.916488 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8116 11:57:38.919607 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8117 11:57:38.920062
8118 11:57:38.922823 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8119 11:57:38.929598 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8120 11:57:38.930126 [Gating] SW calibration Done
8121 11:57:38.930576 ==
8122 11:57:38.932769 Dram Type= 6, Freq= 0, CH_1, rank 0
8123 11:57:38.939743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8124 11:57:38.940497 ==
8125 11:57:38.940937 RX Vref Scan: 0
8126 11:57:38.941281
8127 11:57:38.942924 RX Vref 0 -> 0, step: 1
8128 11:57:38.943392
8129 11:57:38.946226 RX Delay 0 -> 252, step: 8
8130 11:57:38.949446 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8131 11:57:38.952984 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8132 11:57:38.956140 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8133 11:57:38.962816 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8134 11:57:38.965966 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8135 11:57:38.969151 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8136 11:57:38.972418 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8137 11:57:38.976165 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8138 11:57:38.979756 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8139 11:57:38.986208 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8140 11:57:38.989425 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8141 11:57:38.992826 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8142 11:57:38.996011 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8143 11:57:39.002659 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8144 11:57:39.006163 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8145 11:57:39.009049 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8146 11:57:39.009505 ==
8147 11:57:39.012750 Dram Type= 6, Freq= 0, CH_1, rank 0
8148 11:57:39.016049 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8149 11:57:39.016637 ==
8150 11:57:39.018871 DQS Delay:
8151 11:57:39.019500 DQS0 = 0, DQS1 = 0
8152 11:57:39.022353 DQM Delay:
8153 11:57:39.022927 DQM0 = 129, DQM1 = 125
8154 11:57:39.026142 DQ Delay:
8155 11:57:39.029253 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8156 11:57:39.032454 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8157 11:57:39.035613 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8158 11:57:39.038800 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8159 11:57:39.039255
8160 11:57:39.039610
8161 11:57:39.039943 ==
8162 11:57:39.042201 Dram Type= 6, Freq= 0, CH_1, rank 0
8163 11:57:39.045433 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8164 11:57:39.045891 ==
8165 11:57:39.046249
8166 11:57:39.046585
8167 11:57:39.048707 TX Vref Scan disable
8168 11:57:39.051949 == TX Byte 0 ==
8169 11:57:39.055472 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8170 11:57:39.058662 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8171 11:57:39.062230 == TX Byte 1 ==
8172 11:57:39.065412 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8173 11:57:39.068625 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8174 11:57:39.069082 ==
8175 11:57:39.071965 Dram Type= 6, Freq= 0, CH_1, rank 0
8176 11:57:39.078955 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8177 11:57:39.079509 ==
8178 11:57:39.089555
8179 11:57:39.092944 TX Vref early break, caculate TX vref
8180 11:57:39.096246 TX Vref=16, minBit 3, minWin=21, winSum=367
8181 11:57:39.099843 TX Vref=18, minBit 0, minWin=23, winSum=379
8182 11:57:39.102675 TX Vref=20, minBit 3, minWin=22, winSum=387
8183 11:57:39.106194 TX Vref=22, minBit 3, minWin=23, winSum=395
8184 11:57:39.109464 TX Vref=24, minBit 4, minWin=23, winSum=404
8185 11:57:39.115871 TX Vref=26, minBit 1, minWin=24, winSum=412
8186 11:57:39.119125 TX Vref=28, minBit 3, minWin=23, winSum=413
8187 11:57:39.122582 TX Vref=30, minBit 1, minWin=24, winSum=404
8188 11:57:39.125763 TX Vref=32, minBit 0, minWin=24, winSum=399
8189 11:57:39.128914 TX Vref=34, minBit 1, minWin=22, winSum=391
8190 11:57:39.135597 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 26
8191 11:57:39.136148
8192 11:57:39.138950 Final TX Range 0 Vref 26
8193 11:57:39.139404
8194 11:57:39.139761 ==
8195 11:57:39.142432 Dram Type= 6, Freq= 0, CH_1, rank 0
8196 11:57:39.145603 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8197 11:57:39.146062 ==
8198 11:57:39.146422
8199 11:57:39.146757
8200 11:57:39.149194 TX Vref Scan disable
8201 11:57:39.155532 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8202 11:57:39.156102 == TX Byte 0 ==
8203 11:57:39.159214 u2DelayCellOfst[0]=18 cells (5 PI)
8204 11:57:39.162333 u2DelayCellOfst[1]=10 cells (3 PI)
8205 11:57:39.166019 u2DelayCellOfst[2]=0 cells (0 PI)
8206 11:57:39.168571 u2DelayCellOfst[3]=7 cells (2 PI)
8207 11:57:39.172322 u2DelayCellOfst[4]=10 cells (3 PI)
8208 11:57:39.175459 u2DelayCellOfst[5]=18 cells (5 PI)
8209 11:57:39.178757 u2DelayCellOfst[6]=18 cells (5 PI)
8210 11:57:39.182021 u2DelayCellOfst[7]=7 cells (2 PI)
8211 11:57:39.185820 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8212 11:57:39.188962 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8213 11:57:39.192118 == TX Byte 1 ==
8214 11:57:39.192599 u2DelayCellOfst[8]=0 cells (0 PI)
8215 11:57:39.195447 u2DelayCellOfst[9]=7 cells (2 PI)
8216 11:57:39.198531 u2DelayCellOfst[10]=10 cells (3 PI)
8217 11:57:39.202155 u2DelayCellOfst[11]=7 cells (2 PI)
8218 11:57:39.205077 u2DelayCellOfst[12]=18 cells (5 PI)
8219 11:57:39.208757 u2DelayCellOfst[13]=18 cells (5 PI)
8220 11:57:39.212064 u2DelayCellOfst[14]=18 cells (5 PI)
8221 11:57:39.215172 u2DelayCellOfst[15]=18 cells (5 PI)
8222 11:57:39.218223 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8223 11:57:39.225211 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8224 11:57:39.225665 DramC Write-DBI on
8225 11:57:39.226023 ==
8226 11:57:39.228198 Dram Type= 6, Freq= 0, CH_1, rank 0
8227 11:57:39.235430 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8228 11:57:39.235989 ==
8229 11:57:39.236356
8230 11:57:39.236738
8231 11:57:39.237064 TX Vref Scan disable
8232 11:57:39.238730 == TX Byte 0 ==
8233 11:57:39.241711 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8234 11:57:39.245085 == TX Byte 1 ==
8235 11:57:39.248983 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8236 11:57:39.251983 DramC Write-DBI off
8237 11:57:39.252435
8238 11:57:39.252835 [DATLAT]
8239 11:57:39.253171 Freq=1600, CH1 RK0
8240 11:57:39.253500
8241 11:57:39.255124 DATLAT Default: 0xf
8242 11:57:39.255575 0, 0xFFFF, sum = 0
8243 11:57:39.258349 1, 0xFFFF, sum = 0
8244 11:57:39.261891 2, 0xFFFF, sum = 0
8245 11:57:39.262451 3, 0xFFFF, sum = 0
8246 11:57:39.265230 4, 0xFFFF, sum = 0
8247 11:57:39.265785 5, 0xFFFF, sum = 0
8248 11:57:39.268453 6, 0xFFFF, sum = 0
8249 11:57:39.268967 7, 0xFFFF, sum = 0
8250 11:57:39.271647 8, 0xFFFF, sum = 0
8251 11:57:39.272250 9, 0xFFFF, sum = 0
8252 11:57:39.275006 10, 0xFFFF, sum = 0
8253 11:57:39.275511 11, 0xFFFF, sum = 0
8254 11:57:39.278469 12, 0xFFF, sum = 0
8255 11:57:39.279026 13, 0x0, sum = 1
8256 11:57:39.281902 14, 0x0, sum = 2
8257 11:57:39.282461 15, 0x0, sum = 3
8258 11:57:39.284733 16, 0x0, sum = 4
8259 11:57:39.285193 best_step = 14
8260 11:57:39.285552
8261 11:57:39.285883 ==
8262 11:57:39.288295 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 11:57:39.291604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8264 11:57:39.295145 ==
8265 11:57:39.295695 RX Vref Scan: 1
8266 11:57:39.296248
8267 11:57:39.298155 Set Vref Range= 24 -> 127
8268 11:57:39.298606
8269 11:57:39.301808 RX Vref 24 -> 127, step: 1
8270 11:57:39.302370
8271 11:57:39.302735 RX Delay 3 -> 252, step: 4
8272 11:57:39.303072
8273 11:57:39.304719 Set Vref, RX VrefLevel [Byte0]: 24
8274 11:57:39.308271 [Byte1]: 24
8275 11:57:39.312311
8276 11:57:39.312904 Set Vref, RX VrefLevel [Byte0]: 25
8277 11:57:39.315006 [Byte1]: 25
8278 11:57:39.319453
8279 11:57:39.320008 Set Vref, RX VrefLevel [Byte0]: 26
8280 11:57:39.322827 [Byte1]: 26
8281 11:57:39.327379
8282 11:57:39.327925 Set Vref, RX VrefLevel [Byte0]: 27
8283 11:57:39.330995 [Byte1]: 27
8284 11:57:39.335087
8285 11:57:39.335635 Set Vref, RX VrefLevel [Byte0]: 28
8286 11:57:39.338024 [Byte1]: 28
8287 11:57:39.342484
8288 11:57:39.343036 Set Vref, RX VrefLevel [Byte0]: 29
8289 11:57:39.345808 [Byte1]: 29
8290 11:57:39.350361
8291 11:57:39.350908 Set Vref, RX VrefLevel [Byte0]: 30
8292 11:57:39.353599 [Byte1]: 30
8293 11:57:39.357495
8294 11:57:39.357953 Set Vref, RX VrefLevel [Byte0]: 31
8295 11:57:39.360737 [Byte1]: 31
8296 11:57:39.365467
8297 11:57:39.365912 Set Vref, RX VrefLevel [Byte0]: 32
8298 11:57:39.368841 [Byte1]: 32
8299 11:57:39.372857
8300 11:57:39.373302 Set Vref, RX VrefLevel [Byte0]: 33
8301 11:57:39.376330 [Byte1]: 33
8302 11:57:39.380901
8303 11:57:39.381455 Set Vref, RX VrefLevel [Byte0]: 34
8304 11:57:39.384065 [Byte1]: 34
8305 11:57:39.388394
8306 11:57:39.388979 Set Vref, RX VrefLevel [Byte0]: 35
8307 11:57:39.391377 [Byte1]: 35
8308 11:57:39.396427
8309 11:57:39.397010 Set Vref, RX VrefLevel [Byte0]: 36
8310 11:57:39.399463 [Byte1]: 36
8311 11:57:39.403705
8312 11:57:39.404149 Set Vref, RX VrefLevel [Byte0]: 37
8313 11:57:39.407255 [Byte1]: 37
8314 11:57:39.411507
8315 11:57:39.411952 Set Vref, RX VrefLevel [Byte0]: 38
8316 11:57:39.414296 [Byte1]: 38
8317 11:57:39.419188
8318 11:57:39.419747 Set Vref, RX VrefLevel [Byte0]: 39
8319 11:57:39.422190 [Byte1]: 39
8320 11:57:39.426762
8321 11:57:39.427308 Set Vref, RX VrefLevel [Byte0]: 40
8322 11:57:39.429909 [Byte1]: 40
8323 11:57:39.434244
8324 11:57:39.434784 Set Vref, RX VrefLevel [Byte0]: 41
8325 11:57:39.440899 [Byte1]: 41
8326 11:57:39.441444
8327 11:57:39.443913 Set Vref, RX VrefLevel [Byte0]: 42
8328 11:57:39.447639 [Byte1]: 42
8329 11:57:39.448186
8330 11:57:39.450877 Set Vref, RX VrefLevel [Byte0]: 43
8331 11:57:39.453863 [Byte1]: 43
8332 11:57:39.457110
8333 11:57:39.457554 Set Vref, RX VrefLevel [Byte0]: 44
8334 11:57:39.461076 [Byte1]: 44
8335 11:57:39.464842
8336 11:57:39.465289 Set Vref, RX VrefLevel [Byte0]: 45
8337 11:57:39.468074 [Byte1]: 45
8338 11:57:39.472700
8339 11:57:39.473243 Set Vref, RX VrefLevel [Byte0]: 46
8340 11:57:39.475939 [Byte1]: 46
8341 11:57:39.480548
8342 11:57:39.481095 Set Vref, RX VrefLevel [Byte0]: 47
8343 11:57:39.483488 [Byte1]: 47
8344 11:57:39.488126
8345 11:57:39.488709 Set Vref, RX VrefLevel [Byte0]: 48
8346 11:57:39.491186 [Byte1]: 48
8347 11:57:39.495715
8348 11:57:39.496275 Set Vref, RX VrefLevel [Byte0]: 49
8349 11:57:39.499204 [Byte1]: 49
8350 11:57:39.503386
8351 11:57:39.503933 Set Vref, RX VrefLevel [Byte0]: 50
8352 11:57:39.506361 [Byte1]: 50
8353 11:57:39.510831
8354 11:57:39.511378 Set Vref, RX VrefLevel [Byte0]: 51
8355 11:57:39.513990 [Byte1]: 51
8356 11:57:39.518732
8357 11:57:39.519282 Set Vref, RX VrefLevel [Byte0]: 52
8358 11:57:39.522073 [Byte1]: 52
8359 11:57:39.526279
8360 11:57:39.526847 Set Vref, RX VrefLevel [Byte0]: 53
8361 11:57:39.529492 [Byte1]: 53
8362 11:57:39.533941
8363 11:57:39.534488 Set Vref, RX VrefLevel [Byte0]: 54
8364 11:57:39.536901 [Byte1]: 54
8365 11:57:39.541380
8366 11:57:39.541931 Set Vref, RX VrefLevel [Byte0]: 55
8367 11:57:39.544806 [Byte1]: 55
8368 11:57:39.549196
8369 11:57:39.549747 Set Vref, RX VrefLevel [Byte0]: 56
8370 11:57:39.552386 [Byte1]: 56
8371 11:57:39.557374
8372 11:57:39.557921 Set Vref, RX VrefLevel [Byte0]: 57
8373 11:57:39.560028 [Byte1]: 57
8374 11:57:39.564605
8375 11:57:39.565153 Set Vref, RX VrefLevel [Byte0]: 58
8376 11:57:39.567567 [Byte1]: 58
8377 11:57:39.572332
8378 11:57:39.572957 Set Vref, RX VrefLevel [Byte0]: 59
8379 11:57:39.575072 [Byte1]: 59
8380 11:57:39.579972
8381 11:57:39.580561 Set Vref, RX VrefLevel [Byte0]: 60
8382 11:57:39.583357 [Byte1]: 60
8383 11:57:39.587336
8384 11:57:39.587879 Set Vref, RX VrefLevel [Byte0]: 61
8385 11:57:39.590802 [Byte1]: 61
8386 11:57:39.595064
8387 11:57:39.595613 Set Vref, RX VrefLevel [Byte0]: 62
8388 11:57:39.598669 [Byte1]: 62
8389 11:57:39.602518
8390 11:57:39.605753 Set Vref, RX VrefLevel [Byte0]: 63
8391 11:57:39.609035 [Byte1]: 63
8392 11:57:39.609585
8393 11:57:39.612292 Set Vref, RX VrefLevel [Byte0]: 64
8394 11:57:39.615696 [Byte1]: 64
8395 11:57:39.616285
8396 11:57:39.618910 Set Vref, RX VrefLevel [Byte0]: 65
8397 11:57:39.621944 [Byte1]: 65
8398 11:57:39.625663
8399 11:57:39.626132 Set Vref, RX VrefLevel [Byte0]: 66
8400 11:57:39.628722 [Byte1]: 66
8401 11:57:39.633210
8402 11:57:39.633658 Set Vref, RX VrefLevel [Byte0]: 67
8403 11:57:39.636486 [Byte1]: 67
8404 11:57:39.641155
8405 11:57:39.641700 Set Vref, RX VrefLevel [Byte0]: 68
8406 11:57:39.644197 [Byte1]: 68
8407 11:57:39.648726
8408 11:57:39.649274 Set Vref, RX VrefLevel [Byte0]: 69
8409 11:57:39.651730 [Byte1]: 69
8410 11:57:39.656181
8411 11:57:39.656781 Set Vref, RX VrefLevel [Byte0]: 70
8412 11:57:39.659565 [Byte1]: 70
8413 11:57:39.663918
8414 11:57:39.664466 Set Vref, RX VrefLevel [Byte0]: 71
8415 11:57:39.667143 [Byte1]: 71
8416 11:57:39.671608
8417 11:57:39.672159 Set Vref, RX VrefLevel [Byte0]: 72
8418 11:57:39.674695 [Byte1]: 72
8419 11:57:39.679527
8420 11:57:39.680082 Set Vref, RX VrefLevel [Byte0]: 73
8421 11:57:39.682395 [Byte1]: 73
8422 11:57:39.686815
8423 11:57:39.687361 Set Vref, RX VrefLevel [Byte0]: 74
8424 11:57:39.690166 [Byte1]: 74
8425 11:57:39.694445
8426 11:57:39.695008 Final RX Vref Byte 0 = 64 to rank0
8427 11:57:39.698232 Final RX Vref Byte 1 = 55 to rank0
8428 11:57:39.701271 Final RX Vref Byte 0 = 64 to rank1
8429 11:57:39.704607 Final RX Vref Byte 1 = 55 to rank1==
8430 11:57:39.707842 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 11:57:39.714536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8432 11:57:39.715126 ==
8433 11:57:39.715554 DQS Delay:
8434 11:57:39.717450 DQS0 = 0, DQS1 = 0
8435 11:57:39.718123 DQM Delay:
8436 11:57:39.718517 DQM0 = 127, DQM1 = 124
8437 11:57:39.720938 DQ Delay:
8438 11:57:39.724080 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =128
8439 11:57:39.727732 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =124
8440 11:57:39.730660 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8441 11:57:39.734428 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8442 11:57:39.734983
8443 11:57:39.735341
8444 11:57:39.735676
8445 11:57:39.737367 [DramC_TX_OE_Calibration] TA2
8446 11:57:39.740931 Original DQ_B0 (3 6) =30, OEN = 27
8447 11:57:39.744541 Original DQ_B1 (3 6) =30, OEN = 27
8448 11:57:39.747782 24, 0x0, End_B0=24 End_B1=24
8449 11:57:39.748360 25, 0x0, End_B0=25 End_B1=25
8450 11:57:39.750917 26, 0x0, End_B0=26 End_B1=26
8451 11:57:39.754189 27, 0x0, End_B0=27 End_B1=27
8452 11:57:39.757159 28, 0x0, End_B0=28 End_B1=28
8453 11:57:39.760682 29, 0x0, End_B0=29 End_B1=29
8454 11:57:39.761241 30, 0x0, End_B0=30 End_B1=30
8455 11:57:39.764378 31, 0x4141, End_B0=30 End_B1=30
8456 11:57:39.767504 Byte0 end_step=30 best_step=27
8457 11:57:39.770478 Byte1 end_step=30 best_step=27
8458 11:57:39.773820 Byte0 TX OE(2T, 0.5T) = (3, 3)
8459 11:57:39.777241 Byte1 TX OE(2T, 0.5T) = (3, 3)
8460 11:57:39.777694
8461 11:57:39.778049
8462 11:57:39.784318 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8463 11:57:39.787681 CH1 RK0: MR19=303, MR18=2525
8464 11:57:39.793808 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8465 11:57:39.794358
8466 11:57:39.797426 ----->DramcWriteLeveling(PI) begin...
8467 11:57:39.797986 ==
8468 11:57:39.800275 Dram Type= 6, Freq= 0, CH_1, rank 1
8469 11:57:39.804105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8470 11:57:39.804705 ==
8471 11:57:39.807064 Write leveling (Byte 0): 23 => 23
8472 11:57:39.810526 Write leveling (Byte 1): 20 => 20
8473 11:57:39.813404 DramcWriteLeveling(PI) end<-----
8474 11:57:39.813856
8475 11:57:39.814260 ==
8476 11:57:39.816813 Dram Type= 6, Freq= 0, CH_1, rank 1
8477 11:57:39.820293 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8478 11:57:39.820909 ==
8479 11:57:39.823617 [Gating] SW mode calibration
8480 11:57:39.829990 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8481 11:57:39.836754 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8482 11:57:39.840263 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 11:57:39.846920 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8484 11:57:39.850079 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8485 11:57:39.853199 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8486 11:57:39.860084 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8487 11:57:39.863169 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8488 11:57:39.866700 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8489 11:57:39.873122 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8490 11:57:39.876190 0 13 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8491 11:57:39.879697 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8492 11:57:39.886304 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8493 11:57:39.889564 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8494 11:57:39.893044 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8495 11:57:39.899819 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8496 11:57:39.903283 0 13 24 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8497 11:57:39.906201 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8498 11:57:39.912665 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8499 11:57:39.916658 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 11:57:39.919718 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8501 11:57:39.926209 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8502 11:57:39.929372 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8503 11:57:39.932286 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8504 11:57:39.938989 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8505 11:57:39.942618 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8506 11:57:39.945648 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8507 11:57:39.952438 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 11:57:39.955860 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 11:57:39.959250 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 11:57:39.962756 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 11:57:39.969127 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 11:57:39.972130 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 11:57:39.975646 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 11:57:39.982340 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 11:57:39.985459 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 11:57:39.989138 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 11:57:39.995704 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 11:57:39.998793 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 11:57:40.002153 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 11:57:40.008755 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8521 11:57:40.011881 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8522 11:57:40.015219 Total UI for P1: 0, mck2ui 16
8523 11:57:40.018638 best dqsien dly found for B0: ( 1, 0, 24)
8524 11:57:40.022145 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8525 11:57:40.028886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8526 11:57:40.031459 Total UI for P1: 0, mck2ui 16
8527 11:57:40.034955 best dqsien dly found for B1: ( 1, 0, 30)
8528 11:57:40.038509 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8529 11:57:40.041537 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8530 11:57:40.041991
8531 11:57:40.044693 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8532 11:57:40.048298 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8533 11:57:40.051613 [Gating] SW calibration Done
8534 11:57:40.052067 ==
8535 11:57:40.054820 Dram Type= 6, Freq= 0, CH_1, rank 1
8536 11:57:40.058329 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8537 11:57:40.058885 ==
8538 11:57:40.061246 RX Vref Scan: 0
8539 11:57:40.061700
8540 11:57:40.064693 RX Vref 0 -> 0, step: 1
8541 11:57:40.065242
8542 11:57:40.065607 RX Delay 0 -> 252, step: 8
8543 11:57:40.071171 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8544 11:57:40.074682 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8545 11:57:40.077981 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8546 11:57:40.081410 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8547 11:57:40.084911 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8548 11:57:40.091175 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8549 11:57:40.094518 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8550 11:57:40.097786 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8551 11:57:40.101199 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8552 11:57:40.104478 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8553 11:57:40.111214 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8554 11:57:40.114175 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8555 11:57:40.117803 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8556 11:57:40.121190 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8557 11:57:40.124699 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8558 11:57:40.131075 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8559 11:57:40.131630 ==
8560 11:57:40.134238 Dram Type= 6, Freq= 0, CH_1, rank 1
8561 11:57:40.137482 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8562 11:57:40.137940 ==
8563 11:57:40.138297 DQS Delay:
8564 11:57:40.140563 DQS0 = 0, DQS1 = 0
8565 11:57:40.141016 DQM Delay:
8566 11:57:40.144128 DQM0 = 130, DQM1 = 125
8567 11:57:40.144736 DQ Delay:
8568 11:57:40.147163 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =127
8569 11:57:40.150876 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8570 11:57:40.153834 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8571 11:57:40.160658 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8572 11:57:40.161211
8573 11:57:40.161574
8574 11:57:40.161908 ==
8575 11:57:40.164155 Dram Type= 6, Freq= 0, CH_1, rank 1
8576 11:57:40.167495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8577 11:57:40.168048 ==
8578 11:57:40.168408
8579 11:57:40.168791
8580 11:57:40.170571 TX Vref Scan disable
8581 11:57:40.171022 == TX Byte 0 ==
8582 11:57:40.176983 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8583 11:57:40.180904 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8584 11:57:40.181454 == TX Byte 1 ==
8585 11:57:40.187194 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8586 11:57:40.190068 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8587 11:57:40.190527 ==
8588 11:57:40.193733 Dram Type= 6, Freq= 0, CH_1, rank 1
8589 11:57:40.197169 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8590 11:57:40.197726 ==
8591 11:57:40.210578
8592 11:57:40.213824 TX Vref early break, caculate TX vref
8593 11:57:40.217873 TX Vref=16, minBit 0, minWin=21, winSum=377
8594 11:57:40.221024 TX Vref=18, minBit 0, minWin=23, winSum=388
8595 11:57:40.223747 TX Vref=20, minBit 0, minWin=22, winSum=395
8596 11:57:40.227194 TX Vref=22, minBit 0, minWin=23, winSum=404
8597 11:57:40.230861 TX Vref=24, minBit 5, minWin=24, winSum=413
8598 11:57:40.237253 TX Vref=26, minBit 0, minWin=24, winSum=414
8599 11:57:40.240307 TX Vref=28, minBit 0, minWin=24, winSum=419
8600 11:57:40.243934 TX Vref=30, minBit 0, minWin=24, winSum=415
8601 11:57:40.247230 TX Vref=32, minBit 0, minWin=22, winSum=406
8602 11:57:40.250383 TX Vref=34, minBit 0, minWin=23, winSum=397
8603 11:57:40.257427 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 28
8604 11:57:40.257989
8605 11:57:40.260018 Final TX Range 0 Vref 28
8606 11:57:40.260471
8607 11:57:40.260876 ==
8608 11:57:40.263323 Dram Type= 6, Freq= 0, CH_1, rank 1
8609 11:57:40.267063 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8610 11:57:40.267613 ==
8611 11:57:40.267977
8612 11:57:40.268312
8613 11:57:40.269936 TX Vref Scan disable
8614 11:57:40.276661 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8615 11:57:40.277118 == TX Byte 0 ==
8616 11:57:40.280020 u2DelayCellOfst[0]=18 cells (5 PI)
8617 11:57:40.283756 u2DelayCellOfst[1]=7 cells (2 PI)
8618 11:57:40.286963 u2DelayCellOfst[2]=0 cells (0 PI)
8619 11:57:40.289803 u2DelayCellOfst[3]=7 cells (2 PI)
8620 11:57:40.293264 u2DelayCellOfst[4]=7 cells (2 PI)
8621 11:57:40.296656 u2DelayCellOfst[5]=18 cells (5 PI)
8622 11:57:40.300162 u2DelayCellOfst[6]=14 cells (4 PI)
8623 11:57:40.303122 u2DelayCellOfst[7]=3 cells (1 PI)
8624 11:57:40.306536 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8625 11:57:40.310110 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8626 11:57:40.313511 == TX Byte 1 ==
8627 11:57:40.314072 u2DelayCellOfst[8]=0 cells (0 PI)
8628 11:57:40.316644 u2DelayCellOfst[9]=3 cells (1 PI)
8629 11:57:40.320239 u2DelayCellOfst[10]=10 cells (3 PI)
8630 11:57:40.323131 u2DelayCellOfst[11]=3 cells (1 PI)
8631 11:57:40.326189 u2DelayCellOfst[12]=14 cells (4 PI)
8632 11:57:40.329664 u2DelayCellOfst[13]=18 cells (5 PI)
8633 11:57:40.332854 u2DelayCellOfst[14]=18 cells (5 PI)
8634 11:57:40.336241 u2DelayCellOfst[15]=18 cells (5 PI)
8635 11:57:40.339878 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8636 11:57:40.346371 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8637 11:57:40.346930 DramC Write-DBI on
8638 11:57:40.347299 ==
8639 11:57:40.349462 Dram Type= 6, Freq= 0, CH_1, rank 1
8640 11:57:40.353167 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8641 11:57:40.356135 ==
8642 11:57:40.356632
8643 11:57:40.356997
8644 11:57:40.357335 TX Vref Scan disable
8645 11:57:40.359791 == TX Byte 0 ==
8646 11:57:40.363230 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8647 11:57:40.366642 == TX Byte 1 ==
8648 11:57:40.369500 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8649 11:57:40.372905 DramC Write-DBI off
8650 11:57:40.373471
8651 11:57:40.373835 [DATLAT]
8652 11:57:40.374172 Freq=1600, CH1 RK1
8653 11:57:40.374503
8654 11:57:40.375897 DATLAT Default: 0xe
8655 11:57:40.379433 0, 0xFFFF, sum = 0
8656 11:57:40.379995 1, 0xFFFF, sum = 0
8657 11:57:40.382742 2, 0xFFFF, sum = 0
8658 11:57:40.383302 3, 0xFFFF, sum = 0
8659 11:57:40.386006 4, 0xFFFF, sum = 0
8660 11:57:40.386564 5, 0xFFFF, sum = 0
8661 11:57:40.389312 6, 0xFFFF, sum = 0
8662 11:57:40.389869 7, 0xFFFF, sum = 0
8663 11:57:40.392822 8, 0xFFFF, sum = 0
8664 11:57:40.393379 9, 0xFFFF, sum = 0
8665 11:57:40.396021 10, 0xFFFF, sum = 0
8666 11:57:40.396485 11, 0xFFFF, sum = 0
8667 11:57:40.399536 12, 0xF7F, sum = 0
8668 11:57:40.400097 13, 0x0, sum = 1
8669 11:57:40.402401 14, 0x0, sum = 2
8670 11:57:40.402860 15, 0x0, sum = 3
8671 11:57:40.405650 16, 0x0, sum = 4
8672 11:57:40.406111 best_step = 14
8673 11:57:40.406472
8674 11:57:40.406803 ==
8675 11:57:40.408995 Dram Type= 6, Freq= 0, CH_1, rank 1
8676 11:57:40.412261 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8677 11:57:40.416196 ==
8678 11:57:40.416799 RX Vref Scan: 0
8679 11:57:40.417170
8680 11:57:40.418875 RX Vref 0 -> 0, step: 1
8681 11:57:40.419343
8682 11:57:40.422248 RX Delay 3 -> 252, step: 4
8683 11:57:40.425612 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8684 11:57:40.428954 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8685 11:57:40.432161 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8686 11:57:40.439191 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8687 11:57:40.442210 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8688 11:57:40.445433 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8689 11:57:40.448862 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8690 11:57:40.452352 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8691 11:57:40.459169 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8692 11:57:40.462167 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8693 11:57:40.465514 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8694 11:57:40.468865 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8695 11:57:40.472064 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8696 11:57:40.478731 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8697 11:57:40.482378 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8698 11:57:40.485376 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8699 11:57:40.485923 ==
8700 11:57:40.489170 Dram Type= 6, Freq= 0, CH_1, rank 1
8701 11:57:40.492309 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8702 11:57:40.492918 ==
8703 11:57:40.495324 DQS Delay:
8704 11:57:40.495867 DQS0 = 0, DQS1 = 0
8705 11:57:40.498749 DQM Delay:
8706 11:57:40.499307 DQM0 = 127, DQM1 = 123
8707 11:57:40.501999 DQ Delay:
8708 11:57:40.505223 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8709 11:57:40.508618 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =124
8710 11:57:40.512202 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =114
8711 11:57:40.515165 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8712 11:57:40.515715
8713 11:57:40.516075
8714 11:57:40.516413
8715 11:57:40.518111 [DramC_TX_OE_Calibration] TA2
8716 11:57:40.521495 Original DQ_B0 (3 6) =30, OEN = 27
8717 11:57:40.525235 Original DQ_B1 (3 6) =30, OEN = 27
8718 11:57:40.525792 24, 0x0, End_B0=24 End_B1=24
8719 11:57:40.528075 25, 0x0, End_B0=25 End_B1=25
8720 11:57:40.531676 26, 0x0, End_B0=26 End_B1=26
8721 11:57:40.535431 27, 0x0, End_B0=27 End_B1=27
8722 11:57:40.538245 28, 0x0, End_B0=28 End_B1=28
8723 11:57:40.538798 29, 0x0, End_B0=29 End_B1=29
8724 11:57:40.541256 30, 0x0, End_B0=30 End_B1=30
8725 11:57:40.545004 31, 0x5151, End_B0=30 End_B1=30
8726 11:57:40.548017 Byte0 end_step=30 best_step=27
8727 11:57:40.551362 Byte1 end_step=30 best_step=27
8728 11:57:40.555039 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 11:57:40.555599 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 11:57:40.555967
8731 11:57:40.557959
8732 11:57:40.564827 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8733 11:57:40.567917 CH1 RK1: MR19=303, MR18=1F1F
8734 11:57:40.574842 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8735 11:57:40.577768 [RxdqsGatingPostProcess] freq 1600
8736 11:57:40.581382 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8737 11:57:40.584692 Pre-setting of DQS Precalculation
8738 11:57:40.591483 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8739 11:57:40.597900 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8740 11:57:40.604503 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8741 11:57:40.605107
8742 11:57:40.605474
8743 11:57:40.608082 [Calibration Summary] 3200 Mbps
8744 11:57:40.608687 CH 0, Rank 0
8745 11:57:40.611427 SW Impedance : PASS
8746 11:57:40.614430 DUTY Scan : NO K
8747 11:57:40.614994 ZQ Calibration : PASS
8748 11:57:40.617641 Jitter Meter : NO K
8749 11:57:40.621336 CBT Training : PASS
8750 11:57:40.621892 Write leveling : PASS
8751 11:57:40.624405 RX DQS gating : PASS
8752 11:57:40.627351 RX DQ/DQS(RDDQC) : PASS
8753 11:57:40.627811 TX DQ/DQS : PASS
8754 11:57:40.631255 RX DATLAT : PASS
8755 11:57:40.634073 RX DQ/DQS(Engine): PASS
8756 11:57:40.634527 TX OE : PASS
8757 11:57:40.634892 All Pass.
8758 11:57:40.635228
8759 11:57:40.637509 CH 0, Rank 1
8760 11:57:40.640725 SW Impedance : PASS
8761 11:57:40.641178 DUTY Scan : NO K
8762 11:57:40.644197 ZQ Calibration : PASS
8763 11:57:40.644797 Jitter Meter : NO K
8764 11:57:40.647617 CBT Training : PASS
8765 11:57:40.650649 Write leveling : PASS
8766 11:57:40.651108 RX DQS gating : PASS
8767 11:57:40.654569 RX DQ/DQS(RDDQC) : PASS
8768 11:57:40.657564 TX DQ/DQS : PASS
8769 11:57:40.658120 RX DATLAT : PASS
8770 11:57:40.660840 RX DQ/DQS(Engine): PASS
8771 11:57:40.664082 TX OE : PASS
8772 11:57:40.664578 All Pass.
8773 11:57:40.664947
8774 11:57:40.665282 CH 1, Rank 0
8775 11:57:40.667220 SW Impedance : PASS
8776 11:57:40.670453 DUTY Scan : NO K
8777 11:57:40.670908 ZQ Calibration : PASS
8778 11:57:40.673940 Jitter Meter : NO K
8779 11:57:40.677083 CBT Training : PASS
8780 11:57:40.677538 Write leveling : PASS
8781 11:57:40.680556 RX DQS gating : PASS
8782 11:57:40.683817 RX DQ/DQS(RDDQC) : PASS
8783 11:57:40.684270 TX DQ/DQS : PASS
8784 11:57:40.687358 RX DATLAT : PASS
8785 11:57:40.690699 RX DQ/DQS(Engine): PASS
8786 11:57:40.691272 TX OE : PASS
8787 11:57:40.691643 All Pass.
8788 11:57:40.693969
8789 11:57:40.694520 CH 1, Rank 1
8790 11:57:40.697297 SW Impedance : PASS
8791 11:57:40.697850 DUTY Scan : NO K
8792 11:57:40.700432 ZQ Calibration : PASS
8793 11:57:40.701023 Jitter Meter : NO K
8794 11:57:40.704238 CBT Training : PASS
8795 11:57:40.707333 Write leveling : PASS
8796 11:57:40.707885 RX DQS gating : PASS
8797 11:57:40.710535 RX DQ/DQS(RDDQC) : PASS
8798 11:57:40.713840 TX DQ/DQS : PASS
8799 11:57:40.714399 RX DATLAT : PASS
8800 11:57:40.716828 RX DQ/DQS(Engine): PASS
8801 11:57:40.720396 TX OE : PASS
8802 11:57:40.720997 All Pass.
8803 11:57:40.721368
8804 11:57:40.723514 DramC Write-DBI on
8805 11:57:40.724064 PER_BANK_REFRESH: Hybrid Mode
8806 11:57:40.727210 TX_TRACKING: ON
8807 11:57:40.736823 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8808 11:57:40.743444 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8809 11:57:40.750469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8810 11:57:40.753355 [FAST_K] Save calibration result to emmc
8811 11:57:40.756687 sync common calibartion params.
8812 11:57:40.760187 sync cbt_mode0:0, 1:0
8813 11:57:40.761039 dram_init: ddr_geometry: 0
8814 11:57:40.763236 dram_init: ddr_geometry: 0
8815 11:57:40.766637 dram_init: ddr_geometry: 0
8816 11:57:40.770028 0:dram_rank_size:80000000
8817 11:57:40.770497 1:dram_rank_size:80000000
8818 11:57:40.776743 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8819 11:57:40.780087 DFS_SHUFFLE_HW_MODE: ON
8820 11:57:40.783181 dramc_set_vcore_voltage set vcore to 725000
8821 11:57:40.783642 Read voltage for 1600, 0
8822 11:57:40.786830 Vio18 = 0
8823 11:57:40.787386 Vcore = 725000
8824 11:57:40.787752 Vdram = 0
8825 11:57:40.789764 Vddq = 0
8826 11:57:40.790220 Vmddr = 0
8827 11:57:40.793358 switch to 3200 Mbps bootup
8828 11:57:40.793917 [DramcRunTimeConfig]
8829 11:57:40.794285 PHYPLL
8830 11:57:40.796765 DPM_CONTROL_AFTERK: ON
8831 11:57:40.800064 PER_BANK_REFRESH: ON
8832 11:57:40.800679 REFRESH_OVERHEAD_REDUCTION: ON
8833 11:57:40.803388 CMD_PICG_NEW_MODE: OFF
8834 11:57:40.806579 XRTWTW_NEW_MODE: ON
8835 11:57:40.807137 XRTRTR_NEW_MODE: ON
8836 11:57:40.809805 TX_TRACKING: ON
8837 11:57:40.810366 RDSEL_TRACKING: OFF
8838 11:57:40.813268 DQS Precalculation for DVFS: ON
8839 11:57:40.813852 RX_TRACKING: OFF
8840 11:57:40.816434 HW_GATING DBG: ON
8841 11:57:40.816953 ZQCS_ENABLE_LP4: ON
8842 11:57:40.819780 RX_PICG_NEW_MODE: ON
8843 11:57:40.823138 TX_PICG_NEW_MODE: ON
8844 11:57:40.823697 ENABLE_RX_DCM_DPHY: ON
8845 11:57:40.826365 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8846 11:57:40.829636 DUMMY_READ_FOR_TRACKING: OFF
8847 11:57:40.833059 !!! SPM_CONTROL_AFTERK: OFF
8848 11:57:40.836353 !!! SPM could not control APHY
8849 11:57:40.836896 IMPEDANCE_TRACKING: ON
8850 11:57:40.839700 TEMP_SENSOR: ON
8851 11:57:40.840254 HW_SAVE_FOR_SR: OFF
8852 11:57:40.842877 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8853 11:57:40.846482 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8854 11:57:40.849938 Read ODT Tracking: ON
8855 11:57:40.850509 Refresh Rate DeBounce: ON
8856 11:57:40.853001 DFS_NO_QUEUE_FLUSH: ON
8857 11:57:40.856181 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8858 11:57:40.859502 ENABLE_DFS_RUNTIME_MRW: OFF
8859 11:57:40.860052 DDR_RESERVE_NEW_MODE: ON
8860 11:57:40.863062 MR_CBT_SWITCH_FREQ: ON
8861 11:57:40.866227 =========================
8862 11:57:40.884369 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8863 11:57:40.887675 dram_init: ddr_geometry: 0
8864 11:57:40.905271 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8865 11:57:40.908963 dram_init: dram init end (result: 0)
8866 11:57:40.915569 DRAM-K: Full calibration passed in 23423 msecs
8867 11:57:40.918746 MRC: failed to locate region type 0.
8868 11:57:40.919297 DRAM rank0 size:0x80000000,
8869 11:57:40.922343 DRAM rank1 size=0x80000000
8870 11:57:40.932029 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8871 11:57:40.939299 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8872 11:57:40.945359 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8873 11:57:40.951998 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8874 11:57:40.955670 DRAM rank0 size:0x80000000,
8875 11:57:40.958735 DRAM rank1 size=0x80000000
8876 11:57:40.959280 CBMEM:
8877 11:57:40.962539 IMD: root @ 0xfffff000 254 entries.
8878 11:57:40.965727 IMD: root @ 0xffffec00 62 entries.
8879 11:57:40.969032 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8880 11:57:40.972101 WARNING: RO_VPD is uninitialized or empty.
8881 11:57:40.978481 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8882 11:57:40.985158 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8883 11:57:40.998249 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8884 11:57:41.009385 BS: romstage times (exec / console): total (unknown) / 22960 ms
8885 11:57:41.009951
8886 11:57:41.010319
8887 11:57:41.019371 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8888 11:57:41.022768 ARM64: Exception handlers installed.
8889 11:57:41.025494 ARM64: Testing exception
8890 11:57:41.029231 ARM64: Done test exception
8891 11:57:41.029940 Enumerating buses...
8892 11:57:41.032247 Show all devs... Before device enumeration.
8893 11:57:41.035771 Root Device: enabled 1
8894 11:57:41.039151 CPU_CLUSTER: 0: enabled 1
8895 11:57:41.039702 CPU: 00: enabled 1
8896 11:57:41.042425 Compare with tree...
8897 11:57:41.042978 Root Device: enabled 1
8898 11:57:41.045820 CPU_CLUSTER: 0: enabled 1
8899 11:57:41.048765 CPU: 00: enabled 1
8900 11:57:41.049222 Root Device scanning...
8901 11:57:41.052546 scan_static_bus for Root Device
8902 11:57:41.056006 CPU_CLUSTER: 0 enabled
8903 11:57:41.058903 scan_static_bus for Root Device done
8904 11:57:41.062261 scan_bus: bus Root Device finished in 8 msecs
8905 11:57:41.062827 done
8906 11:57:41.068739 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8907 11:57:41.072480 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8908 11:57:41.078950 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8909 11:57:41.082066 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8910 11:57:41.085048 Allocating resources...
8911 11:57:41.088650 Reading resources...
8912 11:57:41.092109 Root Device read_resources bus 0 link: 0
8913 11:57:41.095471 DRAM rank0 size:0x80000000,
8914 11:57:41.096023 DRAM rank1 size=0x80000000
8915 11:57:41.098646 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8916 11:57:41.101548 CPU: 00 missing read_resources
8917 11:57:41.108316 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8918 11:57:41.111586 Root Device read_resources bus 0 link: 0 done
8919 11:57:41.112152 Done reading resources.
8920 11:57:41.118375 Show resources in subtree (Root Device)...After reading.
8921 11:57:41.121572 Root Device child on link 0 CPU_CLUSTER: 0
8922 11:57:41.124932 CPU_CLUSTER: 0 child on link 0 CPU: 00
8923 11:57:41.134931 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8924 11:57:41.135490 CPU: 00
8925 11:57:41.137976 Root Device assign_resources, bus 0 link: 0
8926 11:57:41.141246 CPU_CLUSTER: 0 missing set_resources
8927 11:57:41.148281 Root Device assign_resources, bus 0 link: 0 done
8928 11:57:41.148911 Done setting resources.
8929 11:57:41.154527 Show resources in subtree (Root Device)...After assigning values.
8930 11:57:41.158095 Root Device child on link 0 CPU_CLUSTER: 0
8931 11:57:41.161616 CPU_CLUSTER: 0 child on link 0 CPU: 00
8932 11:57:41.171432 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8933 11:57:41.171995 CPU: 00
8934 11:57:41.175019 Done allocating resources.
8935 11:57:41.181117 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8936 11:57:41.181586 Enabling resources...
8937 11:57:41.181953 done.
8938 11:57:41.187676 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8939 11:57:41.188226 Initializing devices...
8940 11:57:41.191409 Root Device init
8941 11:57:41.191964 init hardware done!
8942 11:57:41.194535 0x00000018: ctrlr->caps
8943 11:57:41.198074 52.000 MHz: ctrlr->f_max
8944 11:57:41.198642 0.400 MHz: ctrlr->f_min
8945 11:57:41.201190 0x40ff8080: ctrlr->voltages
8946 11:57:41.204396 sclk: 390625
8947 11:57:41.204907 Bus Width = 1
8948 11:57:41.205271 sclk: 390625
8949 11:57:41.207664 Bus Width = 1
8950 11:57:41.208221 Early init status = 3
8951 11:57:41.214563 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8952 11:57:41.217704 in-header: 03 fc 00 00 01 00 00 00
8953 11:57:41.220546 in-data: 00
8954 11:57:41.223757 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8955 11:57:41.229849 in-header: 03 fd 00 00 00 00 00 00
8956 11:57:41.233079 in-data:
8957 11:57:41.236224 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8958 11:57:41.240670 in-header: 03 fc 00 00 01 00 00 00
8959 11:57:41.243907 in-data: 00
8960 11:57:41.247562 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8961 11:57:41.253222 in-header: 03 fd 00 00 00 00 00 00
8962 11:57:41.256578 in-data:
8963 11:57:41.260049 [SSUSB] Setting up USB HOST controller...
8964 11:57:41.263403 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8965 11:57:41.266825 [SSUSB] phy power-on done.
8966 11:57:41.269875 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8967 11:57:41.276745 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8968 11:57:41.279691 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8969 11:57:41.286127 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8970 11:57:41.293069 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8971 11:57:41.299597 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8972 11:57:41.306269 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8973 11:57:41.312738 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8974 11:57:41.316331 SPM: binary array size = 0x9dc
8975 11:57:41.319514 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8976 11:57:41.326062 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8977 11:57:41.333016 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8978 11:57:41.335965 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8979 11:57:41.342723 configure_display: Starting display init
8980 11:57:41.376257 anx7625_power_on_init: Init interface.
8981 11:57:41.379302 anx7625_disable_pd_protocol: Disabled PD feature.
8982 11:57:41.382905 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8983 11:57:41.410946 anx7625_start_dp_work: Secure OCM version=00
8984 11:57:41.413794 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8985 11:57:41.428990 sp_tx_get_edid_block: EDID Block = 1
8986 11:57:41.531582 Extracted contents:
8987 11:57:41.534775 header: 00 ff ff ff ff ff ff 00
8988 11:57:41.538222 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8989 11:57:41.541218 version: 01 04
8990 11:57:41.544499 basic params: 95 1f 11 78 0a
8991 11:57:41.548078 chroma info: 76 90 94 55 54 90 27 21 50 54
8992 11:57:41.551340 established: 00 00 00
8993 11:57:41.557876 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8994 11:57:41.564613 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8995 11:57:41.567734 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8996 11:57:41.574062 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8997 11:57:41.580996 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8998 11:57:41.584187 extensions: 00
8999 11:57:41.584787 checksum: fb
9000 11:57:41.585160
9001 11:57:41.590717 Manufacturer: IVO Model 57d Serial Number 0
9002 11:57:41.591269 Made week 0 of 2020
9003 11:57:41.594303 EDID version: 1.4
9004 11:57:41.594863 Digital display
9005 11:57:41.597273 6 bits per primary color channel
9006 11:57:41.597735 DisplayPort interface
9007 11:57:41.601126 Maximum image size: 31 cm x 17 cm
9008 11:57:41.604217 Gamma: 220%
9009 11:57:41.604805 Check DPMS levels
9010 11:57:41.607463 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9011 11:57:41.614158 First detailed timing is preferred timing
9012 11:57:41.614729 Established timings supported:
9013 11:57:41.617351 Standard timings supported:
9014 11:57:41.620629 Detailed timings
9015 11:57:41.623894 Hex of detail: 383680a07038204018303c0035ae10000019
9016 11:57:41.630754 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9017 11:57:41.633716 0780 0798 07c8 0820 hborder 0
9018 11:57:41.637357 0438 043b 0447 0458 vborder 0
9019 11:57:41.640637 -hsync -vsync
9020 11:57:41.641190 Did detailed timing
9021 11:57:41.647268 Hex of detail: 000000000000000000000000000000000000
9022 11:57:41.650525 Manufacturer-specified data, tag 0
9023 11:57:41.653980 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9024 11:57:41.657066 ASCII string: InfoVision
9025 11:57:41.660662 Hex of detail: 000000fe00523134304e574635205248200a
9026 11:57:41.663753 ASCII string: R140NWF5 RH
9027 11:57:41.664306 Checksum
9028 11:57:41.667317 Checksum: 0xfb (valid)
9029 11:57:41.670456 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9030 11:57:41.673606 DSI data_rate: 832800000 bps
9031 11:57:41.680044 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9032 11:57:41.683659 anx7625_parse_edid: pixelclock(138800).
9033 11:57:41.686615 hactive(1920), hsync(48), hfp(24), hbp(88)
9034 11:57:41.690223 vactive(1080), vsync(12), vfp(3), vbp(17)
9035 11:57:41.693586 anx7625_dsi_config: config dsi.
9036 11:57:41.700121 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9037 11:57:41.713345 anx7625_dsi_config: success to config DSI
9038 11:57:41.717056 anx7625_dp_start: MIPI phy setup OK.
9039 11:57:41.720211 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9040 11:57:41.723577 mtk_ddp_mode_set invalid vrefresh 60
9041 11:57:41.727428 main_disp_path_setup
9042 11:57:41.727978 ovl_layer_smi_id_en
9043 11:57:41.730519 ovl_layer_smi_id_en
9044 11:57:41.731074 ccorr_config
9045 11:57:41.731436 aal_config
9046 11:57:41.733730 gamma_config
9047 11:57:41.734185 postmask_config
9048 11:57:41.736559 dither_config
9049 11:57:41.740078 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9050 11:57:41.746562 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9051 11:57:41.750321 Root Device init finished in 555 msecs
9052 11:57:41.753220 CPU_CLUSTER: 0 init
9053 11:57:41.760201 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9054 11:57:41.763812 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9055 11:57:41.766812 APU_MBOX 0x190000b0 = 0x10001
9056 11:57:41.769798 APU_MBOX 0x190001b0 = 0x10001
9057 11:57:41.773152 APU_MBOX 0x190005b0 = 0x10001
9058 11:57:41.776763 APU_MBOX 0x190006b0 = 0x10001
9059 11:57:41.779761 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9060 11:57:41.792776 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9061 11:57:41.804939 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9062 11:57:41.811608 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9063 11:57:41.823124 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9064 11:57:41.832682 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9065 11:57:41.835495 CPU_CLUSTER: 0 init finished in 81 msecs
9066 11:57:41.838951 Devices initialized
9067 11:57:41.842327 Show all devs... After init.
9068 11:57:41.842887 Root Device: enabled 1
9069 11:57:41.845346 CPU_CLUSTER: 0: enabled 1
9070 11:57:41.849148 CPU: 00: enabled 1
9071 11:57:41.852361 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9072 11:57:41.855127 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9073 11:57:41.858837 ELOG: NV offset 0x57f000 size 0x1000
9074 11:57:41.865378 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9075 11:57:41.872285 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9076 11:57:41.875008 ELOG: Event(17) added with size 13 at 2023-11-23 11:57:43 UTC
9077 11:57:41.881587 out: cmd=0x121: 03 db 21 01 00 00 00 00
9078 11:57:41.884931 in-header: 03 f0 00 00 2c 00 00 00
9079 11:57:41.895013 in-data: 73 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9080 11:57:41.901703 ELOG: Event(A1) added with size 10 at 2023-11-23 11:57:43 UTC
9081 11:57:41.908555 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9082 11:57:41.914964 ELOG: Event(A0) added with size 9 at 2023-11-23 11:57:43 UTC
9083 11:57:41.918389 elog_add_boot_reason: Logged dev mode boot
9084 11:57:41.925069 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9085 11:57:41.925624 Finalize devices...
9086 11:57:41.928043 Devices finalized
9087 11:57:41.931585 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9088 11:57:41.934832 Writing coreboot table at 0xffe64000
9089 11:57:41.937841 0. 000000000010a000-0000000000113fff: RAMSTAGE
9090 11:57:41.944460 1. 0000000040000000-00000000400fffff: RAM
9091 11:57:41.947736 2. 0000000040100000-000000004032afff: RAMSTAGE
9092 11:57:41.951504 3. 000000004032b000-00000000545fffff: RAM
9093 11:57:41.954414 4. 0000000054600000-000000005465ffff: BL31
9094 11:57:41.958200 5. 0000000054660000-00000000ffe63fff: RAM
9095 11:57:41.964681 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9096 11:57:41.968166 7. 0000000100000000-000000013fffffff: RAM
9097 11:57:41.971373 Passing 5 GPIOs to payload:
9098 11:57:41.974420 NAME | PORT | POLARITY | VALUE
9099 11:57:41.981001 EC in RW | 0x000000aa | low | undefined
9100 11:57:41.984317 EC interrupt | 0x00000005 | low | undefined
9101 11:57:41.987885 TPM interrupt | 0x000000ab | high | undefined
9102 11:57:41.994728 SD card detect | 0x00000011 | high | undefined
9103 11:57:41.997586 speaker enable | 0x00000093 | high | undefined
9104 11:57:42.000991 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9105 11:57:42.004440 in-header: 03 f8 00 00 02 00 00 00
9106 11:57:42.007695 in-data: 03 00
9107 11:57:42.011368 ADC[4]: Raw value=668590 ID=5
9108 11:57:42.011934 ADC[3]: Raw value=212549 ID=1
9109 11:57:42.014540 RAM Code: 0x51
9110 11:57:42.017450 ADC[6]: Raw value=74778 ID=0
9111 11:57:42.017944 ADC[5]: Raw value=211812 ID=1
9112 11:57:42.021279 SKU Code: 0x1
9113 11:57:42.024387 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9ab
9114 11:57:42.027419 coreboot table: 964 bytes.
9115 11:57:42.031326 IMD ROOT 0. 0xfffff000 0x00001000
9116 11:57:42.034332 IMD SMALL 1. 0xffffe000 0x00001000
9117 11:57:42.037577 RO MCACHE 2. 0xffffc000 0x00001104
9118 11:57:42.040635 CONSOLE 3. 0xfff7c000 0x00080000
9119 11:57:42.044050 FMAP 4. 0xfff7b000 0x00000452
9120 11:57:42.047416 TIME STAMP 5. 0xfff7a000 0x00000910
9121 11:57:42.050817 VBOOT WORK 6. 0xfff66000 0x00014000
9122 11:57:42.054148 RAMOOPS 7. 0xffe66000 0x00100000
9123 11:57:42.057131 COREBOOT 8. 0xffe64000 0x00002000
9124 11:57:42.060732 IMD small region:
9125 11:57:42.063740 IMD ROOT 0. 0xffffec00 0x00000400
9126 11:57:42.067585 VPD 1. 0xffffeb80 0x0000006c
9127 11:57:42.070687 MMC STATUS 2. 0xffffeb60 0x00000004
9128 11:57:42.073930 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9129 11:57:42.077058 Probing TPM: done!
9130 11:57:42.080913 Connected to device vid:did:rid of 1ae0:0028:00
9131 11:57:42.090990 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9132 11:57:42.094435 Initialized TPM device CR50 revision 0
9133 11:57:42.098037 Checking cr50 for pending updates
9134 11:57:42.101680 Reading cr50 TPM mode
9135 11:57:42.110976 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9136 11:57:42.117164 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9137 11:57:42.157128 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9138 11:57:42.160453 Checking segment from ROM address 0x40100000
9139 11:57:42.163666 Checking segment from ROM address 0x4010001c
9140 11:57:42.170539 Loading segment from ROM address 0x40100000
9141 11:57:42.171108 code (compression=0)
9142 11:57:42.180415 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9143 11:57:42.187289 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9144 11:57:42.187858 it's not compressed!
9145 11:57:42.194071 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9146 11:57:42.197222 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9147 11:57:42.217553 Loading segment from ROM address 0x4010001c
9148 11:57:42.218123 Entry Point 0x80000000
9149 11:57:42.220693 Loaded segments
9150 11:57:42.224257 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9151 11:57:42.231109 Jumping to boot code at 0x80000000(0xffe64000)
9152 11:57:42.237783 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9153 11:57:42.244362 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9154 11:57:42.251929 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9155 11:57:42.255404 Checking segment from ROM address 0x40100000
9156 11:57:42.258726 Checking segment from ROM address 0x4010001c
9157 11:57:42.265544 Loading segment from ROM address 0x40100000
9158 11:57:42.266118 code (compression=1)
9159 11:57:42.271920 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9160 11:57:42.281697 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9161 11:57:42.282323 using LZMA
9162 11:57:42.290330 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9163 11:57:42.297131 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9164 11:57:42.300368 Loading segment from ROM address 0x4010001c
9165 11:57:42.300970 Entry Point 0x54601000
9166 11:57:42.303932 Loaded segments
9167 11:57:42.306934 NOTICE: MT8192 bl31_setup
9168 11:57:42.314123 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9169 11:57:42.317343 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9170 11:57:42.320580 WARNING: region 0:
9171 11:57:42.324162 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9172 11:57:42.324771 WARNING: region 1:
9173 11:57:42.330995 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9174 11:57:42.334137 WARNING: region 2:
9175 11:57:42.337386 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9176 11:57:42.340430 WARNING: region 3:
9177 11:57:42.344075 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9178 11:57:42.347737 WARNING: region 4:
9179 11:57:42.353761 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9180 11:57:42.354242 WARNING: region 5:
9181 11:57:42.357214 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9182 11:57:42.360963 WARNING: region 6:
9183 11:57:42.364223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9184 11:57:42.364840 WARNING: region 7:
9185 11:57:42.370666 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9186 11:57:42.377048 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9187 11:57:42.380450 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9188 11:57:42.383953 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9189 11:57:42.390518 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9190 11:57:42.393897 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9191 11:57:42.397241 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9192 11:57:42.404138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9193 11:57:42.407269 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9194 11:57:42.413732 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9195 11:57:42.417275 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9196 11:57:42.420337 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9197 11:57:42.427173 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9198 11:57:42.430850 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9199 11:57:42.434187 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9200 11:57:42.440684 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9201 11:57:42.444098 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9202 11:57:42.447391 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9203 11:57:42.453770 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9204 11:57:42.457076 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9205 11:57:42.463940 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9206 11:57:42.467146 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9207 11:57:42.470622 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9208 11:57:42.477355 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9209 11:57:42.480636 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9210 11:57:42.487442 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9211 11:57:42.490695 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9212 11:57:42.493625 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9213 11:57:42.500826 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9214 11:57:42.503573 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9215 11:57:42.510565 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9216 11:57:42.514025 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9217 11:57:42.517115 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9218 11:57:42.523756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9219 11:57:42.527135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9220 11:57:42.530259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9221 11:57:42.533987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9222 11:57:42.540323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9223 11:57:42.543776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9224 11:57:42.547091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9225 11:57:42.550720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9226 11:57:42.553749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9227 11:57:42.560582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9228 11:57:42.563992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9229 11:57:42.566972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9230 11:57:42.573495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9231 11:57:42.577077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9232 11:57:42.580294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9233 11:57:42.583380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9234 11:57:42.590580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9235 11:57:42.593730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9236 11:57:42.600262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9237 11:57:42.603797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9238 11:57:42.607264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9239 11:57:42.613992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9240 11:57:42.617046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9241 11:57:42.623486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9242 11:57:42.627001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9243 11:57:42.634116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9244 11:57:42.637074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9245 11:57:42.643818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9246 11:57:42.646905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9247 11:57:42.650033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9248 11:57:42.657191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9249 11:57:42.660479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9250 11:57:42.666671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9251 11:57:42.670195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9252 11:57:42.676861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9253 11:57:42.680381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9254 11:57:42.683198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9255 11:57:42.690076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9256 11:57:42.693413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9257 11:57:42.700030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9258 11:57:42.703618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9259 11:57:42.710182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9260 11:57:42.713756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9261 11:57:42.716896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9262 11:57:42.723572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9263 11:57:42.726981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9264 11:57:42.733508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9265 11:57:42.736988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9266 11:57:42.743796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9267 11:57:42.747241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9268 11:57:42.750135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9269 11:57:42.756705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9270 11:57:42.760390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9271 11:57:42.766881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9272 11:57:42.770214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9273 11:57:42.776812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9274 11:57:42.780400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9275 11:57:42.783279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9276 11:57:42.790485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9277 11:57:42.793867 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9278 11:57:42.800236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9279 11:57:42.803830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9280 11:57:42.810572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9281 11:57:42.813263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9282 11:57:42.816844 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9283 11:57:42.823455 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9284 11:57:42.826490 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9285 11:57:42.830023 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9286 11:57:42.833787 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9287 11:57:42.839728 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9288 11:57:42.843815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9289 11:57:42.849767 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9290 11:57:42.853270 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9291 11:57:42.856584 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9292 11:57:42.863302 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9293 11:57:42.866378 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9294 11:57:42.873099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9295 11:57:42.876612 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9296 11:57:42.879980 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9297 11:57:42.886755 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9298 11:57:42.890557 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9299 11:57:42.896293 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9300 11:57:42.900493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9301 11:57:42.903267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9302 11:57:42.906637 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9303 11:57:42.913450 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9304 11:57:42.916862 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9305 11:57:42.919973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9306 11:57:42.926582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9307 11:57:42.929962 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9308 11:57:42.933233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9309 11:57:42.936719 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9310 11:57:42.943250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9311 11:57:42.946671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9312 11:57:42.953104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9313 11:57:42.956365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9314 11:57:42.960020 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9315 11:57:42.966565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9316 11:57:42.969934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9317 11:57:42.973468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9318 11:57:42.980263 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9319 11:57:42.983207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9320 11:57:42.990589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9321 11:57:42.993247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9322 11:57:42.996927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9323 11:57:43.003590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9324 11:57:43.006770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9325 11:57:43.013198 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9326 11:57:43.016679 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9327 11:57:43.020419 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9328 11:57:43.026381 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9329 11:57:43.029912 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9330 11:57:43.036630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9331 11:57:43.039771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9332 11:57:43.043075 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9333 11:57:43.049667 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9334 11:57:43.052739 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9335 11:57:43.059651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9336 11:57:43.063376 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9337 11:57:43.066752 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9338 11:57:43.073233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9339 11:57:43.076250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9340 11:57:43.082737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9341 11:57:43.086569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9342 11:57:43.089585 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9343 11:57:43.096301 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9344 11:57:43.099437 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9345 11:57:43.103484 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9346 11:57:43.109456 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9347 11:57:43.112788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9348 11:57:43.119466 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9349 11:57:43.122790 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9350 11:57:43.126358 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9351 11:57:43.132757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9352 11:57:43.136148 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9353 11:57:43.142295 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9354 11:57:43.145576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9355 11:57:43.148964 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9356 11:57:43.155690 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9357 11:57:43.158693 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9358 11:57:43.165998 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9359 11:57:43.168888 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9360 11:57:43.171958 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9361 11:57:43.178855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9362 11:57:43.181976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9363 11:57:43.188683 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9364 11:57:43.192484 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9365 11:57:43.195791 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9366 11:57:43.201986 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9367 11:57:43.205196 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9368 11:57:43.212307 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9369 11:57:43.215295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9370 11:57:43.218549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9371 11:57:43.225130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9372 11:57:43.228743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9373 11:57:43.234910 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9374 11:57:43.238562 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9375 11:57:43.241874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9376 11:57:43.248575 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9377 11:57:43.251953 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9378 11:57:43.258866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9379 11:57:43.261686 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9380 11:57:43.264835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9381 11:57:43.271548 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9382 11:57:43.274915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9383 11:57:43.281256 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9384 11:57:43.284563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9385 11:57:43.291710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9386 11:57:43.294973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9387 11:57:43.298246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9388 11:57:43.305116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9389 11:57:43.308210 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9390 11:57:43.314655 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9391 11:57:43.318192 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9392 11:57:43.324846 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9393 11:57:43.328352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9394 11:57:43.331451 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9395 11:57:43.338625 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9396 11:57:43.341308 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9397 11:57:43.348222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9398 11:57:43.351101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9399 11:57:43.355008 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9400 11:57:43.361064 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9401 11:57:43.365009 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9402 11:57:43.371268 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9403 11:57:43.374524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9404 11:57:43.377747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9405 11:57:43.384425 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9406 11:57:43.387665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9407 11:57:43.394574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9408 11:57:43.397843 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9409 11:57:43.404231 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9410 11:57:43.407645 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9411 11:57:43.411137 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9412 11:57:43.417447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9413 11:57:43.420956 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9414 11:57:43.427660 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9415 11:57:43.430744 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9416 11:57:43.434309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9417 11:57:43.437494 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9418 11:57:43.444216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9419 11:57:43.447730 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9420 11:57:43.450864 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9421 11:57:43.457492 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9422 11:57:43.460856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9423 11:57:43.463916 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9424 11:57:43.470923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9425 11:57:43.473777 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9426 11:57:43.477570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9427 11:57:43.483705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9428 11:57:43.487331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9429 11:57:43.490288 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9430 11:57:43.497113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9431 11:57:43.500642 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9432 11:57:43.507476 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9433 11:57:43.510270 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9434 11:57:43.514040 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9435 11:57:43.520250 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9436 11:57:43.523887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9437 11:57:43.526922 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9438 11:57:43.533744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9439 11:57:43.537067 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9440 11:57:43.543488 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9441 11:57:43.546893 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9442 11:57:43.550173 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9443 11:57:43.556814 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9444 11:57:43.560170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9445 11:57:43.563265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9446 11:57:43.569877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9447 11:57:43.573422 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9448 11:57:43.580333 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9449 11:57:43.583330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9450 11:57:43.586413 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9451 11:57:43.593166 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9452 11:57:43.596312 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9453 11:57:43.599755 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9454 11:57:43.606487 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9455 11:57:43.610132 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9456 11:57:43.613089 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9457 11:57:43.616592 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9458 11:57:43.622890 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9459 11:57:43.626451 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9460 11:57:43.629707 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9461 11:57:43.632830 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9462 11:57:43.636432 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9463 11:57:43.643046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9464 11:57:43.646007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9465 11:57:43.649380 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9466 11:57:43.656258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9467 11:57:43.659608 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9468 11:57:43.662850 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9469 11:57:43.669306 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9470 11:57:43.672780 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9471 11:57:43.679627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9472 11:57:43.682603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9473 11:57:43.685983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9474 11:57:43.692635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9475 11:57:43.695824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9476 11:57:43.702423 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9477 11:57:43.705410 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9478 11:57:43.712197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9479 11:57:43.715695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9480 11:57:43.718739 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9481 11:57:43.725492 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9482 11:57:43.729139 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9483 11:57:43.735503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9484 11:57:43.738893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9485 11:57:43.741895 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9486 11:57:43.748573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9487 11:57:43.752196 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9488 11:57:43.758985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9489 11:57:43.762235 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9490 11:57:43.765375 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9491 11:57:43.772161 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9492 11:57:43.775515 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9493 11:57:43.782205 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9494 11:57:43.785430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9495 11:57:43.789113 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9496 11:57:43.795300 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9497 11:57:43.798642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9498 11:57:43.805247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9499 11:57:43.808625 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9500 11:57:43.812008 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9501 11:57:43.818812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9502 11:57:43.821886 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9503 11:57:43.828619 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9504 11:57:43.832021 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9505 11:57:43.838447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9506 11:57:43.841756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9507 11:57:43.845174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9508 11:57:43.851855 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9509 11:57:43.855163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9510 11:57:43.861356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9511 11:57:43.864752 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9512 11:57:43.871033 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9513 11:57:43.874937 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9514 11:57:43.877507 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9515 11:57:43.884562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9516 11:57:43.888050 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9517 11:57:43.894707 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9518 11:57:43.897557 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9519 11:57:43.901347 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9520 11:57:43.907944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9521 11:57:43.911102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9522 11:57:43.918040 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9523 11:57:43.921163 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9524 11:57:43.924596 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9525 11:57:43.931100 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9526 11:57:43.934173 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9527 11:57:43.941060 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9528 11:57:43.944205 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9529 11:57:43.950884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9530 11:57:43.954342 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9531 11:57:43.957348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9532 11:57:43.964042 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9533 11:57:43.967763 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9534 11:57:43.973878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9535 11:57:43.976956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9536 11:57:43.980421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9537 11:57:43.986982 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9538 11:57:43.990981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9539 11:57:43.997143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9540 11:57:44.000291 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9541 11:57:44.003957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9542 11:57:44.010278 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9543 11:57:44.013264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9544 11:57:44.020100 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9545 11:57:44.023619 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9546 11:57:44.030447 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9547 11:57:44.033236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9548 11:57:44.040004 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9549 11:57:44.043551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9550 11:57:44.046711 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9551 11:57:44.053132 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9552 11:57:44.056551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9553 11:57:44.063392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9554 11:57:44.066591 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9555 11:57:44.073209 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9556 11:57:44.076471 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9557 11:57:44.079553 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9558 11:57:44.086521 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9559 11:57:44.089445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9560 11:57:44.096498 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9561 11:57:44.099512 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9562 11:57:44.106213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9563 11:57:44.109482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9564 11:57:44.116165 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9565 11:57:44.119473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9566 11:57:44.126051 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9567 11:57:44.129131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9568 11:57:44.132729 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9569 11:57:44.139206 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9570 11:57:44.142565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9571 11:57:44.149241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9572 11:57:44.152424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9573 11:57:44.159017 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9574 11:57:44.162343 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9575 11:57:44.165360 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9576 11:57:44.172194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9577 11:57:44.175535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9578 11:57:44.182144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9579 11:57:44.185389 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9580 11:57:44.191857 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9581 11:57:44.195419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9582 11:57:44.201593 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9583 11:57:44.205229 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9584 11:57:44.208851 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9585 11:57:44.215274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9586 11:57:44.218673 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9587 11:57:44.225195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9588 11:57:44.228098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9589 11:57:44.231377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9590 11:57:44.238505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9591 11:57:44.241517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9592 11:57:44.248504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9593 11:57:44.251504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9594 11:57:44.257774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9595 11:57:44.260957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9596 11:57:44.268186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9597 11:57:44.271373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9598 11:57:44.277796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9599 11:57:44.280992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9600 11:57:44.287693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9601 11:57:44.291199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9602 11:57:44.297288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9603 11:57:44.300885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9604 11:57:44.307695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9605 11:57:44.310501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9606 11:57:44.317146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9607 11:57:44.320583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9608 11:57:44.327575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9609 11:57:44.330839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9610 11:57:44.337494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9611 11:57:44.340878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9612 11:57:44.347388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9613 11:57:44.350353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9614 11:57:44.357443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9615 11:57:44.360369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9616 11:57:44.366891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9617 11:57:44.370458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9618 11:57:44.377062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9619 11:57:44.379980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9620 11:57:44.386842 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9621 11:57:44.387464 INFO: [APUAPC] vio 0
9622 11:57:44.393663 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9623 11:57:44.397194 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9624 11:57:44.400123 INFO: [APUAPC] D0_APC_0: 0x400510
9625 11:57:44.403641 INFO: [APUAPC] D0_APC_1: 0x0
9626 11:57:44.406898 INFO: [APUAPC] D0_APC_2: 0x1540
9627 11:57:44.410719 INFO: [APUAPC] D0_APC_3: 0x0
9628 11:57:44.413646 INFO: [APUAPC] D1_APC_0: 0xffffffff
9629 11:57:44.417276 INFO: [APUAPC] D1_APC_1: 0xffffffff
9630 11:57:44.420253 INFO: [APUAPC] D1_APC_2: 0x3fffff
9631 11:57:44.423531 INFO: [APUAPC] D1_APC_3: 0x0
9632 11:57:44.427126 INFO: [APUAPC] D2_APC_0: 0xffffffff
9633 11:57:44.430215 INFO: [APUAPC] D2_APC_1: 0xffffffff
9634 11:57:44.433618 INFO: [APUAPC] D2_APC_2: 0x3fffff
9635 11:57:44.437100 INFO: [APUAPC] D2_APC_3: 0x0
9636 11:57:44.440564 INFO: [APUAPC] D3_APC_0: 0xffffffff
9637 11:57:44.443534 INFO: [APUAPC] D3_APC_1: 0xffffffff
9638 11:57:44.446919 INFO: [APUAPC] D3_APC_2: 0x3fffff
9639 11:57:44.449975 INFO: [APUAPC] D3_APC_3: 0x0
9640 11:57:44.453357 INFO: [APUAPC] D4_APC_0: 0xffffffff
9641 11:57:44.457135 INFO: [APUAPC] D4_APC_1: 0xffffffff
9642 11:57:44.460208 INFO: [APUAPC] D4_APC_2: 0x3fffff
9643 11:57:44.460835 INFO: [APUAPC] D4_APC_3: 0x0
9644 11:57:44.466461 INFO: [APUAPC] D5_APC_0: 0xffffffff
9645 11:57:44.470133 INFO: [APUAPC] D5_APC_1: 0xffffffff
9646 11:57:44.473262 INFO: [APUAPC] D5_APC_2: 0x3fffff
9647 11:57:44.473826 INFO: [APUAPC] D5_APC_3: 0x0
9648 11:57:44.476606 INFO: [APUAPC] D6_APC_0: 0xffffffff
9649 11:57:44.479825 INFO: [APUAPC] D6_APC_1: 0xffffffff
9650 11:57:44.483115 INFO: [APUAPC] D6_APC_2: 0x3fffff
9651 11:57:44.486528 INFO: [APUAPC] D6_APC_3: 0x0
9652 11:57:44.489834 INFO: [APUAPC] D7_APC_0: 0xffffffff
9653 11:57:44.493013 INFO: [APUAPC] D7_APC_1: 0xffffffff
9654 11:57:44.496241 INFO: [APUAPC] D7_APC_2: 0x3fffff
9655 11:57:44.499789 INFO: [APUAPC] D7_APC_3: 0x0
9656 11:57:44.503045 INFO: [APUAPC] D8_APC_0: 0xffffffff
9657 11:57:44.506474 INFO: [APUAPC] D8_APC_1: 0xffffffff
9658 11:57:44.509909 INFO: [APUAPC] D8_APC_2: 0x3fffff
9659 11:57:44.512770 INFO: [APUAPC] D8_APC_3: 0x0
9660 11:57:44.516320 INFO: [APUAPC] D9_APC_0: 0xffffffff
9661 11:57:44.519464 INFO: [APUAPC] D9_APC_1: 0xffffffff
9662 11:57:44.523115 INFO: [APUAPC] D9_APC_2: 0x3fffff
9663 11:57:44.526174 INFO: [APUAPC] D9_APC_3: 0x0
9664 11:57:44.529585 INFO: [APUAPC] D10_APC_0: 0xffffffff
9665 11:57:44.532907 INFO: [APUAPC] D10_APC_1: 0xffffffff
9666 11:57:44.536270 INFO: [APUAPC] D10_APC_2: 0x3fffff
9667 11:57:44.539773 INFO: [APUAPC] D10_APC_3: 0x0
9668 11:57:44.542392 INFO: [APUAPC] D11_APC_0: 0xffffffff
9669 11:57:44.546003 INFO: [APUAPC] D11_APC_1: 0xffffffff
9670 11:57:44.549424 INFO: [APUAPC] D11_APC_2: 0x3fffff
9671 11:57:44.552578 INFO: [APUAPC] D11_APC_3: 0x0
9672 11:57:44.555851 INFO: [APUAPC] D12_APC_0: 0xffffffff
9673 11:57:44.559680 INFO: [APUAPC] D12_APC_1: 0xffffffff
9674 11:57:44.562813 INFO: [APUAPC] D12_APC_2: 0x3fffff
9675 11:57:44.566116 INFO: [APUAPC] D12_APC_3: 0x0
9676 11:57:44.569454 INFO: [APUAPC] D13_APC_0: 0xffffffff
9677 11:57:44.572659 INFO: [APUAPC] D13_APC_1: 0xffffffff
9678 11:57:44.576159 INFO: [APUAPC] D13_APC_2: 0x3fffff
9679 11:57:44.579495 INFO: [APUAPC] D13_APC_3: 0x0
9680 11:57:44.582769 INFO: [APUAPC] D14_APC_0: 0xffffffff
9681 11:57:44.585762 INFO: [APUAPC] D14_APC_1: 0xffffffff
9682 11:57:44.589059 INFO: [APUAPC] D14_APC_2: 0x3fffff
9683 11:57:44.592774 INFO: [APUAPC] D14_APC_3: 0x0
9684 11:57:44.595971 INFO: [APUAPC] D15_APC_0: 0xffffffff
9685 11:57:44.599605 INFO: [APUAPC] D15_APC_1: 0xffffffff
9686 11:57:44.602725 INFO: [APUAPC] D15_APC_2: 0x3fffff
9687 11:57:44.605999 INFO: [APUAPC] D15_APC_3: 0x0
9688 11:57:44.609456 INFO: [APUAPC] APC_CON: 0x4
9689 11:57:44.612663 INFO: [NOCDAPC] D0_APC_0: 0x0
9690 11:57:44.615881 INFO: [NOCDAPC] D0_APC_1: 0x0
9691 11:57:44.619328 INFO: [NOCDAPC] D1_APC_0: 0x0
9692 11:57:44.622453 INFO: [NOCDAPC] D1_APC_1: 0xfff
9693 11:57:44.626002 INFO: [NOCDAPC] D2_APC_0: 0x0
9694 11:57:44.629099 INFO: [NOCDAPC] D2_APC_1: 0xfff
9695 11:57:44.629572 INFO: [NOCDAPC] D3_APC_0: 0x0
9696 11:57:44.632304 INFO: [NOCDAPC] D3_APC_1: 0xfff
9697 11:57:44.635893 INFO: [NOCDAPC] D4_APC_0: 0x0
9698 11:57:44.638967 INFO: [NOCDAPC] D4_APC_1: 0xfff
9699 11:57:44.642136 INFO: [NOCDAPC] D5_APC_0: 0x0
9700 11:57:44.645768 INFO: [NOCDAPC] D5_APC_1: 0xfff
9701 11:57:44.649128 INFO: [NOCDAPC] D6_APC_0: 0x0
9702 11:57:44.652056 INFO: [NOCDAPC] D6_APC_1: 0xfff
9703 11:57:44.655240 INFO: [NOCDAPC] D7_APC_0: 0x0
9704 11:57:44.659186 INFO: [NOCDAPC] D7_APC_1: 0xfff
9705 11:57:44.662155 INFO: [NOCDAPC] D8_APC_0: 0x0
9706 11:57:44.662719 INFO: [NOCDAPC] D8_APC_1: 0xfff
9707 11:57:44.665703 INFO: [NOCDAPC] D9_APC_0: 0x0
9708 11:57:44.669314 INFO: [NOCDAPC] D9_APC_1: 0xfff
9709 11:57:44.672163 INFO: [NOCDAPC] D10_APC_0: 0x0
9710 11:57:44.675834 INFO: [NOCDAPC] D10_APC_1: 0xfff
9711 11:57:44.678922 INFO: [NOCDAPC] D11_APC_0: 0x0
9712 11:57:44.682084 INFO: [NOCDAPC] D11_APC_1: 0xfff
9713 11:57:44.685771 INFO: [NOCDAPC] D12_APC_0: 0x0
9714 11:57:44.688340 INFO: [NOCDAPC] D12_APC_1: 0xfff
9715 11:57:44.692242 INFO: [NOCDAPC] D13_APC_0: 0x0
9716 11:57:44.695328 INFO: [NOCDAPC] D13_APC_1: 0xfff
9717 11:57:44.698724 INFO: [NOCDAPC] D14_APC_0: 0x0
9718 11:57:44.702043 INFO: [NOCDAPC] D14_APC_1: 0xfff
9719 11:57:44.705061 INFO: [NOCDAPC] D15_APC_0: 0x0
9720 11:57:44.708674 INFO: [NOCDAPC] D15_APC_1: 0xfff
9721 11:57:44.709237 INFO: [NOCDAPC] APC_CON: 0x4
9722 11:57:44.711943 INFO: [APUAPC] set_apusys_apc done
9723 11:57:44.715305 INFO: [DEVAPC] devapc_init done
9724 11:57:44.721927 INFO: GICv3 without legacy support detected.
9725 11:57:44.724962 INFO: ARM GICv3 driver initialized in EL3
9726 11:57:44.728496 INFO: Maximum SPI INTID supported: 639
9727 11:57:44.731818 INFO: BL31: Initializing runtime services
9728 11:57:44.738132 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9729 11:57:44.741470 INFO: SPM: enable CPC mode
9730 11:57:44.744660 INFO: mcdi ready for mcusys-off-idle and system suspend
9731 11:57:44.751441 INFO: BL31: Preparing for EL3 exit to normal world
9732 11:57:44.754742 INFO: Entry point address = 0x80000000
9733 11:57:44.755255 INFO: SPSR = 0x8
9734 11:57:44.761674
9735 11:57:44.762218
9736 11:57:44.762582
9737 11:57:44.765322 Starting depthcharge on Spherion...
9738 11:57:44.765777
9739 11:57:44.766134 Wipe memory regions:
9740 11:57:44.766623
9741 11:57:44.769234 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9742 11:57:44.769777 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9743 11:57:44.770210 Setting prompt string to ['asurada:']
9744 11:57:44.770624 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9745 11:57:44.771333 [0x00000040000000, 0x00000054600000)
9746 11:57:44.890679
9747 11:57:44.891217 [0x00000054660000, 0x00000080000000)
9748 11:57:45.151322
9749 11:57:45.151862 [0x000000821a7280, 0x000000ffe64000)
9750 11:57:45.896443
9751 11:57:45.897033 [0x00000100000000, 0x00000140000000)
9752 11:57:46.277114
9753 11:57:46.281353 Initializing XHCI USB controller at 0x11200000.
9754 11:57:47.318231
9755 11:57:47.321406 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9756 11:57:47.321954
9757 11:57:47.322313
9758 11:57:47.322645
9759 11:57:47.323439 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9761 11:57:47.424812 asurada: tftpboot 192.168.201.1 12066571/tftp-deploy-hke564pf/kernel/image.itb 12066571/tftp-deploy-hke564pf/kernel/cmdline
9762 11:57:47.425474 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9763 11:57:47.425965 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9764 11:57:47.430815 tftpboot 192.168.201.1 12066571/tftp-deploy-hke564pf/kernel/image.ittp-deploy-hke564pf/kernel/cmdline
9765 11:57:47.431375
9766 11:57:47.431736 Waiting for link
9767 11:57:47.591062
9768 11:57:47.591610 R8152: Initializing
9769 11:57:47.591972
9770 11:57:47.594144 Version 9 (ocp_data = 6010)
9771 11:57:47.594593
9772 11:57:47.597579 R8152: Done initializing
9773 11:57:47.598063
9774 11:57:47.598430 Adding net device
9775 11:57:49.605816
9776 11:57:49.606384 done.
9777 11:57:49.606996
9778 11:57:49.607357 MAC: 00:e0:4c:68:03:bd
9779 11:57:49.607765
9780 11:57:49.609304 Sending DHCP discover... done.
9781 11:57:49.609750
9782 11:57:49.612317 Waiting for reply... done.
9783 11:57:49.612952
9784 11:57:49.615529 Sending DHCP request... done.
9785 11:57:49.615997
9786 11:57:49.621569 Waiting for reply... done.
9787 11:57:49.622062
9788 11:57:49.622426 My ip is 192.168.201.16
9789 11:57:49.622773
9790 11:57:49.625299 The DHCP server ip is 192.168.201.1
9791 11:57:49.625748
9792 11:57:49.632077 TFTP server IP predefined by user: 192.168.201.1
9793 11:57:49.632709
9794 11:57:49.638131 Bootfile predefined by user: 12066571/tftp-deploy-hke564pf/kernel/image.itb
9795 11:57:49.638582
9796 11:57:49.638989 Sending tftp read request... done.
9797 11:57:49.641633
9798 11:57:49.647985 Waiting for the transfer...
9799 11:57:49.648582
9800 11:57:49.922870 00000000 ################################################################
9801 11:57:49.923002
9802 11:57:50.209247 00080000 ################################################################
9803 11:57:50.209389
9804 11:57:50.523801 00100000 ################################################################
9805 11:57:50.523936
9806 11:57:50.843920 00180000 ################################################################
9807 11:57:50.844159
9808 11:57:51.230588 00200000 ################################################################
9809 11:57:51.231096
9810 11:57:51.555270 00280000 ################################################################
9811 11:57:51.555407
9812 11:57:51.853398 00300000 ################################################################
9813 11:57:51.853534
9814 11:57:52.126569 00380000 ################################################################
9815 11:57:52.126717
9816 11:57:52.391453 00400000 ################################################################
9817 11:57:52.391595
9818 11:57:52.673954 00480000 ################################################################
9819 11:57:52.674100
9820 11:57:52.960117 00500000 ################################################################
9821 11:57:52.960246
9822 11:57:53.247785 00580000 ################################################################
9823 11:57:53.247918
9824 11:57:53.544787 00600000 ################################################################
9825 11:57:53.544932
9826 11:57:53.844974 00680000 ################################################################
9827 11:57:53.845113
9828 11:57:54.144817 00700000 ################################################################
9829 11:57:54.144975
9830 11:57:54.445180 00780000 ################################################################
9831 11:57:54.445316
9832 11:57:54.745447 00800000 ################################################################
9833 11:57:54.745587
9834 11:57:55.049256 00880000 ################################################################
9835 11:57:55.049676
9836 11:57:55.458328 00900000 ################################################################
9837 11:57:55.458647
9838 11:57:55.785924 00980000 ################################################################
9839 11:57:55.786068
9840 11:57:56.092832 00a00000 ################################################################
9841 11:57:56.092968
9842 11:57:56.394985 00a80000 ################################################################
9843 11:57:56.395127
9844 11:57:56.740418 00b00000 ################################################################
9845 11:57:56.740953
9846 11:57:57.141265 00b80000 ################################################################
9847 11:57:57.141755
9848 11:57:57.547466 00c00000 ################################################################
9849 11:57:57.547966
9850 11:57:57.905918 00c80000 ################################################################
9851 11:57:57.906421
9852 11:57:58.292717 00d00000 ################################################################
9853 11:57:58.293356
9854 11:57:58.657177 00d80000 ################################################################
9855 11:57:58.657313
9856 11:57:58.952061 00e00000 ################################################################
9857 11:57:58.952197
9858 11:57:59.249473 00e80000 ################################################################
9859 11:57:59.249643
9860 11:57:59.692002 00f00000 ################################################################
9861 11:57:59.692566
9862 11:58:00.103134 00f80000 ################################################################
9863 11:58:00.103648
9864 11:58:00.500794 01000000 ################################################################
9865 11:58:00.501304
9866 11:58:00.900470 01080000 ################################################################
9867 11:58:00.901017
9868 11:58:01.291118 01100000 ################################################################
9869 11:58:01.291622
9870 11:58:01.708613 01180000 ################################################################
9871 11:58:01.709284
9872 11:58:02.113736 01200000 ################################################################
9873 11:58:02.114286
9874 11:58:02.489251 01280000 ################################################################
9875 11:58:02.489395
9876 11:58:02.844600 01300000 ################################################################
9877 11:58:02.845145
9878 11:58:03.246830 01380000 ################################################################
9879 11:58:03.247339
9880 11:58:03.650818 01400000 ################################################################
9881 11:58:03.651369
9882 11:58:03.955943 01480000 ################################################################
9883 11:58:03.956080
9884 11:58:04.236864 01500000 ################################################################
9885 11:58:04.237002
9886 11:58:04.539110 01580000 ################################################################
9887 11:58:04.539247
9888 11:58:04.836194 01600000 ################################################################
9889 11:58:04.836332
9890 11:58:05.139470 01680000 ################################################################
9891 11:58:05.139609
9892 11:58:05.444177 01700000 ################################################################
9893 11:58:05.444318
9894 11:58:05.747395 01780000 ################################################################
9895 11:58:05.747558
9896 11:58:06.048154 01800000 ################################################################
9897 11:58:06.048307
9898 11:58:06.351696 01880000 ################################################################
9899 11:58:06.351822
9900 11:58:06.655595 01900000 ################################################################
9901 11:58:06.655731
9902 11:58:07.047579 01980000 ################################################################
9903 11:58:07.048073
9904 11:58:07.433485 01a00000 ################################################################
9905 11:58:07.434026
9906 11:58:07.790681 01a80000 ################################################################
9907 11:58:07.791172
9908 11:58:08.195371 01b00000 ################################################################
9909 11:58:08.195849
9910 11:58:08.541836 01b80000 ################################################################
9911 11:58:08.541967
9912 11:58:08.829384 01c00000 ################################################################
9913 11:58:08.829511
9914 11:58:09.116005 01c80000 ################################################################
9915 11:58:09.116130
9916 11:58:09.416952 01d00000 ################################################################
9917 11:58:09.417081
9918 11:58:09.719860 01d80000 ################################################################
9919 11:58:09.719987
9920 11:58:10.023701 01e00000 ################################################################
9921 11:58:10.023836
9922 11:58:10.319089 01e80000 ################################################################
9923 11:58:10.319241
9924 11:58:10.612350 01f00000 ################################################################
9925 11:58:10.612510
9926 11:58:10.903345 01f80000 ################################################################
9927 11:58:10.903498
9928 11:58:11.206772 02000000 ################################################################
9929 11:58:11.206898
9930 11:58:11.492457 02080000 ################################################################
9931 11:58:11.492622
9932 11:58:11.779488 02100000 ################################################################
9933 11:58:11.779616
9934 11:58:12.069931 02180000 ################################################################
9935 11:58:12.070060
9936 11:58:12.352362 02200000 ################################################################
9937 11:58:12.352538
9938 11:58:12.651203 02280000 ################################################################
9939 11:58:12.651355
9940 11:58:12.939425 02300000 ################################################################
9941 11:58:12.939574
9942 11:58:13.228888 02380000 ################################################################
9943 11:58:13.229014
9944 11:58:13.611970 02400000 ################################################################
9945 11:58:13.612544
9946 11:58:13.967756 02480000 ################################################################
9947 11:58:13.967887
9948 11:58:14.270648 02500000 ################################################################
9949 11:58:14.270775
9950 11:58:14.574346 02580000 ################################################################
9951 11:58:14.574475
9952 11:58:14.866790 02600000 ################################################################
9953 11:58:14.866919
9954 11:58:15.165631 02680000 ################################################################
9955 11:58:15.165760
9956 11:58:15.465976 02700000 ################################################################
9957 11:58:15.466105
9958 11:58:15.767711 02780000 ################################################################
9959 11:58:15.767843
9960 11:58:16.071260 02800000 ################################################################
9961 11:58:16.071392
9962 11:58:16.370544 02880000 ################################################################
9963 11:58:16.370675
9964 11:58:16.661975 02900000 ################################################################
9965 11:58:16.662138
9966 11:58:16.948279 02980000 ################################################################
9967 11:58:16.948425
9968 11:58:17.237292 02a00000 ################################################################
9969 11:58:17.237418
9970 11:58:17.527905 02a80000 ################################################################
9971 11:58:17.528046
9972 11:58:17.812485 02b00000 ################################################################
9973 11:58:17.812630
9974 11:58:18.104749 02b80000 ################################################################
9975 11:58:18.104872
9976 11:58:18.396424 02c00000 ################################################################
9977 11:58:18.396573
9978 11:58:18.682948 02c80000 ################################################################
9979 11:58:18.683071
9980 11:58:18.975674 02d00000 ################################################################
9981 11:58:18.975810
9982 11:58:19.357129 02d80000 ################################################################
9983 11:58:19.357610
9984 11:58:19.764372 02e00000 ################################################################
9985 11:58:19.764902
9986 11:58:20.074981 02e80000 ################################################################
9987 11:58:20.075108
9988 11:58:20.366542 02f00000 ################################################################
9989 11:58:20.366671
9990 11:58:20.662151 02f80000 ################################################################
9991 11:58:20.662279
9992 11:58:20.742179 03000000 ################## done.
9993 11:58:20.742288
9994 11:58:20.745354 The bootfile was 50471018 bytes long.
9995 11:58:20.745442
9996 11:58:20.748781 Sending tftp read request... done.
9997 11:58:20.748868
9998 11:58:20.748972 Waiting for the transfer...
9999 11:58:20.749125
10000 11:58:20.752176 00000000 # done.
10001 11:58:20.752271
10002 11:58:20.758784 Command line loaded dynamically from TFTP file: 12066571/tftp-deploy-hke564pf/kernel/cmdline
10003 11:58:20.758953
10004 11:58:20.772343 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10005 11:58:20.772570
10006 11:58:20.775511 Loading FIT.
10007 11:58:20.775729
10008 11:58:20.778694 Image ramdisk-1 has 39374523 bytes.
10009 11:58:20.778910
10010 11:58:20.782167 Image fdt-1 has 47278 bytes.
10011 11:58:20.782344
10012 11:58:20.782480 Image kernel-1 has 11047184 bytes.
10013 11:58:20.782607
10014 11:58:20.792384 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10015 11:58:20.792652
10016 11:58:20.808873 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10017 11:58:20.812263
10018 11:58:20.815425 Choosing best match conf-1 for compat google,spherion-rev3.
10019 11:58:20.820055
10020 11:58:20.824278 Connected to device vid:did:rid of 1ae0:0028:00
10021 11:58:20.831686
10022 11:58:20.834457 tpm_get_response: command 0x17b, return code 0x0
10023 11:58:20.834917
10024 11:58:20.837909 ec_init: CrosEC protocol v3 supported (256, 248)
10025 11:58:20.842224
10026 11:58:20.845677 tpm_cleanup: add release locality here.
10027 11:58:20.846234
10028 11:58:20.846703 Shutting down all USB controllers.
10029 11:58:20.848896
10030 11:58:20.849400 Removing current net device
10031 11:58:20.849798
10032 11:58:20.855837 Exiting depthcharge with code 4 at timestamp: 64322607
10033 11:58:20.856294
10034 11:58:20.858691 LZMA decompressing kernel-1 to 0x821a6718
10035 11:58:20.859149
10036 11:58:20.861503 LZMA decompressing kernel-1 to 0x40000000
10037 11:58:22.249132
10038 11:58:22.249671 jumping to kernel
10039 11:58:22.251883 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10040 11:58:22.252416 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10041 11:58:22.253052 Setting prompt string to ['Linux version [0-9]']
10042 11:58:22.253537 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 11:58:22.253937 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10044 11:58:22.299269
10045 11:58:22.302421 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10046 11:58:22.306719 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10047 11:58:22.307214 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10048 11:58:22.307602 Setting prompt string to []
10049 11:58:22.308026 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10050 11:58:22.308421 Using line separator: #'\n'#
10051 11:58:22.308800 No login prompt set.
10052 11:58:22.309145 Parsing kernel messages
10053 11:58:22.309455 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10054 11:58:22.310000 [login-action] Waiting for messages, (timeout 00:03:49)
10055 11:58:22.325804 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10056 11:58:22.329048 [ 0.000000] random: crng init done
10057 11:58:22.335710 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10058 11:58:22.338735 [ 0.000000] efi: UEFI not found.
10059 11:58:22.345625 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10060 11:58:22.351764 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10061 11:58:22.361642 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10062 11:58:22.371445 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10063 11:58:22.378244 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10064 11:58:22.384851 [ 0.000000] printk: bootconsole [mtk8250] enabled
10065 11:58:22.391549 [ 0.000000] NUMA: No NUMA configuration found
10066 11:58:22.398110 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10067 11:58:22.401417 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10068 11:58:22.405005 [ 0.000000] Zone ranges:
10069 11:58:22.411441 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10070 11:58:22.414978 [ 0.000000] DMA32 empty
10071 11:58:22.421344 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10072 11:58:22.424649 [ 0.000000] Movable zone start for each node
10073 11:58:22.428047 [ 0.000000] Early memory node ranges
10074 11:58:22.434636 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10075 11:58:22.441136 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10076 11:58:22.447818 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10077 11:58:22.454298 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10078 11:58:22.460645 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10079 11:58:22.467550 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10080 11:58:22.498239 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10081 11:58:22.504643 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10082 11:58:22.511479 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10083 11:58:22.514326 [ 0.000000] psci: probing for conduit method from DT.
10084 11:58:22.520968 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10085 11:58:22.524616 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10086 11:58:22.530751 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10087 11:58:22.534304 [ 0.000000] psci: SMC Calling Convention v1.2
10088 11:58:22.541080 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10089 11:58:22.544153 [ 0.000000] Detected VIPT I-cache on CPU0
10090 11:58:22.550711 [ 0.000000] CPU features: detected: GIC system register CPU interface
10091 11:58:22.557456 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10092 11:58:22.563904 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10093 11:58:22.570471 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10094 11:58:22.580564 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10095 11:58:22.587060 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10096 11:58:22.590645 [ 0.000000] alternatives: applying boot alternatives
10097 11:58:22.597076 [ 0.000000] Fallback order for Node 0: 0
10098 11:58:22.603791 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10099 11:58:22.607029 [ 0.000000] Policy zone: Normal
10100 11:58:22.620192 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10101 11:58:22.630193 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10102 11:58:22.640549 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10103 11:58:22.650402 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10104 11:58:22.656851 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10105 11:58:22.660276 <6>[ 0.000000] software IO TLB: area num 8.
10106 11:58:22.715966 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10107 11:58:22.796232 <6>[ 0.000000] Memory: 3816756K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 341708K reserved, 32768K cma-reserved)
10108 11:58:22.803153 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10109 11:58:22.809786 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10110 11:58:22.813430 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10111 11:58:22.819878 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10112 11:58:22.826506 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10113 11:58:22.829717 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10114 11:58:22.839485 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10115 11:58:22.846294 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10116 11:58:22.852617 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10117 11:58:22.859257 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10118 11:58:22.862618 <6>[ 0.000000] GICv3: 608 SPIs implemented
10119 11:58:22.866179 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10120 11:58:22.872375 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10121 11:58:22.876178 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10122 11:58:22.882594 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10123 11:58:22.895972 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10124 11:58:22.909012 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10125 11:58:22.915310 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10126 11:58:22.922954 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10127 11:58:22.936374 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10128 11:58:22.942872 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10129 11:58:22.949410 <6>[ 0.009227] Console: colour dummy device 80x25
10130 11:58:22.959135 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10131 11:58:22.966323 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10132 11:58:22.969537 <6>[ 0.029298] LSM: Security Framework initializing
10133 11:58:22.976254 <6>[ 0.034209] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10134 11:58:22.986174 <6>[ 0.041817] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10135 11:58:22.993129 <6>[ 0.051044] cblist_init_generic: Setting adjustable number of callback queues.
10136 11:58:22.999723 <6>[ 0.058487] cblist_init_generic: Setting shift to 3 and lim to 1.
10137 11:58:23.009307 <6>[ 0.064825] cblist_init_generic: Setting adjustable number of callback queues.
10138 11:58:23.012249 <6>[ 0.072297] cblist_init_generic: Setting shift to 3 and lim to 1.
10139 11:58:23.019317 <6>[ 0.078696] rcu: Hierarchical SRCU implementation.
10140 11:58:23.026176 <6>[ 0.083742] rcu: Max phase no-delay instances is 1000.
10141 11:58:23.032488 <6>[ 0.090758] EFI services will not be available.
10142 11:58:23.035449 <6>[ 0.095710] smp: Bringing up secondary CPUs ...
10143 11:58:23.043408 <6>[ 0.100781] Detected VIPT I-cache on CPU1
10144 11:58:23.049935 <6>[ 0.100850] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10145 11:58:23.056615 <6>[ 0.100882] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10146 11:58:23.060353 <6>[ 0.101215] Detected VIPT I-cache on CPU2
10147 11:58:23.069942 <6>[ 0.101265] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10148 11:58:23.076503 <6>[ 0.101283] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10149 11:58:23.079430 <6>[ 0.101537] Detected VIPT I-cache on CPU3
10150 11:58:23.086740 <6>[ 0.101584] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10151 11:58:23.092987 <6>[ 0.101597] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10152 11:58:23.096165 <6>[ 0.101897] CPU features: detected: Spectre-v4
10153 11:58:23.103180 <6>[ 0.101904] CPU features: detected: Spectre-BHB
10154 11:58:23.106098 <6>[ 0.101909] Detected PIPT I-cache on CPU4
10155 11:58:23.112879 <6>[ 0.101966] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10156 11:58:23.119596 <6>[ 0.101983] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10157 11:58:23.125763 <6>[ 0.102269] Detected PIPT I-cache on CPU5
10158 11:58:23.132769 <6>[ 0.102332] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10159 11:58:23.139070 <6>[ 0.102348] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10160 11:58:23.142612 <6>[ 0.102627] Detected PIPT I-cache on CPU6
10161 11:58:23.149106 <6>[ 0.102689] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10162 11:58:23.155773 <6>[ 0.102705] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10163 11:58:23.162123 <6>[ 0.103004] Detected PIPT I-cache on CPU7
10164 11:58:23.168865 <6>[ 0.103070] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10165 11:58:23.175644 <6>[ 0.103086] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10166 11:58:23.179050 <6>[ 0.103134] smp: Brought up 1 node, 8 CPUs
10167 11:58:23.185404 <6>[ 0.244595] SMP: Total of 8 processors activated.
10168 11:58:23.188581 <6>[ 0.249515] CPU features: detected: 32-bit EL0 Support
10169 11:58:23.198989 <6>[ 0.254878] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10170 11:58:23.205407 <6>[ 0.263679] CPU features: detected: Common not Private translations
10171 11:58:23.211866 <6>[ 0.270154] CPU features: detected: CRC32 instructions
10172 11:58:23.218235 <6>[ 0.275505] CPU features: detected: RCpc load-acquire (LDAPR)
10173 11:58:23.221842 <6>[ 0.281465] CPU features: detected: LSE atomic instructions
10174 11:58:23.228098 <6>[ 0.287282] CPU features: detected: Privileged Access Never
10175 11:58:23.234890 <6>[ 0.293097] CPU features: detected: RAS Extension Support
10176 11:58:23.241495 <6>[ 0.298705] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10177 11:58:23.245213 <6>[ 0.305922] CPU: All CPU(s) started at EL2
10178 11:58:23.251402 <6>[ 0.310239] alternatives: applying system-wide alternatives
10179 11:58:23.260366 <6>[ 0.320145] devtmpfs: initialized
10180 11:58:23.275186 <6>[ 0.328460] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10181 11:58:23.281759 <6>[ 0.338420] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10182 11:58:23.288416 <6>[ 0.346057] pinctrl core: initialized pinctrl subsystem
10183 11:58:23.292018 <6>[ 0.352729] DMI not present or invalid.
10184 11:58:23.298595 <6>[ 0.357136] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10185 11:58:23.304906 <6>[ 0.363990] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10186 11:58:23.315312 <6>[ 0.371432] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10187 11:58:23.321974 <6>[ 0.379519] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10188 11:58:23.328430 <6>[ 0.387673] audit: initializing netlink subsys (disabled)
10189 11:58:23.338208 <5>[ 0.393367] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10190 11:58:23.341322 <6>[ 0.394065] thermal_sys: Registered thermal governor 'step_wise'
10191 11:58:23.351320 <6>[ 0.401333] thermal_sys: Registered thermal governor 'power_allocator'
10192 11:58:23.354690 <6>[ 0.407587] cpuidle: using governor menu
10193 11:58:23.357862 <6>[ 0.418545] NET: Registered PF_QIPCRTR protocol family
10194 11:58:23.368230 <6>[ 0.424030] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10195 11:58:23.370928 <6>[ 0.431133] ASID allocator initialised with 32768 entries
10196 11:58:23.377782 <6>[ 0.437684] Serial: AMBA PL011 UART driver
10197 11:58:23.386798 <4>[ 0.446447] Trying to register duplicate clock ID: 134
10198 11:58:23.441470 <6>[ 0.504528] KASLR enabled
10199 11:58:23.455642 <6>[ 0.512265] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10200 11:58:23.462783 <6>[ 0.519281] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10201 11:58:23.469312 <6>[ 0.525774] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10202 11:58:23.475840 <6>[ 0.532779] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10203 11:58:23.482299 <6>[ 0.539266] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10204 11:58:23.488692 <6>[ 0.546270] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10205 11:58:23.495372 <6>[ 0.552760] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10206 11:58:23.501975 <6>[ 0.559763] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10207 11:58:23.505514 <6>[ 0.567245] ACPI: Interpreter disabled.
10208 11:58:23.514275 <6>[ 0.573620] iommu: Default domain type: Translated
10209 11:58:23.520547 <6>[ 0.578733] iommu: DMA domain TLB invalidation policy: strict mode
10210 11:58:23.523847 <5>[ 0.585387] SCSI subsystem initialized
10211 11:58:23.530374 <6>[ 0.589549] usbcore: registered new interface driver usbfs
10212 11:58:23.537071 <6>[ 0.595283] usbcore: registered new interface driver hub
10213 11:58:23.540230 <6>[ 0.600838] usbcore: registered new device driver usb
10214 11:58:23.547574 <6>[ 0.606931] pps_core: LinuxPPS API ver. 1 registered
10215 11:58:23.557050 <6>[ 0.612125] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10216 11:58:23.560341 <6>[ 0.621473] PTP clock support registered
10217 11:58:23.564100 <6>[ 0.625715] EDAC MC: Ver: 3.0.0
10218 11:58:23.571392 <6>[ 0.630851] FPGA manager framework
10219 11:58:23.574516 <6>[ 0.634530] Advanced Linux Sound Architecture Driver Initialized.
10220 11:58:23.578312 <6>[ 0.641296] vgaarb: loaded
10221 11:58:23.584705 <6>[ 0.644455] clocksource: Switched to clocksource arch_sys_counter
10222 11:58:23.591370 <5>[ 0.650882] VFS: Disk quotas dquot_6.6.0
10223 11:58:23.598073 <6>[ 0.655067] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10224 11:58:23.601707 <6>[ 0.662255] pnp: PnP ACPI: disabled
10225 11:58:23.609544 <6>[ 0.668882] NET: Registered PF_INET protocol family
10226 11:58:23.615481 <6>[ 0.674256] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10227 11:58:23.628046 <6>[ 0.684257] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10228 11:58:23.637424 <6>[ 0.693043] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10229 11:58:23.644291 <6>[ 0.701009] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10230 11:58:23.650805 <6>[ 0.709411] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10231 11:58:23.661728 <6>[ 0.718072] TCP: Hash tables configured (established 32768 bind 32768)
10232 11:58:23.668258 <6>[ 0.724915] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10233 11:58:23.674937 <6>[ 0.731934] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10234 11:58:23.681372 <6>[ 0.739446] NET: Registered PF_UNIX/PF_LOCAL protocol family
10235 11:58:23.688026 <6>[ 0.745572] RPC: Registered named UNIX socket transport module.
10236 11:58:23.691489 <6>[ 0.751724] RPC: Registered udp transport module.
10237 11:58:23.698406 <6>[ 0.756659] RPC: Registered tcp transport module.
10238 11:58:23.704743 <6>[ 0.761592] RPC: Registered tcp NFSv4.1 backchannel transport module.
10239 11:58:23.708040 <6>[ 0.768258] PCI: CLS 0 bytes, default 64
10240 11:58:23.711189 <6>[ 0.772607] Unpacking initramfs...
10241 11:58:23.736703 <6>[ 0.793096] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10242 11:58:23.746503 <6>[ 0.801740] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10243 11:58:23.749600 <6>[ 0.810615] kvm [1]: IPA Size Limit: 40 bits
10244 11:58:23.756356 <6>[ 0.815132] kvm [1]: GICv3: no GICV resource entry
10245 11:58:23.759941 <6>[ 0.820154] kvm [1]: disabling GICv2 emulation
10246 11:58:23.766224 <6>[ 0.824840] kvm [1]: GIC system register CPU interface enabled
10247 11:58:23.770029 <6>[ 0.831000] kvm [1]: vgic interrupt IRQ18
10248 11:58:23.776199 <6>[ 0.835355] kvm [1]: VHE mode initialized successfully
10249 11:58:23.782971 <5>[ 0.841811] Initialise system trusted keyrings
10250 11:58:23.789274 <6>[ 0.846601] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10251 11:58:23.796943 <6>[ 0.856576] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10252 11:58:23.803723 <5>[ 0.862976] NFS: Registering the id_resolver key type
10253 11:58:23.806712 <5>[ 0.868276] Key type id_resolver registered
10254 11:58:23.813211 <5>[ 0.872693] Key type id_legacy registered
10255 11:58:23.820150 <6>[ 0.876972] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10256 11:58:23.826856 <6>[ 0.883894] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10257 11:58:23.833342 <6>[ 0.891608] 9p: Installing v9fs 9p2000 file system support
10258 11:58:23.870091 <5>[ 0.929772] Key type asymmetric registered
10259 11:58:23.873294 <5>[ 0.934102] Asymmetric key parser 'x509' registered
10260 11:58:23.883175 <6>[ 0.939241] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10261 11:58:23.886757 <6>[ 0.946873] io scheduler mq-deadline registered
10262 11:58:23.890113 <6>[ 0.951655] io scheduler kyber registered
10263 11:58:23.908610 <6>[ 0.968756] EINJ: ACPI disabled.
10264 11:58:23.941134 <4>[ 0.994498] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10265 11:58:23.951092 <4>[ 1.005134] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10266 11:58:23.966378 <6>[ 1.025840] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10267 11:58:23.974095 <6>[ 1.033776] printk: console [ttyS0] disabled
10268 11:58:24.001902 <6>[ 1.058422] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10269 11:58:24.008363 <6>[ 1.067898] printk: console [ttyS0] enabled
10270 11:58:24.012142 <6>[ 1.067898] printk: console [ttyS0] enabled
10271 11:58:24.019024 <6>[ 1.076791] printk: bootconsole [mtk8250] disabled
10272 11:58:24.021877 <6>[ 1.076791] printk: bootconsole [mtk8250] disabled
10273 11:58:24.028528 <6>[ 1.088001] SuperH (H)SCI(F) driver initialized
10274 11:58:24.031957 <6>[ 1.093282] msm_serial: driver initialized
10275 11:58:24.045754 <6>[ 1.102225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10276 11:58:24.055687 <6>[ 1.110770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10277 11:58:24.062185 <6>[ 1.119312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10278 11:58:24.072398 <6>[ 1.127941] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10279 11:58:24.082123 <6>[ 1.136648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10280 11:58:24.089151 <6>[ 1.145362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10281 11:58:24.098984 <6>[ 1.153911] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10282 11:58:24.106103 <6>[ 1.162720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10283 11:58:24.115315 <6>[ 1.171266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10284 11:58:24.126939 <6>[ 1.186671] loop: module loaded
10285 11:58:24.133238 <6>[ 1.192734] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10286 11:58:24.156146 <4>[ 1.216103] mtk-pmic-keys: Failed to locate of_node [id: -1]
10287 11:58:24.163270 <6>[ 1.223217] megasas: 07.719.03.00-rc1
10288 11:58:24.173531 <6>[ 1.233067] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10289 11:58:24.180307 <6>[ 1.239838] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10290 11:58:24.196575 <6>[ 1.256359] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10291 11:58:24.253108 <6>[ 1.306330] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10292 11:58:25.321789 <6>[ 2.381856] Freeing initrd memory: 38448K
10293 11:58:25.332408 <6>[ 2.392276] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10294 11:58:25.343362 <6>[ 2.403333] tun: Universal TUN/TAP device driver, 1.6
10295 11:58:25.346538 <6>[ 2.409423] thunder_xcv, ver 1.0
10296 11:58:25.349851 <6>[ 2.412930] thunder_bgx, ver 1.0
10297 11:58:25.353164 <6>[ 2.416420] nicpf, ver 1.0
10298 11:58:25.363742 <6>[ 2.420471] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10299 11:58:25.367214 <6>[ 2.427945] hns3: Copyright (c) 2017 Huawei Corporation.
10300 11:58:25.373700 <6>[ 2.433533] hclge is initializing
10301 11:58:25.376987 <6>[ 2.437113] e1000: Intel(R) PRO/1000 Network Driver
10302 11:58:25.383923 <6>[ 2.442243] e1000: Copyright (c) 1999-2006 Intel Corporation.
10303 11:58:25.387080 <6>[ 2.448256] e1000e: Intel(R) PRO/1000 Network Driver
10304 11:58:25.393806 <6>[ 2.453471] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10305 11:58:25.400335 <6>[ 2.459658] igb: Intel(R) Gigabit Ethernet Network Driver
10306 11:58:25.407043 <6>[ 2.465308] igb: Copyright (c) 2007-2014 Intel Corporation.
10307 11:58:25.413257 <6>[ 2.471144] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10308 11:58:25.420168 <6>[ 2.477662] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10309 11:58:25.423259 <6>[ 2.484126] sky2: driver version 1.30
10310 11:58:25.429774 <6>[ 2.489158] VFIO - User Level meta-driver version: 0.3
10311 11:58:25.437713 <6>[ 2.497481] usbcore: registered new interface driver usb-storage
10312 11:58:25.444135 <6>[ 2.503924] usbcore: registered new device driver onboard-usb-hub
10313 11:58:25.453268 <6>[ 2.513113] mt6397-rtc mt6359-rtc: registered as rtc0
10314 11:58:25.463077 <6>[ 2.518601] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:58:26 UTC (1700740706)
10315 11:58:25.466247 <6>[ 2.528224] i2c_dev: i2c /dev entries driver
10316 11:58:25.483175 <6>[ 2.539921] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10317 11:58:25.503925 <6>[ 2.563910] cpu cpu0: EM: created perf domain
10318 11:58:25.507054 <6>[ 2.568813] cpu cpu4: EM: created perf domain
10319 11:58:25.514212 <6>[ 2.574321] sdhci: Secure Digital Host Controller Interface driver
10320 11:58:25.521262 <6>[ 2.580752] sdhci: Copyright(c) Pierre Ossman
10321 11:58:25.527953 <6>[ 2.585667] Synopsys Designware Multimedia Card Interface Driver
10322 11:58:25.534384 <6>[ 2.592262] sdhci-pltfm: SDHCI platform and OF driver helper
10323 11:58:25.537387 <6>[ 2.592414] mmc0: CQHCI version 5.10
10324 11:58:25.544062 <6>[ 2.602356] ledtrig-cpu: registered to indicate activity on CPUs
10325 11:58:25.550939 <6>[ 2.609308] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10326 11:58:25.557249 <6>[ 2.616332] usbcore: registered new interface driver usbhid
10327 11:58:25.560969 <6>[ 2.622157] usbhid: USB HID core driver
10328 11:58:25.567201 <6>[ 2.626358] spi_master spi0: will run message pump with realtime priority
10329 11:58:25.612343 <6>[ 2.665462] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10330 11:58:25.632114 <6>[ 2.681899] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10331 11:58:25.639136 <6>[ 2.696559] cros-ec-spi spi0.0: Chrome EC device registered
10332 11:58:25.642558 <6>[ 2.702636] mmc0: Command Queue Engine enabled
10333 11:58:25.648955 <6>[ 2.707384] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10334 11:58:25.655858 <6>[ 2.714698] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10335 11:58:25.662489 <6>[ 2.717471] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10336 11:58:25.668913 <6>[ 2.723201] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10337 11:58:25.675385 <6>[ 2.729795] NET: Registered PF_PACKET protocol family
10338 11:58:25.678895 <6>[ 2.735941] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10339 11:58:25.685479 <6>[ 2.740096] 9pnet: Installing 9P2000 support
10340 11:58:25.688714 <6>[ 2.745920] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10341 11:58:25.695167 <5>[ 2.749797] Key type dns_resolver registered
10342 11:58:25.701824 <6>[ 2.755665] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10343 11:58:25.705336 <6>[ 2.759943] registered taskstats version 1
10344 11:58:25.712003 <5>[ 2.770418] Loading compiled-in X.509 certificates
10345 11:58:25.738446 <4>[ 2.791722] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10346 11:58:25.748696 <4>[ 2.802447] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10347 11:58:25.755099 <3>[ 2.812983] debugfs: File 'uA_load' in directory '/' already present!
10348 11:58:25.761325 <3>[ 2.819682] debugfs: File 'min_uV' in directory '/' already present!
10349 11:58:25.768245 <3>[ 2.826289] debugfs: File 'max_uV' in directory '/' already present!
10350 11:58:25.774647 <3>[ 2.832957] debugfs: File 'constraint_flags' in directory '/' already present!
10351 11:58:25.785578 <3>[ 2.842554] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10352 11:58:25.795922 <6>[ 2.855897] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10353 11:58:25.803126 <6>[ 2.862743] xhci-mtk 11200000.usb: xHCI Host Controller
10354 11:58:25.809201 <6>[ 2.868240] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10355 11:58:25.819523 <6>[ 2.876194] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10356 11:58:25.826444 <6>[ 2.885643] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10357 11:58:25.832989 <6>[ 2.891719] xhci-mtk 11200000.usb: xHCI Host Controller
10358 11:58:25.839513 <6>[ 2.897217] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10359 11:58:25.845880 <6>[ 2.904880] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10360 11:58:25.853404 <6>[ 2.912756] hub 1-0:1.0: USB hub found
10361 11:58:25.856276 <6>[ 2.916770] hub 1-0:1.0: 1 port detected
10362 11:58:25.865755 <6>[ 2.921038] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10363 11:58:25.869190 <6>[ 2.929740] hub 2-0:1.0: USB hub found
10364 11:58:25.872667 <6>[ 2.933756] hub 2-0:1.0: 1 port detected
10365 11:58:25.881795 <6>[ 2.942016] mtk-msdc 11f70000.mmc: Got CD GPIO
10366 11:58:25.888581 <6>[ 2.947113] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10367 11:58:25.898297 <6>[ 2.955150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10368 11:58:25.908339 <4>[ 2.963036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10369 11:58:25.914903 <6>[ 2.972557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10370 11:58:25.925109 <6>[ 2.980635] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10371 11:58:25.931146 <6>[ 2.988764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10372 11:58:25.937782 <6>[ 2.996690] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10373 11:58:25.948030 <6>[ 3.004563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10374 11:58:25.958149 <6>[ 3.012383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10375 11:58:25.967702 <6>[ 3.022927] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10376 11:58:25.974423 <6>[ 3.031287] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10377 11:58:25.984336 <6>[ 3.039667] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10378 11:58:25.990674 <6>[ 3.048011] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10379 11:58:26.000661 <6>[ 3.056360] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10380 11:58:26.007426 <6>[ 3.064699] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10381 11:58:26.017100 <6>[ 3.073046] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10382 11:58:26.023912 <6>[ 3.081385] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10383 11:58:26.033717 <6>[ 3.089747] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10384 11:58:26.040292 <6>[ 3.098086] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10385 11:58:26.050514 <6>[ 3.106433] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10386 11:58:26.057090 <6>[ 3.114771] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10387 11:58:26.066679 <6>[ 3.123108] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10388 11:58:26.073420 <6>[ 3.131447] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10389 11:58:26.083649 <6>[ 3.139783] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10390 11:58:26.090068 <6>[ 3.148578] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10391 11:58:26.096614 <6>[ 3.155747] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10392 11:58:26.103029 <6>[ 3.162499] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10393 11:58:26.109887 <6>[ 3.169229] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10394 11:58:26.116394 <6>[ 3.176126] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10395 11:58:26.126391 <6>[ 3.182980] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10396 11:58:26.136480 <6>[ 3.192108] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10397 11:58:26.146247 <6>[ 3.201231] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10398 11:58:26.155960 <6>[ 3.210523] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10399 11:58:26.165731 <6>[ 3.220014] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10400 11:58:26.172606 <6>[ 3.229487] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10401 11:58:26.182547 <6>[ 3.238610] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10402 11:58:26.192272 <6>[ 3.248079] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10403 11:58:26.202128 <6>[ 3.257196] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10404 11:58:26.211909 <6>[ 3.266490] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10405 11:58:26.221828 <6>[ 3.276649] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10406 11:58:26.231640 <6>[ 3.288177] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10407 11:58:26.264269 <6>[ 3.321002] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10408 11:58:26.292327 <6>[ 3.352416] hub 2-1:1.0: USB hub found
10409 11:58:26.296227 <6>[ 3.356902] hub 2-1:1.0: 3 ports detected
10410 11:58:26.304286 <6>[ 3.364135] hub 2-1:1.0: USB hub found
10411 11:58:26.307642 <6>[ 3.368579] hub 2-1:1.0: 3 ports detected
10412 11:58:26.415741 <6>[ 3.472659] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10413 11:58:26.570771 <6>[ 3.630722] hub 1-1:1.0: USB hub found
10414 11:58:26.574018 <6>[ 3.635197] hub 1-1:1.0: 4 ports detected
10415 11:58:26.583447 <6>[ 3.643381] hub 1-1:1.0: USB hub found
10416 11:58:26.586930 <6>[ 3.647714] hub 1-1:1.0: 4 ports detected
10417 11:58:26.648295 <6>[ 3.704840] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10418 11:58:26.907803 <6>[ 3.964809] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10419 11:58:27.040720 <6>[ 4.100667] hub 1-1.4:1.0: USB hub found
10420 11:58:27.043847 <6>[ 4.105332] hub 1-1.4:1.0: 2 ports detected
10421 11:58:27.053704 <6>[ 4.113519] hub 1-1.4:1.0: USB hub found
10422 11:58:27.056590 <6>[ 4.118188] hub 1-1.4:1.0: 2 ports detected
10423 11:58:27.351766 <6>[ 4.408735] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10424 11:58:27.543304 <6>[ 4.600803] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10425 11:58:38.533221 <6>[ 15.597718] ALSA device list:
10426 11:58:38.539427 <6>[ 15.601007] No soundcards found.
10427 11:58:38.547627 <6>[ 15.608776] Freeing unused kernel memory: 8384K
10428 11:58:38.550441 <6>[ 15.613759] Run /init as init process
10429 11:58:38.600564 <6>[ 15.661700] NET: Registered PF_INET6 protocol family
10430 11:58:38.606894 <6>[ 15.667841] Segment Routing with IPv6
10431 11:58:38.610449 <6>[ 15.671790] In-situ OAM (IOAM) with IPv6
10432 11:58:38.644321 <30>[ 15.685807] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10433 11:58:38.647625 <30>[ 15.709587] systemd[1]: Detected architecture arm64.
10434 11:58:38.648191
10435 11:58:38.654111 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10436 11:58:38.654573
10437 11:58:38.667115 <30>[ 15.728712] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10438 11:58:38.790688 <30>[ 15.848764] systemd[1]: Queued start job for default target Graphical Interface.
10439 11:58:38.820407 <30>[ 15.881749] systemd[1]: Created slice system-getty.slice.
10440 11:58:38.827022 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10441 11:58:38.843656 <30>[ 15.905177] systemd[1]: Created slice system-modprobe.slice.
10442 11:58:38.850431 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10443 11:58:38.868474 <30>[ 15.929829] systemd[1]: Created slice system-serial\x2dgetty.slice.
10444 11:58:38.878801 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10445 11:58:38.892173 <30>[ 15.953758] systemd[1]: Created slice User and Session Slice.
10446 11:58:38.898940 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10447 11:58:38.919027 <30>[ 15.977282] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10448 11:58:38.928714 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10449 11:58:38.946935 <30>[ 16.005340] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10450 11:58:38.953896 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10451 11:58:38.978606 <30>[ 16.033212] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10452 11:58:38.985002 <30>[ 16.045503] systemd[1]: Reached target Local Encrypted Volumes.
10453 11:58:38.991588 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10454 11:58:39.007870 <30>[ 16.069202] systemd[1]: Reached target Paths.
10455 11:58:39.014188 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10456 11:58:39.027957 <30>[ 16.088745] systemd[1]: Reached target Remote File Systems.
10457 11:58:39.034082 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10458 11:58:39.051565 <30>[ 16.113105] systemd[1]: Reached target Slices.
10459 11:58:39.057868 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10460 11:58:39.071442 <30>[ 16.132760] systemd[1]: Reached target Swap.
10461 11:58:39.074445 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10462 11:58:39.094898 <30>[ 16.153237] systemd[1]: Listening on initctl Compatibility Named Pipe.
10463 11:58:39.101508 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10464 11:58:39.108260 <30>[ 16.168427] systemd[1]: Listening on Journal Audit Socket.
10465 11:58:39.114528 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10466 11:58:39.127669 <30>[ 16.189206] systemd[1]: Listening on Journal Socket (/dev/log).
10467 11:58:39.134361 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10468 11:58:39.152349 <30>[ 16.213951] systemd[1]: Listening on Journal Socket.
10469 11:58:39.159237 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10470 11:58:39.175127 <30>[ 16.233435] systemd[1]: Listening on Network Service Netlink Socket.
10471 11:58:39.181578 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10472 11:58:39.195713 <30>[ 16.257278] systemd[1]: Listening on udev Control Socket.
10473 11:58:39.202429 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10474 11:58:39.220608 <30>[ 16.281815] systemd[1]: Listening on udev Kernel Socket.
10475 11:58:39.226674 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10476 11:58:39.283251 <30>[ 16.344934] systemd[1]: Mounting Huge Pages File System...
10477 11:58:39.290229 Mounting [0;1;39mHuge Pages File System[0m...
10478 11:58:39.307081 <30>[ 16.368349] systemd[1]: Mounting POSIX Message Queue File System...
10479 11:58:39.313444 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10480 11:58:39.363413 <30>[ 16.424888] systemd[1]: Mounting Kernel Debug File System...
10481 11:58:39.370101 Mounting [0;1;39mKernel Debug File System[0m...
10482 11:58:39.386895 <30>[ 16.445172] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10483 11:58:39.414942 <30>[ 16.473013] systemd[1]: Starting Create list of static device nodes for the current kernel...
10484 11:58:39.421789 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10485 11:58:39.443903 <30>[ 16.505150] systemd[1]: Starting Load Kernel Module configfs...
10486 11:58:39.450346 Starting [0;1;39mLoad Kernel Module configfs[0m...
10487 11:58:39.467724 <30>[ 16.529012] systemd[1]: Starting Load Kernel Module drm...
10488 11:58:39.473985 Starting [0;1;39mLoad Kernel Module drm[0m...
10489 11:58:39.491092 <30>[ 16.549109] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10490 11:58:39.524272 <30>[ 16.585447] systemd[1]: Starting Journal Service...
10491 11:58:39.527670 Starting [0;1;39mJournal Service[0m...
10492 11:58:39.547750 <30>[ 16.609252] systemd[1]: Starting Load Kernel Modules...
10493 11:58:39.554569 Starting [0;1;39mLoad Kernel Modules[0m...
10494 11:58:39.573217 <30>[ 16.631553] systemd[1]: Starting Remount Root and Kernel File Systems...
10495 11:58:39.579744 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10496 11:58:39.592916 <30>[ 16.654485] systemd[1]: Starting Coldplug All udev Devices...
10497 11:58:39.599876 Starting [0;1;39mColdplug All udev Devices[0m...
10498 11:58:39.621183 <30>[ 16.682732] systemd[1]: Started Journal Service.
10499 11:58:39.628045 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10500 11:58:39.644603 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10501 11:58:39.660125 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10502 11:58:39.676376 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10503 11:58:39.696272 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10504 11:58:39.712994 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10505 11:58:39.734299 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10506 11:58:39.757289 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10507 11:58:39.777201 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10508 11:58:39.791162 See 'systemctl status systemd-remount-fs.service' for details.
10509 11:58:39.841718 Mounting [0;1;39mKernel Configuration File System[0m...
10510 11:58:39.863481 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10511 11:58:39.887661 <46>[ 16.946089] systemd-journald[176]: Received client request to flush runtime journal.
10512 11:58:39.894170 Starting [0;1;39mLoad/Save Random Seed[0m...
10513 11:58:39.916089 Starting [0;1;39mApply Kernel Variables[0m...
10514 11:58:39.936839 Starting [0;1;39mCreate System Users[0m...
10515 11:58:39.956672 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10516 11:58:39.972148 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10517 11:58:39.992381 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10518 11:58:40.004971 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10519 11:58:40.021020 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10520 11:58:40.037134 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10521 11:58:40.091812 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10522 11:58:40.115581 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10523 11:58:40.127454 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10524 11:58:40.143313 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10525 11:58:40.200378 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10526 11:58:40.230795 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10527 11:58:40.247667 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10528 11:58:40.269287 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10529 11:58:40.324269 Starting [0;1;39mNetwork Service[0m...
10530 11:58:40.348380 Starting [0;1;39mNetwork Time Synchronization[0m...
10531 11:58:40.369337 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10532 11:58:40.408114 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10533 11:58:40.427551 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10534 11:58:40.443649 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10535 11:58:40.471168 <6>[ 17.529240] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10536 11:58:40.480901 [[0;32m OK [<6>[ 17.537330] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10537 11:58:40.490523 0m] Created slic<6>[ 17.539439] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10538 11:58:40.500757 e [0;1;39msyste<6>[ 17.547433] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10539 11:58:40.507508 m-systemd\x2dbac<4>[ 17.558238] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10540 11:58:40.510626 klight.slice[0m.
10541 11:58:40.517330 <4>[ 17.576504] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10542 11:58:40.523777 <6>[ 17.577025] remoteproc remoteproc0: scp is available
10543 11:58:40.526968 <6>[ 17.578526] usbcore: registered new interface driver r8152
10544 11:58:40.533794 <6>[ 17.584230] mc: Linux media interface: v0.10
10545 11:58:40.537075 <6>[ 17.589521] remoteproc remoteproc0: powering up scp
10546 11:58:40.547086 <6>[ 17.604559] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10547 11:58:40.553304 <6>[ 17.613135] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10548 11:58:40.564013 [[0;32m OK [0m] Reached targ<3>[ 17.621103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10549 11:58:40.566535 et [0;1;39mSystem Time Set[0m.
10550 11:58:40.573250 <3>[ 17.633620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10551 11:58:40.583622 <3>[ 17.642059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10552 11:58:40.590137 <6>[ 17.642995] videodev: Linux video capture interface: v2.00
10553 11:58:40.596820 <6>[ 17.644399] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10554 11:58:40.603195 <3>[ 17.650420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10555 11:58:40.613745 <4>[ 17.665154] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10556 11:58:40.619674 <4>[ 17.665154] Fallback method does not support PEC.
10557 11:58:40.626544 <6>[ 17.668770] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10558 11:58:40.633282 <6>[ 17.669812] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10559 11:58:40.639908 <6>[ 17.669816] pci_bus 0000:00: root bus resource [bus 00-ff]
10560 11:58:40.646193 <6>[ 17.669820] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10561 11:58:40.656222 <6>[ 17.669823] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10562 11:58:40.663255 <6>[ 17.669851] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10563 11:58:40.669871 <6>[ 17.669864] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10564 11:58:40.673245 <6>[ 17.669925] pci 0000:00:00.0: supports D1 D2
10565 11:58:40.679744 <6>[ 17.669926] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10566 11:58:40.689807 <6>[ 17.670825] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10567 11:58:40.696381 <6>[ 17.670916] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10568 11:58:40.702776 <6>[ 17.670942] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10569 11:58:40.709451 <6>[ 17.670957] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10570 11:58:40.715974 <6>[ 17.670972] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10571 11:58:40.723133 <6>[ 17.671078] pci 0000:01:00.0: supports D1 D2
10572 11:58:40.729760 <6>[ 17.671079] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10573 11:58:40.736421 <6>[ 17.684691] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10574 11:58:40.743181 <3>[ 17.685444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10575 11:58:40.754236 <6>[ 17.691204] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10576 11:58:40.760981 <4>[ 17.692239] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10577 11:58:40.771322 <4>[ 17.692248] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10578 11:58:40.778487 <6>[ 17.692599] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10579 11:58:40.785144 <6>[ 17.692608] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10580 11:58:40.795276 <6>[ 17.692625] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10581 11:58:40.805469 <6>[ 17.693164] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10582 11:58:40.812548 <6>[ 17.693392] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10583 11:58:40.822351 <3>[ 17.699836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10584 11:58:40.829734 <6>[ 17.705280] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10585 11:58:40.836224 <6>[ 17.706704] usbcore: registered new interface driver cdc_ether
10586 11:58:40.843120 <3>[ 17.712381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10587 11:58:40.853015 <3>[ 17.712387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10588 11:58:40.859562 <6>[ 17.712926] usbcore: registered new interface driver r8153_ecm
10589 11:58:40.866291 <6>[ 17.722315] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10590 11:58:40.876337 <3>[ 17.728660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10591 11:58:40.879176 <6>[ 17.733056] Bluetooth: Core ver 2.22
10592 11:58:40.882638 <6>[ 17.733112] NET: Registered PF_BLUETOOTH protocol family
10593 11:58:40.889365 <6>[ 17.733114] Bluetooth: HCI device and connection manager initialized
10594 11:58:40.895714 <6>[ 17.733132] Bluetooth: HCI socket layer initialized
10595 11:58:40.899474 <6>[ 17.733139] Bluetooth: L2CAP socket layer initialized
10596 11:58:40.906351 <6>[ 17.733148] Bluetooth: SCO socket layer initialized
10597 11:58:40.912805 <6>[ 17.736125] pci 0000:00:00.0: PCI bridge to [bus 01]
10598 11:58:40.919520 <3>[ 17.740687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10599 11:58:40.922597 <6>[ 17.744574] r8152 2-1.3:1.0 eth0: v1.12.13
10600 11:58:40.932437 <6>[ 17.747606] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10601 11:58:40.939217 <6>[ 17.748725] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10602 11:58:40.952417 <6>[ 17.750127] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10603 11:58:40.955752 <6>[ 17.750235] usbcore: registered new interface driver uvcvideo
10604 11:58:40.965999 <6>[ 17.753353] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10605 11:58:40.972998 <3>[ 17.755723] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10606 11:58:40.979544 <6>[ 17.757540] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10607 11:58:40.989607 <6>[ 17.762030] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10608 11:58:40.996567 <6>[ 17.763295] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10609 11:58:41.000200 <6>[ 17.764558] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10610 11:58:41.010454 <6>[ 17.764756] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10611 11:58:41.016771 <6>[ 17.765319] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10612 11:58:41.023538 <6>[ 17.766226] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10613 11:58:41.029867 <3>[ 17.769453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 11:58:41.036975 <6>[ 17.776950] remoteproc remoteproc0: remote processor scp is now up
10615 11:58:41.043327 <3>[ 17.784490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 11:58:41.050897 <6>[ 17.786500] usbcore: registered new interface driver btusb
10617 11:58:41.057210 <6>[ 17.786570] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10618 11:58:41.067978 <4>[ 17.787417] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10619 11:58:41.074474 <3>[ 17.787447] Bluetooth: hci0: Failed to load firmware file (-2)
10620 11:58:41.077793 <3>[ 17.787453] Bluetooth: hci0: Failed to set up firmware (-2)
10621 11:58:41.088073 <4>[ 17.787459] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10622 11:58:41.098355 <3>[ 17.797265] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 11:58:41.108255 <3>[ 17.798006] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10624 11:58:41.115647 <3>[ 17.803176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10625 11:58:41.122987 <5>[ 17.824114] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10626 11:58:41.132629 <3>[ 17.825390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 11:58:41.138890 <3>[ 17.829254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10628 11:58:41.148892 <3>[ 17.829261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10629 11:58:41.155540 <3>[ 17.829264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10630 11:58:41.165474 <3>[ 17.829303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10631 11:58:41.172250 <3>[ 17.843426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 11:58:41.178992 <5>[ 17.849548] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10633 11:58:41.189025 <3>[ 17.879144] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 11:58:41.198265 <3>[ 17.879728] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10635 11:58:41.205128 <4>[ 17.881097] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10636 11:58:41.214723 <3>[ 17.899088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 11:58:41.218298 <6>[ 17.903157] cfg80211: failed to load regulatory.db
10638 11:58:41.228098 <3>[ 17.968976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 11:58:41.234733 <6>[ 18.013166] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10640 11:58:41.244627 <3>[ 18.037509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10641 11:58:41.251328 <6>[ 18.039362] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10642 11:58:41.257997 <3>[ 18.066850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 11:58:41.264747 <6>[ 18.088865] mt7921e 0000:01:00.0: ASIC revision: 79610010
10644 11:58:41.270934 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10645 11:58:41.307566 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10646 11:58:41.323961 Starting [0;1;39mNetwork Name Resolution[0m...
10647 11:58:41.344204 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10648 11:58:41.369914 <4>[ 18.424813] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10649 11:58:41.379431 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10650 11:58:41.416341 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10651 11:58:41.487428 <4>[ 18.542825] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10652 11:58:41.551843 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10653 11:58:41.567094 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10654 11:58:41.586438 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10655 11:58:41.610168 [[0;32m OK [0m] Reached targ<4>[ 18.662900] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10656 11:58:41.612722 et [0;1;39mSystem Initialization[0m.
10657 11:58:41.631642 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10658 11:58:41.646649 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10659 11:58:41.663352 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10660 11:58:41.683113 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10661 11:58:41.699192 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10662 11:58:41.727188 [[0;32m OK [0m] Reached target [0;1;39mBasi<4>[ 18.783277] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10663 11:58:41.730553 c System[0m.
10664 11:58:41.749155 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10665 11:58:41.800259 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10666 11:58:41.850015 Starting [0;1;39mUser Login Management<4>[ 18.904665] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10667 11:58:41.850621 [0m...
10668 11:58:41.874101 Starting [0;1;39mPermit User Sessions[0m...
10669 11:58:41.899939 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10670 11:58:41.915854 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10671 11:58:41.933130 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10672 11:58:41.952637 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10673 11:58:41.971970 <4>[ 19.027031] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10674 11:58:42.000798 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10675 11:58:42.021101 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10676 11:58:42.040317 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10677 11:58:42.055610 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10678 11:58:42.073007 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10679 11:58:42.087652 <4>[ 19.142859] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10680 11:58:42.144636 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10681 11:58:42.182868 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10682 11:58:42.208197 <4>[ 19.263537] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10683 11:58:42.223072
10684 11:58:42.223648
10685 11:58:42.226515 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10686 11:58:42.227076
10687 11:58:42.229589 debian-bullseye-arm64 login: root (automatic login)
10688 11:58:42.230055
10689 11:58:42.230455
10690 11:58:42.258609 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP P<6>[ 19.317452] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10691 11:58:42.265489 REEMPT Thu Nov 2<6>[ 19.325705] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10692 11:58:42.268727 3 11:35:49 UTC 2023 aarch64
10693 11:58:42.269296
10694 11:58:42.274675 The programs included with the Debian GNU/Linux system are free software;
10695 11:58:42.281200 the exact distribution terms for each program are described in the
10696 11:58:42.284957 individual files in /usr/share/doc/*/copyright.
10697 11:58:42.285420
10698 11:58:42.291327 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10699 11:58:42.294452 permitted by applicable law.
10700 11:58:42.295971 Matched prompt #10: / #
10702 11:58:42.297146 Setting prompt string to ['/ #']
10703 11:58:42.297676 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10705 11:58:42.298772 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10706 11:58:42.299250 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
10707 11:58:42.299677 Setting prompt string to ['/ #']
10708 11:58:42.300053 Forcing a shell prompt, looking for ['/ #']
10710 11:58:42.351141 / #
10711 11:58:42.351767 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10712 11:58:42.352207 Waiting using forced prompt support (timeout 00:02:30)
10713 11:58:42.352771 <4>[ 19.383212] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10714 11:58:42.357279
10715 11:58:42.358211 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10716 11:58:42.358740 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
10717 11:58:42.359258 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10718 11:58:42.359770 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
10719 11:58:42.360275 end: 2 depthcharge-action (duration 00:01:31) [common]
10720 11:58:42.360819 start: 3 lava-test-retry (timeout 00:08:10) [common]
10721 11:58:42.361291 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
10722 11:58:42.361704 Using namespace: common
10724 11:58:42.462809 / # #
10725 11:58:42.463418 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10726 11:58:42.464088 #<4>[ 19.502685] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10727 11:58:42.469085
10728 11:58:42.469991 Using /lava-12066571
10730 11:58:42.571082 / # export SHELL=/bin/sh
10731 11:58:42.571840 export SHELL=/bin/sh<3>[ 19.616274] mt7921e 0000:01:00.0: hardware init failed
10732 11:58:42.576912
10734 11:58:42.678500 / # . /lava-12066571/environment
10735 11:58:42.684732 . /lava-12066571/environment
10737 11:58:42.786392 / # /lava-12066571/bin/lava-test-runner /lava-12066571/0
10738 11:58:42.786981 Test shell timeout: 10s (minimum of the action and connection timeout)
10739 11:58:42.792750 /lava-12066571/bin/lava-test-runner /lava-12066571/0
10740 11:58:42.815822 + export TESTRUN_ID=0_v4l2-compliance-uvc
10741 11:58:42.819403 + cd /lava-12066571/0/tests/0_v4l2-compliance-uvc
10742 11:58:42.819941 + cat uuid
10743 11:58:42.822390 + UUID=12066571_1.5.2.3.1
10744 11:58:42.822854 + set +x
10745 11:58:42.828947 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12066571_1.5.2.3.1>
10746 11:58:42.829694 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12066571_1.5.2.3.1
10747 11:58:42.830112 Starting test lava.0_v4l2-compliance-uvc (12066571_1.5.2.3.1)
10748 11:58:42.830544 Skipping test definition patterns.
10749 11:58:42.832485 + /usr/bin/v4l2-parser.sh -d uvcvideo
10750 11:58:42.838983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10751 11:58:42.839509 device: /dev/video0
10752 11:58:42.840147 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10754 12:06:52.361623 Marking unfinished test run as failed
10757 12:06:52.363169 end: 3.1 lava-test-shell (duration 00:08:10) [common]
10759 12:06:52.364137 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 490 seconds'
10761 12:06:52.364973 end: 3 lava-test-retry (duration 00:08:10) [common]
10763 12:06:52.366411 Cleaning after the job
10764 12:06:52.366924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/ramdisk
10765 12:06:52.372328 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/kernel
10766 12:06:52.387490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/dtb
10767 12:06:52.387683 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066571/tftp-deploy-hke564pf/modules
10768 12:06:52.394785 start: 4.1 power-off (timeout 00:00:30) [common]
10769 12:06:52.394953 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10770 12:06:52.473611 >> Command sent successfully.
10771 12:06:52.478227 Returned 0 in 0 seconds
10772 12:06:52.579265 end: 4.1 power-off (duration 00:00:00) [common]
10774 12:06:52.581608 start: 4.2 read-feedback (timeout 00:10:00) [common]
10775 12:06:52.583145 Listened to connection for namespace 'common' for up to 1s
10776 12:06:53.583806 Finalising connection for namespace 'common'
10777 12:06:53.584473 Disconnecting from shell: Finalise
10778 12:06:53.685598 end: 4.2 read-feedback (duration 00:00:01) [common]
10779 12:06:53.686225 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066571
10780 12:06:53.794256 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066571
10781 12:06:53.794447 TestError: A test failed to run, look at the error message.