Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 36
- Kernel Warnings: 20
- Boot result: FAIL
- Errors: 2
1 11:55:15.360935 lava-dispatcher, installed at version: 2023.10
2 11:55:15.361126 start: 0 validate
3 11:55:15.361252 Start time: 2023-11-23 11:55:15.361244+00:00 (UTC)
4 11:55:15.361367 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:55:15.361496 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:55:15.641138 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:55:15.641898 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:55:15.923773 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:55:15.924701 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:55:16.198578 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:55:16.199338 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:55:16.474341 validate duration: 1.11
14 11:55:16.474668 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:55:16.474767 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:55:16.474857 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:55:16.474986 Not decompressing ramdisk as can be used compressed.
18 11:55:16.475077 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 11:55:16.475191 saving as /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/ramdisk/rootfs.cpio.gz
20 11:55:16.475288 total size: 34390042 (32 MB)
21 11:55:16.476369 progress 0 % (0 MB)
22 11:55:16.484990 progress 5 % (1 MB)
23 11:55:16.493432 progress 10 % (3 MB)
24 11:55:16.502111 progress 15 % (4 MB)
25 11:55:16.510743 progress 20 % (6 MB)
26 11:55:16.519934 progress 25 % (8 MB)
27 11:55:16.528942 progress 30 % (9 MB)
28 11:55:16.537626 progress 35 % (11 MB)
29 11:55:16.546045 progress 40 % (13 MB)
30 11:55:16.554645 progress 45 % (14 MB)
31 11:55:16.563051 progress 50 % (16 MB)
32 11:55:16.571725 progress 55 % (18 MB)
33 11:55:16.580200 progress 60 % (19 MB)
34 11:55:16.588799 progress 65 % (21 MB)
35 11:55:16.597571 progress 70 % (22 MB)
36 11:55:16.607071 progress 75 % (24 MB)
37 11:55:16.616274 progress 80 % (26 MB)
38 11:55:16.625640 progress 85 % (27 MB)
39 11:55:16.634274 progress 90 % (29 MB)
40 11:55:16.642929 progress 95 % (31 MB)
41 11:55:16.651335 progress 100 % (32 MB)
42 11:55:16.651512 32 MB downloaded in 0.18 s (186.11 MB/s)
43 11:55:16.651669 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:55:16.651975 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:55:16.652067 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:55:16.652155 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:55:16.652292 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:55:16.652366 saving as /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/kernel/Image
50 11:55:16.652429 total size: 49107456 (46 MB)
51 11:55:16.652491 No compression specified
52 11:55:16.653571 progress 0 % (0 MB)
53 11:55:16.665738 progress 5 % (2 MB)
54 11:55:16.677978 progress 10 % (4 MB)
55 11:55:16.690138 progress 15 % (7 MB)
56 11:55:16.702214 progress 20 % (9 MB)
57 11:55:16.714660 progress 25 % (11 MB)
58 11:55:16.727076 progress 30 % (14 MB)
59 11:55:16.739498 progress 35 % (16 MB)
60 11:55:16.751859 progress 40 % (18 MB)
61 11:55:16.764200 progress 45 % (21 MB)
62 11:55:16.776502 progress 50 % (23 MB)
63 11:55:16.788878 progress 55 % (25 MB)
64 11:55:16.801178 progress 60 % (28 MB)
65 11:55:16.813386 progress 65 % (30 MB)
66 11:55:16.825615 progress 70 % (32 MB)
67 11:55:16.837658 progress 75 % (35 MB)
68 11:55:16.849811 progress 80 % (37 MB)
69 11:55:16.861939 progress 85 % (39 MB)
70 11:55:16.874070 progress 90 % (42 MB)
71 11:55:16.886051 progress 95 % (44 MB)
72 11:55:16.897993 progress 100 % (46 MB)
73 11:55:16.898194 46 MB downloaded in 0.25 s (190.56 MB/s)
74 11:55:16.898346 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:55:16.898618 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:55:16.898713 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:55:16.898802 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:55:16.898940 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:55:16.899011 saving as /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/dtb/mt8192-asurada-spherion-r0.dtb
81 11:55:16.899074 total size: 47278 (0 MB)
82 11:55:16.899136 No compression specified
83 11:55:16.900309 progress 69 % (0 MB)
84 11:55:16.900583 progress 100 % (0 MB)
85 11:55:16.900738 0 MB downloaded in 0.00 s (27.13 MB/s)
86 11:55:16.900861 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:55:16.901082 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:55:16.901167 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:55:16.901249 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:55:16.901361 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:55:16.901433 saving as /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/modules/modules.tar
93 11:55:16.901495 total size: 8621364 (8 MB)
94 11:55:16.901557 Using unxz to decompress xz
95 11:55:16.905187 progress 0 % (0 MB)
96 11:55:16.925752 progress 5 % (0 MB)
97 11:55:16.948518 progress 10 % (0 MB)
98 11:55:16.971456 progress 15 % (1 MB)
99 11:55:16.994221 progress 20 % (1 MB)
100 11:55:17.018268 progress 25 % (2 MB)
101 11:55:17.043529 progress 30 % (2 MB)
102 11:55:17.068835 progress 35 % (2 MB)
103 11:55:17.091387 progress 40 % (3 MB)
104 11:55:17.115138 progress 45 % (3 MB)
105 11:55:17.140000 progress 50 % (4 MB)
106 11:55:17.163608 progress 55 % (4 MB)
107 11:55:17.187727 progress 60 % (4 MB)
108 11:55:17.214658 progress 65 % (5 MB)
109 11:55:17.239077 progress 70 % (5 MB)
110 11:55:17.261658 progress 75 % (6 MB)
111 11:55:17.287682 progress 80 % (6 MB)
112 11:55:17.312696 progress 85 % (7 MB)
113 11:55:17.337137 progress 90 % (7 MB)
114 11:55:17.365568 progress 95 % (7 MB)
115 11:55:17.394370 progress 100 % (8 MB)
116 11:55:17.399026 8 MB downloaded in 0.50 s (16.53 MB/s)
117 11:55:17.399267 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:55:17.399522 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:55:17.399614 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:55:17.399726 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:55:17.399849 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:55:17.399933 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:55:17.400145 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye
125 11:55:17.400272 makedir: /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin
126 11:55:17.400375 makedir: /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/tests
127 11:55:17.400469 makedir: /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/results
128 11:55:17.400583 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-add-keys
129 11:55:17.400728 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-add-sources
130 11:55:17.400851 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-background-process-start
131 11:55:17.400976 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-background-process-stop
132 11:55:17.401095 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-common-functions
133 11:55:17.401213 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-echo-ipv4
134 11:55:17.401331 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-install-packages
135 11:55:17.401449 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-installed-packages
136 11:55:17.401564 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-os-build
137 11:55:17.401682 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-probe-channel
138 11:55:17.401799 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-probe-ip
139 11:55:17.401917 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-target-ip
140 11:55:17.402033 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-target-mac
141 11:55:17.402149 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-target-storage
142 11:55:17.402270 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-case
143 11:55:17.402392 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-event
144 11:55:17.402544 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-feedback
145 11:55:17.402662 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-raise
146 11:55:17.402780 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-reference
147 11:55:17.402897 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-runner
148 11:55:17.403014 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-set
149 11:55:17.403131 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-test-shell
150 11:55:17.403250 Updating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-install-packages (oe)
151 11:55:17.403395 Updating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/bin/lava-installed-packages (oe)
152 11:55:17.403512 Creating /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/environment
153 11:55:17.403607 LAVA metadata
154 11:55:17.403679 - LAVA_JOB_ID=12066556
155 11:55:17.403742 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:55:17.403872 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:55:17.403972 skipped lava-vland-overlay
158 11:55:17.404046 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:55:17.404125 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:55:17.404189 skipped lava-multinode-overlay
161 11:55:17.404264 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:55:17.404347 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:55:17.404421 Loading test definitions
164 11:55:17.404558 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:55:17.404670 Using /lava-12066556 at stage 0
166 11:55:17.404960 uuid=12066556_1.5.2.3.1 testdef=None
167 11:55:17.405047 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:55:17.405133 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:55:17.405617 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:55:17.405837 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:55:17.406522 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:55:17.406747 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:55:17.407326 runner path: /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/0/tests/0_cros-ec test_uuid 12066556_1.5.2.3.1
176 11:55:17.407472 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:55:17.407674 Creating lava-test-runner.conf files
179 11:55:17.407736 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066556/lava-overlay-8cf90vye/lava-12066556/0 for stage 0
180 11:55:17.407821 - 0_cros-ec
181 11:55:17.407914 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:55:17.408045 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:55:17.414680 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:55:17.414789 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:55:17.414874 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:55:17.414958 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:55:17.415048 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:55:18.325929 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:55:18.326284 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:55:18.326424 extracting modules file /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066556/extract-overlay-ramdisk-di2wy__f/ramdisk
191 11:55:18.537954 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:55:18.538129 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:55:18.538226 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066556/compress-overlay-je1uftob/overlay-1.5.2.4.tar.gz to ramdisk
194 11:55:18.538299 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066556/compress-overlay-je1uftob/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066556/extract-overlay-ramdisk-di2wy__f/ramdisk
195 11:55:18.544553 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:55:18.544667 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:55:18.544758 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:55:18.544850 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:55:18.544931 Building ramdisk /var/lib/lava/dispatcher/tmp/12066556/extract-overlay-ramdisk-di2wy__f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066556/extract-overlay-ramdisk-di2wy__f/ramdisk
200 11:55:19.270851 >> 271067 blocks
201 11:55:23.900230 rename /var/lib/lava/dispatcher/tmp/12066556/extract-overlay-ramdisk-di2wy__f/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/ramdisk/ramdisk.cpio.gz
202 11:55:23.900673 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:55:23.900805 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:55:23.900907 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:55:23.901010 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/kernel/Image'
206 11:55:35.786869 Returned 0 in 11 seconds
207 11:55:35.887870 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/kernel/image.itb
208 11:55:36.615951 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:55:36.616306 output: Created: Thu Nov 23 11:55:36 2023
210 11:55:36.616381 output: Image 0 (kernel-1)
211 11:55:36.616451 output: Description:
212 11:55:36.616517 output: Created: Thu Nov 23 11:55:36 2023
213 11:55:36.616583 output: Type: Kernel Image
214 11:55:36.616647 output: Compression: lzma compressed
215 11:55:36.616706 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
216 11:55:36.616767 output: Architecture: AArch64
217 11:55:36.616826 output: OS: Linux
218 11:55:36.616883 output: Load Address: 0x00000000
219 11:55:36.616940 output: Entry Point: 0x00000000
220 11:55:36.616995 output: Hash algo: crc32
221 11:55:36.617050 output: Hash value: e6d7c86f
222 11:55:36.617107 output: Image 1 (fdt-1)
223 11:55:36.617162 output: Description: mt8192-asurada-spherion-r0
224 11:55:36.617216 output: Created: Thu Nov 23 11:55:36 2023
225 11:55:36.617271 output: Type: Flat Device Tree
226 11:55:36.617325 output: Compression: uncompressed
227 11:55:36.617379 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:55:36.617434 output: Architecture: AArch64
229 11:55:36.617488 output: Hash algo: crc32
230 11:55:36.617542 output: Hash value: cc4352de
231 11:55:36.617595 output: Image 2 (ramdisk-1)
232 11:55:36.617648 output: Description: unavailable
233 11:55:36.617701 output: Created: Thu Nov 23 11:55:36 2023
234 11:55:36.617755 output: Type: RAMDisk Image
235 11:55:36.617809 output: Compression: Unknown Compression
236 11:55:36.617862 output: Data Size: 47538113 Bytes = 46423.94 KiB = 45.34 MiB
237 11:55:36.617916 output: Architecture: AArch64
238 11:55:36.617969 output: OS: Linux
239 11:55:36.618023 output: Load Address: unavailable
240 11:55:36.618077 output: Entry Point: unavailable
241 11:55:36.618130 output: Hash algo: crc32
242 11:55:36.618183 output: Hash value: 3d4f0850
243 11:55:36.618237 output: Default Configuration: 'conf-1'
244 11:55:36.618290 output: Configuration 0 (conf-1)
245 11:55:36.618344 output: Description: mt8192-asurada-spherion-r0
246 11:55:36.618402 output: Kernel: kernel-1
247 11:55:36.618490 output: Init Ramdisk: ramdisk-1
248 11:55:36.618543 output: FDT: fdt-1
249 11:55:36.618597 output: Loadables: kernel-1
250 11:55:36.618649 output:
251 11:55:36.618841 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:55:36.618939 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:55:36.619047 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 11:55:36.619156 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 11:55:36.619243 No LXC device requested
256 11:55:36.619326 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:55:36.619414 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 11:55:36.619494 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:55:36.619567 Checking files for TFTP limit of 4294967296 bytes.
260 11:55:36.620051 end: 1 tftp-deploy (duration 00:00:20) [common]
261 11:55:36.620157 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:55:36.620251 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:55:36.620375 substitutions:
264 11:55:36.620443 - {DTB}: 12066556/tftp-deploy-ht9p51d_/dtb/mt8192-asurada-spherion-r0.dtb
265 11:55:36.620508 - {INITRD}: 12066556/tftp-deploy-ht9p51d_/ramdisk/ramdisk.cpio.gz
266 11:55:36.620568 - {KERNEL}: 12066556/tftp-deploy-ht9p51d_/kernel/Image
267 11:55:36.620627 - {LAVA_MAC}: None
268 11:55:36.620686 - {PRESEED_CONFIG}: None
269 11:55:36.620742 - {PRESEED_LOCAL}: None
270 11:55:36.620799 - {RAMDISK}: 12066556/tftp-deploy-ht9p51d_/ramdisk/ramdisk.cpio.gz
271 11:55:36.620855 - {ROOT_PART}: None
272 11:55:36.620910 - {ROOT}: None
273 11:55:36.620965 - {SERVER_IP}: 192.168.201.1
274 11:55:36.621019 - {TEE}: None
275 11:55:36.621088 Parsed boot commands:
276 11:55:36.621149 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:55:36.621323 Parsed boot commands: tftpboot 192.168.201.1 12066556/tftp-deploy-ht9p51d_/kernel/image.itb 12066556/tftp-deploy-ht9p51d_/kernel/cmdline
278 11:55:36.621412 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:55:36.621499 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:55:36.621591 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:55:36.621678 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:55:36.621747 Not connected, no need to disconnect.
283 11:55:36.621822 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:55:36.621900 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:55:36.621967 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 11:55:36.625312 Setting prompt string to ['lava-test: # ']
287 11:55:36.625634 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:55:36.625742 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:55:36.625843 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:55:36.625954 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:55:36.626212 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 11:55:41.773161 >> Command sent successfully.
293 11:55:41.784163 Returned 0 in 5 seconds
294 11:55:41.885547 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:55:41.887165 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:55:41.887716 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:55:41.888216 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:55:41.888612 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:55:41.889004 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:55:41.890308 [Enter `^Ec?' for help]
302 11:55:42.053843
303 11:55:42.054505
304 11:55:42.054916 F0: 102B 0000
305 11:55:42.055296
306 11:55:42.055639 F3: 1001 0000 [0200]
307 11:55:42.057782
308 11:55:42.058381 F3: 1001 0000
309 11:55:42.058814
310 11:55:42.059172 F7: 102D 0000
311 11:55:42.059514
312 11:55:42.060421 F1: 0000 0000
313 11:55:42.060904
314 11:55:42.061286 V0: 0000 0000 [0001]
315 11:55:42.061643
316 11:55:42.063602 00: 0007 8000
317 11:55:42.064106
318 11:55:42.064488 01: 0000 0000
319 11:55:42.064854
320 11:55:42.067018 BP: 0C00 0209 [0000]
321 11:55:42.067500
322 11:55:42.067887 G0: 1182 0000
323 11:55:42.068242
324 11:55:42.070948 EC: 0000 0021 [4000]
325 11:55:42.071430
326 11:55:42.071888 S7: 0000 0000 [0000]
327 11:55:42.072522
328 11:55:42.074476 CC: 0000 0000 [0001]
329 11:55:42.074959
330 11:55:42.075398 T0: 0000 0040 [010F]
331 11:55:42.075787
332 11:55:42.076139 Jump to BL
333 11:55:42.076479
334 11:55:42.101242
335 11:55:42.101812
336 11:55:42.102199
337 11:55:42.107653 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:55:42.111055 ARM64: Exception handlers installed.
339 11:55:42.114775 ARM64: Testing exception
340 11:55:42.118542 ARM64: Done test exception
341 11:55:42.124652 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:55:42.135304 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:55:42.141813 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:55:42.152604 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:55:42.158903 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:55:42.165609 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:55:42.177757 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:55:42.184849 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:55:42.203881 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:55:42.207256 WDT: Last reset was cold boot
351 11:55:42.210544 SPI1(PAD0) initialized at 2873684 Hz
352 11:55:42.213732 SPI5(PAD0) initialized at 992727 Hz
353 11:55:42.217457 VBOOT: Loading verstage.
354 11:55:42.223953 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:55:42.227325 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:55:42.230320 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:55:42.233593 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:55:42.241457 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:55:42.248307 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:55:42.258542 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:55:42.259147
362 11:55:42.259530
363 11:55:42.269019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:55:42.271795 ARM64: Exception handlers installed.
365 11:55:42.275248 ARM64: Testing exception
366 11:55:42.275826 ARM64: Done test exception
367 11:55:42.281774 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:55:42.284994 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:55:42.299688 Probing TPM: . done!
370 11:55:42.300262 TPM ready after 0 ms
371 11:55:42.306639 Connected to device vid:did:rid of 1ae0:0028:00
372 11:55:42.313820 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:55:42.369202 Initialized TPM device CR50 revision 0
374 11:55:42.381163 tlcl_send_startup: Startup return code is 0
375 11:55:42.381846 TPM: setup succeeded
376 11:55:42.392949 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:55:42.401561 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:55:42.411814 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:55:42.421126 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:55:42.424158 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:55:42.432434 in-header: 03 07 00 00 08 00 00 00
382 11:55:42.436642 in-data: aa e4 47 04 13 02 00 00
383 11:55:42.439749 Chrome EC: UHEPI supported
384 11:55:42.447113 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:55:42.451068 in-header: 03 ad 00 00 08 00 00 00
386 11:55:42.455097 in-data: 00 20 20 08 00 00 00 00
387 11:55:42.455533 Phase 1
388 11:55:42.458656 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:55:42.466278 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:55:42.469940 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:55:42.473590 Recovery requested (1009000e)
392 11:55:42.481889 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:55:42.487178 tlcl_extend: response is 0
394 11:55:42.496614 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:55:42.503163 tlcl_extend: response is 0
396 11:55:42.509492 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:55:42.529923 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:55:42.537071 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:55:42.537252
400 11:55:42.537336
401 11:55:42.546890 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:55:42.550328 ARM64: Exception handlers installed.
403 11:55:42.550552 ARM64: Testing exception
404 11:55:42.553492 ARM64: Done test exception
405 11:55:42.575599 pmic_efuse_setting: Set efuses in 11 msecs
406 11:55:42.578840 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:55:42.585524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:55:42.589865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:55:42.592910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:55:42.599833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:55:42.602934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:55:42.610231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:55:42.614263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:55:42.617506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:55:42.621100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:55:42.628776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:55:42.632280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:55:42.636217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:55:42.639304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:55:42.646701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:55:42.653509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:55:42.660856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:55:42.664329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:55:42.672278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:55:42.675511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:55:42.682074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:55:42.685942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:55:42.693245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:55:42.696126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:55:42.703053 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:55:42.709880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:55:42.713030 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:55:42.719898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:55:42.722978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:55:42.730117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:55:42.733674 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:55:42.740101 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:55:42.743084 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:55:42.750236 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:55:42.753244 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:55:42.760080 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:55:42.763174 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:55:42.769944 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:55:42.773274 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:55:42.780164 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:55:42.783724 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:55:42.787371 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:55:42.790827 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:55:42.797608 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:55:42.801019 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:55:42.804209 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:55:42.810695 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:55:42.813934 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:55:42.817326 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:55:42.821222 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:55:42.827562 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:55:42.830705 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:55:42.837538 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:55:42.847295 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:55:42.850969 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:55:42.857541 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:55:42.867351 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:55:42.870973 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:55:42.877405 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:55:42.880804 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:55:42.887906 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:55:42.894147 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:55:42.898292 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:55:42.900967 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:55:42.912780 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 11:55:42.922171 [RTC]rtc_get_frequency_meter,154: input=23, output=956
472 11:55:42.931225 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 11:55:42.940523 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 11:55:42.950273 [RTC]rtc_get_frequency_meter,154: input=16, output=794
475 11:55:42.953786 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 11:55:42.960377 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 11:55:42.963849 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 11:55:42.966996 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 11:55:42.970765 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 11:55:42.973913 ADC[4]: Raw value=902507 ID=7
481 11:55:42.977073 ADC[3]: Raw value=213179 ID=1
482 11:55:42.977695 RAM Code: 0x71
483 11:55:42.983892 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 11:55:42.986868 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 11:55:42.997101 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 11:55:43.004023 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 11:55:43.007515 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 11:55:43.010914 in-header: 03 07 00 00 08 00 00 00
489 11:55:43.014367 in-data: aa e4 47 04 13 02 00 00
490 11:55:43.017953 Chrome EC: UHEPI supported
491 11:55:43.024161 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 11:55:43.027335 in-header: 03 ed 00 00 08 00 00 00
493 11:55:43.031052 in-data: 80 20 60 08 00 00 00 00
494 11:55:43.034954 MRC: failed to locate region type 0.
495 11:55:43.041214 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 11:55:43.044394 DRAM-K: Running full calibration
497 11:55:43.047279 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 11:55:43.051089 header.status = 0x0
499 11:55:43.053854 header.version = 0x6 (expected: 0x6)
500 11:55:43.057806 header.size = 0xd00 (expected: 0xd00)
501 11:55:43.060885 header.flags = 0x0
502 11:55:43.064368 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 11:55:43.083322 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 11:55:43.089673 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 11:55:43.093323 dram_init: ddr_geometry: 2
506 11:55:43.096383 [EMI] MDL number = 2
507 11:55:43.097031 [EMI] Get MDL freq = 0
508 11:55:43.099861 dram_init: ddr_type: 0
509 11:55:43.100440 is_discrete_lpddr4: 1
510 11:55:43.102998 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 11:55:43.103477
512 11:55:43.103858
513 11:55:43.106462 [Bian_co] ETT version 0.0.0.1
514 11:55:43.110186 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 11:55:43.110864
516 11:55:43.117582 dramc_set_vcore_voltage set vcore to 650000
517 11:55:43.118162 Read voltage for 800, 4
518 11:55:43.118598 Vio18 = 0
519 11:55:43.121051 Vcore = 650000
520 11:55:43.121531 Vdram = 0
521 11:55:43.121936 Vddq = 0
522 11:55:43.124832 Vmddr = 0
523 11:55:43.125312 dram_init: config_dvfs: 1
524 11:55:43.132352 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 11:55:43.136254 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 11:55:43.139913 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 11:55:43.143355 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 11:55:43.147577 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 11:55:43.151425 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 11:55:43.154890 MEM_TYPE=3, freq_sel=18
531 11:55:43.155389 sv_algorithm_assistance_LP4_1600
532 11:55:43.162408 ============ PULL DRAM RESETB DOWN ============
533 11:55:43.165918 ========== PULL DRAM RESETB DOWN end =========
534 11:55:43.170044 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 11:55:43.173472 ===================================
536 11:55:43.174040 LPDDR4 DRAM CONFIGURATION
537 11:55:43.176564 ===================================
538 11:55:43.180138 EX_ROW_EN[0] = 0x0
539 11:55:43.183689 EX_ROW_EN[1] = 0x0
540 11:55:43.184177 LP4Y_EN = 0x0
541 11:55:43.186460 WORK_FSP = 0x0
542 11:55:43.186944 WL = 0x2
543 11:55:43.190200 RL = 0x2
544 11:55:43.190838 BL = 0x2
545 11:55:43.193388 RPST = 0x0
546 11:55:43.193970 RD_PRE = 0x0
547 11:55:43.196952 WR_PRE = 0x1
548 11:55:43.197561 WR_PST = 0x0
549 11:55:43.200438 DBI_WR = 0x0
550 11:55:43.201018 DBI_RD = 0x0
551 11:55:43.203820 OTF = 0x1
552 11:55:43.206778 ===================================
553 11:55:43.210547 ===================================
554 11:55:43.211124 ANA top config
555 11:55:43.213577 ===================================
556 11:55:43.217245 DLL_ASYNC_EN = 0
557 11:55:43.220147 ALL_SLAVE_EN = 1
558 11:55:43.220728 NEW_RANK_MODE = 1
559 11:55:43.223579 DLL_IDLE_MODE = 1
560 11:55:43.227503 LP45_APHY_COMB_EN = 1
561 11:55:43.231695 TX_ODT_DIS = 1
562 11:55:43.232268 NEW_8X_MODE = 1
563 11:55:43.235457 ===================================
564 11:55:43.239000 ===================================
565 11:55:43.242922 data_rate = 1600
566 11:55:43.243515 CKR = 1
567 11:55:43.246556 DQ_P2S_RATIO = 8
568 11:55:43.250548 ===================================
569 11:55:43.253823 CA_P2S_RATIO = 8
570 11:55:43.256983 DQ_CA_OPEN = 0
571 11:55:43.257469 DQ_SEMI_OPEN = 0
572 11:55:43.260318 CA_SEMI_OPEN = 0
573 11:55:43.264032 CA_FULL_RATE = 0
574 11:55:43.267139 DQ_CKDIV4_EN = 1
575 11:55:43.270778 CA_CKDIV4_EN = 1
576 11:55:43.274165 CA_PREDIV_EN = 0
577 11:55:43.274778 PH8_DLY = 0
578 11:55:43.277509 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 11:55:43.280792 DQ_AAMCK_DIV = 4
580 11:55:43.283836 CA_AAMCK_DIV = 4
581 11:55:43.287080 CA_ADMCK_DIV = 4
582 11:55:43.290914 DQ_TRACK_CA_EN = 0
583 11:55:43.291493 CA_PICK = 800
584 11:55:43.294018 CA_MCKIO = 800
585 11:55:43.297448 MCKIO_SEMI = 0
586 11:55:43.301154 PLL_FREQ = 3068
587 11:55:43.304391 DQ_UI_PI_RATIO = 32
588 11:55:43.307119 CA_UI_PI_RATIO = 0
589 11:55:43.310669 ===================================
590 11:55:43.314027 ===================================
591 11:55:43.314674 memory_type:LPDDR4
592 11:55:43.317194 GP_NUM : 10
593 11:55:43.320654 SRAM_EN : 1
594 11:55:43.321234 MD32_EN : 0
595 11:55:43.323910 ===================================
596 11:55:43.327774 [ANA_INIT] >>>>>>>>>>>>>>
597 11:55:43.331611 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 11:55:43.335522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:55:43.336104 ===================================
600 11:55:43.339190 data_rate = 1600,PCW = 0X7600
601 11:55:43.342749 ===================================
602 11:55:43.346472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 11:55:43.350086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 11:55:43.357524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 11:55:43.361172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 11:55:43.364561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 11:55:43.368103 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 11:55:43.371232 [ANA_INIT] flow start
609 11:55:43.371715 [ANA_INIT] PLL >>>>>>>>
610 11:55:43.374365 [ANA_INIT] PLL <<<<<<<<
611 11:55:43.377898 [ANA_INIT] MIDPI >>>>>>>>
612 11:55:43.381388 [ANA_INIT] MIDPI <<<<<<<<
613 11:55:43.381873 [ANA_INIT] DLL >>>>>>>>
614 11:55:43.384602 [ANA_INIT] flow end
615 11:55:43.388189 ============ LP4 DIFF to SE enter ============
616 11:55:43.391521 ============ LP4 DIFF to SE exit ============
617 11:55:43.394963 [ANA_INIT] <<<<<<<<<<<<<
618 11:55:43.397877 [Flow] Enable top DCM control >>>>>
619 11:55:43.401080 [Flow] Enable top DCM control <<<<<
620 11:55:43.405162 Enable DLL master slave shuffle
621 11:55:43.408375 ==============================================================
622 11:55:43.411344 Gating Mode config
623 11:55:43.418346 ==============================================================
624 11:55:43.418974 Config description:
625 11:55:43.428311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 11:55:43.434952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 11:55:43.441437 SELPH_MODE 0: By rank 1: By Phase
628 11:55:43.445145 ==============================================================
629 11:55:43.448281 GAT_TRACK_EN = 1
630 11:55:43.451135 RX_GATING_MODE = 2
631 11:55:43.454880 RX_GATING_TRACK_MODE = 2
632 11:55:43.458552 SELPH_MODE = 1
633 11:55:43.461820 PICG_EARLY_EN = 1
634 11:55:43.464595 VALID_LAT_VALUE = 1
635 11:55:43.468189 ==============================================================
636 11:55:43.471544 Enter into Gating configuration >>>>
637 11:55:43.474761 Exit from Gating configuration <<<<
638 11:55:43.478715 Enter into DVFS_PRE_config >>>>>
639 11:55:43.491788 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 11:55:43.492395 Exit from DVFS_PRE_config <<<<<
641 11:55:43.494939 Enter into PICG configuration >>>>
642 11:55:43.498179 Exit from PICG configuration <<<<
643 11:55:43.501772 [RX_INPUT] configuration >>>>>
644 11:55:43.505420 [RX_INPUT] configuration <<<<<
645 11:55:43.511612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 11:55:43.515227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 11:55:43.521573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 11:55:43.528721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 11:55:43.535292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 11:55:43.541973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 11:55:43.544978 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 11:55:43.548779 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 11:55:43.552079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 11:55:43.555807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 11:55:43.558942 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 11:55:43.565812 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 11:55:43.569330 ===================================
658 11:55:43.572349 LPDDR4 DRAM CONFIGURATION
659 11:55:43.572843 ===================================
660 11:55:43.575775 EX_ROW_EN[0] = 0x0
661 11:55:43.579095 EX_ROW_EN[1] = 0x0
662 11:55:43.579685 LP4Y_EN = 0x0
663 11:55:43.582087 WORK_FSP = 0x0
664 11:55:43.582621 WL = 0x2
665 11:55:43.585336 RL = 0x2
666 11:55:43.585893 BL = 0x2
667 11:55:43.588990 RPST = 0x0
668 11:55:43.589483 RD_PRE = 0x0
669 11:55:43.592673 WR_PRE = 0x1
670 11:55:43.593265 WR_PST = 0x0
671 11:55:43.595340 DBI_WR = 0x0
672 11:55:43.595836 DBI_RD = 0x0
673 11:55:43.598849 OTF = 0x1
674 11:55:43.602104 ===================================
675 11:55:43.605631 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 11:55:43.609107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 11:55:43.615936 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 11:55:43.618839 ===================================
679 11:55:43.619336 LPDDR4 DRAM CONFIGURATION
680 11:55:43.621973 ===================================
681 11:55:43.629693 EX_ROW_EN[0] = 0x10
682 11:55:43.630271 EX_ROW_EN[1] = 0x0
683 11:55:43.630765 LP4Y_EN = 0x0
684 11:55:43.632448 WORK_FSP = 0x0
685 11:55:43.632930 WL = 0x2
686 11:55:43.635386 RL = 0x2
687 11:55:43.635865 BL = 0x2
688 11:55:43.638815 RPST = 0x0
689 11:55:43.639298 RD_PRE = 0x0
690 11:55:43.642435 WR_PRE = 0x1
691 11:55:43.642921 WR_PST = 0x0
692 11:55:43.645591 DBI_WR = 0x0
693 11:55:43.646067 DBI_RD = 0x0
694 11:55:43.649407 OTF = 0x1
695 11:55:43.652469 ===================================
696 11:55:43.659285 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 11:55:43.662691 nWR fixed to 40
698 11:55:43.663267 [ModeRegInit_LP4] CH0 RK0
699 11:55:43.665737 [ModeRegInit_LP4] CH0 RK1
700 11:55:43.669179 [ModeRegInit_LP4] CH1 RK0
701 11:55:43.669751 [ModeRegInit_LP4] CH1 RK1
702 11:55:43.672275 match AC timing 13
703 11:55:43.675727 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 11:55:43.678909 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 11:55:43.685598 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 11:55:43.688904 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 11:55:43.695593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 11:55:43.696167 [EMI DOE] emi_dcm 0
709 11:55:43.701944 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 11:55:43.702446 ==
711 11:55:43.706018 Dram Type= 6, Freq= 0, CH_0, rank 0
712 11:55:43.709297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 11:55:43.709883 ==
714 11:55:43.712211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 11:55:43.719113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 11:55:43.729210 [CA 0] Center 38 (7~69) winsize 63
717 11:55:43.732768 [CA 1] Center 38 (7~69) winsize 63
718 11:55:43.735605 [CA 2] Center 35 (5~66) winsize 62
719 11:55:43.739187 [CA 3] Center 35 (5~66) winsize 62
720 11:55:43.742496 [CA 4] Center 35 (4~66) winsize 63
721 11:55:43.745770 [CA 5] Center 33 (3~64) winsize 62
722 11:55:43.746248
723 11:55:43.749331 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 11:55:43.749804
725 11:55:43.752963 [CATrainingPosCal] consider 1 rank data
726 11:55:43.756253 u2DelayCellTimex100 = 270/100 ps
727 11:55:43.759762 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 11:55:43.763489 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 11:55:43.766535 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 11:55:43.769880 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 11:55:43.773707 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
732 11:55:43.777355 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 11:55:43.777480
734 11:55:43.780638 CA PerBit enable=1, Macro0, CA PI delay=33
735 11:55:43.780761
736 11:55:43.784533 [CBTSetCACLKResult] CA Dly = 33
737 11:55:43.788512 CS Dly: 6 (0~37)
738 11:55:43.788618 ==
739 11:55:43.791804 Dram Type= 6, Freq= 0, CH_0, rank 1
740 11:55:43.795147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 11:55:43.795242 ==
742 11:55:43.798773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 11:55:43.805656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 11:55:43.815628 [CA 0] Center 38 (7~69) winsize 63
745 11:55:43.819558 [CA 1] Center 38 (7~69) winsize 63
746 11:55:43.823117 [CA 2] Center 36 (6~66) winsize 61
747 11:55:43.826999 [CA 3] Center 35 (5~66) winsize 62
748 11:55:43.830793 [CA 4] Center 35 (4~66) winsize 63
749 11:55:43.830879 [CA 5] Center 34 (4~65) winsize 62
750 11:55:43.830948
751 11:55:43.834462 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 11:55:43.837997
753 11:55:43.838083 [CATrainingPosCal] consider 2 rank data
754 11:55:43.841689 u2DelayCellTimex100 = 270/100 ps
755 11:55:43.845513 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 11:55:43.848881 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 11:55:43.852727 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 11:55:43.856335 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 11:55:43.860245 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
760 11:55:43.863970 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 11:55:43.864057
762 11:55:43.867660 CA PerBit enable=1, Macro0, CA PI delay=34
763 11:55:43.867748
764 11:55:43.871535 [CBTSetCACLKResult] CA Dly = 34
765 11:55:43.871621 CS Dly: 6 (0~38)
766 11:55:43.875049
767 11:55:43.875143 ----->DramcWriteLeveling(PI) begin...
768 11:55:43.878960 ==
769 11:55:43.879073 Dram Type= 6, Freq= 0, CH_0, rank 0
770 11:55:43.882769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 11:55:43.886320 ==
772 11:55:43.886449 Write leveling (Byte 0): 31 => 31
773 11:55:43.890261 Write leveling (Byte 1): 30 => 30
774 11:55:43.893441 DramcWriteLeveling(PI) end<-----
775 11:55:43.893529
776 11:55:43.893596 ==
777 11:55:43.897342 Dram Type= 6, Freq= 0, CH_0, rank 0
778 11:55:43.900939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 11:55:43.901041 ==
780 11:55:43.904608 [Gating] SW mode calibration
781 11:55:43.911939 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 11:55:43.916191 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 11:55:43.919585 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 11:55:43.927713 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 11:55:43.931075 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:55:43.934989 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:55:43.939058 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:55:43.942302 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:55:43.946828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:55:43.953458 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:55:43.957093 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:55:43.960548 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:55:43.964344 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:55:43.968785 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:55:43.975338 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:55:43.979438 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:55:43.982658 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:55:43.986620 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:55:43.990005 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:55:43.997946 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
801 11:55:44.001342 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 11:55:44.005420 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:55:44.009134 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:55:44.012467 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:55:44.016485 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:55:44.024057 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:55:44.027363 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:55:44.031230 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
809 11:55:44.035208 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 11:55:44.038608 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
811 11:55:44.046461 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:55:44.049973 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:55:44.053606 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 11:55:44.057440 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:55:44.061230 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:55:44.065116 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
817 11:55:44.072089 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
818 11:55:44.075955 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
819 11:55:44.079079 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:55:44.082301 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:55:44.089121 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:55:44.092051 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:55:44.095956 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:55:44.102431 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
825 11:55:44.105565 0 11 8 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
826 11:55:44.108700 0 11 12 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
827 11:55:44.115435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:55:44.118874 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:55:44.122367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 11:55:44.128997 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:55:44.132516 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:55:44.135432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 11:55:44.142706 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:55:44.145995 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:55:44.149014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:55:44.155791 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:55:44.158935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:55:44.162597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:55:44.166085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:55:44.172740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:55:44.175713 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:55:44.179035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:55:44.186257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:55:44.189475 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:55:44.192485 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:55:44.199283 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:55:44.202843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:55:44.205923 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 11:55:44.212683 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:55:44.215734 Total UI for P1: 0, mck2ui 16
851 11:55:44.219603 best dqsien dly found for B0: ( 0, 14, 4)
852 11:55:44.220186 Total UI for P1: 0, mck2ui 16
853 11:55:44.226058 best dqsien dly found for B1: ( 0, 14, 6)
854 11:55:44.229319 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 11:55:44.232723 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 11:55:44.233303
857 11:55:44.236083 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 11:55:44.239485 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 11:55:44.242931 [Gating] SW calibration Done
860 11:55:44.243514 ==
861 11:55:44.246010 Dram Type= 6, Freq= 0, CH_0, rank 0
862 11:55:44.249422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 11:55:44.249995 ==
864 11:55:44.252997 RX Vref Scan: 0
865 11:55:44.253573
866 11:55:44.253954 RX Vref 0 -> 0, step: 1
867 11:55:44.254304
868 11:55:44.256060 RX Delay -130 -> 252, step: 16
869 11:55:44.259283 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 11:55:44.266017 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 11:55:44.269480 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
872 11:55:44.272677 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
873 11:55:44.276398 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 11:55:44.279448 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 11:55:44.283000 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 11:55:44.289937 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 11:55:44.292950 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 11:55:44.296306 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 11:55:44.299557 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 11:55:44.303167 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 11:55:44.309704 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
882 11:55:44.312911 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 11:55:44.316225 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 11:55:44.319675 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 11:55:44.320256 ==
886 11:55:44.323030 Dram Type= 6, Freq= 0, CH_0, rank 0
887 11:55:44.329666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 11:55:44.330255 ==
889 11:55:44.330674 DQS Delay:
890 11:55:44.332756 DQS0 = 0, DQS1 = 0
891 11:55:44.333228 DQM Delay:
892 11:55:44.333605 DQM0 = 93, DQM1 = 80
893 11:55:44.336432 DQ Delay:
894 11:55:44.339833 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
895 11:55:44.343193 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 11:55:44.346379 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 11:55:44.349840 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
898 11:55:44.350460
899 11:55:44.350903
900 11:55:44.351270 ==
901 11:55:44.352960 Dram Type= 6, Freq= 0, CH_0, rank 0
902 11:55:44.356130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 11:55:44.356738 ==
904 11:55:44.357253
905 11:55:44.357790
906 11:55:44.359260 TX Vref Scan disable
907 11:55:44.362902 == TX Byte 0 ==
908 11:55:44.366435 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 11:55:44.369798 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 11:55:44.372803 == TX Byte 1 ==
911 11:55:44.376064 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 11:55:44.379380 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 11:55:44.379862 ==
914 11:55:44.382627 Dram Type= 6, Freq= 0, CH_0, rank 0
915 11:55:44.386186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 11:55:44.386717 ==
917 11:55:44.400596 TX Vref=22, minBit 6, minWin=27, winSum=441
918 11:55:44.403969 TX Vref=24, minBit 8, minWin=26, winSum=442
919 11:55:44.407326 TX Vref=26, minBit 6, minWin=27, winSum=444
920 11:55:44.410323 TX Vref=28, minBit 10, minWin=27, winSum=453
921 11:55:44.413522 TX Vref=30, minBit 6, minWin=28, winSum=456
922 11:55:44.420109 TX Vref=32, minBit 12, minWin=27, winSum=452
923 11:55:44.423560 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 30
924 11:55:44.424392
925 11:55:44.427179 Final TX Range 1 Vref 30
926 11:55:44.427671
927 11:55:44.428052 ==
928 11:55:44.430728 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:55:44.433727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:55:44.434217 ==
931 11:55:44.434699
932 11:55:44.437073
933 11:55:44.437551 TX Vref Scan disable
934 11:55:44.440258 == TX Byte 0 ==
935 11:55:44.444265 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 11:55:44.446831 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 11:55:44.450551 == TX Byte 1 ==
938 11:55:44.453689 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
939 11:55:44.457092 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
940 11:55:44.460583
941 11:55:44.461157 [DATLAT]
942 11:55:44.461543 Freq=800, CH0 RK0
943 11:55:44.461931
944 11:55:44.463815 DATLAT Default: 0xa
945 11:55:44.464401 0, 0xFFFF, sum = 0
946 11:55:44.466914 1, 0xFFFF, sum = 0
947 11:55:44.467399 2, 0xFFFF, sum = 0
948 11:55:44.470796 3, 0xFFFF, sum = 0
949 11:55:44.471396 4, 0xFFFF, sum = 0
950 11:55:44.474165 5, 0xFFFF, sum = 0
951 11:55:44.474812 6, 0xFFFF, sum = 0
952 11:55:44.477127 7, 0xFFFF, sum = 0
953 11:55:44.477617 8, 0xFFFF, sum = 0
954 11:55:44.480634 9, 0x0, sum = 1
955 11:55:44.481248 10, 0x0, sum = 2
956 11:55:44.483856 11, 0x0, sum = 3
957 11:55:44.484437 12, 0x0, sum = 4
958 11:55:44.487046 best_step = 10
959 11:55:44.487623
960 11:55:44.488292 ==
961 11:55:44.490255 Dram Type= 6, Freq= 0, CH_0, rank 0
962 11:55:44.493681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 11:55:44.494265 ==
964 11:55:44.497355 RX Vref Scan: 1
965 11:55:44.497936
966 11:55:44.498321 Set Vref Range= 32 -> 127
967 11:55:44.498785
968 11:55:44.500348 RX Vref 32 -> 127, step: 1
969 11:55:44.500829
970 11:55:44.503776 RX Delay -95 -> 252, step: 8
971 11:55:44.504352
972 11:55:44.507299 Set Vref, RX VrefLevel [Byte0]: 32
973 11:55:44.510623 [Byte1]: 32
974 11:55:44.511192
975 11:55:44.513928 Set Vref, RX VrefLevel [Byte0]: 33
976 11:55:44.517012 [Byte1]: 33
977 11:55:44.520793
978 11:55:44.521365 Set Vref, RX VrefLevel [Byte0]: 34
979 11:55:44.524169 [Byte1]: 34
980 11:55:44.528685
981 11:55:44.529258 Set Vref, RX VrefLevel [Byte0]: 35
982 11:55:44.531775 [Byte1]: 35
983 11:55:44.535976
984 11:55:44.536551 Set Vref, RX VrefLevel [Byte0]: 36
985 11:55:44.539239 [Byte1]: 36
986 11:55:44.544186
987 11:55:44.544760 Set Vref, RX VrefLevel [Byte0]: 37
988 11:55:44.546607 [Byte1]: 37
989 11:55:44.551259
990 11:55:44.551834 Set Vref, RX VrefLevel [Byte0]: 38
991 11:55:44.555009 [Byte1]: 38
992 11:55:44.558855
993 11:55:44.559329 Set Vref, RX VrefLevel [Byte0]: 39
994 11:55:44.562023 [Byte1]: 39
995 11:55:44.566187
996 11:55:44.566789 Set Vref, RX VrefLevel [Byte0]: 40
997 11:55:44.569333 [Byte1]: 40
998 11:55:44.573816
999 11:55:44.574417 Set Vref, RX VrefLevel [Byte0]: 41
1000 11:55:44.577336 [Byte1]: 41
1001 11:55:44.582692
1002 11:55:44.583263 Set Vref, RX VrefLevel [Byte0]: 42
1003 11:55:44.585557 [Byte1]: 42
1004 11:55:44.589040
1005 11:55:44.589521 Set Vref, RX VrefLevel [Byte0]: 43
1006 11:55:44.592879 [Byte1]: 43
1007 11:55:44.596688
1008 11:55:44.597172 Set Vref, RX VrefLevel [Byte0]: 44
1009 11:55:44.600362 [Byte1]: 44
1010 11:55:44.604853
1011 11:55:44.605425 Set Vref, RX VrefLevel [Byte0]: 45
1012 11:55:44.607706 [Byte1]: 45
1013 11:55:44.611786
1014 11:55:44.612263 Set Vref, RX VrefLevel [Byte0]: 46
1015 11:55:44.615588 [Byte1]: 46
1016 11:55:44.620142
1017 11:55:44.620622 Set Vref, RX VrefLevel [Byte0]: 47
1018 11:55:44.622501 [Byte1]: 47
1019 11:55:44.626897
1020 11:55:44.627372 Set Vref, RX VrefLevel [Byte0]: 48
1021 11:55:44.630958 [Byte1]: 48
1022 11:55:44.634348
1023 11:55:44.634850 Set Vref, RX VrefLevel [Byte0]: 49
1024 11:55:44.637966 [Byte1]: 49
1025 11:55:44.642368
1026 11:55:44.642985 Set Vref, RX VrefLevel [Byte0]: 50
1027 11:55:44.645887 [Byte1]: 50
1028 11:55:44.649793
1029 11:55:44.650262 Set Vref, RX VrefLevel [Byte0]: 51
1030 11:55:44.652831 [Byte1]: 51
1031 11:55:44.657673
1032 11:55:44.658240 Set Vref, RX VrefLevel [Byte0]: 52
1033 11:55:44.660871 [Byte1]: 52
1034 11:55:44.665150
1035 11:55:44.665734 Set Vref, RX VrefLevel [Byte0]: 53
1036 11:55:44.668314 [Byte1]: 53
1037 11:55:44.672565
1038 11:55:44.673127 Set Vref, RX VrefLevel [Byte0]: 54
1039 11:55:44.675783 [Byte1]: 54
1040 11:55:44.680698
1041 11:55:44.681262 Set Vref, RX VrefLevel [Byte0]: 55
1042 11:55:44.683815 [Byte1]: 55
1043 11:55:44.687669
1044 11:55:44.688229 Set Vref, RX VrefLevel [Byte0]: 56
1045 11:55:44.691457 [Byte1]: 56
1046 11:55:44.695806
1047 11:55:44.696368 Set Vref, RX VrefLevel [Byte0]: 57
1048 11:55:44.698850 [Byte1]: 57
1049 11:55:44.703185
1050 11:55:44.703745 Set Vref, RX VrefLevel [Byte0]: 58
1051 11:55:44.706518 [Byte1]: 58
1052 11:55:44.711072
1053 11:55:44.711632 Set Vref, RX VrefLevel [Byte0]: 59
1054 11:55:44.713867 [Byte1]: 59
1055 11:55:44.718338
1056 11:55:44.718951 Set Vref, RX VrefLevel [Byte0]: 60
1057 11:55:44.721329 [Byte1]: 60
1058 11:55:44.726046
1059 11:55:44.726638 Set Vref, RX VrefLevel [Byte0]: 61
1060 11:55:44.729142 [Byte1]: 61
1061 11:55:44.733458
1062 11:55:44.734100 Set Vref, RX VrefLevel [Byte0]: 62
1063 11:55:44.736913 [Byte1]: 62
1064 11:55:44.741208
1065 11:55:44.741767 Set Vref, RX VrefLevel [Byte0]: 63
1066 11:55:44.744872 [Byte1]: 63
1067 11:55:44.748652
1068 11:55:44.749212 Set Vref, RX VrefLevel [Byte0]: 64
1069 11:55:44.752128 [Byte1]: 64
1070 11:55:44.756342
1071 11:55:44.756906 Set Vref, RX VrefLevel [Byte0]: 65
1072 11:55:44.759665 [Byte1]: 65
1073 11:55:44.763812
1074 11:55:44.764374 Set Vref, RX VrefLevel [Byte0]: 66
1075 11:55:44.767102 [Byte1]: 66
1076 11:55:44.771918
1077 11:55:44.772485 Set Vref, RX VrefLevel [Byte0]: 67
1078 11:55:44.774651 [Byte1]: 67
1079 11:55:44.778786
1080 11:55:44.779324 Set Vref, RX VrefLevel [Byte0]: 68
1081 11:55:44.782169 [Byte1]: 68
1082 11:55:44.786526
1083 11:55:44.787084 Set Vref, RX VrefLevel [Byte0]: 69
1084 11:55:44.789886 [Byte1]: 69
1085 11:55:44.793906
1086 11:55:44.794374 Set Vref, RX VrefLevel [Byte0]: 70
1087 11:55:44.797725 [Byte1]: 70
1088 11:55:44.801715
1089 11:55:44.802282 Set Vref, RX VrefLevel [Byte0]: 71
1090 11:55:44.805274 [Byte1]: 71
1091 11:55:44.809648
1092 11:55:44.810209 Set Vref, RX VrefLevel [Byte0]: 72
1093 11:55:44.812532 [Byte1]: 72
1094 11:55:44.817046
1095 11:55:44.817510 Set Vref, RX VrefLevel [Byte0]: 73
1096 11:55:44.820431 [Byte1]: 73
1097 11:55:44.824874
1098 11:55:44.825462 Set Vref, RX VrefLevel [Byte0]: 74
1099 11:55:44.827774 [Byte1]: 74
1100 11:55:44.832117
1101 11:55:44.832683 Set Vref, RX VrefLevel [Byte0]: 75
1102 11:55:44.835654 [Byte1]: 75
1103 11:55:44.839564
1104 11:55:44.840027 Set Vref, RX VrefLevel [Byte0]: 76
1105 11:55:44.843063 [Byte1]: 76
1106 11:55:44.847380
1107 11:55:44.847943 Set Vref, RX VrefLevel [Byte0]: 77
1108 11:55:44.850439 [Byte1]: 77
1109 11:55:44.855001
1110 11:55:44.858574 Final RX Vref Byte 0 = 61 to rank0
1111 11:55:44.859145 Final RX Vref Byte 1 = 63 to rank0
1112 11:55:44.861340 Final RX Vref Byte 0 = 61 to rank1
1113 11:55:44.864756 Final RX Vref Byte 1 = 63 to rank1==
1114 11:55:44.868267 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 11:55:44.874905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 11:55:44.875474 ==
1117 11:55:44.875854 DQS Delay:
1118 11:55:44.878037 DQS0 = 0, DQS1 = 0
1119 11:55:44.878597 DQM Delay:
1120 11:55:44.879001 DQM0 = 93, DQM1 = 83
1121 11:55:44.881545 DQ Delay:
1122 11:55:44.885160 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1123 11:55:44.887940 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1124 11:55:44.891453 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1125 11:55:44.894572 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1126 11:55:44.895042
1127 11:55:44.895415
1128 11:55:44.901517 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1129 11:55:44.904792 CH0 RK0: MR19=606, MR18=3A35
1130 11:55:44.911528 CH0_RK0: MR19=0x606, MR18=0x3A35, DQSOSC=395, MR23=63, INC=94, DEC=63
1131 11:55:44.912096
1132 11:55:44.914718 ----->DramcWriteLeveling(PI) begin...
1133 11:55:44.915192 ==
1134 11:55:44.917890 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 11:55:44.921032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 11:55:44.921504 ==
1137 11:55:44.924378 Write leveling (Byte 0): 34 => 34
1138 11:55:44.928003 Write leveling (Byte 1): 27 => 27
1139 11:55:44.931297 DramcWriteLeveling(PI) end<-----
1140 11:55:44.931868
1141 11:55:44.932241 ==
1142 11:55:44.934846 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 11:55:44.937963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 11:55:44.938579 ==
1145 11:55:44.941480 [Gating] SW mode calibration
1146 11:55:44.948315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 11:55:44.954981 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 11:55:44.958283 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 11:55:44.961921 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 11:55:44.968297 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:55:44.971551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:55:44.975083 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:55:45.022261 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:55:45.022960 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:55:45.023468 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:55:45.024287 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:55:45.024897 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:55:45.025507 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:55:45.026040 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:55:45.026554 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:55:45.026901 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:55:45.027305 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:55:45.027645 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:55:45.027963 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1165 11:55:45.034085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1166 11:55:45.037025 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1167 11:55:45.041256 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:55:45.047047 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:55:45.050634 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:55:45.054493 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:55:45.060879 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:55:45.064235 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:55:45.067340 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1174 11:55:45.074611 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1175 11:55:45.077317 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 11:55:45.080500 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 11:55:45.087261 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:55:45.090440 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 11:55:45.094079 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 11:55:45.101464 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:55:45.104123 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
1182 11:55:45.107262 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
1183 11:55:45.110784 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:55:45.117751 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:55:45.121460 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:55:45.124104 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:55:45.130894 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:55:45.134525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:55:45.137249 0 11 4 | B1->B0 | 2525 2f2f | 1 0 | (0 0) (0 0)
1190 11:55:45.144123 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1191 11:55:45.147817 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 11:55:45.151212 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 11:55:45.158469 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:55:45.161636 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:55:45.164994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:55:45.169513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:55:45.173230 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:55:45.179292 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:55:45.182995 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:55:45.187196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:55:45.190031 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:55:45.197081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:55:45.200002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:55:45.203625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:55:45.210247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:55:45.213760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:55:45.216918 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:55:45.223263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:55:45.226754 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:55:45.230235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:55:45.237061 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:55:45.240698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:55:45.243843 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 11:55:45.246888 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 11:55:45.253837 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 11:55:45.257135 Total UI for P1: 0, mck2ui 16
1217 11:55:45.260788 best dqsien dly found for B0: ( 0, 14, 6)
1218 11:55:45.264049 Total UI for P1: 0, mck2ui 16
1219 11:55:45.267285 best dqsien dly found for B1: ( 0, 14, 8)
1220 11:55:45.270563 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1221 11:55:45.273615 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 11:55:45.274184
1223 11:55:45.277223 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 11:55:45.280302 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 11:55:45.283445 [Gating] SW calibration Done
1226 11:55:45.283923 ==
1227 11:55:45.287024 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 11:55:45.290888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 11:55:45.291497 ==
1230 11:55:45.293772 RX Vref Scan: 0
1231 11:55:45.294245
1232 11:55:45.294669 RX Vref 0 -> 0, step: 1
1233 11:55:45.295028
1234 11:55:45.297024 RX Delay -130 -> 252, step: 16
1235 11:55:45.300208 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1236 11:55:45.307306 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 11:55:45.310852 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1238 11:55:45.313462 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1239 11:55:45.317236 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 11:55:45.320735 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1241 11:55:45.327565 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 11:55:45.330141 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1243 11:55:45.333891 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1244 11:55:45.337451 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1245 11:55:45.340285 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1246 11:55:45.347301 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1247 11:55:45.350577 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1248 11:55:45.353850 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1249 11:55:45.357229 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 11:55:45.360982 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1251 11:55:45.361561 ==
1252 11:55:45.364078 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 11:55:45.370916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 11:55:45.371498 ==
1255 11:55:45.371878 DQS Delay:
1256 11:55:45.374214 DQS0 = 0, DQS1 = 0
1257 11:55:45.374841 DQM Delay:
1258 11:55:45.375222 DQM0 = 91, DQM1 = 82
1259 11:55:45.377416 DQ Delay:
1260 11:55:45.380599 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1261 11:55:45.383855 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1262 11:55:45.387679 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1263 11:55:45.391204 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1264 11:55:45.391772
1265 11:55:45.392145
1266 11:55:45.392490 ==
1267 11:55:45.393697 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 11:55:45.397622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 11:55:45.398192 ==
1270 11:55:45.398627
1271 11:55:45.398968
1272 11:55:45.400769 TX Vref Scan disable
1273 11:55:45.404166 == TX Byte 0 ==
1274 11:55:45.407692 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1275 11:55:45.410809 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1276 11:55:45.414609 == TX Byte 1 ==
1277 11:55:45.417918 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1278 11:55:45.420824 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1279 11:55:45.421396 ==
1280 11:55:45.423890 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 11:55:45.427749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 11:55:45.428328 ==
1283 11:55:45.442588 TX Vref=22, minBit 8, minWin=27, winSum=448
1284 11:55:45.445989 TX Vref=24, minBit 8, minWin=27, winSum=451
1285 11:55:45.449025 TX Vref=26, minBit 8, minWin=27, winSum=454
1286 11:55:45.452351 TX Vref=28, minBit 10, minWin=27, winSum=454
1287 11:55:45.455758 TX Vref=30, minBit 8, minWin=28, winSum=458
1288 11:55:45.462605 TX Vref=32, minBit 8, minWin=27, winSum=460
1289 11:55:45.465715 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1290 11:55:45.466184
1291 11:55:45.469627 Final TX Range 1 Vref 30
1292 11:55:45.470194
1293 11:55:45.470624 ==
1294 11:55:45.472781 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 11:55:45.475836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 11:55:45.476297 ==
1297 11:55:45.479327
1298 11:55:45.479778
1299 11:55:45.480138 TX Vref Scan disable
1300 11:55:45.482493 == TX Byte 0 ==
1301 11:55:45.486036 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1302 11:55:45.492858 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1303 11:55:45.493509 == TX Byte 1 ==
1304 11:55:45.495915 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1305 11:55:45.499274 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1306 11:55:45.502679
1307 11:55:45.503003 [DATLAT]
1308 11:55:45.503258 Freq=800, CH0 RK1
1309 11:55:45.503503
1310 11:55:45.506159 DATLAT Default: 0xa
1311 11:55:45.506513 0, 0xFFFF, sum = 0
1312 11:55:45.509438 1, 0xFFFF, sum = 0
1313 11:55:45.509782 2, 0xFFFF, sum = 0
1314 11:55:45.512597 3, 0xFFFF, sum = 0
1315 11:55:45.512935 4, 0xFFFF, sum = 0
1316 11:55:45.515849 5, 0xFFFF, sum = 0
1317 11:55:45.516096 6, 0xFFFF, sum = 0
1318 11:55:45.519185 7, 0xFFFF, sum = 0
1319 11:55:45.522715 8, 0xFFFF, sum = 0
1320 11:55:45.523055 9, 0x0, sum = 1
1321 11:55:45.523262 10, 0x0, sum = 2
1322 11:55:45.525762 11, 0x0, sum = 3
1323 11:55:45.526007 12, 0x0, sum = 4
1324 11:55:45.529160 best_step = 10
1325 11:55:45.529489
1326 11:55:45.529694 ==
1327 11:55:45.532803 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:55:45.536201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:55:45.536447 ==
1330 11:55:45.539087 RX Vref Scan: 0
1331 11:55:45.539329
1332 11:55:45.539522 RX Vref 0 -> 0, step: 1
1333 11:55:45.539702
1334 11:55:45.543079 RX Delay -79 -> 252, step: 8
1335 11:55:45.549800 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 11:55:45.553030 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1337 11:55:45.556281 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1338 11:55:45.559753 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1339 11:55:45.563265 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1340 11:55:45.570257 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1341 11:55:45.573101 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 11:55:45.576199 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 11:55:45.579787 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1344 11:55:45.582729 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 11:55:45.589775 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1346 11:55:45.592999 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1347 11:55:45.596321 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1348 11:55:45.599533 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1349 11:55:45.603158 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 11:55:45.610141 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1351 11:55:45.610757 ==
1352 11:55:45.613649 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 11:55:45.616581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 11:55:45.617052 ==
1355 11:55:45.617422 DQS Delay:
1356 11:55:45.620054 DQS0 = 0, DQS1 = 0
1357 11:55:45.620625 DQM Delay:
1358 11:55:45.623302 DQM0 = 91, DQM1 = 80
1359 11:55:45.623866 DQ Delay:
1360 11:55:45.626932 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1361 11:55:45.629845 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1362 11:55:45.633209 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1363 11:55:45.636427 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =84
1364 11:55:45.636894
1365 11:55:45.637263
1366 11:55:45.643246 [DQSOSCAuto] RK1, (LSB)MR18= 0x4620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1367 11:55:45.646477 CH0 RK1: MR19=606, MR18=4620
1368 11:55:45.653421 CH0_RK1: MR19=0x606, MR18=0x4620, DQSOSC=392, MR23=63, INC=96, DEC=64
1369 11:55:45.656539 [RxdqsGatingPostProcess] freq 800
1370 11:55:45.663661 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 11:55:45.664234 Pre-setting of DQS Precalculation
1372 11:55:45.670119 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 11:55:45.670739 ==
1374 11:55:45.673194 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 11:55:45.676819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 11:55:45.677404 ==
1377 11:55:45.683441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 11:55:45.690525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 11:55:45.697842 [CA 0] Center 36 (6~67) winsize 62
1380 11:55:45.701251 [CA 1] Center 36 (6~67) winsize 62
1381 11:55:45.704522 [CA 2] Center 35 (5~65) winsize 61
1382 11:55:45.707963 [CA 3] Center 34 (4~65) winsize 62
1383 11:55:45.711685 [CA 4] Center 34 (4~65) winsize 62
1384 11:55:45.714608 [CA 5] Center 34 (3~65) winsize 63
1385 11:55:45.715169
1386 11:55:45.717520 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1387 11:55:45.718255
1388 11:55:45.720990 [CATrainingPosCal] consider 1 rank data
1389 11:55:45.724082 u2DelayCellTimex100 = 270/100 ps
1390 11:55:45.727591 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1391 11:55:45.731311 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 11:55:45.738099 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1393 11:55:45.741024 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1394 11:55:45.744270 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 11:55:45.747748 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1396 11:55:45.748311
1397 11:55:45.751086 CA PerBit enable=1, Macro0, CA PI delay=34
1398 11:55:45.751674
1399 11:55:45.754361 [CBTSetCACLKResult] CA Dly = 34
1400 11:55:45.754888 CS Dly: 5 (0~36)
1401 11:55:45.755386 ==
1402 11:55:45.757778 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 11:55:45.764432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 11:55:45.765025 ==
1405 11:55:45.768261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 11:55:45.774486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 11:55:45.784099 [CA 0] Center 36 (6~67) winsize 62
1408 11:55:45.787368 [CA 1] Center 37 (6~68) winsize 63
1409 11:55:45.790787 [CA 2] Center 35 (5~66) winsize 62
1410 11:55:45.794221 [CA 3] Center 34 (4~65) winsize 62
1411 11:55:45.797235 [CA 4] Center 34 (4~65) winsize 62
1412 11:55:45.800970 [CA 5] Center 34 (3~65) winsize 63
1413 11:55:45.801563
1414 11:55:45.804741 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1415 11:55:45.805438
1416 11:55:45.808107 [CATrainingPosCal] consider 2 rank data
1417 11:55:45.810547 u2DelayCellTimex100 = 270/100 ps
1418 11:55:45.814492 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 11:55:45.817645 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 11:55:45.824350 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 11:55:45.824932 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 11:55:45.828642 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 11:55:45.832070 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1424 11:55:45.832578
1425 11:55:45.835420 CA PerBit enable=1, Macro0, CA PI delay=34
1426 11:55:45.839528
1427 11:55:45.840015 [CBTSetCACLKResult] CA Dly = 34
1428 11:55:45.842871 CS Dly: 6 (0~38)
1429 11:55:45.843472
1430 11:55:45.847008 ----->DramcWriteLeveling(PI) begin...
1431 11:55:45.847604 ==
1432 11:55:45.850543 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 11:55:45.853986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:55:45.854516 ==
1435 11:55:45.858180 Write leveling (Byte 0): 27 => 27
1436 11:55:45.858715 Write leveling (Byte 1): 27 => 27
1437 11:55:45.861374 DramcWriteLeveling(PI) end<-----
1438 11:55:45.861945
1439 11:55:45.862326 ==
1440 11:55:45.864502 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 11:55:45.871347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 11:55:45.871916 ==
1443 11:55:45.875218 [Gating] SW mode calibration
1444 11:55:45.881077 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 11:55:45.884424 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 11:55:45.891327 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1447 11:55:45.895104 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1448 11:55:45.897982 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1449 11:55:45.901290 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:55:45.908132 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:55:45.911654 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:55:45.914582 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:55:45.921946 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:55:45.924937 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:55:45.928564 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:55:45.934999 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:55:45.938374 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:55:45.941672 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:55:45.948391 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:55:45.952102 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:55:45.955245 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:55:45.961564 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1463 11:55:45.965014 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1464 11:55:45.968489 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:55:45.972211 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:55:45.978480 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:55:45.981660 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:55:45.985183 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:55:45.991694 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:55:45.995181 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:55:45.998774 0 9 4 | B1->B0 | 2424 2d2d | 1 1 | (1 1) (1 1)
1472 11:55:46.005696 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 11:55:46.008667 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 11:55:46.012280 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 11:55:46.019053 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 11:55:46.022278 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 11:55:46.025424 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:55:46.032108 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:55:46.035370 0 10 4 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
1480 11:55:46.038755 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1481 11:55:46.041817 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:55:46.048607 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:55:46.052128 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:55:46.055504 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:55:46.061964 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:55:46.065449 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1487 11:55:46.068539 0 11 4 | B1->B0 | 3434 3939 | 1 0 | (0 0) (0 0)
1488 11:55:46.075399 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1489 11:55:46.078534 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:55:46.081734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 11:55:46.088956 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 11:55:46.091801 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 11:55:46.095663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:55:46.102492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1495 11:55:46.105327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1496 11:55:46.108598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:55:46.115594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:55:46.118566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:55:46.122340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:55:46.128860 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:55:46.131993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:55:46.135279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:55:46.138657 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:55:46.145495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:55:46.148678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:55:46.152003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:55:46.158695 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:55:46.162368 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:55:46.165280 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:55:46.172061 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:55:46.175300 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1512 11:55:46.178766 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 11:55:46.182186 Total UI for P1: 0, mck2ui 16
1514 11:55:46.185275 best dqsien dly found for B0: ( 0, 14, 4)
1515 11:55:46.188558 Total UI for P1: 0, mck2ui 16
1516 11:55:46.192043 best dqsien dly found for B1: ( 0, 14, 6)
1517 11:55:46.195271 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 11:55:46.198516 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 11:55:46.199122
1520 11:55:46.202001 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 11:55:46.209182 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 11:55:46.209759 [Gating] SW calibration Done
1523 11:55:46.210141 ==
1524 11:55:46.212187 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 11:55:46.218724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 11:55:46.219199 ==
1527 11:55:46.219579 RX Vref Scan: 0
1528 11:55:46.219929
1529 11:55:46.222278 RX Vref 0 -> 0, step: 1
1530 11:55:46.222783
1531 11:55:46.225579 RX Delay -130 -> 252, step: 16
1532 11:55:46.229171 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 11:55:46.232569 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1534 11:55:46.235802 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1535 11:55:46.239271 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1536 11:55:46.246335 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1537 11:55:46.249180 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1538 11:55:46.252529 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1539 11:55:46.255681 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1540 11:55:46.259292 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1541 11:55:46.266534 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1542 11:55:46.269104 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1543 11:55:46.272649 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1544 11:55:46.276409 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 11:55:46.279175 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 11:55:46.285833 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 11:55:46.289261 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 11:55:46.289733 ==
1549 11:55:46.292235 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 11:55:46.295984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 11:55:46.296600 ==
1552 11:55:46.299049 DQS Delay:
1553 11:55:46.299534 DQS0 = 0, DQS1 = 0
1554 11:55:46.299902 DQM Delay:
1555 11:55:46.302489 DQM0 = 88, DQM1 = 82
1556 11:55:46.302961 DQ Delay:
1557 11:55:46.305835 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1558 11:55:46.309182 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1559 11:55:46.312779 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1560 11:55:46.316229 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 11:55:46.316702
1562 11:55:46.317074
1563 11:55:46.317418 ==
1564 11:55:46.319165 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 11:55:46.326362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 11:55:46.326991 ==
1567 11:55:46.327373
1568 11:55:46.327723
1569 11:55:46.328057 TX Vref Scan disable
1570 11:55:46.328949 == TX Byte 0 ==
1571 11:55:46.332803 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1572 11:55:46.339463 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1573 11:55:46.340045 == TX Byte 1 ==
1574 11:55:46.342993 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1575 11:55:46.349318 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1576 11:55:46.349896 ==
1577 11:55:46.352669 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 11:55:46.355889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 11:55:46.356470 ==
1580 11:55:46.368709 TX Vref=22, minBit 10, minWin=27, winSum=452
1581 11:55:46.371635 TX Vref=24, minBit 10, minWin=27, winSum=456
1582 11:55:46.375360 TX Vref=26, minBit 15, minWin=27, winSum=454
1583 11:55:46.378334 TX Vref=28, minBit 0, minWin=28, winSum=457
1584 11:55:46.381756 TX Vref=30, minBit 8, minWin=28, winSum=460
1585 11:55:46.388290 TX Vref=32, minBit 8, minWin=28, winSum=459
1586 11:55:46.391507 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1587 11:55:46.391992
1588 11:55:46.394954 Final TX Range 1 Vref 30
1589 11:55:46.395432
1590 11:55:46.395806 ==
1591 11:55:46.398203 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 11:55:46.401317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 11:55:46.404978 ==
1594 11:55:46.405442
1595 11:55:46.405809
1596 11:55:46.406153 TX Vref Scan disable
1597 11:55:46.409244 == TX Byte 0 ==
1598 11:55:46.413585 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1599 11:55:46.415497 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1600 11:55:46.418822 == TX Byte 1 ==
1601 11:55:46.422578 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 11:55:46.425796 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 11:55:46.426369
1604 11:55:46.428983 [DATLAT]
1605 11:55:46.429469 Freq=800, CH1 RK0
1606 11:55:46.429844
1607 11:55:46.432642 DATLAT Default: 0xa
1608 11:55:46.433224 0, 0xFFFF, sum = 0
1609 11:55:46.435957 1, 0xFFFF, sum = 0
1610 11:55:46.436529 2, 0xFFFF, sum = 0
1611 11:55:46.439161 3, 0xFFFF, sum = 0
1612 11:55:46.439739 4, 0xFFFF, sum = 0
1613 11:55:46.442834 5, 0xFFFF, sum = 0
1614 11:55:46.443406 6, 0xFFFF, sum = 0
1615 11:55:46.446339 7, 0xFFFF, sum = 0
1616 11:55:46.446963 8, 0xFFFF, sum = 0
1617 11:55:46.449158 9, 0x0, sum = 1
1618 11:55:46.449737 10, 0x0, sum = 2
1619 11:55:46.452671 11, 0x0, sum = 3
1620 11:55:46.453142 12, 0x0, sum = 4
1621 11:55:46.455903 best_step = 10
1622 11:55:46.456468
1623 11:55:46.456838 ==
1624 11:55:46.459199 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:55:46.462561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:55:46.463126 ==
1627 11:55:46.463789 RX Vref Scan: 1
1628 11:55:46.465830
1629 11:55:46.466300 Set Vref Range= 32 -> 127
1630 11:55:46.466738
1631 11:55:46.469056 RX Vref 32 -> 127, step: 1
1632 11:55:46.469520
1633 11:55:46.472354 RX Delay -79 -> 252, step: 8
1634 11:55:46.473094
1635 11:55:46.475640 Set Vref, RX VrefLevel [Byte0]: 32
1636 11:55:46.479085 [Byte1]: 32
1637 11:55:46.479555
1638 11:55:46.482251 Set Vref, RX VrefLevel [Byte0]: 33
1639 11:55:46.485930 [Byte1]: 33
1640 11:55:46.486438
1641 11:55:46.488959 Set Vref, RX VrefLevel [Byte0]: 34
1642 11:55:46.492281 [Byte1]: 34
1643 11:55:46.496001
1644 11:55:46.496465 Set Vref, RX VrefLevel [Byte0]: 35
1645 11:55:46.499255 [Byte1]: 35
1646 11:55:46.503900
1647 11:55:46.504466 Set Vref, RX VrefLevel [Byte0]: 36
1648 11:55:46.506925 [Byte1]: 36
1649 11:55:46.511331
1650 11:55:46.512071 Set Vref, RX VrefLevel [Byte0]: 37
1651 11:55:46.514334 [Byte1]: 37
1652 11:55:46.518846
1653 11:55:46.519312 Set Vref, RX VrefLevel [Byte0]: 38
1654 11:55:46.521855 [Byte1]: 38
1655 11:55:46.526212
1656 11:55:46.526814 Set Vref, RX VrefLevel [Byte0]: 39
1657 11:55:46.529767 [Byte1]: 39
1658 11:55:46.534054
1659 11:55:46.534654 Set Vref, RX VrefLevel [Byte0]: 40
1660 11:55:46.537274 [Byte1]: 40
1661 11:55:46.541407
1662 11:55:46.541962 Set Vref, RX VrefLevel [Byte0]: 41
1663 11:55:46.544732 [Byte1]: 41
1664 11:55:46.549098
1665 11:55:46.549657 Set Vref, RX VrefLevel [Byte0]: 42
1666 11:55:46.552381 [Byte1]: 42
1667 11:55:46.556487
1668 11:55:46.557059 Set Vref, RX VrefLevel [Byte0]: 43
1669 11:55:46.559803 [Byte1]: 43
1670 11:55:46.564207
1671 11:55:46.564765 Set Vref, RX VrefLevel [Byte0]: 44
1672 11:55:46.567479 [Byte1]: 44
1673 11:55:46.571794
1674 11:55:46.572350 Set Vref, RX VrefLevel [Byte0]: 45
1675 11:55:46.574941 [Byte1]: 45
1676 11:55:46.579318
1677 11:55:46.579874 Set Vref, RX VrefLevel [Byte0]: 46
1678 11:55:46.582521 [Byte1]: 46
1679 11:55:46.586736
1680 11:55:46.587286 Set Vref, RX VrefLevel [Byte0]: 47
1681 11:55:46.589937 [Byte1]: 47
1682 11:55:46.594699
1683 11:55:46.595256 Set Vref, RX VrefLevel [Byte0]: 48
1684 11:55:46.597760 [Byte1]: 48
1685 11:55:46.601617
1686 11:55:46.602083 Set Vref, RX VrefLevel [Byte0]: 49
1687 11:55:46.605282 [Byte1]: 49
1688 11:55:46.609634
1689 11:55:46.610203 Set Vref, RX VrefLevel [Byte0]: 50
1690 11:55:46.612416 [Byte1]: 50
1691 11:55:46.616816
1692 11:55:46.617330 Set Vref, RX VrefLevel [Byte0]: 51
1693 11:55:46.620212 [Byte1]: 51
1694 11:55:46.624131
1695 11:55:46.624704 Set Vref, RX VrefLevel [Byte0]: 52
1696 11:55:46.627689 [Byte1]: 52
1697 11:55:46.631739
1698 11:55:46.632203 Set Vref, RX VrefLevel [Byte0]: 53
1699 11:55:46.635621 [Byte1]: 53
1700 11:55:46.639564
1701 11:55:46.640029 Set Vref, RX VrefLevel [Byte0]: 54
1702 11:55:46.642906 [Byte1]: 54
1703 11:55:46.647054
1704 11:55:46.647517 Set Vref, RX VrefLevel [Byte0]: 55
1705 11:55:46.650547 [Byte1]: 55
1706 11:55:46.654767
1707 11:55:46.655332 Set Vref, RX VrefLevel [Byte0]: 56
1708 11:55:46.658116 [Byte1]: 56
1709 11:55:46.662026
1710 11:55:46.662514 Set Vref, RX VrefLevel [Byte0]: 57
1711 11:55:46.665625 [Byte1]: 57
1712 11:55:46.669967
1713 11:55:46.670563 Set Vref, RX VrefLevel [Byte0]: 58
1714 11:55:46.672945 [Byte1]: 58
1715 11:55:46.677410
1716 11:55:46.677896 Set Vref, RX VrefLevel [Byte0]: 59
1717 11:55:46.680545 [Byte1]: 59
1718 11:55:46.684688
1719 11:55:46.685156 Set Vref, RX VrefLevel [Byte0]: 60
1720 11:55:46.688282 [Byte1]: 60
1721 11:55:46.693208
1722 11:55:46.693773 Set Vref, RX VrefLevel [Byte0]: 61
1723 11:55:46.695642 [Byte1]: 61
1724 11:55:46.700270
1725 11:55:46.700846 Set Vref, RX VrefLevel [Byte0]: 62
1726 11:55:46.703258 [Byte1]: 62
1727 11:55:46.707200
1728 11:55:46.707668 Set Vref, RX VrefLevel [Byte0]: 63
1729 11:55:46.711126 [Byte1]: 63
1730 11:55:46.714935
1731 11:55:46.715545 Set Vref, RX VrefLevel [Byte0]: 64
1732 11:55:46.718288 [Byte1]: 64
1733 11:55:46.722704
1734 11:55:46.723269 Set Vref, RX VrefLevel [Byte0]: 65
1735 11:55:46.725733 [Byte1]: 65
1736 11:55:46.730067
1737 11:55:46.730666 Set Vref, RX VrefLevel [Byte0]: 66
1738 11:55:46.733442 [Byte1]: 66
1739 11:55:46.737609
1740 11:55:46.738178 Set Vref, RX VrefLevel [Byte0]: 67
1741 11:55:46.741520 [Byte1]: 67
1742 11:55:46.745215
1743 11:55:46.745771 Set Vref, RX VrefLevel [Byte0]: 68
1744 11:55:46.748642 [Byte1]: 68
1745 11:55:46.752927
1746 11:55:46.753395 Set Vref, RX VrefLevel [Byte0]: 69
1747 11:55:46.756115 [Byte1]: 69
1748 11:55:46.760872
1749 11:55:46.761442 Set Vref, RX VrefLevel [Byte0]: 70
1750 11:55:46.763702 [Byte1]: 70
1751 11:55:46.767956
1752 11:55:46.768520 Set Vref, RX VrefLevel [Byte0]: 71
1753 11:55:46.771237 [Byte1]: 71
1754 11:55:46.775550
1755 11:55:46.776162 Set Vref, RX VrefLevel [Byte0]: 72
1756 11:55:46.779051 [Byte1]: 72
1757 11:55:46.783058
1758 11:55:46.783624 Set Vref, RX VrefLevel [Byte0]: 73
1759 11:55:46.786683 [Byte1]: 73
1760 11:55:46.790549
1761 11:55:46.791111 Set Vref, RX VrefLevel [Byte0]: 74
1762 11:55:46.793871 [Byte1]: 74
1763 11:55:46.798628
1764 11:55:46.799182 Set Vref, RX VrefLevel [Byte0]: 75
1765 11:55:46.801137 [Byte1]: 75
1766 11:55:46.805560
1767 11:55:46.806131 Set Vref, RX VrefLevel [Byte0]: 76
1768 11:55:46.812018 [Byte1]: 76
1769 11:55:46.812587
1770 11:55:46.815347 Set Vref, RX VrefLevel [Byte0]: 77
1771 11:55:46.818559 [Byte1]: 77
1772 11:55:46.819117
1773 11:55:46.822157 Final RX Vref Byte 0 = 50 to rank0
1774 11:55:46.825695 Final RX Vref Byte 1 = 63 to rank0
1775 11:55:46.828970 Final RX Vref Byte 0 = 50 to rank1
1776 11:55:46.831786 Final RX Vref Byte 1 = 63 to rank1==
1777 11:55:46.835396 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 11:55:46.838790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 11:55:46.839364 ==
1780 11:55:46.841552 DQS Delay:
1781 11:55:46.842017 DQS0 = 0, DQS1 = 0
1782 11:55:46.842413 DQM Delay:
1783 11:55:46.845521 DQM0 = 92, DQM1 = 82
1784 11:55:46.845988 DQ Delay:
1785 11:55:46.848717 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1786 11:55:46.852044 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1787 11:55:46.855028 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1788 11:55:46.858628 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1789 11:55:46.859189
1790 11:55:46.859563
1791 11:55:46.868932 [DQSOSCAuto] RK0, (LSB)MR18= 0x3350, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1792 11:55:46.869505 CH1 RK0: MR19=606, MR18=3350
1793 11:55:46.875533 CH1_RK0: MR19=0x606, MR18=0x3350, DQSOSC=389, MR23=63, INC=97, DEC=65
1794 11:55:46.876117
1795 11:55:46.878447 ----->DramcWriteLeveling(PI) begin...
1796 11:55:46.878923 ==
1797 11:55:46.882291 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 11:55:46.889054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 11:55:46.889628 ==
1800 11:55:46.891713 Write leveling (Byte 0): 26 => 26
1801 11:55:46.895247 Write leveling (Byte 1): 30 => 30
1802 11:55:46.895813 DramcWriteLeveling(PI) end<-----
1803 11:55:46.899247
1804 11:55:46.899809 ==
1805 11:55:46.902012 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 11:55:46.905471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 11:55:46.906141 ==
1808 11:55:46.908822 [Gating] SW mode calibration
1809 11:55:46.915605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 11:55:46.918790 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 11:55:46.925685 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1812 11:55:46.928576 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 11:55:46.931925 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:55:46.938816 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:55:46.941864 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:55:46.945354 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:55:46.951946 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:55:46.955266 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:55:46.958562 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:55:46.965461 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:55:46.968744 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:55:46.971800 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:55:46.975323 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:55:46.982013 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:55:46.985588 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:55:46.988797 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:55:46.995727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:55:46.998890 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1829 11:55:47.002195 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:55:47.009090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:55:47.012123 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:55:47.015401 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:55:47.021819 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:55:47.025595 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:55:47.028420 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:55:47.035621 0 9 4 | B1->B0 | 2424 2424 | 1 1 | (1 1) (1 1)
1837 11:55:47.038990 0 9 8 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
1838 11:55:47.042343 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:55:47.049038 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:55:47.052316 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:55:47.055521 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:55:47.058637 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:55:47.065325 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:55:47.068747 0 10 4 | B1->B0 | 2a2a 3030 | 1 0 | (1 1) (0 1)
1845 11:55:47.072145 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1846 11:55:47.078952 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:55:47.082146 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:55:47.085368 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:55:47.091873 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:55:47.095556 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:55:47.098947 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:55:47.105432 0 11 4 | B1->B0 | 2c2c 2929 | 0 1 | (0 0) (0 0)
1853 11:55:47.108992 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1854 11:55:47.112407 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:55:47.118723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:55:47.122266 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:55:47.125383 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:55:47.132255 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:55:47.135332 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 11:55:47.139053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1861 11:55:47.142679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1862 11:55:47.149600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:55:47.152624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:55:47.156129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:55:47.162527 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:55:47.165773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:55:47.169465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:55:47.175689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:55:47.178695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:55:47.182320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:55:47.189048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:55:47.192697 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:55:47.195943 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:55:47.202840 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:55:47.205557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:55:47.209237 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1877 11:55:47.212486 Total UI for P1: 0, mck2ui 16
1878 11:55:47.215720 best dqsien dly found for B1: ( 0, 14, 2)
1879 11:55:47.219043 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 11:55:47.222567 Total UI for P1: 0, mck2ui 16
1881 11:55:47.225723 best dqsien dly found for B0: ( 0, 14, 4)
1882 11:55:47.229153 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1883 11:55:47.232533 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1884 11:55:47.236314
1885 11:55:47.239214 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 11:55:47.242777 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 11:55:47.245679 [Gating] SW calibration Done
1888 11:55:47.246154 ==
1889 11:55:47.248954 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 11:55:47.252439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 11:55:47.252777 ==
1892 11:55:47.253045 RX Vref Scan: 0
1893 11:55:47.253293
1894 11:55:47.256134 RX Vref 0 -> 0, step: 1
1895 11:55:47.256469
1896 11:55:47.259033 RX Delay -130 -> 252, step: 16
1897 11:55:47.262155 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1898 11:55:47.265754 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1899 11:55:47.272515 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1900 11:55:47.275658 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1901 11:55:47.278845 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1902 11:55:47.282188 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1903 11:55:47.285543 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1904 11:55:47.289366 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1905 11:55:47.295523 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1906 11:55:47.299218 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1907 11:55:47.302561 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1908 11:55:47.305714 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1909 11:55:47.309583 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1910 11:55:47.315861 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1911 11:55:47.319229 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 11:55:47.322738 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1913 11:55:47.323205 ==
1914 11:55:47.326121 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 11:55:47.329522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 11:55:47.332740 ==
1917 11:55:47.333316 DQS Delay:
1918 11:55:47.333699 DQS0 = 0, DQS1 = 0
1919 11:55:47.336309 DQM Delay:
1920 11:55:47.336865 DQM0 = 87, DQM1 = 83
1921 11:55:47.339281 DQ Delay:
1922 11:55:47.339745 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1923 11:55:47.342590 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1924 11:55:47.346101 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1925 11:55:47.349276 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1926 11:55:47.349832
1927 11:55:47.353189
1928 11:55:47.353746 ==
1929 11:55:47.356423 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 11:55:47.359266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 11:55:47.359825 ==
1932 11:55:47.360199
1933 11:55:47.360541
1934 11:55:47.362838 TX Vref Scan disable
1935 11:55:47.363401 == TX Byte 0 ==
1936 11:55:47.369733 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1937 11:55:47.372803 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1938 11:55:47.373364 == TX Byte 1 ==
1939 11:55:47.379096 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1940 11:55:47.382480 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1941 11:55:47.382946 ==
1942 11:55:47.385935 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 11:55:47.389084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 11:55:47.389657 ==
1945 11:55:47.403603 TX Vref=22, minBit 12, minWin=27, winSum=451
1946 11:55:47.406286 TX Vref=24, minBit 13, minWin=27, winSum=454
1947 11:55:47.409761 TX Vref=26, minBit 13, minWin=27, winSum=457
1948 11:55:47.413119 TX Vref=28, minBit 8, minWin=28, winSum=459
1949 11:55:47.416899 TX Vref=30, minBit 8, minWin=28, winSum=459
1950 11:55:47.423005 TX Vref=32, minBit 8, minWin=28, winSum=459
1951 11:55:47.426617 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1952 11:55:47.427179
1953 11:55:47.429469 Final TX Range 1 Vref 28
1954 11:55:47.429936
1955 11:55:47.430304 ==
1956 11:55:47.432999 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:55:47.436318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:55:47.439427 ==
1959 11:55:47.439995
1960 11:55:47.440370
1961 11:55:47.440711 TX Vref Scan disable
1962 11:55:47.443291 == TX Byte 0 ==
1963 11:55:47.446919 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1964 11:55:47.453332 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1965 11:55:47.453949 == TX Byte 1 ==
1966 11:55:47.456940 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1967 11:55:47.459947 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1968 11:55:47.463280
1969 11:55:47.463846 [DATLAT]
1970 11:55:47.464225 Freq=800, CH1 RK1
1971 11:55:47.464573
1972 11:55:47.466695 DATLAT Default: 0xa
1973 11:55:47.467264 0, 0xFFFF, sum = 0
1974 11:55:47.470024 1, 0xFFFF, sum = 0
1975 11:55:47.470713 2, 0xFFFF, sum = 0
1976 11:55:47.473344 3, 0xFFFF, sum = 0
1977 11:55:47.473919 4, 0xFFFF, sum = 0
1978 11:55:47.476404 5, 0xFFFF, sum = 0
1979 11:55:47.476981 6, 0xFFFF, sum = 0
1980 11:55:47.480048 7, 0xFFFF, sum = 0
1981 11:55:47.483080 8, 0xFFFF, sum = 0
1982 11:55:47.483653 9, 0x0, sum = 1
1983 11:55:47.484043 10, 0x0, sum = 2
1984 11:55:47.486332 11, 0x0, sum = 3
1985 11:55:47.486828 12, 0x0, sum = 4
1986 11:55:47.489424 best_step = 10
1987 11:55:47.489890
1988 11:55:47.490262 ==
1989 11:55:47.493046 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:55:47.496212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:55:47.496945 ==
1992 11:55:47.499739 RX Vref Scan: 0
1993 11:55:47.500311
1994 11:55:47.500845 RX Vref 0 -> 0, step: 1
1995 11:55:47.501387
1996 11:55:47.503000 RX Delay -95 -> 252, step: 8
1997 11:55:47.509542 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1998 11:55:47.512914 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1999 11:55:47.516186 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2000 11:55:47.519563 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2001 11:55:47.522980 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2002 11:55:47.529525 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2003 11:55:47.532778 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2004 11:55:47.536291 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2005 11:55:47.539670 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2006 11:55:47.543001 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2007 11:55:47.546568 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2008 11:55:47.553306 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2009 11:55:47.556410 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2010 11:55:47.559966 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2011 11:55:47.563142 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2012 11:55:47.570061 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2013 11:55:47.570636 ==
2014 11:55:47.573734 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 11:55:47.576730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 11:55:47.577304 ==
2017 11:55:47.577682 DQS Delay:
2018 11:55:47.579923 DQS0 = 0, DQS1 = 0
2019 11:55:47.580490 DQM Delay:
2020 11:55:47.583247 DQM0 = 90, DQM1 = 83
2021 11:55:47.583812 DQ Delay:
2022 11:55:47.586809 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2023 11:55:47.589566 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2024 11:55:47.593163 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2025 11:55:47.596321 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2026 11:55:47.596892
2027 11:55:47.597267
2028 11:55:47.603161 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2029 11:55:47.606267 CH1 RK1: MR19=606, MR18=3E13
2030 11:55:47.613102 CH1_RK1: MR19=0x606, MR18=0x3E13, DQSOSC=394, MR23=63, INC=95, DEC=63
2031 11:55:47.616625 [RxdqsGatingPostProcess] freq 800
2032 11:55:47.623009 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 11:55:47.623565 Pre-setting of DQS Precalculation
2034 11:55:47.629883 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 11:55:47.636564 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 11:55:47.643558 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 11:55:47.644134
2038 11:55:47.644510
2039 11:55:47.646940 [Calibration Summary] 1600 Mbps
2040 11:55:47.650282 CH 0, Rank 0
2041 11:55:47.650879 SW Impedance : PASS
2042 11:55:47.653258 DUTY Scan : NO K
2043 11:55:47.653727 ZQ Calibration : PASS
2044 11:55:47.657064 Jitter Meter : NO K
2045 11:55:47.660178 CBT Training : PASS
2046 11:55:47.660753 Write leveling : PASS
2047 11:55:47.663881 RX DQS gating : PASS
2048 11:55:47.666941 RX DQ/DQS(RDDQC) : PASS
2049 11:55:47.667512 TX DQ/DQS : PASS
2050 11:55:47.670147 RX DATLAT : PASS
2051 11:55:47.673667 RX DQ/DQS(Engine): PASS
2052 11:55:47.674230 TX OE : NO K
2053 11:55:47.677220 All Pass.
2054 11:55:47.677786
2055 11:55:47.678161 CH 0, Rank 1
2056 11:55:47.680439 SW Impedance : PASS
2057 11:55:47.681009 DUTY Scan : NO K
2058 11:55:47.683464 ZQ Calibration : PASS
2059 11:55:47.686888 Jitter Meter : NO K
2060 11:55:47.687361 CBT Training : PASS
2061 11:55:47.689942 Write leveling : PASS
2062 11:55:47.690442 RX DQS gating : PASS
2063 11:55:47.693706 RX DQ/DQS(RDDQC) : PASS
2064 11:55:47.697283 TX DQ/DQS : PASS
2065 11:55:47.697860 RX DATLAT : PASS
2066 11:55:47.700168 RX DQ/DQS(Engine): PASS
2067 11:55:47.703279 TX OE : NO K
2068 11:55:47.703759 All Pass.
2069 11:55:47.704137
2070 11:55:47.704480 CH 1, Rank 0
2071 11:55:47.706543 SW Impedance : PASS
2072 11:55:47.710034 DUTY Scan : NO K
2073 11:55:47.710530 ZQ Calibration : PASS
2074 11:55:47.713556 Jitter Meter : NO K
2075 11:55:47.716695 CBT Training : PASS
2076 11:55:47.717182 Write leveling : PASS
2077 11:55:47.720377 RX DQS gating : PASS
2078 11:55:47.723389 RX DQ/DQS(RDDQC) : PASS
2079 11:55:47.723857 TX DQ/DQS : PASS
2080 11:55:47.727037 RX DATLAT : PASS
2081 11:55:47.729919 RX DQ/DQS(Engine): PASS
2082 11:55:47.730415 TX OE : NO K
2083 11:55:47.730810 All Pass.
2084 11:55:47.731160
2085 11:55:47.733584 CH 1, Rank 1
2086 11:55:47.734154 SW Impedance : PASS
2087 11:55:47.737167 DUTY Scan : NO K
2088 11:55:47.740237 ZQ Calibration : PASS
2089 11:55:47.740705 Jitter Meter : NO K
2090 11:55:47.743434 CBT Training : PASS
2091 11:55:47.747034 Write leveling : PASS
2092 11:55:47.747602 RX DQS gating : PASS
2093 11:55:47.750910 RX DQ/DQS(RDDQC) : PASS
2094 11:55:47.753698 TX DQ/DQS : PASS
2095 11:55:47.754276 RX DATLAT : PASS
2096 11:55:47.757147 RX DQ/DQS(Engine): PASS
2097 11:55:47.760284 TX OE : NO K
2098 11:55:47.760753 All Pass.
2099 11:55:47.761126
2100 11:55:47.761469 DramC Write-DBI off
2101 11:55:47.763808 PER_BANK_REFRESH: Hybrid Mode
2102 11:55:47.766914 TX_TRACKING: ON
2103 11:55:47.770287 [GetDramInforAfterCalByMRR] Vendor 6.
2104 11:55:47.773636 [GetDramInforAfterCalByMRR] Revision 606.
2105 11:55:47.776984 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 11:55:47.777551 MR0 0x3b3b
2107 11:55:47.780360 MR8 0x5151
2108 11:55:47.783611 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 11:55:47.784182
2110 11:55:47.784558 MR0 0x3b3b
2111 11:55:47.784905 MR8 0x5151
2112 11:55:47.787008 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 11:55:47.790244
2114 11:55:47.796933 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 11:55:47.800206 [FAST_K] Save calibration result to emmc
2116 11:55:47.803814 [FAST_K] Save calibration result to emmc
2117 11:55:47.806655 dram_init: config_dvfs: 1
2118 11:55:47.810487 dramc_set_vcore_voltage set vcore to 662500
2119 11:55:47.813615 Read voltage for 1200, 2
2120 11:55:47.814174 Vio18 = 0
2121 11:55:47.816817 Vcore = 662500
2122 11:55:47.817281 Vdram = 0
2123 11:55:47.817677 Vddq = 0
2124 11:55:47.818028 Vmddr = 0
2125 11:55:47.824126 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 11:55:47.830216 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 11:55:47.830720 MEM_TYPE=3, freq_sel=15
2128 11:55:47.833417 sv_algorithm_assistance_LP4_1600
2129 11:55:47.837020 ============ PULL DRAM RESETB DOWN ============
2130 11:55:47.843686 ========== PULL DRAM RESETB DOWN end =========
2131 11:55:47.847045 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 11:55:47.850424 ===================================
2133 11:55:47.854572 LPDDR4 DRAM CONFIGURATION
2134 11:55:47.857311 ===================================
2135 11:55:47.857882 EX_ROW_EN[0] = 0x0
2136 11:55:47.860390 EX_ROW_EN[1] = 0x0
2137 11:55:47.860856 LP4Y_EN = 0x0
2138 11:55:47.863871 WORK_FSP = 0x0
2139 11:55:47.864444 WL = 0x4
2140 11:55:47.867296 RL = 0x4
2141 11:55:47.867863 BL = 0x2
2142 11:55:47.870609 RPST = 0x0
2143 11:55:47.871171 RD_PRE = 0x0
2144 11:55:47.873982 WR_PRE = 0x1
2145 11:55:47.874591 WR_PST = 0x0
2146 11:55:47.877289 DBI_WR = 0x0
2147 11:55:47.877754 DBI_RD = 0x0
2148 11:55:47.881246 OTF = 0x1
2149 11:55:47.884329 ===================================
2150 11:55:47.887516 ===================================
2151 11:55:47.887985 ANA top config
2152 11:55:47.890345 ===================================
2153 11:55:47.894147 DLL_ASYNC_EN = 0
2154 11:55:47.896936 ALL_SLAVE_EN = 0
2155 11:55:47.900330 NEW_RANK_MODE = 1
2156 11:55:47.900902 DLL_IDLE_MODE = 1
2157 11:55:47.903790 LP45_APHY_COMB_EN = 1
2158 11:55:47.906899 TX_ODT_DIS = 1
2159 11:55:47.910242 NEW_8X_MODE = 1
2160 11:55:47.914170 ===================================
2161 11:55:47.917360 ===================================
2162 11:55:47.920440 data_rate = 2400
2163 11:55:47.920908 CKR = 1
2164 11:55:47.924131 DQ_P2S_RATIO = 8
2165 11:55:47.927009 ===================================
2166 11:55:47.930470 CA_P2S_RATIO = 8
2167 11:55:47.933674 DQ_CA_OPEN = 0
2168 11:55:47.937661 DQ_SEMI_OPEN = 0
2169 11:55:47.940586 CA_SEMI_OPEN = 0
2170 11:55:47.941102 CA_FULL_RATE = 0
2171 11:55:47.943517 DQ_CKDIV4_EN = 0
2172 11:55:47.947255 CA_CKDIV4_EN = 0
2173 11:55:47.950800 CA_PREDIV_EN = 0
2174 11:55:47.953826 PH8_DLY = 17
2175 11:55:47.957637 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 11:55:47.958222 DQ_AAMCK_DIV = 4
2177 11:55:47.961235 CA_AAMCK_DIV = 4
2178 11:55:47.964702 CA_ADMCK_DIV = 4
2179 11:55:47.967365 DQ_TRACK_CA_EN = 0
2180 11:55:47.970741 CA_PICK = 1200
2181 11:55:47.974277 CA_MCKIO = 1200
2182 11:55:47.974928 MCKIO_SEMI = 0
2183 11:55:47.977470 PLL_FREQ = 2366
2184 11:55:47.980909 DQ_UI_PI_RATIO = 32
2185 11:55:47.984356 CA_UI_PI_RATIO = 0
2186 11:55:47.987821 ===================================
2187 11:55:47.991754 ===================================
2188 11:55:47.994643 memory_type:LPDDR4
2189 11:55:47.995212 GP_NUM : 10
2190 11:55:47.997648 SRAM_EN : 1
2191 11:55:47.998217 MD32_EN : 0
2192 11:55:48.001209 ===================================
2193 11:55:48.004639 [ANA_INIT] >>>>>>>>>>>>>>
2194 11:55:48.007914 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 11:55:48.011788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 11:55:48.014623 ===================================
2197 11:55:48.018593 data_rate = 2400,PCW = 0X5b00
2198 11:55:48.021184 ===================================
2199 11:55:48.024169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 11:55:48.030777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 11:55:48.034287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 11:55:48.041511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 11:55:48.044158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 11:55:48.048086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 11:55:48.048653 [ANA_INIT] flow start
2206 11:55:48.051028 [ANA_INIT] PLL >>>>>>>>
2207 11:55:48.054172 [ANA_INIT] PLL <<<<<<<<
2208 11:55:48.054697 [ANA_INIT] MIDPI >>>>>>>>
2209 11:55:48.057608 [ANA_INIT] MIDPI <<<<<<<<
2210 11:55:48.060985 [ANA_INIT] DLL >>>>>>>>
2211 11:55:48.061563 [ANA_INIT] DLL <<<<<<<<
2212 11:55:48.064292 [ANA_INIT] flow end
2213 11:55:48.067630 ============ LP4 DIFF to SE enter ============
2214 11:55:48.074050 ============ LP4 DIFF to SE exit ============
2215 11:55:48.074646 [ANA_INIT] <<<<<<<<<<<<<
2216 11:55:48.077288 [Flow] Enable top DCM control >>>>>
2217 11:55:48.080824 [Flow] Enable top DCM control <<<<<
2218 11:55:48.084248 Enable DLL master slave shuffle
2219 11:55:48.090725 ==============================================================
2220 11:55:48.091301 Gating Mode config
2221 11:55:48.097290 ==============================================================
2222 11:55:48.097854 Config description:
2223 11:55:48.107753 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 11:55:48.114155 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 11:55:48.121297 SELPH_MODE 0: By rank 1: By Phase
2226 11:55:48.124079 ==============================================================
2227 11:55:48.127240 GAT_TRACK_EN = 1
2228 11:55:48.131114 RX_GATING_MODE = 2
2229 11:55:48.134282 RX_GATING_TRACK_MODE = 2
2230 11:55:48.137757 SELPH_MODE = 1
2231 11:55:48.140749 PICG_EARLY_EN = 1
2232 11:55:48.144067 VALID_LAT_VALUE = 1
2233 11:55:48.147507 ==============================================================
2234 11:55:48.151012 Enter into Gating configuration >>>>
2235 11:55:48.154618 Exit from Gating configuration <<<<
2236 11:55:48.157980 Enter into DVFS_PRE_config >>>>>
2237 11:55:48.170975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 11:55:48.174323 Exit from DVFS_PRE_config <<<<<
2239 11:55:48.178140 Enter into PICG configuration >>>>
2240 11:55:48.178744 Exit from PICG configuration <<<<
2241 11:55:48.181040 [RX_INPUT] configuration >>>>>
2242 11:55:48.184389 [RX_INPUT] configuration <<<<<
2243 11:55:48.190935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 11:55:48.194799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 11:55:48.201212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 11:55:48.207881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 11:55:48.214641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 11:55:48.221203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 11:55:48.224465 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 11:55:48.227984 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 11:55:48.231163 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 11:55:48.237706 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 11:55:48.241786 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 11:55:48.244850 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 11:55:48.248025 ===================================
2256 11:55:48.251516 LPDDR4 DRAM CONFIGURATION
2257 11:55:48.254504 ===================================
2258 11:55:48.254976 EX_ROW_EN[0] = 0x0
2259 11:55:48.257922 EX_ROW_EN[1] = 0x0
2260 11:55:48.261513 LP4Y_EN = 0x0
2261 11:55:48.262102 WORK_FSP = 0x0
2262 11:55:48.264860 WL = 0x4
2263 11:55:48.265427 RL = 0x4
2264 11:55:48.267941 BL = 0x2
2265 11:55:48.268523 RPST = 0x0
2266 11:55:48.271200 RD_PRE = 0x0
2267 11:55:48.271667 WR_PRE = 0x1
2268 11:55:48.274912 WR_PST = 0x0
2269 11:55:48.275479 DBI_WR = 0x0
2270 11:55:48.278900 DBI_RD = 0x0
2271 11:55:48.279471 OTF = 0x1
2272 11:55:48.281098 ===================================
2273 11:55:48.284865 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 11:55:48.291364 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 11:55:48.294664 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 11:55:48.298014 ===================================
2277 11:55:48.301437 LPDDR4 DRAM CONFIGURATION
2278 11:55:48.304707 ===================================
2279 11:55:48.305280 EX_ROW_EN[0] = 0x10
2280 11:55:48.308274 EX_ROW_EN[1] = 0x0
2281 11:55:48.308858 LP4Y_EN = 0x0
2282 11:55:48.311140 WORK_FSP = 0x0
2283 11:55:48.311608 WL = 0x4
2284 11:55:48.314561 RL = 0x4
2285 11:55:48.315027 BL = 0x2
2286 11:55:48.317955 RPST = 0x0
2287 11:55:48.321210 RD_PRE = 0x0
2288 11:55:48.321676 WR_PRE = 0x1
2289 11:55:48.324248 WR_PST = 0x0
2290 11:55:48.324714 DBI_WR = 0x0
2291 11:55:48.328122 DBI_RD = 0x0
2292 11:55:48.328693 OTF = 0x1
2293 11:55:48.331106 ===================================
2294 11:55:48.337547 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 11:55:48.338044 ==
2296 11:55:48.341007 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 11:55:48.345264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 11:55:48.345723 ==
2299 11:55:48.347668 [Duty_Offset_Calibration]
2300 11:55:48.348124 B0:2 B1:0 CA:1
2301 11:55:48.351423
2302 11:55:48.354252 [DutyScan_Calibration_Flow] k_type=0
2303 11:55:48.361404
2304 11:55:48.361956 ==CLK 0==
2305 11:55:48.364866 Final CLK duty delay cell = -4
2306 11:55:48.367983 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2307 11:55:48.371212 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2308 11:55:48.374752 [-4] AVG Duty = 4953%(X100)
2309 11:55:48.375323
2310 11:55:48.378041 CH0 CLK Duty spec in!! Max-Min= 156%
2311 11:55:48.381501 [DutyScan_Calibration_Flow] ====Done====
2312 11:55:48.382066
2313 11:55:48.384434 [DutyScan_Calibration_Flow] k_type=1
2314 11:55:48.400109
2315 11:55:48.400655 ==DQS 0 ==
2316 11:55:48.403736 Final DQS duty delay cell = 0
2317 11:55:48.406633 [0] MAX Duty = 5187%(X100), DQS PI = 30
2318 11:55:48.409979 [0] MIN Duty = 4938%(X100), DQS PI = 0
2319 11:55:48.410470 [0] AVG Duty = 5062%(X100)
2320 11:55:48.413423
2321 11:55:48.413877 ==DQS 1 ==
2322 11:55:48.417155 Final DQS duty delay cell = -4
2323 11:55:48.420866 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2324 11:55:48.423328 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2325 11:55:48.427152 [-4] AVG Duty = 5031%(X100)
2326 11:55:48.427703
2327 11:55:48.430343 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2328 11:55:48.430850
2329 11:55:48.433984 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2330 11:55:48.437241 [DutyScan_Calibration_Flow] ====Done====
2331 11:55:48.437799
2332 11:55:48.440401 [DutyScan_Calibration_Flow] k_type=3
2333 11:55:48.456874
2334 11:55:48.457560 ==DQM 0 ==
2335 11:55:48.460356 Final DQM duty delay cell = 0
2336 11:55:48.464482 [0] MAX Duty = 5062%(X100), DQS PI = 24
2337 11:55:48.467137 [0] MIN Duty = 4813%(X100), DQS PI = 2
2338 11:55:48.467699 [0] AVG Duty = 4937%(X100)
2339 11:55:48.470711
2340 11:55:48.471264 ==DQM 1 ==
2341 11:55:48.473879 Final DQM duty delay cell = 0
2342 11:55:48.477357 [0] MAX Duty = 5187%(X100), DQS PI = 48
2343 11:55:48.480526 [0] MIN Duty = 5000%(X100), DQS PI = 22
2344 11:55:48.481096 [0] AVG Duty = 5093%(X100)
2345 11:55:48.483723
2346 11:55:48.487403 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2347 11:55:48.487968
2348 11:55:48.490582 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2349 11:55:48.493376 [DutyScan_Calibration_Flow] ====Done====
2350 11:55:48.493865
2351 11:55:48.496849 [DutyScan_Calibration_Flow] k_type=2
2352 11:55:48.512756
2353 11:55:48.513319 ==DQ 0 ==
2354 11:55:48.516190 Final DQ duty delay cell = -4
2355 11:55:48.519714 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2356 11:55:48.522582 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2357 11:55:48.526505 [-4] AVG Duty = 4968%(X100)
2358 11:55:48.527074
2359 11:55:48.527450 ==DQ 1 ==
2360 11:55:48.529596 Final DQ duty delay cell = 0
2361 11:55:48.533235 [0] MAX Duty = 4938%(X100), DQS PI = 4
2362 11:55:48.536270 [0] MIN Duty = 4907%(X100), DQS PI = 0
2363 11:55:48.536758 [0] AVG Duty = 4922%(X100)
2364 11:55:48.537133
2365 11:55:48.539733 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2366 11:55:48.540302
2367 11:55:48.542724 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2368 11:55:48.549364 [DutyScan_Calibration_Flow] ====Done====
2369 11:55:48.549844 ==
2370 11:55:48.552741 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 11:55:48.556152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 11:55:48.556642 ==
2373 11:55:48.559415 [Duty_Offset_Calibration]
2374 11:55:48.560176 B0:0 B1:-1 CA:2
2375 11:55:48.560786
2376 11:55:48.562643 [DutyScan_Calibration_Flow] k_type=0
2377 11:55:48.572740
2378 11:55:48.573212 ==CLK 0==
2379 11:55:48.576089 Final CLK duty delay cell = 0
2380 11:55:48.579965 [0] MAX Duty = 5156%(X100), DQS PI = 14
2381 11:55:48.583095 [0] MIN Duty = 4938%(X100), DQS PI = 44
2382 11:55:48.583681 [0] AVG Duty = 5047%(X100)
2383 11:55:48.584063
2384 11:55:48.586315 CH1 CLK Duty spec in!! Max-Min= 218%
2385 11:55:48.592937 [DutyScan_Calibration_Flow] ====Done====
2386 11:55:48.593414
2387 11:55:48.596190 [DutyScan_Calibration_Flow] k_type=1
2388 11:55:48.612063
2389 11:55:48.612626 ==DQS 0 ==
2390 11:55:48.615819 Final DQS duty delay cell = 0
2391 11:55:48.618650 [0] MAX Duty = 5093%(X100), DQS PI = 22
2392 11:55:48.622171 [0] MIN Duty = 4969%(X100), DQS PI = 0
2393 11:55:48.622679 [0] AVG Duty = 5031%(X100)
2394 11:55:48.626023
2395 11:55:48.626636 ==DQS 1 ==
2396 11:55:48.629018 Final DQS duty delay cell = 0
2397 11:55:48.631921 [0] MAX Duty = 5156%(X100), DQS PI = 0
2398 11:55:48.635343 [0] MIN Duty = 4844%(X100), DQS PI = 36
2399 11:55:48.635818 [0] AVG Duty = 5000%(X100)
2400 11:55:48.638944
2401 11:55:48.642513 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2402 11:55:48.643077
2403 11:55:48.645458 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2404 11:55:48.649240 [DutyScan_Calibration_Flow] ====Done====
2405 11:55:48.649810
2406 11:55:48.652491 [DutyScan_Calibration_Flow] k_type=3
2407 11:55:48.669595
2408 11:55:48.670156 ==DQM 0 ==
2409 11:55:48.673286 Final DQM duty delay cell = 4
2410 11:55:48.676178 [4] MAX Duty = 5093%(X100), DQS PI = 6
2411 11:55:48.679585 [4] MIN Duty = 4969%(X100), DQS PI = 30
2412 11:55:48.680155 [4] AVG Duty = 5031%(X100)
2413 11:55:48.683053
2414 11:55:48.683520 ==DQM 1 ==
2415 11:55:48.686280 Final DQM duty delay cell = 0
2416 11:55:48.689551 [0] MAX Duty = 5249%(X100), DQS PI = 0
2417 11:55:48.693926 [0] MIN Duty = 4875%(X100), DQS PI = 36
2418 11:55:48.694527 [0] AVG Duty = 5062%(X100)
2419 11:55:48.694910
2420 11:55:48.699751 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2421 11:55:48.700318
2422 11:55:48.702839 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2423 11:55:48.706600 [DutyScan_Calibration_Flow] ====Done====
2424 11:55:48.707158
2425 11:55:48.709603 [DutyScan_Calibration_Flow] k_type=2
2426 11:55:48.726015
2427 11:55:48.726740 ==DQ 0 ==
2428 11:55:48.729483 Final DQ duty delay cell = 0
2429 11:55:48.732608 [0] MAX Duty = 5062%(X100), DQS PI = 20
2430 11:55:48.736044 [0] MIN Duty = 4938%(X100), DQS PI = 46
2431 11:55:48.736515 [0] AVG Duty = 5000%(X100)
2432 11:55:48.736886
2433 11:55:48.739315 ==DQ 1 ==
2434 11:55:48.742690 Final DQ duty delay cell = 0
2435 11:55:48.745809 [0] MAX Duty = 5031%(X100), DQS PI = 0
2436 11:55:48.749646 [0] MIN Duty = 4813%(X100), DQS PI = 36
2437 11:55:48.750217 [0] AVG Duty = 4922%(X100)
2438 11:55:48.750632
2439 11:55:48.753070 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2440 11:55:48.753542
2441 11:55:48.756152 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2442 11:55:48.762623 [DutyScan_Calibration_Flow] ====Done====
2443 11:55:48.766202 nWR fixed to 30
2444 11:55:48.766810 [ModeRegInit_LP4] CH0 RK0
2445 11:55:48.769608 [ModeRegInit_LP4] CH0 RK1
2446 11:55:48.772767 [ModeRegInit_LP4] CH1 RK0
2447 11:55:48.773335 [ModeRegInit_LP4] CH1 RK1
2448 11:55:48.775996 match AC timing 7
2449 11:55:48.779412 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 11:55:48.782685 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 11:55:48.789497 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 11:55:48.792545 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 11:55:48.799714 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 11:55:48.800280 ==
2455 11:55:48.802754 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 11:55:48.806417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 11:55:48.806990 ==
2458 11:55:48.812590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 11:55:48.815934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2460 11:55:48.825946 [CA 0] Center 38 (8~69) winsize 62
2461 11:55:48.829065 [CA 1] Center 38 (8~69) winsize 62
2462 11:55:48.832267 [CA 2] Center 35 (5~66) winsize 62
2463 11:55:48.835646 [CA 3] Center 35 (4~66) winsize 63
2464 11:55:48.839055 [CA 4] Center 34 (4~65) winsize 62
2465 11:55:48.842510 [CA 5] Center 33 (3~63) winsize 61
2466 11:55:48.843075
2467 11:55:48.846530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2468 11:55:48.847098
2469 11:55:48.848909 [CATrainingPosCal] consider 1 rank data
2470 11:55:48.852208 u2DelayCellTimex100 = 270/100 ps
2471 11:55:48.855926 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2472 11:55:48.859111 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2473 11:55:48.865791 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 11:55:48.869487 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2475 11:55:48.872438 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2476 11:55:48.875604 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 11:55:48.876174
2478 11:55:48.879118 CA PerBit enable=1, Macro0, CA PI delay=33
2479 11:55:48.879685
2480 11:55:48.882348 [CBTSetCACLKResult] CA Dly = 33
2481 11:55:48.882947 CS Dly: 6 (0~37)
2482 11:55:48.885615 ==
2483 11:55:48.886176 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 11:55:48.892101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 11:55:48.892572 ==
2486 11:55:48.895604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 11:55:48.902562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2488 11:55:48.911336 [CA 0] Center 39 (8~70) winsize 63
2489 11:55:48.914840 [CA 1] Center 38 (8~69) winsize 62
2490 11:55:48.918120 [CA 2] Center 35 (5~66) winsize 62
2491 11:55:48.921256 [CA 3] Center 35 (5~66) winsize 62
2492 11:55:48.924748 [CA 4] Center 34 (4~65) winsize 62
2493 11:55:48.928231 [CA 5] Center 34 (4~64) winsize 61
2494 11:55:48.928792
2495 11:55:48.931247 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2496 11:55:48.931714
2497 11:55:48.935154 [CATrainingPosCal] consider 2 rank data
2498 11:55:48.938035 u2DelayCellTimex100 = 270/100 ps
2499 11:55:48.941552 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2500 11:55:48.945167 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2501 11:55:48.951423 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 11:55:48.955029 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 11:55:48.958771 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2504 11:55:48.961802 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2505 11:55:48.962369
2506 11:55:48.965108 CA PerBit enable=1, Macro0, CA PI delay=33
2507 11:55:48.965674
2508 11:55:48.968445 [CBTSetCACLKResult] CA Dly = 33
2509 11:55:48.969014 CS Dly: 7 (0~39)
2510 11:55:48.969388
2511 11:55:48.971699 ----->DramcWriteLeveling(PI) begin...
2512 11:55:48.972171 ==
2513 11:55:48.975031 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 11:55:48.982745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 11:55:48.983315 ==
2516 11:55:48.985599 Write leveling (Byte 0): 34 => 34
2517 11:55:48.989085 Write leveling (Byte 1): 30 => 30
2518 11:55:48.989555 DramcWriteLeveling(PI) end<-----
2519 11:55:48.990030
2520 11:55:48.991742 ==
2521 11:55:48.995221 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 11:55:48.998282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 11:55:48.998807 ==
2524 11:55:49.001617 [Gating] SW mode calibration
2525 11:55:49.009402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 11:55:49.011789 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 11:55:49.018539 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2528 11:55:49.022232 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2529 11:55:49.025374 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:55:49.032233 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:55:49.035464 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:55:49.038504 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:55:49.045669 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:55:49.048925 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (0 0) (1 0)
2535 11:55:49.052190 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2536 11:55:49.055292 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2537 11:55:49.062333 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:55:49.066371 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:55:49.069076 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:55:49.076396 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:55:49.078950 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2542 11:55:49.082119 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2543 11:55:49.088866 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2544 11:55:49.092459 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2545 11:55:49.095444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:55:49.102453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:55:49.105897 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:55:49.109454 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:55:49.112436 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:55:49.119239 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 11:55:49.122168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 11:55:49.125558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:55:49.132487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:55:49.135645 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:55:49.139038 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:55:49.146216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:55:49.149124 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:55:49.152377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:55:49.159029 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:55:49.162667 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:55:49.166167 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:55:49.172616 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:55:49.175845 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:55:49.179446 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:55:49.186192 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 11:55:49.189192 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 11:55:49.193206 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 11:55:49.195709 Total UI for P1: 0, mck2ui 16
2569 11:55:49.199102 best dqsien dly found for B0: ( 1, 3, 26)
2570 11:55:49.202919 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 11:55:49.205872 Total UI for P1: 0, mck2ui 16
2572 11:55:49.209362 best dqsien dly found for B1: ( 1, 4, 0)
2573 11:55:49.212834 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2574 11:55:49.216112 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2575 11:55:49.216596
2576 11:55:49.222595 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2577 11:55:49.225859 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2578 11:55:49.226454 [Gating] SW calibration Done
2579 11:55:49.229725 ==
2580 11:55:49.233184 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 11:55:49.236278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 11:55:49.236882 ==
2583 11:55:49.237267 RX Vref Scan: 0
2584 11:55:49.237618
2585 11:55:49.239303 RX Vref 0 -> 0, step: 1
2586 11:55:49.239776
2587 11:55:49.242574 RX Delay -40 -> 252, step: 8
2588 11:55:49.246137 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2589 11:55:49.249430 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2590 11:55:49.252828 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2591 11:55:49.259448 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2592 11:55:49.262996 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2593 11:55:49.266325 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2594 11:55:49.269307 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2595 11:55:49.272847 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2596 11:55:49.279320 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2597 11:55:49.282986 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2598 11:55:49.286423 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2599 11:55:49.289911 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2600 11:55:49.293004 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2601 11:55:49.299767 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2602 11:55:49.303297 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2603 11:55:49.306835 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2604 11:55:49.307405 ==
2605 11:55:49.309728 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 11:55:49.312638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 11:55:49.313111 ==
2608 11:55:49.316030 DQS Delay:
2609 11:55:49.316510 DQS0 = 0, DQS1 = 0
2610 11:55:49.319498 DQM Delay:
2611 11:55:49.320079 DQM0 = 122, DQM1 = 110
2612 11:55:49.320564 DQ Delay:
2613 11:55:49.322597 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2614 11:55:49.329639 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2615 11:55:49.332664 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2616 11:55:49.336199 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2617 11:55:49.336783
2618 11:55:49.337274
2619 11:55:49.337728 ==
2620 11:55:49.340028 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 11:55:49.342809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 11:55:49.343290 ==
2623 11:55:49.343773
2624 11:55:49.344223
2625 11:55:49.345966 TX Vref Scan disable
2626 11:55:49.349552 == TX Byte 0 ==
2627 11:55:49.353130 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2628 11:55:49.356050 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2629 11:55:49.356522 == TX Byte 1 ==
2630 11:55:49.363044 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2631 11:55:49.366327 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2632 11:55:49.366922 ==
2633 11:55:49.369536 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 11:55:49.372546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 11:55:49.373015 ==
2636 11:55:49.386304 TX Vref=22, minBit 0, minWin=23, winSum=395
2637 11:55:49.389033 TX Vref=24, minBit 0, minWin=24, winSum=410
2638 11:55:49.392632 TX Vref=26, minBit 0, minWin=24, winSum=412
2639 11:55:49.396201 TX Vref=28, minBit 3, minWin=25, winSum=419
2640 11:55:49.399391 TX Vref=30, minBit 3, minWin=25, winSum=416
2641 11:55:49.402752 TX Vref=32, minBit 1, minWin=25, winSum=418
2642 11:55:49.409460 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 28
2643 11:55:49.410030
2644 11:55:49.412808 Final TX Range 1 Vref 28
2645 11:55:49.413280
2646 11:55:49.413658 ==
2647 11:55:49.416271 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 11:55:49.419047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 11:55:49.419528 ==
2650 11:55:49.419904
2651 11:55:49.422504
2652 11:55:49.423163 TX Vref Scan disable
2653 11:55:49.426434 == TX Byte 0 ==
2654 11:55:49.429252 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2655 11:55:49.432705 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2656 11:55:49.436176 == TX Byte 1 ==
2657 11:55:49.439696 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2658 11:55:49.443104 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2659 11:55:49.443668
2660 11:55:49.446227 [DATLAT]
2661 11:55:49.446831 Freq=1200, CH0 RK0
2662 11:55:49.447240
2663 11:55:49.449718 DATLAT Default: 0xd
2664 11:55:49.450276 0, 0xFFFF, sum = 0
2665 11:55:49.452839 1, 0xFFFF, sum = 0
2666 11:55:49.453408 2, 0xFFFF, sum = 0
2667 11:55:49.456216 3, 0xFFFF, sum = 0
2668 11:55:49.456781 4, 0xFFFF, sum = 0
2669 11:55:49.459632 5, 0xFFFF, sum = 0
2670 11:55:49.460200 6, 0xFFFF, sum = 0
2671 11:55:49.462828 7, 0xFFFF, sum = 0
2672 11:55:49.463394 8, 0xFFFF, sum = 0
2673 11:55:49.466702 9, 0xFFFF, sum = 0
2674 11:55:49.467282 10, 0xFFFF, sum = 0
2675 11:55:49.469399 11, 0xFFFF, sum = 0
2676 11:55:49.472773 12, 0x0, sum = 1
2677 11:55:49.473377 13, 0x0, sum = 2
2678 11:55:49.473764 14, 0x0, sum = 3
2679 11:55:49.476444 15, 0x0, sum = 4
2680 11:55:49.477040 best_step = 13
2681 11:55:49.477420
2682 11:55:49.477764 ==
2683 11:55:49.479030 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 11:55:49.486055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 11:55:49.486648 ==
2686 11:55:49.487031 RX Vref Scan: 1
2687 11:55:49.487381
2688 11:55:49.489431 Set Vref Range= 32 -> 127
2689 11:55:49.490034
2690 11:55:49.492676 RX Vref 32 -> 127, step: 1
2691 11:55:49.493146
2692 11:55:49.496560 RX Delay -13 -> 252, step: 4
2693 11:55:49.497124
2694 11:55:49.499066 Set Vref, RX VrefLevel [Byte0]: 32
2695 11:55:49.502837 [Byte1]: 32
2696 11:55:49.503401
2697 11:55:49.505856 Set Vref, RX VrefLevel [Byte0]: 33
2698 11:55:49.509887 [Byte1]: 33
2699 11:55:49.510495
2700 11:55:49.512524 Set Vref, RX VrefLevel [Byte0]: 34
2701 11:55:49.516368 [Byte1]: 34
2702 11:55:49.520122
2703 11:55:49.520699 Set Vref, RX VrefLevel [Byte0]: 35
2704 11:55:49.523084 [Byte1]: 35
2705 11:55:49.528005
2706 11:55:49.528579 Set Vref, RX VrefLevel [Byte0]: 36
2707 11:55:49.531465 [Byte1]: 36
2708 11:55:49.536155
2709 11:55:49.536732 Set Vref, RX VrefLevel [Byte0]: 37
2710 11:55:49.539060 [Byte1]: 37
2711 11:55:49.543600
2712 11:55:49.544233 Set Vref, RX VrefLevel [Byte0]: 38
2713 11:55:49.546997 [Byte1]: 38
2714 11:55:49.551680
2715 11:55:49.552256 Set Vref, RX VrefLevel [Byte0]: 39
2716 11:55:49.555126 [Byte1]: 39
2717 11:55:49.559395
2718 11:55:49.559975 Set Vref, RX VrefLevel [Byte0]: 40
2719 11:55:49.563066 [Byte1]: 40
2720 11:55:49.567978
2721 11:55:49.568554 Set Vref, RX VrefLevel [Byte0]: 41
2722 11:55:49.570445 [Byte1]: 41
2723 11:55:49.575151
2724 11:55:49.575857 Set Vref, RX VrefLevel [Byte0]: 42
2725 11:55:49.578339 [Byte1]: 42
2726 11:55:49.583172
2727 11:55:49.583885 Set Vref, RX VrefLevel [Byte0]: 43
2728 11:55:49.586556 [Byte1]: 43
2729 11:55:49.590718
2730 11:55:49.591226 Set Vref, RX VrefLevel [Byte0]: 44
2731 11:55:49.594069 [Byte1]: 44
2732 11:55:49.598637
2733 11:55:49.599326 Set Vref, RX VrefLevel [Byte0]: 45
2734 11:55:49.601823 [Byte1]: 45
2735 11:55:49.606541
2736 11:55:49.607020 Set Vref, RX VrefLevel [Byte0]: 46
2737 11:55:49.610479 [Byte1]: 46
2738 11:55:49.614635
2739 11:55:49.615121 Set Vref, RX VrefLevel [Byte0]: 47
2740 11:55:49.617879 [Byte1]: 47
2741 11:55:49.622546
2742 11:55:49.623017 Set Vref, RX VrefLevel [Byte0]: 48
2743 11:55:49.625622 [Byte1]: 48
2744 11:55:49.630498
2745 11:55:49.630969 Set Vref, RX VrefLevel [Byte0]: 49
2746 11:55:49.633469 [Byte1]: 49
2747 11:55:49.638422
2748 11:55:49.638990 Set Vref, RX VrefLevel [Byte0]: 50
2749 11:55:49.641875 [Byte1]: 50
2750 11:55:49.646345
2751 11:55:49.646968 Set Vref, RX VrefLevel [Byte0]: 51
2752 11:55:49.649354 [Byte1]: 51
2753 11:55:49.654075
2754 11:55:49.654672 Set Vref, RX VrefLevel [Byte0]: 52
2755 11:55:49.657317 [Byte1]: 52
2756 11:55:49.662742
2757 11:55:49.663310 Set Vref, RX VrefLevel [Byte0]: 53
2758 11:55:49.665493 [Byte1]: 53
2759 11:55:49.670155
2760 11:55:49.670770 Set Vref, RX VrefLevel [Byte0]: 54
2761 11:55:49.673305 [Byte1]: 54
2762 11:55:49.677648
2763 11:55:49.678216 Set Vref, RX VrefLevel [Byte0]: 55
2764 11:55:49.680858 [Byte1]: 55
2765 11:55:49.685623
2766 11:55:49.686183 Set Vref, RX VrefLevel [Byte0]: 56
2767 11:55:49.689139 [Byte1]: 56
2768 11:55:49.693321
2769 11:55:49.693809 Set Vref, RX VrefLevel [Byte0]: 57
2770 11:55:49.697176 [Byte1]: 57
2771 11:55:49.701383
2772 11:55:49.701948 Set Vref, RX VrefLevel [Byte0]: 58
2773 11:55:49.704849 [Byte1]: 58
2774 11:55:49.709173
2775 11:55:49.709735 Set Vref, RX VrefLevel [Byte0]: 59
2776 11:55:49.712675 [Byte1]: 59
2777 11:55:49.717440
2778 11:55:49.717909 Set Vref, RX VrefLevel [Byte0]: 60
2779 11:55:49.720523 [Byte1]: 60
2780 11:55:49.724964
2781 11:55:49.725527 Set Vref, RX VrefLevel [Byte0]: 61
2782 11:55:49.728256 [Byte1]: 61
2783 11:55:49.733204
2784 11:55:49.733768 Set Vref, RX VrefLevel [Byte0]: 62
2785 11:55:49.736631 [Byte1]: 62
2786 11:55:49.741132
2787 11:55:49.741699 Set Vref, RX VrefLevel [Byte0]: 63
2788 11:55:49.745041 [Byte1]: 63
2789 11:55:49.748878
2790 11:55:49.749444 Set Vref, RX VrefLevel [Byte0]: 64
2791 11:55:49.751858 [Byte1]: 64
2792 11:55:49.756693
2793 11:55:49.757255 Set Vref, RX VrefLevel [Byte0]: 65
2794 11:55:49.760174 [Byte1]: 65
2795 11:55:49.765047
2796 11:55:49.765609 Set Vref, RX VrefLevel [Byte0]: 66
2797 11:55:49.768013 [Byte1]: 66
2798 11:55:49.772747
2799 11:55:49.773314 Set Vref, RX VrefLevel [Byte0]: 67
2800 11:55:49.775871 [Byte1]: 67
2801 11:55:49.780614
2802 11:55:49.781181 Set Vref, RX VrefLevel [Byte0]: 68
2803 11:55:49.783965 [Byte1]: 68
2804 11:55:49.788390
2805 11:55:49.788955 Set Vref, RX VrefLevel [Byte0]: 69
2806 11:55:49.791265 [Byte1]: 69
2807 11:55:49.796388
2808 11:55:49.796948 Set Vref, RX VrefLevel [Byte0]: 70
2809 11:55:49.799267 [Byte1]: 70
2810 11:55:49.804109
2811 11:55:49.804675 Final RX Vref Byte 0 = 58 to rank0
2812 11:55:49.807733 Final RX Vref Byte 1 = 52 to rank0
2813 11:55:49.810777 Final RX Vref Byte 0 = 58 to rank1
2814 11:55:49.813643 Final RX Vref Byte 1 = 52 to rank1==
2815 11:55:49.817545 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 11:55:49.820481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 11:55:49.823844 ==
2818 11:55:49.824315 DQS Delay:
2819 11:55:49.824693 DQS0 = 0, DQS1 = 0
2820 11:55:49.826990 DQM Delay:
2821 11:55:49.827489 DQM0 = 122, DQM1 = 109
2822 11:55:49.830973 DQ Delay:
2823 11:55:49.834482 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2824 11:55:49.837385 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2825 11:55:49.840948 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2826 11:55:49.844070 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2827 11:55:49.844690
2828 11:55:49.845080
2829 11:55:49.850928 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2830 11:55:49.854873 CH0 RK0: MR19=404, MR18=D0A
2831 11:55:49.860606 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2832 11:55:49.861205
2833 11:55:49.864131 ----->DramcWriteLeveling(PI) begin...
2834 11:55:49.864711 ==
2835 11:55:49.867565 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 11:55:49.871050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 11:55:49.871628 ==
2838 11:55:49.874030 Write leveling (Byte 0): 36 => 36
2839 11:55:49.877560 Write leveling (Byte 1): 29 => 29
2840 11:55:49.881028 DramcWriteLeveling(PI) end<-----
2841 11:55:49.881604
2842 11:55:49.881977 ==
2843 11:55:49.884093 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 11:55:49.887409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 11:55:49.890897 ==
2846 11:55:49.891471 [Gating] SW mode calibration
2847 11:55:49.900599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 11:55:49.903872 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 11:55:49.907300 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2850 11:55:49.914041 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 11:55:49.916957 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 11:55:49.920370 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 11:55:49.927231 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:55:49.930302 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:55:49.933847 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:55:49.940850 0 15 28 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
2857 11:55:49.943873 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 11:55:49.946946 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 11:55:49.954054 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 11:55:49.957887 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 11:55:49.961158 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:55:49.967104 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:55:49.970611 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2864 11:55:49.974723 1 0 28 | B1->B0 | 3939 3e3e | 0 0 | (1 1) (0 0)
2865 11:55:49.977685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 11:55:49.984077 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 11:55:49.987245 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 11:55:49.991241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 11:55:49.997580 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:55:50.000795 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:55:50.004210 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:55:50.011035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:55:50.013858 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2874 11:55:50.017149 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:55:50.024405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:55:50.027369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:55:50.030754 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:55:50.037614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:55:50.040698 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:55:50.044148 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:55:50.050886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:55:50.054338 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:55:50.057535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:55:50.061153 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:55:50.067924 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:55:50.070881 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:55:50.074885 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:55:50.081234 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2889 11:55:50.084861 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 11:55:50.088112 Total UI for P1: 0, mck2ui 16
2891 11:55:50.091575 best dqsien dly found for B0: ( 1, 3, 28)
2892 11:55:50.094541 Total UI for P1: 0, mck2ui 16
2893 11:55:50.097796 best dqsien dly found for B1: ( 1, 3, 28)
2894 11:55:50.101043 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2895 11:55:50.104266 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2896 11:55:50.104841
2897 11:55:50.108183 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2898 11:55:50.111227 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 11:55:50.114149 [Gating] SW calibration Done
2900 11:55:50.114651 ==
2901 11:55:50.117985 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 11:55:50.121067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 11:55:50.121598 ==
2904 11:55:50.124178 RX Vref Scan: 0
2905 11:55:50.124650
2906 11:55:50.127473 RX Vref 0 -> 0, step: 1
2907 11:55:50.127942
2908 11:55:50.128311 RX Delay -40 -> 252, step: 8
2909 11:55:50.134495 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2910 11:55:50.137541 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2911 11:55:50.141050 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2912 11:55:50.144476 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2913 11:55:50.147848 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2914 11:55:50.154296 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2915 11:55:50.158070 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2916 11:55:50.161424 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2917 11:55:50.164774 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2918 11:55:50.168294 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2919 11:55:50.171543 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2920 11:55:50.178052 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2921 11:55:50.181655 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2922 11:55:50.185081 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2923 11:55:50.188298 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2924 11:55:50.191592 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2925 11:55:50.194759 ==
2926 11:55:50.198282 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 11:55:50.201646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 11:55:50.202227 ==
2929 11:55:50.202649 DQS Delay:
2930 11:55:50.205386 DQS0 = 0, DQS1 = 0
2931 11:55:50.205995 DQM Delay:
2932 11:55:50.208355 DQM0 = 120, DQM1 = 108
2933 11:55:50.208937 DQ Delay:
2934 11:55:50.211600 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2935 11:55:50.215002 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2936 11:55:50.218560 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2937 11:55:50.221569 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2938 11:55:50.222049
2939 11:55:50.222473
2940 11:55:50.222836 ==
2941 11:55:50.225178 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 11:55:50.231389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 11:55:50.231974 ==
2944 11:55:50.232352
2945 11:55:50.232696
2946 11:55:50.233031 TX Vref Scan disable
2947 11:55:50.234758 == TX Byte 0 ==
2948 11:55:50.238237 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2949 11:55:50.242048 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2950 11:55:50.245017 == TX Byte 1 ==
2951 11:55:50.248090 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2952 11:55:50.254944 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2953 11:55:50.255567 ==
2954 11:55:50.258302 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 11:55:50.261453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 11:55:50.262020 ==
2957 11:55:50.273412 TX Vref=22, minBit 0, minWin=25, winSum=412
2958 11:55:50.276961 TX Vref=24, minBit 0, minWin=25, winSum=418
2959 11:55:50.280218 TX Vref=26, minBit 0, minWin=25, winSum=421
2960 11:55:50.283370 TX Vref=28, minBit 2, minWin=25, winSum=420
2961 11:55:50.287054 TX Vref=30, minBit 1, minWin=25, winSum=424
2962 11:55:50.290345 TX Vref=32, minBit 5, minWin=25, winSum=426
2963 11:55:50.297253 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 32
2964 11:55:50.297827
2965 11:55:50.300459 Final TX Range 1 Vref 32
2966 11:55:50.301024
2967 11:55:50.301399 ==
2968 11:55:50.303779 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 11:55:50.306739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 11:55:50.307322 ==
2971 11:55:50.307704
2972 11:55:50.310163
2973 11:55:50.310676 TX Vref Scan disable
2974 11:55:50.313531 == TX Byte 0 ==
2975 11:55:50.316910 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2976 11:55:50.319960 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2977 11:55:50.323253 == TX Byte 1 ==
2978 11:55:50.327029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2979 11:55:50.330627 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2980 11:55:50.331201
2981 11:55:50.333582 [DATLAT]
2982 11:55:50.334051 Freq=1200, CH0 RK1
2983 11:55:50.334468
2984 11:55:50.336551 DATLAT Default: 0xd
2985 11:55:50.337026 0, 0xFFFF, sum = 0
2986 11:55:50.340028 1, 0xFFFF, sum = 0
2987 11:55:50.340512 2, 0xFFFF, sum = 0
2988 11:55:50.343063 3, 0xFFFF, sum = 0
2989 11:55:50.346718 4, 0xFFFF, sum = 0
2990 11:55:50.347200 5, 0xFFFF, sum = 0
2991 11:55:50.349988 6, 0xFFFF, sum = 0
2992 11:55:50.350597 7, 0xFFFF, sum = 0
2993 11:55:50.353343 8, 0xFFFF, sum = 0
2994 11:55:50.353934 9, 0xFFFF, sum = 0
2995 11:55:50.357108 10, 0xFFFF, sum = 0
2996 11:55:50.357693 11, 0xFFFF, sum = 0
2997 11:55:50.359975 12, 0x0, sum = 1
2998 11:55:50.360560 13, 0x0, sum = 2
2999 11:55:50.363091 14, 0x0, sum = 3
3000 11:55:50.363568 15, 0x0, sum = 4
3001 11:55:50.363951 best_step = 13
3002 11:55:50.364298
3003 11:55:50.366361 ==
3004 11:55:50.369733 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 11:55:50.373385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 11:55:50.373973 ==
3007 11:55:50.374357 RX Vref Scan: 0
3008 11:55:50.374755
3009 11:55:50.376534 RX Vref 0 -> 0, step: 1
3010 11:55:50.377109
3011 11:55:50.380079 RX Delay -21 -> 252, step: 4
3012 11:55:50.383382 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3013 11:55:50.387268 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3014 11:55:50.393338 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3015 11:55:50.396713 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3016 11:55:50.400632 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3017 11:55:50.403572 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3018 11:55:50.407148 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3019 11:55:50.414413 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3020 11:55:50.417124 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3021 11:55:50.419871 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3022 11:55:50.423232 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3023 11:55:50.427280 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3024 11:55:50.433506 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3025 11:55:50.436904 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3026 11:55:50.440436 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3027 11:55:50.443619 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3028 11:55:50.444187 ==
3029 11:55:50.447020 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 11:55:50.453553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 11:55:50.454238 ==
3032 11:55:50.454745 DQS Delay:
3033 11:55:50.455108 DQS0 = 0, DQS1 = 0
3034 11:55:50.457072 DQM Delay:
3035 11:55:50.457633 DQM0 = 119, DQM1 = 108
3036 11:55:50.460142 DQ Delay:
3037 11:55:50.463587 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3038 11:55:50.466870 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3039 11:55:50.470476 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3040 11:55:50.473703 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =114
3041 11:55:50.474176
3042 11:55:50.474583
3043 11:55:50.480487 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3044 11:55:50.483719 CH0 RK1: MR19=403, MR18=EF5
3045 11:55:50.490919 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3046 11:55:50.493474 [RxdqsGatingPostProcess] freq 1200
3047 11:55:50.500520 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 11:55:50.501105 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 11:55:50.503410 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 11:55:50.507038 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 11:55:50.510352 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 11:55:50.513779 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 11:55:50.517188 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 11:55:50.520338 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 11:55:50.523785 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 11:55:50.526965 Pre-setting of DQS Precalculation
3057 11:55:50.530300 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 11:55:50.534003 ==
3059 11:55:50.534638 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 11:55:50.540372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 11:55:50.540936 ==
3062 11:55:50.543690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 11:55:50.550273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3064 11:55:50.559454 [CA 0] Center 37 (7~68) winsize 62
3065 11:55:50.562755 [CA 1] Center 37 (7~68) winsize 62
3066 11:55:50.565990 [CA 2] Center 35 (5~65) winsize 61
3067 11:55:50.569642 [CA 3] Center 34 (4~65) winsize 62
3068 11:55:50.572778 [CA 4] Center 34 (4~64) winsize 61
3069 11:55:50.575958 [CA 5] Center 33 (3~64) winsize 62
3070 11:55:50.576521
3071 11:55:50.579043 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3072 11:55:50.579513
3073 11:55:50.583092 [CATrainingPosCal] consider 1 rank data
3074 11:55:50.586360 u2DelayCellTimex100 = 270/100 ps
3075 11:55:50.589589 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 11:55:50.592693 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 11:55:50.599304 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3078 11:55:50.602773 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3079 11:55:50.606169 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 11:55:50.609783 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3081 11:55:50.610350
3082 11:55:50.612720 CA PerBit enable=1, Macro0, CA PI delay=33
3083 11:55:50.613281
3084 11:55:50.615877 [CBTSetCACLKResult] CA Dly = 33
3085 11:55:50.616349 CS Dly: 5 (0~36)
3086 11:55:50.616720 ==
3087 11:55:50.619345 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 11:55:50.625930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 11:55:50.626591 ==
3090 11:55:50.629170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 11:55:50.635845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3092 11:55:50.645173 [CA 0] Center 38 (8~68) winsize 61
3093 11:55:50.648325 [CA 1] Center 38 (7~69) winsize 63
3094 11:55:50.651518 [CA 2] Center 35 (5~66) winsize 62
3095 11:55:50.655221 [CA 3] Center 34 (4~65) winsize 62
3096 11:55:50.658224 [CA 4] Center 35 (5~65) winsize 61
3097 11:55:50.661697 [CA 5] Center 34 (4~64) winsize 61
3098 11:55:50.662263
3099 11:55:50.665168 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3100 11:55:50.665739
3101 11:55:50.668447 [CATrainingPosCal] consider 2 rank data
3102 11:55:50.672111 u2DelayCellTimex100 = 270/100 ps
3103 11:55:50.674995 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3104 11:55:50.678502 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3105 11:55:50.685382 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3106 11:55:50.688040 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3107 11:55:50.691711 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3108 11:55:50.694861 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3109 11:55:50.695344
3110 11:55:50.698620 CA PerBit enable=1, Macro0, CA PI delay=34
3111 11:55:50.699186
3112 11:55:50.701675 [CBTSetCACLKResult] CA Dly = 34
3113 11:55:50.702205 CS Dly: 6 (0~39)
3114 11:55:50.702623
3115 11:55:50.704845 ----->DramcWriteLeveling(PI) begin...
3116 11:55:50.708487 ==
3117 11:55:50.709058 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 11:55:50.714827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 11:55:50.715400 ==
3120 11:55:50.718172 Write leveling (Byte 0): 24 => 24
3121 11:55:50.721794 Write leveling (Byte 1): 27 => 27
3122 11:55:50.722265 DramcWriteLeveling(PI) end<-----
3123 11:55:50.724902
3124 11:55:50.725413 ==
3125 11:55:50.728294 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 11:55:50.731905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 11:55:50.732472 ==
3128 11:55:50.734955 [Gating] SW mode calibration
3129 11:55:50.741993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 11:55:50.745237 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 11:55:50.751936 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 11:55:50.755293 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 11:55:50.758308 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 11:55:50.765990 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 11:55:50.768727 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:55:50.771584 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3137 11:55:50.779120 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
3138 11:55:50.782042 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3139 11:55:50.785374 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 11:55:50.792179 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 11:55:50.795261 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 11:55:50.798402 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 11:55:50.805032 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:55:50.808806 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3145 11:55:50.812191 1 0 24 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
3146 11:55:50.815378 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:55:50.821904 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 11:55:50.825679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 11:55:50.828697 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 11:55:50.835187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 11:55:50.838918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:55:50.842712 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:55:50.849166 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3154 11:55:50.852250 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3155 11:55:50.855408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:55:50.862217 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:55:50.865882 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:55:50.869221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:55:50.875598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:55:50.879043 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:55:50.882568 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:55:50.885978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:55:50.892635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:55:50.895438 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:55:50.898910 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:55:50.905386 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:55:50.909096 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:55:50.912814 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:55:50.918910 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3170 11:55:50.922830 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3171 11:55:50.925595 Total UI for P1: 0, mck2ui 16
3172 11:55:50.929093 best dqsien dly found for B0: ( 1, 3, 24)
3173 11:55:50.932280 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 11:55:50.936209 Total UI for P1: 0, mck2ui 16
3175 11:55:50.939059 best dqsien dly found for B1: ( 1, 3, 26)
3176 11:55:50.942496 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3177 11:55:50.946012 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3178 11:55:50.946618
3179 11:55:50.949401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3180 11:55:50.955999 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3181 11:55:50.956578 [Gating] SW calibration Done
3182 11:55:50.956961 ==
3183 11:55:50.958733 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 11:55:50.965934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 11:55:50.966550 ==
3186 11:55:50.966939 RX Vref Scan: 0
3187 11:55:50.967295
3188 11:55:50.969580 RX Vref 0 -> 0, step: 1
3189 11:55:50.970152
3190 11:55:50.972453 RX Delay -40 -> 252, step: 8
3191 11:55:50.975915 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 11:55:50.979130 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 11:55:50.982509 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 11:55:50.989360 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3195 11:55:50.992478 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3196 11:55:50.995522 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3197 11:55:50.999071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3198 11:55:51.002551 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3199 11:55:51.005683 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3200 11:55:51.012787 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3201 11:55:51.015444 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 11:55:51.019353 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3203 11:55:51.022444 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 11:55:51.025609 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3205 11:55:51.033072 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3206 11:55:51.035952 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3207 11:55:51.036540 ==
3208 11:55:51.039091 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 11:55:51.042337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 11:55:51.042972 ==
3211 11:55:51.045904 DQS Delay:
3212 11:55:51.046519 DQS0 = 0, DQS1 = 0
3213 11:55:51.046905 DQM Delay:
3214 11:55:51.049303 DQM0 = 119, DQM1 = 112
3215 11:55:51.049880 DQ Delay:
3216 11:55:51.052194 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3217 11:55:51.055770 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3218 11:55:51.059186 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3219 11:55:51.066131 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3220 11:55:51.066741
3221 11:55:51.067128
3222 11:55:51.067478 ==
3223 11:55:51.069077 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 11:55:51.072755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 11:55:51.073252 ==
3226 11:55:51.073633
3227 11:55:51.073984
3228 11:55:51.075943 TX Vref Scan disable
3229 11:55:51.076529 == TX Byte 0 ==
3230 11:55:51.082632 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3231 11:55:51.085425 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3232 11:55:51.085902 == TX Byte 1 ==
3233 11:55:51.092316 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 11:55:51.096244 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 11:55:51.096725 ==
3236 11:55:51.099206 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 11:55:51.102642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 11:55:51.103224 ==
3239 11:55:51.115047 TX Vref=22, minBit 11, minWin=23, winSum=406
3240 11:55:51.118615 TX Vref=24, minBit 11, minWin=24, winSum=407
3241 11:55:51.121997 TX Vref=26, minBit 8, minWin=25, winSum=416
3242 11:55:51.125041 TX Vref=28, minBit 9, minWin=25, winSum=421
3243 11:55:51.128460 TX Vref=30, minBit 0, minWin=26, winSum=424
3244 11:55:51.135041 TX Vref=32, minBit 1, minWin=26, winSum=425
3245 11:55:51.139449 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 32
3246 11:55:51.140018
3247 11:55:51.142062 Final TX Range 1 Vref 32
3248 11:55:51.142588
3249 11:55:51.142969 ==
3250 11:55:51.145069 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 11:55:51.149034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 11:55:51.149605 ==
3253 11:55:51.149985
3254 11:55:51.151958
3255 11:55:51.152426 TX Vref Scan disable
3256 11:55:51.155297 == TX Byte 0 ==
3257 11:55:51.158764 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3258 11:55:51.161879 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3259 11:55:51.165467 == TX Byte 1 ==
3260 11:55:51.168658 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3261 11:55:51.171898 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3262 11:55:51.172462
3263 11:55:51.175463 [DATLAT]
3264 11:55:51.176030 Freq=1200, CH1 RK0
3265 11:55:51.176407
3266 11:55:51.178596 DATLAT Default: 0xd
3267 11:55:51.179165 0, 0xFFFF, sum = 0
3268 11:55:51.182149 1, 0xFFFF, sum = 0
3269 11:55:51.182756 2, 0xFFFF, sum = 0
3270 11:55:51.185317 3, 0xFFFF, sum = 0
3271 11:55:51.185887 4, 0xFFFF, sum = 0
3272 11:55:51.188821 5, 0xFFFF, sum = 0
3273 11:55:51.189396 6, 0xFFFF, sum = 0
3274 11:55:51.192192 7, 0xFFFF, sum = 0
3275 11:55:51.192763 8, 0xFFFF, sum = 0
3276 11:55:51.195280 9, 0xFFFF, sum = 0
3277 11:55:51.195925 10, 0xFFFF, sum = 0
3278 11:55:51.198824 11, 0xFFFF, sum = 0
3279 11:55:51.199306 12, 0x0, sum = 1
3280 11:55:51.202149 13, 0x0, sum = 2
3281 11:55:51.202931 14, 0x0, sum = 3
3282 11:55:51.205565 15, 0x0, sum = 4
3283 11:55:51.206136 best_step = 13
3284 11:55:51.206567
3285 11:55:51.206958 ==
3286 11:55:51.208874 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 11:55:51.215388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 11:55:51.215955 ==
3289 11:55:51.216334 RX Vref Scan: 1
3290 11:55:51.216712
3291 11:55:51.218566 Set Vref Range= 32 -> 127
3292 11:55:51.219052
3293 11:55:51.222190 RX Vref 32 -> 127, step: 1
3294 11:55:51.222693
3295 11:55:51.225611 RX Delay -13 -> 252, step: 4
3296 11:55:51.226115
3297 11:55:51.226592 Set Vref, RX VrefLevel [Byte0]: 32
3298 11:55:51.228902 [Byte1]: 32
3299 11:55:51.233503
3300 11:55:51.233955 Set Vref, RX VrefLevel [Byte0]: 33
3301 11:55:51.236985 [Byte1]: 33
3302 11:55:51.241323
3303 11:55:51.241776 Set Vref, RX VrefLevel [Byte0]: 34
3304 11:55:51.244448 [Byte1]: 34
3305 11:55:51.249705
3306 11:55:51.250214 Set Vref, RX VrefLevel [Byte0]: 35
3307 11:55:51.252812 [Byte1]: 35
3308 11:55:51.256902
3309 11:55:51.257311 Set Vref, RX VrefLevel [Byte0]: 36
3310 11:55:51.260736 [Byte1]: 36
3311 11:55:51.265343
3312 11:55:51.265854 Set Vref, RX VrefLevel [Byte0]: 37
3313 11:55:51.268167 [Byte1]: 37
3314 11:55:51.272881
3315 11:55:51.273451 Set Vref, RX VrefLevel [Byte0]: 38
3316 11:55:51.276089 [Byte1]: 38
3317 11:55:51.280579
3318 11:55:51.281129 Set Vref, RX VrefLevel [Byte0]: 39
3319 11:55:51.284161 [Byte1]: 39
3320 11:55:51.288604
3321 11:55:51.289157 Set Vref, RX VrefLevel [Byte0]: 40
3322 11:55:51.292020 [Byte1]: 40
3323 11:55:51.296563
3324 11:55:51.297120 Set Vref, RX VrefLevel [Byte0]: 41
3325 11:55:51.299747 [Byte1]: 41
3326 11:55:51.304789
3327 11:55:51.305344 Set Vref, RX VrefLevel [Byte0]: 42
3328 11:55:51.307622 [Byte1]: 42
3329 11:55:51.312307
3330 11:55:51.312854 Set Vref, RX VrefLevel [Byte0]: 43
3331 11:55:51.315428 [Byte1]: 43
3332 11:55:51.319901
3333 11:55:51.320355 Set Vref, RX VrefLevel [Byte0]: 44
3334 11:55:51.323331 [Byte1]: 44
3335 11:55:51.327741
3336 11:55:51.328212 Set Vref, RX VrefLevel [Byte0]: 45
3337 11:55:51.331246 [Byte1]: 45
3338 11:55:51.335720
3339 11:55:51.336195 Set Vref, RX VrefLevel [Byte0]: 46
3340 11:55:51.339090 [Byte1]: 46
3341 11:55:51.343972
3342 11:55:51.344704 Set Vref, RX VrefLevel [Byte0]: 47
3343 11:55:51.347197 [Byte1]: 47
3344 11:55:51.351494
3345 11:55:51.351963 Set Vref, RX VrefLevel [Byte0]: 48
3346 11:55:51.355200 [Byte1]: 48
3347 11:55:51.359312
3348 11:55:51.359883 Set Vref, RX VrefLevel [Byte0]: 49
3349 11:55:51.363025 [Byte1]: 49
3350 11:55:51.367372
3351 11:55:51.367943 Set Vref, RX VrefLevel [Byte0]: 50
3352 11:55:51.370846 [Byte1]: 50
3353 11:55:51.375319
3354 11:55:51.375888 Set Vref, RX VrefLevel [Byte0]: 51
3355 11:55:51.378766 [Byte1]: 51
3356 11:55:51.383304
3357 11:55:51.383878 Set Vref, RX VrefLevel [Byte0]: 52
3358 11:55:51.386590 [Byte1]: 52
3359 11:55:51.391365
3360 11:55:51.391938 Set Vref, RX VrefLevel [Byte0]: 53
3361 11:55:51.394597 [Byte1]: 53
3362 11:55:51.399050
3363 11:55:51.399615 Set Vref, RX VrefLevel [Byte0]: 54
3364 11:55:51.402464 [Byte1]: 54
3365 11:55:51.407001
3366 11:55:51.407568 Set Vref, RX VrefLevel [Byte0]: 55
3367 11:55:51.410193 [Byte1]: 55
3368 11:55:51.415312
3369 11:55:51.415886 Set Vref, RX VrefLevel [Byte0]: 56
3370 11:55:51.417893 [Byte1]: 56
3371 11:55:51.422761
3372 11:55:51.423469 Set Vref, RX VrefLevel [Byte0]: 57
3373 11:55:51.425834 [Byte1]: 57
3374 11:55:51.430517
3375 11:55:51.431028 Set Vref, RX VrefLevel [Byte0]: 58
3376 11:55:51.433847 [Byte1]: 58
3377 11:55:51.438808
3378 11:55:51.439405 Set Vref, RX VrefLevel [Byte0]: 59
3379 11:55:51.441791 [Byte1]: 59
3380 11:55:51.446100
3381 11:55:51.446610 Set Vref, RX VrefLevel [Byte0]: 60
3382 11:55:51.449665 [Byte1]: 60
3383 11:55:51.453961
3384 11:55:51.454458 Set Vref, RX VrefLevel [Byte0]: 61
3385 11:55:51.458141 [Byte1]: 61
3386 11:55:51.462541
3387 11:55:51.463103 Set Vref, RX VrefLevel [Byte0]: 62
3388 11:55:51.465453 [Byte1]: 62
3389 11:55:51.470523
3390 11:55:51.471087 Set Vref, RX VrefLevel [Byte0]: 63
3391 11:55:51.473757 [Byte1]: 63
3392 11:55:51.478147
3393 11:55:51.478776 Set Vref, RX VrefLevel [Byte0]: 64
3394 11:55:51.481140 [Byte1]: 64
3395 11:55:51.485863
3396 11:55:51.486470 Set Vref, RX VrefLevel [Byte0]: 65
3397 11:55:51.489458 [Byte1]: 65
3398 11:55:51.493908
3399 11:55:51.494530 Set Vref, RX VrefLevel [Byte0]: 66
3400 11:55:51.496830 [Byte1]: 66
3401 11:55:51.502459
3402 11:55:51.503026 Set Vref, RX VrefLevel [Byte0]: 67
3403 11:55:51.504831 [Byte1]: 67
3404 11:55:51.509669
3405 11:55:51.510234 Final RX Vref Byte 0 = 53 to rank0
3406 11:55:51.513010 Final RX Vref Byte 1 = 58 to rank0
3407 11:55:51.515832 Final RX Vref Byte 0 = 53 to rank1
3408 11:55:51.519920 Final RX Vref Byte 1 = 58 to rank1==
3409 11:55:51.522792 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 11:55:51.529450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 11:55:51.530031 ==
3412 11:55:51.530447 DQS Delay:
3413 11:55:51.530802 DQS0 = 0, DQS1 = 0
3414 11:55:51.532704 DQM Delay:
3415 11:55:51.533166 DQM0 = 119, DQM1 = 113
3416 11:55:51.536328 DQ Delay:
3417 11:55:51.539312 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3418 11:55:51.542707 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3419 11:55:51.545938 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =106
3420 11:55:51.549156 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =122
3421 11:55:51.549626
3422 11:55:51.549996
3423 11:55:51.556259 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3424 11:55:51.559892 CH1 RK0: MR19=404, MR18=316
3425 11:55:51.566452 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3426 11:55:51.567027
3427 11:55:51.569988 ----->DramcWriteLeveling(PI) begin...
3428 11:55:51.570596 ==
3429 11:55:51.573129 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 11:55:51.575869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 11:55:51.576339 ==
3432 11:55:51.579558 Write leveling (Byte 0): 24 => 24
3433 11:55:51.582919 Write leveling (Byte 1): 29 => 29
3434 11:55:51.586320 DramcWriteLeveling(PI) end<-----
3435 11:55:51.586909
3436 11:55:51.587283 ==
3437 11:55:51.589213 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 11:55:51.595934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 11:55:51.596499 ==
3440 11:55:51.596902 [Gating] SW mode calibration
3441 11:55:51.606570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 11:55:51.609868 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 11:55:51.613257 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 11:55:51.620364 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 11:55:51.622942 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 11:55:51.626608 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 11:55:51.633229 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:55:51.636483 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:55:51.639772 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 1)
3450 11:55:51.646365 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 0)
3451 11:55:51.649856 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 11:55:51.653018 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 11:55:51.656586 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 11:55:51.663427 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 11:55:51.666691 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 11:55:51.669736 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:55:51.676670 1 0 24 | B1->B0 | 3a3a 2e2e | 0 0 | (0 0) (1 1)
3458 11:55:51.680269 1 0 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
3459 11:55:51.683310 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 11:55:51.690142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 11:55:51.693282 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 11:55:51.696516 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:55:51.703504 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:55:51.706640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:55:51.710144 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 11:55:51.717012 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 11:55:51.720118 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:55:51.723170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:55:51.729788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:55:51.733140 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:55:51.736605 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:55:51.743132 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:55:51.746592 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:55:51.749870 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:55:51.752881 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:55:51.759731 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:55:51.763470 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:55:51.766421 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:55:51.772845 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:55:51.776318 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:55:51.779969 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 11:55:51.786229 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 11:55:51.789913 Total UI for P1: 0, mck2ui 16
3484 11:55:51.792719 best dqsien dly found for B0: ( 1, 3, 24)
3485 11:55:51.795984 Total UI for P1: 0, mck2ui 16
3486 11:55:51.799663 best dqsien dly found for B1: ( 1, 3, 24)
3487 11:55:51.802969 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3488 11:55:51.806088 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3489 11:55:51.806575
3490 11:55:51.809709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3491 11:55:51.813308 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3492 11:55:51.816129 [Gating] SW calibration Done
3493 11:55:51.816701 ==
3494 11:55:51.819016 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 11:55:51.822672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 11:55:51.823252 ==
3497 11:55:51.826242 RX Vref Scan: 0
3498 11:55:51.826864
3499 11:55:51.829121 RX Vref 0 -> 0, step: 1
3500 11:55:51.829590
3501 11:55:51.829963 RX Delay -40 -> 252, step: 8
3502 11:55:51.835990 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3503 11:55:51.838995 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3504 11:55:51.842129 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3505 11:55:51.845790 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3506 11:55:51.848832 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3507 11:55:51.855977 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 11:55:51.858856 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3509 11:55:51.862985 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3510 11:55:51.865765 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3511 11:55:51.869117 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3512 11:55:51.872548 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3513 11:55:51.879284 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3514 11:55:51.882626 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3515 11:55:51.886109 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3516 11:55:51.889616 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3517 11:55:51.895984 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3518 11:55:51.896556 ==
3519 11:55:51.899469 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 11:55:51.902553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 11:55:51.903133 ==
3522 11:55:51.903508 DQS Delay:
3523 11:55:51.906412 DQS0 = 0, DQS1 = 0
3524 11:55:51.906983 DQM Delay:
3525 11:55:51.909773 DQM0 = 120, DQM1 = 113
3526 11:55:51.910341 DQ Delay:
3527 11:55:51.912759 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3528 11:55:51.915793 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3529 11:55:51.919314 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3530 11:55:51.922673 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3531 11:55:51.923237
3532 11:55:51.923604
3533 11:55:51.923942 ==
3534 11:55:51.925844 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 11:55:51.932942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 11:55:51.933516 ==
3537 11:55:51.933895
3538 11:55:51.934242
3539 11:55:51.934634 TX Vref Scan disable
3540 11:55:51.936173 == TX Byte 0 ==
3541 11:55:51.939374 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3542 11:55:51.946080 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3543 11:55:51.946705 == TX Byte 1 ==
3544 11:55:51.949469 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3545 11:55:51.955850 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3546 11:55:51.956416 ==
3547 11:55:51.959068 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 11:55:51.962419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 11:55:51.962903 ==
3550 11:55:51.974415 TX Vref=22, minBit 9, minWin=24, winSum=418
3551 11:55:51.977490 TX Vref=24, minBit 1, minWin=25, winSum=419
3552 11:55:51.981099 TX Vref=26, minBit 1, minWin=26, winSum=423
3553 11:55:51.984382 TX Vref=28, minBit 3, minWin=26, winSum=428
3554 11:55:51.987250 TX Vref=30, minBit 1, minWin=26, winSum=429
3555 11:55:51.990982 TX Vref=32, minBit 0, minWin=26, winSum=425
3556 11:55:51.998073 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3557 11:55:51.998709
3558 11:55:52.000447 Final TX Range 1 Vref 30
3559 11:55:52.000915
3560 11:55:52.001285 ==
3561 11:55:52.004128 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 11:55:52.007510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 11:55:52.007984 ==
3564 11:55:52.008353
3565 11:55:52.011192
3566 11:55:52.011755 TX Vref Scan disable
3567 11:55:52.014204 == TX Byte 0 ==
3568 11:55:52.017619 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 11:55:52.020579 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 11:55:52.024255 == TX Byte 1 ==
3571 11:55:52.027716 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3572 11:55:52.030368 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3573 11:55:52.030866
3574 11:55:52.034078 [DATLAT]
3575 11:55:52.034688 Freq=1200, CH1 RK1
3576 11:55:52.035068
3577 11:55:52.037561 DATLAT Default: 0xd
3578 11:55:52.038125 0, 0xFFFF, sum = 0
3579 11:55:52.040710 1, 0xFFFF, sum = 0
3580 11:55:52.041285 2, 0xFFFF, sum = 0
3581 11:55:52.044024 3, 0xFFFF, sum = 0
3582 11:55:52.044604 4, 0xFFFF, sum = 0
3583 11:55:52.047566 5, 0xFFFF, sum = 0
3584 11:55:52.050674 6, 0xFFFF, sum = 0
3585 11:55:52.051251 7, 0xFFFF, sum = 0
3586 11:55:52.054018 8, 0xFFFF, sum = 0
3587 11:55:52.054630 9, 0xFFFF, sum = 0
3588 11:55:52.057296 10, 0xFFFF, sum = 0
3589 11:55:52.057873 11, 0xFFFF, sum = 0
3590 11:55:52.060479 12, 0x0, sum = 1
3591 11:55:52.061053 13, 0x0, sum = 2
3592 11:55:52.063773 14, 0x0, sum = 3
3593 11:55:52.064248 15, 0x0, sum = 4
3594 11:55:52.064627 best_step = 13
3595 11:55:52.064972
3596 11:55:52.067221 ==
3597 11:55:52.070483 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:55:52.074057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:55:52.074820 ==
3600 11:55:52.075221 RX Vref Scan: 0
3601 11:55:52.075572
3602 11:55:52.077160 RX Vref 0 -> 0, step: 1
3603 11:55:52.077625
3604 11:55:52.080887 RX Delay -13 -> 252, step: 4
3605 11:55:52.084036 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3606 11:55:52.090717 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3607 11:55:52.093784 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3608 11:55:52.097377 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3609 11:55:52.100861 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3610 11:55:52.104009 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3611 11:55:52.110450 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3612 11:55:52.113969 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3613 11:55:52.117310 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3614 11:55:52.120319 iDelay=191, Bit 9, Center 104 (39 ~ 170) 132
3615 11:55:52.124124 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3616 11:55:52.130299 iDelay=191, Bit 11, Center 108 (43 ~ 174) 132
3617 11:55:52.133557 iDelay=191, Bit 12, Center 124 (63 ~ 186) 124
3618 11:55:52.137267 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3619 11:55:52.140512 iDelay=191, Bit 14, Center 120 (59 ~ 182) 124
3620 11:55:52.143222 iDelay=191, Bit 15, Center 126 (63 ~ 190) 128
3621 11:55:52.146699 ==
3622 11:55:52.150497 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 11:55:52.153497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 11:55:52.154057 ==
3625 11:55:52.154465 DQS Delay:
3626 11:55:52.157192 DQS0 = 0, DQS1 = 0
3627 11:55:52.157750 DQM Delay:
3628 11:55:52.160248 DQM0 = 119, DQM1 = 114
3629 11:55:52.160812 DQ Delay:
3630 11:55:52.163554 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3631 11:55:52.166727 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3632 11:55:52.170086 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3633 11:55:52.173551 DQ12 =124, DQ13 =120, DQ14 =120, DQ15 =126
3634 11:55:52.174108
3635 11:55:52.174514
3636 11:55:52.183585 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3637 11:55:52.184154 CH1 RK1: MR19=403, MR18=CF1
3638 11:55:52.190173 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3639 11:55:52.193510 [RxdqsGatingPostProcess] freq 1200
3640 11:55:52.199987 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 11:55:52.203072 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 11:55:52.206821 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 11:55:52.209937 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 11:55:52.213359 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 11:55:52.216872 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 11:55:52.220154 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 11:55:52.220722 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 11:55:52.223273 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 11:55:52.226797 Pre-setting of DQS Precalculation
3650 11:55:52.233418 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 11:55:52.239765 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 11:55:52.246875 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 11:55:52.247446
3654 11:55:52.247816
3655 11:55:52.250088 [Calibration Summary] 2400 Mbps
3656 11:55:52.253003 CH 0, Rank 0
3657 11:55:52.253572 SW Impedance : PASS
3658 11:55:52.256824 DUTY Scan : NO K
3659 11:55:52.260020 ZQ Calibration : PASS
3660 11:55:52.260583 Jitter Meter : NO K
3661 11:55:52.263048 CBT Training : PASS
3662 11:55:52.263615 Write leveling : PASS
3663 11:55:52.266744 RX DQS gating : PASS
3664 11:55:52.269888 RX DQ/DQS(RDDQC) : PASS
3665 11:55:52.270499 TX DQ/DQS : PASS
3666 11:55:52.273048 RX DATLAT : PASS
3667 11:55:52.276552 RX DQ/DQS(Engine): PASS
3668 11:55:52.277122 TX OE : NO K
3669 11:55:52.279587 All Pass.
3670 11:55:52.280086
3671 11:55:52.280462 CH 0, Rank 1
3672 11:55:52.283195 SW Impedance : PASS
3673 11:55:52.283663 DUTY Scan : NO K
3674 11:55:52.286647 ZQ Calibration : PASS
3675 11:55:52.289517 Jitter Meter : NO K
3676 11:55:52.289984 CBT Training : PASS
3677 11:55:52.292687 Write leveling : PASS
3678 11:55:52.296382 RX DQS gating : PASS
3679 11:55:52.297060 RX DQ/DQS(RDDQC) : PASS
3680 11:55:52.299611 TX DQ/DQS : PASS
3681 11:55:52.302829 RX DATLAT : PASS
3682 11:55:52.303294 RX DQ/DQS(Engine): PASS
3683 11:55:52.306091 TX OE : NO K
3684 11:55:52.306584 All Pass.
3685 11:55:52.306954
3686 11:55:52.309413 CH 1, Rank 0
3687 11:55:52.309977 SW Impedance : PASS
3688 11:55:52.313138 DUTY Scan : NO K
3689 11:55:52.313711 ZQ Calibration : PASS
3690 11:55:52.316251 Jitter Meter : NO K
3691 11:55:52.319307 CBT Training : PASS
3692 11:55:52.319772 Write leveling : PASS
3693 11:55:52.322844 RX DQS gating : PASS
3694 11:55:52.326329 RX DQ/DQS(RDDQC) : PASS
3695 11:55:52.326931 TX DQ/DQS : PASS
3696 11:55:52.329792 RX DATLAT : PASS
3697 11:55:52.332868 RX DQ/DQS(Engine): PASS
3698 11:55:52.333480 TX OE : NO K
3699 11:55:52.336010 All Pass.
3700 11:55:52.336475
3701 11:55:52.336847 CH 1, Rank 1
3702 11:55:52.339492 SW Impedance : PASS
3703 11:55:52.339977 DUTY Scan : NO K
3704 11:55:52.342917 ZQ Calibration : PASS
3705 11:55:52.346512 Jitter Meter : NO K
3706 11:55:52.346982 CBT Training : PASS
3707 11:55:52.349340 Write leveling : PASS
3708 11:55:52.352332 RX DQS gating : PASS
3709 11:55:52.352804 RX DQ/DQS(RDDQC) : PASS
3710 11:55:52.355903 TX DQ/DQS : PASS
3711 11:55:52.359095 RX DATLAT : PASS
3712 11:55:52.359560 RX DQ/DQS(Engine): PASS
3713 11:55:52.362370 TX OE : NO K
3714 11:55:52.362871 All Pass.
3715 11:55:52.363243
3716 11:55:52.366025 DramC Write-DBI off
3717 11:55:52.369063 PER_BANK_REFRESH: Hybrid Mode
3718 11:55:52.369531 TX_TRACKING: ON
3719 11:55:52.379028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 11:55:52.382045 [FAST_K] Save calibration result to emmc
3721 11:55:52.385580 dramc_set_vcore_voltage set vcore to 650000
3722 11:55:52.388860 Read voltage for 600, 5
3723 11:55:52.389056 Vio18 = 0
3724 11:55:52.389215 Vcore = 650000
3725 11:55:52.391934 Vdram = 0
3726 11:55:52.392134 Vddq = 0
3727 11:55:52.392262 Vmddr = 0
3728 11:55:52.398653 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 11:55:52.401886 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 11:55:52.405304 MEM_TYPE=3, freq_sel=19
3731 11:55:52.408692 sv_algorithm_assistance_LP4_1600
3732 11:55:52.412118 ============ PULL DRAM RESETB DOWN ============
3733 11:55:52.415064 ========== PULL DRAM RESETB DOWN end =========
3734 11:55:52.421969 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 11:55:52.425260 ===================================
3736 11:55:52.425399 LPDDR4 DRAM CONFIGURATION
3737 11:55:52.428698 ===================================
3738 11:55:52.431942 EX_ROW_EN[0] = 0x0
3739 11:55:52.435412 EX_ROW_EN[1] = 0x0
3740 11:55:52.435552 LP4Y_EN = 0x0
3741 11:55:52.438563 WORK_FSP = 0x0
3742 11:55:52.438700 WL = 0x2
3743 11:55:52.441799 RL = 0x2
3744 11:55:52.441936 BL = 0x2
3745 11:55:52.445004 RPST = 0x0
3746 11:55:52.445184 RD_PRE = 0x0
3747 11:55:52.448448 WR_PRE = 0x1
3748 11:55:52.448586 WR_PST = 0x0
3749 11:55:52.451630 DBI_WR = 0x0
3750 11:55:52.451768 DBI_RD = 0x0
3751 11:55:52.455247 OTF = 0x1
3752 11:55:52.458417 ===================================
3753 11:55:52.461639 ===================================
3754 11:55:52.461776 ANA top config
3755 11:55:52.465096 ===================================
3756 11:55:52.468298 DLL_ASYNC_EN = 0
3757 11:55:52.471519 ALL_SLAVE_EN = 1
3758 11:55:52.474681 NEW_RANK_MODE = 1
3759 11:55:52.474819 DLL_IDLE_MODE = 1
3760 11:55:52.478302 LP45_APHY_COMB_EN = 1
3761 11:55:52.481712 TX_ODT_DIS = 1
3762 11:55:52.484775 NEW_8X_MODE = 1
3763 11:55:52.488375 ===================================
3764 11:55:52.491405 ===================================
3765 11:55:52.494572 data_rate = 1200
3766 11:55:52.494723 CKR = 1
3767 11:55:52.498292 DQ_P2S_RATIO = 8
3768 11:55:52.501514 ===================================
3769 11:55:52.504570 CA_P2S_RATIO = 8
3770 11:55:52.508340 DQ_CA_OPEN = 0
3771 11:55:52.511478 DQ_SEMI_OPEN = 0
3772 11:55:52.514752 CA_SEMI_OPEN = 0
3773 11:55:52.514980 CA_FULL_RATE = 0
3774 11:55:52.518117 DQ_CKDIV4_EN = 1
3775 11:55:52.521570 CA_CKDIV4_EN = 1
3776 11:55:52.525373 CA_PREDIV_EN = 0
3777 11:55:52.528343 PH8_DLY = 0
3778 11:55:52.531397 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 11:55:52.531744 DQ_AAMCK_DIV = 4
3780 11:55:52.534629 CA_AAMCK_DIV = 4
3781 11:55:52.538106 CA_ADMCK_DIV = 4
3782 11:55:52.541615 DQ_TRACK_CA_EN = 0
3783 11:55:52.545044 CA_PICK = 600
3784 11:55:52.548432 CA_MCKIO = 600
3785 11:55:52.549008 MCKIO_SEMI = 0
3786 11:55:52.551755 PLL_FREQ = 2288
3787 11:55:52.554987 DQ_UI_PI_RATIO = 32
3788 11:55:52.559041 CA_UI_PI_RATIO = 0
3789 11:55:52.561943 ===================================
3790 11:55:52.565386 ===================================
3791 11:55:52.568321 memory_type:LPDDR4
3792 11:55:52.568895 GP_NUM : 10
3793 11:55:52.571766 SRAM_EN : 1
3794 11:55:52.574969 MD32_EN : 0
3795 11:55:52.578258 ===================================
3796 11:55:52.578855 [ANA_INIT] >>>>>>>>>>>>>>
3797 11:55:52.581974 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 11:55:52.584918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 11:55:52.588050 ===================================
3800 11:55:52.591465 data_rate = 1200,PCW = 0X5800
3801 11:55:52.594795 ===================================
3802 11:55:52.598489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 11:55:52.604622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 11:55:52.608235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 11:55:52.614894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 11:55:52.618147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 11:55:52.621440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 11:55:52.622100 [ANA_INIT] flow start
3809 11:55:52.624876 [ANA_INIT] PLL >>>>>>>>
3810 11:55:52.627892 [ANA_INIT] PLL <<<<<<<<
3811 11:55:52.628511 [ANA_INIT] MIDPI >>>>>>>>
3812 11:55:52.631446 [ANA_INIT] MIDPI <<<<<<<<
3813 11:55:52.634920 [ANA_INIT] DLL >>>>>>>>
3814 11:55:52.635383 [ANA_INIT] flow end
3815 11:55:52.641728 ============ LP4 DIFF to SE enter ============
3816 11:55:52.644982 ============ LP4 DIFF to SE exit ============
3817 11:55:52.648163 [ANA_INIT] <<<<<<<<<<<<<
3818 11:55:52.651148 [Flow] Enable top DCM control >>>>>
3819 11:55:52.654950 [Flow] Enable top DCM control <<<<<
3820 11:55:52.655515 Enable DLL master slave shuffle
3821 11:55:52.662356 ==============================================================
3822 11:55:52.665033 Gating Mode config
3823 11:55:52.668335 ==============================================================
3824 11:55:52.671423 Config description:
3825 11:55:52.681859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 11:55:52.687958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 11:55:52.691087 SELPH_MODE 0: By rank 1: By Phase
3828 11:55:52.697967 ==============================================================
3829 11:55:52.701041 GAT_TRACK_EN = 1
3830 11:55:52.704561 RX_GATING_MODE = 2
3831 11:55:52.707497 RX_GATING_TRACK_MODE = 2
3832 11:55:52.711512 SELPH_MODE = 1
3833 11:55:52.712185 PICG_EARLY_EN = 1
3834 11:55:52.714356 VALID_LAT_VALUE = 1
3835 11:55:52.720868 ==============================================================
3836 11:55:52.724551 Enter into Gating configuration >>>>
3837 11:55:52.727659 Exit from Gating configuration <<<<
3838 11:55:52.730717 Enter into DVFS_PRE_config >>>>>
3839 11:55:52.740844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 11:55:52.744409 Exit from DVFS_PRE_config <<<<<
3841 11:55:52.747291 Enter into PICG configuration >>>>
3842 11:55:52.750763 Exit from PICG configuration <<<<
3843 11:55:52.754150 [RX_INPUT] configuration >>>>>
3844 11:55:52.757695 [RX_INPUT] configuration <<<<<
3845 11:55:52.760787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 11:55:52.767351 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 11:55:52.773981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 11:55:52.780725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 11:55:52.787253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 11:55:52.794028 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 11:55:52.797366 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 11:55:52.800545 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 11:55:52.803965 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 11:55:52.810476 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 11:55:52.814121 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 11:55:52.817058 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 11:55:52.820445 ===================================
3858 11:55:52.823785 LPDDR4 DRAM CONFIGURATION
3859 11:55:52.827053 ===================================
3860 11:55:52.827627 EX_ROW_EN[0] = 0x0
3861 11:55:52.830850 EX_ROW_EN[1] = 0x0
3862 11:55:52.831314 LP4Y_EN = 0x0
3863 11:55:52.833551 WORK_FSP = 0x0
3864 11:55:52.834145 WL = 0x2
3865 11:55:52.837267 RL = 0x2
3866 11:55:52.837730 BL = 0x2
3867 11:55:52.840228 RPST = 0x0
3868 11:55:52.843741 RD_PRE = 0x0
3869 11:55:52.844307 WR_PRE = 0x1
3870 11:55:52.847176 WR_PST = 0x0
3871 11:55:52.847644 DBI_WR = 0x0
3872 11:55:52.850334 DBI_RD = 0x0
3873 11:55:52.850945 OTF = 0x1
3874 11:55:52.853673 ===================================
3875 11:55:52.857188 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 11:55:52.863769 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 11:55:52.867079 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 11:55:52.870165 ===================================
3879 11:55:52.873791 LPDDR4 DRAM CONFIGURATION
3880 11:55:52.877121 ===================================
3881 11:55:52.877692 EX_ROW_EN[0] = 0x10
3882 11:55:52.880470 EX_ROW_EN[1] = 0x0
3883 11:55:52.881037 LP4Y_EN = 0x0
3884 11:55:52.883736 WORK_FSP = 0x0
3885 11:55:52.884304 WL = 0x2
3886 11:55:52.887026 RL = 0x2
3887 11:55:52.887596 BL = 0x2
3888 11:55:52.890253 RPST = 0x0
3889 11:55:52.890860 RD_PRE = 0x0
3890 11:55:52.893697 WR_PRE = 0x1
3891 11:55:52.894260 WR_PST = 0x0
3892 11:55:52.896793 DBI_WR = 0x0
3893 11:55:52.899917 DBI_RD = 0x0
3894 11:55:52.900552 OTF = 0x1
3895 11:55:52.903501 ===================================
3896 11:55:52.910281 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 11:55:52.913829 nWR fixed to 30
3898 11:55:52.916897 [ModeRegInit_LP4] CH0 RK0
3899 11:55:52.917465 [ModeRegInit_LP4] CH0 RK1
3900 11:55:52.920373 [ModeRegInit_LP4] CH1 RK0
3901 11:55:52.923585 [ModeRegInit_LP4] CH1 RK1
3902 11:55:52.924146 match AC timing 17
3903 11:55:52.930093 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 11:55:52.933414 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 11:55:52.936924 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 11:55:52.943580 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 11:55:52.946759 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 11:55:52.947231 ==
3909 11:55:52.949905 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 11:55:52.953696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 11:55:52.954274 ==
3912 11:55:52.960518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 11:55:52.966955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3914 11:55:52.970126 [CA 0] Center 36 (6~67) winsize 62
3915 11:55:52.973902 [CA 1] Center 36 (6~67) winsize 62
3916 11:55:52.976973 [CA 2] Center 34 (4~65) winsize 62
3917 11:55:52.980311 [CA 3] Center 34 (4~65) winsize 62
3918 11:55:52.983668 [CA 4] Center 34 (3~65) winsize 63
3919 11:55:52.987063 [CA 5] Center 33 (3~64) winsize 62
3920 11:55:52.987626
3921 11:55:52.990033 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3922 11:55:52.990625
3923 11:55:52.993860 [CATrainingPosCal] consider 1 rank data
3924 11:55:52.996977 u2DelayCellTimex100 = 270/100 ps
3925 11:55:53.000340 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 11:55:53.003295 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 11:55:53.007258 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 11:55:53.010122 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 11:55:53.013374 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3930 11:55:53.016674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 11:55:53.020286
3932 11:55:53.023301 CA PerBit enable=1, Macro0, CA PI delay=33
3933 11:55:53.023864
3934 11:55:53.026337 [CBTSetCACLKResult] CA Dly = 33
3935 11:55:53.026844 CS Dly: 4 (0~35)
3936 11:55:53.027215 ==
3937 11:55:53.029883 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 11:55:53.033077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 11:55:53.033557 ==
3940 11:55:53.039728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 11:55:53.046524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 11:55:53.050017 [CA 0] Center 36 (6~67) winsize 62
3943 11:55:53.053520 [CA 1] Center 36 (6~67) winsize 62
3944 11:55:53.056699 [CA 2] Center 34 (4~65) winsize 62
3945 11:55:53.059779 [CA 3] Center 34 (4~65) winsize 62
3946 11:55:53.063396 [CA 4] Center 34 (3~65) winsize 63
3947 11:55:53.067016 [CA 5] Center 33 (3~64) winsize 62
3948 11:55:53.067586
3949 11:55:53.070214 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 11:55:53.070824
3951 11:55:53.073701 [CATrainingPosCal] consider 2 rank data
3952 11:55:53.076712 u2DelayCellTimex100 = 270/100 ps
3953 11:55:53.079945 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 11:55:53.083190 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 11:55:53.086671 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 11:55:53.089852 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 11:55:53.093076 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3958 11:55:53.100191 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 11:55:53.100857
3960 11:55:53.103153 CA PerBit enable=1, Macro0, CA PI delay=33
3961 11:55:53.103622
3962 11:55:53.106645 [CBTSetCACLKResult] CA Dly = 33
3963 11:55:53.107205 CS Dly: 5 (0~37)
3964 11:55:53.107578
3965 11:55:53.110071 ----->DramcWriteLeveling(PI) begin...
3966 11:55:53.110680 ==
3967 11:55:53.113621 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 11:55:53.116549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 11:55:53.119889 ==
3970 11:55:53.122911 Write leveling (Byte 0): 34 => 34
3971 11:55:53.123380 Write leveling (Byte 1): 32 => 32
3972 11:55:53.126494 DramcWriteLeveling(PI) end<-----
3973 11:55:53.127054
3974 11:55:53.127424 ==
3975 11:55:53.129503 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 11:55:53.136532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 11:55:53.137135 ==
3978 11:55:53.140259 [Gating] SW mode calibration
3979 11:55:53.146260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 11:55:53.149423 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 11:55:53.156081 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 11:55:53.159524 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 11:55:53.162691 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 11:55:53.169359 0 9 12 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (1 0)
3985 11:55:53.172752 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
3986 11:55:53.176535 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 11:55:53.179695 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 11:55:53.186162 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:55:53.189441 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 11:55:53.193437 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 11:55:53.199331 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3992 11:55:53.202815 0 10 12 | B1->B0 | 2929 3939 | 0 0 | (0 0) (1 1)
3993 11:55:53.206162 0 10 16 | B1->B0 | 4140 4646 | 1 0 | (0 0) (0 0)
3994 11:55:53.213131 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:55:53.216213 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:55:53.219374 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:55:53.225987 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:55:53.229625 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:55:53.232723 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:55:53.239176 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 11:55:53.242372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:55:53.246034 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:55:53.252747 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:55:53.255902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:55:53.259593 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:55:53.266157 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:55:53.269303 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:55:53.272598 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:55:53.279210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:55:53.282758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:55:53.286510 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:55:53.289460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:55:53.296512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:55:53.299329 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:55:53.302964 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:55:53.309651 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4017 11:55:53.312729 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4018 11:55:53.316412 Total UI for P1: 0, mck2ui 16
4019 11:55:53.319599 best dqsien dly found for B0: ( 0, 13, 12)
4020 11:55:53.322815 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 11:55:53.326173 Total UI for P1: 0, mck2ui 16
4022 11:55:53.329551 best dqsien dly found for B1: ( 0, 13, 14)
4023 11:55:53.332622 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4024 11:55:53.339073 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4025 11:55:53.339547
4026 11:55:53.342206 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4027 11:55:53.345586 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4028 11:55:53.348915 [Gating] SW calibration Done
4029 11:55:53.349490 ==
4030 11:55:53.352581 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 11:55:53.355598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 11:55:53.356099 ==
4033 11:55:53.356477 RX Vref Scan: 0
4034 11:55:53.358761
4035 11:55:53.359390 RX Vref 0 -> 0, step: 1
4036 11:55:53.359779
4037 11:55:53.362133 RX Delay -230 -> 252, step: 16
4038 11:55:53.366007 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4039 11:55:53.372537 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4040 11:55:53.375694 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4041 11:55:53.378825 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4042 11:55:53.382654 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4043 11:55:53.385501 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4044 11:55:53.392482 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4045 11:55:53.395921 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4046 11:55:53.399291 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4047 11:55:53.402085 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4048 11:55:53.409370 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4049 11:55:53.412177 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4050 11:55:53.415756 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4051 11:55:53.419225 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4052 11:55:53.422125 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4053 11:55:53.429056 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4054 11:55:53.429639 ==
4055 11:55:53.432355 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 11:55:53.435407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 11:55:53.435885 ==
4058 11:55:53.436267 DQS Delay:
4059 11:55:53.439274 DQS0 = 0, DQS1 = 0
4060 11:55:53.439739 DQM Delay:
4061 11:55:53.443263 DQM0 = 51, DQM1 = 41
4062 11:55:53.443731 DQ Delay:
4063 11:55:53.445933 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4064 11:55:53.449135 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4065 11:55:53.452154 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4066 11:55:53.455779 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4067 11:55:53.456252
4068 11:55:53.456624
4069 11:55:53.456971 ==
4070 11:55:53.458880 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 11:55:53.462092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 11:55:53.465918 ==
4073 11:55:53.466533
4074 11:55:53.466906
4075 11:55:53.467246 TX Vref Scan disable
4076 11:55:53.468706 == TX Byte 0 ==
4077 11:55:53.472526 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4078 11:55:53.475883 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4079 11:55:53.478864 == TX Byte 1 ==
4080 11:55:53.482495 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4081 11:55:53.485588 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4082 11:55:53.486054 ==
4083 11:55:53.489447 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 11:55:53.496001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 11:55:53.496577 ==
4086 11:55:53.496951
4087 11:55:53.497293
4088 11:55:53.497624 TX Vref Scan disable
4089 11:55:53.500154 == TX Byte 0 ==
4090 11:55:53.503479 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4091 11:55:53.507302 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4092 11:55:53.510515 == TX Byte 1 ==
4093 11:55:53.513931 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4094 11:55:53.517293 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4095 11:55:53.520173
4096 11:55:53.520636 [DATLAT]
4097 11:55:53.521030 Freq=600, CH0 RK0
4098 11:55:53.521398
4099 11:55:53.523643 DATLAT Default: 0x9
4100 11:55:53.524105 0, 0xFFFF, sum = 0
4101 11:55:53.527425 1, 0xFFFF, sum = 0
4102 11:55:53.527895 2, 0xFFFF, sum = 0
4103 11:55:53.530567 3, 0xFFFF, sum = 0
4104 11:55:53.531042 4, 0xFFFF, sum = 0
4105 11:55:53.533669 5, 0xFFFF, sum = 0
4106 11:55:53.536890 6, 0xFFFF, sum = 0
4107 11:55:53.537369 7, 0xFFFF, sum = 0
4108 11:55:53.537749 8, 0x0, sum = 1
4109 11:55:53.540556 9, 0x0, sum = 2
4110 11:55:53.541137 10, 0x0, sum = 3
4111 11:55:53.543542 11, 0x0, sum = 4
4112 11:55:53.544121 best_step = 9
4113 11:55:53.544497
4114 11:55:53.544840 ==
4115 11:55:53.546683 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 11:55:53.553605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 11:55:53.554178 ==
4118 11:55:53.554622 RX Vref Scan: 1
4119 11:55:53.554982
4120 11:55:53.556594 RX Vref 0 -> 0, step: 1
4121 11:55:53.557078
4122 11:55:53.560024 RX Delay -179 -> 252, step: 8
4123 11:55:53.560516
4124 11:55:53.563207 Set Vref, RX VrefLevel [Byte0]: 58
4125 11:55:53.566658 [Byte1]: 52
4126 11:55:53.567131
4127 11:55:53.570479 Final RX Vref Byte 0 = 58 to rank0
4128 11:55:53.573055 Final RX Vref Byte 1 = 52 to rank0
4129 11:55:53.576488 Final RX Vref Byte 0 = 58 to rank1
4130 11:55:53.580036 Final RX Vref Byte 1 = 52 to rank1==
4131 11:55:53.583143 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 11:55:53.586709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 11:55:53.587182 ==
4134 11:55:53.589709 DQS Delay:
4135 11:55:53.590174 DQS0 = 0, DQS1 = 0
4136 11:55:53.593511 DQM Delay:
4137 11:55:53.594076 DQM0 = 49, DQM1 = 39
4138 11:55:53.594485 DQ Delay:
4139 11:55:53.596839 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4140 11:55:53.599793 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4141 11:55:53.603342 DQ8 =32, DQ9 =24, DQ10 =40, DQ11 =32
4142 11:55:53.607245 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4143 11:55:53.607716
4144 11:55:53.608085
4145 11:55:53.616658 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4146 11:55:53.619735 CH0 RK0: MR19=808, MR18=5751
4147 11:55:53.626501 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4148 11:55:53.627069
4149 11:55:53.629761 ----->DramcWriteLeveling(PI) begin...
4150 11:55:53.630334 ==
4151 11:55:53.632957 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 11:55:53.636381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:55:53.636966 ==
4154 11:55:53.639550 Write leveling (Byte 0): 33 => 33
4155 11:55:53.642886 Write leveling (Byte 1): 31 => 31
4156 11:55:53.646687 DramcWriteLeveling(PI) end<-----
4157 11:55:53.647253
4158 11:55:53.647630 ==
4159 11:55:53.649647 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 11:55:53.652960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 11:55:53.653536 ==
4162 11:55:53.656618 [Gating] SW mode calibration
4163 11:55:53.663059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4164 11:55:53.669560 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4165 11:55:53.672962 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 11:55:53.676590 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 11:55:53.683184 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 11:55:53.686511 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4169 11:55:53.689448 0 9 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
4170 11:55:53.696048 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 11:55:53.699536 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:55:53.703026 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 11:55:53.706847 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 11:55:53.712844 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 11:55:53.716899 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:55:53.719408 0 10 12 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
4177 11:55:53.726023 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4178 11:55:53.729335 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 11:55:53.732482 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:55:53.739326 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 11:55:53.742827 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 11:55:53.746042 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 11:55:53.753269 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:55:53.756648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:55:53.759235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:55:53.766181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:55:53.769298 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:55:53.772467 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:55:53.779276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:55:53.782500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:55:53.785922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:55:53.792571 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:55:53.795696 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:55:53.799444 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:55:53.805555 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:55:53.809134 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:55:53.812644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:55:53.819280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:55:53.822545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:55:53.825826 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4201 11:55:53.832342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:55:53.832899 Total UI for P1: 0, mck2ui 16
4203 11:55:53.835914 best dqsien dly found for B0: ( 0, 13, 12)
4204 11:55:53.838910 Total UI for P1: 0, mck2ui 16
4205 11:55:53.842204 best dqsien dly found for B1: ( 0, 13, 14)
4206 11:55:53.845809 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4207 11:55:53.852549 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4208 11:55:53.853116
4209 11:55:53.855695 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4210 11:55:53.858666 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4211 11:55:53.862529 [Gating] SW calibration Done
4212 11:55:53.863088 ==
4213 11:55:53.865570 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 11:55:53.869325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 11:55:53.869894 ==
4216 11:55:53.872256 RX Vref Scan: 0
4217 11:55:53.872822
4218 11:55:53.873202 RX Vref 0 -> 0, step: 1
4219 11:55:53.873552
4220 11:55:53.875703 RX Delay -230 -> 252, step: 16
4221 11:55:53.878765 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4222 11:55:53.886069 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4223 11:55:53.888869 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4224 11:55:53.892376 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4225 11:55:53.895805 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4226 11:55:53.898995 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4227 11:55:53.905326 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4228 11:55:53.908950 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4229 11:55:53.911916 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4230 11:55:53.915904 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4231 11:55:53.922128 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4232 11:55:53.925605 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4233 11:55:53.928957 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4234 11:55:53.931992 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4235 11:55:53.938686 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4236 11:55:53.942001 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4237 11:55:53.942517 ==
4238 11:55:53.945505 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 11:55:53.949028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 11:55:53.949599 ==
4241 11:55:53.952184 DQS Delay:
4242 11:55:53.952745 DQS0 = 0, DQS1 = 0
4243 11:55:53.953115 DQM Delay:
4244 11:55:53.955197 DQM0 = 49, DQM1 = 40
4245 11:55:53.955664 DQ Delay:
4246 11:55:53.958732 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4247 11:55:53.962842 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4248 11:55:53.965717 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4249 11:55:53.968858 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4250 11:55:53.969428
4251 11:55:53.969800
4252 11:55:53.970141 ==
4253 11:55:53.972133 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 11:55:53.978664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 11:55:53.979262 ==
4256 11:55:53.979652
4257 11:55:53.979996
4258 11:55:53.980322 TX Vref Scan disable
4259 11:55:53.982083 == TX Byte 0 ==
4260 11:55:53.985138 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4261 11:55:53.988827 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4262 11:55:53.992053 == TX Byte 1 ==
4263 11:55:53.995777 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4264 11:55:54.001941 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4265 11:55:54.002558 ==
4266 11:55:54.005138 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 11:55:54.008740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 11:55:54.009310 ==
4269 11:55:54.009693
4270 11:55:54.010037
4271 11:55:54.011847 TX Vref Scan disable
4272 11:55:54.015691 == TX Byte 0 ==
4273 11:55:54.018454 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4274 11:55:54.022082 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4275 11:55:54.024985 == TX Byte 1 ==
4276 11:55:54.028339 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4277 11:55:54.032110 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4278 11:55:54.032699
4279 11:55:54.033075 [DATLAT]
4280 11:55:54.035293 Freq=600, CH0 RK1
4281 11:55:54.035757
4282 11:55:54.036125 DATLAT Default: 0x9
4283 11:55:54.038439 0, 0xFFFF, sum = 0
4284 11:55:54.041649 1, 0xFFFF, sum = 0
4285 11:55:54.042122 2, 0xFFFF, sum = 0
4286 11:55:54.045179 3, 0xFFFF, sum = 0
4287 11:55:54.045752 4, 0xFFFF, sum = 0
4288 11:55:54.049143 5, 0xFFFF, sum = 0
4289 11:55:54.049719 6, 0xFFFF, sum = 0
4290 11:55:54.051945 7, 0xFFFF, sum = 0
4291 11:55:54.052516 8, 0x0, sum = 1
4292 11:55:54.054872 9, 0x0, sum = 2
4293 11:55:54.055335 10, 0x0, sum = 3
4294 11:55:54.055700 11, 0x0, sum = 4
4295 11:55:54.058310 best_step = 9
4296 11:55:54.058807
4297 11:55:54.059170 ==
4298 11:55:54.061355 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 11:55:54.065028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 11:55:54.065485 ==
4301 11:55:54.067994 RX Vref Scan: 0
4302 11:55:54.068446
4303 11:55:54.068806 RX Vref 0 -> 0, step: 1
4304 11:55:54.071535
4305 11:55:54.071987 RX Delay -179 -> 252, step: 8
4306 11:55:54.079178 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4307 11:55:54.082654 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4308 11:55:54.085896 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4309 11:55:54.089073 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4310 11:55:54.092234 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4311 11:55:54.099178 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4312 11:55:54.102219 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4313 11:55:54.105480 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4314 11:55:54.108987 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4315 11:55:54.113050 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4316 11:55:54.119178 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4317 11:55:54.122417 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4318 11:55:54.125578 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4319 11:55:54.129120 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4320 11:55:54.135279 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4321 11:55:54.139149 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4322 11:55:54.139712 ==
4323 11:55:54.142116 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 11:55:54.145668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 11:55:54.146225 ==
4326 11:55:54.149069 DQS Delay:
4327 11:55:54.149625 DQS0 = 0, DQS1 = 0
4328 11:55:54.149990 DQM Delay:
4329 11:55:54.152327 DQM0 = 47, DQM1 = 41
4330 11:55:54.152877 DQ Delay:
4331 11:55:54.156052 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4332 11:55:54.159067 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4333 11:55:54.162083 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4334 11:55:54.165439 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4335 11:55:54.165992
4336 11:55:54.166352
4337 11:55:54.175722 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4338 11:55:54.176283 CH0 RK1: MR19=808, MR18=5F2D
4339 11:55:54.182134 CH0_RK1: MR19=0x808, MR18=0x5F2D, DQSOSC=391, MR23=63, INC=171, DEC=114
4340 11:55:54.185889 [RxdqsGatingPostProcess] freq 600
4341 11:55:54.192276 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4342 11:55:54.195410 Pre-setting of DQS Precalculation
4343 11:55:54.198577 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4344 11:55:54.199125 ==
4345 11:55:54.201789 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 11:55:54.208906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 11:55:54.209464 ==
4348 11:55:54.212279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 11:55:54.218899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4350 11:55:54.222124 [CA 0] Center 35 (5~66) winsize 62
4351 11:55:54.225363 [CA 1] Center 35 (5~66) winsize 62
4352 11:55:54.228611 [CA 2] Center 34 (4~65) winsize 62
4353 11:55:54.231742 [CA 3] Center 34 (3~65) winsize 63
4354 11:55:54.235092 [CA 4] Center 34 (3~65) winsize 63
4355 11:55:54.238532 [CA 5] Center 33 (3~64) winsize 62
4356 11:55:54.239100
4357 11:55:54.241745 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4358 11:55:54.242354
4359 11:55:54.245384 [CATrainingPosCal] consider 1 rank data
4360 11:55:54.248537 u2DelayCellTimex100 = 270/100 ps
4361 11:55:54.251937 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 11:55:54.255712 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 11:55:54.262076 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 11:55:54.266091 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4365 11:55:54.268703 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4366 11:55:54.271993 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4367 11:55:54.272563
4368 11:55:54.275372 CA PerBit enable=1, Macro0, CA PI delay=33
4369 11:55:54.275942
4370 11:55:54.279066 [CBTSetCACLKResult] CA Dly = 33
4371 11:55:54.279634 CS Dly: 4 (0~35)
4372 11:55:54.280006 ==
4373 11:55:54.281842 Dram Type= 6, Freq= 0, CH_1, rank 1
4374 11:55:54.289009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 11:55:54.289585 ==
4376 11:55:54.292220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 11:55:54.298553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4378 11:55:54.301945 [CA 0] Center 35 (5~66) winsize 62
4379 11:55:54.305006 [CA 1] Center 35 (5~66) winsize 62
4380 11:55:54.308950 [CA 2] Center 34 (4~65) winsize 62
4381 11:55:54.312225 [CA 3] Center 34 (4~65) winsize 62
4382 11:55:54.315360 [CA 4] Center 34 (4~65) winsize 62
4383 11:55:54.318844 [CA 5] Center 34 (3~65) winsize 63
4384 11:55:54.319405
4385 11:55:54.321777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4386 11:55:54.322335
4387 11:55:54.325945 [CATrainingPosCal] consider 2 rank data
4388 11:55:54.328855 u2DelayCellTimex100 = 270/100 ps
4389 11:55:54.331967 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 11:55:54.335090 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4391 11:55:54.341613 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 11:55:54.345062 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 11:55:54.348692 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 11:55:54.352175 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 11:55:54.352743
4396 11:55:54.355221 CA PerBit enable=1, Macro0, CA PI delay=33
4397 11:55:54.355689
4398 11:55:54.358638 [CBTSetCACLKResult] CA Dly = 33
4399 11:55:54.359204 CS Dly: 4 (0~36)
4400 11:55:54.359580
4401 11:55:54.361753 ----->DramcWriteLeveling(PI) begin...
4402 11:55:54.365212 ==
4403 11:55:54.368664 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 11:55:54.371779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:55:54.372350 ==
4406 11:55:54.375707 Write leveling (Byte 0): 30 => 30
4407 11:55:54.378463 Write leveling (Byte 1): 29 => 29
4408 11:55:54.382034 DramcWriteLeveling(PI) end<-----
4409 11:55:54.382629
4410 11:55:54.383002 ==
4411 11:55:54.385238 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 11:55:54.388527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 11:55:54.389097 ==
4414 11:55:54.391864 [Gating] SW mode calibration
4415 11:55:54.398351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 11:55:54.401860 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4417 11:55:54.408350 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 11:55:54.411762 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 11:55:54.415010 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
4420 11:55:54.421585 0 9 12 | B1->B0 | 2b2b 2727 | 1 0 | (1 1) (1 0)
4421 11:55:54.424984 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:55:54.428316 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:55:54.435032 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:55:54.438499 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:55:54.441532 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:55:54.448881 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:55:54.451921 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4428 11:55:54.455212 0 10 12 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
4429 11:55:54.461682 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:55:54.464960 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:55:54.468217 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:55:54.475004 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:55:54.478256 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:55:54.481432 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:55:54.487881 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:55:54.491674 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4437 11:55:54.495128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:55:54.501568 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:55:54.504394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:55:54.507944 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:55:54.514607 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:55:54.518313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:55:54.521290 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:55:54.527648 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:55:54.530906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:55:54.534409 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:55:54.541294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:55:54.544422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:55:54.548039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:55:54.550861 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:55:54.557663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:55:54.560906 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 11:55:54.564409 Total UI for P1: 0, mck2ui 16
4454 11:55:54.567904 best dqsien dly found for B0: ( 0, 13, 10)
4455 11:55:54.571264 Total UI for P1: 0, mck2ui 16
4456 11:55:54.574430 best dqsien dly found for B1: ( 0, 13, 10)
4457 11:55:54.577581 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4458 11:55:54.581661 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4459 11:55:54.582238
4460 11:55:54.584113 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 11:55:54.591294 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4462 11:55:54.591867 [Gating] SW calibration Done
4463 11:55:54.592247 ==
4464 11:55:54.594011 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 11:55:54.601239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 11:55:54.601819 ==
4467 11:55:54.602200 RX Vref Scan: 0
4468 11:55:54.602594
4469 11:55:54.603797 RX Vref 0 -> 0, step: 1
4470 11:55:54.604266
4471 11:55:54.607253 RX Delay -230 -> 252, step: 16
4472 11:55:54.610577 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4473 11:55:54.614265 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 11:55:54.617345 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 11:55:54.624039 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4476 11:55:54.627439 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4477 11:55:54.630931 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4478 11:55:54.633766 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 11:55:54.640292 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4480 11:55:54.643611 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4481 11:55:54.646997 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 11:55:54.650645 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4483 11:55:54.657267 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 11:55:54.660433 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 11:55:54.663926 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 11:55:54.667624 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4487 11:55:54.673875 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4488 11:55:54.674494 ==
4489 11:55:54.677199 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 11:55:54.680609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 11:55:54.681177 ==
4492 11:55:54.681555 DQS Delay:
4493 11:55:54.683639 DQS0 = 0, DQS1 = 0
4494 11:55:54.684204 DQM Delay:
4495 11:55:54.687034 DQM0 = 46, DQM1 = 44
4496 11:55:54.687602 DQ Delay:
4497 11:55:54.690622 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4498 11:55:54.693621 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4499 11:55:54.697207 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4500 11:55:54.700570 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4501 11:55:54.701131
4502 11:55:54.701501
4503 11:55:54.701840 ==
4504 11:55:54.703661 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 11:55:54.707003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 11:55:54.707574 ==
4507 11:55:54.707950
4508 11:55:54.708292
4509 11:55:54.710107 TX Vref Scan disable
4510 11:55:54.713585 == TX Byte 0 ==
4511 11:55:54.716790 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4512 11:55:54.720144 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4513 11:55:54.723381 == TX Byte 1 ==
4514 11:55:54.726841 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4515 11:55:54.730247 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4516 11:55:54.730855 ==
4517 11:55:54.733163 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 11:55:54.740007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 11:55:54.740484 ==
4520 11:55:54.740859
4521 11:55:54.741206
4522 11:55:54.741534 TX Vref Scan disable
4523 11:55:54.744232 == TX Byte 0 ==
4524 11:55:54.747845 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 11:55:54.753964 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 11:55:54.754722 == TX Byte 1 ==
4527 11:55:54.757405 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4528 11:55:54.764084 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4529 11:55:54.764600
4530 11:55:54.765238 [DATLAT]
4531 11:55:54.765701 Freq=600, CH1 RK0
4532 11:55:54.766147
4533 11:55:54.767323 DATLAT Default: 0x9
4534 11:55:54.767835 0, 0xFFFF, sum = 0
4535 11:55:54.770551 1, 0xFFFF, sum = 0
4536 11:55:54.771056 2, 0xFFFF, sum = 0
4537 11:55:54.774069 3, 0xFFFF, sum = 0
4538 11:55:54.777683 4, 0xFFFF, sum = 0
4539 11:55:54.778171 5, 0xFFFF, sum = 0
4540 11:55:54.781000 6, 0xFFFF, sum = 0
4541 11:55:54.781587 7, 0xFFFF, sum = 0
4542 11:55:54.784072 8, 0x0, sum = 1
4543 11:55:54.784662 9, 0x0, sum = 2
4544 11:55:54.785162 10, 0x0, sum = 3
4545 11:55:54.787530 11, 0x0, sum = 4
4546 11:55:54.788016 best_step = 9
4547 11:55:54.788497
4548 11:55:54.788948 ==
4549 11:55:54.790952 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 11:55:54.797577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 11:55:54.798165 ==
4552 11:55:54.798700 RX Vref Scan: 1
4553 11:55:54.799153
4554 11:55:54.800399 RX Vref 0 -> 0, step: 1
4555 11:55:54.800876
4556 11:55:54.803950 RX Delay -179 -> 252, step: 8
4557 11:55:54.804429
4558 11:55:54.807099 Set Vref, RX VrefLevel [Byte0]: 53
4559 11:55:54.810761 [Byte1]: 58
4560 11:55:54.811338
4561 11:55:54.814719 Final RX Vref Byte 0 = 53 to rank0
4562 11:55:54.817512 Final RX Vref Byte 1 = 58 to rank0
4563 11:55:54.820669 Final RX Vref Byte 0 = 53 to rank1
4564 11:55:54.824053 Final RX Vref Byte 1 = 58 to rank1==
4565 11:55:54.827285 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 11:55:54.830728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 11:55:54.831308 ==
4568 11:55:54.834126 DQS Delay:
4569 11:55:54.834775 DQS0 = 0, DQS1 = 0
4570 11:55:54.835163 DQM Delay:
4571 11:55:54.837333 DQM0 = 45, DQM1 = 37
4572 11:55:54.837901 DQ Delay:
4573 11:55:54.840799 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =44
4574 11:55:54.844055 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4575 11:55:54.847558 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4576 11:55:54.850974 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =44
4577 11:55:54.851471
4578 11:55:54.851843
4579 11:55:54.860816 [DQSOSCAuto] RK0, (LSB)MR18= 0x476e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4580 11:55:54.864113 CH1 RK0: MR19=808, MR18=476E
4581 11:55:54.867385 CH1_RK0: MR19=0x808, MR18=0x476E, DQSOSC=389, MR23=63, INC=173, DEC=115
4582 11:55:54.867860
4583 11:55:54.870419 ----->DramcWriteLeveling(PI) begin...
4584 11:55:54.873898 ==
4585 11:55:54.877303 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 11:55:54.880870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 11:55:54.881453 ==
4588 11:55:54.884099 Write leveling (Byte 0): 30 => 30
4589 11:55:54.887550 Write leveling (Byte 1): 31 => 31
4590 11:55:54.890985 DramcWriteLeveling(PI) end<-----
4591 11:55:54.891549
4592 11:55:54.891925 ==
4593 11:55:54.894279 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 11:55:54.897531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 11:55:54.898098 ==
4596 11:55:54.901152 [Gating] SW mode calibration
4597 11:55:54.907686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 11:55:54.911689 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 11:55:54.917811 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 11:55:54.920670 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 11:55:54.924140 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4602 11:55:54.931172 0 9 12 | B1->B0 | 2323 2f2f | 0 1 | (1 0) (1 1)
4603 11:55:54.934087 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 11:55:54.937201 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 11:55:54.943784 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:55:54.947031 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 11:55:54.950285 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:55:54.956863 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:55:54.960056 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (1 1) (0 0)
4610 11:55:54.963433 0 10 12 | B1->B0 | 3d3d 3333 | 0 0 | (0 0) (0 0)
4611 11:55:54.970572 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 11:55:54.973679 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 11:55:54.977004 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:55:54.983570 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 11:55:54.986838 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:55:54.990090 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:55:54.997184 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:55:55.000133 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4619 11:55:55.003226 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:55:55.010070 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:55:55.013328 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:55:55.016854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:55:55.023233 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:55:55.026729 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:55:55.029822 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:55:55.036240 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:55:55.039637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:55:55.042848 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:55:55.049611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:55:55.052941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:55:55.055967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:55:55.062662 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:55:55.065957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4634 11:55:55.069614 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:55:55.072782 Total UI for P1: 0, mck2ui 16
4636 11:55:55.075954 best dqsien dly found for B0: ( 0, 13, 8)
4637 11:55:55.079499 Total UI for P1: 0, mck2ui 16
4638 11:55:55.082835 best dqsien dly found for B1: ( 0, 13, 10)
4639 11:55:55.086125 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4640 11:55:55.089537 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4641 11:55:55.090105
4642 11:55:55.092856 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4643 11:55:55.099001 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4644 11:55:55.099552 [Gating] SW calibration Done
4645 11:55:55.102762 ==
4646 11:55:55.103326 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 11:55:55.109296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 11:55:55.109882 ==
4649 11:55:55.110267 RX Vref Scan: 0
4650 11:55:55.110685
4651 11:55:55.112382 RX Vref 0 -> 0, step: 1
4652 11:55:55.112852
4653 11:55:55.115932 RX Delay -230 -> 252, step: 16
4654 11:55:55.119426 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4655 11:55:55.122517 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4656 11:55:55.129239 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4657 11:55:55.132671 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4658 11:55:55.136237 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4659 11:55:55.139142 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4660 11:55:55.142693 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4661 11:55:55.149046 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4662 11:55:55.152770 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4663 11:55:55.155532 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4664 11:55:55.159374 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4665 11:55:55.162325 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4666 11:55:55.168960 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4667 11:55:55.172361 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4668 11:55:55.175585 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4669 11:55:55.178790 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4670 11:55:55.182276 ==
4671 11:55:55.185857 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 11:55:55.189193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 11:55:55.189678 ==
4674 11:55:55.190157 DQS Delay:
4675 11:55:55.193155 DQS0 = 0, DQS1 = 0
4676 11:55:55.193739 DQM Delay:
4677 11:55:55.195507 DQM0 = 50, DQM1 = 45
4678 11:55:55.195990 DQ Delay:
4679 11:55:55.198786 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4680 11:55:55.202046 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4681 11:55:55.206002 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4682 11:55:55.208904 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4683 11:55:55.209388
4684 11:55:55.209870
4685 11:55:55.210327 ==
4686 11:55:55.212479 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 11:55:55.215635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 11:55:55.216217 ==
4689 11:55:55.216709
4690 11:55:55.217188
4691 11:55:55.218809 TX Vref Scan disable
4692 11:55:55.222922 == TX Byte 0 ==
4693 11:55:55.225989 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4694 11:55:55.229103 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4695 11:55:55.233305 == TX Byte 1 ==
4696 11:55:55.235518 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4697 11:55:55.239082 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4698 11:55:55.239552 ==
4699 11:55:55.242615 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 11:55:55.245480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 11:55:55.248731 ==
4702 11:55:55.249209
4703 11:55:55.249586
4704 11:55:55.249936 TX Vref Scan disable
4705 11:55:55.253086 == TX Byte 0 ==
4706 11:55:55.256143 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 11:55:55.263172 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 11:55:55.263752 == TX Byte 1 ==
4709 11:55:55.266153 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4710 11:55:55.272908 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4711 11:55:55.273491
4712 11:55:55.273866 [DATLAT]
4713 11:55:55.274212 Freq=600, CH1 RK1
4714 11:55:55.274613
4715 11:55:55.276816 DATLAT Default: 0x9
4716 11:55:55.277393 0, 0xFFFF, sum = 0
4717 11:55:55.279729 1, 0xFFFF, sum = 0
4718 11:55:55.280212 2, 0xFFFF, sum = 0
4719 11:55:55.282722 3, 0xFFFF, sum = 0
4720 11:55:55.286711 4, 0xFFFF, sum = 0
4721 11:55:55.287291 5, 0xFFFF, sum = 0
4722 11:55:55.289121 6, 0xFFFF, sum = 0
4723 11:55:55.289595 7, 0xFFFF, sum = 0
4724 11:55:55.292739 8, 0x0, sum = 1
4725 11:55:55.293319 9, 0x0, sum = 2
4726 11:55:55.293705 10, 0x0, sum = 3
4727 11:55:55.295862 11, 0x0, sum = 4
4728 11:55:55.296342 best_step = 9
4729 11:55:55.296717
4730 11:55:55.297060 ==
4731 11:55:55.299811 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 11:55:55.306272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 11:55:55.307015 ==
4734 11:55:55.307413 RX Vref Scan: 0
4735 11:55:55.307764
4736 11:55:55.309581 RX Vref 0 -> 0, step: 1
4737 11:55:55.310150
4738 11:55:55.312737 RX Delay -179 -> 252, step: 8
4739 11:55:55.315866 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4740 11:55:55.322717 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4741 11:55:55.325631 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4742 11:55:55.329229 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4743 11:55:55.332687 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4744 11:55:55.335776 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4745 11:55:55.342358 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4746 11:55:55.345917 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4747 11:55:55.349034 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4748 11:55:55.352587 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4749 11:55:55.355985 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4750 11:55:55.362886 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4751 11:55:55.365955 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4752 11:55:55.369676 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4753 11:55:55.372642 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4754 11:55:55.379008 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4755 11:55:55.379575 ==
4756 11:55:55.382466 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 11:55:55.385807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 11:55:55.386425 ==
4759 11:55:55.386818 DQS Delay:
4760 11:55:55.389247 DQS0 = 0, DQS1 = 0
4761 11:55:55.389814 DQM Delay:
4762 11:55:55.392466 DQM0 = 46, DQM1 = 40
4763 11:55:55.393036 DQ Delay:
4764 11:55:55.395976 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4765 11:55:55.399127 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4766 11:55:55.402521 DQ8 =24, DQ9 =32, DQ10 =40, DQ11 =36
4767 11:55:55.405565 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =52
4768 11:55:55.406034
4769 11:55:55.406440
4770 11:55:55.412498 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4771 11:55:55.416045 CH1 RK1: MR19=808, MR18=5D23
4772 11:55:55.422089 CH1_RK1: MR19=0x808, MR18=0x5D23, DQSOSC=392, MR23=63, INC=170, DEC=113
4773 11:55:55.425824 [RxdqsGatingPostProcess] freq 600
4774 11:55:55.432386 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4775 11:55:55.435595 Pre-setting of DQS Precalculation
4776 11:55:55.438971 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4777 11:55:55.445497 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4778 11:55:55.452498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4779 11:55:55.453154
4780 11:55:55.453618
4781 11:55:55.455664 [Calibration Summary] 1200 Mbps
4782 11:55:55.458692 CH 0, Rank 0
4783 11:55:55.459156 SW Impedance : PASS
4784 11:55:55.462448 DUTY Scan : NO K
4785 11:55:55.465589 ZQ Calibration : PASS
4786 11:55:55.466151 Jitter Meter : NO K
4787 11:55:55.468916 CBT Training : PASS
4788 11:55:55.472540 Write leveling : PASS
4789 11:55:55.473109 RX DQS gating : PASS
4790 11:55:55.475577 RX DQ/DQS(RDDQC) : PASS
4791 11:55:55.476143 TX DQ/DQS : PASS
4792 11:55:55.478606 RX DATLAT : PASS
4793 11:55:55.482064 RX DQ/DQS(Engine): PASS
4794 11:55:55.482688 TX OE : NO K
4795 11:55:55.485190 All Pass.
4796 11:55:55.485655
4797 11:55:55.486023 CH 0, Rank 1
4798 11:55:55.488838 SW Impedance : PASS
4799 11:55:55.489410 DUTY Scan : NO K
4800 11:55:55.491910 ZQ Calibration : PASS
4801 11:55:55.495645 Jitter Meter : NO K
4802 11:55:55.496211 CBT Training : PASS
4803 11:55:55.498943 Write leveling : PASS
4804 11:55:55.501960 RX DQS gating : PASS
4805 11:55:55.502570 RX DQ/DQS(RDDQC) : PASS
4806 11:55:55.505165 TX DQ/DQS : PASS
4807 11:55:55.508364 RX DATLAT : PASS
4808 11:55:55.508832 RX DQ/DQS(Engine): PASS
4809 11:55:55.511672 TX OE : NO K
4810 11:55:55.512137 All Pass.
4811 11:55:55.512509
4812 11:55:55.515208 CH 1, Rank 0
4813 11:55:55.515774 SW Impedance : PASS
4814 11:55:55.518267 DUTY Scan : NO K
4815 11:55:55.521896 ZQ Calibration : PASS
4816 11:55:55.522497 Jitter Meter : NO K
4817 11:55:55.525157 CBT Training : PASS
4818 11:55:55.528150 Write leveling : PASS
4819 11:55:55.528618 RX DQS gating : PASS
4820 11:55:55.532112 RX DQ/DQS(RDDQC) : PASS
4821 11:55:55.535313 TX DQ/DQS : PASS
4822 11:55:55.535876 RX DATLAT : PASS
4823 11:55:55.538103 RX DQ/DQS(Engine): PASS
4824 11:55:55.538629 TX OE : NO K
4825 11:55:55.541746 All Pass.
4826 11:55:55.542453
4827 11:55:55.542854 CH 1, Rank 1
4828 11:55:55.545106 SW Impedance : PASS
4829 11:55:55.545583 DUTY Scan : NO K
4830 11:55:55.548026 ZQ Calibration : PASS
4831 11:55:55.551820 Jitter Meter : NO K
4832 11:55:55.552397 CBT Training : PASS
4833 11:55:55.554838 Write leveling : PASS
4834 11:55:55.558550 RX DQS gating : PASS
4835 11:55:55.559123 RX DQ/DQS(RDDQC) : PASS
4836 11:55:55.562050 TX DQ/DQS : PASS
4837 11:55:55.564985 RX DATLAT : PASS
4838 11:55:55.565553 RX DQ/DQS(Engine): PASS
4839 11:55:55.568505 TX OE : NO K
4840 11:55:55.569073 All Pass.
4841 11:55:55.569447
4842 11:55:55.571544 DramC Write-DBI off
4843 11:55:55.574608 PER_BANK_REFRESH: Hybrid Mode
4844 11:55:55.575077 TX_TRACKING: ON
4845 11:55:55.585072 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4846 11:55:55.588554 [FAST_K] Save calibration result to emmc
4847 11:55:55.591241 dramc_set_vcore_voltage set vcore to 662500
4848 11:55:55.594557 Read voltage for 933, 3
4849 11:55:55.595026 Vio18 = 0
4850 11:55:55.595396 Vcore = 662500
4851 11:55:55.598124 Vdram = 0
4852 11:55:55.598722 Vddq = 0
4853 11:55:55.599097 Vmddr = 0
4854 11:55:55.605370 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4855 11:55:55.607972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4856 11:55:55.611620 MEM_TYPE=3, freq_sel=17
4857 11:55:55.614932 sv_algorithm_assistance_LP4_1600
4858 11:55:55.618413 ============ PULL DRAM RESETB DOWN ============
4859 11:55:55.621438 ========== PULL DRAM RESETB DOWN end =========
4860 11:55:55.628352 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 11:55:55.631384 ===================================
4862 11:55:55.631857 LPDDR4 DRAM CONFIGURATION
4863 11:55:55.634537 ===================================
4864 11:55:55.638115 EX_ROW_EN[0] = 0x0
4865 11:55:55.641440 EX_ROW_EN[1] = 0x0
4866 11:55:55.642003 LP4Y_EN = 0x0
4867 11:55:55.644661 WORK_FSP = 0x0
4868 11:55:55.645245 WL = 0x3
4869 11:55:55.647658 RL = 0x3
4870 11:55:55.648124 BL = 0x2
4871 11:55:55.651038 RPST = 0x0
4872 11:55:55.651500 RD_PRE = 0x0
4873 11:55:55.654754 WR_PRE = 0x1
4874 11:55:55.655322 WR_PST = 0x0
4875 11:55:55.657905 DBI_WR = 0x0
4876 11:55:55.658371 DBI_RD = 0x0
4877 11:55:55.661164 OTF = 0x1
4878 11:55:55.664716 ===================================
4879 11:55:55.667853 ===================================
4880 11:55:55.668422 ANA top config
4881 11:55:55.671263 ===================================
4882 11:55:55.674819 DLL_ASYNC_EN = 0
4883 11:55:55.677853 ALL_SLAVE_EN = 1
4884 11:55:55.681580 NEW_RANK_MODE = 1
4885 11:55:55.682151 DLL_IDLE_MODE = 1
4886 11:55:55.684962 LP45_APHY_COMB_EN = 1
4887 11:55:55.687944 TX_ODT_DIS = 1
4888 11:55:55.691282 NEW_8X_MODE = 1
4889 11:55:55.694769 ===================================
4890 11:55:55.697838 ===================================
4891 11:55:55.698447 data_rate = 1866
4892 11:55:55.701099 CKR = 1
4893 11:55:55.704726 DQ_P2S_RATIO = 8
4894 11:55:55.708015 ===================================
4895 11:55:55.711004 CA_P2S_RATIO = 8
4896 11:55:55.714322 DQ_CA_OPEN = 0
4897 11:55:55.717823 DQ_SEMI_OPEN = 0
4898 11:55:55.718298 CA_SEMI_OPEN = 0
4899 11:55:55.721028 CA_FULL_RATE = 0
4900 11:55:55.724337 DQ_CKDIV4_EN = 1
4901 11:55:55.727588 CA_CKDIV4_EN = 1
4902 11:55:55.731099 CA_PREDIV_EN = 0
4903 11:55:55.734586 PH8_DLY = 0
4904 11:55:55.735174 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4905 11:55:55.738145 DQ_AAMCK_DIV = 4
4906 11:55:55.741152 CA_AAMCK_DIV = 4
4907 11:55:55.744398 CA_ADMCK_DIV = 4
4908 11:55:55.747458 DQ_TRACK_CA_EN = 0
4909 11:55:55.751197 CA_PICK = 933
4910 11:55:55.754148 CA_MCKIO = 933
4911 11:55:55.754649 MCKIO_SEMI = 0
4912 11:55:55.757845 PLL_FREQ = 3732
4913 11:55:55.760865 DQ_UI_PI_RATIO = 32
4914 11:55:55.764302 CA_UI_PI_RATIO = 0
4915 11:55:55.767598 ===================================
4916 11:55:55.771115 ===================================
4917 11:55:55.774180 memory_type:LPDDR4
4918 11:55:55.774789 GP_NUM : 10
4919 11:55:55.777509 SRAM_EN : 1
4920 11:55:55.780989 MD32_EN : 0
4921 11:55:55.783826 ===================================
4922 11:55:55.784295 [ANA_INIT] >>>>>>>>>>>>>>
4923 11:55:55.787183 <<<<<< [CONFIGURE PHASE]: ANA_TX
4924 11:55:55.790272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4925 11:55:55.793544 ===================================
4926 11:55:55.797282 data_rate = 1866,PCW = 0X8f00
4927 11:55:55.800352 ===================================
4928 11:55:55.803493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4929 11:55:55.810321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 11:55:55.817169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 11:55:55.820130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4932 11:55:55.823486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4933 11:55:55.826880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4934 11:55:55.827332 [ANA_INIT] flow start
4935 11:55:55.830352 [ANA_INIT] PLL >>>>>>>>
4936 11:55:55.833507 [ANA_INIT] PLL <<<<<<<<
4937 11:55:55.836823 [ANA_INIT] MIDPI >>>>>>>>
4938 11:55:55.837357 [ANA_INIT] MIDPI <<<<<<<<
4939 11:55:55.840163 [ANA_INIT] DLL >>>>>>>>
4940 11:55:55.843213 [ANA_INIT] flow end
4941 11:55:55.846589 ============ LP4 DIFF to SE enter ============
4942 11:55:55.850071 ============ LP4 DIFF to SE exit ============
4943 11:55:55.853648 [ANA_INIT] <<<<<<<<<<<<<
4944 11:55:55.857082 [Flow] Enable top DCM control >>>>>
4945 11:55:55.860717 [Flow] Enable top DCM control <<<<<
4946 11:55:55.863620 Enable DLL master slave shuffle
4947 11:55:55.866873 ==============================================================
4948 11:55:55.870303 Gating Mode config
4949 11:55:55.873759 ==============================================================
4950 11:55:55.877315 Config description:
4951 11:55:55.887280 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4952 11:55:55.893428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4953 11:55:55.897430 SELPH_MODE 0: By rank 1: By Phase
4954 11:55:55.904207 ==============================================================
4955 11:55:55.906714 GAT_TRACK_EN = 1
4956 11:55:55.910044 RX_GATING_MODE = 2
4957 11:55:55.913270 RX_GATING_TRACK_MODE = 2
4958 11:55:55.917018 SELPH_MODE = 1
4959 11:55:55.917595 PICG_EARLY_EN = 1
4960 11:55:55.919998 VALID_LAT_VALUE = 1
4961 11:55:55.927058 ==============================================================
4962 11:55:55.930049 Enter into Gating configuration >>>>
4963 11:55:55.933180 Exit from Gating configuration <<<<
4964 11:55:55.936728 Enter into DVFS_PRE_config >>>>>
4965 11:55:55.946766 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4966 11:55:55.950023 Exit from DVFS_PRE_config <<<<<
4967 11:55:55.953445 Enter into PICG configuration >>>>
4968 11:55:55.956857 Exit from PICG configuration <<<<
4969 11:55:55.960019 [RX_INPUT] configuration >>>>>
4970 11:55:55.963162 [RX_INPUT] configuration <<<<<
4971 11:55:55.966820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4972 11:55:55.974102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4973 11:55:55.980176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 11:55:55.986837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 11:55:55.993339 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 11:55:55.996747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 11:55:56.003379 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4978 11:55:56.006752 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4979 11:55:56.009758 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4980 11:55:56.013279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4981 11:55:56.019839 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4982 11:55:56.023235 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 11:55:56.026338 ===================================
4984 11:55:56.029503 LPDDR4 DRAM CONFIGURATION
4985 11:55:56.033171 ===================================
4986 11:55:56.033740 EX_ROW_EN[0] = 0x0
4987 11:55:56.036449 EX_ROW_EN[1] = 0x0
4988 11:55:56.036918 LP4Y_EN = 0x0
4989 11:55:56.039776 WORK_FSP = 0x0
4990 11:55:56.040243 WL = 0x3
4991 11:55:56.043376 RL = 0x3
4992 11:55:56.043939 BL = 0x2
4993 11:55:56.046367 RPST = 0x0
4994 11:55:56.046873 RD_PRE = 0x0
4995 11:55:56.049584 WR_PRE = 0x1
4996 11:55:56.050306 WR_PST = 0x0
4997 11:55:56.052977 DBI_WR = 0x0
4998 11:55:56.056302 DBI_RD = 0x0
4999 11:55:56.056775 OTF = 0x1
5000 11:55:56.059824 ===================================
5001 11:55:56.063000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5002 11:55:56.066843 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5003 11:55:56.073489 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 11:55:56.076976 ===================================
5005 11:55:56.080016 LPDDR4 DRAM CONFIGURATION
5006 11:55:56.080582 ===================================
5007 11:55:56.083695 EX_ROW_EN[0] = 0x10
5008 11:55:56.086627 EX_ROW_EN[1] = 0x0
5009 11:55:56.087186 LP4Y_EN = 0x0
5010 11:55:56.089720 WORK_FSP = 0x0
5011 11:55:56.090282 WL = 0x3
5012 11:55:56.093147 RL = 0x3
5013 11:55:56.093711 BL = 0x2
5014 11:55:56.096583 RPST = 0x0
5015 11:55:56.097055 RD_PRE = 0x0
5016 11:55:56.100091 WR_PRE = 0x1
5017 11:55:56.100659 WR_PST = 0x0
5018 11:55:56.103276 DBI_WR = 0x0
5019 11:55:56.103843 DBI_RD = 0x0
5020 11:55:56.106278 OTF = 0x1
5021 11:55:56.109677 ===================================
5022 11:55:56.116374 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5023 11:55:56.119397 nWR fixed to 30
5024 11:55:56.123022 [ModeRegInit_LP4] CH0 RK0
5025 11:55:56.123586 [ModeRegInit_LP4] CH0 RK1
5026 11:55:56.126183 [ModeRegInit_LP4] CH1 RK0
5027 11:55:56.129878 [ModeRegInit_LP4] CH1 RK1
5028 11:55:56.130488 match AC timing 9
5029 11:55:56.135924 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5030 11:55:56.139337 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5031 11:55:56.142597 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5032 11:55:56.149230 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5033 11:55:56.152453 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5034 11:55:56.152949 ==
5035 11:55:56.156339 Dram Type= 6, Freq= 0, CH_0, rank 0
5036 11:55:56.159394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5037 11:55:56.159871 ==
5038 11:55:56.165672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5039 11:55:56.172653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5040 11:55:56.176551 [CA 0] Center 38 (7~69) winsize 63
5041 11:55:56.179052 [CA 1] Center 38 (8~69) winsize 62
5042 11:55:56.182310 [CA 2] Center 35 (5~66) winsize 62
5043 11:55:56.185825 [CA 3] Center 35 (5~66) winsize 62
5044 11:55:56.189176 [CA 4] Center 34 (4~65) winsize 62
5045 11:55:56.192421 [CA 5] Center 33 (3~64) winsize 62
5046 11:55:56.192988
5047 11:55:56.195320 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5048 11:55:56.195797
5049 11:55:56.199096 [CATrainingPosCal] consider 1 rank data
5050 11:55:56.202168 u2DelayCellTimex100 = 270/100 ps
5051 11:55:56.205586 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5052 11:55:56.208535 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5053 11:55:56.212414 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5054 11:55:56.215540 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5055 11:55:56.219153 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 11:55:56.225718 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5057 11:55:56.226288
5058 11:55:56.229054 CA PerBit enable=1, Macro0, CA PI delay=33
5059 11:55:56.229624
5060 11:55:56.232331 [CBTSetCACLKResult] CA Dly = 33
5061 11:55:56.232901 CS Dly: 6 (0~37)
5062 11:55:56.233282 ==
5063 11:55:56.235214 Dram Type= 6, Freq= 0, CH_0, rank 1
5064 11:55:56.238767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 11:55:56.242090 ==
5066 11:55:56.245722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 11:55:56.252539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5068 11:55:56.255462 [CA 0] Center 38 (8~69) winsize 62
5069 11:55:56.258748 [CA 1] Center 38 (8~69) winsize 62
5070 11:55:56.262323 [CA 2] Center 36 (6~66) winsize 61
5071 11:55:56.265591 [CA 3] Center 35 (5~66) winsize 62
5072 11:55:56.268776 [CA 4] Center 34 (4~65) winsize 62
5073 11:55:56.272312 [CA 5] Center 34 (4~64) winsize 61
5074 11:55:56.272880
5075 11:55:56.275119 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5076 11:55:56.275586
5077 11:55:56.278473 [CATrainingPosCal] consider 2 rank data
5078 11:55:56.282084 u2DelayCellTimex100 = 270/100 ps
5079 11:55:56.285433 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 11:55:56.288578 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5081 11:55:56.292104 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5082 11:55:56.295067 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5083 11:55:56.301971 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5084 11:55:56.305269 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 11:55:56.305832
5086 11:55:56.308693 CA PerBit enable=1, Macro0, CA PI delay=34
5087 11:55:56.309161
5088 11:55:56.312202 [CBTSetCACLKResult] CA Dly = 34
5089 11:55:56.312772 CS Dly: 7 (0~39)
5090 11:55:56.313145
5091 11:55:56.315955 ----->DramcWriteLeveling(PI) begin...
5092 11:55:56.316530 ==
5093 11:55:56.319114 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 11:55:56.325348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 11:55:56.325915 ==
5096 11:55:56.328638 Write leveling (Byte 0): 33 => 33
5097 11:55:56.331730 Write leveling (Byte 1): 27 => 27
5098 11:55:56.332199 DramcWriteLeveling(PI) end<-----
5099 11:55:56.332567
5100 11:55:56.335304 ==
5101 11:55:56.338648 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 11:55:56.341676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 11:55:56.342145 ==
5104 11:55:56.344887 [Gating] SW mode calibration
5105 11:55:56.351728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5106 11:55:56.355095 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5107 11:55:56.361792 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5108 11:55:56.365150 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 11:55:56.368518 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 11:55:56.374916 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 11:55:56.378684 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 11:55:56.382367 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:55:56.388397 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5114 11:55:56.391920 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5115 11:55:56.395316 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5116 11:55:56.402501 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 11:55:56.405174 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 11:55:56.408570 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 11:55:56.411728 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:55:56.418423 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:55:56.422100 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5122 11:55:56.425388 0 15 28 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
5123 11:55:56.431689 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5124 11:55:56.435024 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:55:56.438362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 11:55:56.444573 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 11:55:56.448516 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:55:56.451565 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:55:56.458573 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 11:55:56.461343 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 11:55:56.464700 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 11:55:56.471238 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 11:55:56.474812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:55:56.478533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:55:56.484619 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:55:56.487994 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:55:56.491333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:55:56.498513 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:55:56.501585 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:55:56.504790 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:55:56.511135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:55:56.514902 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:55:56.518192 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:55:56.524930 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:55:56.528435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5146 11:55:56.531406 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 11:55:56.537758 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5148 11:55:56.538315 Total UI for P1: 0, mck2ui 16
5149 11:55:56.541106 best dqsien dly found for B0: ( 1, 2, 26)
5150 11:55:56.548063 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 11:55:56.551107 Total UI for P1: 0, mck2ui 16
5152 11:55:56.554664 best dqsien dly found for B1: ( 1, 3, 0)
5153 11:55:56.558329 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5154 11:55:56.561419 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5155 11:55:56.561985
5156 11:55:56.564858 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5157 11:55:56.568217 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5158 11:55:56.571599 [Gating] SW calibration Done
5159 11:55:56.572170 ==
5160 11:55:56.574774 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 11:55:56.578121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 11:55:56.578787 ==
5163 11:55:56.581437 RX Vref Scan: 0
5164 11:55:56.581900
5165 11:55:56.582268 RX Vref 0 -> 0, step: 1
5166 11:55:56.582670
5167 11:55:56.584710 RX Delay -80 -> 252, step: 8
5168 11:55:56.591633 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5169 11:55:56.594887 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5170 11:55:56.597733 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 11:55:56.601181 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5172 11:55:56.604885 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5173 11:55:56.608216 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5174 11:55:56.611396 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5175 11:55:56.618141 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5176 11:55:56.621452 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5177 11:55:56.624490 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5178 11:55:56.628418 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5179 11:55:56.631583 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5180 11:55:56.638105 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5181 11:55:56.641291 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5182 11:55:56.644982 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5183 11:55:56.647966 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 11:55:56.648433 ==
5185 11:55:56.651376 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 11:55:56.654317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 11:55:56.654843 ==
5188 11:55:56.658018 DQS Delay:
5189 11:55:56.658621 DQS0 = 0, DQS1 = 0
5190 11:55:56.661270 DQM Delay:
5191 11:55:56.661826 DQM0 = 105, DQM1 = 89
5192 11:55:56.662200 DQ Delay:
5193 11:55:56.664420 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5194 11:55:56.667860 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5195 11:55:56.671135 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5196 11:55:56.674798 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5197 11:55:56.677950
5198 11:55:56.678549
5199 11:55:56.678930 ==
5200 11:55:56.681501 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 11:55:56.684471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 11:55:56.685038 ==
5203 11:55:56.685412
5204 11:55:56.685749
5205 11:55:56.687595 TX Vref Scan disable
5206 11:55:56.688312 == TX Byte 0 ==
5207 11:55:56.694674 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5208 11:55:56.697517 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5209 11:55:56.697990 == TX Byte 1 ==
5210 11:55:56.704444 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5211 11:55:56.707792 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5212 11:55:56.708359 ==
5213 11:55:56.710903 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 11:55:56.714289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 11:55:56.714899 ==
5216 11:55:56.715275
5217 11:55:56.715620
5218 11:55:56.717336 TX Vref Scan disable
5219 11:55:56.721002 == TX Byte 0 ==
5220 11:55:56.724009 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5221 11:55:56.727580 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5222 11:55:56.730919 == TX Byte 1 ==
5223 11:55:56.734242 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5224 11:55:56.737831 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5225 11:55:56.738298
5226 11:55:56.740619 [DATLAT]
5227 11:55:56.741105 Freq=933, CH0 RK0
5228 11:55:56.741479
5229 11:55:56.744295 DATLAT Default: 0xd
5230 11:55:56.744862 0, 0xFFFF, sum = 0
5231 11:55:56.747514 1, 0xFFFF, sum = 0
5232 11:55:56.747988 2, 0xFFFF, sum = 0
5233 11:55:56.750478 3, 0xFFFF, sum = 0
5234 11:55:56.750894 4, 0xFFFF, sum = 0
5235 11:55:56.753979 5, 0xFFFF, sum = 0
5236 11:55:56.754490 6, 0xFFFF, sum = 0
5237 11:55:56.757241 7, 0xFFFF, sum = 0
5238 11:55:56.757712 8, 0xFFFF, sum = 0
5239 11:55:56.761153 9, 0xFFFF, sum = 0
5240 11:55:56.761723 10, 0x0, sum = 1
5241 11:55:56.764361 11, 0x0, sum = 2
5242 11:55:56.764935 12, 0x0, sum = 3
5243 11:55:56.767708 13, 0x0, sum = 4
5244 11:55:56.768280 best_step = 11
5245 11:55:56.768655
5246 11:55:56.768997 ==
5247 11:55:56.771089 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 11:55:56.777727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 11:55:56.778300 ==
5250 11:55:56.778714 RX Vref Scan: 1
5251 11:55:56.779062
5252 11:55:56.780781 RX Vref 0 -> 0, step: 1
5253 11:55:56.781343
5254 11:55:56.783966 RX Delay -53 -> 252, step: 4
5255 11:55:56.784534
5256 11:55:56.787329 Set Vref, RX VrefLevel [Byte0]: 58
5257 11:55:56.790300 [Byte1]: 52
5258 11:55:56.790805
5259 11:55:56.793856 Final RX Vref Byte 0 = 58 to rank0
5260 11:55:56.797079 Final RX Vref Byte 1 = 52 to rank0
5261 11:55:56.800732 Final RX Vref Byte 0 = 58 to rank1
5262 11:55:56.803814 Final RX Vref Byte 1 = 52 to rank1==
5263 11:55:56.806898 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 11:55:56.810130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 11:55:56.810661 ==
5266 11:55:56.813544 DQS Delay:
5267 11:55:56.814011 DQS0 = 0, DQS1 = 0
5268 11:55:56.816929 DQM Delay:
5269 11:55:56.817395 DQM0 = 107, DQM1 = 92
5270 11:55:56.817767 DQ Delay:
5271 11:55:56.820288 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5272 11:55:56.823598 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =116
5273 11:55:56.826968 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5274 11:55:56.833472 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5275 11:55:56.833940
5276 11:55:56.834310
5277 11:55:56.840141 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5278 11:55:56.843739 CH0 RK0: MR19=505, MR18=2622
5279 11:55:56.851317 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5280 11:55:56.851885
5281 11:55:56.853699 ----->DramcWriteLeveling(PI) begin...
5282 11:55:56.854327 ==
5283 11:55:56.857149 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 11:55:56.860763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:55:56.861335 ==
5286 11:55:56.863781 Write leveling (Byte 0): 34 => 34
5287 11:55:56.866931 Write leveling (Byte 1): 30 => 30
5288 11:55:56.870191 DramcWriteLeveling(PI) end<-----
5289 11:55:56.870688
5290 11:55:56.871059 ==
5291 11:55:56.874557 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 11:55:56.876890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 11:55:56.877352 ==
5294 11:55:56.880015 [Gating] SW mode calibration
5295 11:55:56.886792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 11:55:56.893552 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 11:55:56.896788 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 11:55:56.900000 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 11:55:56.906841 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 11:55:56.910545 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:55:56.913340 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:55:56.919854 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:55:56.923275 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5304 11:55:56.927183 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (0 0)
5305 11:55:56.933450 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 11:55:56.936739 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 11:55:56.940299 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 11:55:56.946909 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:55:56.950073 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:55:56.953226 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:55:56.960127 0 15 24 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5312 11:55:56.963170 0 15 28 | B1->B0 | 3434 4242 | 0 0 | (1 1) (0 0)
5313 11:55:56.967069 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 11:55:56.973570 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 11:55:56.976684 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 11:55:56.979876 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:55:56.986353 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:55:56.990104 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:55:56.993596 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5320 11:55:56.997018 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 11:55:57.003047 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:55:57.006303 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:55:57.010144 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:55:57.016493 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:55:57.019612 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:55:57.022885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:55:57.029960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:55:57.032954 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:55:57.036425 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:55:57.043029 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:55:57.046814 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:55:57.049735 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:55:57.056257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:55:57.059757 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:55:57.063265 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5336 11:55:57.070231 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 11:55:57.073024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 11:55:57.076830 Total UI for P1: 0, mck2ui 16
5339 11:55:57.079769 best dqsien dly found for B0: ( 1, 2, 26)
5340 11:55:57.083028 Total UI for P1: 0, mck2ui 16
5341 11:55:57.086545 best dqsien dly found for B1: ( 1, 2, 26)
5342 11:55:57.089552 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5343 11:55:57.093895 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5344 11:55:57.094542
5345 11:55:57.096422 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5346 11:55:57.099701 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5347 11:55:57.102824 [Gating] SW calibration Done
5348 11:55:57.103302 ==
5349 11:55:57.106917 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 11:55:57.109846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 11:55:57.110497 ==
5352 11:55:57.112728 RX Vref Scan: 0
5353 11:55:57.113277
5354 11:55:57.116154 RX Vref 0 -> 0, step: 1
5355 11:55:57.116694
5356 11:55:57.117077 RX Delay -80 -> 252, step: 8
5357 11:55:57.122966 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5358 11:55:57.126106 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5359 11:55:57.129693 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5360 11:55:57.132767 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5361 11:55:57.136363 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 11:55:57.139771 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5363 11:55:57.146128 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5364 11:55:57.149575 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5365 11:55:57.153066 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5366 11:55:57.156290 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5367 11:55:57.159423 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5368 11:55:57.166305 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5369 11:55:57.169948 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5370 11:55:57.172981 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5371 11:55:57.176305 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5372 11:55:57.179444 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5373 11:55:57.180017 ==
5374 11:55:57.182826 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 11:55:57.186233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:55:57.189664 ==
5377 11:55:57.190246 DQS Delay:
5378 11:55:57.190690 DQS0 = 0, DQS1 = 0
5379 11:55:57.192903 DQM Delay:
5380 11:55:57.193577 DQM0 = 104, DQM1 = 90
5381 11:55:57.196115 DQ Delay:
5382 11:55:57.200068 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5383 11:55:57.202765 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5384 11:55:57.206134 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5385 11:55:57.209854 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5386 11:55:57.210474
5387 11:55:57.210861
5388 11:55:57.211214 ==
5389 11:55:57.212735 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 11:55:57.216817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 11:55:57.217392 ==
5392 11:55:57.217764
5393 11:55:57.218108
5394 11:55:57.219916 TX Vref Scan disable
5395 11:55:57.220487 == TX Byte 0 ==
5396 11:55:57.225985 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5397 11:55:57.229771 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5398 11:55:57.230338 == TX Byte 1 ==
5399 11:55:57.235817 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5400 11:55:57.239260 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5401 11:55:57.239727 ==
5402 11:55:57.242470 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 11:55:57.245801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 11:55:57.246365 ==
5405 11:55:57.248918
5406 11:55:57.249383
5407 11:55:57.249751 TX Vref Scan disable
5408 11:55:57.252325 == TX Byte 0 ==
5409 11:55:57.256331 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5410 11:55:57.258974 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5411 11:55:57.262284 == TX Byte 1 ==
5412 11:55:57.265585 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5413 11:55:57.272564 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5414 11:55:57.273135
5415 11:55:57.273505 [DATLAT]
5416 11:55:57.273846 Freq=933, CH0 RK1
5417 11:55:57.274184
5418 11:55:57.276031 DATLAT Default: 0xb
5419 11:55:57.276598 0, 0xFFFF, sum = 0
5420 11:55:57.278788 1, 0xFFFF, sum = 0
5421 11:55:57.279264 2, 0xFFFF, sum = 0
5422 11:55:57.282304 3, 0xFFFF, sum = 0
5423 11:55:57.282807 4, 0xFFFF, sum = 0
5424 11:55:57.285936 5, 0xFFFF, sum = 0
5425 11:55:57.288858 6, 0xFFFF, sum = 0
5426 11:55:57.289334 7, 0xFFFF, sum = 0
5427 11:55:57.292687 8, 0xFFFF, sum = 0
5428 11:55:57.293258 9, 0xFFFF, sum = 0
5429 11:55:57.295913 10, 0x0, sum = 1
5430 11:55:57.296491 11, 0x0, sum = 2
5431 11:55:57.296870 12, 0x0, sum = 3
5432 11:55:57.298901 13, 0x0, sum = 4
5433 11:55:57.299378 best_step = 11
5434 11:55:57.299747
5435 11:55:57.302475 ==
5436 11:55:57.305447 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 11:55:57.309419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 11:55:57.309992 ==
5439 11:55:57.310370 RX Vref Scan: 0
5440 11:55:57.310756
5441 11:55:57.312603 RX Vref 0 -> 0, step: 1
5442 11:55:57.313065
5443 11:55:57.315908 RX Delay -53 -> 252, step: 4
5444 11:55:57.319298 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5445 11:55:57.325950 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5446 11:55:57.328949 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5447 11:55:57.332243 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5448 11:55:57.335673 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5449 11:55:57.339268 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5450 11:55:57.345410 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5451 11:55:57.349174 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5452 11:55:57.352103 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5453 11:55:57.355451 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5454 11:55:57.358540 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5455 11:55:57.362111 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5456 11:55:57.368748 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5457 11:55:57.372194 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5458 11:55:57.375555 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5459 11:55:57.378564 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5460 11:55:57.379034 ==
5461 11:55:57.382787 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:55:57.388611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:55:57.389185 ==
5464 11:55:57.389563 DQS Delay:
5465 11:55:57.391895 DQS0 = 0, DQS1 = 0
5466 11:55:57.392463 DQM Delay:
5467 11:55:57.392838 DQM0 = 104, DQM1 = 93
5468 11:55:57.395243 DQ Delay:
5469 11:55:57.398933 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5470 11:55:57.401585 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5471 11:55:57.405975 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5472 11:55:57.408771 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5473 11:55:57.409338
5474 11:55:57.409711
5475 11:55:57.415784 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5476 11:55:57.418634 CH0 RK1: MR19=505, MR18=2C0D
5477 11:55:57.425188 CH0_RK1: MR19=0x505, MR18=0x2C0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 11:55:57.428902 [RxdqsGatingPostProcess] freq 933
5479 11:55:57.435032 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 11:55:57.435600 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 11:55:57.439072 best DQS1 dly(2T, 0.5T) = (0, 11)
5482 11:55:57.441513 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 11:55:57.444891 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5484 11:55:57.448351 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 11:55:57.451864 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 11:55:57.455250 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 11:55:57.458443 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 11:55:57.461462 Pre-setting of DQS Precalculation
5489 11:55:57.465025 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 11:55:57.468813 ==
5491 11:55:57.471798 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 11:55:57.475026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 11:55:57.475499 ==
5494 11:55:57.481782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 11:55:57.485024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5496 11:55:57.489329 [CA 0] Center 37 (7~68) winsize 62
5497 11:55:57.491985 [CA 1] Center 37 (7~68) winsize 62
5498 11:55:57.495926 [CA 2] Center 35 (5~66) winsize 62
5499 11:55:57.498976 [CA 3] Center 34 (4~65) winsize 62
5500 11:55:57.502257 [CA 4] Center 35 (5~65) winsize 61
5501 11:55:57.505480 [CA 5] Center 34 (4~65) winsize 62
5502 11:55:57.506050
5503 11:55:57.508893 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5504 11:55:57.509453
5505 11:55:57.511850 [CATrainingPosCal] consider 1 rank data
5506 11:55:57.515586 u2DelayCellTimex100 = 270/100 ps
5507 11:55:57.518633 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5508 11:55:57.525395 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5509 11:55:57.528676 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5510 11:55:57.532172 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5511 11:55:57.535134 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5512 11:55:57.538521 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5513 11:55:57.539096
5514 11:55:57.541949 CA PerBit enable=1, Macro0, CA PI delay=34
5515 11:55:57.542478
5516 11:55:57.545176 [CBTSetCACLKResult] CA Dly = 34
5517 11:55:57.545745 CS Dly: 6 (0~37)
5518 11:55:57.548484 ==
5519 11:55:57.551642 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 11:55:57.554988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 11:55:57.555462 ==
5522 11:55:57.558375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 11:55:57.564948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 11:55:57.568799 [CA 0] Center 38 (8~69) winsize 62
5525 11:55:57.572124 [CA 1] Center 38 (8~69) winsize 62
5526 11:55:57.575196 [CA 2] Center 36 (6~66) winsize 61
5527 11:55:57.578981 [CA 3] Center 35 (5~65) winsize 61
5528 11:55:57.581862 [CA 4] Center 35 (5~65) winsize 61
5529 11:55:57.585761 [CA 5] Center 34 (4~65) winsize 62
5530 11:55:57.586339
5531 11:55:57.589059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 11:55:57.589628
5533 11:55:57.591918 [CATrainingPosCal] consider 2 rank data
5534 11:55:57.595605 u2DelayCellTimex100 = 270/100 ps
5535 11:55:57.598792 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5536 11:55:57.602147 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5537 11:55:57.608569 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5538 11:55:57.612000 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5539 11:55:57.615186 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5540 11:55:57.618745 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5541 11:55:57.619313
5542 11:55:57.622129 CA PerBit enable=1, Macro0, CA PI delay=34
5543 11:55:57.622752
5544 11:55:57.625514 [CBTSetCACLKResult] CA Dly = 34
5545 11:55:57.625985 CS Dly: 7 (0~39)
5546 11:55:57.626360
5547 11:55:57.628808 ----->DramcWriteLeveling(PI) begin...
5548 11:55:57.631986 ==
5549 11:55:57.635298 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 11:55:57.638763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 11:55:57.639336 ==
5552 11:55:57.641982 Write leveling (Byte 0): 26 => 26
5553 11:55:57.645291 Write leveling (Byte 1): 27 => 27
5554 11:55:57.648462 DramcWriteLeveling(PI) end<-----
5555 11:55:57.649028
5556 11:55:57.649401 ==
5557 11:55:57.652143 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 11:55:57.656114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 11:55:57.656701 ==
5560 11:55:57.658483 [Gating] SW mode calibration
5561 11:55:57.665365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 11:55:57.672024 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 11:55:57.674967 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 11:55:57.678428 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 11:55:57.684915 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 11:55:57.688343 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:55:57.692196 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:55:57.695061 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5569 11:55:57.701616 0 14 24 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
5570 11:55:57.705685 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5571 11:55:57.708643 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 11:55:57.715241 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 11:55:57.718548 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 11:55:57.722091 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:55:57.728693 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:55:57.731934 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:55:57.735284 0 15 24 | B1->B0 | 2828 2828 | 1 0 | (0 0) (0 0)
5578 11:55:57.741725 0 15 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5579 11:55:57.744916 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 11:55:57.747993 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 11:55:57.755188 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 11:55:57.758868 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:55:57.761539 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:55:57.768213 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:55:57.771189 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5586 11:55:57.775119 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5587 11:55:57.781645 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:55:57.784680 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:55:57.787930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:55:57.794665 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:55:57.798014 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:55:57.801426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:55:57.808329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:55:57.811188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:55:57.814897 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:55:57.821184 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:55:57.824407 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:55:57.827934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:55:57.831391 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:55:57.838212 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:55:57.841217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5602 11:55:57.844288 Total UI for P1: 0, mck2ui 16
5603 11:55:57.847867 best dqsien dly found for B0: ( 1, 2, 22)
5604 11:55:57.851240 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:55:57.854601 Total UI for P1: 0, mck2ui 16
5606 11:55:57.858075 best dqsien dly found for B1: ( 1, 2, 24)
5607 11:55:57.861198 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5608 11:55:57.864709 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5609 11:55:57.865180
5610 11:55:57.872249 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5611 11:55:57.874568 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5612 11:55:57.877944 [Gating] SW calibration Done
5613 11:55:57.878575 ==
5614 11:55:57.881008 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 11:55:57.884761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 11:55:57.885344 ==
5617 11:55:57.885723 RX Vref Scan: 0
5618 11:55:57.886073
5619 11:55:57.887905 RX Vref 0 -> 0, step: 1
5620 11:55:57.888373
5621 11:55:57.890967 RX Delay -80 -> 252, step: 8
5622 11:55:57.895065 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5623 11:55:57.897943 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5624 11:55:57.901254 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5625 11:55:57.907856 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5626 11:55:57.911758 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5627 11:55:57.914167 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5628 11:55:57.918009 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5629 11:55:57.921158 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5630 11:55:57.924875 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5631 11:55:57.931260 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5632 11:55:57.934127 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5633 11:55:57.937803 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5634 11:55:57.940779 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5635 11:55:57.944299 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5636 11:55:57.950887 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5637 11:55:57.954366 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5638 11:55:57.954977 ==
5639 11:55:57.957806 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 11:55:57.960953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 11:55:57.961429 ==
5642 11:55:57.961803 DQS Delay:
5643 11:55:57.964488 DQS0 = 0, DQS1 = 0
5644 11:55:57.964967 DQM Delay:
5645 11:55:57.967629 DQM0 = 101, DQM1 = 95
5646 11:55:57.968196 DQ Delay:
5647 11:55:57.970808 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5648 11:55:57.974258 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5649 11:55:57.977989 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5650 11:55:57.980857 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5651 11:55:57.981425
5652 11:55:57.981799
5653 11:55:57.982182 ==
5654 11:55:57.984078 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 11:55:57.991207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 11:55:57.991799 ==
5657 11:55:57.992184
5658 11:55:57.992531
5659 11:55:57.992863 TX Vref Scan disable
5660 11:55:57.994117 == TX Byte 0 ==
5661 11:55:57.997610 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5662 11:55:58.004419 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5663 11:55:58.004995 == TX Byte 1 ==
5664 11:55:58.007598 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 11:55:58.010844 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 11:55:58.014123 ==
5667 11:55:58.017664 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 11:55:58.021108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 11:55:58.021700 ==
5670 11:55:58.022192
5671 11:55:58.022683
5672 11:55:58.024353 TX Vref Scan disable
5673 11:55:58.024852 == TX Byte 0 ==
5674 11:55:58.031057 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 11:55:58.034234 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 11:55:58.034858 == TX Byte 1 ==
5677 11:55:58.041022 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 11:55:58.044042 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 11:55:58.044530
5680 11:55:58.045011 [DATLAT]
5681 11:55:58.047324 Freq=933, CH1 RK0
5682 11:55:58.047890
5683 11:55:58.048376 DATLAT Default: 0xd
5684 11:55:58.050631 0, 0xFFFF, sum = 0
5685 11:55:58.051119 1, 0xFFFF, sum = 0
5686 11:55:58.054629 2, 0xFFFF, sum = 0
5687 11:55:58.055218 3, 0xFFFF, sum = 0
5688 11:55:58.057714 4, 0xFFFF, sum = 0
5689 11:55:58.058308 5, 0xFFFF, sum = 0
5690 11:55:58.061042 6, 0xFFFF, sum = 0
5691 11:55:58.061537 7, 0xFFFF, sum = 0
5692 11:55:58.063796 8, 0xFFFF, sum = 0
5693 11:55:58.067515 9, 0xFFFF, sum = 0
5694 11:55:58.068089 10, 0x0, sum = 1
5695 11:55:58.068473 11, 0x0, sum = 2
5696 11:55:58.071130 12, 0x0, sum = 3
5697 11:55:58.071610 13, 0x0, sum = 4
5698 11:55:58.074298 best_step = 11
5699 11:55:58.074809
5700 11:55:58.075188 ==
5701 11:55:58.077301 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 11:55:58.080813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 11:55:58.081385 ==
5704 11:55:58.083966 RX Vref Scan: 1
5705 11:55:58.084436
5706 11:55:58.084815 RX Vref 0 -> 0, step: 1
5707 11:55:58.085167
5708 11:55:58.087162 RX Delay -53 -> 252, step: 4
5709 11:55:58.087635
5710 11:55:58.090674 Set Vref, RX VrefLevel [Byte0]: 53
5711 11:55:58.094135 [Byte1]: 58
5712 11:55:58.098187
5713 11:55:58.098803 Final RX Vref Byte 0 = 53 to rank0
5714 11:55:58.101522 Final RX Vref Byte 1 = 58 to rank0
5715 11:55:58.104838 Final RX Vref Byte 0 = 53 to rank1
5716 11:55:58.108085 Final RX Vref Byte 1 = 58 to rank1==
5717 11:55:58.111661 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 11:55:58.118085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 11:55:58.118709 ==
5720 11:55:58.119095 DQS Delay:
5721 11:55:58.119443 DQS0 = 0, DQS1 = 0
5722 11:55:58.121643 DQM Delay:
5723 11:55:58.122145 DQM0 = 104, DQM1 = 97
5724 11:55:58.124706 DQ Delay:
5725 11:55:58.128009 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5726 11:55:58.131273 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5727 11:55:58.134574 DQ8 =88, DQ9 =84, DQ10 =102, DQ11 =92
5728 11:55:58.138062 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =104
5729 11:55:58.138666
5730 11:55:58.139044
5731 11:55:58.144429 [DQSOSCAuto] RK0, (LSB)MR18= 0x1730, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5732 11:55:58.147868 CH1 RK0: MR19=505, MR18=1730
5733 11:55:58.154673 CH1_RK0: MR19=0x505, MR18=0x1730, DQSOSC=406, MR23=63, INC=65, DEC=43
5734 11:55:58.155243
5735 11:55:58.157874 ----->DramcWriteLeveling(PI) begin...
5736 11:55:58.158493 ==
5737 11:55:58.161087 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 11:55:58.164385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 11:55:58.168156 ==
5740 11:55:58.168734 Write leveling (Byte 0): 26 => 26
5741 11:55:58.171107 Write leveling (Byte 1): 29 => 29
5742 11:55:58.174584 DramcWriteLeveling(PI) end<-----
5743 11:55:58.175155
5744 11:55:58.175640 ==
5745 11:55:58.177798 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 11:55:58.184386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 11:55:58.184968 ==
5748 11:55:58.185461 [Gating] SW mode calibration
5749 11:55:58.194586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5750 11:55:58.197641 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5751 11:55:58.204327 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5752 11:55:58.207458 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 11:55:58.210934 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 11:55:58.217625 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 11:55:58.220672 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:55:58.223899 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:55:58.227689 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (0 1) (1 1)
5758 11:55:58.234100 0 14 28 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (1 0)
5759 11:55:58.237149 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:55:58.243605 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 11:55:58.247614 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 11:55:58.250098 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 11:55:58.254016 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:55:58.260705 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:55:58.263870 0 15 24 | B1->B0 | 2a2a 2727 | 1 0 | (0 0) (0 0)
5766 11:55:58.267852 0 15 28 | B1->B0 | 3d3d 3939 | 0 0 | (1 1) (0 0)
5767 11:55:58.273944 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5768 11:55:58.277308 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 11:55:58.280541 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:55:58.287041 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:55:58.290340 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:55:58.293603 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:55:58.300463 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5774 11:55:58.304091 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5775 11:55:58.307092 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5776 11:55:58.313740 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:55:58.317200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:55:58.320288 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:55:58.326499 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:55:58.330005 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:55:58.333485 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:55:58.339610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:55:58.343139 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:55:58.346251 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:55:58.353337 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:55:58.356491 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:55:58.359962 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:55:58.366465 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:55:58.369541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5790 11:55:58.373434 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5791 11:55:58.376415 Total UI for P1: 0, mck2ui 16
5792 11:55:58.379534 best dqsien dly found for B1: ( 1, 2, 24)
5793 11:55:58.386511 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 11:55:58.387103 Total UI for P1: 0, mck2ui 16
5795 11:55:58.393275 best dqsien dly found for B0: ( 1, 2, 26)
5796 11:55:58.396727 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5797 11:55:58.399456 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5798 11:55:58.399938
5799 11:55:58.403100 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5800 11:55:58.406101 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 11:55:58.409611 [Gating] SW calibration Done
5802 11:55:58.410249 ==
5803 11:55:58.412728 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 11:55:58.415640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 11:55:58.416115 ==
5806 11:55:58.419625 RX Vref Scan: 0
5807 11:55:58.420197
5808 11:55:58.420571 RX Vref 0 -> 0, step: 1
5809 11:55:58.420919
5810 11:55:58.422464 RX Delay -80 -> 252, step: 8
5811 11:55:58.425824 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5812 11:55:58.432429 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5813 11:55:58.435656 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5814 11:55:58.438976 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5815 11:55:58.442278 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5816 11:55:58.445530 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5817 11:55:58.452260 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5818 11:55:58.455442 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5819 11:55:58.458907 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5820 11:55:58.461992 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5821 11:55:58.466150 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5822 11:55:58.469454 iDelay=200, Bit 11, Center 91 (-8 ~ 191) 200
5823 11:55:58.475516 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5824 11:55:58.478959 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5825 11:55:58.482303 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5826 11:55:58.485677 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5827 11:55:58.486251 ==
5828 11:55:58.488687 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 11:55:58.492034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 11:55:58.496445 ==
5831 11:55:58.497017 DQS Delay:
5832 11:55:58.497401 DQS0 = 0, DQS1 = 0
5833 11:55:58.499141 DQM Delay:
5834 11:55:58.499614 DQM0 = 101, DQM1 = 95
5835 11:55:58.502330 DQ Delay:
5836 11:55:58.505570 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5837 11:55:58.508545 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5838 11:55:58.511944 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5839 11:55:58.515588 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5840 11:55:58.516061
5841 11:55:58.516442
5842 11:55:58.516792 ==
5843 11:55:58.518354 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 11:55:58.522056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 11:55:58.522666 ==
5846 11:55:58.523050
5847 11:55:58.523400
5848 11:55:58.525569 TX Vref Scan disable
5849 11:55:58.528516 == TX Byte 0 ==
5850 11:55:58.531597 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5851 11:55:58.535157 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5852 11:55:58.538462 == TX Byte 1 ==
5853 11:55:58.541833 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5854 11:55:58.545185 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5855 11:55:58.545652 ==
5856 11:55:58.548242 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 11:55:58.551673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 11:55:58.552146 ==
5859 11:55:58.555360
5860 11:55:58.555824
5861 11:55:58.556191 TX Vref Scan disable
5862 11:55:58.558156 == TX Byte 0 ==
5863 11:55:58.561515 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5864 11:55:58.568160 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5865 11:55:58.568630 == TX Byte 1 ==
5866 11:55:58.572083 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5867 11:55:58.575233 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5868 11:55:58.578427
5869 11:55:58.578895 [DATLAT]
5870 11:55:58.579265 Freq=933, CH1 RK1
5871 11:55:58.579613
5872 11:55:58.581893 DATLAT Default: 0xb
5873 11:55:58.582357 0, 0xFFFF, sum = 0
5874 11:55:58.585021 1, 0xFFFF, sum = 0
5875 11:55:58.585492 2, 0xFFFF, sum = 0
5876 11:55:58.589081 3, 0xFFFF, sum = 0
5877 11:55:58.589657 4, 0xFFFF, sum = 0
5878 11:55:58.591990 5, 0xFFFF, sum = 0
5879 11:55:58.595071 6, 0xFFFF, sum = 0
5880 11:55:58.595642 7, 0xFFFF, sum = 0
5881 11:55:58.598542 8, 0xFFFF, sum = 0
5882 11:55:58.599111 9, 0xFFFF, sum = 0
5883 11:55:58.601969 10, 0x0, sum = 1
5884 11:55:58.602573 11, 0x0, sum = 2
5885 11:55:58.602952 12, 0x0, sum = 3
5886 11:55:58.605411 13, 0x0, sum = 4
5887 11:55:58.605985 best_step = 11
5888 11:55:58.606361
5889 11:55:58.606745 ==
5890 11:55:58.608563 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 11:55:58.615300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 11:55:58.616044 ==
5893 11:55:58.616431 RX Vref Scan: 0
5894 11:55:58.616779
5895 11:55:58.618604 RX Vref 0 -> 0, step: 1
5896 11:55:58.619070
5897 11:55:58.622880 RX Delay -53 -> 252, step: 4
5898 11:55:58.625420 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5899 11:55:58.631983 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5900 11:55:58.635124 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5901 11:55:58.638416 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5902 11:55:58.641415 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5903 11:55:58.645149 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5904 11:55:58.648228 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5905 11:55:58.655064 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5906 11:55:58.658055 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5907 11:55:58.661509 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5908 11:55:58.664637 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5909 11:55:58.668072 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5910 11:55:58.674682 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5911 11:55:58.678103 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5912 11:55:58.681282 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5913 11:55:58.684692 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5914 11:55:58.685258 ==
5915 11:55:58.688274 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:55:58.695071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:55:58.695634 ==
5918 11:55:58.696008 DQS Delay:
5919 11:55:58.698140 DQS0 = 0, DQS1 = 0
5920 11:55:58.698565 DQM Delay:
5921 11:55:58.698908 DQM0 = 104, DQM1 = 97
5922 11:55:58.701566 DQ Delay:
5923 11:55:58.705013 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5924 11:55:58.708175 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5925 11:55:58.711521 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =94
5926 11:55:58.714839 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5927 11:55:58.715415
5928 11:55:58.715903
5929 11:55:58.721583 [DQSOSCAuto] RK1, (LSB)MR18= 0x2703, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5930 11:55:58.724624 CH1 RK1: MR19=505, MR18=2703
5931 11:55:58.731307 CH1_RK1: MR19=0x505, MR18=0x2703, DQSOSC=409, MR23=63, INC=64, DEC=43
5932 11:55:58.734627 [RxdqsGatingPostProcess] freq 933
5933 11:55:58.741135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5934 11:55:58.744494 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 11:55:58.744959 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 11:55:58.747815 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 11:55:58.751256 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 11:55:58.754490 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 11:55:58.757780 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 11:55:58.761089 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 11:55:58.764621 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 11:55:58.767742 Pre-setting of DQS Precalculation
5943 11:55:58.774449 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5944 11:55:58.781206 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5945 11:55:58.787983 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5946 11:55:58.788548
5947 11:55:58.788923
5948 11:55:58.790972 [Calibration Summary] 1866 Mbps
5949 11:55:58.791444 CH 0, Rank 0
5950 11:55:58.793972 SW Impedance : PASS
5951 11:55:58.797815 DUTY Scan : NO K
5952 11:55:58.798378 ZQ Calibration : PASS
5953 11:55:58.801465 Jitter Meter : NO K
5954 11:55:58.805027 CBT Training : PASS
5955 11:55:58.805596 Write leveling : PASS
5956 11:55:58.808110 RX DQS gating : PASS
5957 11:55:58.808681 RX DQ/DQS(RDDQC) : PASS
5958 11:55:58.810925 TX DQ/DQS : PASS
5959 11:55:58.814525 RX DATLAT : PASS
5960 11:55:58.815093 RX DQ/DQS(Engine): PASS
5961 11:55:58.817800 TX OE : NO K
5962 11:55:58.818269 All Pass.
5963 11:55:58.818694
5964 11:55:58.820616 CH 0, Rank 1
5965 11:55:58.821085 SW Impedance : PASS
5966 11:55:58.823979 DUTY Scan : NO K
5967 11:55:58.827846 ZQ Calibration : PASS
5968 11:55:58.828425 Jitter Meter : NO K
5969 11:55:58.831550 CBT Training : PASS
5970 11:55:58.834096 Write leveling : PASS
5971 11:55:58.834709 RX DQS gating : PASS
5972 11:55:58.837221 RX DQ/DQS(RDDQC) : PASS
5973 11:55:58.840963 TX DQ/DQS : PASS
5974 11:55:58.841437 RX DATLAT : PASS
5975 11:55:58.844128 RX DQ/DQS(Engine): PASS
5976 11:55:58.847600 TX OE : NO K
5977 11:55:58.848112 All Pass.
5978 11:55:58.848501
5979 11:55:58.848855 CH 1, Rank 0
5980 11:55:58.851056 SW Impedance : PASS
5981 11:55:58.854029 DUTY Scan : NO K
5982 11:55:58.854560 ZQ Calibration : PASS
5983 11:55:58.857609 Jitter Meter : NO K
5984 11:55:58.858081 CBT Training : PASS
5985 11:55:58.860738 Write leveling : PASS
5986 11:55:58.864178 RX DQS gating : PASS
5987 11:55:58.864688 RX DQ/DQS(RDDQC) : PASS
5988 11:55:58.867276 TX DQ/DQS : PASS
5989 11:55:58.870590 RX DATLAT : PASS
5990 11:55:58.871208 RX DQ/DQS(Engine): PASS
5991 11:55:58.874269 TX OE : NO K
5992 11:55:58.874808 All Pass.
5993 11:55:58.875191
5994 11:55:58.877354 CH 1, Rank 1
5995 11:55:58.877828 SW Impedance : PASS
5996 11:55:58.880741 DUTY Scan : NO K
5997 11:55:58.883905 ZQ Calibration : PASS
5998 11:55:58.884378 Jitter Meter : NO K
5999 11:55:58.887608 CBT Training : PASS
6000 11:55:58.890503 Write leveling : PASS
6001 11:55:58.890976 RX DQS gating : PASS
6002 11:55:58.894197 RX DQ/DQS(RDDQC) : PASS
6003 11:55:58.897795 TX DQ/DQS : PASS
6004 11:55:58.898379 RX DATLAT : PASS
6005 11:55:58.900859 RX DQ/DQS(Engine): PASS
6006 11:55:58.901434 TX OE : NO K
6007 11:55:58.904444 All Pass.
6008 11:55:58.905016
6009 11:55:58.905399 DramC Write-DBI off
6010 11:55:58.907560 PER_BANK_REFRESH: Hybrid Mode
6011 11:55:58.910902 TX_TRACKING: ON
6012 11:55:58.917257 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6013 11:55:58.920742 [FAST_K] Save calibration result to emmc
6014 11:55:58.927252 dramc_set_vcore_voltage set vcore to 650000
6015 11:55:58.927827 Read voltage for 400, 6
6016 11:55:58.928208 Vio18 = 0
6017 11:55:58.931006 Vcore = 650000
6018 11:55:58.931584 Vdram = 0
6019 11:55:58.931965 Vddq = 0
6020 11:55:58.934476 Vmddr = 0
6021 11:55:58.937473 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6022 11:55:58.943921 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6023 11:55:58.944402 MEM_TYPE=3, freq_sel=20
6024 11:55:58.947653 sv_algorithm_assistance_LP4_800
6025 11:55:58.954144 ============ PULL DRAM RESETB DOWN ============
6026 11:55:58.957414 ========== PULL DRAM RESETB DOWN end =========
6027 11:55:58.960682 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 11:55:58.963883 ===================================
6029 11:55:58.967392 LPDDR4 DRAM CONFIGURATION
6030 11:55:58.970328 ===================================
6031 11:55:58.974023 EX_ROW_EN[0] = 0x0
6032 11:55:58.974627 EX_ROW_EN[1] = 0x0
6033 11:55:58.976943 LP4Y_EN = 0x0
6034 11:55:58.977415 WORK_FSP = 0x0
6035 11:55:58.980414 WL = 0x2
6036 11:55:58.980979 RL = 0x2
6037 11:55:58.983732 BL = 0x2
6038 11:55:58.984205 RPST = 0x0
6039 11:55:58.987181 RD_PRE = 0x0
6040 11:55:58.987656 WR_PRE = 0x1
6041 11:55:58.990194 WR_PST = 0x0
6042 11:55:58.990700 DBI_WR = 0x0
6043 11:55:58.994145 DBI_RD = 0x0
6044 11:55:58.994834 OTF = 0x1
6045 11:55:58.996903 ===================================
6046 11:55:59.000718 ===================================
6047 11:55:59.003697 ANA top config
6048 11:55:59.007126 ===================================
6049 11:55:59.010972 DLL_ASYNC_EN = 0
6050 11:55:59.011538 ALL_SLAVE_EN = 1
6051 11:55:59.013638 NEW_RANK_MODE = 1
6052 11:55:59.016891 DLL_IDLE_MODE = 1
6053 11:55:59.020600 LP45_APHY_COMB_EN = 1
6054 11:55:59.021168 TX_ODT_DIS = 1
6055 11:55:59.023889 NEW_8X_MODE = 1
6056 11:55:59.026837 ===================================
6057 11:55:59.030131 ===================================
6058 11:55:59.033508 data_rate = 800
6059 11:55:59.036920 CKR = 1
6060 11:55:59.040169 DQ_P2S_RATIO = 4
6061 11:55:59.043940 ===================================
6062 11:55:59.046953 CA_P2S_RATIO = 4
6063 11:55:59.047430 DQ_CA_OPEN = 0
6064 11:55:59.050296 DQ_SEMI_OPEN = 1
6065 11:55:59.053301 CA_SEMI_OPEN = 1
6066 11:55:59.056990 CA_FULL_RATE = 0
6067 11:55:59.060150 DQ_CKDIV4_EN = 0
6068 11:55:59.063162 CA_CKDIV4_EN = 1
6069 11:55:59.063735 CA_PREDIV_EN = 0
6070 11:55:59.066367 PH8_DLY = 0
6071 11:55:59.069698 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6072 11:55:59.073206 DQ_AAMCK_DIV = 0
6073 11:55:59.076268 CA_AAMCK_DIV = 0
6074 11:55:59.080362 CA_ADMCK_DIV = 4
6075 11:55:59.080932 DQ_TRACK_CA_EN = 0
6076 11:55:59.083070 CA_PICK = 800
6077 11:55:59.086512 CA_MCKIO = 400
6078 11:55:59.089885 MCKIO_SEMI = 400
6079 11:55:59.093457 PLL_FREQ = 3016
6080 11:55:59.096411 DQ_UI_PI_RATIO = 32
6081 11:55:59.100076 CA_UI_PI_RATIO = 32
6082 11:55:59.102995 ===================================
6083 11:55:59.106437 ===================================
6084 11:55:59.107004 memory_type:LPDDR4
6085 11:55:59.109696 GP_NUM : 10
6086 11:55:59.113836 SRAM_EN : 1
6087 11:55:59.114445 MD32_EN : 0
6088 11:55:59.116131 ===================================
6089 11:55:59.119645 [ANA_INIT] >>>>>>>>>>>>>>
6090 11:55:59.123329 <<<<<< [CONFIGURE PHASE]: ANA_TX
6091 11:55:59.126469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6092 11:55:59.130195 ===================================
6093 11:55:59.132974 data_rate = 800,PCW = 0X7400
6094 11:55:59.136323 ===================================
6095 11:55:59.140225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6096 11:55:59.143350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 11:55:59.156249 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 11:55:59.159891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6099 11:55:59.162769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6100 11:55:59.166561 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6101 11:55:59.169383 [ANA_INIT] flow start
6102 11:55:59.172807 [ANA_INIT] PLL >>>>>>>>
6103 11:55:59.173372 [ANA_INIT] PLL <<<<<<<<
6104 11:55:59.175908 [ANA_INIT] MIDPI >>>>>>>>
6105 11:55:59.179587 [ANA_INIT] MIDPI <<<<<<<<
6106 11:55:59.180152 [ANA_INIT] DLL >>>>>>>>
6107 11:55:59.182667 [ANA_INIT] flow end
6108 11:55:59.185894 ============ LP4 DIFF to SE enter ============
6109 11:55:59.189546 ============ LP4 DIFF to SE exit ============
6110 11:55:59.192970 [ANA_INIT] <<<<<<<<<<<<<
6111 11:55:59.196058 [Flow] Enable top DCM control >>>>>
6112 11:55:59.199289 [Flow] Enable top DCM control <<<<<
6113 11:55:59.203085 Enable DLL master slave shuffle
6114 11:55:59.209875 ==============================================================
6115 11:55:59.210493 Gating Mode config
6116 11:55:59.215940 ==============================================================
6117 11:55:59.216512 Config description:
6118 11:55:59.226415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6119 11:55:59.232635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6120 11:55:59.239284 SELPH_MODE 0: By rank 1: By Phase
6121 11:55:59.242710 ==============================================================
6122 11:55:59.245826 GAT_TRACK_EN = 0
6123 11:55:59.249320 RX_GATING_MODE = 2
6124 11:55:59.252424 RX_GATING_TRACK_MODE = 2
6125 11:55:59.256337 SELPH_MODE = 1
6126 11:55:59.259498 PICG_EARLY_EN = 1
6127 11:55:59.262605 VALID_LAT_VALUE = 1
6128 11:55:59.269065 ==============================================================
6129 11:55:59.272665 Enter into Gating configuration >>>>
6130 11:55:59.275808 Exit from Gating configuration <<<<
6131 11:55:59.276279 Enter into DVFS_PRE_config >>>>>
6132 11:55:59.289306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6133 11:55:59.292583 Exit from DVFS_PRE_config <<<<<
6134 11:55:59.296125 Enter into PICG configuration >>>>
6135 11:55:59.299147 Exit from PICG configuration <<<<
6136 11:55:59.299723 [RX_INPUT] configuration >>>>>
6137 11:55:59.302482 [RX_INPUT] configuration <<<<<
6138 11:55:59.309253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6139 11:55:59.313214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6140 11:55:59.319179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 11:55:59.326104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 11:55:59.332672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 11:55:59.339281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 11:55:59.342523 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6145 11:55:59.346098 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6146 11:55:59.349657 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6147 11:55:59.355973 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6148 11:55:59.359223 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6149 11:55:59.362705 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 11:55:59.366054 ===================================
6151 11:55:59.368903 LPDDR4 DRAM CONFIGURATION
6152 11:55:59.372530 ===================================
6153 11:55:59.375828 EX_ROW_EN[0] = 0x0
6154 11:55:59.376408 EX_ROW_EN[1] = 0x0
6155 11:55:59.379185 LP4Y_EN = 0x0
6156 11:55:59.379669 WORK_FSP = 0x0
6157 11:55:59.382837 WL = 0x2
6158 11:55:59.383419 RL = 0x2
6159 11:55:59.385437 BL = 0x2
6160 11:55:59.386016 RPST = 0x0
6161 11:55:59.388697 RD_PRE = 0x0
6162 11:55:59.389177 WR_PRE = 0x1
6163 11:55:59.392467 WR_PST = 0x0
6164 11:55:59.393044 DBI_WR = 0x0
6165 11:55:59.395337 DBI_RD = 0x0
6166 11:55:59.395819 OTF = 0x1
6167 11:55:59.398599 ===================================
6168 11:55:59.405498 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6169 11:55:59.408954 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6170 11:55:59.412154 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 11:55:59.415401 ===================================
6172 11:55:59.418871 LPDDR4 DRAM CONFIGURATION
6173 11:55:59.422549 ===================================
6174 11:55:59.425492 EX_ROW_EN[0] = 0x10
6175 11:55:59.426075 EX_ROW_EN[1] = 0x0
6176 11:55:59.428853 LP4Y_EN = 0x0
6177 11:55:59.429434 WORK_FSP = 0x0
6178 11:55:59.432230 WL = 0x2
6179 11:55:59.432812 RL = 0x2
6180 11:55:59.435366 BL = 0x2
6181 11:55:59.435943 RPST = 0x0
6182 11:55:59.438550 RD_PRE = 0x0
6183 11:55:59.439123 WR_PRE = 0x1
6184 11:55:59.442313 WR_PST = 0x0
6185 11:55:59.442939 DBI_WR = 0x0
6186 11:55:59.445075 DBI_RD = 0x0
6187 11:55:59.445557 OTF = 0x1
6188 11:55:59.448450 ===================================
6189 11:55:59.455226 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6190 11:55:59.460274 nWR fixed to 30
6191 11:55:59.463189 [ModeRegInit_LP4] CH0 RK0
6192 11:55:59.463764 [ModeRegInit_LP4] CH0 RK1
6193 11:55:59.466629 [ModeRegInit_LP4] CH1 RK0
6194 11:55:59.469936 [ModeRegInit_LP4] CH1 RK1
6195 11:55:59.470480 match AC timing 19
6196 11:55:59.476594 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6197 11:55:59.479861 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6198 11:55:59.483085 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6199 11:55:59.490140 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6200 11:55:59.492783 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6201 11:55:59.493256 ==
6202 11:55:59.495974 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 11:55:59.499588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6204 11:55:59.500161 ==
6205 11:55:59.506162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6206 11:55:59.512924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6207 11:55:59.516054 [CA 0] Center 36 (8~64) winsize 57
6208 11:55:59.519549 [CA 1] Center 36 (8~64) winsize 57
6209 11:55:59.523018 [CA 2] Center 36 (8~64) winsize 57
6210 11:55:59.523583 [CA 3] Center 36 (8~64) winsize 57
6211 11:55:59.526865 [CA 4] Center 36 (8~64) winsize 57
6212 11:55:59.529855 [CA 5] Center 36 (8~64) winsize 57
6213 11:55:59.530459
6214 11:55:59.536640 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6215 11:55:59.537206
6216 11:55:59.539699 [CATrainingPosCal] consider 1 rank data
6217 11:55:59.543063 u2DelayCellTimex100 = 270/100 ps
6218 11:55:59.546235 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 11:55:59.549528 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 11:55:59.552702 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 11:55:59.555987 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:55:59.559532 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:55:59.562913 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:55:59.563476
6225 11:55:59.566275 CA PerBit enable=1, Macro0, CA PI delay=36
6226 11:55:59.566891
6227 11:55:59.569038 [CBTSetCACLKResult] CA Dly = 36
6228 11:55:59.573135 CS Dly: 1 (0~32)
6229 11:55:59.573701 ==
6230 11:55:59.576049 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 11:55:59.579139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 11:55:59.579615 ==
6233 11:55:59.586272 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 11:55:59.589688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6235 11:55:59.592665 [CA 0] Center 36 (8~64) winsize 57
6236 11:55:59.596314 [CA 1] Center 36 (8~64) winsize 57
6237 11:55:59.599266 [CA 2] Center 36 (8~64) winsize 57
6238 11:55:59.602541 [CA 3] Center 36 (8~64) winsize 57
6239 11:55:59.605840 [CA 4] Center 36 (8~64) winsize 57
6240 11:55:59.609219 [CA 5] Center 36 (8~64) winsize 57
6241 11:55:59.609798
6242 11:55:59.612859 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6243 11:55:59.613430
6244 11:55:59.615996 [CATrainingPosCal] consider 2 rank data
6245 11:55:59.618760 u2DelayCellTimex100 = 270/100 ps
6246 11:55:59.622641 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:55:59.625697 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:55:59.632678 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:55:59.635399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:55:59.639174 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:55:59.642654 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:55:59.643343
6253 11:55:59.645824 CA PerBit enable=1, Macro0, CA PI delay=36
6254 11:55:59.646434
6255 11:55:59.648465 [CBTSetCACLKResult] CA Dly = 36
6256 11:55:59.648937 CS Dly: 1 (0~32)
6257 11:55:59.649313
6258 11:55:59.652411 ----->DramcWriteLeveling(PI) begin...
6259 11:55:59.655721 ==
6260 11:55:59.658842 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 11:55:59.662161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 11:55:59.662763 ==
6263 11:55:59.665470 Write leveling (Byte 0): 40 => 8
6264 11:55:59.669397 Write leveling (Byte 1): 32 => 0
6265 11:55:59.669870 DramcWriteLeveling(PI) end<-----
6266 11:55:59.672426
6267 11:55:59.672895 ==
6268 11:55:59.675736 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 11:55:59.678818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 11:55:59.679294 ==
6271 11:55:59.682279 [Gating] SW mode calibration
6272 11:55:59.688970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 11:55:59.692618 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6274 11:55:59.699160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 11:55:59.702802 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 11:55:59.705687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 11:55:59.712246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 11:55:59.715570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 11:55:59.718848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 11:55:59.725486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 11:55:59.728896 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 11:55:59.732431 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 11:55:59.735234 Total UI for P1: 0, mck2ui 16
6284 11:55:59.738665 best dqsien dly found for B0: ( 0, 14, 24)
6285 11:55:59.742342 Total UI for P1: 0, mck2ui 16
6286 11:55:59.745636 best dqsien dly found for B1: ( 0, 14, 24)
6287 11:55:59.749080 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6288 11:55:59.751967 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6289 11:55:59.752441
6290 11:55:59.758949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 11:55:59.762159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 11:55:59.762755 [Gating] SW calibration Done
6293 11:55:59.765423 ==
6294 11:55:59.768688 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 11:55:59.772076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 11:55:59.772542 ==
6297 11:55:59.772907 RX Vref Scan: 0
6298 11:55:59.773243
6299 11:55:59.775113 RX Vref 0 -> 0, step: 1
6300 11:55:59.775571
6301 11:55:59.778347 RX Delay -410 -> 252, step: 16
6302 11:55:59.781797 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6303 11:55:59.785151 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6304 11:55:59.792544 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6305 11:55:59.795190 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6306 11:55:59.798601 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6307 11:55:59.802013 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6308 11:55:59.808834 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6309 11:55:59.812140 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6310 11:55:59.815172 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6311 11:55:59.818523 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6312 11:55:59.825212 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6313 11:55:59.828408 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6314 11:55:59.832031 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6315 11:55:59.838927 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6316 11:55:59.842002 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6317 11:55:59.845010 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6318 11:55:59.845470 ==
6319 11:55:59.848962 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 11:55:59.851729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 11:55:59.852196 ==
6322 11:55:59.855230 DQS Delay:
6323 11:55:59.855780 DQS0 = 27, DQS1 = 43
6324 11:55:59.858694 DQM Delay:
6325 11:55:59.859252 DQM0 = 12, DQM1 = 13
6326 11:55:59.861810 DQ Delay:
6327 11:55:59.862365 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6328 11:55:59.865186 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6329 11:55:59.868400 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6330 11:55:59.871731 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6331 11:55:59.872272
6332 11:55:59.872634
6333 11:55:59.872975 ==
6334 11:55:59.875328 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 11:55:59.881862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 11:55:59.882458 ==
6337 11:55:59.882835
6338 11:55:59.883173
6339 11:55:59.883498 TX Vref Scan disable
6340 11:55:59.885260 == TX Byte 0 ==
6341 11:55:59.888286 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 11:55:59.891494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 11:55:59.894604 == TX Byte 1 ==
6344 11:55:59.898294 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6345 11:55:59.901285 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6346 11:55:59.905109 ==
6347 11:55:59.907932 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 11:55:59.911579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 11:55:59.912056 ==
6350 11:55:59.912432
6351 11:55:59.912776
6352 11:55:59.914646 TX Vref Scan disable
6353 11:55:59.915135 == TX Byte 0 ==
6354 11:55:59.918261 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 11:55:59.924426 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 11:55:59.924897 == TX Byte 1 ==
6357 11:55:59.927988 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 11:55:59.934501 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 11:55:59.935050
6360 11:55:59.935424 [DATLAT]
6361 11:55:59.935769 Freq=400, CH0 RK0
6362 11:55:59.936099
6363 11:55:59.938000 DATLAT Default: 0xf
6364 11:55:59.941341 0, 0xFFFF, sum = 0
6365 11:55:59.941914 1, 0xFFFF, sum = 0
6366 11:55:59.944363 2, 0xFFFF, sum = 0
6367 11:55:59.944841 3, 0xFFFF, sum = 0
6368 11:55:59.947933 4, 0xFFFF, sum = 0
6369 11:55:59.948414 5, 0xFFFF, sum = 0
6370 11:55:59.951038 6, 0xFFFF, sum = 0
6371 11:55:59.951516 7, 0xFFFF, sum = 0
6372 11:55:59.954255 8, 0xFFFF, sum = 0
6373 11:55:59.954791 9, 0xFFFF, sum = 0
6374 11:55:59.958088 10, 0xFFFF, sum = 0
6375 11:55:59.958714 11, 0xFFFF, sum = 0
6376 11:55:59.961287 12, 0xFFFF, sum = 0
6377 11:55:59.961853 13, 0x0, sum = 1
6378 11:55:59.964489 14, 0x0, sum = 2
6379 11:55:59.965063 15, 0x0, sum = 3
6380 11:55:59.967870 16, 0x0, sum = 4
6381 11:55:59.968345 best_step = 14
6382 11:55:59.968714
6383 11:55:59.969058 ==
6384 11:55:59.971055 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 11:55:59.974427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 11:55:59.978118 ==
6387 11:55:59.978625 RX Vref Scan: 1
6388 11:55:59.979001
6389 11:55:59.981353 RX Vref 0 -> 0, step: 1
6390 11:55:59.981818
6391 11:55:59.984624 RX Delay -327 -> 252, step: 8
6392 11:55:59.985190
6393 11:55:59.988279 Set Vref, RX VrefLevel [Byte0]: 58
6394 11:55:59.991710 [Byte1]: 52
6395 11:55:59.992278
6396 11:55:59.994289 Final RX Vref Byte 0 = 58 to rank0
6397 11:55:59.998470 Final RX Vref Byte 1 = 52 to rank0
6398 11:56:00.001225 Final RX Vref Byte 0 = 58 to rank1
6399 11:56:00.004535 Final RX Vref Byte 1 = 52 to rank1==
6400 11:56:00.007907 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 11:56:00.011310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 11:56:00.011880 ==
6403 11:56:00.014547 DQS Delay:
6404 11:56:00.015110 DQS0 = 28, DQS1 = 48
6405 11:56:00.017859 DQM Delay:
6406 11:56:00.018473 DQM0 = 12, DQM1 = 14
6407 11:56:00.018865 DQ Delay:
6408 11:56:00.021035 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6409 11:56:00.024570 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6410 11:56:00.027627 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6411 11:56:00.030997 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6412 11:56:00.031671
6413 11:56:00.032053
6414 11:56:00.040712 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6415 11:56:00.044289 CH0 RK0: MR19=C0C, MR18=A9A2
6416 11:56:00.047566 CH0_RK0: MR19=0xC0C, MR18=0xA9A2, DQSOSC=388, MR23=63, INC=392, DEC=261
6417 11:56:00.050609 ==
6418 11:56:00.051077 Dram Type= 6, Freq= 0, CH_0, rank 1
6419 11:56:00.057542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 11:56:00.058114 ==
6421 11:56:00.060789 [Gating] SW mode calibration
6422 11:56:00.067592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 11:56:00.070824 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6424 11:56:00.077671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 11:56:00.081295 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 11:56:00.084451 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 11:56:00.090834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 11:56:00.093924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 11:56:00.097596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 11:56:00.103975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 11:56:00.107600 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 11:56:00.111239 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 11:56:00.114115 Total UI for P1: 0, mck2ui 16
6434 11:56:00.117608 best dqsien dly found for B0: ( 0, 14, 24)
6435 11:56:00.120635 Total UI for P1: 0, mck2ui 16
6436 11:56:00.123916 best dqsien dly found for B1: ( 0, 14, 24)
6437 11:56:00.127331 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6438 11:56:00.131192 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6439 11:56:00.131787
6440 11:56:00.137145 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 11:56:00.140324 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 11:56:00.140804 [Gating] SW calibration Done
6443 11:56:00.143568 ==
6444 11:56:00.147169 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 11:56:00.150562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 11:56:00.151127 ==
6447 11:56:00.151502 RX Vref Scan: 0
6448 11:56:00.151846
6449 11:56:00.153445 RX Vref 0 -> 0, step: 1
6450 11:56:00.154060
6451 11:56:00.156728 RX Delay -410 -> 252, step: 16
6452 11:56:00.160247 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6453 11:56:00.163704 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6454 11:56:00.170701 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6455 11:56:00.173407 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6456 11:56:00.177594 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6457 11:56:00.180136 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6458 11:56:00.186931 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6459 11:56:00.190472 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6460 11:56:00.193668 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6461 11:56:00.197265 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6462 11:56:00.204083 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6463 11:56:00.207298 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6464 11:56:00.210744 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6465 11:56:00.213948 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6466 11:56:00.220359 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6467 11:56:00.223865 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6468 11:56:00.224433 ==
6469 11:56:00.227414 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 11:56:00.230647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 11:56:00.231214 ==
6472 11:56:00.233646 DQS Delay:
6473 11:56:00.234212 DQS0 = 27, DQS1 = 43
6474 11:56:00.237323 DQM Delay:
6475 11:56:00.237889 DQM0 = 9, DQM1 = 14
6476 11:56:00.238264 DQ Delay:
6477 11:56:00.240546 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6478 11:56:00.243769 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6479 11:56:00.246681 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6480 11:56:00.250477 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6481 11:56:00.251048
6482 11:56:00.251425
6483 11:56:00.251772 ==
6484 11:56:00.253460 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 11:56:00.260069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 11:56:00.260646 ==
6487 11:56:00.261032
6488 11:56:00.261378
6489 11:56:00.261708 TX Vref Scan disable
6490 11:56:00.263577 == TX Byte 0 ==
6491 11:56:00.266498 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6492 11:56:00.269896 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6493 11:56:00.273069 == TX Byte 1 ==
6494 11:56:00.276567 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6495 11:56:00.279767 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6496 11:56:00.280238 ==
6497 11:56:00.283244 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 11:56:00.289969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 11:56:00.290594 ==
6500 11:56:00.290982
6501 11:56:00.291332
6502 11:56:00.291670 TX Vref Scan disable
6503 11:56:00.293179 == TX Byte 0 ==
6504 11:56:00.296833 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6505 11:56:00.300370 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6506 11:56:00.303161 == TX Byte 1 ==
6507 11:56:00.306616 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6508 11:56:00.310083 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6509 11:56:00.310709
6510 11:56:00.313477 [DATLAT]
6511 11:56:00.314045 Freq=400, CH0 RK1
6512 11:56:00.314473
6513 11:56:00.316711 DATLAT Default: 0xe
6514 11:56:00.317279 0, 0xFFFF, sum = 0
6515 11:56:00.319699 1, 0xFFFF, sum = 0
6516 11:56:00.320329 2, 0xFFFF, sum = 0
6517 11:56:00.323291 3, 0xFFFF, sum = 0
6518 11:56:00.323862 4, 0xFFFF, sum = 0
6519 11:56:00.326893 5, 0xFFFF, sum = 0
6520 11:56:00.327465 6, 0xFFFF, sum = 0
6521 11:56:00.330051 7, 0xFFFF, sum = 0
6522 11:56:00.330661 8, 0xFFFF, sum = 0
6523 11:56:00.333358 9, 0xFFFF, sum = 0
6524 11:56:00.333936 10, 0xFFFF, sum = 0
6525 11:56:00.336503 11, 0xFFFF, sum = 0
6526 11:56:00.337033 12, 0xFFFF, sum = 0
6527 11:56:00.339681 13, 0x0, sum = 1
6528 11:56:00.340164 14, 0x0, sum = 2
6529 11:56:00.343213 15, 0x0, sum = 3
6530 11:56:00.343791 16, 0x0, sum = 4
6531 11:56:00.346271 best_step = 14
6532 11:56:00.346784
6533 11:56:00.347164 ==
6534 11:56:00.350115 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 11:56:00.353338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 11:56:00.353912 ==
6537 11:56:00.356610 RX Vref Scan: 0
6538 11:56:00.357177
6539 11:56:00.357560 RX Vref 0 -> 0, step: 1
6540 11:56:00.357913
6541 11:56:00.359819 RX Delay -327 -> 252, step: 8
6542 11:56:00.367688 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6543 11:56:00.370912 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6544 11:56:00.374337 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6545 11:56:00.378112 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6546 11:56:00.384707 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6547 11:56:00.388401 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6548 11:56:00.391104 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6549 11:56:00.394330 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6550 11:56:00.401272 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6551 11:56:00.404410 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6552 11:56:00.407677 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6553 11:56:00.410835 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6554 11:56:00.417747 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6555 11:56:00.420828 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6556 11:56:00.424550 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6557 11:56:00.427893 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6558 11:56:00.431092 ==
6559 11:56:00.434579 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 11:56:00.437675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 11:56:00.438242 ==
6562 11:56:00.438661 DQS Delay:
6563 11:56:00.440954 DQS0 = 28, DQS1 = 44
6564 11:56:00.441520 DQM Delay:
6565 11:56:00.444044 DQM0 = 10, DQM1 = 16
6566 11:56:00.444515 DQ Delay:
6567 11:56:00.447394 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6568 11:56:00.450999 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6569 11:56:00.454178 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6570 11:56:00.457507 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6571 11:56:00.458073
6572 11:56:00.458487
6573 11:56:00.464343 [DQSOSCAuto] RK1, (LSB)MR18= 0xb96c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6574 11:56:00.467705 CH0 RK1: MR19=C0C, MR18=B96C
6575 11:56:00.474192 CH0_RK1: MR19=0xC0C, MR18=0xB96C, DQSOSC=386, MR23=63, INC=396, DEC=264
6576 11:56:00.477445 [RxdqsGatingPostProcess] freq 400
6577 11:56:00.481322 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6578 11:56:00.484276 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 11:56:00.487240 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 11:56:00.491008 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 11:56:00.494222 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 11:56:00.497424 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 11:56:00.500906 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 11:56:00.503898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 11:56:00.507536 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 11:56:00.510831 Pre-setting of DQS Precalculation
6587 11:56:00.514258 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6588 11:56:00.517313 ==
6589 11:56:00.520677 Dram Type= 6, Freq= 0, CH_1, rank 0
6590 11:56:00.524042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 11:56:00.524623 ==
6592 11:56:00.527958 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6593 11:56:00.534460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6594 11:56:00.537153 [CA 0] Center 36 (8~64) winsize 57
6595 11:56:00.540815 [CA 1] Center 36 (8~64) winsize 57
6596 11:56:00.543848 [CA 2] Center 36 (8~64) winsize 57
6597 11:56:00.546920 [CA 3] Center 36 (8~64) winsize 57
6598 11:56:00.550438 [CA 4] Center 36 (8~64) winsize 57
6599 11:56:00.553904 [CA 5] Center 36 (8~64) winsize 57
6600 11:56:00.554528
6601 11:56:00.557805 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6602 11:56:00.558428
6603 11:56:00.560609 [CATrainingPosCal] consider 1 rank data
6604 11:56:00.564136 u2DelayCellTimex100 = 270/100 ps
6605 11:56:00.567202 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 11:56:00.570100 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 11:56:00.574114 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 11:56:00.576899 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:56:00.583965 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:56:00.586983 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:56:00.587482
6612 11:56:00.590180 CA PerBit enable=1, Macro0, CA PI delay=36
6613 11:56:00.590683
6614 11:56:00.593506 [CBTSetCACLKResult] CA Dly = 36
6615 11:56:00.593981 CS Dly: 1 (0~32)
6616 11:56:00.594549 ==
6617 11:56:00.596537 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 11:56:00.603745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 11:56:00.604338 ==
6620 11:56:00.607049 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 11:56:00.613752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 11:56:00.617044 [CA 0] Center 36 (8~64) winsize 57
6623 11:56:00.620335 [CA 1] Center 36 (8~64) winsize 57
6624 11:56:00.623852 [CA 2] Center 36 (8~64) winsize 57
6625 11:56:00.626778 [CA 3] Center 36 (8~64) winsize 57
6626 11:56:00.630151 [CA 4] Center 36 (8~64) winsize 57
6627 11:56:00.633590 [CA 5] Center 36 (8~64) winsize 57
6628 11:56:00.634172
6629 11:56:00.636961 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 11:56:00.637541
6631 11:56:00.640232 [CATrainingPosCal] consider 2 rank data
6632 11:56:00.643279 u2DelayCellTimex100 = 270/100 ps
6633 11:56:00.646587 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:56:00.650120 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:56:00.653660 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:56:00.657121 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:56:00.660008 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:56:00.663597 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:56:00.664169
6640 11:56:00.670589 CA PerBit enable=1, Macro0, CA PI delay=36
6641 11:56:00.671159
6642 11:56:00.671537 [CBTSetCACLKResult] CA Dly = 36
6643 11:56:00.673470 CS Dly: 1 (0~32)
6644 11:56:00.674035
6645 11:56:00.676295 ----->DramcWriteLeveling(PI) begin...
6646 11:56:00.676793 ==
6647 11:56:00.680031 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 11:56:00.683078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 11:56:00.683560 ==
6650 11:56:00.686360 Write leveling (Byte 0): 40 => 8
6651 11:56:00.690136 Write leveling (Byte 1): 32 => 0
6652 11:56:00.693060 DramcWriteLeveling(PI) end<-----
6653 11:56:00.693686
6654 11:56:00.694092 ==
6655 11:56:00.696506 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 11:56:00.700198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 11:56:00.703182 ==
6658 11:56:00.703653 [Gating] SW mode calibration
6659 11:56:00.709920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6660 11:56:00.716643 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6661 11:56:00.719828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 11:56:00.726515 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 11:56:00.730115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 11:56:00.733208 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 11:56:00.739721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 11:56:00.742921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 11:56:00.746670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 11:56:00.753872 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:56:00.756847 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 11:56:00.760433 Total UI for P1: 0, mck2ui 16
6671 11:56:00.763161 best dqsien dly found for B0: ( 0, 14, 24)
6672 11:56:00.766834 Total UI for P1: 0, mck2ui 16
6673 11:56:00.769756 best dqsien dly found for B1: ( 0, 14, 24)
6674 11:56:00.773007 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6675 11:56:00.776132 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6676 11:56:00.776603
6677 11:56:00.779581 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 11:56:00.782773 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 11:56:00.786091 [Gating] SW calibration Done
6680 11:56:00.786595 ==
6681 11:56:00.789561 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 11:56:00.792784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 11:56:00.796215 ==
6684 11:56:00.796779 RX Vref Scan: 0
6685 11:56:00.797159
6686 11:56:00.799186 RX Vref 0 -> 0, step: 1
6687 11:56:00.799658
6688 11:56:00.803088 RX Delay -410 -> 252, step: 16
6689 11:56:00.806365 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6690 11:56:00.809585 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6691 11:56:00.812511 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6692 11:56:00.819663 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6693 11:56:00.822493 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6694 11:56:00.825936 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6695 11:56:00.829404 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6696 11:56:00.836176 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6697 11:56:00.839246 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6698 11:56:00.842550 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6699 11:56:00.846106 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6700 11:56:00.853089 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6701 11:56:00.856435 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6702 11:56:00.859330 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6703 11:56:00.862762 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6704 11:56:00.869654 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6705 11:56:00.870229 ==
6706 11:56:00.872996 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 11:56:00.875651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 11:56:00.876224 ==
6709 11:56:00.876792 DQS Delay:
6710 11:56:00.879015 DQS0 = 27, DQS1 = 43
6711 11:56:00.879481 DQM Delay:
6712 11:56:00.882284 DQM0 = 8, DQM1 = 16
6713 11:56:00.882808 DQ Delay:
6714 11:56:00.885474 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6715 11:56:00.889962 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6716 11:56:00.892127 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6717 11:56:00.895887 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6718 11:56:00.896465
6719 11:56:00.896840
6720 11:56:00.897186 ==
6721 11:56:00.898883 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 11:56:00.901957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 11:56:00.902455 ==
6724 11:56:00.902837
6725 11:56:00.903181
6726 11:56:00.905708 TX Vref Scan disable
6727 11:56:00.908977 == TX Byte 0 ==
6728 11:56:00.912098 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 11:56:00.915546 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 11:56:00.919263 == TX Byte 1 ==
6731 11:56:00.922283 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6732 11:56:00.925451 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6733 11:56:00.925917 ==
6734 11:56:00.928562 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 11:56:00.932473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 11:56:00.932992 ==
6737 11:56:00.935236
6738 11:56:00.935701
6739 11:56:00.936095 TX Vref Scan disable
6740 11:56:00.939085 == TX Byte 0 ==
6741 11:56:00.941914 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 11:56:00.945342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 11:56:00.948365 == TX Byte 1 ==
6744 11:56:00.952288 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6745 11:56:00.955241 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6746 11:56:00.955668
6747 11:56:00.958486 [DATLAT]
6748 11:56:00.958908 Freq=400, CH1 RK0
6749 11:56:00.959247
6750 11:56:00.961920 DATLAT Default: 0xf
6751 11:56:00.962340 0, 0xFFFF, sum = 0
6752 11:56:00.965335 1, 0xFFFF, sum = 0
6753 11:56:00.965865 2, 0xFFFF, sum = 0
6754 11:56:00.968518 3, 0xFFFF, sum = 0
6755 11:56:00.968947 4, 0xFFFF, sum = 0
6756 11:56:00.971974 5, 0xFFFF, sum = 0
6757 11:56:00.972507 6, 0xFFFF, sum = 0
6758 11:56:00.975197 7, 0xFFFF, sum = 0
6759 11:56:00.975626 8, 0xFFFF, sum = 0
6760 11:56:00.978456 9, 0xFFFF, sum = 0
6761 11:56:00.978892 10, 0xFFFF, sum = 0
6762 11:56:00.981639 11, 0xFFFF, sum = 0
6763 11:56:00.982068 12, 0xFFFF, sum = 0
6764 11:56:00.985128 13, 0x0, sum = 1
6765 11:56:00.985664 14, 0x0, sum = 2
6766 11:56:00.988512 15, 0x0, sum = 3
6767 11:56:00.989090 16, 0x0, sum = 4
6768 11:56:00.991521 best_step = 14
6769 11:56:00.991990
6770 11:56:00.992364 ==
6771 11:56:00.994768 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 11:56:00.998339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 11:56:00.998854 ==
6774 11:56:01.001553 RX Vref Scan: 1
6775 11:56:01.002015
6776 11:56:01.002417 RX Vref 0 -> 0, step: 1
6777 11:56:01.002783
6778 11:56:01.004829 RX Delay -327 -> 252, step: 8
6779 11:56:01.005297
6780 11:56:01.008228 Set Vref, RX VrefLevel [Byte0]: 53
6781 11:56:01.011615 [Byte1]: 58
6782 11:56:01.016337
6783 11:56:01.016901 Final RX Vref Byte 0 = 53 to rank0
6784 11:56:01.019713 Final RX Vref Byte 1 = 58 to rank0
6785 11:56:01.023390 Final RX Vref Byte 0 = 53 to rank1
6786 11:56:01.026066 Final RX Vref Byte 1 = 58 to rank1==
6787 11:56:01.029959 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 11:56:01.036337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 11:56:01.036772 ==
6790 11:56:01.037110 DQS Delay:
6791 11:56:01.037421 DQS0 = 28, DQS1 = 40
6792 11:56:01.039596 DQM Delay:
6793 11:56:01.040017 DQM0 = 8, DQM1 = 13
6794 11:56:01.043131 DQ Delay:
6795 11:56:01.043569 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6796 11:56:01.046355 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6797 11:56:01.049795 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6798 11:56:01.053244 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6799 11:56:01.053776
6800 11:56:01.054118
6801 11:56:01.063054 [DQSOSCAuto] RK0, (LSB)MR18= 0x95d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6802 11:56:01.066484 CH1 RK0: MR19=C0C, MR18=95D0
6803 11:56:01.073263 CH1_RK0: MR19=0xC0C, MR18=0x95D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6804 11:56:01.073789 ==
6805 11:56:01.076452 Dram Type= 6, Freq= 0, CH_1, rank 1
6806 11:56:01.079288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 11:56:01.079722 ==
6808 11:56:01.082971 [Gating] SW mode calibration
6809 11:56:01.089584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6810 11:56:01.092803 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6811 11:56:01.099532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 11:56:01.103013 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 11:56:01.105993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 11:56:01.112482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 11:56:01.116461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 11:56:01.119685 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 11:56:01.126109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 11:56:01.128975 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 11:56:01.133072 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 11:56:01.135705 Total UI for P1: 0, mck2ui 16
6821 11:56:01.139561 best dqsien dly found for B0: ( 0, 14, 24)
6822 11:56:01.142152 Total UI for P1: 0, mck2ui 16
6823 11:56:01.145484 best dqsien dly found for B1: ( 0, 14, 24)
6824 11:56:01.148913 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6825 11:56:01.152796 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6826 11:56:01.155580
6827 11:56:01.158974 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 11:56:01.162613 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 11:56:01.165856 [Gating] SW calibration Done
6830 11:56:01.166458 ==
6831 11:56:01.169029 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 11:56:01.172480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 11:56:01.173050 ==
6834 11:56:01.173426 RX Vref Scan: 0
6835 11:56:01.173771
6836 11:56:01.175846 RX Vref 0 -> 0, step: 1
6837 11:56:01.176319
6838 11:56:01.178767 RX Delay -410 -> 252, step: 16
6839 11:56:01.182669 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6840 11:56:01.189225 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6841 11:56:01.192632 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6842 11:56:01.195665 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6843 11:56:01.199244 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6844 11:56:01.202323 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6845 11:56:01.208997 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6846 11:56:01.212463 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6847 11:56:01.215997 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6848 11:56:01.218817 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6849 11:56:01.225699 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6850 11:56:01.228812 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6851 11:56:01.232178 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6852 11:56:01.239714 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6853 11:56:01.241870 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6854 11:56:01.245330 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6855 11:56:01.245916 ==
6856 11:56:01.248542 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 11:56:01.252245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 11:56:01.255462 ==
6859 11:56:01.255942 DQS Delay:
6860 11:56:01.256322 DQS0 = 35, DQS1 = 43
6861 11:56:01.259295 DQM Delay:
6862 11:56:01.259871 DQM0 = 17, DQM1 = 19
6863 11:56:01.261898 DQ Delay:
6864 11:56:01.265666 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6865 11:56:01.266245 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6866 11:56:01.269106 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6867 11:56:01.272290 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =32
6868 11:56:01.272871
6869 11:56:01.275755
6870 11:56:01.276329 ==
6871 11:56:01.278548 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 11:56:01.282289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 11:56:01.282911 ==
6874 11:56:01.283293
6875 11:56:01.283641
6876 11:56:01.285604 TX Vref Scan disable
6877 11:56:01.286077 == TX Byte 0 ==
6878 11:56:01.288932 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6879 11:56:01.295677 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6880 11:56:01.296245 == TX Byte 1 ==
6881 11:56:01.298671 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6882 11:56:01.305907 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6883 11:56:01.306523 ==
6884 11:56:01.308680 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 11:56:01.312322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 11:56:01.312902 ==
6887 11:56:01.313283
6888 11:56:01.313626
6889 11:56:01.315502 TX Vref Scan disable
6890 11:56:01.316070 == TX Byte 0 ==
6891 11:56:01.318996 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6892 11:56:01.325434 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6893 11:56:01.326029 == TX Byte 1 ==
6894 11:56:01.328435 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6895 11:56:01.335434 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6896 11:56:01.335998
6897 11:56:01.336376 [DATLAT]
6898 11:56:01.336726 Freq=400, CH1 RK1
6899 11:56:01.337066
6900 11:56:01.338857 DATLAT Default: 0xe
6901 11:56:01.339329 0, 0xFFFF, sum = 0
6902 11:56:01.341992 1, 0xFFFF, sum = 0
6903 11:56:01.342596 2, 0xFFFF, sum = 0
6904 11:56:01.345139 3, 0xFFFF, sum = 0
6905 11:56:01.345617 4, 0xFFFF, sum = 0
6906 11:56:01.348900 5, 0xFFFF, sum = 0
6907 11:56:01.352168 6, 0xFFFF, sum = 0
6908 11:56:01.352650 7, 0xFFFF, sum = 0
6909 11:56:01.355353 8, 0xFFFF, sum = 0
6910 11:56:01.355828 9, 0xFFFF, sum = 0
6911 11:56:01.358593 10, 0xFFFF, sum = 0
6912 11:56:01.359179 11, 0xFFFF, sum = 0
6913 11:56:01.361980 12, 0xFFFF, sum = 0
6914 11:56:01.362586 13, 0x0, sum = 1
6915 11:56:01.365796 14, 0x0, sum = 2
6916 11:56:01.366369 15, 0x0, sum = 3
6917 11:56:01.368941 16, 0x0, sum = 4
6918 11:56:01.369521 best_step = 14
6919 11:56:01.369900
6920 11:56:01.370244 ==
6921 11:56:01.371801 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 11:56:01.375315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 11:56:01.375884 ==
6924 11:56:01.378502 RX Vref Scan: 0
6925 11:56:01.379142
6926 11:56:01.382191 RX Vref 0 -> 0, step: 1
6927 11:56:01.382813
6928 11:56:01.383198 RX Delay -327 -> 252, step: 8
6929 11:56:01.390771 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6930 11:56:01.393971 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6931 11:56:01.398013 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6932 11:56:01.400981 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6933 11:56:01.407363 iDelay=217, Bit 4, Center -20 (-247 ~ 208) 456
6934 11:56:01.410591 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6935 11:56:01.413948 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6936 11:56:01.417348 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6937 11:56:01.424072 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6938 11:56:01.427086 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6939 11:56:01.430561 iDelay=217, Bit 10, Center -24 (-255 ~ 208) 464
6940 11:56:01.433975 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6941 11:56:01.440552 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6942 11:56:01.443483 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6943 11:56:01.447657 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6944 11:56:01.454018 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6945 11:56:01.454617 ==
6946 11:56:01.456853 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 11:56:01.460172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 11:56:01.460741 ==
6949 11:56:01.461118 DQS Delay:
6950 11:56:01.463646 DQS0 = 32, DQS1 = 40
6951 11:56:01.464394 DQM Delay:
6952 11:56:01.466895 DQM0 = 12, DQM1 = 14
6953 11:56:01.467363 DQ Delay:
6954 11:56:01.470338 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6955 11:56:01.473498 DQ4 =12, DQ5 =24, DQ6 =16, DQ7 =8
6956 11:56:01.476978 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6957 11:56:01.479923 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6958 11:56:01.480407
6959 11:56:01.480785
6960 11:56:01.486860 [DQSOSCAuto] RK1, (LSB)MR18= 0xad55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6961 11:56:01.489931 CH1 RK1: MR19=C0C, MR18=AD55
6962 11:56:01.496734 CH1_RK1: MR19=0xC0C, MR18=0xAD55, DQSOSC=388, MR23=63, INC=392, DEC=261
6963 11:56:01.500217 [RxdqsGatingPostProcess] freq 400
6964 11:56:01.506636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6965 11:56:01.509969 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 11:56:01.510557 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 11:56:01.513443 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 11:56:01.516293 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 11:56:01.519907 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 11:56:01.523273 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 11:56:01.526693 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 11:56:01.529865 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 11:56:01.532984 Pre-setting of DQS Precalculation
6974 11:56:01.539895 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6975 11:56:01.546485 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6976 11:56:01.553205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6977 11:56:01.553779
6978 11:56:01.554153
6979 11:56:01.556599 [Calibration Summary] 800 Mbps
6980 11:56:01.557068 CH 0, Rank 0
6981 11:56:01.559911 SW Impedance : PASS
6982 11:56:01.563087 DUTY Scan : NO K
6983 11:56:01.563559 ZQ Calibration : PASS
6984 11:56:01.566312 Jitter Meter : NO K
6985 11:56:01.569830 CBT Training : PASS
6986 11:56:01.570435 Write leveling : PASS
6987 11:56:01.572940 RX DQS gating : PASS
6988 11:56:01.573559 RX DQ/DQS(RDDQC) : PASS
6989 11:56:01.576579 TX DQ/DQS : PASS
6990 11:56:01.579889 RX DATLAT : PASS
6991 11:56:01.580498 RX DQ/DQS(Engine): PASS
6992 11:56:01.582915 TX OE : NO K
6993 11:56:01.583385 All Pass.
6994 11:56:01.583754
6995 11:56:01.586854 CH 0, Rank 1
6996 11:56:01.587317 SW Impedance : PASS
6997 11:56:01.589749 DUTY Scan : NO K
6998 11:56:01.593450 ZQ Calibration : PASS
6999 11:56:01.594025 Jitter Meter : NO K
7000 11:56:01.596600 CBT Training : PASS
7001 11:56:01.599760 Write leveling : NO K
7002 11:56:01.600328 RX DQS gating : PASS
7003 11:56:01.603156 RX DQ/DQS(RDDQC) : PASS
7004 11:56:01.606662 TX DQ/DQS : PASS
7005 11:56:01.607233 RX DATLAT : PASS
7006 11:56:01.609699 RX DQ/DQS(Engine): PASS
7007 11:56:01.613183 TX OE : NO K
7008 11:56:01.613753 All Pass.
7009 11:56:01.614126
7010 11:56:01.614529 CH 1, Rank 0
7011 11:56:01.616558 SW Impedance : PASS
7012 11:56:01.619767 DUTY Scan : NO K
7013 11:56:01.620335 ZQ Calibration : PASS
7014 11:56:01.623243 Jitter Meter : NO K
7015 11:56:01.623873 CBT Training : PASS
7016 11:56:01.626056 Write leveling : PASS
7017 11:56:01.629584 RX DQS gating : PASS
7018 11:56:01.630150 RX DQ/DQS(RDDQC) : PASS
7019 11:56:01.632674 TX DQ/DQS : PASS
7020 11:56:01.636190 RX DATLAT : PASS
7021 11:56:01.636759 RX DQ/DQS(Engine): PASS
7022 11:56:01.639377 TX OE : NO K
7023 11:56:01.639962 All Pass.
7024 11:56:01.640442
7025 11:56:01.642850 CH 1, Rank 1
7026 11:56:01.643415 SW Impedance : PASS
7027 11:56:01.645750 DUTY Scan : NO K
7028 11:56:01.649560 ZQ Calibration : PASS
7029 11:56:01.650073 Jitter Meter : NO K
7030 11:56:01.652716 CBT Training : PASS
7031 11:56:01.655986 Write leveling : NO K
7032 11:56:01.656449 RX DQS gating : PASS
7033 11:56:01.659160 RX DQ/DQS(RDDQC) : PASS
7034 11:56:01.662751 TX DQ/DQS : PASS
7035 11:56:01.663330 RX DATLAT : PASS
7036 11:56:01.665904 RX DQ/DQS(Engine): PASS
7037 11:56:01.669419 TX OE : NO K
7038 11:56:01.669992 All Pass.
7039 11:56:01.670370
7040 11:56:01.670750 DramC Write-DBI off
7041 11:56:01.672826 PER_BANK_REFRESH: Hybrid Mode
7042 11:56:01.675769 TX_TRACKING: ON
7043 11:56:01.682465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7044 11:56:01.686460 [FAST_K] Save calibration result to emmc
7045 11:56:01.692702 dramc_set_vcore_voltage set vcore to 725000
7046 11:56:01.693272 Read voltage for 1600, 0
7047 11:56:01.693647 Vio18 = 0
7048 11:56:01.695735 Vcore = 725000
7049 11:56:01.696202 Vdram = 0
7050 11:56:01.696568 Vddq = 0
7051 11:56:01.699490 Vmddr = 0
7052 11:56:01.702985 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7053 11:56:01.709516 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7054 11:56:01.713100 MEM_TYPE=3, freq_sel=13
7055 11:56:01.713666 sv_algorithm_assistance_LP4_3733
7056 11:56:01.719323 ============ PULL DRAM RESETB DOWN ============
7057 11:56:01.722901 ========== PULL DRAM RESETB DOWN end =========
7058 11:56:01.725985 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7059 11:56:01.728856 ===================================
7060 11:56:01.732549 LPDDR4 DRAM CONFIGURATION
7061 11:56:01.735791 ===================================
7062 11:56:01.739304 EX_ROW_EN[0] = 0x0
7063 11:56:01.739875 EX_ROW_EN[1] = 0x0
7064 11:56:01.743097 LP4Y_EN = 0x0
7065 11:56:01.743667 WORK_FSP = 0x1
7066 11:56:01.745799 WL = 0x5
7067 11:56:01.746265 RL = 0x5
7068 11:56:01.749026 BL = 0x2
7069 11:56:01.749636 RPST = 0x0
7070 11:56:01.752269 RD_PRE = 0x0
7071 11:56:01.752830 WR_PRE = 0x1
7072 11:56:01.755593 WR_PST = 0x1
7073 11:56:01.756060 DBI_WR = 0x0
7074 11:56:01.758767 DBI_RD = 0x0
7075 11:56:01.759235 OTF = 0x1
7076 11:56:01.762262 ===================================
7077 11:56:01.765613 ===================================
7078 11:56:01.769378 ANA top config
7079 11:56:01.772497 ===================================
7080 11:56:01.776250 DLL_ASYNC_EN = 0
7081 11:56:01.776818 ALL_SLAVE_EN = 0
7082 11:56:01.778849 NEW_RANK_MODE = 1
7083 11:56:01.782187 DLL_IDLE_MODE = 1
7084 11:56:01.785534 LP45_APHY_COMB_EN = 1
7085 11:56:01.786000 TX_ODT_DIS = 0
7086 11:56:01.789135 NEW_8X_MODE = 1
7087 11:56:01.792075 ===================================
7088 11:56:01.795739 ===================================
7089 11:56:01.798884 data_rate = 3200
7090 11:56:01.802209 CKR = 1
7091 11:56:01.805610 DQ_P2S_RATIO = 8
7092 11:56:01.808858 ===================================
7093 11:56:01.812688 CA_P2S_RATIO = 8
7094 11:56:01.813254 DQ_CA_OPEN = 0
7095 11:56:01.815713 DQ_SEMI_OPEN = 0
7096 11:56:01.818906 CA_SEMI_OPEN = 0
7097 11:56:01.822695 CA_FULL_RATE = 0
7098 11:56:01.825459 DQ_CKDIV4_EN = 0
7099 11:56:01.829172 CA_CKDIV4_EN = 0
7100 11:56:01.829741 CA_PREDIV_EN = 0
7101 11:56:01.832336 PH8_DLY = 12
7102 11:56:01.835302 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7103 11:56:01.839209 DQ_AAMCK_DIV = 4
7104 11:56:01.842212 CA_AAMCK_DIV = 4
7105 11:56:01.845294 CA_ADMCK_DIV = 4
7106 11:56:01.845867 DQ_TRACK_CA_EN = 0
7107 11:56:01.848711 CA_PICK = 1600
7108 11:56:01.851950 CA_MCKIO = 1600
7109 11:56:01.855331 MCKIO_SEMI = 0
7110 11:56:01.858583 PLL_FREQ = 3068
7111 11:56:01.861808 DQ_UI_PI_RATIO = 32
7112 11:56:01.865881 CA_UI_PI_RATIO = 0
7113 11:56:01.868547 ===================================
7114 11:56:01.872105 ===================================
7115 11:56:01.872575 memory_type:LPDDR4
7116 11:56:01.875692 GP_NUM : 10
7117 11:56:01.878679 SRAM_EN : 1
7118 11:56:01.879153 MD32_EN : 0
7119 11:56:01.881744 ===================================
7120 11:56:01.885765 [ANA_INIT] >>>>>>>>>>>>>>
7121 11:56:01.888621 <<<<<< [CONFIGURE PHASE]: ANA_TX
7122 11:56:01.892189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7123 11:56:01.895524 ===================================
7124 11:56:01.898507 data_rate = 3200,PCW = 0X7600
7125 11:56:01.901886 ===================================
7126 11:56:01.905358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7127 11:56:01.908972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 11:56:01.915487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 11:56:01.918437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7130 11:56:01.921790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7131 11:56:01.925213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7132 11:56:01.928562 [ANA_INIT] flow start
7133 11:56:01.931964 [ANA_INIT] PLL >>>>>>>>
7134 11:56:01.932532 [ANA_INIT] PLL <<<<<<<<
7135 11:56:01.935312 [ANA_INIT] MIDPI >>>>>>>>
7136 11:56:01.939944 [ANA_INIT] MIDPI <<<<<<<<
7137 11:56:01.941698 [ANA_INIT] DLL >>>>>>>>
7138 11:56:01.942164 [ANA_INIT] DLL <<<<<<<<
7139 11:56:01.945165 [ANA_INIT] flow end
7140 11:56:01.948099 ============ LP4 DIFF to SE enter ============
7141 11:56:01.951801 ============ LP4 DIFF to SE exit ============
7142 11:56:01.955166 [ANA_INIT] <<<<<<<<<<<<<
7143 11:56:01.958241 [Flow] Enable top DCM control >>>>>
7144 11:56:01.962034 [Flow] Enable top DCM control <<<<<
7145 11:56:01.964663 Enable DLL master slave shuffle
7146 11:56:01.968485 ==============================================================
7147 11:56:01.971450 Gating Mode config
7148 11:56:01.978346 ==============================================================
7149 11:56:01.978856 Config description:
7150 11:56:01.988570 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7151 11:56:01.994911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7152 11:56:01.998300 SELPH_MODE 0: By rank 1: By Phase
7153 11:56:02.004759 ==============================================================
7154 11:56:02.008219 GAT_TRACK_EN = 1
7155 11:56:02.011906 RX_GATING_MODE = 2
7156 11:56:02.014840 RX_GATING_TRACK_MODE = 2
7157 11:56:02.018002 SELPH_MODE = 1
7158 11:56:02.021712 PICG_EARLY_EN = 1
7159 11:56:02.024760 VALID_LAT_VALUE = 1
7160 11:56:02.028309 ==============================================================
7161 11:56:02.031782 Enter into Gating configuration >>>>
7162 11:56:02.034843 Exit from Gating configuration <<<<
7163 11:56:02.038220 Enter into DVFS_PRE_config >>>>>
7164 11:56:02.051948 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7165 11:56:02.054772 Exit from DVFS_PRE_config <<<<<
7166 11:56:02.055295 Enter into PICG configuration >>>>
7167 11:56:02.058196 Exit from PICG configuration <<<<
7168 11:56:02.061436 [RX_INPUT] configuration >>>>>
7169 11:56:02.064770 [RX_INPUT] configuration <<<<<
7170 11:56:02.071792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7171 11:56:02.074681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7172 11:56:02.081403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 11:56:02.089227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 11:56:02.094556 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 11:56:02.101477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 11:56:02.104575 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7177 11:56:02.107783 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7178 11:56:02.111533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7179 11:56:02.118266 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7180 11:56:02.121590 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7181 11:56:02.125077 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 11:56:02.128094 ===================================
7183 11:56:02.131822 LPDDR4 DRAM CONFIGURATION
7184 11:56:02.135241 ===================================
7185 11:56:02.135830 EX_ROW_EN[0] = 0x0
7186 11:56:02.137939 EX_ROW_EN[1] = 0x0
7187 11:56:02.141395 LP4Y_EN = 0x0
7188 11:56:02.141976 WORK_FSP = 0x1
7189 11:56:02.144959 WL = 0x5
7190 11:56:02.145660 RL = 0x5
7191 11:56:02.147756 BL = 0x2
7192 11:56:02.148250 RPST = 0x0
7193 11:56:02.151624 RD_PRE = 0x0
7194 11:56:02.152113 WR_PRE = 0x1
7195 11:56:02.154652 WR_PST = 0x1
7196 11:56:02.155216 DBI_WR = 0x0
7197 11:56:02.157985 DBI_RD = 0x0
7198 11:56:02.158618 OTF = 0x1
7199 11:56:02.161530 ===================================
7200 11:56:02.164640 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7201 11:56:02.171265 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7202 11:56:02.174520 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 11:56:02.178228 ===================================
7204 11:56:02.181188 LPDDR4 DRAM CONFIGURATION
7205 11:56:02.184375 ===================================
7206 11:56:02.184867 EX_ROW_EN[0] = 0x10
7207 11:56:02.188181 EX_ROW_EN[1] = 0x0
7208 11:56:02.188955 LP4Y_EN = 0x0
7209 11:56:02.191243 WORK_FSP = 0x1
7210 11:56:02.194454 WL = 0x5
7211 11:56:02.195042 RL = 0x5
7212 11:56:02.197858 BL = 0x2
7213 11:56:02.198579 RPST = 0x0
7214 11:56:02.201430 RD_PRE = 0x0
7215 11:56:02.202010 WR_PRE = 0x1
7216 11:56:02.204269 WR_PST = 0x1
7217 11:56:02.204782 DBI_WR = 0x0
7218 11:56:02.207531 DBI_RD = 0x0
7219 11:56:02.208021 OTF = 0x1
7220 11:56:02.210844 ===================================
7221 11:56:02.217914 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7222 11:56:02.218527 ==
7223 11:56:02.220944 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 11:56:02.224282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7225 11:56:02.224758 ==
7226 11:56:02.228031 [Duty_Offset_Calibration]
7227 11:56:02.231363 B0:2 B1:0 CA:1
7228 11:56:02.231934
7229 11:56:02.234917 [DutyScan_Calibration_Flow] k_type=0
7230 11:56:02.242348
7231 11:56:02.242965 ==CLK 0==
7232 11:56:02.245343 Final CLK duty delay cell = -4
7233 11:56:02.248479 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7234 11:56:02.251960 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7235 11:56:02.255276 [-4] AVG Duty = 4922%(X100)
7236 11:56:02.255849
7237 11:56:02.258666 CH0 CLK Duty spec in!! Max-Min= 218%
7238 11:56:02.262209 [DutyScan_Calibration_Flow] ====Done====
7239 11:56:02.262850
7240 11:56:02.264984 [DutyScan_Calibration_Flow] k_type=1
7241 11:56:02.281600
7242 11:56:02.282181 ==DQS 0 ==
7243 11:56:02.284762 Final DQS duty delay cell = 0
7244 11:56:02.288291 [0] MAX Duty = 5249%(X100), DQS PI = 32
7245 11:56:02.291315 [0] MIN Duty = 4969%(X100), DQS PI = 0
7246 11:56:02.294782 [0] AVG Duty = 5109%(X100)
7247 11:56:02.295383
7248 11:56:02.295979 ==DQS 1 ==
7249 11:56:02.298046 Final DQS duty delay cell = -4
7250 11:56:02.301123 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7251 11:56:02.304916 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7252 11:56:02.307954 [-4] AVG Duty = 5000%(X100)
7253 11:56:02.308425
7254 11:56:02.311244 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7255 11:56:02.311879
7256 11:56:02.314630 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7257 11:56:02.318481 [DutyScan_Calibration_Flow] ====Done====
7258 11:56:02.319047
7259 11:56:02.321585 [DutyScan_Calibration_Flow] k_type=3
7260 11:56:02.339227
7261 11:56:02.339790 ==DQM 0 ==
7262 11:56:02.342172 Final DQM duty delay cell = 0
7263 11:56:02.346000 [0] MAX Duty = 5093%(X100), DQS PI = 26
7264 11:56:02.348608 [0] MIN Duty = 4813%(X100), DQS PI = 50
7265 11:56:02.352303 [0] AVG Duty = 4953%(X100)
7266 11:56:02.352879
7267 11:56:02.353255 ==DQM 1 ==
7268 11:56:02.355331 Final DQM duty delay cell = 0
7269 11:56:02.358854 [0] MAX Duty = 5249%(X100), DQS PI = 42
7270 11:56:02.362363 [0] MIN Duty = 5031%(X100), DQS PI = 10
7271 11:56:02.365517 [0] AVG Duty = 5140%(X100)
7272 11:56:02.366092
7273 11:56:02.368922 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7274 11:56:02.369496
7275 11:56:02.371998 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7276 11:56:02.375820 [DutyScan_Calibration_Flow] ====Done====
7277 11:56:02.376393
7278 11:56:02.378959 [DutyScan_Calibration_Flow] k_type=2
7279 11:56:02.396354
7280 11:56:02.396970 ==DQ 0 ==
7281 11:56:02.399404 Final DQ duty delay cell = 0
7282 11:56:02.403224 [0] MAX Duty = 5124%(X100), DQS PI = 34
7283 11:56:02.406007 [0] MIN Duty = 5000%(X100), DQS PI = 0
7284 11:56:02.406660 [0] AVG Duty = 5062%(X100)
7285 11:56:02.407051
7286 11:56:02.409337 ==DQ 1 ==
7287 11:56:02.412790 Final DQ duty delay cell = 0
7288 11:56:02.416158 [0] MAX Duty = 4969%(X100), DQS PI = 50
7289 11:56:02.419163 [0] MIN Duty = 4875%(X100), DQS PI = 10
7290 11:56:02.419637 [0] AVG Duty = 4922%(X100)
7291 11:56:02.420013
7292 11:56:02.422980 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7293 11:56:02.425757
7294 11:56:02.429073 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7295 11:56:02.432726 [DutyScan_Calibration_Flow] ====Done====
7296 11:56:02.433187 ==
7297 11:56:02.435821 Dram Type= 6, Freq= 0, CH_1, rank 0
7298 11:56:02.439028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 11:56:02.439498 ==
7300 11:56:02.442836 [Duty_Offset_Calibration]
7301 11:56:02.443299 B0:0 B1:-1 CA:2
7302 11:56:02.443662
7303 11:56:02.445947 [DutyScan_Calibration_Flow] k_type=0
7304 11:56:02.456538
7305 11:56:02.457100 ==CLK 0==
7306 11:56:02.459514 Final CLK duty delay cell = 0
7307 11:56:02.463066 [0] MAX Duty = 5156%(X100), DQS PI = 10
7308 11:56:02.466728 [0] MIN Duty = 4938%(X100), DQS PI = 44
7309 11:56:02.467300 [0] AVG Duty = 5047%(X100)
7310 11:56:02.469746
7311 11:56:02.472736 CH1 CLK Duty spec in!! Max-Min= 218%
7312 11:56:02.476364 [DutyScan_Calibration_Flow] ====Done====
7313 11:56:02.476934
7314 11:56:02.479372 [DutyScan_Calibration_Flow] k_type=1
7315 11:56:02.495911
7316 11:56:02.496502 ==DQS 0 ==
7317 11:56:02.499624 Final DQS duty delay cell = 0
7318 11:56:02.502877 [0] MAX Duty = 5093%(X100), DQS PI = 26
7319 11:56:02.505754 [0] MIN Duty = 4969%(X100), DQS PI = 2
7320 11:56:02.506218 [0] AVG Duty = 5031%(X100)
7321 11:56:02.509480
7322 11:56:02.510034 ==DQS 1 ==
7323 11:56:02.512956 Final DQS duty delay cell = 0
7324 11:56:02.515874 [0] MAX Duty = 5187%(X100), DQS PI = 0
7325 11:56:02.519395 [0] MIN Duty = 4844%(X100), DQS PI = 32
7326 11:56:02.519860 [0] AVG Duty = 5015%(X100)
7327 11:56:02.522980
7328 11:56:02.526260 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7329 11:56:02.526781
7330 11:56:02.529503 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7331 11:56:02.532836 [DutyScan_Calibration_Flow] ====Done====
7332 11:56:02.533402
7333 11:56:02.536214 [DutyScan_Calibration_Flow] k_type=3
7334 11:56:02.553914
7335 11:56:02.554522 ==DQM 0 ==
7336 11:56:02.556965 Final DQM duty delay cell = 4
7337 11:56:02.560076 [4] MAX Duty = 5125%(X100), DQS PI = 6
7338 11:56:02.563623 [4] MIN Duty = 5000%(X100), DQS PI = 44
7339 11:56:02.564097 [4] AVG Duty = 5062%(X100)
7340 11:56:02.567160
7341 11:56:02.567738 ==DQM 1 ==
7342 11:56:02.570169 Final DQM duty delay cell = 0
7343 11:56:02.573760 [0] MAX Duty = 5281%(X100), DQS PI = 60
7344 11:56:02.577135 [0] MIN Duty = 4844%(X100), DQS PI = 34
7345 11:56:02.580408 [0] AVG Duty = 5062%(X100)
7346 11:56:02.580998
7347 11:56:02.583806 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7348 11:56:02.584389
7349 11:56:02.586873 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7350 11:56:02.590187 [DutyScan_Calibration_Flow] ====Done====
7351 11:56:02.590812
7352 11:56:02.593485 [DutyScan_Calibration_Flow] k_type=2
7353 11:56:02.610441
7354 11:56:02.611039 ==DQ 0 ==
7355 11:56:02.613826 Final DQ duty delay cell = 0
7356 11:56:02.617376 [0] MAX Duty = 5093%(X100), DQS PI = 18
7357 11:56:02.620524 [0] MIN Duty = 4969%(X100), DQS PI = 46
7358 11:56:02.621010 [0] AVG Duty = 5031%(X100)
7359 11:56:02.623566
7360 11:56:02.624036 ==DQ 1 ==
7361 11:56:02.626892 Final DQ duty delay cell = 0
7362 11:56:02.630115 [0] MAX Duty = 5031%(X100), DQS PI = 0
7363 11:56:02.633636 [0] MIN Duty = 4844%(X100), DQS PI = 32
7364 11:56:02.634193 [0] AVG Duty = 4937%(X100)
7365 11:56:02.634613
7366 11:56:02.637219 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7367 11:56:02.640304
7368 11:56:02.643829 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7369 11:56:02.646945 [DutyScan_Calibration_Flow] ====Done====
7370 11:56:02.650602 nWR fixed to 30
7371 11:56:02.651173 [ModeRegInit_LP4] CH0 RK0
7372 11:56:02.653716 [ModeRegInit_LP4] CH0 RK1
7373 11:56:02.657225 [ModeRegInit_LP4] CH1 RK0
7374 11:56:02.660006 [ModeRegInit_LP4] CH1 RK1
7375 11:56:02.660477 match AC timing 5
7376 11:56:02.664177 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7377 11:56:02.670812 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7378 11:56:02.673315 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7379 11:56:02.680377 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7380 11:56:02.683833 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7381 11:56:02.684401 [MiockJmeterHQA]
7382 11:56:02.684778
7383 11:56:02.686780 [DramcMiockJmeter] u1RxGatingPI = 0
7384 11:56:02.690251 0 : 4365, 4140
7385 11:56:02.690870 4 : 4252, 4027
7386 11:56:02.691254 8 : 4365, 4140
7387 11:56:02.693540 12 : 4258, 4030
7388 11:56:02.694113 16 : 4253, 4026
7389 11:56:02.697132 20 : 4363, 4137
7390 11:56:02.697704 24 : 4255, 4029
7391 11:56:02.700000 28 : 4363, 4138
7392 11:56:02.700476 32 : 4252, 4027
7393 11:56:02.704490 36 : 4252, 4027
7394 11:56:02.705061 40 : 4257, 4029
7395 11:56:02.705443 44 : 4252, 4027
7396 11:56:02.706555 48 : 4365, 4140
7397 11:56:02.707035 52 : 4363, 4137
7398 11:56:02.710107 56 : 4252, 4029
7399 11:56:02.710730 60 : 4252, 4030
7400 11:56:02.713499 64 : 4360, 4137
7401 11:56:02.714075 68 : 4250, 4027
7402 11:56:02.716521 72 : 4363, 4140
7403 11:56:02.717001 76 : 4255, 4029
7404 11:56:02.717383 80 : 4249, 4027
7405 11:56:02.719816 84 : 4249, 4027
7406 11:56:02.720292 88 : 4250, 3643
7407 11:56:02.723579 92 : 4360, 0
7408 11:56:02.724059 96 : 4363, 0
7409 11:56:02.724440 100 : 4252, 0
7410 11:56:02.726556 104 : 4361, 0
7411 11:56:02.727094 108 : 4361, 0
7412 11:56:02.729758 112 : 4250, 0
7413 11:56:02.730242 116 : 4255, 0
7414 11:56:02.730680 120 : 4253, 0
7415 11:56:02.733592 124 : 4363, 0
7416 11:56:02.734178 128 : 4255, 0
7417 11:56:02.736423 132 : 4250, 0
7418 11:56:02.736909 136 : 4360, 0
7419 11:56:02.737297 140 : 4250, 0
7420 11:56:02.740065 144 : 4253, 0
7421 11:56:02.740654 148 : 4250, 0
7422 11:56:02.741043 152 : 4252, 0
7423 11:56:02.742979 156 : 4365, 0
7424 11:56:02.743465 160 : 4253, 0
7425 11:56:02.746577 164 : 4250, 0
7426 11:56:02.747057 168 : 4257, 0
7427 11:56:02.747442 172 : 4361, 0
7428 11:56:02.749916 176 : 4249, 0
7429 11:56:02.750430 180 : 4250, 0
7430 11:56:02.753073 184 : 4250, 0
7431 11:56:02.753583 188 : 4360, 0
7432 11:56:02.753962 192 : 4250, 0
7433 11:56:02.756769 196 : 4253, 0
7434 11:56:02.757359 200 : 4249, 11
7435 11:56:02.759553 204 : 4253, 2488
7436 11:56:02.760034 208 : 4250, 4027
7437 11:56:02.762760 212 : 4252, 4030
7438 11:56:02.763245 216 : 4250, 4027
7439 11:56:02.766437 220 : 4252, 4027
7440 11:56:02.767020 224 : 4253, 4029
7441 11:56:02.767409 228 : 4250, 4027
7442 11:56:02.769685 232 : 4363, 4140
7443 11:56:02.770269 236 : 4250, 4026
7444 11:56:02.773001 240 : 4250, 4027
7445 11:56:02.773588 244 : 4249, 4027
7446 11:56:02.776330 248 : 4363, 4140
7447 11:56:02.776920 252 : 4360, 4137
7448 11:56:02.779635 256 : 4250, 4026
7449 11:56:02.780224 260 : 4363, 4140
7450 11:56:02.783041 264 : 4252, 4030
7451 11:56:02.783627 268 : 4249, 4027
7452 11:56:02.786304 272 : 4250, 4027
7453 11:56:02.786937 276 : 4253, 4029
7454 11:56:02.789334 280 : 4250, 4027
7455 11:56:02.789814 284 : 4363, 4140
7456 11:56:02.790198 288 : 4250, 4027
7457 11:56:02.793051 292 : 4250, 4027
7458 11:56:02.793636 296 : 4250, 4027
7459 11:56:02.796844 300 : 4363, 4140
7460 11:56:02.797429 304 : 4360, 4137
7461 11:56:02.799702 308 : 4247, 4025
7462 11:56:02.800289 312 : 4363, 4077
7463 11:56:02.803240 316 : 4252, 2186
7464 11:56:02.803826 320 : 4249, 2
7465 11:56:02.804211
7466 11:56:02.806227 MIOCK jitter meter ch=0
7467 11:56:02.806846
7468 11:56:02.810100 1T = (320-92) = 228 dly cells
7469 11:56:02.812867 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7470 11:56:02.813450 ==
7471 11:56:02.816023 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 11:56:02.822991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 11:56:02.823576 ==
7474 11:56:02.826037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 11:56:02.832802 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 11:56:02.835818 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 11:56:02.842740 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 11:56:02.850550 [CA 0] Center 42 (12~73) winsize 62
7479 11:56:02.853760 [CA 1] Center 43 (13~73) winsize 61
7480 11:56:02.857319 [CA 2] Center 38 (8~68) winsize 61
7481 11:56:02.860551 [CA 3] Center 37 (8~67) winsize 60
7482 11:56:02.864184 [CA 4] Center 36 (6~66) winsize 61
7483 11:56:02.867618 [CA 5] Center 35 (5~65) winsize 61
7484 11:56:02.868200
7485 11:56:02.870911 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7486 11:56:02.871492
7487 11:56:02.874103 [CATrainingPosCal] consider 1 rank data
7488 11:56:02.877683 u2DelayCellTimex100 = 285/100 ps
7489 11:56:02.880641 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 11:56:02.887438 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7491 11:56:02.890870 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7492 11:56:02.894152 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7493 11:56:02.897453 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7494 11:56:02.900577 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7495 11:56:02.901155
7496 11:56:02.903799 CA PerBit enable=1, Macro0, CA PI delay=35
7497 11:56:02.904380
7498 11:56:02.907323 [CBTSetCACLKResult] CA Dly = 35
7499 11:56:02.910761 CS Dly: 9 (0~40)
7500 11:56:02.914109 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 11:56:02.917536 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 11:56:02.918111 ==
7503 11:56:02.920908 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 11:56:02.924266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 11:56:02.924850 ==
7506 11:56:02.930709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 11:56:02.933759 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 11:56:02.940558 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 11:56:02.943512 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 11:56:02.953892 [CA 0] Center 43 (13~74) winsize 62
7511 11:56:02.957450 [CA 1] Center 43 (13~73) winsize 61
7512 11:56:02.960827 [CA 2] Center 38 (9~68) winsize 60
7513 11:56:02.964091 [CA 3] Center 38 (9~68) winsize 60
7514 11:56:02.967361 [CA 4] Center 37 (7~67) winsize 61
7515 11:56:02.970881 [CA 5] Center 36 (6~66) winsize 61
7516 11:56:02.971459
7517 11:56:02.973979 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 11:56:02.974602
7519 11:56:02.977260 [CATrainingPosCal] consider 2 rank data
7520 11:56:02.980570 u2DelayCellTimex100 = 285/100 ps
7521 11:56:02.984252 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7522 11:56:02.990378 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7523 11:56:02.993865 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7524 11:56:02.997170 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7525 11:56:03.000869 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7526 11:56:03.003969 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7527 11:56:03.004551
7528 11:56:03.007016 CA PerBit enable=1, Macro0, CA PI delay=35
7529 11:56:03.007598
7530 11:56:03.010432 [CBTSetCACLKResult] CA Dly = 35
7531 11:56:03.013904 CS Dly: 11 (0~44)
7532 11:56:03.017126 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 11:56:03.020765 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 11:56:03.021342
7535 11:56:03.024592 ----->DramcWriteLeveling(PI) begin...
7536 11:56:03.025182 ==
7537 11:56:03.027556 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 11:56:03.030321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 11:56:03.033587 ==
7540 11:56:03.037581 Write leveling (Byte 0): 38 => 38
7541 11:56:03.038178 Write leveling (Byte 1): 31 => 31
7542 11:56:03.040313 DramcWriteLeveling(PI) end<-----
7543 11:56:03.040893
7544 11:56:03.041347 ==
7545 11:56:03.043513 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 11:56:03.050091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 11:56:03.050687 ==
7548 11:56:03.053517 [Gating] SW mode calibration
7549 11:56:03.060354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 11:56:03.063889 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 11:56:03.067174 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 11:56:03.074229 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 11:56:03.077274 1 4 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7554 11:56:03.080991 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7555 11:56:03.087331 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7556 11:56:03.090239 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7557 11:56:03.093983 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 11:56:03.100665 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 11:56:03.104267 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 11:56:03.107330 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 11:56:03.113670 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
7562 11:56:03.117476 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7563 11:56:03.120702 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7564 11:56:03.126910 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7565 11:56:03.130043 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:56:03.133324 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:56:03.140101 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 11:56:03.144043 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7569 11:56:03.146698 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7570 11:56:03.153354 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 11:56:03.156988 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7572 11:56:03.159810 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7573 11:56:03.166681 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 11:56:03.170154 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 11:56:03.173404 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 11:56:03.180013 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 11:56:03.182961 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 11:56:03.186738 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 11:56:03.193359 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7580 11:56:03.196539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 11:56:03.199721 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 11:56:03.206577 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:56:03.209751 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:56:03.213426 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:56:03.219825 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:56:03.223114 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:56:03.226368 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:56:03.229571 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:56:03.236166 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:56:03.240038 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:56:03.243300 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:56:03.249462 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:56:03.252913 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 11:56:03.256387 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 11:56:03.263047 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 11:56:03.265925 Total UI for P1: 0, mck2ui 16
7597 11:56:03.269760 best dqsien dly found for B0: ( 1, 9, 10)
7598 11:56:03.272731 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 11:56:03.276414 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 11:56:03.279597 Total UI for P1: 0, mck2ui 16
7601 11:56:03.282670 best dqsien dly found for B1: ( 1, 9, 18)
7602 11:56:03.286512 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 11:56:03.289368 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7604 11:56:03.289895
7605 11:56:03.295936 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 11:56:03.299609 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7607 11:56:03.302571 [Gating] SW calibration Done
7608 11:56:03.303039 ==
7609 11:56:03.306223 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 11:56:03.310328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 11:56:03.311078 ==
7612 11:56:03.311462 RX Vref Scan: 0
7613 11:56:03.312828
7614 11:56:03.313291 RX Vref 0 -> 0, step: 1
7615 11:56:03.313662
7616 11:56:03.316050 RX Delay 0 -> 252, step: 8
7617 11:56:03.319165 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7618 11:56:03.323360 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7619 11:56:03.329217 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7620 11:56:03.332821 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7621 11:56:03.336245 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 11:56:03.339596 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7623 11:56:03.342257 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 11:56:03.345820 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7625 11:56:03.352901 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7626 11:56:03.355786 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7627 11:56:03.359467 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7628 11:56:03.362646 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7629 11:56:03.369000 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7630 11:56:03.372489 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7631 11:56:03.375618 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 11:56:03.378928 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7633 11:56:03.379402 ==
7634 11:56:03.382279 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 11:56:03.385600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 11:56:03.388765 ==
7637 11:56:03.389193 DQS Delay:
7638 11:56:03.389534 DQS0 = 0, DQS1 = 0
7639 11:56:03.392120 DQM Delay:
7640 11:56:03.392591 DQM0 = 138, DQM1 = 127
7641 11:56:03.395872 DQ Delay:
7642 11:56:03.399010 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7643 11:56:03.402455 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7644 11:56:03.406043 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7645 11:56:03.409166 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7646 11:56:03.409699
7647 11:56:03.410041
7648 11:56:03.410357 ==
7649 11:56:03.412409 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:56:03.415696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:56:03.416234 ==
7652 11:56:03.416573
7653 11:56:03.418718
7654 11:56:03.419142 TX Vref Scan disable
7655 11:56:03.422325 == TX Byte 0 ==
7656 11:56:03.425841 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7657 11:56:03.428984 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7658 11:56:03.432362 == TX Byte 1 ==
7659 11:56:03.435440 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7660 11:56:03.439345 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7661 11:56:03.439882 ==
7662 11:56:03.442236 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:56:03.449082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:56:03.449606 ==
7665 11:56:03.460855
7666 11:56:03.464080 TX Vref early break, caculate TX vref
7667 11:56:03.467305 TX Vref=16, minBit 12, minWin=22, winSum=378
7668 11:56:03.470968 TX Vref=18, minBit 7, minWin=23, winSum=388
7669 11:56:03.474481 TX Vref=20, minBit 7, minWin=23, winSum=397
7670 11:56:03.477673 TX Vref=22, minBit 7, minWin=24, winSum=410
7671 11:56:03.481405 TX Vref=24, minBit 6, minWin=25, winSum=420
7672 11:56:03.487417 TX Vref=26, minBit 12, minWin=25, winSum=428
7673 11:56:03.490235 TX Vref=28, minBit 0, minWin=26, winSum=431
7674 11:56:03.493781 TX Vref=30, minBit 0, minWin=26, winSum=423
7675 11:56:03.497256 TX Vref=32, minBit 2, minWin=25, winSum=416
7676 11:56:03.500686 TX Vref=34, minBit 0, minWin=24, winSum=403
7677 11:56:03.507533 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7678 11:56:03.508114
7679 11:56:03.510506 Final TX Range 0 Vref 28
7680 11:56:03.511077
7681 11:56:03.511461 ==
7682 11:56:03.514246 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 11:56:03.517592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 11:56:03.518174 ==
7685 11:56:03.518615
7686 11:56:03.518974
7687 11:56:03.520626 TX Vref Scan disable
7688 11:56:03.527072 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7689 11:56:03.527642 == TX Byte 0 ==
7690 11:56:03.530441 u2DelayCellOfst[0]=13 cells (4 PI)
7691 11:56:03.534210 u2DelayCellOfst[1]=20 cells (6 PI)
7692 11:56:03.537460 u2DelayCellOfst[2]=13 cells (4 PI)
7693 11:56:03.540292 u2DelayCellOfst[3]=13 cells (4 PI)
7694 11:56:03.544379 u2DelayCellOfst[4]=10 cells (3 PI)
7695 11:56:03.547234 u2DelayCellOfst[5]=0 cells (0 PI)
7696 11:56:03.550297 u2DelayCellOfst[6]=20 cells (6 PI)
7697 11:56:03.553939 u2DelayCellOfst[7]=17 cells (5 PI)
7698 11:56:03.557509 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7699 11:56:03.560732 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7700 11:56:03.563846 == TX Byte 1 ==
7701 11:56:03.567167 u2DelayCellOfst[8]=0 cells (0 PI)
7702 11:56:03.567644 u2DelayCellOfst[9]=0 cells (0 PI)
7703 11:56:03.570358 u2DelayCellOfst[10]=6 cells (2 PI)
7704 11:56:03.573834 u2DelayCellOfst[11]=3 cells (1 PI)
7705 11:56:03.577049 u2DelayCellOfst[12]=13 cells (4 PI)
7706 11:56:03.580598 u2DelayCellOfst[13]=13 cells (4 PI)
7707 11:56:03.583705 u2DelayCellOfst[14]=13 cells (4 PI)
7708 11:56:03.586894 u2DelayCellOfst[15]=10 cells (3 PI)
7709 11:56:03.590545 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7710 11:56:03.597065 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7711 11:56:03.597647 DramC Write-DBI on
7712 11:56:03.598029 ==
7713 11:56:03.600156 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 11:56:03.603810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 11:56:03.606839 ==
7716 11:56:03.607317
7717 11:56:03.607692
7718 11:56:03.608040 TX Vref Scan disable
7719 11:56:03.611345 == TX Byte 0 ==
7720 11:56:03.614276 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7721 11:56:03.617274 == TX Byte 1 ==
7722 11:56:03.621170 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7723 11:56:03.624001 DramC Write-DBI off
7724 11:56:03.624578
7725 11:56:03.624957 [DATLAT]
7726 11:56:03.625305 Freq=1600, CH0 RK0
7727 11:56:03.625646
7728 11:56:03.627188 DATLAT Default: 0xf
7729 11:56:03.627666 0, 0xFFFF, sum = 0
7730 11:56:03.630343 1, 0xFFFF, sum = 0
7731 11:56:03.633523 2, 0xFFFF, sum = 0
7732 11:56:03.634002 3, 0xFFFF, sum = 0
7733 11:56:03.637012 4, 0xFFFF, sum = 0
7734 11:56:03.637496 5, 0xFFFF, sum = 0
7735 11:56:03.640099 6, 0xFFFF, sum = 0
7736 11:56:03.640581 7, 0xFFFF, sum = 0
7737 11:56:03.643950 8, 0xFFFF, sum = 0
7738 11:56:03.644538 9, 0xFFFF, sum = 0
7739 11:56:03.646933 10, 0xFFFF, sum = 0
7740 11:56:03.647414 11, 0xFFFF, sum = 0
7741 11:56:03.650186 12, 0xFFFF, sum = 0
7742 11:56:03.650718 13, 0xFFFF, sum = 0
7743 11:56:03.653656 14, 0x0, sum = 1
7744 11:56:03.654138 15, 0x0, sum = 2
7745 11:56:03.657193 16, 0x0, sum = 3
7746 11:56:03.657776 17, 0x0, sum = 4
7747 11:56:03.660141 best_step = 15
7748 11:56:03.660619
7749 11:56:03.661020 ==
7750 11:56:03.663583 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 11:56:03.667486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 11:56:03.668067 ==
7753 11:56:03.670381 RX Vref Scan: 1
7754 11:56:03.670999
7755 11:56:03.671378 Set Vref Range= 24 -> 127
7756 11:56:03.671733
7757 11:56:03.673524 RX Vref 24 -> 127, step: 1
7758 11:56:03.674000
7759 11:56:03.676834 RX Delay 19 -> 252, step: 4
7760 11:56:03.677308
7761 11:56:03.680206 Set Vref, RX VrefLevel [Byte0]: 24
7762 11:56:03.683811 [Byte1]: 24
7763 11:56:03.684288
7764 11:56:03.686968 Set Vref, RX VrefLevel [Byte0]: 25
7765 11:56:03.690267 [Byte1]: 25
7766 11:56:03.690896
7767 11:56:03.693485 Set Vref, RX VrefLevel [Byte0]: 26
7768 11:56:03.696875 [Byte1]: 26
7769 11:56:03.700801
7770 11:56:03.701297 Set Vref, RX VrefLevel [Byte0]: 27
7771 11:56:03.704468 [Byte1]: 27
7772 11:56:03.708280
7773 11:56:03.708870 Set Vref, RX VrefLevel [Byte0]: 28
7774 11:56:03.711496 [Byte1]: 28
7775 11:56:03.716059
7776 11:56:03.716624 Set Vref, RX VrefLevel [Byte0]: 29
7777 11:56:03.720070 [Byte1]: 29
7778 11:56:03.723977
7779 11:56:03.724547 Set Vref, RX VrefLevel [Byte0]: 30
7780 11:56:03.727145 [Byte1]: 30
7781 11:56:03.731617
7782 11:56:03.732187 Set Vref, RX VrefLevel [Byte0]: 31
7783 11:56:03.735046 [Byte1]: 31
7784 11:56:03.738564
7785 11:56:03.739029 Set Vref, RX VrefLevel [Byte0]: 32
7786 11:56:03.742477 [Byte1]: 32
7787 11:56:03.746561
7788 11:56:03.747142 Set Vref, RX VrefLevel [Byte0]: 33
7789 11:56:03.750000 [Byte1]: 33
7790 11:56:03.754039
7791 11:56:03.754683 Set Vref, RX VrefLevel [Byte0]: 34
7792 11:56:03.757501 [Byte1]: 34
7793 11:56:03.761689
7794 11:56:03.762253 Set Vref, RX VrefLevel [Byte0]: 35
7795 11:56:03.764910 [Byte1]: 35
7796 11:56:03.768970
7797 11:56:03.769537 Set Vref, RX VrefLevel [Byte0]: 36
7798 11:56:03.772396 [Byte1]: 36
7799 11:56:03.776884
7800 11:56:03.777439 Set Vref, RX VrefLevel [Byte0]: 37
7801 11:56:03.779851 [Byte1]: 37
7802 11:56:03.783983
7803 11:56:03.787594 Set Vref, RX VrefLevel [Byte0]: 38
7804 11:56:03.790601 [Byte1]: 38
7805 11:56:03.791171
7806 11:56:03.793709 Set Vref, RX VrefLevel [Byte0]: 39
7807 11:56:03.797308 [Byte1]: 39
7808 11:56:03.797881
7809 11:56:03.800289 Set Vref, RX VrefLevel [Byte0]: 40
7810 11:56:03.803760 [Byte1]: 40
7811 11:56:03.804333
7812 11:56:03.807412 Set Vref, RX VrefLevel [Byte0]: 41
7813 11:56:03.810034 [Byte1]: 41
7814 11:56:03.814314
7815 11:56:03.814913 Set Vref, RX VrefLevel [Byte0]: 42
7816 11:56:03.817541 [Byte1]: 42
7817 11:56:03.822048
7818 11:56:03.822678 Set Vref, RX VrefLevel [Byte0]: 43
7819 11:56:03.825657 [Byte1]: 43
7820 11:56:03.829586
7821 11:56:03.830076 Set Vref, RX VrefLevel [Byte0]: 44
7822 11:56:03.832913 [Byte1]: 44
7823 11:56:03.837610
7824 11:56:03.838176 Set Vref, RX VrefLevel [Byte0]: 45
7825 11:56:03.840387 [Byte1]: 45
7826 11:56:03.844811
7827 11:56:03.845379 Set Vref, RX VrefLevel [Byte0]: 46
7828 11:56:03.847918 [Byte1]: 46
7829 11:56:03.852148
7830 11:56:03.852714 Set Vref, RX VrefLevel [Byte0]: 47
7831 11:56:03.855352 [Byte1]: 47
7832 11:56:03.860580
7833 11:56:03.861198 Set Vref, RX VrefLevel [Byte0]: 48
7834 11:56:03.863679 [Byte1]: 48
7835 11:56:03.867390
7836 11:56:03.867954 Set Vref, RX VrefLevel [Byte0]: 49
7837 11:56:03.870932 [Byte1]: 49
7838 11:56:03.875156
7839 11:56:03.875725 Set Vref, RX VrefLevel [Byte0]: 50
7840 11:56:03.878586 [Byte1]: 50
7841 11:56:03.882784
7842 11:56:03.883347 Set Vref, RX VrefLevel [Byte0]: 51
7843 11:56:03.885915 [Byte1]: 51
7844 11:56:03.890227
7845 11:56:03.890843 Set Vref, RX VrefLevel [Byte0]: 52
7846 11:56:03.893867 [Byte1]: 52
7847 11:56:03.898074
7848 11:56:03.898717 Set Vref, RX VrefLevel [Byte0]: 53
7849 11:56:03.900880 [Byte1]: 53
7850 11:56:03.905529
7851 11:56:03.906107 Set Vref, RX VrefLevel [Byte0]: 54
7852 11:56:03.908543 [Byte1]: 54
7853 11:56:03.913005
7854 11:56:03.913608 Set Vref, RX VrefLevel [Byte0]: 55
7855 11:56:03.919249 [Byte1]: 55
7856 11:56:03.919826
7857 11:56:03.922565 Set Vref, RX VrefLevel [Byte0]: 56
7858 11:56:03.925853 [Byte1]: 56
7859 11:56:03.926469
7860 11:56:03.929255 Set Vref, RX VrefLevel [Byte0]: 57
7861 11:56:03.933019 [Byte1]: 57
7862 11:56:03.933588
7863 11:56:03.936090 Set Vref, RX VrefLevel [Byte0]: 58
7864 11:56:03.939643 [Byte1]: 58
7865 11:56:03.943249
7866 11:56:03.943814 Set Vref, RX VrefLevel [Byte0]: 59
7867 11:56:03.946635 [Byte1]: 59
7868 11:56:03.950955
7869 11:56:03.951520 Set Vref, RX VrefLevel [Byte0]: 60
7870 11:56:03.954517 [Byte1]: 60
7871 11:56:03.958935
7872 11:56:03.959506 Set Vref, RX VrefLevel [Byte0]: 61
7873 11:56:03.961809 [Byte1]: 61
7874 11:56:03.965956
7875 11:56:03.966553 Set Vref, RX VrefLevel [Byte0]: 62
7876 11:56:03.969433 [Byte1]: 62
7877 11:56:03.973816
7878 11:56:03.974381 Set Vref, RX VrefLevel [Byte0]: 63
7879 11:56:03.976589 [Byte1]: 63
7880 11:56:03.981465
7881 11:56:03.982032 Set Vref, RX VrefLevel [Byte0]: 64
7882 11:56:03.984546 [Byte1]: 64
7883 11:56:03.989209
7884 11:56:03.989774 Set Vref, RX VrefLevel [Byte0]: 65
7885 11:56:03.992163 [Byte1]: 65
7886 11:56:03.996383
7887 11:56:03.996944 Set Vref, RX VrefLevel [Byte0]: 66
7888 11:56:03.999225 [Byte1]: 66
7889 11:56:04.003900
7890 11:56:04.004475 Set Vref, RX VrefLevel [Byte0]: 67
7891 11:56:04.007163 [Byte1]: 67
7892 11:56:04.011473
7893 11:56:04.012051 Set Vref, RX VrefLevel [Byte0]: 68
7894 11:56:04.014603 [Byte1]: 68
7895 11:56:04.018970
7896 11:56:04.019536 Set Vref, RX VrefLevel [Byte0]: 69
7897 11:56:04.022053 [Byte1]: 69
7898 11:56:04.026566
7899 11:56:04.027122 Set Vref, RX VrefLevel [Byte0]: 70
7900 11:56:04.029937 [Byte1]: 70
7901 11:56:04.034078
7902 11:56:04.034677 Set Vref, RX VrefLevel [Byte0]: 71
7903 11:56:04.037425 [Byte1]: 71
7904 11:56:04.041895
7905 11:56:04.042497 Set Vref, RX VrefLevel [Byte0]: 72
7906 11:56:04.045063 [Byte1]: 72
7907 11:56:04.049349
7908 11:56:04.049916 Set Vref, RX VrefLevel [Byte0]: 73
7909 11:56:04.052361 [Byte1]: 73
7910 11:56:04.056885
7911 11:56:04.057451 Set Vref, RX VrefLevel [Byte0]: 74
7912 11:56:04.060114 [Byte1]: 74
7913 11:56:04.064678
7914 11:56:04.065246 Set Vref, RX VrefLevel [Byte0]: 75
7915 11:56:04.068123 [Byte1]: 75
7916 11:56:04.072007
7917 11:56:04.072572 Set Vref, RX VrefLevel [Byte0]: 76
7918 11:56:04.075164 [Byte1]: 76
7919 11:56:04.080099
7920 11:56:04.080674 Set Vref, RX VrefLevel [Byte0]: 77
7921 11:56:04.082950 [Byte1]: 77
7922 11:56:04.087302
7923 11:56:04.087866 Set Vref, RX VrefLevel [Byte0]: 78
7924 11:56:04.090729 [Byte1]: 78
7925 11:56:04.095112
7926 11:56:04.095680 Set Vref, RX VrefLevel [Byte0]: 79
7927 11:56:04.097958 [Byte1]: 79
7928 11:56:04.102430
7929 11:56:04.103006 Set Vref, RX VrefLevel [Byte0]: 80
7930 11:56:04.105974 [Byte1]: 80
7931 11:56:04.109641
7932 11:56:04.110204 Final RX Vref Byte 0 = 60 to rank0
7933 11:56:04.113365 Final RX Vref Byte 1 = 60 to rank0
7934 11:56:04.116570 Final RX Vref Byte 0 = 60 to rank1
7935 11:56:04.119507 Final RX Vref Byte 1 = 60 to rank1==
7936 11:56:04.123519 Dram Type= 6, Freq= 0, CH_0, rank 0
7937 11:56:04.129529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7938 11:56:04.130003 ==
7939 11:56:04.130533 DQS Delay:
7940 11:56:04.130896 DQS0 = 0, DQS1 = 0
7941 11:56:04.132977 DQM Delay:
7942 11:56:04.133542 DQM0 = 136, DQM1 = 124
7943 11:56:04.136356 DQ Delay:
7944 11:56:04.139518 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7945 11:56:04.142671 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7946 11:56:04.146327 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7947 11:56:04.149559 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7948 11:56:04.150125
7949 11:56:04.150552
7950 11:56:04.150903
7951 11:56:04.152971 [DramC_TX_OE_Calibration] TA2
7952 11:56:04.155998 Original DQ_B0 (3 6) =30, OEN = 27
7953 11:56:04.159681 Original DQ_B1 (3 6) =30, OEN = 27
7954 11:56:04.162856 24, 0x0, End_B0=24 End_B1=24
7955 11:56:04.163330 25, 0x0, End_B0=25 End_B1=25
7956 11:56:04.166468 26, 0x0, End_B0=26 End_B1=26
7957 11:56:04.169679 27, 0x0, End_B0=27 End_B1=27
7958 11:56:04.173109 28, 0x0, End_B0=28 End_B1=28
7959 11:56:04.176467 29, 0x0, End_B0=29 End_B1=29
7960 11:56:04.177081 30, 0x0, End_B0=30 End_B1=30
7961 11:56:04.179447 31, 0x4141, End_B0=30 End_B1=30
7962 11:56:04.182970 Byte0 end_step=30 best_step=27
7963 11:56:04.186018 Byte1 end_step=30 best_step=27
7964 11:56:04.189898 Byte0 TX OE(2T, 0.5T) = (3, 3)
7965 11:56:04.192815 Byte1 TX OE(2T, 0.5T) = (3, 3)
7966 11:56:04.193384
7967 11:56:04.193758
7968 11:56:04.199321 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7969 11:56:04.202552 CH0 RK0: MR19=303, MR18=1E1C
7970 11:56:04.209265 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7971 11:56:04.209841
7972 11:56:04.212765 ----->DramcWriteLeveling(PI) begin...
7973 11:56:04.213357 ==
7974 11:56:04.216052 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 11:56:04.219548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 11:56:04.220180 ==
7977 11:56:04.222576 Write leveling (Byte 0): 37 => 37
7978 11:56:04.226097 Write leveling (Byte 1): 29 => 29
7979 11:56:04.229166 DramcWriteLeveling(PI) end<-----
7980 11:56:04.229736
7981 11:56:04.230332 ==
7982 11:56:04.232694 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 11:56:04.235868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 11:56:04.236444 ==
7985 11:56:04.239265 [Gating] SW mode calibration
7986 11:56:04.245975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7987 11:56:04.252494 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7988 11:56:04.256095 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 11:56:04.259431 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 11:56:04.266015 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 11:56:04.269330 1 4 12 | B1->B0 | 2928 3333 | 1 0 | (0 0) (0 0)
7992 11:56:04.272714 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 11:56:04.279293 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 11:56:04.282469 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 11:56:04.286090 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 11:56:04.292613 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 11:56:04.295540 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 11:56:04.299184 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7999 11:56:04.305977 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
8000 11:56:04.309530 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
8001 11:56:04.312545 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 11:56:04.318697 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 11:56:04.322568 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 11:56:04.325588 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:56:04.331959 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 11:56:04.335775 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8007 11:56:04.339194 1 6 12 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
8008 11:56:04.345633 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8009 11:56:04.349142 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 11:56:04.352204 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 11:56:04.358841 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 11:56:04.362276 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 11:56:04.365557 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 11:56:04.371916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:56:04.375302 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 11:56:04.378741 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8017 11:56:04.385259 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 11:56:04.388808 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 11:56:04.392278 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 11:56:04.398421 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:56:04.402101 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:56:04.405142 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:56:04.408666 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:56:04.415272 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 11:56:04.418794 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:56:04.421926 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:56:04.428626 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:56:04.431536 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:56:04.434972 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:56:04.441628 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 11:56:04.444983 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 11:56:04.448376 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8033 11:56:04.451654 Total UI for P1: 0, mck2ui 16
8034 11:56:04.454833 best dqsien dly found for B0: ( 1, 9, 12)
8035 11:56:04.461568 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 11:56:04.462081 Total UI for P1: 0, mck2ui 16
8037 11:56:04.468100 best dqsien dly found for B1: ( 1, 9, 14)
8038 11:56:04.471540 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8039 11:56:04.475240 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8040 11:56:04.475828
8041 11:56:04.478117 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8042 11:56:04.481589 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8043 11:56:04.485226 [Gating] SW calibration Done
8044 11:56:04.485818 ==
8045 11:56:04.488338 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 11:56:04.491545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 11:56:04.492142 ==
8048 11:56:04.495152 RX Vref Scan: 0
8049 11:56:04.495635
8050 11:56:04.496115 RX Vref 0 -> 0, step: 1
8051 11:56:04.497893
8052 11:56:04.498363 RX Delay 0 -> 252, step: 8
8053 11:56:04.501293 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8054 11:56:04.508232 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8055 11:56:04.511216 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8056 11:56:04.514501 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8057 11:56:04.518133 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8058 11:56:04.521411 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8059 11:56:04.527797 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8060 11:56:04.531428 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8061 11:56:04.534850 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8062 11:56:04.537849 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8063 11:56:04.541116 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8064 11:56:04.547762 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8065 11:56:04.551087 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8066 11:56:04.554729 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8067 11:56:04.558004 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8068 11:56:04.564454 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
8069 11:56:04.564936 ==
8070 11:56:04.567928 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 11:56:04.571148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 11:56:04.571726 ==
8073 11:56:04.572172 DQS Delay:
8074 11:56:04.574295 DQS0 = 0, DQS1 = 0
8075 11:56:04.574792 DQM Delay:
8076 11:56:04.577753 DQM0 = 136, DQM1 = 124
8077 11:56:04.578217 DQ Delay:
8078 11:56:04.581368 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8079 11:56:04.584558 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8080 11:56:04.587944 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8081 11:56:04.591273 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
8082 11:56:04.591740
8083 11:56:04.592107
8084 11:56:04.592447 ==
8085 11:56:04.594347 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 11:56:04.601261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 11:56:04.601841 ==
8088 11:56:04.602228
8089 11:56:04.602641
8090 11:56:04.604310 TX Vref Scan disable
8091 11:56:04.604784 == TX Byte 0 ==
8092 11:56:04.607682 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8093 11:56:04.614504 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8094 11:56:04.615069 == TX Byte 1 ==
8095 11:56:04.617895 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8096 11:56:04.624601 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8097 11:56:04.625173 ==
8098 11:56:04.627442 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 11:56:04.630924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 11:56:04.631619 ==
8101 11:56:04.646101
8102 11:56:04.650016 TX Vref early break, caculate TX vref
8103 11:56:04.652798 TX Vref=16, minBit 8, minWin=23, winSum=388
8104 11:56:04.656015 TX Vref=18, minBit 0, minWin=24, winSum=402
8105 11:56:04.659242 TX Vref=20, minBit 0, minWin=24, winSum=408
8106 11:56:04.662751 TX Vref=22, minBit 0, minWin=25, winSum=412
8107 11:56:04.666240 TX Vref=24, minBit 0, minWin=25, winSum=420
8108 11:56:04.672770 TX Vref=26, minBit 0, minWin=26, winSum=429
8109 11:56:04.675614 TX Vref=28, minBit 0, minWin=26, winSum=432
8110 11:56:04.678989 TX Vref=30, minBit 0, minWin=25, winSum=426
8111 11:56:04.683046 TX Vref=32, minBit 2, minWin=25, winSum=420
8112 11:56:04.686089 TX Vref=34, minBit 11, minWin=24, winSum=410
8113 11:56:04.689161 TX Vref=36, minBit 2, minWin=24, winSum=401
8114 11:56:04.695836 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8115 11:56:04.696409
8116 11:56:04.699029 Final TX Range 0 Vref 28
8117 11:56:04.699509
8118 11:56:04.699885 ==
8119 11:56:04.702997 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 11:56:04.705903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 11:56:04.706525 ==
8122 11:56:04.706913
8123 11:56:04.707262
8124 11:56:04.709503 TX Vref Scan disable
8125 11:56:04.715526 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8126 11:56:04.716082 == TX Byte 0 ==
8127 11:56:04.718795 u2DelayCellOfst[0]=10 cells (3 PI)
8128 11:56:04.722559 u2DelayCellOfst[1]=17 cells (5 PI)
8129 11:56:04.725888 u2DelayCellOfst[2]=10 cells (3 PI)
8130 11:56:04.729411 u2DelayCellOfst[3]=10 cells (3 PI)
8131 11:56:04.732162 u2DelayCellOfst[4]=6 cells (2 PI)
8132 11:56:04.735815 u2DelayCellOfst[5]=0 cells (0 PI)
8133 11:56:04.739100 u2DelayCellOfst[6]=17 cells (5 PI)
8134 11:56:04.742599 u2DelayCellOfst[7]=13 cells (4 PI)
8135 11:56:04.745863 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8136 11:56:04.749291 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8137 11:56:04.752811 == TX Byte 1 ==
8138 11:56:04.755584 u2DelayCellOfst[8]=0 cells (0 PI)
8139 11:56:04.759246 u2DelayCellOfst[9]=0 cells (0 PI)
8140 11:56:04.759884 u2DelayCellOfst[10]=10 cells (3 PI)
8141 11:56:04.762096 u2DelayCellOfst[11]=3 cells (1 PI)
8142 11:56:04.765537 u2DelayCellOfst[12]=13 cells (4 PI)
8143 11:56:04.768655 u2DelayCellOfst[13]=10 cells (3 PI)
8144 11:56:04.772022 u2DelayCellOfst[14]=13 cells (4 PI)
8145 11:56:04.775631 u2DelayCellOfst[15]=10 cells (3 PI)
8146 11:56:04.782616 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8147 11:56:04.785502 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8148 11:56:04.786075 DramC Write-DBI on
8149 11:56:04.786524 ==
8150 11:56:04.788937 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 11:56:04.795758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 11:56:04.796342 ==
8153 11:56:04.796724
8154 11:56:04.797068
8155 11:56:04.797398 TX Vref Scan disable
8156 11:56:04.799464 == TX Byte 0 ==
8157 11:56:04.803015 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8158 11:56:04.806280 == TX Byte 1 ==
8159 11:56:04.809776 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8160 11:56:04.810342 DramC Write-DBI off
8161 11:56:04.812952
8162 11:56:04.813517 [DATLAT]
8163 11:56:04.813889 Freq=1600, CH0 RK1
8164 11:56:04.814234
8165 11:56:04.816293 DATLAT Default: 0xf
8166 11:56:04.816862 0, 0xFFFF, sum = 0
8167 11:56:04.819380 1, 0xFFFF, sum = 0
8168 11:56:04.819945 2, 0xFFFF, sum = 0
8169 11:56:04.822723 3, 0xFFFF, sum = 0
8170 11:56:04.826214 4, 0xFFFF, sum = 0
8171 11:56:04.826811 5, 0xFFFF, sum = 0
8172 11:56:04.829592 6, 0xFFFF, sum = 0
8173 11:56:04.830165 7, 0xFFFF, sum = 0
8174 11:56:04.832764 8, 0xFFFF, sum = 0
8175 11:56:04.833239 9, 0xFFFF, sum = 0
8176 11:56:04.836305 10, 0xFFFF, sum = 0
8177 11:56:04.836886 11, 0xFFFF, sum = 0
8178 11:56:04.839421 12, 0xFFFF, sum = 0
8179 11:56:04.840001 13, 0xFFFF, sum = 0
8180 11:56:04.842985 14, 0x0, sum = 1
8181 11:56:04.843563 15, 0x0, sum = 2
8182 11:56:04.846339 16, 0x0, sum = 3
8183 11:56:04.846944 17, 0x0, sum = 4
8184 11:56:04.849593 best_step = 15
8185 11:56:04.850157
8186 11:56:04.850562 ==
8187 11:56:04.852880 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 11:56:04.855921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 11:56:04.856396 ==
8190 11:56:04.856835 RX Vref Scan: 0
8191 11:56:04.859695
8192 11:56:04.860158 RX Vref 0 -> 0, step: 1
8193 11:56:04.860528
8194 11:56:04.862517 RX Delay 11 -> 252, step: 4
8195 11:56:04.866418 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8196 11:56:04.872635 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8197 11:56:04.875813 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8198 11:56:04.879224 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8199 11:56:04.882668 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8200 11:56:04.886061 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8201 11:56:04.889372 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8202 11:56:04.896233 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8203 11:56:04.899323 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8204 11:56:04.902737 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8205 11:56:04.907136 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8206 11:56:04.909558 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8207 11:56:04.916191 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8208 11:56:04.919111 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8209 11:56:04.922738 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8210 11:56:04.925904 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8211 11:56:04.926514 ==
8212 11:56:04.929175 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 11:56:04.936061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 11:56:04.936635 ==
8215 11:56:04.937010 DQS Delay:
8216 11:56:04.939564 DQS0 = 0, DQS1 = 0
8217 11:56:04.940132 DQM Delay:
8218 11:56:04.942656 DQM0 = 133, DQM1 = 123
8219 11:56:04.943218 DQ Delay:
8220 11:56:04.946139 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8221 11:56:04.949284 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8222 11:56:04.952733 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8223 11:56:04.956177 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8224 11:56:04.956773
8225 11:56:04.957163
8226 11:56:04.957505
8227 11:56:04.958969 [DramC_TX_OE_Calibration] TA2
8228 11:56:04.962363 Original DQ_B0 (3 6) =30, OEN = 27
8229 11:56:04.965958 Original DQ_B1 (3 6) =30, OEN = 27
8230 11:56:04.969683 24, 0x0, End_B0=24 End_B1=24
8231 11:56:04.970255 25, 0x0, End_B0=25 End_B1=25
8232 11:56:04.972165 26, 0x0, End_B0=26 End_B1=26
8233 11:56:04.975763 27, 0x0, End_B0=27 End_B1=27
8234 11:56:04.979536 28, 0x0, End_B0=28 End_B1=28
8235 11:56:04.982299 29, 0x0, End_B0=29 End_B1=29
8236 11:56:04.982806 30, 0x0, End_B0=30 End_B1=30
8237 11:56:04.985806 31, 0x4141, End_B0=30 End_B1=30
8238 11:56:04.988772 Byte0 end_step=30 best_step=27
8239 11:56:04.992587 Byte1 end_step=30 best_step=27
8240 11:56:04.995891 Byte0 TX OE(2T, 0.5T) = (3, 3)
8241 11:56:04.999217 Byte1 TX OE(2T, 0.5T) = (3, 3)
8242 11:56:04.999685
8243 11:56:05.000083
8244 11:56:05.005653 [DQSOSCAuto] RK1, (LSB)MR18= 0x2410, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8245 11:56:05.008801 CH0 RK1: MR19=303, MR18=2410
8246 11:56:05.015772 CH0_RK1: MR19=0x303, MR18=0x2410, DQSOSC=391, MR23=63, INC=24, DEC=16
8247 11:56:05.019727 [RxdqsGatingPostProcess] freq 1600
8248 11:56:05.022290 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8249 11:56:05.025757 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 11:56:05.028879 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 11:56:05.032315 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 11:56:05.035772 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 11:56:05.038829 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 11:56:05.042162 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 11:56:05.045623 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 11:56:05.049004 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 11:56:05.052172 Pre-setting of DQS Precalculation
8258 11:56:05.055182 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8259 11:56:05.055655 ==
8260 11:56:05.058990 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 11:56:05.061830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 11:56:05.065390 ==
8263 11:56:05.069117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 11:56:05.071904 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 11:56:05.078476 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 11:56:05.085371 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 11:56:05.092433 [CA 0] Center 42 (12~72) winsize 61
8268 11:56:05.095699 [CA 1] Center 42 (12~72) winsize 61
8269 11:56:05.098912 [CA 2] Center 38 (9~68) winsize 60
8270 11:56:05.102338 [CA 3] Center 37 (8~67) winsize 60
8271 11:56:05.105672 [CA 4] Center 37 (8~67) winsize 60
8272 11:56:05.109097 [CA 5] Center 37 (7~67) winsize 61
8273 11:56:05.109668
8274 11:56:05.112492 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8275 11:56:05.112956
8276 11:56:05.115534 [CATrainingPosCal] consider 1 rank data
8277 11:56:05.118987 u2DelayCellTimex100 = 285/100 ps
8278 11:56:05.122140 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8279 11:56:05.129020 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8280 11:56:05.132550 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8281 11:56:05.135878 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8282 11:56:05.139339 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8283 11:56:05.142416 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8284 11:56:05.142978
8285 11:56:05.145622 CA PerBit enable=1, Macro0, CA PI delay=37
8286 11:56:05.146198
8287 11:56:05.149171 [CBTSetCACLKResult] CA Dly = 37
8288 11:56:05.149742 CS Dly: 8 (0~39)
8289 11:56:05.156477 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 11:56:05.158863 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 11:56:05.159334 ==
8292 11:56:05.162143 Dram Type= 6, Freq= 0, CH_1, rank 1
8293 11:56:05.165531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 11:56:05.165990 ==
8295 11:56:05.172307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 11:56:05.175384 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 11:56:05.181923 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 11:56:05.185307 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 11:56:05.195427 [CA 0] Center 42 (12~72) winsize 61
8300 11:56:05.199230 [CA 1] Center 41 (11~72) winsize 62
8301 11:56:05.202427 [CA 2] Center 38 (8~68) winsize 61
8302 11:56:05.205635 [CA 3] Center 37 (8~67) winsize 60
8303 11:56:05.208747 [CA 4] Center 37 (8~67) winsize 60
8304 11:56:05.211842 [CA 5] Center 36 (7~66) winsize 60
8305 11:56:05.212425
8306 11:56:05.215562 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 11:56:05.216137
8308 11:56:05.218851 [CATrainingPosCal] consider 2 rank data
8309 11:56:05.222354 u2DelayCellTimex100 = 285/100 ps
8310 11:56:05.225170 CA0 delay=42 (12~72),Diff = 6 PI (20 cell)
8311 11:56:05.231903 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8312 11:56:05.235357 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8313 11:56:05.239389 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8314 11:56:05.241829 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8315 11:56:05.245714 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 11:56:05.246277
8317 11:56:05.248650 CA PerBit enable=1, Macro0, CA PI delay=36
8318 11:56:05.249214
8319 11:56:05.252035 [CBTSetCACLKResult] CA Dly = 36
8320 11:56:05.255255 CS Dly: 9 (0~42)
8321 11:56:05.258336 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 11:56:05.262010 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 11:56:05.262626
8324 11:56:05.265437 ----->DramcWriteLeveling(PI) begin...
8325 11:56:05.266007 ==
8326 11:56:05.268751 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 11:56:05.271906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 11:56:05.275443 ==
8329 11:56:05.276014 Write leveling (Byte 0): 23 => 23
8330 11:56:05.278556 Write leveling (Byte 1): 28 => 28
8331 11:56:05.281803 DramcWriteLeveling(PI) end<-----
8332 11:56:05.282468
8333 11:56:05.282854 ==
8334 11:56:05.285290 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 11:56:05.292402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 11:56:05.292971 ==
8337 11:56:05.293344 [Gating] SW mode calibration
8338 11:56:05.302134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8339 11:56:05.305343 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8340 11:56:05.308374 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 11:56:05.315107 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 11:56:05.318428 1 4 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (1 1)
8343 11:56:05.321768 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 11:56:05.328533 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 11:56:05.331662 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 11:56:05.334904 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 11:56:05.342011 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 11:56:05.345404 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 11:56:05.348621 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8350 11:56:05.355057 1 5 8 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 1)
8351 11:56:05.358482 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8352 11:56:05.361909 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 11:56:05.368440 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 11:56:05.371986 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 11:56:05.375091 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 11:56:05.381945 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:56:05.385087 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:56:05.388288 1 6 8 | B1->B0 | 2b2b 3e3e | 0 1 | (0 0) (0 0)
8359 11:56:05.395000 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 11:56:05.398632 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 11:56:05.401586 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 11:56:05.408306 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 11:56:05.411578 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:56:05.415144 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 11:56:05.421611 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:56:05.425098 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8367 11:56:05.428631 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8368 11:56:05.431882 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8369 11:56:05.438443 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 11:56:05.441589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 11:56:05.448207 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:56:05.451070 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:56:05.454499 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:56:05.458179 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:56:05.464919 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:56:05.468122 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:56:05.471294 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:56:05.477981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:56:05.481210 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:56:05.484591 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:56:05.491298 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8382 11:56:05.494889 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8383 11:56:05.497937 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8384 11:56:05.501415 Total UI for P1: 0, mck2ui 16
8385 11:56:05.504215 best dqsien dly found for B0: ( 1, 9, 6)
8386 11:56:05.511099 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 11:56:05.511885 Total UI for P1: 0, mck2ui 16
8388 11:56:05.517777 best dqsien dly found for B1: ( 1, 9, 12)
8389 11:56:05.521185 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8390 11:56:05.524533 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8391 11:56:05.525131
8392 11:56:05.527934 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8393 11:56:05.530812 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8394 11:56:05.534258 [Gating] SW calibration Done
8395 11:56:05.534806 ==
8396 11:56:05.537697 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 11:56:05.541147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 11:56:05.541622 ==
8399 11:56:05.544211 RX Vref Scan: 0
8400 11:56:05.544784
8401 11:56:05.545160 RX Vref 0 -> 0, step: 1
8402 11:56:05.547766
8403 11:56:05.548338 RX Delay 0 -> 252, step: 8
8404 11:56:05.550680 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8405 11:56:05.557601 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8406 11:56:05.561144 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8407 11:56:05.563956 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8408 11:56:05.567382 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8409 11:56:05.570808 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8410 11:56:05.577368 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8411 11:56:05.580805 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8412 11:56:05.584718 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8413 11:56:05.587136 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8414 11:56:05.590878 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8415 11:56:05.597257 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8416 11:56:05.600612 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8417 11:56:05.603486 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8418 11:56:05.606866 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8419 11:56:05.610677 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8420 11:56:05.613417 ==
8421 11:56:05.613893 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 11:56:05.620493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 11:56:05.621127 ==
8424 11:56:05.621515 DQS Delay:
8425 11:56:05.623954 DQS0 = 0, DQS1 = 0
8426 11:56:05.624541 DQM Delay:
8427 11:56:05.627351 DQM0 = 138, DQM1 = 129
8428 11:56:05.627825 DQ Delay:
8429 11:56:05.630266 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8430 11:56:05.633314 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8431 11:56:05.637391 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8432 11:56:05.640786 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8433 11:56:05.641367
8434 11:56:05.641742
8435 11:56:05.642090 ==
8436 11:56:05.643487 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 11:56:05.650199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 11:56:05.650825 ==
8439 11:56:05.651215
8440 11:56:05.651567
8441 11:56:05.651904 TX Vref Scan disable
8442 11:56:05.653832 == TX Byte 0 ==
8443 11:56:05.656717 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8444 11:56:05.660385 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8445 11:56:05.663709 == TX Byte 1 ==
8446 11:56:05.667300 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 11:56:05.673875 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 11:56:05.674503 ==
8449 11:56:05.676997 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 11:56:05.680080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 11:56:05.680562 ==
8452 11:56:05.693913
8453 11:56:05.697011 TX Vref early break, caculate TX vref
8454 11:56:05.700463 TX Vref=16, minBit 6, minWin=22, winSum=369
8455 11:56:05.703937 TX Vref=18, minBit 15, minWin=22, winSum=379
8456 11:56:05.707150 TX Vref=20, minBit 0, minWin=24, winSum=393
8457 11:56:05.710156 TX Vref=22, minBit 9, minWin=24, winSum=404
8458 11:56:05.713796 TX Vref=24, minBit 10, minWin=24, winSum=412
8459 11:56:05.720342 TX Vref=26, minBit 1, minWin=25, winSum=414
8460 11:56:05.723682 TX Vref=28, minBit 15, minWin=25, winSum=424
8461 11:56:05.726859 TX Vref=30, minBit 13, minWin=24, winSum=418
8462 11:56:05.730423 TX Vref=32, minBit 10, minWin=24, winSum=414
8463 11:56:05.733447 TX Vref=34, minBit 10, minWin=24, winSum=406
8464 11:56:05.740351 TX Vref=36, minBit 10, minWin=22, winSum=386
8465 11:56:05.743756 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 28
8466 11:56:05.744235
8467 11:56:05.746627 Final TX Range 0 Vref 28
8468 11:56:05.747106
8469 11:56:05.747528 ==
8470 11:56:05.750241 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 11:56:05.753632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 11:56:05.756678 ==
8473 11:56:05.757157
8474 11:56:05.757528
8475 11:56:05.757873 TX Vref Scan disable
8476 11:56:05.764005 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8477 11:56:05.764585 == TX Byte 0 ==
8478 11:56:05.767173 u2DelayCellOfst[0]=17 cells (5 PI)
8479 11:56:05.770425 u2DelayCellOfst[1]=10 cells (3 PI)
8480 11:56:05.773739 u2DelayCellOfst[2]=0 cells (0 PI)
8481 11:56:05.776943 u2DelayCellOfst[3]=6 cells (2 PI)
8482 11:56:05.780056 u2DelayCellOfst[4]=6 cells (2 PI)
8483 11:56:05.783335 u2DelayCellOfst[5]=20 cells (6 PI)
8484 11:56:05.787018 u2DelayCellOfst[6]=17 cells (5 PI)
8485 11:56:05.790456 u2DelayCellOfst[7]=3 cells (1 PI)
8486 11:56:05.793629 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8487 11:56:05.797063 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8488 11:56:05.800358 == TX Byte 1 ==
8489 11:56:05.803568 u2DelayCellOfst[8]=0 cells (0 PI)
8490 11:56:05.807105 u2DelayCellOfst[9]=3 cells (1 PI)
8491 11:56:05.810194 u2DelayCellOfst[10]=10 cells (3 PI)
8492 11:56:05.810808 u2DelayCellOfst[11]=3 cells (1 PI)
8493 11:56:05.813874 u2DelayCellOfst[12]=17 cells (5 PI)
8494 11:56:05.816633 u2DelayCellOfst[13]=17 cells (5 PI)
8495 11:56:05.820304 u2DelayCellOfst[14]=17 cells (5 PI)
8496 11:56:05.823464 u2DelayCellOfst[15]=17 cells (5 PI)
8497 11:56:05.830323 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8498 11:56:05.833499 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8499 11:56:05.834080 DramC Write-DBI on
8500 11:56:05.834514 ==
8501 11:56:05.836592 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 11:56:05.843402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 11:56:05.843972 ==
8504 11:56:05.844353
8505 11:56:05.844703
8506 11:56:05.845037 TX Vref Scan disable
8507 11:56:05.847794 == TX Byte 0 ==
8508 11:56:05.850702 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8509 11:56:05.854025 == TX Byte 1 ==
8510 11:56:05.857301 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8511 11:56:05.857778 DramC Write-DBI off
8512 11:56:05.860781
8513 11:56:05.861355 [DATLAT]
8514 11:56:05.861740 Freq=1600, CH1 RK0
8515 11:56:05.862099
8516 11:56:05.864627 DATLAT Default: 0xf
8517 11:56:05.865213 0, 0xFFFF, sum = 0
8518 11:56:05.867407 1, 0xFFFF, sum = 0
8519 11:56:05.870961 2, 0xFFFF, sum = 0
8520 11:56:05.871545 3, 0xFFFF, sum = 0
8521 11:56:05.874333 4, 0xFFFF, sum = 0
8522 11:56:05.874958 5, 0xFFFF, sum = 0
8523 11:56:05.877781 6, 0xFFFF, sum = 0
8524 11:56:05.878369 7, 0xFFFF, sum = 0
8525 11:56:05.880573 8, 0xFFFF, sum = 0
8526 11:56:05.881053 9, 0xFFFF, sum = 0
8527 11:56:05.884297 10, 0xFFFF, sum = 0
8528 11:56:05.884884 11, 0xFFFF, sum = 0
8529 11:56:05.887118 12, 0xFFFF, sum = 0
8530 11:56:05.887597 13, 0xFFFF, sum = 0
8531 11:56:05.890622 14, 0x0, sum = 1
8532 11:56:05.891203 15, 0x0, sum = 2
8533 11:56:05.894205 16, 0x0, sum = 3
8534 11:56:05.894851 17, 0x0, sum = 4
8535 11:56:05.897195 best_step = 15
8536 11:56:05.897773
8537 11:56:05.898151 ==
8538 11:56:05.900820 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 11:56:05.903760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 11:56:05.904343 ==
8541 11:56:05.907038 RX Vref Scan: 1
8542 11:56:05.907509
8543 11:56:05.907885 Set Vref Range= 24 -> 127
8544 11:56:05.908233
8545 11:56:05.910334 RX Vref 24 -> 127, step: 1
8546 11:56:05.910856
8547 11:56:05.913679 RX Delay 19 -> 252, step: 4
8548 11:56:05.914155
8549 11:56:05.917064 Set Vref, RX VrefLevel [Byte0]: 24
8550 11:56:05.920634 [Byte1]: 24
8551 11:56:05.921216
8552 11:56:05.923753 Set Vref, RX VrefLevel [Byte0]: 25
8553 11:56:05.926899 [Byte1]: 25
8554 11:56:05.927379
8555 11:56:05.930446 Set Vref, RX VrefLevel [Byte0]: 26
8556 11:56:05.933768 [Byte1]: 26
8557 11:56:05.937716
8558 11:56:05.938292 Set Vref, RX VrefLevel [Byte0]: 27
8559 11:56:05.941098 [Byte1]: 27
8560 11:56:05.945750
8561 11:56:05.946332 Set Vref, RX VrefLevel [Byte0]: 28
8562 11:56:05.948756 [Byte1]: 28
8563 11:56:05.952989
8564 11:56:05.953572 Set Vref, RX VrefLevel [Byte0]: 29
8565 11:56:05.956252 [Byte1]: 29
8566 11:56:05.960654
8567 11:56:05.961145 Set Vref, RX VrefLevel [Byte0]: 30
8568 11:56:05.964219 [Byte1]: 30
8569 11:56:05.967979
8570 11:56:05.968553 Set Vref, RX VrefLevel [Byte0]: 31
8571 11:56:05.971182 [Byte1]: 31
8572 11:56:05.975644
8573 11:56:05.976222 Set Vref, RX VrefLevel [Byte0]: 32
8574 11:56:05.979403 [Byte1]: 32
8575 11:56:05.983235
8576 11:56:05.983811 Set Vref, RX VrefLevel [Byte0]: 33
8577 11:56:05.986291 [Byte1]: 33
8578 11:56:05.990471
8579 11:56:05.990948 Set Vref, RX VrefLevel [Byte0]: 34
8580 11:56:05.993875 [Byte1]: 34
8581 11:56:05.998295
8582 11:56:05.998814 Set Vref, RX VrefLevel [Byte0]: 35
8583 11:56:06.001717 [Byte1]: 35
8584 11:56:06.005907
8585 11:56:06.006546 Set Vref, RX VrefLevel [Byte0]: 36
8586 11:56:06.009551 [Byte1]: 36
8587 11:56:06.013632
8588 11:56:06.014212 Set Vref, RX VrefLevel [Byte0]: 37
8589 11:56:06.017001 [Byte1]: 37
8590 11:56:06.021572
8591 11:56:06.022152 Set Vref, RX VrefLevel [Byte0]: 38
8592 11:56:06.024253 [Byte1]: 38
8593 11:56:06.028818
8594 11:56:06.029394 Set Vref, RX VrefLevel [Byte0]: 39
8595 11:56:06.031822 [Byte1]: 39
8596 11:56:06.036448
8597 11:56:06.037036 Set Vref, RX VrefLevel [Byte0]: 40
8598 11:56:06.039373 [Byte1]: 40
8599 11:56:06.043803
8600 11:56:06.044276 Set Vref, RX VrefLevel [Byte0]: 41
8601 11:56:06.047002 [Byte1]: 41
8602 11:56:06.051443
8603 11:56:06.052023 Set Vref, RX VrefLevel [Byte0]: 42
8604 11:56:06.054881 [Byte1]: 42
8605 11:56:06.059017
8606 11:56:06.059491 Set Vref, RX VrefLevel [Byte0]: 43
8607 11:56:06.062547 [Byte1]: 43
8608 11:56:06.066201
8609 11:56:06.066719 Set Vref, RX VrefLevel [Byte0]: 44
8610 11:56:06.069824 [Byte1]: 44
8611 11:56:06.074451
8612 11:56:06.075040 Set Vref, RX VrefLevel [Byte0]: 45
8613 11:56:06.077721 [Byte1]: 45
8614 11:56:06.082059
8615 11:56:06.082680 Set Vref, RX VrefLevel [Byte0]: 46
8616 11:56:06.085313 [Byte1]: 46
8617 11:56:06.089661
8618 11:56:06.090243 Set Vref, RX VrefLevel [Byte0]: 47
8619 11:56:06.092612 [Byte1]: 47
8620 11:56:06.097141
8621 11:56:06.097720 Set Vref, RX VrefLevel [Byte0]: 48
8622 11:56:06.100336 [Byte1]: 48
8623 11:56:06.104605
8624 11:56:06.105179 Set Vref, RX VrefLevel [Byte0]: 49
8625 11:56:06.107503 [Byte1]: 49
8626 11:56:06.112185
8627 11:56:06.112764 Set Vref, RX VrefLevel [Byte0]: 50
8628 11:56:06.115042 [Byte1]: 50
8629 11:56:06.119829
8630 11:56:06.120421 Set Vref, RX VrefLevel [Byte0]: 51
8631 11:56:06.122513 [Byte1]: 51
8632 11:56:06.127189
8633 11:56:06.127769 Set Vref, RX VrefLevel [Byte0]: 52
8634 11:56:06.131072 [Byte1]: 52
8635 11:56:06.134847
8636 11:56:06.135441 Set Vref, RX VrefLevel [Byte0]: 53
8637 11:56:06.137723 [Byte1]: 53
8638 11:56:06.142254
8639 11:56:06.142884 Set Vref, RX VrefLevel [Byte0]: 54
8640 11:56:06.145579 [Byte1]: 54
8641 11:56:06.149782
8642 11:56:06.150354 Set Vref, RX VrefLevel [Byte0]: 55
8643 11:56:06.153559 [Byte1]: 55
8644 11:56:06.157199
8645 11:56:06.157674 Set Vref, RX VrefLevel [Byte0]: 56
8646 11:56:06.160610 [Byte1]: 56
8647 11:56:06.165150
8648 11:56:06.165626 Set Vref, RX VrefLevel [Byte0]: 57
8649 11:56:06.168561 [Byte1]: 57
8650 11:56:06.172380
8651 11:56:06.172965 Set Vref, RX VrefLevel [Byte0]: 58
8652 11:56:06.175591 [Byte1]: 58
8653 11:56:06.180056
8654 11:56:06.180527 Set Vref, RX VrefLevel [Byte0]: 59
8655 11:56:06.183239 [Byte1]: 59
8656 11:56:06.187800
8657 11:56:06.188377 Set Vref, RX VrefLevel [Byte0]: 60
8658 11:56:06.190818 [Byte1]: 60
8659 11:56:06.195286
8660 11:56:06.195863 Set Vref, RX VrefLevel [Byte0]: 61
8661 11:56:06.198686 [Byte1]: 61
8662 11:56:06.202914
8663 11:56:06.203499 Set Vref, RX VrefLevel [Byte0]: 62
8664 11:56:06.206124 [Byte1]: 62
8665 11:56:06.210368
8666 11:56:06.210884 Set Vref, RX VrefLevel [Byte0]: 63
8667 11:56:06.213603 [Byte1]: 63
8668 11:56:06.218015
8669 11:56:06.218524 Set Vref, RX VrefLevel [Byte0]: 64
8670 11:56:06.221128 [Byte1]: 64
8671 11:56:06.225850
8672 11:56:06.226325 Set Vref, RX VrefLevel [Byte0]: 65
8673 11:56:06.228813 [Byte1]: 65
8674 11:56:06.233189
8675 11:56:06.233766 Set Vref, RX VrefLevel [Byte0]: 66
8676 11:56:06.236291 [Byte1]: 66
8677 11:56:06.240473
8678 11:56:06.241008 Set Vref, RX VrefLevel [Byte0]: 67
8679 11:56:06.243959 [Byte1]: 67
8680 11:56:06.248626
8681 11:56:06.249203 Set Vref, RX VrefLevel [Byte0]: 68
8682 11:56:06.251487 [Byte1]: 68
8683 11:56:06.256108
8684 11:56:06.256752 Set Vref, RX VrefLevel [Byte0]: 69
8685 11:56:06.258955 [Byte1]: 69
8686 11:56:06.263553
8687 11:56:06.264065 Set Vref, RX VrefLevel [Byte0]: 70
8688 11:56:06.266321 [Byte1]: 70
8689 11:56:06.271125
8690 11:56:06.271692 Set Vref, RX VrefLevel [Byte0]: 71
8691 11:56:06.274112 [Byte1]: 71
8692 11:56:06.278588
8693 11:56:06.279167 Set Vref, RX VrefLevel [Byte0]: 72
8694 11:56:06.281821 [Byte1]: 72
8695 11:56:06.286657
8696 11:56:06.287223 Set Vref, RX VrefLevel [Byte0]: 73
8697 11:56:06.289422 [Byte1]: 73
8698 11:56:06.293823
8699 11:56:06.294427 Final RX Vref Byte 0 = 51 to rank0
8700 11:56:06.297228 Final RX Vref Byte 1 = 61 to rank0
8701 11:56:06.300265 Final RX Vref Byte 0 = 51 to rank1
8702 11:56:06.303876 Final RX Vref Byte 1 = 61 to rank1==
8703 11:56:06.306658 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 11:56:06.313650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 11:56:06.314223 ==
8706 11:56:06.314666 DQS Delay:
8707 11:56:06.315024 DQS0 = 0, DQS1 = 0
8708 11:56:06.317033 DQM Delay:
8709 11:56:06.317503 DQM0 = 133, DQM1 = 129
8710 11:56:06.320286 DQ Delay:
8711 11:56:06.323944 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8712 11:56:06.326966 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8713 11:56:06.330170 DQ8 =114, DQ9 =120, DQ10 =132, DQ11 =122
8714 11:56:06.333642 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =136
8715 11:56:06.334209
8716 11:56:06.334645
8717 11:56:06.334993
8718 11:56:06.337219 [DramC_TX_OE_Calibration] TA2
8719 11:56:06.339933 Original DQ_B0 (3 6) =30, OEN = 27
8720 11:56:06.343484 Original DQ_B1 (3 6) =30, OEN = 27
8721 11:56:06.346488 24, 0x0, End_B0=24 End_B1=24
8722 11:56:06.346927 25, 0x0, End_B0=25 End_B1=25
8723 11:56:06.349980 26, 0x0, End_B0=26 End_B1=26
8724 11:56:06.353270 27, 0x0, End_B0=27 End_B1=27
8725 11:56:06.356743 28, 0x0, End_B0=28 End_B1=28
8726 11:56:06.359468 29, 0x0, End_B0=29 End_B1=29
8727 11:56:06.360025 30, 0x0, End_B0=30 End_B1=30
8728 11:56:06.363505 31, 0x5151, End_B0=30 End_B1=30
8729 11:56:06.366363 Byte0 end_step=30 best_step=27
8730 11:56:06.369723 Byte1 end_step=30 best_step=27
8731 11:56:06.373299 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 11:56:06.376462 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 11:56:06.376935
8734 11:56:06.377310
8735 11:56:06.383078 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8736 11:56:06.386993 CH1 RK0: MR19=303, MR18=1826
8737 11:56:06.393634 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8738 11:56:06.394202
8739 11:56:06.396458 ----->DramcWriteLeveling(PI) begin...
8740 11:56:06.397027 ==
8741 11:56:06.399831 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 11:56:06.403256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 11:56:06.403825 ==
8744 11:56:06.406943 Write leveling (Byte 0): 27 => 27
8745 11:56:06.409716 Write leveling (Byte 1): 28 => 28
8746 11:56:06.413579 DramcWriteLeveling(PI) end<-----
8747 11:56:06.414141
8748 11:56:06.414574 ==
8749 11:56:06.416841 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 11:56:06.419974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 11:56:06.420556 ==
8752 11:56:06.423403 [Gating] SW mode calibration
8753 11:56:06.430160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 11:56:06.436444 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 11:56:06.439843 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 11:56:06.443194 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 11:56:06.449845 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8758 11:56:06.453542 1 4 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
8759 11:56:06.456068 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 11:56:06.463104 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 11:56:06.466581 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 11:56:06.469597 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 11:56:06.476392 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 11:56:06.479846 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 11:56:06.482975 1 5 8 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 0)
8766 11:56:06.489705 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 0)
8767 11:56:06.493188 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8768 11:56:06.497343 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:56:06.502966 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 11:56:06.506374 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 11:56:06.509895 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 11:56:06.516510 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8773 11:56:06.519727 1 6 8 | B1->B0 | 3f3f 2424 | 0 0 | (0 0) (0 0)
8774 11:56:06.523720 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8775 11:56:06.529669 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:56:06.533068 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 11:56:06.535952 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 11:56:06.542792 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 11:56:06.546315 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 11:56:06.549938 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 11:56:06.553212 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 11:56:06.559838 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 11:56:06.562888 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8784 11:56:06.566353 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:56:06.573123 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:56:06.576061 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:56:06.579162 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:56:06.586468 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:56:06.589589 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:56:06.592832 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:56:06.599052 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:56:06.602749 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:56:06.606171 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:56:06.612752 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 11:56:06.616451 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:56:06.619405 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:56:06.626208 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 11:56:06.629201 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8799 11:56:06.632654 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 11:56:06.635775 Total UI for P1: 0, mck2ui 16
8801 11:56:06.639653 best dqsien dly found for B0: ( 1, 9, 10)
8802 11:56:06.642493 Total UI for P1: 0, mck2ui 16
8803 11:56:06.646056 best dqsien dly found for B1: ( 1, 9, 10)
8804 11:56:06.648918 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8805 11:56:06.653000 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8806 11:56:06.653566
8807 11:56:06.659061 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8808 11:56:06.662640 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8809 11:56:06.663207 [Gating] SW calibration Done
8810 11:56:06.666106 ==
8811 11:56:06.668913 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 11:56:06.672834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 11:56:06.673405 ==
8814 11:56:06.673777 RX Vref Scan: 0
8815 11:56:06.674353
8816 11:56:06.675701 RX Vref 0 -> 0, step: 1
8817 11:56:06.676214
8818 11:56:06.679147 RX Delay 0 -> 252, step: 8
8819 11:56:06.682517 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8820 11:56:06.685511 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8821 11:56:06.689209 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8822 11:56:06.695838 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8823 11:56:06.699146 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8824 11:56:06.702046 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8825 11:56:06.706193 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8826 11:56:06.708949 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8827 11:56:06.712646 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8828 11:56:06.718969 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8829 11:56:06.722622 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8830 11:56:06.725677 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8831 11:56:06.729429 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8832 11:56:06.732666 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8833 11:56:06.738961 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8834 11:56:06.742956 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8835 11:56:06.743527 ==
8836 11:56:06.745716 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 11:56:06.748960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 11:56:06.749431 ==
8839 11:56:06.752871 DQS Delay:
8840 11:56:06.753444 DQS0 = 0, DQS1 = 0
8841 11:56:06.753823 DQM Delay:
8842 11:56:06.756048 DQM0 = 138, DQM1 = 131
8843 11:56:06.756618 DQ Delay:
8844 11:56:06.758772 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8845 11:56:06.762241 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8846 11:56:06.769185 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8847 11:56:06.772436 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8848 11:56:06.773004
8849 11:56:06.773392
8850 11:56:06.773781 ==
8851 11:56:06.775904 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 11:56:06.778892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 11:56:06.779361 ==
8854 11:56:06.779729
8855 11:56:06.780069
8856 11:56:06.781938 TX Vref Scan disable
8857 11:56:06.785407 == TX Byte 0 ==
8858 11:56:06.788640 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8859 11:56:06.792058 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8860 11:56:06.792526 == TX Byte 1 ==
8861 11:56:06.799075 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8862 11:56:06.802487 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8863 11:56:06.803065 ==
8864 11:56:06.805434 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 11:56:06.809020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 11:56:06.809491 ==
8867 11:56:06.824149
8868 11:56:06.827079 TX Vref early break, caculate TX vref
8869 11:56:06.830613 TX Vref=16, minBit 1, minWin=24, winSum=390
8870 11:56:06.833922 TX Vref=18, minBit 15, minWin=23, winSum=399
8871 11:56:06.837809 TX Vref=20, minBit 13, minWin=24, winSum=407
8872 11:56:06.840561 TX Vref=22, minBit 0, minWin=25, winSum=416
8873 11:56:06.844036 TX Vref=24, minBit 0, minWin=25, winSum=420
8874 11:56:06.851014 TX Vref=26, minBit 10, minWin=25, winSum=426
8875 11:56:06.853733 TX Vref=28, minBit 10, minWin=25, winSum=425
8876 11:56:06.857383 TX Vref=30, minBit 0, minWin=26, winSum=422
8877 11:56:06.860253 TX Vref=32, minBit 10, minWin=25, winSum=416
8878 11:56:06.863852 TX Vref=34, minBit 0, minWin=24, winSum=406
8879 11:56:06.870910 TX Vref=36, minBit 10, minWin=23, winSum=395
8880 11:56:06.873750 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
8881 11:56:06.874332
8882 11:56:06.877123 Final TX Range 0 Vref 30
8883 11:56:06.877702
8884 11:56:06.878080 ==
8885 11:56:06.880111 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 11:56:06.883582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 11:56:06.886899 ==
8888 11:56:06.887485
8889 11:56:06.887871
8890 11:56:06.888223 TX Vref Scan disable
8891 11:56:06.893701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8892 11:56:06.894294 == TX Byte 0 ==
8893 11:56:06.896918 u2DelayCellOfst[0]=17 cells (5 PI)
8894 11:56:06.900242 u2DelayCellOfst[1]=13 cells (4 PI)
8895 11:56:06.903598 u2DelayCellOfst[2]=0 cells (0 PI)
8896 11:56:06.906806 u2DelayCellOfst[3]=6 cells (2 PI)
8897 11:56:06.910252 u2DelayCellOfst[4]=10 cells (3 PI)
8898 11:56:06.913326 u2DelayCellOfst[5]=20 cells (6 PI)
8899 11:56:06.917302 u2DelayCellOfst[6]=17 cells (5 PI)
8900 11:56:06.920506 u2DelayCellOfst[7]=6 cells (2 PI)
8901 11:56:06.923608 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 11:56:06.926575 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8903 11:56:06.930237 == TX Byte 1 ==
8904 11:56:06.933606 u2DelayCellOfst[8]=0 cells (0 PI)
8905 11:56:06.937932 u2DelayCellOfst[9]=6 cells (2 PI)
8906 11:56:06.940311 u2DelayCellOfst[10]=10 cells (3 PI)
8907 11:56:06.943553 u2DelayCellOfst[11]=6 cells (2 PI)
8908 11:56:06.944119 u2DelayCellOfst[12]=17 cells (5 PI)
8909 11:56:06.946901 u2DelayCellOfst[13]=17 cells (5 PI)
8910 11:56:06.950259 u2DelayCellOfst[14]=17 cells (5 PI)
8911 11:56:06.953506 u2DelayCellOfst[15]=17 cells (5 PI)
8912 11:56:06.959971 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 11:56:06.963435 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 11:56:06.964004 DramC Write-DBI on
8915 11:56:06.967016 ==
8916 11:56:06.967639 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:56:06.973631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:56:06.974201 ==
8919 11:56:06.974621
8920 11:56:06.974972
8921 11:56:06.976311 TX Vref Scan disable
8922 11:56:06.976780 == TX Byte 0 ==
8923 11:56:06.983286 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8924 11:56:06.983841 == TX Byte 1 ==
8925 11:56:06.986741 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8926 11:56:06.989867 DramC Write-DBI off
8927 11:56:06.990470
8928 11:56:06.990856 [DATLAT]
8929 11:56:06.993290 Freq=1600, CH1 RK1
8930 11:56:06.993760
8931 11:56:06.994130 DATLAT Default: 0xf
8932 11:56:06.996426 0, 0xFFFF, sum = 0
8933 11:56:06.996902 1, 0xFFFF, sum = 0
8934 11:56:06.999533 2, 0xFFFF, sum = 0
8935 11:56:07.000010 3, 0xFFFF, sum = 0
8936 11:56:07.002873 4, 0xFFFF, sum = 0
8937 11:56:07.003354 5, 0xFFFF, sum = 0
8938 11:56:07.006297 6, 0xFFFF, sum = 0
8939 11:56:07.006811 7, 0xFFFF, sum = 0
8940 11:56:07.009705 8, 0xFFFF, sum = 0
8941 11:56:07.010280 9, 0xFFFF, sum = 0
8942 11:56:07.013001 10, 0xFFFF, sum = 0
8943 11:56:07.016540 11, 0xFFFF, sum = 0
8944 11:56:07.017112 12, 0xFFFF, sum = 0
8945 11:56:07.019753 13, 0xFFFF, sum = 0
8946 11:56:07.020229 14, 0x0, sum = 1
8947 11:56:07.022985 15, 0x0, sum = 2
8948 11:56:07.023461 16, 0x0, sum = 3
8949 11:56:07.023840 17, 0x0, sum = 4
8950 11:56:07.026514 best_step = 15
8951 11:56:07.027085
8952 11:56:07.027459 ==
8953 11:56:07.029767 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 11:56:07.033249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 11:56:07.033717 ==
8956 11:56:07.036430 RX Vref Scan: 0
8957 11:56:07.037020
8958 11:56:07.039461 RX Vref 0 -> 0, step: 1
8959 11:56:07.039931
8960 11:56:07.040302 RX Delay 19 -> 252, step: 4
8961 11:56:07.046630 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8962 11:56:07.050278 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
8963 11:56:07.053491 iDelay=195, Bit 2, Center 120 (75 ~ 166) 92
8964 11:56:07.056321 iDelay=195, Bit 3, Center 132 (87 ~ 178) 92
8965 11:56:07.060194 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8966 11:56:07.066438 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8967 11:56:07.069784 iDelay=195, Bit 6, Center 140 (95 ~ 186) 92
8968 11:56:07.073344 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8969 11:56:07.076338 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8970 11:56:07.079777 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8971 11:56:07.083431 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8972 11:56:07.089846 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8973 11:56:07.092911 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8974 11:56:07.096349 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8975 11:56:07.099416 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8976 11:56:07.106033 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8977 11:56:07.106860 ==
8978 11:56:07.109516 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 11:56:07.112472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 11:56:07.112945 ==
8981 11:56:07.113385 DQS Delay:
8982 11:56:07.115908 DQS0 = 0, DQS1 = 0
8983 11:56:07.116350 DQM Delay:
8984 11:56:07.119245 DQM0 = 133, DQM1 = 129
8985 11:56:07.119739 DQ Delay:
8986 11:56:07.122751 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8987 11:56:07.126014 DQ4 =134, DQ5 =146, DQ6 =140, DQ7 =132
8988 11:56:07.129139 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8989 11:56:07.132756 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =140
8990 11:56:07.133302
8991 11:56:07.133748
8992 11:56:07.135812
8993 11:56:07.136237 [DramC_TX_OE_Calibration] TA2
8994 11:56:07.139019 Original DQ_B0 (3 6) =30, OEN = 27
8995 11:56:07.142520 Original DQ_B1 (3 6) =30, OEN = 27
8996 11:56:07.146077 24, 0x0, End_B0=24 End_B1=24
8997 11:56:07.149594 25, 0x0, End_B0=25 End_B1=25
8998 11:56:07.153071 26, 0x0, End_B0=26 End_B1=26
8999 11:56:07.153647 27, 0x0, End_B0=27 End_B1=27
9000 11:56:07.156583 28, 0x0, End_B0=28 End_B1=28
9001 11:56:07.159026 29, 0x0, End_B0=29 End_B1=29
9002 11:56:07.162844 30, 0x0, End_B0=30 End_B1=30
9003 11:56:07.166009 31, 0x4545, End_B0=30 End_B1=30
9004 11:56:07.166626 Byte0 end_step=30 best_step=27
9005 11:56:07.169426 Byte1 end_step=30 best_step=27
9006 11:56:07.173035 Byte0 TX OE(2T, 0.5T) = (3, 3)
9007 11:56:07.175869 Byte1 TX OE(2T, 0.5T) = (3, 3)
9008 11:56:07.176434
9009 11:56:07.176809
9010 11:56:07.182813 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9011 11:56:07.186012 CH1 RK1: MR19=303, MR18=1D08
9012 11:56:07.192386 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9013 11:56:07.195858 [RxdqsGatingPostProcess] freq 1600
9014 11:56:07.202988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9015 11:56:07.205626 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 11:56:07.206192 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 11:56:07.208835 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 11:56:07.212108 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 11:56:07.215635 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 11:56:07.218974 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 11:56:07.222229 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 11:56:07.225688 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 11:56:07.228850 Pre-setting of DQS Precalculation
9024 11:56:07.232180 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9025 11:56:07.242065 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9026 11:56:07.248877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9027 11:56:07.249455
9028 11:56:07.249867
9029 11:56:07.252223 [Calibration Summary] 3200 Mbps
9030 11:56:07.252810 CH 0, Rank 0
9031 11:56:07.256071 SW Impedance : PASS
9032 11:56:07.256653 DUTY Scan : NO K
9033 11:56:07.258562 ZQ Calibration : PASS
9034 11:56:07.261918 Jitter Meter : NO K
9035 11:56:07.262410 CBT Training : PASS
9036 11:56:07.266261 Write leveling : PASS
9037 11:56:07.269026 RX DQS gating : PASS
9038 11:56:07.269598 RX DQ/DQS(RDDQC) : PASS
9039 11:56:07.272101 TX DQ/DQS : PASS
9040 11:56:07.275299 RX DATLAT : PASS
9041 11:56:07.275871 RX DQ/DQS(Engine): PASS
9042 11:56:07.278622 TX OE : PASS
9043 11:56:07.279191 All Pass.
9044 11:56:07.279564
9045 11:56:07.282121 CH 0, Rank 1
9046 11:56:07.282812 SW Impedance : PASS
9047 11:56:07.285531 DUTY Scan : NO K
9048 11:56:07.288878 ZQ Calibration : PASS
9049 11:56:07.289453 Jitter Meter : NO K
9050 11:56:07.292182 CBT Training : PASS
9051 11:56:07.295217 Write leveling : PASS
9052 11:56:07.295786 RX DQS gating : PASS
9053 11:56:07.298965 RX DQ/DQS(RDDQC) : PASS
9054 11:56:07.299547 TX DQ/DQS : PASS
9055 11:56:07.302081 RX DATLAT : PASS
9056 11:56:07.305412 RX DQ/DQS(Engine): PASS
9057 11:56:07.305988 TX OE : PASS
9058 11:56:07.308716 All Pass.
9059 11:56:07.309291
9060 11:56:07.309667 CH 1, Rank 0
9061 11:56:07.311940 SW Impedance : PASS
9062 11:56:07.312415 DUTY Scan : NO K
9063 11:56:07.315049 ZQ Calibration : PASS
9064 11:56:07.318437 Jitter Meter : NO K
9065 11:56:07.318912 CBT Training : PASS
9066 11:56:07.322193 Write leveling : PASS
9067 11:56:07.325433 RX DQS gating : PASS
9068 11:56:07.326007 RX DQ/DQS(RDDQC) : PASS
9069 11:56:07.328652 TX DQ/DQS : PASS
9070 11:56:07.332128 RX DATLAT : PASS
9071 11:56:07.332607 RX DQ/DQS(Engine): PASS
9072 11:56:07.335076 TX OE : PASS
9073 11:56:07.335553 All Pass.
9074 11:56:07.335927
9075 11:56:07.338251 CH 1, Rank 1
9076 11:56:07.338886 SW Impedance : PASS
9077 11:56:07.341932 DUTY Scan : NO K
9078 11:56:07.344880 ZQ Calibration : PASS
9079 11:56:07.345348 Jitter Meter : NO K
9080 11:56:07.348605 CBT Training : PASS
9081 11:56:07.349197 Write leveling : PASS
9082 11:56:07.351831 RX DQS gating : PASS
9083 11:56:07.355180 RX DQ/DQS(RDDQC) : PASS
9084 11:56:07.355680 TX DQ/DQS : PASS
9085 11:56:07.358165 RX DATLAT : PASS
9086 11:56:07.361629 RX DQ/DQS(Engine): PASS
9087 11:56:07.362172 TX OE : PASS
9088 11:56:07.365146 All Pass.
9089 11:56:07.365723
9090 11:56:07.366100 DramC Write-DBI on
9091 11:56:07.368642 PER_BANK_REFRESH: Hybrid Mode
9092 11:56:07.371623 TX_TRACKING: ON
9093 11:56:07.378831 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9094 11:56:07.388335 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9095 11:56:07.395319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 11:56:07.398545 [FAST_K] Save calibration result to emmc
9097 11:56:07.401789 sync common calibartion params.
9098 11:56:07.402364 sync cbt_mode0:1, 1:1
9099 11:56:07.404875 dram_init: ddr_geometry: 2
9100 11:56:07.408648 dram_init: ddr_geometry: 2
9101 11:56:07.409297 dram_init: ddr_geometry: 2
9102 11:56:07.411865 0:dram_rank_size:100000000
9103 11:56:07.414995 1:dram_rank_size:100000000
9104 11:56:07.421361 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9105 11:56:07.421975 DFS_SHUFFLE_HW_MODE: ON
9106 11:56:07.424940 dramc_set_vcore_voltage set vcore to 725000
9107 11:56:07.428356 Read voltage for 1600, 0
9108 11:56:07.428930 Vio18 = 0
9109 11:56:07.431467 Vcore = 725000
9110 11:56:07.431938 Vdram = 0
9111 11:56:07.432311 Vddq = 0
9112 11:56:07.434572 Vmddr = 0
9113 11:56:07.435043 switch to 3200 Mbps bootup
9114 11:56:07.438021 [DramcRunTimeConfig]
9115 11:56:07.438553 PHYPLL
9116 11:56:07.441473 DPM_CONTROL_AFTERK: ON
9117 11:56:07.441899 PER_BANK_REFRESH: ON
9118 11:56:07.445221 REFRESH_OVERHEAD_REDUCTION: ON
9119 11:56:07.448028 CMD_PICG_NEW_MODE: OFF
9120 11:56:07.448456 XRTWTW_NEW_MODE: ON
9121 11:56:07.451407 XRTRTR_NEW_MODE: ON
9122 11:56:07.451888 TX_TRACKING: ON
9123 11:56:07.454468 RDSEL_TRACKING: OFF
9124 11:56:07.458048 DQS Precalculation for DVFS: ON
9125 11:56:07.458504 RX_TRACKING: OFF
9126 11:56:07.461961 HW_GATING DBG: ON
9127 11:56:07.462566 ZQCS_ENABLE_LP4: ON
9128 11:56:07.464745 RX_PICG_NEW_MODE: ON
9129 11:56:07.465172 TX_PICG_NEW_MODE: ON
9130 11:56:07.467994 ENABLE_RX_DCM_DPHY: ON
9131 11:56:07.471149 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9132 11:56:07.474775 DUMMY_READ_FOR_TRACKING: OFF
9133 11:56:07.475306 !!! SPM_CONTROL_AFTERK: OFF
9134 11:56:07.478189 !!! SPM could not control APHY
9135 11:56:07.481284 IMPEDANCE_TRACKING: ON
9136 11:56:07.481713 TEMP_SENSOR: ON
9137 11:56:07.484562 HW_SAVE_FOR_SR: OFF
9138 11:56:07.487978 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9139 11:56:07.491692 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9140 11:56:07.492224 Read ODT Tracking: ON
9141 11:56:07.494823 Refresh Rate DeBounce: ON
9142 11:56:07.499089 DFS_NO_QUEUE_FLUSH: ON
9143 11:56:07.501512 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9144 11:56:07.501939 ENABLE_DFS_RUNTIME_MRW: OFF
9145 11:56:07.505084 DDR_RESERVE_NEW_MODE: ON
9146 11:56:07.508597 MR_CBT_SWITCH_FREQ: ON
9147 11:56:07.509132 =========================
9148 11:56:07.528663 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9149 11:56:07.531522 dram_init: ddr_geometry: 2
9150 11:56:07.550127 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9151 11:56:07.553283 dram_init: dram init end (result: 0)
9152 11:56:07.559773 DRAM-K: Full calibration passed in 24505 msecs
9153 11:56:07.563308 MRC: failed to locate region type 0.
9154 11:56:07.563778 DRAM rank0 size:0x100000000,
9155 11:56:07.566730 DRAM rank1 size=0x100000000
9156 11:56:07.576661 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9157 11:56:07.583481 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9158 11:56:07.590000 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9159 11:56:07.597502 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9160 11:56:07.599886 DRAM rank0 size:0x100000000,
9161 11:56:07.603532 DRAM rank1 size=0x100000000
9162 11:56:07.604105 CBMEM:
9163 11:56:07.606573 IMD: root @ 0xfffff000 254 entries.
9164 11:56:07.610095 IMD: root @ 0xffffec00 62 entries.
9165 11:56:07.613553 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9166 11:56:07.616267 WARNING: RO_VPD is uninitialized or empty.
9167 11:56:07.623318 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9168 11:56:07.630172 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9169 11:56:07.642503 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9170 11:56:07.654145 BS: romstage times (exec / console): total (unknown) / 24002 ms
9171 11:56:07.654775
9172 11:56:07.655156
9173 11:56:07.663923 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9174 11:56:07.667576 ARM64: Exception handlers installed.
9175 11:56:07.670737 ARM64: Testing exception
9176 11:56:07.674116 ARM64: Done test exception
9177 11:56:07.674627 Enumerating buses...
9178 11:56:07.677728 Show all devs... Before device enumeration.
9179 11:56:07.680727 Root Device: enabled 1
9180 11:56:07.684048 CPU_CLUSTER: 0: enabled 1
9181 11:56:07.684577 CPU: 00: enabled 1
9182 11:56:07.687170 Compare with tree...
9183 11:56:07.687641 Root Device: enabled 1
9184 11:56:07.690322 CPU_CLUSTER: 0: enabled 1
9185 11:56:07.694476 CPU: 00: enabled 1
9186 11:56:07.695037 Root Device scanning...
9187 11:56:07.697591 scan_static_bus for Root Device
9188 11:56:07.700901 CPU_CLUSTER: 0 enabled
9189 11:56:07.704038 scan_static_bus for Root Device done
9190 11:56:07.707293 scan_bus: bus Root Device finished in 8 msecs
9191 11:56:07.707863 done
9192 11:56:07.713812 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9193 11:56:07.716796 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9194 11:56:07.723889 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9195 11:56:07.727016 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9196 11:56:07.730654 Allocating resources...
9197 11:56:07.734066 Reading resources...
9198 11:56:07.737040 Root Device read_resources bus 0 link: 0
9199 11:56:07.737608 DRAM rank0 size:0x100000000,
9200 11:56:07.740254 DRAM rank1 size=0x100000000
9201 11:56:07.743823 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9202 11:56:07.747141 CPU: 00 missing read_resources
9203 11:56:07.750445 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9204 11:56:07.756982 Root Device read_resources bus 0 link: 0 done
9205 11:56:07.757544 Done reading resources.
9206 11:56:07.763905 Show resources in subtree (Root Device)...After reading.
9207 11:56:07.767065 Root Device child on link 0 CPU_CLUSTER: 0
9208 11:56:07.770235 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 11:56:07.780112 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 11:56:07.780675 CPU: 00
9211 11:56:07.783639 Root Device assign_resources, bus 0 link: 0
9212 11:56:07.787298 CPU_CLUSTER: 0 missing set_resources
9213 11:56:07.793627 Root Device assign_resources, bus 0 link: 0 done
9214 11:56:07.794199 Done setting resources.
9215 11:56:07.800257 Show resources in subtree (Root Device)...After assigning values.
9216 11:56:07.803402 Root Device child on link 0 CPU_CLUSTER: 0
9217 11:56:07.807110 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 11:56:07.816538 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 11:56:07.817118 CPU: 00
9220 11:56:07.819928 Done allocating resources.
9221 11:56:07.823568 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9222 11:56:07.827141 Enabling resources...
9223 11:56:07.827617 done.
9224 11:56:07.833186 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9225 11:56:07.833753 Initializing devices...
9226 11:56:07.836940 Root Device init
9227 11:56:07.837429 init hardware done!
9228 11:56:07.839979 0x00000018: ctrlr->caps
9229 11:56:07.843810 52.000 MHz: ctrlr->f_max
9230 11:56:07.844399 0.400 MHz: ctrlr->f_min
9231 11:56:07.847105 0x40ff8080: ctrlr->voltages
9232 11:56:07.847697 sclk: 390625
9233 11:56:07.850070 Bus Width = 1
9234 11:56:07.850677 sclk: 390625
9235 11:56:07.853367 Bus Width = 1
9236 11:56:07.853950 Early init status = 3
9237 11:56:07.859934 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9238 11:56:07.863456 in-header: 03 fc 00 00 01 00 00 00
9239 11:56:07.863983 in-data: 00
9240 11:56:07.870462 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9241 11:56:07.873360 in-header: 03 fd 00 00 00 00 00 00
9242 11:56:07.876846 in-data:
9243 11:56:07.879899 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 11:56:07.883515 in-header: 03 fc 00 00 01 00 00 00
9245 11:56:07.887046 in-data: 00
9246 11:56:07.890259 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9247 11:56:07.895768 in-header: 03 fd 00 00 00 00 00 00
9248 11:56:07.899059 in-data:
9249 11:56:07.902109 [SSUSB] Setting up USB HOST controller...
9250 11:56:07.905930 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 11:56:07.909076 [SSUSB] phy power-on done.
9252 11:56:07.912345 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 11:56:07.919121 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 11:56:07.922280 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 11:56:07.929214 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 11:56:07.935477 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 11:56:07.942111 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 11:56:07.948799 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 11:56:07.955046 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9260 11:56:07.958326 SPM: binary array size = 0x9dc
9261 11:56:07.962016 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 11:56:07.968600 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 11:56:07.975111 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 11:56:07.978748 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 11:56:07.984925 configure_display: Starting display init
9266 11:56:08.018794 anx7625_power_on_init: Init interface.
9267 11:56:08.022351 anx7625_disable_pd_protocol: Disabled PD feature.
9268 11:56:08.025334 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 11:56:08.053973 anx7625_start_dp_work: Secure OCM version=00
9270 11:56:08.057280 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 11:56:08.071357 sp_tx_get_edid_block: EDID Block = 1
9272 11:56:08.174015 Extracted contents:
9273 11:56:08.177827 header: 00 ff ff ff ff ff ff 00
9274 11:56:08.180681 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 11:56:08.184212 version: 01 04
9276 11:56:08.187321 basic params: 95 1f 11 78 0a
9277 11:56:08.190272 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 11:56:08.193960 established: 00 00 00
9279 11:56:08.200612 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 11:56:08.203862 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 11:56:08.210498 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 11:56:08.216918 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 11:56:08.223808 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 11:56:08.226891 extensions: 00
9285 11:56:08.227365 checksum: fb
9286 11:56:08.227742
9287 11:56:08.230360 Manufacturer: IVO Model 57d Serial Number 0
9288 11:56:08.233673 Made week 0 of 2020
9289 11:56:08.234247 EDID version: 1.4
9290 11:56:08.236828 Digital display
9291 11:56:08.240197 6 bits per primary color channel
9292 11:56:08.240679 DisplayPort interface
9293 11:56:08.243338 Maximum image size: 31 cm x 17 cm
9294 11:56:08.246753 Gamma: 220%
9295 11:56:08.247211 Check DPMS levels
9296 11:56:08.250224 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 11:56:08.253541 First detailed timing is preferred timing
9298 11:56:08.256704 Established timings supported:
9299 11:56:08.260472 Standard timings supported:
9300 11:56:08.263470 Detailed timings
9301 11:56:08.266981 Hex of detail: 383680a07038204018303c0035ae10000019
9302 11:56:08.270156 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 11:56:08.276456 0780 0798 07c8 0820 hborder 0
9304 11:56:08.279908 0438 043b 0447 0458 vborder 0
9305 11:56:08.283268 -hsync -vsync
9306 11:56:08.283807 Did detailed timing
9307 11:56:08.290049 Hex of detail: 000000000000000000000000000000000000
9308 11:56:08.290655 Manufacturer-specified data, tag 0
9309 11:56:08.296788 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 11:56:08.299973 ASCII string: InfoVision
9311 11:56:08.303051 Hex of detail: 000000fe00523134304e574635205248200a
9312 11:56:08.306500 ASCII string: R140NWF5 RH
9313 11:56:08.307144 Checksum
9314 11:56:08.309829 Checksum: 0xfb (valid)
9315 11:56:08.313362 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 11:56:08.316507 DSI data_rate: 832800000 bps
9317 11:56:08.323594 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 11:56:08.326624 anx7625_parse_edid: pixelclock(138800).
9319 11:56:08.330064 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 11:56:08.333247 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 11:56:08.336513 anx7625_dsi_config: config dsi.
9322 11:56:08.343027 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 11:56:08.356161 anx7625_dsi_config: success to config DSI
9324 11:56:08.359298 anx7625_dp_start: MIPI phy setup OK.
9325 11:56:08.362759 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 11:56:08.366017 mtk_ddp_mode_set invalid vrefresh 60
9327 11:56:08.369510 main_disp_path_setup
9328 11:56:08.370088 ovl_layer_smi_id_en
9329 11:56:08.372459 ovl_layer_smi_id_en
9330 11:56:08.372922 ccorr_config
9331 11:56:08.373319 aal_config
9332 11:56:08.376035 gamma_config
9333 11:56:08.376589 postmask_config
9334 11:56:08.379342 dither_config
9335 11:56:08.382896 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 11:56:08.389134 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 11:56:08.393076 Root Device init finished in 553 msecs
9338 11:56:08.395856 CPU_CLUSTER: 0 init
9339 11:56:08.402681 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 11:56:08.406153 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 11:56:08.409249 APU_MBOX 0x190000b0 = 0x10001
9342 11:56:08.412503 APU_MBOX 0x190001b0 = 0x10001
9343 11:56:08.415667 APU_MBOX 0x190005b0 = 0x10001
9344 11:56:08.419049 APU_MBOX 0x190006b0 = 0x10001
9345 11:56:08.422503 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 11:56:08.435038 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9347 11:56:08.447445 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 11:56:08.454066 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 11:56:08.465823 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9350 11:56:08.475050 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 11:56:08.478758 CPU_CLUSTER: 0 init finished in 81 msecs
9352 11:56:08.481526 Devices initialized
9353 11:56:08.484899 Show all devs... After init.
9354 11:56:08.485469 Root Device: enabled 1
9355 11:56:08.488416 CPU_CLUSTER: 0: enabled 1
9356 11:56:08.491793 CPU: 00: enabled 1
9357 11:56:08.494984 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9358 11:56:08.498231 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 11:56:08.501641 ELOG: NV offset 0x57f000 size 0x1000
9360 11:56:08.508296 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9361 11:56:08.515043 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 11:56:08.518495 ELOG: Event(17) added with size 13 at 2023-11-23 11:55:33 UTC
9363 11:56:08.521256 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 11:56:08.525549 in-header: 03 30 00 00 2c 00 00 00
9365 11:56:08.538515 in-data: 2f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 11:56:08.545325 ELOG: Event(A1) added with size 10 at 2023-11-23 11:55:33 UTC
9367 11:56:08.551625 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 11:56:08.558484 ELOG: Event(A0) added with size 9 at 2023-11-23 11:55:33 UTC
9369 11:56:08.561505 elog_add_boot_reason: Logged dev mode boot
9370 11:56:08.564718 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 11:56:08.568169 Finalize devices...
9372 11:56:08.568732 Devices finalized
9373 11:56:08.575309 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 11:56:08.578074 Writing coreboot table at 0xffe64000
9375 11:56:08.581584 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 11:56:08.584445 1. 0000000040000000-00000000400fffff: RAM
9377 11:56:08.591243 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 11:56:08.594426 3. 000000004032b000-00000000545fffff: RAM
9379 11:56:08.597734 4. 0000000054600000-000000005465ffff: BL31
9380 11:56:08.601070 5. 0000000054660000-00000000ffe63fff: RAM
9381 11:56:08.607607 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 11:56:08.610996 7. 0000000100000000-000000023fffffff: RAM
9383 11:56:08.614279 Passing 5 GPIOs to payload:
9384 11:56:08.617686 NAME | PORT | POLARITY | VALUE
9385 11:56:08.621107 EC in RW | 0x000000aa | low | undefined
9386 11:56:08.627711 EC interrupt | 0x00000005 | low | undefined
9387 11:56:08.631117 TPM interrupt | 0x000000ab | high | undefined
9388 11:56:08.637853 SD card detect | 0x00000011 | high | undefined
9389 11:56:08.640829 speaker enable | 0x00000093 | high | undefined
9390 11:56:08.644466 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 11:56:08.647895 in-header: 03 f9 00 00 02 00 00 00
9392 11:56:08.648464 in-data: 02 00
9393 11:56:08.651046 ADC[4]: Raw value=900295 ID=7
9394 11:56:08.654499 ADC[3]: Raw value=212810 ID=1
9395 11:56:08.655059 RAM Code: 0x71
9396 11:56:08.657894 ADC[6]: Raw value=74502 ID=0
9397 11:56:08.661241 ADC[5]: Raw value=212072 ID=1
9398 11:56:08.661737 SKU Code: 0x1
9399 11:56:08.667652 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f933
9400 11:56:08.671084 coreboot table: 964 bytes.
9401 11:56:08.674526 IMD ROOT 0. 0xfffff000 0x00001000
9402 11:56:08.677811 IMD SMALL 1. 0xffffe000 0x00001000
9403 11:56:08.681085 RO MCACHE 2. 0xffffc000 0x00001104
9404 11:56:08.684358 CONSOLE 3. 0xfff7c000 0x00080000
9405 11:56:08.687887 FMAP 4. 0xfff7b000 0x00000452
9406 11:56:08.690993 TIME STAMP 5. 0xfff7a000 0x00000910
9407 11:56:08.694821 VBOOT WORK 6. 0xfff66000 0x00014000
9408 11:56:08.697677 RAMOOPS 7. 0xffe66000 0x00100000
9409 11:56:08.701028 COREBOOT 8. 0xffe64000 0x00002000
9410 11:56:08.701607 IMD small region:
9411 11:56:08.704200 IMD ROOT 0. 0xffffec00 0x00000400
9412 11:56:08.707908 VPD 1. 0xffffeb80 0x0000006c
9413 11:56:08.710773 MMC STATUS 2. 0xffffeb60 0x00000004
9414 11:56:08.717473 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 11:56:08.721243 Probing TPM: done!
9416 11:56:08.723909 Connected to device vid:did:rid of 1ae0:0028:00
9417 11:56:08.734049 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9418 11:56:08.737776 Initialized TPM device CR50 revision 0
9419 11:56:08.741440 Checking cr50 for pending updates
9420 11:56:08.744524 Reading cr50 TPM mode
9421 11:56:08.753299 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 11:56:08.759952 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 11:56:08.800050 read SPI 0x3990ec 0x4f1b0: 34854 us, 9296 KB/s, 74.368 Mbps
9424 11:56:08.803656 Checking segment from ROM address 0x40100000
9425 11:56:08.806555 Checking segment from ROM address 0x4010001c
9426 11:56:08.813186 Loading segment from ROM address 0x40100000
9427 11:56:08.813764 code (compression=0)
9428 11:56:08.823101 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 11:56:08.829805 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 11:56:08.830434 it's not compressed!
9431 11:56:08.836895 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 11:56:08.839729 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 11:56:08.860157 Loading segment from ROM address 0x4010001c
9434 11:56:08.860704 Entry Point 0x80000000
9435 11:56:08.863480 Loaded segments
9436 11:56:08.867350 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 11:56:08.873918 Jumping to boot code at 0x80000000(0xffe64000)
9438 11:56:08.880483 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 11:56:08.886990 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 11:56:08.894946 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9441 11:56:08.898187 Checking segment from ROM address 0x40100000
9442 11:56:08.901626 Checking segment from ROM address 0x4010001c
9443 11:56:08.908199 Loading segment from ROM address 0x40100000
9444 11:56:08.908767 code (compression=1)
9445 11:56:08.915039 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 11:56:08.924589 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 11:56:08.925204 using LZMA
9448 11:56:08.933052 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 11:56:08.940042 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 11:56:08.943356 Loading segment from ROM address 0x4010001c
9451 11:56:08.943830 Entry Point 0x54601000
9452 11:56:08.946292 Loaded segments
9453 11:56:08.949538 NOTICE: MT8192 bl31_setup
9454 11:56:08.956920 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 11:56:08.960135 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 11:56:08.963444 WARNING: region 0:
9457 11:56:08.967238 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 11:56:08.967807 WARNING: region 1:
9459 11:56:08.973917 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 11:56:08.976935 WARNING: region 2:
9461 11:56:08.980635 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 11:56:08.983615 WARNING: region 3:
9463 11:56:08.987235 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 11:56:08.991022 WARNING: region 4:
9465 11:56:08.994107 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 11:56:08.996955 WARNING: region 5:
9467 11:56:09.000635 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 11:56:09.003875 WARNING: region 6:
9469 11:56:09.007341 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 11:56:09.007912 WARNING: region 7:
9471 11:56:09.013752 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 11:56:09.021123 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 11:56:09.023546 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 11:56:09.027153 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 11:56:09.030894 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 11:56:09.036993 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 11:56:09.040483 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 11:56:09.046905 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 11:56:09.050227 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 11:56:09.053598 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 11:56:09.060549 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 11:56:09.063850 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 11:56:09.067497 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 11:56:09.073940 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 11:56:09.077278 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 11:56:09.083911 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 11:56:09.086997 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 11:56:09.090957 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 11:56:09.097280 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 11:56:09.100573 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 11:56:09.104329 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 11:56:09.110712 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 11:56:09.114042 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 11:56:09.120827 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 11:56:09.123583 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 11:56:09.126976 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 11:56:09.133871 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 11:56:09.137319 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 11:56:09.144059 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 11:56:09.147070 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 11:56:09.150743 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 11:56:09.157223 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 11:56:09.160703 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 11:56:09.163815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 11:56:09.170752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 11:56:09.174070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 11:56:09.177642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 11:56:09.181147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 11:56:09.187339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 11:56:09.191062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 11:56:09.194522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 11:56:09.197382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 11:56:09.204172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 11:56:09.207218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 11:56:09.210607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 11:56:09.214379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 11:56:09.220866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 11:56:09.223980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 11:56:09.227037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 11:56:09.234069 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 11:56:09.237462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 11:56:09.241085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 11:56:09.247668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 11:56:09.250767 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 11:56:09.257418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 11:56:09.260860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 11:56:09.263908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 11:56:09.270997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 11:56:09.274007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 11:56:09.281272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 11:56:09.284192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 11:56:09.291330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 11:56:09.294600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 11:56:09.301151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 11:56:09.304251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 11:56:09.307494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 11:56:09.314365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 11:56:09.317942 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 11:56:09.324050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 11:56:09.327299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 11:56:09.330979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 11:56:09.337822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 11:56:09.340948 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 11:56:09.347788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 11:56:09.351083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 11:56:09.357651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 11:56:09.360676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 11:56:09.364119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 11:56:09.370957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 11:56:09.374497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 11:56:09.381360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 11:56:09.384234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 11:56:09.391152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 11:56:09.394529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 11:56:09.401038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 11:56:09.404544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 11:56:09.408124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 11:56:09.414438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 11:56:09.417783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 11:56:09.424095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 11:56:09.427839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 11:56:09.431067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 11:56:09.438029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 11:56:09.441103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 11:56:09.448339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 11:56:09.451266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 11:56:09.457805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 11:56:09.461429 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 11:56:09.464261 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 11:56:09.467644 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 11:56:09.474432 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 11:56:09.477994 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 11:56:09.481163 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 11:56:09.487787 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 11:56:09.491125 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 11:56:09.498059 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 11:56:09.501162 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 11:56:09.505277 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 11:56:09.511631 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 11:56:09.514739 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 11:56:09.517827 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 11:56:09.524884 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 11:56:09.528165 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 11:56:09.534910 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 11:56:09.538236 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 11:56:09.541756 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 11:56:09.548263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 11:56:09.551983 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 11:56:09.554947 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 11:56:09.561886 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 11:56:09.564589 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 11:56:09.568192 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 11:56:09.571209 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 11:56:09.578085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 11:56:09.581746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 11:56:09.584832 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 11:56:09.591864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 11:56:09.595287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 11:56:09.598218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 11:56:09.604976 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 11:56:09.608096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 11:56:09.611806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 11:56:09.618429 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 11:56:09.621625 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 11:56:09.628794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 11:56:09.631488 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 11:56:09.635119 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 11:56:09.641723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 11:56:09.645291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 11:56:09.651787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 11:56:09.654878 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 11:56:09.658325 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 11:56:09.664792 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 11:56:09.668021 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 11:56:09.674650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 11:56:09.677931 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 11:56:09.681296 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 11:56:09.688077 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 11:56:09.691357 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 11:56:09.697744 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 11:56:09.701157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 11:56:09.704693 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 11:56:09.711483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 11:56:09.714515 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 11:56:09.717908 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 11:56:09.724190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 11:56:09.727654 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 11:56:09.734585 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 11:56:09.737723 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 11:56:09.741069 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 11:56:09.747853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 11:56:09.751116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 11:56:09.757757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 11:56:09.761038 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 11:56:09.764124 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 11:56:09.770991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 11:56:09.773954 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 11:56:09.780713 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 11:56:09.783938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 11:56:09.787277 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 11:56:09.794014 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 11:56:09.797302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 11:56:09.803881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 11:56:09.807097 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 11:56:09.810688 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 11:56:09.817640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 11:56:09.820361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 11:56:09.826688 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 11:56:09.830598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 11:56:09.833883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 11:56:09.840234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 11:56:09.843408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 11:56:09.850327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 11:56:09.853655 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 11:56:09.856888 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 11:56:09.863424 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 11:56:09.866771 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 11:56:09.870200 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 11:56:09.876699 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 11:56:09.879906 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 11:56:09.886476 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 11:56:09.890054 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 11:56:09.896726 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 11:56:09.900093 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 11:56:09.903523 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 11:56:09.910039 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 11:56:09.913680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 11:56:09.920076 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 11:56:09.923277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 11:56:09.926455 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 11:56:09.933600 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 11:56:09.937240 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 11:56:09.943735 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 11:56:09.946816 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 11:56:09.950506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 11:56:09.956625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 11:56:09.960142 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 11:56:09.966938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 11:56:09.970101 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 11:56:09.973377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 11:56:09.980434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 11:56:09.983291 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 11:56:09.990170 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 11:56:09.993731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 11:56:10.000349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 11:56:10.003628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 11:56:10.006737 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 11:56:10.013464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 11:56:10.017201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 11:56:10.023195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 11:56:10.026785 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 11:56:10.033355 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 11:56:10.036778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 11:56:10.040211 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 11:56:10.046533 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 11:56:10.050415 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 11:56:10.056965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 11:56:10.061237 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 11:56:10.063049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 11:56:10.069918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 11:56:10.073205 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 11:56:10.076999 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 11:56:10.080141 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 11:56:10.086895 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 11:56:10.089771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 11:56:10.093166 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 11:56:10.099463 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 11:56:10.102886 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 11:56:10.106153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 11:56:10.113241 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 11:56:10.116549 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 11:56:10.122880 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 11:56:10.126345 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 11:56:10.129330 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 11:56:10.136641 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 11:56:10.139335 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 11:56:10.142763 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 11:56:10.149286 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 11:56:10.152683 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 11:56:10.155985 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 11:56:10.162914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 11:56:10.166495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 11:56:10.172837 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 11:56:10.176114 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 11:56:10.179263 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 11:56:10.186140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 11:56:10.189609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 11:56:10.192818 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 11:56:10.199652 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 11:56:10.203065 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 11:56:10.206103 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 11:56:10.212733 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 11:56:10.215840 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 11:56:10.222682 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 11:56:10.225934 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 11:56:10.229214 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 11:56:10.236466 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 11:56:10.238949 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 11:56:10.242645 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 11:56:10.249580 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 11:56:10.252395 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 11:56:10.255693 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 11:56:10.259520 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 11:56:10.266091 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 11:56:10.269176 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 11:56:10.273136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 11:56:10.275899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 11:56:10.282332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 11:56:10.285840 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 11:56:10.289126 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 11:56:10.292599 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 11:56:10.299272 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 11:56:10.302301 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 11:56:10.305768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 11:56:10.312463 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 11:56:10.315666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 11:56:10.322071 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 11:56:10.325829 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 11:56:10.328767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 11:56:10.335440 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 11:56:10.338633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 11:56:10.345401 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 11:56:10.348767 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 11:56:10.352280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 11:56:10.358774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 11:56:10.362084 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 11:56:10.368883 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 11:56:10.372360 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 11:56:10.375251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 11:56:10.381912 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 11:56:10.385267 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 11:56:10.391526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 11:56:10.395049 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 11:56:10.401503 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 11:56:10.404861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 11:56:10.412004 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 11:56:10.414773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 11:56:10.417974 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 11:56:10.424389 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 11:56:10.427893 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 11:56:10.434645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 11:56:10.437766 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 11:56:10.441172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 11:56:10.447776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 11:56:10.451024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 11:56:10.457609 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 11:56:10.461017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 11:56:10.464504 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 11:56:10.471022 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 11:56:10.474562 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 11:56:10.481086 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 11:56:10.485001 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 11:56:10.487201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 11:56:10.494757 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 11:56:10.497417 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 11:56:10.504253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 11:56:10.507792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 11:56:10.514205 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 11:56:10.517890 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 11:56:10.521256 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 11:56:10.527500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 11:56:10.530738 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 11:56:10.534509 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 11:56:10.540784 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 11:56:10.544142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 11:56:10.550751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 11:56:10.554046 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 11:56:10.560540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 11:56:10.564105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 11:56:10.567130 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 11:56:10.574276 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 11:56:10.577870 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 11:56:10.584422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 11:56:10.587545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 11:56:10.591247 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 11:56:10.597666 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 11:56:10.600996 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 11:56:10.604626 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 11:56:10.611281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 11:56:10.614331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 11:56:10.620968 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 11:56:10.624640 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 11:56:10.630978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 11:56:10.634117 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 11:56:10.637474 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 11:56:10.643947 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 11:56:10.647837 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 11:56:10.654542 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 11:56:10.657104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 11:56:10.663926 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 11:56:10.667473 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 11:56:10.670484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 11:56:10.677370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 11:56:10.680918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 11:56:10.687270 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 11:56:10.690715 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 11:56:10.697471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 11:56:10.700886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 11:56:10.704272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 11:56:10.711223 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 11:56:10.713940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 11:56:10.721098 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 11:56:10.724150 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 11:56:10.730532 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 11:56:10.733937 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 11:56:10.737440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 11:56:10.743660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 11:56:10.747057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 11:56:10.753648 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 11:56:10.756973 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 11:56:10.763984 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 11:56:10.766872 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 11:56:10.774076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 11:56:10.776735 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 11:56:10.780182 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 11:56:10.787064 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 11:56:10.790524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 11:56:10.797043 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 11:56:10.800306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 11:56:10.807028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 11:56:10.810533 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 11:56:10.813874 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 11:56:10.820510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 11:56:10.823395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 11:56:10.830205 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 11:56:10.833315 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 11:56:10.840078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 11:56:10.843588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 11:56:10.846503 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 11:56:10.853029 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 11:56:10.856820 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 11:56:10.863202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 11:56:10.866684 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 11:56:10.869917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 11:56:10.876482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 11:56:10.880032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 11:56:10.886930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 11:56:10.889601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 11:56:10.896944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 11:56:10.900214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 11:56:10.906243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 11:56:10.909921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 11:56:10.916550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 11:56:10.919756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 11:56:10.926426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 11:56:10.929570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 11:56:10.936538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 11:56:10.939606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 11:56:10.946294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 11:56:10.949253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 11:56:10.956205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 11:56:10.959199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 11:56:10.965999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 11:56:10.969141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 11:56:10.976093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 11:56:10.980330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 11:56:10.982975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 11:56:10.989315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 11:56:10.996247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 11:56:10.999431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 11:56:11.006419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 11:56:11.009911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 11:56:11.016358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 11:56:11.019275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 11:56:11.026168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 11:56:11.029573 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 11:56:11.030159 INFO: [APUAPC] vio 0
9908 11:56:11.036930 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 11:56:11.039994 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 11:56:11.042940 INFO: [APUAPC] D0_APC_0: 0x400510
9911 11:56:11.046686 INFO: [APUAPC] D0_APC_1: 0x0
9912 11:56:11.050137 INFO: [APUAPC] D0_APC_2: 0x1540
9913 11:56:11.053472 INFO: [APUAPC] D0_APC_3: 0x0
9914 11:56:11.056820 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 11:56:11.059999 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 11:56:11.063156 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 11:56:11.066214 INFO: [APUAPC] D1_APC_3: 0x0
9918 11:56:11.069761 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 11:56:11.073283 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 11:56:11.076307 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 11:56:11.079727 INFO: [APUAPC] D2_APC_3: 0x0
9922 11:56:11.083691 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 11:56:11.086197 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 11:56:11.089743 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 11:56:11.093100 INFO: [APUAPC] D3_APC_3: 0x0
9926 11:56:11.096514 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 11:56:11.099986 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 11:56:11.102945 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 11:56:11.103422 INFO: [APUAPC] D4_APC_3: 0x0
9930 11:56:11.106552 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 11:56:11.113195 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 11:56:11.116669 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 11:56:11.117248 INFO: [APUAPC] D5_APC_3: 0x0
9934 11:56:11.119448 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 11:56:11.123319 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 11:56:11.126311 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 11:56:11.129495 INFO: [APUAPC] D6_APC_3: 0x0
9938 11:56:11.132950 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 11:56:11.136400 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 11:56:11.139604 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 11:56:11.142745 INFO: [APUAPC] D7_APC_3: 0x0
9942 11:56:11.146235 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 11:56:11.149426 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 11:56:11.153244 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 11:56:11.156519 INFO: [APUAPC] D8_APC_3: 0x0
9946 11:56:11.159534 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 11:56:11.162490 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 11:56:11.166104 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 11:56:11.169285 INFO: [APUAPC] D9_APC_3: 0x0
9950 11:56:11.172660 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 11:56:11.175864 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 11:56:11.179186 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 11:56:11.182450 INFO: [APUAPC] D10_APC_3: 0x0
9954 11:56:11.185650 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 11:56:11.189242 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 11:56:11.192841 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 11:56:11.195719 INFO: [APUAPC] D11_APC_3: 0x0
9958 11:56:11.199451 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 11:56:11.202532 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 11:56:11.205550 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 11:56:11.209030 INFO: [APUAPC] D12_APC_3: 0x0
9962 11:56:11.212587 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 11:56:11.216211 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 11:56:11.219290 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 11:56:11.222965 INFO: [APUAPC] D13_APC_3: 0x0
9966 11:56:11.226648 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 11:56:11.229786 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 11:56:11.233081 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 11:56:11.235698 INFO: [APUAPC] D14_APC_3: 0x0
9970 11:56:11.239264 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 11:56:11.242800 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 11:56:11.246059 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 11:56:11.249792 INFO: [APUAPC] D15_APC_3: 0x0
9974 11:56:11.252802 INFO: [APUAPC] APC_CON: 0x4
9975 11:56:11.256095 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 11:56:11.258933 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 11:56:11.263150 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 11:56:11.265926 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 11:56:11.266569 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 11:56:11.269390 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 11:56:11.272506 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 11:56:11.275790 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 11:56:11.279691 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 11:56:11.282733 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 11:56:11.285555 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 11:56:11.289598 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 11:56:11.292940 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 11:56:11.295779 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 11:56:11.296262 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 11:56:11.298826 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 11:56:11.302298 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 11:56:11.305718 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 11:56:11.309354 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 11:56:11.312148 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 11:56:11.315985 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 11:56:11.319200 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 11:56:11.322908 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 11:56:11.325681 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 11:56:11.329011 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 11:56:11.332522 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 11:56:11.335526 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 11:56:11.338832 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 11:56:11.339308 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 11:56:11.342235 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 11:56:11.345989 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 11:56:11.348791 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 11:56:11.352783 INFO: [NOCDAPC] APC_CON: 0x4
10008 11:56:11.355220 INFO: [APUAPC] set_apusys_apc done
10009 11:56:11.358975 INFO: [DEVAPC] devapc_init done
10010 11:56:11.362034 INFO: GICv3 without legacy support detected.
10011 11:56:11.368940 INFO: ARM GICv3 driver initialized in EL3
10012 11:56:11.372797 INFO: Maximum SPI INTID supported: 639
10013 11:56:11.375549 INFO: BL31: Initializing runtime services
10014 11:56:11.382143 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 11:56:11.382772 INFO: SPM: enable CPC mode
10016 11:56:11.388539 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 11:56:11.392138 INFO: BL31: Preparing for EL3 exit to normal world
10018 11:56:11.398522 INFO: Entry point address = 0x80000000
10019 11:56:11.399101 INFO: SPSR = 0x8
10020 11:56:11.404692
10021 11:56:11.405277
10022 11:56:11.405862
10023 11:56:11.408076 Starting depthcharge on Spherion...
10024 11:56:11.408652
10025 11:56:11.409030 Wipe memory regions:
10026 11:56:11.409383
10027 11:56:11.411806 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10028 11:56:11.412374 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10029 11:56:11.412826 Setting prompt string to ['asurada:']
10030 11:56:11.413259 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10031 11:56:11.413990 [0x00000040000000, 0x00000054600000)
10032 11:56:11.533622
10033 11:56:11.534197 [0x00000054660000, 0x00000080000000)
10034 11:56:11.794285
10035 11:56:11.794903 [0x000000821a7280, 0x000000ffe64000)
10036 11:56:12.539365
10037 11:56:12.539946 [0x00000100000000, 0x00000240000000)
10038 11:56:14.428362
10039 11:56:14.431751 Initializing XHCI USB controller at 0x11200000.
10040 11:56:15.470535
10041 11:56:15.474016 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 11:56:15.474649
10043 11:56:15.475043
10044 11:56:15.475398
10045 11:56:15.476361 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 11:56:15.578052 asurada: tftpboot 192.168.201.1 12066556/tftp-deploy-ht9p51d_/kernel/image.itb 12066556/tftp-deploy-ht9p51d_/kernel/cmdline
10048 11:56:15.578786 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 11:56:15.579334 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 11:56:15.584315 tftpboot 192.168.201.1 12066556/tftp-deploy-ht9p51d_/kernel/image.itp-deploy-ht9p51d_/kernel/cmdline
10051 11:56:15.584972
10052 11:56:15.585531 Waiting for link
10053 11:56:15.744381
10054 11:56:15.744962 R8152: Initializing
10055 11:56:15.745341
10056 11:56:15.747728 Version 9 (ocp_data = 6010)
10057 11:56:15.748310
10058 11:56:15.750764 R8152: Done initializing
10059 11:56:15.751348
10060 11:56:15.751727 Adding net device
10061 11:56:17.619010
10062 11:56:17.619591 done.
10063 11:56:17.619972
10064 11:56:17.620324 MAC: 00:e0:4c:72:2d:d6
10065 11:56:17.620664
10066 11:56:17.621629 Sending DHCP discover... done.
10067 11:56:17.622103
10068 11:56:27.633216 Waiting for reply... R8152: Bulk read error 0xffffffbf
10069 11:56:27.633800
10070 11:56:27.636331 Receive failed.
10071 11:56:27.636790
10072 11:56:27.637152 done.
10073 11:56:27.637489
10074 11:56:27.639917 Sending DHCP request... done.
10075 11:56:27.640479
10076 11:56:27.646930 Waiting for reply... done.
10077 11:56:27.647476
10078 11:56:27.647836 My ip is 192.168.201.21
10079 11:56:27.648172
10080 11:56:27.650130 The DHCP server ip is 192.168.201.1
10081 11:56:27.650642
10082 11:56:27.657035 TFTP server IP predefined by user: 192.168.201.1
10083 11:56:27.657605
10084 11:56:27.663496 Bootfile predefined by user: 12066556/tftp-deploy-ht9p51d_/kernel/image.itb
10085 11:56:27.664060
10086 11:56:27.664428 Sending tftp read request... done.
10087 11:56:27.666846
10088 11:56:27.671372 Waiting for the transfer...
10089 11:56:27.671912
10090 11:56:27.969146 00000000 ################################################################
10091 11:56:27.969294
10092 11:56:28.217874 00080000 ################################################################
10093 11:56:28.218008
10094 11:56:28.466831 00100000 ################################################################
10095 11:56:28.466969
10096 11:56:28.716260 00180000 ################################################################
10097 11:56:28.716388
10098 11:56:28.966308 00200000 ################################################################
10099 11:56:28.966496
10100 11:56:29.215699 00280000 ################################################################
10101 11:56:29.215834
10102 11:56:29.464666 00300000 ################################################################
10103 11:56:29.464803
10104 11:56:29.714123 00380000 ################################################################
10105 11:56:29.714257
10106 11:56:29.963233 00400000 ################################################################
10107 11:56:29.963369
10108 11:56:30.212395 00480000 ################################################################
10109 11:56:30.212529
10110 11:56:30.461835 00500000 ################################################################
10111 11:56:30.461974
10112 11:56:30.729708 00580000 ################################################################
10113 11:56:30.729843
10114 11:56:31.059184 00600000 ################################################################
10115 11:56:31.059325
10116 11:56:31.341764 00680000 ################################################################
10117 11:56:31.341951
10118 11:56:31.601652 00700000 ################################################################
10119 11:56:31.601807
10120 11:56:31.851311 00780000 ################################################################
10121 11:56:31.851468
10122 11:56:32.115942 00800000 ################################################################
10123 11:56:32.116109
10124 11:56:32.385963 00880000 ################################################################
10125 11:56:32.386122
10126 11:56:32.635602 00900000 ################################################################
10127 11:56:32.635740
10128 11:56:32.917077 00980000 ################################################################
10129 11:56:32.917224
10130 11:56:33.213298 00a00000 ################################################################
10131 11:56:33.213441
10132 11:56:33.498681 00a80000 ################################################################
10133 11:56:33.498822
10134 11:56:33.781572 00b00000 ################################################################
10135 11:56:33.781707
10136 11:56:34.064635 00b80000 ################################################################
10137 11:56:34.064806
10138 11:56:34.322203 00c00000 ################################################################
10139 11:56:34.322340
10140 11:56:34.571074 00c80000 ################################################################
10141 11:56:34.571206
10142 11:56:34.819800 00d00000 ################################################################
10143 11:56:34.819930
10144 11:56:35.068866 00d80000 ################################################################
10145 11:56:35.069001
10146 11:56:35.321327 00e00000 ################################################################
10147 11:56:35.321470
10148 11:56:35.602358 00e80000 ################################################################
10149 11:56:35.602532
10150 11:56:35.902206 00f00000 ################################################################
10151 11:56:35.902387
10152 11:56:36.189538 00f80000 ################################################################
10153 11:56:36.189673
10154 11:56:36.471781 01000000 ################################################################
10155 11:56:36.471918
10156 11:56:36.754376 01080000 ################################################################
10157 11:56:36.754545
10158 11:56:37.036617 01100000 ################################################################
10159 11:56:37.036758
10160 11:56:37.303269 01180000 ################################################################
10161 11:56:37.303422
10162 11:56:37.588211 01200000 ################################################################
10163 11:56:37.588361
10164 11:56:37.852555 01280000 ################################################################
10165 11:56:37.852697
10166 11:56:38.136763 01300000 ################################################################
10167 11:56:38.136943
10168 11:56:38.417386 01380000 ################################################################
10169 11:56:38.417537
10170 11:56:38.707625 01400000 ################################################################
10171 11:56:38.707775
10172 11:56:38.981522 01480000 ################################################################
10173 11:56:38.981674
10174 11:56:39.236486 01500000 ################################################################
10175 11:56:39.236667
10176 11:56:39.517584 01580000 ################################################################
10177 11:56:39.517732
10178 11:56:39.798287 01600000 ################################################################
10179 11:56:39.798496
10180 11:56:40.053405 01680000 ################################################################
10181 11:56:40.053559
10182 11:56:40.307254 01700000 ################################################################
10183 11:56:40.307401
10184 11:56:40.561744 01780000 ################################################################
10185 11:56:40.561894
10186 11:56:40.817352 01800000 ################################################################
10187 11:56:40.817497
10188 11:56:41.072751 01880000 ################################################################
10189 11:56:41.072903
10190 11:56:41.328208 01900000 ################################################################
10191 11:56:41.328358
10192 11:56:41.582926 01980000 ################################################################
10193 11:56:41.583112
10194 11:56:41.838743 01a00000 ################################################################
10195 11:56:41.838896
10196 11:56:42.100051 01a80000 ################################################################
10197 11:56:42.100228
10198 11:56:42.373815 01b00000 ################################################################
10199 11:56:42.373994
10200 11:56:42.629440 01b80000 ################################################################
10201 11:56:42.629603
10202 11:56:42.885658 01c00000 ################################################################
10203 11:56:42.885810
10204 11:56:43.155882 01c80000 ################################################################
10205 11:56:43.156031
10206 11:56:43.416682 01d00000 ################################################################
10207 11:56:43.416833
10208 11:56:43.671719 01d80000 ################################################################
10209 11:56:43.671876
10210 11:56:43.919100 01e00000 ################################################################
10211 11:56:43.919274
10212 11:56:44.160529 01e80000 ################################################################
10213 11:56:44.160675
10214 11:56:44.421174 01f00000 ################################################################
10215 11:56:44.421351
10216 11:56:44.703101 01f80000 ################################################################
10217 11:56:44.703298
10218 11:56:44.985362 02000000 ################################################################
10219 11:56:44.985552
10220 11:56:45.266755 02080000 ################################################################
10221 11:56:45.266948
10222 11:56:45.547669 02100000 ################################################################
10223 11:56:45.547835
10224 11:56:45.831133 02180000 ################################################################
10225 11:56:45.831276
10226 11:56:46.129265 02200000 ################################################################
10227 11:56:46.129444
10228 11:56:46.423085 02280000 ################################################################
10229 11:56:46.423240
10230 11:56:46.710309 02300000 ################################################################
10231 11:56:46.710482
10232 11:56:47.000924 02380000 ################################################################
10233 11:56:47.001077
10234 11:56:47.282294 02400000 ################################################################
10235 11:56:47.282463
10236 11:56:47.562571 02480000 ################################################################
10237 11:56:47.562719
10238 11:56:47.844131 02500000 ################################################################
10239 11:56:47.844280
10240 11:56:48.128287 02580000 ################################################################
10241 11:56:48.128436
10242 11:56:48.409104 02600000 ################################################################
10243 11:56:48.409257
10244 11:56:48.660684 02680000 ################################################################
10245 11:56:48.660874
10246 11:56:48.944361 02700000 ################################################################
10247 11:56:48.944516
10248 11:56:49.228919 02780000 ################################################################
10249 11:56:49.229099
10250 11:56:49.470930 02800000 ################################################################
10251 11:56:49.471076
10252 11:56:49.764775 02880000 ################################################################
10253 11:56:49.764948
10254 11:56:50.024804 02900000 ################################################################
10255 11:56:50.024981
10256 11:56:50.270482 02980000 ################################################################
10257 11:56:50.270660
10258 11:56:50.516190 02a00000 ################################################################
10259 11:56:50.516340
10260 11:56:50.768219 02a80000 ################################################################
10261 11:56:50.768365
10262 11:56:51.015914 02b00000 ################################################################
10263 11:56:51.016065
10264 11:56:51.273985 02b80000 ################################################################
10265 11:56:51.274166
10266 11:56:51.529527 02c00000 ################################################################
10267 11:56:51.529672
10268 11:56:51.775318 02c80000 ################################################################
10269 11:56:51.775470
10270 11:56:52.026633 02d00000 ################################################################
10271 11:56:52.026815
10272 11:56:52.305031 02d80000 ################################################################
10273 11:56:52.305169
10274 11:56:52.590252 02e00000 ################################################################
10275 11:56:52.590440
10276 11:56:52.854417 02e80000 ################################################################
10277 11:56:52.854563
10278 11:56:53.103475 02f00000 ################################################################
10279 11:56:53.103624
10280 11:56:53.353596 02f80000 ################################################################
10281 11:56:53.353778
10282 11:56:53.625278 03000000 ################################################################
10283 11:56:53.625428
10284 11:56:53.875688 03080000 ################################################################
10285 11:56:53.875838
10286 11:56:54.137072 03100000 ################################################################
10287 11:56:54.137241
10288 11:56:54.414700 03180000 ################################################################
10289 11:56:54.414849
10290 11:56:54.688601 03200000 ################################################################
10291 11:56:54.688752
10292 11:56:54.967466 03280000 ################################################################
10293 11:56:54.967613
10294 11:56:55.247130 03300000 ################################################################
10295 11:56:55.247273
10296 11:56:55.528079 03380000 ################################################################
10297 11:56:55.528220
10298 11:56:55.788706 03400000 ################################################################
10299 11:56:55.788852
10300 11:56:56.038146 03480000 ################################################################
10301 11:56:56.038289
10302 11:56:56.287897 03500000 ################################################################
10303 11:56:56.288038
10304 11:56:56.537844 03580000 ################################################################
10305 11:56:56.537986
10306 11:56:56.786676 03600000 ################################################################
10307 11:56:56.786818
10308 11:56:57.036215 03680000 ################################################################
10309 11:56:57.036359
10310 11:56:57.290001 03700000 ################################################################
10311 11:56:57.290166
10312 11:56:57.496887 03780000 ###################################################### done.
10313 11:56:57.497029
10314 11:56:57.500000 The bootfile was 58634610 bytes long.
10315 11:56:57.500084
10316 11:56:57.503441 Sending tftp read request... done.
10317 11:56:57.503525
10318 11:56:57.506728 Waiting for the transfer...
10319 11:56:57.506811
10320 11:56:57.506877 00000000 # done.
10321 11:56:57.510090
10322 11:56:57.516733 Command line loaded dynamically from TFTP file: 12066556/tftp-deploy-ht9p51d_/kernel/cmdline
10323 11:56:57.516818
10324 11:56:57.530305 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10325 11:56:57.530413
10326 11:56:57.530493 Loading FIT.
10327 11:56:57.530554
10328 11:56:57.533681 Image ramdisk-1 has 47538113 bytes.
10329 11:56:57.533764
10330 11:56:57.536347 Image fdt-1 has 47278 bytes.
10331 11:56:57.536430
10332 11:56:57.539719 Image kernel-1 has 11047184 bytes.
10333 11:56:57.539801
10334 11:56:57.549536 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10335 11:56:57.549620
10336 11:56:57.565995 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10337 11:56:57.566082
10338 11:56:57.572742 Choosing best match conf-1 for compat google,spherion-rev2.
10339 11:56:57.572825
10340 11:56:57.580558 Connected to device vid:did:rid of 1ae0:0028:00
10341 11:56:57.588753
10342 11:56:57.591815 tpm_get_response: command 0x17b, return code 0x0
10343 11:56:57.591897
10344 11:56:57.598620 ec_init: CrosEC protocol v3 supported (256, 248)
10345 11:56:57.598703
10346 11:56:57.602181 tpm_cleanup: add release locality here.
10347 11:56:57.602262
10348 11:56:57.605433 Shutting down all USB controllers.
10349 11:56:57.605515
10350 11:56:57.608604 Removing current net device
10351 11:56:57.608684
10352 11:56:57.615558 Exiting depthcharge with code 4 at timestamp: 75511215
10353 11:56:57.615639
10354 11:56:57.618692 LZMA decompressing kernel-1 to 0x821a6718
10355 11:56:57.618773
10356 11:56:57.622101 LZMA decompressing kernel-1 to 0x40000000
10357 11:56:59.010091
10358 11:56:59.010243 jumping to kernel
10359 11:56:59.010755 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10360 11:56:59.010854 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10361 11:56:59.010927 Setting prompt string to ['Linux version [0-9]']
10362 11:56:59.010993 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10363 11:56:59.011058 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10364 11:56:59.091817
10365 11:56:59.095290 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10366 11:56:59.098800 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10367 11:56:59.098890 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10368 11:56:59.098960 Setting prompt string to []
10369 11:56:59.099036 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10370 11:56:59.099112 Using line separator: #'\n'#
10371 11:56:59.099171 No login prompt set.
10372 11:56:59.099267 Parsing kernel messages
10373 11:56:59.099321 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10374 11:56:59.099421 [login-action] Waiting for messages, (timeout 00:03:38)
10375 11:56:59.118295 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10376 11:56:59.121838 [ 0.000000] random: crng init done
10377 11:56:59.128491 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10378 11:56:59.128573 [ 0.000000] efi: UEFI not found.
10379 11:56:59.137976 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10380 11:56:59.144931 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10381 11:56:59.154848 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10382 11:56:59.164855 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10383 11:56:59.171217 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10384 11:56:59.178319 [ 0.000000] printk: bootconsole [mtk8250] enabled
10385 11:56:59.184844 [ 0.000000] NUMA: No NUMA configuration found
10386 11:56:59.191342 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10387 11:56:59.194594 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10388 11:56:59.197939 [ 0.000000] Zone ranges:
10389 11:56:59.204704 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10390 11:56:59.207666 [ 0.000000] DMA32 empty
10391 11:56:59.214513 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10392 11:56:59.217707 [ 0.000000] Movable zone start for each node
10393 11:56:59.221046 [ 0.000000] Early memory node ranges
10394 11:56:59.227717 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10395 11:56:59.234138 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10396 11:56:59.240867 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10397 11:56:59.247634 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10398 11:56:59.250915 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10399 11:56:59.260824 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10400 11:56:59.316124 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10401 11:56:59.322579 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10402 11:56:59.329361 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10403 11:56:59.332677 [ 0.000000] psci: probing for conduit method from DT.
10404 11:56:59.339400 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10405 11:56:59.342746 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10406 11:56:59.349077 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10407 11:56:59.352528 [ 0.000000] psci: SMC Calling Convention v1.2
10408 11:56:59.359192 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10409 11:56:59.362353 [ 0.000000] Detected VIPT I-cache on CPU0
10410 11:56:59.369679 [ 0.000000] CPU features: detected: GIC system register CPU interface
10411 11:56:59.375814 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10412 11:56:59.382726 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10413 11:56:59.389134 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10414 11:56:59.395561 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10415 11:56:59.402726 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10416 11:56:59.409011 [ 0.000000] alternatives: applying boot alternatives
10417 11:56:59.412324 [ 0.000000] Fallback order for Node 0: 0
10418 11:56:59.419025 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10419 11:56:59.422167 [ 0.000000] Policy zone: Normal
10420 11:56:59.438766 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10421 11:56:59.448824 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10422 11:56:59.460307 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10423 11:56:59.470328 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10424 11:56:59.476749 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10425 11:56:59.479977 <6>[ 0.000000] software IO TLB: area num 8.
10426 11:56:59.536725 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10427 11:56:59.685719 <6>[ 0.000000] Memory: 7923196K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 429572K reserved, 32768K cma-reserved)
10428 11:56:59.692175 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10429 11:56:59.699157 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10430 11:56:59.702160 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10431 11:56:59.709297 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10432 11:56:59.715320 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10433 11:56:59.718728 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10434 11:56:59.728754 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10435 11:56:59.735841 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10436 11:56:59.741990 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10437 11:56:59.748743 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10438 11:56:59.751855 <6>[ 0.000000] GICv3: 608 SPIs implemented
10439 11:56:59.755490 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10440 11:56:59.761916 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10441 11:56:59.765205 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10442 11:56:59.771656 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10443 11:56:59.785093 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10444 11:56:59.795124 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10445 11:56:59.804704 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10446 11:56:59.812283 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10447 11:56:59.825685 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10448 11:56:59.832256 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10449 11:56:59.839025 <6>[ 0.009180] Console: colour dummy device 80x25
10450 11:56:59.848633 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10451 11:56:59.855456 <6>[ 0.024377] pid_max: default: 32768 minimum: 301
10452 11:56:59.858927 <6>[ 0.029250] LSM: Security Framework initializing
10453 11:56:59.865410 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 11:56:59.875239 <6>[ 0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 11:56:59.882088 <6>[ 0.051477] cblist_init_generic: Setting adjustable number of callback queues.
10456 11:56:59.888512 <6>[ 0.058965] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 11:56:59.898608 <6>[ 0.065343] cblist_init_generic: Setting adjustable number of callback queues.
10458 11:56:59.901971 <6>[ 0.072770] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 11:56:59.908658 <6>[ 0.079172] rcu: Hierarchical SRCU implementation.
10460 11:56:59.915328 <6>[ 0.084219] rcu: Max phase no-delay instances is 1000.
10461 11:56:59.921937 <6>[ 0.091242] EFI services will not be available.
10462 11:56:59.925347 <6>[ 0.096222] smp: Bringing up secondary CPUs ...
10463 11:56:59.933371 <6>[ 0.101298] Detected VIPT I-cache on CPU1
10464 11:56:59.939587 <6>[ 0.101367] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10465 11:56:59.946280 <6>[ 0.101399] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10466 11:56:59.949656 <6>[ 0.101734] Detected VIPT I-cache on CPU2
10467 11:56:59.956859 <6>[ 0.101783] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10468 11:56:59.962860 <6>[ 0.101798] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10469 11:56:59.969885 <6>[ 0.102058] Detected VIPT I-cache on CPU3
10470 11:56:59.976385 <6>[ 0.102104] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10471 11:56:59.983168 <6>[ 0.102117] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10472 11:56:59.986329 <6>[ 0.102415] CPU features: detected: Spectre-v4
10473 11:56:59.992992 <6>[ 0.102421] CPU features: detected: Spectre-BHB
10474 11:56:59.996166 <6>[ 0.102425] Detected PIPT I-cache on CPU4
10475 11:57:00.003444 <6>[ 0.102477] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10476 11:57:00.009722 <6>[ 0.102492] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10477 11:57:00.013011 <6>[ 0.102767] Detected PIPT I-cache on CPU5
10478 11:57:00.022984 <6>[ 0.102829] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10479 11:57:00.029704 <6>[ 0.102846] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10480 11:57:00.032949 <6>[ 0.103128] Detected PIPT I-cache on CPU6
10481 11:57:00.039624 <6>[ 0.103195] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10482 11:57:00.046278 <6>[ 0.103211] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10483 11:57:00.052951 <6>[ 0.103508] Detected PIPT I-cache on CPU7
10484 11:57:00.059284 <6>[ 0.103574] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10485 11:57:00.065931 <6>[ 0.103590] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10486 11:57:00.070005 <6>[ 0.103637] smp: Brought up 1 node, 8 CPUs
10487 11:57:00.075714 <6>[ 0.244945] SMP: Total of 8 processors activated.
10488 11:57:00.078943 <6>[ 0.249866] CPU features: detected: 32-bit EL0 Support
10489 11:57:00.089534 <6>[ 0.255228] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10490 11:57:00.095583 <6>[ 0.264029] CPU features: detected: Common not Private translations
10491 11:57:00.098792 <6>[ 0.270545] CPU features: detected: CRC32 instructions
10492 11:57:00.105733 <6>[ 0.275929] CPU features: detected: RCpc load-acquire (LDAPR)
10493 11:57:00.112004 <6>[ 0.281888] CPU features: detected: LSE atomic instructions
10494 11:57:00.119262 <6>[ 0.287670] CPU features: detected: Privileged Access Never
10495 11:57:00.122620 <6>[ 0.293486] CPU features: detected: RAS Extension Support
10496 11:57:00.131914 <6>[ 0.299129] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10497 11:57:00.135274 <6>[ 0.306391] CPU: All CPU(s) started at EL2
10498 11:57:00.141599 <6>[ 0.310735] alternatives: applying system-wide alternatives
10499 11:57:00.150731 <6>[ 0.321436] devtmpfs: initialized
10500 11:57:00.163139 <6>[ 0.330374] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10501 11:57:00.173430 <6>[ 0.340336] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10502 11:57:00.180318 <6>[ 0.348596] pinctrl core: initialized pinctrl subsystem
10503 11:57:00.183512 <6>[ 0.355373] DMI not present or invalid.
10504 11:57:00.189677 <6>[ 0.359785] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10505 11:57:00.199751 <6>[ 0.366674] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10506 11:57:00.206603 <6>[ 0.374260] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10507 11:57:00.216623 <6>[ 0.382486] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10508 11:57:00.219665 <6>[ 0.390731] audit: initializing netlink subsys (disabled)
10509 11:57:00.229621 <5>[ 0.396426] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10510 11:57:00.236381 <6>[ 0.397166] thermal_sys: Registered thermal governor 'step_wise'
10511 11:57:00.243141 <6>[ 0.404393] thermal_sys: Registered thermal governor 'power_allocator'
10512 11:57:00.246144 <6>[ 0.410649] cpuidle: using governor menu
10513 11:57:00.252663 <6>[ 0.421612] NET: Registered PF_QIPCRTR protocol family
10514 11:57:00.259330 <6>[ 0.427096] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10515 11:57:00.266057 <6>[ 0.434202] ASID allocator initialised with 32768 entries
10516 11:57:00.269177 <6>[ 0.440813] Serial: AMBA PL011 UART driver
10517 11:57:00.279450 <4>[ 0.449980] Trying to register duplicate clock ID: 134
10518 11:57:00.336515 <6>[ 0.510068] KASLR enabled
10519 11:57:00.351003 <6>[ 0.517809] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10520 11:57:00.357111 <6>[ 0.524820] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10521 11:57:00.363809 <6>[ 0.531309] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10522 11:57:00.370531 <6>[ 0.538313] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10523 11:57:00.377204 <6>[ 0.544802] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10524 11:57:00.383771 <6>[ 0.551805] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10525 11:57:00.391065 <6>[ 0.558294] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10526 11:57:00.397330 <6>[ 0.565300] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10527 11:57:00.400338 <6>[ 0.572778] ACPI: Interpreter disabled.
10528 11:57:00.408723 <6>[ 0.579261] iommu: Default domain type: Translated
10529 11:57:00.415189 <6>[ 0.584376] iommu: DMA domain TLB invalidation policy: strict mode
10530 11:57:00.418771 <5>[ 0.591031] SCSI subsystem initialized
10531 11:57:00.425736 <6>[ 0.595194] usbcore: registered new interface driver usbfs
10532 11:57:00.431767 <6>[ 0.600924] usbcore: registered new interface driver hub
10533 11:57:00.435154 <6>[ 0.606475] usbcore: registered new device driver usb
10534 11:57:00.442263 <6>[ 0.612617] pps_core: LinuxPPS API ver. 1 registered
10535 11:57:00.451956 <6>[ 0.617810] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10536 11:57:00.455393 <6>[ 0.627155] PTP clock support registered
10537 11:57:00.458617 <6>[ 0.631400] EDAC MC: Ver: 3.0.0
10538 11:57:00.465940 <6>[ 0.636610] FPGA manager framework
10539 11:57:00.469318 <6>[ 0.640290] Advanced Linux Sound Architecture Driver Initialized.
10540 11:57:00.473127 <6>[ 0.647067] vgaarb: loaded
10541 11:57:00.479850 <6>[ 0.650238] clocksource: Switched to clocksource arch_sys_counter
10542 11:57:00.486730 <5>[ 0.656666] VFS: Disk quotas dquot_6.6.0
10543 11:57:00.492891 <6>[ 0.660852] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10544 11:57:00.496429 <6>[ 0.668042] pnp: PnP ACPI: disabled
10545 11:57:00.504467 <6>[ 0.674675] NET: Registered PF_INET protocol family
10546 11:57:00.514142 <6>[ 0.680262] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10547 11:57:00.525372 <6>[ 0.692560] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10548 11:57:00.535054 <6>[ 0.701372] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10549 11:57:00.541794 <6>[ 0.709342] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10550 11:57:00.551439 <6>[ 0.718043] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10551 11:57:00.558065 <6>[ 0.727782] TCP: Hash tables configured (established 65536 bind 65536)
10552 11:57:00.564936 <6>[ 0.734643] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 11:57:00.574780 <6>[ 0.741843] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 11:57:00.581313 <6>[ 0.749541] NET: Registered PF_UNIX/PF_LOCAL protocol family
10555 11:57:00.585382 <6>[ 0.755710] RPC: Registered named UNIX socket transport module.
10556 11:57:00.591800 <6>[ 0.761866] RPC: Registered udp transport module.
10557 11:57:00.594606 <6>[ 0.766799] RPC: Registered tcp transport module.
10558 11:57:00.601246 <6>[ 0.771731] RPC: Registered tcp NFSv4.1 backchannel transport module.
10559 11:57:00.607762 <6>[ 0.778397] PCI: CLS 0 bytes, default 64
10560 11:57:00.611571 <6>[ 0.782781] Unpacking initramfs...
10561 11:57:00.627689 <6>[ 0.794860] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10562 11:57:00.637581 <6>[ 0.803521] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10563 11:57:00.640751 <6>[ 0.812380] kvm [1]: IPA Size Limit: 40 bits
10564 11:57:00.647624 <6>[ 0.816908] kvm [1]: GICv3: no GICV resource entry
10565 11:57:00.650723 <6>[ 0.821931] kvm [1]: disabling GICv2 emulation
10566 11:57:00.657261 <6>[ 0.826618] kvm [1]: GIC system register CPU interface enabled
10567 11:57:00.664206 <6>[ 0.834276] kvm [1]: vgic interrupt IRQ18
10568 11:57:00.667461 <6>[ 0.838662] kvm [1]: VHE mode initialized successfully
10569 11:57:00.674924 <5>[ 0.845148] Initialise system trusted keyrings
10570 11:57:00.681177 <6>[ 0.849943] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10571 11:57:00.689457 <6>[ 0.860018] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10572 11:57:00.695926 <5>[ 0.866477] NFS: Registering the id_resolver key type
10573 11:57:00.699504 <5>[ 0.871788] Key type id_resolver registered
10574 11:57:00.706051 <5>[ 0.876203] Key type id_legacy registered
10575 11:57:00.712584 <6>[ 0.880479] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10576 11:57:00.719257 <6>[ 0.887401] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10577 11:57:00.725665 <6>[ 0.895159] 9p: Installing v9fs 9p2000 file system support
10578 11:57:00.762664 <5>[ 0.933126] Key type asymmetric registered
10579 11:57:00.766088 <5>[ 0.937460] Asymmetric key parser 'x509' registered
10580 11:57:00.776182 <6>[ 0.942604] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10581 11:57:00.779160 <6>[ 0.950250] io scheduler mq-deadline registered
10582 11:57:00.782301 <6>[ 0.955031] io scheduler kyber registered
10583 11:57:00.801976 <6>[ 0.972578] EINJ: ACPI disabled.
10584 11:57:00.834515 <4>[ 0.998603] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 11:57:00.844752 <4>[ 1.009243] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 11:57:00.859449 <6>[ 1.030308] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10587 11:57:00.867499 <6>[ 1.038346] printk: console [ttyS0] disabled
10588 11:57:00.895766 <6>[ 1.062990] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10589 11:57:00.902366 <6>[ 1.072467] printk: console [ttyS0] enabled
10590 11:57:00.905701 <6>[ 1.072467] printk: console [ttyS0] enabled
10591 11:57:00.912316 <6>[ 1.081367] printk: bootconsole [mtk8250] disabled
10592 11:57:00.915414 <6>[ 1.081367] printk: bootconsole [mtk8250] disabled
10593 11:57:00.922076 <6>[ 1.092678] SuperH (H)SCI(F) driver initialized
10594 11:57:00.925509 <6>[ 1.097987] msm_serial: driver initialized
10595 11:57:00.939968 <6>[ 1.107103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10596 11:57:00.949959 <6>[ 1.115651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10597 11:57:00.956670 <6>[ 1.124193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10598 11:57:00.966488 <6>[ 1.132824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10599 11:57:00.976281 <6>[ 1.141531] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10600 11:57:00.982847 <6>[ 1.150250] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10601 11:57:00.992727 <6>[ 1.158790] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10602 11:57:00.999706 <6>[ 1.167591] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10603 11:57:01.009141 <6>[ 1.176135] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10604 11:57:01.021459 <6>[ 1.191993] loop: module loaded
10605 11:57:01.027950 <6>[ 1.198026] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10606 11:57:01.050789 <4>[ 1.221396] mtk-pmic-keys: Failed to locate of_node [id: -1]
10607 11:57:01.057581 <6>[ 1.228293] megasas: 07.719.03.00-rc1
10608 11:57:01.067966 <6>[ 1.237923] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10609 11:57:01.075099 <6>[ 1.245611] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10610 11:57:01.091975 <6>[ 1.262387] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10611 11:57:01.148028 <6>[ 1.312248] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10612 11:57:02.634101 <6>[ 2.804543] Freeing initrd memory: 46420K
10613 11:57:02.644211 <6>[ 2.815074] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10614 11:57:02.655189 <6>[ 2.826043] tun: Universal TUN/TAP device driver, 1.6
10615 11:57:02.658596 <6>[ 2.832138] thunder_xcv, ver 1.0
10616 11:57:02.661880 <6>[ 2.835644] thunder_bgx, ver 1.0
10617 11:57:02.665131 <6>[ 2.839137] nicpf, ver 1.0
10618 11:57:02.675883 <6>[ 2.843198] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10619 11:57:02.679547 <6>[ 2.850674] hns3: Copyright (c) 2017 Huawei Corporation.
10620 11:57:02.685638 <6>[ 2.856261] hclge is initializing
10621 11:57:02.688961 <6>[ 2.859840] e1000: Intel(R) PRO/1000 Network Driver
10622 11:57:02.696536 <6>[ 2.864969] e1000: Copyright (c) 1999-2006 Intel Corporation.
10623 11:57:02.699027 <6>[ 2.870982] e1000e: Intel(R) PRO/1000 Network Driver
10624 11:57:02.706198 <6>[ 2.876196] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10625 11:57:02.712008 <6>[ 2.882382] igb: Intel(R) Gigabit Ethernet Network Driver
10626 11:57:02.718839 <6>[ 2.888032] igb: Copyright (c) 2007-2014 Intel Corporation.
10627 11:57:02.725558 <6>[ 2.893872] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10628 11:57:02.731963 <6>[ 2.900390] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 11:57:02.735306 <6>[ 2.906857] sky2: driver version 1.30
10630 11:57:02.741868 <6>[ 2.911892] VFIO - User Level meta-driver version: 0.3
10631 11:57:02.749373 <6>[ 2.920212] usbcore: registered new interface driver usb-storage
10632 11:57:02.755787 <6>[ 2.926658] usbcore: registered new device driver onboard-usb-hub
10633 11:57:02.765051 <6>[ 2.935853] mt6397-rtc mt6359-rtc: registered as rtc0
10634 11:57:02.775001 <6>[ 2.941318] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:56:27 UTC (1700740587)
10635 11:57:02.778112 <6>[ 2.950919] i2c_dev: i2c /dev entries driver
10636 11:57:02.795173 <6>[ 2.962848] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10637 11:57:02.816259 <6>[ 2.986863] cpu cpu0: EM: created perf domain
10638 11:57:02.819202 <6>[ 2.991797] cpu cpu4: EM: created perf domain
10639 11:57:02.826453 <6>[ 2.997356] sdhci: Secure Digital Host Controller Interface driver
10640 11:57:02.833124 <6>[ 3.003789] sdhci: Copyright(c) Pierre Ossman
10641 11:57:02.839974 <6>[ 3.008750] Synopsys Designware Multimedia Card Interface Driver
10642 11:57:02.846718 <6>[ 3.015393] sdhci-pltfm: SDHCI platform and OF driver helper
10643 11:57:02.849560 <6>[ 3.015433] mmc0: CQHCI version 5.10
10644 11:57:02.856502 <6>[ 3.025550] ledtrig-cpu: registered to indicate activity on CPUs
10645 11:57:02.863120 <6>[ 3.032601] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10646 11:57:02.869642 <6>[ 3.039658] usbcore: registered new interface driver usbhid
10647 11:57:02.873201 <6>[ 3.045484] usbhid: USB HID core driver
10648 11:57:02.879722 <6>[ 3.049687] spi_master spi0: will run message pump with realtime priority
10649 11:57:02.923537 <6>[ 3.087936] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10650 11:57:02.943297 <6>[ 3.103919] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10651 11:57:02.946740 <6>[ 3.118270] mmc0: Command Queue Engine enabled
10652 11:57:02.953222 <6>[ 3.123020] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 11:57:02.959758 <6>[ 3.129790] cros-ec-spi spi0.0: Chrome EC device registered
10654 11:57:02.963533 <6>[ 3.130252] mmcblk0: mmc0:0001 DA4128 116 GiB
10655 11:57:02.973894 <6>[ 3.144316] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10656 11:57:02.981507 <6>[ 3.151648] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 11:57:02.987325 <6>[ 3.157532] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10658 11:57:02.994085 <6>[ 3.163428] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10659 11:57:03.008044 <6>[ 3.175762] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10660 11:57:03.015596 <6>[ 3.186377] NET: Registered PF_PACKET protocol family
10661 11:57:03.019016 <6>[ 3.191772] 9pnet: Installing 9P2000 support
10662 11:57:03.025589 <5>[ 3.196340] Key type dns_resolver registered
10663 11:57:03.028813 <6>[ 3.201307] registered taskstats version 1
10664 11:57:03.035340 <5>[ 3.205691] Loading compiled-in X.509 certificates
10665 11:57:03.066289 <4>[ 3.230597] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 11:57:03.076848 <4>[ 3.241360] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 11:57:03.082839 <3>[ 3.251899] debugfs: File 'uA_load' in directory '/' already present!
10668 11:57:03.089798 <3>[ 3.258599] debugfs: File 'min_uV' in directory '/' already present!
10669 11:57:03.096289 <3>[ 3.265205] debugfs: File 'max_uV' in directory '/' already present!
10670 11:57:03.102621 <3>[ 3.271813] debugfs: File 'constraint_flags' in directory '/' already present!
10671 11:57:03.114288 <3>[ 3.281636] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10672 11:57:03.123525 <6>[ 3.294398] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10673 11:57:03.130457 <6>[ 3.301218] xhci-mtk 11200000.usb: xHCI Host Controller
10674 11:57:03.137052 <6>[ 3.306721] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10675 11:57:03.147042 <6>[ 3.314593] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10676 11:57:03.153471 <6>[ 3.324013] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10677 11:57:03.160267 <6>[ 3.330104] xhci-mtk 11200000.usb: xHCI Host Controller
10678 11:57:03.166851 <6>[ 3.335581] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10679 11:57:03.173208 <6>[ 3.343229] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10680 11:57:03.179953 <6>[ 3.350897] hub 1-0:1.0: USB hub found
10681 11:57:03.183763 <6>[ 3.354908] hub 1-0:1.0: 1 port detected
10682 11:57:03.190100 <6>[ 3.359185] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10683 11:57:03.196841 <6>[ 3.367732] hub 2-0:1.0: USB hub found
10684 11:57:03.200144 <6>[ 3.371737] hub 2-0:1.0: 1 port detected
10685 11:57:03.208797 <6>[ 3.379731] mtk-msdc 11f70000.mmc: Got CD GPIO
10686 11:57:03.219108 <6>[ 3.386513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10687 11:57:03.225644 <6>[ 3.394536] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10688 11:57:03.235496 <4>[ 3.402439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10689 11:57:03.245875 <6>[ 3.411962] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10690 11:57:03.252255 <6>[ 3.420038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10691 11:57:03.258592 <6>[ 3.428182] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10692 11:57:03.268470 <6>[ 3.436121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10693 11:57:03.275238 <6>[ 3.443939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10694 11:57:03.284841 <6>[ 3.451756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10695 11:57:03.295036 <6>[ 3.462254] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10696 11:57:03.301688 <6>[ 3.470615] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10697 11:57:03.311635 <6>[ 3.478957] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10698 11:57:03.318103 <6>[ 3.487296] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10699 11:57:03.327999 <6>[ 3.495634] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10700 11:57:03.337940 <6>[ 3.503972] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10701 11:57:03.345085 <6>[ 3.512310] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10702 11:57:03.354373 <6>[ 3.520648] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10703 11:57:03.361521 <6>[ 3.528987] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10704 11:57:03.371192 <6>[ 3.537326] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10705 11:57:03.377665 <6>[ 3.545668] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10706 11:57:03.387382 <6>[ 3.554010] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10707 11:57:03.394612 <6>[ 3.562349] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10708 11:57:03.404405 <6>[ 3.570689] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10709 11:57:03.410689 <6>[ 3.579027] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10710 11:57:03.417320 <6>[ 3.587779] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10711 11:57:03.423966 <6>[ 3.594984] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10712 11:57:03.430934 <6>[ 3.601765] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10713 11:57:03.441180 <6>[ 3.608529] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10714 11:57:03.447549 <6>[ 3.615466] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10715 11:57:03.454230 <6>[ 3.622331] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10716 11:57:03.463950 <6>[ 3.631459] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10717 11:57:03.474049 <6>[ 3.640581] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10718 11:57:03.483829 <6>[ 3.649875] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10719 11:57:03.493840 <6>[ 3.659347] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10720 11:57:03.503648 <6>[ 3.668817] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10721 11:57:03.510574 <6>[ 3.677939] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10722 11:57:03.520575 <6>[ 3.687405] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10723 11:57:03.530144 <6>[ 3.696523] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10724 11:57:03.539943 <6>[ 3.705816] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10725 11:57:03.549829 <6>[ 3.715976] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10726 11:57:03.559813 <6>[ 3.727527] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10727 11:57:03.591418 <6>[ 3.758734] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 11:57:03.618696 <6>[ 3.789764] hub 2-1:1.0: USB hub found
10729 11:57:03.622113 <6>[ 3.794175] hub 2-1:1.0: 3 ports detected
10730 11:57:03.630666 <6>[ 3.801584] hub 2-1:1.0: USB hub found
10731 11:57:03.634027 <6>[ 3.805947] hub 2-1:1.0: 3 ports detected
10732 11:57:03.743102 <6>[ 3.910548] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10733 11:57:03.895944 <6>[ 4.066759] hub 1-1:1.0: USB hub found
10734 11:57:03.899044 <6>[ 4.071231] hub 1-1:1.0: 4 ports detected
10735 11:57:03.907554 <6>[ 4.078554] hub 1-1:1.0: USB hub found
10736 11:57:03.910988 <6>[ 4.083029] hub 1-1:1.0: 4 ports detected
10737 11:57:03.979281 <6>[ 4.146713] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10738 11:57:04.231157 <6>[ 4.398532] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10739 11:57:04.363770 <6>[ 4.534295] hub 1-1.4:1.0: USB hub found
10740 11:57:04.366852 <6>[ 4.538947] hub 1-1.4:1.0: 2 ports detected
10741 11:57:04.376282 <6>[ 4.547096] hub 1-1.4:1.0: USB hub found
10742 11:57:04.379242 <6>[ 4.551683] hub 1-1.4:1.0: 2 ports detected
10743 11:57:04.675011 <6>[ 4.842551] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10744 11:57:04.867018 <6>[ 5.034553] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10745 11:57:15.839831 <6>[ 16.015509] ALSA device list:
10746 11:57:15.846804 <6>[ 16.018805] No soundcards found.
10747 11:57:15.854801 <6>[ 16.026804] Freeing unused kernel memory: 8384K
10748 11:57:15.857795 <6>[ 16.031785] Run /init as init process
10749 11:57:15.904574 <6>[ 16.076268] NET: Registered PF_INET6 protocol family
10750 11:57:15.911183 <6>[ 16.082394] Segment Routing with IPv6
10751 11:57:15.914472 <6>[ 16.086371] In-situ OAM (IOAM) with IPv6
10752 11:57:15.948363 <30>[ 16.100434] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10753 11:57:15.951656 <30>[ 16.124147] systemd[1]: Detected architecture arm64.
10754 11:57:15.952095
10755 11:57:15.958325 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10756 11:57:15.958900
10757 11:57:15.974497 <30>[ 16.146624] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10758 11:57:16.140181 <30>[ 16.308999] systemd[1]: Queued start job for default target Graphical Interface.
10759 11:57:16.183497 <30>[ 16.355376] systemd[1]: Created slice system-getty.slice.
10760 11:57:16.190121 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10761 11:57:16.207558 <30>[ 16.379681] systemd[1]: Created slice system-modprobe.slice.
10762 11:57:16.214378 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10763 11:57:16.231105 <30>[ 16.402993] systemd[1]: Created slice system-serial\x2dgetty.slice.
10764 11:57:16.238124 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10765 11:57:16.255951 <30>[ 16.427923] systemd[1]: Created slice User and Session Slice.
10766 11:57:16.262532 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10767 11:57:16.282443 <30>[ 16.451189] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10768 11:57:16.292629 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10769 11:57:16.310888 <30>[ 16.479292] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10770 11:57:16.316958 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10771 11:57:16.342016 <30>[ 16.507025] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10772 11:57:16.349057 <30>[ 16.519285] systemd[1]: Reached target Local Encrypted Volumes.
10773 11:57:16.354942 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10774 11:57:16.370946 <30>[ 16.543084] systemd[1]: Reached target Paths.
10775 11:57:16.374217 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10776 11:57:16.390900 <30>[ 16.562534] systemd[1]: Reached target Remote File Systems.
10777 11:57:16.397322 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10778 11:57:16.410797 <30>[ 16.582486] systemd[1]: Reached target Slices.
10779 11:57:16.414211 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10780 11:57:16.431016 <30>[ 16.602535] systemd[1]: Reached target Swap.
10781 11:57:16.433948 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10782 11:57:16.454464 <30>[ 16.622962] systemd[1]: Listening on initctl Compatibility Named Pipe.
10783 11:57:16.460951 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10784 11:57:16.476026 <30>[ 16.647987] systemd[1]: Listening on Journal Audit Socket.
10785 11:57:16.482367 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10786 11:57:16.499804 <30>[ 16.671674] systemd[1]: Listening on Journal Socket (/dev/log).
10787 11:57:16.506379 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10788 11:57:16.524213 <30>[ 16.695736] systemd[1]: Listening on Journal Socket.
10789 11:57:16.530485 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10790 11:57:16.546621 <30>[ 16.715215] systemd[1]: Listening on Network Service Netlink Socket.
10791 11:57:16.553303 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10792 11:57:16.567963 <30>[ 16.739758] systemd[1]: Listening on udev Control Socket.
10793 11:57:16.574648 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10794 11:57:16.591799 <30>[ 16.763561] systemd[1]: Listening on udev Kernel Socket.
10795 11:57:16.598563 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10796 11:57:16.650867 <30>[ 16.822775] systemd[1]: Mounting Huge Pages File System...
10797 11:57:16.657561 Mounting [0;1;39mHuge Pages File System[0m...
10798 11:57:16.674982 <30>[ 16.846710] systemd[1]: Mounting POSIX Message Queue File System...
10799 11:57:16.681730 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10800 11:57:16.711020 <30>[ 16.882569] systemd[1]: Mounting Kernel Debug File System...
10801 11:57:16.717724 Mounting [0;1;39mKernel Debug File System[0m...
10802 11:57:16.734313 <30>[ 16.902940] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10803 11:57:16.747380 <30>[ 16.916076] systemd[1]: Starting Create list of static device nodes for the current kernel...
10804 11:57:16.754108 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10805 11:57:16.775359 <30>[ 16.946988] systemd[1]: Starting Load Kernel Module configfs...
10806 11:57:16.781649 Starting [0;1;39mLoad Kernel Module configfs[0m...
10807 11:57:16.798898 <30>[ 16.970466] systemd[1]: Starting Load Kernel Module drm...
10808 11:57:16.804934 Starting [0;1;39mLoad Kernel Module drm[0m...
10809 11:57:16.822194 <30>[ 16.990884] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10810 11:57:16.867034 <30>[ 17.038946] systemd[1]: Starting Journal Service...
10811 11:57:16.870311 Starting [0;1;39mJournal Service[0m...
10812 11:57:16.890146 <30>[ 17.061518] systemd[1]: Starting Load Kernel Modules...
10813 11:57:16.896020 Starting [0;1;39mLoad Kernel Modules[0m...
10814 11:57:16.916299 <30>[ 17.084844] systemd[1]: Starting Remount Root and Kernel File Systems...
10815 11:57:16.922358 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10816 11:57:16.938601 <30>[ 17.110550] systemd[1]: Starting Coldplug All udev Devices...
10817 11:57:16.945422 Starting [0;1;39mColdplug All udev Devices[0m...
10818 11:57:16.960710 <30>[ 17.132467] systemd[1]: Mounted Huge Pages File System.
10819 11:57:16.967201 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10820 11:57:16.983172 <30>[ 17.155080] systemd[1]: Started Journal Service.
10821 11:57:16.989780 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10822 11:57:17.005894 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10823 11:57:17.023472 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10824 11:57:17.044353 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10825 11:57:17.061005 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10826 11:57:17.077607 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10827 11:57:17.097117 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10828 11:57:17.117189 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10829 11:57:17.130962 See 'systemctl status systemd-remount-fs.service' for details.
10830 11:57:17.168685 Mounting [0;1;39mKernel Configuration File System[0m...
10831 11:57:17.185297 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10832 11:57:17.198898 <46>[ 17.367390] systemd-journald[173]: Received client request to flush runtime journal.
10833 11:57:17.207905 Starting [0;1;39mLoad/Save Random Seed[0m...
10834 11:57:17.226710 Starting [0;1;39mApply Kernel Variables[0m...
10835 11:57:17.247909 Starting [0;1;39mCreate System Users[0m...
10836 11:57:17.268034 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10837 11:57:17.283441 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10838 11:57:17.308016 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10839 11:57:17.320959 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10840 11:57:17.335295 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10841 11:57:17.351526 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10842 11:57:17.379055 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10843 11:57:17.399554 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10844 11:57:17.415371 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10845 11:57:17.434831 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10846 11:57:17.486747 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10847 11:57:17.512083 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10848 11:57:17.533056 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10849 11:57:17.554969 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10850 11:57:17.568070 Starting [0;1;39mNetwork Service[0m...
10851 11:57:17.588998 Starting [0;1;39mNetwork Time Synchronization[0m...
10852 11:57:17.606760 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10853 11:57:17.626064 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10854 11:57:17.700329 <6>[ 17.868903] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10855 11:57:17.710232 Starting [0;1;39mNetwo<6>[ 17.879812] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10856 11:57:17.723310 rk Name Resoluti<6>[ 17.889699] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10857 11:57:17.723884 on[0m...
10858 11:57:17.742029 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10859 11:57:17.787403 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10860 11:57:17.797363 <4>[ 17.966137] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10861 11:57:17.810572 [[0;32m OK [<4>[ 17.979979] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10862 11:57:17.820531 0m] Started [0;<6>[ 17.982840] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10863 11:57:17.828486 1;39mNetwork Name Resolution[0m.
10864 11:57:17.834987 <6>[ 18.006874] remoteproc remoteproc0: scp is available
10865 11:57:17.841147 <6>[ 18.012520] remoteproc remoteproc0: powering up scp
10866 11:57:17.845359 <6>[ 18.013697] mc: Linux media interface: v0.10
10867 11:57:17.854652 <6>[ 18.017661] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10868 11:57:17.857972 <6>[ 18.017684] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10869 11:57:17.864809 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10870 11:57:17.875258 <6>[ 18.044009] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10871 11:57:17.878504 <6>[ 18.051006] pci_bus 0000:00: root bus resource [bus 00-ff]
10872 11:57:17.888562 <6>[ 18.056929] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10873 11:57:17.898499 <6>[ 18.064144] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10874 11:57:17.905067 <6>[ 18.075794] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10875 11:57:17.912156 <3>[ 18.075955] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 11:57:17.921729 <3>[ 18.075971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 11:57:17.928222 <3>[ 18.075976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 11:57:17.938703 <3>[ 18.079486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 11:57:17.944979 <6>[ 18.084232] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10880 11:57:17.954706 <3>[ 18.091114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 11:57:17.961732 <6>[ 18.095621] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10882 11:57:17.965604 <6>[ 18.098956] pci 0000:00:00.0: supports D1 D2
10883 11:57:17.972317 <6>[ 18.099563] videodev: Linux video capture interface: v2.00
10884 11:57:17.978646 <3>[ 18.106785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 11:57:17.989380 <3>[ 18.106802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 11:57:17.995501 <3>[ 18.106809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 11:57:18.005554 <3>[ 18.106950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 11:57:18.011859 <3>[ 18.107041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 11:57:18.018968 <6>[ 18.115478] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10890 11:57:18.026409 <6>[ 18.116181] usbcore: registered new interface driver r8152
10891 11:57:18.033253 <6>[ 18.118902] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10892 11:57:18.043210 <3>[ 18.122768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 11:57:18.050052 <3>[ 18.122789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 11:57:18.059842 <4>[ 18.125530] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10895 11:57:18.063090 <4>[ 18.125530] Fallback method does not support PEC.
10896 11:57:18.069784 <6>[ 18.142995] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10897 11:57:18.079708 <6>[ 18.143090] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10898 11:57:18.089626 <6>[ 18.143313] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10899 11:57:18.093163 <6>[ 18.143512] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10900 11:57:18.100250 <6>[ 18.143541] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10901 11:57:18.110781 <6>[ 18.143562] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10902 11:57:18.117479 <6>[ 18.143577] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10903 11:57:18.120943 <6>[ 18.143688] pci 0000:01:00.0: supports D1 D2
10904 11:57:18.127447 <6>[ 18.143690] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10905 11:57:18.137623 <3>[ 18.143928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 11:57:18.144517 <3>[ 18.143945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 11:57:18.150778 <3>[ 18.143953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 11:57:18.160678 <3>[ 18.143965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 11:57:18.167625 <3>[ 18.143972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 11:57:18.177697 <3>[ 18.144069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 11:57:18.185295 <3>[ 18.149310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 11:57:18.195600 <6>[ 18.152706] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10913 11:57:18.206339 <6>[ 18.154108] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10914 11:57:18.209714 <6>[ 18.156954] remoteproc remoteproc0: remote processor scp is now up
10915 11:57:18.216105 <6>[ 18.174076] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10916 11:57:18.226223 <6>[ 18.197153] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10917 11:57:18.233150 <6>[ 18.202927] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10918 11:57:18.242569 <3>[ 18.205353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:57:18.249620 <6>[ 18.217556] usbcore: registered new interface driver cdc_ether
10920 11:57:18.256370 <6>[ 18.219567] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10921 11:57:18.260012 <6>[ 18.220950] Bluetooth: Core ver 2.22
10922 11:57:18.263897 <6>[ 18.221012] NET: Registered PF_BLUETOOTH protocol family
10923 11:57:18.270521 <6>[ 18.221014] Bluetooth: HCI device and connection manager initialized
10924 11:57:18.277110 <6>[ 18.221034] Bluetooth: HCI socket layer initialized
10925 11:57:18.283581 <6>[ 18.221040] Bluetooth: L2CAP socket layer initialized
10926 11:57:18.286817 <6>[ 18.221052] Bluetooth: SCO socket layer initialized
10927 11:57:18.297591 <6>[ 18.229522] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10928 11:57:18.304126 <6>[ 18.241236] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10929 11:57:18.310581 <6>[ 18.248691] usbcore: registered new interface driver r8153_ecm
10930 11:57:18.317741 <6>[ 18.252236] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10931 11:57:18.327522 <6>[ 18.256789] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10932 11:57:18.334589 <6>[ 18.256804] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10933 11:57:18.341414 <6>[ 18.257685] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10934 11:57:18.354253 <6>[ 18.258700] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10935 11:57:18.361106 <6>[ 18.258789] usbcore: registered new interface driver uvcvideo
10936 11:57:18.364423 <6>[ 18.279753] usbcore: registered new interface driver btusb
10937 11:57:18.377215 <4>[ 18.280458] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10938 11:57:18.380625 <3>[ 18.280480] Bluetooth: hci0: Failed to load firmware file (-2)
10939 11:57:18.387464 <3>[ 18.280484] Bluetooth: hci0: Failed to set up firmware (-2)
10940 11:57:18.397688 <4>[ 18.280487] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10941 11:57:18.403876 <6>[ 18.283131] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10942 11:57:18.410410 <6>[ 18.286257] pci 0000:00:00.0: PCI bridge to [bus 01]
10943 11:57:18.417508 <6>[ 18.305697] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10944 11:57:18.423984 <6>[ 18.313180] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10945 11:57:18.434258 <3>[ 18.322885] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 11:57:18.441147 <6>[ 18.329480] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10947 11:57:18.444612 <6>[ 18.334418] r8152 2-1.3:1.0 eth0: v1.12.13
10948 11:57:18.450936 <6>[ 18.346975] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10949 11:57:18.454480 <6>[ 18.354138] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10950 11:57:18.464799 <3>[ 18.360282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10951 11:57:18.475217 <3>[ 18.361147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:57:18.481935 <3>[ 18.366521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 11:57:18.488975 <6>[ 18.372871] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10954 11:57:18.495920 <3>[ 18.385774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 11:57:18.505949 <5>[ 18.412557] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10956 11:57:18.512667 <3>[ 18.439477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 11:57:18.522292 <5>[ 18.458163] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10958 11:57:18.529348 <3>[ 18.479899] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:57:18.538989 <4>[ 18.481148] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10960 11:57:18.548898 <3>[ 18.507182] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 11:57:18.552411 <6>[ 18.511419] cfg80211: failed to load regulatory.db
10962 11:57:18.559569 <6>[ 18.585955] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10963 11:57:18.565333 <6>[ 18.736959] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10964 11:57:18.571937 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10965 11:57:18.594319 [[0;32m OK [<6>[ 18.763821] mt7921e 0000:01:00.0: ASIC revision: 79610010
10966 11:57:18.597673 0m] Reached target [0;1;39mNetwork[0m.
10967 11:57:18.617926 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10968 11:57:18.630489 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10969 11:57:18.646695 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10970 11:57:18.695474 Startin<4>[ 18.861773] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 11:57:18.702168 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10972 11:57:18.724535 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10973 11:57:18.815075 <4>[ 18.980701] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 11:57:18.862419 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10975 11:57:18.882315 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10976 11:57:18.906545 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 11:57:18.923411 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10978 11:57:18.933383 <4>[ 19.100847] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 11:57:18.941629 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10980 11:57:18.959679 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10981 11:57:18.974864 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10982 11:57:18.994365 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10983 11:57:19.018514 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10984 11:57:19.055387 <4>[ 19.220667] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 11:57:19.061711 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10986 11:57:19.091021 Starting [0;1;39mUser Login Management[0m...
10987 11:57:19.113050 Starting [0;1;39mPermit User Sessions[0m...
10988 11:57:19.129573 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10989 11:57:19.178547 <4>[ 19.344115] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 11:57:19.185202 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10991 11:57:19.207049 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10992 11:57:19.222878 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10993 11:57:19.246149 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10994 11:57:19.264858 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10995 11:57:19.298711 [[0;32m OK [<4>[ 19.464980] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 11:57:19.305016 0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10997 11:57:19.324335 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10998 11:57:19.342755 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10999 11:57:19.422365 Starting [0;1;39mUpdate UTMP about System Runlevel Cha<4>[ 19.587093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11000 11:57:19.422995 nges[0m...
11001 11:57:19.465182 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11002 11:57:19.504328
11003 11:57:19.504898
11004 11:57:19.507697 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11005 11:57:19.508273
11006 11:57:19.511123 debian-bullseye-arm64 login: root (automatic login)
11007 11:57:19.511690
11008 11:57:19.512063
11009 11:57:19.540082 <4>[ 19.705812] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11010 11:57:19.546724 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
11011 11:57:19.547293
11012 11:57:19.556414 The programs included with the Debian GNU/Linux system are free software;
11013 11:57:19.560092 the exact distribution terms for each program are described in the
11014 11:57:19.566851 individual files in /usr/share/doc/*/copyright.
11015 11:57:19.567440
11016 11:57:19.570124 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11017 11:57:19.573661 permitted by applicable law.
11018 11:57:19.575188 Matched prompt #10: / #
11020 11:57:19.576310 Setting prompt string to ['/ #']
11021 11:57:19.576789 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11023 11:57:19.577853 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11024 11:57:19.578345 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11025 11:57:19.578791 Setting prompt string to ['/ #']
11026 11:57:19.579148 Forcing a shell prompt, looking for ['/ #']
11028 11:57:19.630137 / #
11029 11:57:19.630849 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11030 11:57:19.631319 Waiting using forced prompt support (timeout 00:02:30)
11031 11:57:19.636421
11032 11:57:19.637355 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11033 11:57:19.637897 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11034 11:57:19.638446 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11035 11:57:19.638970 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11036 11:57:19.639432 end: 2 depthcharge-action (duration 00:01:43) [common]
11037 11:57:19.639925 start: 3 lava-test-retry (timeout 00:05:00) [common]
11038 11:57:19.640407 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11039 11:57:19.640815 Using namespace: common
11041 11:57:19.742088 / # #
11042 11:57:19.742813 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11043 11:57:19.743404 <4>[ 19.828877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11044 11:57:19.748471 #
11045 11:57:19.749358 Using /lava-12066556
11047 11:57:19.850530 / # export SHELL=/bin/sh
11048 11:57:19.851317 <4>[ 19.948812] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11049 11:57:19.857258 export SHELL=/bin/sh
11051 11:57:19.959019 / # . /lava-12066556/environment
11052 11:57:19.959809 <3>[ 20.066707] mt7921e 0000:01:00.0: hardware init failed
11053 11:57:19.965494 . /lava-12066556/environment
11055 11:57:20.067378 / # /lava-12066556/bin/lava-test-runner /lava-12066556/0
11056 11:57:20.068015 Test shell timeout: 10s (minimum of the action and connection timeout)
11057 11:57:20.069652 <6>[ 20.188779] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11058 11:57:20.070092 <6>[ 20.196801] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11059 11:57:20.074550 /lava-12066556/bin/lava-test-run/0
11060 11:57:20.114932 -sh: 5: /lava-12066556/bin/lava-test-run/0: not found
11061 11:57:45.979934 / # <6>[ 46.158664] vpu: disabling
11062 11:57:45.982868 <6>[ 46.161781] vproc2: disabling
11063 11:57:45.986336 <6>[ 46.165120] vproc1: disabling
11064 11:57:45.989694 <6>[ 46.168429] vaud18: disabling
11065 11:57:45.996032 <6>[ 46.171937] vsram_others: disabling
11066 11:57:46.000113 <6>[ 46.175899] va09: disabling
11067 11:57:46.003045 <6>[ 46.179063] vsram_md: disabling
11068 11:57:46.007071 <6>[ 46.182626] Vgpu: disabling
11070 12:02:19.640750 end: 3.1 lava-test-shell (duration 00:05:00) [common]
11072 12:02:19.641011 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 300 seconds'
11074 12:02:19.641215 end: 3 lava-test-retry (duration 00:05:00) [common]
11076 12:02:19.641504 Cleaning after the job
11077 12:02:19.641615 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/ramdisk
11078 12:02:19.647935 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/kernel
11079 12:02:19.660022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/dtb
11080 12:02:19.660212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066556/tftp-deploy-ht9p51d_/modules
11081 12:02:19.665499 start: 4.1 power-off (timeout 00:00:30) [common]
11082 12:02:19.665663 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11083 12:02:19.748227 >> Command sent successfully.
11084 12:02:19.759178 Returned 0 in 0 seconds
11085 12:02:19.860521 end: 4.1 power-off (duration 00:00:00) [common]
11087 12:02:19.862123 start: 4.2 read-feedback (timeout 00:10:00) [common]
11088 12:02:19.863546 Listened to connection for namespace 'common' for up to 1s
11089 12:02:20.864329 Finalising connection for namespace 'common'
11090 12:02:20.865097 Disconnecting from shell: Finalise
11091 12:02:20.966236 end: 4.2 read-feedback (duration 00:00:01) [common]
11092 12:02:20.966957 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066556
11093 12:02:21.101051 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066556
11094 12:02:21.101251 TestError: A test failed to run, look at the error message.