Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 35
- Kernel Warnings: 22
- Boot result: PASS
- Errors: 0
1 11:50:30.801197 lava-dispatcher, installed at version: 2023.10
2 11:50:30.801409 start: 0 validate
3 11:50:30.801549 Start time: 2023-11-23 11:50:30.801541+00:00 (UTC)
4 11:50:30.801675 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:50:30.801806 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:50:31.072336 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:50:31.072850 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:50:31.342348 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:50:31.343189 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:51:20.290003 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:51:20.290714 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:51:20.822914 validate duration: 50.02
14 11:51:20.823169 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:51:20.823263 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:51:20.823348 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:51:20.823468 Not decompressing ramdisk as can be used compressed.
18 11:51:20.823555 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 11:51:20.823619 saving as /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/ramdisk/rootfs.cpio.gz
20 11:51:20.823683 total size: 43284872 (41 MB)
21 11:51:23.670115 progress 0 % (0 MB)
22 11:51:23.684697 progress 5 % (2 MB)
23 11:51:23.695517 progress 10 % (4 MB)
24 11:51:23.706339 progress 15 % (6 MB)
25 11:51:23.717237 progress 20 % (8 MB)
26 11:51:23.728268 progress 25 % (10 MB)
27 11:51:23.739412 progress 30 % (12 MB)
28 11:51:23.750338 progress 35 % (14 MB)
29 11:51:23.761674 progress 40 % (16 MB)
30 11:51:23.772829 progress 45 % (18 MB)
31 11:51:23.784062 progress 50 % (20 MB)
32 11:51:23.795027 progress 55 % (22 MB)
33 11:51:23.805919 progress 60 % (24 MB)
34 11:51:23.816866 progress 65 % (26 MB)
35 11:51:23.827791 progress 70 % (28 MB)
36 11:51:23.839010 progress 75 % (30 MB)
37 11:51:23.849873 progress 80 % (33 MB)
38 11:51:23.861012 progress 85 % (35 MB)
39 11:51:23.872229 progress 90 % (37 MB)
40 11:51:23.882981 progress 95 % (39 MB)
41 11:51:23.893781 progress 100 % (41 MB)
42 11:51:23.894020 41 MB downloaded in 3.07 s (13.44 MB/s)
43 11:51:23.894169 end: 1.1.1 http-download (duration 00:00:03) [common]
45 11:51:23.894405 end: 1.1 download-retry (duration 00:00:03) [common]
46 11:51:23.894492 start: 1.2 download-retry (timeout 00:09:57) [common]
47 11:51:23.894576 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 11:51:23.894709 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:51:23.894781 saving as /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/kernel/Image
50 11:51:23.894842 total size: 49107456 (46 MB)
51 11:51:23.894902 No compression specified
52 11:51:23.896073 progress 0 % (0 MB)
53 11:51:23.908532 progress 5 % (2 MB)
54 11:51:23.920819 progress 10 % (4 MB)
55 11:51:23.933360 progress 15 % (7 MB)
56 11:51:23.945968 progress 20 % (9 MB)
57 11:51:23.958513 progress 25 % (11 MB)
58 11:51:23.971001 progress 30 % (14 MB)
59 11:51:23.983335 progress 35 % (16 MB)
60 11:51:23.995758 progress 40 % (18 MB)
61 11:51:24.008205 progress 45 % (21 MB)
62 11:51:24.020890 progress 50 % (23 MB)
63 11:51:24.033461 progress 55 % (25 MB)
64 11:51:24.045849 progress 60 % (28 MB)
65 11:51:24.058499 progress 65 % (30 MB)
66 11:51:24.070997 progress 70 % (32 MB)
67 11:51:24.083268 progress 75 % (35 MB)
68 11:51:24.095656 progress 80 % (37 MB)
69 11:51:24.108012 progress 85 % (39 MB)
70 11:51:24.120502 progress 90 % (42 MB)
71 11:51:24.133300 progress 95 % (44 MB)
72 11:51:24.145552 progress 100 % (46 MB)
73 11:51:24.145767 46 MB downloaded in 0.25 s (186.64 MB/s)
74 11:51:24.145919 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:51:24.146146 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:51:24.146237 start: 1.3 download-retry (timeout 00:09:57) [common]
78 11:51:24.146326 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 11:51:24.146464 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:51:24.146532 saving as /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/dtb/mt8192-asurada-spherion-r0.dtb
81 11:51:24.146592 total size: 47278 (0 MB)
82 11:51:24.146669 No compression specified
83 11:51:24.147763 progress 69 % (0 MB)
84 11:51:24.148062 progress 100 % (0 MB)
85 11:51:24.148215 0 MB downloaded in 0.00 s (27.83 MB/s)
86 11:51:24.148335 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:51:24.148609 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:51:24.148694 start: 1.4 download-retry (timeout 00:09:57) [common]
90 11:51:24.148775 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 11:51:24.148891 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:51:24.148963 saving as /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/modules/modules.tar
93 11:51:24.149023 total size: 8621364 (8 MB)
94 11:51:24.149084 Using unxz to decompress xz
95 11:51:24.153447 progress 0 % (0 MB)
96 11:51:24.174403 progress 5 % (0 MB)
97 11:51:24.197634 progress 10 % (0 MB)
98 11:51:24.221137 progress 15 % (1 MB)
99 11:51:24.244967 progress 20 % (1 MB)
100 11:51:24.268829 progress 25 % (2 MB)
101 11:51:24.294450 progress 30 % (2 MB)
102 11:51:24.320309 progress 35 % (2 MB)
103 11:51:24.345230 progress 40 % (3 MB)
104 11:51:24.370587 progress 45 % (3 MB)
105 11:51:24.395833 progress 50 % (4 MB)
106 11:51:24.420438 progress 55 % (4 MB)
107 11:51:24.445579 progress 60 % (4 MB)
108 11:51:24.474595 progress 65 % (5 MB)
109 11:51:24.500779 progress 70 % (5 MB)
110 11:51:24.523927 progress 75 % (6 MB)
111 11:51:24.550782 progress 80 % (6 MB)
112 11:51:24.576754 progress 85 % (7 MB)
113 11:51:24.601560 progress 90 % (7 MB)
114 11:51:24.631084 progress 95 % (7 MB)
115 11:51:24.660950 progress 100 % (8 MB)
116 11:51:24.665900 8 MB downloaded in 0.52 s (15.91 MB/s)
117 11:51:24.666158 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:51:24.666421 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:51:24.666515 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 11:51:24.666613 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 11:51:24.666696 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:51:24.666783 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 11:51:24.667014 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk
125 11:51:24.667150 makedir: /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin
126 11:51:24.667258 makedir: /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/tests
127 11:51:24.667360 makedir: /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/results
128 11:51:24.667480 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-add-keys
129 11:51:24.667630 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-add-sources
130 11:51:24.667764 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-background-process-start
131 11:51:24.667897 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-background-process-stop
132 11:51:24.668026 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-common-functions
133 11:51:24.668154 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-echo-ipv4
134 11:51:24.668284 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-install-packages
135 11:51:24.668411 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-installed-packages
136 11:51:24.668583 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-os-build
137 11:51:24.668714 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-probe-channel
138 11:51:24.668842 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-probe-ip
139 11:51:24.668969 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-target-ip
140 11:51:24.669102 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-target-mac
141 11:51:24.669228 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-target-storage
142 11:51:24.669360 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-case
143 11:51:24.669489 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-event
144 11:51:24.669615 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-feedback
145 11:51:24.669742 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-raise
146 11:51:24.669870 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-reference
147 11:51:24.669997 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-runner
148 11:51:24.670125 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-set
149 11:51:24.670254 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-test-shell
150 11:51:24.670383 Updating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-install-packages (oe)
151 11:51:24.670540 Updating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/bin/lava-installed-packages (oe)
152 11:51:24.670664 Creating /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/environment
153 11:51:24.670764 LAVA metadata
154 11:51:24.670839 - LAVA_JOB_ID=12066513
155 11:51:24.670904 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:51:24.671015 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 11:51:24.671103 skipped lava-vland-overlay
158 11:51:24.671214 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:51:24.671300 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 11:51:24.671372 skipped lava-multinode-overlay
161 11:51:24.671446 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:51:24.671532 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 11:51:24.671610 Loading test definitions
164 11:51:24.671703 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 11:51:24.671778 Using /lava-12066513 at stage 0
166 11:51:24.672092 uuid=12066513_1.5.2.3.1 testdef=None
167 11:51:24.672182 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:51:24.672267 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 11:51:24.672855 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:51:24.673076 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 11:51:24.673709 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:51:24.673939 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 11:51:24.674603 runner path: /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/0/tests/0_igt-gpu-panfrost test_uuid 12066513_1.5.2.3.1
176 11:51:24.674760 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:51:24.674967 Creating lava-test-runner.conf files
179 11:51:24.675031 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066513/lava-overlay-vvrsndmk/lava-12066513/0 for stage 0
180 11:51:24.675120 - 0_igt-gpu-panfrost
181 11:51:24.675216 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:51:24.675303 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 11:51:24.682011 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:51:24.682119 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 11:51:24.682205 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:51:24.682289 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:51:24.682380 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 11:51:26.079496 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:51:26.079886 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 11:51:26.080008 extracting modules file /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066513/extract-overlay-ramdisk-lzko_msn/ramdisk
191 11:51:26.311502 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:51:26.311676 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 11:51:26.311771 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066513/compress-overlay-kl5_k82_/overlay-1.5.2.4.tar.gz to ramdisk
194 11:51:26.311844 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066513/compress-overlay-kl5_k82_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066513/extract-overlay-ramdisk-lzko_msn/ramdisk
195 11:51:26.318551 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:51:26.318671 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 11:51:26.318766 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:51:26.318857 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 11:51:26.318936 Building ramdisk /var/lib/lava/dispatcher/tmp/12066513/extract-overlay-ramdisk-lzko_msn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066513/extract-overlay-ramdisk-lzko_msn/ramdisk
200 11:51:27.367032 >> 369976 blocks
201 11:51:33.273660 rename /var/lib/lava/dispatcher/tmp/12066513/extract-overlay-ramdisk-lzko_msn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/ramdisk/ramdisk.cpio.gz
202 11:51:33.274109 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:51:33.274231 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 11:51:33.274337 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 11:51:33.274441 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/kernel/Image'
206 11:51:45.373614 Returned 0 in 12 seconds
207 11:51:45.474245 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/kernel/image.itb
208 11:51:46.299702 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:51:46.300089 output: Created: Thu Nov 23 11:51:46 2023
210 11:51:46.300166 output: Image 0 (kernel-1)
211 11:51:46.300235 output: Description:
212 11:51:46.300299 output: Created: Thu Nov 23 11:51:46 2023
213 11:51:46.300363 output: Type: Kernel Image
214 11:51:46.300425 output: Compression: lzma compressed
215 11:51:46.300485 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
216 11:51:46.300587 output: Architecture: AArch64
217 11:51:46.300645 output: OS: Linux
218 11:51:46.300700 output: Load Address: 0x00000000
219 11:51:46.300756 output: Entry Point: 0x00000000
220 11:51:46.300810 output: Hash algo: crc32
221 11:51:46.300865 output: Hash value: e6d7c86f
222 11:51:46.300919 output: Image 1 (fdt-1)
223 11:51:46.300971 output: Description: mt8192-asurada-spherion-r0
224 11:51:46.301024 output: Created: Thu Nov 23 11:51:46 2023
225 11:51:46.301109 output: Type: Flat Device Tree
226 11:51:46.301161 output: Compression: uncompressed
227 11:51:46.301212 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:51:46.301264 output: Architecture: AArch64
229 11:51:46.301315 output: Hash algo: crc32
230 11:51:46.301367 output: Hash value: cc4352de
231 11:51:46.301418 output: Image 2 (ramdisk-1)
232 11:51:46.301470 output: Description: unavailable
233 11:51:46.301521 output: Created: Thu Nov 23 11:51:46 2023
234 11:51:46.301572 output: Type: RAMDisk Image
235 11:51:46.301624 output: Compression: Unknown Compression
236 11:51:46.301676 output: Data Size: 56431561 Bytes = 55108.95 KiB = 53.82 MiB
237 11:51:46.301728 output: Architecture: AArch64
238 11:51:46.301779 output: OS: Linux
239 11:51:46.301830 output: Load Address: unavailable
240 11:51:46.301882 output: Entry Point: unavailable
241 11:51:46.301933 output: Hash algo: crc32
242 11:51:46.301984 output: Hash value: 4c38618c
243 11:51:46.302035 output: Default Configuration: 'conf-1'
244 11:51:46.302086 output: Configuration 0 (conf-1)
245 11:51:46.302138 output: Description: mt8192-asurada-spherion-r0
246 11:51:46.302189 output: Kernel: kernel-1
247 11:51:46.302240 output: Init Ramdisk: ramdisk-1
248 11:51:46.302291 output: FDT: fdt-1
249 11:51:46.302343 output: Loadables: kernel-1
250 11:51:46.302394 output:
251 11:51:46.302600 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:51:46.302701 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:51:46.302804 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 11:51:46.302899 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 11:51:46.302974 No LXC device requested
256 11:51:46.303071 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:51:46.303168 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 11:51:46.303242 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:51:46.303312 Checking files for TFTP limit of 4294967296 bytes.
260 11:51:46.303805 end: 1 tftp-deploy (duration 00:00:25) [common]
261 11:51:46.303914 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:51:46.304001 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:51:46.304119 substitutions:
264 11:51:46.304184 - {DTB}: 12066513/tftp-deploy-5ilml9ro/dtb/mt8192-asurada-spherion-r0.dtb
265 11:51:46.304247 - {INITRD}: 12066513/tftp-deploy-5ilml9ro/ramdisk/ramdisk.cpio.gz
266 11:51:46.304306 - {KERNEL}: 12066513/tftp-deploy-5ilml9ro/kernel/Image
267 11:51:46.304362 - {LAVA_MAC}: None
268 11:51:46.304417 - {PRESEED_CONFIG}: None
269 11:51:46.304471 - {PRESEED_LOCAL}: None
270 11:51:46.304552 - {RAMDISK}: 12066513/tftp-deploy-5ilml9ro/ramdisk/ramdisk.cpio.gz
271 11:51:46.304622 - {ROOT_PART}: None
272 11:51:46.304675 - {ROOT}: None
273 11:51:46.304727 - {SERVER_IP}: 192.168.201.1
274 11:51:46.304780 - {TEE}: None
275 11:51:46.304833 Parsed boot commands:
276 11:51:46.304885 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:51:46.305067 Parsed boot commands: tftpboot 192.168.201.1 12066513/tftp-deploy-5ilml9ro/kernel/image.itb 12066513/tftp-deploy-5ilml9ro/kernel/cmdline
278 11:51:46.305154 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:51:46.305243 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:51:46.305336 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:51:46.305417 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:51:46.305485 Not connected, no need to disconnect.
283 11:51:46.305557 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:51:46.305639 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:51:46.305702 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:51:46.309912 Setting prompt string to ['lava-test: # ']
287 11:51:46.310429 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:51:46.310614 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:51:46.310766 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:51:46.310943 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:51:46.311213 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 11:51:51.442923 >> Command sent successfully.
293 11:51:51.445431 Returned 0 in 5 seconds
294 11:51:51.545810 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:51:51.546127 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:51:51.546233 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:51:51.546322 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:51:51.546388 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:51:51.546457 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:51:51.546718 [Enter `^Ec?' for help]
302 11:51:51.726104
303 11:51:51.726255
304 11:51:51.726324 F0: 102B 0000
305 11:51:51.726391
306 11:51:51.726453 F3: 1001 0000 [0200]
307 11:51:51.729415
308 11:51:51.729498 F3: 1001 0000
309 11:51:51.729565
310 11:51:51.729626 F7: 102D 0000
311 11:51:51.729686
312 11:51:51.732745 F1: 0000 0000
313 11:51:51.732829
314 11:51:51.732896 V0: 0000 0000 [0001]
315 11:51:51.732958
316 11:51:51.735975 00: 0007 8000
317 11:51:51.736060
318 11:51:51.736128 01: 0000 0000
319 11:51:51.736191
320 11:51:51.739292 BP: 0C00 0209 [0000]
321 11:51:51.739375
322 11:51:51.739442 G0: 1182 0000
323 11:51:51.739504
324 11:51:51.743000 EC: 0000 0021 [4000]
325 11:51:51.743083
326 11:51:51.743149 S7: 0000 0000 [0000]
327 11:51:51.743210
328 11:51:51.746893 CC: 0000 0000 [0001]
329 11:51:51.746977
330 11:51:51.747043 T0: 0000 0040 [010F]
331 11:51:51.747104
332 11:51:51.747188 Jump to BL
333 11:51:51.747249
334 11:51:51.773234
335 11:51:51.773339
336 11:51:51.773404
337 11:51:51.780750 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:51:51.784416 ARM64: Exception handlers installed.
339 11:51:51.787809 ARM64: Testing exception
340 11:51:51.791203 ARM64: Done test exception
341 11:51:51.797937 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:51:51.807752 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:51:51.814300 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:51:51.824719 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:51:51.831118 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:51:51.837852 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:51:51.849745 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:51:51.856807 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:51:51.875756 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:51:51.879091 WDT: Last reset was cold boot
351 11:51:51.882492 SPI1(PAD0) initialized at 2873684 Hz
352 11:51:51.886107 SPI5(PAD0) initialized at 992727 Hz
353 11:51:51.889135 VBOOT: Loading verstage.
354 11:51:51.895977 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:51:51.899104 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:51:51.902445 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:51:51.905869 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:51:51.913356 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:51:51.920006 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:51:51.931073 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:51:51.931158
362 11:51:51.931224
363 11:51:51.940899 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:51:51.944720 ARM64: Exception handlers installed.
365 11:51:51.947976 ARM64: Testing exception
366 11:51:51.948067 ARM64: Done test exception
367 11:51:51.954614 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:51:51.958030 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:51:51.972089 Probing TPM: . done!
370 11:51:51.972200 TPM ready after 0 ms
371 11:51:51.978740 Connected to device vid:did:rid of 1ae0:0028:00
372 11:51:51.985600 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 11:51:51.989390 Initialized TPM device CR50 revision 0
374 11:51:52.048412 tlcl_send_startup: Startup return code is 0
375 11:51:52.048613 TPM: setup succeeded
376 11:51:52.059125 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:51:52.068270 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:51:52.078072 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:51:52.087112 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:51:52.089977 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:51:52.093416 in-header: 03 07 00 00 08 00 00 00
382 11:51:52.096707 in-data: aa e4 47 04 13 02 00 00
383 11:51:52.099907 Chrome EC: UHEPI supported
384 11:51:52.106551 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:51:52.110331 in-header: 03 95 00 00 08 00 00 00
386 11:51:52.114088 in-data: 18 20 20 08 00 00 00 00
387 11:51:52.114225 Phase 1
388 11:51:52.117789 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:51:52.124807 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:51:52.128407 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:51:52.132438 Recovery requested (1009000e)
392 11:51:52.141469 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:51:52.147138 tlcl_extend: response is 0
394 11:51:52.156284 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:51:52.161840 tlcl_extend: response is 0
396 11:51:52.168762 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:51:52.189276 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:51:52.196876 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:51:52.196984
400 11:51:52.197050
401 11:51:52.204001 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:51:52.207723 ARM64: Exception handlers installed.
403 11:51:52.211296 ARM64: Testing exception
404 11:51:52.214648 ARM64: Done test exception
405 11:51:52.234413 pmic_efuse_setting: Set efuses in 11 msecs
406 11:51:52.237635 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:51:52.244259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:51:52.247647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:51:52.254372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:51:52.258025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:51:52.264370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:51:52.267712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:51:52.271079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:51:52.277587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:51:52.280932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:51:52.287724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:51:52.290998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:51:52.294664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:51:52.301176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:51:52.307806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:51:52.311441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:51:52.318831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:51:52.322349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:51:52.329724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:51:52.336658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:51:52.340047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:51:52.347074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:51:52.350811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:51:52.357574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:51:52.361390 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:51:52.368820 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:51:52.375773 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:51:52.379349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:51:52.382777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:51:52.389998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:51:52.393689 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:51:52.397100 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:51:52.404264 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:51:52.408216 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:51:52.415142 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:51:52.418982 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:51:52.422754 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:51:52.429948 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:51:52.433515 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:51:52.437381 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:51:52.440897 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:51:52.448293 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:51:52.451878 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:51:52.455467 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:51:52.458778 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:51:52.462862 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:51:52.470204 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:51:52.473640 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:51:52.477376 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:51:52.481203 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:51:52.485016 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:51:52.488614 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:51:52.499165 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:51:52.506506 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:51:52.510044 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:51:52.517401 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:51:52.528766 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:51:52.531977 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:51:52.535605 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:51:52.538863 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:51:52.547925 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:51:52.551348 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:51:52.559720 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:51:52.563011 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:51:52.571685 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 11:51:52.581393 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 11:51:52.590946 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 11:51:52.600330 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 11:51:52.610060 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 11:51:52.619809 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 11:51:52.629202 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 11:51:52.632754 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:51:52.640450 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:51:52.640574 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:51:52.647926 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:51:52.651345 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:51:52.655491 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:51:52.659122 ADC[4]: Raw value=669695 ID=5
484 11:51:52.659204 ADC[3]: Raw value=212917 ID=1
485 11:51:52.662755 RAM Code: 0x51
486 11:51:52.666846 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:51:52.670161 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:51:52.677712 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:51:52.684926 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:51:52.688629 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:51:52.692056 in-header: 03 07 00 00 08 00 00 00
492 11:51:52.695860 in-data: aa e4 47 04 13 02 00 00
493 11:51:52.699025 Chrome EC: UHEPI supported
494 11:51:52.706443 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:51:52.710086 in-header: 03 95 00 00 08 00 00 00
496 11:51:52.713989 in-data: 18 20 20 08 00 00 00 00
497 11:51:52.714072 MRC: failed to locate region type 0.
498 11:51:52.721162 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:51:52.724668 DRAM-K: Running full calibration
500 11:51:52.732121 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:51:52.732204 header.status = 0x0
502 11:51:52.735929 header.version = 0x6 (expected: 0x6)
503 11:51:52.739644 header.size = 0xd00 (expected: 0xd00)
504 11:51:52.739726 header.flags = 0x0
505 11:51:52.746488 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:51:52.765297 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 11:51:52.772622 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:51:52.776154 dram_init: ddr_geometry: 0
509 11:51:52.776239 [EMI] MDL number = 0
510 11:51:52.779912 [EMI] Get MDL freq = 0
511 11:51:52.779993 dram_init: ddr_type: 0
512 11:51:52.783890 is_discrete_lpddr4: 1
513 11:51:52.787533 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:51:52.787615
515 11:51:52.787678
516 11:51:52.787737 [Bian_co] ETT version 0.0.0.1
517 11:51:52.794754 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:51:52.794838
519 11:51:52.798578 dramc_set_vcore_voltage set vcore to 650000
520 11:51:52.798661 Read voltage for 800, 4
521 11:51:52.802121 Vio18 = 0
522 11:51:52.802202 Vcore = 650000
523 11:51:52.802267 Vdram = 0
524 11:51:52.802327 Vddq = 0
525 11:51:52.806143 Vmddr = 0
526 11:51:52.806224 dram_init: config_dvfs: 1
527 11:51:52.813449 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:51:52.817445 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:51:52.821078 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:51:52.824524 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:51:52.828514 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:51:52.832226 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:51:52.835897 MEM_TYPE=3, freq_sel=18
534 11:51:52.836022 sv_algorithm_assistance_LP4_1600
535 11:51:52.843241 ============ PULL DRAM RESETB DOWN ============
536 11:51:52.847026 ========== PULL DRAM RESETB DOWN end =========
537 11:51:52.850666 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:51:52.854265 ===================================
539 11:51:52.858228 LPDDR4 DRAM CONFIGURATION
540 11:51:52.858311 ===================================
541 11:51:52.862051 EX_ROW_EN[0] = 0x0
542 11:51:52.862134 EX_ROW_EN[1] = 0x0
543 11:51:52.865776 LP4Y_EN = 0x0
544 11:51:52.865859 WORK_FSP = 0x0
545 11:51:52.869610 WL = 0x2
546 11:51:52.869720 RL = 0x2
547 11:51:52.873043 BL = 0x2
548 11:51:52.873127 RPST = 0x0
549 11:51:52.876756 RD_PRE = 0x0
550 11:51:52.876839 WR_PRE = 0x1
551 11:51:52.880486 WR_PST = 0x0
552 11:51:52.880604 DBI_WR = 0x0
553 11:51:52.883869 DBI_RD = 0x0
554 11:51:52.883952 OTF = 0x1
555 11:51:52.887904 ===================================
556 11:51:52.891298 ===================================
557 11:51:52.891382 ANA top config
558 11:51:52.894883 ===================================
559 11:51:52.898876 DLL_ASYNC_EN = 0
560 11:51:52.898960 ALL_SLAVE_EN = 1
561 11:51:52.902285 NEW_RANK_MODE = 1
562 11:51:52.905970 DLL_IDLE_MODE = 1
563 11:51:52.909527 LP45_APHY_COMB_EN = 1
564 11:51:52.909656 TX_ODT_DIS = 1
565 11:51:52.912503 NEW_8X_MODE = 1
566 11:51:52.915966 ===================================
567 11:51:52.919553 ===================================
568 11:51:52.922727 data_rate = 1600
569 11:51:52.925980 CKR = 1
570 11:51:52.929414 DQ_P2S_RATIO = 8
571 11:51:52.932773 ===================================
572 11:51:52.932857 CA_P2S_RATIO = 8
573 11:51:52.936680 DQ_CA_OPEN = 0
574 11:51:52.939985 DQ_SEMI_OPEN = 0
575 11:51:52.943679 CA_SEMI_OPEN = 0
576 11:51:52.947177 CA_FULL_RATE = 0
577 11:51:52.947260 DQ_CKDIV4_EN = 1
578 11:51:52.950846 CA_CKDIV4_EN = 1
579 11:51:52.954443 CA_PREDIV_EN = 0
580 11:51:52.958118 PH8_DLY = 0
581 11:51:52.958201 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:51:52.961141 DQ_AAMCK_DIV = 4
583 11:51:52.964545 CA_AAMCK_DIV = 4
584 11:51:52.967828 CA_ADMCK_DIV = 4
585 11:51:52.971083 DQ_TRACK_CA_EN = 0
586 11:51:52.975157 CA_PICK = 800
587 11:51:52.975240 CA_MCKIO = 800
588 11:51:52.978641 MCKIO_SEMI = 0
589 11:51:52.982044 PLL_FREQ = 3068
590 11:51:52.985429 DQ_UI_PI_RATIO = 32
591 11:51:52.988759 CA_UI_PI_RATIO = 0
592 11:51:52.992046 ===================================
593 11:51:52.995565 ===================================
594 11:51:52.995648 memory_type:LPDDR4
595 11:51:52.998760 GP_NUM : 10
596 11:51:53.002281 SRAM_EN : 1
597 11:51:53.002364 MD32_EN : 0
598 11:51:53.006256 ===================================
599 11:51:53.009753 [ANA_INIT] >>>>>>>>>>>>>>
600 11:51:53.009873 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:51:53.013436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:51:53.017256 ===================================
603 11:51:53.020833 data_rate = 1600,PCW = 0X7600
604 11:51:53.024679 ===================================
605 11:51:53.028247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:51:53.031968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:51:53.038747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:51:53.042086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:51:53.045250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:51:53.048667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:51:53.052082 [ANA_INIT] flow start
612 11:51:53.055213 [ANA_INIT] PLL >>>>>>>>
613 11:51:53.055296 [ANA_INIT] PLL <<<<<<<<
614 11:51:53.058649 [ANA_INIT] MIDPI >>>>>>>>
615 11:51:53.062149 [ANA_INIT] MIDPI <<<<<<<<
616 11:51:53.062232 [ANA_INIT] DLL >>>>>>>>
617 11:51:53.065230 [ANA_INIT] flow end
618 11:51:53.068681 ============ LP4 DIFF to SE enter ============
619 11:51:53.075144 ============ LP4 DIFF to SE exit ============
620 11:51:53.075229 [ANA_INIT] <<<<<<<<<<<<<
621 11:51:53.078504 [Flow] Enable top DCM control >>>>>
622 11:51:53.081546 [Flow] Enable top DCM control <<<<<
623 11:51:53.084968 Enable DLL master slave shuffle
624 11:51:53.091657 ==============================================================
625 11:51:53.091741 Gating Mode config
626 11:51:53.098351 ==============================================================
627 11:51:53.101668 Config description:
628 11:51:53.108211 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:51:53.114921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:51:53.121599 SELPH_MODE 0: By rank 1: By Phase
631 11:51:53.128298 ==============================================================
632 11:51:53.128382 GAT_TRACK_EN = 1
633 11:51:53.131628 RX_GATING_MODE = 2
634 11:51:53.134967 RX_GATING_TRACK_MODE = 2
635 11:51:53.138363 SELPH_MODE = 1
636 11:51:53.141745 PICG_EARLY_EN = 1
637 11:51:53.144974 VALID_LAT_VALUE = 1
638 11:51:53.151642 ==============================================================
639 11:51:53.155203 Enter into Gating configuration >>>>
640 11:51:53.158332 Exit from Gating configuration <<<<
641 11:51:53.161419 Enter into DVFS_PRE_config >>>>>
642 11:51:53.171384 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:51:53.174768 Exit from DVFS_PRE_config <<<<<
644 11:51:53.178154 Enter into PICG configuration >>>>
645 11:51:53.181588 Exit from PICG configuration <<<<
646 11:51:53.184749 [RX_INPUT] configuration >>>>>
647 11:51:53.184831 [RX_INPUT] configuration <<<<<
648 11:51:53.191460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:51:53.198103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:51:53.201542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:51:53.208294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:51:53.214983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:51:53.221446 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:51:53.224878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:51:53.228101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:51:53.234933 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:51:53.238266 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:51:53.241607 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:51:53.245009 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:51:53.248273 ===================================
661 11:51:53.251564 LPDDR4 DRAM CONFIGURATION
662 11:51:53.254942 ===================================
663 11:51:53.258270 EX_ROW_EN[0] = 0x0
664 11:51:53.258353 EX_ROW_EN[1] = 0x0
665 11:51:53.261464 LP4Y_EN = 0x0
666 11:51:53.261547 WORK_FSP = 0x0
667 11:51:53.265101 WL = 0x2
668 11:51:53.265184 RL = 0x2
669 11:51:53.268057 BL = 0x2
670 11:51:53.268141 RPST = 0x0
671 11:51:53.271525 RD_PRE = 0x0
672 11:51:53.271608 WR_PRE = 0x1
673 11:51:53.274837 WR_PST = 0x0
674 11:51:53.274920 DBI_WR = 0x0
675 11:51:53.278336 DBI_RD = 0x0
676 11:51:53.278418 OTF = 0x1
677 11:51:53.281569 ===================================
678 11:51:53.288290 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:51:53.291699 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:51:53.294909 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:51:53.298392 ===================================
682 11:51:53.301878 LPDDR4 DRAM CONFIGURATION
683 11:51:53.304962 ===================================
684 11:51:53.308395 EX_ROW_EN[0] = 0x10
685 11:51:53.308478 EX_ROW_EN[1] = 0x0
686 11:51:53.311742 LP4Y_EN = 0x0
687 11:51:53.311824 WORK_FSP = 0x0
688 11:51:53.314865 WL = 0x2
689 11:51:53.314948 RL = 0x2
690 11:51:53.318185 BL = 0x2
691 11:51:53.318267 RPST = 0x0
692 11:51:53.321554 RD_PRE = 0x0
693 11:51:53.321637 WR_PRE = 0x1
694 11:51:53.324990 WR_PST = 0x0
695 11:51:53.325072 DBI_WR = 0x0
696 11:51:53.328249 DBI_RD = 0x0
697 11:51:53.328331 OTF = 0x1
698 11:51:53.331761 ===================================
699 11:51:53.338236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:51:53.342820 nWR fixed to 40
701 11:51:53.346212 [ModeRegInit_LP4] CH0 RK0
702 11:51:53.346295 [ModeRegInit_LP4] CH0 RK1
703 11:51:53.349432 [ModeRegInit_LP4] CH1 RK0
704 11:51:53.352940 [ModeRegInit_LP4] CH1 RK1
705 11:51:53.353023 match AC timing 12
706 11:51:53.359665 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:51:53.362681 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:51:53.365954 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:51:53.372653 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:51:53.375982 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:51:53.376065 [EMI DOE] emi_dcm 0
712 11:51:53.382511 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:51:53.382594 ==
714 11:51:53.386135 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:51:53.389758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:51:53.389841 ==
717 11:51:53.395851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:51:53.402241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:51:53.410156 [CA 0] Center 37 (7~68) winsize 62
720 11:51:53.413527 [CA 1] Center 37 (7~68) winsize 62
721 11:51:53.416752 [CA 2] Center 35 (5~66) winsize 62
722 11:51:53.420198 [CA 3] Center 35 (4~66) winsize 63
723 11:51:53.423435 [CA 4] Center 34 (4~65) winsize 62
724 11:51:53.426698 [CA 5] Center 33 (3~64) winsize 62
725 11:51:53.426781
726 11:51:53.430104 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:51:53.430187
728 11:51:53.433275 [CATrainingPosCal] consider 1 rank data
729 11:51:53.436651 u2DelayCellTimex100 = 270/100 ps
730 11:51:53.439977 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:51:53.443433 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 11:51:53.449937 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:51:53.453361 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 11:51:53.456669 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 11:51:53.460272 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:51:53.460354
737 11:51:53.463459 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:51:53.463540
739 11:51:53.466689 [CBTSetCACLKResult] CA Dly = 33
740 11:51:53.466770 CS Dly: 5 (0~36)
741 11:51:53.470004 ==
742 11:51:53.470086 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:51:53.476625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:51:53.476706 ==
745 11:51:53.480088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:51:53.486616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:51:53.496032 [CA 0] Center 37 (6~68) winsize 63
748 11:51:53.499679 [CA 1] Center 37 (6~68) winsize 63
749 11:51:53.502635 [CA 2] Center 35 (4~66) winsize 63
750 11:51:53.505932 [CA 3] Center 34 (4~65) winsize 62
751 11:51:53.509484 [CA 4] Center 33 (3~64) winsize 62
752 11:51:53.512814 [CA 5] Center 33 (3~64) winsize 62
753 11:51:53.512897
754 11:51:53.516024 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:51:53.516105
756 11:51:53.519139 [CATrainingPosCal] consider 2 rank data
757 11:51:53.522739 u2DelayCellTimex100 = 270/100 ps
758 11:51:53.526226 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:51:53.529423 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:51:53.536236 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:51:53.539324 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:51:53.542865 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 11:51:53.546329 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:51:53.546656
765 11:51:53.549537 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:51:53.549781
767 11:51:53.552949 [CBTSetCACLKResult] CA Dly = 33
768 11:51:53.553192 CS Dly: 6 (0~38)
769 11:51:53.553383
770 11:51:53.556109 ----->DramcWriteLeveling(PI) begin...
771 11:51:53.559688 ==
772 11:51:53.562965 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:51:53.566158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:51:53.566318 ==
775 11:51:53.569378 Write leveling (Byte 0): 27 => 27
776 11:51:53.572745 Write leveling (Byte 1): 27 => 27
777 11:51:53.576541 DramcWriteLeveling(PI) end<-----
778 11:51:53.576701
779 11:51:53.576895 ==
780 11:51:53.579835 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:51:53.583447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:51:53.583607 ==
783 11:51:53.587389 [Gating] SW mode calibration
784 11:51:53.594036 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:51:53.597386 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:51:53.600871 0 6 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
787 11:51:53.608361 0 6 4 | B1->B0 | 2929 2424 | 1 0 | (1 0) (1 0)
788 11:51:53.611464 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:51:53.614821 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:51:53.618160 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:51:53.624779 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:51:53.628070 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:51:53.631442 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:51:53.638195 0 7 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
795 11:51:53.641412 0 7 4 | B1->B0 | 3b3b 4343 | 0 0 | (1 1) (0 0)
796 11:51:53.644803 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:51:53.651418 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:51:53.654739 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:51:53.658041 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:51:53.664829 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:51:53.668201 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:51:53.671602 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 11:51:53.678211 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:51:53.681536 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:51:53.684809 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:51:53.688153 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:51:53.694748 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:51:53.698425 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:51:53.701450 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:51:53.708203 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:51:53.711626 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:51:53.714784 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:51:53.721437 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:51:53.724707 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:51:53.728166 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:51:53.735280 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:51:53.738143 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 11:51:53.741715 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
819 11:51:53.748135 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 11:51:53.748218 Total UI for P1: 0, mck2ui 16
821 11:51:53.754929 best dqsien dly found for B0: ( 0, 10, 2)
822 11:51:53.755012 Total UI for P1: 0, mck2ui 16
823 11:51:53.758250 best dqsien dly found for B1: ( 0, 10, 0)
824 11:51:53.764873 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 11:51:53.768072 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 11:51:53.768213
827 11:51:53.771422 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 11:51:53.774976 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 11:51:53.778155 [Gating] SW calibration Done
830 11:51:53.778237 ==
831 11:51:53.781491 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:51:53.784937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:51:53.785019 ==
834 11:51:53.788420 RX Vref Scan: 0
835 11:51:53.788533
836 11:51:53.788601 RX Vref 0 -> 0, step: 1
837 11:51:53.788662
838 11:51:53.791512 RX Delay -130 -> 252, step: 16
839 11:51:53.794934 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 11:51:53.801500 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:51:53.804973 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 11:51:53.808284 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:51:53.811679 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 11:51:53.814914 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:51:53.821487 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
846 11:51:53.825113 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
847 11:51:53.828329 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 11:51:53.831605 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
849 11:51:53.834923 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:51:53.841640 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:51:53.844853 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 11:51:53.848354 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 11:51:53.851654 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:51:53.854932 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:51:53.855015 ==
856 11:51:53.858197 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:51:53.865045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:51:53.865127 ==
859 11:51:53.865193 DQS Delay:
860 11:51:53.868400 DQS0 = 0, DQS1 = 0
861 11:51:53.868484 DQM Delay:
862 11:51:53.868570 DQM0 = 86, DQM1 = 75
863 11:51:53.871562 DQ Delay:
864 11:51:53.874854 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
865 11:51:53.878359 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
866 11:51:53.881593 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
867 11:51:53.885048 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 11:51:53.885130
869 11:51:53.885195
870 11:51:53.885255 ==
871 11:51:53.888330 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:51:53.891920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:51:53.892003 ==
874 11:51:53.892069
875 11:51:53.892129
876 11:51:53.894979 TX Vref Scan disable
877 11:51:53.895061 == TX Byte 0 ==
878 11:51:53.901533 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 11:51:53.905594 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 11:51:53.905677 == TX Byte 1 ==
881 11:51:53.911737 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 11:51:53.914952 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 11:51:53.915035 ==
884 11:51:53.918468 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:51:53.921491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:51:53.921574 ==
887 11:51:53.935515 TX Vref=22, minBit 0, minWin=27, winSum=441
888 11:51:53.938851 TX Vref=24, minBit 0, minWin=27, winSum=440
889 11:51:53.943121 TX Vref=26, minBit 2, minWin=27, winSum=446
890 11:51:53.945677 TX Vref=28, minBit 11, minWin=27, winSum=452
891 11:51:53.948865 TX Vref=30, minBit 1, minWin=28, winSum=449
892 11:51:53.955580 TX Vref=32, minBit 0, minWin=27, winSum=447
893 11:51:53.958837 [TxChooseVref] Worse bit 1, Min win 28, Win sum 449, Final Vref 30
894 11:51:53.958919
895 11:51:53.962362 Final TX Range 1 Vref 30
896 11:51:53.962446
897 11:51:53.962511 ==
898 11:51:53.965770 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:51:53.969011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:51:53.969094 ==
901 11:51:53.969159
902 11:51:53.972399
903 11:51:53.972514 TX Vref Scan disable
904 11:51:53.975836 == TX Byte 0 ==
905 11:51:53.978963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 11:51:53.982264 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 11:51:53.985707 == TX Byte 1 ==
908 11:51:53.989048 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
909 11:51:53.992395 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
910 11:51:53.992504
911 11:51:53.995755 [DATLAT]
912 11:51:53.995837 Freq=800, CH0 RK0
913 11:51:53.995902
914 11:51:53.998981 DATLAT Default: 0xa
915 11:51:53.999064 0, 0xFFFF, sum = 0
916 11:51:54.002616 1, 0xFFFF, sum = 0
917 11:51:54.002703 2, 0xFFFF, sum = 0
918 11:51:54.005661 3, 0xFFFF, sum = 0
919 11:51:54.005744 4, 0xFFFF, sum = 0
920 11:51:54.008966 5, 0xFFFF, sum = 0
921 11:51:54.009050 6, 0xFFFF, sum = 0
922 11:51:54.012267 7, 0xFFFF, sum = 0
923 11:51:54.012378 8, 0x0, sum = 1
924 11:51:54.015733 9, 0x0, sum = 2
925 11:51:54.015816 10, 0x0, sum = 3
926 11:51:54.019096 11, 0x0, sum = 4
927 11:51:54.019180 best_step = 9
928 11:51:54.019245
929 11:51:54.019306 ==
930 11:51:54.022317 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:51:54.029149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:51:54.029232 ==
933 11:51:54.029297 RX Vref Scan: 1
934 11:51:54.029358
935 11:51:54.032178 Set Vref Range= 32 -> 127
936 11:51:54.032260
937 11:51:54.035533 RX Vref 32 -> 127, step: 1
938 11:51:54.035615
939 11:51:54.035681 RX Delay -95 -> 252, step: 8
940 11:51:54.035742
941 11:51:54.038901 Set Vref, RX VrefLevel [Byte0]: 32
942 11:51:54.042182 [Byte1]: 32
943 11:51:54.046227
944 11:51:54.046308 Set Vref, RX VrefLevel [Byte0]: 33
945 11:51:54.049575 [Byte1]: 33
946 11:51:54.053991
947 11:51:54.054071 Set Vref, RX VrefLevel [Byte0]: 34
948 11:51:54.057147 [Byte1]: 34
949 11:51:54.061946
950 11:51:54.062026 Set Vref, RX VrefLevel [Byte0]: 35
951 11:51:54.064880 [Byte1]: 35
952 11:51:54.069446
953 11:51:54.069527 Set Vref, RX VrefLevel [Byte0]: 36
954 11:51:54.072415 [Byte1]: 36
955 11:51:54.076729
956 11:51:54.076809 Set Vref, RX VrefLevel [Byte0]: 37
957 11:51:54.079843 [Byte1]: 37
958 11:51:54.084453
959 11:51:54.084584 Set Vref, RX VrefLevel [Byte0]: 38
960 11:51:54.087624 [Byte1]: 38
961 11:51:54.091744
962 11:51:54.091824 Set Vref, RX VrefLevel [Byte0]: 39
963 11:51:54.095331 [Byte1]: 39
964 11:51:54.099409
965 11:51:54.099488 Set Vref, RX VrefLevel [Byte0]: 40
966 11:51:54.102697 [Byte1]: 40
967 11:51:54.107027
968 11:51:54.107107 Set Vref, RX VrefLevel [Byte0]: 41
969 11:51:54.110514 [Byte1]: 41
970 11:51:54.114718
971 11:51:54.114799 Set Vref, RX VrefLevel [Byte0]: 42
972 11:51:54.118250 [Byte1]: 42
973 11:51:54.122446
974 11:51:54.122525 Set Vref, RX VrefLevel [Byte0]: 43
975 11:51:54.125681 [Byte1]: 43
976 11:51:54.129767
977 11:51:54.129847 Set Vref, RX VrefLevel [Byte0]: 44
978 11:51:54.133025 [Byte1]: 44
979 11:51:54.137386
980 11:51:54.137466 Set Vref, RX VrefLevel [Byte0]: 45
981 11:51:54.140626 [Byte1]: 45
982 11:51:54.145096
983 11:51:54.145176 Set Vref, RX VrefLevel [Byte0]: 46
984 11:51:54.148270 [Byte1]: 46
985 11:51:54.152742
986 11:51:54.152821 Set Vref, RX VrefLevel [Byte0]: 47
987 11:51:54.156002 [Byte1]: 47
988 11:51:54.160483
989 11:51:54.160575 Set Vref, RX VrefLevel [Byte0]: 48
990 11:51:54.163703 [Byte1]: 48
991 11:51:54.167682
992 11:51:54.167763 Set Vref, RX VrefLevel [Byte0]: 49
993 11:51:54.171041 [Byte1]: 49
994 11:51:54.175503
995 11:51:54.175585 Set Vref, RX VrefLevel [Byte0]: 50
996 11:51:54.179021 [Byte1]: 50
997 11:51:54.182978
998 11:51:54.183060 Set Vref, RX VrefLevel [Byte0]: 51
999 11:51:54.186501 [Byte1]: 51
1000 11:51:54.190608
1001 11:51:54.190689 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:51:54.193933 [Byte1]: 52
1003 11:51:54.198570
1004 11:51:54.198650 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:51:54.201687 [Byte1]: 53
1006 11:51:54.205963
1007 11:51:54.206045 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:51:54.208957 [Byte1]: 54
1009 11:51:54.213375
1010 11:51:54.213485 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:51:54.216740 [Byte1]: 55
1012 11:51:54.220980
1013 11:51:54.221062 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:51:54.224435 [Byte1]: 56
1015 11:51:54.228658
1016 11:51:54.228740 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:51:54.231845 [Byte1]: 57
1018 11:51:54.236087
1019 11:51:54.236168 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:51:54.239574 [Byte1]: 58
1021 11:51:54.244109
1022 11:51:54.244190 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:51:54.247506 [Byte1]: 59
1024 11:51:54.251922
1025 11:51:54.252023 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:51:54.255120 [Byte1]: 60
1027 11:51:54.259134
1028 11:51:54.259218 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:51:54.262543 [Byte1]: 61
1030 11:51:54.266958
1031 11:51:54.267038 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:51:54.270338 [Byte1]: 62
1033 11:51:54.274219
1034 11:51:54.274298 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:51:54.277672 [Byte1]: 63
1036 11:51:54.281588
1037 11:51:54.281667 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:51:54.285190 [Byte1]: 64
1039 11:51:54.289519
1040 11:51:54.289613 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:51:54.292670 [Byte1]: 65
1042 11:51:54.296926
1043 11:51:54.297005 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:51:54.300186 [Byte1]: 66
1045 11:51:54.304401
1046 11:51:54.304544 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:51:54.307673 [Byte1]: 67
1048 11:51:54.312066
1049 11:51:54.312145 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:51:54.315374 [Byte1]: 68
1051 11:51:54.319606
1052 11:51:54.319685 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:51:54.323395 [Byte1]: 69
1054 11:51:54.327358
1055 11:51:54.327452 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:51:54.330538 [Byte1]: 70
1057 11:51:54.334843
1058 11:51:54.334964 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:51:54.338235 [Byte1]: 71
1060 11:51:54.342394
1061 11:51:54.342473 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:51:54.345708 [Byte1]: 72
1063 11:51:54.350057
1064 11:51:54.350136 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:51:54.353515 [Byte1]: 73
1066 11:51:54.357602
1067 11:51:54.357682 Set Vref, RX VrefLevel [Byte0]: 74
1068 11:51:54.360977 [Byte1]: 74
1069 11:51:54.365111
1070 11:51:54.365191 Final RX Vref Byte 0 = 53 to rank0
1071 11:51:54.368722 Final RX Vref Byte 1 = 56 to rank0
1072 11:51:54.372306 Final RX Vref Byte 0 = 53 to rank1
1073 11:51:54.375120 Final RX Vref Byte 1 = 56 to rank1==
1074 11:51:54.378595 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 11:51:54.385223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 11:51:54.385304 ==
1077 11:51:54.385369 DQS Delay:
1078 11:51:54.385428 DQS0 = 0, DQS1 = 0
1079 11:51:54.388632 DQM Delay:
1080 11:51:54.388712 DQM0 = 83, DQM1 = 73
1081 11:51:54.392036 DQ Delay:
1082 11:51:54.395344 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 11:51:54.395425 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 11:51:54.398759 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1085 11:51:54.401830 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1086 11:51:54.405628
1087 11:51:54.405708
1088 11:51:54.412218 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1089 11:51:54.415167 CH0 RK0: MR19=606, MR18=3838
1090 11:51:54.421957 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1091 11:51:54.422039
1092 11:51:54.425133 ----->DramcWriteLeveling(PI) begin...
1093 11:51:54.425216 ==
1094 11:51:54.428497 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 11:51:54.431874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 11:51:54.431954 ==
1097 11:51:54.435284 Write leveling (Byte 0): 29 => 29
1098 11:51:54.438565 Write leveling (Byte 1): 27 => 27
1099 11:51:54.441943 DramcWriteLeveling(PI) end<-----
1100 11:51:54.442023
1101 11:51:54.442087 ==
1102 11:51:54.445407 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 11:51:54.448630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 11:51:54.448711 ==
1105 11:51:54.451945 [Gating] SW mode calibration
1106 11:51:54.458601 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 11:51:54.465269 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 11:51:54.468660 0 6 0 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 1)
1109 11:51:54.471929 0 6 4 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1110 11:51:54.478521 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 11:51:54.481871 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 11:51:54.485236 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 11:51:54.492026 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 11:51:54.495239 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 11:51:54.498503 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 11:51:54.505179 0 7 0 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
1117 11:51:54.508518 0 7 4 | B1->B0 | 4444 4545 | 0 0 | (1 1) (0 0)
1118 11:51:54.511953 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 11:51:54.518532 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 11:51:54.522009 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 11:51:54.525536 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 11:51:54.528799 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 11:51:54.535301 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 11:51:54.538558 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1125 11:51:54.542117 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 11:51:54.548412 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 11:51:54.552022 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 11:51:54.555454 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 11:51:54.561833 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:51:54.565509 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:51:54.568468 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:51:54.575412 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:51:54.578840 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:51:54.582182 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:51:54.588566 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:51:54.591824 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:51:54.595172 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 11:51:54.601875 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 11:51:54.605319 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 11:51:54.608676 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1141 11:51:54.611954 Total UI for P1: 0, mck2ui 16
1142 11:51:54.615153 best dqsien dly found for B0: ( 0, 9, 30)
1143 11:51:54.618461 Total UI for P1: 0, mck2ui 16
1144 11:51:54.621848 best dqsien dly found for B1: ( 0, 9, 30)
1145 11:51:54.625129 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1146 11:51:54.628690 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1147 11:51:54.628769
1148 11:51:54.631905 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1149 11:51:54.638486 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1150 11:51:54.638565 [Gating] SW calibration Done
1151 11:51:54.638629 ==
1152 11:51:54.641810 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 11:51:54.648409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1154 11:51:54.648540 ==
1155 11:51:54.648633 RX Vref Scan: 0
1156 11:51:54.648693
1157 11:51:54.652040 RX Vref 0 -> 0, step: 1
1158 11:51:54.652118
1159 11:51:54.695996 RX Delay -130 -> 252, step: 16
1160 11:51:54.696124 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1161 11:51:54.696386 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1162 11:51:54.696688 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1163 11:51:54.696964 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1164 11:51:54.697031 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1165 11:51:54.697101 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1166 11:51:54.697529 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1167 11:51:54.697609 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1168 11:51:54.697875 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1169 11:51:54.698176 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1170 11:51:54.730405 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1171 11:51:54.730488 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1172 11:51:54.730753 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1173 11:51:54.731015 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1174 11:51:54.731130 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1175 11:51:54.731212 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1176 11:51:54.731269 ==
1177 11:51:54.731563 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 11:51:54.731971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1179 11:51:54.732052 ==
1180 11:51:54.732116 DQS Delay:
1181 11:51:54.732174 DQS0 = 0, DQS1 = 0
1182 11:51:54.732233 DQM Delay:
1183 11:51:54.734707 DQM0 = 82, DQM1 = 74
1184 11:51:54.734786 DQ Delay:
1185 11:51:54.734849 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1186 11:51:54.738114 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1187 11:51:54.741291 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1188 11:51:54.744802 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1189 11:51:54.744883
1190 11:51:54.748269
1191 11:51:54.748348 ==
1192 11:51:54.751386 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 11:51:54.754653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1194 11:51:54.754733 ==
1195 11:51:54.754797
1196 11:51:54.754856
1197 11:51:54.758003 TX Vref Scan disable
1198 11:51:54.758083 == TX Byte 0 ==
1199 11:51:54.764464 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1200 11:51:54.768085 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1201 11:51:54.768166 == TX Byte 1 ==
1202 11:51:54.774537 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1203 11:51:54.777877 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1204 11:51:54.777957 ==
1205 11:51:54.781245 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:51:54.784367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1207 11:51:54.784448 ==
1208 11:51:54.798257 TX Vref=22, minBit 0, minWin=27, winSum=440
1209 11:51:54.801499 TX Vref=24, minBit 0, minWin=27, winSum=445
1210 11:51:54.804895 TX Vref=26, minBit 14, minWin=27, winSum=454
1211 11:51:54.807977 TX Vref=28, minBit 0, minWin=28, winSum=454
1212 11:51:54.811356 TX Vref=30, minBit 2, minWin=28, winSum=456
1213 11:51:54.818037 TX Vref=32, minBit 0, minWin=28, winSum=455
1214 11:51:54.821739 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1215 11:51:54.821819
1216 11:51:54.825414 Final TX Range 1 Vref 30
1217 11:51:54.825495
1218 11:51:54.825558 ==
1219 11:51:54.829293 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 11:51:54.833150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1221 11:51:54.833277 ==
1222 11:51:54.833356
1223 11:51:54.833445
1224 11:51:54.836810 TX Vref Scan disable
1225 11:51:54.836890 == TX Byte 0 ==
1226 11:51:54.843412 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1227 11:51:54.846666 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1228 11:51:54.846746 == TX Byte 1 ==
1229 11:51:54.850754 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1230 11:51:54.857161 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1231 11:51:54.857244
1232 11:51:54.857308 [DATLAT]
1233 11:51:54.860476 Freq=800, CH0 RK1
1234 11:51:54.860580
1235 11:51:54.860673 DATLAT Default: 0x9
1236 11:51:54.863837 0, 0xFFFF, sum = 0
1237 11:51:54.863919 1, 0xFFFF, sum = 0
1238 11:51:54.867211 2, 0xFFFF, sum = 0
1239 11:51:54.867294 3, 0xFFFF, sum = 0
1240 11:51:54.870479 4, 0xFFFF, sum = 0
1241 11:51:54.870562 5, 0xFFFF, sum = 0
1242 11:51:54.873968 6, 0xFFFF, sum = 0
1243 11:51:54.874051 7, 0xFFFF, sum = 0
1244 11:51:54.877613 8, 0x0, sum = 1
1245 11:51:54.877695 9, 0x0, sum = 2
1246 11:51:54.880697 10, 0x0, sum = 3
1247 11:51:54.880780 11, 0x0, sum = 4
1248 11:51:54.880845 best_step = 9
1249 11:51:54.883876
1250 11:51:54.883957 ==
1251 11:51:54.887159 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 11:51:54.890685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1253 11:51:54.890767 ==
1254 11:51:54.890831 RX Vref Scan: 0
1255 11:51:54.890891
1256 11:51:54.894087 RX Vref 0 -> 0, step: 1
1257 11:51:54.894169
1258 11:51:54.897178 RX Delay -111 -> 252, step: 8
1259 11:51:54.900450 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1260 11:51:54.907229 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1261 11:51:54.910430 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1262 11:51:54.913888 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1263 11:51:54.917266 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1264 11:51:54.920463 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1265 11:51:54.927245 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1266 11:51:54.930625 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1267 11:51:54.933938 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1268 11:51:54.937185 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1269 11:51:54.940411 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1270 11:51:54.947541 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1271 11:51:54.950433 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1272 11:51:54.953913 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1273 11:51:54.957389 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1274 11:51:54.960621 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1275 11:51:54.963781 ==
1276 11:51:54.963875 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 11:51:54.970626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1278 11:51:54.970706 ==
1279 11:51:54.970770 DQS Delay:
1280 11:51:54.973961 DQS0 = 0, DQS1 = 0
1281 11:51:54.974041 DQM Delay:
1282 11:51:54.977037 DQM0 = 86, DQM1 = 74
1283 11:51:54.977117 DQ Delay:
1284 11:51:54.980627 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1285 11:51:54.983800 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1286 11:51:54.987517 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1287 11:51:54.990713 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1288 11:51:54.990792
1289 11:51:54.990856
1290 11:51:54.997326 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1291 11:51:55.000722 CH0 RK1: MR19=606, MR18=4141
1292 11:51:55.007314 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1293 11:51:55.010495 [RxdqsGatingPostProcess] freq 800
1294 11:51:55.014015 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1295 11:51:55.017366 Pre-setting of DQS Precalculation
1296 11:51:55.024031 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1297 11:51:55.024111 ==
1298 11:51:55.027338 Dram Type= 6, Freq= 0, CH_1, rank 0
1299 11:51:55.030568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1300 11:51:55.030647 ==
1301 11:51:55.037232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1302 11:51:55.040608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1303 11:51:55.050978 [CA 0] Center 36 (6~67) winsize 62
1304 11:51:55.054342 [CA 1] Center 36 (5~67) winsize 63
1305 11:51:55.057629 [CA 2] Center 34 (4~65) winsize 62
1306 11:51:55.061066 [CA 3] Center 34 (4~65) winsize 62
1307 11:51:55.064334 [CA 4] Center 33 (2~64) winsize 63
1308 11:51:55.067495 [CA 5] Center 33 (3~64) winsize 62
1309 11:51:55.067576
1310 11:51:55.071446 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1311 11:51:55.071527
1312 11:51:55.074261 [CATrainingPosCal] consider 1 rank data
1313 11:51:55.077711 u2DelayCellTimex100 = 270/100 ps
1314 11:51:55.081269 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1315 11:51:55.084335 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1316 11:51:55.087616 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1317 11:51:55.094358 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 11:51:55.097519 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1319 11:51:55.101031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1320 11:51:55.101112
1321 11:51:55.104465 CA PerBit enable=1, Macro0, CA PI delay=33
1322 11:51:55.104553
1323 11:51:55.107825 [CBTSetCACLKResult] CA Dly = 33
1324 11:51:55.107904 CS Dly: 4 (0~35)
1325 11:51:55.107968 ==
1326 11:51:55.110941 Dram Type= 6, Freq= 0, CH_1, rank 1
1327 11:51:55.117805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1328 11:51:55.117886 ==
1329 11:51:55.120942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1330 11:51:55.127405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1331 11:51:55.136498 [CA 0] Center 36 (6~67) winsize 62
1332 11:51:55.140006 [CA 1] Center 36 (5~67) winsize 63
1333 11:51:55.143214 [CA 2] Center 34 (4~65) winsize 62
1334 11:51:55.146470 [CA 3] Center 34 (4~64) winsize 61
1335 11:51:55.150044 [CA 4] Center 33 (3~63) winsize 61
1336 11:51:55.153295 [CA 5] Center 33 (3~63) winsize 61
1337 11:51:55.153376
1338 11:51:55.156833 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1339 11:51:55.156913
1340 11:51:55.159651 [CATrainingPosCal] consider 2 rank data
1341 11:51:55.163065 u2DelayCellTimex100 = 270/100 ps
1342 11:51:55.166373 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1343 11:51:55.173017 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1344 11:51:55.176431 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1345 11:51:55.179673 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1346 11:51:55.183172 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1347 11:51:55.186414 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1348 11:51:55.186494
1349 11:51:55.189785 CA PerBit enable=1, Macro0, CA PI delay=33
1350 11:51:55.189865
1351 11:51:55.192814 [CBTSetCACLKResult] CA Dly = 33
1352 11:51:55.196077 CS Dly: 4 (0~35)
1353 11:51:55.196156
1354 11:51:55.199359 ----->DramcWriteLeveling(PI) begin...
1355 11:51:55.199441 ==
1356 11:51:55.202953 Dram Type= 6, Freq= 0, CH_1, rank 0
1357 11:51:55.206128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1358 11:51:55.206209 ==
1359 11:51:55.209699 Write leveling (Byte 0): 27 => 27
1360 11:51:55.213156 Write leveling (Byte 1): 24 => 24
1361 11:51:55.215994 DramcWriteLeveling(PI) end<-----
1362 11:51:55.216073
1363 11:51:55.216137 ==
1364 11:51:55.219571 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 11:51:55.222820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 11:51:55.222901 ==
1367 11:51:55.226075 [Gating] SW mode calibration
1368 11:51:55.232759 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1369 11:51:55.239687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1370 11:51:55.243053 0 6 0 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
1371 11:51:55.246291 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 11:51:55.249800 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 11:51:55.256259 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 11:51:55.259566 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 11:51:55.262861 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 11:51:55.269527 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 11:51:55.272881 0 6 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (1 1)
1378 11:51:55.276597 0 7 0 | B1->B0 | 3232 4444 | 0 0 | (1 1) (0 0)
1379 11:51:55.282920 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1380 11:51:55.286188 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 11:51:55.289540 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 11:51:55.296250 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 11:51:55.299583 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 11:51:55.303226 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 11:51:55.309633 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1386 11:51:55.313130 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1387 11:51:55.316275 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 11:51:55.323023 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 11:51:55.326376 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 11:51:55.329581 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 11:51:55.336199 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:51:55.339435 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:51:55.342657 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:51:55.349203 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:51:55.352622 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:51:55.355972 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:51:55.362561 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:51:55.365999 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:51:55.369457 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:51:55.372467 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 11:51:55.379300 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 11:51:55.382635 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1403 11:51:55.385928 Total UI for P1: 0, mck2ui 16
1404 11:51:55.389329 best dqsien dly found for B0: ( 0, 9, 30)
1405 11:51:55.392580 Total UI for P1: 0, mck2ui 16
1406 11:51:55.396092 best dqsien dly found for B1: ( 0, 9, 30)
1407 11:51:55.399364 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1408 11:51:55.402975 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1409 11:51:55.403056
1410 11:51:55.406198 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1411 11:51:55.409534 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1412 11:51:55.413049 [Gating] SW calibration Done
1413 11:51:55.413131 ==
1414 11:51:55.416009 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 11:51:55.422802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1416 11:51:55.422918 ==
1417 11:51:55.423069 RX Vref Scan: 0
1418 11:51:55.423147
1419 11:51:55.426009 RX Vref 0 -> 0, step: 1
1420 11:51:55.426090
1421 11:51:55.429330 RX Delay -130 -> 252, step: 16
1422 11:51:55.432627 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1423 11:51:55.436104 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1424 11:51:55.439490 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1425 11:51:55.442752 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1426 11:51:55.449278 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1427 11:51:55.453042 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1428 11:51:55.456066 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1429 11:51:55.459318 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1430 11:51:55.462862 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1431 11:51:55.469229 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1432 11:51:55.472958 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1433 11:51:55.476008 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1434 11:51:55.479552 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1435 11:51:55.482710 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1436 11:51:55.489845 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1437 11:51:55.493474 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1438 11:51:55.493556 ==
1439 11:51:55.497163 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:51:55.500699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1441 11:51:55.500782 ==
1442 11:51:55.500847 DQS Delay:
1443 11:51:55.504341 DQS0 = 0, DQS1 = 0
1444 11:51:55.504423 DQM Delay:
1445 11:51:55.504488 DQM0 = 80, DQM1 = 70
1446 11:51:55.507924 DQ Delay:
1447 11:51:55.511866 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1448 11:51:55.511948 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1449 11:51:55.515181 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1450 11:51:55.518965 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1451 11:51:55.519049
1452 11:51:55.519113
1453 11:51:55.522394 ==
1454 11:51:55.522477 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 11:51:55.529072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1456 11:51:55.529165 ==
1457 11:51:55.529233
1458 11:51:55.529294
1459 11:51:55.529353 TX Vref Scan disable
1460 11:51:55.532890 == TX Byte 0 ==
1461 11:51:55.536015 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1462 11:51:55.539486 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1463 11:51:55.542747 == TX Byte 1 ==
1464 11:51:55.546085 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1465 11:51:55.552823 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1466 11:51:55.552908 ==
1467 11:51:55.556017 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 11:51:55.559481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1469 11:51:55.559565 ==
1470 11:51:55.572031 TX Vref=22, minBit 3, minWin=27, winSum=448
1471 11:51:55.575218 TX Vref=24, minBit 3, minWin=27, winSum=449
1472 11:51:55.578846 TX Vref=26, minBit 0, minWin=28, winSum=452
1473 11:51:55.582048 TX Vref=28, minBit 0, minWin=28, winSum=455
1474 11:51:55.585268 TX Vref=30, minBit 0, minWin=28, winSum=458
1475 11:51:55.588463 TX Vref=32, minBit 0, minWin=28, winSum=457
1476 11:51:55.595186 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1477 11:51:55.595277
1478 11:51:55.598698 Final TX Range 1 Vref 30
1479 11:51:55.598781
1480 11:51:55.598846 ==
1481 11:51:55.601912 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 11:51:55.605328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 11:51:55.605411 ==
1484 11:51:55.605476
1485 11:51:55.608634
1486 11:51:55.608716 TX Vref Scan disable
1487 11:51:55.611764 == TX Byte 0 ==
1488 11:51:55.615240 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1489 11:51:55.618425 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1490 11:51:55.621756 == TX Byte 1 ==
1491 11:51:55.625229 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1492 11:51:55.628413 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1493 11:51:55.631909
1494 11:51:55.631995 [DATLAT]
1495 11:51:55.632061 Freq=800, CH1 RK0
1496 11:51:55.632122
1497 11:51:55.635287 DATLAT Default: 0xa
1498 11:51:55.635370 0, 0xFFFF, sum = 0
1499 11:51:55.638535 1, 0xFFFF, sum = 0
1500 11:51:55.638618 2, 0xFFFF, sum = 0
1501 11:51:55.642087 3, 0xFFFF, sum = 0
1502 11:51:55.642171 4, 0xFFFF, sum = 0
1503 11:51:55.645164 5, 0xFFFF, sum = 0
1504 11:51:55.645269 6, 0xFFFF, sum = 0
1505 11:51:55.648993 7, 0xFFFF, sum = 0
1506 11:51:55.649078 8, 0x0, sum = 1
1507 11:51:55.651906 9, 0x0, sum = 2
1508 11:51:55.651991 10, 0x0, sum = 3
1509 11:51:55.655124 11, 0x0, sum = 4
1510 11:51:55.655209 best_step = 9
1511 11:51:55.655380
1512 11:51:55.655442 ==
1513 11:51:55.658819 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 11:51:55.665136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1515 11:51:55.665239 ==
1516 11:51:55.665385 RX Vref Scan: 1
1517 11:51:55.665447
1518 11:51:55.668655 Set Vref Range= 32 -> 127
1519 11:51:55.668749
1520 11:51:55.671959 RX Vref 32 -> 127, step: 1
1521 11:51:55.672042
1522 11:51:55.672106 RX Delay -111 -> 252, step: 8
1523 11:51:55.672166
1524 11:51:55.675366 Set Vref, RX VrefLevel [Byte0]: 32
1525 11:51:55.678444 [Byte1]: 32
1526 11:51:55.682843
1527 11:51:55.682923 Set Vref, RX VrefLevel [Byte0]: 33
1528 11:51:55.685943 [Byte1]: 33
1529 11:51:55.690436
1530 11:51:55.690517 Set Vref, RX VrefLevel [Byte0]: 34
1531 11:51:55.693681 [Byte1]: 34
1532 11:51:55.698081
1533 11:51:55.698162 Set Vref, RX VrefLevel [Byte0]: 35
1534 11:51:55.701409 [Byte1]: 35
1535 11:51:55.705790
1536 11:51:55.705873 Set Vref, RX VrefLevel [Byte0]: 36
1537 11:51:55.709188 [Byte1]: 36
1538 11:51:55.713328
1539 11:51:55.713411 Set Vref, RX VrefLevel [Byte0]: 37
1540 11:51:55.716630 [Byte1]: 37
1541 11:51:55.721066
1542 11:51:55.721152 Set Vref, RX VrefLevel [Byte0]: 38
1543 11:51:55.724138 [Byte1]: 38
1544 11:51:55.728470
1545 11:51:55.728622 Set Vref, RX VrefLevel [Byte0]: 39
1546 11:51:55.731870 [Byte1]: 39
1547 11:51:55.736352
1548 11:51:55.736436 Set Vref, RX VrefLevel [Byte0]: 40
1549 11:51:55.739909 [Byte1]: 40
1550 11:51:55.744010
1551 11:51:55.744093 Set Vref, RX VrefLevel [Byte0]: 41
1552 11:51:55.747249 [Byte1]: 41
1553 11:51:55.751494
1554 11:51:55.751578 Set Vref, RX VrefLevel [Byte0]: 42
1555 11:51:55.754738 [Byte1]: 42
1556 11:51:55.759295
1557 11:51:55.759381 Set Vref, RX VrefLevel [Byte0]: 43
1558 11:51:55.762359 [Byte1]: 43
1559 11:51:55.766911
1560 11:51:55.766997 Set Vref, RX VrefLevel [Byte0]: 44
1561 11:51:55.770263 [Byte1]: 44
1562 11:51:55.774486
1563 11:51:55.774578 Set Vref, RX VrefLevel [Byte0]: 45
1564 11:51:55.777766 [Byte1]: 45
1565 11:51:55.782113
1566 11:51:55.782199 Set Vref, RX VrefLevel [Byte0]: 46
1567 11:51:55.785370 [Byte1]: 46
1568 11:51:55.789787
1569 11:51:55.789872 Set Vref, RX VrefLevel [Byte0]: 47
1570 11:51:55.793061 [Byte1]: 47
1571 11:51:55.797427
1572 11:51:55.797511 Set Vref, RX VrefLevel [Byte0]: 48
1573 11:51:55.801095 [Byte1]: 48
1574 11:51:55.805187
1575 11:51:55.805271 Set Vref, RX VrefLevel [Byte0]: 49
1576 11:51:55.808429 [Byte1]: 49
1577 11:51:55.812716
1578 11:51:55.812800 Set Vref, RX VrefLevel [Byte0]: 50
1579 11:51:55.816198 [Byte1]: 50
1580 11:51:55.820330
1581 11:51:55.820416 Set Vref, RX VrefLevel [Byte0]: 51
1582 11:51:55.823998 [Byte1]: 51
1583 11:51:55.828111
1584 11:51:55.828197 Set Vref, RX VrefLevel [Byte0]: 52
1585 11:51:55.831208 [Byte1]: 52
1586 11:51:55.835564
1587 11:51:55.835651 Set Vref, RX VrefLevel [Byte0]: 53
1588 11:51:55.839200 [Byte1]: 53
1589 11:51:55.843278
1590 11:51:55.843366 Set Vref, RX VrefLevel [Byte0]: 54
1591 11:51:55.846621 [Byte1]: 54
1592 11:51:55.850985
1593 11:51:55.851071 Set Vref, RX VrefLevel [Byte0]: 55
1594 11:51:55.854343 [Byte1]: 55
1595 11:51:55.858518
1596 11:51:55.858603 Set Vref, RX VrefLevel [Byte0]: 56
1597 11:51:55.861915 [Byte1]: 56
1598 11:51:55.866613
1599 11:51:55.866697 Set Vref, RX VrefLevel [Byte0]: 57
1600 11:51:55.869650 [Byte1]: 57
1601 11:51:55.873879
1602 11:51:55.873966 Set Vref, RX VrefLevel [Byte0]: 58
1603 11:51:55.877235 [Byte1]: 58
1604 11:51:55.881519
1605 11:51:55.881604 Set Vref, RX VrefLevel [Byte0]: 59
1606 11:51:55.884853 [Byte1]: 59
1607 11:51:55.889440
1608 11:51:55.889524 Set Vref, RX VrefLevel [Byte0]: 60
1609 11:51:55.892498 [Byte1]: 60
1610 11:51:55.896856
1611 11:51:55.896942 Set Vref, RX VrefLevel [Byte0]: 61
1612 11:51:55.900268 [Byte1]: 61
1613 11:51:55.904417
1614 11:51:55.904499 Set Vref, RX VrefLevel [Byte0]: 62
1615 11:51:55.907658 [Byte1]: 62
1616 11:51:55.912130
1617 11:51:55.912215 Set Vref, RX VrefLevel [Byte0]: 63
1618 11:51:55.915332 [Byte1]: 63
1619 11:51:55.919820
1620 11:51:55.919908 Set Vref, RX VrefLevel [Byte0]: 64
1621 11:51:55.923052 [Byte1]: 64
1622 11:51:55.927468
1623 11:51:55.927552 Set Vref, RX VrefLevel [Byte0]: 65
1624 11:51:55.930705 [Byte1]: 65
1625 11:51:55.935109
1626 11:51:55.935219 Set Vref, RX VrefLevel [Byte0]: 66
1627 11:51:55.938353 [Byte1]: 66
1628 11:51:55.942659
1629 11:51:55.942743 Set Vref, RX VrefLevel [Byte0]: 67
1630 11:51:55.946062 [Byte1]: 67
1631 11:51:55.950350
1632 11:51:55.950434 Set Vref, RX VrefLevel [Byte0]: 68
1633 11:51:55.953752 [Byte1]: 68
1634 11:51:55.958004
1635 11:51:55.958096 Set Vref, RX VrefLevel [Byte0]: 69
1636 11:51:55.961674 [Byte1]: 69
1637 11:51:55.965563
1638 11:51:55.965649 Set Vref, RX VrefLevel [Byte0]: 70
1639 11:51:55.968946 [Byte1]: 70
1640 11:51:55.973353
1641 11:51:55.973441 Set Vref, RX VrefLevel [Byte0]: 71
1642 11:51:55.976488 [Byte1]: 71
1643 11:51:55.980856
1644 11:51:55.980950 Set Vref, RX VrefLevel [Byte0]: 72
1645 11:51:55.984196 [Byte1]: 72
1646 11:51:55.988481
1647 11:51:55.988577 Set Vref, RX VrefLevel [Byte0]: 73
1648 11:51:55.991812 [Byte1]: 73
1649 11:51:55.996184
1650 11:51:55.996270 Set Vref, RX VrefLevel [Byte0]: 74
1651 11:51:55.999634 [Byte1]: 74
1652 11:51:56.004062
1653 11:51:56.004148 Final RX Vref Byte 0 = 60 to rank0
1654 11:51:56.007197 Final RX Vref Byte 1 = 56 to rank0
1655 11:51:56.010437 Final RX Vref Byte 0 = 60 to rank1
1656 11:51:56.013832 Final RX Vref Byte 1 = 56 to rank1==
1657 11:51:56.017014 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 11:51:56.023677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1659 11:51:56.023772 ==
1660 11:51:56.023840 DQS Delay:
1661 11:51:56.023901 DQS0 = 0, DQS1 = 0
1662 11:51:56.027169 DQM Delay:
1663 11:51:56.027252 DQM0 = 79, DQM1 = 72
1664 11:51:56.030612 DQ Delay:
1665 11:51:56.033646 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1666 11:51:56.037016 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1667 11:51:56.040381 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1668 11:51:56.043913 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1669 11:51:56.044000
1670 11:51:56.044066
1671 11:51:56.050410 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1672 11:51:56.054182 CH1 RK0: MR19=606, MR18=5151
1673 11:51:56.060743 CH1_RK0: MR19=0x606, MR18=0x5151, DQSOSC=389, MR23=63, INC=97, DEC=65
1674 11:51:56.060856
1675 11:51:56.063990 ----->DramcWriteLeveling(PI) begin...
1676 11:51:56.064075 ==
1677 11:51:56.067928 Dram Type= 6, Freq= 0, CH_1, rank 1
1678 11:51:56.071582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1679 11:51:56.071678 ==
1680 11:51:56.074977 Write leveling (Byte 0): 26 => 26
1681 11:51:56.078060 Write leveling (Byte 1): 26 => 26
1682 11:51:56.081238 DramcWriteLeveling(PI) end<-----
1683 11:51:56.081323
1684 11:51:56.081388 ==
1685 11:51:56.084519 Dram Type= 6, Freq= 0, CH_1, rank 1
1686 11:51:56.088165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1687 11:51:56.088251 ==
1688 11:51:56.091261 [Gating] SW mode calibration
1689 11:51:56.097949 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1690 11:51:56.101387 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1691 11:51:56.107939 0 6 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
1692 11:51:56.111592 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1693 11:51:56.114752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1694 11:51:56.121360 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 11:51:56.124701 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 11:51:56.128287 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 11:51:56.134976 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 11:51:56.138203 0 6 28 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1699 11:51:56.141350 0 7 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1700 11:51:56.148335 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1701 11:51:56.151474 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1702 11:51:56.154590 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 11:51:56.161216 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 11:51:56.164714 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 11:51:56.168007 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 11:51:56.174721 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1707 11:51:56.177945 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1708 11:51:56.181225 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1709 11:51:56.187859 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 11:51:56.191454 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 11:51:56.194505 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 11:51:56.197939 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 11:51:56.204456 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 11:51:56.207833 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 11:51:56.211368 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 11:51:56.217805 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 11:51:56.221240 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 11:51:56.224376 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:51:56.231073 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:51:56.234497 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:51:56.237842 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 11:51:56.244501 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1723 11:51:56.247915 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1724 11:51:56.251263 Total UI for P1: 0, mck2ui 16
1725 11:51:56.254614 best dqsien dly found for B0: ( 0, 9, 28)
1726 11:51:56.257882 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1727 11:51:56.261111 Total UI for P1: 0, mck2ui 16
1728 11:51:56.264370 best dqsien dly found for B1: ( 0, 10, 0)
1729 11:51:56.267839 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1730 11:51:56.271286 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1731 11:51:56.271430
1732 11:51:56.277885 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1733 11:51:56.281595 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1734 11:51:56.281683 [Gating] SW calibration Done
1735 11:51:56.284716 ==
1736 11:51:56.287871 Dram Type= 6, Freq= 0, CH_1, rank 1
1737 11:51:56.291059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1738 11:51:56.291145 ==
1739 11:51:56.291210 RX Vref Scan: 0
1740 11:51:56.291270
1741 11:51:56.294603 RX Vref 0 -> 0, step: 1
1742 11:51:56.294688
1743 11:51:56.297809 RX Delay -130 -> 252, step: 16
1744 11:51:56.301081 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1745 11:51:56.304552 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1746 11:51:56.307871 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1747 11:51:56.314748 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1748 11:51:56.317935 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1749 11:51:56.321125 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1750 11:51:56.324339 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1751 11:51:56.327757 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1752 11:51:56.334410 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1753 11:51:56.337640 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1754 11:51:56.341029 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1755 11:51:56.344690 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1756 11:51:56.347832 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1757 11:51:56.354494 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1758 11:51:56.357741 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1759 11:51:56.361273 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1760 11:51:56.361361 ==
1761 11:51:56.364245 Dram Type= 6, Freq= 0, CH_1, rank 1
1762 11:51:56.367690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1763 11:51:56.371124 ==
1764 11:51:56.371241 DQS Delay:
1765 11:51:56.371374 DQS0 = 0, DQS1 = 0
1766 11:51:56.374139 DQM Delay:
1767 11:51:56.374225 DQM0 = 81, DQM1 = 70
1768 11:51:56.377811 DQ Delay:
1769 11:51:56.377901 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1770 11:51:56.381136 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1771 11:51:56.384227 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1772 11:51:56.387499 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1773 11:51:56.390809
1774 11:51:56.390903
1775 11:51:56.390997 ==
1776 11:51:56.394161 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 11:51:56.397468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1778 11:51:56.397556 ==
1779 11:51:56.397622
1780 11:51:56.397682
1781 11:51:56.400980 TX Vref Scan disable
1782 11:51:56.401066 == TX Byte 0 ==
1783 11:51:56.407447 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1784 11:51:56.411161 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1785 11:51:56.411257 == TX Byte 1 ==
1786 11:51:56.417622 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1787 11:51:56.421300 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1788 11:51:56.421396 ==
1789 11:51:56.424265 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 11:51:56.427478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1791 11:51:56.427570 ==
1792 11:51:56.440888 TX Vref=22, minBit 10, minWin=27, winSum=450
1793 11:51:56.444173 TX Vref=24, minBit 10, minWin=27, winSum=451
1794 11:51:56.447440 TX Vref=26, minBit 1, minWin=28, winSum=457
1795 11:51:56.450955 TX Vref=28, minBit 0, minWin=28, winSum=456
1796 11:51:56.454119 TX Vref=30, minBit 0, minWin=28, winSum=455
1797 11:51:56.460824 TX Vref=32, minBit 9, minWin=27, winSum=454
1798 11:51:56.464122 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
1799 11:51:56.464223
1800 11:51:56.467327 Final TX Range 1 Vref 26
1801 11:51:56.467414
1802 11:51:56.467480 ==
1803 11:51:56.470841 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 11:51:56.473955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1805 11:51:56.474049 ==
1806 11:51:56.477289
1807 11:51:56.477376
1808 11:51:56.477444 TX Vref Scan disable
1809 11:51:56.480781 == TX Byte 0 ==
1810 11:51:56.484087 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1811 11:51:56.490742 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1812 11:51:56.490839 == TX Byte 1 ==
1813 11:51:56.494126 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1814 11:51:56.500814 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1815 11:51:56.500912
1816 11:51:56.500979 [DATLAT]
1817 11:51:56.501040 Freq=800, CH1 RK1
1818 11:51:56.501101
1819 11:51:56.504148 DATLAT Default: 0x9
1820 11:51:56.504231 0, 0xFFFF, sum = 0
1821 11:51:56.507459 1, 0xFFFF, sum = 0
1822 11:51:56.507545 2, 0xFFFF, sum = 0
1823 11:51:56.510942 3, 0xFFFF, sum = 0
1824 11:51:56.511030 4, 0xFFFF, sum = 0
1825 11:51:56.514082 5, 0xFFFF, sum = 0
1826 11:51:56.517290 6, 0xFFFF, sum = 0
1827 11:51:56.517382 7, 0xFFFF, sum = 0
1828 11:51:56.517451 8, 0x0, sum = 1
1829 11:51:56.520456 9, 0x0, sum = 2
1830 11:51:56.520606 10, 0x0, sum = 3
1831 11:51:56.523848 11, 0x0, sum = 4
1832 11:51:56.523934 best_step = 9
1833 11:51:56.523999
1834 11:51:56.524059 ==
1835 11:51:56.527286 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 11:51:56.534039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1837 11:51:56.534139 ==
1838 11:51:56.534208 RX Vref Scan: 0
1839 11:51:56.534270
1840 11:51:56.537376 RX Vref 0 -> 0, step: 1
1841 11:51:56.537461
1842 11:51:56.540648 RX Delay -111 -> 252, step: 8
1843 11:51:56.543797 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1844 11:51:56.547212 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1845 11:51:56.553824 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1846 11:51:56.557260 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1847 11:51:56.560618 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1848 11:51:56.563751 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1849 11:51:56.567324 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1850 11:51:56.573935 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1851 11:51:56.577236 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
1852 11:51:56.580948 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1853 11:51:56.583857 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1854 11:51:56.587506 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1855 11:51:56.593860 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1856 11:51:56.597194 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1857 11:51:56.600436 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1858 11:51:56.603723 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1859 11:51:56.603811 ==
1860 11:51:56.607270 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 11:51:56.614020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1862 11:51:56.614133 ==
1863 11:51:56.614203 DQS Delay:
1864 11:51:56.614264 DQS0 = 0, DQS1 = 0
1865 11:51:56.617348 DQM Delay:
1866 11:51:56.617437 DQM0 = 82, DQM1 = 72
1867 11:51:56.620440 DQ Delay:
1868 11:51:56.623735 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1869 11:51:56.623824 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1870 11:51:56.627134 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1871 11:51:56.630531 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1872 11:51:56.633706
1873 11:51:56.633794
1874 11:51:56.640647 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1875 11:51:56.643842 CH1 RK1: MR19=606, MR18=4141
1876 11:51:56.650330 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1877 11:51:56.654016 [RxdqsGatingPostProcess] freq 800
1878 11:51:56.657103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1879 11:51:56.660291 Pre-setting of DQS Precalculation
1880 11:51:56.667031 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1881 11:51:56.673638 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1882 11:51:56.680373 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1883 11:51:56.680487
1884 11:51:56.680566
1885 11:51:56.683623 [Calibration Summary] 1600 Mbps
1886 11:51:56.683707 CH 0, Rank 0
1887 11:51:56.686950 SW Impedance : PASS
1888 11:51:56.690234 DUTY Scan : NO K
1889 11:51:56.690318 ZQ Calibration : PASS
1890 11:51:56.694196 Jitter Meter : NO K
1891 11:51:56.694286 CBT Training : PASS
1892 11:51:56.697019 Write leveling : PASS
1893 11:51:56.700368 RX DQS gating : PASS
1894 11:51:56.700453 RX DQ/DQS(RDDQC) : PASS
1895 11:51:56.703655 TX DQ/DQS : PASS
1896 11:51:56.707028 RX DATLAT : PASS
1897 11:51:56.707112 RX DQ/DQS(Engine): PASS
1898 11:51:56.710518 TX OE : NO K
1899 11:51:56.710603 All Pass.
1900 11:51:56.710668
1901 11:51:56.713665 CH 0, Rank 1
1902 11:51:56.713747 SW Impedance : PASS
1903 11:51:56.716886 DUTY Scan : NO K
1904 11:51:56.720383 ZQ Calibration : PASS
1905 11:51:56.720498 Jitter Meter : NO K
1906 11:51:56.723835 CBT Training : PASS
1907 11:51:56.727371 Write leveling : PASS
1908 11:51:56.727457 RX DQS gating : PASS
1909 11:51:56.730247 RX DQ/DQS(RDDQC) : PASS
1910 11:51:56.730330 TX DQ/DQS : PASS
1911 11:51:56.733527 RX DATLAT : PASS
1912 11:51:56.737134 RX DQ/DQS(Engine): PASS
1913 11:51:56.737230 TX OE : NO K
1914 11:51:56.740283 All Pass.
1915 11:51:56.740366
1916 11:51:56.740431 CH 1, Rank 0
1917 11:51:56.743747 SW Impedance : PASS
1918 11:51:56.743829 DUTY Scan : NO K
1919 11:51:56.747512 ZQ Calibration : PASS
1920 11:51:56.750344 Jitter Meter : NO K
1921 11:51:56.750426 CBT Training : PASS
1922 11:51:56.753766 Write leveling : PASS
1923 11:51:56.757162 RX DQS gating : PASS
1924 11:51:56.757250 RX DQ/DQS(RDDQC) : PASS
1925 11:51:56.760637 TX DQ/DQS : PASS
1926 11:51:56.763755 RX DATLAT : PASS
1927 11:51:56.763840 RX DQ/DQS(Engine): PASS
1928 11:51:56.767081 TX OE : NO K
1929 11:51:56.767167 All Pass.
1930 11:51:56.767234
1931 11:51:56.770699 CH 1, Rank 1
1932 11:51:56.770784 SW Impedance : PASS
1933 11:51:56.773737 DUTY Scan : NO K
1934 11:51:56.773823 ZQ Calibration : PASS
1935 11:51:56.777085 Jitter Meter : NO K
1936 11:51:56.780482 CBT Training : PASS
1937 11:51:56.780578 Write leveling : PASS
1938 11:51:56.783769 RX DQS gating : PASS
1939 11:51:56.787189 RX DQ/DQS(RDDQC) : PASS
1940 11:51:56.787275 TX DQ/DQS : PASS
1941 11:51:56.790514 RX DATLAT : PASS
1942 11:51:56.793824 RX DQ/DQS(Engine): PASS
1943 11:51:56.793910 TX OE : NO K
1944 11:51:56.797334 All Pass.
1945 11:51:56.797418
1946 11:51:56.797484 DramC Write-DBI off
1947 11:51:56.800519 PER_BANK_REFRESH: Hybrid Mode
1948 11:51:56.800607 TX_TRACKING: ON
1949 11:51:56.803793 [GetDramInforAfterCalByMRR] Vendor 6.
1950 11:51:56.810432 [GetDramInforAfterCalByMRR] Revision 606.
1951 11:51:56.813811 [GetDramInforAfterCalByMRR] Revision 2 0.
1952 11:51:56.813905 MR0 0x3939
1953 11:51:56.813971 MR8 0x1111
1954 11:51:56.817191 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1955 11:51:56.817278
1956 11:51:56.820710 MR0 0x3939
1957 11:51:56.820798 MR8 0x1111
1958 11:51:56.823879 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1959 11:51:56.823973
1960 11:51:56.833880 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1961 11:51:56.837294 [FAST_K] Save calibration result to emmc
1962 11:51:56.840650 [FAST_K] Save calibration result to emmc
1963 11:51:56.843736 dram_init: config_dvfs: 1
1964 11:51:56.846969 dramc_set_vcore_voltage set vcore to 662500
1965 11:51:56.850407 Read voltage for 1200, 2
1966 11:51:56.850495 Vio18 = 0
1967 11:51:56.850562 Vcore = 662500
1968 11:51:56.853787 Vdram = 0
1969 11:51:56.853870 Vddq = 0
1970 11:51:56.853936 Vmddr = 0
1971 11:51:56.860481 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1972 11:51:56.863709 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1973 11:51:56.867200 MEM_TYPE=3, freq_sel=15
1974 11:51:56.870462 sv_algorithm_assistance_LP4_1600
1975 11:51:56.873860 ============ PULL DRAM RESETB DOWN ============
1976 11:51:56.877135 ========== PULL DRAM RESETB DOWN end =========
1977 11:51:56.883786 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1978 11:51:56.887120 ===================================
1979 11:51:56.887222 LPDDR4 DRAM CONFIGURATION
1980 11:51:56.890709 ===================================
1981 11:51:56.893855 EX_ROW_EN[0] = 0x0
1982 11:51:56.893941 EX_ROW_EN[1] = 0x0
1983 11:51:56.897334 LP4Y_EN = 0x0
1984 11:51:56.900620 WORK_FSP = 0x0
1985 11:51:56.900706 WL = 0x4
1986 11:51:56.903938 RL = 0x4
1987 11:51:56.904022 BL = 0x2
1988 11:51:56.907288 RPST = 0x0
1989 11:51:56.907374 RD_PRE = 0x0
1990 11:51:56.910858 WR_PRE = 0x1
1991 11:51:56.910944 WR_PST = 0x0
1992 11:51:56.914059 DBI_WR = 0x0
1993 11:51:56.914150 DBI_RD = 0x0
1994 11:51:56.917464 OTF = 0x1
1995 11:51:56.920482 ===================================
1996 11:51:56.923939 ===================================
1997 11:51:56.924030 ANA top config
1998 11:51:56.927355 ===================================
1999 11:51:56.930512 DLL_ASYNC_EN = 0
2000 11:51:56.933931 ALL_SLAVE_EN = 0
2001 11:51:56.934021 NEW_RANK_MODE = 1
2002 11:51:56.937240 DLL_IDLE_MODE = 1
2003 11:51:56.940537 LP45_APHY_COMB_EN = 1
2004 11:51:56.943846 TX_ODT_DIS = 1
2005 11:51:56.943935 NEW_8X_MODE = 1
2006 11:51:56.947667 ===================================
2007 11:51:56.950871 ===================================
2008 11:51:56.954474 data_rate = 2400
2009 11:51:56.957514 CKR = 1
2010 11:51:56.960744 DQ_P2S_RATIO = 8
2011 11:51:56.964301 ===================================
2012 11:51:56.967531 CA_P2S_RATIO = 8
2013 11:51:56.970862 DQ_CA_OPEN = 0
2014 11:51:56.970951 DQ_SEMI_OPEN = 0
2015 11:51:56.974343 CA_SEMI_OPEN = 0
2016 11:51:56.977608 CA_FULL_RATE = 0
2017 11:51:56.980843 DQ_CKDIV4_EN = 0
2018 11:51:56.984114 CA_CKDIV4_EN = 0
2019 11:51:56.987572 CA_PREDIV_EN = 0
2020 11:51:56.987665 PH8_DLY = 17
2021 11:51:56.990880 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2022 11:51:56.994171 DQ_AAMCK_DIV = 4
2023 11:51:56.997499 CA_AAMCK_DIV = 4
2024 11:51:57.000985 CA_ADMCK_DIV = 4
2025 11:51:57.001072 DQ_TRACK_CA_EN = 0
2026 11:51:57.004352 CA_PICK = 1200
2027 11:51:57.007692 CA_MCKIO = 1200
2028 11:51:57.010679 MCKIO_SEMI = 0
2029 11:51:57.014113 PLL_FREQ = 2366
2030 11:51:57.017491 DQ_UI_PI_RATIO = 32
2031 11:51:57.021049 CA_UI_PI_RATIO = 0
2032 11:51:57.024209 ===================================
2033 11:51:57.027576 ===================================
2034 11:51:57.027668 memory_type:LPDDR4
2035 11:51:57.030841 GP_NUM : 10
2036 11:51:57.034055 SRAM_EN : 1
2037 11:51:57.034143 MD32_EN : 0
2038 11:51:57.037618 ===================================
2039 11:51:57.041008 [ANA_INIT] >>>>>>>>>>>>>>
2040 11:51:57.044190 <<<<<< [CONFIGURE PHASE]: ANA_TX
2041 11:51:57.047423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2042 11:51:57.051077 ===================================
2043 11:51:57.054284 data_rate = 2400,PCW = 0X5b00
2044 11:51:57.057464 ===================================
2045 11:51:57.060778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2046 11:51:57.063999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2047 11:51:57.070791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2048 11:51:57.074210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2049 11:51:57.077665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2050 11:51:57.080871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2051 11:51:57.084114 [ANA_INIT] flow start
2052 11:51:57.087778 [ANA_INIT] PLL >>>>>>>>
2053 11:51:57.087866 [ANA_INIT] PLL <<<<<<<<
2054 11:51:57.090803 [ANA_INIT] MIDPI >>>>>>>>
2055 11:51:57.094143 [ANA_INIT] MIDPI <<<<<<<<
2056 11:51:57.094229 [ANA_INIT] DLL >>>>>>>>
2057 11:51:57.097578 [ANA_INIT] DLL <<<<<<<<
2058 11:51:57.100868 [ANA_INIT] flow end
2059 11:51:57.104361 ============ LP4 DIFF to SE enter ============
2060 11:51:57.107696 ============ LP4 DIFF to SE exit ============
2061 11:51:57.110970 [ANA_INIT] <<<<<<<<<<<<<
2062 11:51:57.114194 [Flow] Enable top DCM control >>>>>
2063 11:51:57.117614 [Flow] Enable top DCM control <<<<<
2064 11:51:57.120876 Enable DLL master slave shuffle
2065 11:51:57.124445 ==============================================================
2066 11:51:57.127676 Gating Mode config
2067 11:51:57.134247 ==============================================================
2068 11:51:57.134350 Config description:
2069 11:51:57.144203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2070 11:51:57.151233 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2071 11:51:57.154257 SELPH_MODE 0: By rank 1: By Phase
2072 11:51:57.160820 ==============================================================
2073 11:51:57.164393 GAT_TRACK_EN = 1
2074 11:51:57.167689 RX_GATING_MODE = 2
2075 11:51:57.170916 RX_GATING_TRACK_MODE = 2
2076 11:51:57.174196 SELPH_MODE = 1
2077 11:51:57.177831 PICG_EARLY_EN = 1
2078 11:51:57.180929 VALID_LAT_VALUE = 1
2079 11:51:57.184451 ==============================================================
2080 11:51:57.187447 Enter into Gating configuration >>>>
2081 11:51:57.191072 Exit from Gating configuration <<<<
2082 11:51:57.194063 Enter into DVFS_PRE_config >>>>>
2083 11:51:57.207605 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2084 11:51:57.207751 Exit from DVFS_PRE_config <<<<<
2085 11:51:57.210859 Enter into PICG configuration >>>>
2086 11:51:57.214128 Exit from PICG configuration <<<<
2087 11:51:57.217371 [RX_INPUT] configuration >>>>>
2088 11:51:57.220870 [RX_INPUT] configuration <<<<<
2089 11:51:57.227553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2090 11:51:57.230936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2091 11:51:57.237656 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2092 11:51:57.244206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2093 11:51:57.250868 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2094 11:51:57.257727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2095 11:51:57.261052 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2096 11:51:57.264364 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2097 11:51:57.267884 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2098 11:51:57.274334 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2099 11:51:57.277583 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2100 11:51:57.280963 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2101 11:51:57.284304 ===================================
2102 11:51:57.287598 LPDDR4 DRAM CONFIGURATION
2103 11:51:57.290957 ===================================
2104 11:51:57.291051 EX_ROW_EN[0] = 0x0
2105 11:51:57.294241 EX_ROW_EN[1] = 0x0
2106 11:51:57.294336 LP4Y_EN = 0x0
2107 11:51:57.297514 WORK_FSP = 0x0
2108 11:51:57.297601 WL = 0x4
2109 11:51:57.300943 RL = 0x4
2110 11:51:57.301029 BL = 0x2
2111 11:51:57.304346 RPST = 0x0
2112 11:51:57.307753 RD_PRE = 0x0
2113 11:51:57.307895 WR_PRE = 0x1
2114 11:51:57.311177 WR_PST = 0x0
2115 11:51:57.311271 DBI_WR = 0x0
2116 11:51:57.314440 DBI_RD = 0x0
2117 11:51:57.314530 OTF = 0x1
2118 11:51:57.317531 ===================================
2119 11:51:57.321024 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2120 11:51:57.324192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2121 11:51:57.331177 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2122 11:51:57.334407 ===================================
2123 11:51:57.337707 LPDDR4 DRAM CONFIGURATION
2124 11:51:57.340927 ===================================
2125 11:51:57.341016 EX_ROW_EN[0] = 0x10
2126 11:51:57.344274 EX_ROW_EN[1] = 0x0
2127 11:51:57.344385 LP4Y_EN = 0x0
2128 11:51:57.347567 WORK_FSP = 0x0
2129 11:51:57.347655 WL = 0x4
2130 11:51:57.351138 RL = 0x4
2131 11:51:57.351227 BL = 0x2
2132 11:51:57.354297 RPST = 0x0
2133 11:51:57.354382 RD_PRE = 0x0
2134 11:51:57.357793 WR_PRE = 0x1
2135 11:51:57.357881 WR_PST = 0x0
2136 11:51:57.361025 DBI_WR = 0x0
2137 11:51:57.361113 DBI_RD = 0x0
2138 11:51:57.364449 OTF = 0x1
2139 11:51:57.367689 ===================================
2140 11:51:57.374363 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2141 11:51:57.374474 ==
2142 11:51:57.377653 Dram Type= 6, Freq= 0, CH_0, rank 0
2143 11:51:57.381060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2144 11:51:57.381151 ==
2145 11:51:57.384368 [Duty_Offset_Calibration]
2146 11:51:57.384464 B0:0 B1:2 CA:1
2147 11:51:57.384563
2148 11:51:57.387704 [DutyScan_Calibration_Flow] k_type=0
2149 11:51:57.398133
2150 11:51:57.398245 ==CLK 0==
2151 11:51:57.401323 Final CLK duty delay cell = 0
2152 11:51:57.404863 [0] MAX Duty = 5093%(X100), DQS PI = 12
2153 11:51:57.408077 [0] MIN Duty = 4938%(X100), DQS PI = 52
2154 11:51:57.408169 [0] AVG Duty = 5015%(X100)
2155 11:51:57.411482
2156 11:51:57.414892 CH0 CLK Duty spec in!! Max-Min= 155%
2157 11:51:57.418044 [DutyScan_Calibration_Flow] ====Done====
2158 11:51:57.418183
2159 11:51:57.421429 [DutyScan_Calibration_Flow] k_type=1
2160 11:51:57.437396
2161 11:51:57.437549 ==DQS 0 ==
2162 11:51:57.440751 Final DQS duty delay cell = 0
2163 11:51:57.443974 [0] MAX Duty = 5125%(X100), DQS PI = 28
2164 11:51:57.447443 [0] MIN Duty = 5031%(X100), DQS PI = 6
2165 11:51:57.447529 [0] AVG Duty = 5078%(X100)
2166 11:51:57.450893
2167 11:51:57.450977 ==DQS 1 ==
2168 11:51:57.454127 Final DQS duty delay cell = 0
2169 11:51:57.457276 [0] MAX Duty = 5031%(X100), DQS PI = 50
2170 11:51:57.460475 [0] MIN Duty = 4906%(X100), DQS PI = 16
2171 11:51:57.464218 [0] AVG Duty = 4968%(X100)
2172 11:51:57.464309
2173 11:51:57.467320 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2174 11:51:57.467404
2175 11:51:57.470607 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2176 11:51:57.473980 [DutyScan_Calibration_Flow] ====Done====
2177 11:51:57.474068
2178 11:51:57.477473 [DutyScan_Calibration_Flow] k_type=3
2179 11:51:57.493754
2180 11:51:57.493907 ==DQM 0 ==
2181 11:51:57.497041 Final DQM duty delay cell = 0
2182 11:51:57.500285 [0] MAX Duty = 5156%(X100), DQS PI = 20
2183 11:51:57.503583 [0] MIN Duty = 4969%(X100), DQS PI = 40
2184 11:51:57.507142 [0] AVG Duty = 5062%(X100)
2185 11:51:57.507245
2186 11:51:57.507339 ==DQM 1 ==
2187 11:51:57.510435 Final DQM duty delay cell = 0
2188 11:51:57.513899 [0] MAX Duty = 5000%(X100), DQS PI = 56
2189 11:51:57.516984 [0] MIN Duty = 4844%(X100), DQS PI = 20
2190 11:51:57.520420 [0] AVG Duty = 4922%(X100)
2191 11:51:57.520576
2192 11:51:57.523646 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2193 11:51:57.523729
2194 11:51:57.527154 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2195 11:51:57.530399 [DutyScan_Calibration_Flow] ====Done====
2196 11:51:57.530488
2197 11:51:57.533595 [DutyScan_Calibration_Flow] k_type=2
2198 11:51:57.548822
2199 11:51:57.548966 ==DQ 0 ==
2200 11:51:57.552105 Final DQ duty delay cell = -4
2201 11:51:57.555454 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2202 11:51:57.558897 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2203 11:51:57.562146 [-4] AVG Duty = 4937%(X100)
2204 11:51:57.562237
2205 11:51:57.562303 ==DQ 1 ==
2206 11:51:57.565368 Final DQ duty delay cell = -4
2207 11:51:57.568822 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2208 11:51:57.572012 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2209 11:51:57.575376 [-4] AVG Duty = 4984%(X100)
2210 11:51:57.575466
2211 11:51:57.578917 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2212 11:51:57.579004
2213 11:51:57.582048 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2214 11:51:57.585397 [DutyScan_Calibration_Flow] ====Done====
2215 11:51:57.585487 ==
2216 11:51:57.588644 Dram Type= 6, Freq= 0, CH_1, rank 0
2217 11:51:57.592091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2218 11:51:57.592180 ==
2219 11:51:57.595312 [Duty_Offset_Calibration]
2220 11:51:57.595396 B0:0 B1:5 CA:-5
2221 11:51:57.595462
2222 11:51:57.598683 [DutyScan_Calibration_Flow] k_type=0
2223 11:51:57.609564
2224 11:51:57.609686 ==CLK 0==
2225 11:51:57.612620 Final CLK duty delay cell = 0
2226 11:51:57.615831 [0] MAX Duty = 5094%(X100), DQS PI = 24
2227 11:51:57.619210 [0] MIN Duty = 4875%(X100), DQS PI = 48
2228 11:51:57.622594 [0] AVG Duty = 4984%(X100)
2229 11:51:57.622689
2230 11:51:57.625913 CH1 CLK Duty spec in!! Max-Min= 219%
2231 11:51:57.629302 [DutyScan_Calibration_Flow] ====Done====
2232 11:51:57.629389
2233 11:51:57.632357 [DutyScan_Calibration_Flow] k_type=1
2234 11:51:57.647821
2235 11:51:57.647975 ==DQS 0 ==
2236 11:51:57.651094 Final DQS duty delay cell = 0
2237 11:51:57.654506 [0] MAX Duty = 5125%(X100), DQS PI = 16
2238 11:51:57.658074 [0] MIN Duty = 4875%(X100), DQS PI = 40
2239 11:51:57.658166 [0] AVG Duty = 5000%(X100)
2240 11:51:57.661143
2241 11:51:57.661230 ==DQS 1 ==
2242 11:51:57.664662 Final DQS duty delay cell = -4
2243 11:51:57.667646 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2244 11:51:57.671063 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2245 11:51:57.674260 [-4] AVG Duty = 4953%(X100)
2246 11:51:57.674351
2247 11:51:57.677764 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2248 11:51:57.677869
2249 11:51:57.680959 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2250 11:51:57.684390 [DutyScan_Calibration_Flow] ====Done====
2251 11:51:57.684481
2252 11:51:57.687598 [DutyScan_Calibration_Flow] k_type=3
2253 11:51:57.703081
2254 11:51:57.703230 ==DQM 0 ==
2255 11:51:57.706140 Final DQM duty delay cell = -4
2256 11:51:57.709535 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2257 11:51:57.713131 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2258 11:51:57.716314 [-4] AVG Duty = 4969%(X100)
2259 11:51:57.716416
2260 11:51:57.716483 ==DQM 1 ==
2261 11:51:57.719522 Final DQM duty delay cell = -4
2262 11:51:57.723116 [-4] MAX Duty = 5094%(X100), DQS PI = 4
2263 11:51:57.726209 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2264 11:51:57.729633 [-4] AVG Duty = 5000%(X100)
2265 11:51:57.729719
2266 11:51:57.732869 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2267 11:51:57.732951
2268 11:51:57.736208 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2269 11:51:57.739653 [DutyScan_Calibration_Flow] ====Done====
2270 11:51:57.739738
2271 11:51:57.742893 [DutyScan_Calibration_Flow] k_type=2
2272 11:51:57.760088
2273 11:51:57.760243 ==DQ 0 ==
2274 11:51:57.763290 Final DQ duty delay cell = 0
2275 11:51:57.766665 [0] MAX Duty = 5062%(X100), DQS PI = 0
2276 11:51:57.770044 [0] MIN Duty = 4969%(X100), DQS PI = 42
2277 11:51:57.770133 [0] AVG Duty = 5015%(X100)
2278 11:51:57.770199
2279 11:51:57.773198 ==DQ 1 ==
2280 11:51:57.776548 Final DQ duty delay cell = 0
2281 11:51:57.779971 [0] MAX Duty = 5031%(X100), DQS PI = 8
2282 11:51:57.783315 [0] MIN Duty = 4907%(X100), DQS PI = 0
2283 11:51:57.783406 [0] AVG Duty = 4969%(X100)
2284 11:51:57.783471
2285 11:51:57.786750 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2286 11:51:57.786839
2287 11:51:57.790014 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2288 11:51:57.796747 [DutyScan_Calibration_Flow] ====Done====
2289 11:51:57.800016 nWR fixed to 30
2290 11:51:57.800102 [ModeRegInit_LP4] CH0 RK0
2291 11:51:57.803191 [ModeRegInit_LP4] CH0 RK1
2292 11:51:57.806475 [ModeRegInit_LP4] CH1 RK0
2293 11:51:57.806561 [ModeRegInit_LP4] CH1 RK1
2294 11:51:57.809767 match AC timing 6
2295 11:51:57.813235 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2296 11:51:57.816432 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2297 11:51:57.823109 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2298 11:51:57.826666 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2299 11:51:57.833641 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2300 11:51:57.833745 ==
2301 11:51:57.836728 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 11:51:57.840144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2303 11:51:57.840256 ==
2304 11:51:57.846808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2305 11:51:57.849959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2306 11:51:57.859537 [CA 0] Center 39 (9~70) winsize 62
2307 11:51:57.862670 [CA 1] Center 39 (8~70) winsize 63
2308 11:51:57.866208 [CA 2] Center 36 (5~67) winsize 63
2309 11:51:57.869356 [CA 3] Center 35 (4~66) winsize 63
2310 11:51:57.872847 [CA 4] Center 34 (3~65) winsize 63
2311 11:51:57.876088 [CA 5] Center 34 (3~65) winsize 63
2312 11:51:57.876183
2313 11:51:57.879306 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2314 11:51:57.879399
2315 11:51:57.882646 [CATrainingPosCal] consider 1 rank data
2316 11:51:57.886093 u2DelayCellTimex100 = 270/100 ps
2317 11:51:57.889452 CA0 delay=39 (9~70),Diff = 5 PI (24 cell)
2318 11:51:57.895940 CA1 delay=39 (8~70),Diff = 5 PI (24 cell)
2319 11:51:57.899429 CA2 delay=36 (5~67),Diff = 2 PI (9 cell)
2320 11:51:57.902620 CA3 delay=35 (4~66),Diff = 1 PI (4 cell)
2321 11:51:57.905864 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
2322 11:51:57.909231 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
2323 11:51:57.909319
2324 11:51:57.912466 CA PerBit enable=1, Macro0, CA PI delay=34
2325 11:51:57.912570
2326 11:51:57.915962 [CBTSetCACLKResult] CA Dly = 34
2327 11:51:57.916046 CS Dly: 7 (0~38)
2328 11:51:57.919210 ==
2329 11:51:57.922652 Dram Type= 6, Freq= 0, CH_0, rank 1
2330 11:51:57.925892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2331 11:51:57.925980 ==
2332 11:51:57.929073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2333 11:51:57.935713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2334 11:51:57.944821 [CA 0] Center 39 (8~70) winsize 63
2335 11:51:57.948239 [CA 1] Center 38 (8~69) winsize 62
2336 11:51:57.951831 [CA 2] Center 36 (5~67) winsize 63
2337 11:51:57.954832 [CA 3] Center 35 (4~66) winsize 63
2338 11:51:57.958239 [CA 4] Center 33 (3~64) winsize 62
2339 11:51:57.961560 [CA 5] Center 34 (3~65) winsize 63
2340 11:51:57.961650
2341 11:51:57.964925 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2342 11:51:57.965011
2343 11:51:57.968305 [CATrainingPosCal] consider 2 rank data
2344 11:51:57.971423 u2DelayCellTimex100 = 270/100 ps
2345 11:51:57.974757 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2346 11:51:57.978172 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2347 11:51:57.984879 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2348 11:51:57.988220 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2349 11:51:57.991611 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2350 11:51:57.994892 CA5 delay=34 (3~65),Diff = 1 PI (4 cell)
2351 11:51:57.994980
2352 11:51:57.998525 CA PerBit enable=1, Macro0, CA PI delay=33
2353 11:51:57.998613
2354 11:51:58.001576 [CBTSetCACLKResult] CA Dly = 33
2355 11:51:58.001663 CS Dly: 7 (0~39)
2356 11:51:58.001730
2357 11:51:58.004903 ----->DramcWriteLeveling(PI) begin...
2358 11:51:58.008270 ==
2359 11:51:58.011386 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 11:51:58.014833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2361 11:51:58.014922 ==
2362 11:51:58.018434 Write leveling (Byte 0): 27 => 27
2363 11:51:58.021357 Write leveling (Byte 1): 27 => 27
2364 11:51:58.024691 DramcWriteLeveling(PI) end<-----
2365 11:51:58.024780
2366 11:51:58.024846 ==
2367 11:51:58.028147 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 11:51:58.031429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2369 11:51:58.031517 ==
2370 11:51:58.034526 [Gating] SW mode calibration
2371 11:51:58.041310 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2372 11:51:58.048034 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2373 11:51:58.051351 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2374 11:51:58.054697 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2375 11:51:58.057980 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 11:51:58.064657 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 11:51:58.068003 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2378 11:51:58.071150 0 11 20 | B1->B0 | 2e2e 2929 | 0 0 | (0 1) (1 0)
2379 11:51:58.077965 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2380 11:51:58.081162 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2381 11:51:58.084756 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 11:51:58.091628 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 11:51:58.094544 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 11:51:58.098085 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 11:51:58.104475 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
2386 11:51:58.108130 0 12 20 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
2387 11:51:58.111382 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2388 11:51:58.117903 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2389 11:51:58.121434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 11:51:58.124739 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 11:51:58.131352 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 11:51:58.134558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 11:51:58.137962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 11:51:58.144649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2395 11:51:58.147973 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2396 11:51:58.151182 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2397 11:51:58.158114 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 11:51:58.161410 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 11:51:58.164692 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 11:51:58.167822 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 11:51:58.174791 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 11:51:58.178164 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 11:51:58.181207 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 11:51:58.187847 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 11:51:58.191264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:51:58.194756 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:51:58.201327 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:51:58.204919 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 11:51:58.207987 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2410 11:51:58.214681 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2411 11:51:58.214791 Total UI for P1: 0, mck2ui 16
2412 11:51:58.221550 best dqsien dly found for B0: ( 0, 15, 16)
2413 11:51:58.224868 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 11:51:58.228172 Total UI for P1: 0, mck2ui 16
2415 11:51:58.231561 best dqsien dly found for B1: ( 0, 15, 20)
2416 11:51:58.235013 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2417 11:51:58.238271 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2418 11:51:58.238362
2419 11:51:58.241615 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2420 11:51:58.244792 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2421 11:51:58.248235 [Gating] SW calibration Done
2422 11:51:58.248325 ==
2423 11:51:58.251710 Dram Type= 6, Freq= 0, CH_0, rank 0
2424 11:51:58.254794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2425 11:51:58.254884 ==
2426 11:51:58.258115 RX Vref Scan: 0
2427 11:51:58.258200
2428 11:51:58.261505 RX Vref 0 -> 0, step: 1
2429 11:51:58.261590
2430 11:51:58.261656 RX Delay -40 -> 252, step: 8
2431 11:51:58.268100 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2432 11:51:58.271538 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2433 11:51:58.274707 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2434 11:51:58.278169 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2435 11:51:58.281509 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2436 11:51:58.288207 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2437 11:51:58.291740 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2438 11:51:58.294913 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2439 11:51:58.298453 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2440 11:51:58.301490 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2441 11:51:58.308275 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2442 11:51:58.311539 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2443 11:51:58.315042 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2444 11:51:58.318171 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2445 11:51:58.321793 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2446 11:51:58.328254 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2447 11:51:58.328357 ==
2448 11:51:58.331528 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 11:51:58.334879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2450 11:51:58.334964 ==
2451 11:51:58.335031 DQS Delay:
2452 11:51:58.338295 DQS0 = 0, DQS1 = 0
2453 11:51:58.338382 DQM Delay:
2454 11:51:58.341447 DQM0 = 115, DQM1 = 106
2455 11:51:58.341532 DQ Delay:
2456 11:51:58.344785 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2457 11:51:58.348000 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2458 11:51:58.351775 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2459 11:51:58.354648 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2460 11:51:58.354739
2461 11:51:58.354806
2462 11:51:58.358126 ==
2463 11:51:58.358212 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 11:51:58.364859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2465 11:51:58.364962 ==
2466 11:51:58.365028
2467 11:51:58.365089
2468 11:51:58.365149 TX Vref Scan disable
2469 11:51:58.368494 == TX Byte 0 ==
2470 11:51:58.371840 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2471 11:51:58.375187 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2472 11:51:58.378461 == TX Byte 1 ==
2473 11:51:58.382012 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2474 11:51:58.385351 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2475 11:51:58.388710 ==
2476 11:51:58.392039 Dram Type= 6, Freq= 0, CH_0, rank 0
2477 11:51:58.395137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2478 11:51:58.395228 ==
2479 11:51:58.406347 TX Vref=22, minBit 9, minWin=25, winSum=418
2480 11:51:58.409496 TX Vref=24, minBit 15, minWin=25, winSum=428
2481 11:51:58.412710 TX Vref=26, minBit 9, minWin=25, winSum=430
2482 11:51:58.416096 TX Vref=28, minBit 8, minWin=25, winSum=434
2483 11:51:58.419735 TX Vref=30, minBit 10, minWin=26, winSum=433
2484 11:51:58.426406 TX Vref=32, minBit 10, minWin=26, winSum=431
2485 11:51:58.429504 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
2486 11:51:58.429598
2487 11:51:58.432792 Final TX Range 1 Vref 30
2488 11:51:58.432879
2489 11:51:58.432946 ==
2490 11:51:58.436489 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 11:51:58.439382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2492 11:51:58.442650 ==
2493 11:51:58.442736
2494 11:51:58.442801
2495 11:51:58.442861 TX Vref Scan disable
2496 11:51:58.446066 == TX Byte 0 ==
2497 11:51:58.449474 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2498 11:51:58.456164 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2499 11:51:58.456268 == TX Byte 1 ==
2500 11:51:58.459473 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2501 11:51:58.466324 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2502 11:51:58.466438
2503 11:51:58.466503 [DATLAT]
2504 11:51:58.466563 Freq=1200, CH0 RK0
2505 11:51:58.466622
2506 11:51:58.469560 DATLAT Default: 0xd
2507 11:51:58.469642 0, 0xFFFF, sum = 0
2508 11:51:58.472915 1, 0xFFFF, sum = 0
2509 11:51:58.473002 2, 0xFFFF, sum = 0
2510 11:51:58.476245 3, 0xFFFF, sum = 0
2511 11:51:58.479588 4, 0xFFFF, sum = 0
2512 11:51:58.479683 5, 0xFFFF, sum = 0
2513 11:51:58.483081 6, 0xFFFF, sum = 0
2514 11:51:58.483167 7, 0xFFFF, sum = 0
2515 11:51:58.486127 8, 0xFFFF, sum = 0
2516 11:51:58.486213 9, 0xFFFF, sum = 0
2517 11:51:58.489718 10, 0xFFFF, sum = 0
2518 11:51:58.489803 11, 0x0, sum = 1
2519 11:51:58.492770 12, 0x0, sum = 2
2520 11:51:58.492853 13, 0x0, sum = 3
2521 11:51:58.492919 14, 0x0, sum = 4
2522 11:51:58.496209 best_step = 12
2523 11:51:58.496292
2524 11:51:58.496357 ==
2525 11:51:58.499540 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 11:51:58.502948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2527 11:51:58.503035 ==
2528 11:51:58.506342 RX Vref Scan: 1
2529 11:51:58.506425
2530 11:51:58.509721 Set Vref Range= 32 -> 127
2531 11:51:58.509804
2532 11:51:58.509869 RX Vref 32 -> 127, step: 1
2533 11:51:58.509929
2534 11:51:58.513318 RX Delay -21 -> 252, step: 4
2535 11:51:58.513401
2536 11:51:58.516339 Set Vref, RX VrefLevel [Byte0]: 32
2537 11:51:58.519568 [Byte1]: 32
2538 11:51:58.522960
2539 11:51:58.523055 Set Vref, RX VrefLevel [Byte0]: 33
2540 11:51:58.526517 [Byte1]: 33
2541 11:51:58.531062
2542 11:51:58.531169 Set Vref, RX VrefLevel [Byte0]: 34
2543 11:51:58.534240 [Byte1]: 34
2544 11:51:58.538908
2545 11:51:58.538999 Set Vref, RX VrefLevel [Byte0]: 35
2546 11:51:58.542436 [Byte1]: 35
2547 11:51:58.546757
2548 11:51:58.546848 Set Vref, RX VrefLevel [Byte0]: 36
2549 11:51:58.550132 [Byte1]: 36
2550 11:51:58.554683
2551 11:51:58.554771 Set Vref, RX VrefLevel [Byte0]: 37
2552 11:51:58.558020 [Byte1]: 37
2553 11:51:58.562993
2554 11:51:58.563092 Set Vref, RX VrefLevel [Byte0]: 38
2555 11:51:58.565974 [Byte1]: 38
2556 11:51:58.570498
2557 11:51:58.570593 Set Vref, RX VrefLevel [Byte0]: 39
2558 11:51:58.573751 [Byte1]: 39
2559 11:51:58.578507
2560 11:51:58.578601 Set Vref, RX VrefLevel [Byte0]: 40
2561 11:51:58.581585 [Byte1]: 40
2562 11:51:58.586481
2563 11:51:58.586574 Set Vref, RX VrefLevel [Byte0]: 41
2564 11:51:58.589711 [Byte1]: 41
2565 11:51:58.594302
2566 11:51:58.594391 Set Vref, RX VrefLevel [Byte0]: 42
2567 11:51:58.597491 [Byte1]: 42
2568 11:51:58.602361
2569 11:51:58.602454 Set Vref, RX VrefLevel [Byte0]: 43
2570 11:51:58.605550 [Byte1]: 43
2571 11:51:58.610045
2572 11:51:58.610132 Set Vref, RX VrefLevel [Byte0]: 44
2573 11:51:58.613748 [Byte1]: 44
2574 11:51:58.618220
2575 11:51:58.618310 Set Vref, RX VrefLevel [Byte0]: 45
2576 11:51:58.621506 [Byte1]: 45
2577 11:51:58.625853
2578 11:51:58.625944 Set Vref, RX VrefLevel [Byte0]: 46
2579 11:51:58.632391 [Byte1]: 46
2580 11:51:58.632487
2581 11:51:58.635621 Set Vref, RX VrefLevel [Byte0]: 47
2582 11:51:58.639088 [Byte1]: 47
2583 11:51:58.639175
2584 11:51:58.642651 Set Vref, RX VrefLevel [Byte0]: 48
2585 11:51:58.645620 [Byte1]: 48
2586 11:51:58.649702
2587 11:51:58.649792 Set Vref, RX VrefLevel [Byte0]: 49
2588 11:51:58.653277 [Byte1]: 49
2589 11:51:58.657687
2590 11:51:58.657779 Set Vref, RX VrefLevel [Byte0]: 50
2591 11:51:58.660977 [Byte1]: 50
2592 11:51:58.665511
2593 11:51:58.665604 Set Vref, RX VrefLevel [Byte0]: 51
2594 11:51:58.669120 [Byte1]: 51
2595 11:51:58.673400
2596 11:51:58.673491 Set Vref, RX VrefLevel [Byte0]: 52
2597 11:51:58.677016 [Byte1]: 52
2598 11:51:58.681422
2599 11:51:58.681518 Set Vref, RX VrefLevel [Byte0]: 53
2600 11:51:58.684652 [Byte1]: 53
2601 11:51:58.689222
2602 11:51:58.689317 Set Vref, RX VrefLevel [Byte0]: 54
2603 11:51:58.692447 [Byte1]: 54
2604 11:51:58.697189
2605 11:51:58.697279 Set Vref, RX VrefLevel [Byte0]: 55
2606 11:51:58.700715 [Byte1]: 55
2607 11:51:58.705175
2608 11:51:58.705265 Set Vref, RX VrefLevel [Byte0]: 56
2609 11:51:58.708388 [Byte1]: 56
2610 11:51:58.713113
2611 11:51:58.713204 Set Vref, RX VrefLevel [Byte0]: 57
2612 11:51:58.716374 [Byte1]: 57
2613 11:51:58.721044
2614 11:51:58.721195 Set Vref, RX VrefLevel [Byte0]: 58
2615 11:51:58.724643 [Byte1]: 58
2616 11:51:58.729134
2617 11:51:58.729224 Set Vref, RX VrefLevel [Byte0]: 59
2618 11:51:58.732301 [Byte1]: 59
2619 11:51:58.737238
2620 11:51:58.737329 Set Vref, RX VrefLevel [Byte0]: 60
2621 11:51:58.740319 [Byte1]: 60
2622 11:51:58.744900
2623 11:51:58.744988 Set Vref, RX VrefLevel [Byte0]: 61
2624 11:51:58.747969 [Byte1]: 61
2625 11:51:58.752880
2626 11:51:58.752968 Set Vref, RX VrefLevel [Byte0]: 62
2627 11:51:58.756173 [Byte1]: 62
2628 11:51:58.760767
2629 11:51:58.760888 Set Vref, RX VrefLevel [Byte0]: 63
2630 11:51:58.764121 [Byte1]: 63
2631 11:51:58.768626
2632 11:51:58.768719 Set Vref, RX VrefLevel [Byte0]: 64
2633 11:51:58.771869 [Byte1]: 64
2634 11:51:58.776379
2635 11:51:58.776471 Set Vref, RX VrefLevel [Byte0]: 65
2636 11:51:58.779639 [Byte1]: 65
2637 11:51:58.784390
2638 11:51:58.784480 Final RX Vref Byte 0 = 46 to rank0
2639 11:51:58.787809 Final RX Vref Byte 1 = 47 to rank0
2640 11:51:58.791093 Final RX Vref Byte 0 = 46 to rank1
2641 11:51:58.794236 Final RX Vref Byte 1 = 47 to rank1==
2642 11:51:58.797375 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 11:51:58.804003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2644 11:51:58.804104 ==
2645 11:51:58.804172 DQS Delay:
2646 11:51:58.807329 DQS0 = 0, DQS1 = 0
2647 11:51:58.807413 DQM Delay:
2648 11:51:58.807478 DQM0 = 114, DQM1 = 105
2649 11:51:58.810813 DQ Delay:
2650 11:51:58.814214 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2651 11:51:58.817581 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2652 11:51:58.821055 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2653 11:51:58.824299 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2654 11:51:58.824389
2655 11:51:58.824454
2656 11:51:58.831119 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2657 11:51:58.834269 CH0 RK0: MR19=404, MR18=C0C
2658 11:51:58.840892 CH0_RK0: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2659 11:51:58.840993
2660 11:51:58.844204 ----->DramcWriteLeveling(PI) begin...
2661 11:51:58.844290 ==
2662 11:51:58.847531 Dram Type= 6, Freq= 0, CH_0, rank 1
2663 11:51:58.850981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2664 11:51:58.851066 ==
2665 11:51:58.854128 Write leveling (Byte 0): 27 => 27
2666 11:51:58.857478 Write leveling (Byte 1): 24 => 24
2667 11:51:58.860872 DramcWriteLeveling(PI) end<-----
2668 11:51:58.860958
2669 11:51:58.861022 ==
2670 11:51:58.864262 Dram Type= 6, Freq= 0, CH_0, rank 1
2671 11:51:58.870752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2672 11:51:58.870852 ==
2673 11:51:58.870921 [Gating] SW mode calibration
2674 11:51:58.880895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2675 11:51:58.884151 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2676 11:51:58.887438 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2677 11:51:58.894065 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2678 11:51:58.897648 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2679 11:51:58.900727 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2680 11:51:58.907523 0 11 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2681 11:51:58.910723 0 11 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2682 11:51:58.914023 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2683 11:51:58.920973 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2684 11:51:58.924226 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2685 11:51:58.927312 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2686 11:51:58.934195 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2687 11:51:58.937261 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 11:51:58.940759 0 12 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2689 11:51:58.947253 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2690 11:51:58.950675 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2691 11:51:58.953927 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2692 11:51:58.960445 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2693 11:51:58.963931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2694 11:51:58.967196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2695 11:51:58.973953 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 11:51:58.977135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2697 11:51:58.980477 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2698 11:51:58.983939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2699 11:51:58.990982 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2700 11:51:58.993935 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2701 11:51:58.997233 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 11:51:59.004008 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 11:51:59.007368 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 11:51:59.010739 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 11:51:59.017237 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 11:51:59.020756 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 11:51:59.024358 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 11:51:59.030798 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 11:51:59.033896 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 11:51:59.037244 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 11:51:59.044159 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 11:51:59.047575 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2713 11:51:59.050675 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2714 11:51:59.054523 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 11:51:59.057624 Total UI for P1: 0, mck2ui 16
2716 11:51:59.060746 best dqsien dly found for B0: ( 0, 15, 18)
2717 11:51:59.064089 Total UI for P1: 0, mck2ui 16
2718 11:51:59.067562 best dqsien dly found for B1: ( 0, 15, 20)
2719 11:51:59.070768 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2720 11:51:59.077392 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2721 11:51:59.077501
2722 11:51:59.080810 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2723 11:51:59.084246 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2724 11:51:59.087483 [Gating] SW calibration Done
2725 11:51:59.087573 ==
2726 11:51:59.090981 Dram Type= 6, Freq= 0, CH_0, rank 1
2727 11:51:59.094267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2728 11:51:59.094355 ==
2729 11:51:59.094420 RX Vref Scan: 0
2730 11:51:59.097528
2731 11:51:59.097611 RX Vref 0 -> 0, step: 1
2732 11:51:59.097677
2733 11:51:59.101046 RX Delay -40 -> 252, step: 8
2734 11:51:59.104353 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2735 11:51:59.107632 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2736 11:51:59.114228 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2737 11:51:59.117780 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2738 11:51:59.121135 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2739 11:51:59.124358 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2740 11:51:59.127603 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2741 11:51:59.134135 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2742 11:51:59.137417 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2743 11:51:59.140849 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2744 11:51:59.144059 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2745 11:51:59.147514 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2746 11:51:59.153998 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2747 11:51:59.157446 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2748 11:51:59.160583 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2749 11:51:59.164001 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2750 11:51:59.164092 ==
2751 11:51:59.167252 Dram Type= 6, Freq= 0, CH_0, rank 1
2752 11:51:59.173932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2753 11:51:59.174032 ==
2754 11:51:59.174100 DQS Delay:
2755 11:51:59.174162 DQS0 = 0, DQS1 = 0
2756 11:51:59.177310 DQM Delay:
2757 11:51:59.177396 DQM0 = 113, DQM1 = 106
2758 11:51:59.180565 DQ Delay:
2759 11:51:59.184223 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =107
2760 11:51:59.187298 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2761 11:51:59.190738 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2762 11:51:59.193961 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2763 11:51:59.194049
2764 11:51:59.194114
2765 11:51:59.194175 ==
2766 11:51:59.197243 Dram Type= 6, Freq= 0, CH_0, rank 1
2767 11:51:59.200811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2768 11:51:59.200900 ==
2769 11:51:59.200966
2770 11:51:59.201025
2771 11:51:59.203890 TX Vref Scan disable
2772 11:51:59.207349 == TX Byte 0 ==
2773 11:51:59.210726 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2774 11:51:59.214543 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2775 11:51:59.217448 == TX Byte 1 ==
2776 11:51:59.220756 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2777 11:51:59.223988 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2778 11:51:59.224084 ==
2779 11:51:59.227303 Dram Type= 6, Freq= 0, CH_0, rank 1
2780 11:51:59.233963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2781 11:51:59.234067 ==
2782 11:51:59.244299 TX Vref=22, minBit 8, minWin=24, winSum=414
2783 11:51:59.247790 TX Vref=24, minBit 5, minWin=25, winSum=418
2784 11:51:59.251142 TX Vref=26, minBit 1, minWin=26, winSum=429
2785 11:51:59.254417 TX Vref=28, minBit 1, minWin=26, winSum=429
2786 11:51:59.257606 TX Vref=30, minBit 8, minWin=26, winSum=434
2787 11:51:59.260957 TX Vref=32, minBit 8, minWin=25, winSum=436
2788 11:51:59.267759 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2789 11:51:59.267870
2790 11:51:59.270993 Final TX Range 1 Vref 30
2791 11:51:59.271078
2792 11:51:59.271143 ==
2793 11:51:59.274286 Dram Type= 6, Freq= 0, CH_0, rank 1
2794 11:51:59.277658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2795 11:51:59.277749 ==
2796 11:51:59.277815
2797 11:51:59.281169
2798 11:51:59.281254 TX Vref Scan disable
2799 11:51:59.284379 == TX Byte 0 ==
2800 11:51:59.287604 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2801 11:51:59.290959 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2802 11:51:59.294394 == TX Byte 1 ==
2803 11:51:59.297577 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2804 11:51:59.300911 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2805 11:51:59.301001
2806 11:51:59.304425 [DATLAT]
2807 11:51:59.304540 Freq=1200, CH0 RK1
2808 11:51:59.304608
2809 11:51:59.307738 DATLAT Default: 0xc
2810 11:51:59.307822 0, 0xFFFF, sum = 0
2811 11:51:59.310974 1, 0xFFFF, sum = 0
2812 11:51:59.311060 2, 0xFFFF, sum = 0
2813 11:51:59.314213 3, 0xFFFF, sum = 0
2814 11:51:59.314299 4, 0xFFFF, sum = 0
2815 11:51:59.317528 5, 0xFFFF, sum = 0
2816 11:51:59.317614 6, 0xFFFF, sum = 0
2817 11:51:59.320959 7, 0xFFFF, sum = 0
2818 11:51:59.321044 8, 0xFFFF, sum = 0
2819 11:51:59.324268 9, 0xFFFF, sum = 0
2820 11:51:59.327962 10, 0xFFFF, sum = 0
2821 11:51:59.328053 11, 0x0, sum = 1
2822 11:51:59.328120 12, 0x0, sum = 2
2823 11:51:59.331077 13, 0x0, sum = 3
2824 11:51:59.331163 14, 0x0, sum = 4
2825 11:51:59.334212 best_step = 12
2826 11:51:59.334297
2827 11:51:59.334363 ==
2828 11:51:59.337572 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 11:51:59.340982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2830 11:51:59.341068 ==
2831 11:51:59.344371 RX Vref Scan: 0
2832 11:51:59.344482
2833 11:51:59.344568 RX Vref 0 -> 0, step: 1
2834 11:51:59.344631
2835 11:51:59.347669 RX Delay -21 -> 252, step: 4
2836 11:51:59.354625 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2837 11:51:59.357991 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2838 11:51:59.361251 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2839 11:51:59.364628 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2840 11:51:59.367817 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2841 11:51:59.374595 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2842 11:51:59.377827 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2843 11:51:59.381112 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2844 11:51:59.384420 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2845 11:51:59.387937 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2846 11:51:59.394741 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2847 11:51:59.397829 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2848 11:51:59.401022 iDelay=195, Bit 12, Center 110 (47 ~ 174) 128
2849 11:51:59.404624 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2850 11:51:59.407734 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
2851 11:51:59.414663 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2852 11:51:59.414770 ==
2853 11:51:59.417740 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 11:51:59.421459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2855 11:51:59.421547 ==
2856 11:51:59.421612 DQS Delay:
2857 11:51:59.424761 DQS0 = 0, DQS1 = 0
2858 11:51:59.424850 DQM Delay:
2859 11:51:59.427901 DQM0 = 114, DQM1 = 104
2860 11:51:59.427985 DQ Delay:
2861 11:51:59.431715 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2862 11:51:59.434614 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2863 11:51:59.437973 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2864 11:51:59.441591 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
2865 11:51:59.441714
2866 11:51:59.441845
2867 11:51:59.451357 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2868 11:51:59.451470 CH0 RK1: MR19=404, MR18=F0F
2869 11:51:59.458131 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2870 11:51:59.461059 [RxdqsGatingPostProcess] freq 1200
2871 11:51:59.468012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2872 11:51:59.471115 Pre-setting of DQS Precalculation
2873 11:51:59.474415 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2874 11:51:59.474504 ==
2875 11:51:59.477837 Dram Type= 6, Freq= 0, CH_1, rank 0
2876 11:51:59.484412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2877 11:51:59.484529 ==
2878 11:51:59.487460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2879 11:51:59.494210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2880 11:51:59.502951 [CA 0] Center 37 (7~68) winsize 62
2881 11:51:59.506287 [CA 1] Center 37 (7~68) winsize 62
2882 11:51:59.509771 [CA 2] Center 34 (4~65) winsize 62
2883 11:51:59.513015 [CA 3] Center 33 (3~64) winsize 62
2884 11:51:59.516359 [CA 4] Center 32 (1~63) winsize 63
2885 11:51:59.519677 [CA 5] Center 32 (2~63) winsize 62
2886 11:51:59.519764
2887 11:51:59.522866 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2888 11:51:59.523009
2889 11:51:59.526279 [CATrainingPosCal] consider 1 rank data
2890 11:51:59.529722 u2DelayCellTimex100 = 270/100 ps
2891 11:51:59.533008 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2892 11:51:59.536309 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2893 11:51:59.542915 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2894 11:51:59.546375 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2895 11:51:59.549580 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2896 11:51:59.552895 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2897 11:51:59.552985
2898 11:51:59.556240 CA PerBit enable=1, Macro0, CA PI delay=32
2899 11:51:59.556324
2900 11:51:59.559533 [CBTSetCACLKResult] CA Dly = 32
2901 11:51:59.559618 CS Dly: 6 (0~37)
2902 11:51:59.559683 ==
2903 11:51:59.563144 Dram Type= 6, Freq= 0, CH_1, rank 1
2904 11:51:59.569424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 11:51:59.569530 ==
2906 11:51:59.572991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2907 11:51:59.579373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2908 11:51:59.588168 [CA 0] Center 37 (7~68) winsize 62
2909 11:51:59.591620 [CA 1] Center 37 (6~68) winsize 63
2910 11:51:59.594754 [CA 2] Center 34 (3~65) winsize 63
2911 11:51:59.598424 [CA 3] Center 33 (3~64) winsize 62
2912 11:51:59.601462 [CA 4] Center 32 (2~63) winsize 62
2913 11:51:59.604799 [CA 5] Center 32 (1~63) winsize 63
2914 11:51:59.604886
2915 11:51:59.608194 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2916 11:51:59.608280
2917 11:51:59.611571 [CATrainingPosCal] consider 2 rank data
2918 11:51:59.614723 u2DelayCellTimex100 = 270/100 ps
2919 11:51:59.618171 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2920 11:51:59.621463 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2921 11:51:59.628313 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2922 11:51:59.631615 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2923 11:51:59.634853 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2924 11:51:59.638084 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2925 11:51:59.638169
2926 11:51:59.641511 CA PerBit enable=1, Macro0, CA PI delay=32
2927 11:51:59.641595
2928 11:51:59.645311 [CBTSetCACLKResult] CA Dly = 32
2929 11:51:59.645397 CS Dly: 6 (0~38)
2930 11:51:59.645461
2931 11:51:59.648176 ----->DramcWriteLeveling(PI) begin...
2932 11:51:59.651512 ==
2933 11:51:59.651596 Dram Type= 6, Freq= 0, CH_1, rank 0
2934 11:51:59.658399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2935 11:51:59.658498 ==
2936 11:51:59.661615 Write leveling (Byte 0): 21 => 21
2937 11:51:59.664988 Write leveling (Byte 1): 21 => 21
2938 11:51:59.668068 DramcWriteLeveling(PI) end<-----
2939 11:51:59.668156
2940 11:51:59.668221 ==
2941 11:51:59.671483 Dram Type= 6, Freq= 0, CH_1, rank 0
2942 11:51:59.674858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2943 11:51:59.674944 ==
2944 11:51:59.678098 [Gating] SW mode calibration
2945 11:51:59.685001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2946 11:51:59.688348 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2947 11:51:59.694859 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 11:51:59.698139 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 11:51:59.701688 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 11:51:59.708187 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2951 11:51:59.711625 0 11 16 | B1->B0 | 3030 2626 | 0 0 | (0 0) (1 0)
2952 11:51:59.715060 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2953 11:51:59.721785 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 11:51:59.725051 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 11:51:59.728350 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 11:51:59.735203 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 11:51:59.738285 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 11:51:59.741594 0 12 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2959 11:51:59.748265 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
2960 11:51:59.751703 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 11:51:59.755054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 11:51:59.758275 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 11:51:59.765079 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 11:51:59.768361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 11:51:59.772055 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 11:51:59.778308 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:51:59.781814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2968 11:51:59.784838 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2969 11:51:59.791712 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 11:51:59.795020 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 11:51:59.798199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 11:51:59.805015 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 11:51:59.808256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:51:59.811455 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:51:59.818228 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:51:59.821493 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:51:59.824828 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:51:59.831603 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:51:59.834810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:51:59.838186 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:51:59.845253 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:51:59.848319 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 11:51:59.851749 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2984 11:51:59.858366 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2985 11:51:59.858472 Total UI for P1: 0, mck2ui 16
2986 11:51:59.861681 best dqsien dly found for B0: ( 0, 15, 14)
2987 11:51:59.868344 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 11:51:59.871741 Total UI for P1: 0, mck2ui 16
2989 11:51:59.874997 best dqsien dly found for B1: ( 0, 15, 20)
2990 11:51:59.878553 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2991 11:51:59.881713 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2992 11:51:59.881803
2993 11:51:59.885005 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2994 11:51:59.888372 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2995 11:51:59.892020 [Gating] SW calibration Done
2996 11:51:59.892107 ==
2997 11:51:59.895101 Dram Type= 6, Freq= 0, CH_1, rank 0
2998 11:51:59.898483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2999 11:51:59.898573 ==
3000 11:51:59.901691 RX Vref Scan: 0
3001 11:51:59.901776
3002 11:51:59.904929 RX Vref 0 -> 0, step: 1
3003 11:51:59.905015
3004 11:51:59.905080 RX Delay -40 -> 252, step: 8
3005 11:51:59.911565 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3006 11:51:59.914831 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3007 11:51:59.918228 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3008 11:51:59.921449 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3009 11:51:59.925109 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3010 11:51:59.931562 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3011 11:51:59.934847 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3012 11:51:59.938308 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3013 11:51:59.941667 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3014 11:51:59.944802 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3015 11:51:59.948270 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3016 11:51:59.954827 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3017 11:51:59.958441 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3018 11:51:59.961453 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3019 11:51:59.964817 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3020 11:51:59.971552 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3021 11:51:59.971658 ==
3022 11:51:59.974797 Dram Type= 6, Freq= 0, CH_1, rank 0
3023 11:51:59.978096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3024 11:51:59.978186 ==
3025 11:51:59.978251 DQS Delay:
3026 11:51:59.981534 DQS0 = 0, DQS1 = 0
3027 11:51:59.981620 DQM Delay:
3028 11:51:59.984871 DQM0 = 116, DQM1 = 109
3029 11:51:59.984954 DQ Delay:
3030 11:51:59.988195 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3031 11:51:59.991538 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3032 11:51:59.994983 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =103
3033 11:51:59.998213 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3034 11:51:59.998300
3035 11:51:59.998366
3036 11:51:59.998425 ==
3037 11:52:00.001604 Dram Type= 6, Freq= 0, CH_1, rank 0
3038 11:52:00.008028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3039 11:52:00.008123 ==
3040 11:52:00.008187
3041 11:52:00.008248
3042 11:52:00.008305 TX Vref Scan disable
3043 11:52:00.011729 == TX Byte 0 ==
3044 11:52:00.015246 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3045 11:52:00.021803 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3046 11:52:00.021906 == TX Byte 1 ==
3047 11:52:00.025082 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3048 11:52:00.031742 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3049 11:52:00.031847 ==
3050 11:52:00.035048 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 11:52:00.038416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3052 11:52:00.038502 ==
3053 11:52:00.049271 TX Vref=22, minBit 8, minWin=25, winSum=414
3054 11:52:00.052457 TX Vref=24, minBit 9, minWin=25, winSum=419
3055 11:52:00.055913 TX Vref=26, minBit 0, minWin=26, winSum=426
3056 11:52:00.059255 TX Vref=28, minBit 9, minWin=25, winSum=429
3057 11:52:00.062507 TX Vref=30, minBit 9, minWin=25, winSum=431
3058 11:52:00.066050 TX Vref=32, minBit 1, minWin=26, winSum=427
3059 11:52:00.072466 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 32
3060 11:52:00.072654
3061 11:52:00.075744 Final TX Range 1 Vref 32
3062 11:52:00.075829
3063 11:52:00.075892 ==
3064 11:52:00.079055 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 11:52:00.082467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3066 11:52:00.082558 ==
3067 11:52:00.085827
3068 11:52:00.085911
3069 11:52:00.085975 TX Vref Scan disable
3070 11:52:00.089059 == TX Byte 0 ==
3071 11:52:00.092690 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3072 11:52:00.095887 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3073 11:52:00.099174 == TX Byte 1 ==
3074 11:52:00.102597 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3075 11:52:00.106053 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3076 11:52:00.106152
3077 11:52:00.109240 [DATLAT]
3078 11:52:00.109325 Freq=1200, CH1 RK0
3079 11:52:00.109389
3080 11:52:00.112423 DATLAT Default: 0xd
3081 11:52:00.112555 0, 0xFFFF, sum = 0
3082 11:52:00.115822 1, 0xFFFF, sum = 0
3083 11:52:00.115905 2, 0xFFFF, sum = 0
3084 11:52:00.119198 3, 0xFFFF, sum = 0
3085 11:52:00.119283 4, 0xFFFF, sum = 0
3086 11:52:00.122673 5, 0xFFFF, sum = 0
3087 11:52:00.122760 6, 0xFFFF, sum = 0
3088 11:52:00.125896 7, 0xFFFF, sum = 0
3089 11:52:00.129053 8, 0xFFFF, sum = 0
3090 11:52:00.129142 9, 0xFFFF, sum = 0
3091 11:52:00.132475 10, 0xFFFF, sum = 0
3092 11:52:00.132622 11, 0x0, sum = 1
3093 11:52:00.132688 12, 0x0, sum = 2
3094 11:52:00.135873 13, 0x0, sum = 3
3095 11:52:00.135957 14, 0x0, sum = 4
3096 11:52:00.139216 best_step = 12
3097 11:52:00.139297
3098 11:52:00.139360 ==
3099 11:52:00.142496 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 11:52:00.145946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3101 11:52:00.146030 ==
3102 11:52:00.149097 RX Vref Scan: 1
3103 11:52:00.149180
3104 11:52:00.149243 Set Vref Range= 32 -> 127
3105 11:52:00.152476
3106 11:52:00.152600 RX Vref 32 -> 127, step: 1
3107 11:52:00.152666
3108 11:52:00.155980 RX Delay -29 -> 252, step: 4
3109 11:52:00.156062
3110 11:52:00.159390 Set Vref, RX VrefLevel [Byte0]: 32
3111 11:52:00.162488 [Byte1]: 32
3112 11:52:00.166238
3113 11:52:00.166327 Set Vref, RX VrefLevel [Byte0]: 33
3114 11:52:00.169110 [Byte1]: 33
3115 11:52:00.173736
3116 11:52:00.173827 Set Vref, RX VrefLevel [Byte0]: 34
3117 11:52:00.177266 [Byte1]: 34
3118 11:52:00.181499
3119 11:52:00.185080 Set Vref, RX VrefLevel [Byte0]: 35
3120 11:52:00.188014 [Byte1]: 35
3121 11:52:00.188101
3122 11:52:00.191402 Set Vref, RX VrefLevel [Byte0]: 36
3123 11:52:00.194810 [Byte1]: 36
3124 11:52:00.194895
3125 11:52:00.198133 Set Vref, RX VrefLevel [Byte0]: 37
3126 11:52:00.201865 [Byte1]: 37
3127 11:52:00.205526
3128 11:52:00.205614 Set Vref, RX VrefLevel [Byte0]: 38
3129 11:52:00.208896 [Byte1]: 38
3130 11:52:00.213455
3131 11:52:00.213543 Set Vref, RX VrefLevel [Byte0]: 39
3132 11:52:00.216810 [Byte1]: 39
3133 11:52:00.221574
3134 11:52:00.221673 Set Vref, RX VrefLevel [Byte0]: 40
3135 11:52:00.224686 [Byte1]: 40
3136 11:52:00.229690
3137 11:52:00.229791 Set Vref, RX VrefLevel [Byte0]: 41
3138 11:52:00.232668 [Byte1]: 41
3139 11:52:00.237362
3140 11:52:00.237456 Set Vref, RX VrefLevel [Byte0]: 42
3141 11:52:00.240797 [Byte1]: 42
3142 11:52:00.245254
3143 11:52:00.245343 Set Vref, RX VrefLevel [Byte0]: 43
3144 11:52:00.248461 [Byte1]: 43
3145 11:52:00.253263
3146 11:52:00.253352 Set Vref, RX VrefLevel [Byte0]: 44
3147 11:52:00.256652 [Byte1]: 44
3148 11:52:00.261198
3149 11:52:00.261288 Set Vref, RX VrefLevel [Byte0]: 45
3150 11:52:00.264410 [Byte1]: 45
3151 11:52:00.269176
3152 11:52:00.269272 Set Vref, RX VrefLevel [Byte0]: 46
3153 11:52:00.272477 [Byte1]: 46
3154 11:52:00.277272
3155 11:52:00.277365 Set Vref, RX VrefLevel [Byte0]: 47
3156 11:52:00.280433 [Byte1]: 47
3157 11:52:00.285163
3158 11:52:00.285259 Set Vref, RX VrefLevel [Byte0]: 48
3159 11:52:00.288545 [Byte1]: 48
3160 11:52:00.293272
3161 11:52:00.293367 Set Vref, RX VrefLevel [Byte0]: 49
3162 11:52:00.296323 [Byte1]: 49
3163 11:52:00.301086
3164 11:52:00.301178 Set Vref, RX VrefLevel [Byte0]: 50
3165 11:52:00.304318 [Byte1]: 50
3166 11:52:00.308958
3167 11:52:00.309049 Set Vref, RX VrefLevel [Byte0]: 51
3168 11:52:00.312289 [Byte1]: 51
3169 11:52:00.317075
3170 11:52:00.317165 Set Vref, RX VrefLevel [Byte0]: 52
3171 11:52:00.320408 [Byte1]: 52
3172 11:52:00.325031
3173 11:52:00.325136 Set Vref, RX VrefLevel [Byte0]: 53
3174 11:52:00.328201 [Byte1]: 53
3175 11:52:00.333063
3176 11:52:00.333166 Set Vref, RX VrefLevel [Byte0]: 54
3177 11:52:00.336125 [Byte1]: 54
3178 11:52:00.340874
3179 11:52:00.340968 Set Vref, RX VrefLevel [Byte0]: 55
3180 11:52:00.344358 [Byte1]: 55
3181 11:52:00.348894
3182 11:52:00.348988 Set Vref, RX VrefLevel [Byte0]: 56
3183 11:52:00.352172 [Byte1]: 56
3184 11:52:00.356730
3185 11:52:00.356823 Set Vref, RX VrefLevel [Byte0]: 57
3186 11:52:00.360038 [Byte1]: 57
3187 11:52:00.364731
3188 11:52:00.364821 Set Vref, RX VrefLevel [Byte0]: 58
3189 11:52:00.367853 [Byte1]: 58
3190 11:52:00.372723
3191 11:52:00.372813 Set Vref, RX VrefLevel [Byte0]: 59
3192 11:52:00.376019 [Byte1]: 59
3193 11:52:00.380650
3194 11:52:00.380742 Set Vref, RX VrefLevel [Byte0]: 60
3195 11:52:00.383891 [Byte1]: 60
3196 11:52:00.388504
3197 11:52:00.388603 Set Vref, RX VrefLevel [Byte0]: 61
3198 11:52:00.391839 [Byte1]: 61
3199 11:52:00.396480
3200 11:52:00.396577 Set Vref, RX VrefLevel [Byte0]: 62
3201 11:52:00.399810 [Byte1]: 62
3202 11:52:00.404497
3203 11:52:00.404596 Set Vref, RX VrefLevel [Byte0]: 63
3204 11:52:00.408012 [Byte1]: 63
3205 11:52:00.412521
3206 11:52:00.412609 Set Vref, RX VrefLevel [Byte0]: 64
3207 11:52:00.416034 [Byte1]: 64
3208 11:52:00.420424
3209 11:52:00.420515 Set Vref, RX VrefLevel [Byte0]: 65
3210 11:52:00.423728 [Byte1]: 65
3211 11:52:00.428452
3212 11:52:00.428590 Set Vref, RX VrefLevel [Byte0]: 66
3213 11:52:00.431735 [Byte1]: 66
3214 11:52:00.436391
3215 11:52:00.436483 Final RX Vref Byte 0 = 52 to rank0
3216 11:52:00.439817 Final RX Vref Byte 1 = 49 to rank0
3217 11:52:00.443054 Final RX Vref Byte 0 = 52 to rank1
3218 11:52:00.446416 Final RX Vref Byte 1 = 49 to rank1==
3219 11:52:00.449769 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 11:52:00.453146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3221 11:52:00.456470 ==
3222 11:52:00.456598 DQS Delay:
3223 11:52:00.456665 DQS0 = 0, DQS1 = 0
3224 11:52:00.459898 DQM Delay:
3225 11:52:00.459983 DQM0 = 115, DQM1 = 105
3226 11:52:00.463030 DQ Delay:
3227 11:52:00.466373 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3228 11:52:00.469825 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3229 11:52:00.472961 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3230 11:52:00.476456 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =114
3231 11:52:00.476598
3232 11:52:00.476668
3233 11:52:00.483118 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3234 11:52:00.486498 CH1 RK0: MR19=404, MR18=1C1C
3235 11:52:00.493167 CH1_RK0: MR19=0x404, MR18=0x1C1C, DQSOSC=399, MR23=63, INC=41, DEC=27
3236 11:52:00.493269
3237 11:52:00.496617 ----->DramcWriteLeveling(PI) begin...
3238 11:52:00.496705 ==
3239 11:52:00.499629 Dram Type= 6, Freq= 0, CH_1, rank 1
3240 11:52:00.503213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3241 11:52:00.503302 ==
3242 11:52:00.506437 Write leveling (Byte 0): 22 => 22
3243 11:52:00.509846 Write leveling (Byte 1): 22 => 22
3244 11:52:00.513168 DramcWriteLeveling(PI) end<-----
3245 11:52:00.513274
3246 11:52:00.513362 ==
3247 11:52:00.516317 Dram Type= 6, Freq= 0, CH_1, rank 1
3248 11:52:00.522980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3249 11:52:00.523080 ==
3250 11:52:00.523147 [Gating] SW mode calibration
3251 11:52:00.533282 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3252 11:52:00.536287 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3253 11:52:00.539711 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3254 11:52:00.546410 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3255 11:52:00.549658 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3256 11:52:00.553051 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3257 11:52:00.559712 0 11 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3258 11:52:00.562859 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3259 11:52:00.566451 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3260 11:52:00.573083 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 11:52:00.576672 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 11:52:00.579561 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 11:52:00.586236 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 11:52:00.589606 0 12 12 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
3265 11:52:00.593031 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
3266 11:52:00.599559 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 11:52:00.602844 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3268 11:52:00.606163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 11:52:00.612819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 11:52:00.616161 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 11:52:00.619685 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 11:52:00.622785 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3273 11:52:00.629541 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3274 11:52:00.632818 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3275 11:52:00.636133 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 11:52:00.642838 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 11:52:00.646325 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 11:52:00.649710 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 11:52:00.656140 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 11:52:00.659611 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 11:52:00.662748 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 11:52:00.669794 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 11:52:00.672915 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 11:52:00.676239 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 11:52:00.683022 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:52:00.686161 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:52:00.689399 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3288 11:52:00.696195 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3289 11:52:00.699473 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3290 11:52:00.702875 Total UI for P1: 0, mck2ui 16
3291 11:52:00.706151 best dqsien dly found for B0: ( 0, 15, 10)
3292 11:52:00.709502 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 11:52:00.713177 Total UI for P1: 0, mck2ui 16
3294 11:52:00.716407 best dqsien dly found for B1: ( 0, 15, 16)
3295 11:52:00.719694 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3296 11:52:00.722951 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3297 11:52:00.723037
3298 11:52:00.726221 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3299 11:52:00.733017 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3300 11:52:00.733119 [Gating] SW calibration Done
3301 11:52:00.733185 ==
3302 11:52:00.736403 Dram Type= 6, Freq= 0, CH_1, rank 1
3303 11:52:00.743023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3304 11:52:00.743129 ==
3305 11:52:00.743195 RX Vref Scan: 0
3306 11:52:00.743255
3307 11:52:00.746215 RX Vref 0 -> 0, step: 1
3308 11:52:00.746299
3309 11:52:00.749420 RX Delay -40 -> 252, step: 8
3310 11:52:00.752889 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3311 11:52:00.756231 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3312 11:52:00.759459 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3313 11:52:00.766356 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3314 11:52:00.769587 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3315 11:52:00.773013 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3316 11:52:00.776015 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3317 11:52:00.779354 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3318 11:52:00.786055 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3319 11:52:00.789399 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3320 11:52:00.792496 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3321 11:52:00.796105 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3322 11:52:00.799378 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3323 11:52:00.806029 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3324 11:52:00.809026 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3325 11:52:00.812517 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3326 11:52:00.812605 ==
3327 11:52:00.815825 Dram Type= 6, Freq= 0, CH_1, rank 1
3328 11:52:00.819091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3329 11:52:00.819178 ==
3330 11:52:00.822524 DQS Delay:
3331 11:52:00.822606 DQS0 = 0, DQS1 = 0
3332 11:52:00.826095 DQM Delay:
3333 11:52:00.826183 DQM0 = 115, DQM1 = 105
3334 11:52:00.826248 DQ Delay:
3335 11:52:00.829226 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3336 11:52:00.835781 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3337 11:52:00.839229 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3338 11:52:00.842583 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3339 11:52:00.842671
3340 11:52:00.842735
3341 11:52:00.842795 ==
3342 11:52:00.846077 Dram Type= 6, Freq= 0, CH_1, rank 1
3343 11:52:00.849332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3344 11:52:00.849417 ==
3345 11:52:00.849482
3346 11:52:00.849542
3347 11:52:00.852663 TX Vref Scan disable
3348 11:52:00.852747 == TX Byte 0 ==
3349 11:52:00.859237 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3350 11:52:00.862743 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3351 11:52:00.862828 == TX Byte 1 ==
3352 11:52:00.869355 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3353 11:52:00.872777 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3354 11:52:00.872873 ==
3355 11:52:00.875833 Dram Type= 6, Freq= 0, CH_1, rank 1
3356 11:52:00.879225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3357 11:52:00.879316 ==
3358 11:52:00.891665 TX Vref=22, minBit 7, minWin=25, winSum=424
3359 11:52:00.895169 TX Vref=24, minBit 8, minWin=25, winSum=423
3360 11:52:00.898407 TX Vref=26, minBit 1, minWin=26, winSum=427
3361 11:52:00.901694 TX Vref=28, minBit 8, minWin=26, winSum=432
3362 11:52:00.905115 TX Vref=30, minBit 9, minWin=26, winSum=431
3363 11:52:00.911535 TX Vref=32, minBit 9, minWin=26, winSum=432
3364 11:52:00.914935 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3365 11:52:00.915028
3366 11:52:00.918523 Final TX Range 1 Vref 28
3367 11:52:00.918609
3368 11:52:00.918674 ==
3369 11:52:00.921710 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 11:52:00.925032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 11:52:00.925117 ==
3372 11:52:00.925183
3373 11:52:00.928309
3374 11:52:00.928397 TX Vref Scan disable
3375 11:52:00.931639 == TX Byte 0 ==
3376 11:52:00.934921 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3377 11:52:00.938228 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3378 11:52:00.941724 == TX Byte 1 ==
3379 11:52:00.945134 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3380 11:52:00.948306 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3381 11:52:00.948393
3382 11:52:00.951605 [DATLAT]
3383 11:52:00.951688 Freq=1200, CH1 RK1
3384 11:52:00.951753
3385 11:52:00.955070 DATLAT Default: 0xc
3386 11:52:00.955154 0, 0xFFFF, sum = 0
3387 11:52:00.958413 1, 0xFFFF, sum = 0
3388 11:52:00.958500 2, 0xFFFF, sum = 0
3389 11:52:00.961598 3, 0xFFFF, sum = 0
3390 11:52:00.961682 4, 0xFFFF, sum = 0
3391 11:52:00.965241 5, 0xFFFF, sum = 0
3392 11:52:00.965328 6, 0xFFFF, sum = 0
3393 11:52:00.968231 7, 0xFFFF, sum = 0
3394 11:52:00.971570 8, 0xFFFF, sum = 0
3395 11:52:00.971658 9, 0xFFFF, sum = 0
3396 11:52:00.975008 10, 0xFFFF, sum = 0
3397 11:52:00.975095 11, 0x0, sum = 1
3398 11:52:00.975162 12, 0x0, sum = 2
3399 11:52:00.978235 13, 0x0, sum = 3
3400 11:52:00.978321 14, 0x0, sum = 4
3401 11:52:00.981598 best_step = 12
3402 11:52:00.981681
3403 11:52:00.981761 ==
3404 11:52:00.985091 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 11:52:00.988258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3406 11:52:00.988371 ==
3407 11:52:00.991678 RX Vref Scan: 0
3408 11:52:00.991763
3409 11:52:00.991829 RX Vref 0 -> 0, step: 1
3410 11:52:00.991888
3411 11:52:00.994767 RX Delay -29 -> 252, step: 4
3412 11:52:01.001998 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3413 11:52:01.005227 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3414 11:52:01.008438 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3415 11:52:01.011772 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3416 11:52:01.015169 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3417 11:52:01.021901 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3418 11:52:01.025113 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3419 11:52:01.028405 iDelay=199, Bit 7, Center 110 (39 ~ 182) 144
3420 11:52:01.031912 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3421 11:52:01.035065 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3422 11:52:01.041799 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3423 11:52:01.045172 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3424 11:52:01.048418 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3425 11:52:01.051913 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3426 11:52:01.055188 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3427 11:52:01.062065 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3428 11:52:01.062171 ==
3429 11:52:01.065194 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 11:52:01.068390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3431 11:52:01.068478 ==
3432 11:52:01.068555 DQS Delay:
3433 11:52:01.071863 DQS0 = 0, DQS1 = 0
3434 11:52:01.071946 DQM Delay:
3435 11:52:01.075103 DQM0 = 114, DQM1 = 104
3436 11:52:01.075186 DQ Delay:
3437 11:52:01.078478 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3438 11:52:01.082082 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3439 11:52:01.085116 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3440 11:52:01.088513 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =112
3441 11:52:01.088604
3442 11:52:01.088669
3443 11:52:01.098680 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3444 11:52:01.101782 CH1 RK1: MR19=404, MR18=C0C
3445 11:52:01.105151 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3446 11:52:01.108592 [RxdqsGatingPostProcess] freq 1200
3447 11:52:01.115126 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3448 11:52:01.118492 Pre-setting of DQS Precalculation
3449 11:52:01.122003 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3450 11:52:01.132162 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3451 11:52:01.138538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3452 11:52:01.138651
3453 11:52:01.138717
3454 11:52:01.142011 [Calibration Summary] 2400 Mbps
3455 11:52:01.142097 CH 0, Rank 0
3456 11:52:01.145111 SW Impedance : PASS
3457 11:52:01.145194 DUTY Scan : NO K
3458 11:52:01.148427 ZQ Calibration : PASS
3459 11:52:01.151963 Jitter Meter : NO K
3460 11:52:01.152048 CBT Training : PASS
3461 11:52:01.155442 Write leveling : PASS
3462 11:52:01.155525 RX DQS gating : PASS
3463 11:52:01.158639 RX DQ/DQS(RDDQC) : PASS
3464 11:52:01.162085 TX DQ/DQS : PASS
3465 11:52:01.162170 RX DATLAT : PASS
3466 11:52:01.165424 RX DQ/DQS(Engine): PASS
3467 11:52:01.168801 TX OE : NO K
3468 11:52:01.168889 All Pass.
3469 11:52:01.168955
3470 11:52:01.169015 CH 0, Rank 1
3471 11:52:01.171940 SW Impedance : PASS
3472 11:52:01.175373 DUTY Scan : NO K
3473 11:52:01.175457 ZQ Calibration : PASS
3474 11:52:01.178700 Jitter Meter : NO K
3475 11:52:01.181945 CBT Training : PASS
3476 11:52:01.182044 Write leveling : PASS
3477 11:52:01.185372 RX DQS gating : PASS
3478 11:52:01.188594 RX DQ/DQS(RDDQC) : PASS
3479 11:52:01.188681 TX DQ/DQS : PASS
3480 11:52:01.191953 RX DATLAT : PASS
3481 11:52:01.195367 RX DQ/DQS(Engine): PASS
3482 11:52:01.195452 TX OE : NO K
3483 11:52:01.195518 All Pass.
3484 11:52:01.195578
3485 11:52:01.198993 CH 1, Rank 0
3486 11:52:01.199079 SW Impedance : PASS
3487 11:52:01.202181 DUTY Scan : NO K
3488 11:52:01.205448 ZQ Calibration : PASS
3489 11:52:01.205535 Jitter Meter : NO K
3490 11:52:01.208873 CBT Training : PASS
3491 11:52:01.211974 Write leveling : PASS
3492 11:52:01.212059 RX DQS gating : PASS
3493 11:52:01.215379 RX DQ/DQS(RDDQC) : PASS
3494 11:52:01.218798 TX DQ/DQS : PASS
3495 11:52:01.218884 RX DATLAT : PASS
3496 11:52:01.222004 RX DQ/DQS(Engine): PASS
3497 11:52:01.225294 TX OE : NO K
3498 11:52:01.225380 All Pass.
3499 11:52:01.225445
3500 11:52:01.225504 CH 1, Rank 1
3501 11:52:01.228732 SW Impedance : PASS
3502 11:52:01.232119 DUTY Scan : NO K
3503 11:52:01.232207 ZQ Calibration : PASS
3504 11:52:01.235784 Jitter Meter : NO K
3505 11:52:01.238594 CBT Training : PASS
3506 11:52:01.238722 Write leveling : PASS
3507 11:52:01.241852 RX DQS gating : PASS
3508 11:52:01.241937 RX DQ/DQS(RDDQC) : PASS
3509 11:52:01.245311 TX DQ/DQS : PASS
3510 11:52:01.248454 RX DATLAT : PASS
3511 11:52:01.248551 RX DQ/DQS(Engine): PASS
3512 11:52:01.251843 TX OE : NO K
3513 11:52:01.251926 All Pass.
3514 11:52:01.251989
3515 11:52:01.255217 DramC Write-DBI off
3516 11:52:01.258728 PER_BANK_REFRESH: Hybrid Mode
3517 11:52:01.258813 TX_TRACKING: ON
3518 11:52:01.268605 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3519 11:52:01.272015 [FAST_K] Save calibration result to emmc
3520 11:52:01.275408 dramc_set_vcore_voltage set vcore to 650000
3521 11:52:01.278614 Read voltage for 600, 5
3522 11:52:01.278705 Vio18 = 0
3523 11:52:01.278770 Vcore = 650000
3524 11:52:01.281985 Vdram = 0
3525 11:52:01.282069 Vddq = 0
3526 11:52:01.282146 Vmddr = 0
3527 11:52:01.288786 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3528 11:52:01.291957 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3529 11:52:01.295331 MEM_TYPE=3, freq_sel=19
3530 11:52:01.298851 sv_algorithm_assistance_LP4_1600
3531 11:52:01.302034 ============ PULL DRAM RESETB DOWN ============
3532 11:52:01.305445 ========== PULL DRAM RESETB DOWN end =========
3533 11:52:01.311963 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3534 11:52:01.315467 ===================================
3535 11:52:01.318547 LPDDR4 DRAM CONFIGURATION
3536 11:52:01.322066 ===================================
3537 11:52:01.322154 EX_ROW_EN[0] = 0x0
3538 11:52:01.325229 EX_ROW_EN[1] = 0x0
3539 11:52:01.325312 LP4Y_EN = 0x0
3540 11:52:01.328554 WORK_FSP = 0x0
3541 11:52:01.328656 WL = 0x2
3542 11:52:01.332146 RL = 0x2
3543 11:52:01.332229 BL = 0x2
3544 11:52:01.335180 RPST = 0x0
3545 11:52:01.335262 RD_PRE = 0x0
3546 11:52:01.338551 WR_PRE = 0x1
3547 11:52:01.338633 WR_PST = 0x0
3548 11:52:01.341965 DBI_WR = 0x0
3549 11:52:01.342050 DBI_RD = 0x0
3550 11:52:01.345412 OTF = 0x1
3551 11:52:01.348400 ===================================
3552 11:52:01.351758 ===================================
3553 11:52:01.351843 ANA top config
3554 11:52:01.355072 ===================================
3555 11:52:01.358448 DLL_ASYNC_EN = 0
3556 11:52:01.361815 ALL_SLAVE_EN = 1
3557 11:52:01.365171 NEW_RANK_MODE = 1
3558 11:52:01.365258 DLL_IDLE_MODE = 1
3559 11:52:01.368426 LP45_APHY_COMB_EN = 1
3560 11:52:01.371843 TX_ODT_DIS = 1
3561 11:52:01.375280 NEW_8X_MODE = 1
3562 11:52:01.378482 ===================================
3563 11:52:01.381671 ===================================
3564 11:52:01.385042 data_rate = 1200
3565 11:52:01.385133 CKR = 1
3566 11:52:01.388348 DQ_P2S_RATIO = 8
3567 11:52:01.391603 ===================================
3568 11:52:01.394956 CA_P2S_RATIO = 8
3569 11:52:01.398203 DQ_CA_OPEN = 0
3570 11:52:01.401638 DQ_SEMI_OPEN = 0
3571 11:52:01.404941 CA_SEMI_OPEN = 0
3572 11:52:01.405027 CA_FULL_RATE = 0
3573 11:52:01.408204 DQ_CKDIV4_EN = 1
3574 11:52:01.411642 CA_CKDIV4_EN = 1
3575 11:52:01.414966 CA_PREDIV_EN = 0
3576 11:52:01.418236 PH8_DLY = 0
3577 11:52:01.421599 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3578 11:52:01.421686 DQ_AAMCK_DIV = 4
3579 11:52:01.424999 CA_AAMCK_DIV = 4
3580 11:52:01.428268 CA_ADMCK_DIV = 4
3581 11:52:01.431647 DQ_TRACK_CA_EN = 0
3582 11:52:01.434864 CA_PICK = 600
3583 11:52:01.438158 CA_MCKIO = 600
3584 11:52:01.438242 MCKIO_SEMI = 0
3585 11:52:01.441708 PLL_FREQ = 2288
3586 11:52:01.445346 DQ_UI_PI_RATIO = 32
3587 11:52:01.448235 CA_UI_PI_RATIO = 0
3588 11:52:01.451487 ===================================
3589 11:52:01.454762 ===================================
3590 11:52:01.458062 memory_type:LPDDR4
3591 11:52:01.458147 GP_NUM : 10
3592 11:52:01.461571 SRAM_EN : 1
3593 11:52:01.464887 MD32_EN : 0
3594 11:52:01.468006 ===================================
3595 11:52:01.468119 [ANA_INIT] >>>>>>>>>>>>>>
3596 11:52:01.471461 <<<<<< [CONFIGURE PHASE]: ANA_TX
3597 11:52:01.474629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3598 11:52:01.478108 ===================================
3599 11:52:01.481393 data_rate = 1200,PCW = 0X5800
3600 11:52:01.484642 ===================================
3601 11:52:01.487849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3602 11:52:01.494637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3603 11:52:01.497787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3604 11:52:01.504422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3605 11:52:01.507919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3606 11:52:01.511196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3607 11:52:01.511283 [ANA_INIT] flow start
3608 11:52:01.514502 [ANA_INIT] PLL >>>>>>>>
3609 11:52:01.518041 [ANA_INIT] PLL <<<<<<<<
3610 11:52:01.521160 [ANA_INIT] MIDPI >>>>>>>>
3611 11:52:01.521244 [ANA_INIT] MIDPI <<<<<<<<
3612 11:52:01.524470 [ANA_INIT] DLL >>>>>>>>
3613 11:52:01.527841 [ANA_INIT] flow end
3614 11:52:01.531192 ============ LP4 DIFF to SE enter ============
3615 11:52:01.534387 ============ LP4 DIFF to SE exit ============
3616 11:52:01.537661 [ANA_INIT] <<<<<<<<<<<<<
3617 11:52:01.541016 [Flow] Enable top DCM control >>>>>
3618 11:52:01.544440 [Flow] Enable top DCM control <<<<<
3619 11:52:01.547815 Enable DLL master slave shuffle
3620 11:52:01.551072 ==============================================================
3621 11:52:01.554359 Gating Mode config
3622 11:52:01.557822 ==============================================================
3623 11:52:01.561163 Config description:
3624 11:52:01.571070 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3625 11:52:01.577516 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3626 11:52:01.581242 SELPH_MODE 0: By rank 1: By Phase
3627 11:52:01.587470 ==============================================================
3628 11:52:01.590745 GAT_TRACK_EN = 1
3629 11:52:01.594161 RX_GATING_MODE = 2
3630 11:52:01.597260 RX_GATING_TRACK_MODE = 2
3631 11:52:01.600622 SELPH_MODE = 1
3632 11:52:01.604186 PICG_EARLY_EN = 1
3633 11:52:01.607190 VALID_LAT_VALUE = 1
3634 11:52:01.610450 ==============================================================
3635 11:52:01.613791 Enter into Gating configuration >>>>
3636 11:52:01.617097 Exit from Gating configuration <<<<
3637 11:52:01.620629 Enter into DVFS_PRE_config >>>>>
3638 11:52:01.633690 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3639 11:52:01.633836 Exit from DVFS_PRE_config <<<<<
3640 11:52:01.637220 Enter into PICG configuration >>>>
3641 11:52:01.640340 Exit from PICG configuration <<<<
3642 11:52:01.643557 [RX_INPUT] configuration >>>>>
3643 11:52:01.646920 [RX_INPUT] configuration <<<<<
3644 11:52:01.653518 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3645 11:52:01.657031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3646 11:52:01.663650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3647 11:52:01.670130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3648 11:52:01.676773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3649 11:52:01.683327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3650 11:52:01.686594 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3651 11:52:01.690038 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3652 11:52:01.693399 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3653 11:52:01.699982 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3654 11:52:01.703293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3655 11:52:01.706582 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3656 11:52:01.709827 ===================================
3657 11:52:01.713218 LPDDR4 DRAM CONFIGURATION
3658 11:52:01.716491 ===================================
3659 11:52:01.719765 EX_ROW_EN[0] = 0x0
3660 11:52:01.719854 EX_ROW_EN[1] = 0x0
3661 11:52:01.723248 LP4Y_EN = 0x0
3662 11:52:01.723334 WORK_FSP = 0x0
3663 11:52:01.726558 WL = 0x2
3664 11:52:01.726671 RL = 0x2
3665 11:52:01.729953 BL = 0x2
3666 11:52:01.730044 RPST = 0x0
3667 11:52:01.733052 RD_PRE = 0x0
3668 11:52:01.733136 WR_PRE = 0x1
3669 11:52:01.736317 WR_PST = 0x0
3670 11:52:01.736401 DBI_WR = 0x0
3671 11:52:01.739644 DBI_RD = 0x0
3672 11:52:01.739731 OTF = 0x1
3673 11:52:01.743140 ===================================
3674 11:52:01.749715 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3675 11:52:01.752850 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3676 11:52:01.756162 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3677 11:52:01.759541 ===================================
3678 11:52:01.762843 LPDDR4 DRAM CONFIGURATION
3679 11:52:01.766171 ===================================
3680 11:52:01.766260 EX_ROW_EN[0] = 0x10
3681 11:52:01.769451 EX_ROW_EN[1] = 0x0
3682 11:52:01.772815 LP4Y_EN = 0x0
3683 11:52:01.772903 WORK_FSP = 0x0
3684 11:52:01.775935 WL = 0x2
3685 11:52:01.776021 RL = 0x2
3686 11:52:01.779393 BL = 0x2
3687 11:52:01.779481 RPST = 0x0
3688 11:52:01.782762 RD_PRE = 0x0
3689 11:52:01.782846 WR_PRE = 0x1
3690 11:52:01.786065 WR_PST = 0x0
3691 11:52:01.786151 DBI_WR = 0x0
3692 11:52:01.789434 DBI_RD = 0x0
3693 11:52:01.789518 OTF = 0x1
3694 11:52:01.792875 ===================================
3695 11:52:01.799456 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3696 11:52:01.803922 nWR fixed to 30
3697 11:52:01.807191 [ModeRegInit_LP4] CH0 RK0
3698 11:52:01.807282 [ModeRegInit_LP4] CH0 RK1
3699 11:52:01.810373 [ModeRegInit_LP4] CH1 RK0
3700 11:52:01.813914 [ModeRegInit_LP4] CH1 RK1
3701 11:52:01.814001 match AC timing 16
3702 11:52:01.820382 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3703 11:52:01.823576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3704 11:52:01.826836 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3705 11:52:01.833679 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3706 11:52:01.836808 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3707 11:52:01.836901 ==
3708 11:52:01.840096 Dram Type= 6, Freq= 0, CH_0, rank 0
3709 11:52:01.843676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3710 11:52:01.843763 ==
3711 11:52:01.850391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3712 11:52:01.856611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3713 11:52:01.860162 [CA 0] Center 35 (5~66) winsize 62
3714 11:52:01.863106 [CA 1] Center 35 (5~66) winsize 62
3715 11:52:01.866800 [CA 2] Center 34 (4~65) winsize 62
3716 11:52:01.870126 [CA 3] Center 34 (4~65) winsize 62
3717 11:52:01.873262 [CA 4] Center 33 (3~64) winsize 62
3718 11:52:01.876935 [CA 5] Center 33 (3~64) winsize 62
3719 11:52:01.877024
3720 11:52:01.879934 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3721 11:52:01.880021
3722 11:52:01.883170 [CATrainingPosCal] consider 1 rank data
3723 11:52:01.886520 u2DelayCellTimex100 = 270/100 ps
3724 11:52:01.889829 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3725 11:52:01.893390 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3726 11:52:01.896498 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3727 11:52:01.900036 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3728 11:52:01.903170 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3729 11:52:01.909969 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3730 11:52:01.910071
3731 11:52:01.913103 CA PerBit enable=1, Macro0, CA PI delay=33
3732 11:52:01.913188
3733 11:52:01.916454 [CBTSetCACLKResult] CA Dly = 33
3734 11:52:01.916545 CS Dly: 4 (0~35)
3735 11:52:01.916611 ==
3736 11:52:01.919739 Dram Type= 6, Freq= 0, CH_0, rank 1
3737 11:52:01.923044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3738 11:52:01.926322 ==
3739 11:52:01.929783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3740 11:52:01.936257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3741 11:52:01.939608 [CA 0] Center 36 (6~66) winsize 61
3742 11:52:01.942838 [CA 1] Center 35 (5~66) winsize 62
3743 11:52:01.946334 [CA 2] Center 34 (4~65) winsize 62
3744 11:52:01.949956 [CA 3] Center 34 (4~65) winsize 62
3745 11:52:01.953053 [CA 4] Center 33 (3~64) winsize 62
3746 11:52:01.956267 [CA 5] Center 33 (3~64) winsize 62
3747 11:52:01.956359
3748 11:52:01.959781 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3749 11:52:01.959868
3750 11:52:01.963141 [CATrainingPosCal] consider 2 rank data
3751 11:52:01.966289 u2DelayCellTimex100 = 270/100 ps
3752 11:52:01.969535 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3753 11:52:01.972847 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3754 11:52:01.976121 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3755 11:52:01.979516 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3756 11:52:01.986201 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3757 11:52:01.989463 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3758 11:52:01.989558
3759 11:52:01.993154 CA PerBit enable=1, Macro0, CA PI delay=33
3760 11:52:01.993241
3761 11:52:01.996236 [CBTSetCACLKResult] CA Dly = 33
3762 11:52:01.996320 CS Dly: 4 (0~36)
3763 11:52:01.996385
3764 11:52:01.999633 ----->DramcWriteLeveling(PI) begin...
3765 11:52:01.999718 ==
3766 11:52:02.002978 Dram Type= 6, Freq= 0, CH_0, rank 0
3767 11:52:02.009641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3768 11:52:02.009739 ==
3769 11:52:02.012762 Write leveling (Byte 0): 30 => 30
3770 11:52:02.012847 Write leveling (Byte 1): 28 => 28
3771 11:52:02.016007 DramcWriteLeveling(PI) end<-----
3772 11:52:02.016092
3773 11:52:02.019370 ==
3774 11:52:02.019454 Dram Type= 6, Freq= 0, CH_0, rank 0
3775 11:52:02.026098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3776 11:52:02.026195 ==
3777 11:52:02.029314 [Gating] SW mode calibration
3778 11:52:02.036054 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3779 11:52:02.039342 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3780 11:52:02.046167 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3781 11:52:02.049325 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3782 11:52:02.052485 0 5 8 | B1->B0 | 3434 3030 | 0 1 | (0 1) (1 1)
3783 11:52:02.059210 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3784 11:52:02.062707 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3785 11:52:02.065858 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3786 11:52:02.072693 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3787 11:52:02.075643 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3788 11:52:02.079034 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 11:52:02.085645 0 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3790 11:52:02.088942 0 6 8 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (0 0)
3791 11:52:02.092279 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3792 11:52:02.098859 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3793 11:52:02.102357 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3794 11:52:02.105479 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3795 11:52:02.112075 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3796 11:52:02.115786 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 11:52:02.118834 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 11:52:02.125309 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 11:52:02.128695 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3800 11:52:02.132409 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3801 11:52:02.135252 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3802 11:52:02.142076 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3803 11:52:02.145109 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3804 11:52:02.148641 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 11:52:02.155143 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 11:52:02.158633 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 11:52:02.162008 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 11:52:02.168469 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 11:52:02.171748 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 11:52:02.175006 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 11:52:02.181940 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 11:52:02.184891 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 11:52:02.188227 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 11:52:02.194853 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 11:52:02.198307 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3816 11:52:02.201495 Total UI for P1: 0, mck2ui 16
3817 11:52:02.204783 best dqsien dly found for B0: ( 0, 9, 10)
3818 11:52:02.208324 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3819 11:52:02.211522 Total UI for P1: 0, mck2ui 16
3820 11:52:02.214986 best dqsien dly found for B1: ( 0, 9, 12)
3821 11:52:02.218182 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3822 11:52:02.221714 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3823 11:52:02.221797
3824 11:52:02.228072 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3825 11:52:02.231246 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3826 11:52:02.234830 [Gating] SW calibration Done
3827 11:52:02.234911 ==
3828 11:52:02.238007 Dram Type= 6, Freq= 0, CH_0, rank 0
3829 11:52:02.241429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3830 11:52:02.241512 ==
3831 11:52:02.241576 RX Vref Scan: 0
3832 11:52:02.244517
3833 11:52:02.244631 RX Vref 0 -> 0, step: 1
3834 11:52:02.244697
3835 11:52:02.247743 RX Delay -230 -> 252, step: 16
3836 11:52:02.251295 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3837 11:52:02.257917 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3838 11:52:02.261155 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3839 11:52:02.264816 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3840 11:52:02.268027 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3841 11:52:02.271147 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3842 11:52:02.278152 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3843 11:52:02.281268 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
3844 11:52:02.284502 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3845 11:52:02.287884 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3846 11:52:02.294578 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3847 11:52:02.297787 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3848 11:52:02.301015 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3849 11:52:02.304462 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3850 11:52:02.311134 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3851 11:52:02.314312 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3852 11:52:02.314394 ==
3853 11:52:02.317907 Dram Type= 6, Freq= 0, CH_0, rank 0
3854 11:52:02.321054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3855 11:52:02.321136 ==
3856 11:52:02.321200 DQS Delay:
3857 11:52:02.324284 DQS0 = 0, DQS1 = 0
3858 11:52:02.324365 DQM Delay:
3859 11:52:02.327627 DQM0 = 41, DQM1 = 33
3860 11:52:02.327707 DQ Delay:
3861 11:52:02.330848 DQ0 =33, DQ1 =33, DQ2 =41, DQ3 =33
3862 11:52:02.334151 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
3863 11:52:02.337505 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3864 11:52:02.341177 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3865 11:52:02.341258
3866 11:52:02.341321
3867 11:52:02.341380 ==
3868 11:52:02.344201 Dram Type= 6, Freq= 0, CH_0, rank 0
3869 11:52:02.347596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3870 11:52:02.350864 ==
3871 11:52:02.350945
3872 11:52:02.351009
3873 11:52:02.351067 TX Vref Scan disable
3874 11:52:02.354312 == TX Byte 0 ==
3875 11:52:02.357810 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3876 11:52:02.364014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3877 11:52:02.364095 == TX Byte 1 ==
3878 11:52:02.367259 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3879 11:52:02.373945 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3880 11:52:02.374029 ==
3881 11:52:02.377421 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 11:52:02.380504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3883 11:52:02.380632 ==
3884 11:52:02.380696
3885 11:52:02.380757
3886 11:52:02.383937 TX Vref Scan disable
3887 11:52:02.387178 == TX Byte 0 ==
3888 11:52:02.390708 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3889 11:52:02.393943 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3890 11:52:02.397218 == TX Byte 1 ==
3891 11:52:02.400384 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3892 11:52:02.403857 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3893 11:52:02.403938
3894 11:52:02.404001 [DATLAT]
3895 11:52:02.407229 Freq=600, CH0 RK0
3896 11:52:02.407311
3897 11:52:02.410498 DATLAT Default: 0x9
3898 11:52:02.410579 0, 0xFFFF, sum = 0
3899 11:52:02.413771 1, 0xFFFF, sum = 0
3900 11:52:02.413854 2, 0xFFFF, sum = 0
3901 11:52:02.417368 3, 0xFFFF, sum = 0
3902 11:52:02.417451 4, 0xFFFF, sum = 0
3903 11:52:02.420367 5, 0xFFFF, sum = 0
3904 11:52:02.420448 6, 0xFFFF, sum = 0
3905 11:52:02.423526 7, 0x0, sum = 1
3906 11:52:02.423608 8, 0x0, sum = 2
3907 11:52:02.423674 9, 0x0, sum = 3
3908 11:52:02.426885 10, 0x0, sum = 4
3909 11:52:02.426968 best_step = 8
3910 11:52:02.427031
3911 11:52:02.430326 ==
3912 11:52:02.430408 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 11:52:02.436842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3914 11:52:02.436956 ==
3915 11:52:02.437049 RX Vref Scan: 1
3916 11:52:02.437131
3917 11:52:02.440144 RX Vref 0 -> 0, step: 1
3918 11:52:02.440254
3919 11:52:02.443532 RX Delay -195 -> 252, step: 8
3920 11:52:02.443620
3921 11:52:02.446686 Set Vref, RX VrefLevel [Byte0]: 46
3922 11:52:02.449984 [Byte1]: 47
3923 11:52:02.450071
3924 11:52:02.453618 Final RX Vref Byte 0 = 46 to rank0
3925 11:52:02.456630 Final RX Vref Byte 1 = 47 to rank0
3926 11:52:02.460169 Final RX Vref Byte 0 = 46 to rank1
3927 11:52:02.463323 Final RX Vref Byte 1 = 47 to rank1==
3928 11:52:02.466509 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 11:52:02.469824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 11:52:02.473393 ==
3931 11:52:02.473480 DQS Delay:
3932 11:52:02.473545 DQS0 = 0, DQS1 = 0
3933 11:52:02.476524 DQM Delay:
3934 11:52:02.476620 DQM0 = 40, DQM1 = 30
3935 11:52:02.476685 DQ Delay:
3936 11:52:02.479876 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3937 11:52:02.483449 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3938 11:52:02.486761 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3939 11:52:02.489967 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3940 11:52:02.490045
3941 11:52:02.490134
3942 11:52:02.500073 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3943 11:52:02.503253 CH0 RK0: MR19=808, MR18=5D5D
3944 11:52:02.509957 CH0_RK0: MR19=0x808, MR18=0x5D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
3945 11:52:02.510042
3946 11:52:02.513272 ----->DramcWriteLeveling(PI) begin...
3947 11:52:02.513355 ==
3948 11:52:02.516389 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 11:52:02.519725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 11:52:02.519807 ==
3951 11:52:02.523025 Write leveling (Byte 0): 30 => 30
3952 11:52:02.526375 Write leveling (Byte 1): 30 => 30
3953 11:52:02.529927 DramcWriteLeveling(PI) end<-----
3954 11:52:02.530012
3955 11:52:02.530077 ==
3956 11:52:02.533303 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 11:52:02.536342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3958 11:52:02.536424 ==
3959 11:52:02.539734 [Gating] SW mode calibration
3960 11:52:02.546307 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3961 11:52:02.553133 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3962 11:52:02.556336 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 11:52:02.559511 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 11:52:02.566158 0 5 8 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 1)
3965 11:52:02.569388 0 5 12 | B1->B0 | 2929 2626 | 1 0 | (1 0) (0 0)
3966 11:52:02.572528 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 11:52:02.579313 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 11:52:02.582644 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 11:52:02.585951 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 11:52:02.592676 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 11:52:02.595838 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 11:52:02.599250 0 6 8 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
3973 11:52:02.605874 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3974 11:52:02.609229 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 11:52:02.612450 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 11:52:02.618980 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 11:52:02.622384 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 11:52:02.625840 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 11:52:02.632451 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 11:52:02.635530 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3981 11:52:02.638865 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3982 11:52:02.645510 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 11:52:02.648658 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 11:52:02.652146 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 11:52:02.658689 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 11:52:02.661962 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 11:52:02.665357 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:52:02.671831 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 11:52:02.675505 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 11:52:02.678633 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 11:52:02.685198 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:52:02.688648 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:52:02.691978 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:52:02.698524 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:52:02.701749 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:52:02.705190 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3997 11:52:02.711903 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:52:02.711985 Total UI for P1: 0, mck2ui 16
3999 11:52:02.715155 best dqsien dly found for B0: ( 0, 9, 8)
4000 11:52:02.718445 Total UI for P1: 0, mck2ui 16
4001 11:52:02.721918 best dqsien dly found for B1: ( 0, 9, 10)
4002 11:52:02.725252 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4003 11:52:02.728425 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4004 11:52:02.731692
4005 11:52:02.735249 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4006 11:52:02.738221 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4007 11:52:02.741710 [Gating] SW calibration Done
4008 11:52:02.741792 ==
4009 11:52:02.745167 Dram Type= 6, Freq= 0, CH_0, rank 1
4010 11:52:02.748262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4011 11:52:02.748344 ==
4012 11:52:02.748408 RX Vref Scan: 0
4013 11:52:02.751654
4014 11:52:02.751735 RX Vref 0 -> 0, step: 1
4015 11:52:02.751799
4016 11:52:02.754965 RX Delay -230 -> 252, step: 16
4017 11:52:02.758416 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4018 11:52:02.765083 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4019 11:52:02.768488 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4020 11:52:02.771472 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4021 11:52:02.774725 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4022 11:52:02.778548 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4023 11:52:02.784734 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4024 11:52:02.788073 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4025 11:52:02.791429 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4026 11:52:02.794811 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4027 11:52:02.801365 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4028 11:52:02.804754 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4029 11:52:02.807972 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4030 11:52:02.811375 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4031 11:52:02.817960 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4032 11:52:02.821507 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4033 11:52:02.821589 ==
4034 11:52:02.824796 Dram Type= 6, Freq= 0, CH_0, rank 1
4035 11:52:02.828179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4036 11:52:02.828261 ==
4037 11:52:02.828325 DQS Delay:
4038 11:52:02.831585 DQS0 = 0, DQS1 = 0
4039 11:52:02.831667 DQM Delay:
4040 11:52:02.834647 DQM0 = 42, DQM1 = 31
4041 11:52:02.834729 DQ Delay:
4042 11:52:02.838115 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4043 11:52:02.841354 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4044 11:52:02.844908 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4045 11:52:02.848059 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4046 11:52:02.848141
4047 11:52:02.848205
4048 11:52:02.848264 ==
4049 11:52:02.851164 Dram Type= 6, Freq= 0, CH_0, rank 1
4050 11:52:02.854624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4051 11:52:02.857716 ==
4052 11:52:02.857797
4053 11:52:02.857861
4054 11:52:02.857921 TX Vref Scan disable
4055 11:52:02.861209 == TX Byte 0 ==
4056 11:52:02.864335 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4057 11:52:02.871100 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4058 11:52:02.871219 == TX Byte 1 ==
4059 11:52:02.874507 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4060 11:52:02.877776 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4061 11:52:02.881163 ==
4062 11:52:02.884270 Dram Type= 6, Freq= 0, CH_0, rank 1
4063 11:52:02.887919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4064 11:52:02.888001 ==
4065 11:52:02.888066
4066 11:52:02.888126
4067 11:52:02.890989 TX Vref Scan disable
4068 11:52:02.891070 == TX Byte 0 ==
4069 11:52:02.897747 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4070 11:52:02.900962 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4071 11:52:02.904095 == TX Byte 1 ==
4072 11:52:02.907378 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4073 11:52:02.911153 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4074 11:52:02.911290
4075 11:52:02.911416 [DATLAT]
4076 11:52:02.914091 Freq=600, CH0 RK1
4077 11:52:02.914174
4078 11:52:02.914240 DATLAT Default: 0x8
4079 11:52:02.917463 0, 0xFFFF, sum = 0
4080 11:52:02.920664 1, 0xFFFF, sum = 0
4081 11:52:02.920749 2, 0xFFFF, sum = 0
4082 11:52:02.923914 3, 0xFFFF, sum = 0
4083 11:52:02.923998 4, 0xFFFF, sum = 0
4084 11:52:02.927321 5, 0xFFFF, sum = 0
4085 11:52:02.927406 6, 0xFFFF, sum = 0
4086 11:52:02.930440 7, 0x0, sum = 1
4087 11:52:02.930528 8, 0x0, sum = 2
4088 11:52:02.933627 9, 0x0, sum = 3
4089 11:52:02.933712 10, 0x0, sum = 4
4090 11:52:02.933779 best_step = 8
4091 11:52:02.933843
4092 11:52:02.937058 ==
4093 11:52:02.937140 Dram Type= 6, Freq= 0, CH_0, rank 1
4094 11:52:02.944259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4095 11:52:02.944346 ==
4096 11:52:02.944412 RX Vref Scan: 0
4097 11:52:02.944473
4098 11:52:02.947279 RX Vref 0 -> 0, step: 1
4099 11:52:02.947362
4100 11:52:02.950362 RX Delay -195 -> 252, step: 8
4101 11:52:02.956931 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4102 11:52:02.960304 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4103 11:52:02.963567 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4104 11:52:02.966848 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4105 11:52:02.970123 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4106 11:52:02.976999 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4107 11:52:02.980298 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4108 11:52:02.983484 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4109 11:52:02.986620 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4110 11:52:02.993271 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4111 11:52:02.996530 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4112 11:52:02.999999 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4113 11:52:03.003197 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4114 11:52:03.009753 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4115 11:52:03.013221 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4116 11:52:03.016670 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4117 11:52:03.016755 ==
4118 11:52:03.019625 Dram Type= 6, Freq= 0, CH_0, rank 1
4119 11:52:03.022893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4120 11:52:03.022978 ==
4121 11:52:03.026137 DQS Delay:
4122 11:52:03.026223 DQS0 = 0, DQS1 = 0
4123 11:52:03.029747 DQM Delay:
4124 11:52:03.029831 DQM0 = 40, DQM1 = 31
4125 11:52:03.029897 DQ Delay:
4126 11:52:03.032792 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4127 11:52:03.036435 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4128 11:52:03.039583 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4129 11:52:03.042896 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4130 11:52:03.042980
4131 11:52:03.046155
4132 11:52:03.052845 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4133 11:52:03.056136 CH0 RK1: MR19=808, MR18=6E6E
4134 11:52:03.062822 CH0_RK1: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4135 11:52:03.065998 [RxdqsGatingPostProcess] freq 600
4136 11:52:03.069512 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4137 11:52:03.072634 Pre-setting of DQS Precalculation
4138 11:52:03.079201 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4139 11:52:03.079302 ==
4140 11:52:03.082489 Dram Type= 6, Freq= 0, CH_1, rank 0
4141 11:52:03.086044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4142 11:52:03.086140 ==
4143 11:52:03.092534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4144 11:52:03.095731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4145 11:52:03.099904 [CA 0] Center 35 (5~66) winsize 62
4146 11:52:03.103055 [CA 1] Center 34 (4~65) winsize 62
4147 11:52:03.106268 [CA 2] Center 33 (3~64) winsize 62
4148 11:52:03.109648 [CA 3] Center 33 (3~64) winsize 62
4149 11:52:03.112986 [CA 4] Center 33 (2~64) winsize 63
4150 11:52:03.116390 [CA 5] Center 33 (2~64) winsize 63
4151 11:52:03.116490
4152 11:52:03.119887 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4153 11:52:03.119978
4154 11:52:03.123110 [CATrainingPosCal] consider 1 rank data
4155 11:52:03.126271 u2DelayCellTimex100 = 270/100 ps
4156 11:52:03.129755 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4157 11:52:03.133138 CA1 delay=34 (4~65),Diff = 1 PI (9 cell)
4158 11:52:03.139637 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4159 11:52:03.143041 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4160 11:52:03.146014 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4161 11:52:03.149425 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4162 11:52:03.149584
4163 11:52:03.152712 CA PerBit enable=1, Macro0, CA PI delay=33
4164 11:52:03.152816
4165 11:52:03.156049 [CBTSetCACLKResult] CA Dly = 33
4166 11:52:03.156165 CS Dly: 5 (0~36)
4167 11:52:03.159515 ==
4168 11:52:03.162750 Dram Type= 6, Freq= 0, CH_1, rank 1
4169 11:52:03.165925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4170 11:52:03.166011 ==
4171 11:52:03.169316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4172 11:52:03.176114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4173 11:52:03.179619 [CA 0] Center 35 (5~66) winsize 62
4174 11:52:03.182920 [CA 1] Center 34 (4~65) winsize 62
4175 11:52:03.186304 [CA 2] Center 33 (3~64) winsize 62
4176 11:52:03.189610 [CA 3] Center 33 (3~64) winsize 62
4177 11:52:03.193094 [CA 4] Center 32 (2~63) winsize 62
4178 11:52:03.196367 [CA 5] Center 32 (2~63) winsize 62
4179 11:52:03.196449
4180 11:52:03.199688 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4181 11:52:03.199770
4182 11:52:03.203387 [CATrainingPosCal] consider 2 rank data
4183 11:52:03.206183 u2DelayCellTimex100 = 270/100 ps
4184 11:52:03.209534 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4185 11:52:03.216334 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4186 11:52:03.219682 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4187 11:52:03.222699 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4188 11:52:03.226180 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4189 11:52:03.229547 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4190 11:52:03.229628
4191 11:52:03.232837 CA PerBit enable=1, Macro0, CA PI delay=32
4192 11:52:03.232921
4193 11:52:03.236121 [CBTSetCACLKResult] CA Dly = 32
4194 11:52:03.236201 CS Dly: 5 (0~36)
4195 11:52:03.239618
4196 11:52:03.242830 ----->DramcWriteLeveling(PI) begin...
4197 11:52:03.242914 ==
4198 11:52:03.245953 Dram Type= 6, Freq= 0, CH_1, rank 0
4199 11:52:03.249228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4200 11:52:03.249310 ==
4201 11:52:03.252708 Write leveling (Byte 0): 28 => 28
4202 11:52:03.255845 Write leveling (Byte 1): 27 => 27
4203 11:52:03.259168 DramcWriteLeveling(PI) end<-----
4204 11:52:03.259249
4205 11:52:03.259313 ==
4206 11:52:03.262643 Dram Type= 6, Freq= 0, CH_1, rank 0
4207 11:52:03.265938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4208 11:52:03.266027 ==
4209 11:52:03.269297 [Gating] SW mode calibration
4210 11:52:03.275850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 11:52:03.282385 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4212 11:52:03.285756 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 11:52:03.289055 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4214 11:52:03.296019 0 5 8 | B1->B0 | 2f2f 2323 | 1 1 | (1 1) (1 0)
4215 11:52:03.299349 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 11:52:03.302366 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 11:52:03.309102 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 11:52:03.312421 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 11:52:03.315669 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 11:52:03.318952 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:52:03.326067 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4222 11:52:03.328909 0 6 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4223 11:52:03.332331 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 11:52:03.338886 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 11:52:03.342271 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 11:52:03.345475 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:52:03.352084 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 11:52:03.355478 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:52:03.358701 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4230 11:52:03.365496 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 11:52:03.368707 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 11:52:03.372079 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:52:03.378694 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 11:52:03.381997 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:52:03.385571 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:52:03.392000 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:52:03.395344 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:52:03.398583 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:52:03.405268 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:52:03.408377 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:52:03.411854 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:52:03.418372 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:52:03.421708 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:52:03.425122 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:52:03.431787 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4246 11:52:03.435301 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4247 11:52:03.438369 Total UI for P1: 0, mck2ui 16
4248 11:52:03.441870 best dqsien dly found for B0: ( 0, 9, 4)
4249 11:52:03.444995 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:52:03.448170 Total UI for P1: 0, mck2ui 16
4251 11:52:03.451633 best dqsien dly found for B1: ( 0, 9, 8)
4252 11:52:03.454994 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4253 11:52:03.458369 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4254 11:52:03.458450
4255 11:52:03.461525 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4256 11:52:03.468250 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4257 11:52:03.468333 [Gating] SW calibration Done
4258 11:52:03.468397 ==
4259 11:52:03.471672 Dram Type= 6, Freq= 0, CH_1, rank 0
4260 11:52:03.478084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4261 11:52:03.478168 ==
4262 11:52:03.478232 RX Vref Scan: 0
4263 11:52:03.478293
4264 11:52:03.481481 RX Vref 0 -> 0, step: 1
4265 11:52:03.481562
4266 11:52:03.484767 RX Delay -230 -> 252, step: 16
4267 11:52:03.487977 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4268 11:52:03.491619 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4269 11:52:03.498096 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4270 11:52:03.501394 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4271 11:52:03.504631 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4272 11:52:03.508025 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4273 11:52:03.511518 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4274 11:52:03.518127 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4275 11:52:03.521485 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4276 11:52:03.524743 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4277 11:52:03.528294 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4278 11:52:03.534879 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4279 11:52:03.537977 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4280 11:52:03.541484 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4281 11:52:03.544622 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4282 11:52:03.551183 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4283 11:52:03.551263 ==
4284 11:52:03.554465 Dram Type= 6, Freq= 0, CH_1, rank 0
4285 11:52:03.557948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4286 11:52:03.558030 ==
4287 11:52:03.558094 DQS Delay:
4288 11:52:03.561174 DQS0 = 0, DQS1 = 0
4289 11:52:03.561255 DQM Delay:
4290 11:52:03.564441 DQM0 = 39, DQM1 = 32
4291 11:52:03.564551 DQ Delay:
4292 11:52:03.567815 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4293 11:52:03.571103 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4294 11:52:03.574325 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4295 11:52:03.577729 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4296 11:52:03.577809
4297 11:52:03.577873
4298 11:52:03.577932 ==
4299 11:52:03.581114 Dram Type= 6, Freq= 0, CH_1, rank 0
4300 11:52:03.584595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4301 11:52:03.584678 ==
4302 11:52:03.584742
4303 11:52:03.584801
4304 11:52:03.587940 TX Vref Scan disable
4305 11:52:03.591150 == TX Byte 0 ==
4306 11:52:03.594523 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4307 11:52:03.597708 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4308 11:52:03.601047 == TX Byte 1 ==
4309 11:52:03.604370 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4310 11:52:03.607869 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4311 11:52:03.607951 ==
4312 11:52:03.611304 Dram Type= 6, Freq= 0, CH_1, rank 0
4313 11:52:03.617406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4314 11:52:03.617491 ==
4315 11:52:03.617555
4316 11:52:03.617614
4317 11:52:03.617671 TX Vref Scan disable
4318 11:52:03.622110 == TX Byte 0 ==
4319 11:52:03.625412 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4320 11:52:03.631652 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4321 11:52:03.631739 == TX Byte 1 ==
4322 11:52:03.634962 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4323 11:52:03.641724 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4324 11:52:03.641807
4325 11:52:03.641871 [DATLAT]
4326 11:52:03.641930 Freq=600, CH1 RK0
4327 11:52:03.641988
4328 11:52:03.644940 DATLAT Default: 0x9
4329 11:52:03.645022 0, 0xFFFF, sum = 0
4330 11:52:03.648184 1, 0xFFFF, sum = 0
4331 11:52:03.651646 2, 0xFFFF, sum = 0
4332 11:52:03.651729 3, 0xFFFF, sum = 0
4333 11:52:03.655120 4, 0xFFFF, sum = 0
4334 11:52:03.655202 5, 0xFFFF, sum = 0
4335 11:52:03.658159 6, 0xFFFF, sum = 0
4336 11:52:03.658243 7, 0x0, sum = 1
4337 11:52:03.661541 8, 0x0, sum = 2
4338 11:52:03.661623 9, 0x0, sum = 3
4339 11:52:03.661688 10, 0x0, sum = 4
4340 11:52:03.664860 best_step = 8
4341 11:52:03.664940
4342 11:52:03.665003 ==
4343 11:52:03.668224 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 11:52:03.671635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4345 11:52:03.671716 ==
4346 11:52:03.674902 RX Vref Scan: 1
4347 11:52:03.674982
4348 11:52:03.675046 RX Vref 0 -> 0, step: 1
4349 11:52:03.675105
4350 11:52:03.678319 RX Delay -195 -> 252, step: 8
4351 11:52:03.678400
4352 11:52:03.681457 Set Vref, RX VrefLevel [Byte0]: 52
4353 11:52:03.684556 [Byte1]: 49
4354 11:52:03.689203
4355 11:52:03.689285 Final RX Vref Byte 0 = 52 to rank0
4356 11:52:03.692192 Final RX Vref Byte 1 = 49 to rank0
4357 11:52:03.695612 Final RX Vref Byte 0 = 52 to rank1
4358 11:52:03.698733 Final RX Vref Byte 1 = 49 to rank1==
4359 11:52:03.701982 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 11:52:03.708836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4361 11:52:03.708919 ==
4362 11:52:03.708983 DQS Delay:
4363 11:52:03.709042 DQS0 = 0, DQS1 = 0
4364 11:52:03.711961 DQM Delay:
4365 11:52:03.712041 DQM0 = 37, DQM1 = 29
4366 11:52:03.715401 DQ Delay:
4367 11:52:03.718678 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4368 11:52:03.722037 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4369 11:52:03.725300 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4370 11:52:03.728555 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4371 11:52:03.728636
4372 11:52:03.728699
4373 11:52:03.735104 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4374 11:52:03.738484 CH1 RK0: MR19=808, MR18=7F7F
4375 11:52:03.745081 CH1_RK0: MR19=0x808, MR18=0x7F7F, DQSOSC=386, MR23=63, INC=176, DEC=117
4376 11:52:03.745169
4377 11:52:03.748314 ----->DramcWriteLeveling(PI) begin...
4378 11:52:03.748396 ==
4379 11:52:03.752016 Dram Type= 6, Freq= 0, CH_1, rank 1
4380 11:52:03.755269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 11:52:03.755352 ==
4382 11:52:03.758657 Write leveling (Byte 0): 27 => 27
4383 11:52:03.761833 Write leveling (Byte 1): 27 => 27
4384 11:52:03.765297 DramcWriteLeveling(PI) end<-----
4385 11:52:03.765379
4386 11:52:03.765442 ==
4387 11:52:03.768364 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 11:52:03.771798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4389 11:52:03.771879 ==
4390 11:52:03.775183 [Gating] SW mode calibration
4391 11:52:03.781768 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4392 11:52:03.788527 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4393 11:52:03.791838 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4394 11:52:03.798488 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4395 11:52:03.801658 0 5 8 | B1->B0 | 3131 2525 | 1 0 | (0 0) (1 1)
4396 11:52:03.805003 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 11:52:03.811732 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 11:52:03.814819 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 11:52:03.818267 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 11:52:03.824689 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 11:52:03.828103 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 11:52:03.831453 0 6 4 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
4403 11:52:03.834841 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4404 11:52:03.841404 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 11:52:03.844483 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 11:52:03.847871 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 11:52:03.854460 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 11:52:03.857769 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 11:52:03.861093 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 11:52:03.867721 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4411 11:52:03.871235 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 11:52:03.874575 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:52:03.881102 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:52:03.884346 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:52:03.887638 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:52:03.894361 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:52:03.897854 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:52:03.901105 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:52:03.907609 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:52:03.910786 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:52:03.914063 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:52:03.920735 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:52:03.924110 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:52:03.927342 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:52:03.933954 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:52:03.937454 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4427 11:52:03.940720 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:52:03.943960 Total UI for P1: 0, mck2ui 16
4429 11:52:03.947215 best dqsien dly found for B0: ( 0, 9, 4)
4430 11:52:03.950555 Total UI for P1: 0, mck2ui 16
4431 11:52:03.953922 best dqsien dly found for B1: ( 0, 9, 6)
4432 11:52:03.957135 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4433 11:52:03.960458 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4434 11:52:03.960556
4435 11:52:03.966973 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4436 11:52:03.970435 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4437 11:52:03.970518 [Gating] SW calibration Done
4438 11:52:03.973667 ==
4439 11:52:03.976935 Dram Type= 6, Freq= 0, CH_1, rank 1
4440 11:52:03.980284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4441 11:52:03.980367 ==
4442 11:52:03.980432 RX Vref Scan: 0
4443 11:52:03.980492
4444 11:52:03.983632 RX Vref 0 -> 0, step: 1
4445 11:52:03.983715
4446 11:52:03.987088 RX Delay -230 -> 252, step: 16
4447 11:52:03.990434 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4448 11:52:03.993917 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4449 11:52:04.000255 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4450 11:52:04.003569 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4451 11:52:04.007302 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4452 11:52:04.010395 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4453 11:52:04.013614 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4454 11:52:04.020273 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4455 11:52:04.023867 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4456 11:52:04.027006 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4457 11:52:04.030184 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4458 11:52:04.036824 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4459 11:52:04.040264 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4460 11:52:04.043650 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4461 11:52:04.046807 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4462 11:52:04.053408 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4463 11:52:04.053495 ==
4464 11:52:04.056759 Dram Type= 6, Freq= 0, CH_1, rank 1
4465 11:52:04.059992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4466 11:52:04.060075 ==
4467 11:52:04.060139 DQS Delay:
4468 11:52:04.063357 DQS0 = 0, DQS1 = 0
4469 11:52:04.063439 DQM Delay:
4470 11:52:04.066664 DQM0 = 40, DQM1 = 33
4471 11:52:04.066746 DQ Delay:
4472 11:52:04.069957 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4473 11:52:04.073070 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4474 11:52:04.076487 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4475 11:52:04.079793 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4476 11:52:04.079874
4477 11:52:04.079938
4478 11:52:04.079998 ==
4479 11:52:04.083173 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 11:52:04.086476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4481 11:52:04.086559 ==
4482 11:52:04.089844
4483 11:52:04.089924
4484 11:52:04.089988 TX Vref Scan disable
4485 11:52:04.093248 == TX Byte 0 ==
4486 11:52:04.096459 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4487 11:52:04.099833 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4488 11:52:04.103418 == TX Byte 1 ==
4489 11:52:04.106573 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4490 11:52:04.109770 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4491 11:52:04.109853 ==
4492 11:52:04.112985 Dram Type= 6, Freq= 0, CH_1, rank 1
4493 11:52:04.119645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4494 11:52:04.119729 ==
4495 11:52:04.119795
4496 11:52:04.119855
4497 11:52:04.122931 TX Vref Scan disable
4498 11:52:04.123017 == TX Byte 0 ==
4499 11:52:04.129713 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4500 11:52:04.132918 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4501 11:52:04.133004 == TX Byte 1 ==
4502 11:52:04.139370 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4503 11:52:04.142646 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4504 11:52:04.142729
4505 11:52:04.142794 [DATLAT]
4506 11:52:04.146008 Freq=600, CH1 RK1
4507 11:52:04.146090
4508 11:52:04.146155 DATLAT Default: 0x8
4509 11:52:04.149455 0, 0xFFFF, sum = 0
4510 11:52:04.149539 1, 0xFFFF, sum = 0
4511 11:52:04.152797 2, 0xFFFF, sum = 0
4512 11:52:04.152880 3, 0xFFFF, sum = 0
4513 11:52:04.156052 4, 0xFFFF, sum = 0
4514 11:52:04.156134 5, 0xFFFF, sum = 0
4515 11:52:04.159283 6, 0xFFFF, sum = 0
4516 11:52:04.159367 7, 0x0, sum = 1
4517 11:52:04.162802 8, 0x0, sum = 2
4518 11:52:04.162886 9, 0x0, sum = 3
4519 11:52:04.166058 10, 0x0, sum = 4
4520 11:52:04.166140 best_step = 8
4521 11:52:04.166205
4522 11:52:04.166265 ==
4523 11:52:04.169315 Dram Type= 6, Freq= 0, CH_1, rank 1
4524 11:52:04.175982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4525 11:52:04.176067 ==
4526 11:52:04.176132 RX Vref Scan: 0
4527 11:52:04.176192
4528 11:52:04.179239 RX Vref 0 -> 0, step: 1
4529 11:52:04.179320
4530 11:52:04.182694 RX Delay -195 -> 252, step: 8
4531 11:52:04.186086 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4532 11:52:04.192425 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4533 11:52:04.195755 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4534 11:52:04.199114 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4535 11:52:04.202526 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4536 11:52:04.205867 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4537 11:52:04.212179 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4538 11:52:04.215596 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4539 11:52:04.218864 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4540 11:52:04.222202 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4541 11:52:04.228716 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4542 11:52:04.232161 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4543 11:52:04.235650 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4544 11:52:04.238711 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4545 11:52:04.245257 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4546 11:52:04.248416 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4547 11:52:04.248502 ==
4548 11:52:04.252151 Dram Type= 6, Freq= 0, CH_1, rank 1
4549 11:52:04.255221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4550 11:52:04.255305 ==
4551 11:52:04.258399 DQS Delay:
4552 11:52:04.258481 DQS0 = 0, DQS1 = 0
4553 11:52:04.258545 DQM Delay:
4554 11:52:04.261995 DQM0 = 36, DQM1 = 30
4555 11:52:04.262076 DQ Delay:
4556 11:52:04.265328 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4557 11:52:04.268481 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4558 11:52:04.272001 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4559 11:52:04.275039 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4560 11:52:04.275120
4561 11:52:04.275185
4562 11:52:04.284928 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4563 11:52:04.288213 CH1 RK1: MR19=808, MR18=6161
4564 11:52:04.291463 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4565 11:52:04.294968 [RxdqsGatingPostProcess] freq 600
4566 11:52:04.301691 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4567 11:52:04.304716 Pre-setting of DQS Precalculation
4568 11:52:04.308296 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4569 11:52:04.317917 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4570 11:52:04.324618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4571 11:52:04.324711
4572 11:52:04.324777
4573 11:52:04.327922 [Calibration Summary] 1200 Mbps
4574 11:52:04.328004 CH 0, Rank 0
4575 11:52:04.331530 SW Impedance : PASS
4576 11:52:04.331612 DUTY Scan : NO K
4577 11:52:04.334388 ZQ Calibration : PASS
4578 11:52:04.337811 Jitter Meter : NO K
4579 11:52:04.337895 CBT Training : PASS
4580 11:52:04.341338 Write leveling : PASS
4581 11:52:04.344432 RX DQS gating : PASS
4582 11:52:04.344540 RX DQ/DQS(RDDQC) : PASS
4583 11:52:04.347795 TX DQ/DQS : PASS
4584 11:52:04.351064 RX DATLAT : PASS
4585 11:52:04.351146 RX DQ/DQS(Engine): PASS
4586 11:52:04.354519 TX OE : NO K
4587 11:52:04.354601 All Pass.
4588 11:52:04.354666
4589 11:52:04.357792 CH 0, Rank 1
4590 11:52:04.357873 SW Impedance : PASS
4591 11:52:04.361029 DUTY Scan : NO K
4592 11:52:04.364329 ZQ Calibration : PASS
4593 11:52:04.364414 Jitter Meter : NO K
4594 11:52:04.367657 CBT Training : PASS
4595 11:52:04.367738 Write leveling : PASS
4596 11:52:04.370904 RX DQS gating : PASS
4597 11:52:04.374375 RX DQ/DQS(RDDQC) : PASS
4598 11:52:04.374496 TX DQ/DQS : PASS
4599 11:52:04.377445 RX DATLAT : PASS
4600 11:52:04.381015 RX DQ/DQS(Engine): PASS
4601 11:52:04.381097 TX OE : NO K
4602 11:52:04.384145 All Pass.
4603 11:52:04.384227
4604 11:52:04.384291 CH 1, Rank 0
4605 11:52:04.387176 SW Impedance : PASS
4606 11:52:04.387258 DUTY Scan : NO K
4607 11:52:04.390614 ZQ Calibration : PASS
4608 11:52:04.393954 Jitter Meter : NO K
4609 11:52:04.394038 CBT Training : PASS
4610 11:52:04.397445 Write leveling : PASS
4611 11:52:04.400667 RX DQS gating : PASS
4612 11:52:04.400751 RX DQ/DQS(RDDQC) : PASS
4613 11:52:04.403981 TX DQ/DQS : PASS
4614 11:52:04.407192 RX DATLAT : PASS
4615 11:52:04.407276 RX DQ/DQS(Engine): PASS
4616 11:52:04.410659 TX OE : NO K
4617 11:52:04.410742 All Pass.
4618 11:52:04.410807
4619 11:52:04.413995 CH 1, Rank 1
4620 11:52:04.414077 SW Impedance : PASS
4621 11:52:04.417402 DUTY Scan : NO K
4622 11:52:04.421044 ZQ Calibration : PASS
4623 11:52:04.421129 Jitter Meter : NO K
4624 11:52:04.423842 CBT Training : PASS
4625 11:52:04.427436 Write leveling : PASS
4626 11:52:04.427520 RX DQS gating : PASS
4627 11:52:04.430628 RX DQ/DQS(RDDQC) : PASS
4628 11:52:04.430710 TX DQ/DQS : PASS
4629 11:52:04.433998 RX DATLAT : PASS
4630 11:52:04.437391 RX DQ/DQS(Engine): PASS
4631 11:52:04.437477 TX OE : NO K
4632 11:52:04.440436 All Pass.
4633 11:52:04.440544
4634 11:52:04.440625 DramC Write-DBI off
4635 11:52:04.443578 PER_BANK_REFRESH: Hybrid Mode
4636 11:52:04.446882 TX_TRACKING: ON
4637 11:52:04.453762 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4638 11:52:04.456946 [FAST_K] Save calibration result to emmc
4639 11:52:04.463404 dramc_set_vcore_voltage set vcore to 662500
4640 11:52:04.463492 Read voltage for 933, 3
4641 11:52:04.463557 Vio18 = 0
4642 11:52:04.466918 Vcore = 662500
4643 11:52:04.467000 Vdram = 0
4644 11:52:04.467064 Vddq = 0
4645 11:52:04.470020 Vmddr = 0
4646 11:52:04.473357 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4647 11:52:04.480053 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4648 11:52:04.483336 MEM_TYPE=3, freq_sel=17
4649 11:52:04.483424 sv_algorithm_assistance_LP4_1600
4650 11:52:04.489806 ============ PULL DRAM RESETB DOWN ============
4651 11:52:04.493138 ========== PULL DRAM RESETB DOWN end =========
4652 11:52:04.496393 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4653 11:52:04.499806 ===================================
4654 11:52:04.503295 LPDDR4 DRAM CONFIGURATION
4655 11:52:04.506563 ===================================
4656 11:52:04.509715 EX_ROW_EN[0] = 0x0
4657 11:52:04.509799 EX_ROW_EN[1] = 0x0
4658 11:52:04.512933 LP4Y_EN = 0x0
4659 11:52:04.513014 WORK_FSP = 0x0
4660 11:52:04.516281 WL = 0x3
4661 11:52:04.516361 RL = 0x3
4662 11:52:04.519745 BL = 0x2
4663 11:52:04.519826 RPST = 0x0
4664 11:52:04.522950 RD_PRE = 0x0
4665 11:52:04.523032 WR_PRE = 0x1
4666 11:52:04.526315 WR_PST = 0x0
4667 11:52:04.526397 DBI_WR = 0x0
4668 11:52:04.529586 DBI_RD = 0x0
4669 11:52:04.532930 OTF = 0x1
4670 11:52:04.536088 ===================================
4671 11:52:04.539674 ===================================
4672 11:52:04.539760 ANA top config
4673 11:52:04.543150 ===================================
4674 11:52:04.546398 DLL_ASYNC_EN = 0
4675 11:52:04.546481 ALL_SLAVE_EN = 1
4676 11:52:04.549437 NEW_RANK_MODE = 1
4677 11:52:04.552649 DLL_IDLE_MODE = 1
4678 11:52:04.556121 LP45_APHY_COMB_EN = 1
4679 11:52:04.559206 TX_ODT_DIS = 1
4680 11:52:04.559292 NEW_8X_MODE = 1
4681 11:52:04.562814 ===================================
4682 11:52:04.565871 ===================================
4683 11:52:04.569213 data_rate = 1866
4684 11:52:04.572706 CKR = 1
4685 11:52:04.575768 DQ_P2S_RATIO = 8
4686 11:52:04.579011 ===================================
4687 11:52:04.582520 CA_P2S_RATIO = 8
4688 11:52:04.585604 DQ_CA_OPEN = 0
4689 11:52:04.585690 DQ_SEMI_OPEN = 0
4690 11:52:04.588989 CA_SEMI_OPEN = 0
4691 11:52:04.592389 CA_FULL_RATE = 0
4692 11:52:04.595618 DQ_CKDIV4_EN = 1
4693 11:52:04.598895 CA_CKDIV4_EN = 1
4694 11:52:04.602212 CA_PREDIV_EN = 0
4695 11:52:04.602297 PH8_DLY = 0
4696 11:52:04.605652 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4697 11:52:04.608628 DQ_AAMCK_DIV = 4
4698 11:52:04.612105 CA_AAMCK_DIV = 4
4699 11:52:04.615366 CA_ADMCK_DIV = 4
4700 11:52:04.618728 DQ_TRACK_CA_EN = 0
4701 11:52:04.622081 CA_PICK = 933
4702 11:52:04.622168 CA_MCKIO = 933
4703 11:52:04.625279 MCKIO_SEMI = 0
4704 11:52:04.628818 PLL_FREQ = 3732
4705 11:52:04.632048 DQ_UI_PI_RATIO = 32
4706 11:52:04.635265 CA_UI_PI_RATIO = 0
4707 11:52:04.638761 ===================================
4708 11:52:04.641697 ===================================
4709 11:52:04.645153 memory_type:LPDDR4
4710 11:52:04.645238 GP_NUM : 10
4711 11:52:04.648302 SRAM_EN : 1
4712 11:52:04.648387 MD32_EN : 0
4713 11:52:04.651697 ===================================
4714 11:52:04.654993 [ANA_INIT] >>>>>>>>>>>>>>
4715 11:52:04.658474 <<<<<< [CONFIGURE PHASE]: ANA_TX
4716 11:52:04.661606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4717 11:52:04.664858 ===================================
4718 11:52:04.668241 data_rate = 1866,PCW = 0X8f00
4719 11:52:04.671523 ===================================
4720 11:52:04.674993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4721 11:52:04.681469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4722 11:52:04.684942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4723 11:52:04.691483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4724 11:52:04.694800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4725 11:52:04.698189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4726 11:52:04.698271 [ANA_INIT] flow start
4727 11:52:04.701484 [ANA_INIT] PLL >>>>>>>>
4728 11:52:04.704840 [ANA_INIT] PLL <<<<<<<<
4729 11:52:04.704921 [ANA_INIT] MIDPI >>>>>>>>
4730 11:52:04.707921 [ANA_INIT] MIDPI <<<<<<<<
4731 11:52:04.711288 [ANA_INIT] DLL >>>>>>>>
4732 11:52:04.711369 [ANA_INIT] flow end
4733 11:52:04.717718 ============ LP4 DIFF to SE enter ============
4734 11:52:04.721044 ============ LP4 DIFF to SE exit ============
4735 11:52:04.724374 [ANA_INIT] <<<<<<<<<<<<<
4736 11:52:04.727685 [Flow] Enable top DCM control >>>>>
4737 11:52:04.731045 [Flow] Enable top DCM control <<<<<
4738 11:52:04.731127 Enable DLL master slave shuffle
4739 11:52:04.737741 ==============================================================
4740 11:52:04.741089 Gating Mode config
4741 11:52:04.744433 ==============================================================
4742 11:52:04.747732 Config description:
4743 11:52:04.757556 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4744 11:52:04.764392 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4745 11:52:04.767747 SELPH_MODE 0: By rank 1: By Phase
4746 11:52:04.774150 ==============================================================
4747 11:52:04.777472 GAT_TRACK_EN = 1
4748 11:52:04.780729 RX_GATING_MODE = 2
4749 11:52:04.784099 RX_GATING_TRACK_MODE = 2
4750 11:52:04.787337 SELPH_MODE = 1
4751 11:52:04.787421 PICG_EARLY_EN = 1
4752 11:52:04.790709 VALID_LAT_VALUE = 1
4753 11:52:04.797537 ==============================================================
4754 11:52:04.800682 Enter into Gating configuration >>>>
4755 11:52:04.803931 Exit from Gating configuration <<<<
4756 11:52:04.807218 Enter into DVFS_PRE_config >>>>>
4757 11:52:04.817461 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4758 11:52:04.820463 Exit from DVFS_PRE_config <<<<<
4759 11:52:04.824059 Enter into PICG configuration >>>>
4760 11:52:04.827348 Exit from PICG configuration <<<<
4761 11:52:04.830653 [RX_INPUT] configuration >>>>>
4762 11:52:04.833903 [RX_INPUT] configuration <<<<<
4763 11:52:04.837302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4764 11:52:04.843741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4765 11:52:04.850391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4766 11:52:04.856970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4767 11:52:04.863697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4768 11:52:04.870436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4769 11:52:04.873606 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4770 11:52:04.876975 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4771 11:52:04.880065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4772 11:52:04.886980 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4773 11:52:04.890165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4774 11:52:04.893663 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4775 11:52:04.896757 ===================================
4776 11:52:04.900179 LPDDR4 DRAM CONFIGURATION
4777 11:52:04.903422 ===================================
4778 11:52:04.903515 EX_ROW_EN[0] = 0x0
4779 11:52:04.906678 EX_ROW_EN[1] = 0x0
4780 11:52:04.906760 LP4Y_EN = 0x0
4781 11:52:04.910412 WORK_FSP = 0x0
4782 11:52:04.910496 WL = 0x3
4783 11:52:04.913448 RL = 0x3
4784 11:52:04.913535 BL = 0x2
4785 11:52:04.916823 RPST = 0x0
4786 11:52:04.920041 RD_PRE = 0x0
4787 11:52:04.920124 WR_PRE = 0x1
4788 11:52:04.923396 WR_PST = 0x0
4789 11:52:04.923479 DBI_WR = 0x0
4790 11:52:04.926789 DBI_RD = 0x0
4791 11:52:04.926872 OTF = 0x1
4792 11:52:04.929973 ===================================
4793 11:52:04.933326 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4794 11:52:04.940024 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4795 11:52:04.943711 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4796 11:52:04.946473 ===================================
4797 11:52:04.949822 LPDDR4 DRAM CONFIGURATION
4798 11:52:04.953093 ===================================
4799 11:52:04.953176 EX_ROW_EN[0] = 0x10
4800 11:52:04.956615 EX_ROW_EN[1] = 0x0
4801 11:52:04.956698 LP4Y_EN = 0x0
4802 11:52:04.960053 WORK_FSP = 0x0
4803 11:52:04.960135 WL = 0x3
4804 11:52:04.963235 RL = 0x3
4805 11:52:04.963318 BL = 0x2
4806 11:52:04.966434 RPST = 0x0
4807 11:52:04.966516 RD_PRE = 0x0
4808 11:52:04.969849 WR_PRE = 0x1
4809 11:52:04.973391 WR_PST = 0x0
4810 11:52:04.973473 DBI_WR = 0x0
4811 11:52:04.976401 DBI_RD = 0x0
4812 11:52:04.976482 OTF = 0x1
4813 11:52:04.979677 ===================================
4814 11:52:04.986493 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4815 11:52:04.989929 nWR fixed to 30
4816 11:52:04.993421 [ModeRegInit_LP4] CH0 RK0
4817 11:52:04.993504 [ModeRegInit_LP4] CH0 RK1
4818 11:52:04.996730 [ModeRegInit_LP4] CH1 RK0
4819 11:52:05.000015 [ModeRegInit_LP4] CH1 RK1
4820 11:52:05.000097 match AC timing 8
4821 11:52:05.006483 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4822 11:52:05.009830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4823 11:52:05.013079 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4824 11:52:05.019903 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4825 11:52:05.023161 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4826 11:52:05.023244 ==
4827 11:52:05.026353 Dram Type= 6, Freq= 0, CH_0, rank 0
4828 11:52:05.029541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4829 11:52:05.029624 ==
4830 11:52:05.036333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4831 11:52:05.042993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4832 11:52:05.046429 [CA 0] Center 38 (8~69) winsize 62
4833 11:52:05.049475 [CA 1] Center 38 (8~69) winsize 62
4834 11:52:05.052825 [CA 2] Center 36 (5~67) winsize 63
4835 11:52:05.056218 [CA 3] Center 36 (5~67) winsize 63
4836 11:52:05.059572 [CA 4] Center 34 (4~65) winsize 62
4837 11:52:05.062840 [CA 5] Center 34 (4~65) winsize 62
4838 11:52:05.062922
4839 11:52:05.065982 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4840 11:52:05.066063
4841 11:52:05.069238 [CATrainingPosCal] consider 1 rank data
4842 11:52:05.072473 u2DelayCellTimex100 = 270/100 ps
4843 11:52:05.075840 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4844 11:52:05.079266 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4845 11:52:05.082574 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4846 11:52:05.085751 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4847 11:52:05.092397 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4848 11:52:05.095849 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4849 11:52:05.095942
4850 11:52:05.099221 CA PerBit enable=1, Macro0, CA PI delay=34
4851 11:52:05.099303
4852 11:52:05.102482 [CBTSetCACLKResult] CA Dly = 34
4853 11:52:05.102564 CS Dly: 7 (0~38)
4854 11:52:05.102630 ==
4855 11:52:05.105817 Dram Type= 6, Freq= 0, CH_0, rank 1
4856 11:52:05.109298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4857 11:52:05.112418 ==
4858 11:52:05.115874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4859 11:52:05.122525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4860 11:52:05.125683 [CA 0] Center 38 (8~69) winsize 62
4861 11:52:05.128945 [CA 1] Center 38 (8~69) winsize 62
4862 11:52:05.132372 [CA 2] Center 36 (5~67) winsize 63
4863 11:52:05.135620 [CA 3] Center 35 (5~66) winsize 62
4864 11:52:05.138875 [CA 4] Center 34 (4~65) winsize 62
4865 11:52:05.142185 [CA 5] Center 34 (4~65) winsize 62
4866 11:52:05.142266
4867 11:52:05.145376 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4868 11:52:05.145458
4869 11:52:05.148862 [CATrainingPosCal] consider 2 rank data
4870 11:52:05.151994 u2DelayCellTimex100 = 270/100 ps
4871 11:52:05.155473 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4872 11:52:05.158633 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4873 11:52:05.161950 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4874 11:52:05.168527 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4875 11:52:05.171832 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4876 11:52:05.175485 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4877 11:52:05.175566
4878 11:52:05.178565 CA PerBit enable=1, Macro0, CA PI delay=34
4879 11:52:05.178647
4880 11:52:05.181995 [CBTSetCACLKResult] CA Dly = 34
4881 11:52:05.182077 CS Dly: 7 (0~39)
4882 11:52:05.182143
4883 11:52:05.185264 ----->DramcWriteLeveling(PI) begin...
4884 11:52:05.188601 ==
4885 11:52:05.188708 Dram Type= 6, Freq= 0, CH_0, rank 0
4886 11:52:05.195128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4887 11:52:05.195235 ==
4888 11:52:05.198315 Write leveling (Byte 0): 27 => 27
4889 11:52:05.201647 Write leveling (Byte 1): 26 => 26
4890 11:52:05.205083 DramcWriteLeveling(PI) end<-----
4891 11:52:05.205188
4892 11:52:05.205283 ==
4893 11:52:05.208298 Dram Type= 6, Freq= 0, CH_0, rank 0
4894 11:52:05.212041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4895 11:52:05.212147 ==
4896 11:52:05.215103 [Gating] SW mode calibration
4897 11:52:05.221535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4898 11:52:05.228200 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4899 11:52:05.231514 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4900 11:52:05.234931 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4901 11:52:05.238263 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4902 11:52:05.244924 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4903 11:52:05.247999 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4904 11:52:05.251339 0 10 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4905 11:52:05.258113 0 10 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4906 11:52:05.261403 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4907 11:52:05.264675 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4908 11:52:05.271345 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4909 11:52:05.274495 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4910 11:52:05.277983 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 11:52:05.284636 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 11:52:05.288111 0 11 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4913 11:52:05.291167 0 11 24 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4914 11:52:05.297971 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4915 11:52:05.301068 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4916 11:52:05.304323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4917 11:52:05.311261 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4918 11:52:05.314324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 11:52:05.317694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 11:52:05.324426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4921 11:52:05.327699 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4922 11:52:05.331082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4923 11:52:05.337560 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4924 11:52:05.340798 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4925 11:52:05.344192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 11:52:05.350698 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 11:52:05.354102 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 11:52:05.357320 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 11:52:05.364153 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 11:52:05.367605 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 11:52:05.370668 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 11:52:05.377334 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 11:52:05.380621 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 11:52:05.383996 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 11:52:05.390535 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 11:52:05.393822 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4937 11:52:05.397138 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 11:52:05.400462 Total UI for P1: 0, mck2ui 16
4939 11:52:05.403934 best dqsien dly found for B0: ( 0, 14, 20)
4940 11:52:05.407123 Total UI for P1: 0, mck2ui 16
4941 11:52:05.410365 best dqsien dly found for B1: ( 0, 14, 20)
4942 11:52:05.413814 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4943 11:52:05.416974 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4944 11:52:05.417077
4945 11:52:05.423891 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4946 11:52:05.426930 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4947 11:52:05.427034 [Gating] SW calibration Done
4948 11:52:05.430369 ==
4949 11:52:05.430473 Dram Type= 6, Freq= 0, CH_0, rank 0
4950 11:52:05.436823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4951 11:52:05.436934 ==
4952 11:52:05.437027 RX Vref Scan: 0
4953 11:52:05.437114
4954 11:52:05.440394 RX Vref 0 -> 0, step: 1
4955 11:52:05.440499
4956 11:52:05.443596 RX Delay -80 -> 252, step: 8
4957 11:52:05.446941 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4958 11:52:05.450138 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4959 11:52:05.453468 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4960 11:52:05.460145 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4961 11:52:05.463685 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4962 11:52:05.466779 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4963 11:52:05.470262 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4964 11:52:05.473414 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4965 11:52:05.476695 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4966 11:52:05.483477 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4967 11:52:05.486555 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4968 11:52:05.490040 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4969 11:52:05.493299 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
4970 11:52:05.496641 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4971 11:52:05.503292 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4972 11:52:05.506510 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4973 11:52:05.506614 ==
4974 11:52:05.509665 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 11:52:05.513118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 11:52:05.513221 ==
4977 11:52:05.516458 DQS Delay:
4978 11:52:05.516600 DQS0 = 0, DQS1 = 0
4979 11:52:05.516726 DQM Delay:
4980 11:52:05.519617 DQM0 = 94, DQM1 = 84
4981 11:52:05.519718 DQ Delay:
4982 11:52:05.522893 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4983 11:52:05.526273 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =103
4984 11:52:05.529463 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
4985 11:52:05.533172 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
4986 11:52:05.533275
4987 11:52:05.533366
4988 11:52:05.533453 ==
4989 11:52:05.536378 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 11:52:05.542803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 11:52:05.542910 ==
4992 11:52:05.543001
4993 11:52:05.543088
4994 11:52:05.543175 TX Vref Scan disable
4995 11:52:05.546607 == TX Byte 0 ==
4996 11:52:05.550000 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
4997 11:52:05.553254 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
4998 11:52:05.556724 == TX Byte 1 ==
4999 11:52:05.559785 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5000 11:52:05.566601 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5001 11:52:05.566707 ==
5002 11:52:05.569639 Dram Type= 6, Freq= 0, CH_0, rank 0
5003 11:52:05.573144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5004 11:52:05.573249 ==
5005 11:52:05.573340
5006 11:52:05.573428
5007 11:52:05.576449 TX Vref Scan disable
5008 11:52:05.576605 == TX Byte 0 ==
5009 11:52:05.583124 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5010 11:52:05.586563 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5011 11:52:05.586667 == TX Byte 1 ==
5012 11:52:05.592815 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5013 11:52:05.596224 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5014 11:52:05.596326
5015 11:52:05.596417 [DATLAT]
5016 11:52:05.599660 Freq=933, CH0 RK0
5017 11:52:05.599763
5018 11:52:05.599854 DATLAT Default: 0xd
5019 11:52:05.602751 0, 0xFFFF, sum = 0
5020 11:52:05.602856 1, 0xFFFF, sum = 0
5021 11:52:05.606060 2, 0xFFFF, sum = 0
5022 11:52:05.609363 3, 0xFFFF, sum = 0
5023 11:52:05.609469 4, 0xFFFF, sum = 0
5024 11:52:05.612807 5, 0xFFFF, sum = 0
5025 11:52:05.612912 6, 0xFFFF, sum = 0
5026 11:52:05.616023 7, 0xFFFF, sum = 0
5027 11:52:05.616127 8, 0xFFFF, sum = 0
5028 11:52:05.619359 9, 0xFFFF, sum = 0
5029 11:52:05.619463 10, 0x0, sum = 1
5030 11:52:05.622689 11, 0x0, sum = 2
5031 11:52:05.622796 12, 0x0, sum = 3
5032 11:52:05.626038 13, 0x0, sum = 4
5033 11:52:05.626143 best_step = 11
5034 11:52:05.626233
5035 11:52:05.626321 ==
5036 11:52:05.629448 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 11:52:05.632837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5038 11:52:05.632940 ==
5039 11:52:05.636084 RX Vref Scan: 1
5040 11:52:05.636190
5041 11:52:05.639201 RX Vref 0 -> 0, step: 1
5042 11:52:05.639305
5043 11:52:05.639396 RX Delay -69 -> 252, step: 4
5044 11:52:05.639485
5045 11:52:05.642581 Set Vref, RX VrefLevel [Byte0]: 46
5046 11:52:05.645697 [Byte1]: 47
5047 11:52:05.650722
5048 11:52:05.650826 Final RX Vref Byte 0 = 46 to rank0
5049 11:52:05.653839 Final RX Vref Byte 1 = 47 to rank0
5050 11:52:05.657535 Final RX Vref Byte 0 = 46 to rank1
5051 11:52:05.660659 Final RX Vref Byte 1 = 47 to rank1==
5052 11:52:05.664002 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 11:52:05.670393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5054 11:52:05.670501 ==
5055 11:52:05.670594 DQS Delay:
5056 11:52:05.670683 DQS0 = 0, DQS1 = 0
5057 11:52:05.673948 DQM Delay:
5058 11:52:05.674053 DQM0 = 97, DQM1 = 86
5059 11:52:05.677074 DQ Delay:
5060 11:52:05.680400 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =96
5061 11:52:05.683833 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5062 11:52:05.686953 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =80
5063 11:52:05.690404 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5064 11:52:05.690509
5065 11:52:05.690601
5066 11:52:05.697075 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5067 11:52:05.700484 CH0 RK0: MR19=505, MR18=2525
5068 11:52:05.707150 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5069 11:52:05.707257
5070 11:52:05.710153 ----->DramcWriteLeveling(PI) begin...
5071 11:52:05.710260 ==
5072 11:52:05.713547 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 11:52:05.717058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 11:52:05.717164 ==
5075 11:52:05.720115 Write leveling (Byte 0): 26 => 26
5076 11:52:05.723511 Write leveling (Byte 1): 26 => 26
5077 11:52:05.726770 DramcWriteLeveling(PI) end<-----
5078 11:52:05.726875
5079 11:52:05.726966 ==
5080 11:52:05.730095 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 11:52:05.733500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5082 11:52:05.733606 ==
5083 11:52:05.736932 [Gating] SW mode calibration
5084 11:52:05.743821 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5085 11:52:05.749918 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5086 11:52:05.753378 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 11:52:05.759995 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 11:52:05.763363 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 11:52:05.766764 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 11:52:05.773335 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 11:52:05.776679 0 10 20 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 0)
5092 11:52:05.779974 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5093 11:52:05.786644 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 11:52:05.790072 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 11:52:05.793205 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 11:52:05.799792 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 11:52:05.802994 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 11:52:05.806327 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5099 11:52:05.809714 0 11 20 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
5100 11:52:05.816415 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5101 11:52:05.819613 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 11:52:05.822906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 11:52:05.829515 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 11:52:05.833052 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 11:52:05.836431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 11:52:05.842880 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 11:52:05.846431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5108 11:52:05.849414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 11:52:05.856127 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:52:05.859367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:52:05.862665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:52:05.869518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 11:52:05.872681 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:52:05.876121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:52:05.882585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:52:05.885964 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:52:05.889295 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:52:05.895893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:52:05.899396 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:52:05.902386 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:52:05.909092 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:52:05.912593 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:52:05.915691 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5124 11:52:05.919202 Total UI for P1: 0, mck2ui 16
5125 11:52:05.922368 best dqsien dly found for B1: ( 0, 14, 18)
5126 11:52:05.929160 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5127 11:52:05.932260 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:52:05.935658 Total UI for P1: 0, mck2ui 16
5129 11:52:05.938880 best dqsien dly found for B0: ( 0, 14, 22)
5130 11:52:05.942267 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5131 11:52:05.945553 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5132 11:52:05.945660
5133 11:52:05.948861 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5134 11:52:05.952144 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5135 11:52:05.955572 [Gating] SW calibration Done
5136 11:52:05.955678 ==
5137 11:52:05.958929 Dram Type= 6, Freq= 0, CH_0, rank 1
5138 11:52:05.962177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5139 11:52:05.965347 ==
5140 11:52:05.965452 RX Vref Scan: 0
5141 11:52:05.965544
5142 11:52:05.968893 RX Vref 0 -> 0, step: 1
5143 11:52:05.968998
5144 11:52:05.972061 RX Delay -80 -> 252, step: 8
5145 11:52:05.975467 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5146 11:52:05.978598 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5147 11:52:05.981834 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5148 11:52:05.985158 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5149 11:52:05.988784 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5150 11:52:05.995163 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5151 11:52:05.998429 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5152 11:52:06.001734 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5153 11:52:06.005191 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5154 11:52:06.008582 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5155 11:52:06.015076 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5156 11:52:06.018499 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5157 11:52:06.021790 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5158 11:52:06.025178 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5159 11:52:06.028452 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5160 11:52:06.031735 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5161 11:52:06.035019 ==
5162 11:52:06.038252 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 11:52:06.041422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 11:52:06.041529 ==
5165 11:52:06.041622 DQS Delay:
5166 11:52:06.045085 DQS0 = 0, DQS1 = 0
5167 11:52:06.045188 DQM Delay:
5168 11:52:06.048239 DQM0 = 96, DQM1 = 86
5169 11:52:06.048343 DQ Delay:
5170 11:52:06.051526 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5171 11:52:06.054810 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5172 11:52:06.058172 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5173 11:52:06.061575 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =99
5174 11:52:06.061681
5175 11:52:06.061774
5176 11:52:06.061863 ==
5177 11:52:06.065012 Dram Type= 6, Freq= 0, CH_0, rank 1
5178 11:52:06.068400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5179 11:52:06.068511 ==
5180 11:52:06.068606
5181 11:52:06.068696
5182 11:52:06.071506 TX Vref Scan disable
5183 11:52:06.075290 == TX Byte 0 ==
5184 11:52:06.078145 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5185 11:52:06.081745 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5186 11:52:06.084902 == TX Byte 1 ==
5187 11:52:06.088167 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5188 11:52:06.091522 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5189 11:52:06.091628 ==
5190 11:52:06.094739 Dram Type= 6, Freq= 0, CH_0, rank 1
5191 11:52:06.101585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5192 11:52:06.101694 ==
5193 11:52:06.101787
5194 11:52:06.101876
5195 11:52:06.101966 TX Vref Scan disable
5196 11:52:06.105256 == TX Byte 0 ==
5197 11:52:06.108417 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5198 11:52:06.111845 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5199 11:52:06.115125 == TX Byte 1 ==
5200 11:52:06.118572 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5201 11:52:06.125063 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5202 11:52:06.125171
5203 11:52:06.125264 [DATLAT]
5204 11:52:06.125355 Freq=933, CH0 RK1
5205 11:52:06.125450
5206 11:52:06.128256 DATLAT Default: 0xb
5207 11:52:06.128360 0, 0xFFFF, sum = 0
5208 11:52:06.131740 1, 0xFFFF, sum = 0
5209 11:52:06.131847 2, 0xFFFF, sum = 0
5210 11:52:06.134988 3, 0xFFFF, sum = 0
5211 11:52:06.138359 4, 0xFFFF, sum = 0
5212 11:52:06.138468 5, 0xFFFF, sum = 0
5213 11:52:06.141779 6, 0xFFFF, sum = 0
5214 11:52:06.141885 7, 0xFFFF, sum = 0
5215 11:52:06.145016 8, 0xFFFF, sum = 0
5216 11:52:06.145122 9, 0xFFFF, sum = 0
5217 11:52:06.148304 10, 0x0, sum = 1
5218 11:52:06.148410 11, 0x0, sum = 2
5219 11:52:06.151591 12, 0x0, sum = 3
5220 11:52:06.151697 13, 0x0, sum = 4
5221 11:52:06.151792 best_step = 11
5222 11:52:06.151881
5223 11:52:06.154950 ==
5224 11:52:06.158228 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 11:52:06.161493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 11:52:06.161598 ==
5227 11:52:06.161690 RX Vref Scan: 0
5228 11:52:06.161779
5229 11:52:06.164964 RX Vref 0 -> 0, step: 1
5230 11:52:06.165069
5231 11:52:06.168203 RX Delay -69 -> 252, step: 4
5232 11:52:06.171605 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5233 11:52:06.178115 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5234 11:52:06.181821 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5235 11:52:06.184823 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5236 11:52:06.188290 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5237 11:52:06.191551 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5238 11:52:06.194753 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5239 11:52:06.201265 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5240 11:52:06.204768 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5241 11:52:06.207892 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5242 11:52:06.211398 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5243 11:52:06.214813 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5244 11:52:06.221411 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5245 11:52:06.224677 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5246 11:52:06.227767 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5247 11:52:06.231079 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5248 11:52:06.231184 ==
5249 11:52:06.234495 Dram Type= 6, Freq= 0, CH_0, rank 1
5250 11:52:06.237745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5251 11:52:06.240971 ==
5252 11:52:06.241077 DQS Delay:
5253 11:52:06.241170 DQS0 = 0, DQS1 = 0
5254 11:52:06.244223 DQM Delay:
5255 11:52:06.244326 DQM0 = 97, DQM1 = 86
5256 11:52:06.247547 DQ Delay:
5257 11:52:06.251356 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5258 11:52:06.254243 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5259 11:52:06.257766 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
5260 11:52:06.260807 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5261 11:52:06.260911
5262 11:52:06.261003
5263 11:52:06.267834 [DQSOSCAuto] RK1, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5264 11:52:06.271132 CH0 RK1: MR19=505, MR18=3131
5265 11:52:06.277407 CH0_RK1: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5266 11:52:06.280754 [RxdqsGatingPostProcess] freq 933
5267 11:52:06.283876 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5268 11:52:06.287291 Pre-setting of DQS Precalculation
5269 11:52:06.293739 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5270 11:52:06.293850 ==
5271 11:52:06.297150 Dram Type= 6, Freq= 0, CH_1, rank 0
5272 11:52:06.300361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5273 11:52:06.300465 ==
5274 11:52:06.306995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5275 11:52:06.313614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5276 11:52:06.316995 [CA 0] Center 37 (6~68) winsize 63
5277 11:52:06.320079 [CA 1] Center 37 (6~68) winsize 63
5278 11:52:06.323614 [CA 2] Center 34 (4~65) winsize 62
5279 11:52:06.326675 [CA 3] Center 34 (3~65) winsize 63
5280 11:52:06.330464 [CA 4] Center 32 (2~63) winsize 62
5281 11:52:06.333437 [CA 5] Center 33 (2~64) winsize 63
5282 11:52:06.333543
5283 11:52:06.336598 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5284 11:52:06.336816
5285 11:52:06.339993 [CATrainingPosCal] consider 1 rank data
5286 11:52:06.343222 u2DelayCellTimex100 = 270/100 ps
5287 11:52:06.346591 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5288 11:52:06.350085 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5289 11:52:06.353471 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5290 11:52:06.356482 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5291 11:52:06.359899 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5292 11:52:06.363074 CA5 delay=33 (2~64),Diff = 1 PI (6 cell)
5293 11:52:06.366606
5294 11:52:06.370086 CA PerBit enable=1, Macro0, CA PI delay=32
5295 11:52:06.370168
5296 11:52:06.373051 [CBTSetCACLKResult] CA Dly = 32
5297 11:52:06.373133 CS Dly: 5 (0~36)
5298 11:52:06.373197 ==
5299 11:52:06.376539 Dram Type= 6, Freq= 0, CH_1, rank 1
5300 11:52:06.379800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5301 11:52:06.379881 ==
5302 11:52:06.386331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5303 11:52:06.392840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5304 11:52:06.396272 [CA 0] Center 37 (6~68) winsize 63
5305 11:52:06.399545 [CA 1] Center 37 (6~68) winsize 63
5306 11:52:06.402976 [CA 2] Center 34 (4~65) winsize 62
5307 11:52:06.406108 [CA 3] Center 34 (3~65) winsize 63
5308 11:52:06.409515 [CA 4] Center 33 (3~64) winsize 62
5309 11:52:06.412865 [CA 5] Center 33 (3~63) winsize 61
5310 11:52:06.412945
5311 11:52:06.416089 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5312 11:52:06.416170
5313 11:52:06.419572 [CATrainingPosCal] consider 2 rank data
5314 11:52:06.422901 u2DelayCellTimex100 = 270/100 ps
5315 11:52:06.426167 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5316 11:52:06.429545 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5317 11:52:06.432516 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5318 11:52:06.435842 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5319 11:52:06.439224 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5320 11:52:06.445919 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5321 11:52:06.446035
5322 11:52:06.449284 CA PerBit enable=1, Macro0, CA PI delay=33
5323 11:52:06.449365
5324 11:52:06.452447 [CBTSetCACLKResult] CA Dly = 33
5325 11:52:06.452583 CS Dly: 5 (0~37)
5326 11:52:06.452649
5327 11:52:06.455919 ----->DramcWriteLeveling(PI) begin...
5328 11:52:06.456002 ==
5329 11:52:06.459123 Dram Type= 6, Freq= 0, CH_1, rank 0
5330 11:52:06.465907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5331 11:52:06.465991 ==
5332 11:52:06.469061 Write leveling (Byte 0): 22 => 22
5333 11:52:06.469145 Write leveling (Byte 1): 27 => 27
5334 11:52:06.472561 DramcWriteLeveling(PI) end<-----
5335 11:52:06.472674
5336 11:52:06.472742 ==
5337 11:52:06.475794 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 11:52:06.482205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 11:52:06.482292 ==
5340 11:52:06.485708 [Gating] SW mode calibration
5341 11:52:06.492087 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 11:52:06.495336 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5343 11:52:06.502070 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 11:52:06.505621 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 11:52:06.508490 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 11:52:06.515200 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 11:52:06.518538 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
5348 11:52:06.521763 0 10 20 | B1->B0 | 3232 2424 | 1 0 | (1 0) (1 0)
5349 11:52:06.528402 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 11:52:06.531747 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 11:52:06.535038 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 11:52:06.541562 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 11:52:06.544946 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 11:52:06.548305 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 11:52:06.555025 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5356 11:52:06.558312 0 11 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5357 11:52:06.561454 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5358 11:52:06.568050 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 11:52:06.571333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 11:52:06.574535 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 11:52:06.581400 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 11:52:06.584774 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:52:06.587807 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5364 11:52:06.594467 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 11:52:06.597674 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:52:06.601163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:52:06.607688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:52:06.611097 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:52:06.614456 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:52:06.621226 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:52:06.624478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:52:06.627764 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:52:06.634445 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:52:06.637805 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:52:06.640972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:52:06.647588 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:52:06.650835 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:52:06.654021 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:52:06.660406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:52:06.663927 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 11:52:06.667490 Total UI for P1: 0, mck2ui 16
5382 11:52:06.670516 best dqsien dly found for B0: ( 0, 14, 18)
5383 11:52:06.673911 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:52:06.677327 Total UI for P1: 0, mck2ui 16
5385 11:52:06.680319 best dqsien dly found for B1: ( 0, 14, 20)
5386 11:52:06.683807 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5387 11:52:06.687178 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5388 11:52:06.687289
5389 11:52:06.693516 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5390 11:52:06.696805 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5391 11:52:06.696911 [Gating] SW calibration Done
5392 11:52:06.700249 ==
5393 11:52:06.703577 Dram Type= 6, Freq= 0, CH_1, rank 0
5394 11:52:06.707018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5395 11:52:06.707125 ==
5396 11:52:06.707217 RX Vref Scan: 0
5397 11:52:06.707308
5398 11:52:06.710100 RX Vref 0 -> 0, step: 1
5399 11:52:06.710204
5400 11:52:06.713574 RX Delay -80 -> 252, step: 8
5401 11:52:06.716650 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5402 11:52:06.720016 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5403 11:52:06.723362 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5404 11:52:06.729907 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5405 11:52:06.733263 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5406 11:52:06.736489 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5407 11:52:06.739791 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5408 11:52:06.743082 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5409 11:52:06.746520 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5410 11:52:06.753177 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5411 11:52:06.756233 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5412 11:52:06.759607 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5413 11:52:06.763192 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5414 11:52:06.766364 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5415 11:52:06.773044 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5416 11:52:06.776290 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5417 11:52:06.776396 ==
5418 11:52:06.779674 Dram Type= 6, Freq= 0, CH_1, rank 0
5419 11:52:06.782989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5420 11:52:06.783096 ==
5421 11:52:06.783189 DQS Delay:
5422 11:52:06.786299 DQS0 = 0, DQS1 = 0
5423 11:52:06.786406 DQM Delay:
5424 11:52:06.789547 DQM0 = 94, DQM1 = 89
5425 11:52:06.789653 DQ Delay:
5426 11:52:06.792762 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5427 11:52:06.796081 DQ4 =95, DQ5 =103, DQ6 =99, DQ7 =91
5428 11:52:06.799311 DQ8 =71, DQ9 =79, DQ10 =95, DQ11 =79
5429 11:52:06.802887 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5430 11:52:06.802993
5431 11:52:06.803086
5432 11:52:06.803175 ==
5433 11:52:06.805987 Dram Type= 6, Freq= 0, CH_1, rank 0
5434 11:52:06.812475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5435 11:52:06.812593 ==
5436 11:52:06.812685
5437 11:52:06.812773
5438 11:52:06.812861 TX Vref Scan disable
5439 11:52:06.816059 == TX Byte 0 ==
5440 11:52:06.819356 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5441 11:52:06.826058 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5442 11:52:06.826164 == TX Byte 1 ==
5443 11:52:06.829261 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5444 11:52:06.835758 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5445 11:52:06.835865 ==
5446 11:52:06.839090 Dram Type= 6, Freq= 0, CH_1, rank 0
5447 11:52:06.842518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5448 11:52:06.842627 ==
5449 11:52:06.842720
5450 11:52:06.842810
5451 11:52:06.845816 TX Vref Scan disable
5452 11:52:06.849269 == TX Byte 0 ==
5453 11:52:06.852444 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5454 11:52:06.855696 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5455 11:52:06.858932 == TX Byte 1 ==
5456 11:52:06.862253 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5457 11:52:06.865608 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5458 11:52:06.865712
5459 11:52:06.865803 [DATLAT]
5460 11:52:06.868778 Freq=933, CH1 RK0
5461 11:52:06.868881
5462 11:52:06.872073 DATLAT Default: 0xd
5463 11:52:06.872175 0, 0xFFFF, sum = 0
5464 11:52:06.875670 1, 0xFFFF, sum = 0
5465 11:52:06.875775 2, 0xFFFF, sum = 0
5466 11:52:06.878897 3, 0xFFFF, sum = 0
5467 11:52:06.879002 4, 0xFFFF, sum = 0
5468 11:52:06.882026 5, 0xFFFF, sum = 0
5469 11:52:06.882131 6, 0xFFFF, sum = 0
5470 11:52:06.885287 7, 0xFFFF, sum = 0
5471 11:52:06.885393 8, 0xFFFF, sum = 0
5472 11:52:06.888710 9, 0xFFFF, sum = 0
5473 11:52:06.888815 10, 0x0, sum = 1
5474 11:52:06.892135 11, 0x0, sum = 2
5475 11:52:06.892240 12, 0x0, sum = 3
5476 11:52:06.895278 13, 0x0, sum = 4
5477 11:52:06.895383 best_step = 11
5478 11:52:06.895474
5479 11:52:06.895563 ==
5480 11:52:06.898620 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 11:52:06.902112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5482 11:52:06.902216 ==
5483 11:52:06.905302 RX Vref Scan: 1
5484 11:52:06.905404
5485 11:52:06.908521 RX Vref 0 -> 0, step: 1
5486 11:52:06.908624
5487 11:52:06.908714 RX Delay -69 -> 252, step: 4
5488 11:52:06.908852
5489 11:52:06.912322 Set Vref, RX VrefLevel [Byte0]: 52
5490 11:52:06.915327 [Byte1]: 49
5491 11:52:06.920009
5492 11:52:06.920112 Final RX Vref Byte 0 = 52 to rank0
5493 11:52:06.923535 Final RX Vref Byte 1 = 49 to rank0
5494 11:52:06.926854 Final RX Vref Byte 0 = 52 to rank1
5495 11:52:06.930286 Final RX Vref Byte 1 = 49 to rank1==
5496 11:52:06.933344 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 11:52:06.939980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 11:52:06.940091 ==
5499 11:52:06.940184 DQS Delay:
5500 11:52:06.940273 DQS0 = 0, DQS1 = 0
5501 11:52:06.943258 DQM Delay:
5502 11:52:06.943362 DQM0 = 94, DQM1 = 87
5503 11:52:06.946602 DQ Delay:
5504 11:52:06.949971 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5505 11:52:06.953252 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5506 11:52:06.956685 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5507 11:52:06.959893 DQ12 =94, DQ13 =98, DQ14 =98, DQ15 =98
5508 11:52:06.959999
5509 11:52:06.960089
5510 11:52:06.966550 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5511 11:52:06.969673 CH1 RK0: MR19=505, MR18=3131
5512 11:52:06.976457 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5513 11:52:06.976604
5514 11:52:06.979760 ----->DramcWriteLeveling(PI) begin...
5515 11:52:06.979864 ==
5516 11:52:06.982972 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 11:52:06.986359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5518 11:52:06.986465 ==
5519 11:52:06.989717 Write leveling (Byte 0): 23 => 23
5520 11:52:06.992930 Write leveling (Byte 1): 26 => 26
5521 11:52:06.996165 DramcWriteLeveling(PI) end<-----
5522 11:52:06.996269
5523 11:52:06.996360 ==
5524 11:52:06.999648 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 11:52:07.002981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 11:52:07.003085 ==
5527 11:52:07.006096 [Gating] SW mode calibration
5528 11:52:07.012811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5529 11:52:07.019302 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5530 11:52:07.022630 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5531 11:52:07.029379 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5532 11:52:07.032522 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5533 11:52:07.036288 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5534 11:52:07.042741 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
5535 11:52:07.045954 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5536 11:52:07.049304 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5537 11:52:07.055966 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5538 11:52:07.059122 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 11:52:07.062435 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 11:52:07.069190 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 11:52:07.072361 0 11 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5542 11:52:07.075852 0 11 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5543 11:52:07.082282 0 11 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5544 11:52:07.085898 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5545 11:52:07.089056 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5546 11:52:07.095473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 11:52:07.099211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 11:52:07.102083 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 11:52:07.105441 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5550 11:52:07.112169 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5551 11:52:07.115400 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5552 11:52:07.119035 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5553 11:52:07.125264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 11:52:07.128635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 11:52:07.132057 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 11:52:07.138556 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 11:52:07.142000 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 11:52:07.145216 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 11:52:07.151874 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 11:52:07.155186 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 11:52:07.158634 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:52:07.165287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:52:07.168762 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:52:07.172047 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:52:07.178613 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:52:07.181895 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5567 11:52:07.185262 Total UI for P1: 0, mck2ui 16
5568 11:52:07.188721 best dqsien dly found for B0: ( 0, 14, 14)
5569 11:52:07.191734 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5570 11:52:07.198442 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 11:52:07.198528 Total UI for P1: 0, mck2ui 16
5572 11:52:07.205364 best dqsien dly found for B1: ( 0, 14, 18)
5573 11:52:07.208381 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5574 11:52:07.212429 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5575 11:52:07.212544
5576 11:52:07.215049 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5577 11:52:07.218478 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5578 11:52:07.221875 [Gating] SW calibration Done
5579 11:52:07.221958 ==
5580 11:52:07.225132 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 11:52:07.228291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5582 11:52:07.228375 ==
5583 11:52:07.231651 RX Vref Scan: 0
5584 11:52:07.231734
5585 11:52:07.231799 RX Vref 0 -> 0, step: 1
5586 11:52:07.231860
5587 11:52:07.234903 RX Delay -80 -> 252, step: 8
5588 11:52:07.238409 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5589 11:52:07.245113 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5590 11:52:07.248237 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5591 11:52:07.251634 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5592 11:52:07.254939 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5593 11:52:07.258095 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5594 11:52:07.261452 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5595 11:52:07.268159 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5596 11:52:07.271680 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5597 11:52:07.274644 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5598 11:52:07.278016 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5599 11:52:07.281254 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5600 11:52:07.287974 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5601 11:52:07.291271 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5602 11:52:07.294690 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5603 11:52:07.298003 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5604 11:52:07.298086 ==
5605 11:52:07.301158 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 11:52:07.308086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5607 11:52:07.308174 ==
5608 11:52:07.308240 DQS Delay:
5609 11:52:07.308302 DQS0 = 0, DQS1 = 0
5610 11:52:07.311151 DQM Delay:
5611 11:52:07.311234 DQM0 = 95, DQM1 = 89
5612 11:52:07.314445 DQ Delay:
5613 11:52:07.317914 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5614 11:52:07.321274 DQ4 =99, DQ5 =107, DQ6 =103, DQ7 =91
5615 11:52:07.321357 DQ8 =75, DQ9 =75, DQ10 =83, DQ11 =83
5616 11:52:07.327844 DQ12 =95, DQ13 =103, DQ14 =99, DQ15 =99
5617 11:52:07.327926
5618 11:52:07.327991
5619 11:52:07.328050 ==
5620 11:52:07.331079 Dram Type= 6, Freq= 0, CH_1, rank 1
5621 11:52:07.334682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5622 11:52:07.334767 ==
5623 11:52:07.334833
5624 11:52:07.334894
5625 11:52:07.337889 TX Vref Scan disable
5626 11:52:07.337971 == TX Byte 0 ==
5627 11:52:07.344752 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5628 11:52:07.347933 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5629 11:52:07.348016 == TX Byte 1 ==
5630 11:52:07.354298 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5631 11:52:07.357597 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5632 11:52:07.357679 ==
5633 11:52:07.360953 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 11:52:07.364242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5635 11:52:07.364323 ==
5636 11:52:07.364387
5637 11:52:07.367370
5638 11:52:07.367451 TX Vref Scan disable
5639 11:52:07.370749 == TX Byte 0 ==
5640 11:52:07.374176 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5641 11:52:07.380735 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5642 11:52:07.380817 == TX Byte 1 ==
5643 11:52:07.383931 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5644 11:52:07.390533 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5645 11:52:07.390614
5646 11:52:07.390678 [DATLAT]
5647 11:52:07.390739 Freq=933, CH1 RK1
5648 11:52:07.390798
5649 11:52:07.393905 DATLAT Default: 0xb
5650 11:52:07.393985 0, 0xFFFF, sum = 0
5651 11:52:07.397241 1, 0xFFFF, sum = 0
5652 11:52:07.397324 2, 0xFFFF, sum = 0
5653 11:52:07.400746 3, 0xFFFF, sum = 0
5654 11:52:07.403930 4, 0xFFFF, sum = 0
5655 11:52:07.404012 5, 0xFFFF, sum = 0
5656 11:52:07.407706 6, 0xFFFF, sum = 0
5657 11:52:07.407817 7, 0xFFFF, sum = 0
5658 11:52:07.410522 8, 0xFFFF, sum = 0
5659 11:52:07.410604 9, 0xFFFF, sum = 0
5660 11:52:07.413819 10, 0x0, sum = 1
5661 11:52:07.413902 11, 0x0, sum = 2
5662 11:52:07.416987 12, 0x0, sum = 3
5663 11:52:07.417069 13, 0x0, sum = 4
5664 11:52:07.417134 best_step = 11
5665 11:52:07.420324
5666 11:52:07.420404 ==
5667 11:52:07.423627 Dram Type= 6, Freq= 0, CH_1, rank 1
5668 11:52:07.427091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5669 11:52:07.427172 ==
5670 11:52:07.427237 RX Vref Scan: 0
5671 11:52:07.427296
5672 11:52:07.430242 RX Vref 0 -> 0, step: 1
5673 11:52:07.430322
5674 11:52:07.433558 RX Delay -69 -> 252, step: 4
5675 11:52:07.440319 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5676 11:52:07.443650 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5677 11:52:07.447099 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5678 11:52:07.450085 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5679 11:52:07.453410 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5680 11:52:07.456817 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5681 11:52:07.463350 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5682 11:52:07.466656 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5683 11:52:07.470044 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5684 11:52:07.473384 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5685 11:52:07.476796 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5686 11:52:07.479942 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5687 11:52:07.486545 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5688 11:52:07.489637 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5689 11:52:07.492970 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5690 11:52:07.496445 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5691 11:52:07.496548 ==
5692 11:52:07.499590 Dram Type= 6, Freq= 0, CH_1, rank 1
5693 11:52:07.506407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5694 11:52:07.506489 ==
5695 11:52:07.506553 DQS Delay:
5696 11:52:07.506613 DQS0 = 0, DQS1 = 0
5697 11:52:07.509697 DQM Delay:
5698 11:52:07.509777 DQM0 = 96, DQM1 = 87
5699 11:52:07.513159 DQ Delay:
5700 11:52:07.516348 DQ0 =94, DQ1 =92, DQ2 =88, DQ3 =94
5701 11:52:07.519893 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5702 11:52:07.522956 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =82
5703 11:52:07.526157 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =94
5704 11:52:07.526238
5705 11:52:07.526303
5706 11:52:07.532815 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5707 11:52:07.536194 CH1 RK1: MR19=505, MR18=2525
5708 11:52:07.542698 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5709 11:52:07.546396 [RxdqsGatingPostProcess] freq 933
5710 11:52:07.549399 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5711 11:52:07.552486 Pre-setting of DQS Precalculation
5712 11:52:07.559253 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5713 11:52:07.566050 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5714 11:52:07.572452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5715 11:52:07.572588
5716 11:52:07.572654
5717 11:52:07.575729 [Calibration Summary] 1866 Mbps
5718 11:52:07.575811 CH 0, Rank 0
5719 11:52:07.578982 SW Impedance : PASS
5720 11:52:07.582374 DUTY Scan : NO K
5721 11:52:07.582455 ZQ Calibration : PASS
5722 11:52:07.585437 Jitter Meter : NO K
5723 11:52:07.588977 CBT Training : PASS
5724 11:52:07.589057 Write leveling : PASS
5725 11:52:07.592192 RX DQS gating : PASS
5726 11:52:07.595757 RX DQ/DQS(RDDQC) : PASS
5727 11:52:07.595838 TX DQ/DQS : PASS
5728 11:52:07.598916 RX DATLAT : PASS
5729 11:52:07.601913 RX DQ/DQS(Engine): PASS
5730 11:52:07.601994 TX OE : NO K
5731 11:52:07.605311 All Pass.
5732 11:52:07.605391
5733 11:52:07.605455 CH 0, Rank 1
5734 11:52:07.608637 SW Impedance : PASS
5735 11:52:07.608719 DUTY Scan : NO K
5736 11:52:07.612195 ZQ Calibration : PASS
5737 11:52:07.615160 Jitter Meter : NO K
5738 11:52:07.615241 CBT Training : PASS
5739 11:52:07.618366 Write leveling : PASS
5740 11:52:07.621669 RX DQS gating : PASS
5741 11:52:07.621750 RX DQ/DQS(RDDQC) : PASS
5742 11:52:07.625063 TX DQ/DQS : PASS
5743 11:52:07.628363 RX DATLAT : PASS
5744 11:52:07.628442 RX DQ/DQS(Engine): PASS
5745 11:52:07.631711 TX OE : NO K
5746 11:52:07.631793 All Pass.
5747 11:52:07.631874
5748 11:52:07.635045 CH 1, Rank 0
5749 11:52:07.635125 SW Impedance : PASS
5750 11:52:07.638370 DUTY Scan : NO K
5751 11:52:07.641617 ZQ Calibration : PASS
5752 11:52:07.641700 Jitter Meter : NO K
5753 11:52:07.644963 CBT Training : PASS
5754 11:52:07.645044 Write leveling : PASS
5755 11:52:07.648123 RX DQS gating : PASS
5756 11:52:07.651418 RX DQ/DQS(RDDQC) : PASS
5757 11:52:07.651500 TX DQ/DQS : PASS
5758 11:52:07.654746 RX DATLAT : PASS
5759 11:52:07.658168 RX DQ/DQS(Engine): PASS
5760 11:52:07.658250 TX OE : NO K
5761 11:52:07.661394 All Pass.
5762 11:52:07.661476
5763 11:52:07.661541 CH 1, Rank 1
5764 11:52:07.664612 SW Impedance : PASS
5765 11:52:07.664695 DUTY Scan : NO K
5766 11:52:07.668372 ZQ Calibration : PASS
5767 11:52:07.671665 Jitter Meter : NO K
5768 11:52:07.671823 CBT Training : PASS
5769 11:52:07.674891 Write leveling : PASS
5770 11:52:07.678419 RX DQS gating : PASS
5771 11:52:07.678590 RX DQ/DQS(RDDQC) : PASS
5772 11:52:07.681528 TX DQ/DQS : PASS
5773 11:52:07.684804 RX DATLAT : PASS
5774 11:52:07.684967 RX DQ/DQS(Engine): PASS
5775 11:52:07.688006 TX OE : NO K
5776 11:52:07.688160 All Pass.
5777 11:52:07.688251
5778 11:52:07.691513 DramC Write-DBI off
5779 11:52:07.694736 PER_BANK_REFRESH: Hybrid Mode
5780 11:52:07.694897 TX_TRACKING: ON
5781 11:52:07.704583 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5782 11:52:07.707983 [FAST_K] Save calibration result to emmc
5783 11:52:07.711034 dramc_set_vcore_voltage set vcore to 650000
5784 11:52:07.714657 Read voltage for 400, 6
5785 11:52:07.714857 Vio18 = 0
5786 11:52:07.715001 Vcore = 650000
5787 11:52:07.717805 Vdram = 0
5788 11:52:07.717997 Vddq = 0
5789 11:52:07.718135 Vmddr = 0
5790 11:52:07.724403 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5791 11:52:07.728046 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5792 11:52:07.731217 MEM_TYPE=3, freq_sel=20
5793 11:52:07.734458 sv_algorithm_assistance_LP4_800
5794 11:52:07.737840 ============ PULL DRAM RESETB DOWN ============
5795 11:52:07.741040 ========== PULL DRAM RESETB DOWN end =========
5796 11:52:07.747820 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5797 11:52:07.751176 ===================================
5798 11:52:07.754845 LPDDR4 DRAM CONFIGURATION
5799 11:52:07.757822 ===================================
5800 11:52:07.758325 EX_ROW_EN[0] = 0x0
5801 11:52:07.761054 EX_ROW_EN[1] = 0x0
5802 11:52:07.761446 LP4Y_EN = 0x0
5803 11:52:07.764635 WORK_FSP = 0x0
5804 11:52:07.765117 WL = 0x2
5805 11:52:07.767568 RL = 0x2
5806 11:52:07.767956 BL = 0x2
5807 11:52:07.770514 RPST = 0x0
5808 11:52:07.770597 RD_PRE = 0x0
5809 11:52:07.774068 WR_PRE = 0x1
5810 11:52:07.774245 WR_PST = 0x0
5811 11:52:07.777366 DBI_WR = 0x0
5812 11:52:07.777536 DBI_RD = 0x0
5813 11:52:07.780627 OTF = 0x1
5814 11:52:07.783789 ===================================
5815 11:52:07.787248 ===================================
5816 11:52:07.787363 ANA top config
5817 11:52:07.790574 ===================================
5818 11:52:07.793958 DLL_ASYNC_EN = 0
5819 11:52:07.797234 ALL_SLAVE_EN = 1
5820 11:52:07.800456 NEW_RANK_MODE = 1
5821 11:52:07.800607 DLL_IDLE_MODE = 1
5822 11:52:07.803650 LP45_APHY_COMB_EN = 1
5823 11:52:07.807041 TX_ODT_DIS = 1
5824 11:52:07.810382 NEW_8X_MODE = 1
5825 11:52:07.813774 ===================================
5826 11:52:07.816959 ===================================
5827 11:52:07.820586 data_rate = 800
5828 11:52:07.820716 CKR = 1
5829 11:52:07.823702 DQ_P2S_RATIO = 4
5830 11:52:07.827138 ===================================
5831 11:52:07.830454 CA_P2S_RATIO = 4
5832 11:52:07.833623 DQ_CA_OPEN = 0
5833 11:52:07.837099 DQ_SEMI_OPEN = 1
5834 11:52:07.840459 CA_SEMI_OPEN = 1
5835 11:52:07.841132 CA_FULL_RATE = 0
5836 11:52:07.843672 DQ_CKDIV4_EN = 0
5837 11:52:07.847284 CA_CKDIV4_EN = 1
5838 11:52:07.850200 CA_PREDIV_EN = 0
5839 11:52:07.853536 PH8_DLY = 0
5840 11:52:07.856484 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5841 11:52:07.856596 DQ_AAMCK_DIV = 0
5842 11:52:07.860123 CA_AAMCK_DIV = 0
5843 11:52:07.863215 CA_ADMCK_DIV = 4
5844 11:52:07.866529 DQ_TRACK_CA_EN = 0
5845 11:52:07.869961 CA_PICK = 800
5846 11:52:07.873354 CA_MCKIO = 400
5847 11:52:07.876464 MCKIO_SEMI = 400
5848 11:52:07.879792 PLL_FREQ = 3016
5849 11:52:07.879884 DQ_UI_PI_RATIO = 32
5850 11:52:07.883002 CA_UI_PI_RATIO = 32
5851 11:52:07.886386 ===================================
5852 11:52:07.889669 ===================================
5853 11:52:07.892944 memory_type:LPDDR4
5854 11:52:07.896383 GP_NUM : 10
5855 11:52:07.896486 SRAM_EN : 1
5856 11:52:07.899731 MD32_EN : 0
5857 11:52:07.902857 ===================================
5858 11:52:07.906142 [ANA_INIT] >>>>>>>>>>>>>>
5859 11:52:07.906238 <<<<<< [CONFIGURE PHASE]: ANA_TX
5860 11:52:07.909598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5861 11:52:07.912932 ===================================
5862 11:52:07.916098 data_rate = 800,PCW = 0X7400
5863 11:52:07.919459 ===================================
5864 11:52:07.922872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5865 11:52:07.929500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5866 11:52:07.939324 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5867 11:52:07.946099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5868 11:52:07.949245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5869 11:52:07.952460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5870 11:52:07.955878 [ANA_INIT] flow start
5871 11:52:07.955997 [ANA_INIT] PLL >>>>>>>>
5872 11:52:07.959298 [ANA_INIT] PLL <<<<<<<<
5873 11:52:07.962643 [ANA_INIT] MIDPI >>>>>>>>
5874 11:52:07.962751 [ANA_INIT] MIDPI <<<<<<<<
5875 11:52:07.966296 [ANA_INIT] DLL >>>>>>>>
5876 11:52:07.969484 [ANA_INIT] flow end
5877 11:52:07.972886 ============ LP4 DIFF to SE enter ============
5878 11:52:07.975941 ============ LP4 DIFF to SE exit ============
5879 11:52:07.979190 [ANA_INIT] <<<<<<<<<<<<<
5880 11:52:07.982401 [Flow] Enable top DCM control >>>>>
5881 11:52:07.985786 [Flow] Enable top DCM control <<<<<
5882 11:52:07.989170 Enable DLL master slave shuffle
5883 11:52:07.992478 ==============================================================
5884 11:52:07.995988 Gating Mode config
5885 11:52:08.002595 ==============================================================
5886 11:52:08.002690 Config description:
5887 11:52:08.012386 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5888 11:52:08.018927 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5889 11:52:08.022145 SELPH_MODE 0: By rank 1: By Phase
5890 11:52:08.028892 ==============================================================
5891 11:52:08.032366 GAT_TRACK_EN = 0
5892 11:52:08.035505 RX_GATING_MODE = 2
5893 11:52:08.038869 RX_GATING_TRACK_MODE = 2
5894 11:52:08.042141 SELPH_MODE = 1
5895 11:52:08.045528 PICG_EARLY_EN = 1
5896 11:52:08.048731 VALID_LAT_VALUE = 1
5897 11:52:08.052078 ==============================================================
5898 11:52:08.055368 Enter into Gating configuration >>>>
5899 11:52:08.058786 Exit from Gating configuration <<<<
5900 11:52:08.061990 Enter into DVFS_PRE_config >>>>>
5901 11:52:08.075300 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5902 11:52:08.075410 Exit from DVFS_PRE_config <<<<<
5903 11:52:08.078599 Enter into PICG configuration >>>>
5904 11:52:08.081797 Exit from PICG configuration <<<<
5905 11:52:08.085175 [RX_INPUT] configuration >>>>>
5906 11:52:08.088493 [RX_INPUT] configuration <<<<<
5907 11:52:08.094920 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5908 11:52:08.098278 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5909 11:52:08.105127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5910 11:52:08.111602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5911 11:52:08.118081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5912 11:52:08.124538 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5913 11:52:08.127989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5914 11:52:08.131494 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5915 11:52:08.134738 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5916 11:52:08.141262 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5917 11:52:08.144792 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5918 11:52:08.147933 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5919 11:52:08.151194 ===================================
5920 11:52:08.154621 LPDDR4 DRAM CONFIGURATION
5921 11:52:08.157872 ===================================
5922 11:52:08.161415 EX_ROW_EN[0] = 0x0
5923 11:52:08.161519 EX_ROW_EN[1] = 0x0
5924 11:52:08.164751 LP4Y_EN = 0x0
5925 11:52:08.164835 WORK_FSP = 0x0
5926 11:52:08.167695 WL = 0x2
5927 11:52:08.167804 RL = 0x2
5928 11:52:08.171006 BL = 0x2
5929 11:52:08.171089 RPST = 0x0
5930 11:52:08.174514 RD_PRE = 0x0
5931 11:52:08.174668 WR_PRE = 0x1
5932 11:52:08.177671 WR_PST = 0x0
5933 11:52:08.177790 DBI_WR = 0x0
5934 11:52:08.181230 DBI_RD = 0x0
5935 11:52:08.181311 OTF = 0x1
5936 11:52:08.184310 ===================================
5937 11:52:08.187817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5938 11:52:08.194927 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5939 11:52:08.198187 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5940 11:52:08.201347 ===================================
5941 11:52:08.205178 LPDDR4 DRAM CONFIGURATION
5942 11:52:08.208017 ===================================
5943 11:52:08.208620 EX_ROW_EN[0] = 0x10
5944 11:52:08.211392 EX_ROW_EN[1] = 0x0
5945 11:52:08.214651 LP4Y_EN = 0x0
5946 11:52:08.215030 WORK_FSP = 0x0
5947 11:52:08.218096 WL = 0x2
5948 11:52:08.218477 RL = 0x2
5949 11:52:08.221276 BL = 0x2
5950 11:52:08.221653 RPST = 0x0
5951 11:52:08.224576 RD_PRE = 0x0
5952 11:52:08.224850 WR_PRE = 0x1
5953 11:52:08.228022 WR_PST = 0x0
5954 11:52:08.228410 DBI_WR = 0x0
5955 11:52:08.230970 DBI_RD = 0x0
5956 11:52:08.231180 OTF = 0x1
5957 11:52:08.234382 ===================================
5958 11:52:08.241068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5959 11:52:08.245084 nWR fixed to 30
5960 11:52:08.248317 [ModeRegInit_LP4] CH0 RK0
5961 11:52:08.248448 [ModeRegInit_LP4] CH0 RK1
5962 11:52:08.252145 [ModeRegInit_LP4] CH1 RK0
5963 11:52:08.255087 [ModeRegInit_LP4] CH1 RK1
5964 11:52:08.255217 match AC timing 18
5965 11:52:08.261876 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5966 11:52:08.264907 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5967 11:52:08.268528 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5968 11:52:08.275136 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5969 11:52:08.278157 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5970 11:52:08.278265 ==
5971 11:52:08.281649 Dram Type= 6, Freq= 0, CH_0, rank 0
5972 11:52:08.284997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5973 11:52:08.285105 ==
5974 11:52:08.291523 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5975 11:52:08.298103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5976 11:52:08.301495 [CA 0] Center 36 (8~64) winsize 57
5977 11:52:08.304971 [CA 1] Center 36 (8~64) winsize 57
5978 11:52:08.308386 [CA 2] Center 36 (8~64) winsize 57
5979 11:52:08.311707 [CA 3] Center 36 (8~64) winsize 57
5980 11:52:08.315089 [CA 4] Center 36 (8~64) winsize 57
5981 11:52:08.315722 [CA 5] Center 36 (8~64) winsize 57
5982 11:52:08.316287
5983 11:52:08.321512 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5984 11:52:08.321794
5985 11:52:08.324714 [CATrainingPosCal] consider 1 rank data
5986 11:52:08.328036 u2DelayCellTimex100 = 270/100 ps
5987 11:52:08.331788 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5988 11:52:08.334790 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5989 11:52:08.337873 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 11:52:08.341373 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 11:52:08.344615 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 11:52:08.347926 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 11:52:08.348073
5994 11:52:08.351225 CA PerBit enable=1, Macro0, CA PI delay=36
5995 11:52:08.351374
5996 11:52:08.355086 [CBTSetCACLKResult] CA Dly = 36
5997 11:52:08.357979 CS Dly: 1 (0~32)
5998 11:52:08.358209 ==
5999 11:52:08.361196 Dram Type= 6, Freq= 0, CH_0, rank 1
6000 11:52:08.364606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6001 11:52:08.364836 ==
6002 11:52:08.371189 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6003 11:52:08.378060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6004 11:52:08.381326 [CA 0] Center 36 (8~64) winsize 57
6005 11:52:08.381647 [CA 1] Center 36 (8~64) winsize 57
6006 11:52:08.384397 [CA 2] Center 36 (8~64) winsize 57
6007 11:52:08.387612 [CA 3] Center 36 (8~64) winsize 57
6008 11:52:08.391073 [CA 4] Center 36 (8~64) winsize 57
6009 11:52:08.394401 [CA 5] Center 36 (8~64) winsize 57
6010 11:52:08.394823
6011 11:52:08.398232 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6012 11:52:08.398762
6013 11:52:08.404706 [CATrainingPosCal] consider 2 rank data
6014 11:52:08.405236 u2DelayCellTimex100 = 270/100 ps
6015 11:52:08.407916 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 11:52:08.414547 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 11:52:08.418310 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 11:52:08.421032 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 11:52:08.424419 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 11:52:08.427758 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 11:52:08.428287
6022 11:52:08.430815 CA PerBit enable=1, Macro0, CA PI delay=36
6023 11:52:08.431239
6024 11:52:08.434622 [CBTSetCACLKResult] CA Dly = 36
6025 11:52:08.435154 CS Dly: 1 (0~32)
6026 11:52:08.437447
6027 11:52:08.441013 ----->DramcWriteLeveling(PI) begin...
6028 11:52:08.441458 ==
6029 11:52:08.444268 Dram Type= 6, Freq= 0, CH_0, rank 0
6030 11:52:08.448238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6031 11:52:08.448837 ==
6032 11:52:08.451290 Write leveling (Byte 0): 32 => 0
6033 11:52:08.454095 Write leveling (Byte 1): 32 => 0
6034 11:52:08.458049 DramcWriteLeveling(PI) end<-----
6035 11:52:08.458566
6036 11:52:08.458894 ==
6037 11:52:08.460912 Dram Type= 6, Freq= 0, CH_0, rank 0
6038 11:52:08.464682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 11:52:08.465288 ==
6040 11:52:08.467660 [Gating] SW mode calibration
6041 11:52:08.474552 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6042 11:52:08.481037 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6043 11:52:08.484557 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6044 11:52:08.487633 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6045 11:52:08.494393 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6046 11:52:08.497435 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6047 11:52:08.500929 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6048 11:52:08.504090 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6049 11:52:08.510849 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6050 11:52:08.514314 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6051 11:52:08.517747 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6052 11:52:08.520853 Total UI for P1: 0, mck2ui 16
6053 11:52:08.524083 best dqsien dly found for B0: ( 0, 10, 16)
6054 11:52:08.527433 Total UI for P1: 0, mck2ui 16
6055 11:52:08.530856 best dqsien dly found for B1: ( 0, 10, 24)
6056 11:52:08.534083 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6057 11:52:08.540755 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6058 11:52:08.541267
6059 11:52:08.543756 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6060 11:52:08.547337 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6061 11:52:08.550375 [Gating] SW calibration Done
6062 11:52:08.550792 ==
6063 11:52:08.553656 Dram Type= 6, Freq= 0, CH_0, rank 0
6064 11:52:08.556973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6065 11:52:08.557394 ==
6066 11:52:08.560467 RX Vref Scan: 0
6067 11:52:08.560936
6068 11:52:08.561270 RX Vref 0 -> 0, step: 1
6069 11:52:08.561578
6070 11:52:08.563951 RX Delay -410 -> 252, step: 16
6071 11:52:08.570637 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6072 11:52:08.573680 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6073 11:52:08.576900 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6074 11:52:08.580447 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6075 11:52:08.586808 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6076 11:52:08.590303 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6077 11:52:08.593274 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6078 11:52:08.596771 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6079 11:52:08.603773 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6080 11:52:08.606805 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6081 11:52:08.610200 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6082 11:52:08.613409 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6083 11:52:08.619555 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6084 11:52:08.623398 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6085 11:52:08.626765 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6086 11:52:08.629859 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6087 11:52:08.633148 ==
6088 11:52:08.636484 Dram Type= 6, Freq= 0, CH_0, rank 0
6089 11:52:08.639845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6090 11:52:08.640379 ==
6091 11:52:08.640879 DQS Delay:
6092 11:52:08.642723 DQS0 = 51, DQS1 = 59
6093 11:52:08.643236 DQM Delay:
6094 11:52:08.645966 DQM0 = 12, DQM1 = 12
6095 11:52:08.646386 DQ Delay:
6096 11:52:08.649197 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6097 11:52:08.652767 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6098 11:52:08.656369 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6099 11:52:08.659790 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6100 11:52:08.660313
6101 11:52:08.660743
6102 11:52:08.661065 ==
6103 11:52:08.662797 Dram Type= 6, Freq= 0, CH_0, rank 0
6104 11:52:08.666399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6105 11:52:08.666929 ==
6106 11:52:08.667262
6107 11:52:08.667570
6108 11:52:08.669186 TX Vref Scan disable
6109 11:52:08.669604 == TX Byte 0 ==
6110 11:52:08.676249 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6111 11:52:08.679584 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6112 11:52:08.680119 == TX Byte 1 ==
6113 11:52:08.685885 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6114 11:52:08.689212 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6115 11:52:08.689633 ==
6116 11:52:08.692654 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 11:52:08.695748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 11:52:08.696172 ==
6119 11:52:08.696501
6120 11:52:08.696874
6121 11:52:08.699533 TX Vref Scan disable
6122 11:52:08.702936 == TX Byte 0 ==
6123 11:52:08.706247 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6124 11:52:08.709032 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6125 11:52:08.712704 == TX Byte 1 ==
6126 11:52:08.716281 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 11:52:08.719278 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 11:52:08.719794
6129 11:52:08.720133 [DATLAT]
6130 11:52:08.722308 Freq=400, CH0 RK0
6131 11:52:08.722729
6132 11:52:08.725926 DATLAT Default: 0xf
6133 11:52:08.726438 0, 0xFFFF, sum = 0
6134 11:52:08.729570 1, 0xFFFF, sum = 0
6135 11:52:08.730097 2, 0xFFFF, sum = 0
6136 11:52:08.732657 3, 0xFFFF, sum = 0
6137 11:52:08.733184 4, 0xFFFF, sum = 0
6138 11:52:08.735807 5, 0xFFFF, sum = 0
6139 11:52:08.736327 6, 0xFFFF, sum = 0
6140 11:52:08.738810 7, 0xFFFF, sum = 0
6141 11:52:08.739237 8, 0xFFFF, sum = 0
6142 11:52:08.742390 9, 0xFFFF, sum = 0
6143 11:52:08.742914 10, 0xFFFF, sum = 0
6144 11:52:08.745221 11, 0xFFFF, sum = 0
6145 11:52:08.745649 12, 0x0, sum = 1
6146 11:52:08.748880 13, 0x0, sum = 2
6147 11:52:08.749305 14, 0x0, sum = 3
6148 11:52:08.752211 15, 0x0, sum = 4
6149 11:52:08.752768 best_step = 13
6150 11:52:08.753111
6151 11:52:08.753424 ==
6152 11:52:08.755369 Dram Type= 6, Freq= 0, CH_0, rank 0
6153 11:52:08.761989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6154 11:52:08.762504 ==
6155 11:52:08.762843 RX Vref Scan: 1
6156 11:52:08.763156
6157 11:52:08.765032 RX Vref 0 -> 0, step: 1
6158 11:52:08.765452
6159 11:52:08.768860 RX Delay -359 -> 252, step: 8
6160 11:52:08.769375
6161 11:52:08.772197 Set Vref, RX VrefLevel [Byte0]: 46
6162 11:52:08.775112 [Byte1]: 47
6163 11:52:08.775544
6164 11:52:08.778714 Final RX Vref Byte 0 = 46 to rank0
6165 11:52:08.781900 Final RX Vref Byte 1 = 47 to rank0
6166 11:52:08.785113 Final RX Vref Byte 0 = 46 to rank1
6167 11:52:08.788418 Final RX Vref Byte 1 = 47 to rank1==
6168 11:52:08.791858 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 11:52:08.795001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 11:52:08.798849 ==
6171 11:52:08.799481 DQS Delay:
6172 11:52:08.799825 DQS0 = 52, DQS1 = 68
6173 11:52:08.801402 DQM Delay:
6174 11:52:08.801819 DQM0 = 9, DQM1 = 17
6175 11:52:08.804964 DQ Delay:
6176 11:52:08.805382 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6177 11:52:08.808541 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6178 11:52:08.811948 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6179 11:52:08.815256 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6180 11:52:08.815780
6181 11:52:08.816131
6182 11:52:08.825171 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6183 11:52:08.828229 CH0 RK0: MR19=C0C, MR18=A0A0
6184 11:52:08.834802 CH0_RK0: MR19=0xC0C, MR18=0xA0A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6185 11:52:08.835329 ==
6186 11:52:08.837755 Dram Type= 6, Freq= 0, CH_0, rank 1
6187 11:52:08.841449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6188 11:52:08.841968 ==
6189 11:52:08.844318 [Gating] SW mode calibration
6190 11:52:08.851576 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6191 11:52:08.854960 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6192 11:52:08.861267 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6193 11:52:08.864604 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6194 11:52:08.867903 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6195 11:52:08.874653 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6196 11:52:08.877718 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6197 11:52:08.881177 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6198 11:52:08.887742 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6199 11:52:08.891006 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6200 11:52:08.894350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6201 11:52:08.897254 Total UI for P1: 0, mck2ui 16
6202 11:52:08.900968 best dqsien dly found for B0: ( 0, 10, 16)
6203 11:52:08.903751 Total UI for P1: 0, mck2ui 16
6204 11:52:08.907767 best dqsien dly found for B1: ( 0, 10, 24)
6205 11:52:08.910850 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6206 11:52:08.917471 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6207 11:52:08.918007
6208 11:52:08.920612 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6209 11:52:08.923913 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6210 11:52:08.927288 [Gating] SW calibration Done
6211 11:52:08.927825 ==
6212 11:52:08.930885 Dram Type= 6, Freq= 0, CH_0, rank 1
6213 11:52:08.934186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6214 11:52:08.934722 ==
6215 11:52:08.937178 RX Vref Scan: 0
6216 11:52:08.937691
6217 11:52:08.938137 RX Vref 0 -> 0, step: 1
6218 11:52:08.938554
6219 11:52:08.940375 RX Delay -410 -> 252, step: 16
6220 11:52:08.947102 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6221 11:52:08.949838 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6222 11:52:08.953348 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6223 11:52:08.956802 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6224 11:52:08.963447 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6225 11:52:08.966658 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6226 11:52:08.970280 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6227 11:52:08.974086 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6228 11:52:08.980064 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6229 11:52:08.982918 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6230 11:52:08.986526 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6231 11:52:08.989716 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6232 11:52:08.996279 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6233 11:52:08.999776 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6234 11:52:09.003192 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6235 11:52:09.006545 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6236 11:52:09.010195 ==
6237 11:52:09.013173 Dram Type= 6, Freq= 0, CH_0, rank 1
6238 11:52:09.016865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6239 11:52:09.017384 ==
6240 11:52:09.017716 DQS Delay:
6241 11:52:09.019910 DQS0 = 43, DQS1 = 59
6242 11:52:09.020328 DQM Delay:
6243 11:52:09.023259 DQM0 = 7, DQM1 = 15
6244 11:52:09.023772 DQ Delay:
6245 11:52:09.026601 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6246 11:52:09.029564 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6247 11:52:09.032702 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6248 11:52:09.036539 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6249 11:52:09.037066
6250 11:52:09.037398
6251 11:52:09.037705 ==
6252 11:52:09.039663 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 11:52:09.042921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6254 11:52:09.043438 ==
6255 11:52:09.043774
6256 11:52:09.044082
6257 11:52:09.046464 TX Vref Scan disable
6258 11:52:09.046881 == TX Byte 0 ==
6259 11:52:09.052676 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6260 11:52:09.056060 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6261 11:52:09.056481 == TX Byte 1 ==
6262 11:52:09.062974 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6263 11:52:09.066453 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6264 11:52:09.066873 ==
6265 11:52:09.069772 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 11:52:09.072643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 11:52:09.073069 ==
6268 11:52:09.073407
6269 11:52:09.073716
6270 11:52:09.075737 TX Vref Scan disable
6271 11:52:09.076157 == TX Byte 0 ==
6272 11:52:09.082630 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6273 11:52:09.085789 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6274 11:52:09.086298 == TX Byte 1 ==
6275 11:52:09.092618 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6276 11:52:09.095702 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6277 11:52:09.096121
6278 11:52:09.096496 [DATLAT]
6279 11:52:09.099020 Freq=400, CH0 RK1
6280 11:52:09.099438
6281 11:52:09.099771 DATLAT Default: 0xd
6282 11:52:09.102834 0, 0xFFFF, sum = 0
6283 11:52:09.103364 1, 0xFFFF, sum = 0
6284 11:52:09.105847 2, 0xFFFF, sum = 0
6285 11:52:09.106371 3, 0xFFFF, sum = 0
6286 11:52:09.109068 4, 0xFFFF, sum = 0
6287 11:52:09.109494 5, 0xFFFF, sum = 0
6288 11:52:09.112408 6, 0xFFFF, sum = 0
6289 11:52:09.113163 7, 0xFFFF, sum = 0
6290 11:52:09.115685 8, 0xFFFF, sum = 0
6291 11:52:09.116109 9, 0xFFFF, sum = 0
6292 11:52:09.119193 10, 0xFFFF, sum = 0
6293 11:52:09.122177 11, 0xFFFF, sum = 0
6294 11:52:09.122597 12, 0x0, sum = 1
6295 11:52:09.125323 13, 0x0, sum = 2
6296 11:52:09.125741 14, 0x0, sum = 3
6297 11:52:09.126075 15, 0x0, sum = 4
6298 11:52:09.128750 best_step = 13
6299 11:52:09.129163
6300 11:52:09.129489 ==
6301 11:52:09.131854 Dram Type= 6, Freq= 0, CH_0, rank 1
6302 11:52:09.135432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6303 11:52:09.135848 ==
6304 11:52:09.138527 RX Vref Scan: 0
6305 11:52:09.138942
6306 11:52:09.139269 RX Vref 0 -> 0, step: 1
6307 11:52:09.142421
6308 11:52:09.142930 RX Delay -359 -> 252, step: 8
6309 11:52:09.150577 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6310 11:52:09.154167 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6311 11:52:09.157075 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6312 11:52:09.160538 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6313 11:52:09.167238 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6314 11:52:09.170819 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6315 11:52:09.173964 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6316 11:52:09.177104 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6317 11:52:09.183662 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6318 11:52:09.186972 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6319 11:52:09.190174 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6320 11:52:09.196862 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6321 11:52:09.200298 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6322 11:52:09.203597 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6323 11:52:09.206966 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6324 11:52:09.213948 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6325 11:52:09.214461 ==
6326 11:52:09.216605 Dram Type= 6, Freq= 0, CH_0, rank 1
6327 11:52:09.220296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6328 11:52:09.220864 ==
6329 11:52:09.221202 DQS Delay:
6330 11:52:09.223533 DQS0 = 52, DQS1 = 64
6331 11:52:09.223943 DQM Delay:
6332 11:52:09.226820 DQM0 = 10, DQM1 = 13
6333 11:52:09.227237 DQ Delay:
6334 11:52:09.230416 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6335 11:52:09.233657 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6336 11:52:09.236794 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6337 11:52:09.240258 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6338 11:52:09.240837
6339 11:52:09.241174
6340 11:52:09.246469 [DQSOSCAuto] RK1, (LSB)MR18= 0xbebe, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6341 11:52:09.249978 CH0 RK1: MR19=C0C, MR18=BEBE
6342 11:52:09.256640 CH0_RK1: MR19=0xC0C, MR18=0xBEBE, DQSOSC=386, MR23=63, INC=396, DEC=264
6343 11:52:09.260012 [RxdqsGatingPostProcess] freq 400
6344 11:52:09.266743 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6345 11:52:09.270063 Pre-setting of DQS Precalculation
6346 11:52:09.273117 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6347 11:52:09.273532 ==
6348 11:52:09.276431 Dram Type= 6, Freq= 0, CH_1, rank 0
6349 11:52:09.279933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6350 11:52:09.280448 ==
6351 11:52:09.286901 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6352 11:52:09.292885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6353 11:52:09.296080 [CA 0] Center 36 (8~64) winsize 57
6354 11:52:09.299949 [CA 1] Center 36 (8~64) winsize 57
6355 11:52:09.302927 [CA 2] Center 36 (8~64) winsize 57
6356 11:52:09.306275 [CA 3] Center 36 (8~64) winsize 57
6357 11:52:09.309481 [CA 4] Center 36 (8~64) winsize 57
6358 11:52:09.309992 [CA 5] Center 36 (8~64) winsize 57
6359 11:52:09.313127
6360 11:52:09.316300 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6361 11:52:09.316864
6362 11:52:09.319646 [CATrainingPosCal] consider 1 rank data
6363 11:52:09.322858 u2DelayCellTimex100 = 270/100 ps
6364 11:52:09.326107 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 11:52:09.329285 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 11:52:09.332558 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 11:52:09.336095 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 11:52:09.339006 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 11:52:09.342689 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 11:52:09.343225
6371 11:52:09.345683 CA PerBit enable=1, Macro0, CA PI delay=36
6372 11:52:09.346110
6373 11:52:09.349208 [CBTSetCACLKResult] CA Dly = 36
6374 11:52:09.352746 CS Dly: 1 (0~32)
6375 11:52:09.353254 ==
6376 11:52:09.356091 Dram Type= 6, Freq= 0, CH_1, rank 1
6377 11:52:09.359205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6378 11:52:09.359723 ==
6379 11:52:09.365816 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6380 11:52:09.372567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6381 11:52:09.375825 [CA 0] Center 36 (8~64) winsize 57
6382 11:52:09.379057 [CA 1] Center 36 (8~64) winsize 57
6383 11:52:09.379574 [CA 2] Center 36 (8~64) winsize 57
6384 11:52:09.382306 [CA 3] Center 36 (8~64) winsize 57
6385 11:52:09.385328 [CA 4] Center 36 (8~64) winsize 57
6386 11:52:09.388924 [CA 5] Center 36 (8~64) winsize 57
6387 11:52:09.389491
6388 11:52:09.392216 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6389 11:52:09.392795
6390 11:52:09.398903 [CATrainingPosCal] consider 2 rank data
6391 11:52:09.399422 u2DelayCellTimex100 = 270/100 ps
6392 11:52:09.405561 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 11:52:09.408907 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 11:52:09.412582 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 11:52:09.415716 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 11:52:09.419152 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 11:52:09.422032 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 11:52:09.422548
6399 11:52:09.425516 CA PerBit enable=1, Macro0, CA PI delay=36
6400 11:52:09.426029
6401 11:52:09.428857 [CBTSetCACLKResult] CA Dly = 36
6402 11:52:09.432287 CS Dly: 1 (0~32)
6403 11:52:09.432868
6404 11:52:09.435196 ----->DramcWriteLeveling(PI) begin...
6405 11:52:09.435644 ==
6406 11:52:09.438698 Dram Type= 6, Freq= 0, CH_1, rank 0
6407 11:52:09.441657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6408 11:52:09.442078 ==
6409 11:52:09.445001 Write leveling (Byte 0): 32 => 0
6410 11:52:09.448389 Write leveling (Byte 1): 32 => 0
6411 11:52:09.451812 DramcWriteLeveling(PI) end<-----
6412 11:52:09.452325
6413 11:52:09.452723 ==
6414 11:52:09.455034 Dram Type= 6, Freq= 0, CH_1, rank 0
6415 11:52:09.458697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 11:52:09.459211 ==
6417 11:52:09.461911 [Gating] SW mode calibration
6418 11:52:09.468604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 11:52:09.475337 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6420 11:52:09.478791 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 11:52:09.482014 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 11:52:09.488330 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 11:52:09.491516 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6424 11:52:09.494652 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:52:09.501661 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:52:09.505440 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:52:09.508813 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6428 11:52:09.515023 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:52:09.515543 Total UI for P1: 0, mck2ui 16
6430 11:52:09.521458 best dqsien dly found for B0: ( 0, 10, 16)
6431 11:52:09.521975 Total UI for P1: 0, mck2ui 16
6432 11:52:09.527832 best dqsien dly found for B1: ( 0, 10, 16)
6433 11:52:09.531582 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6434 11:52:09.534498 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6435 11:52:09.534972
6436 11:52:09.537857 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6437 11:52:09.541380 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6438 11:52:09.544284 [Gating] SW calibration Done
6439 11:52:09.544817 ==
6440 11:52:09.547893 Dram Type= 6, Freq= 0, CH_1, rank 0
6441 11:52:09.551095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6442 11:52:09.551549 ==
6443 11:52:09.554911 RX Vref Scan: 0
6444 11:52:09.555540
6445 11:52:09.555986 RX Vref 0 -> 0, step: 1
6446 11:52:09.556400
6447 11:52:09.558303 RX Delay -410 -> 252, step: 16
6448 11:52:09.564475 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6449 11:52:09.568036 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6450 11:52:09.571038 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6451 11:52:09.574635 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6452 11:52:09.580973 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6453 11:52:09.584459 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6454 11:52:09.587853 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6455 11:52:09.590901 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6456 11:52:09.597271 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6457 11:52:09.600805 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6458 11:52:09.604278 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6459 11:52:09.608110 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6460 11:52:09.613958 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6461 11:52:09.617535 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6462 11:52:09.620659 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6463 11:52:09.627305 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6464 11:52:09.627740 ==
6465 11:52:09.630865 Dram Type= 6, Freq= 0, CH_1, rank 0
6466 11:52:09.634300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6467 11:52:09.634740 ==
6468 11:52:09.635215 DQS Delay:
6469 11:52:09.637212 DQS0 = 43, DQS1 = 59
6470 11:52:09.637645 DQM Delay:
6471 11:52:09.640419 DQM0 = 6, DQM1 = 14
6472 11:52:09.640901 DQ Delay:
6473 11:52:09.643658 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6474 11:52:09.648042 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6475 11:52:09.650426 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 11:52:09.653692 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6477 11:52:09.654108
6478 11:52:09.654438
6479 11:52:09.654742 ==
6480 11:52:09.657000 Dram Type= 6, Freq= 0, CH_1, rank 0
6481 11:52:09.660221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6482 11:52:09.660683 ==
6483 11:52:09.661027
6484 11:52:09.661334
6485 11:52:09.663980 TX Vref Scan disable
6486 11:52:09.664502 == TX Byte 0 ==
6487 11:52:09.670523 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6488 11:52:09.673873 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6489 11:52:09.674400 == TX Byte 1 ==
6490 11:52:09.680668 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6491 11:52:09.684016 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6492 11:52:09.684592 ==
6493 11:52:09.686966 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 11:52:09.690444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 11:52:09.690879 ==
6496 11:52:09.691211
6497 11:52:09.691518
6498 11:52:09.693363 TX Vref Scan disable
6499 11:52:09.696880 == TX Byte 0 ==
6500 11:52:09.700237 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6501 11:52:09.703951 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6502 11:52:09.706987 == TX Byte 1 ==
6503 11:52:09.710085 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 11:52:09.713758 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 11:52:09.714380
6506 11:52:09.714726 [DATLAT]
6507 11:52:09.717262 Freq=400, CH1 RK0
6508 11:52:09.717686
6509 11:52:09.720241 DATLAT Default: 0xf
6510 11:52:09.720702 0, 0xFFFF, sum = 0
6511 11:52:09.723808 1, 0xFFFF, sum = 0
6512 11:52:09.724371 2, 0xFFFF, sum = 0
6513 11:52:09.726955 3, 0xFFFF, sum = 0
6514 11:52:09.727485 4, 0xFFFF, sum = 0
6515 11:52:09.730338 5, 0xFFFF, sum = 0
6516 11:52:09.730866 6, 0xFFFF, sum = 0
6517 11:52:09.733251 7, 0xFFFF, sum = 0
6518 11:52:09.733679 8, 0xFFFF, sum = 0
6519 11:52:09.737138 9, 0xFFFF, sum = 0
6520 11:52:09.737662 10, 0xFFFF, sum = 0
6521 11:52:09.740425 11, 0xFFFF, sum = 0
6522 11:52:09.740990 12, 0x0, sum = 1
6523 11:52:09.743676 13, 0x0, sum = 2
6524 11:52:09.744220 14, 0x0, sum = 3
6525 11:52:09.746866 15, 0x0, sum = 4
6526 11:52:09.747396 best_step = 13
6527 11:52:09.747768
6528 11:52:09.748084 ==
6529 11:52:09.749977 Dram Type= 6, Freq= 0, CH_1, rank 0
6530 11:52:09.756493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6531 11:52:09.756946 ==
6532 11:52:09.757283 RX Vref Scan: 1
6533 11:52:09.757640
6534 11:52:09.759937 RX Vref 0 -> 0, step: 1
6535 11:52:09.760380
6536 11:52:09.762969 RX Delay -359 -> 252, step: 8
6537 11:52:09.763389
6538 11:52:09.766458 Set Vref, RX VrefLevel [Byte0]: 52
6539 11:52:09.769623 [Byte1]: 49
6540 11:52:09.770044
6541 11:52:09.772909 Final RX Vref Byte 0 = 52 to rank0
6542 11:52:09.776137 Final RX Vref Byte 1 = 49 to rank0
6543 11:52:09.779496 Final RX Vref Byte 0 = 52 to rank1
6544 11:52:09.782925 Final RX Vref Byte 1 = 49 to rank1==
6545 11:52:09.786161 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 11:52:09.789411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 11:52:09.792634 ==
6548 11:52:09.793050 DQS Delay:
6549 11:52:09.793379 DQS0 = 48, DQS1 = 64
6550 11:52:09.795984 DQM Delay:
6551 11:52:09.796542 DQM0 = 8, DQM1 = 16
6552 11:52:09.799514 DQ Delay:
6553 11:52:09.800025 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6554 11:52:09.802973 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6555 11:52:09.806462 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6556 11:52:09.809479 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6557 11:52:09.809997
6558 11:52:09.810327
6559 11:52:09.819475 [DQSOSCAuto] RK0, (LSB)MR18= 0xe3e3, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6560 11:52:09.822905 CH1 RK0: MR19=C0C, MR18=E3E3
6561 11:52:09.826107 CH1_RK0: MR19=0xC0C, MR18=0xE3E3, DQSOSC=381, MR23=63, INC=406, DEC=271
6562 11:52:09.829443 ==
6563 11:52:09.832471 Dram Type= 6, Freq= 0, CH_1, rank 1
6564 11:52:09.836051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6565 11:52:09.836628 ==
6566 11:52:09.839096 [Gating] SW mode calibration
6567 11:52:09.846142 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6568 11:52:09.849543 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6569 11:52:09.856034 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6570 11:52:09.859212 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6571 11:52:09.862383 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6572 11:52:09.868841 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6573 11:52:09.872682 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6574 11:52:09.875710 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6575 11:52:09.882380 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6576 11:52:09.885307 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6577 11:52:09.888746 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6578 11:52:09.891923 Total UI for P1: 0, mck2ui 16
6579 11:52:09.895468 best dqsien dly found for B0: ( 0, 10, 16)
6580 11:52:09.898511 Total UI for P1: 0, mck2ui 16
6581 11:52:09.901640 best dqsien dly found for B1: ( 0, 10, 16)
6582 11:52:09.905535 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6583 11:52:09.908692 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6584 11:52:09.909203
6585 11:52:09.915301 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6586 11:52:09.918841 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6587 11:52:09.922204 [Gating] SW calibration Done
6588 11:52:09.922720 ==
6589 11:52:09.925341 Dram Type= 6, Freq= 0, CH_1, rank 1
6590 11:52:09.928560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6591 11:52:09.929084 ==
6592 11:52:09.929456 RX Vref Scan: 0
6593 11:52:09.931931
6594 11:52:09.932346 RX Vref 0 -> 0, step: 1
6595 11:52:09.932752
6596 11:52:09.935331 RX Delay -410 -> 252, step: 16
6597 11:52:09.938439 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6598 11:52:09.945104 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6599 11:52:09.948773 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6600 11:52:09.951580 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6601 11:52:09.955224 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6602 11:52:09.961329 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6603 11:52:09.964888 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6604 11:52:09.968153 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6605 11:52:09.971761 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6606 11:52:09.977956 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6607 11:52:09.981392 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6608 11:52:09.984738 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6609 11:52:09.987863 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6610 11:52:09.994481 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6611 11:52:09.997785 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6612 11:52:10.001148 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6613 11:52:10.001691 ==
6614 11:52:10.004408 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 11:52:10.010926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6616 11:52:10.011443 ==
6617 11:52:10.011806 DQS Delay:
6618 11:52:10.014369 DQS0 = 43, DQS1 = 59
6619 11:52:10.014905 DQM Delay:
6620 11:52:10.018023 DQM0 = 10, DQM1 = 17
6621 11:52:10.018538 DQ Delay:
6622 11:52:10.021261 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6623 11:52:10.024750 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6624 11:52:10.025264 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6625 11:52:10.027598 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6626 11:52:10.030869
6627 11:52:10.031383
6628 11:52:10.031720 ==
6629 11:52:10.034116 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 11:52:10.037556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6631 11:52:10.038138 ==
6632 11:52:10.038495
6633 11:52:10.038808
6634 11:52:10.041046 TX Vref Scan disable
6635 11:52:10.041561 == TX Byte 0 ==
6636 11:52:10.043762 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6637 11:52:10.050607 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6638 11:52:10.051217 == TX Byte 1 ==
6639 11:52:10.054210 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6640 11:52:10.060972 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6641 11:52:10.061499 ==
6642 11:52:10.064020 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 11:52:10.067292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 11:52:10.067836 ==
6645 11:52:10.068319
6646 11:52:10.068807
6647 11:52:10.070569 TX Vref Scan disable
6648 11:52:10.071085 == TX Byte 0 ==
6649 11:52:10.074106 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6650 11:52:10.080708 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6651 11:52:10.081228 == TX Byte 1 ==
6652 11:52:10.084295 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6653 11:52:10.090499 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6654 11:52:10.091004
6655 11:52:10.091335 [DATLAT]
6656 11:52:10.093510 Freq=400, CH1 RK1
6657 11:52:10.093928
6658 11:52:10.094258 DATLAT Default: 0xd
6659 11:52:10.097242 0, 0xFFFF, sum = 0
6660 11:52:10.097788 1, 0xFFFF, sum = 0
6661 11:52:10.100591 2, 0xFFFF, sum = 0
6662 11:52:10.101115 3, 0xFFFF, sum = 0
6663 11:52:10.104173 4, 0xFFFF, sum = 0
6664 11:52:10.104744 5, 0xFFFF, sum = 0
6665 11:52:10.107046 6, 0xFFFF, sum = 0
6666 11:52:10.107564 7, 0xFFFF, sum = 0
6667 11:52:10.110579 8, 0xFFFF, sum = 0
6668 11:52:10.111101 9, 0xFFFF, sum = 0
6669 11:52:10.113328 10, 0xFFFF, sum = 0
6670 11:52:10.113747 11, 0xFFFF, sum = 0
6671 11:52:10.116830 12, 0x0, sum = 1
6672 11:52:10.117272 13, 0x0, sum = 2
6673 11:52:10.120075 14, 0x0, sum = 3
6674 11:52:10.120646 15, 0x0, sum = 4
6675 11:52:10.124101 best_step = 13
6676 11:52:10.124662
6677 11:52:10.125002 ==
6678 11:52:10.126855 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 11:52:10.130034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6680 11:52:10.130456 ==
6681 11:52:10.133884 RX Vref Scan: 0
6682 11:52:10.134401
6683 11:52:10.134731 RX Vref 0 -> 0, step: 1
6684 11:52:10.135037
6685 11:52:10.136848 RX Delay -359 -> 252, step: 8
6686 11:52:10.145446 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6687 11:52:10.148092 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6688 11:52:10.151308 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6689 11:52:10.161159 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6690 11:52:10.161255 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6691 11:52:10.164453 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6692 11:52:10.168154 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6693 11:52:10.171232 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6694 11:52:10.177753 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6695 11:52:10.180904 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6696 11:52:10.184692 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6697 11:52:10.188055 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6698 11:52:10.194416 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6699 11:52:10.197331 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6700 11:52:10.201015 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6701 11:52:10.207845 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6702 11:52:10.208120 ==
6703 11:52:10.211446 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 11:52:10.214428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6705 11:52:10.214741 ==
6706 11:52:10.214930 DQS Delay:
6707 11:52:10.217677 DQS0 = 48, DQS1 = 64
6708 11:52:10.218046 DQM Delay:
6709 11:52:10.221432 DQM0 = 9, DQM1 = 15
6710 11:52:10.221887 DQ Delay:
6711 11:52:10.224453 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6712 11:52:10.227934 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6713 11:52:10.231356 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6714 11:52:10.234398 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6715 11:52:10.234914
6716 11:52:10.235242
6717 11:52:10.241136 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6718 11:52:10.244674 CH1 RK1: MR19=C0C, MR18=A8A8
6719 11:52:10.250959 CH1_RK1: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6720 11:52:10.254671 [RxdqsGatingPostProcess] freq 400
6721 11:52:10.260721 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6722 11:52:10.261139 Pre-setting of DQS Precalculation
6723 11:52:10.268162 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6724 11:52:10.274436 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6725 11:52:10.280724 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6726 11:52:10.281146
6727 11:52:10.281478
6728 11:52:10.284373 [Calibration Summary] 800 Mbps
6729 11:52:10.287868 CH 0, Rank 0
6730 11:52:10.288389 SW Impedance : PASS
6731 11:52:10.290607 DUTY Scan : NO K
6732 11:52:10.291132 ZQ Calibration : PASS
6733 11:52:10.294121 Jitter Meter : NO K
6734 11:52:10.297409 CBT Training : PASS
6735 11:52:10.298237 Write leveling : PASS
6736 11:52:10.300627 RX DQS gating : PASS
6737 11:52:10.303794 RX DQ/DQS(RDDQC) : PASS
6738 11:52:10.304296 TX DQ/DQS : PASS
6739 11:52:10.307616 RX DATLAT : PASS
6740 11:52:10.310949 RX DQ/DQS(Engine): PASS
6741 11:52:10.311470 TX OE : NO K
6742 11:52:10.314151 All Pass.
6743 11:52:10.314664
6744 11:52:10.315002 CH 0, Rank 1
6745 11:52:10.317340 SW Impedance : PASS
6746 11:52:10.317861 DUTY Scan : NO K
6747 11:52:10.320901 ZQ Calibration : PASS
6748 11:52:10.324060 Jitter Meter : NO K
6749 11:52:10.324483 CBT Training : PASS
6750 11:52:10.327516 Write leveling : NO K
6751 11:52:10.330694 RX DQS gating : PASS
6752 11:52:10.331209 RX DQ/DQS(RDDQC) : PASS
6753 11:52:10.334252 TX DQ/DQS : PASS
6754 11:52:10.337536 RX DATLAT : PASS
6755 11:52:10.337961 RX DQ/DQS(Engine): PASS
6756 11:52:10.340750 TX OE : NO K
6757 11:52:10.341264 All Pass.
6758 11:52:10.341600
6759 11:52:10.341912 CH 1, Rank 0
6760 11:52:10.344197 SW Impedance : PASS
6761 11:52:10.347536 DUTY Scan : NO K
6762 11:52:10.348049 ZQ Calibration : PASS
6763 11:52:10.351168 Jitter Meter : NO K
6764 11:52:10.353758 CBT Training : PASS
6765 11:52:10.354182 Write leveling : PASS
6766 11:52:10.357191 RX DQS gating : PASS
6767 11:52:10.360450 RX DQ/DQS(RDDQC) : PASS
6768 11:52:10.360907 TX DQ/DQS : PASS
6769 11:52:10.364018 RX DATLAT : PASS
6770 11:52:10.367404 RX DQ/DQS(Engine): PASS
6771 11:52:10.367917 TX OE : NO K
6772 11:52:10.370776 All Pass.
6773 11:52:10.371285
6774 11:52:10.371618 CH 1, Rank 1
6775 11:52:10.373714 SW Impedance : PASS
6776 11:52:10.374137 DUTY Scan : NO K
6777 11:52:10.377292 ZQ Calibration : PASS
6778 11:52:10.380461 Jitter Meter : NO K
6779 11:52:10.380926 CBT Training : PASS
6780 11:52:10.383736 Write leveling : NO K
6781 11:52:10.384160 RX DQS gating : PASS
6782 11:52:10.387409 RX DQ/DQS(RDDQC) : PASS
6783 11:52:10.390570 TX DQ/DQS : PASS
6784 11:52:10.391164 RX DATLAT : PASS
6785 11:52:10.393744 RX DQ/DQS(Engine): PASS
6786 11:52:10.397112 TX OE : NO K
6787 11:52:10.397545 All Pass.
6788 11:52:10.397883
6789 11:52:10.400409 DramC Write-DBI off
6790 11:52:10.400851 PER_BANK_REFRESH: Hybrid Mode
6791 11:52:10.403950 TX_TRACKING: ON
6792 11:52:10.414196 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6793 11:52:10.417137 [FAST_K] Save calibration result to emmc
6794 11:52:10.420642 dramc_set_vcore_voltage set vcore to 725000
6795 11:52:10.423875 Read voltage for 1600, 0
6796 11:52:10.424389 Vio18 = 0
6797 11:52:10.424768 Vcore = 725000
6798 11:52:10.425085 Vdram = 0
6799 11:52:10.426915 Vddq = 0
6800 11:52:10.427335 Vmddr = 0
6801 11:52:10.434007 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6802 11:52:10.437197 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6803 11:52:10.439954 MEM_TYPE=3, freq_sel=13
6804 11:52:10.444156 sv_algorithm_assistance_LP4_3733
6805 11:52:10.447326 ============ PULL DRAM RESETB DOWN ============
6806 11:52:10.450783 ========== PULL DRAM RESETB DOWN end =========
6807 11:52:10.456767 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6808 11:52:10.460263 ===================================
6809 11:52:10.460729 LPDDR4 DRAM CONFIGURATION
6810 11:52:10.463716 ===================================
6811 11:52:10.466975 EX_ROW_EN[0] = 0x0
6812 11:52:10.470253 EX_ROW_EN[1] = 0x0
6813 11:52:10.470768 LP4Y_EN = 0x0
6814 11:52:10.473720 WORK_FSP = 0x1
6815 11:52:10.474241 WL = 0x5
6816 11:52:10.476741 RL = 0x5
6817 11:52:10.477260 BL = 0x2
6818 11:52:10.480109 RPST = 0x0
6819 11:52:10.480683 RD_PRE = 0x0
6820 11:52:10.483558 WR_PRE = 0x1
6821 11:52:10.484080 WR_PST = 0x1
6822 11:52:10.486835 DBI_WR = 0x0
6823 11:52:10.487570 DBI_RD = 0x0
6824 11:52:10.490135 OTF = 0x1
6825 11:52:10.493401 ===================================
6826 11:52:10.497150 ===================================
6827 11:52:10.497687 ANA top config
6828 11:52:10.500348 ===================================
6829 11:52:10.503905 DLL_ASYNC_EN = 0
6830 11:52:10.507009 ALL_SLAVE_EN = 0
6831 11:52:10.507523 NEW_RANK_MODE = 1
6832 11:52:10.510283 DLL_IDLE_MODE = 1
6833 11:52:10.513554 LP45_APHY_COMB_EN = 1
6834 11:52:10.516740 TX_ODT_DIS = 0
6835 11:52:10.520162 NEW_8X_MODE = 1
6836 11:52:10.523574 ===================================
6837 11:52:10.526880 ===================================
6838 11:52:10.527476 data_rate = 3200
6839 11:52:10.529902 CKR = 1
6840 11:52:10.533396 DQ_P2S_RATIO = 8
6841 11:52:10.536560 ===================================
6842 11:52:10.540180 CA_P2S_RATIO = 8
6843 11:52:10.543913 DQ_CA_OPEN = 0
6844 11:52:10.546599 DQ_SEMI_OPEN = 0
6845 11:52:10.547115 CA_SEMI_OPEN = 0
6846 11:52:10.549923 CA_FULL_RATE = 0
6847 11:52:10.553493 DQ_CKDIV4_EN = 0
6848 11:52:10.556401 CA_CKDIV4_EN = 0
6849 11:52:10.559896 CA_PREDIV_EN = 0
6850 11:52:10.563249 PH8_DLY = 12
6851 11:52:10.563818 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6852 11:52:10.566410 DQ_AAMCK_DIV = 4
6853 11:52:10.569689 CA_AAMCK_DIV = 4
6854 11:52:10.572849 CA_ADMCK_DIV = 4
6855 11:52:10.576740 DQ_TRACK_CA_EN = 0
6856 11:52:10.579736 CA_PICK = 1600
6857 11:52:10.583171 CA_MCKIO = 1600
6858 11:52:10.583684 MCKIO_SEMI = 0
6859 11:52:10.586574 PLL_FREQ = 3068
6860 11:52:10.589661 DQ_UI_PI_RATIO = 32
6861 11:52:10.592696 CA_UI_PI_RATIO = 0
6862 11:52:10.596324 ===================================
6863 11:52:10.599412 ===================================
6864 11:52:10.602556 memory_type:LPDDR4
6865 11:52:10.603078 GP_NUM : 10
6866 11:52:10.606024 SRAM_EN : 1
6867 11:52:10.609678 MD32_EN : 0
6868 11:52:10.612778 ===================================
6869 11:52:10.613339 [ANA_INIT] >>>>>>>>>>>>>>
6870 11:52:10.615898 <<<<<< [CONFIGURE PHASE]: ANA_TX
6871 11:52:10.619304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6872 11:52:10.622577 ===================================
6873 11:52:10.625989 data_rate = 3200,PCW = 0X7600
6874 11:52:10.629400 ===================================
6875 11:52:10.632775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6876 11:52:10.639494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6877 11:52:10.642805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6878 11:52:10.649344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6879 11:52:10.652673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6880 11:52:10.655577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6881 11:52:10.659249 [ANA_INIT] flow start
6882 11:52:10.659836 [ANA_INIT] PLL >>>>>>>>
6883 11:52:10.662337 [ANA_INIT] PLL <<<<<<<<
6884 11:52:10.665269 [ANA_INIT] MIDPI >>>>>>>>
6885 11:52:10.665734 [ANA_INIT] MIDPI <<<<<<<<
6886 11:52:10.668955 [ANA_INIT] DLL >>>>>>>>
6887 11:52:10.672185 [ANA_INIT] DLL <<<<<<<<
6888 11:52:10.672892 [ANA_INIT] flow end
6889 11:52:10.679121 ============ LP4 DIFF to SE enter ============
6890 11:52:10.681872 ============ LP4 DIFF to SE exit ============
6891 11:52:10.682341 [ANA_INIT] <<<<<<<<<<<<<
6892 11:52:10.685540 [Flow] Enable top DCM control >>>>>
6893 11:52:10.688486 [Flow] Enable top DCM control <<<<<
6894 11:52:10.691874 Enable DLL master slave shuffle
6895 11:52:10.698767 ==============================================================
6896 11:52:10.701595 Gating Mode config
6897 11:52:10.705059 ==============================================================
6898 11:52:10.708710 Config description:
6899 11:52:10.718345 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6900 11:52:10.725081 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6901 11:52:10.728488 SELPH_MODE 0: By rank 1: By Phase
6902 11:52:10.735140 ==============================================================
6903 11:52:10.738256 GAT_TRACK_EN = 1
6904 11:52:10.741656 RX_GATING_MODE = 2
6905 11:52:10.745072 RX_GATING_TRACK_MODE = 2
6906 11:52:10.745594 SELPH_MODE = 1
6907 11:52:10.748374 PICG_EARLY_EN = 1
6908 11:52:10.751845 VALID_LAT_VALUE = 1
6909 11:52:10.758287 ==============================================================
6910 11:52:10.761379 Enter into Gating configuration >>>>
6911 11:52:10.764977 Exit from Gating configuration <<<<
6912 11:52:10.768375 Enter into DVFS_PRE_config >>>>>
6913 11:52:10.778470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6914 11:52:10.781364 Exit from DVFS_PRE_config <<<<<
6915 11:52:10.784970 Enter into PICG configuration >>>>
6916 11:52:10.788160 Exit from PICG configuration <<<<
6917 11:52:10.791451 [RX_INPUT] configuration >>>>>
6918 11:52:10.794589 [RX_INPUT] configuration <<<<<
6919 11:52:10.798039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6920 11:52:10.804460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6921 11:52:10.811456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6922 11:52:10.817770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6923 11:52:10.824540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6924 11:52:10.828063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6925 11:52:10.834432 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6926 11:52:10.837844 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6927 11:52:10.841647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6928 11:52:10.844809 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6929 11:52:10.851167 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6930 11:52:10.854981 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6931 11:52:10.857923 ===================================
6932 11:52:10.860885 LPDDR4 DRAM CONFIGURATION
6933 11:52:10.864407 ===================================
6934 11:52:10.865018 EX_ROW_EN[0] = 0x0
6935 11:52:10.867806 EX_ROW_EN[1] = 0x0
6936 11:52:10.868262 LP4Y_EN = 0x0
6937 11:52:10.871208 WORK_FSP = 0x1
6938 11:52:10.871723 WL = 0x5
6939 11:52:10.874336 RL = 0x5
6940 11:52:10.874843 BL = 0x2
6941 11:52:10.877930 RPST = 0x0
6942 11:52:10.878547 RD_PRE = 0x0
6943 11:52:10.880605 WR_PRE = 0x1
6944 11:52:10.881021 WR_PST = 0x1
6945 11:52:10.884025 DBI_WR = 0x0
6946 11:52:10.887289 DBI_RD = 0x0
6947 11:52:10.887704 OTF = 0x1
6948 11:52:10.890769 ===================================
6949 11:52:10.894432 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6950 11:52:10.897629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6951 11:52:10.904037 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6952 11:52:10.907584 ===================================
6953 11:52:10.910624 LPDDR4 DRAM CONFIGURATION
6954 11:52:10.914094 ===================================
6955 11:52:10.914618 EX_ROW_EN[0] = 0x10
6956 11:52:10.917200 EX_ROW_EN[1] = 0x0
6957 11:52:10.917616 LP4Y_EN = 0x0
6958 11:52:10.920344 WORK_FSP = 0x1
6959 11:52:10.920781 WL = 0x5
6960 11:52:10.924092 RL = 0x5
6961 11:52:10.924640 BL = 0x2
6962 11:52:10.927173 RPST = 0x0
6963 11:52:10.927586 RD_PRE = 0x0
6964 11:52:10.930621 WR_PRE = 0x1
6965 11:52:10.931132 WR_PST = 0x1
6966 11:52:10.934033 DBI_WR = 0x0
6967 11:52:10.937204 DBI_RD = 0x0
6968 11:52:10.937721 OTF = 0x1
6969 11:52:10.940403 ===================================
6970 11:52:10.947221 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6971 11:52:10.947741 ==
6972 11:52:10.950069 Dram Type= 6, Freq= 0, CH_0, rank 0
6973 11:52:10.953587 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6974 11:52:10.954105 ==
6975 11:52:10.957024 [Duty_Offset_Calibration]
6976 11:52:10.957435 B0:0 B1:2 CA:1
6977 11:52:10.960157
6978 11:52:10.960605 [DutyScan_Calibration_Flow] k_type=0
6979 11:52:10.971750
6980 11:52:10.972262 ==CLK 0==
6981 11:52:10.974885 Final CLK duty delay cell = 0
6982 11:52:10.978179 [0] MAX Duty = 5187%(X100), DQS PI = 24
6983 11:52:10.981877 [0] MIN Duty = 4938%(X100), DQS PI = 54
6984 11:52:10.984828 [0] AVG Duty = 5062%(X100)
6985 11:52:10.985251
6986 11:52:10.988112 CH0 CLK Duty spec in!! Max-Min= 249%
6987 11:52:10.991466 [DutyScan_Calibration_Flow] ====Done====
6988 11:52:10.992027
6989 11:52:10.994533 [DutyScan_Calibration_Flow] k_type=1
6990 11:52:11.010776
6991 11:52:11.011330 ==DQS 0 ==
6992 11:52:11.014226 Final DQS duty delay cell = -4
6993 11:52:11.017890 [-4] MAX Duty = 4969%(X100), DQS PI = 4
6994 11:52:11.020351 [-4] MIN Duty = 4875%(X100), DQS PI = 8
6995 11:52:11.023938 [-4] AVG Duty = 4922%(X100)
6996 11:52:11.024395
6997 11:52:11.024793 ==DQS 1 ==
6998 11:52:11.027424 Final DQS duty delay cell = 0
6999 11:52:11.030920 [0] MAX Duty = 5031%(X100), DQS PI = 4
7000 11:52:11.033699 [0] MIN Duty = 4876%(X100), DQS PI = 14
7001 11:52:11.037467 [0] AVG Duty = 4953%(X100)
7002 11:52:11.038025
7003 11:52:11.040484 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7004 11:52:11.041004
7005 11:52:11.044307 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7006 11:52:11.047407 [DutyScan_Calibration_Flow] ====Done====
7007 11:52:11.047823
7008 11:52:11.050582 [DutyScan_Calibration_Flow] k_type=3
7009 11:52:11.068490
7010 11:52:11.069094 ==DQM 0 ==
7011 11:52:11.071235 Final DQM duty delay cell = 0
7012 11:52:11.074876 [0] MAX Duty = 5187%(X100), DQS PI = 24
7013 11:52:11.078141 [0] MIN Duty = 4907%(X100), DQS PI = 56
7014 11:52:11.080981 [0] AVG Duty = 5047%(X100)
7015 11:52:11.081442
7016 11:52:11.081802 ==DQM 1 ==
7017 11:52:11.084415 Final DQM duty delay cell = 0
7018 11:52:11.088326 [0] MAX Duty = 5031%(X100), DQS PI = 50
7019 11:52:11.091505 [0] MIN Duty = 4782%(X100), DQS PI = 14
7020 11:52:11.094406 [0] AVG Duty = 4906%(X100)
7021 11:52:11.094870
7022 11:52:11.097728 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7023 11:52:11.098322
7024 11:52:11.101558 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7025 11:52:11.104604 [DutyScan_Calibration_Flow] ====Done====
7026 11:52:11.105064
7027 11:52:11.107522 [DutyScan_Calibration_Flow] k_type=2
7028 11:52:11.124569
7029 11:52:11.125128 ==DQ 0 ==
7030 11:52:11.127848 Final DQ duty delay cell = 0
7031 11:52:11.131136 [0] MAX Duty = 5218%(X100), DQS PI = 18
7032 11:52:11.134345 [0] MIN Duty = 4938%(X100), DQS PI = 56
7033 11:52:11.134902 [0] AVG Duty = 5078%(X100)
7034 11:52:11.137901
7035 11:52:11.138454 ==DQ 1 ==
7036 11:52:11.140755 Final DQ duty delay cell = -4
7037 11:52:11.144165 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7038 11:52:11.147559 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7039 11:52:11.151131 [-4] AVG Duty = 4969%(X100)
7040 11:52:11.151685
7041 11:52:11.154171 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7042 11:52:11.154731
7043 11:52:11.157519 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7044 11:52:11.160758 [DutyScan_Calibration_Flow] ====Done====
7045 11:52:11.161218 ==
7046 11:52:11.164277 Dram Type= 6, Freq= 0, CH_1, rank 0
7047 11:52:11.167349 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7048 11:52:11.167810 ==
7049 11:52:11.171119 [Duty_Offset_Calibration]
7050 11:52:11.171676 B0:0 B1:5 CA:-5
7051 11:52:11.172043
7052 11:52:11.173910 [DutyScan_Calibration_Flow] k_type=0
7053 11:52:11.185114
7054 11:52:11.185662 ==CLK 0==
7055 11:52:11.188386 Final CLK duty delay cell = 0
7056 11:52:11.192167 [0] MAX Duty = 5156%(X100), DQS PI = 22
7057 11:52:11.195037 [0] MIN Duty = 4906%(X100), DQS PI = 52
7058 11:52:11.195599 [0] AVG Duty = 5031%(X100)
7059 11:52:11.198775
7060 11:52:11.201516 CH1 CLK Duty spec in!! Max-Min= 250%
7061 11:52:11.205305 [DutyScan_Calibration_Flow] ====Done====
7062 11:52:11.205869
7063 11:52:11.208161 [DutyScan_Calibration_Flow] k_type=1
7064 11:52:11.224214
7065 11:52:11.224812 ==DQS 0 ==
7066 11:52:11.227129 Final DQS duty delay cell = 0
7067 11:52:11.230880 [0] MAX Duty = 5187%(X100), DQS PI = 20
7068 11:52:11.233766 [0] MIN Duty = 4907%(X100), DQS PI = 42
7069 11:52:11.237120 [0] AVG Duty = 5047%(X100)
7070 11:52:11.237676
7071 11:52:11.238041 ==DQS 1 ==
7072 11:52:11.240885 Final DQS duty delay cell = -4
7073 11:52:11.243785 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7074 11:52:11.247150 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7075 11:52:11.250722 [-4] AVG Duty = 4922%(X100)
7076 11:52:11.251288
7077 11:52:11.253948 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7078 11:52:11.254541
7079 11:52:11.256957 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7080 11:52:11.260556 [DutyScan_Calibration_Flow] ====Done====
7081 11:52:11.261124
7082 11:52:11.263684 [DutyScan_Calibration_Flow] k_type=3
7083 11:52:11.279625
7084 11:52:11.280180 ==DQM 0 ==
7085 11:52:11.282863 Final DQM duty delay cell = -4
7086 11:52:11.286362 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7087 11:52:11.289592 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7088 11:52:11.292705 [-4] AVG Duty = 4953%(X100)
7089 11:52:11.293274
7090 11:52:11.293643 ==DQM 1 ==
7091 11:52:11.295893 Final DQM duty delay cell = -4
7092 11:52:11.299651 [-4] MAX Duty = 5062%(X100), DQS PI = 0
7093 11:52:11.302727 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7094 11:52:11.306349 [-4] AVG Duty = 4984%(X100)
7095 11:52:11.306906
7096 11:52:11.309388 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7097 11:52:11.309850
7098 11:52:11.312886 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7099 11:52:11.316190 [DutyScan_Calibration_Flow] ====Done====
7100 11:52:11.316820
7101 11:52:11.319093 [DutyScan_Calibration_Flow] k_type=2
7102 11:52:11.337209
7103 11:52:11.337758 ==DQ 0 ==
7104 11:52:11.340622 Final DQ duty delay cell = 0
7105 11:52:11.343873 [0] MAX Duty = 5093%(X100), DQS PI = 20
7106 11:52:11.347235 [0] MIN Duty = 4969%(X100), DQS PI = 46
7107 11:52:11.347791 [0] AVG Duty = 5031%(X100)
7108 11:52:11.350765
7109 11:52:11.351483 ==DQ 1 ==
7110 11:52:11.353505 Final DQ duty delay cell = 0
7111 11:52:11.356999 [0] MAX Duty = 5031%(X100), DQS PI = 4
7112 11:52:11.360318 [0] MIN Duty = 4907%(X100), DQS PI = 22
7113 11:52:11.360826 [0] AVG Duty = 4969%(X100)
7114 11:52:11.361192
7115 11:52:11.363763 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7116 11:52:11.366925
7117 11:52:11.370258 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7118 11:52:11.374001 [DutyScan_Calibration_Flow] ====Done====
7119 11:52:11.376909 nWR fixed to 30
7120 11:52:11.377373 [ModeRegInit_LP4] CH0 RK0
7121 11:52:11.380420 [ModeRegInit_LP4] CH0 RK1
7122 11:52:11.383774 [ModeRegInit_LP4] CH1 RK0
7123 11:52:11.387102 [ModeRegInit_LP4] CH1 RK1
7124 11:52:11.387655 match AC timing 4
7125 11:52:11.390485 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7126 11:52:11.396752 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7127 11:52:11.400023 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7128 11:52:11.406958 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7129 11:52:11.409990 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7130 11:52:11.410515 [MiockJmeterHQA]
7131 11:52:11.410878
7132 11:52:11.413642 [DramcMiockJmeter] u1RxGatingPI = 0
7133 11:52:11.416842 0 : 4363, 4138
7134 11:52:11.417405 4 : 4363, 4138
7135 11:52:11.420254 8 : 4252, 4027
7136 11:52:11.420866 12 : 4253, 4026
7137 11:52:11.421245 16 : 4252, 4026
7138 11:52:11.423455 20 : 4363, 4138
7139 11:52:11.424017 24 : 4253, 4026
7140 11:52:11.426699 28 : 4363, 4138
7141 11:52:11.427257 32 : 4252, 4026
7142 11:52:11.430131 36 : 4252, 4027
7143 11:52:11.430692 40 : 4252, 4027
7144 11:52:11.433523 44 : 4252, 4026
7145 11:52:11.434090 48 : 4363, 4138
7146 11:52:11.434459 52 : 4253, 4027
7147 11:52:11.436863 56 : 4363, 4137
7148 11:52:11.437422 60 : 4252, 4027
7149 11:52:11.440136 64 : 4250, 4026
7150 11:52:11.440749 68 : 4250, 4027
7151 11:52:11.443379 72 : 4361, 4137
7152 11:52:11.443942 76 : 4250, 4026
7153 11:52:11.444312 80 : 4360, 4138
7154 11:52:11.446528 84 : 4250, 4027
7155 11:52:11.447092 88 : 4250, 4027
7156 11:52:11.449604 92 : 4250, 4027
7157 11:52:11.450069 96 : 4252, 4029
7158 11:52:11.453121 100 : 4360, 2799
7159 11:52:11.453691 104 : 4250, 0
7160 11:52:11.454064 108 : 4250, 0
7161 11:52:11.456500 112 : 4253, 0
7162 11:52:11.457115 116 : 4250, 0
7163 11:52:11.459715 120 : 4360, 0
7164 11:52:11.460176 124 : 4250, 0
7165 11:52:11.460601 128 : 4361, 0
7166 11:52:11.463028 132 : 4360, 0
7167 11:52:11.463495 136 : 4363, 0
7168 11:52:11.466482 140 : 4250, 0
7169 11:52:11.467046 144 : 4250, 0
7170 11:52:11.467418 148 : 4249, 0
7171 11:52:11.469978 152 : 4252, 0
7172 11:52:11.470560 156 : 4250, 0
7173 11:52:11.472848 160 : 4250, 0
7174 11:52:11.473313 164 : 4252, 0
7175 11:52:11.473686 168 : 4250, 0
7176 11:52:11.476359 172 : 4249, 0
7177 11:52:11.476873 176 : 4252, 0
7178 11:52:11.479708 180 : 4361, 0
7179 11:52:11.480277 184 : 4363, 0
7180 11:52:11.480708 188 : 4363, 0
7181 11:52:11.483397 192 : 4250, 0
7182 11:52:11.483957 196 : 4250, 0
7183 11:52:11.484329 200 : 4249, 0
7184 11:52:11.486695 204 : 4253, 0
7185 11:52:11.487257 208 : 4250, 0
7186 11:52:11.489935 212 : 4250, 0
7187 11:52:11.490497 216 : 4250, 0
7188 11:52:11.490867 220 : 4250, 494
7189 11:52:11.493111 224 : 4250, 3972
7190 11:52:11.493571 228 : 4250, 4026
7191 11:52:11.496049 232 : 4250, 4027
7192 11:52:11.496551 236 : 4360, 4138
7193 11:52:11.499730 240 : 4250, 4026
7194 11:52:11.500338 244 : 4250, 4027
7195 11:52:11.503271 248 : 4360, 4138
7196 11:52:11.503833 252 : 4361, 4137
7197 11:52:11.506365 256 : 4248, 4024
7198 11:52:11.506927 260 : 4361, 4137
7199 11:52:11.509367 264 : 4360, 4138
7200 11:52:11.509829 268 : 4250, 4027
7201 11:52:11.513188 272 : 4252, 4027
7202 11:52:11.513757 276 : 4250, 4026
7203 11:52:11.514135 280 : 4250, 4027
7204 11:52:11.516422 284 : 4252, 4026
7205 11:52:11.517029 288 : 4250, 4027
7206 11:52:11.519687 292 : 4250, 4026
7207 11:52:11.520252 296 : 4250, 4027
7208 11:52:11.522866 300 : 4360, 4138
7209 11:52:11.523441 304 : 4360, 4138
7210 11:52:11.526284 308 : 4248, 4024
7211 11:52:11.526848 312 : 4361, 4137
7212 11:52:11.529660 316 : 4360, 4138
7213 11:52:11.530225 320 : 4250, 4027
7214 11:52:11.533263 324 : 4250, 4027
7215 11:52:11.533827 328 : 4250, 4026
7216 11:52:11.536248 332 : 4250, 4027
7217 11:52:11.536864 336 : 4250, 3966
7218 11:52:11.537247 340 : 4250, 2216
7219 11:52:11.539644 344 : 4250, 0
7220 11:52:11.540206
7221 11:52:11.542966 MIOCK jitter meter ch=0
7222 11:52:11.543518
7223 11:52:11.543882 1T = (344-104) = 240 dly cells
7224 11:52:11.549423 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7225 11:52:11.549982 ==
7226 11:52:11.552842 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 11:52:11.556562 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7228 11:52:11.559193 ==
7229 11:52:11.562778 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7230 11:52:11.566121 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7231 11:52:11.572545 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7232 11:52:11.578971 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7233 11:52:11.585691 [CA 0] Center 42 (12~73) winsize 62
7234 11:52:11.588889 [CA 1] Center 42 (12~73) winsize 62
7235 11:52:11.592662 [CA 2] Center 39 (9~69) winsize 61
7236 11:52:11.595731 [CA 3] Center 38 (9~68) winsize 60
7237 11:52:11.598998 [CA 4] Center 37 (7~67) winsize 61
7238 11:52:11.602131 [CA 5] Center 36 (6~66) winsize 61
7239 11:52:11.602591
7240 11:52:11.605710 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7241 11:52:11.606260
7242 11:52:11.609083 [CATrainingPosCal] consider 1 rank data
7243 11:52:11.612011 u2DelayCellTimex100 = 271/100 ps
7244 11:52:11.615880 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7245 11:52:11.622651 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7246 11:52:11.625741 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7247 11:52:11.629308 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7248 11:52:11.632192 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7249 11:52:11.635942 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7250 11:52:11.636488
7251 11:52:11.638661 CA PerBit enable=1, Macro0, CA PI delay=36
7252 11:52:11.639121
7253 11:52:11.642094 [CBTSetCACLKResult] CA Dly = 36
7254 11:52:11.645422 CS Dly: 10 (0~41)
7255 11:52:11.648570 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7256 11:52:11.652005 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7257 11:52:11.652596 ==
7258 11:52:11.655695 Dram Type= 6, Freq= 0, CH_0, rank 1
7259 11:52:11.658644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7260 11:52:11.662121 ==
7261 11:52:11.665157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7262 11:52:11.668686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7263 11:52:11.675506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7264 11:52:11.681613 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7265 11:52:11.688632 [CA 0] Center 42 (12~73) winsize 62
7266 11:52:11.691929 [CA 1] Center 41 (11~72) winsize 62
7267 11:52:11.694989 [CA 2] Center 38 (8~68) winsize 61
7268 11:52:11.698351 [CA 3] Center 37 (7~67) winsize 61
7269 11:52:11.701535 [CA 4] Center 35 (5~65) winsize 61
7270 11:52:11.704939 [CA 5] Center 35 (5~66) winsize 62
7271 11:52:11.705431
7272 11:52:11.708276 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7273 11:52:11.708882
7274 11:52:11.711941 [CATrainingPosCal] consider 2 rank data
7275 11:52:11.715046 u2DelayCellTimex100 = 271/100 ps
7276 11:52:11.721773 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7277 11:52:11.725122 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7278 11:52:11.728166 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7279 11:52:11.731652 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7280 11:52:11.735040 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7281 11:52:11.737966 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7282 11:52:11.738521
7283 11:52:11.741473 CA PerBit enable=1, Macro0, CA PI delay=36
7284 11:52:11.742027
7285 11:52:11.744738 [CBTSetCACLKResult] CA Dly = 36
7286 11:52:11.747821 CS Dly: 11 (0~43)
7287 11:52:11.751390 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7288 11:52:11.754558 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7289 11:52:11.755129
7290 11:52:11.758173 ----->DramcWriteLeveling(PI) begin...
7291 11:52:11.758737 ==
7292 11:52:11.760830 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 11:52:11.767435 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7294 11:52:11.768084 ==
7295 11:52:11.770912 Write leveling (Byte 0): 28 => 28
7296 11:52:11.774276 Write leveling (Byte 1): 25 => 25
7297 11:52:11.774848 DramcWriteLeveling(PI) end<-----
7298 11:52:11.775352
7299 11:52:11.777269 ==
7300 11:52:11.780867 Dram Type= 6, Freq= 0, CH_0, rank 0
7301 11:52:11.783905 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7302 11:52:11.784302 ==
7303 11:52:11.787473 [Gating] SW mode calibration
7304 11:52:11.793903 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7305 11:52:11.797405 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7306 11:52:11.803735 0 12 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7307 11:52:11.807238 0 12 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7308 11:52:11.810408 0 12 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7309 11:52:11.817265 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7310 11:52:11.820730 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7311 11:52:11.823947 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7312 11:52:11.830964 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7313 11:52:11.834056 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7314 11:52:11.837226 0 13 0 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7315 11:52:11.844314 0 13 4 | B1->B0 | 3131 2424 | 0 0 | (1 0) (0 0)
7316 11:52:11.847311 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7317 11:52:11.850693 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 11:52:11.857685 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 11:52:11.860599 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 11:52:11.863842 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7321 11:52:11.870707 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 11:52:11.873979 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7323 11:52:11.877296 0 14 4 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
7324 11:52:11.884151 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7325 11:52:11.887534 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 11:52:11.890553 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7327 11:52:11.893798 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 11:52:11.900631 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7329 11:52:11.903761 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 11:52:11.907268 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 11:52:11.913963 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7332 11:52:11.917059 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7333 11:52:11.920703 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7334 11:52:11.927292 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 11:52:11.930453 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 11:52:11.933867 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 11:52:11.940277 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 11:52:11.943189 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 11:52:11.947003 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 11:52:11.953775 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 11:52:11.957221 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 11:52:11.960306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 11:52:11.966970 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 11:52:11.970527 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 11:52:11.973440 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7346 11:52:11.979973 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7347 11:52:11.983174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7348 11:52:11.986710 Total UI for P1: 0, mck2ui 16
7349 11:52:11.989929 best dqsien dly found for B0: ( 1, 0, 30)
7350 11:52:11.993223 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7351 11:52:11.999704 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 11:52:12.000167 Total UI for P1: 0, mck2ui 16
7353 11:52:12.006662 best dqsien dly found for B1: ( 1, 1, 4)
7354 11:52:12.009928 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7355 11:52:12.013187 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7356 11:52:12.013692
7357 11:52:12.016628 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7358 11:52:12.019985 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7359 11:52:12.022854 [Gating] SW calibration Done
7360 11:52:12.023331 ==
7361 11:52:12.026435 Dram Type= 6, Freq= 0, CH_0, rank 0
7362 11:52:12.029757 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7363 11:52:12.030334 ==
7364 11:52:12.033423 RX Vref Scan: 0
7365 11:52:12.034001
7366 11:52:12.034494 RX Vref 0 -> 0, step: 1
7367 11:52:12.034960
7368 11:52:12.036034 RX Delay 0 -> 252, step: 8
7369 11:52:12.039548 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7370 11:52:12.046739 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7371 11:52:12.049908 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7372 11:52:12.052956 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7373 11:52:12.056593 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7374 11:52:12.059694 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7375 11:52:12.066448 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7376 11:52:12.069578 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7377 11:52:12.072612 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7378 11:52:12.076224 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7379 11:52:12.079599 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7380 11:52:12.085954 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7381 11:52:12.089460 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7382 11:52:12.092661 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7383 11:52:12.096006 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7384 11:52:12.099327 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7385 11:52:12.102617 ==
7386 11:52:12.105613 Dram Type= 6, Freq= 0, CH_0, rank 0
7387 11:52:12.109271 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7388 11:52:12.109832 ==
7389 11:52:12.110201 DQS Delay:
7390 11:52:12.112380 DQS0 = 0, DQS1 = 0
7391 11:52:12.112882 DQM Delay:
7392 11:52:12.115842 DQM0 = 129, DQM1 = 124
7393 11:52:12.116390 DQ Delay:
7394 11:52:12.118977 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7395 11:52:12.122129 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =135
7396 11:52:12.125613 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7397 11:52:12.128731 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7398 11:52:12.129292
7399 11:52:12.129757
7400 11:52:12.130113 ==
7401 11:52:12.132214 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 11:52:12.138810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 11:52:12.139369 ==
7404 11:52:12.139948
7405 11:52:12.140334
7406 11:52:12.142101 TX Vref Scan disable
7407 11:52:12.142655 == TX Byte 0 ==
7408 11:52:12.145359 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7409 11:52:12.152000 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7410 11:52:12.152594 == TX Byte 1 ==
7411 11:52:12.155340 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7412 11:52:12.161984 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7413 11:52:12.162630 ==
7414 11:52:12.165196 Dram Type= 6, Freq= 0, CH_0, rank 0
7415 11:52:12.168730 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7416 11:52:12.169288 ==
7417 11:52:12.181782
7418 11:52:12.184791 TX Vref early break, caculate TX vref
7419 11:52:12.188290 TX Vref=16, minBit 8, minWin=21, winSum=367
7420 11:52:12.191692 TX Vref=18, minBit 8, minWin=22, winSum=379
7421 11:52:12.194995 TX Vref=20, minBit 15, minWin=22, winSum=383
7422 11:52:12.198121 TX Vref=22, minBit 10, minWin=23, winSum=395
7423 11:52:12.201503 TX Vref=24, minBit 8, minWin=24, winSum=405
7424 11:52:12.208201 TX Vref=26, minBit 10, minWin=24, winSum=410
7425 11:52:12.211382 TX Vref=28, minBit 1, minWin=25, winSum=412
7426 11:52:12.214728 TX Vref=30, minBit 1, minWin=24, winSum=407
7427 11:52:12.218160 TX Vref=32, minBit 0, minWin=24, winSum=396
7428 11:52:12.221109 TX Vref=34, minBit 1, minWin=23, winSum=387
7429 11:52:12.227503 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 28
7430 11:52:12.227969
7431 11:52:12.231095 Final TX Range 0 Vref 28
7432 11:52:12.231652
7433 11:52:12.232019 ==
7434 11:52:12.234629 Dram Type= 6, Freq= 0, CH_0, rank 0
7435 11:52:12.238171 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7436 11:52:12.238769 ==
7437 11:52:12.239140
7438 11:52:12.239478
7439 11:52:12.241211 TX Vref Scan disable
7440 11:52:12.247832 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7441 11:52:12.248389 == TX Byte 0 ==
7442 11:52:12.251039 u2DelayCellOfst[0]=14 cells (4 PI)
7443 11:52:12.254581 u2DelayCellOfst[1]=14 cells (4 PI)
7444 11:52:12.257592 u2DelayCellOfst[2]=10 cells (3 PI)
7445 11:52:12.261116 u2DelayCellOfst[3]=10 cells (3 PI)
7446 11:52:12.264023 u2DelayCellOfst[4]=7 cells (2 PI)
7447 11:52:12.267614 u2DelayCellOfst[5]=0 cells (0 PI)
7448 11:52:12.270846 u2DelayCellOfst[6]=18 cells (5 PI)
7449 11:52:12.274429 u2DelayCellOfst[7]=18 cells (5 PI)
7450 11:52:12.277779 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7451 11:52:12.281157 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7452 11:52:12.284047 == TX Byte 1 ==
7453 11:52:12.287539 u2DelayCellOfst[8]=3 cells (1 PI)
7454 11:52:12.290930 u2DelayCellOfst[9]=0 cells (0 PI)
7455 11:52:12.291488 u2DelayCellOfst[10]=10 cells (3 PI)
7456 11:52:12.293964 u2DelayCellOfst[11]=3 cells (1 PI)
7457 11:52:12.297244 u2DelayCellOfst[12]=14 cells (4 PI)
7458 11:52:12.300683 u2DelayCellOfst[13]=18 cells (5 PI)
7459 11:52:12.303867 u2DelayCellOfst[14]=18 cells (5 PI)
7460 11:52:12.307392 u2DelayCellOfst[15]=14 cells (4 PI)
7461 11:52:12.313973 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7462 11:52:12.317004 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7463 11:52:12.317561 DramC Write-DBI on
7464 11:52:12.317927 ==
7465 11:52:12.320211 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 11:52:12.327098 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7467 11:52:12.327669 ==
7468 11:52:12.328042
7469 11:52:12.328380
7470 11:52:12.330691 TX Vref Scan disable
7471 11:52:12.331269 == TX Byte 0 ==
7472 11:52:12.336964 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7473 11:52:12.337525 == TX Byte 1 ==
7474 11:52:12.339914 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7475 11:52:12.343541 DramC Write-DBI off
7476 11:52:12.344096
7477 11:52:12.344463 [DATLAT]
7478 11:52:12.346781 Freq=1600, CH0 RK0
7479 11:52:12.347336
7480 11:52:12.347701 DATLAT Default: 0xf
7481 11:52:12.350164 0, 0xFFFF, sum = 0
7482 11:52:12.350729 1, 0xFFFF, sum = 0
7483 11:52:12.353534 2, 0xFFFF, sum = 0
7484 11:52:12.354094 3, 0xFFFF, sum = 0
7485 11:52:12.356710 4, 0xFFFF, sum = 0
7486 11:52:12.357279 5, 0xFFFF, sum = 0
7487 11:52:12.359964 6, 0xFFFF, sum = 0
7488 11:52:12.360549 7, 0xFFFF, sum = 0
7489 11:52:12.363107 8, 0xFFFF, sum = 0
7490 11:52:12.366443 9, 0xFFFF, sum = 0
7491 11:52:12.367012 10, 0xFFFF, sum = 0
7492 11:52:12.370124 11, 0xFFFF, sum = 0
7493 11:52:12.370684 12, 0xFFF, sum = 0
7494 11:52:12.373018 13, 0x0, sum = 1
7495 11:52:12.373489 14, 0x0, sum = 2
7496 11:52:12.376123 15, 0x0, sum = 3
7497 11:52:12.376641 16, 0x0, sum = 4
7498 11:52:12.377103 best_step = 14
7499 11:52:12.377494
7500 11:52:12.379915 ==
7501 11:52:12.382818 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 11:52:12.386007 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7503 11:52:12.386428 ==
7504 11:52:12.386759 RX Vref Scan: 1
7505 11:52:12.387071
7506 11:52:12.389463 Set Vref Range= 24 -> 127
7507 11:52:12.389879
7508 11:52:12.392928 RX Vref 24 -> 127, step: 1
7509 11:52:12.393345
7510 11:52:12.396218 RX Delay 11 -> 252, step: 4
7511 11:52:12.396679
7512 11:52:12.399454 Set Vref, RX VrefLevel [Byte0]: 24
7513 11:52:12.402508 [Byte1]: 24
7514 11:52:12.402929
7515 11:52:12.406079 Set Vref, RX VrefLevel [Byte0]: 25
7516 11:52:12.409316 [Byte1]: 25
7517 11:52:12.409824
7518 11:52:12.412903 Set Vref, RX VrefLevel [Byte0]: 26
7519 11:52:12.415853 [Byte1]: 26
7520 11:52:12.419477
7521 11:52:12.419893 Set Vref, RX VrefLevel [Byte0]: 27
7522 11:52:12.423111 [Byte1]: 27
7523 11:52:12.427600
7524 11:52:12.428114 Set Vref, RX VrefLevel [Byte0]: 28
7525 11:52:12.430652 [Byte1]: 28
7526 11:52:12.434776
7527 11:52:12.435195 Set Vref, RX VrefLevel [Byte0]: 29
7528 11:52:12.438063 [Byte1]: 29
7529 11:52:12.442607
7530 11:52:12.443120 Set Vref, RX VrefLevel [Byte0]: 30
7531 11:52:12.445843 [Byte1]: 30
7532 11:52:12.450200
7533 11:52:12.450714 Set Vref, RX VrefLevel [Byte0]: 31
7534 11:52:12.453503 [Byte1]: 31
7535 11:52:12.457762
7536 11:52:12.458274 Set Vref, RX VrefLevel [Byte0]: 32
7537 11:52:12.461103 [Byte1]: 32
7538 11:52:12.465156
7539 11:52:12.465577 Set Vref, RX VrefLevel [Byte0]: 33
7540 11:52:12.468394 [Byte1]: 33
7541 11:52:12.472870
7542 11:52:12.473373 Set Vref, RX VrefLevel [Byte0]: 34
7543 11:52:12.476196 [Byte1]: 34
7544 11:52:12.480488
7545 11:52:12.481058 Set Vref, RX VrefLevel [Byte0]: 35
7546 11:52:12.483832 [Byte1]: 35
7547 11:52:12.488362
7548 11:52:12.488919 Set Vref, RX VrefLevel [Byte0]: 36
7549 11:52:12.491662 [Byte1]: 36
7550 11:52:12.495826
7551 11:52:12.496320 Set Vref, RX VrefLevel [Byte0]: 37
7552 11:52:12.498911 [Byte1]: 37
7553 11:52:12.503501
7554 11:52:12.504090 Set Vref, RX VrefLevel [Byte0]: 38
7555 11:52:12.507163 [Byte1]: 38
7556 11:52:12.511248
7557 11:52:12.511757 Set Vref, RX VrefLevel [Byte0]: 39
7558 11:52:12.514821 [Byte1]: 39
7559 11:52:12.519261
7560 11:52:12.519768 Set Vref, RX VrefLevel [Byte0]: 40
7561 11:52:12.522132 [Byte1]: 40
7562 11:52:12.526464
7563 11:52:12.526989 Set Vref, RX VrefLevel [Byte0]: 41
7564 11:52:12.529819 [Byte1]: 41
7565 11:52:12.534187
7566 11:52:12.534700 Set Vref, RX VrefLevel [Byte0]: 42
7567 11:52:12.537137 [Byte1]: 42
7568 11:52:12.541551
7569 11:52:12.542099 Set Vref, RX VrefLevel [Byte0]: 43
7570 11:52:12.545090 [Byte1]: 43
7571 11:52:12.549317
7572 11:52:12.549829 Set Vref, RX VrefLevel [Byte0]: 44
7573 11:52:12.552680 [Byte1]: 44
7574 11:52:12.557293
7575 11:52:12.557808 Set Vref, RX VrefLevel [Byte0]: 45
7576 11:52:12.560060 [Byte1]: 45
7577 11:52:12.564416
7578 11:52:12.564882 Set Vref, RX VrefLevel [Byte0]: 46
7579 11:52:12.567446 [Byte1]: 46
7580 11:52:12.572081
7581 11:52:12.572644 Set Vref, RX VrefLevel [Byte0]: 47
7582 11:52:12.575257 [Byte1]: 47
7583 11:52:12.580303
7584 11:52:12.580870 Set Vref, RX VrefLevel [Byte0]: 48
7585 11:52:12.582779 [Byte1]: 48
7586 11:52:12.587325
7587 11:52:12.587838 Set Vref, RX VrefLevel [Byte0]: 49
7588 11:52:12.590338 [Byte1]: 49
7589 11:52:12.594617
7590 11:52:12.595293 Set Vref, RX VrefLevel [Byte0]: 50
7591 11:52:12.597839 [Byte1]: 50
7592 11:52:12.602299
7593 11:52:12.602758 Set Vref, RX VrefLevel [Byte0]: 51
7594 11:52:12.605769 [Byte1]: 51
7595 11:52:12.610105
7596 11:52:12.610657 Set Vref, RX VrefLevel [Byte0]: 52
7597 11:52:12.613547 [Byte1]: 52
7598 11:52:12.617689
7599 11:52:12.618244 Set Vref, RX VrefLevel [Byte0]: 53
7600 11:52:12.620878 [Byte1]: 53
7601 11:52:12.625061
7602 11:52:12.625517 Set Vref, RX VrefLevel [Byte0]: 54
7603 11:52:12.628761 [Byte1]: 54
7604 11:52:12.633196
7605 11:52:12.633753 Set Vref, RX VrefLevel [Byte0]: 55
7606 11:52:12.636407 [Byte1]: 55
7607 11:52:12.640617
7608 11:52:12.641171 Set Vref, RX VrefLevel [Byte0]: 56
7609 11:52:12.643896 [Byte1]: 56
7610 11:52:12.648283
7611 11:52:12.648896 Set Vref, RX VrefLevel [Byte0]: 57
7612 11:52:12.651443 [Byte1]: 57
7613 11:52:12.655742
7614 11:52:12.656300 Set Vref, RX VrefLevel [Byte0]: 58
7615 11:52:12.659078 [Byte1]: 58
7616 11:52:12.663654
7617 11:52:12.664230 Set Vref, RX VrefLevel [Byte0]: 59
7618 11:52:12.666743 [Byte1]: 59
7619 11:52:12.671204
7620 11:52:12.671756 Set Vref, RX VrefLevel [Byte0]: 60
7621 11:52:12.674595 [Byte1]: 60
7622 11:52:12.678638
7623 11:52:12.679195 Set Vref, RX VrefLevel [Byte0]: 61
7624 11:52:12.681958 [Byte1]: 61
7625 11:52:12.686265
7626 11:52:12.686833 Set Vref, RX VrefLevel [Byte0]: 62
7627 11:52:12.689378 [Byte1]: 62
7628 11:52:12.693629
7629 11:52:12.694087 Set Vref, RX VrefLevel [Byte0]: 63
7630 11:52:12.696992 [Byte1]: 63
7631 11:52:12.701210
7632 11:52:12.701670 Set Vref, RX VrefLevel [Byte0]: 64
7633 11:52:12.704768 [Byte1]: 64
7634 11:52:12.709015
7635 11:52:12.709570 Set Vref, RX VrefLevel [Byte0]: 65
7636 11:52:12.712423 [Byte1]: 65
7637 11:52:12.716598
7638 11:52:12.717159 Set Vref, RX VrefLevel [Byte0]: 66
7639 11:52:12.719977 [Byte1]: 66
7640 11:52:12.724176
7641 11:52:12.724657 Set Vref, RX VrefLevel [Byte0]: 67
7642 11:52:12.727804 [Byte1]: 67
7643 11:52:12.731962
7644 11:52:12.732548 Set Vref, RX VrefLevel [Byte0]: 68
7645 11:52:12.735133 [Byte1]: 68
7646 11:52:12.739738
7647 11:52:12.740295 Set Vref, RX VrefLevel [Byte0]: 69
7648 11:52:12.742767 [Byte1]: 69
7649 11:52:12.747045
7650 11:52:12.747498 Set Vref, RX VrefLevel [Byte0]: 70
7651 11:52:12.750770 [Byte1]: 70
7652 11:52:12.754622
7653 11:52:12.755177 Set Vref, RX VrefLevel [Byte0]: 71
7654 11:52:12.757922 [Byte1]: 71
7655 11:52:12.762404
7656 11:52:12.762956 Final RX Vref Byte 0 = 54 to rank0
7657 11:52:12.765644 Final RX Vref Byte 1 = 57 to rank0
7658 11:52:12.768852 Final RX Vref Byte 0 = 54 to rank1
7659 11:52:12.772319 Final RX Vref Byte 1 = 57 to rank1==
7660 11:52:12.775580 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 11:52:12.782159 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7662 11:52:12.782723 ==
7663 11:52:12.783089 DQS Delay:
7664 11:52:12.785286 DQS0 = 0, DQS1 = 0
7665 11:52:12.785745 DQM Delay:
7666 11:52:12.786107 DQM0 = 127, DQM1 = 121
7667 11:52:12.788585 DQ Delay:
7668 11:52:12.792166 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7669 11:52:12.795513 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7670 11:52:12.798408 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7671 11:52:12.802104 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7672 11:52:12.802680
7673 11:52:12.803052
7674 11:52:12.803393
7675 11:52:12.805178 [DramC_TX_OE_Calibration] TA2
7676 11:52:12.808367 Original DQ_B0 (3 6) =30, OEN = 27
7677 11:52:12.811938 Original DQ_B1 (3 6) =30, OEN = 27
7678 11:52:12.815534 24, 0x0, End_B0=24 End_B1=24
7679 11:52:12.818540 25, 0x0, End_B0=25 End_B1=25
7680 11:52:12.819106 26, 0x0, End_B0=26 End_B1=26
7681 11:52:12.821390 27, 0x0, End_B0=27 End_B1=27
7682 11:52:12.824658 28, 0x0, End_B0=28 End_B1=28
7683 11:52:12.828360 29, 0x0, End_B0=29 End_B1=29
7684 11:52:12.828971 30, 0x0, End_B0=30 End_B1=30
7685 11:52:12.831722 31, 0x4141, End_B0=30 End_B1=30
7686 11:52:12.835005 Byte0 end_step=30 best_step=27
7687 11:52:12.838272 Byte1 end_step=30 best_step=27
7688 11:52:12.841483 Byte0 TX OE(2T, 0.5T) = (3, 3)
7689 11:52:12.845200 Byte1 TX OE(2T, 0.5T) = (3, 3)
7690 11:52:12.845754
7691 11:52:12.846122
7692 11:52:12.851479 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7693 11:52:12.854996 CH0 RK0: MR19=303, MR18=1D1D
7694 11:52:12.861595 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7695 11:52:12.862155
7696 11:52:12.864617 ----->DramcWriteLeveling(PI) begin...
7697 11:52:12.865229 ==
7698 11:52:12.867657 Dram Type= 6, Freq= 0, CH_0, rank 1
7699 11:52:12.871389 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7700 11:52:12.871952 ==
7701 11:52:12.874644 Write leveling (Byte 0): 30 => 30
7702 11:52:12.877845 Write leveling (Byte 1): 27 => 27
7703 11:52:12.881043 DramcWriteLeveling(PI) end<-----
7704 11:52:12.881501
7705 11:52:12.881862 ==
7706 11:52:12.884573 Dram Type= 6, Freq= 0, CH_0, rank 1
7707 11:52:12.887872 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7708 11:52:12.891470 ==
7709 11:52:12.892025 [Gating] SW mode calibration
7710 11:52:12.897901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7711 11:52:12.904631 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7712 11:52:12.907804 0 12 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7713 11:52:12.914288 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7714 11:52:12.917702 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7715 11:52:12.920737 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7716 11:52:12.927682 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7717 11:52:12.930934 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 11:52:12.934485 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7719 11:52:12.940872 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7720 11:52:12.943761 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7721 11:52:12.947232 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (0 1) (0 0)
7722 11:52:12.954033 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7723 11:52:12.957335 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7724 11:52:12.960657 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7725 11:52:12.967287 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 11:52:12.970455 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 11:52:12.973844 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7728 11:52:12.980381 0 14 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7729 11:52:12.983765 0 14 4 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7730 11:52:12.987353 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7731 11:52:12.993315 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7732 11:52:12.996640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7733 11:52:13.000467 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 11:52:13.006701 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7735 11:52:13.010338 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7736 11:52:13.013543 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7737 11:52:13.020102 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7738 11:52:13.023523 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7739 11:52:13.026920 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7740 11:52:13.033209 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7741 11:52:13.036668 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7742 11:52:13.040045 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 11:52:13.046668 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 11:52:13.050101 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 11:52:13.053455 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 11:52:13.060011 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 11:52:13.063349 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 11:52:13.066506 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 11:52:13.073147 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 11:52:13.076264 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 11:52:13.079941 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7752 11:52:13.086402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7753 11:52:13.089677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7754 11:52:13.092863 Total UI for P1: 0, mck2ui 16
7755 11:52:13.096108 best dqsien dly found for B0: ( 1, 0, 30)
7756 11:52:13.099297 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7757 11:52:13.103237 Total UI for P1: 0, mck2ui 16
7758 11:52:13.105729 best dqsien dly found for B1: ( 1, 1, 4)
7759 11:52:13.109393 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7760 11:52:13.112651 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7761 11:52:13.113210
7762 11:52:13.115764 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7763 11:52:13.122544 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7764 11:52:13.123101 [Gating] SW calibration Done
7765 11:52:13.123468 ==
7766 11:52:13.125882 Dram Type= 6, Freq= 0, CH_0, rank 1
7767 11:52:13.132371 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7768 11:52:13.133010 ==
7769 11:52:13.133382 RX Vref Scan: 0
7770 11:52:13.133718
7771 11:52:13.135457 RX Vref 0 -> 0, step: 1
7772 11:52:13.135914
7773 11:52:13.139313 RX Delay 0 -> 252, step: 8
7774 11:52:13.142447 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7775 11:52:13.145988 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7776 11:52:13.149059 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7777 11:52:13.152673 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7778 11:52:13.158872 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7779 11:52:13.162461 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7780 11:52:13.165573 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7781 11:52:13.168863 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7782 11:52:13.172500 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7783 11:52:13.179038 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7784 11:52:13.182498 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7785 11:52:13.185456 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7786 11:52:13.189087 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7787 11:52:13.192455 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7788 11:52:13.198673 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7789 11:52:13.201718 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7790 11:52:13.202177 ==
7791 11:52:13.205145 Dram Type= 6, Freq= 0, CH_0, rank 1
7792 11:52:13.208796 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7793 11:52:13.209466 ==
7794 11:52:13.212009 DQS Delay:
7795 11:52:13.212633 DQS0 = 0, DQS1 = 0
7796 11:52:13.215568 DQM Delay:
7797 11:52:13.216130 DQM0 = 131, DQM1 = 125
7798 11:52:13.216502 DQ Delay:
7799 11:52:13.218504 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7800 11:52:13.225204 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7801 11:52:13.228750 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7802 11:52:13.232376 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7803 11:52:13.233000
7804 11:52:13.233369
7805 11:52:13.233710 ==
7806 11:52:13.235287 Dram Type= 6, Freq= 0, CH_0, rank 1
7807 11:52:13.238390 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7808 11:52:13.238961 ==
7809 11:52:13.239333
7810 11:52:13.239671
7811 11:52:13.241440 TX Vref Scan disable
7812 11:52:13.244729 == TX Byte 0 ==
7813 11:52:13.248160 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7814 11:52:13.251367 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7815 11:52:13.255005 == TX Byte 1 ==
7816 11:52:13.258335 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7817 11:52:13.261415 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7818 11:52:13.261881 ==
7819 11:52:13.264708 Dram Type= 6, Freq= 0, CH_0, rank 1
7820 11:52:13.268092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7821 11:52:13.271292 ==
7822 11:52:13.284771
7823 11:52:13.288446 TX Vref early break, caculate TX vref
7824 11:52:13.291683 TX Vref=16, minBit 7, minWin=21, winSum=366
7825 11:52:13.295174 TX Vref=18, minBit 1, minWin=22, winSum=378
7826 11:52:13.298135 TX Vref=20, minBit 7, minWin=22, winSum=383
7827 11:52:13.301573 TX Vref=22, minBit 1, minWin=23, winSum=390
7828 11:52:13.304780 TX Vref=24, minBit 1, minWin=24, winSum=397
7829 11:52:13.311385 TX Vref=26, minBit 0, minWin=24, winSum=402
7830 11:52:13.315577 TX Vref=28, minBit 1, minWin=24, winSum=407
7831 11:52:13.318038 TX Vref=30, minBit 1, minWin=24, winSum=401
7832 11:52:13.321638 TX Vref=32, minBit 1, minWin=23, winSum=395
7833 11:52:13.324891 TX Vref=34, minBit 0, minWin=23, winSum=386
7834 11:52:13.328016 TX Vref=36, minBit 1, minWin=23, winSum=386
7835 11:52:13.335151 TX Vref=38, minBit 1, minWin=21, winSum=370
7836 11:52:13.338310 [TxChooseVref] Worse bit 1, Min win 24, Win sum 407, Final Vref 28
7837 11:52:13.338826
7838 11:52:13.341756 Final TX Range 0 Vref 28
7839 11:52:13.342275
7840 11:52:13.342602 ==
7841 11:52:13.344868 Dram Type= 6, Freq= 0, CH_0, rank 1
7842 11:52:13.347957 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7843 11:52:13.351366 ==
7844 11:52:13.351883
7845 11:52:13.352247
7846 11:52:13.352626 TX Vref Scan disable
7847 11:52:13.358300 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7848 11:52:13.358860 == TX Byte 0 ==
7849 11:52:13.361209 u2DelayCellOfst[0]=10 cells (3 PI)
7850 11:52:13.364660 u2DelayCellOfst[1]=18 cells (5 PI)
7851 11:52:13.367912 u2DelayCellOfst[2]=10 cells (3 PI)
7852 11:52:13.371348 u2DelayCellOfst[3]=10 cells (3 PI)
7853 11:52:13.374401 u2DelayCellOfst[4]=7 cells (2 PI)
7854 11:52:13.377586 u2DelayCellOfst[5]=0 cells (0 PI)
7855 11:52:13.381179 u2DelayCellOfst[6]=18 cells (5 PI)
7856 11:52:13.384490 u2DelayCellOfst[7]=18 cells (5 PI)
7857 11:52:13.387721 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7858 11:52:13.391355 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7859 11:52:13.394892 == TX Byte 1 ==
7860 11:52:13.397711 u2DelayCellOfst[8]=3 cells (1 PI)
7861 11:52:13.401278 u2DelayCellOfst[9]=0 cells (0 PI)
7862 11:52:13.404446 u2DelayCellOfst[10]=10 cells (3 PI)
7863 11:52:13.407680 u2DelayCellOfst[11]=3 cells (1 PI)
7864 11:52:13.411246 u2DelayCellOfst[12]=14 cells (4 PI)
7865 11:52:13.414493 u2DelayCellOfst[13]=14 cells (4 PI)
7866 11:52:13.414952 u2DelayCellOfst[14]=18 cells (5 PI)
7867 11:52:13.417809 u2DelayCellOfst[15]=14 cells (4 PI)
7868 11:52:13.424466 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7869 11:52:13.427664 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7870 11:52:13.431269 DramC Write-DBI on
7871 11:52:13.431826 ==
7872 11:52:13.434400 Dram Type= 6, Freq= 0, CH_0, rank 1
7873 11:52:13.437362 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7874 11:52:13.437826 ==
7875 11:52:13.438190
7876 11:52:13.438526
7877 11:52:13.441104 TX Vref Scan disable
7878 11:52:13.441659 == TX Byte 0 ==
7879 11:52:13.447937 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7880 11:52:13.448494 == TX Byte 1 ==
7881 11:52:13.450951 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7882 11:52:13.454302 DramC Write-DBI off
7883 11:52:13.454858
7884 11:52:13.455223 [DATLAT]
7885 11:52:13.457592 Freq=1600, CH0 RK1
7886 11:52:13.458147
7887 11:52:13.458513 DATLAT Default: 0xe
7888 11:52:13.461026 0, 0xFFFF, sum = 0
7889 11:52:13.461587 1, 0xFFFF, sum = 0
7890 11:52:13.464475 2, 0xFFFF, sum = 0
7891 11:52:13.465096 3, 0xFFFF, sum = 0
7892 11:52:13.467441 4, 0xFFFF, sum = 0
7893 11:52:13.467906 5, 0xFFFF, sum = 0
7894 11:52:13.471070 6, 0xFFFF, sum = 0
7895 11:52:13.471545 7, 0xFFFF, sum = 0
7896 11:52:13.473893 8, 0xFFFF, sum = 0
7897 11:52:13.477189 9, 0xFFFF, sum = 0
7898 11:52:13.477655 10, 0xFFFF, sum = 0
7899 11:52:13.480730 11, 0xFFFF, sum = 0
7900 11:52:13.481195 12, 0x8FFF, sum = 0
7901 11:52:13.484035 13, 0x0, sum = 1
7902 11:52:13.484501 14, 0x0, sum = 2
7903 11:52:13.487542 15, 0x0, sum = 3
7904 11:52:13.488113 16, 0x0, sum = 4
7905 11:52:13.488482 best_step = 14
7906 11:52:13.490734
7907 11:52:13.491290 ==
7908 11:52:13.494489 Dram Type= 6, Freq= 0, CH_0, rank 1
7909 11:52:13.497338 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7910 11:52:13.497851 ==
7911 11:52:13.498227 RX Vref Scan: 0
7912 11:52:13.498626
7913 11:52:13.500549 RX Vref 0 -> 0, step: 1
7914 11:52:13.501196
7915 11:52:13.503822 RX Delay 11 -> 252, step: 4
7916 11:52:13.507270 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7917 11:52:13.510678 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7918 11:52:13.517459 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7919 11:52:13.520717 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7920 11:52:13.523933 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7921 11:52:13.527346 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7922 11:52:13.530760 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7923 11:52:13.537247 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7924 11:52:13.540488 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7925 11:52:13.544022 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7926 11:52:13.547035 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7927 11:52:13.553965 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7928 11:52:13.556799 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7929 11:52:13.559984 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7930 11:52:13.563353 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7931 11:52:13.566778 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7932 11:52:13.570022 ==
7933 11:52:13.570444 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 11:52:13.576680 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 11:52:13.577183 ==
7936 11:52:13.577516 DQS Delay:
7937 11:52:13.580259 DQS0 = 0, DQS1 = 0
7938 11:52:13.580843 DQM Delay:
7939 11:52:13.583531 DQM0 = 129, DQM1 = 120
7940 11:52:13.584086 DQ Delay:
7941 11:52:13.587091 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7942 11:52:13.589820 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7943 11:52:13.593726 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7944 11:52:13.596931 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7945 11:52:13.597543
7946 11:52:13.597916
7947 11:52:13.598503
7948 11:52:13.599836 [DramC_TX_OE_Calibration] TA2
7949 11:52:13.603387 Original DQ_B0 (3 6) =30, OEN = 27
7950 11:52:13.606598 Original DQ_B1 (3 6) =30, OEN = 27
7951 11:52:13.609925 24, 0x0, End_B0=24 End_B1=24
7952 11:52:13.613165 25, 0x0, End_B0=25 End_B1=25
7953 11:52:13.613634 26, 0x0, End_B0=26 End_B1=26
7954 11:52:13.616678 27, 0x0, End_B0=27 End_B1=27
7955 11:52:13.620068 28, 0x0, End_B0=28 End_B1=28
7956 11:52:13.623223 29, 0x0, End_B0=29 End_B1=29
7957 11:52:13.626271 30, 0x0, End_B0=30 End_B1=30
7958 11:52:13.626742 31, 0x5151, End_B0=30 End_B1=30
7959 11:52:13.630143 Byte0 end_step=30 best_step=27
7960 11:52:13.633214 Byte1 end_step=30 best_step=27
7961 11:52:13.636659 Byte0 TX OE(2T, 0.5T) = (3, 3)
7962 11:52:13.639845 Byte1 TX OE(2T, 0.5T) = (3, 3)
7963 11:52:13.640399
7964 11:52:13.640811
7965 11:52:13.646427 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
7966 11:52:13.649481 CH0 RK1: MR19=303, MR18=2525
7967 11:52:13.656355 CH0_RK1: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
7968 11:52:13.659966 [RxdqsGatingPostProcess] freq 1600
7969 11:52:13.665963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7970 11:52:13.666427 Pre-setting of DQS Precalculation
7971 11:52:13.672978 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7972 11:52:13.673524 ==
7973 11:52:13.675932 Dram Type= 6, Freq= 0, CH_1, rank 0
7974 11:52:13.679413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7975 11:52:13.679976 ==
7976 11:52:13.685800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7977 11:52:13.689180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7978 11:52:13.695831 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7979 11:52:13.699033 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7980 11:52:13.708292 [CA 0] Center 41 (11~71) winsize 61
7981 11:52:13.711551 [CA 1] Center 40 (10~70) winsize 61
7982 11:52:13.714782 [CA 2] Center 36 (7~66) winsize 60
7983 11:52:13.718365 [CA 3] Center 35 (6~65) winsize 60
7984 11:52:13.721426 [CA 4] Center 33 (4~63) winsize 60
7985 11:52:13.724703 [CA 5] Center 33 (4~63) winsize 60
7986 11:52:13.725249
7987 11:52:13.727798 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7988 11:52:13.728262
7989 11:52:13.731885 [CATrainingPosCal] consider 1 rank data
7990 11:52:13.734601 u2DelayCellTimex100 = 271/100 ps
7991 11:52:13.741434 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7992 11:52:13.744853 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
7993 11:52:13.748151 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
7994 11:52:13.751238 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7995 11:52:13.754368 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
7996 11:52:13.757789 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7997 11:52:13.758251
7998 11:52:13.761128 CA PerBit enable=1, Macro0, CA PI delay=33
7999 11:52:13.761590
8000 11:52:13.764924 [CBTSetCACLKResult] CA Dly = 33
8001 11:52:13.767736 CS Dly: 9 (0~40)
8002 11:52:13.770934 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8003 11:52:13.774230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8004 11:52:13.774690 ==
8005 11:52:13.777634 Dram Type= 6, Freq= 0, CH_1, rank 1
8006 11:52:13.784476 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 11:52:13.785094 ==
8008 11:52:13.787902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8009 11:52:13.790955 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8010 11:52:13.797695 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8011 11:52:13.804055 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8012 11:52:13.810971 [CA 0] Center 41 (11~71) winsize 61
8013 11:52:13.814115 [CA 1] Center 40 (10~71) winsize 62
8014 11:52:13.817445 [CA 2] Center 36 (7~66) winsize 60
8015 11:52:13.820692 [CA 3] Center 35 (6~65) winsize 60
8016 11:52:13.824132 [CA 4] Center 34 (4~64) winsize 61
8017 11:52:13.827989 [CA 5] Center 34 (4~64) winsize 61
8018 11:52:13.828585
8019 11:52:13.830752 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8020 11:52:13.831303
8021 11:52:13.834274 [CATrainingPosCal] consider 2 rank data
8022 11:52:13.837554 u2DelayCellTimex100 = 271/100 ps
8023 11:52:13.841082 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8024 11:52:13.847373 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8025 11:52:13.851191 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8026 11:52:13.854174 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8027 11:52:13.857100 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8028 11:52:13.860860 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8029 11:52:13.861425
8030 11:52:13.864170 CA PerBit enable=1, Macro0, CA PI delay=33
8031 11:52:13.864769
8032 11:52:13.867786 [CBTSetCACLKResult] CA Dly = 33
8033 11:52:13.870776 CS Dly: 9 (0~41)
8034 11:52:13.873861 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8035 11:52:13.877261 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8036 11:52:13.877725
8037 11:52:13.880426 ----->DramcWriteLeveling(PI) begin...
8038 11:52:13.880935 ==
8039 11:52:13.884015 Dram Type= 6, Freq= 0, CH_1, rank 0
8040 11:52:13.887213 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8041 11:52:13.890782 ==
8042 11:52:13.891498 Write leveling (Byte 0): 22 => 22
8043 11:52:13.894248 Write leveling (Byte 1): 22 => 22
8044 11:52:13.897151 DramcWriteLeveling(PI) end<-----
8045 11:52:13.897796
8046 11:52:13.898253 ==
8047 11:52:13.900414 Dram Type= 6, Freq= 0, CH_1, rank 0
8048 11:52:13.906976 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8049 11:52:13.907646 ==
8050 11:52:13.910512 [Gating] SW mode calibration
8051 11:52:13.917176 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 11:52:13.920413 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8053 11:52:13.926864 0 12 0 | B1->B0 | 2525 3434 | 0 1 | (1 1) (1 1)
8054 11:52:13.930169 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8055 11:52:13.933262 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 11:52:13.940611 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 11:52:13.943553 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 11:52:13.947773 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:52:13.953209 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8060 11:52:13.956732 0 12 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8061 11:52:13.960011 0 13 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
8062 11:52:13.966421 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8063 11:52:13.969927 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:52:13.973084 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 11:52:13.979972 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:52:13.983397 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:52:13.986300 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8068 11:52:13.989978 0 13 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8069 11:52:13.996877 0 14 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8070 11:52:13.999372 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 11:52:14.002730 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 11:52:14.010033 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 11:52:14.013465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 11:52:14.016433 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 11:52:14.023190 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:52:14.026465 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8077 11:52:14.029526 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 11:52:14.036397 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 11:52:14.039677 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:52:14.042773 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 11:52:14.049343 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:52:14.052642 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:52:14.056065 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:52:14.062931 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:52:14.065749 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:52:14.069472 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:52:14.075651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:52:14.079423 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:52:14.082588 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:52:14.089167 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:52:14.092707 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 11:52:14.096101 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8093 11:52:14.102266 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8094 11:52:14.105709 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8095 11:52:14.109500 Total UI for P1: 0, mck2ui 16
8096 11:52:14.112324 best dqsien dly found for B0: ( 1, 0, 28)
8097 11:52:14.115873 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 11:52:14.119030 Total UI for P1: 0, mck2ui 16
8099 11:52:14.122635 best dqsien dly found for B1: ( 1, 1, 2)
8100 11:52:14.125621 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8101 11:52:14.128850 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8102 11:52:14.129401
8103 11:52:14.135439 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8104 11:52:14.138746 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8105 11:52:14.139307 [Gating] SW calibration Done
8106 11:52:14.142524 ==
8107 11:52:14.143086 Dram Type= 6, Freq= 0, CH_1, rank 0
8108 11:52:14.148847 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8109 11:52:14.149408 ==
8110 11:52:14.149793 RX Vref Scan: 0
8111 11:52:14.150234
8112 11:52:14.151809 RX Vref 0 -> 0, step: 1
8113 11:52:14.152277
8114 11:52:14.155414 RX Delay 0 -> 252, step: 8
8115 11:52:14.158855 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8116 11:52:14.162049 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8117 11:52:14.165262 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8118 11:52:14.171850 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8119 11:52:14.175290 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8120 11:52:14.178959 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8121 11:52:14.181937 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8122 11:52:14.185254 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8123 11:52:14.191698 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8124 11:52:14.195171 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8125 11:52:14.198547 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8126 11:52:14.201687 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8127 11:52:14.204992 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8128 11:52:14.211852 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8129 11:52:14.215045 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8130 11:52:14.218567 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8131 11:52:14.219122 ==
8132 11:52:14.221600 Dram Type= 6, Freq= 0, CH_1, rank 0
8133 11:52:14.224704 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8134 11:52:14.227969 ==
8135 11:52:14.228430 DQS Delay:
8136 11:52:14.228833 DQS0 = 0, DQS1 = 0
8137 11:52:14.231319 DQM Delay:
8138 11:52:14.231863 DQM0 = 130, DQM1 = 126
8139 11:52:14.234562 DQ Delay:
8140 11:52:14.238074 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8141 11:52:14.241717 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8142 11:52:14.244712 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8143 11:52:14.248078 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8144 11:52:14.248678
8145 11:52:14.249048
8146 11:52:14.249384 ==
8147 11:52:14.251373 Dram Type= 6, Freq= 0, CH_1, rank 0
8148 11:52:14.254418 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8149 11:52:14.254929 ==
8150 11:52:14.255296
8151 11:52:14.258456
8152 11:52:14.259013 TX Vref Scan disable
8153 11:52:14.261215 == TX Byte 0 ==
8154 11:52:14.264729 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8155 11:52:14.267982 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8156 11:52:14.271278 == TX Byte 1 ==
8157 11:52:14.274562 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8158 11:52:14.277717 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8159 11:52:14.278183 ==
8160 11:52:14.281477 Dram Type= 6, Freq= 0, CH_1, rank 0
8161 11:52:14.287854 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8162 11:52:14.288408 ==
8163 11:52:14.298635
8164 11:52:14.302092 TX Vref early break, caculate TX vref
8165 11:52:14.305400 TX Vref=16, minBit 3, minWin=21, winSum=368
8166 11:52:14.308757 TX Vref=18, minBit 1, minWin=22, winSum=377
8167 11:52:14.311814 TX Vref=20, minBit 3, minWin=22, winSum=381
8168 11:52:14.315129 TX Vref=22, minBit 0, minWin=23, winSum=392
8169 11:52:14.318581 TX Vref=24, minBit 3, minWin=24, winSum=404
8170 11:52:14.325521 TX Vref=26, minBit 1, minWin=24, winSum=407
8171 11:52:14.328380 TX Vref=28, minBit 0, minWin=24, winSum=408
8172 11:52:14.331814 TX Vref=30, minBit 1, minWin=24, winSum=404
8173 11:52:14.335053 TX Vref=32, minBit 2, minWin=23, winSum=396
8174 11:52:14.338526 TX Vref=34, minBit 0, minWin=23, winSum=384
8175 11:52:14.344836 [TxChooseVref] Worse bit 0, Min win 24, Win sum 408, Final Vref 28
8176 11:52:14.345302
8177 11:52:14.348650 Final TX Range 0 Vref 28
8178 11:52:14.349195
8179 11:52:14.349566 ==
8180 11:52:14.351760 Dram Type= 6, Freq= 0, CH_1, rank 0
8181 11:52:14.355357 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8182 11:52:14.355917 ==
8183 11:52:14.356286
8184 11:52:14.356682
8185 11:52:14.358099 TX Vref Scan disable
8186 11:52:14.364836 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8187 11:52:14.365362 == TX Byte 0 ==
8188 11:52:14.368468 u2DelayCellOfst[0]=14 cells (4 PI)
8189 11:52:14.371518 u2DelayCellOfst[1]=10 cells (3 PI)
8190 11:52:14.374731 u2DelayCellOfst[2]=0 cells (0 PI)
8191 11:52:14.378453 u2DelayCellOfst[3]=3 cells (1 PI)
8192 11:52:14.381438 u2DelayCellOfst[4]=7 cells (2 PI)
8193 11:52:14.384883 u2DelayCellOfst[5]=14 cells (4 PI)
8194 11:52:14.388033 u2DelayCellOfst[6]=14 cells (4 PI)
8195 11:52:14.391471 u2DelayCellOfst[7]=3 cells (1 PI)
8196 11:52:14.394886 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8197 11:52:14.397856 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8198 11:52:14.401530 == TX Byte 1 ==
8199 11:52:14.401993 u2DelayCellOfst[8]=0 cells (0 PI)
8200 11:52:14.404642 u2DelayCellOfst[9]=7 cells (2 PI)
8201 11:52:14.408037 u2DelayCellOfst[10]=10 cells (3 PI)
8202 11:52:14.411187 u2DelayCellOfst[11]=3 cells (1 PI)
8203 11:52:14.414837 u2DelayCellOfst[12]=18 cells (5 PI)
8204 11:52:14.418110 u2DelayCellOfst[13]=21 cells (6 PI)
8205 11:52:14.421211 u2DelayCellOfst[14]=21 cells (6 PI)
8206 11:52:14.424777 u2DelayCellOfst[15]=18 cells (5 PI)
8207 11:52:14.427935 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8208 11:52:14.434243 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8209 11:52:14.434799 DramC Write-DBI on
8210 11:52:14.435174 ==
8211 11:52:14.437400 Dram Type= 6, Freq= 0, CH_1, rank 0
8212 11:52:14.443849 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8213 11:52:14.444396 ==
8214 11:52:14.444787
8215 11:52:14.445153
8216 11:52:14.445493 TX Vref Scan disable
8217 11:52:14.447830 == TX Byte 0 ==
8218 11:52:14.451568 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8219 11:52:14.454746 == TX Byte 1 ==
8220 11:52:14.457864 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8221 11:52:14.461436 DramC Write-DBI off
8222 11:52:14.462064
8223 11:52:14.462436 [DATLAT]
8224 11:52:14.462769 Freq=1600, CH1 RK0
8225 11:52:14.463096
8226 11:52:14.464483 DATLAT Default: 0xf
8227 11:52:14.467974 0, 0xFFFF, sum = 0
8228 11:52:14.468569 1, 0xFFFF, sum = 0
8229 11:52:14.471264 2, 0xFFFF, sum = 0
8230 11:52:14.471820 3, 0xFFFF, sum = 0
8231 11:52:14.474640 4, 0xFFFF, sum = 0
8232 11:52:14.475201 5, 0xFFFF, sum = 0
8233 11:52:14.477562 6, 0xFFFF, sum = 0
8234 11:52:14.478031 7, 0xFFFF, sum = 0
8235 11:52:14.480876 8, 0xFFFF, sum = 0
8236 11:52:14.481345 9, 0xFFFF, sum = 0
8237 11:52:14.484308 10, 0xFFFF, sum = 0
8238 11:52:14.484878 11, 0xFFFF, sum = 0
8239 11:52:14.487263 12, 0xFFF, sum = 0
8240 11:52:14.487730 13, 0x0, sum = 1
8241 11:52:14.491396 14, 0x0, sum = 2
8242 11:52:14.491956 15, 0x0, sum = 3
8243 11:52:14.494562 16, 0x0, sum = 4
8244 11:52:14.495117 best_step = 14
8245 11:52:14.495485
8246 11:52:14.495827 ==
8247 11:52:14.497303 Dram Type= 6, Freq= 0, CH_1, rank 0
8248 11:52:14.500741 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8249 11:52:14.504096 ==
8250 11:52:14.504589 RX Vref Scan: 1
8251 11:52:14.504964
8252 11:52:14.507398 Set Vref Range= 24 -> 127
8253 11:52:14.507855
8254 11:52:14.510780 RX Vref 24 -> 127, step: 1
8255 11:52:14.511331
8256 11:52:14.511692 RX Delay 3 -> 252, step: 4
8257 11:52:14.512030
8258 11:52:14.514026 Set Vref, RX VrefLevel [Byte0]: 24
8259 11:52:14.517446 [Byte1]: 24
8260 11:52:14.521299
8261 11:52:14.521854 Set Vref, RX VrefLevel [Byte0]: 25
8262 11:52:14.524595 [Byte1]: 25
8263 11:52:14.529167
8264 11:52:14.529721 Set Vref, RX VrefLevel [Byte0]: 26
8265 11:52:14.532261 [Byte1]: 26
8266 11:52:14.536630
8267 11:52:14.537181 Set Vref, RX VrefLevel [Byte0]: 27
8268 11:52:14.539606 [Byte1]: 27
8269 11:52:14.544426
8270 11:52:14.545012 Set Vref, RX VrefLevel [Byte0]: 28
8271 11:52:14.547471 [Byte1]: 28
8272 11:52:14.552040
8273 11:52:14.552647 Set Vref, RX VrefLevel [Byte0]: 29
8274 11:52:14.555034 [Byte1]: 29
8275 11:52:14.559540
8276 11:52:14.560135 Set Vref, RX VrefLevel [Byte0]: 30
8277 11:52:14.562818 [Byte1]: 30
8278 11:52:14.567243
8279 11:52:14.567796 Set Vref, RX VrefLevel [Byte0]: 31
8280 11:52:14.570510 [Byte1]: 31
8281 11:52:14.575029
8282 11:52:14.575592 Set Vref, RX VrefLevel [Byte0]: 32
8283 11:52:14.577968 [Byte1]: 32
8284 11:52:14.582298
8285 11:52:14.582942 Set Vref, RX VrefLevel [Byte0]: 33
8286 11:52:14.585531 [Byte1]: 33
8287 11:52:14.590337
8288 11:52:14.590890 Set Vref, RX VrefLevel [Byte0]: 34
8289 11:52:14.593393 [Byte1]: 34
8290 11:52:14.597766
8291 11:52:14.598225 Set Vref, RX VrefLevel [Byte0]: 35
8292 11:52:14.600883 [Byte1]: 35
8293 11:52:14.605082
8294 11:52:14.605722 Set Vref, RX VrefLevel [Byte0]: 36
8295 11:52:14.608710 [Byte1]: 36
8296 11:52:14.613026
8297 11:52:14.613519 Set Vref, RX VrefLevel [Byte0]: 37
8298 11:52:14.616140 [Byte1]: 37
8299 11:52:14.620826
8300 11:52:14.621275 Set Vref, RX VrefLevel [Byte0]: 38
8301 11:52:14.623836 [Byte1]: 38
8302 11:52:14.628672
8303 11:52:14.629326 Set Vref, RX VrefLevel [Byte0]: 39
8304 11:52:14.631890 [Byte1]: 39
8305 11:52:14.636086
8306 11:52:14.636690 Set Vref, RX VrefLevel [Byte0]: 40
8307 11:52:14.639333 [Byte1]: 40
8308 11:52:14.643717
8309 11:52:14.644265 Set Vref, RX VrefLevel [Byte0]: 41
8310 11:52:14.646928 [Byte1]: 41
8311 11:52:14.651586
8312 11:52:14.652133 Set Vref, RX VrefLevel [Byte0]: 42
8313 11:52:14.655025 [Byte1]: 42
8314 11:52:14.658967
8315 11:52:14.659423 Set Vref, RX VrefLevel [Byte0]: 43
8316 11:52:14.662312 [Byte1]: 43
8317 11:52:14.666719
8318 11:52:14.667267 Set Vref, RX VrefLevel [Byte0]: 44
8319 11:52:14.669843 [Byte1]: 44
8320 11:52:14.674045
8321 11:52:14.674496 Set Vref, RX VrefLevel [Byte0]: 45
8322 11:52:14.677372 [Byte1]: 45
8323 11:52:14.681976
8324 11:52:14.682605 Set Vref, RX VrefLevel [Byte0]: 46
8325 11:52:14.684928 [Byte1]: 46
8326 11:52:14.689681
8327 11:52:14.690167 Set Vref, RX VrefLevel [Byte0]: 47
8328 11:52:14.692691 [Byte1]: 47
8329 11:52:14.697169
8330 11:52:14.697690 Set Vref, RX VrefLevel [Byte0]: 48
8331 11:52:14.700284 [Byte1]: 48
8332 11:52:14.704910
8333 11:52:14.705360 Set Vref, RX VrefLevel [Byte0]: 49
8334 11:52:14.708220 [Byte1]: 49
8335 11:52:14.712460
8336 11:52:14.713057 Set Vref, RX VrefLevel [Byte0]: 50
8337 11:52:14.715833 [Byte1]: 50
8338 11:52:14.720068
8339 11:52:14.720665 Set Vref, RX VrefLevel [Byte0]: 51
8340 11:52:14.723297 [Byte1]: 51
8341 11:52:14.727941
8342 11:52:14.728496 Set Vref, RX VrefLevel [Byte0]: 52
8343 11:52:14.731103 [Byte1]: 52
8344 11:52:14.735746
8345 11:52:14.736298 Set Vref, RX VrefLevel [Byte0]: 53
8346 11:52:14.739221 [Byte1]: 53
8347 11:52:14.743139
8348 11:52:14.743763 Set Vref, RX VrefLevel [Byte0]: 54
8349 11:52:14.746251 [Byte1]: 54
8350 11:52:14.750618
8351 11:52:14.751071 Set Vref, RX VrefLevel [Byte0]: 55
8352 11:52:14.753910 [Byte1]: 55
8353 11:52:14.758508
8354 11:52:14.758960 Set Vref, RX VrefLevel [Byte0]: 56
8355 11:52:14.761553 [Byte1]: 56
8356 11:52:14.765900
8357 11:52:14.766461 Set Vref, RX VrefLevel [Byte0]: 57
8358 11:52:14.769071 [Byte1]: 57
8359 11:52:14.773613
8360 11:52:14.774291 Set Vref, RX VrefLevel [Byte0]: 58
8361 11:52:14.777204 [Byte1]: 58
8362 11:52:14.781739
8363 11:52:14.782305 Set Vref, RX VrefLevel [Byte0]: 59
8364 11:52:14.787598 [Byte1]: 59
8365 11:52:14.788129
8366 11:52:14.791071 Set Vref, RX VrefLevel [Byte0]: 60
8367 11:52:14.794161 [Byte1]: 60
8368 11:52:14.794625
8369 11:52:14.797802 Set Vref, RX VrefLevel [Byte0]: 61
8370 11:52:14.800978 [Byte1]: 61
8371 11:52:14.804477
8372 11:52:14.804986 Set Vref, RX VrefLevel [Byte0]: 62
8373 11:52:14.807371 [Byte1]: 62
8374 11:52:14.811648
8375 11:52:14.812108 Set Vref, RX VrefLevel [Byte0]: 63
8376 11:52:14.815471 [Byte1]: 63
8377 11:52:14.819652
8378 11:52:14.820208 Set Vref, RX VrefLevel [Byte0]: 64
8379 11:52:14.822906 [Byte1]: 64
8380 11:52:14.827128
8381 11:52:14.827661 Set Vref, RX VrefLevel [Byte0]: 65
8382 11:52:14.830314 [Byte1]: 65
8383 11:52:14.835174
8384 11:52:14.835698 Set Vref, RX VrefLevel [Byte0]: 66
8385 11:52:14.837988 [Byte1]: 66
8386 11:52:14.842383
8387 11:52:14.842940 Set Vref, RX VrefLevel [Byte0]: 67
8388 11:52:14.846065 [Byte1]: 67
8389 11:52:14.850020
8390 11:52:14.850493 Set Vref, RX VrefLevel [Byte0]: 68
8391 11:52:14.853487 [Byte1]: 68
8392 11:52:14.857863
8393 11:52:14.858410 Set Vref, RX VrefLevel [Byte0]: 69
8394 11:52:14.861277 [Byte1]: 69
8395 11:52:14.865383
8396 11:52:14.865921 Set Vref, RX VrefLevel [Byte0]: 70
8397 11:52:14.868885 [Byte1]: 70
8398 11:52:14.873163
8399 11:52:14.873638 Set Vref, RX VrefLevel [Byte0]: 71
8400 11:52:14.877088 [Byte1]: 71
8401 11:52:14.880593
8402 11:52:14.881053 Set Vref, RX VrefLevel [Byte0]: 72
8403 11:52:14.884035 [Byte1]: 72
8404 11:52:14.888884
8405 11:52:14.889471 Set Vref, RX VrefLevel [Byte0]: 73
8406 11:52:14.891894 [Byte1]: 73
8407 11:52:14.896139
8408 11:52:14.896747 Set Vref, RX VrefLevel [Byte0]: 74
8409 11:52:14.899540 [Byte1]: 74
8410 11:52:14.903796
8411 11:52:14.904387 Set Vref, RX VrefLevel [Byte0]: 75
8412 11:52:14.907500 [Byte1]: 75
8413 11:52:14.911441
8414 11:52:14.912008 Set Vref, RX VrefLevel [Byte0]: 76
8415 11:52:14.914875 [Byte1]: 76
8416 11:52:14.919240
8417 11:52:14.919880 Final RX Vref Byte 0 = 63 to rank0
8418 11:52:14.922685 Final RX Vref Byte 1 = 56 to rank0
8419 11:52:14.925964 Final RX Vref Byte 0 = 63 to rank1
8420 11:52:14.929209 Final RX Vref Byte 1 = 56 to rank1==
8421 11:52:14.932765 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 11:52:14.939323 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8423 11:52:14.939906 ==
8424 11:52:14.940396 DQS Delay:
8425 11:52:14.940902 DQS0 = 0, DQS1 = 0
8426 11:52:14.942206 DQM Delay:
8427 11:52:14.942685 DQM0 = 128, DQM1 = 124
8428 11:52:14.945988 DQ Delay:
8429 11:52:14.948866 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8430 11:52:14.952579 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =124
8431 11:52:14.955549 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8432 11:52:14.959018 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8433 11:52:14.959569
8434 11:52:14.959937
8435 11:52:14.960280
8436 11:52:14.962206 [DramC_TX_OE_Calibration] TA2
8437 11:52:14.965733 Original DQ_B0 (3 6) =30, OEN = 27
8438 11:52:14.968683 Original DQ_B1 (3 6) =30, OEN = 27
8439 11:52:14.972595 24, 0x0, End_B0=24 End_B1=24
8440 11:52:14.973126 25, 0x0, End_B0=25 End_B1=25
8441 11:52:14.975450 26, 0x0, End_B0=26 End_B1=26
8442 11:52:14.978519 27, 0x0, End_B0=27 End_B1=27
8443 11:52:14.982365 28, 0x0, End_B0=28 End_B1=28
8444 11:52:14.985303 29, 0x0, End_B0=29 End_B1=29
8445 11:52:14.985779 30, 0x0, End_B0=30 End_B1=30
8446 11:52:14.988846 31, 0x4141, End_B0=30 End_B1=30
8447 11:52:14.992085 Byte0 end_step=30 best_step=27
8448 11:52:14.995411 Byte1 end_step=30 best_step=27
8449 11:52:14.998950 Byte0 TX OE(2T, 0.5T) = (3, 3)
8450 11:52:15.002123 Byte1 TX OE(2T, 0.5T) = (3, 3)
8451 11:52:15.002591
8452 11:52:15.002959
8453 11:52:15.008669 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8454 11:52:15.012223 CH1 RK0: MR19=303, MR18=2A2A
8455 11:52:15.018787 CH1_RK0: MR19=0x303, MR18=0x2A2A, DQSOSC=388, MR23=63, INC=24, DEC=16
8456 11:52:15.019359
8457 11:52:15.022334 ----->DramcWriteLeveling(PI) begin...
8458 11:52:15.022910 ==
8459 11:52:15.025643 Dram Type= 6, Freq= 0, CH_1, rank 1
8460 11:52:15.028369 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8461 11:52:15.028902 ==
8462 11:52:15.032207 Write leveling (Byte 0): 23 => 23
8463 11:52:15.035463 Write leveling (Byte 1): 23 => 23
8464 11:52:15.038775 DramcWriteLeveling(PI) end<-----
8465 11:52:15.039237
8466 11:52:15.039598 ==
8467 11:52:15.042338 Dram Type= 6, Freq= 0, CH_1, rank 1
8468 11:52:15.045226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8469 11:52:15.045689 ==
8470 11:52:15.048381 [Gating] SW mode calibration
8471 11:52:15.055256 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8472 11:52:15.061692 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8473 11:52:15.064991 0 12 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8474 11:52:15.068728 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 11:52:15.075094 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 11:52:15.078665 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 11:52:15.081489 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 11:52:15.088291 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 11:52:15.091685 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8480 11:52:15.094999 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8481 11:52:15.101230 0 13 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8482 11:52:15.105049 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 11:52:15.107884 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 11:52:15.114625 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 11:52:15.118114 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 11:52:15.121511 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 11:52:15.127978 0 13 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8488 11:52:15.131348 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8489 11:52:15.134380 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8490 11:52:15.141168 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 11:52:15.144766 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 11:52:15.147725 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 11:52:15.154245 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 11:52:15.157769 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8495 11:52:15.160893 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8496 11:52:15.167593 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8497 11:52:15.171088 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8498 11:52:15.174159 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 11:52:15.180763 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 11:52:15.184095 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 11:52:15.187352 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 11:52:15.193842 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 11:52:15.197514 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 11:52:15.200562 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 11:52:15.207173 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 11:52:15.210329 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 11:52:15.213660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 11:52:15.220708 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 11:52:15.223840 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 11:52:15.227468 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 11:52:15.233866 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8512 11:52:15.237208 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8513 11:52:15.240183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8514 11:52:15.243774 Total UI for P1: 0, mck2ui 16
8515 11:52:15.247021 best dqsien dly found for B0: ( 1, 0, 26)
8516 11:52:15.253369 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8517 11:52:15.253906 Total UI for P1: 0, mck2ui 16
8518 11:52:15.259878 best dqsien dly found for B1: ( 1, 1, 0)
8519 11:52:15.263567 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8520 11:52:15.267240 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8521 11:52:15.267800
8522 11:52:15.270015 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8523 11:52:15.273207 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8524 11:52:15.276697 [Gating] SW calibration Done
8525 11:52:15.277156 ==
8526 11:52:15.279814 Dram Type= 6, Freq= 0, CH_1, rank 1
8527 11:52:15.283149 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8528 11:52:15.283613 ==
8529 11:52:15.286670 RX Vref Scan: 0
8530 11:52:15.287225
8531 11:52:15.287593 RX Vref 0 -> 0, step: 1
8532 11:52:15.287936
8533 11:52:15.289944 RX Delay 0 -> 252, step: 8
8534 11:52:15.293664 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8535 11:52:15.300459 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8536 11:52:15.303380 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8537 11:52:15.306412 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8538 11:52:15.309890 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8539 11:52:15.312904 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8540 11:52:15.319554 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8541 11:52:15.323227 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8542 11:52:15.326125 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8543 11:52:15.329317 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8544 11:52:15.332940 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8545 11:52:15.339209 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8546 11:52:15.342957 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8547 11:52:15.346519 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8548 11:52:15.349829 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8549 11:52:15.353232 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8550 11:52:15.356233 ==
8551 11:52:15.356740 Dram Type= 6, Freq= 0, CH_1, rank 1
8552 11:52:15.362818 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8553 11:52:15.363350 ==
8554 11:52:15.363718 DQS Delay:
8555 11:52:15.365952 DQS0 = 0, DQS1 = 0
8556 11:52:15.366414 DQM Delay:
8557 11:52:15.369269 DQM0 = 130, DQM1 = 125
8558 11:52:15.369802 DQ Delay:
8559 11:52:15.372897 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =131
8560 11:52:15.375778 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8561 11:52:15.379146 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8562 11:52:15.382513 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8563 11:52:15.382998
8564 11:52:15.383370
8565 11:52:15.383714 ==
8566 11:52:15.385830 Dram Type= 6, Freq= 0, CH_1, rank 1
8567 11:52:15.392316 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8568 11:52:15.392899 ==
8569 11:52:15.393438
8570 11:52:15.393816
8571 11:52:15.394156 TX Vref Scan disable
8572 11:52:15.396044 == TX Byte 0 ==
8573 11:52:15.399540 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8574 11:52:15.402776 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8575 11:52:15.406355 == TX Byte 1 ==
8576 11:52:15.409512 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8577 11:52:15.412992 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8578 11:52:15.416061 ==
8579 11:52:15.419571 Dram Type= 6, Freq= 0, CH_1, rank 1
8580 11:52:15.422645 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8581 11:52:15.423174 ==
8582 11:52:15.434921
8583 11:52:15.437961 TX Vref early break, caculate TX vref
8584 11:52:15.441417 TX Vref=16, minBit 0, minWin=22, winSum=375
8585 11:52:15.444551 TX Vref=18, minBit 0, minWin=22, winSum=385
8586 11:52:15.448124 TX Vref=20, minBit 5, minWin=22, winSum=392
8587 11:52:15.451709 TX Vref=22, minBit 0, minWin=23, winSum=401
8588 11:52:15.454452 TX Vref=24, minBit 0, minWin=24, winSum=407
8589 11:52:15.461100 TX Vref=26, minBit 0, minWin=25, winSum=415
8590 11:52:15.464605 TX Vref=28, minBit 0, minWin=24, winSum=414
8591 11:52:15.467594 TX Vref=30, minBit 0, minWin=23, winSum=409
8592 11:52:15.471117 TX Vref=32, minBit 0, minWin=23, winSum=401
8593 11:52:15.474321 TX Vref=34, minBit 0, minWin=22, winSum=390
8594 11:52:15.480994 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8595 11:52:15.481525
8596 11:52:15.484201 Final TX Range 0 Vref 26
8597 11:52:15.484709
8598 11:52:15.485276 ==
8599 11:52:15.487472 Dram Type= 6, Freq= 0, CH_1, rank 1
8600 11:52:15.491031 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8601 11:52:15.491519 ==
8602 11:52:15.491901
8603 11:52:15.492242
8604 11:52:15.494211 TX Vref Scan disable
8605 11:52:15.501069 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8606 11:52:15.501536 == TX Byte 0 ==
8607 11:52:15.504356 u2DelayCellOfst[0]=14 cells (4 PI)
8608 11:52:15.507702 u2DelayCellOfst[1]=10 cells (3 PI)
8609 11:52:15.511102 u2DelayCellOfst[2]=0 cells (0 PI)
8610 11:52:15.514105 u2DelayCellOfst[3]=3 cells (1 PI)
8611 11:52:15.517563 u2DelayCellOfst[4]=7 cells (2 PI)
8612 11:52:15.521041 u2DelayCellOfst[5]=18 cells (5 PI)
8613 11:52:15.524098 u2DelayCellOfst[6]=14 cells (4 PI)
8614 11:52:15.524664 u2DelayCellOfst[7]=3 cells (1 PI)
8615 11:52:15.530811 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8616 11:52:15.534261 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8617 11:52:15.534902 == TX Byte 1 ==
8618 11:52:15.537490 u2DelayCellOfst[8]=0 cells (0 PI)
8619 11:52:15.540779 u2DelayCellOfst[9]=7 cells (2 PI)
8620 11:52:15.544099 u2DelayCellOfst[10]=14 cells (4 PI)
8621 11:52:15.547259 u2DelayCellOfst[11]=3 cells (1 PI)
8622 11:52:15.550391 u2DelayCellOfst[12]=18 cells (5 PI)
8623 11:52:15.553886 u2DelayCellOfst[13]=21 cells (6 PI)
8624 11:52:15.557074 u2DelayCellOfst[14]=21 cells (6 PI)
8625 11:52:15.560399 u2DelayCellOfst[15]=21 cells (6 PI)
8626 11:52:15.563631 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8627 11:52:15.570793 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8628 11:52:15.571353 DramC Write-DBI on
8629 11:52:15.571833 ==
8630 11:52:15.573886 Dram Type= 6, Freq= 0, CH_1, rank 1
8631 11:52:15.577353 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8632 11:52:15.580721 ==
8633 11:52:15.581274
8634 11:52:15.581641
8635 11:52:15.581984 TX Vref Scan disable
8636 11:52:15.583590 == TX Byte 0 ==
8637 11:52:15.587555 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8638 11:52:15.590802 == TX Byte 1 ==
8639 11:52:15.594083 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8640 11:52:15.597432 DramC Write-DBI off
8641 11:52:15.597894
8642 11:52:15.598260 [DATLAT]
8643 11:52:15.598598 Freq=1600, CH1 RK1
8644 11:52:15.598926
8645 11:52:15.600307 DATLAT Default: 0xe
8646 11:52:15.600951 0, 0xFFFF, sum = 0
8647 11:52:15.603581 1, 0xFFFF, sum = 0
8648 11:52:15.606793 2, 0xFFFF, sum = 0
8649 11:52:15.607261 3, 0xFFFF, sum = 0
8650 11:52:15.610180 4, 0xFFFF, sum = 0
8651 11:52:15.610663 5, 0xFFFF, sum = 0
8652 11:52:15.613660 6, 0xFFFF, sum = 0
8653 11:52:15.614320 7, 0xFFFF, sum = 0
8654 11:52:15.616722 8, 0xFFFF, sum = 0
8655 11:52:15.617229 9, 0xFFFF, sum = 0
8656 11:52:15.620003 10, 0xFFFF, sum = 0
8657 11:52:15.620561 11, 0xFFFF, sum = 0
8658 11:52:15.623596 12, 0xFFF, sum = 0
8659 11:52:15.624211 13, 0x0, sum = 1
8660 11:52:15.627211 14, 0x0, sum = 2
8661 11:52:15.627785 15, 0x0, sum = 3
8662 11:52:15.630017 16, 0x0, sum = 4
8663 11:52:15.630518 best_step = 14
8664 11:52:15.630908
8665 11:52:15.631253 ==
8666 11:52:15.633208 Dram Type= 6, Freq= 0, CH_1, rank 1
8667 11:52:15.637024 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8668 11:52:15.640348 ==
8669 11:52:15.640976 RX Vref Scan: 0
8670 11:52:15.641380
8671 11:52:15.643358 RX Vref 0 -> 0, step: 1
8672 11:52:15.643820
8673 11:52:15.644184 RX Delay 3 -> 252, step: 4
8674 11:52:15.650583 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8675 11:52:15.654276 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8676 11:52:15.657846 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8677 11:52:15.660643 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8678 11:52:15.663918 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8679 11:52:15.670982 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8680 11:52:15.673945 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8681 11:52:15.677062 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8682 11:52:15.680854 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8683 11:52:15.683713 iDelay=195, Bit 9, Center 110 (59 ~ 162) 104
8684 11:52:15.690503 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8685 11:52:15.694256 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8686 11:52:15.697322 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8687 11:52:15.700719 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8688 11:52:15.707165 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8689 11:52:15.710254 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8690 11:52:15.710718 ==
8691 11:52:15.713676 Dram Type= 6, Freq= 0, CH_1, rank 1
8692 11:52:15.717428 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8693 11:52:15.717952 ==
8694 11:52:15.720738 DQS Delay:
8695 11:52:15.721292 DQS0 = 0, DQS1 = 0
8696 11:52:15.721659 DQM Delay:
8697 11:52:15.724064 DQM0 = 127, DQM1 = 122
8698 11:52:15.724574 DQ Delay:
8699 11:52:15.727496 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =124
8700 11:52:15.731044 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =124
8701 11:52:15.733817 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8702 11:52:15.740609 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8703 11:52:15.741164
8704 11:52:15.741528
8705 11:52:15.741866
8706 11:52:15.742189 [DramC_TX_OE_Calibration] TA2
8707 11:52:15.743699 Original DQ_B0 (3 6) =30, OEN = 27
8708 11:52:15.747093 Original DQ_B1 (3 6) =30, OEN = 27
8709 11:52:15.750301 24, 0x0, End_B0=24 End_B1=24
8710 11:52:15.753980 25, 0x0, End_B0=25 End_B1=25
8711 11:52:15.756883 26, 0x0, End_B0=26 End_B1=26
8712 11:52:15.757354 27, 0x0, End_B0=27 End_B1=27
8713 11:52:15.760890 28, 0x0, End_B0=28 End_B1=28
8714 11:52:15.763924 29, 0x0, End_B0=29 End_B1=29
8715 11:52:15.767329 30, 0x0, End_B0=30 End_B1=30
8716 11:52:15.770221 31, 0x4141, End_B0=30 End_B1=30
8717 11:52:15.773610 Byte0 end_step=30 best_step=27
8718 11:52:15.774133 Byte1 end_step=30 best_step=27
8719 11:52:15.776817 Byte0 TX OE(2T, 0.5T) = (3, 3)
8720 11:52:15.780343 Byte1 TX OE(2T, 0.5T) = (3, 3)
8721 11:52:15.780840
8722 11:52:15.781209
8723 11:52:15.790279 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8724 11:52:15.790753 CH1 RK1: MR19=303, MR18=1D1D
8725 11:52:15.796697 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8726 11:52:15.800199 [RxdqsGatingPostProcess] freq 1600
8727 11:52:15.806596 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8728 11:52:15.809975 Pre-setting of DQS Precalculation
8729 11:52:15.813704 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8730 11:52:15.820349 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8731 11:52:15.830183 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8732 11:52:15.830749
8733 11:52:15.831121
8734 11:52:15.833321 [Calibration Summary] 3200 Mbps
8735 11:52:15.833788 CH 0, Rank 0
8736 11:52:15.836652 SW Impedance : PASS
8737 11:52:15.837117 DUTY Scan : NO K
8738 11:52:15.840094 ZQ Calibration : PASS
8739 11:52:15.843239 Jitter Meter : NO K
8740 11:52:15.843699 CBT Training : PASS
8741 11:52:15.846680 Write leveling : PASS
8742 11:52:15.847238 RX DQS gating : PASS
8743 11:52:15.849890 RX DQ/DQS(RDDQC) : PASS
8744 11:52:15.853170 TX DQ/DQS : PASS
8745 11:52:15.853634 RX DATLAT : PASS
8746 11:52:15.857133 RX DQ/DQS(Engine): PASS
8747 11:52:15.860154 TX OE : PASS
8748 11:52:15.860748 All Pass.
8749 11:52:15.861119
8750 11:52:15.861461 CH 0, Rank 1
8751 11:52:15.863646 SW Impedance : PASS
8752 11:52:15.866915 DUTY Scan : NO K
8753 11:52:15.867477 ZQ Calibration : PASS
8754 11:52:15.869791 Jitter Meter : NO K
8755 11:52:15.873320 CBT Training : PASS
8756 11:52:15.873874 Write leveling : PASS
8757 11:52:15.876573 RX DQS gating : PASS
8758 11:52:15.880347 RX DQ/DQS(RDDQC) : PASS
8759 11:52:15.880963 TX DQ/DQS : PASS
8760 11:52:15.883217 RX DATLAT : PASS
8761 11:52:15.886343 RX DQ/DQS(Engine): PASS
8762 11:52:15.886806 TX OE : PASS
8763 11:52:15.887174 All Pass.
8764 11:52:15.889606
8765 11:52:15.890069 CH 1, Rank 0
8766 11:52:15.893062 SW Impedance : PASS
8767 11:52:15.893525 DUTY Scan : NO K
8768 11:52:15.896275 ZQ Calibration : PASS
8769 11:52:15.896790 Jitter Meter : NO K
8770 11:52:15.899585 CBT Training : PASS
8771 11:52:15.902872 Write leveling : PASS
8772 11:52:15.903335 RX DQS gating : PASS
8773 11:52:15.906236 RX DQ/DQS(RDDQC) : PASS
8774 11:52:15.909547 TX DQ/DQS : PASS
8775 11:52:15.910013 RX DATLAT : PASS
8776 11:52:15.912948 RX DQ/DQS(Engine): PASS
8777 11:52:15.916594 TX OE : PASS
8778 11:52:15.917125 All Pass.
8779 11:52:15.917513
8780 11:52:15.917870 CH 1, Rank 1
8781 11:52:15.919570 SW Impedance : PASS
8782 11:52:15.923153 DUTY Scan : NO K
8783 11:52:15.923681 ZQ Calibration : PASS
8784 11:52:15.925989 Jitter Meter : NO K
8785 11:52:15.929440 CBT Training : PASS
8786 11:52:15.929963 Write leveling : PASS
8787 11:52:15.933096 RX DQS gating : PASS
8788 11:52:15.936023 RX DQ/DQS(RDDQC) : PASS
8789 11:52:15.936485 TX DQ/DQS : PASS
8790 11:52:15.939647 RX DATLAT : PASS
8791 11:52:15.942724 RX DQ/DQS(Engine): PASS
8792 11:52:15.943323 TX OE : PASS
8793 11:52:15.943713 All Pass.
8794 11:52:15.944060
8795 11:52:15.946445 DramC Write-DBI on
8796 11:52:15.949444 PER_BANK_REFRESH: Hybrid Mode
8797 11:52:15.949909 TX_TRACKING: ON
8798 11:52:15.959795 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8799 11:52:15.966555 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8800 11:52:15.976202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8801 11:52:15.979408 [FAST_K] Save calibration result to emmc
8802 11:52:15.982732 sync common calibartion params.
8803 11:52:15.983305 sync cbt_mode0:0, 1:0
8804 11:52:15.985903 dram_init: ddr_geometry: 0
8805 11:52:15.989386 dram_init: ddr_geometry: 0
8806 11:52:15.989845 dram_init: ddr_geometry: 0
8807 11:52:15.992733 0:dram_rank_size:80000000
8808 11:52:15.995945 1:dram_rank_size:80000000
8809 11:52:15.999729 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8810 11:52:16.002466 DFS_SHUFFLE_HW_MODE: ON
8811 11:52:16.005780 dramc_set_vcore_voltage set vcore to 725000
8812 11:52:16.009384 Read voltage for 1600, 0
8813 11:52:16.010038 Vio18 = 0
8814 11:52:16.010427 Vcore = 725000
8815 11:52:16.012786 Vdram = 0
8816 11:52:16.013277 Vddq = 0
8817 11:52:16.013860 Vmddr = 0
8818 11:52:16.015705 switch to 3200 Mbps bootup
8819 11:52:16.019674 [DramcRunTimeConfig]
8820 11:52:16.020398 PHYPLL
8821 11:52:16.021042 DPM_CONTROL_AFTERK: ON
8822 11:52:16.022628 PER_BANK_REFRESH: ON
8823 11:52:16.025864 REFRESH_OVERHEAD_REDUCTION: ON
8824 11:52:16.026427 CMD_PICG_NEW_MODE: OFF
8825 11:52:16.029419 XRTWTW_NEW_MODE: ON
8826 11:52:16.032250 XRTRTR_NEW_MODE: ON
8827 11:52:16.032740 TX_TRACKING: ON
8828 11:52:16.035881 RDSEL_TRACKING: OFF
8829 11:52:16.036447 DQS Precalculation for DVFS: ON
8830 11:52:16.038931 RX_TRACKING: OFF
8831 11:52:16.039393 HW_GATING DBG: ON
8832 11:52:16.042254 ZQCS_ENABLE_LP4: ON
8833 11:52:16.045907 RX_PICG_NEW_MODE: ON
8834 11:52:16.046391 TX_PICG_NEW_MODE: ON
8835 11:52:16.049007 ENABLE_RX_DCM_DPHY: ON
8836 11:52:16.052020 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8837 11:52:16.052483 DUMMY_READ_FOR_TRACKING: OFF
8838 11:52:16.055521 !!! SPM_CONTROL_AFTERK: OFF
8839 11:52:16.058984 !!! SPM could not control APHY
8840 11:52:16.061992 IMPEDANCE_TRACKING: ON
8841 11:52:16.062458 TEMP_SENSOR: ON
8842 11:52:16.065897 HW_SAVE_FOR_SR: OFF
8843 11:52:16.066460 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8844 11:52:16.072287 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8845 11:52:16.072805 Read ODT Tracking: ON
8846 11:52:16.075430 Refresh Rate DeBounce: ON
8847 11:52:16.078674 DFS_NO_QUEUE_FLUSH: ON
8848 11:52:16.082264 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8849 11:52:16.082812 ENABLE_DFS_RUNTIME_MRW: OFF
8850 11:52:16.085339 DDR_RESERVE_NEW_MODE: ON
8851 11:52:16.088731 MR_CBT_SWITCH_FREQ: ON
8852 11:52:16.089195 =========================
8853 11:52:16.108591 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8854 11:52:16.111623 dram_init: ddr_geometry: 0
8855 11:52:16.129869 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8856 11:52:16.133279 dram_init: dram init end (result: 0)
8857 11:52:16.139971 DRAM-K: Full calibration passed in 23403 msecs
8858 11:52:16.142659 MRC: failed to locate region type 0.
8859 11:52:16.143119 DRAM rank0 size:0x80000000,
8860 11:52:16.146150 DRAM rank1 size=0x80000000
8861 11:52:16.156449 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8862 11:52:16.162769 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8863 11:52:16.169542 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8864 11:52:16.175762 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8865 11:52:16.179122 DRAM rank0 size:0x80000000,
8866 11:52:16.182610 DRAM rank1 size=0x80000000
8867 11:52:16.183073 CBMEM:
8868 11:52:16.185839 IMD: root @ 0xfffff000 254 entries.
8869 11:52:16.189147 IMD: root @ 0xffffec00 62 entries.
8870 11:52:16.192447 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8871 11:52:16.195820 WARNING: RO_VPD is uninitialized or empty.
8872 11:52:16.202649 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8873 11:52:16.209014 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8874 11:52:16.222227 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8875 11:52:16.233899 BS: romstage times (exec / console): total (unknown) / 22948 ms
8876 11:52:16.234462
8877 11:52:16.234832
8878 11:52:16.243773 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8879 11:52:16.246870 ARM64: Exception handlers installed.
8880 11:52:16.250116 ARM64: Testing exception
8881 11:52:16.253270 ARM64: Done test exception
8882 11:52:16.253792 Enumerating buses...
8883 11:52:16.256913 Show all devs... Before device enumeration.
8884 11:52:16.259813 Root Device: enabled 1
8885 11:52:16.263389 CPU_CLUSTER: 0: enabled 1
8886 11:52:16.264074 CPU: 00: enabled 1
8887 11:52:16.266728 Compare with tree...
8888 11:52:16.267187 Root Device: enabled 1
8889 11:52:16.269666 CPU_CLUSTER: 0: enabled 1
8890 11:52:16.273132 CPU: 00: enabled 1
8891 11:52:16.273686 Root Device scanning...
8892 11:52:16.276680 scan_static_bus for Root Device
8893 11:52:16.279797 CPU_CLUSTER: 0 enabled
8894 11:52:16.283271 scan_static_bus for Root Device done
8895 11:52:16.286151 scan_bus: bus Root Device finished in 8 msecs
8896 11:52:16.286614 done
8897 11:52:16.292874 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8898 11:52:16.296119 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8899 11:52:16.302926 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8900 11:52:16.306337 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8901 11:52:16.309484 Allocating resources...
8902 11:52:16.312919 Reading resources...
8903 11:52:16.316139 Root Device read_resources bus 0 link: 0
8904 11:52:16.319418 DRAM rank0 size:0x80000000,
8905 11:52:16.319977 DRAM rank1 size=0x80000000
8906 11:52:16.323168 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8907 11:52:16.325941 CPU: 00 missing read_resources
8908 11:52:16.333179 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8909 11:52:16.336325 Root Device read_resources bus 0 link: 0 done
8910 11:52:16.336923 Done reading resources.
8911 11:52:16.342994 Show resources in subtree (Root Device)...After reading.
8912 11:52:16.346181 Root Device child on link 0 CPU_CLUSTER: 0
8913 11:52:16.349361 CPU_CLUSTER: 0 child on link 0 CPU: 00
8914 11:52:16.359763 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8915 11:52:16.360328 CPU: 00
8916 11:52:16.362835 Root Device assign_resources, bus 0 link: 0
8917 11:52:16.366262 CPU_CLUSTER: 0 missing set_resources
8918 11:52:16.372898 Root Device assign_resources, bus 0 link: 0 done
8919 11:52:16.373456 Done setting resources.
8920 11:52:16.379138 Show resources in subtree (Root Device)...After assigning values.
8921 11:52:16.382559 Root Device child on link 0 CPU_CLUSTER: 0
8922 11:52:16.385795 CPU_CLUSTER: 0 child on link 0 CPU: 00
8923 11:52:16.395627 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8924 11:52:16.396191 CPU: 00
8925 11:52:16.399011 Done allocating resources.
8926 11:52:16.405669 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8927 11:52:16.406161 Enabling resources...
8928 11:52:16.406537 done.
8929 11:52:16.412171 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8930 11:52:16.412665 Initializing devices...
8931 11:52:16.415792 Root Device init
8932 11:52:16.416447 init hardware done!
8933 11:52:16.418928 0x00000018: ctrlr->caps
8934 11:52:16.422305 52.000 MHz: ctrlr->f_max
8935 11:52:16.422881 0.400 MHz: ctrlr->f_min
8936 11:52:16.425721 0x40ff8080: ctrlr->voltages
8937 11:52:16.429046 sclk: 390625
8938 11:52:16.429611 Bus Width = 1
8939 11:52:16.429982 sclk: 390625
8940 11:52:16.432326 Bus Width = 1
8941 11:52:16.432927 Early init status = 3
8942 11:52:16.438479 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8943 11:52:16.442011 in-header: 03 fb 00 00 01 00 00 00
8944 11:52:16.445323 in-data: 01
8945 11:52:16.448948 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8946 11:52:16.452565 in-header: 03 fb 00 00 01 00 00 00
8947 11:52:16.456007 in-data: 01
8948 11:52:16.459184 [SSUSB] Setting up USB HOST controller...
8949 11:52:16.462816 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8950 11:52:16.465759 [SSUSB] phy power-on done.
8951 11:52:16.469497 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8952 11:52:16.475845 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8953 11:52:16.479344 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8954 11:52:16.485471 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8955 11:52:16.492428 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8956 11:52:16.498847 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8957 11:52:16.505579 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8958 11:52:16.512353 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8959 11:52:16.515333 SPM: binary array size = 0x9dc
8960 11:52:16.518760 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8961 11:52:16.525202 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8962 11:52:16.532141 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8963 11:52:16.538349 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8964 11:52:16.542140 configure_display: Starting display init
8965 11:52:16.575983 anx7625_power_on_init: Init interface.
8966 11:52:16.579707 anx7625_disable_pd_protocol: Disabled PD feature.
8967 11:52:16.582568 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8968 11:52:16.610561 anx7625_start_dp_work: Secure OCM version=00
8969 11:52:16.613417 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8970 11:52:16.628353 sp_tx_get_edid_block: EDID Block = 1
8971 11:52:16.731235 Extracted contents:
8972 11:52:16.734411 header: 00 ff ff ff ff ff ff 00
8973 11:52:16.737818 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8974 11:52:16.740837 version: 01 04
8975 11:52:16.743819 basic params: 95 1f 11 78 0a
8976 11:52:16.747204 chroma info: 76 90 94 55 54 90 27 21 50 54
8977 11:52:16.750854 established: 00 00 00
8978 11:52:16.757224 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8979 11:52:16.764103 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8980 11:52:16.767307 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8981 11:52:16.773872 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8982 11:52:16.780644 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8983 11:52:16.783538 extensions: 00
8984 11:52:16.784085 checksum: fb
8985 11:52:16.784454
8986 11:52:16.790214 Manufacturer: IVO Model 57d Serial Number 0
8987 11:52:16.790757 Made week 0 of 2020
8988 11:52:16.793309 EDID version: 1.4
8989 11:52:16.793768 Digital display
8990 11:52:16.796628 6 bits per primary color channel
8991 11:52:16.797302 DisplayPort interface
8992 11:52:16.799955 Maximum image size: 31 cm x 17 cm
8993 11:52:16.803716 Gamma: 220%
8994 11:52:16.804281 Check DPMS levels
8995 11:52:16.809969 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8996 11:52:16.813942 First detailed timing is preferred timing
8997 11:52:16.814567 Established timings supported:
8998 11:52:16.816699 Standard timings supported:
8999 11:52:16.819761 Detailed timings
9000 11:52:16.822954 Hex of detail: 383680a07038204018303c0035ae10000019
9001 11:52:16.829928 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9002 11:52:16.833444 0780 0798 07c8 0820 hborder 0
9003 11:52:16.836478 0438 043b 0447 0458 vborder 0
9004 11:52:16.840107 -hsync -vsync
9005 11:52:16.840710 Did detailed timing
9006 11:52:16.846884 Hex of detail: 000000000000000000000000000000000000
9007 11:52:16.849922 Manufacturer-specified data, tag 0
9008 11:52:16.853355 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9009 11:52:16.856566 ASCII string: InfoVision
9010 11:52:16.860109 Hex of detail: 000000fe00523134304e574635205248200a
9011 11:52:16.863385 ASCII string: R140NWF5 RH
9012 11:52:16.864018 Checksum
9013 11:52:16.866368 Checksum: 0xfb (valid)
9014 11:52:16.869723 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9015 11:52:16.872970 DSI data_rate: 832800000 bps
9016 11:52:16.879666 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9017 11:52:16.882793 anx7625_parse_edid: pixelclock(138800).
9018 11:52:16.886150 hactive(1920), hsync(48), hfp(24), hbp(88)
9019 11:52:16.889296 vactive(1080), vsync(12), vfp(3), vbp(17)
9020 11:52:16.892627 anx7625_dsi_config: config dsi.
9021 11:52:16.899192 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9022 11:52:16.913104 anx7625_dsi_config: success to config DSI
9023 11:52:16.916260 anx7625_dp_start: MIPI phy setup OK.
9024 11:52:16.919579 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9025 11:52:16.922812 mtk_ddp_mode_set invalid vrefresh 60
9026 11:52:16.926279 main_disp_path_setup
9027 11:52:16.926852 ovl_layer_smi_id_en
9028 11:52:16.929316 ovl_layer_smi_id_en
9029 11:52:16.929841 ccorr_config
9030 11:52:16.930318 aal_config
9031 11:52:16.932623 gamma_config
9032 11:52:16.933099 postmask_config
9033 11:52:16.935949 dither_config
9034 11:52:16.939382 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9035 11:52:16.946234 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9036 11:52:16.949369 Root Device init finished in 530 msecs
9037 11:52:16.952587 CPU_CLUSTER: 0 init
9038 11:52:16.959553 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9039 11:52:16.966233 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9040 11:52:16.966804 APU_MBOX 0x190000b0 = 0x10001
9041 11:52:16.969123 APU_MBOX 0x190001b0 = 0x10001
9042 11:52:16.972746 APU_MBOX 0x190005b0 = 0x10001
9043 11:52:16.976028 APU_MBOX 0x190006b0 = 0x10001
9044 11:52:16.982271 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9045 11:52:16.991913 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9046 11:52:17.004651 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9047 11:52:17.011056 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9048 11:52:17.022583 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9049 11:52:17.032085 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9050 11:52:17.035141 CPU_CLUSTER: 0 init finished in 81 msecs
9051 11:52:17.038595 Devices initialized
9052 11:52:17.041891 Show all devs... After init.
9053 11:52:17.042450 Root Device: enabled 1
9054 11:52:17.045182 CPU_CLUSTER: 0: enabled 1
9055 11:52:17.048295 CPU: 00: enabled 1
9056 11:52:17.051723 BS: BS_DEV_INIT run times (exec / console): 207 / 428 ms
9057 11:52:17.054723 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9058 11:52:17.058092 ELOG: NV offset 0x57f000 size 0x1000
9059 11:52:17.064790 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9060 11:52:17.071842 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9061 11:52:17.074731 ELOG: Event(17) added with size 13 at 2023-11-23 11:52:18 UTC
9062 11:52:17.078007 out: cmd=0x121: 03 db 21 01 00 00 00 00
9063 11:52:17.083011 in-header: 03 1f 00 00 2c 00 00 00
9064 11:52:17.096732 in-data: 44 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9065 11:52:17.102933 ELOG: Event(A1) added with size 10 at 2023-11-23 11:52:18 UTC
9066 11:52:17.109517 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9067 11:52:17.116062 ELOG: Event(A0) added with size 9 at 2023-11-23 11:52:18 UTC
9068 11:52:17.119948 elog_add_boot_reason: Logged dev mode boot
9069 11:52:17.123055 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9070 11:52:17.126455 Finalize devices...
9071 11:52:17.127012 Devices finalized
9072 11:52:17.132736 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9073 11:52:17.136207 Writing coreboot table at 0xffe64000
9074 11:52:17.139385 0. 000000000010a000-0000000000113fff: RAMSTAGE
9075 11:52:17.142851 1. 0000000040000000-00000000400fffff: RAM
9076 11:52:17.149471 2. 0000000040100000-000000004032afff: RAMSTAGE
9077 11:52:17.152593 3. 000000004032b000-00000000545fffff: RAM
9078 11:52:17.155653 4. 0000000054600000-000000005465ffff: BL31
9079 11:52:17.159042 5. 0000000054660000-00000000ffe63fff: RAM
9080 11:52:17.165967 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9081 11:52:17.169436 7. 0000000100000000-000000013fffffff: RAM
9082 11:52:17.172318 Passing 5 GPIOs to payload:
9083 11:52:17.175927 NAME | PORT | POLARITY | VALUE
9084 11:52:17.179162 EC in RW | 0x000000aa | low | undefined
9085 11:52:17.185472 EC interrupt | 0x00000005 | low | undefined
9086 11:52:17.189141 TPM interrupt | 0x000000ab | high | undefined
9087 11:52:17.195335 SD card detect | 0x00000011 | high | undefined
9088 11:52:17.199036 speaker enable | 0x00000093 | high | undefined
9089 11:52:17.202172 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9090 11:52:17.205186 in-header: 03 f4 00 00 02 00 00 00
9091 11:52:17.208696 in-data: 07 00
9092 11:52:17.209164 ADC[4]: Raw value=668590 ID=5
9093 11:52:17.212039 ADC[3]: Raw value=212549 ID=1
9094 11:52:17.215290 RAM Code: 0x51
9095 11:52:17.215754 ADC[6]: Raw value=74410 ID=0
9096 11:52:17.218245 ADC[5]: Raw value=211812 ID=1
9097 11:52:17.221729 SKU Code: 0x1
9098 11:52:17.224796 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9a7
9099 11:52:17.228270 coreboot table: 964 bytes.
9100 11:52:17.231747 IMD ROOT 0. 0xfffff000 0x00001000
9101 11:52:17.234870 IMD SMALL 1. 0xffffe000 0x00001000
9102 11:52:17.238249 RO MCACHE 2. 0xffffc000 0x00001104
9103 11:52:17.241350 CONSOLE 3. 0xfff7c000 0x00080000
9104 11:52:17.245155 FMAP 4. 0xfff7b000 0x00000452
9105 11:52:17.248551 TIME STAMP 5. 0xfff7a000 0x00000910
9106 11:52:17.251659 VBOOT WORK 6. 0xfff66000 0x00014000
9107 11:52:17.255013 RAMOOPS 7. 0xffe66000 0x00100000
9108 11:52:17.258046 COREBOOT 8. 0xffe64000 0x00002000
9109 11:52:17.258602 IMD small region:
9110 11:52:17.265011 IMD ROOT 0. 0xffffec00 0x00000400
9111 11:52:17.267933 VPD 1. 0xffffeb80 0x0000006c
9112 11:52:17.271401 MMC STATUS 2. 0xffffeb60 0x00000004
9113 11:52:17.274438 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9114 11:52:17.277947 Probing TPM: done!
9115 11:52:17.281411 Connected to device vid:did:rid of 1ae0:0028:00
9116 11:52:17.291660 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9117 11:52:17.294977 Initialized TPM device CR50 revision 0
9118 11:52:17.298750 Checking cr50 for pending updates
9119 11:52:17.302307 Reading cr50 TPM mode
9120 11:52:17.311263 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9121 11:52:17.317280 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9122 11:52:17.357913 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9123 11:52:17.360861 Checking segment from ROM address 0x40100000
9124 11:52:17.364382 Checking segment from ROM address 0x4010001c
9125 11:52:17.370985 Loading segment from ROM address 0x40100000
9126 11:52:17.371533 code (compression=0)
9127 11:52:17.380782 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9128 11:52:17.387429 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9129 11:52:17.387980 it's not compressed!
9130 11:52:17.394047 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9131 11:52:17.400323 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9132 11:52:17.418121 Loading segment from ROM address 0x4010001c
9133 11:52:17.418697 Entry Point 0x80000000
9134 11:52:17.421327 Loaded segments
9135 11:52:17.424918 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9136 11:52:17.431821 Jumping to boot code at 0x80000000(0xffe64000)
9137 11:52:17.437924 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9138 11:52:17.444676 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9139 11:52:17.452573 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9140 11:52:17.455826 Checking segment from ROM address 0x40100000
9141 11:52:17.459369 Checking segment from ROM address 0x4010001c
9142 11:52:17.466010 Loading segment from ROM address 0x40100000
9143 11:52:17.466573 code (compression=1)
9144 11:52:17.472951 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9145 11:52:17.482534 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9146 11:52:17.483111 using LZMA
9147 11:52:17.490806 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9148 11:52:17.497494 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9149 11:52:17.500761 Loading segment from ROM address 0x4010001c
9150 11:52:17.501357 Entry Point 0x54601000
9151 11:52:17.504107 Loaded segments
9152 11:52:17.507191 NOTICE: MT8192 bl31_setup
9153 11:52:17.514405 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9154 11:52:17.517770 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9155 11:52:17.521220 WARNING: region 0:
9156 11:52:17.524597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9157 11:52:17.525158 WARNING: region 1:
9158 11:52:17.531238 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9159 11:52:17.534308 WARNING: region 2:
9160 11:52:17.538247 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9161 11:52:17.541353 WARNING: region 3:
9162 11:52:17.544833 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9163 11:52:17.548022 WARNING: region 4:
9164 11:52:17.554700 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9165 11:52:17.555265 WARNING: region 5:
9166 11:52:17.557849 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9167 11:52:17.561316 WARNING: region 6:
9168 11:52:17.564662 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9169 11:52:17.567783 WARNING: region 7:
9170 11:52:17.571223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9171 11:52:17.577616 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9172 11:52:17.580919 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9173 11:52:17.584309 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9174 11:52:17.591199 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9175 11:52:17.594045 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9176 11:52:17.597671 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9177 11:52:17.604003 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9178 11:52:17.607795 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9179 11:52:17.614095 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9180 11:52:17.617569 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9181 11:52:17.621098 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9182 11:52:17.627606 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9183 11:52:17.631046 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9184 11:52:17.634334 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9185 11:52:17.641127 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9186 11:52:17.644406 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9187 11:52:17.651043 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9188 11:52:17.654112 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9189 11:52:17.657883 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9190 11:52:17.664467 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9191 11:52:17.667973 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9192 11:52:17.670918 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9193 11:52:17.677672 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9194 11:52:17.681187 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9195 11:52:17.688138 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9196 11:52:17.691357 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9197 11:52:17.694220 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9198 11:52:17.701101 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9199 11:52:17.704493 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9200 11:52:17.707775 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9201 11:52:17.714502 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9202 11:52:17.717920 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9203 11:52:17.724644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9204 11:52:17.727927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9205 11:52:17.731038 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9206 11:52:17.734823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9207 11:52:17.737781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9208 11:52:17.744694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9209 11:52:17.747789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9210 11:52:17.751218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9211 11:52:17.754627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9212 11:52:17.761240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9213 11:52:17.764563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9214 11:52:17.767681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9215 11:52:17.774484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9216 11:52:17.778056 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9217 11:52:17.780826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9218 11:52:17.784370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9219 11:52:17.791009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9220 11:52:17.794068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9221 11:52:17.800641 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9222 11:52:17.804282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9223 11:52:17.807349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9224 11:52:17.814558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9225 11:52:17.817326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9226 11:52:17.824008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9227 11:52:17.827540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9228 11:52:17.833788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9229 11:52:17.837219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9230 11:52:17.844298 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9231 11:52:17.847598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9232 11:52:17.850827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9233 11:52:17.857392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9234 11:52:17.860644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9235 11:52:17.867630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9236 11:52:17.870809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9237 11:52:17.877172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9238 11:52:17.880681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9239 11:52:17.883954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9240 11:52:17.890712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9241 11:52:17.893623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9242 11:52:17.900617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9243 11:52:17.903949 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9244 11:52:17.910081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9245 11:52:17.913683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9246 11:52:17.920631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9247 11:52:17.923782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9248 11:52:17.927163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9249 11:52:17.934194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9250 11:52:17.936942 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9251 11:52:17.943887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9252 11:52:17.947179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9253 11:52:17.954030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9254 11:52:17.956971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9255 11:52:17.960139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9256 11:52:17.966948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9257 11:52:17.970235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9258 11:52:17.977012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9259 11:52:17.980111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9260 11:52:17.986936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9261 11:52:17.990565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9262 11:52:17.993654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9263 11:52:18.000173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9264 11:52:18.003684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9265 11:52:18.010073 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9266 11:52:18.013537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9267 11:52:18.020240 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9268 11:52:18.023841 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9269 11:52:18.027124 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9270 11:52:18.030366 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9271 11:52:18.033448 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9272 11:52:18.040113 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9273 11:52:18.043448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9274 11:52:18.050222 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9275 11:52:18.053500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9276 11:52:18.057025 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9277 11:52:18.063508 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9278 11:52:18.067013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9279 11:52:18.074041 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9280 11:52:18.076949 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9281 11:52:18.079946 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9282 11:52:18.086747 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9283 11:52:18.089880 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9284 11:52:18.096651 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9285 11:52:18.099916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9286 11:52:18.103398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9287 11:52:18.110319 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9288 11:52:18.113316 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9289 11:52:18.116902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9290 11:52:18.123528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9291 11:52:18.126516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9292 11:52:18.130024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9293 11:52:18.133322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9294 11:52:18.140044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9295 11:52:18.143158 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9296 11:52:18.146830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9297 11:52:18.153318 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9298 11:52:18.156452 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9299 11:52:18.159869 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9300 11:52:18.166132 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9301 11:52:18.169884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9302 11:52:18.176392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9303 11:52:18.179535 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9304 11:52:18.182880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9305 11:52:18.189478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9306 11:52:18.192803 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9307 11:52:18.199360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9308 11:52:18.202873 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9309 11:52:18.206252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9310 11:52:18.212697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9311 11:52:18.215957 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9312 11:52:18.222840 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9313 11:52:18.225979 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9314 11:52:18.229498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9315 11:52:18.235995 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9316 11:52:18.239294 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9317 11:52:18.245896 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9318 11:52:18.249302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9319 11:52:18.252893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9320 11:52:18.259216 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9321 11:52:18.262505 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9322 11:52:18.266079 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9323 11:52:18.272400 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9324 11:52:18.275827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9325 11:52:18.282381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9326 11:52:18.285787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9327 11:52:18.289531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9328 11:52:18.295700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9329 11:52:18.299057 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9330 11:52:18.306308 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9331 11:52:18.309112 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9332 11:52:18.312483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9333 11:52:18.319126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9334 11:52:18.322504 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9335 11:52:18.328810 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9336 11:52:18.332383 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9337 11:52:18.335615 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9338 11:52:18.342297 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9339 11:52:18.345465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9340 11:52:18.349046 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9341 11:52:18.355761 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9342 11:52:18.358710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9343 11:52:18.365448 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9344 11:52:18.368698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9345 11:52:18.371991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9346 11:52:18.378716 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9347 11:52:18.381934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9348 11:52:18.388564 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9349 11:52:18.391863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9350 11:52:18.395208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9351 11:52:18.401634 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9352 11:52:18.405135 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9353 11:52:18.411766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9354 11:52:18.415108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9355 11:52:18.418661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9356 11:52:18.425030 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9357 11:52:18.428258 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9358 11:52:18.435006 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9359 11:52:18.438553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9360 11:52:18.441965 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9361 11:52:18.448406 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9362 11:52:18.451869 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9363 11:52:18.458321 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9364 11:52:18.461630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9365 11:52:18.464865 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9366 11:52:18.471463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9367 11:52:18.474866 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9368 11:52:18.481494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9369 11:52:18.484882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9370 11:52:18.491277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9371 11:52:18.494865 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9372 11:52:18.498145 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9373 11:52:18.504870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9374 11:52:18.508038 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9375 11:52:18.514534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9376 11:52:18.517941 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9377 11:52:18.524276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9378 11:52:18.527723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9379 11:52:18.531103 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9380 11:52:18.537838 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9381 11:52:18.541027 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9382 11:52:18.547790 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9383 11:52:18.550881 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9384 11:52:18.554206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9385 11:52:18.560865 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9386 11:52:18.564480 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9387 11:52:18.570982 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9388 11:52:18.574247 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9389 11:52:18.580963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9390 11:52:18.584038 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9391 11:52:18.587251 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9392 11:52:18.593961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9393 11:52:18.597263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9394 11:52:18.603912 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9395 11:52:18.607306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9396 11:52:18.613913 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9397 11:52:18.617368 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9398 11:52:18.620678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9399 11:52:18.627185 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9400 11:52:18.630653 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9401 11:52:18.633872 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9402 11:52:18.637011 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9403 11:52:18.643760 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9404 11:52:18.646919 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9405 11:52:18.650179 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9406 11:52:18.656774 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9407 11:52:18.660036 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9408 11:52:18.663684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9409 11:52:18.669959 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9410 11:52:18.673432 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9411 11:52:18.680154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9412 11:52:18.683289 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9413 11:52:18.686676 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9414 11:52:18.693287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9415 11:52:18.696366 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9416 11:52:18.699757 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9417 11:52:18.706546 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9418 11:52:18.709634 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9419 11:52:18.713064 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9420 11:52:18.719728 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9421 11:52:18.722922 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9422 11:52:18.729633 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9423 11:52:18.732859 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9424 11:52:18.736105 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9425 11:52:18.742663 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9426 11:52:18.746220 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9427 11:52:18.752625 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9428 11:52:18.756136 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9429 11:52:18.759451 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9430 11:52:18.766138 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9431 11:52:18.769484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9432 11:52:18.772337 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9433 11:52:18.779003 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9434 11:52:18.782741 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9435 11:52:18.785955 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9436 11:52:18.792660 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9437 11:52:18.796000 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9438 11:52:18.802357 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9439 11:52:18.805696 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9440 11:52:18.809052 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9441 11:52:18.812387 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9442 11:52:18.815871 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9443 11:52:18.822265 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9444 11:52:18.826022 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9445 11:52:18.828951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9446 11:52:18.832146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9447 11:52:18.838980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9448 11:52:18.842482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9449 11:52:18.845389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9450 11:52:18.848962 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9451 11:52:18.855789 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9452 11:52:18.859017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9453 11:52:18.862556 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9454 11:52:18.868813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9455 11:52:18.872253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9456 11:52:18.878891 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9457 11:52:18.881928 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9458 11:52:18.888629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9459 11:52:18.891809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9460 11:52:18.895451 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9461 11:52:18.902177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9462 11:52:18.905327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9463 11:52:18.912035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9464 11:52:18.915029 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9465 11:52:18.918709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9466 11:52:18.924991 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9467 11:52:18.928652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9468 11:52:18.935195 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9469 11:52:18.938472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9470 11:52:18.941547 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9471 11:52:18.948421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9472 11:52:18.951638 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9473 11:52:18.958605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9474 11:52:18.961793 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9475 11:52:18.968439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9476 11:52:18.971514 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9477 11:52:18.975180 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9478 11:52:18.981592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9479 11:52:18.985053 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9480 11:52:18.991381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9481 11:52:18.994722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9482 11:52:18.998173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9483 11:52:19.004829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9484 11:52:19.007889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9485 11:52:19.014517 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9486 11:52:19.018100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9487 11:52:19.021243 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9488 11:52:19.028038 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9489 11:52:19.031285 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9490 11:52:19.037593 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9491 11:52:19.041013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9492 11:52:19.044600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9493 11:52:19.050960 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9494 11:52:19.054250 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9495 11:52:19.060885 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9496 11:52:19.064114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9497 11:52:19.070791 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9498 11:52:19.074181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9499 11:52:19.077962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9500 11:52:19.084273 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9501 11:52:19.087473 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9502 11:52:19.093817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9503 11:52:19.097209 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9504 11:52:19.104016 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9505 11:52:19.107185 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9506 11:52:19.110269 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9507 11:52:19.117101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9508 11:52:19.120462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9509 11:52:19.127320 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9510 11:52:19.130591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9511 11:52:19.133704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9512 11:52:19.140552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9513 11:52:19.143835 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9514 11:52:19.150704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9515 11:52:19.154106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9516 11:52:19.156907 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9517 11:52:19.163625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9518 11:52:19.167072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9519 11:52:19.173874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9520 11:52:19.177028 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9521 11:52:19.180200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9522 11:52:19.186834 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9523 11:52:19.190283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9524 11:52:19.196980 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9525 11:52:19.199951 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9526 11:52:19.206862 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9527 11:52:19.210191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9528 11:52:19.213474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9529 11:52:19.219947 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9530 11:52:19.223172 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9531 11:52:19.229903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9532 11:52:19.233338 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9533 11:52:19.240228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9534 11:52:19.243134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9535 11:52:19.246470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9536 11:52:19.253325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9537 11:52:19.256917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9538 11:52:19.263399 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9539 11:52:19.266353 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9540 11:52:19.273081 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9541 11:52:19.276458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9542 11:52:19.280157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9543 11:52:19.286310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9544 11:52:19.289743 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9545 11:52:19.296301 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9546 11:52:19.299599 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9547 11:52:19.306101 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9548 11:52:19.309607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9549 11:52:19.316089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9550 11:52:19.319455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9551 11:52:19.323100 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9552 11:52:19.329515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9553 11:52:19.332552 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9554 11:52:19.339455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9555 11:52:19.342691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9556 11:52:19.349276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9557 11:52:19.352498 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9558 11:52:19.356032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9559 11:52:19.362522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9560 11:52:19.365984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9561 11:52:19.372612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9562 11:52:19.375840 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9563 11:52:19.382574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9564 11:52:19.385958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9565 11:52:19.392226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9566 11:52:19.395848 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9567 11:52:19.398873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9568 11:52:19.405757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9569 11:52:19.408947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9570 11:52:19.415449 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9571 11:52:19.418743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9572 11:52:19.425554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9573 11:52:19.429210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9574 11:52:19.432177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9575 11:52:19.438732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9576 11:52:19.442059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9577 11:52:19.448543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9578 11:52:19.451860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9579 11:52:19.458749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9580 11:52:19.462234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9581 11:52:19.468640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9582 11:52:19.471972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9583 11:52:19.478563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9584 11:52:19.481703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9585 11:52:19.488440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9586 11:52:19.491624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9587 11:52:19.498149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9588 11:52:19.501387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9589 11:52:19.508471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9590 11:52:19.511361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9591 11:52:19.518155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9592 11:52:19.521807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9593 11:52:19.528056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9594 11:52:19.531394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9595 11:52:19.537952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9596 11:52:19.541310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9597 11:52:19.547911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9598 11:52:19.551208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9599 11:52:19.557785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9600 11:52:19.561139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9601 11:52:19.567934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9602 11:52:19.570918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9603 11:52:19.577922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9604 11:52:19.581158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9605 11:52:19.584353 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9606 11:52:19.587908 INFO: [APUAPC] vio 0
9607 11:52:19.594314 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9608 11:52:19.597673 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9609 11:52:19.601049 INFO: [APUAPC] D0_APC_0: 0x400510
9610 11:52:19.604182 INFO: [APUAPC] D0_APC_1: 0x0
9611 11:52:19.607722 INFO: [APUAPC] D0_APC_2: 0x1540
9612 11:52:19.610822 INFO: [APUAPC] D0_APC_3: 0x0
9613 11:52:19.614344 INFO: [APUAPC] D1_APC_0: 0xffffffff
9614 11:52:19.617537 INFO: [APUAPC] D1_APC_1: 0xffffffff
9615 11:52:19.621287 INFO: [APUAPC] D1_APC_2: 0x3fffff
9616 11:52:19.621368 INFO: [APUAPC] D1_APC_3: 0x0
9617 11:52:19.627351 INFO: [APUAPC] D2_APC_0: 0xffffffff
9618 11:52:19.630900 INFO: [APUAPC] D2_APC_1: 0xffffffff
9619 11:52:19.634142 INFO: [APUAPC] D2_APC_2: 0x3fffff
9620 11:52:19.634228 INFO: [APUAPC] D2_APC_3: 0x0
9621 11:52:19.637269 INFO: [APUAPC] D3_APC_0: 0xffffffff
9622 11:52:19.643891 INFO: [APUAPC] D3_APC_1: 0xffffffff
9623 11:52:19.643969 INFO: [APUAPC] D3_APC_2: 0x3fffff
9624 11:52:19.647610 INFO: [APUAPC] D3_APC_3: 0x0
9625 11:52:19.650836 INFO: [APUAPC] D4_APC_0: 0xffffffff
9626 11:52:19.653824 INFO: [APUAPC] D4_APC_1: 0xffffffff
9627 11:52:19.657628 INFO: [APUAPC] D4_APC_2: 0x3fffff
9628 11:52:19.661004 INFO: [APUAPC] D4_APC_3: 0x0
9629 11:52:19.663771 INFO: [APUAPC] D5_APC_0: 0xffffffff
9630 11:52:19.667127 INFO: [APUAPC] D5_APC_1: 0xffffffff
9631 11:52:19.670326 INFO: [APUAPC] D5_APC_2: 0x3fffff
9632 11:52:19.673900 INFO: [APUAPC] D5_APC_3: 0x0
9633 11:52:19.677149 INFO: [APUAPC] D6_APC_0: 0xffffffff
9634 11:52:19.680570 INFO: [APUAPC] D6_APC_1: 0xffffffff
9635 11:52:19.683761 INFO: [APUAPC] D6_APC_2: 0x3fffff
9636 11:52:19.687083 INFO: [APUAPC] D6_APC_3: 0x0
9637 11:52:19.690401 INFO: [APUAPC] D7_APC_0: 0xffffffff
9638 11:52:19.693962 INFO: [APUAPC] D7_APC_1: 0xffffffff
9639 11:52:19.696896 INFO: [APUAPC] D7_APC_2: 0x3fffff
9640 11:52:19.700248 INFO: [APUAPC] D7_APC_3: 0x0
9641 11:52:19.703654 INFO: [APUAPC] D8_APC_0: 0xffffffff
9642 11:52:19.706854 INFO: [APUAPC] D8_APC_1: 0xffffffff
9643 11:52:19.710179 INFO: [APUAPC] D8_APC_2: 0x3fffff
9644 11:52:19.713508 INFO: [APUAPC] D8_APC_3: 0x0
9645 11:52:19.716762 INFO: [APUAPC] D9_APC_0: 0xffffffff
9646 11:52:19.720110 INFO: [APUAPC] D9_APC_1: 0xffffffff
9647 11:52:19.723449 INFO: [APUAPC] D9_APC_2: 0x3fffff
9648 11:52:19.726602 INFO: [APUAPC] D9_APC_3: 0x0
9649 11:52:19.730209 INFO: [APUAPC] D10_APC_0: 0xffffffff
9650 11:52:19.733216 INFO: [APUAPC] D10_APC_1: 0xffffffff
9651 11:52:19.737051 INFO: [APUAPC] D10_APC_2: 0x3fffff
9652 11:52:19.740289 INFO: [APUAPC] D10_APC_3: 0x0
9653 11:52:19.743161 INFO: [APUAPC] D11_APC_0: 0xffffffff
9654 11:52:19.746674 INFO: [APUAPC] D11_APC_1: 0xffffffff
9655 11:52:19.750081 INFO: [APUAPC] D11_APC_2: 0x3fffff
9656 11:52:19.753463 INFO: [APUAPC] D11_APC_3: 0x0
9657 11:52:19.756433 INFO: [APUAPC] D12_APC_0: 0xffffffff
9658 11:52:19.760046 INFO: [APUAPC] D12_APC_1: 0xffffffff
9659 11:52:19.763141 INFO: [APUAPC] D12_APC_2: 0x3fffff
9660 11:52:19.766957 INFO: [APUAPC] D12_APC_3: 0x0
9661 11:52:19.769980 INFO: [APUAPC] D13_APC_0: 0xffffffff
9662 11:52:19.773112 INFO: [APUAPC] D13_APC_1: 0xffffffff
9663 11:52:19.776563 INFO: [APUAPC] D13_APC_2: 0x3fffff
9664 11:52:19.780020 INFO: [APUAPC] D13_APC_3: 0x0
9665 11:52:19.783495 INFO: [APUAPC] D14_APC_0: 0xffffffff
9666 11:52:19.786445 INFO: [APUAPC] D14_APC_1: 0xffffffff
9667 11:52:19.789859 INFO: [APUAPC] D14_APC_2: 0x3fffff
9668 11:52:19.793141 INFO: [APUAPC] D14_APC_3: 0x0
9669 11:52:19.796266 INFO: [APUAPC] D15_APC_0: 0xffffffff
9670 11:52:19.799895 INFO: [APUAPC] D15_APC_1: 0xffffffff
9671 11:52:19.803016 INFO: [APUAPC] D15_APC_2: 0x3fffff
9672 11:52:19.806314 INFO: [APUAPC] D15_APC_3: 0x0
9673 11:52:19.809627 INFO: [APUAPC] APC_CON: 0x4
9674 11:52:19.812849 INFO: [NOCDAPC] D0_APC_0: 0x0
9675 11:52:19.816386 INFO: [NOCDAPC] D0_APC_1: 0x0
9676 11:52:19.819453 INFO: [NOCDAPC] D1_APC_0: 0x0
9677 11:52:19.823322 INFO: [NOCDAPC] D1_APC_1: 0xfff
9678 11:52:19.823401 INFO: [NOCDAPC] D2_APC_0: 0x0
9679 11:52:19.826129 INFO: [NOCDAPC] D2_APC_1: 0xfff
9680 11:52:19.829822 INFO: [NOCDAPC] D3_APC_0: 0x0
9681 11:52:19.832895 INFO: [NOCDAPC] D3_APC_1: 0xfff
9682 11:52:19.836167 INFO: [NOCDAPC] D4_APC_0: 0x0
9683 11:52:19.839543 INFO: [NOCDAPC] D4_APC_1: 0xfff
9684 11:52:19.843027 INFO: [NOCDAPC] D5_APC_0: 0x0
9685 11:52:19.846201 INFO: [NOCDAPC] D5_APC_1: 0xfff
9686 11:52:19.849654 INFO: [NOCDAPC] D6_APC_0: 0x0
9687 11:52:19.853030 INFO: [NOCDAPC] D6_APC_1: 0xfff
9688 11:52:19.853109 INFO: [NOCDAPC] D7_APC_0: 0x0
9689 11:52:19.856175 INFO: [NOCDAPC] D7_APC_1: 0xfff
9690 11:52:19.859495 INFO: [NOCDAPC] D8_APC_0: 0x0
9691 11:52:19.863399 INFO: [NOCDAPC] D8_APC_1: 0xfff
9692 11:52:19.866156 INFO: [NOCDAPC] D9_APC_0: 0x0
9693 11:52:19.869526 INFO: [NOCDAPC] D9_APC_1: 0xfff
9694 11:52:19.872860 INFO: [NOCDAPC] D10_APC_0: 0x0
9695 11:52:19.876017 INFO: [NOCDAPC] D10_APC_1: 0xfff
9696 11:52:19.879554 INFO: [NOCDAPC] D11_APC_0: 0x0
9697 11:52:19.882901 INFO: [NOCDAPC] D11_APC_1: 0xfff
9698 11:52:19.886302 INFO: [NOCDAPC] D12_APC_0: 0x0
9699 11:52:19.889418 INFO: [NOCDAPC] D12_APC_1: 0xfff
9700 11:52:19.892620 INFO: [NOCDAPC] D13_APC_0: 0x0
9701 11:52:19.895909 INFO: [NOCDAPC] D13_APC_1: 0xfff
9702 11:52:19.895994 INFO: [NOCDAPC] D14_APC_0: 0x0
9703 11:52:19.899247 INFO: [NOCDAPC] D14_APC_1: 0xfff
9704 11:52:19.902790 INFO: [NOCDAPC] D15_APC_0: 0x0
9705 11:52:19.905902 INFO: [NOCDAPC] D15_APC_1: 0xfff
9706 11:52:19.909403 INFO: [NOCDAPC] APC_CON: 0x4
9707 11:52:19.912710 INFO: [APUAPC] set_apusys_apc done
9708 11:52:19.916275 INFO: [DEVAPC] devapc_init done
9709 11:52:19.919332 INFO: GICv3 without legacy support detected.
9710 11:52:19.925905 INFO: ARM GICv3 driver initialized in EL3
9711 11:52:19.929180 INFO: Maximum SPI INTID supported: 639
9712 11:52:19.932425 INFO: BL31: Initializing runtime services
9713 11:52:19.939506 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9714 11:52:19.939591 INFO: SPM: enable CPC mode
9715 11:52:19.946207 INFO: mcdi ready for mcusys-off-idle and system suspend
9716 11:52:19.949309 INFO: BL31: Preparing for EL3 exit to normal world
9717 11:52:19.952364 INFO: Entry point address = 0x80000000
9718 11:52:19.955687 INFO: SPSR = 0x8
9719 11:52:19.961550
9720 11:52:19.961634
9721 11:52:19.961721
9722 11:52:19.965186 Starting depthcharge on Spherion...
9723 11:52:19.965271
9724 11:52:19.965357 Wipe memory regions:
9725 11:52:19.965439
9726 11:52:19.966247 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9727 11:52:19.966382 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9728 11:52:19.966596 Setting prompt string to ['asurada:']
9729 11:52:19.966727 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9730 11:52:19.968212 [0x00000040000000, 0x00000054600000)
9731 11:52:20.090526
9732 11:52:20.090641 [0x00000054660000, 0x00000080000000)
9733 11:52:20.350886
9734 11:52:20.351019 [0x000000821a7280, 0x000000ffe64000)
9735 11:52:21.095500
9736 11:52:21.095652 [0x00000100000000, 0x00000140000000)
9737 11:52:21.476685
9738 11:52:21.479709 Initializing XHCI USB controller at 0x11200000.
9739 11:52:22.517329
9740 11:52:22.520853 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9741 11:52:22.520944
9742 11:52:22.521030
9743 11:52:22.521111
9744 11:52:22.521431 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9746 11:52:22.621878 asurada: tftpboot 192.168.201.1 12066513/tftp-deploy-5ilml9ro/kernel/image.itb 12066513/tftp-deploy-5ilml9ro/kernel/cmdline
9747 11:52:22.622022 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9748 11:52:22.622135 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9749 11:52:22.626362 tftpboot 192.168.201.1 12066513/tftp-deploy-5ilml9ro/kernel/image.itp-deploy-5ilml9ro/kernel/cmdline
9750 11:52:22.626452
9751 11:52:22.626534 Waiting for link
9752 11:52:22.786680
9753 11:52:22.786804 R8152: Initializing
9754 11:52:22.786869
9755 11:52:22.790025 Version 9 (ocp_data = 6010)
9756 11:52:22.790165
9757 11:52:22.793272 R8152: Done initializing
9758 11:52:22.793351
9759 11:52:22.793413 Adding net device
9760 11:52:24.805567
9761 11:52:24.805708 done.
9762 11:52:24.805774
9763 11:52:24.805834 MAC: 00:e0:4c:68:03:bd
9764 11:52:24.805892
9765 11:52:24.808434 Sending DHCP discover... done.
9766 11:52:24.808572
9767 11:52:34.853394 Waiting for reply... R8152: Bulk read error 0xffffffbf
9768 11:52:34.853995
9769 11:52:34.856189 Receive failed.
9770 11:52:34.856747
9771 11:52:34.857241 done.
9772 11:52:34.857709
9773 11:52:34.859701 Sending DHCP request... done.
9774 11:52:34.860179
9775 11:52:34.862931 Waiting for reply... done.
9776 11:52:34.863421
9777 11:52:34.866310 My ip is 192.168.201.16
9778 11:52:34.866882
9779 11:52:34.869413 The DHCP server ip is 192.168.201.1
9780 11:52:34.869892
9781 11:52:34.872634 TFTP server IP predefined by user: 192.168.201.1
9782 11:52:34.873122
9783 11:52:34.879523 Bootfile predefined by user: 12066513/tftp-deploy-5ilml9ro/kernel/image.itb
9784 11:52:34.880099
9785 11:52:34.882872 Sending tftp read request... done.
9786 11:52:34.883351
9787 11:52:34.890816 Waiting for the transfer...
9788 11:52:34.891429
9789 11:52:35.296252 00000000 ################################################################
9790 11:52:35.296975
9791 11:52:35.665231 00080000 ################################################################
9792 11:52:35.665774
9793 11:52:36.022873 00100000 ################################################################
9794 11:52:36.023005
9795 11:52:36.316800 00180000 ################################################################
9796 11:52:36.316932
9797 11:52:36.577018 00200000 ################################################################
9798 11:52:36.577147
9799 11:52:36.859994 00280000 ################################################################
9800 11:52:36.860124
9801 11:52:37.155009 00300000 ################################################################
9802 11:52:37.155142
9803 11:52:37.455602 00380000 ################################################################
9804 11:52:37.455734
9805 11:52:37.758404 00400000 ################################################################
9806 11:52:37.758535
9807 11:52:38.052423 00480000 ################################################################
9808 11:52:38.052586
9809 11:52:38.329980 00500000 ################################################################
9810 11:52:38.330128
9811 11:52:38.586556 00580000 ################################################################
9812 11:52:38.586687
9813 11:52:38.841903 00600000 ################################################################
9814 11:52:38.842028
9815 11:52:39.116068 00680000 ################################################################
9816 11:52:39.116196
9817 11:52:39.418512 00700000 ################################################################
9818 11:52:39.418647
9819 11:52:39.768740 00780000 ################################################################
9820 11:52:39.769260
9821 11:52:40.181315 00800000 ################################################################
9822 11:52:40.181918
9823 11:52:40.617603 00880000 ################################################################
9824 11:52:40.618160
9825 11:52:41.006880 00900000 ################################################################
9826 11:52:41.007019
9827 11:52:41.309713 00980000 ################################################################
9828 11:52:41.309849
9829 11:52:41.649897 00a00000 ################################################################
9830 11:52:41.650062
9831 11:52:41.935175 00a80000 ################################################################
9832 11:52:41.935299
9833 11:52:42.225124 00b00000 ################################################################
9834 11:52:42.225258
9835 11:52:42.522794 00b80000 ################################################################
9836 11:52:42.522932
9837 11:52:42.818877 00c00000 ################################################################
9838 11:52:42.819020
9839 11:52:43.218771 00c80000 ################################################################
9840 11:52:43.219287
9841 11:52:43.626514 00d00000 ################################################################
9842 11:52:43.627064
9843 11:52:44.047400 00d80000 ################################################################
9844 11:52:44.048046
9845 11:52:44.437214 00e00000 ################################################################
9846 11:52:44.437785
9847 11:52:44.851647 00e80000 ################################################################
9848 11:52:44.852156
9849 11:52:45.271994 00f00000 ################################################################
9850 11:52:45.272592
9851 11:52:45.704939 00f80000 ################################################################
9852 11:52:45.705467
9853 11:52:46.034128 01000000 ################################################################
9854 11:52:46.034264
9855 11:52:46.337776 01080000 ################################################################
9856 11:52:46.337905
9857 11:52:46.641943 01100000 ################################################################
9858 11:52:46.642094
9859 11:52:46.944434 01180000 ################################################################
9860 11:52:46.944587
9861 11:52:47.246697 01200000 ################################################################
9862 11:52:47.246837
9863 11:52:47.548445 01280000 ################################################################
9864 11:52:47.548588
9865 11:52:47.835003 01300000 ################################################################
9866 11:52:47.835139
9867 11:52:48.122749 01380000 ################################################################
9868 11:52:48.122883
9869 11:52:48.418842 01400000 ################################################################
9870 11:52:48.418984
9871 11:52:48.718696 01480000 ################################################################
9872 11:52:48.718830
9873 11:52:49.021391 01500000 ################################################################
9874 11:52:49.021527
9875 11:52:49.323557 01580000 ################################################################
9876 11:52:49.323695
9877 11:52:49.614042 01600000 ################################################################
9878 11:52:49.614179
9879 11:52:49.911690 01680000 ################################################################
9880 11:52:49.911829
9881 11:52:50.204577 01700000 ################################################################
9882 11:52:50.204712
9883 11:52:50.604250 01780000 ################################################################
9884 11:52:50.604879
9885 11:52:51.004981 01800000 ################################################################
9886 11:52:51.005511
9887 11:52:51.392576 01880000 ################################################################
9888 11:52:51.393279
9889 11:52:51.707217 01900000 ################################################################
9890 11:52:51.707360
9891 11:52:52.004571 01980000 ################################################################
9892 11:52:52.004700
9893 11:52:52.303784 01a00000 ################################################################
9894 11:52:52.303918
9895 11:52:52.599734 01a80000 ################################################################
9896 11:52:52.599891
9897 11:52:52.892611 01b00000 ################################################################
9898 11:52:52.892747
9899 11:52:53.187874 01b80000 ################################################################
9900 11:52:53.188000
9901 11:52:53.477770 01c00000 ################################################################
9902 11:52:53.477892
9903 11:52:53.778116 01c80000 ################################################################
9904 11:52:53.778251
9905 11:52:54.080234 01d00000 ################################################################
9906 11:52:54.080393
9907 11:52:54.383120 01d80000 ################################################################
9908 11:52:54.383256
9909 11:52:54.686042 01e00000 ################################################################
9910 11:52:54.686165
9911 11:52:54.988011 01e80000 ################################################################
9912 11:52:54.988149
9913 11:52:55.289376 01f00000 ################################################################
9914 11:52:55.289511
9915 11:52:55.594200 01f80000 ################################################################
9916 11:52:55.594330
9917 11:52:55.896372 02000000 ################################################################
9918 11:52:55.896564
9919 11:52:56.186671 02080000 ################################################################
9920 11:52:56.186846
9921 11:52:56.470470 02100000 ################################################################
9922 11:52:56.470642
9923 11:52:56.743273 02180000 ################################################################
9924 11:52:56.743443
9925 11:52:57.029483 02200000 ################################################################
9926 11:52:57.029648
9927 11:52:57.308560 02280000 ################################################################
9928 11:52:57.308722
9929 11:52:57.585426 02300000 ################################################################
9930 11:52:57.585592
9931 11:52:57.863789 02380000 ################################################################
9932 11:52:57.863933
9933 11:52:58.129478 02400000 ################################################################
9934 11:52:58.129622
9935 11:52:58.431506 02480000 ################################################################
9936 11:52:58.431662
9937 11:52:58.733019 02500000 ################################################################
9938 11:52:58.733173
9939 11:52:59.006160 02580000 ################################################################
9940 11:52:59.006315
9941 11:52:59.269186 02600000 ################################################################
9942 11:52:59.269318
9943 11:52:59.547655 02680000 ################################################################
9944 11:52:59.547786
9945 11:52:59.854988 02700000 ################################################################
9946 11:52:59.855132
9947 11:53:00.204265 02780000 ################################################################
9948 11:53:00.204415
9949 11:53:00.554379 02800000 ################################################################
9950 11:53:00.554558
9951 11:53:00.879694 02880000 ################################################################
9952 11:53:00.879858
9953 11:53:01.195526 02900000 ################################################################
9954 11:53:01.195685
9955 11:53:01.457904 02980000 ################################################################
9956 11:53:01.458070
9957 11:53:01.719709 02a00000 ################################################################
9958 11:53:01.719869
9959 11:53:01.978174 02a80000 ################################################################
9960 11:53:01.978327
9961 11:53:02.259760 02b00000 ################################################################
9962 11:53:02.259937
9963 11:53:02.537023 02b80000 ################################################################
9964 11:53:02.537159
9965 11:53:02.819360 02c00000 ################################################################
9966 11:53:02.819492
9967 11:53:03.088330 02c80000 ################################################################
9968 11:53:03.088481
9969 11:53:03.372932 02d00000 ################################################################
9970 11:53:03.373078
9971 11:53:03.663152 02d80000 ################################################################
9972 11:53:03.663284
9973 11:53:03.940396 02e00000 ################################################################
9974 11:53:03.940574
9975 11:53:04.202189 02e80000 ################################################################
9976 11:53:04.202326
9977 11:53:04.495658 02f00000 ################################################################
9978 11:53:04.495797
9979 11:53:04.785423 02f80000 ################################################################
9980 11:53:04.785571
9981 11:53:05.060875 03000000 ################################################################
9982 11:53:05.061010
9983 11:53:05.327245 03080000 ################################################################
9984 11:53:05.327379
9985 11:53:05.578447 03100000 ################################################################
9986 11:53:05.578578
9987 11:53:05.855112 03180000 ################################################################
9988 11:53:05.855248
9989 11:53:06.135735 03200000 ################################################################
9990 11:53:06.135869
9991 11:53:06.412750 03280000 ################################################################
9992 11:53:06.412905
9993 11:53:06.663869 03300000 ################################################################
9994 11:53:06.664001
9995 11:53:06.925102 03380000 ################################################################
9996 11:53:06.925238
9997 11:53:07.226282 03400000 ################################################################
9998 11:53:07.226415
9999 11:53:07.529016 03480000 ################################################################
10000 11:53:07.529153
10001 11:53:07.822069 03500000 ################################################################
10002 11:53:07.822197
10003 11:53:08.149443 03580000 ################################################################
10004 11:53:08.149589
10005 11:53:08.416443 03600000 ################################################################
10006 11:53:08.416637
10007 11:53:08.706913 03680000 ################################################################
10008 11:53:08.707062
10009 11:53:08.975129 03700000 ################################################################
10010 11:53:08.975275
10011 11:53:09.268835 03780000 ################################################################
10012 11:53:09.269009
10013 11:53:09.576397 03800000 ################################################################
10014 11:53:09.576609
10015 11:53:09.868073 03880000 ################################################################
10016 11:53:09.868247
10017 11:53:10.170598 03900000 ################################################################
10018 11:53:10.170775
10019 11:53:10.494137 03980000 ################################################################
10020 11:53:10.494278
10021 11:53:10.830751 03a00000 ################################################################
10022 11:53:10.830931
10023 11:53:11.166192 03a80000 ################################################################
10024 11:53:11.166338
10025 11:53:11.498536 03b00000 ################################################################
10026 11:53:11.498684
10027 11:53:11.805198 03b80000 ################################################################
10028 11:53:11.805343
10029 11:53:12.115084 03c00000 ################################################################
10030 11:53:12.115254
10031 11:53:12.421117 03c80000 ################################################################
10032 11:53:12.421277
10033 11:53:12.777929 03d00000 ################################################################
10034 11:53:12.778079
10035 11:53:13.080622 03d80000 ################################################################
10036 11:53:13.080773
10037 11:53:13.369027 03e00000 ################################################################
10038 11:53:13.369169
10039 11:53:13.651792 03e80000 ################################################################
10040 11:53:13.651920
10041 11:53:13.927979 03f00000 ################################################################
10042 11:53:13.928145
10043 11:53:14.189691 03f80000 ################################################################
10044 11:53:14.189827
10045 11:53:14.413249 04000000 #################################################### done.
10046 11:53:14.413391
10047 11:53:14.416472 The bootfile was 67528058 bytes long.
10048 11:53:14.416572
10049 11:53:14.420089 Sending tftp read request... done.
10050 11:53:14.420255
10051 11:53:14.423404 Waiting for the transfer...
10052 11:53:14.423577
10053 11:53:14.423663 00000000 # done.
10054 11:53:14.423744
10055 11:53:14.433112 Command line loaded dynamically from TFTP file: 12066513/tftp-deploy-5ilml9ro/kernel/cmdline
10056 11:53:14.433306
10057 11:53:14.446892 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10058 11:53:14.447142
10059 11:53:14.447277 Loading FIT.
10060 11:53:14.447398
10061 11:53:14.450036 Image ramdisk-1 has 56431561 bytes.
10062 11:53:14.450273
10063 11:53:14.453052 Image fdt-1 has 47278 bytes.
10064 11:53:14.453316
10065 11:53:14.456679 Image kernel-1 has 11047184 bytes.
10066 11:53:14.456972
10067 11:53:14.463337 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
10068 11:53:14.463678
10069 11:53:14.483386 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10070 11:53:14.483985
10071 11:53:14.486701 Choosing best match conf-1 for compat google,spherion.
10072 11:53:14.491339
10073 11:53:14.495498 Connected to device vid:did:rid of 1ae0:0028:00
10074 11:53:14.502298
10075 11:53:14.505809 tpm_get_response: command 0x17b, return code 0x0
10076 11:53:14.506522
10077 11:53:14.509081 ec_init: CrosEC protocol v3 supported (256, 248)
10078 11:53:14.513145
10079 11:53:14.516273 tpm_cleanup: add release locality here.
10080 11:53:14.516782
10081 11:53:14.517159 Shutting down all USB controllers.
10082 11:53:14.519615
10083 11:53:14.520078 Removing current net device
10084 11:53:14.520446
10085 11:53:14.526238 Exiting depthcharge with code 4 at timestamp: 82749312
10086 11:53:14.526705
10087 11:53:14.529923 LZMA decompressing kernel-1 to 0x821a6718
10088 11:53:14.530493
10089 11:53:14.532796 LZMA decompressing kernel-1 to 0x40000000
10090 11:53:15.920869
10091 11:53:15.921417 jumping to kernel
10092 11:53:15.923538 end: 2.2.4 bootloader-commands (duration 00:00:56) [common]
10093 11:53:15.924083 start: 2.2.5 auto-login-action (timeout 00:03:30) [common]
10094 11:53:15.924541 Setting prompt string to ['Linux version [0-9]']
10095 11:53:15.924949 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 11:53:15.925329 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10097 11:53:15.971020
10098 11:53:15.974126 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10099 11:53:15.978002 start: 2.2.5.1 login-action (timeout 00:03:30) [common]
10100 11:53:15.978572 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10101 11:53:15.979041 Setting prompt string to []
10102 11:53:15.979521 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10103 11:53:15.979941 Using line separator: #'\n'#
10104 11:53:15.980318 No login prompt set.
10105 11:53:15.980738 Parsing kernel messages
10106 11:53:15.981058 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10107 11:53:15.981614 [login-action] Waiting for messages, (timeout 00:03:30)
10108 11:53:15.997073 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10109 11:53:16.000903 [ 0.000000] random: crng init done
10110 11:53:16.007352 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10111 11:53:16.010586 [ 0.000000] efi: UEFI not found.
10112 11:53:16.017135 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10113 11:53:16.023504 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10114 11:53:16.033376 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10115 11:53:16.043550 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10116 11:53:16.049684 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10117 11:53:16.056615 [ 0.000000] printk: bootconsole [mtk8250] enabled
10118 11:53:16.063403 [ 0.000000] NUMA: No NUMA configuration found
10119 11:53:16.069785 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10120 11:53:16.073194 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10121 11:53:16.076420 [ 0.000000] Zone ranges:
10122 11:53:16.082997 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10123 11:53:16.086399 [ 0.000000] DMA32 empty
10124 11:53:16.092972 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10125 11:53:16.096391 [ 0.000000] Movable zone start for each node
10126 11:53:16.099533 [ 0.000000] Early memory node ranges
10127 11:53:16.106410 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10128 11:53:16.112754 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10129 11:53:16.119327 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10130 11:53:16.125843 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10131 11:53:16.132495 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10132 11:53:16.139153 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10133 11:53:16.168703 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10134 11:53:16.175617 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10135 11:53:16.181935 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10136 11:53:16.185480 [ 0.000000] psci: probing for conduit method from DT.
10137 11:53:16.191934 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10138 11:53:16.195267 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10139 11:53:16.201901 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10140 11:53:16.204901 [ 0.000000] psci: SMC Calling Convention v1.2
10141 11:53:16.212081 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10142 11:53:16.215107 [ 0.000000] Detected VIPT I-cache on CPU0
10143 11:53:16.221393 [ 0.000000] CPU features: detected: GIC system register CPU interface
10144 11:53:16.228167 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10145 11:53:16.234981 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10146 11:53:16.241206 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10147 11:53:16.251568 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10148 11:53:16.257897 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10149 11:53:16.261226 [ 0.000000] alternatives: applying boot alternatives
10150 11:53:16.267732 [ 0.000000] Fallback order for Node 0: 0
10151 11:53:16.274311 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10152 11:53:16.277745 [ 0.000000] Policy zone: Normal
10153 11:53:16.290699 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10154 11:53:16.301089 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10155 11:53:16.312035 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10156 11:53:16.321647 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10157 11:53:16.328434 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10158 11:53:16.331601 <6>[ 0.000000] software IO TLB: area num 8.
10159 11:53:16.387189 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10160 11:53:16.467320 <6>[ 0.000000] Memory: 3800096K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 358368K reserved, 32768K cma-reserved)
10161 11:53:16.473740 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10162 11:53:16.480826 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10163 11:53:16.483885 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10164 11:53:16.490301 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10165 11:53:16.497007 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10166 11:53:16.500203 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10167 11:53:16.509715 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10168 11:53:16.516774 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10169 11:53:16.523199 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10170 11:53:16.530017 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10171 11:53:16.533219 <6>[ 0.000000] GICv3: 608 SPIs implemented
10172 11:53:16.536822 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10173 11:53:16.543410 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10174 11:53:16.546618 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10175 11:53:16.553039 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10176 11:53:16.566614 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10177 11:53:16.579637 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10178 11:53:16.586375 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10179 11:53:16.594358 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10180 11:53:16.607340 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10181 11:53:16.613668 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10182 11:53:16.620761 <6>[ 0.009230] Console: colour dummy device 80x25
10183 11:53:16.630113 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10184 11:53:16.636800 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10185 11:53:16.640277 <6>[ 0.029270] LSM: Security Framework initializing
10186 11:53:16.646699 <6>[ 0.034213] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10187 11:53:16.656964 <6>[ 0.041819] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10188 11:53:16.663340 <6>[ 0.051048] cblist_init_generic: Setting adjustable number of callback queues.
10189 11:53:16.669784 <6>[ 0.058535] cblist_init_generic: Setting shift to 3 and lim to 1.
10190 11:53:16.679598 <6>[ 0.064872] cblist_init_generic: Setting adjustable number of callback queues.
10191 11:53:16.683283 <6>[ 0.072299] cblist_init_generic: Setting shift to 3 and lim to 1.
10192 11:53:16.689891 <6>[ 0.078737] rcu: Hierarchical SRCU implementation.
10193 11:53:16.696548 <6>[ 0.083751] rcu: Max phase no-delay instances is 1000.
10194 11:53:16.702993 <6>[ 0.090759] EFI services will not be available.
10195 11:53:16.705974 <6>[ 0.095712] smp: Bringing up secondary CPUs ...
10196 11:53:16.714092 <6>[ 0.100784] Detected VIPT I-cache on CPU1
10197 11:53:16.720892 <6>[ 0.100851] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10198 11:53:16.727633 <6>[ 0.100883] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10199 11:53:16.730930 <6>[ 0.101218] Detected VIPT I-cache on CPU2
10200 11:53:16.737233 <6>[ 0.101267] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10201 11:53:16.747453 <6>[ 0.101283] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10202 11:53:16.750596 <6>[ 0.101543] Detected VIPT I-cache on CPU3
10203 11:53:16.757225 <6>[ 0.101588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10204 11:53:16.763679 <6>[ 0.101601] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10205 11:53:16.767228 <6>[ 0.101904] CPU features: detected: Spectre-v4
10206 11:53:16.773564 <6>[ 0.101911] CPU features: detected: Spectre-BHB
10207 11:53:16.776973 <6>[ 0.101915] Detected PIPT I-cache on CPU4
10208 11:53:16.783745 <6>[ 0.101972] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10209 11:53:16.790043 <6>[ 0.101988] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10210 11:53:16.797396 <6>[ 0.102281] Detected PIPT I-cache on CPU5
10211 11:53:16.803304 <6>[ 0.102342] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10212 11:53:16.809724 <6>[ 0.102358] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10213 11:53:16.812997 <6>[ 0.102637] Detected PIPT I-cache on CPU6
10214 11:53:16.822944 <6>[ 0.102697] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10215 11:53:16.829409 <6>[ 0.102713] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10216 11:53:16.832917 <6>[ 0.103009] Detected PIPT I-cache on CPU7
10217 11:53:16.839580 <6>[ 0.103073] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10218 11:53:16.846295 <6>[ 0.103089] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10219 11:53:16.849216 <6>[ 0.103136] smp: Brought up 1 node, 8 CPUs
10220 11:53:16.856215 <6>[ 0.244557] SMP: Total of 8 processors activated.
10221 11:53:16.862691 <6>[ 0.249477] CPU features: detected: 32-bit EL0 Support
10222 11:53:16.869232 <6>[ 0.254840] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10223 11:53:16.875918 <6>[ 0.263640] CPU features: detected: Common not Private translations
10224 11:53:16.882248 <6>[ 0.270116] CPU features: detected: CRC32 instructions
10225 11:53:16.889080 <6>[ 0.275500] CPU features: detected: RCpc load-acquire (LDAPR)
10226 11:53:16.892398 <6>[ 0.281460] CPU features: detected: LSE atomic instructions
10227 11:53:16.898770 <6>[ 0.287241] CPU features: detected: Privileged Access Never
10228 11:53:16.905447 <6>[ 0.293021] CPU features: detected: RAS Extension Support
10229 11:53:16.912234 <6>[ 0.298665] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10230 11:53:16.915572 <6>[ 0.305927] CPU: All CPU(s) started at EL2
10231 11:53:16.921883 <6>[ 0.310244] alternatives: applying system-wide alternatives
10232 11:53:16.931165 <6>[ 0.320150] devtmpfs: initialized
10233 11:53:16.942890 <6>[ 0.328324] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10234 11:53:16.952636 <6>[ 0.338284] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10235 11:53:16.959462 <6>[ 0.346462] pinctrl core: initialized pinctrl subsystem
10236 11:53:16.962405 <6>[ 0.353127] DMI not present or invalid.
10237 11:53:16.969257 <6>[ 0.357445] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10238 11:53:16.978957 <6>[ 0.364312] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10239 11:53:16.985739 <6>[ 0.371760] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10240 11:53:16.995321 <6>[ 0.379851] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10241 11:53:16.998921 <6>[ 0.388007] audit: initializing netlink subsys (disabled)
10242 11:53:17.008780 <5>[ 0.393702] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10243 11:53:17.015749 <6>[ 0.394391] thermal_sys: Registered thermal governor 'step_wise'
10244 11:53:17.022100 <6>[ 0.401669] thermal_sys: Registered thermal governor 'power_allocator'
10245 11:53:17.025318 <6>[ 0.407924] cpuidle: using governor menu
10246 11:53:17.031699 <6>[ 0.418877] NET: Registered PF_QIPCRTR protocol family
10247 11:53:17.038469 <6>[ 0.424330] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10248 11:53:17.041877 <6>[ 0.431433] ASID allocator initialised with 32768 entries
10249 11:53:17.048946 <6>[ 0.437980] Serial: AMBA PL011 UART driver
10250 11:53:17.057797 <4>[ 0.446765] Trying to register duplicate clock ID: 134
10251 11:53:17.112269 <6>[ 0.504479] KASLR enabled
10252 11:53:17.126284 <6>[ 0.512171] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10253 11:53:17.133126 <6>[ 0.519183] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10254 11:53:17.139981 <6>[ 0.525673] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10255 11:53:17.146272 <6>[ 0.532679] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10256 11:53:17.153260 <6>[ 0.539168] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10257 11:53:17.159547 <6>[ 0.546170] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10258 11:53:17.166069 <6>[ 0.552659] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10259 11:53:17.172793 <6>[ 0.559661] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10260 11:53:17.176037 <6>[ 0.567139] ACPI: Interpreter disabled.
10261 11:53:17.184460 <6>[ 0.573531] iommu: Default domain type: Translated
10262 11:53:17.191546 <6>[ 0.578644] iommu: DMA domain TLB invalidation policy: strict mode
10263 11:53:17.194595 <5>[ 0.585299] SCSI subsystem initialized
10264 11:53:17.201154 <6>[ 0.589462] usbcore: registered new interface driver usbfs
10265 11:53:17.207494 <6>[ 0.595195] usbcore: registered new interface driver hub
10266 11:53:17.210812 <6>[ 0.600747] usbcore: registered new device driver usb
10267 11:53:17.217815 <6>[ 0.606838] pps_core: LinuxPPS API ver. 1 registered
10268 11:53:17.228105 <6>[ 0.612031] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10269 11:53:17.231155 <6>[ 0.621380] PTP clock support registered
10270 11:53:17.234033 <6>[ 0.625615] EDAC MC: Ver: 3.0.0
10271 11:53:17.241880 <6>[ 0.630765] FPGA manager framework
10272 11:53:17.248651 <6>[ 0.634444] Advanced Linux Sound Architecture Driver Initialized.
10273 11:53:17.251624 <6>[ 0.641209] vgaarb: loaded
10274 11:53:17.258502 <6>[ 0.644371] clocksource: Switched to clocksource arch_sys_counter
10275 11:53:17.261956 <5>[ 0.650800] VFS: Disk quotas dquot_6.6.0
10276 11:53:17.268196 <6>[ 0.654982] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10277 11:53:17.271457 <6>[ 0.662168] pnp: PnP ACPI: disabled
10278 11:53:17.280043 <6>[ 0.668801] NET: Registered PF_INET protocol family
10279 11:53:17.286325 <6>[ 0.674169] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10280 11:53:17.298756 <6>[ 0.684174] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10281 11:53:17.308436 <6>[ 0.692962] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10282 11:53:17.314945 <6>[ 0.700927] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10283 11:53:17.321460 <6>[ 0.709317] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10284 11:53:17.332430 <6>[ 0.717977] TCP: Hash tables configured (established 32768 bind 32768)
10285 11:53:17.339056 <6>[ 0.724822] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10286 11:53:17.345356 <6>[ 0.731842] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10287 11:53:17.352127 <6>[ 0.739348] NET: Registered PF_UNIX/PF_LOCAL protocol family
10288 11:53:17.359122 <6>[ 0.745465] RPC: Registered named UNIX socket transport module.
10289 11:53:17.361762 <6>[ 0.751619] RPC: Registered udp transport module.
10290 11:53:17.368702 <6>[ 0.756551] RPC: Registered tcp transport module.
10291 11:53:17.375691 <6>[ 0.761480] RPC: Registered tcp NFSv4.1 backchannel transport module.
10292 11:53:17.378681 <6>[ 0.768148] PCI: CLS 0 bytes, default 64
10293 11:53:17.381638 <6>[ 0.772589] Unpacking initramfs...
10294 11:53:17.392114 <6>[ 0.776294] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10295 11:53:17.398369 <6>[ 0.784918] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10296 11:53:17.405065 <6>[ 0.793744] kvm [1]: IPA Size Limit: 40 bits
10297 11:53:17.408452 <6>[ 0.798266] kvm [1]: GICv3: no GICV resource entry
10298 11:53:17.414887 <6>[ 0.803290] kvm [1]: disabling GICv2 emulation
10299 11:53:17.421322 <6>[ 0.807975] kvm [1]: GIC system register CPU interface enabled
10300 11:53:17.424974 <6>[ 0.814135] kvm [1]: vgic interrupt IRQ18
10301 11:53:17.431637 <6>[ 0.818495] kvm [1]: VHE mode initialized successfully
10302 11:53:17.434948 <5>[ 0.824811] Initialise system trusted keyrings
10303 11:53:17.441445 <6>[ 0.829608] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10304 11:53:17.450413 <6>[ 0.839574] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10305 11:53:17.457423 <5>[ 0.845957] NFS: Registering the id_resolver key type
10306 11:53:17.460908 <5>[ 0.851257] Key type id_resolver registered
10307 11:53:17.467389 <5>[ 0.855671] Key type id_legacy registered
10308 11:53:17.474159 <6>[ 0.859948] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10309 11:53:17.480464 <6>[ 0.866871] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10310 11:53:17.487156 <6>[ 0.874629] 9p: Installing v9fs 9p2000 file system support
10311 11:53:17.524114 <5>[ 0.913080] Key type asymmetric registered
10312 11:53:17.527695 <5>[ 0.917411] Asymmetric key parser 'x509' registered
10313 11:53:17.537478 <6>[ 0.922558] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10314 11:53:17.540781 <6>[ 0.930170] io scheduler mq-deadline registered
10315 11:53:17.544289 <6>[ 0.934931] io scheduler kyber registered
10316 11:53:17.563558 <6>[ 0.952288] EINJ: ACPI disabled.
10317 11:53:17.595806 <4>[ 0.977954] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10318 11:53:17.605211 <4>[ 0.988580] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10319 11:53:17.620830 <6>[ 1.009331] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10320 11:53:17.628362 <6>[ 1.017365] printk: console [ttyS0] disabled
10321 11:53:17.656317 <6>[ 1.042014] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10322 11:53:17.663256 <6>[ 1.051502] printk: console [ttyS0] enabled
10323 11:53:17.666247 <6>[ 1.051502] printk: console [ttyS0] enabled
10324 11:53:17.672963 <6>[ 1.060397] printk: bootconsole [mtk8250] disabled
10325 11:53:17.676244 <6>[ 1.060397] printk: bootconsole [mtk8250] disabled
10326 11:53:17.682505 <6>[ 1.071639] SuperH (H)SCI(F) driver initialized
10327 11:53:17.686414 <6>[ 1.076915] msm_serial: driver initialized
10328 11:53:17.700174 <6>[ 1.085901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10329 11:53:17.710094 <6>[ 1.094446] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10330 11:53:17.717074 <6>[ 1.102990] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10331 11:53:17.726649 <6>[ 1.111619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10332 11:53:17.736571 <6>[ 1.120326] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10333 11:53:17.743151 <6>[ 1.129045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10334 11:53:17.752948 <6>[ 1.137587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10335 11:53:17.760057 <6>[ 1.146396] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10336 11:53:17.769813 <6>[ 1.154941] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10337 11:53:17.781512 <6>[ 1.170464] loop: module loaded
10338 11:53:17.788255 <6>[ 1.176442] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10339 11:53:17.810601 <4>[ 1.199643] mtk-pmic-keys: Failed to locate of_node [id: -1]
10340 11:53:17.817426 <6>[ 1.206505] megasas: 07.719.03.00-rc1
10341 11:53:17.826993 <6>[ 1.216017] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10342 11:53:17.834963 <6>[ 1.223751] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10343 11:53:17.851221 <6>[ 1.240009] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10344 11:53:17.906651 <6>[ 1.289173] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10345 11:53:19.783974 <6>[ 3.173143] Freeing initrd memory: 55108K
10346 11:53:19.794439 <6>[ 3.183831] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10347 11:53:19.806028 <6>[ 3.194762] tun: Universal TUN/TAP device driver, 1.6
10348 11:53:19.808939 <6>[ 3.200832] thunder_xcv, ver 1.0
10349 11:53:19.812333 <6>[ 3.204330] thunder_bgx, ver 1.0
10350 11:53:19.815637 <6>[ 3.207826] nicpf, ver 1.0
10351 11:53:19.826149 <6>[ 3.211832] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10352 11:53:19.829307 <6>[ 3.219308] hns3: Copyright (c) 2017 Huawei Corporation.
10353 11:53:19.835900 <6>[ 3.224898] hclge is initializing
10354 11:53:19.839167 <6>[ 3.228477] e1000: Intel(R) PRO/1000 Network Driver
10355 11:53:19.845676 <6>[ 3.233607] e1000: Copyright (c) 1999-2006 Intel Corporation.
10356 11:53:19.848967 <6>[ 3.239618] e1000e: Intel(R) PRO/1000 Network Driver
10357 11:53:19.855696 <6>[ 3.244834] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10358 11:53:19.862617 <6>[ 3.251019] igb: Intel(R) Gigabit Ethernet Network Driver
10359 11:53:19.868956 <6>[ 3.256669] igb: Copyright (c) 2007-2014 Intel Corporation.
10360 11:53:19.875368 <6>[ 3.262503] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10361 11:53:19.882136 <6>[ 3.269022] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10362 11:53:19.885279 <6>[ 3.275487] sky2: driver version 1.30
10363 11:53:19.892257 <6>[ 3.280477] VFIO - User Level meta-driver version: 0.3
10364 11:53:19.899417 <6>[ 3.288727] usbcore: registered new interface driver usb-storage
10365 11:53:19.906266 <6>[ 3.295173] usbcore: registered new device driver onboard-usb-hub
10366 11:53:19.915264 <6>[ 3.304290] mt6397-rtc mt6359-rtc: registered as rtc0
10367 11:53:19.925149 <6>[ 3.309757] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:53:21 UTC (1700740401)
10368 11:53:19.928089 <6>[ 3.319319] i2c_dev: i2c /dev entries driver
10369 11:53:19.945065 <6>[ 3.331061] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10370 11:53:19.964869 <6>[ 3.354044] cpu cpu0: EM: created perf domain
10371 11:53:19.968204 <6>[ 3.358955] cpu cpu4: EM: created perf domain
10372 11:53:19.975413 <6>[ 3.364471] sdhci: Secure Digital Host Controller Interface driver
10373 11:53:19.981915 <6>[ 3.370900] sdhci: Copyright(c) Pierre Ossman
10374 11:53:19.988724 <6>[ 3.375836] Synopsys Designware Multimedia Card Interface Driver
10375 11:53:19.995135 <6>[ 3.382436] sdhci-pltfm: SDHCI platform and OF driver helper
10376 11:53:19.998222 <6>[ 3.382487] mmc0: CQHCI version 5.10
10377 11:53:20.004853 <6>[ 3.392382] ledtrig-cpu: registered to indicate activity on CPUs
10378 11:53:20.011557 <6>[ 3.399329] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10379 11:53:20.018421 <6>[ 3.406351] usbcore: registered new interface driver usbhid
10380 11:53:20.021495 <6>[ 3.412175] usbhid: USB HID core driver
10381 11:53:20.027729 <6>[ 3.416371] spi_master spi0: will run message pump with realtime priority
10382 11:53:20.072583 <6>[ 3.455004] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10383 11:53:20.091542 <6>[ 3.471074] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10384 11:53:20.095298 <6>[ 3.484716] mmc0: Command Queue Engine enabled
10385 11:53:20.101820 <6>[ 3.489485] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10386 11:53:20.108462 <6>[ 3.496773] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10387 11:53:20.111821 <6>[ 3.501689] cros-ec-spi spi0.0: Chrome EC device registered
10388 11:53:20.118313 <6>[ 3.505531] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10389 11:53:20.126021 <6>[ 3.515290] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10390 11:53:20.132381 <6>[ 3.521227] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10391 11:53:20.139192 <6>[ 3.527361] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10392 11:53:20.157324 <6>[ 3.543281] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10393 11:53:20.165042 <6>[ 3.554036] NET: Registered PF_PACKET protocol family
10394 11:53:20.168345 <6>[ 3.559422] 9pnet: Installing 9P2000 support
10395 11:53:20.174694 <5>[ 3.563985] Key type dns_resolver registered
10396 11:53:20.178207 <6>[ 3.568966] registered taskstats version 1
10397 11:53:20.185038 <5>[ 3.573346] Loading compiled-in X.509 certificates
10398 11:53:20.214339 <4>[ 3.597016] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10399 11:53:20.224286 <4>[ 3.607781] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10400 11:53:20.231075 <3>[ 3.618324] debugfs: File 'uA_load' in directory '/' already present!
10401 11:53:20.237953 <3>[ 3.625025] debugfs: File 'min_uV' in directory '/' already present!
10402 11:53:20.244678 <3>[ 3.631631] debugfs: File 'max_uV' in directory '/' already present!
10403 11:53:20.251353 <3>[ 3.638238] debugfs: File 'constraint_flags' in directory '/' already present!
10404 11:53:20.262056 <3>[ 3.647912] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10405 11:53:20.270889 <6>[ 3.659935] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10406 11:53:20.277360 <6>[ 3.666717] xhci-mtk 11200000.usb: xHCI Host Controller
10407 11:53:20.284412 <6>[ 3.672234] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10408 11:53:20.294139 <6>[ 3.680083] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10409 11:53:20.301151 <6>[ 3.689512] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10410 11:53:20.307285 <6>[ 3.695576] xhci-mtk 11200000.usb: xHCI Host Controller
10411 11:53:20.313829 <6>[ 3.701052] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10412 11:53:20.320556 <6>[ 3.708702] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10413 11:53:20.327039 <6>[ 3.716381] hub 1-0:1.0: USB hub found
10414 11:53:20.330442 <6>[ 3.720388] hub 1-0:1.0: 1 port detected
10415 11:53:20.340302 <6>[ 3.724639] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10416 11:53:20.343522 <6>[ 3.733199] hub 2-0:1.0: USB hub found
10417 11:53:20.346677 <6>[ 3.737202] hub 2-0:1.0: 1 port detected
10418 11:53:20.355598 <6>[ 3.744662] mtk-msdc 11f70000.mmc: Got CD GPIO
10419 11:53:20.365346 <6>[ 3.750706] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10420 11:53:20.372294 <6>[ 3.758727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10421 11:53:20.381814 <4>[ 3.766616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10422 11:53:20.388606 <6>[ 3.776130] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10423 11:53:20.398561 <6>[ 3.784206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10424 11:53:20.405207 <6>[ 3.792284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10425 11:53:20.415051 <6>[ 3.800208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10426 11:53:20.421782 <6>[ 3.808083] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10427 11:53:20.431727 <6>[ 3.815906] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10428 11:53:20.441949 <6>[ 3.826278] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10429 11:53:20.448258 <6>[ 3.834629] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10430 11:53:20.457915 <6>[ 3.842993] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10431 11:53:20.464671 <6>[ 3.851334] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10432 11:53:20.474597 <6>[ 3.859684] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10433 11:53:20.481188 <6>[ 3.868023] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10434 11:53:20.491111 <6>[ 3.876371] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10435 11:53:20.497721 <6>[ 3.884710] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10436 11:53:20.507427 <6>[ 3.893056] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10437 11:53:20.513967 <6>[ 3.901396] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10438 11:53:20.524025 <6>[ 3.909742] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10439 11:53:20.530812 <6>[ 3.918080] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10440 11:53:20.540410 <6>[ 3.926417] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10441 11:53:20.550353 <6>[ 3.934756] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10442 11:53:20.557063 <6>[ 3.943094] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10443 11:53:20.563835 <6>[ 3.951841] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10444 11:53:20.570032 <6>[ 3.958969] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10445 11:53:20.576769 <6>[ 3.965702] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10446 11:53:20.583311 <6>[ 3.972432] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10447 11:53:20.593505 <6>[ 3.979336] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10448 11:53:20.599703 <6>[ 3.986186] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10449 11:53:20.609897 <6>[ 3.995310] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10450 11:53:20.619941 <6>[ 4.004428] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10451 11:53:20.629627 <6>[ 4.013720] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10452 11:53:20.639704 <6>[ 4.023233] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10453 11:53:20.646083 <6>[ 4.032786] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10454 11:53:20.656241 <6>[ 4.041908] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10455 11:53:20.665706 <6>[ 4.051374] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10456 11:53:20.675978 <6>[ 4.060491] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10457 11:53:20.685573 <6>[ 4.069785] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10458 11:53:20.695744 <6>[ 4.079945] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10459 11:53:20.705688 <6>[ 4.091481] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10460 11:53:20.774908 <6>[ 4.160638] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10461 11:53:20.928949 <6>[ 4.318363] hub 1-1:1.0: USB hub found
10462 11:53:20.932358 <6>[ 4.322867] hub 1-1:1.0: 4 ports detected
10463 11:53:20.941324 <6>[ 4.330695] hub 1-1:1.0: USB hub found
10464 11:53:20.944396 <6>[ 4.335001] hub 1-1:1.0: 4 ports detected
10465 11:53:21.054892 <6>[ 4.440994] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10466 11:53:21.081139 <6>[ 4.470345] hub 2-1:1.0: USB hub found
10467 11:53:21.084240 <6>[ 4.474843] hub 2-1:1.0: 3 ports detected
10468 11:53:21.093286 <6>[ 4.482722] hub 2-1:1.0: USB hub found
10469 11:53:21.096575 <6>[ 4.487171] hub 2-1:1.0: 3 ports detected
10470 11:53:21.270954 <6>[ 4.656663] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10471 11:53:21.403115 <6>[ 4.792289] hub 1-1.4:1.0: USB hub found
10472 11:53:21.406391 <6>[ 4.796959] hub 1-1.4:1.0: 2 ports detected
10473 11:53:21.414960 <6>[ 4.804304] hub 1-1.4:1.0: USB hub found
10474 11:53:21.418014 <6>[ 4.808909] hub 1-1.4:1.0: 2 ports detected
10475 11:53:21.482701 <6>[ 4.868816] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10476 11:53:21.714624 <6>[ 5.100734] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10477 11:53:21.906859 <6>[ 5.292655] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10478 11:53:33.003375 <6>[ 16.397664] ALSA device list:
10479 11:53:33.010441 <6>[ 16.400959] No soundcards found.
10480 11:53:33.018098 <6>[ 16.408815] Freeing unused kernel memory: 8384K
10481 11:53:33.021148 <6>[ 16.413790] Run /init as init process
10482 11:53:33.069799 <6>[ 16.460444] NET: Registered PF_INET6 protocol family
10483 11:53:33.076832 <6>[ 16.467059] Segment Routing with IPv6
10484 11:53:33.079716 <6>[ 16.471086] In-situ OAM (IOAM) with IPv6
10485 11:53:33.113701 <30>[ 16.484405] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10486 11:53:33.116827 <30>[ 16.508193] systemd[1]: Detected architecture arm64.
10487 11:53:33.117387
10488 11:53:33.122884 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10489 11:53:33.123345
10490 11:53:33.138216 <30>[ 16.528659] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10491 11:53:33.260000 <30>[ 16.647241] systemd[1]: Queued start job for default target Graphical Interface.
10492 11:53:33.294612 <30>[ 16.685343] systemd[1]: Created slice system-getty.slice.
10493 11:53:33.301191 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10494 11:53:33.318194 <30>[ 16.708928] systemd[1]: Created slice system-modprobe.slice.
10495 11:53:33.324598 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10496 11:53:33.342555 <30>[ 16.733227] systemd[1]: Created slice system-serial\x2dgetty.slice.
10497 11:53:33.352388 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10498 11:53:33.366938 <30>[ 16.757647] systemd[1]: Created slice User and Session Slice.
10499 11:53:33.373471 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10500 11:53:33.393481 <30>[ 16.781208] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10501 11:53:33.403628 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10502 11:53:33.421360 <30>[ 16.808815] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10503 11:53:33.427920 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10504 11:53:33.448642 <30>[ 16.832570] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10505 11:53:33.455063 <30>[ 16.844635] systemd[1]: Reached target Local Encrypted Volumes.
10506 11:53:33.461309 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10507 11:53:33.478085 <30>[ 16.869035] systemd[1]: Reached target Paths.
10508 11:53:33.481661 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10509 11:53:33.497549 <30>[ 16.888650] systemd[1]: Reached target Remote File Systems.
10510 11:53:33.504148 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10511 11:53:33.518254 <30>[ 16.908713] systemd[1]: Reached target Slices.
10512 11:53:33.521412 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10513 11:53:33.538063 <30>[ 16.928672] systemd[1]: Reached target Swap.
10514 11:53:33.541126 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10515 11:53:33.561522 <30>[ 16.949085] systemd[1]: Listening on initctl Compatibility Named Pipe.
10516 11:53:33.568262 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10517 11:53:33.583418 <30>[ 16.974158] systemd[1]: Listening on Journal Audit Socket.
10518 11:53:33.590102 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10519 11:53:33.607112 <30>[ 16.997794] systemd[1]: Listening on Journal Socket (/dev/log).
10520 11:53:33.613496 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10521 11:53:33.630794 <30>[ 17.021837] systemd[1]: Listening on Journal Socket.
10522 11:53:33.637559 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10523 11:53:33.650479 <30>[ 17.041212] systemd[1]: Listening on udev Control Socket.
10524 11:53:33.657288 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10525 11:53:33.675072 <30>[ 17.065682] systemd[1]: Listening on udev Kernel Socket.
10526 11:53:33.681580 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10527 11:53:33.734043 <30>[ 17.124805] systemd[1]: Mounting Huge Pages File System...
10528 11:53:33.740957 Mounting [0;1;39mHuge Pages File System[0m...
10529 11:53:33.757296 <30>[ 17.148209] systemd[1]: Mounting POSIX Message Queue File System...
10530 11:53:33.764060 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10531 11:53:33.789903 <30>[ 17.180707] systemd[1]: Mounting Kernel Debug File System...
10532 11:53:33.796241 Mounting [0;1;39mKernel Debug File System[0m...
10533 11:53:33.817581 <30>[ 17.205188] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10534 11:53:33.831121 <30>[ 17.218675] systemd[1]: Starting Create list of static device nodes for the current kernel...
10535 11:53:33.838104 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10536 11:53:33.862599 <30>[ 17.253153] systemd[1]: Starting Load Kernel Module configfs...
10537 11:53:33.869219 Starting [0;1;39mLoad Kernel Module configfs[0m...
10538 11:53:33.890358 <30>[ 17.281194] systemd[1]: Starting Load Kernel Module drm...
10539 11:53:33.897162 Starting [0;1;39mLoad Kernel Module drm[0m...
10540 11:53:33.917466 <30>[ 17.305114] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10541 11:53:33.932415 <30>[ 17.322908] systemd[1]: Starting Journal Service...
10542 11:53:33.938633 Starting [0;1;39mJournal Service[0m...
10543 11:53:33.960089 <30>[ 17.350717] systemd[1]: Starting Load Kernel Modules...
10544 11:53:33.966414 Starting [0;1;39mLoad Kernel Modules[0m...
10545 11:53:33.994131 <30>[ 17.381198] systemd[1]: Starting Remount Root and Kernel File Systems...
10546 11:53:34.000428 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10547 11:53:34.021161 <30>[ 17.411843] systemd[1]: Starting Coldplug All udev Devices...
10548 11:53:34.027802 Starting [0;1;39mColdplug All udev Devices[0m...
10549 11:53:34.048662 <30>[ 17.439587] systemd[1]: Started Journal Service.
10550 11:53:34.055107 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10551 11:53:34.076646 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10552 11:53:34.095388 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10553 11:53:34.111208 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10554 11:53:34.134881 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10555 11:53:34.152837 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10556 11:53:34.176740 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10557 11:53:34.195935 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10558 11:53:34.220115 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10559 11:53:34.234026 See 'systemctl status systemd-remount-fs.service' for details.
10560 11:53:34.275829 Mounting [0;1;39mKernel Configuration File System[0m...
10561 11:53:34.293288 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10562 11:53:34.307304 <46>[ 17.694943] systemd-journald[181]: Received client request to flush runtime journal.
10563 11:53:34.317284 Starting [0;1;39mLoad/Save Random Seed[0m...
10564 11:53:34.338519 Starting [0;1;39mApply Kernel Variables[0m...
10565 11:53:34.359288 Starting [0;1;39mCreate System Users[0m...
10566 11:53:34.377905 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10567 11:53:34.400279 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10568 11:53:34.427170 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10569 11:53:34.443744 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10570 11:53:34.460250 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10571 11:53:34.479399 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10572 11:53:34.518650 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10573 11:53:34.547298 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10574 11:53:34.562483 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10575 11:53:34.578392 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10576 11:53:34.630503 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10577 11:53:34.655032 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10578 11:53:34.675901 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10579 11:53:34.696739 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10580 11:53:34.763299 Starting [0;1;39mNetwork Time Synchronization[0m...
10581 11:53:34.781401 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10582 11:53:34.822707 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<6>[ 18.210285] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10583 11:53:34.823348 .
10584 11:53:34.832906 <6>[ 18.220347] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10585 11:53:34.843505 <6>[ 18.229441] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10586 11:53:34.849299 <4>[ 18.230734] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10587 11:53:34.866186 <4>[ 18.253946] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10588 11:53:34.885071 <3>[ 18.272626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10589 11:53:34.891590 <3>[ 18.281027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10590 11:53:34.901816 <3>[ 18.289169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10591 11:53:34.908225 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10592 11:53:34.918316 <3>[ 18.305014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10593 11:53:34.921482 <6>[ 18.305103] mc: Linux media interface: v0.10
10594 11:53:34.931337 <3>[ 18.313186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10595 11:53:34.937816 <3>[ 18.313191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10596 11:53:34.948226 <3>[ 18.313196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10597 11:53:34.954275 <3>[ 18.313200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10598 11:53:34.960961 <3>[ 18.316199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 11:53:34.967588 <6>[ 18.317858] usbcore: registered new interface driver r8152
10600 11:53:34.977619 <3>[ 18.327651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10601 11:53:34.985207 <6>[ 18.340789] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10602 11:53:34.991622 <3>[ 18.342490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10603 11:53:34.998401 <6>[ 18.361883] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10604 11:53:35.008178 <3>[ 18.364558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10605 11:53:35.015421 <4>[ 18.365298] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10606 11:53:35.022720 <4>[ 18.365298] Fallback method does not support PEC.
10607 11:53:35.029205 <6>[ 18.368561] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10608 11:53:35.035843 <6>[ 18.372653] pci_bus 0000:00: root bus resource [bus 00-ff]
10609 11:53:35.045679 <3>[ 18.380388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 11:53:35.052602 <3>[ 18.381838] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 11:53:35.058785 <6>[ 18.388220] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10612 11:53:35.068904 <3>[ 18.395080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 11:53:35.075332 <3>[ 18.395090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 11:53:35.085412 <6>[ 18.403181] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10615 11:53:35.091957 <6>[ 18.403259] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10616 11:53:35.101847 <3>[ 18.416828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10617 11:53:35.108755 <3>[ 18.416831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10618 11:53:35.115522 <3>[ 18.416866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10619 11:53:35.125367 <6>[ 18.420665] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10620 11:53:35.132091 <6>[ 18.426299] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10621 11:53:35.141706 <6>[ 18.441066] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10622 11:53:35.145312 <6>[ 18.449181] pci 0000:00:00.0: supports D1 D2
10623 11:53:35.156214 <3>[ 18.449659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 11:53:35.162849 <3>[ 18.456656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10625 11:53:35.173580 <6>[ 18.456954] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10626 11:53:35.183760 <4>[ 18.460934] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10627 11:53:35.190737 <4>[ 18.460942] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10628 11:53:35.196969 <6>[ 18.464612] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10629 11:53:35.203593 <6>[ 18.466257] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10630 11:53:35.209973 <6>[ 18.473206] remoteproc remoteproc0: scp is available
10631 11:53:35.214069 <6>[ 18.474203] videodev: Linux video capture interface: v2.00
10632 11:53:35.221283 <6>[ 18.479575] usbcore: registered new interface driver cdc_ether
10633 11:53:35.227548 <6>[ 18.482829] usbcore: registered new interface driver r8153_ecm
10634 11:53:35.234497 <6>[ 18.483327] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10635 11:53:35.241353 <6>[ 18.483414] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10636 11:53:35.248745 <6>[ 18.483439] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10637 11:53:35.255531 <6>[ 18.483455] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10638 11:53:35.265397 <6>[ 18.483470] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10639 11:53:35.268735 <6>[ 18.483576] pci 0000:01:00.0: supports D1 D2
10640 11:53:35.275492 <6>[ 18.483578] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10641 11:53:35.281829 <6>[ 18.489067] remoteproc remoteproc0: powering up scp
10642 11:53:35.285275 <6>[ 18.489458] Bluetooth: Core ver 2.22
10643 11:53:35.291938 <6>[ 18.489513] NET: Registered PF_BLUETOOTH protocol family
10644 11:53:35.299082 <6>[ 18.489517] Bluetooth: HCI device and connection manager initialized
10645 11:53:35.302658 <6>[ 18.489533] Bluetooth: HCI socket layer initialized
10646 11:53:35.305772 <6>[ 18.489539] Bluetooth: L2CAP socket layer initialized
10647 11:53:35.312561 <6>[ 18.489545] Bluetooth: SCO socket layer initialized
10648 11:53:35.319108 <6>[ 18.492453] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10649 11:53:35.328723 <6>[ 18.492499] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10650 11:53:35.335570 <6>[ 18.492503] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10651 11:53:35.342162 <6>[ 18.492513] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10652 11:53:35.352332 <6>[ 18.492525] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10653 11:53:35.359178 <6>[ 18.492537] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10654 11:53:35.365610 <6>[ 18.492549] pci 0000:00:00.0: PCI bridge to [bus 01]
10655 11:53:35.372699 <6>[ 18.492555] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10656 11:53:35.379579 <6>[ 18.492783] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10657 11:53:35.386042 <6>[ 18.493431] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10658 11:53:35.389646 <6>[ 18.494348] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10659 11:53:35.399981 <5>[ 18.506881] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10660 11:53:35.403090 <6>[ 18.512499] r8152 2-1.3:1.0 eth0: v1.12.13
10661 11:53:35.412821 <6>[ 18.512966] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10662 11:53:35.416944 <6>[ 18.524739] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10663 11:53:35.423743 <6>[ 18.527541] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10664 11:53:35.430055 <5>[ 18.530814] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10665 11:53:35.436626 <6>[ 18.551057] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10666 11:53:35.446981 <3>[ 18.556055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10667 11:53:35.453407 <3>[ 18.556875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10668 11:53:35.463389 <3>[ 18.559565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 11:53:35.470039 <6>[ 18.579108] usbcore: registered new interface driver btusb
10670 11:53:35.479981 <4>[ 18.580018] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10671 11:53:35.486526 <3>[ 18.580030] Bluetooth: hci0: Failed to load firmware file (-2)
10672 11:53:35.493343 <3>[ 18.580033] Bluetooth: hci0: Failed to set up firmware (-2)
10673 11:53:35.503083 <4>[ 18.580036] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10674 11:53:35.509627 <3>[ 18.583428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 11:53:35.522802 <6>[ 18.587285] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10676 11:53:35.529277 <6>[ 18.594018] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10677 11:53:35.535685 <6>[ 18.600210] usbcore: registered new interface driver uvcvideo
10678 11:53:35.545767 <4>[ 18.608900] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10679 11:53:35.552366 <3>[ 18.615589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 11:53:35.559310 <6>[ 18.617418] cfg80211: failed to load regulatory.db
10681 11:53:35.565808 <3>[ 18.642375] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10682 11:53:35.575730 <6>[ 18.665188] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10683 11:53:35.582335 <6>[ 18.684646] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10684 11:53:35.588780 <6>[ 18.684682] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10685 11:53:35.595562 <6>[ 18.684689] remoteproc remoteproc0: remote processor scp is now up
10686 11:53:35.602069 <6>[ 18.686315] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10687 11:53:35.611868 <3>[ 18.699255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10688 11:53:35.618378 <6>[ 18.699427] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10689 11:53:35.628293 <6>[ 18.700655] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10690 11:53:35.634690 <6>[ 18.723557] mt7921e 0000:01:00.0: ASIC revision: 79610010
10691 11:53:35.641862 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10692 11:53:35.658426 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10693 11:53:35.681476 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10694 11:53:35.719488 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10695 11:53:35.739681 <4>[ 19.124100] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10696 11:53:35.857598 <4>[ 19.242078] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10697 11:53:35.864245 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10698 11:53:35.877736 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10699 11:53:35.897057 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10700 11:53:35.909710 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10701 11:53:35.925660 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10702 11:53:35.945483 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10703 11:53:35.957702 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10704 11:53:35.973675 <4>[ 19.358436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10705 11:53:35.983698 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10706 11:53:35.997734 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10707 11:53:36.013938 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10708 11:53:36.033226 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10709 11:53:36.061786 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10710 11:53:36.090576 <4>[ 19.475322] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10711 11:53:36.103680 Starting [0;1;39mUser Login Management[0m...
10712 11:53:36.123085 Starting [0;1;39mPermit User Sessions[0m...
10713 11:53:36.141368 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10714 11:53:36.182639 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10715 11:53:36.210064 <4>[ 19.594668] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10716 11:53:36.220732 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10717 11:53:36.229713 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10718 11:53:36.266999 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10719 11:53:36.283286 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10720 11:53:36.300681 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10721 11:53:36.330611 [[0;32m OK [<4>[ 19.714975] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10722 11:53:36.336629 0m] Reached target [0;1;39mMulti-User System[0m.
10723 11:53:36.351518 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10724 11:53:36.411274 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10725 11:53:36.453998 [[0;32m OK [<4>[ 19.839437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 11:53:36.460470 0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10727 11:53:36.502182
10728 11:53:36.502761
10729 11:53:36.505104 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10730 11:53:36.505576
10731 11:53:36.508439 debian-bullseye-arm64 login: root (automatic login)
10732 11:53:36.508946
10733 11:53:36.509318
10734 11:53:36.524548 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
10735 11:53:36.525125
10736 11:53:36.531114 The programs included with the Debian GNU/Linux system are free software;
10737 11:53:36.537752 the exact distribution terms for each program are described in the
10738 11:53:36.541050 individual files in /usr/share/doc/*/copyright.
10739 11:53:36.541518
10740 11:53:36.547584 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10741 11:53:36.550993 permitted by applicable law.
10742 11:53:36.552565 Matched prompt #10: / #
10744 11:53:36.553719 Setting prompt string to ['/ #']
10745 11:53:36.554183 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10747 11:53:36.555420 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10748 11:53:36.555989 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
10749 11:53:36.556451 Setting prompt string to ['/ #']
10750 11:53:36.556858 Forcing a shell prompt, looking for ['/ #']
10752 11:53:36.607845 / #
10753 11:53:36.608569 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10754 11:53:36.609068 Waiting using forced prompt support (timeout 00:02:30)
10755 11:53:36.609588 <4>[ 19.958835] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 11:53:36.614330
10757 11:53:36.615278 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10758 11:53:36.615808 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
10759 11:53:36.616319 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10760 11:53:36.616843 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
10761 11:53:36.617322 end: 2 depthcharge-action (duration 00:01:50) [common]
10762 11:53:36.617809 start: 3 lava-test-retry (timeout 00:07:44) [common]
10763 11:53:36.618297 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
10764 11:53:36.618698 Using namespace: common
10766 11:53:36.719941 / # #
10767 11:53:36.720661 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10768 11:53:36.721300 #<4>[ 20.079155] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 11:53:36.726244
10770 11:53:36.727135 Using /lava-12066513
10772 11:53:36.828698 / # export SHELL=/bin/sh
10773 11:53:36.829497 export SHELL=/bin/sh<4>[ 20.197997] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 11:53:36.834836
10776 11:53:36.936627 / # . /lava-12066513/environment
10777 11:53:36.937647 . /lava-12066513/environment<3>[ 20.312648] mt7921e 0000:01:00.0: hardware init failed
10778 11:53:36.943216
10780 11:53:37.045179 / # /lava-12066513/bin/lava-test-runner /lava-12066513/0
10781 11:53:37.045824 Test shell timeout: 10s (minimum of the action and connection timeout)
10782 11:53:37.051343 /lava-12066513/bin/lava-test-runner /lava-12066513/0
10783 11:53:37.078299 + export TESTRUN_I<8>[ 20.467479] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12066513_1.5.2.3.1>
10784 11:53:37.079161 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12066513_1.5.2.3.1
10785 11:53:37.079577 Starting test lava.0_igt-gpu-panfrost (12066513_1.5.2.3.1)
10786 11:53:37.080025 Skipping test definition patterns.
10787 11:53:37.081152 D=0_igt-gpu-panfrost
10788 11:53:37.084702 + cd /lava-12066513/0/tests/0_igt-gpu-panfrost
10789 11:53:37.085261 + cat uuid
10790 11:53:37.088032 + UUID=12066513_1.5.2.3.1
10791 11:53:37.088658 + set +x
10792 11:53:37.098186 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
10793 11:53:37.110214 <8>[ 20.501527] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10794 11:53:37.111054 Received signal: <TESTSET> START panfrost_gem_new
10795 11:53:37.111470 Starting test_set panfrost_gem_new
10796 11:53:37.127468 <14>[ 20.518432] [IGT] panfrost_gem_new: executing
10797 11:53:37.134127 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.525298] [IGT] panfrost_gem_new: exiting, ret=77
10798 11:53:37.137428 rch64) (Linux: 6.1.62-cip9 aarch64)
10799 11:53:37.150636 Test requirement not met in function drm_op<8>[ 20.537647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10800 11:53:37.151485 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10802 11:53:37.153532 en_driver, file ../lib/drmtest.c:621:
10803 11:53:37.153996 Test requirement: !(fd<0)
10804 11:53:37.160565 No known gpu found for chipset flags 0x32 (panfrost)
10805 11:53:37.163786 Last errno: 2, No such file or directory
10806 11:53:37.166990 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10807 11:53:37.181326 <14>[ 20.572381] [IGT] panfrost_gem_new: executing
10808 11:53:37.191207 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.580111] [IGT] panfrost_gem_new: exiting, ret=77
10809 11:53:37.191784 .1.62-cip9 aarch64)
10810 11:53:37.204807 Test requirement not met in function drm_open_driver, file <8>[ 20.592598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10811 11:53:37.205677 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10813 11:53:37.207605 ../lib/drmtest.c:621:
10814 11:53:37.208073 Test requirement: !(fd<0)
10815 11:53:37.214508 No known gpu found for chipset flags 0x32 (panfrost)
10816 11:53:37.221279 Last errno: 2, No such file or directory<14>[ 20.611685] [IGT] panfrost_gem_new: executing
10817 11:53:37.221849
10818 11:53:37.230543 [1mSubtest gem-new-0: SKIP (0<14>[ 20.619471] [IGT] panfrost_gem_new: exiting, ret=77
10819 11:53:37.231092 .000s)[0m
10820 11:53:37.237096 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10821 11:53:37.244240 <8>[ 20.631572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10822 11:53:37.244870
10823 11:53:37.245532 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10825 11:53:37.250879 Test requirement not met in fun<8>[ 20.641546] <LAVA_SIGNAL_TESTSET STOP>
10826 11:53:37.251716 Received signal: <TESTSET> STOP
10827 11:53:37.252119 Closing test_set panfrost_gem_new
10828 11:53:37.254118 ction drm_open_driver, file ../lib/drmtest.c:621:
10829 11:53:37.257038 Test requirement: !(fd<0)
10830 11:53:37.260776 No known gpu found for chipset flags 0x32 (panfrost)
10831 11:53:37.267290 Last errno: 2, No such file or directory
10832 11:53:37.273514 [1mSubtest gem-ne<8>[ 20.662423] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10833 11:53:37.274338 Received signal: <TESTSET> START panfrost_get_param
10834 11:53:37.274734 Starting test_set panfrost_get_param
10835 11:53:37.276740 w-zeroed: SKIP (0.000s)[0m
10836 11:53:37.289581 <14>[ 20.680641] [IGT] panfrost_get_param: executing
10837 11:53:37.296246 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.687464] [IGT] panfrost_get_param: exiting, ret=77
10838 11:53:37.299529 rch64) (Linux: 6.1.62-cip9 aarch64)
10839 11:53:37.309245 Test requirement not met in<8>[ 20.698213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10840 11:53:37.310098 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10842 11:53:37.315936 function drm_open_driver, file ../lib/drmtest.c:621:
10843 11:53:37.316542 Test requirement: !(fd<0)
10844 11:53:37.322703 No known gpu found for chipset flags 0x32 (panfrost)
10845 11:53:37.325660 Last errno: 2, No such file or directory
10846 11:53:37.328640 [1mSubtest base-params: SKIP (0.000s)[0m
10847 11:53:37.337710 <14>[ 20.729067] [IGT] panfrost_get_param: executing
10848 11:53:37.347794 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.737450] [IGT] panfrost_get_param: exiting, ret=77
10849 11:53:37.348358 .1.62-cip9 aarch64)
10850 11:53:37.361449 Test requirement not met in function drm_open_driver, file <8>[ 20.749475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10851 11:53:37.362455 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10853 11:53:37.364318 ../lib/drmtest.c:621:
10854 11:53:37.364818 Test requirement: !(fd<0)
10855 11:53:37.371235 No known gpu found for chipset flags 0x32 (panfrost)
10856 11:53:37.377627 Last errno: 2, No such file or directory<14>[ 20.769558] [IGT] panfrost_get_param: executing
10857 11:53:37.378193
10858 11:53:37.387684 [1mSubtest get-bad-param: SKI<14>[ 20.776870] [IGT] panfrost_get_param: exiting, ret=77
10859 11:53:37.388244 P (0.000s)[0m
10860 11:53:37.400578 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<8>[ 20.788917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10861 11:53:37.401147 .1.62-cip9 aarch64)
10862 11:53:37.401801 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10864 11:53:37.407520 Test requir<8>[ 20.797744] <LAVA_SIGNAL_TESTSET STOP>
10865 11:53:37.408368 Received signal: <TESTSET> STOP
10866 11:53:37.408818 Closing test_set panfrost_get_param
10867 11:53:37.413932 ement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10868 11:53:37.414493 Test requirement: !(fd<0)
10869 11:53:37.421105 No known gpu found for chipset flags 0x32 (panfrost)
10870 11:53:37.426698 Last err<8>[ 20.816702] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10871 11:53:37.427515 Received signal: <TESTSET> START panfrost_prime
10872 11:53:37.427906 Starting test_set panfrost_prime
10873 11:53:37.430155 no: 2, No such file or directory
10874 11:53:37.433718 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10875 11:53:37.446988 <14>[ 20.838106] [IGT] panfrost_prime: executing
10876 11:53:37.453490 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.844788] [IGT] panfrost_prime: exiting, ret=77
10877 11:53:37.456912 rch64) (Linux: 6.1.62-cip9 aarch64)
10878 11:53:37.466470 Test requirement not met in<8>[ 20.854984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10879 11:53:37.467309 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10881 11:53:37.473514 function drm_open_driver, file <8>[ 20.865777] <LAVA_SIGNAL_TESTSET STOP>
10882 11:53:37.474363 Received signal: <TESTSET> STOP
10883 11:53:37.474754 Closing test_set panfrost_prime
10884 11:53:37.476739 ../lib/drmtest.c:621:
10885 11:53:37.480404 Test requirement: !(fd<0)
10886 11:53:37.483399 No known gpu found for chipset flags 0x32 (panfrost)
10887 11:53:37.486632 Last errno: 2, No such file or directory
10888 11:53:37.493490 [1mSubtest ge<8>[ 20.884017] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10889 11:53:37.494345 Received signal: <TESTSET> START panfrost_submit
10890 11:53:37.494743 Starting test_set panfrost_submit
10891 11:53:37.496847 m-prime-import: SKIP (0.000s)[0m
10892 11:53:37.508215 <14>[ 20.899577] [IGT] panfrost_submit: executing
10893 11:53:37.515436 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.906058] [IGT] panfrost_submit: exiting, ret=77
10894 11:53:37.519482 rch64) (Linux: 6.1.62-cip9 aarch64)
10895 11:53:37.528402 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10897 11:53:37.531044 Test requirement not met in function drm_op<8>[ 20.918089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10898 11:53:37.534543 en_driver, file ../lib/drmtest.c:621:
10899 11:53:37.535123 Test requirement: !(fd<0)
10900 11:53:37.541073 No known gpu found for chipset flags 0x32 (panfrost)
10901 11:53:37.548064 Last errno: 2, No such f<14>[ 20.937735] [IGT] panfrost_submit: executing
10902 11:53:37.548687 ile or directory
10903 11:53:37.554388 [1mSubtest pa<14>[ 20.945037] [IGT] panfrost_submit: exiting, ret=77
10904 11:53:37.558173 n-submit: SKIP (0.000s)[0m
10905 11:53:37.571165 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<8>[ 20.956869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10906 11:53:37.571746 62-cip9 aarch64)
10907 11:53:37.572416 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10909 11:53:37.577550 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10910 11:53:37.581076 Test requirement: !(fd<0)
10911 11:53:37.587909 No known gpu foun<14>[ 20.977466] [IGT] panfrost_submit: executing
10912 11:53:37.594123 d for chipset flags 0x32 (panfro<14>[ 20.985039] [IGT] panfrost_submit: exiting, ret=77
10913 11:53:37.594684 st)
10914 11:53:37.600595 Last errno: 2, No such file or directory
10915 11:53:37.611069 [1mSubtest pan-submit-error-no-j<8>[ 20.996925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10916 11:53:37.611936 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10918 11:53:37.614009 c: SKIP (0.000s)[0m
10919 11:53:37.617246 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10920 11:53:37.627521 Test requirement not met in function drm_open_driver,<14>[ 21.018266] [IGT] panfrost_submit: executing
10921 11:53:37.630527 file ../lib/drmtest.c:621:
10922 11:53:37.637453 Tes<14>[ 21.025712] [IGT] panfrost_submit: exiting, ret=77
10923 11:53:37.638026 t requirement: !(fd<0)
10924 11:53:37.643439 No known gpu found for chipset flags 0x32 (panfrost)
10925 11:53:37.650464 La<8>[ 21.037751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10926 11:53:37.651302 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10928 11:53:37.653778 st errno: 2, No such file or directory
10929 11:53:37.660206 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10930 11:53:37.666749 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 21.058716] [IGT] panfrost_submit: executing
10931 11:53:37.670205 nux: 6.1.62-cip9 aarch64)
10932 11:53:37.676860 Test <14>[ 21.066290] [IGT] panfrost_submit: exiting, ret=77
10933 11:53:37.683660 requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10934 11:53:37.693473 Tes<8>[ 21.078234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10935 11:53:37.694103 t requirement: !(fd<0)
10936 11:53:37.694759 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10938 11:53:37.700273 No known gpu found for chipset flags 0x32 (panfrost)
10939 11:53:37.703469 Last errno: 2, No such file or directory
10940 11:53:37.710351 [1mSubtest pan-submit-e<14>[ 21.099824] [IGT] panfrost_submit: executing
10941 11:53:37.716455 rror-bad-bo-handles: SKIP (0.000<14>[ 21.107536] [IGT] panfrost_submit: exiting, ret=77
10942 11:53:37.717068 s)[0m
10943 11:53:37.729643 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-ci<8>[ 21.117877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10944 11:53:37.730583 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10946 11:53:37.733130 p9 aarch64)
10947 11:53:37.739660 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10948 11:53:37.742748 Test requirement: !(fd<0)
10949 11:53:37.746447 No kno<14>[ 21.137639] [IGT] panfrost_submit: executing
10950 11:53:37.756465 wn gpu found for chipset flags 0<14>[ 21.145139] [IGT] panfrost_submit: exiting, ret=77
10951 11:53:37.757112 x32 (panfrost)
10952 11:53:37.759671 Last errno: 2, No such file or directory
10953 11:53:37.769393 [1mSubtest pan-submit<8>[ 21.157087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10954 11:53:37.770255 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10956 11:53:37.772656 -error-bad-requirements: SKIP (0.000s)[0m
10957 11:53:37.779400 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10958 11:53:37.786170 Test requiremen<14>[ 21.176132] [IGT] panfrost_submit: executing
10959 11:53:37.792707 t not met in function drm_open_d<14>[ 21.182667] [IGT] panfrost_submit: exiting, ret=77
10960 11:53:37.795899 river, file ../lib/drmtest.c:621:
10961 11:53:37.799288 Test requirement: !(fd<0)
10962 11:53:37.805706 No<8>[ 21.193291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10963 11:53:37.806542 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
10965 11:53:37.808867 known gpu found for chipset flags 0x32 (panfrost)
10966 11:53:37.815426 Last errno: 2, No such file or directory
10967 11:53:37.822333 [1mSubtest pan-submit-error-bad-o<14>[ 21.212241] [IGT] panfrost_submit: executing
10968 11:53:37.825359 ut-sync: SKIP (0.000s)[0m
10969 11:53:37.828728 IGT-<14>[ 21.219835] [IGT] panfrost_submit: exiting, ret=77
10970 11:53:37.835659 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10971 11:53:37.841772 <8>[ 21.230279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
10972 11:53:37.842243
10973 11:53:37.842875 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
10975 11:53:37.848446 Test requirement not met in fun<8>[ 21.240892] <LAVA_SIGNAL_TESTSET STOP>
10976 11:53:37.849222 Received signal: <TESTSET> STOP
10977 11:53:37.849604 Closing test_set panfrost_submit
10978 11:53:37.858815 ction drm_open_driver, file ../l<8>[ 21.247751] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12066513_1.5.2.3.1>
10979 11:53:37.859659 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12066513_1.5.2.3.1
10980 11:53:37.860122 Ending use of test pattern.
10981 11:53:37.860480 Ending test lava.0_igt-gpu-panfrost (12066513_1.5.2.3.1), duration 0.78
10983 11:53:37.862176 ib/drmtest.c:621:
10984 11:53:37.865256 Test requirement: !(fd<0)
10985 11:53:37.868603 No known gpu found for chipset flags 0x32 (panfrost)
10986 11:53:37.872000 Last errno: 2, No such file or directory
10987 11:53:37.875030 [1mSubtest pan-reset: SKIP (0.000s)[0m
10988 11:53:37.881346 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10989 11:53:37.888362 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10990 11:53:37.891718 Test requirement: !(fd<0)
10991 11:53:37.894796 No known gpu found for chipset flags 0x32 (panfrost)
10992 11:53:37.898128 Last errno: 2, No such file or directory
10993 11:53:37.904779 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
10994 11:53:37.911412 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10995 11:53:37.917913 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10996 11:53:37.918483 Test requirement: !(fd<0)
10997 11:53:37.924444 No known gpu found for chipset flags 0x32 (panfrost)
10998 11:53:37.927780 Last errno: 2, No such file or directory
10999 11:53:37.930950 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11000 11:53:37.934427 + set +x
11001 11:53:37.934989 <LAVA_TEST_RUNNER EXIT>
11002 11:53:37.935659 ok: lava_test_shell seems to have completed
11003 11:53:37.937494 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11004 11:53:37.938033 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11005 11:53:37.938498 end: 3 lava-test-retry (duration 00:00:01) [common]
11006 11:53:37.938978 start: 4 finalize (timeout 00:07:43) [common]
11007 11:53:37.939464 start: 4.1 power-off (timeout 00:00:30) [common]
11008 11:53:37.940348 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11009 11:53:38.065132 >> Command sent successfully.
11010 11:53:38.069555 Returned 0 in 0 seconds
11011 11:53:38.170528 end: 4.1 power-off (duration 00:00:00) [common]
11013 11:53:38.172095 start: 4.2 read-feedback (timeout 00:07:43) [common]
11014 11:53:38.173538 Listened to connection for namespace 'common' for up to 1s
11015 11:53:39.174107 Finalising connection for namespace 'common'
11016 11:53:39.174965 Disconnecting from shell: Finalise
11017 11:53:39.175430 / #
11018 11:53:39.276498 end: 4.2 read-feedback (duration 00:00:01) [common]
11019 11:53:39.277438 end: 4 finalize (duration 00:00:01) [common]
11020 11:53:39.278143 Cleaning after the job
11021 11:53:39.278679 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/ramdisk
11022 11:53:39.312793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/kernel
11023 11:53:39.327864 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/dtb
11024 11:53:39.328129 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066513/tftp-deploy-5ilml9ro/modules
11025 11:53:39.337641 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066513
11026 11:53:39.456311 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066513
11027 11:53:39.456496 Job finished correctly